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Farnell PDF
Moving Average Filters Chapitre 15 - Analog Devices
Moving Average Filters Chapitre 15 - Analog Devices
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Farnell Element 14 :
See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…
Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.
Puce électronique / Microchip :
Sans fil - Wireless :
Texas instrument :
Ordinateurs :
Logiciels :
Tutoriels :
Autres documentations :
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CHAPTER
15
EQUATION 15-1
Equation of the moving average filter. In
this equation, x[ ] is the input signal, y[ ] is
the output signal, and M is the number of
points used in the moving average. This
equation only uses points on one side of the
output sample being calculated.
y[i ] ’ 1
M
j M&1
j’ 0
x [ i %j ]
y [80] ’ x [80] % x [81] % x [82] % x [83] % x [84]
5
Moving Average Filters
The moving average is the most common filter in DSP, mainly because it is the easiest digital
filter to understand and use. In spite of its simplicity, the moving average filter is optimal for
a common task: reducing random noise while retaining a sharp step response. This makes it the
premier filter for time domain encoded signals. However, the moving average is the worst filter
for frequency domain encoded signals, with little ability to separate one band of frequencies from
another. Relatives of the moving average filter include the Gaussian, Blackman, and multiplepass
moving average. These have slightly better performance in the frequency domain, at the
expense of increased computation time.
Implementation by Convolution
As the name implies, the moving average filter operates by averaging a number
of points from the input signal to produce each point in the output signal. In
equation form, this is written:
Where x [ ] is the input signal, y [ ] is the output signal, and M is the number
of points in the average. For example, in a 5 point moving average filter, point
80 in the output signal is given by:
278 The Scientist and Engineer's Guide to Digital Signal Processing
y [80] ’ x [78] % x [79] % x [80] % x [81] % x [82]
5
100 'MOVING AVERAGE FILTER
110 'This program filters 5000 samples with a 101 point moving
120 'average filter, resulting in 4900 samples of filtered data.
130 '
140 DIM X[4999] 'X[ ] holds the input signal
150 DIM Y[4999] 'Y[ ] holds the output signal
160 '
170 GOSUB XXXX 'Mythical subroutine to load X[ ]
180 '
190 FOR I% = 50 TO 4949 'Loop for each point in the output signal
200 Y[I%] = 0 'Zero, so it can be used as an accumulator
210 FOR J% = -50 TO 50 'Calculate the summation
220 Y[I%] = Y[I%] + X(I%+J%]
230 NEXT J%
240 Y[I%] = Y[I%]/101 'Complete the average by dividing
250 NEXT I%
260 '
270 END
TABLE 15-1
As an alternative, the group of points from the input signal can be chosen
symmetrically around the output point:
This corresponds to changing the summation in Eq. 15-1 from: j ’ 0 to M&1 ,
to: j ’ &(M&1) /2 to (M&1) /2 . For instance, in an 11 point moving average
filter, the index, j, can run from 0 to 11 (one side averaging) or -5 to 5
(symmetrical averaging). Symmetrical averaging requires that M be an odd
number. Programming is slightly easier with the points on only one side;
however, this produces a relative shift between the input and output signals.
You should recognize that the moving average filter is a convolution using a
very simple filter kernel. For example, a 5 point filter has the filter kernel:
þ 0, 0, 1/5, 1/5, 1/5, 1/5, 1/5, 0, 0 þ . That is, the moving average filter is a
convolution of the input signal with a rectangular pulse having an area of one.
Table 15-1 shows a program to implement the moving average filter.
Noise Reduction vs. Step Response
Many scientists and engineers feel guilty about using the moving average filter.
Because it is so very simple, the moving average filter is often the first thing
tried when faced with a problem. Even if the problem is completely solved,
there is still the feeling that something more should be done. This situation is
truly ironic. Not only is the moving average filter very good for many
applications, it is optimal for a common problem, reducing random white noise
while keeping the sharpest step response.
Chapter 15- Moving Average Filters 279
Sample number
0 100 200 300 400 500
-1
0
1
2
a. Original signal
Sample number
0 100 200 300 400 500
-1
0
1
2
b. 11 point moving average
FIGURE 15-1
Example of a moving average filter. In (a), a
rectangular pulse is buried in random noise. In
(b) and (c), this signal is filtered with 11 and 51
point moving average filters, respectively. As
the number of points in the filter increases, the
noise becomes lower; however, the edges
becoming less sharp. The moving average filter
is the optimal solution for this problem,
providing the lowest noise possible for a given
edge sharpness.
Sample number
0 100 200 300 400 500
-1
0
1
2
c. 51 point moving average
Amplitude Amplitude
Amplitude
Figure 15-1 shows an example of how this works. The signal in (a) is a pulse
buried in random noise. In (b) and (c), the smoothing action of the moving
average filter decreases the amplitude of the random noise (good), but also
reduces the sharpness of the edges (bad). Of all the possible linear filters that
could be used, the moving average produces the lowest noise for a given edge
sharpness. The amount of noise reduction is equal to the square-root of the
number of points in the average. For example, a 100 point moving average
filter reduces the noise by a factor of 10.
To understand why the moving average if the best solution, imagine we want
to design a filter with a fixed edge sharpness. For example, let's assume we fix
the edge sharpness by specifying that there are eleven points in the rise of the
step response. This requires that the filter kernel have eleven points. The
optimization question is: how do we choose the eleven values in the filter
kernel to minimize the noise on the output signal? Since the noise we are
trying to reduce is random, none of the input points is special; each is just as
noisy as its neighbor. Therefore, it is useless to give preferential treatment to
any one of the input points by assigning it a larger coefficient in the filter
kernel. The lowest noise is obtained when all the input samples are treated
equally, i.e., the moving average filter. (Later in this chapter we show that
other filters are essentially as good. The point is, no filter is better than the
simple moving average).
280 The Scientist and Engineer's Guide to Digital Signal Processing
EQUATION 15-2
Frequency response of an M point moving
average filter. The frequency, f, runs between
0 and 0.5. For f ’ 0, use: H[ f ] ’ 1
H [ f ] ’ sin(Bf M )
M sin(Bf )
Frequency
0 0.1 0.2 0.3 0.4 0.5
0.0
0.2
0.4
0.6
0.8
1.0
1.2
3 point
11 point
31 point
FIGURE 15-2
Frequency response of the moving average
filter. The moving average is a very poor
low-pass filter, due to its slow roll-off and
poor stopband attenuation. These curves are
generated by Eq. 15-2.
Amplitude
Frequency Response
Figure 15-2 shows the frequency response of the moving average filter. It is
mathematically described by the Fourier transform of the rectangular pulse, as
discussed in Chapter 11:
The roll-off is very slow and the stopband attenuation is ghastly. Clearly, the
moving average filter cannot separate one band of frequencies from another.
Remember, good performance in the time domain results in poor performance
in the frequency domain, and vice versa. In short, the moving average is an
exceptionally good smoothing filter (the action in the time domain), but an
exceptionally bad low-pass filter (the action in the frequency domain).
Relatives of the Moving Average Filter
In a perfect world, filter designers would only have to deal with time
domain or frequency domain encoded information, but never a mixture of
the two in the same signal. Unfortunately, there are some applications
where both domains are simultaneously important. For instance, television
signals fall into this nasty category. Video information is encoded in the
time domain, that is, the shape of the waveform corresponds to the patterns
of brightness in the image. However, during transmission the video signal
is treated according to its frequency composition, such as its total
bandwidth, how the carrier waves for sound & color are added, elimination
& restoration of the DC component, etc. As another example, electromagnetic
interference is best understood in the frequency domain, even if
Chapter 15- Moving Average Filters 281
Sample number
0 6 12 18 24
0.0
0.1
0.2
2 pass
4 pass
1 pass
a. Filter kernel
Sample number
0 6 12 18 24
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1 pass
4 pass
2 pass
b. Step response
Frequency
0 0.1 0.2 0.3 0.4 0.5
-120
-100
-80
-60
-40
-20
0
20
40
1 pass
2 pass
4 pass
d. Frequency response (dB)
FIGURE 15-3
Characteristics of multiple-pass moving average filters. Figure (a) shows the filter kernels resulting from
passing a seven point moving average filter over the data once, twice and four times. Figure (b) shows the
corresponding step responses, while (c) and (d) show the corresponding frequency responses.
FFT
Integrate 20 Log( )
Amplitude Amplitude
Frequency
0 0.1 0.2 0.3 0.4 0.5
0.00
0.25
0.50
0.75
1.00
1.25
1 pass
2 pass
4 pass
c. Frequency response
Amplitude (dB) Amplitude
the signal's information is encoded in the time domain. For instance, the
temperature monitor in a scientific experiment might be contaminated with 60
hertz from the power lines, 30 kHz from a switching power supply, or 1320
kHz from a local AM radio station. Relatives of the moving average filter
have better frequency domain performance, and can be useful in these mixed
domain applications.
Multiple-pass moving average filters involve passing the input signal
through a moving average filter two or more times. Figure 15-3a shows the
overall filter kernel resulting from one, two and four passes. Two passes are
equivalent to using a triangular filter kernel (a rectangular filter kernel
convolved with itself). After four or more passes, the equivalent filter kernel
looks like a Gaussian (recall the Central Limit Theorem). As shown in (b),
multiple passes produce an "s" shaped step response, as compared to the
straight line of the single pass. The frequency responses in (c) and (d) are
given by Eq. 15-2 multiplied by itself for each pass. That is, each time domain
convolution results in a multiplication of the frequency spectra.
282 The Scientist and Engineer's Guide to Digital Signal Processing
Figure 15-4 shows the frequency response of two other relatives of the moving
average filter. When a pure Gaussian is used as a filter kernel, the frequency
response is also a Gaussian, as discussed in Chapter 11. The Gaussian is
important because it is the impulse response of many natural and manmade
systems. For example, a brief pulse of light entering a long fiber optic
transmission line will exit as a Gaussian pulse, due to the different paths taken
by the photons within the fiber. The Gaussian filter kernel is also used
extensively in image processing because it has unique properties that allow
fast two-dimensional convolutions (see Chapter 24). The second frequency
response in Fig. 15-4 corresponds to using a Blackman window as a filter
kernel. (The term window has no meaning here; it is simply part of the
accepted name of this curve). The exact shape of the Blackman window is
given in Chapter 16 (Eq. 16-2, Fig. 16-2); however, it looks much like a
Gaussian.
How are these relatives of the moving average filter better than the moving
average filter itself? Three ways: First, and most important, these filters have
better stopband attenuation than the moving average filter. Second, the filter
kernels taper to a smaller amplitude near the ends. Recall that each point in
the output signal is a weighted sum of a group of samples from the input. If the
filter kernel tapers, samples in the input signal that are farther away are given
less weight than those close by. Third, the step responses are smooth curves,
rather than the abrupt straight line of the moving average. These last two are
usually of limited benefit, although you might find applications where they are
genuine advantages.
The moving average filter and its relatives are all about the same at reducing
random noise while maintaining a sharp step response. The ambiguity lies in
how the risetime of the step response is measured. If the risetime is measured
from 0% to 100% of the step, the moving average filter is the best you can do,
as previously shown. In comparison, measuring the risetime from 10% to 90%
makes the Blackman window better than the moving average filter. The point
is, this is just theoretical squabbling; consider these filters equal in this
parameter.
The biggest difference in these filters is execution speed. Using a recursive
algorithm (described next), the moving average filter will run like lightning in
your computer. In fact, it is the fastest digital filter available. Multiple passes
of the moving average will be correspondingly slower, but still very quick. In
comparison, the Gaussian and Blackman filters are excruciatingly slow,
because they must use convolution. Think a factor of ten times the number of
points in the filter kernel (based on multiplication being about 10 times slower
than addition). For example, expect a 100 point Gaussian to be 1000 times
slower than a moving average using recursion.
Recursive Implementation
A tremendous advantage of the moving average filter is that it can be
implemented with an algorithm that is very fast. To understand this
Chapter 15- Moving Average Filters 283
FIGURE 15-4
Frequency response of the Blackman window
and Gaussian filter kernels. Both these filters
provide better stopband attenuation than the
moving average filter. This has no advantage in
removing random noise from time domain
encoded signals, but it can be useful in mixed
domain problems. The disadvantage of these
filters is that they must use convolution, a
terribly slow algorithm.
Frequency
0 0.1 0.2 0.3 0.4 0.5
-140
-120
-100
-80
-60
-40
-20
0
20
Gaussian
Blackman
Amplitude (dB)
y [50] ’ x [47] % x [48] % x [49] % x [50] % x [51] % x [52] % x [53]
y [51] ’ x [48] % x [49] % x [50] % x [51] % x [52] % x [53] % x [54]
y [51] ’ y [50] % x [54] & x [47]
EQUATION 15-3
Recursive implementation of the moving
average filter. In this equation, x[ ] is the
input signal, y[ ] is the output signal, M is the
number of points in the moving average (an
odd number). Before this equation can be
used, the first point in the signal must be
calculated using a standard summation.
y [i ] ’ y [i &1] % x [i %p] & x [i &q]
q ’ p % 1
where: p ’ (M&1) /2
algorithm, imagine passing an input signal, x [ ], through a seven point moving
average filter to form an output signal, y [ ]. Now look at how two adjacent
output points, y [50] and y [51], are calculated:
These are nearly the same calculation; points x [48] through x [53] must be
added for y [50], and again for y [51]. If y [50] has already been calculated, the
most efficient way to calculate y [51] is:
Once y [51] has been found using y [50], then y [52] can be calculated from
sample y [51], and so on. After the first point is calculated in y [ ], all of the
other points can be found with only a single addition and subtraction per point.
This can be expressed in the equation:
Notice that this equation use two sources of data to calculate each point in the
output: points from the input and previously calculated points from the output.
This is called a recursive equation, meaning that the result of one calculation
284 The Scientist and Engineer's Guide to Digital Signal Processing
100 'MOVING AVERAGE FILTER IMPLEMENTED BY RECURSION
110 'This program filters 5000 samples with a 101 point moving
120 'average filter, resulting in 4900 samples of filtered data.
130 'A double precision accumulator is used to prevent round-off drift.
140 '
150 DIM X[4999] 'X[ ] holds the input signal
160 DIM Y[4999] 'Y[ ] holds the output signal
170 DEFDBL ACC 'Define the variable ACC to be double precision
180 '
190 GOSUB XXXX 'Mythical subroutine to load X[ ]
200 '
210 ACC = 0 'Find Y[50] by averaging points X[0] to X[100]
220 FOR I% = 0 TO 100
230 ACC = ACC + X[I%]
240 NEXT I%
250 Y[[50] = ACC/101
260 ' 'Recursive moving average filter (Eq. 15-3)
270 FOR I% = 51 TO 4949
280 ACC = ACC + X[I%+50] - X[I%-51]
290 Y[I%] = ACC
300 NEXT I%
310 '
320 END
TABLE 15-2
CHAPTER
6 Convolution
Convolution is a mathematical way of combining two signals to form a third signal. It is the
single most important technique in Digital Signal Processing. Using the strategy of impulse
decomposition, systems are described by a signal called the impulse response. Convolution is
important because it relates the three signals of interest: the input signal, the output signal, and
the impulse response. This chapter presents convolution from two different viewpoints, called
the input side algorithm and the output side algorithm. Convolution provides the mathematical
framework for DSP; there is nothing more important in this book.
The Delta Function and Impulse Response
The previous chapter describes how a signal can be decomposed into a group
of components called impulses. An impulse is a signal composed of all zeros,
except a single nonzero point. In effect, impulse decomposition provides a way
to analyze signals one sample at a time. The previous chapter also presented
the fundamental concept of DSP: the input signal is decomposed into simple
additive components, each of these components is passed through a linear
system, and the resulting output components are synthesized (added). The
signal resulting from this divide-and-conquer procedure is identical to that
obtained by directly passing the original signal through the system. While
many different decompositions are possible, two form the backbone of signal
processing: impulse decomposition and Fourier decomposition. When impulse
decomposition is used, the procedure can be described by a mathematical
operation called convolution. In this chapter (and most of the following ones)
we will only be dealing with discrete signals. Convolution also applies to
continuous signals, but the mathematics is more complicated. We will look at
how continious signals are processed in Chapter 13.
Figure 6-1 defines two important terms used in DSP. The first is the delta
function, symbolized by the Greek letter delta, *[n]. The delta function is
a normalized impulse, that is, sample number zero has a value of one, while
108 The Scientist and Engineer's Guide to Digital Signal Processing
all other samples have a value of zero. For this reason, the delta function is
frequently called the unit impulse.
The second term defined in Fig. 6-1 is the impulse response. As the name
suggests, the impulse response is the signal that exits a system when a delta
function (unit impulse) is the input. If two systems are different in any way,
they will have different impulse responses. Just as the input and output signals
are often called x[n] and y[n] , the impulse response is usually given the
symbol, h[n]. Of course, this can be changed if a more descriptive name is
available, for instance, f [n] might be used to identify the impulse response of
a filter.
Any impulse can be represented as a shifted and scaled delta function.
Consider a signal, a[n] , composed of all zeros except sample number 8,
which has a value of -3. This is the same as a delta function shifted to the
right by 8 samples, and multiplied by -3. In equation form:
a[n] ’ &3*[n&8]. Make sure you understand this notation, it is used in
nearly all DSP equations.
If the input to a system is an impulse, such as &3*[n&8] , what is the system's
output? This is where the properties of homogeneity and shift invariance are
used. Scaling and shifting the input results in an identical scaling and shifting
of the output. If *[n] results in h[n] , it follows that &3*[n&8] results in
&3h[n&8] . In words, the output is a version of the impulse response that has
been shifted and scaled by the same amount as the delta function on the input.
If you know a system's impulse response, you immediately know how it will
react to any impulse.
Convolution
Let's summarize this way of understanding how a system changes an input
signal into an output signal. First, the input signal can be decomposed into a
set of impulses, each of which can be viewed as a scaled and shifted delta
function. Second, the output resulting from each impulse is a scaled and shifted
version of the impulse response. Third, the overall output signal can be found
by adding these scaled and shifted impulse responses. In other words, if we
know a system's impulse response, then we can calculate what the output will
be for any possible input signal. This means we know everything about the
system. There is nothing more that can be learned about a linear system's
characteristics. (However, in later chapters we will show that this information
can be represented in different forms).
The impulse response goes by a different name in some applications. If the
system being considered is a filter, the impulse response is called the filter
kernel, the convolution kernel, or simply, the kernel. In image processing,
the impulse response is called the point spread function. While these terms
are used in slightly different ways, they all mean the same thing, the signal
produced by a system when the input is a delta function.
Chapter 6- Convolution 109
System
-2 -1 0 1 2 3 4 5 6
-1
0
1
2
-2 -1 0 1 2 3 4 5 6
-1
0
1
2
*[n] h[n]
Delta Impulse
Response
Linear
Function
FIGURE 6-1
Definition of delta function and impulse response. The delta function is a normalized impulse. All of
its samples have a value of zero, except for sample number zero, which has a value of one. The Greek
letter delta, *[n] , is used to identify the delta function. The impulse response of a linear system, usually
denoted by h[n] , is the output of the system when the input is a delta function.
x[n] h[n] = y[n]
x[n] y[n]
Linear
System
h[n]
FIGURE 6-2
How convolution is used in DSP. The
output signal from a linear system is
equal to the input signal convolved
with the system's impulse response.
Convolution is denoted by a star when
writing equations.
Convolution is a formal mathematical operation, just as multiplication,
addition, and integration. Addition takes two numbers and produces a third
number, while convolution takes two signals and produces a third signal.
Convolution is used in the mathematics of many fields, such as probability and
statistics. In linear systems, convolution is used to describe the relationship
between three signals of interest: the input signal, the impulse response, and the
output signal.
Figure 6-2 shows the notation when convolution is used with linear systems.
An input signal, x[n] , enters a linear system with an impulse response, h[n] ,
resulting in an output signal, y[n] . In equation form: x[n] t h[n] ’ y[n] .
Expressed in words, the input signal convolved with the impulse response is
equal to the output signal. Just as addition is represented by the plus, +, and
multiplication by the cross, ×, convolution is represented by the star, t. It is
unfortunate that most programming languages also use the star to indicate
multiplication. A star in a computer program means multiplication, while a star
in an equation means convolution.
110 The Scientist and Engineer's Guide to Digital Signal Processing
Sample number
0 10 20 30 40 50 60 70 80 90 100 110
-2
-1
0
1
2
3
4
S
0 10 20 30
-0.25
0.00
0.25
0.50
0.75
1.00
1.25
S
0 10 20 30
-0.02
0.00
0.02
0.04
0.06
0.08
a. Low-pass Filter
b. High-pass Filter
Sample number
0 10 20 30 40 50 60 70 80
-2
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1
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4
Sample number
0 10 20 30 40 50 60 70 80 90 100 110
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-1
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Sample number
0 10 20 30 40 50 60 70 80
-2
-1
0
1
2
3
4
Sample number
Sample number
Input Signal Impulse Response Output Signal
Amplitude Amplitude
Amplitude Amplitude
Amplitude Amplitude
FIGURE 6-3
Examples of low-pass and high-pass filtering using convolution. In this example, the input signal
is a few cycles of a sine wave plus a slowly rising ramp. These two components are separated by
using properly selected impulse responses.
Figure 6-3 shows convolution being used for low-pass and high-pass filtering.
The example input signal is the sum of two components: three cycles of a sine
wave (representing a high frequency), plus a slowly rising ramp (composed of
low frequencies). In (a), the impulse response for the low-pass filter is a
smooth arch, resulting in only the slowly changing ramp waveform being
passed to the output. Similarly, the high-pass filter, (b), allows only the more
rapidly changing sinusoid to pass.
Figure 6-4 illustrates two additional examples of how convolution is used to
process signals. The inverting attenuator, (a), flips the signal top-for-bottom,
and reduces its amplitude. The discrete derivative (also called the first
difference), shown in (b), results in an output signal related to the slope of the
input signal.
Notice the lengths of the signals in Figs. 6-3 and 6-4. The input signals are
81 samples long, while each impulse response is composed of 31 samples.
In most DSP applications, the input signal is hundreds, thousands, or even
millions of samples in length. The impulse response is usually much shorter,
say, a few points to a few hundred points. The mathematics behind
convolution doesn't restrict how long these signals are. It does, however,
specify the length of the output signal. The length of the output signal is
Chapter 6- Convolution 111
S
0 10 20 30
-2.00
-1.00
0.00
1.00
2.00
S
0 10 20 30
-2.00
-1.00
0.00
1.00
2.00
a. Inverting Attenuator
b. Discrete Derivative
Sample number
0 10 20 30 40 50 60 70 80 90 100 110
-2
-1
0
1
2
3
4
Sample number
0 10 20 30 40 50 60 70 80 90 100 110
-2
-1
0
1
2
3
4
Sample number
0 10 20 30 40 50 60 70 80
-2
-1
0
1
2
3
4
Sample number
0 10 20 30 40 50 60 70 80
-2
-1
0
1
2
3
4
Input Signal Impulse Response Output Signal
Sample number
Sample number
Amplitude Amplitude
Amplitude Amplitude
Amplitude Amplitude
FIGURE 6-4
Examples of signals being processed using convolution. Many signal processing tasks use very
simple impulse responses. As shown in these examples, dramatic changes can be achieved with only
a few nonzero points.
equal to the length of the input signal, plus the length of the impulse
response, minus one. For the signals in Figs. 6-3 and 6-4, each output
signal is: 81% 31& 1 ’ 111 samples long. The input signal runs from sample
0 to 80, the impulse response from sample 0 to 30, and the output signal
from sample 0 to 110.
Now we come to the detailed mathematics of convolution. As used in Digital
Signal Processing, convolution can be understood in two separate ways. The
first looks at convolution from the viewpoint of the input signal. This
involves analyzing how each sample in the input signal contributes to many
points in the output signal. The second way looks at convolution from the
viewpoint of the output signal. This examines how each sample in the
output signal has received information from many points in the input signal.
Keep in mind that these two perspectives are different ways of thinking
about the same mathematical operation. The first viewpoint is important
because it provides a conceptual understanding of how convolution pertains
to DSP. The second viewpoint describes the mathematics of convolution.
This typifies one of the most difficult tasks you will encounter in DSP:
making your conceptual understanding fit with the jumble of mathematics
used to communicate the ideas.
112 The Scientist and Engineer's Guide to Digital Signal Processing
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
0 1 2 3 4 5 6 7 8
-3
-2
-1
0
1
2
3
0 1 2 3
-3
-2
-1
0
1
2
3
x[n] h[n] y[n]
FIGURE 6-5
Example convolution problem. A nine point input signal, convolved with a four point impulse response, results
in a twelve point output signal. Each point in the input signal contributes a scaled and shifted impulse response
to the output signal. These nine scaled and shifted impulse responses are shown in Fig. 6-6.
Now examine sample x[8] , the last point in the input signal. This sample is at
index number eight, and has a value of -0.5. As shown in the lower-right graph
of Fig. 6-6, x[8] results in an impulse response that has been shifted to the right
by eight points and multiplied by -0.5. Place holding zeros have been added at
points 0-7. Lastly, examine the effect of points x[0] and x[7] . Both these
samples have a value of zero, and therefore produce output components
consisting of all zeros.
The Input Side Algorithm
Figure 6-5 shows a simple convolution problem: a 9 point input signal, x[n] ,
is passed through a system with a 4 point impulse response, h[n] , resulting
in a 9% 4& 1 ’ 12 point output signal, y[n] . In mathematical terms, x[n] is
convolved with h[n] to produce y[n] . This first viewpoint of convolution is
based on the fundamental concept of DSP: decompose the input, pass the
components through the system, and synthesize the output. In this example,
each of the nine samples in the input signal will contribute a scaled and
shifted version of the impulse response to the output signal. These nine
signals are shown in Fig. 6-6. Adding these nine signals produces the
output signal, y[n] .
Let's look at several of these nine signals in detail. We will start with sample
number four in the input signal, i.e., x[4] . This sample is at index number four,
and has a value of 1.4. When the signal is decomposed, this turns into an
impulse represented as: 1.4*[n&4]. After passing through the system, the
resulting output component will be: 1.4 h[n&4]. This signal is shown in the
center box of the nine signals in Fig. 6-6. Notice that this is the impulse
response, h[n] , multiplied by 1.4, and shifted four samples to the right. Zeros
have been added at samples 0-3 and at samples 8-11 to serve as place holders.
To make this more clear, Fig. 6-6 uses squares to represent the data points that
come from the shifted and scaled impulse response, and diamonds for the added
zeros.
Chapter 6- Convolution 113
FIGURE 6-6
Output signal components for the convolution in Fig. 6-5. In these signals, each point that results from a scaled
and shifted impulse response is represented by a square marker. The remaining data points, represented by
diamonds, are zeros that have been added as place holders.
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
contribution
from x[ ] h[n- ]
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
contribution
from x[ ] h[n- ]
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
contribution
from x[ ] h[n- ]
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
contribution
from x[ ] h[n- ]
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
contribution
from x[ ] h[n- ]
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
contribution
from x[ ] h[n- ]
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
contribution
from x[ ] h[n- ]
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
contribution
from x[ ] h[n- ]
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
contribution
from x[ ] h[n- ]
0 0 1 1 2 2
3 3 4 4 5 5
6 6 7 7 8 8
In this example, x[n] is a nine point signal and h[n] is a four point signal. In
our next example, shown in Fig. 6-7, we will reverse the situation by making x[n]
a four point signal, and h[n] a nine point signal. The same two waveforms are
used, they are just swapped. As shown by the output signal components, the
four samples in x[n] result in four shifted and scaled versions of the nine point
impulse response. Just as before, leading and trailing zeros are added as place
holders.
But wait just one moment! The output signal in Fig. 6-7 is identical to the
output signal in Fig. 6-5. This isn't a mistake, but an important property.
Convolution is commutative: a[n]tb[n] ’ b[n]ta[n] . The mathematics does
not care which is the input signal and which is the impulse response, only
that two signals are convolved with each other. Although the mathematics
may allow it, exchanging the two signals has no physical meaning in system
theory. The input signal and impulse response are two totally different
things and exchanging them doesn't make sense. What the commutative
property provides is a mathematical tool for manipulating equations to
achieve various results.
114 The Scientist and Engineer's Guide to Digital Signal Processing
TABLE 6-1
100 'CONVOLUTION USING THE INPUT SIDE ALGORITHM
110 '
120 DIM X[80] 'The input signal, 81 points
130 DIM H[30] 'The impulse response, 31 points
140 DIM Y[110] 'The output signal, 111 points
150 '
160 GOSUB XXXX 'Mythical subroutine to load X[ ] and H[ ]
170 '
180 FOR I% = 0 TO 110 'Zero the output array
190 Y(I%) = 0
200 NEXT I%
210 '
220 FOR I% = 0 TO 80 'Loop for each point in X[ ]
230 FOR J% = 0 TO 30 'Loop for each point in H[ ]
240 Y[I%+J%] = Y[I%+J%] + X[I%]tH[J%]
250 NEXT J%
260 NEXT I% '(remember, t is multiplication in programs!)
270 '
280 GOSUB XXXX 'Mythical subroutine to store Y[ ]
290 '
300 END
A program for calculating convolutions using the input side algorithm is shown
in Table 6-1. Remember, the programs in this book are meant to convey
algorithms in the simplest form, even at the expense of good programming
style. For instance, all of the input and output is handled in mythical
subroutines (lines 160 and 280), meaning we do not define how these
operations are conducted. Do not skip over these programs; they are a key
part of the material and you need to understand them in detail.
The program convolves an 81 point input signal, held in array X[ ], with a 31
point impulse response, held in array H[ ], resulting in a 111 point output
signal, held in array Y[ ]. These are the same lengths shown in Figs. 6-3 and
6-4. Notice that the names of these arrays use upper case letters. This is a
violation of the naming conventions previously discussed, because upper case
letters are reserved for frequency domain signals. Unfortunately, the simple
BASIC used in this book does not allow lower case variable names. Also
notice that line 240 uses a star for multiplication. Remember, a star in a
program means multiplication, while a star in an equation means convolution.
A star in text (such as documentation or program comments) can mean either.
The mythical subroutine in line 160 places the input signal into X[ ] and the
impulse response into H[ ]. Lines 180-200 set all of the values in Y[ ] to
zero. This is necessary because Y[ ] is used as an accumulator to sum the
output components as they are calculated. Lines 220 to 260 are the heart of
the program. The FOR statement in line 220 controls a loop that steps through
each point in the input signal, X[ ]. For each sample in the input signal, an
inner loop (lines 230-250) calculates a scaled and shifted version of the
impulse response, and adds it to the array accumulating the output signal,
Y[ ]. This nested loop structure (one loop within another loop) is a key
characteristic of convolution programs; become familiar with it.
Chapter 6- Convolution 115
FIGURE 6-7
A second example of convolution. The waveforms for the input signal and impulse response
are exchanged from the example of Fig. 6-5. Since convolution is commutative, the output
signals for the two examples are identical.
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
0 1 2 3 4 5 6 7 8
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-2
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x[n] h[n] y[n]
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
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1
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3
contribution
from x[ ] h[n- ]
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
contribution
from x[ ] h[n- ]
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
contribution
from x[ ] h[n- ]
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
contribution
from x[ ] h[n- ]
0 0 1 1
2 2 3 3
Output signal components
Keeping the indexing straight in line 240 can drive you crazy! Let's say we
are halfway through the execution of this program, so that we have just
begun action on sample X[40], i.e., I% = 40. The inner loop runs through
each point in the impulse response doing three things. First, the impulse
response is scaled by multiplying it by the value of the input sample. If this
were the only action taken by the inner loop, line 240 could be written,
Y[J%] = X[40]tH[J%]. Second, the scaled impulse is shifted 40 samples
to the right by adding this number to the index used in the output signal.
This second action would change line 240 to: Y[40+J%] = X[40]tH[J%].
Third, Y[ ] must accumulate (synthesize) all the signals resulting from each
sample in the input signal. Therefore, the new information must be added
to the information that is already in the array. This results in the final
command: Y[40+J%] = Y[40+J%] + X[40]tH[J%]. Study this carefully;
it is very confusing, but very important.
116 The Scientist and Engineer's Guide to Digital Signal Processing
The Output Side Algorithm
The first viewpoint of convolution analyzes how each sample in the input
signal affects many samples in the output signal. In this second viewpoint,
we reverse this by looking at individual samples in the output signal, and
finding the contributing points from the input. This is important from both
mathematical and practical standpoints. Suppose that we are given some
input signal and impulse response, and want to find the convolution of the
two. The most straightforward method would be to write a program that
loops through the output signal, calculating one sample on each loop cycle.
Likewise, equations are written in the form: y[n] ’ some combination of
other variables. That is, sample n in the output signal is equal to some
combination of the many values in the input signal and impulse response.
This requires a knowledge of how each sample in the output signal can be
calculated independently of all other samples in the output signal. The
output side algorithm provides this information.
Let's look at an example of how a single point in the output signal is influenced
by several points from the input. The example point we will use is y[6] in Fig.
6-5. This point is equal to the sum of all the sixth points in the nine output
components, shown in Fig. 6-6. Now, look closely at these nine output
components and identify which can affect y[6] . That is, find which of these
nine signals contains a nonzero sample at the sixth position. Five of the output
components only have added zeros (the diamond markers) at the sixth sample,
and can therefore be ignored. Only four of the output components are capable
of having a nonzero value in the sixth position. These are the output
components generated from the input samples: x[3], x[4], x[5], and x[6] . By
adding the sixth sample from each of these output components, y[6] is
determined as: y[6] ’ x[3]h[3] % x[4]h[2] % x[5]h[1] % x[6]h[0] . That is, four
samples from the input signal are multiplied by the four samples in the impulse
response, and the products added.
Figure 6-8 illustrates the output side algorithm as a convolution machine, a
flow diagram of how convolution occurs. Think of the input signal, x[n] , and
the output signal, y[n] , as fixed on the page. The convolution machine,
everything inside the dashed box, is free to move left and right as needed. The
convolution machine is positioned so that its output is aligned with the output
sample being calculated. Four samples from the input signal fall into the inputs
of the convolution machine. These values are multiplied by the indicated
samples in the impulse response, and the products are added. This produces the
value for the output signal, which drops into its proper place. For example,
y[6] i s s h own b e i n g c a l c u l a t e d f r om t h e f o u r i n p u t s amp l e s :
x[3], x[4], x[5], and x[6] .
To calculate y[7] , the convolution machine moves one sample to the right. This
results in another four samples entering the machine, x[4] through x[7] , and the
value for y[7] dropping into the proper place. This process is repeated for all
points in the output signal needing to be calculated.
Chapter 6- Convolution 117
0 1 2 3 4 5 6 7 8
-3
-2
-1
0
1
2
3
-3 -2 -1 0
3.0
2.0
1.0
0.0
1.0
2.0
3.0
x[n]
y[n]
h[n] 0
-1
-2
-3
2
3
1
(flipped)
FIGURE 6-8
The convolution machine. This is a flow diagram showing how each sample in the output signal
is influenced by the input signal and impulse response. See the text for details.
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
The arrangement of the impulse response inside the convolution machine is
very important. The impulse response is flipped left-for-right. This places
sample number zero on the right, and increasingly positive sample numbers
running to the left. Compare this to the normal impulse response in Fig. 6-5
to understand the geometry of this flip. Why is this flip needed? It simply
falls out of the mathematics. The impulse response describes how each point
in the input signal affects the output signal. This results in each point in the
output signal being affected by points in the input signal weighted by a flipped
impulse response.
118 The Scientist and Engineer's Guide to Digital Signal Processing
FIGURE 6-9
The convolution machine in action. Figures (a) through (d) show the convolution machine
set to calculate four different output signal samples, y[0], y[3], y[8], and y[11].
0 1 2 3 4 5 6 7 8
-3
-2
-1
0
1
2
3
-3 -2 -1 0
3.0
2.0
1.0
0.0
1.0
2.0
3.0
x[n]
y[n]
h[n] 0
-1
-2
-3
2
3
1
(flipped)
a. Set to calculate y[0]
0 1 2 3 4 5 6 7 8
-3
-2
-1
0
1
2
3
-3 -2 -1 0
3.0
2.0
1.0
0.0
1.0
2.0
3.0
x[n]
y[n]
h[n] 0
-1
-2
-3
2
3
1
(flipped)
b. Set to calculate y[3]
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
Figure 6-9 shows the convolution machine being used to calculate several
samples in the output signal. This diagram also illustrates a real nuisance in
convolution. In (a), the convolution machine is located fully to the left with its
output aimed at y[0] . In this position, it is trying to receive input from
samples: x[&3], x[&2], x[&1], and x[0] . The problem is, three of these samples:
x[&3], x[&2], and x[&1] , do not exist! This same dilemma arises in (d), where
the convolution machine tries to accept samples to the right of the defined input
signal, points x[9], x[10], and x[11] .
One way to handle this problem is by inventing the nonexistent samples. This
involves adding samples to the ends of the input signal, with each of the added
samples having a value of zero. This is called padding the signal with zeros.
Instead of trying to access a nonexistent value, the convolution machine
receives a sample that has a value of zero. Since this zero is eliminated
during the multiplication, the result is mathematically the same as ignoring the
nonexistent inputs.
Chapter 6- Convolution 119
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
0 1 2 3 4 5 6 7 8
-3
-2
-1
0
1
2
3
-3 -2 -1 0
3.0
2.0
1.0
0.0
1.0
2.0
3.0
x[n]
y[n]
h[n] 0
-1
-2
-3
2
3
1
(flipped)
c. Set to calculate y[8]
0 1 2 3 4 5 6 7 8
-3
-2
-1
0
1
2
3
-3 -2 -1 0
3.0
2.0
1.0
0.0
1.0
2.0
3.0
x[n]
y[n]
h[n] 0
-1
-2
-3
2
3
1
(flipped)
d. Set to calculate y[11]
Figure 6-9 (continued)
The important part is that the far left and far right samples in the output signal
are based on incomplete information. In DSP jargon, the impulse response
is not fully immersed in the input signal. If the impulse response is M
points in length, the first and last M&1 samples in the output signal are based
on less information than the samples between. This is analogous to an
electronic circuit requiring a certain amount of time to stabilize after the power
is applied. The difference is that this transient is easy to ignore in electronics,
but very prominent in DSP.
Figure 6-10 shows an example of the trouble these end effects can cause. The
input signal is a sine wave plus a DC component. The desire is to remove the
DC part of the signal, while leaving the sine wave intact. This calls for a highpass
filter, such as the impulse response shown in the figure. The problem is,
the first and last 30 points are a mess! The shape of these end regions can be
understood by imagining the input signal padded with 30 zeros on the left side,
samples x[&1] through x[&30] , and 30 zeros on the right, samples x[81]
through x[110] . The output signal can then be viewed as a filtered version
of this longer waveform. These "end effect" problems are widespread in
120 The Scientist and Engineer's Guide to Digital Signal Processing
EQUATION 6-1
The convolution summation. This is the
formal definition of convolution, written in
the shorthand: y [n] ’ x [n] t h[n]. In this
equation, h[n] is an M point signal with
indexes running from 0 to M-1.
y [i ] ’ jM&1
j ’0
h[ j ] x [i&j ]
DSP. As a general rule, expect that the beginning and ending samples in
processed signals will be quite useless.
Now the math. Using the convolution machine as a guideline, we can write the
standard equation for convolution. If x[n] is an N point signal running from 0
to N-1, and h[n] is an M point signal running from 0 to M-1, the convolution
of the two: y[n] ’ x[n] t h[n], is an N+M-1 point signal running from 0 to
N+M-2, given by:
This equation is called the convolution sum. It allows each point in the
output signal to be calculated independently of all other points in the output
signal. The index, i, determines which sample in the output signal is being
calculated, and therefore corresponds to the left-right position of the
convolution machine. In computer programs performing convolution, a loop
makes this index run through each sample in the output signal. To
calculate one of the output samples, the index, j, is used inside of the
convolution machine. As j runs through 0 to M-1, each sample in the
impulse response, h[ j], is multiplied by the proper sample from the input
signal, x[i& j ]. All these products are added to produce the output sample
being calculated. Study Eq. 6-1 until you fully understand how it is
implemented by the convolution machine. Much of DSP is based on this
equation. (Don't be confused by the n in y[n] ’ x[n] t h[n]. This is merely
a place holder to indicate that some variable is the index into the array.
Sometimes the equations are written: y[ ] ’ x[ ] t h[ ], just to avoid having
to bring in a meaningless symbol).
Table 6-2 shows a program for performing convolutions using the output side
algorithm, a direct use of Eq. 6-1. This program produces the same output
signal as the program for the input side algorithm, shown previously in Table
6-1. Notice the main difference between these two programs: the input side
algorithm loops through each sample in the input signal (line 220 of Table 6-
1), while the output side algorithm loops through each sample in the output
signal (line 180 of Table 6-2).
Here is a detailed operation of this program. The FOR-NEXT loop in lines 180
to 250 steps through each sample in the output signal, using I% as the index.
For each of these values, an inner loop, composed of lines 200 to 230,
calculates the value of the output sample, Y[I%]. The value of Y[I%] is set
to zero in line 190, allowing it to accumulate the products inside of the
convolution machine. The FOR-NEXT loop in lines 200 to 240 provide a
direct implementation of Eq. 6-1. The index, J%, steps through each
Chapter 6- Convolution 121
sample in the impulse response. Line 230 provides the multiplication of each
sample in the impulse response, H[J%], with the appropriate sample from the
input signal, X[I%-J%], and adds the result to the accumulator.
In line 230, the sample taken from the input signal is: X[I%-J%]. Lines 210
and 220 prevent this from being outside the defined array, X[0] to X[80]. In
other words, this program handles undefined samples in the input signal by
ignoring them. Another alternative would be to define the input signal's array
from X[-30] to X[110], allowing 30 zeros to be padded on each side of the true
data. As a third alternative, the FOR-NEXT loop in line 180 could be changed
to run from 30 to 80, rather than 0 to 110. That is, the program would only
calculate the samples in the output signal where the impulse response is fully
immersed in the input signal. The important thing is that you must use one of
these three techniques. If you don't, the program will crash when it tries to read
the out-of-bounds data.
S
0 10 20 30
-0.5
0.0
0.5
1.0
1.5
Sample number
0 10 20 30 40 50 60 70 80
-4
-2
0
2
4
Sample number
0 10 20 30 40 50 60 70 80 90 100 110
-4
-2
0
2
4
Input signal Impulse response Output signal
unusable usable unusable
Sample number
Amplitude
Amplitude
Amplitude
FIGURE 6-10
End effects in convolution. When an input signal is convolved with an M point impulse response,
the first and last M-1 points in the output signal may not be usable. In this example, the impulse
response is a high-pass filter used to remove the DC component from the input signal.
100 'CONVOLUTION USING THE OUTPUT SIDE ALGORITHM
110 '
120 DIM X[80] 'The input signal, 81 points
130 DIM H[30] 'The impulse response, 31 points
140 DIM Y[110] 'The output signal, 111 points
150 '
160 GOSUB XXXX 'Mythical subroutine to load X[ ] and H[ ]
170 '
180 FOR I% = 0 TO 110 'Loop for each point in Y[ ]
190 Y[I%] = 0 'Zero the sample in the output array
200 FOR J% = 0 TO 30 'Loop for each point in H[ ]
210 IF (I%-J% < 0) THEN GOTO 240
220 IF (I%-J% > 80) THEN GOTO 240
230 Y(I%) = Y(I%) + H(J%) t X(I%-J%)
240 NEXT J%
250 NEXT I%
260 '
270 GOSUB XXXX 'Mythical subroutine to store Y[ ]
280 '
290 END
TABLE 6-2
122 The Scientist and Engineer's Guide to Digital Signal Processing
The Sum of Weighted Inputs
The characteristics of a linear system are completely described by its impulse
response. This is the basis of the input side algorithm: each point in the input
signal contributes a scaled and shifted version of the impulse response to the
output signal. The mathematical consequences of this lead to the output side
algorithm: each point in the output signal receives a contribution from many
points in the input signal, multiplied by a flipped impulse response. While this
is all true, it doesn't provide the full story on why convolution is important in
signal processing.
Look back at the convolution machine in Fig. 6-8, and ignore that the signal
inside the dotted box is an impulse response. Think of it as a set of weighing
coefficients that happen to be embedded in the flow diagram. In this view,
each sample in the output signal is equal to a sum of weighted inputs. Each
sample in the output is influenced by a region of samples in the input signal,
as determined by what the weighing coefficients are chosen to be. For
example, imagine there are ten weighing coefficients, each with a value of onetenth.
This makes each sample in the output signal the average of ten samples
from the input.
Taking this further, the weighing coefficients do not need to be restricted to the
left side of the output sample being calculated. For instance, Fig. 6-8 shows y[6]
being calculated from: x[3], x[4], x[5], and x[6] . Viewing the convolution
machine as a sum of weighted inputs, the weighing coefficients could be chosen
symmetrically around the output sample. For example, y[6] might receive
contributions from: x[4], x[5], x[6], x[7], and x[8] . Using the same indexing
notation as in Fig. 6-8, the weighing coefficients for these five inputs would be
held in: h[2], h[1], h[0], h[&1], and h[&2] . In other words, the impulse
response that corresponds to our selection of symmetrical weighing coefficients
requires the use of negative indexes. We will return to this in the next chapter.
Mathematically, there is only one concept here: convolution as defined by Eq.
6-1. However, science and engineering problems approach this single concept
from two distinct directions. Sometimes you will want to think of a system in
terms of what its impulse response looks like. Other times you will understand
the system as a set of weighing coefficients. You need to become familiar with
both views, and how to toggle between them.
Digital Signal Processors
Digital Signal Processing is carried out by mathematical operations. In comparison, word
processing and similar programs merely rearrange stored data. This means that computers
designed for business and other general applications are not optimized for algorithms such as
digital filtering and Fourier analysis. Digital Signal Processors are microprocessors specifically
designed to handle Digital Signal Processing tasks. These devices have seen tremendous growth
in the last decade, finding use in everything from cellular telephones to advanced scientific
instruments. In fact, hardware engineers use "DSP" to mean Digital Signal Processor, just as
algorithm developers use "DSP" to mean Digital Signal Processing. This chapter looks at how
DSPs are different from other types of microprocessors, how to decide if a DSP is right for your
application, and how to get started in this exciting new field. In the next chapter we will take a
more detailed look at one of these sophisticated products: the Analog Devices SHARC® family.
How DSPs are Different from Other Microprocessors
In the 1960s it was predicted that artificial intelligence would revolutionize the
way humans interact with computers and other machines. It was believed that
by the end of the century we would have robots cleaning our houses, computers
driving our cars, and voice interfaces controlling the storage and retrieval of
information. This hasn't happened; these abstract tasks are far more
complicated than expected, and very difficult to carry out with the step-by-step
logic provided by digital computers.
However, the last forty years have shown that computers are extremely capable
in two broad areas, (1) data manipulation, such as word processing and
database management, and (2) mathematical calculation, used in science,
engineering, and Digital Signal Processing. All microprocessors can perform
both tasks; however, it is difficult (expensive) to make a device that is
optimized for both. There are technical tradeoffs in the hardware design, such
as the size of the instruction set and how interrupts are handled. Even
504 The Scientist and Engineer's Guide to Digital Signal Processing
Data Manipulation Math Calculation
Word processing, database
management, spread sheets,
operating sytems, etc.
Digital Signal Processing,
motion control, scientific and
engineering simulations, etc.
data movement (A º B)
value testing (If A=B then ...)
addition (A+B=C )
multiplication (A×B=C )
Typical
Applications
Main
Operations
FIGURE 28-1
Data manipulation versus mathematical calculation. Digital computers are useful for two general
tasks: data manipulation and mathematical calculation. Data manipulation is based on moving
data and testing inequalities, while mathematical calculation uses multiplication and addition.
more important, there are marketing issues involved: development and
manufacturing cost, competitive position, product lifetime, and so on. As a
broad generalization, these factors have made traditional microprocessors, such
as the Pentium®, primarily directed at data manipulation. Similarly, DSPs are
designed to perform the mathematical calculations needed in Digital Signal
Processing.
Figure 28-1 lists the most important differences between these two
categories. Data manipulation involves storing and sorting information.
For instance, consider a word processing program. The basic task is to
store the information (typed in by the operator), organize the information
(cut and paste, spell checking, page layout, etc.), and then retrieve the
information (such as saving the document on a floppy disk or printing it
with a laser printer). These tasks are accomplished by moving data from
one location to another, and testing for inequalities (A=B, AB THEN ...). Second, if the two entries
are not in alphabetical order, switch them so that they are (AWB). When
this two step process is repeated many times on all adjacent pairs, the list
will eventually become alphabetized.
As another example, consider how a document is printed from a word
processor. The computer continually tests the input device (mouse or keyboard)
for the binary code that indicates "print the document." When this code is
detected, the program moves the data from the computer's memory to the
printer. Here we have the same two basic operations: moving data and
inequality testing. While mathematics is occasionally used in this type of
Chapter 28- Digital Signal Processors 505
y[n] ’ a0 x[n] % a1 x[n&1] % a2 x[n&2] % a3 x[n&3] % a4 x[n&4] % þ
×a0
×a1
×a2
×a3
×a4
×a5
×a6
×a7
Input Signal, x[ ]
Output signal, y[ ]
x[n]
x[n-1]
x[n-2]
x[n-3]
y[n]
FIGURE 28-2
FIR digital filter. In FIR filtering, each
sample in the output signal, y[n], is found
by multiplying samples from the input
signal, x[n], x[n-1], x[n-2], ..., by the filter
kernel coefficients, a0, a1, a2, a3 ..., and
summing the products.
application, it is infrequent and does not significantly affect the overall
execution speed.
In comparison, the execution speed of most DSP algorithms is limited almost
completely by the number of multiplications and additions required. For
example, Fig. 28-2 shows the implementation of an FIR digital filter, the most
common DSP technique. Using the standard notation, the input signal is
referred to by x[ ], while the output signal is denoted by y[ ]. Our task is to
calculate the sample at location n in the output signal, i.e., y[n] . An FIR filter
performs this calculation by multiplying appropriate samples from the input
signal by a group of coefficients, denoted by: a , and then adding 0, a1, a2, a3,þ
the products. In equation form, y[n] is found by:
This is simply saying that the input signal has been convolved with a filter
kernel (i.e., an impulse response) consisting of: a . Depending on 0, a1, a2, a3,þ
the application, there may only be a few coefficients in the filter kernel, or
many thousands. While there is some data transfer and inequality evaluation
in this algorithm, such as to keep track of the intermediate results and control
the loops, the math operations dominate the execution time.
506 The Scientist and Engineer's Guide to Digital Signal Processing
In addition to preforming mathematical calculations very rapidly, DSPs must
also have a predictable execution time. Suppose you launch your desktop
computer on some task, say, converting a word-processing document from one
form to another. It doesn't matter if the processing takes ten milliseconds or
ten seconds; you simply wait for the action to be completed before you give the
computer its next assignment.
In comparison, most DSPs are used in applications where the processing is
continuous, not having a defined start or end. For instance, consider an
engineer designing a DSP system for an audio signal, such as a hearing aid.
If the digital signal is being received at 20,000 samples per second, the DSP
must be able to maintain a sustained throughput of 20,000 samples per second.
However, there are important reasons not to make it any faster than necessary.
As the speed increases, so does the cost, the power consumption, the design
difficulty, and so on. This makes an accurate knowledge of the execution time
critical for selecting the proper device, as well as the algorithms that can be
applied.
Circular Buffering
Digital Signal Processors are designed to quickly carry out FIR filters and
similar techniques. To understand the hardware, we must first understand the
algorithms. In this section we will make a detailed list of the steps needed to
implement an FIR filter. In the next section we will see how DSPs are
designed to perform these steps as efficiently as possible.
To start, we need to distinguish between off-line processing and real-time
processing. In off-line processing, the entire input signal resides in the
computer at the same time. For example, a geophysicist might use a
seismometer to record the ground movement during an earthquake. After the
shaking is over, the information may be read into a computer and analyzed in
some way. Another example of off-line processing is medical imaging, such
as computed tomography and MRI. The data set is acquired while the patient
is inside the machine, but the image reconstruction may be delayed until a later
time. The key point is that all of the information is simultaneously available
to the processing program. This is common in scientific research and
engineering, but not in consumer products. Off-line processing is the realm of
personal computers and mainframes.
In real-time processing, the output signal is produced at the same time that the
input signal is being acquired. For example, this is needed in telephone
communication, hearing aids, and radar. These applications must have the
information immediately available, although it can be delayed by a short
amount. For instance, a 10 millisecond delay in a telephone call cannot be
detected by the speaker or listener. Likewise, it makes no difference if a
radar signal is delayed by a few seconds before being displayed to the
operator. Real-time applications input a sample, perform the algorithm, and
output a sample, over-and-over. Alternatively, they may input a group
Chapter 28- Digital Signal Processors 507
x[n-3]
x[n-2]
x[n-1]
x[n]
x[n-6]
x[n-5]
x[n-4]
x[n-7]
20040
20041
20042
20043
20044
20045
20046
20047
20048
20049
-0.225767
-0.269847
-0.228918
-0.113940
-0.048679
-0.222977
-0.371370
-0.462791
ADDRESS VALUE
newest sample
oldest sample
MEMORY STORED
x[n-4]
x[n-3]
x[n-2]
x[n-1]
x[n-7]
x[n-6]
x[n-5]
x[n]
20040
20041
20042
20043
20044
20045
20046
20047
20048
20049
-0.225767
-0.269847
-0.228918
-0.113940
-0.062222
-0.222977
-0.371370
-0.462791
ADDRESS VALUE
newest sample
oldest sample
MEMORY STORED
a. Circular buffer at some instant b. Circular buffer after next sample
FIGURE 28-3
Circular buffer operation. Circular buffers are used to store the most recent values of a continually
updated signal. This illustration shows how an eight sample circular buffer might appear at some
instant in time (a), and how it would appear one sample later (b).
of samples, perform the algorithm, and output a group of samples. This is the
world of Digital Signal Processors.
Now look back at Fig. 28-2 and imagine that this is an FIR filter being
implemented in real-time. To calculate the output sample, we must have access
to a certain number of the most recent samples from the input. For example,
suppose we use eight coefficients in this filter, a . This means we 0, a1, þ a7
must know the value of the eight most recent samples from the input signal,
x[n], x[n&1], þ x[n&7] . These eight samples must be stored in memory and
continually updated as new samples are acquired. What is the best way to
manage these stored samples? The answer is circular buffering.
Figure 28-3 illustrates an eight sample circular buffer. We have placed this
circular buffer in eight consecutive memory locations, 20041 to 20048. Figure
(a) shows how the eight samples from the input might be stored at one
particular instant in time, while (b) shows the changes after the next sample
is acquired. The idea of circular buffering is that the end of this linear array is
connected to its beginning; memory location 20041 is viewed as being next to
20048, just as 20044 is next to 20045. You keep track of the array by a
pointer (a variable whose value is an address) that indicates where the most
recent sample resides. For instance, in (a) the pointer contains the address
20044, while in (b) it contains 20045. When a new sample is acquired, it
replaces the oldest sample in the array, and the pointer is moved one address
ahead. Circular buffers are efficient because only one value needs to be
changed when a new sample is acquired.
Four parameters are needed to manage a circular buffer. First, there must be
a pointer that indicates the start of the circular buffer in memory (in this
example, 20041). Second, there must be a pointer indicating the end of the
508 The Scientist and Engineer's Guide to Digital Signal Processing
1. Obtain a sample with the ADC; generate an interrupt
2. Detect and manage the interrupt
3. Move the sample into the input signal's circular buffer
4. Update the pointer for the input signal's circular buffer
5. Zero the accumulator
6. Control the loop through each of the coefficients
7. Fetch the coefficient from the coefficient's circular buffer
8. Update the pointer for the coefficient's circular buffer
9. Fetch the sample from the input signal's circular buffer
10. Update the pointer for the input signal's circular buffer
11. Multiply the coefficient by the sample
12. Add the product to the accumulator
13. Move the output sample (accumulator) to a holding buffer
14. Move the output sample from the holding buffer to the DAC
TABLE 28-1
FIR filter steps.
array (e.g., 20048), or a variable that holds its length (e.g., 8). Third, the step
size of the memory addressing must be specified. In Fig. 28-3 the step size is
one, for example: address 20043 contains one sample, address 20044 contains
the next sample, and so on. This is frequently not the case. For instance, the
addressing may refer to bytes, and each sample may require two or four bytes
to hold its value. In these cases, the step size would need to be two or four,
respectively.
These three values define the size and configuration of the circular buffer, and
will not change during the program operation. The fourth value, the pointer to
the most recent sample, must be modified as each new sample is acquired. In
other words, there must be program logic that controls how this fourth value is
updated based on the value of the first three values. While this logic is quite
simple, it must be very fast. This is the whole point of this discussion; DSPs
should be optimized at managing circular buffers to achieve the highest
possible execution speed.
As an aside, circular buffering is also useful in off-line processing. Consider
a program where both the input and the output signals are completely contained
in memory. Circular buffering isn't needed for a convolution calculation,
because every sample can be immediately accessed. However, many algorithms
are implemented in stages, with an intermediate signal being created between
each stage. For instance, a recursive filter carried out as a series of biquads
operates in this way. The brute force method is to store the entire length of
each intermediate signal in memory. Circular buffering provides another
option: store only those intermediate samples needed for the calculation at
hand. This reduces the required amount of memory, at the expense of a more
complicated algorithm. The important idea is that circular buffers are useful
for off-line processing, but critical for real-time applications.
Now we can look at the steps needed to implement an FIR filter using circular
buffers for both the input signal and the coefficients. This list may seem trivial
and overexamined- it's not! The efficient handling of these individual tasks is
what separates a DSP from a traditional microprocessor. For each new sample,
all the following steps need to be taken:
Chapter 28- Digital Signal Processors 509
The goal is to make these steps execute quickly. Since steps 6-12 will be
repeated many times (once for each coefficient in the filter), special attention
must be given to these operations. Traditional microprocessors must generally
carry out these 14 steps in serial (one after another), while DSPs are designed
to perform them in parallel. In some cases, all of the operations within the
loop (steps 6-12) can be completed in a single clock cycle. Let's look at the
internal architecture that allows this magnificent performance.
Architecture of the Digital Signal Processor
One of the biggest bottlenecks in executing DSP algorithms is transferring
information to and from memory. This includes data, such as samples from the
input signal and the filter coefficients, as well as program instructions, the
binary codes that go into the program sequencer. For example, suppose we
need to multiply two numbers that reside somewhere in memory. To do this,
we must fetch three binary values from memory, the numbers to be multiplied,
plus the program instruction describing what to do.
Figure 28-4a shows how this seemingly simple task is done in a traditional
microprocessor. This is often called a Von Neumann architecture, after the
brilliant American mathematician John Von Neumann (1903-1957). Von
Neumann guided the mathematics of many important discoveries of the early
twentieth century. His many achievements include: developing the concept of
a stored program computer, formalizing the mathematics of quantum mechanics,
and work on the atomic bomb. If it was new and exciting, Von Neumann was
there!
As shown in (a), a Von Neumann architecture contains a single memory and a
single bus for transferring data into and out of the central processing unit
(CPU). Multiplying two numbers requires at least three clock cycles, one to
transfer each of the three numbers over the bus from the memory to the CPU.
We don't count the time to transfer the result back to memory, because we
assume that it remains in the CPU for additional manipulation (such as the sum
of products in an FIR filter). The Von Neumann design is quite satisfactory
when you are content to execute all of the required tasks in serial. In fact,
most computers today are of the Von Neumann design. We only need other
architectures when very fast processing is required, and we are willing to pay
the price of increased complexity.
This leads us to the Harvard architecture, shown in (b). This is named for
the work done at Harvard University in the 1940s under the leadership of
Howard Aiken (1900-1973). As shown in this illustration, Aiken insisted on
separate memories for data and program instructions, with separate buses for
each. Since the buses operate independently, program instructions and data can
be fetched at the same time, improving the speed over the single bus design.
Most present day DSPs use this dual bus architecture.
Figure (c) illustrates the next level of sophistication, the Super Harvard
Architecture. This term was coined by Analog Devices to describe the
510 The Scientist and Engineer's Guide to Digital Signal Processing
internal operation of their ADSP-2106x and new ADSP-211xx families of
Digital Signal Processors. These are called SHARC® DSPs, a contraction of
the longer term, Super Harvard ARChitecture. The idea is to build upon the
Harvard architecture by adding features to improve the throughput. While the
SHARC DSPs are optimized in dozens of ways, two areas are important
enough to be included in Fig. 28-4c: an instruction cache, and an I/O
controller.
First, let's look at how the instruction cache improves the performance of the
Harvard architecture. A handicap of the basic Harvard design is that the data
memory bus is busier than the program memory bus. When two numbers are
multiplied, two binary values (the numbers) must be passed over the data
memory bus, while only one binary value (the program instruction) is passed
over the program memory bus. To improve upon this situation, we start by
relocating part of the "data" to program memory. For instance, we might place
the filter coefficients in program memory, while keeping the input signal in data
memory. (This relocated data is called "secondary data" in the illustration).
At first glance, this doesn't seem to help the situation; now we must transfer
one value over the data memory bus (the input signal sample), but two values
over the program memory bus (the program instruction and the coefficient). In
fact, if we were executing random instructions, this situation would be no better
at all.
However, DSP algorithms generally spend most of their execution time in
loops, such as instructions 6-12 of Table 28-1. This means that the same set
of program instructions will continually pass from program memory to the
CPU. The Super Harvard architecture takes advantage of this situation by
including an instruction cache in the CPU. This is a small memory that
contains about 32 of the most recent program instructions. The first time
through a loop, the program instructions must be passed over the program
memory bus. This results in slower operation because of the conflict with the
coefficients that must also be fetched along this path. However, on additional
executions of the loop, the program instructions can be pulled from the
instruction cache. This means that all of the memory to CPU information
transfers can be accomplished in a single cycle: the sample from the input
signal comes over the data memory bus, the coefficient comes over the program
memory bus, and the program instruction comes from the instruction cache. In
the jargon of the field, this efficient transfer of data is called a high memoryaccess
bandwidth.
Figure 28-5 presents a more detailed view of the SHARC architecture,
showing the I/O controller connected to data memory. This is how the
signals enter and exit the system. For instance, the SHARC DSPs provides
both serial and parallel communications ports. These are extremely high
speed connections. For example, at a 40 MHz clock speed, there are two
serial ports that operate at 40 Mbits/second each, while six parallel ports
each provide a 40 Mbytes/second data transfer. When all six parallel
ports are used together, the data transfer rate is an incredible 240
Mbytes/second.
Chapter 28- Digital Signal Processors 511
Memory
data and
instructions
Program
Memory
Data
Memory
instructions and
secondary data data only
Program
Memory
Data
Memory
instructions only data only
a. Von Neumann Architecture ( )
b. Harvard Architecture ( )
c. Super Harvard Architecture ( )
address bus CPU
data bus
PM address bus
PM data bus
PM address bus
PM data bus
DM address bus
DM data bus
CPU
DM address bus
DM data bus
single memory
dual memory
dual memory, instruction cache, I/O controller
Instruction
Cache
CPU
I/O
Controller
data
FIGURE 28-4
Microprocessor architecture. The Von Neumann architecture
uses a single memory to hold both data and instructions. In
comparison, the Harvard architecture uses separate memories
for data and instructions, providing higher speed. The Super
Harvard Architecture improves upon the Harvard design by
adding an instruction cache and a dedicated I/O controller.
This is fast enough to transfer the entire text of this book in only 2
milliseconds! Just as important, dedicated hardware allows these data streams
to be transferred directly into memory (Direct Memory Access, or DMA),
without having to pass through the CPU's registers. In other words, tasks 1 &
14 on our list happen independently and simultaneously with the other tasks;
no cycles are stolen from the CPU. The main buses (program memory bus and
data memory bus) are also accessible from outside the chip, providing an
additional interface to off-chip memory and peripherals. This allows the
SHARC DSPs to use a four Gigaword (16 Gbyte) memory, accessible at 40
Mwords/second (160 Mbytes/second), for 32 bit data. Wow!
This type of high speed I/O is a key characteristic of DSPs. The overriding
goal is to move the data in, perform the math, and move the data out before the
next sample is available. Everything else is secondary. Some DSPs have onboard
analog-to-digital and digital-to-analog converters, a feature called mixed
signal. However, all DSPs can interface with external converters through
serial or parallel ports.
512 The Scientist and Engineer's Guide to Digital Signal Processing
Now let's look inside the CPU. At the top of the diagram are two blocks
labeled Data Address Generator (DAG), one for each of the two
memories. These control the addresses sent to the program and data
memories, specifying where the information is to be read from or written to.
In simpler microprocessors this task is handled as an inherent part of the
program sequencer, and is quite transparent to the programmer. However,
DSPs are designed to operate with circular buffers, and benefit from the
extra hardware to manage them efficiently. This avoids needing to use
precious CPU clock cycles to keep track of how the data are stored. For
instance, in the SHARC DSPs, each of the two DAGs can control eight
circular buffers. This means that each DAG holds 32 variables (4 per
buffer), plus the required logic.
Why so many circular buffers? Some DSP algorithms are best carried out in
stages. For instance, IIR filters are more stable if implemented as a cascade
of biquads (a stage containing two poles and up to two zeros). Multiple stages
require multiple circular buffers for the fastest operation. The DAGs in the
SHARC DSPs are also designed to efficiently carry out the Fast Fourier
transform. In this mode, the DAGs are configured to generate bit-reversed
addresses into the circular buffers, a necessary part of the FFT algorithm. In
addition, an abundance of circular buffers greatly simplifies DSP code
generation- both for the human programmer as well as high-level language
compilers, such as C.
The data register section of the CPU is used in the same way as in traditional
microprocessors. In the ADSP-2106x SHARC DSPs, there are 16 general
purpose registers of 40 bits each. These can hold intermediate calculations,
prepare data for the math processor, serve as a buffer for data transfer, hold
flags for program control, and so on. If needed, these registers can also be
used to control loops and counters; however, the SHARC DSPs have extra
hardware registers to carry out many of these functions.
The math processing is broken into three sections, a multiplier, an
arithmetic logic unit (ALU), and a barrel shifter. The multiplier takes
the values from two registers, multiplies them, and places the result into
another register. The ALU performs addition, subtraction, absolute value,
logical operations (AND, OR, XOR, NOT), conversion between fixed and
floating point formats, and similar functions. Elementary binary operations
are carried out by the barrel shifter, such as shifting, rotating, extracting
and depositing segments, and so on. A powerful feature of the SHARC
family is that the multiplier and the ALU can be accessed in parallel. In a
single clock cycle, data from registers 0-7 can be passed to the multiplier,
data from registers 8-15 can be passed to the ALU, and the two results
returned to any of the 16 registers.
There are also many important features of the SHARC family architecture that
aren't shown in this simplified illustration. For instance, an 80 bit
accumulator is built into the multiplier to reduce the round-off error
associated with multiple fixed-point math operations. Another interesting
Chapter 28- Digital Signal Processors 513
Program
Memory
Data
Memory
instructions and
secondary data data only
Address
PM Data
Generator
Address
DM Data
Generator
Data
Registers
Muliplier
ALU
Shifter
PM address bus DM address bus
PM data bus DM data bus
Program Sequencer
Instruction
Cache
I/O Controller
(DMA)
High speed I/O
(serial, parallel,
ADC, DAC, etc.)
FIGURE 28-5
Typical DSP architecture. Digital Signal Processors are designed to implement tasks in parallel. This
simplified diagram is of the Analog Devices SHARC DSP. Compare this architecture with the tasks
needed to implement an FIR filter, as listed in Table 28-1. All of the steps within the loop can be
executed in a single clock cycle.
feature is the use of shadow registers for all the CPU's key registers. These
are duplicate registers that can be switched with their counterparts in a single
clock cycle. They are used for fast context switching, the ability to handle
interrupts quickly. When an interrupt occurs in traditional microprocessors, all
the internal data must be saved before the interrupt can be handled. This
usually involves pushing all of the occupied registers onto the stack, one at a
time. In comparison, an interrupt in the SHARC family is handled by moving
the internal data into the shadow registers in a single clock cycle. When the
interrupt routine is completed, the registers are just as quickly restored. This
feature allows step 4 on our list (managing the sample-ready interrupt) to be
handled very quickly and efficiently.
Now we come to the critical performance of the architecture, how many of the
operations within the loop (steps 6-12 of Table 28-1) can be carried out at the
same time. Because of its highly parallel nature, the SHARC DSP can
simultaneously carry out all of these tasks. Specifically, within a single clock
cycle, it can perform a multiply (step 11), an addition (step 12), two data
moves (steps 7 and 9), update two circular buffer pointers (steps 8 and 10), and
514 The Scientist and Engineer's Guide to Digital Signal Processing
control the loop (step 6). There will be extra clock cycles associated with
beginning and ending the loop (steps 3, 4, 5 and 13, plus moving initial values
into place); however, these tasks are also handled very efficiently. If the loop
is executed more than a few times, this overhead will be negligible. As an
example, suppose you write an efficient FIR filter program using 100
coefficients. You can expect it to require about 105 to 110 clock cycles per
sample to execute (i.e., 100 coefficient loops plus overhead). This is very
impressive; a traditional microprocessor requires many thousands of clock
cycles for this algorithm.
Fixed versus Floating Point
Digital Signal Processing can be divided into two categories, fixed point and
floating point. These refer to the format used to store and manipulate
numbers within the devices. Fixed point DSPs usually represent each number
with a minimum of 16 bits, although a different length can be used. For
instance, Motorola manufactures a family of fixed point DSPs that use 24 bits.
There are four common ways that these 216 ’ 65,536 possible bit patterns can
represent a number. In unsigned integer, the stored number can take on any
integer value from 0 to 65,535. Similarly, signed integer uses two's
complement to make the range include negative numbers, from -32,768 to
32,767. With unsigned fraction notation, the 65,536 levels are spread
uniformly between 0 and 1. Lastly, the signed fraction format allows
negative numbers, equally spaced between -1 and 1.
In comparison, floating point DSPs typically use a minimum of 32 bits to
store each value. This results in many more bit patterns than for fixed
point, 232 ’ 4,294,967,296 to be exact. A key feature of floating point notation
is that the represented numbers are not uniformly spaced. In the most common
format (ANSI/IEEE Std. 754-1985), the largest and smallest numbers are
±3.4×1038 and ±1.2×10 , respectively. The represented values are unequally &38
spaced between these two extremes, such that the gap between any two
numbers is about ten-million times smaller than the value of the numbers.
This is important because it places large gaps between large numbers, but small
gaps between small numbers. Floating point notation is discussed in more
detail in Chapter 4.
All floating point DSPs can also handle fixed point numbers, a necessity to
implement counters, loops, and signals coming from the ADC and going to the
DAC. However, this doesn't mean that fixed point math will be carried out as
quickly as the floating point operations; it depends on the internal architecture.
For instance, the SHARC DSPs are optimized for both floating point and fixed
point operations, and executes them with equal efficiency. For this reason, the
SHARC devices are often referred to as "32-bit DSPs," rather than just
"Floating Point."
Figure 28-6 illustrates the primary trade-offs between fixed and floating point
DSPs. In Chapter 3 we stressed that fixed point arithmetic is much
Chapter 28- Digital Signal Processors 515
Precision Product Cost
Development Time
Floating Point Fixed Point
FIGURE 28-6 Dynamic Range
Fixed versus floating point. Fixed point DSPs
are generally cheaper, while floating point
devices have better precision, higher dynamic
range, and a shorter development cycle.
faster than floating point in general purpose computers. However, with DSPs
the speed is about the same, a result of the hardware being highly optimized for
math operations. The internal architecture of a floating point DSP is more
complicated than for a fixed point device. All the registers and data buses must
be 32 bits wide instead of only 16; the multiplier and ALU must be able to
quickly perform floating point arithmetic, the instruction set must be larger (so
that they can handle both floating and fixed point numbers), and so on.
Floating point (32 bit) has better precision and a higher dynamic range than
fixed point (16 bit) . In addition, floating point programs often have a shorter
development cycle, since the programmer doesn't generally need to worry about
issues such as overflow, underflow, and round-off error.
On the other hand, fixed point DSPs have traditionally been cheaper than
floating point devices. Nothing changes more rapidly than the price of
electronics; anything you find in a book will be out-of-date before it is
printed. Nevertheless, cost is a key factor in understanding how DSPs are
evolving, and we need to give you a general idea. When this book was
completed in 1999, fixed point DSPs sold for between $5 and $100, while
floating point devices were in the range of $10 to $300. This difference in
cost can be viewed as a measure of the relative complexity between the
devices. If you want to find out what the prices are today, you need to look
today.
Now let's turn our attention to performance; what can a 32-bit floating point
system do that a 16-bit fixed point can't? The answer to this question is
signal-to-noise ratio. Suppose we store a number in a 32 bit floating point
format. As previously mentioned, the gap between this number and its adjacent
neighbor is about one ten-millionth of the value of the number. To store the
number, it must be round up or down by a maximum of one-half the gap size.
In other words, each time we store a number in floating point notation, we add
noise to the signal.
The same thing happens when a number is stored as a 16-bit fixed point value,
except that the added noise is much worse. This is because the gaps between
adjacent numbers are much larger. For instance, suppose we store the number
10,000 as a signed integer (running from -32,768 to 32,767). The gap between
numbers is one ten-thousandth of the value of the number we are storing. If we
516 The Scientist and Engineer's Guide to Digital Signal Processing
want to store the number 1000, the gap between numbers is only one onethousandth
of the value.
Noise in signals is usually represented by its standard deviation. This was
discussed in detail in Chapter 2. For here, the important fact is that the
standard deviation of this quantization noise is about one-third of the gap
size. This means that the signal-to-noise ratio for storing a floating point
number is about 30 million to one, while for a fixed point number it is only
about ten-thousand to one. In other words, floating point has roughly 30,000
times less quantization noise than fixed point.
This brings up an important way that DSPs are different from traditional
microprocessors. Suppose we implement an FIR filter in fixed point. To do
this, we loop through each coefficient, multiply it by the appropriate sample
from the input signal, and add the product to an accumulator. Here's the
problem. In traditional microprocessors, this accumulator is just another 16 bit
fixed point variable. To avoid overflow, we need to scale the values being
added, and will correspondingly add quantization noise on each step. In the
worst case, this quantization noise will simply add, greatly lowering the signalto-
noise ratio of the system. For instance, in a 500 coefficient FIR filter, the
noise on each output sample may be 500 times the noise on each input sample.
The signal-to-noise ratio of ten-thousand to one has dropped to a ghastly
twenty to one. Although this is an extreme case, it illustrates the main point:
when many operations are carried out on each sample, it's bad, really bad. See
Chapter 3 for more details.
DSPs handle this problem by using an extended precision accumulator.
This is a special register that has 2-3 times as many bits as the other memory
locations. For example, in a 16 bit DSP it may have 32 to 40 bits, while in the
SHARC DSPs it contains 80 bits for fixed point use. This extended range
virtually eliminates round-off noise while the accumulation is in progress. The
only round-off error suffered is when the accumulator is scaled and stored in
the 16 bit memory. This strategy works very well, although it does limit how
some algorithms must be carried out. In comparison, floating point has such
low quantization noise that these techniques are usually not necessary.
In addition to having lower quantization noise, floating point systems are also
easier to develop algorithms for. Most DSP techniques are based on repeated
multiplications and additions. In fixed point, the possibility of an overflow or
underflow needs to be considered after each operation. The programmer needs
to continually understand the amplitude of the numbers, how the quantization
errors are accumulating, and what scaling needs to take place. In comparison,
these issues do not arise in floating point; the numbers take care of themselves
(except in rare cases).
To give you a better understanding of this issue, Fig. 28-7 shows a table from
the SHARC user manual. This describes the ways that multiplication can be
carried out for both fixed and floating point formats. First, look at how
floating point numbers can be multiplied; there is only one way! That
Chapter 28- Digital Signal Processors 517
Rn
MRF
MRB
Rn
Rn
MRF
MRB
Rn
Rn
MRF
MRB
Rn
Rn
MRF
MRB
Rn
Rn
MRF
MRB
MRF
MRB
MRxF
MRxB
Rn
= MRF
= MRB
= MRF
= MRB
= MRF
= MRB
= MRF
= MRB
= SAT MRF
= SAT MRB
= SAT MRF
= SAT MRB
= RND MRF
= RND MRB
= RND MRF
= RND MRB
= 0
= Rn
= MRxF
MRxB
= Rx * Ry
+ Rx * Ry
- Rx * Ry
S S F
U U I
FR
S
S
(SI)
(UI)
(SF)
(UF)
(SF)
(UF)
)
S F
U U I
FR
)
S F
U U I
FR
)
Fn = Fx * Fy
Fixed Point Floating Point
(
(
(
FIGURE 28-7
Fixed versus floating point instructions. These are the multiplication instructions used in
the SHARC DSPs. While only a single command is needed for floating point, many
options are needed for fixed point. See the text for an explanation of these options.
is, Fn = Fx * Fy, where Fn, Fx, and Fy are any of the 16 data registers. It
could not be any simpler. In comparison, look at all the possible commands for
fixed point multiplication. These are the many options needed to efficiently
handle the problems of round-off, scaling, and format.
In Fig. 28-7, Rn, Rx, and Ry refer to any of the 16 data registers, and MRF
and MRB are 80 bit accumulators. The vertical lines indicate options. For
instance, the top-left entry in this table means that all the following are valid
commands: Rn = Rx * Ry, MRF = Rx * Ry, and MRB = Rx * Ry. In other
words, the value of any two registers can be multiplied and placed into another
register, or into one of the extended precision accumulators. This table also
shows that the numbers may be either signed or unsigned (S or U), and may be
fractional or integer (F or I). The RND and SAT options are ways of
controlling rounding and register overflow.
518 The Scientist and Engineer's Guide to Digital Signal Processing
There are other details and options in the table, but they are not important for
our present discussion. The important idea is that the fixed point programmer
must understand dozens of ways to carry out the very basic task of
multiplication. In contrast, the floating point programmer can spend his time
concentrating on the algorithm.
Given these tradeoffs between fixed and floating point, how do you choose
which to use? Here are some things to consider. First, look at how many bits
are used in the ADC and DAC. In many applications, 12-14 bits per sample
is the crossover for using fixed versus floating point. For instance, television
and other video signals typically use 8 bit ADC and DAC, and the precision of
fixed point is acceptable. In comparison, professional audio applications can
sample with as high as 20 or 24 bits, and almost certainly need floating point
to capture the large dynamic range.
The next thing to look at is the complexity of the algorithm that will be run.
If it is relatively simple, think fixed point; if it is more complicated, think
floating point. For example, FIR filtering and other operations in the time
domain only require a few dozen lines of code, making them suitable for fixed
point. In contrast, frequency domain algorithms, such as spectral analysis and
FFT convolution, are very detailed and can be much more difficult to program.
While they can be written in fixed point, the development time will be greatly
reduced if floating point is used.
Lastly, think about the money: how important is the cost of the product, and
how important is the cost of the development? When fixed point is chosen, the
cost of the product will be reduced, but the development cost will probably be
higher due to the more difficult algorithms. In the reverse manner, floating
point will generally result in a quicker and cheaper development cycle, but a
more expensive final product.
Figure 28-8 shows some of the major trends in DSPs. Figure (a) illustrates the
impact that Digital Signal Processors have had on the embedded market. These
are applications that use a microprocessor to directly operate and control some
larger system, such as a cellular telephone, microwave oven, or automotive
instrument display panel. The name "microcontroller" is often used in
referring to these devices, to distinguish them from the microprocessors used
in personal computers. As shown in (a), about 38% of embedded designers
have already started using DSPs, and another 49% are considering the switch.
The high throughput and computational power of DSPs often makes them an
ideal choice for embedded designs.
As illustrated in (b), about twice as many engineers currently use fixed
point as use floating point DSPs. However, this depends greatly on the
application. Fixed point is more popular in competitive consumer products
where the cost of the electronics must be kept very low. A good example
of this is cellular telephones. When you are in competition to sell millions
of your product, a cost difference of only a few dollars can be the difference
between success and failure. In comparison, floating point is more common
when greater performance is needed and cost is not important. For
Chapter 28- Digital Signal Processors 519
No Plans
Floating Point
Next Year
in 2000
Next
Fixed Point
Migrate
Migrate
Migrate
Design
b. DSP currently used
c. Migration to floating point
Considering
Changed
Considering
Have Already
Not
a. Changing from uProc to DSP
FIGURE 28-8
Major trends in DSPs. As illustrated in (a), about 38% of embedded designers have already switched from
conventional microprocessors to DSPs, and another 49% are considering the change. In (b), about twice as
many engineers use fixed point as use floating point DSPs. This is mainly driven by consumer products that
must have low cost electronics, such as cellular telephones. However, as shown in (c), floating point is the
fastest growing segment; over one-half of engineers currently using 16 bit devices plan to migrate to floating
point DSPs
instance, suppose you are designing a medical imaging system, such a
computed tomography scanner. Only a few hundred of the model will ever
be sold, at a price of several hundred-thousand dollars each. For this
application, the cost of the DSP is insignificant, but the performance is
critical. In spite of the larger number of fixed point DSPs being used, the
floating point market is the fastest growing segment. As shown in (c), over
one-half of engineers using 16-bits devices plan to migrate to floating point
at some time in the near future.
Before leaving this topic, we should reemphasize that floating point and fixed
point usually use 32 bits and 16 bits, respectively, but not always. For
520 The Scientist and Engineer's Guide to Digital Signal Processing
instance, the SHARC family can represent numbers in 32-bit fixed point, a
mode that is common in digital audio applications. This makes the 232
quantization levels spaced uniformly over a relatively small range, say,
between -1 and 1. In comparison, floating point notation places the 232
quantization levels logarithmically over a huge range, typically ±3.4×1038.
This gives 32-bit fixed point better precision, that is, the quantization error on
any one sample will be lower. However, 32-bit floating point has a higher
dynamic range, meaning there is a greater difference between the largest
number and the smallest number that can be represented.
C versus Assembly
DSPs are programmed in the same languages as other scientific and engineering
applications, usually assembly or C. Programs written in assembly can execute
faster, while programs written in C are easier to develop and maintain. In
traditional applications, such as programs run on personal computers and
mainframes, C is almost always the first choice. If assembly is used at all, it
is restricted to short subroutines that must run with the utmost speed. This is
shown graphically in Fig. 28-9a; for every traditional programmer that works
in assembly, there are approximately ten that use C.
However, DSP programs are different from traditional software tasks in two
important respects. First, the programs are usually much shorter, say, onehundred
lines versus ten-thousand lines. Second, the execution speed is
often a critical part of the application. After all, that's why someone uses
a DSP in the first place, for its blinding speed. These two factors motivate
many software engineers to switch from C to assembly for programming
Digital Signal Processors. This is illustrated in (b); nearly as many DSP
programmers use assembly as use C.
Figure (c) takes this further by looking at the revenue produced by DSP
products. For every dollar made with a DSP programmed in C, two dollars are
made with a DSP programmed in assembly. The reason for this is simple;
money is made by outperforming the competition. From a pure performance
standpoint, such as execution speed and manufacturing cost, assembly almost
always has the advantage over C. For instance, C code usually requires a
larger memory than assembly, resulting in more expensive hardware. However,
the DSP market is continually changing. As the market grows, manufacturers
will respond by designing DSPs that are optimized for programming in C. For
instance, C is much more efficient when there is a large, general purpose
register set and a unified memory space. These future improvements will
minimize the difference in execution time between C and assembly, and allow
C to be used in more applications.
To better understand this decision between C and assembly, let's look at
a typical DSP task programmed in each language. The example we will
use is the calculation of the dot product of the two arrays, x [ ] and y [ ].
This is a simple mathematical operation, we multiply each coefficient in one
Chapter 28- Digital Signal Processors 521
Assembly
C
b. DSP Programmers
Assembly
C
a. Traditional Programmers
Assembly
C
FIGURE 28-9 c. DSP Revenue
Programming in C versus assembly. As
shown in (a), only about 10% of traditional
programmers (such as those that work on
personal computers and mainframes) use
assembly. However, as illustrated in (b),
assembly is much more common in Digital
Signal Processors. This is because DSP
programs must operate as fast as possible,
and are usually quite short. Figure (c) shows
that assembly is even more common in
products that generate a high revenue.
TABLE 28-2
Dot product in C. This progam calculates
the dot product of two arrays, x[ ] and y[ ],
and stores the result in the variable, result.
001 #define LEN 20
002 float dm x[LEN];
003 float pm y[LEN];
004 float result;
005
006 main()
007
008 {
009 int n;
010 float s;
011 for (n=0;n pi/2 x = pi -x }
ay0=ax0; { store sign of result in ay0}
sin_approx:
I5=^sin_coeff; {Pointer to coeff. buffer}
my1=ar; {Coeffs in 4.12 format}
mf=ar*my1 (rnd), mx1=pm(i5,m5); {mf = x**2}
mr=mx1*my1 (ss), mx1=pm(i5,m5); {mr = c1*x}
cntr=3;
do approx1 until ce;
mr=mr+mx1*mf (SS); {Do summation }
approx1: mf=ar*mf (RND), mx1=PM(I5,M5);
mr=mr+mx1*mf (SS);
sr=ASHIFT mr1 by 3 (HI);
sr=sr or LSHIFT mr0 by 3 (LO); {Convert to 1.15 format}
ar=pass sr1;
if LT ar=pass ay1; {Saturate if needed}
af=pass ay0;
if LT ar=-ar; {Negate output if needed}
rts;
Atan_:
I5 = ^ATN_COEFF; {point to coefficients}
ay0=0;
ax1=mr1;
ar=pass mr1;
if GE jump posi; {Check for positive input}
ar=-mr0; {Make negative number positive}
a Basic trigonometric subroutines for the ADMC300 AN300-10
© Analog Devices Inc., January 2000 Page 6 of 11
mr0=ar;
ar=ay0-mr1+c-1;
mr1=ar;
posi: sr=LSHIFT mr0 by -1 (LO); {Produce 1.15 value in SR0}
ar=sr0;
ay1=mr1;
af=pass mr1;
if EQ jump noinv; {If input < 1, no need to invert}
se=exp mr1 (HI); {Invert input}
sr=norm mr1 (HI);
sr=sr or NORM mr0 (LO);
ax0=sr1;
si=0x0001;
sr=NORM si (HI);
ay1=sr1;
ay0=sr0;
divs ay1,ax0;
divq ax0; divq ax0; divq ax0;
divq ax0; divq ax0; divq ax0;
divq ax0; divq ax0; divq ax0;
divq ax0; divq ax0; divq ax0;
divq ax0; divq ax0; divq ax0;
ar=ay0;
noinv: my0=ar;
mf=ar*my0 (RND), my1=PM(I5,M5);
mr=ar*my1 (SS), mx1=PM(I5,M5);
cntr=3;
do approx2 until CE;
mr=mr+mx1*mf (SS), mx1=PM(I5,M5);
approx2: mf=ar*mf (RND);
mr=mr+mx1*mf (SS);
ar=mr1;
ay0=0x4000;
af=pass ay1;
if NE ar=ay0-mr1;
af=pass ax1;
if LT ar=-ar;
rts;
1.6 Access to the library: the header file
The library may be accessed by including the header file “trigono.h” in the application code.
The header file is intended to provide function-like calls to the routines presented in the previous section. It
defines the calls shown in Error! Reference source not found.. The file is self-explaining and needs no
further comments.
It is worth adding a few comments about efficiency of these routines. The first macro simply sets the DAG
registers M5 and L5 to its correct values. The user may however just replace the macro with one of its
instructions when the application code modifies just one of these registers. The sine and cosine subroutines
expect the argument to be placed into ax0. This is what the macros do. However, if the angle is already
stored in ax0, the user may just place an instruction call Sin_; instead of Sin(ax0) in order to avoid an
additional instruction ax0 = ax0; in the expanded code. Similarly, a instruction Atan(mr1, mr0) should be
avoided or replaced by the direct call to the subroutine Atan_.
.MACRO Set_DAG_registers_for_trigonometric;
M5 = 1;
L5 = 0;
.ENDMACRO;
.MACRO Sin(%0);
ax0 = %0;
call Sin_;
.ENDMACRO;
.MACRO Cos(%0);
ax0 = %0;
a Basic trigonometric subroutines for the ADMC300 AN300-10
© Analog Devices Inc., January 2000 Page 7 of 11
call Cos_;
.ENDMACRO;
.MACRO Atan(%0, %1);
mr1= %0;
mr0= %1;
call Atan_;
.ENDMACRO;
2 Software Example: Testing the Trigonometric Functions
2.1 The main program: main.dsp
The example demonstrates how to use the routines. All it does is to cycle through the whole range of
definition of the sine function and converting the results by means of the digital to analog converter. The
application has been adapted from two previous notes6,7. This section will only explain the few and
intuitive modifications to those applications.
The file “main.dsp” contains the initialisation and PWM Sync and Trip interrupt service routines. To
activate, build the executable file using the attached build.bat either within your DOS prompt or clicking
on it from Windows Explorer. This will create the object files and the main.exe example file. This file
may be run on the Motion Control Debugger.
In the following, a brief description of the additional code (put in evidence by bold characters) is given.
Start of code – declaring start location in program memory
.MODULE/RAM/SEG=USER_PM1/ABS=0x60 Main_Program;
Next, the general systems constants and PWM configuration constants (main.h – see the next section) are
included. Also included are the PWM library, the DAC interface library and the trigonometric library.
{***************************************************************************************
* Include General System Parameters and Libraries *
***************************************************************************************}
#include ;
#include ;
#include ;
#include ;
The argument variable Theta is defined hereafter.
{***************************************************************************************
* Local Variables Defined in this Module *
***************************************************************************************}
.VAR/DM/RAM/SEG=USER_DM Theta; { Current angle }
.INIT Theta : 0x0000;
First, the PWM block is set up to generate interrupts every 100μs (see “main.h” in the next Section). The
variable Theta, which stores the argument of the trigonometric functions, is set to zero. Before using the
trigonometric functions, it is necessary to initialise certain registers of the data-address-generator (DAG) of
the DSP core. This will be discussed in more detail in the next section. However, note that this is done only
once in this example. If those registers are modified in other parts of the user’s code, then it must be repeated
before a call to a trigonometric function.
The main loop just waits for interrupts..
6 AN300-03: Three-Phase Sine-Wave Generation using the PWM Unit of the ADMC300
7 AN300-06: Using the Serial Digital to Analog Converter of the ADMC Connector Board
a Basic trigonometric subroutines for the ADMC300 AN300-10
© Analog Devices Inc., January 2000 Page 8 of 11
{********************************************************************************************}
{ Start of program code }
{********************************************************************************************}
Startup:
PWM_Init(PWMSYNC_ISR, PWMTRIP_ISR);
DAC_Init;
IFC = 0x80; { Clear any pending IRQ2 inter. }
ay0 = 0x200; { unmask irq2 interrupts. }
ar = IMASK;
ar = ar or ay0;
IMASK = ar; { IRQ2 ints fully enabled here }
ar = pass 0;
DM(Theta)= ar;
Set_DAG_registers_for_trigonometric;
Main: { Wait for interrupt to occur }
jump Main;
rts;
The interrupt service routine simply shows how to make use of the trigonometric routines. It invokes the three
routines (the integer part of the Atan_ function is set to zero – it is intended to illustrate the possibility of
constant arguments). The result of Sin, Cos and Atan (in register ar) are stored in channels 1, 2 and 3
respectively and send to the DAC (refer to the above mentioned application note AN300-6 for details). Then
Theta is incremented, so that the whole range of definition of the sine functions is swept. Refer to Section 1.2
for the used formats of inputs and outputs. After 65536 interrupts (corresponding to approx. 6.55s) the whole
period is completed. Since only the fractional part of the arctan argument is used, this function will generate
the output from 0 to π/4 (hexadecimal 0x2000).
{********************************************************************************************}
{ PWM Interrupt Service Routine }
{********************************************************************************************}
PWMSYNC_ISR:
ax0 = dm(Theta);
Sin(ax0);
DAC_Put(1, ar);
Cos(ax0);
DAC_Put(2, ar);
Atan(0, ax0);
DAC_Put(3, ar);
DAC_Update;
ax1= DM(Theta);
ar= ax1 +1;
DM(Theta)= ar;
rti;
2.2 The main include file: main.h
This file contains the definitions of ADMC300 constants, general purpose macros and the configuration
parameters of the system and library routines. It should be included in every application. For more
information refer to the Library Documentation File.
This file is mostly self-explaining. As already mentioned, the trigonometric library does not require any
configuration parameters. The following defines the parameters for the PWM ISR used in this example.
{********************************************************************************************}
{ Library: PWM block }
{ file : PWM300.dsp }
{ Application Note: Usage of the ADMC300 Pulse Width Modulation Block }
.CONST PWM_freq = 10000; {Desired PWM switching frequency [Hz] }
.CONST PWM_deadtime = 1000; {Desired deadtime [nsec] }
.CONST PWM_minpulse = 1000; {Desired minimal pulse time [nsec] }
.CONST PWM_syncpulse = 1540; {Desired sync pulse time [nsec] }
{********************************************************************************************}
a Basic trigonometric subroutines for the ADMC300 AN300-10
© Analog Devices Inc., January 2000 Page 9 of 11
2.3 Example output
The signals that are generated by this demonstration program is shown in the following figure. Note that
the use of only the fractional part for the arctan function limits it’s output to the range of 0 to 0.25
(corresponding to ¼π = arctan(1)). Refer to section 1.2 for details on the format of inputs and outputs.
Figure 1 Produced output of the example program.
The waveforms represent the signals on the DAC outputs 1 (sine), 2 (cosine) and 3 (arctangent).
3 Precision of the routines
3.1 Sine and Cosine functions
The following figure plots the obtained error of the implemented sine function (16 bit fixed point
arithmetic) versus the result of floating point calculations. The graph is limited to the 1st quadrant for the
usual symmetry properties and may obviously be extended to the cosine function as well. Its maximum is
found to be of approx. 0.016%, resulting in a precision of 12.7 bits for the sine and cosine functions.
a Basic trigonometric subroutines for the ADMC300 AN300-10
© Analog Devices Inc., January 2000 Page 10 of 11
Figure 2 Error of sine function in the 1st quadrant (0 to ½π). The x-axis is scaled to 1.15 format.
3.2 Arctangent function
The following figures plot the obtained error of the implemented arctangent function (16 bit fixed point
arithmetic) versus the result of floating point calculations. The analysis has been split into the two cases
of the argument laying in the range of 0 to 1 (increments of 2-14 - Figure 3) and in the range from 1 to
2048 (steps of 0.5 - Figure 4). The maximum error is found to be of approx. 0.0059%, resulting in a
precision of 14 bits for the arctangent function. The result may obviously be extended to negative values
for the usual symmetry properties.
Figure 3 Error of arctangent function in the range of 0 to 1. The y-axis is scaled to 1.15 format.
a Basic trigonometric subroutines for the ADMC300 AN300-10
© Analog Devices Inc., January 2000 Page 11 of 11
Figure 4 Error of arctangent function in the range of 1 to 2048. The y-axis is scaled to 1.15 format.
4 Differences between library and ADMC300 “ROM-Utilities”
The main purpose of this application note is to document, to analyse and to standardise the trigonometric
functions on this part. The routines presented herein do not differ from the ones present in the ROM of the
ADMC300, except for the atan_ routine, which now uses I5, M5 and L5 instead of I4, M4 and L4. This
choice has been made in order to use the same pointers for all of the trigonometric functions. However,
the ones present in the ROM may still be used.
Introduction to Digital Filters
Digital filters are used for two general purposes: (1) separation of signals that have been
combined, and (2) restoration of signals that have been distorted in some way. Analog
(electronic) filters can be used for these same tasks; however, digital filters can achieve far
superior results. The most popular digital filters are described and compared in the next seven
chapters. This introductory chapter describes the parameters you want to look for when learning
about each of these filters.
Filter Basics
Digital filters are a very important part of DSP. In fact, their extraordinary
performance is one of the key reasons that DSP has become so popular. As
mentioned in the introduction, filters have two uses: signal separation and
signal restoration. Signal separation is needed when a signal has been
contaminated with interference, noise, or other signals. For example, imagine
a device for measuring the electrical activity of a baby's heart (EKG) while
still in the womb. The raw signal will likely be corrupted by the breathing and
heartbeat of the mother. A filter might be used to separate these signals so that
they can be individually analyzed.
Signal restoration is used when a signal has been distorted in some way. For
example, an audio recording made with poor equipment may be filtered to
better represent the sound as it actually occurred. Another example is the
deblurring of an image acquired with an improperly focused lens, or a shaky
camera.
These problems can be attacked with either analog or digital filters. Which
is better? Analog filters are cheap, fast, and have a large dynamic range in
both amplitude and frequency. Digital filters, in comparison, are vastly
superior in the level of performance that can be achieved. For example, a
low-pass digital filter presented in Chapter 16 has a gain of 1 +/- 0.0002 from
DC to 1000 hertz, and a gain of less than 0.0002 for frequencies above
262 The Scientist and Engineer's Guide to Digital Signal Processing
1001 hertz. The entire transition occurs within only 1 hertz. Don't expect
this from an op amp circuit! Digital filters can achieve thousands of times
better performance than analog filters. This makes a dramatic difference in
how filtering problems are approached. With analog filters, the emphasis
is on handling limitations of the electronics, such as the accuracy and
stability of the resistors and capacitors. In comparison, digital filters are
so good that the performance of the filter is frequently ignored. The
emphasis shifts to the limitations of the signals, and the theoretical issues
regarding their processing.
It is common in DSP to say that a filter's input and output signals are in the
time domain. This is because signals are usually created by sampling at
regular intervals of time. But this is not the only way sampling can take place.
The second most common way of sampling is at equal intervals in space. For
example, imagine taking simultaneous readings from an array of strain sensors
mounted at one centimeter increments along the length of an aircraft wing.
Many other domains are possible; however, time and space are by far the most
common. When you see the term time domain in DSP, remember that it may
actually refer to samples taken over time, or it may be a general reference to
any domain that the samples are taken in.
As shown in Fig. 14-1, every linear filter has an impulse response, a step
response and a frequency response. Each of these responses contains
complete information about the filter, but in a different form. If one of the
three is specified, the other two are fixed and can be directly calculated. All
three of these representations are important, because they describe how the
filter will react under different circumstances.
The most straightforward way to implement a digital filter is by convolving the
input signal with the digital filter's impulse response. All possible linear filters
can be made in this manner. (This should be obvious. If it isn't, you probably
don't have the background to understand this section on filter design. Try
reviewing the previous section on DSP fundamentals). When the impulse
response is used in this way, filter designers give it a special name: the filter
kernel.
There is also another way to make digital filters, called recursion. When
a filter is implemented by convolution, each sample in the output is
calculated by weighting the samples in the input, and adding them together.
Recursive filters are an extension of this, using previously calculated values
from the output, besides points from the input. Instead of using a filter
kernel, recursive filters are defined by a set of recursion coefficients. This
method will be discussed in detail in Chapter 19. For now, the important
point is that all linear filters have an impulse response, even if you don't
use it to implement the filter. To find the impulse response of a recursive
filter, simply feed in an impulse, and see what comes out. The impulse
responses of recursive filters are composed of sinusoids that exponentially
decay in amplitude. In principle, this makes their impulse responses
infinitely long. However, the amplitude eventually drops below the round-off
noise of the system, and the remaining samples can be ignored. Because
Chapter 14- Introduction to Digital Filters 263
Frequency
0 0.1 0.2 0.3 0.4 0.5
-0.5
0.0
0.5
1.0
1.5
c. Frequency response
Sample number
0 32 64 96 128
-0.1
0.0
0.1
0.2
127
a. Impulse response
0.3
Sample number
0 32 64 96 128
-0.5
0.0
0.5
1.0
1.5
127
b. Step response
Frequency
0 0.1 0.2 0.3 0.4 0.5
-60
-40
-20
0
20
40
d. Frequency response (in dB)
FIGURE 14-1
Filter parameters. Every linear filter has an impulse response, a step response, and a frequency response. The
step response, (b), can be found by discrete integration of the impulse response, (a). The frequency response
can be found from the impulse response by using the Fast Fourier Transform (FFT), and can be displayed either
on a linear scale, (c), or in decibels, (d).
FFT
Integrate 20 Log( )
Amplitude
Amplitude (dB) Amplitude
Amplitude
of this characteristic, recursive filters are also called Infinite Impulse
Response or IIR filters. In comparison, filters carried out by convolution are
called Finite Impulse Response or FIR filters.
As you know, the impulse response is the output of a system when the input is
an impulse. In this same manner, the step response is the output when the
input is a step (also called an edge, and an edge response). Since the step is
the integral of the impulse, the step response is the integral of the impulse
response. This provides two ways to find the step response: (1) feed a step
waveform into the filter and see what comes out, or (2) integrate the impulse
response. (To be mathematically correct: integration is used with continuous
signals, while discrete integration, i.e., a running sum, is used with discrete
signals). The frequency response can be found by taking the DFT (using the
FFT algorithm) of the impulse response. This will be reviewed later in this
264 The Scientist and Engineer's Guide to Digital Signal Processing
dB ’ 10 log10
P2
P1
dB ’ 20 log10
A2
A1
EQUATION 14-1
Definition of decibels. Decibels are a
way of expressing a ratio between two
signals. Ratios of power (P1 & P2) use a
different equation from ratios of
amplitude (A1 & A2).
chapter. The frequency response can be plotted on a linear vertical axis, such
as in (c), or on a logarithmic scale (decibels), as shown in (d). The linear
scale is best at showing the passband ripple and roll-off, while the decibel scale
is needed to show the stopband attenuation.
Don't remember decibels? Here is a quick review. A bel (in honor of
Alexander Graham Bell) means that the power is changed by a factor of ten.
For example, an electronic circuit that has 3 bels of amplification produces an
output signal with 10×10×10 ’ 1000 times the power of the input. A decibel
(dB) is one-tenth of a bel. Therefore, the decibel values of: -20dB, -10dB,
0dB, 10dB & 20dB, mean the power ratios: 0.01, 0.1, 1, 10, & 100,
respectively. In other words, every ten decibels mean that the power has
changed by a factor of ten.
Here's the catch: you usually want to work with a signal's amplitude, not
its power. For example, imagine an amplifier with 20dB of gain. By
definition, this means that the power in the signal has increased by a factor
of 100. Since amplitude is proportional to the square-root of power, the
amplitude of the output is 10 times the amplitude of the input. While 20dB
means a factor of 100 in power, it only means a factor of 10 in amplitude.
Every twenty decibels mean that the amplitude has changed by a factor of
ten. In equation form:
The above equations use the base 10 logarithm; however, many computer
languages only provide a function for the base e logarithm (the natural log,
written log or ). The natural log can be use by modifying the above e x ln x
equations: dB ’ 4.342945 log and . e (P2 /P1) dB ’ 8.685890 loge (A2 /A1)
Since decibels are a way of expressing the ratio between two signals, they are
ideal for describing the gain of a system, i.e., the ratio between the output and
the input signal. However, engineers also use decibels to specify the amplitude
(or power) of a single signal, by referencing it to some standard. For example,
the term: dBV means that the signal is being referenced to a 1 volt rms signal.
Likewise, dBm indicates a reference signal producing 1 mW into a 600 ohms
load (about 0.78 volts rms).
If you understand nothing else about decibels, remember two things: First,
-3dB means that the amplitude is reduced to 0.707 (and the power is
Chapter 14- Introduction to Digital Filters 265
60dB = 1000
40dB = 100
20dB = 10
0dB = 1
-20dB = 0.1
-40dB = 0.01
-60dB = 0.001
therefore reduced to 0.5). Second, memorize the following conversions
between decibels and amplitude ratios:
How Information is Represented in Signals
The most important part of any DSP task is understanding how information is
contained in the signals you are working with. There are many ways that
information can be contained in a signal. This is especially true if the signal
is manmade. For instance, consider all of the modulation schemes that have
been devised: AM, FM, single-sideband, pulse-code modulation, pulse-width
modulation, etc. The list goes on and on. Fortunately, there are only two
ways that are common for information to be represented in naturally occurring
signals. We will call these: information represented in the time domain,
and information represented in the frequency domain.
Information represented in the time domain describes when something occurs
and what the amplitude of the occurrence is. For example, imagine an
experiment to study the light output from the sun. The light output is measured
and recorded once each second. Each sample in the signal indicates what is
happening at that instant, and the level of the event. If a solar flare occurs, the
signal directly provides information on the time it occurred, the duration, the
development over time, etc. Each sample contains information that is
interpretable without reference to any other sample. Even if you have only one
sample from this signal, you still know something about what you are
measuring. This is the simplest way for information to be contained in a
signal.
In contrast, information represented in the frequency domain is more
indirect. Many things in our universe show periodic motion. For example,
a wine glass struck with a fingernail will vibrate, producing a ringing
sound; the pendulum of a grandfather clock swings back and forth; stars
and planets rotate on their axis and revolve around each other, and so forth.
By measuring the frequency, phase, and amplitude of this periodic motion,
information can often be obtained about the system producing the motion.
Suppose we sample the sound produced by the ringing wine glass. The
fundamental frequency and harmonics of the periodic vibration relate to the
mass and elasticity of the material. A single sample, in itself, contains no
information about the periodic motion, and therefore no information about
the wine glass. The information is contained in the relationship between
many points in the signal.
266 The Scientist and Engineer's Guide to Digital Signal Processing
This brings us to the importance of the step and frequency responses. The step
response describes how information represented in the time domain is being
modified by the system. In contrast, the frequency response shows how
information represented in the frequency domain is being changed. This
distinction is absolutely critical in filter design because it is not possible to
optimize a filter for both applications. Good performance in the time domain
results in poor performance in the frequency domain, and vice versa. If you are
designing a filter to remove noise from an EKG signal (information represented
in the time domain), the step response is the important parameter, and the
frequency response is of little concern. If your task is to design a digital filter
for a hearing aid (with the information in the frequency domain), the frequency
response is all important, while the step response doesn't matter. Now let's
look at what makes a filter optimal for time domain or frequency domain
applications.
Time Domain Parameters
It may not be obvious why the step response is of such concern in time domain
filters. You may be wondering why the impulse response isn't the important
parameter. The answer lies in the way that the human mind understands and
processes information. Remember that the step, impulse and frequency
responses all contain identical information, just in different arrangements. The
step response is useful in time domain analysis because it matches the way
humans view the information contained in the signals.
For example, suppose you are given a signal of some unknown origin and
asked to analyze it. The first thing you will do is divide the signal into
regions of similar characteristics. You can't stop from doing this; your
mind will do it automatically. Some of the regions may be smooth; others
may have large amplitude peaks; others may be noisy. This segmentation
is accomplished by identifying the points that separate the regions. This is
where the step function comes in. The step function is the purest way of
representing a division between two dissimilar regions. It can mark when
an event starts, or when an event ends. It tells you that whatever is on the
left is somehow different from whatever is on the right. This is how the
human mind views time domain information: a group of step functions
dividing the information into regions of similar characteristics. The step
response, in turn, is important because it describes how the dividing lines
are being modified by the filter.
The step response parameters that are important in filter design are shown
in Fig. 14-2. To distinguish events in a signal, the duration of the step
response must be shorter than the spacing of the events. This dictates that
the step response should be as fast (the DSP jargon) as possible. This is
shown in Figs. (a) & (b). The most common way to specify the risetime
(more jargon) is to quote the number of samples between the 10% and 90%
amplitude levels. Why isn't a very fast risetime always possible? There are
many reasons, noise reduction, inherent limitations of the data acquisition
system, avoiding aliasing, etc.
Chapter 14- Introduction to Digital Filters 267
Sample number
0 16 32 48 64
-0.5
0.0
0.5
1.0
1.5
a. Slow step response
Sample number
0 16 32 48 64
-0.5
0.0
0.5
1.0
1.5
b. Fast step response
Sample number
0 16 32 48 64
-0.5
0.0
0.5
1.0
1.5
e. Nonlinear phase
Sample number
0 16 32 48 64
-0.5
0.0
0.5
1.0
1.5
f. Linear phase
FIGURE 14-2
Parameters for evaluating time domain performance. The step response is used to measure how well a filter
performs in the time domain. Three parameters are important: (1) transition speed (risetime), shown in (a) and
(b), (2) overshoot, shown in (c) and (d), and (3) phase linearity (symmetry between the top and bottom halves
of the step), shown in (e) and (f).
Sample number
0 16 32 48 64
-0.5
0.0
0.5
1.0
1.5
d. No overshoot
Sample number
0 16 32 48 64
-0.5
0.0
0.5
1.0
1.5
c. Overshoot
POOR GOOD
Amplitude
Amplitude
Amplitude Amplitude
Amplitude Amplitude
Figures (c) and (d) shows the next parameter that is important: overshoot in
the step response. Overshoot must generally be eliminated because it changes
the amplitude of samples in the signal; this is a basic distortion of
the information contained in the time domain. This can be summed up in
268 The Scientist and Engineer's Guide to Digital Signal Processing
Frequency
a. Low-pass
Frequency
c. Band-pass
Frequency
b. High-pass
Frequency
d. Band-reject
passband
stopband
transition
band
FIGURE 14-3
The four common frequency responses.
Frequency domain filters are generally
used to pass certain frequencies (the
passband), while blocking others (the
stopband). Four responses are the most
common: low-pass, high-pass, band-pass,
and band-reject.
Amplitude
Amplitude Amplitude
Amplitude
one question: Is the overshoot you observe in a signal coming from the thing
you are trying to measure, or from the filter you have used?
Finally, it is often desired that the upper half of the step response be
symmetrical with the lower half, as illustrated in (e) and (f). This symmetry
is needed to make the rising edges look the same as the falling edges. This
symmetry is called linear phase, because the frequency response has a phase
that is a straight line (discussed in Chapter 19). Make sure you understand
these three parameters; they are the key to evaluating time domain filters.
Frequency Domain Parameters
Figure 14-3 shows the four basic frequency responses. The purpose of
these filters is to allow some frequencies to pass unaltered, while
completely blocking other frequencies. The passband refers to those
frequencies that are passed, while the stopband contains those frequencies
that are blocked. The transition band is between. A fast roll-off means
that the transition band is very narrow. The division between the passband
and transition band is called the cutoff frequency. In analog filter design,
the cutoff frequency is usually defined to be where the amplitude is reduced
to 0.707 (i.e., -3dB). Digital filters are less standardized, and it is
common to see 99%, 90%, 70.7%, and 50% amplitude levels defined to be
the cutoff frequency.
Figure 14-4 shows three parameters that measure how well a filter performs
in the frequency domain. To separate closely spaced frequencies, the filter
must have a fast roll-off, as illustrated in (a) and (b). For the passband
frequencies to move through the filter unaltered, there must be no passband
ripple, as shown in (c) and (d). Lastly, to adequately block the stopband
frequencies, it is necessary to have good stopband attenuation, displayed
in (e) and (f).
Chapter 14- Introduction to Digital Filters 269
Frequency
0 0.1 0.2 0.3 0.4 0.5
-0.5
0.0
0.5
1.0
1.5
a. Slow roll-off
Frequency
0 0.1 0.2 0.3 0.4 0.5
-0.5
0.0
0.5
1.0
1.5
b. Fast roll-off
Frequency
0 0.1 0.2 0.3 0.4 0.5
-120
-100
-80
-60
-40
-20
0
20
40
e. Poor stopband attenuation
Frequency
0 0.1 0.2 0.3 0.4 0.5
-120
-100
-80
-60
-40
-20
0
20
40
f. Good stopband attenuation
FIGURE 14-4
Parameters for evaluating frequency domain performance. The frequency responses shown are for low-pass
filters. Three parameters are important: (1) roll-off sharpness, shown in (a) and (b), (2) passband ripple, shown
in (c) and (d), and (3) stopband attenuation, shown in (e) and (f).
Frequency
0 0.1 0.2 0.3 0.4 0.5
-0.5
0.0
0.5
1.0
1.5
d. Flat passband
Frequency
0 0.1 0.2 0.3 0.4 0.5
-0.5
0.0
0.5
1.0
1.5
c. Ripple in passband
POOR GOOD
Amplitude (dB)
Amplitude (dB)
Amplitude Amplitude
Amplitude Amplitude
Why is there nothing about the phase in these parameters? First, the phase
isn't important in most frequency domain applications. For example, the phase
of an audio signal is almost completely random, and contains little useful
information. Second, if the phase is important, it is very easy to make digital
270 The Scientist and Engineer's Guide to Digital Signal Processing
filters with a perfect phase response, i.e., all frequencies pass through the filter
with a zero phase shift (also discussed in Chapter 19). In comparison, analog
filters are ghastly in this respect.
Previous chapters have described how the DFT converts a system's impulse
response into its frequency response. Here is a brief review. The quickest
way to calculate the DFT is by means of the FFT algorithm presented in
Chapter 12. Starting with a filter kernel N samples long, the FFT calculates
the frequency spectrum consisting of an N point real part and an N point
imaginary part. Only samples 0 to N/2 of the FFT's real and imaginary parts
contain useful information; the remaining points are duplicates (negative
frequencies) and can be ignored. Since the real and imaginary parts are
difficult for humans to understand, they are usually converted into polar
notation as described in Chapter 8. This provides the magnitude and phase
signals, each running from sample 0 to sample N/2 (i.e., N/2%1 samples in
each signal). For example, an impulse response of 256 points will result in a
frequency response running from point 0 to 128. Sample 0 represents DC, i.e.,
zero frequency. Sample 128 represents one-half of the sampling rate.
Remember, no frequencies higher than one-half of the sampling rate can appear
in sampled data.
The number of samples used to represent the impulse response can be
arbitrarily large. For instance, suppose you want to find the frequency
response of a filter kernel that consists of 80 points. Since the FFT only works
with signals that are a power of two, you need to add 48 zeros to the signal to
bring it to a length of 128 samples. This padding with zeros does not change
the impulse response. To understand why this is so, think about what happens
to these added zeros when the input signal is convolved with the system's
impulse response. The added zeros simply vanish in the convolution, and do
not affect the outcome.
Taking this a step further, you could add many zeros to the impulse response
to make it, say, 256, 512, or 1024 points long. The important idea is that
longer impulse responses result in a closer spacing of the data points in the
frequency response. That is, there are more samples spread between DC and
one-half of the sampling rate. Taking this to the extreme, if the impulse
response is padded with an infinite number of zeros, the data points in the
frequency response are infinitesimally close together, i.e., a continuous line.
In other words, the frequency response of a filter is really a continuous signal
between DC and one-half of the sampling rate. The output of the DFT is a
sampling of this continuous line. What length of impulse response should you
use when calculating a filter's frequency response? As a first thought, try
N’1024 , but don't be afraid to change it if needed (such as insufficient
resolution or excessive computation time).
Keep in mind that the "good" and "bad" parameters discussed in this chapter
are only generalizations. Many signals don't fall neatly into categories. For
example, consider an EKG signal contaminated with 60 hertz interference.
The information is encoded in the time domain, but the interference is best
dealt with in the frequency domain. The best design for this application is
Chapter 14- Introduction to Digital Filters 271
Sample number
0 10 20 30 40 50
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
a. Original filter kernel
Frequency
0 0.1 0.2 0.3 0.4 0.5
0.0
0.5
1.0
1.5
b. Original frequency response
FIGURE 14-5
Example of spectral inversion. The low-pass filter kernel in (a) has the frequency response shown in (b). A
high-pass filter kernel, (c), is formed by changing the sign of each sample in (a), and adding one to the sample
at the center of symmetry. This action in the time domain inverts the frequency spectrum (i.e., flips it top-forbottom),
as shown by the high-pass frequency response in (d).
Frequency
0 0.1 0.2 0.3 0.4 0.5
0.0
0.5
1.0
1.5
d. Inverted frequency response
Flipped
top-for-bottom
Sample number
0 10 20 30 40 50
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
c. Filter kernel with spectral inversion
Time Domain Frequency Domain
Amplitude Amplitude
Amplitude Amplitude
bound to have trade-offs, and might go against the conventional wisdom of this
chapter. Remember the number one rule of education: A paragraph in a book
doesn't give you a license to stop thinking.
High-Pass, Band-Pass and Band-Reject Filters
High-pass, band-pass and band-reject filters are designed by starting with a
low-pass filter, and then converting it into the desired response. For this
reason, most discussions on filter design only give examples of low-pass
filters. There are two methods for the low-pass to high-pass conversion:
spectral inversion and spectral reversal. Both are equally useful.
An example of spectral inversion is shown in 14-5. Figure (a) shows a lowpass
filter kernel called a windowed-sinc (the topic of Chapter 16). This filter
kernel is 51 points in length, although many of samples have a value
so small that they appear to be zero in this graph. The corresponding
272 The Scientist and Engineer's Guide to Digital Signal Processing
x[n] y[n]
x[n] *[n] - h[n] y[n]
h[n]
*[n]
Low-pass
All-pass
b. High-pass High-pass
in a single stage
a. High-pass by
adding parallel stages
FIGURE 14-6
Block diagram of spectral inversion. In
(a), the input signal, x[n] , is applied to two
systems in parallel, having impulse
responses of h[n] and *[n] . As shown in
(b), the combined system has an impulse
response of *[n]& h[n] . This means that
the frequency response of the combined
system is the inversion of the frequency
response of h[n] .
frequency response is shown in (b), found by adding 13 zeros to the filter
kernel and taking a 64 point FFT. Two things must be done to change the
low-pass filter kernel into a high-pass filter kernel. First, change the sign of
each sample in the filter kernel. Second, add one to the sample at the center
of symmetry. This results in the high-pass filter kernel shown in (c), with the
frequency response shown in (d). Spectral inversion flips the frequency
response top-for-bottom, changing the passbands into stopbands, and the
stopbands into passbands. In other words, it changes a filter from low-pass to
high-pass, high-pass to low-pass, band-pass to band-reject, or band-reject to
band-pass.
Figure 14-6 shows why this two step modification to the time domain results
in an inverted frequency spectrum. In (a), the input signal, x[n] , is applied to
two systems in parallel. One of these systems is a low-pass filter, with an
impulse response given by h[n] . The other system does nothing to the signal,
and therefore has an impulse response that is a delta function, *[n] . The
overall output, y[n] , is equal to the output of the all-pass system minus the
output of the low-pass system. Since the low frequency components are
subtracted from the original signal, only the high frequency components appear
in the output. Thus, a high-pass filter is formed.
This could be performed as a two step operation in a computer program:
run the signal through a low-pass filter, and then subtract the filtered signal
from the original. However, the entire operation can be performed in a
signal stage by combining the two filter kernels. As described in Chapter
Chapter 14- Introduction to Digital Filters 273
Sample number
0 10 20 30 40 50
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
a. Original filter kernel
Frequency
0 0.1 0.2 0.3 0.4 0.5
0.0
0.5
1.0
1.5
b. Original frequency response
FIGURE 14-7
Example of spectral reversal. The low-pass filter kernel in (a) has the frequency response shown in (b). A
high-pass filter kernel, (c), is formed by changing the sign of every other sample in (a). This action in the time
domain results in the frequency domain being flipped left-for-right, resulting in the high-pass frequency
response shown in (d).
Frequency
0 0.1 0.2 0.3 0.4 0.5
0.0
0.5
1.0
1.5
d. Reversed frequency response
Flipped
left-for-right
Sample number
0 10 20 30 40 50
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
c. Filter kernel with spectral reversal
Time Domain Frequency Domain
Amplitude Amplitude
Amplitude Amplitude
7, parallel systems with added outputs can be combined into a single stage by
adding their impulse responses. As shown in (b), the filter kernel for the highpass
filter is given by: *[n] & h[n]. That is, change the sign of all the samples,
and then add one to the sample at the center of symmetry.
For this technique to work, the low-frequency components exiting the low-pass
filter must have the same phase as the low-frequency components exiting the
all-pass system. Otherwise a complete subtraction cannot take place. This
places two restrictions on the method: (1) the original filter kernel must have
left-right symmetry (i.e., a zero or linear phase), and (2) the impulse must be
added at the center of symmetry.
The second method for low-pass to high-pass conversion, spectral reversal, is
illustrated in Fig. 14-7. Just as before, the low-pass filter kernel in (a)
corresponds to the frequency response in (b). The high-pass filter kernel, (c),
is formed by changing the sign of every other sample in (a). As shown in
(d), this flips the frequency domain left-for-right: 0 becomes 0.5 and 0.5
274 The Scientist and Engineer's Guide to Digital Signal Processing
h1x[n] [n] h2[n] y[n]
h1[n] h2x[n] [n] y[n]
Band-pass
a. Band-pass by Low-pass High-pass
cascading stages
b. Band-pass
in a single stage
FIGURE 14-8
Designing a band-pass filter. As shown
in (a), a band-pass filter can be formed
by cascading a low-pass filter and a
high-pass filter. This can be reduced to
a single stage, shown in (b). The filter
kernel of the single stage is equal to the
convolution of the low-pass and highpass
filter kernels.
becomes 0. The cutoff frequency of the example low-pass filter is 0.15,
resulting in the cutoff frequency of the high-pass filter being 0.35.
Changing the sign of every other sample is equivalent to multiplying the filter
kernel by a sinusoid with a frequency of 0.5. As discussed in Chapter 10, this
has the effect of shifting the frequency domain by 0.5. Look at (b) and imagine
the negative frequencies between -0.5 and 0 that are of mirror image of the
frequencies between 0 and 0.5. The frequencies that appear in (d) are the
negative frequencies from (b) shifted by 0.5.
Lastly, Figs. 14-8 and 14-9 show how low-pass and high-pass filter kernels can
be combined to form band-pass and band-reject filters. In short, adding the
filter kernels produces a band-reject filter, while convolving the filter kernels
produces a band-pass filter. These are based on the way cascaded and
parallel systems are be combined, as discussed in Chapter 7. Multiple
combination of these techniques can also be used. For instance, a band-pass
filter can be designed by adding the two filter kernels to form a stop-pass
filter, and then use spectral inversion or spectral reversal as previously
described. All these techniques work very well with few surprises.
Filter Classification
Table 14-1 summarizes how digital filters are classified by their use and by
their implementation. The use of a digital filter can be broken into three
categories: time domain, frequency domain and custom. As previously
described, time domain filters are used when the information is encoded in the
shape of the signal's waveform. Time domain filtering is used for such
actions as: smoothing, DC removal, waveform shaping, etc. In contrast,
frequency domain filters are used when the information is contained in the
Chapter 14- Introduction to Digital Filters 275
x[n] y[n]
x[n] h1[n] + h2[n] y[n]
h1[n]
h2[n]
Low-pass
High-pass
b. Band-reject Band-reject
in a single stage
a. Band-reject by
adding parallel stages
FIGURE 14-9
Designing a band-reject filter. As shown
in (a), a band-reject filter is formed by
the parallel combination of a low-pass
filter and a high-pass filter with their
outputs added. Figure (b) shows this
reduced to a single stage, with the filter
kernel found by adding the low-pass
and high-pass filter kernels.
Recursion
Time Domain
Frequency Domain
Finite Impulse Response (FIR) Infinite Impulse Response (IIR)
Moving average (Ch. 15) Single pole (Ch. 19)
Windowed-sinc (Ch. 16) Chebyshev (Ch. 20)
Custom FIR custom (Ch. 17) Iterative design (Ch. 26)
(Deconvolution)
Convolution
FILTER IMPLEMENTED BY:
(smoothing, DC removal)
(separating frequencies)
FILTER USED FOR:
TABLE 14-1
Filter classification. Filters can be divided by their use, and how they are implemented.
amplitude, frequency, and phase of the component sinusoids. The goal of these
filters is to separate one band of frequencies from another. Custom filters are
used when a special action is required by the filter, something more elaborate
than the four basic responses (high-pass, low-pass, band-pass and band-reject).
For instance, Chapter 17 describes how custom filters can be used for
deconvolution, a way of counteracting an unwanted convolution.
276 The Scientist and Engineer's Guide to Digital Signal Processing
Digital filters can be implemented in two ways, by convolution (also called
finite impulse response or FIR) and by recursion (also called infinite impulse
response or IIR). Filters carried out by convolution can have far better
performance than filters using recursion, but execute much more slowly.
The next six chapters describe digital filters according to the classifications in
Table 14-1. First, we will look at filters carried out by convolution. The
moving average (Chapter 15) is used in the time domain, the windowed-sinc
(Chapter 16) is used in the frequency domain, and FIR custom (Chapter 17) is
used when something special is needed. To finish the discussion of FIR filters,
Chapter 18 presents a technique called FFT convolution. This is an algorithm
for increasing the speed of convolution, allowing FIR filters to execute faster.
Next, we look at recursive filters. The single pole recursive filter (Chapter 19)
is used in the time domain, while the Chebyshev (Chapter 20) is used in the
frequency domain. Recursive filters having a custom response are designed by
iterative techniques. For this reason, we will delay their discussion until
Chapter 26, where they will be presented with another type of iterative
procedure: the neural network.
As shown in Table 14-1, convolution and recursion are rival techniques; you
must use one or the other for a particular application. How do you choose?
Chapter 21 presents a head-to-head comparison of the two, in both the time and
frequency domains.
The Complex Fourier Transform
Although complex numbers are fundamentally disconnected from our reality, they can be used to
solve science and engineering problems in two ways. First, the parameters from a real world
problem can be substituted into a complex form, as presented in the last chapter. The second
method is much more elegant and powerful, a way of making the complex numbers
mathematically equivalent to the physical problem. This approach leads to the complex Fourier
transform, a more sophisticated version of the real Fourier transform discussed in Chapter 8.
The complex Fourier transform is important in itself, but also as a stepping stone to more
powerful complex techniques, such as the Laplace and z-transforms. These complex transforms
are the foundation of theoretical DSP.
The Real DFT
All four members of the Fourier transform family (DFT, DTFT, Fourier
Transform & Fourier Series) can be carried out with either real numbers or
complex numbers. Since DSP is mainly concerned with the DFT, we will use
it as an example. Before jumping into the complex math, let's review the real
DFT with a special emphasis on things that are awkward with the mathematics.
In Chapter 8 we defined the real version of the Discrete Fourier Transform
according to the equations:
In words, an N sample time domain signal, x [n] , is decomposed into a set
of N/2%1 cosine waves, and N/2%1 sine waves, with frequencies given by the
568 The Scientist and Engineer's Guide to Digital Signal Processing
index, k. The amplitudes of the cosine waves are contained in ReX[k ], while
the amplitudes of the sine waves are contained in Im X[k] . These equations
operate by correlating the respective cosine or sine wave with the time domain
signal. In spite of using the names: real part and imaginary part, there are no
complex numbers in these equations. There isn't a j anywhere in sight! We
have also included the normalization factor, 2/N in these equations.
Remember, this can be placed in front of either the synthesis or analysis
equation, or be handled as a separate step (as described by Eq. 8-3). These
equations should be very familiar from previous chapters. If they aren't, go
back and brush up on these concepts before continuing. If you don't understand
the real DFT, you will never be able to understand the complex DFT.
Even though the real DFT uses only real numbers, substitution allows the
frequency domain to be represented using complex numbers. As suggested by
the names of the arrays, ReX[k ] becomes the real part of the complex
frequency spectrum, and Im X[k] becomes the imaginary part. In other words,
we place a j with each value in the imaginary part, and add the result to the
real part. However, do not make the mistake of thinking that this is the
"complex DFT." This is nothing more than the real DFT with complex
substitution.
While the real DFT is adequate for many applications in science and
engineering, it is mathematically awkward in three respects. First, it can only
take advantage of complex numbers through the use of substitution. This
makes mathematicians uncomfortable; they want to say: "this equals that," not
simply: "this represents that." For instance, imagine we are given the
mathematical statement: A equals B. We immediately know countless
consequences: 5A’ 5B, 1%A ’ 1%B, A/ x ’ B/ x, etc. Now suppose we are
given the statement: A represents B. Without additional information, we know
absolutely nothing! When things are equal, we have access to four-thousand
years of mathematics. When things only represent each other, we must start
from scratch with new definitions. For example, when sinusoids are
represented by complex numbers, we allow addition and subtraction, but
prohibit multiplication and division.
The second thing handled poorly by the real Fourier transform is the negative
frequency portion of the spectrum. As you recall from Chapter 10, sine and
cosine waves can be described as having a positive frequency or a negative
frequency. Since the two views are identical, the real Fourier transform
ignores the negative frequencies. However, there are applications where the
negative frequencies are important. This occurs when negative frequency
components are forced to move into the positive frequency portion of the
spectrum. The ghosts take human form, so to speak. For instance, this is what
happens in aliasing, circular convolution, and amplitude modulation. Since the
real Fourier transform doesn't use negative frequencies, its ability to deal with
these situations is very limited.
Our third complaint is the special handing of ReX [0] and ReX [N/2], the
first and last points in the frequency spectrum. Suppose we start with an N
Chapter 31- The Complex Fourier Transform 569
EQUATION 31-2
Euler's relation. e jx ’ cos(x) % j sin (x)
EQUATION 31-3
Euler's relation for
sine & cosine.
sin (x) ’ e jx & e &jx
2j
cos (x) ’ e jx % e &jx
2
sin(Tt ) ’ 1
2
je j (&T)t & 1
2
je jTt
EQUATION 31-4
Sinusoids as complex numbers. Using
complex numbers, cosine and sine waves
can be written as the sum of a positive
and a negative frequency.
cos(Tt ) ’ 1
2
e j (&T)t % 1
2
e jTt
point signal, x [n]. Taking the DFT provides the frequency spectrum contained
in ReX [k] and ImX [k] , where k runs from 0 to N/2. However, these are not
the amplitudes needed to reconstruct the time domain waveform; samples
ReX [0] and ReX [N/2] must first be divided by two. (See Eq. 8-3 to refresh
your memory). This is easily carried out in computer programs, but
inconvenient to deal with in equations.
The complex Fourier transform is an elegant solution to these problems. It is
natural for complex numbers and negative frequencies to go hand-in-hand.
Let's see how it works.
Mathematical Equivalence
Our first step is to show how sine and cosine waves can be written in an
equation with complex numbers. The key to this is Euler's relation, presented
in the last chapter:
At first glance, this doesn't appear to be much help; one complex expression is
equal to another complex expression. Nevertheless, a little algebra can
rearrange the relation into two other forms:
This result is extremely important, we have developed a way of writing
equations between complex numbers and ordinary sinusoids. Although Eq. 31-
3 is the standard form of the identity, it will be more useful for this discussion
if we change a few terms around:
Each expression is the sum of two exponentials: one containing a positive
frequency (T), and the other containing a negative frequency (-T). In other
words, when sine and cosine waves are written as complex numbers, the
570 The Scientist and Engineer's Guide to Digital Signal Processing
EQUATION 31-5
The forward complex DFT. Both the
time domain, x [n], and the frequency
domain, X[k], are arrays of complex
numbers, with k and n running from 0
to N-1. This equation is in polar form,
the most common for DSP.
X[k] ’ 1
N
j N& 1
n’ 0
x [n] e &j 2B kn /N
X[k] ’ 1
N
j N& 1
n’ 0
x[n] cos (2Bkn/N) & j sin (2Bkn/N)
EQUATION 31-6
The forward complex DFT
(rectangular form).
negative portion of the frequency spectrum is automatically included. The
positive and negative frequencies are treated with an equal status; it requires
one-half of each to form a complete waveform.
The Complex DFT
The forward complex DFT, written in polar form, is given by:
Alternatively, Euler's relation can be used to rewrite the forward transform in
rectangular form:
To start, compare this equation of the complex Fourier transform with the
equation of the real Fourier transform, Eq. 31-1. At first glance, they appear
to be identical, with only small amount of algebra being required to turn Eq.
31-6 into Eq. 31-1. However, this is very misleading; the differences between
these two equations are very subtle and easy to overlook, but tremendously
important. Let's go through the differences in detail.
First, the real Fourier transform converts a real time domain signal, x [n], into
two real frequency domain signals, ReX[k ] & ImX[k ]. By using complex
substitution, the frequency domain can be represented by a single complex
array, X[k] . In the complex Fourier transform, both x [n] & X[k] are arrays
of complex numbers. A practical note: Even though the time domain is
complex, there is nothing that requires us to use the imaginary part. Suppose
we want to process a real signal, such as a series of voltage measurements
taken over time. This group of data becomes the real part of the time domain
signal, while the imaginary part is composed of zeros.
Second, the real Fourier transform only deals with positive frequencies.
That is, the frequency domain index, k, only runs from 0 to N/2. In
comparison, the complex Fourier transform includes both positive and
negative frequencies. This means k runs from 0 to N-1. The frequencies
between 0 and N/2 are positive, while the frequencies between N/2 and N-1
are negative. Remember, the frequency spectrum of a discrete signal is
periodic, making the negative frequencies between N/2 and N-1 the same as
Chapter 31- The Complex Fourier Transform 571
between -N/2 and 0. The samples at 0 and N/2 straddle the line between
positive and negative. If you need to refresh your memory on this, look
back at Chapters 10 and 12.
Third, in the real Fourier transform with substitution, a j was added to the sine
wave terms, allowing the frequency spectrum to be represented by complex
numbers. To convert back to ordinary sine and cosine waves, we can simply
drop the j. This is the sloppiness that comes when one thing only represents
another thing. In comparison, the complex DFT, Eq. 31-5, is a formal
mathematical equation with j being an integral part. In this view, we cannot
arbitrary add or remove a j any more than we can add or remove any other
variable in the equation.
Forth, the real Fourier transform has a scaling factor of two in front, while the
complex Fourier transform does not. Say we take the real DFT of a cosine
wave with an amplitude of one. The spectral value corresponding to the cosine
wave is also one. Now, let's repeat the process using the complex DFT. In
this case, the cosine wave corresponds to two spectral values, a positive and a
negative frequency. Both these frequencies have a value of ½. In other words,
a positive frequency with an amplitude of ½, combines with a negative
frequency with an amplitude of ½, producing a cosine wave with an amplitude
of one.
Fifth, the real Fourier transform requires special handling of two frequency
domain samples: ReX [0] & ReX [N/2], but the complex Fourier transform does
not. Suppose we start with a time domain signal, and take the DFT to find the
frequency domain signal. To reverse the process, we take the Inverse DFT of
the frequency domain signal, reconstructing the original time domain signal.
However, there is scaling required to make the reconstructed signal be identical
to the original signal. For the complex Fourier transform, a factor of 1/N must
be introduced somewhere along the way. This can be tacked-on to the forward
transform, the inverse transform, or kept as a separate step between the two.
For the real Fourier transform, an additional factor of two is required (2/N), as
described above. However, the real Fourier transform also requires an
additional scaling step: ReX [0] and ReX [N/2] must be divided by two
somewhere along the way. Put in other words, a scaling factor of 1/N is used
with these two samples, while 2/N is used for the remainder of the spectrum.
As previously stated, this awkward step is one of our complaints about the real
Fourier transform.
Why are the real and complex DFTs different in how these two points are
handled? To answer this, remember that a cosine (or sine) wave in the time
domain becomes split between a positive and a negative frequency in the
complex DFT's spectrum. However, there are two exceptions to this, the
spectral values at 0 and N/2. These correspond to zero frequency (DC) and
the Nyquist frequency (one-half the sampling rate). Since these points
straddle the positive and negative portions of the spectrum, they do not have
a matching point. Because they are not combined with another value, they
inherently have only one-half the contribution to the time domain as the
other frequencies.
572 The Scientist and Engineer's Guide to Digital Signal Processing
x[n] ’ j N& 1
k’ 0
X[k ]e j 2B kn /N
EQUATION 31-7
The inverse complex DFT. This is
matching equation to the forward
complex DFT in Eq. 31-5.
Im X[ ]
Re X[ ]
Frequency
-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
-1.0
-0.5
0.0
0.5
1.0
Frequency
-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
-1.0
-0.5
0.0
0.5
1.0
2 1
3
4
FIGURE 31-1
Complex frequency spectrum. These
curves correspond to an entirely real
time domain signal, because the real
part of the spectrum has an even
symmetry, and the imaginary part has
an odd symmetry. The two square
markers in the real part correspond to
a cosine wave with an amplitude of
one, and a frequency of 0.23. The
two round markers in the imaginary
part correspond to a sine wave with an
amplitude of one, and a frequency of
0.23.
Amplitude Amplitude
Figure 31-1 illustrates the complex DFT's frequency spectrum. This figure
assumes the time domain is entirely real, that is, its imaginary part is zero.
We will discuss the idea of imaginary time domain signals shortly. There
are two common ways of displaying a complex frequency spectrum. As
shown here, zero frequency can be placed in the center, with positive
frequencies to the right and negative frequencies to the left. This is the best
way to think about the complete spectrum, and is the only way that an
aperiodic spectrum can be displayed.
The problem is that the spectrum of a discrete signal is periodic (such as with
the DFT and the DTFT). This means that everything between -0.5 and 0.5
repeats itself an infinite number of times to the left and to the right. In this
case, the spectrum between 0 and 1.0 contains the same information as from -
0.5 to 0.5. When graphs are made, such as Fig. 31-1, the -0.5 to 0.5
convention is usually used. However, many equations and programs use the 0
to 1.0 form. For instance, in Eqs. 31-5 and 31-6 the frequency index, k, runs
from 0 to N-1 (coinciding with 0 to 1.0). However, we could write it to run
from -N/2 to N/2-1 (coinciding with -0.5 to 0.5), if we desired.
Using the spectrum in Fig. 31-1 as a guide, we can examine how the inverse
complex DFT reconstructs the time domain signal. The inverse complex DFT,
written in polar form, is given by:
Chapter 31- The Complex Fourier Transform 573
x[n] ’ j N& 1
k’ 0
ReX[k] cos(2Bkn/N ) % j sin (2Bkn/N)
EQUATION 31-8
The inverse complex DFT.
This is Eq. 31-7 rewritten to
show how each value in the
frequency spectrum affects
the time domain.
& j N& 1
k’ 0
ImX[k] sin (2Bkn/N) & j cos (2Bkn/N)
½ cos(2B0.23n) % ½ j sin (2B0.23n)
½ cos(2B(&0.23) n) % ½ j sin (2B(&0.23)n)
½ cos(2B0.23n) & ½ j sin (2B0.23n)
Using Euler's relation, this can be written in rectangular form as:
The compact form of Eq. 31-7 is how the inverse DFT is usually written,
although the expanded version in Eq. 31-9 can be easier to understand. In
words, each value in the real part of the frequency domain contributes a real
cosine wave and an imaginary sine wave to the time domain. Likewise, each
value in the imaginary part of the frequency domain contributes a real sine
wave and an imaginary cosine wave. The time domain is found by adding all
these real and imaginary sinusoids. The important concept is that each value
in the frequency domain produces both a real sinusoid and an imaginary
sinusoid in the time domain.
For example, imagine we want to reconstruct a unity amplitude cosine wave at
a frequency of 2Bk/N . This requires a positive frequency and a negative
frequency, both from the real part of the frequency spectrum. The two square
markers in Fig. 31-1 are an example of this, with the frequency set at:
k /N ’ 0.23 . The positive frequency at 0.23 (labeled 1 in Fig. 31-1) contributes
a cosine wave and an imaginary sine wave to the time domain:
Likewise, the negative frequency at -0.23 (labeled 2 in Fig. 31-1) also
contributes a cosine and an imaginary sine wave to the time domain:
The negative sign within the cosine and sine terms can be eliminated by the
relations: cos(&x) ’ cos(x) and sin(&x) ’ &sin(x) . This allows the negative
frequency's contribution to be rewritten:
574 The Scientist and Engineer's Guide to Digital Signal Processing
½ cos(2B0.23n) % ½ j sin (2B0.23n )
cos(2B0.23n)
contribution from positive frequency !
contribution from negative frequency !
resultant time domain signal !
½ cos(2B0.23n) & ½ j sin (2B0.23n )
contribution from positive frequency ! & ½ sin(2B0.23n) & ½ j cos (2B0.23n )
& sin (2B0.23n)
contribution from negative frequency !
resultant time domain signal !
& ½ sin (2B0.23n) % ½ j cos(2B0.23n )
Adding the contributions from the positive and the negative frequencies
reconstructs the time domain signal:
In this same way, we can synthesize a sine wave in the time domain. In this
case, we need a positive and negative frequency from the imaginary part of the
frequency spectrum. This is shown by the round markers in Fig. 31-1. From
Eq. 31-8, these spectral values contribute a sine wave and an imaginary cosine
wave to the time domain. The imaginary cosine waves cancel, while the real
sine waves add:
Notice that a negative sine wave is generated, even though the positive
frequency had a value that was positive. This sign inversion is an inherent part
of the mathematics of the complex DFT. As you recall, this same sign
inversion is commonly used in the real DFT. That is, a positive value in the
imaginary part of the frequency spectrum corresponds to a negative sine wave.
Most authors include this sign inversion in the definition of the real Fourier
transform to make it consistent with its complex counterpart. The point is, this
sign inversion must be used in the complex Fourier transform, but is merely an
option in the real Fourier transform.
The symmetry of the complex Fourier transform is very important. As
illustrated in Fig. 31-1, a real time domain signal corresponds to a frequency
spectrum with an even real part, and an odd imaginary part. In other words,
the negative and positive frequencies have the same sign in the real part (such
as points 1 and 2 in Fig. 31-1), but opposite signs in the imaginary part (points
3 and 4).
This brings up another topic: the imaginary part of the time domain. Until now
we have assumed that the time domain is completely real, that is, the imaginary
part is zero. However, the complex Fourier transform does not require this.
Chapter 31- The Complex Fourier Transform 575
What is the physical meaning of an imaginary time domain signal? Usually,
there is none. This is just something allowed by the complex mathematics,
without a correspondence to the world we live in. However, there are
applications where it can be used or manipulated for a mathematical
purpose.
An example of this is presented in Chapter 12. The imaginary part of the time
domain produces a frequency spectrum with an odd real part, and an even
imaginary part. This is just the opposite of the spectrum produced by the real
part of the time domain (Fig. 31-1). When the time domain contains both a real
part and an imaginary part, the frequency spectrum is the sum of the two
spectra, had they been calculated individually. Chapter 12 describes how this
can be used to make the FFT algorithm calculate the frequency spectra of two
real signals at once. One signal is placed in the real part of the time domain,
while the other is place in the imaginary part. After the FFT calculation, the
spectra of the two signals are separated by an even/odd decomposition.
The Family of Fourier Transforms
Just as the DFT has a real and complex version, so do the other members of the
Fourier transform family. This produces the zoo of equations shown in Table
31-1. Rather than studying these equations individually, try to understand them
as a well organized and symmetrical group. The following comments describe
the organization of the Fourier transform family. It is detailed, repetitive, and
boring. Nevertheless, this is the background needed to understand theoretical
DSP. Study it well.
1. Four Fourier Transforms
A time domain signal can be either continuous or discrete, and it can be either
periodic or aperiodic. This defines four types of Fourier transforms: the
Discrete Fourier Transform (discrete, periodic), the Discrete Time
Fourier Transform (discrete, aperiodic), the Fourier Series (continuous,
periodic), and the Fourier Transform (continuous, aperiodic). Don't try to
understand the reasoning behind these names, there isn't any.
If a signal is discrete in one domain, it will be periodic in the other. Likewise,
if a signal is continuous in one domain, will be aperiodic in the other.
Continuous signals are represented by parenthesis, ( ), while discrete signals
are represented by brackets, [ ]. There is no notation to indicate if a signal is
periodic or aperiodic.
2. Real versus Complex
Each of these four transforms has a complex version and a real version. The
complex versions have a complex time domain signal and a complex frequency
domain signal. The real versions have a real time domain signal and two real
frequency domain signals. Both positive and negative frequencies are used in
the complex cases, while only positive frequencies are used for the real
transforms. The complex transforms are usually written in an exponential
576 The Scientist and Engineer's Guide to Digital Signal Processing
form; however, Euler's relation can be used to change them into a cosine and
sine form if needed.
3. Analysis and Synthesis
Each transform has an analysis equation (also called the forward transform)
and a synthesis equation (also called the inverse transform). The analysis
equations describe how to calculate each value in the frequency domain based
on all of the values in the time domain. The synthesis equations describe how
to calculate each value in the time domain based on all of the values in the
frequency domain.
4. Time Domain Notation
Continuous time domain signals are called x (t ), while discrete time domain
signals are called x[n] . For the complex transforms, these signals are complex.
For the real transforms, these signals are real. All of the time domain signals
extend from minus infinity to positive infinity. However, if the time domain is
periodic, we are only concerned with a single cycle, because the rest is
redundant. The variables, T and N, denote the periods of continuous and
discrete signals in the time domain, respectively.
5. Frequency Domain Notation
Continuous frequency domain signals are called X(T) if dt hey are complex, an ReX(T)
& ImX(T) if they ared real. Discrete frequency domain signals are calle X[k]
if they are complex, and ReX [k ] & ImX [k ] if they are real. The complex
transforms have negative frequencies that extend from minus infinity to zero,
and positive frequencies that extend from zero to positive infinity. The real
transforms only use positive frequencies. If the frequency domain is periodic,
we are only concerned with a single cycle, because the rest is redundant. For
continuous frequency domains, the independent variable, T, makes one complete
period from -B to B. In the discrete case, we use the period where k runs from
0 to N-1
6. The Analysis Equations
The analysis equations operate by correlation, i.e., multiplying the time
domain signal by a sinusoid and integrating (continuous time domain) or
summing (discrete time domain) over the appropriate time domain section.
If the time domain signal is aperiodic, the appropriate section is from minus
infinity to positive infinity. If the time domain signal is periodic, the
appropriate section is over any one complete period. The equations shown
here are written with the integration (or summation) over the period: 0 to
T (or 0 to N-1). However, any other complete period would give identical
results, i.e., -T to 0, -T/2 to T/2, etc.
7. The Synthesis Equations
The synthesis equations describe how an individual value in the time domain
is calculated from all the points in the frequency domain. This is done by
multiplying the frequency domain by a sinusoid, and integrating (continuous
frequency domain) or summing (discrete frequency domain) over the
appropriate frequency domain section. If the frequency domain is complex and
aperiodic, the appropriate section is negative infinity to positive infinity. If the
Chapter 31- The Complex Fourier Transform 577
Using f instead of T by the relation: T’ 2Bf
Integrating over other periods, such as: -T to 0, -T/2 to T/2, or 0 to T
Moving all or part of the scaling factor to the synthesis equation
Replacing the period with the fundamental frequency, f0
’ 1/T
Using other variable names, for example, T can become S in the DTFT,
and Re X [k] & Im Xs [k] can become ak & bk in the Fourier Serie
frequency domain is complex and periodic, the appropriate section is over one
complete cycle, i.e., -B to B (continuous frequency domain), or 0 to N-1
(discrete frequency domain). If the frequency domain is real and aperiodic, the
appropriate section is zero to positive infinity, that is, only the positive
frequencies. Lastly, if the frequency domain is real and periodic, the
appropriate section is over the one-half cycle containing the positive
frequencies, either 0 to B (continuous frequency domain) or 0 to N/2 (discrete
frequency domain).
8. Scaling
To make the analysis and synthesis equations undo each other, a scaling factor
must be placed on one or the other equation. In Table 31-1, we have placed
the scaling factors with the analysis equations. In the complex case, these
scaling factors are: 1/N, 1/T, or 1/2B. Since the real transforms do not use
negative frequencies, the scaling factors are twice as large: 2/N, 2/T, or 1/B.
The real transforms also include a negative sign in the calculation of the
imaginary part of the frequency spectrum (an option used to make the real
transforms more consistent with the complex transforms). Lastly, the synthesis
equations for the real DFT and the real Fourier Series have special scaling
instructions involving Re X(0 ) and Re X [N/2] .
9. Variations
These equations may look different in other publications. Here are a few
variations to watch out for:
Why the Complex Fourier Transform is Used
It is painfully obvious from this chapter that the complex DFT is much more
complicated than the real DFT. Are the benefits of the complex DFT really
worth the effort to learn the intricate mathematics? The answer to this
question depends on who you are, and what you plan on using DSP for. A
basic premise of this book is that most practical DSP techniques can be
understood and used without resorting to complex transforms. If you are
learning DSP to assist in your non-DSP research or engineering, the
complex DFT is probably overkill.
Nevertheless, complex mathematics is the primary language of those that
specialize in DSP. If you do not understand this language, you cannot
communicate with professionals in the field. This includes the ability to
understand the DSP literature: books, papers, technical articles, etc. Why are
complex techniques so popular with the professional DSP crowd?
578 The Scientist and Engineer's Guide to Digital Signal Processing
Discrete Fourier Transform (DFT)
x[n] ’ j N&1
k’ 0
X[k] e j 2Bk n/N x[n] ’ j N/2
k’ 0
ReX[k] cos(2Bkn/N )
X[k] ’ 1
N
j N&1
n’ 0
x[n] e &j 2Bkn/N
ImX[k] ’
&2
N
j N&1
n’ 0
x[n] sin (2Bkn/N )
& ImX[k] sin (2Bkn/N )
ReX[k] ’ 2
N
j N&1
n’ 0
x[n] cos(2Bkn/N )
complex transform real transform
synthesis
analysis
synthesis
analysis
Time domain:
x[n] is complex, discrete and periodic
n runs over one period, from 0 to N-1
Frequency domain:
X[k] is complex, discrete and periodic
k runs over one period, from 0 to N-1
k = 0 to N/2 are positive frequencies
k = N/2 to N-1 are negative frequencies
Time domain:
x[n] is real, discrete and periodic
n runs over one period, from 0 to N-1
Frequency domain:
Re X[k] is real, discrete and periodic
Im X[k] is real, discrete and periodic
k runs over one-half period, from 0 to N/2
Note: Before using the synthesis equation, the values
for Re X[0] and Re X[N/2] must be divided by two.
Discrete Time Fourier Transform (DTFT)
x[n] ’ m
2B
0
X(T) e jTn dT x[n] ’ m
B
0
ReX(T) cos(Tn)
X(T) ’ 1
2B j%4
n ’&4
x[n] e &jTn
ImX(T) ’
&1
B j%4
n’&4
x[n] sin (Tn)
& ImX (T) sin(Tn)dT
ReX(T) ’ 1
B j%4
n’&4
x[n]cos(Tn)
complex transform real transform
synthesis
analysis
synthesis
analysis
Time domain:
x[n] is complex, discrete and aperiodic
n runs from negative to positive infinity
Frequency domain:
X(T) is complex, continuous, and periodic
T runs over a single period, from 0 to 2B
T = 0 to B are positive frequencies
T = B to 2B are negative frequencies
Time domain:
x[n] is real, discrete and aperiodic
n runs from negative to positive infinity
Frequency domain:
Re X(T) is real, continuous and periodic
Im X(T) is real, continuous and periodic
T runs over one-half period, from 0 to B
TABLE 31-1 The Fourier Transforms
Chapter 31- The Complex Fourier Transform 579
Fourier Series
x(t ) ’ j%4
k’ &4
X[k] e j 2Bkt /T x(t ) ’ j%4
k’ 0
ReX[k] cos(2Bkt /T )
X[k] ’ 1
T mT
0
x(t ) e &j 2Bkt /T dt
& ImX[k] sin (2Bkt /T )
ReX[k] ’ 2
T mT
0
x(t ) cos(2Bkt /T ) dt
complex transform real transform
synthesis
analysis
synthesis
analysis
Time domain:
x(t) is complex, continuous and periodic
t runs over one period, from 0 to T
Frequency domain:
X[k] is complex, discrete, and aperiodic
k runs from negative to positive infinity
k > 0 are positive frequencies
k < 0 are negative frequencies
Time domain:
x(t) is real, continuous, and periodic
t runs over one period, from 0 to T
Frequency domain:
Re X[k] is real, discrete and aperiodic
Im X[k] is real, discrete and aperiodic
k runs from zero to positive infinity
Note: Before using the synthesis equation, the value for
Re X[0] must be divided by two.
ImX[k] ’
&2
T mT
0
x(t ) sin (2Bkt /T ) dt
Fourier Transform
x(t ) ’ m
%4
&4
X(T) e jTt dT x(t ) ’ m
%4
0
ReX(T) cos(Tt)
X(T) ’ 1
2B m
%4
&4
x(t ) e &jTt dt
& ImX(T) sin (Tt) dt
ReX(T) ’ 1
B m
%4
&4
x(t ) cos(Tt) dt
complex transform real transform
synthesis
analysis
synthesis
analysis
Time domain:
x(t) is complex, continious and aperiodic
t runs from negative to positive infinity
Frequency domain:
X(T) is complex, continious, and aperiodic
T runs from negative to positive infinity
T > 0 are positive frequencies
T < 0 are negative frequencies
Time domain:
x(t) is real, continuous, and aperiodic
t runs from negative to positive infinity
Frequency domain:
Re X[T] is real, continuous and aperiodic
Im X[T] is real, continuous and aperiodic
T runs from zero to positive infinity
TABLE 31-1 The Fourier Transforms
ImX(T) ’
&1
B m
%4
&4
x(t ) sin (Tt) dt
580 The Scientist and Engineer's Guide to Digital Signal Processing
There are several reasons we have already mentioned: compact equations,
symmetry between the analysis and synthesis equations, symmetry between the
time and frequency domains, inclusion of negative frequencies, a stepping stone
to the Laplace and z-transforms, etc.
There is also a more philosophical reason we have not discussed, something
called truth. We started this chapter by listing several ways that the real
Fourier transform is awkward. When the complex Fourier transform was
introduced, the problems vanished. Wonderful, we said, the complex Fourier
transform has solved the difficulties.
While this is true, it does not give the complex Fourier transform its proper
due. Look at this situation this way. In spite of its abstract nature, the complex
Fourier transform properly describes how physical systems behave. When we
restrict the mathematics to be real numbers, problems arise. In other words,
these problems are not solved by the complex Fourier transform, they are
introduced by the real Fourier transform. In the world of mathematics, the
complex Fourier transform is a greater truth than the real Fourier transform.
This holds great appeal to mathematicians and academicians, a group that
strives to expand human knowledge, rather than simply solving a particular
problem at hand.
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 1 of 16
a
Basic Mathematical
Subroutines for the ADMC300
AN300-09
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 2 of 16
Table of Contents
SUMMARY...................................................................................................................... 3
1 THE MATHEMATICAL LIBRARY ROUTINES ........................................................ 3
1.1 Using the Mathematical Routines .................................................................................................................3
1.2 Formats of inputs and outputs and usage of DSP core registers ................................................................4
1.3 Square Root.....................................................................................................................................................4
1.4 Logarithm........................................................................................................................................................6
1.4.1 Common Logarithm (Base 10) ................................................................................................................6
1.4.2 Natural Logarithm....................................................................................................................................6
1.5 Reciprocal........................................................................................................................................................8
2.2 Division........................................................................................................................................................8
1.6 Access to the library: the header file.............................................................................................................9
2 SOFTWARE EXAMPLE: TESTING THE MATHEMATICAL FUNCTIONS ........... 10
2.1 The main program: main.dsp......................................................................................................................10
2.2 The main include file: main.h ......................................................................................................................12
2.3 Example outputs ...........................................................................................................................................13
2.3.1 Square Root ...........................................................................................................................................13
2.3.2 Logarithm ..............................................................................................................................................14
2.3.3 Division..................................................................................................................................................15
2.3.4 Reciprocal ..............................................................................................................................................15
3 DIFFERENCES BETWEEN LIBRARY AND ADMC300 “ROM-UTILITIES” ......... 16
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 3 of 16
Summary
This application note illustrates the usage of some basic trigonometric subroutines such as sine and
cosine. They are implemented in a library-like module for easy access. The realisation follows the one
described in chapter 4 of the DSP applications handbook1. Then, a software example will be described
that may be downloaded from the accompanying zipped files. Finally, some data will be shown
concerning the accuracy of the algorithms.
1 The Mathematical Library Routines
1.1 Using the Mathematical Routines
The routines are developed as an easy-to-use library, which has to be linked to the user’s application. The
library consists of two files. The file “mathfun.dsp” contains the assembly code for the subroutines. This
package has to be compiled and can then be linked to an application. The user simply has to include the
header file “mathfun.h”, which provides function-like calls to the routines. The following table
summarises the set of macros that are defined in this library. Note that every function stores the result in
the sr1 register, except for the division routine which makes the results available in ar.
Operation Usage Operands
Initialisation Set_DAG_registers_for_math_function; none
Square Root Square_Root (integer_part, fractional_part);
integer_part = dreg2 or constant
fractional_part = dreg3 or constant
Logarithm Base 10 Log10(integer_part, fractional_part);
integer_part = dreg2 or constant
fractional_part = dreg3 or constant
Natural Logarithm LogN(integer_part, fractional_part);
integer_part = dreg2 or constant
fractional_part = dreg3 or constant
Reciprocal Inverse(integer_part, fractional_part);
integer_part = dreg2 or constant
fractional_part = dreg3 or constant
Signed Division Signed_Division(integer_part, fractional_part);
integer_part = dreg2 or constant
fractional_part = dreg3 or constant
Table 1: Implemented routines
The routines do not require any configuration constants from the main include-file “main.h” that comes
with every application note. For more information about the general structure of the application notes and
including libraries into user applications refer to the Library Documentation File. Section 2 shows an
example of usage of this library. In the following sections each routine is explained in detail with the
relevant segments of code which is found in either “mathfun.h” or “mathfun.dsp”. For more information
see the comments in those files.
1 a ”Digital Signal Applications using the ADSP-2100 Family”, Volume 1, Prentice Hall, 1992
2 Any data register of the ADSP-2171 core except mr0
3 Any data register of the ADSP-2171 core except mr1
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 4 of 16
1.2 Formats of inputs and outputs and usage of DSP core registers
The implementation of the macros listed in the previous section is based on the subroutines of Table 2.
Note that the first four accept input in the unsigned 16.16 format and that the output is in various single
precision format. The division routine expects a signed double precision value (for instance 1.31 or 8.24
…). Its output is in the ar register in a format that is determined by the input.
It may also be noted that the DAG registers M5 and L5 must be set to 1 and 0 respectively and that they
are not modified by the mathematical routines. The already mentioned call to
Set_DAG_registers_for_math_function prepares these registers for the functions. It now becomes clear
that this routine is necessary only once if M5 and/or L5 are not modified in another part of the user’s
code, as shown in the example in section 2.
Refer to the above-mentioned DSP applications handbook for more details on the routines described in
the previous sections.
Subroutine Input Output Modified Registers Other registers
(Must be set)
sqrt_(x) MR1, MR0 unsigned
16.16 Format
0 ≤ X <65536
SR1 in unsigned
8.8 format
AX0,AX1,AY0,AY1,AF,AR,
MY0, MY1,MX0,MF, MR,
SE, SR, I5
M5=1
L5=0
Log10_(x) MR1, MR0 unsigned
16.16 format
0 ≤ X <65536
SR1 in signed 4.12
format
AX0, AX1,AY0,AR,
MY1, MX0, MX1, MF, MR,
SE, SR, I5
M5=1
L5=0
Ln_(x) MR1, MR0 unsigned
16.16 format
0 ≤ X <65536
SR1 in signed
5.11 format
AX0, AX1,AY0,AR,
MY1, MX0, MX1, MF, MR,
SE, SR, I5
M5=1
L5=0
inv_(x) MR1, MR0 16.16
Format 1 ≤ x <32768
SR1 in signed 1.15
format
AX0,AY1, AY0,
MR1, MR0,
SR1, SR0
---
div_(x) Dividend NL.NR format
Divisor DL.DR format
AR in signed (NL
–DL+1).(NR-DR-
1) format
AX0, AX1, AR, AF, AY0, AY1
---
Table 2: Input and output format, modified registers for the mathematical routines
1.3 Square Root
The following equation approximates the square root of the input value x, where 0.5 ≤ x ≤1:
0.0560605 0.1037903
0.5* ( ) 0.7274475 0.672455 0.553406 0.2682495
5
2 3 4
+ +
= − + − +
x
sqrt x x x x x
( 1)
Text Box 1.2 shows the part of subroutine for getting square root when the original input falls into the
equation valid range between 0.5 and 1.0.
In the square root subroutine, the input is in 16.16 format, with unsigned integer in MR1 register and full
fraction in MR0 register. Therefore, the valid input range for the square root subroutine is between 0 and
65536 (0xFFFF.FFFF). If the input value is out of the range between 0.5 and 1.0, the square root
subroutine will scale the input in MR1 and MR0 registers by shift operation so that the scaled value will
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 5 of 16
fall into the valid equation range as input to equation ( 1) for computation. Obviously, the square root of
the scaled input obtained from equation ( 1) must be multiplied by the square root of the scaling value to
produce the square root of the original input as implemented in the following segment.
.VAR/PM/RAM/SEG=USER_PM1 sqrt_coeff[5];
.INIT sqrt_coeff : 0x5D1D00, 0xA9ED00, 0x46D600, 0xDDAA00, 0x072D00;
sqrt_: AX1=MR1; { store for knowing MSB }
AR = PASS MR1;
IF GE JUMP calculation; {MSB = 1 ?}
SR = LSHIFT MR1 BY -1 (HI); { left shift by 1 }
SR = SR OR LSHIFT MR0 BY -1 (LO);
MR1 = SR1; MR0 = SR0;
calculation: I5 = ^sqrt_coeff; {pointer to coeff. buffer}
SE=EXP MR1 (HI); {Check for redundant bits}
SE=EXP MR0 (LO);
AX0=SE, SR=Norm MR1 (HI);
SR=SR OR NORM MR0 (LO);
MY0=SR1, AR=PASS SR1;
IF EQ RTS;
MR=0;
MR1=base; {Load constant value}
MF=AR*MY0 (RND), MX0=PM(I5,M5); {MF =x*x}
MR=MR+MX0*MY0 (SS), MX0=PM(I5,M5); {MR = base + C1*x}
CNTR=4;
DO approx UNTIL CE;
MR=MR+MX0*MF (SS), MX0=PM(I5,M5);
approx: MF=AR*MF (RND);
AY0=15;
MY0=MR1, AR=AX0+AY0; {SE + 15 = 0?}
IF NE JUMP scale; {No, compute scaling value}
SR=ASHIFT MR1 BY -6 (HI);
Jump modification;
The next segment shows that the scaling value (1 2) 15 = ÷ + SE s is calculated where SE is the exponent
detector value of the original input. If (SE+15) is negative, it means that original input is less than 0.5
and the approximated result of the scaled input is to be multiplied by the scaling number of
15 (1 2) ÷ + SE . Otherwise, the original value is larger than 1.0 and the approximated square root of the
scaled input is multiplied with the reciprocal of the scaling number in order to get the result of the original
input. It should be realised that equation ( 1) is for calculation of 0.5*Square_Root(x) and it is one of the
factors under consideration when the subroutine Square_Root(x) shifts the result to get 8.8 format for the
output of the original input.
scale: MR=0;
MR1=sqrt2a; {Load 1/sqrt2(2)}
MY1=MR1, AR=ABS AR;
AY0=AR;
AR=AY0-1;
IF EQ JUMP pwr_ok;
CNTR=AR; {Compute S=(1/sqrt2(2))^(ABS(SE+15)) }
DO compute UNTIL CE;
compute: MR=MR1*MY1 (RND);
pwr_ok: IF NEG JUMP frac; {If (SE+15) is negative, ...}
AY1=0x0080; {Load a 1 in 9.23 format}
AY0=0; {calculate 1/S, if (SE+15) positive }
DIVS AY1, MR1;
DIVQ MR1; DIVQ MR1; DIVQ MR1;
DIVQ MR1; DIVQ MR1; DIVQ MR1;
DIVQ MR1; DIVQ MR1; DIVQ MR1;
DIVQ MR1; DIVQ MR1; DIVQ MR1;
DIVQ MR1; DIVQ MR1; DIVQ MR1;
MX0=AY0;
MR=0;
MR0=0x2000;
MR=MR+MX0*MY0 (US); { 9.23 format in result }
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 6 of 16
SR=ASHIFT MR1 BY 2 (HI); { to compensate the coefficient scaling }
SR=SR OR LSHIFT MR0 BY 2 (LO); { and get 8.8 format }
Jump modification;
frac: MR=MR1*MY0 (RND);
SR=ASHIFT MR1 BY -6 (HI); { compensate coefficient scaling }
{ and get 8.8 format}
modification: AR = PASS AX1;
IF GE RTS; { MSB = 1? }
MY1 = sqrt_2; { if yes, the original left shifted 1 bit }
MR = SR1 * MY1(uu); { multiplied by sqrt2(2) to get final result }
SR1 = MR1;
RTS;
1.4 Logarithm
1.4.1 Common Logarithm (Base 10)
The following equation approximates the common logarithm of the input value 11, is shown here. If the input
falls outside of this valid range, the output will reach saturation and ALU overflow bit AC in the ASTAT
register will be set. The integer part of the input is stored in MR1 register in signed 16.0 twos complement
format, while the fractional part of the input in MR0 in 0.16 format. The final result is in signed 1.15
format in SR1 register.
inv_: AR = PASS MR1;
IF GE JUMP dps1; { x >= 0 ?? }
JUMP dps2;
dps1: AY1 = 0x1; AY0 = 0x0; { x > 1 ?? }
AR = MR0-AY0;
SR0=AR, AR = MR1-AY1+C-1;
JUMP overflow;
dps2: SR1 = 0xFFFF; SR0 = 0x0; { x < -1 }
AY1 = MR1; AY0 = MR0;
AR = SR0-AY0;
AR = SR1-AY1+C-1;
overflow: IF GT JUMP inv_1; { if ABS(x)<=1, overflow }
SR1 = 0x7FFF;
AR = PASS AY1;
IF GT JUMP Returning;
SR1 = 0x8000;
Returning: ASTAT=0x4; { set AV }
RTS;
inv_1: AY1=0x4000; { if ABS(x)>1, division start here }
AY0=0; { numerator = 1 }
SE=EXP MR1 (HI); {Check for redundant bits}
SR=NORM MR1 (HI);
SR=SR OR NORM MR0 (LO);
DIVS AY1, SR1;
DIVQ SR1; DIVQ SR1; DIVQ SR1;
DIVQ SR1; DIVQ SR1; DIVQ SR1;
DIVQ SR1; DIVQ SR1; DIVQ SR1;
DIVQ SR1; DIVQ SR1; DIVQ SR1;
DIVQ SR1; DIVQ SR1; DIVQ SR1;
MR1= AY0; { in 1.15 format }
AX0=-14; AY1=SE;
AR = AX0 - AY1;
SE = AR;
SR = ASHIFT MR1 (HI); { Output in SR1 in 1.15 format }
RTS;
2.2 Division
A single-precision division subroutine is implemented hereafter, with a 32-bit signed dividend
(numerator) and a 16-bit signed divisor (denominator) to yield a 16-bit quotient. The dividend is in
NL.NR format and divisor is in DL.DR format. The quotient will be in (NL-DL+1).(NR-DR-1) format.
For example, if the divisor is in 1.31 format and divisor 1.15 format, the quotient will be in 1.15 format.
Some format manipulation may be necessary to guarantee the validity of the quotient, otherwise, the
output may saturate and AV in ASTAT register is set. For example, if both operands are positive and
fully fractional with dividend and divisor in 1.31 and 1.15 signed format respectively, the result is fully
fractional in 1.15 format and therefore the dividend must be smaller than the divisor for a valid result.
This subroutine can not be used for integer division or unsigned division.
div_: AX1=AY1,AF=AX0-AY1;
AR=ABS AX0;
if NE JUMP test_2;
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 9 of 16
AR=0x7FFF;
AF=PASS AY1;
if LT AR= NOT AR; {return +/- infinity}
ASTAT=0x4; {Division by Zero }
RTS;
test_2: {Division by -1}
if NOT AV JUMP test_3;
AR = -AY1; {Return -x }
RTS;
test_3: {x=y therefore return 1}
AF=PASS AF;
if NE JUMP test_4;
AR=0x7FFF;
ASTAT=0x0;
RTS;
test_4:
AX1=AY1,AR=ABS AX0;
AF=ABS AX1;
AF=AF-AR;
if LT JUMP do_div;
AR=0x7FFF;
AF=PASS AY1;
if LT AR= NOT AR; {return - infinity}
AF=PASS AX0;
if LT AR= NOT AR; {return - * - infinity}
ASTAT=0x4; {Division Overflow}
RTS;
do_div:
DIVS AY1,AX0;
CNTR=15;
do do_div01 until ce;
do_div01: DIVQ AX0;
AR=AY0;
AF=PASS AX0;
if LT AR=-AR;
RTS;
1.6 Access to the library: the header file
The library may be accessed by including the header file “mathfun.h” into the application code.
The header file is intended to provide function-like calls to the routines presented in the previous section. It
defines the calls shown in Table 1. The file is self-explaining and needs no further comments.
It is worth adding a few comments about efficiency of these routines. The first macro simply sets the DAG
registers M5 and L5 to its correct values. The user may however just replace the macro with one of its
instructions when the application code modifies just one of these registers. The sine and cosine subroutines
expect the argument to be placed into certain registers. This is what the macros do. However, if the argument
is already in the correct registers, the macro call inserts obsolete instruction. In this case, it is more efficient
to replace the macro call by a call instruction to the corresponding subroutine.
.MACRO Set_DAG_registers_for_math_function;
M5 = 1;
L5 = 0;
.ENDMACRO;
.MACRO Square_Root(%0, %1);
MR1 = %0;
MR0 = %1;
call sqrt_;
.ENDMACRO;
.MACRO Log10(%0, %1);
MR1 = %0;
MR0 = %1;
call Log10_;
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 10 of 16
.ENDMACRO;
.MACRO LogN(%0, %1);
MR1 = %0;
MR0 = %1;
call ln_;
.ENDMACRO;
.MACRO Inverse(%0, %1);
MR1 = %0;
MR0 = %1;
call inv_;
.ENDMACRO;
.MACRO Signed_Division(%0,%1,%2);
AY1 = %0;
AY0 = %1;
AX0 = %2;
call div_;
.ENDMACRO;
.MACRO Atan(%0, %1);
mr1= %0;
mr0= %1;
call Atan_;
.ENDMACRO;
2 Software Example: Testing the Mathematical Functions
2.1 The main program: main.dsp
The example demonstrates how to use the routines. All it does is to cycle through parts of the range of
definition of the functions and converting the results by means of the digital to analog converter. The
application has been adapted from two previous notes4,5. This section will only explain the few and
intuitive modifications to those applications.
The file “main.dsp” contains the initialisation and PWM Sync and Trip interrupt service routines. To
activate, build the executable file using the attached build.bat either within your DOS prompt or clicking
on it from Windows Explorer. This will create the object files and the main.exe example file. This file
may be run on the Motion Control Debugger.
In the following, a brief description of the additional code (put in evidence by bold characters) is given.
Start of code – declaring start location in program memory
.MODULE/RAM/SEG=USER_PM1/ABS=0x60 Main_Program;
Next, the general systems constants and PWM configuration constants (main.h – see the next section) are
included. Also included are the PWM library, the DAC interface library, the trigonometric library and the
mathematical library.
{***************************************************************************************
* Include General System Parameters and Libraries *
***************************************************************************************}
#include ;
#include ;
#include ;
#include ;
4 AN300-03: Three-Phase Sine-Wave Generation using the PWM Unit of the ADMC300
5 AN300-06: Using the Serial Digital to Analog Converter of the ADMC Connector Board
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 11 of 16
#include ;
The argument variable Theta is defined hereafter.
{***************************************************************************************
* Local Variables Defined in this Module *
***************************************************************************************}
.VAR/DM/RAM/SEG=USER_DM Theta; { Current angle }
.INIT Theta : 0x0000;
First, the PWM block is set up to generate interrupts every 100μs (see “main.h” in the next Section). The
variable Theta, which stores the argument of the trigonometric functions, is set to zero. Before using the
trigonometric functions, it is necessary to initialise certain registers of the data-address-generator (DAG) of
the DSP core. This will be discussed in more detail in the next section. However, note that this is done only
once in this example. If those registers are modified in other parts of the user’s code, then it must be repeated
before a call to a trigonometric function.
The main loop just waits for interrupts.
{********************************************************************************************}
{ Start of program code }
{********************************************************************************************}
Startup:
PWM_Init(PWMSYNC_ISR, PWMTRIP_ISR);
DAC_Init;
IFC = 0x80; { Clear any pending IRQ2 inter. }
ay0 = 0x200; { unmask irq2 interrupts. }
ar = IMASK;
ar = ar or ay0;
IMASK = ar; { IRQ2 ints fully enabled here }
ar = pass 0;
DM(Theta)= ar;
Set_DAG_registers_for_trigonometric;
Main: { Wait for interrupt to occur }
jump Main;
rts;
The interrupt service routine simply shows how to use the described functions. Variable Theta is incremented
in every interrupt service and is used as input for testing the mathematical functions. This main routine is
very similar to the one used in Application Note: AN300-10.
{********************************************************************************************}
{ PWM Interrupt Service Routine }
{********************************************************************************************}
PWMSYNC_ISR:
AX1 = DM(THETA);
COS(ax1);
DAC_PUT(1, AR); { output cos(x) }
MY0 = 0x4000;
MR = AR * MY0(SS);
AY0 = 0x4000;
AR = MR1 + AY0;
SR = LSHIFT AR BY 1 (LO);
Square_Root(SR1, SR0);
SR = LSHIFT SR1 BY 7 (HI);
DAC_PUT(2, SR1); { output ABS(cos(x/2) }
SR1 = DM(THETA);
SR0 = 0;
Square_Root(SR1, SR0);
SR = LSHIFT SR1 BY -1 (HI); { output Square_Root(x) }
DAC_PUT(3, SR1);
AX1 = DM(THETA); { log10(x), fractional input }
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 12 of 16
LOG10(0x0000,AX1);
DAC_PUT(4, SR1);
AX1 = DM(THETA); { Log10(x), integer input }
LOG10(AX1, 0x0000);
DAC_PUT(5, SR1);
AX1 = DM(THETA); { LogN(x), fractional input }
LogN(0x0000,AX1);
DAC_PUT(6, SR1);
AX1 = DM(THETA); { LogN(x), integer input }
LogN(AX1, 0x0000);
DAC_PUT(7, SR1);
{ tan(x) for division test }
{ AX0= DM(THETA);
AY1 = 0x1FFF; AR=ABS AX0;
AR = AR - AY1;
IF GT JUMP No_div;
cos(AX0);
AX1 = AR;
sin(AX0);
Signed_Division(AR,0x0000,AX1);
Jump PUT;
No_div: AR = 0;
PUT: DAC_PUT(8, AR);
}
SR1 = DM(THETA); { Inverse(x) }
SR = ASHIFT SR1 by -11 (HI);
Inverse(SR1, SR0);
DAC_PUT(8, SR1);
DAC_Update;
ax1= DM(Theta);
ar= ax1 +1;
DM(Theta)= ar;
RTI;
2.2 The main include file: main.h
This file contains the definitions of ADMC300 constants, general-purpose macros and the configuration
parameters of the system and library routines. It should be included in every application. For more
information refer to the Library Documentation File.
This file is mostly self-explaining. As already mentioned, the trigonometric library does not require any
configuration parameters. The following defines the parameters for the PWM ISR used in this example.
{********************************************************************************************}
{ Library: PWM block }
{ file : PWM300.dsp }
{ Application Note: Usage of the ADMC300 Pulse Width Modulation Block }
.CONST PWM_freq = 10000; {Desired PWM switching frequency [Hz] }
.CONST PWM_deadtime = 1000; {Desired deadtime [nsec] }
.CONST PWM_minpulse = 1000; {Desired minimal pulse time [nsec] }
.CONST PWM_syncpulse = 1540; {Desired sync pulse time [nsec] }
{********************************************************************************************}
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 13 of 16
2.3 Example outputs
2.3.1 Square Root
The example applies the square root function to perform the calculation of equation (4.1). The result is
directed to the digital to analog converters on the connection board. Figure 1 shows the output waveforms
of cos(x) and cos(x / 2) .
It is well known that
2
cos( ) 1
cos( ) / 2) = + x
x ( 6)
Figure 1: cos(x) and cos(x / 2)
The valid input to the square root function is from 0x0000.0000 to 0xFFFF.FFFF in MR registers. For the
D/A converter, digital value 0 is corresponding to 2.5v, -1 to 0V and +1 to 5V in the DAC outputs.
Figure 2: Square _ Root(x)
Figure 2 shows the result in another test when x is increased from 0x0000.0000 to 0xFFFF.0000. The
output is in a range of 0x00.00 and 0xFF.00.
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 14 of 16
2.3.2 Logarithm
2.3.2.1 Common logarithm
Figure 3 shows the results of calculating log10(x) for an input range 0= 0 THEN PHASE[K%] = PHASE[K%] + PI
300 NEXT K%
310 '
320 '
330 ' 'Polar-to-rectangular conversion, Eq. 8-7
340 FOR K% = 0 TO 256
350 REX[K%] = MAG[K%] * COS( PHASE[K%] )
360 IMX[K%] = MAG[K%] * SIN( PHASE[K%] )
370 NEXT K%
380 '
390 END
TABLE 8-3
Nuisance 2: Divide by zero error
When converting from rectangular to polar notation, it is very common to
find frequencies where the real part is zero and the imaginary part is some
nonzero value. This simply means that the phase is exactly 90 or -90
degrees. Try to tell your computer this! When your program tries to
calculate the phase from: Phase X[k] ’ arctan( Im X[k] / Re X[k]) , a divide by
zero error occurs. Even if the program execution doesn't halt, the phase
you obtain for this frequency won't be correct. To avoid this problem, the
real part must be tested for being zero before the division. If it is zero, the
imaginary part must be tested for being positive or negative, to determine
whether to set the phase to B/2 or -B/2, respectively. Lastly, the division
needs to be bypassed. Nothing difficult in all these steps, just the potential
for aggravation. An alternative way to handle this problem is shown in
line 250 of Table 8-3. If the real part is zero, change it to a negligibly
small number to keep the math processor happy during the division.
Nuisance 3: Incorrect arctan
Consider a frequency domain sample where ReX[k] ’ 1 and Im X[k] ’ 1.
Equation 8-6 provides the corresponding polar values of Mag X[k] ’ 1.414 and
Phase X[k] ’ 45E. Now consider another sample where ReX[k] ’ &1 and
166 The Scientist and Engineer's Guide to Digital Signal Processing
FIGURE 8-11
The phase of small magnitude signals. At frequencies where the magnitude drops to a very low value, round-off
noise can cause wild excursions of the phase. Don't make the mistake of thinking this is a meaningful signal.
Frequency
0 0.1 0.2 0.3 0.4 0.5
0.0
0.5
1.0
1.5
a. Mag X[ ]
Frequency
0 0.1 0.2 0.3 0.4 0.5
-5
-4
-3
-2
-1
0
1
2
3
4
5
b. Phase X[ ]
Amplitude
Phase (radians)
Im X[k] ’ &1. Again, Eq. 8-6 provides the values of Mag X[k] ’ 1.414 and
Phase X[k] ’ 45E. The problem is, the phase is wrong! It should be &135E.
This error occurs whenever the real part is negative. This problem can be
corrected by testing the real and imaginary parts after the phase has been
calculated. If both the real and imaginary parts are negative, subtract 180E
(or B radians) from the calculated phase. If the real part is negative and the
imaginary part is positive, add 180E (or B radians). Lines 340 and 350 of the
program in Table 8-3 show how this is done. If you fail to catch this problem,
the calculated value of the phase will only run between -B/2 and B/2, rather
than between -B and B. Drill this into your mind. If you see the phase only
extending to ±1.5708, you have forgotten to correct the ambiguity in the
arctangent calculation.
Nuisance 4: Phase of very small magnitudes
Imagine the following scenario. You are grinding away at some DSP task, and
suddenly notice that part of the phase doesn't look right. It might be noisy,
jumping all over, or just plain wrong. After spending the next hour looking
through hundreds of lines of computer code, you find the answer. The
corresponding values in the magnitude are so small that they are buried in
round-off noise. If the magnitude is negligibly small, the phase doesn't have
any meaning, and can assume unusual values. An example of this is shown in
Fig. 8-11. It is usually obvious when an amplitude signal is lost in noise; the
values are so small that you are forced to suspect that the values are
meaningless. The phase is different. When a polar signal is contaminated
with noise, the values in the phase are random numbers between -B and B.
Unfortunately, this often looks like a real signal, rather than the nonsense it
really is.
Nuisance 5: 2B ambiguity of the phase
Look again at Fig. 8-10d, and notice the several discontinuities in the data.
Every time a point looks as if it is going to dip below -3.14592, it snaps
back to 3.141592. This is a result of the periodic nature of sinusoids. For
Chapter 8- The Discrete Fourier Transform 167
FIGURE 8-12
Example of phase unwrapping. The top curve
shows a typical phase signal obtained from a
rectangular-to-polar conversion routine. Each
value in the signal must be between -B and B
(i.e., -3.14159 and 3.14159). As shown in the
lower curve, the phase can be unwrapped by
adding or subtracting integer multiplies of 2B
from each sample, where the integer is chosen
to minimize the discontinuities between points.
Frequency
0 0.1 0.2 0.3 0.4 0.5
-40
-30
-20
-10
0
10
wrapped
unwrapped
Phase (radians)
100 ' PHASE UNWRAPPING
110 '
120 DIM PHASE[256] 'PHASE[ ] holds the original phase
130 DIM UWPHASE[256] 'UWPHASE[ ] holds the unwrapped phase
140 '
150 PI = 3.14159265
160 '
170 GOSUB XXXX 'Mythical subroutine to load data into PHASE[ ]
180 '
190 UWPHASE[0] = 0 'The first point of all phase signals is zero
200 '
210 ' 'Go through the unwrapping algorithm
220 FOR K% = 1 TO 256
230 C% = CINT( (UWPHASE[K%-1] - PHASE[K%]) / (2 * PI) )
240 UWPHASE[K%] = PHASE[K%] + C%*2*PI
250 NEXT K%
260 '
270 END
TABLE 8-4
example, a phase shift of q is exactly the same as a phase shift of q + 2p , q + 4p ,
q + 6p , etc. Any sinusoid is unchanged when you add an integer multiple of
2B to the phase. The apparent discontinuities in the signal are a result of the
computer algorithm picking its favorite choice from an infinite number of
equivalent possibilities. The smallest possible value is always chosen, keeping
the phase between -B and B.
It is often easier to understand the phase if it does not have these
discontinuities, even if it means that the phase extends above B, or below -B.
This is called unwrapping the phase, and an example is shown in Fig. 8-12.
As shown by the program in Table 8-4, a multiple of 2B is added or subtracted
from each value of the phase. The exact value is determined by an algorithm
that minimizes the difference between adjacent samples.
Nuisance 6: The magnitude is always positive (B ambiguity of the phase)
Figure 8-13 shows a frequency domain signal in rectangular and polar form.
The real part is smooth and quite easy to understand, while the imaginary
part is entirely zero. In comparison, the polar signals contain abrupt
168 The Scientist and Engineer's Guide to Digital Signal Processing
Frequency
0 0.1 0.2 0.3 0.4 0.5
-1
0
1
2
3
a. Re X[ ]
Frequency
0 0.1 0.2 0.3 0.4 0.5
-1
0
1
2
3
c. Mag X[ ]
Frequency
0 0.1 0.2 0.3 0.4 0.5
-5
-4
-3
-2
-1
0
1
2
3
4
5
d. Phase X[ ]
Rectangular Polar
FIGURE 8-13
Example signals in rectangular and polar form. Since the magnitude must always be positive (by definition),
the magnitude and phase may contain abrupt discontinuities and sharp corners. Figure (d) also shows
another nuisance: random noise can cause the phase to rapidly oscillate between B or -B.
Frequency
0 0.1 0.2 0.3 0.4 0.5
-3
-2
-1
0
1
2
3
b. Im X[ ]
Amplitude
Amplitude Amplitude
Phase (radians)
discontinuities and sharp corners. This is because the magnitude must always
be positive, by definition. Whenever the real part dips below zero, the
magnitude remains positive by changing the phase by B (or -B, which is the
same thing). While this is not a problem for the mathematics, the irregular
curves can be difficult to interpret.
One solution is to allow the magnitude to have negative values. In the example
of Fig. 8-13, this would make the magnitude appear the same as the real part,
while the phase would be entirely zero. There is nothing wrong with this if it
helps your understanding. Just be careful not to call a signal with negative
values the "magnitude" since this violates its formal definition. In this book we
use the weasel words: unwrapped magnitude to indicate a "magnitude" that is
allowed to have negative values.
Nuisance 7: Spikes between B and -B
Since B and -B represent the same phase shift, round-off noise can cause
adjacent points in the phase to rapidly switch between the two values. As
shown in Fig. 8-13d, this can produce sharp breaks and spikes in an otherwise
smooth curve. Don't be fooled, the phase isn't really this discontinuous.
Low Power, 12.65 mW, 2.3 V to 5.5 V,
Programmable Waveform Generator
Data Sheet AD9833
Rev. E Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2012 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Digitally programmable frequency and phase
12.65 mW power consumption at 3 V
0 MHz to 12.5 MHz output frequency range
28-bit resolution: 0.1 Hz at 25 MHz reference clock
Sinusoidal, triangular, and square wave outputs
2.3 V to 5.5 V power supply
No external components required
3-wire SPI interface
Extended temperature range: −40°C to +105°C
Power-down option
10-lead MSOP package
Qualified for automotive applications
APPLICATIONS
Frequency stimulus/waveform generation
Liquid and gas flow measurement
Sensory applications: proximity, motion, and defect detection
Line loss/attenuation
Test and medical equipment
Sweep/clock generators
Time domain reflectometry (TDR) applications
GENERAL DESCRIPTION
The AD9833 is a low power, programmable waveform generator capable of producing sine, triangular, and square wave outputs. Waveform generation is required in various types of sensing, actuation, and time domain reflectometry (TDR) applications. The output frequency and phase are software programmable, allowing easy tuning. No external components are needed. The frequency registers are 28 bits wide: with a 25 MHz clock rate, resolution of 0.1 Hz can be achieved; with a 1 MHz clock rate, the AD9833 can be tuned to 0.004 Hz resolution.
The AD9833 is written to via a 3-wire serial interface. This serial interface operates at clock rates up to 40 MHz and is compatible with DSP and microcontroller standards. The device operates with a power supply from 2.3 V to 5.5 V.
The AD9833 has a power-down function (SLEEP). This function allows sections of the device that are not being used to be powered down, thus minimizing the current consumption of the part. For example, the DAC can be powered down when a clock output is being generated.
The AD9833 is available in a 10-lead MSOP package.
FUNCTIONAL BLOCK DIAGRAM
SERIAL INTERFACEANDCONTROL LOGICSCLKSDATAFSYNCCONTROL REGISTERPHASE1 REGPHASE0 REGMUXSINROM10-BITDACMUXFREQ0 REGFREQ1 REG12ON-BOARDREFERENCEAGNDDGNDVDDAD9833PHASEACCUMULATOR(28-BIT)REGULATORCAP/2.5V2.5VAVDD/DVDDMUXDIVIDEBY 2MSBMUXFULL-SCALECONTROLCOMPVOUTR200ΩMCLK02704-001
Figure 1.
AD9833 Data Sheet
Rev. E | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Terminology .................................................................................... 10
Theory of Operation ...................................................................... 11
Circuit Description ......................................................................... 12
Numerically Controlled Oscillator Plus Phase Modulator ... 12
Sin ROM ...................................................................................... 12
Digital-to-Analog Converter (DAC) ....................................... 12
Regulator...................................................................................... 12
Functional Description .................................................................. 13
Serial Interface ............................................................................ 13
Powering Up the AD9833 ......................................................... 13
Latency Period ............................................................................ 13
Control Register ......................................................................... 13
Frequency and Phase Registers ................................................ 15
Reset Function ............................................................................ 16
Sleep Function ............................................................................ 16
VOUT Pin ................................................................................... 16
Applications Information .............................................................. 17
Grounding and Layout .............................................................. 17
Interfacing to Microprocessors ..................................................... 20
AD9833 to 68HC11/68L11 Interface ....................................... 20
AD9833 to 80C51/80L51 Interface .......................................... 20
AD9833 to DSP56002 Interface ............................................... 20
Evaluation Board ............................................................................ 21
System Demonstration Platform .............................................. 21
AD9833 to SPORT Interface ..................................................... 21
Evaluation Kit ............................................................................. 21
Crystal Oscillator vs. External Clock ....................................... 21
Power Supply ............................................................................... 21
Evaluation Board Schematics ................................................... 22
Evaluation Board Layout ........................................................... 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
Automotive Products ................................................................. 24
REVISION HISTORY
9/12—Rev. D to Rev. E
Changed Input Current, IINH/IINL from 10 mA to 10 μA.............. 3
4/11—Rev. C to Rev. D
Change to Figure 13 ......................................................................... 8
Changes to Table 9 .......................................................................... 15
Deleted AD9833 to ADSP-2101/ADSP-2103 Interface Section .............................................................................................. 20
Changes to Evaluation Board Section .......................................... 21
Added System Demonstration Platform Section, AD9833 to SPORT Interface Section, and Evaluation Kit Section .......... 21
Changes to Crystal Oscillator vs. External Clock Section and Power Supply Section ............................................................. 21
Added Figure 32 and Figure 33; Renumbered Figures Sequentially ..................................................................................... 21
Deleted Prototyping Area Section and Figure 33 ....................... 22
Added Evaluation Board Schematics Section, Figure 34, and Figure 35 ................................................................................... 22
Deleted Table 16 .............................................................................. 23
Added Evaluation Board Layout Section, Figure 36, Figure 37, and Figure 38 ................................................................ 23
Changes to Ordering Guide .......................................................... 24
9/10—Rev. B to Rev. C
Changed 20 mW to 12.65 mW in Data Sheet Title and Features List ................................................................................ 1
Changes to Figure 6 Caption and Figure 7..................................... 7
6/10—Rev. A to Rev. B
Changes to Features Section ............................................................ 1
Changes to Serial Interface Section.............................................. 13
Changes to VOUT Pin Section ..................................................... 16
Changes to Grounding and Layout Section ................................ 17
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
Added Automotive Products Section .......................................... 24
6/03—Rev. 0 to Rev. A
Updated Ordering Guide ................................................................. 4
Data Sheet AD9833
Rev. E | Page 3 of 24
SPECIFICATIONS
VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, RSET = 6.8 kΩ for VOUT, unless otherwise noted.
Table 1.
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
SIGNAL DAC SPECIFICATIONS
Resolution
10
Bits
Update Rate
25
MSPS
VOUT Maximum
0.65
V
VOUT Minimum
38
mV
VOUT Temperature Coefficient
200
ppm/°C
DC Accuracy
Integral Nonlinearity
±1.0
LSB
Differential Nonlinearity
±0.5
LSB
DDS SPECIFICATIONS (SFDR)
Dynamic Specifications
Signal-to-Noise Ratio (SNR)
55
60
dB
fMCLK = 25 MHz, fOUT = fMCLK/4096
Total Harmonic Distortion (THD)
−66
−56
dBc
fMCLK = 25 MHz, fOUT = fMCLK/4096
Spurious-Free Dynamic Range (SFDR)
Wideband (0 to Nyquist)
−60
dBc
fMCLK = 25 MHz, fOUT = fMCLK/50
Narrow-Band (±200 kHz)
−78
dBc
fMCLK = 25 MHz, fOUT = fMCLK/50
Clock Feedthrough
−60
dBc
Wake-Up Time
1
ms
LOGIC INPUTS
Input High Voltage, VINH
1.7
V
2.3 V to 2.7 V power supply
2.0
V
2.7 V to 3.6 V power supply
2.8
V
4.5 V to 5.5 V power supply
Input Low Voltage, VINL
0.5
V
2.3 V to 2.7 V power supply
0.7
V
2.7 V to 3.6 V power supply
0.8
V
4.5 V to 5.5 V power supply
Input Current, IINH/IINL
10
μA
Input Capacitance, CIN
3
pF
POWER SUPPLIES
fMCLK = 25 MHz, fOUT = fMCLK/4096
VDD
2.3
5.5
V
IDD
4.5
5.5
mA
IDD code dependent; see Figure 7
Low Power Sleep Mode
0.5
mA
DAC powered down, MCLK running
1 Operating temperature range is −40°C to +105°C; typical specifications are at 25°C.
VOUTCOMP12AD983310-BIT DACSINROM20pF10nFVDDREGULATOR100nFCAP/2.5V02704-002
Figure 2. Test Circuit Used to Test Specifications
AD9833 Data Sheet
Rev. E | Page 4 of 24
TIMING CHARACTERISTICS
VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.1
Table 2.
Parameter
Limit at TMIN to TMAX
Unit
Description
t1
40
ns min
MCLK period
t2
16
ns min
MCLK high duration
t3
16
ns min
MCLK low duration
t4
25
ns min
SCLK period
t5
10
ns min
SCLK high duration
t6
10
ns min
SCLK low duration
t7
5
ns min
FSYNC to SCLK falling edge setup time
t8 min
10
ns min
FSYNC to SCLK hold time
t8 max
t4 − 5
ns max
t9
5
ns min
Data setup time
t10
3
ns min
Data hold time
t11
5
ns min
SCLK high to FSYNC falling edge setup time
1 Guaranteed by design, not production tested.
Timing Diagrams
t2t1MCLKt302704-003
Figure 3. Master Clock
t5t4t6t7t8t10t941D51DD0D1D2D14SCLKFSYNCSDATAD15t1102704-004
Figure 4. Serial Timing
Data Sheet AD9833
Rev. E | Page 5 of 24
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
Rating
VDD to AGND
−0.3 V to +6 V
VDD to DGND
−0.3 V to +6 V
AGND to DGND
−0.3 V to +0.3 V
CAP/2.5V
2.75 V
Digital I/O Voltage to DGND
−0.3 V to VDD + 0.3 V
Analog I/O Voltage to AGND
−0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version)
−40°C to +105°C
Storage Temperature Range
−65°C to +150°C
Maximum Junction Temperature
150°C
MSOP Package
θJA Thermal Impedance
206°C/W
θJC Thermal Impedance
44°C/W
Lead Temperature, Soldering (10 sec)
300°C
IR Reflow, Peak Temperature
220°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
AD9833 Data Sheet
Rev. E | Page 6 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
COMP1VDD2CAP/2.5V3DGND4MCLK5VOUT10AGND9FSYNC8SCLK7SDATA6AD9833TOP VIEW(Not to Scale)02704-005
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
COMP
DAC Bias Pin. This pin is used for decoupling the DAC bias voltage.
2
VDD
Positive Power Supply for the Analog and Digital Interface Sections. The on-board 2.5 V regulator is also supplied from VDD. VDD can have a value from 2.3 V to 5.5 V. A 0.1 μF and a 10 μF decoupling capacitor should be connected between VDD and AGND.
3
CAP/2.5V
The digital circuitry operates from a 2.5 V power supply. This 2.5 V is generated from VDD using an on-board regulator when VDD exceeds 2.7 V. The regulator requires a decoupling capacitor of 100 nF typical, which is connected from CAP/2.5V to DGND. If VDD is less than or equal to 2.7 V, CAP/2.5V should be tied directly to VDD.
4
DGND
Digital Ground.
5
MCLK
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The output frequency accuracy and phase noise are determined by this clock.
6
SDATA
Serial Data Input. The 16-bit serial data-word is applied to this input.
7
SCLK
Serial Clock Input. Data is clocked into the AD9833 on each falling edge of SCLK.
8
FSYNC
Active Low Control Input. FSYNC is the frame synchronization signal for the input data. When FSYNC is taken low, the internal logic is informed that a new word is being loaded into the device.
9
AGND
Analog Ground.
10
VOUT
Voltage Output. The analog and digital output from the AD9833 is available at this pin. An external load resistor is not required because the device has a 200 Ω resistor on board.
Data Sheet AD9833
Rev. E | Page 7 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
MCLK FREQUENCY (MHz)IDD (mA)5.55.03.03.54.04.50510152025TA = 25°C02704-006VDD = 5VVDD = 3V
Figure 6. Typical Current Consumption (IDD) vs. MCLK Frequency for fOUT = MCLK/10
01234561001k10k100k1M10MIDD (
mA)fOUT (Hz)VDD = 5VVDD = 3V02704-007
Figure 7. Typical IDD vs. fOUT for fMCLK = 25 MHz
0510152025MCLK FREQUENCY (MHz)SFDR (dBc)–65–60–90–70–75–80–85MCLK/7MCLK/50VDD = 3VTA= 25°C02704-008
Figure 8. Narrow-Band SFDR vs. MCLK Frequency
–45–40–705791113151719212325–50–55–60–65MCLK FREQUENCY (MHz)SFDR (dBc)MCLK/7MCLK/50VDD = 3VTA= 25°C02704-009
Figure 9. Wideband SFDR vs. MCLK Frequency
fOUT/fMCLK–30–90–80–70–60–50–40SFDR (
dB)0–20–10fMCLK =1MHzfMCLK =10MHz0.0010.010.1110100fMCLK =25MHzVDD = 3VTA= 25°C02704-010fMCLK =18MHz
Figure 10. Wideband SFDR vs. fOUT/fMCLK for Various MCLK Frequencies
MCLK FREQUENCY (MHz)1.05.010.012.525.0SNR (
dB)–60–65–70–50–55–40–45VDD = 3VTA= 25°CfOUT= MCLK/409602704-011
Figure 11. SNR vs. MCLK Frequency
AD9833 Data Sheet
Rev. E | Page 8 of 24
5001000700650600550850750800900950–4025105TEMPERATURE (°C)WAKE-UP TIME (μs)VDD = 5.5V02704-012VDD = 2.3V
Figure 12. Wake-Up Time vs. Temperature
–4025105TEMPERATURE (°C)VREF (V)LOWER RANGEUPPER RANGE1.1501.1251.1001.1751.2001.2501.22502704-013
Figure 13. VREF vs. Temperature
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–100100kRWB 100ST 100 SECVWB 3002704-014
Figure 14. Power vs. Frequency, fMCLK = 10 MHz, fOUT = 2.4 kHz, Frequency Word = 0x000FBA9
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–1005MRWB 1kST 50 SECVWB 30002704-015
Figure 15. Power vs. Frequency, fMCLK = 10 MHz, fOUT = 1.43 MHz = fMCLK/7, Frequency Word = 0x2492492
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–1005MRWB 1kST 50 SECVWB 30002704-016
Figure 16. Power vs. Frequency, fMCLK = 10 MHz, fOUT = 3.33 MHz = fMCLK/3, Frequency Word = 0x5555555
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–100100kRWB 100ST 100 SECVWB 3002704-017
Figure 17. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 6 kHz, Frequency Word = 0x000FBA9
Data Sheet AD9833
Rev. E | Page 9 of 24
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–1001MRWB 300ST 100 SECVWB 10002704-018
Figure 18. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 60 kHz, Frequency Word = 0x009D495
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–10012.5MRWB 1kST 100 SECVWB 30002704-019
Figure 19. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 600 kHz, Frequency Word = 0x0624DD3
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–10012.5MRWB 1kST 100 SECVWB 30002704-020
Figure 20. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 2.4 MHz, Frequency Word = 0x189374D
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–10012.5MRWB 1kST 100 SECVWB 30002704-021
Figure 21. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 3.857 MHz = fMCLK/7, Frequency Word = 0x2492492
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–10012.5MRWB 1kST 100 SECVWB 30002704-022
Figure 22. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 8.333 MHz = fMCLK/3, Frequency Word = 0x5555555
AD9833 Data Sheet
Rev. E | Page 10 of 24
TERMINOLOGY
Integral Nonlinearity (INL)
INL is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The end-points of the transfer function are zero scale, a point 0.5 LSB below the first code transition (000 … 00 to 000 … 01), and full scale, a point 0.5 LSB above the last code transition (111 … 10 to 111 … 11). The error is expressed in LSBs.
Differential Nonlinearity (DNL)
DNL is the difference between the measured and ideal 1 LSB change between two adjacent codes in the DAC. A specified DNL of ±1 LSB maximum ensures monotonicity.
Output Compliance
Output compliance refers to the maximum voltage that can be generated at the output of the DAC to meet the specifications. When voltages greater than that specified for the output compli-ance are generated, the AD9833 may not meet the specifications listed in the data sheet.
Spurious-Free Dynamic Range (SFDR)
Along with the frequency of interest, harmonics of the funda-mental frequency and images of these frequencies are present at the output of a DDS device. SFDR refers to the largest spur or harmonic present in the band of interest. The wideband SFDR gives the magnitude of the largest spur or harmonic relative to the magnitude of the fundamental frequency in the zero to Nyquist bandwidth. The narrow-band SFDR gives the attenuation of the largest spur or harmonic in a bandwidth of ±200 kHz about the fundamental frequency.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the rms value of the fundamental. For the AD9833, THD is defined as
12625242322log20THDVVVVVV++++=
where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through sixth harmonics.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency. The value for SNR is expressed in decibels.
Clock Feedthrough
There is feedthrough from the MCLK input to the analog output. Clock feedthrough refers to the magnitude of the MCLK signal relative to the fundamental frequency in the output spectrum of the AD9833.
Data Sheet AD9833
Rev. E | Page 11 of 24 THEORY OF OPERATION
Sine waves are typically thought of in terms of their magnitude form: a(t) = sin(ωt). However, these sine waves are nonlinear and not easy to generate except through piecewise construction. On the other hand, the angular information is linear in nature. That
is, the phase angle rotates through a fixed angle for each unit of
time. The angular rate depends on the frequency of the signal
by the traditional rate of ω = 2πf.
MAGNITUDE
PHASE
+1
0
–1
2p
0
2π 4π
6π
2π 4π 6π
02704-023
Figure 23. Sine Wave
Knowing that the phase of a sine wave is linear and given a
reference interval (clock period), the phase rotation for that period can be determined.
ΔPhase = ωΔt
Solving for ω, ω = ΔPhase/Δt = 2πf
Solving for f and substituting the reference clock frequency for the reference period (1/fMCLK = Δt)
f = ΔPhase × fMCLK∕2π
The AD9833 builds the output based on this simple equation. A
simple DDS chip can implement this equation with three major
subcircuits: numerically controlled oscillator (NCO) and phase
modulator, SIN ROM, and digital-to-analog converter (DAC). Each subcircuit is described in the Circuit Description section.
AD9833 Data Sheet
Rev. E | Page 12 of 24
CIRCUIT DESCRIPTION
The AD9833 is a fully integrated direct digital synthesis (DDS) chip. The chip requires one reference clock, one low precision resistor, and decoupling capacitors to provide digitally created sine waves up to 12.5 MHz. In addition to the generation of this RF signal, the chip is fully capable of a broad range of simple and complex modulation schemes. These modulation schemes are fully implemented in the digital domain, allowing accurate and simple realization of complex modulation algorithms using DSP techniques.
The internal circuitry of the AD9833 consists of the following main sections: a numerically controlled oscillator (NCO), frequency and phase modulators, SIN ROM, a DAC, and a regulator.
NUMERICALLY CONTROLLED OSCILLATOR PLUS PHASE MODULATOR
This consists of two frequency select registers, a phase accumulator, two phase offset registers, and a phase offset adder. The main component of the NCO is a 28-bit phase accumulator. Continuous time signals have a phase range of 0 to 2π. Outside this range of numbers, the sinusoid functions repeat themselves in a periodic manner. The digital implementation is no different. The accumulator simply scales the range of phase numbers into a multibit digital word. The phase accumulator in the AD9833 is implemented with 28 bits. Therefore, in the AD9833, 2π = 228. Likewise, the ΔPhase term is scaled into this range of numbers:
0 < ΔPhase < 228 − 1
With these substitutions, the previous equation becomes
f = ΔPhase × fMCLK∕228
where 0 < ΔPhase < 228 − 1.
The input to the phase accumulator can be selected from either the FREQ0 register or the FREQ1 register and is controlled by the FSELECT bit. NCOs inherently generate continuous phase signals, thus avoiding any output discontinuity when switching between frequencies.
Following the NCO, a phase offset can be added to perform phase modulation using the 12-bit phase registers. The contents of one of these phase registers are added to the most significant bits of the NCO. The AD9833 has two phase registers; their resolution is 2π/4096.
SIN ROM
To make the output from the NCO useful, it must be converted from phase information into a sinusoidal value. Because phase information maps directly into amplitude, the SIN ROM uses the digital phase information as an address to a lookup table and converts the phase information into amplitude. Although the NCO contains a 28-bit phase accumulator, the output of the NCO is truncated to 12 bits. Using the full resolution of the phase accumulator is impractical and unnecessary, because this would require a lookup table of 228 entries. It is necessary only to have sufficient phase resolution such that the errors due to truncation are smaller than the resolution of the 10-bit DAC. This requires that the SIN ROM have two bits of phase resolution more than the 10-bit DAC.
The SIN ROM is enabled using the mode bit (D1) in the control register (see Table 15).
DIGITAL-TO-ANALOG CONVERTER (DAC)
The AD9833 includes a high impedance, current source 10-bit DAC. The DAC receives the digital words from the SIN ROM and converts them into the corresponding analog voltages.
The DAC is configured for single-ended operation. An external load resistor is not required because the device has a 200 Ω resistor on board. The DAC generates an output voltage of typically 0.6 V p-p.
REGULATOR
VDD provides the power supply required for the analog section and the digital section of the AD9833. This supply can have a value of 2.3 V to 5.5 V.
The internal digital section of the AD9833 is operated at 2.5 V. An on-board regulator steps down the voltage applied at VDD to 2.5 V. When the applied voltage at the VDD pin of the AD9833 is less than or equal to 2.7 V, the CAP/2.5V and VDD pins should be tied together, thus bypassing the on-board regulator.
Data Sheet AD9833
Rev. E | Page 13 of 24
FUNCTIONAL DESCRIPTION
SERIAL INTERFACE
The AD9833 has a standard 3-wire serial interface that is compatible with the SPI, QSPI™, MICROWIRE®, and DSP interface standards.
Data is loaded into the device as a 16-bit word under the control of a serial clock input, SCLK. The timing diagram for this operation is given in .
The FSYNC input is a level-triggered input that acts as a frame synchronization and chip enable. Data can be transferred into the device only when FSYNC is low. To start the serial data transfer, FSYNC should be taken low, observing the minimum FSYNC-to-SCLK falling edge setup time, t7. After FSYNC goes low, serial data is shifted into the input shift register of the device on the falling edges of SCLK for 16 clock pulses. FSYNC may be taken high after the 16th falling edge of SCLK, observing the minimum SCLK falling edge to FSYNC rising edge time, t8. Alternatively, FSYNC can be kept low for a multiple of 16 SCLK pulses and then brought high at the end of the data transfer. In this way, a continuous stream of 16-bit words can be loaded while FSYNC is held low; FSYNC goes high only after the 16th SCLK falling edge of the last word loaded.
The SCLK can be continuous, or it can idle high or low between write operations. In either case, it must be high when FSYNC goes low (t11).
For an example of how to program the AD9833, see the AN-1070 Application Note on the Analog Devices, Inc., website.
POWERING UP THE AD9833
The flowchart in Figure 26 shows the operating routine for the AD9833. When the AD9833 is powered up, the part should be reset. This resets the appropriate internal registers to 0 to provide an analog output of midscale.
To avoid spurious DAC outputs during AD9833 initialization, the reset bit should be set to 1 until the part is ready to begin generating an output. A reset does not reset the phase, frequency, or control registers. These registers will contain invalid data and, therefore, should be set to known values by the user. The reset bit should then be set to 0 to begin generating an output. The data appears on the DAC output seven or eight MCLK cycles after the reset bit is set to 0.
LATENCY PERIOD
A latency period is associated with each asynchronous write operation in the AD9833. If a selected frequency or phase register is loaded with a new word, there is a delay of seven or eight MCLK cycles before the analog output changes. The delay can be seven or eight cycles, depending on the position of the MCLK rising edge when the data is loaded into the destination register.
CONTROL REGISTER
The AD9833 contains a 16-bit control register that allows the user to configure the operation of the AD9833. All control bits other than the mode bit are sampled on the internal falling edge of MCLK.
Table 6 describes the individual bits of the control register. The different functions and the various output options of the AD9833 are described in more detail in the Frequency and Phase Registers section.
To inform the AD9833 that the contents of the control register will be altered, D15 and D14 must be set to 0, as shown in Table 5.
Table 5. Control Register Bits
D15
D14
D13
D0
0
0
Control Bits
SINROMPHASEACCUMULATOR(28-BIT)AD9833(LOW POWER)10-BIT DAC0MUX1SLEEP12SLEEP1RESETMODE + OPBITENDIV2OPBITENVOUT1MUX0DIGITALOUTPUT(ENABLE)DIVIDEBY 2DB150DB140DB13B28DB12HLBDB11FSELECTDB10PSELECTDB90DB8RESETDB7SLEEP1DB6SLEEP12DB5OPBITENDB40DB3DIV2DB20DB1MODEDB0002704-024
Figure 24. Function of Control Bits
AD9833 Data Sheet
Rev. E | Page 14 of 24
Table 6. Description of Bits in the Control Register
Bit
Name
Function
D13
B28
Two write operations are required to load a complete word into either of the frequency registers. B28 = 1 allows a complete word to be loaded into a frequency register in two consecutive writes. The first write contains the 14 LSBs of the frequency word, and the next write contains the 14 MSBs. The first two bits of each 16-bit word define the frequency register to which the word is loaded and should, therefore, be the same for both of the consecutive writes. See Table 8 for the appropriate addresses. The write to the frequency register occurs after both words have been loaded; therefore, the register never holds an intermediate value. An example of a complete 28-bit write is shown in Table 9. When B28 = 0, the 28-bit frequency register operates as two 14-bit registers, one containing the 14 MSBs and the other containing the 14 LSBs. This means that the 14 MSBs of the frequency word can be altered independent of the 14 LSBs, and vice versa. To alter the 14 MSBs or the 14 LSBs, a single write is made to the appropriate frequency address. The control bit D12 (HLB) informs the AD9833 whether the bits to be altered are the 14 MSBs or 14 LSBs.
D12
HLB
This control bit allows the user to continuously load the MSBs or LSBs of a frequency register while ignoring the remaining 14 bits. This is useful if the complete 28-bit resolution is not required. HLB is used in conjunction with D13 (B28). This control bit indicates whether the 14 bits being loaded are being transferred to the 14 MSBs or 14 LSBs of the addressed frequency register. D13 (B28) must be set to 0 to be able to change the MSBs and LSBs of a frequency word separately. When D13 (B28) = 1, this control bit is ignored. HLB = 1 allows a write to the 14 MSBs of the addressed frequency register. HLB = 0 allows a write to the 14 LSBs of the addressed frequency register.
D11
FSELECT
The FSELECT bit defines whether the FREQ0 register or the FREQ1 register is used in the phase accumulator.
D10
PSELECT
The PSELECT bit defines whether the PHASE0 register or the PHASE1 register data is added to the output of the phase accumulator.
D9
Reserved
This bit should be set to 0.
D8
Reset
Reset = 1 resets internal registers to 0, which corresponds to an analog output of midscale. Reset = 0 disables reset. This function is explained further in Table 13.
D7
SLEEP1
When SLEEP1 = 1, the internal MCLK clock is disabled, and the DAC output remains at its present value because the NCO is no longer accumulating. When SLEEP1 = 0, MCLK is enabled. This function is explained further in Table 14.
D6
SLEEP12
SLEEP12 = 1 powers down the on-chip DAC. This is useful when the AD9833 is used to output the MSB of the DAC data.
SLEEP12 = 0 implies that the DAC is active. This function is explained further in Table 14.
D5
OPBITEN
The function of this bit, in association with D1 (mode), is to control what is output at the VOUT pin. This is explained further in Table 15. When OPBITEN = 1, the output of the DAC is no longer available at the VOUT pin. Instead, the MSB (or MSB/2) of the DAC data is connected to the VOUT pin. This is useful as a coarse clock source. The DIV2 bit controls whether it is the MSB or MSB/2 that is output. When OPBITEN = 0, the DAC is connected to VOUT. The mode bit determines whether it is a sinusoidal or a ramp output that is available.
D4
Reserved
This bit must be set to 0.
D3
DIV2
DIV2 is used in association with D5 (OPBITEN). This is explained further in Table 15. When DIV2 = 1, the MSB of the DAC data is passed directly to the VOUT pin. When DIV2 = 0, the MSB/2 of the DAC data is output at the VOUT pin.
D2
Reserved
This bit must be set to 0.
D1
Mode
This bit is used in association with OPBITEN (D5). The function of this bit is to control what is output at the VOUT pin when the on-chip DAC is connected to VOUT. This bit should be set to 0 if the control bit OPBITEN = 1. This is explained further in Table 15. When mode = 1, the SIN ROM is bypassed, resulting in a triangle output from the DAC. When mode = 0, the SIN ROM is used to convert the phase information into amplitude information, which results in a sinusoidal signal at the output.
D0
Reserved
This bit must be set to 0.
Data Sheet AD9833
Rev. E | Page 15 of 24 FREQUENCY AND PHASE REGISTERS
The AD9833 contains two frequency registers and two phase
registers, which are described in Table 7. Table 7. Frequency and Phase Registers
Register Size Description FREQ0 28 bits Frequency Register 0. When the FSELECT
bit = 0, this register defines the output
frequency as a fraction of the MCLK
frequency.
FREQ1 28 bits Frequency Register 1. When the FSELECT
bit = 1, this register defines the output
frequency as a fraction of the MCLK
frequency.
PHASE0 12 bits Phase Offset Register 0. When the PSELECT
bit = 0, the contents of this register are
added to the output of the phase
accumulator. PHASE1 12 bits Phase Offset Register 1. When the PSELECT
bit = 1, the contents of this register are
added to the output of the phase
accumulator. The analog output from the AD9833 is
fMCLK/228 × FREQREG
where FREQREG is the value loaded into the selected frequency
register. This signal is phase shifted by 2π/4096 × PHASEREG where PHASEREG is the value contained in the selected phase register. Consideration must be given to the relationship of the
selected output frequency and the reference clock frequency to avoid unwanted output anomalies. The flowchart in Figure 28 shows the routine for writing to the
frequency and phase registers of the AD9833. Writing to a Frequency Register
When writing to a frequency register, Bit D15 and Bit D14 give
the address of the frequency register.
Table 8. Frequency Register Bits
D15 D14 D13 D0
0 1 MSB 14 FREQ0 REG bits LSB
1 0 MSB 14 FREQ1 REG bits LSB
If the user wants to change the entire contents of a frequency
register, two consecutive writes to the same address must be
performed because the frequency registers are 28 bits wide. The
first write contains the 14 LSBs, and the second write contains the 14 MSBs. For this mode of operation, the B28 (D13) control
bit should be set to 1. An example of a 28-bit write is shown in Table 9. Table 9. Writing 0xFFFC000 to the FREQ0 Register SDATA Input Result of Input Word 0010 0000 0000 0000 Control word write (D15, D14 = 00), B28 (D13) = 1, HLB (D12) = X 0100 0000 0000 0000 FREQ0 register write
(D15, D14 = 01), 14 LSBs = 0x0000
0111 1111 1111 1111 FREQ0 register write
(D15, D14 = 01), 14 MSBs = 0x3FFF
In some applications, the user does not need to alter all 28 bits
of the frequency register. With coarse tuning, only the 14 MSBs
are altered, while with fine tuning, only the 14 LSBs are altered.
By setting the B28 (D13) control bit to 0, the 28-bit frequency
register operates as two, 14-bit registers, one containing the 14 MSBs
and the other containing the 14 LSBs. This means that the 14 MSBs of the frequency word can be altered independent of the 14 LSBs,
and vice versa. Bit HLB (D12) in the control register identifies
which 14 bits are being altered. Examples of this are shown in
Table 10 and Table 11. Table 10. Writing 0x3FFF to the 14 LSBs of the FREQ1 Register SDATA Input Result of Input Word 0000 0000 0000 0000 Control word write (D15, D14 = 00), B28 (D13) = 0; HLB (D12) = 0, that is, LSBs
1011 1111 1111 1111 FREQ1 REG write (D15, D14 = 10), 14 LSBs = 0x3FFF
Table 11. Writing 0x00FF to the 14 MSBs of the FREQ0 Register SDATA Input Result of Input Word 0001 0000 0000 0000 Control word write (D15, D14 = 00),
B28 (D13) = 0, HLB (D12) = 1, that is, MSBs 0100 0000 1111 1111 FREQ0 REG write (D15, D14 = 01), 14 MSBs = 0x00FF
Writing to a Phase Register
When writing to a phase register, Bit D15 and Bit D14 are set to 11.
Bit D13 identifies which phase register is being loaded. Table 12. Phase Register Bits
D15 D14 D13 D12 D11 D0
1 1 0 X MSB 12 PHASE0 bits LSB
1 1 1 X MSB 12 PHASE1 bits LSB
AD9833 Data Sheet
Rev. E | Page 16 of 24
RESET FUNCTION
The reset function resets appropriate internal registers to 0 to provide an analog output of midscale. Reset does not reset the phase, frequency, or control registers. When the AD9833 is powered up, the part should be reset. To reset the AD9833, set the reset bit to 1. To take the part out of reset, set the bit to 0. A signal appears at the DAC to output eight MCLK cycles after reset is set to 0.
Table 13. Applying the Reset Function
Reset Bit
Result
0
No reset applied
1
Internal registers reset
SLEEP FUNCTION
Sections of the AD9833 that are not in use can be powered down to minimize power consumption. This is done using the sleep function. The parts of the chip that can be powered down are the internal clock and the DAC. The bits required for the sleep function are outlined in Table 14.
Table 14. Applying the Sleep Function
SLEEP1 Bit
SLEEP12 Bit
Result
0
0
No power-down
0
1
DAC powered down
1
0
Internal clock disabled
1
1
Both the DAC powered down and the internal clock disabled
DAC Powered Down
This is useful when the AD9833 is used to output the MSB of the DAC data only. In this case, the DAC is not required; therefore, it can be powered down to reduce power consumption.
Internal Clock Disabled
When the internal clock of the AD9833 is disabled, the DAC output remains at its present value because the NCO is no longer accumulating. New frequency, phase, and control words can be written to the part when the SLEEP1 control bit is active. The synchronizing clock is still active, which means that the selected frequency and phase registers can also be changed using the control bits. Setting the SLEEP1 bit to 0 enables the MCLK. Any changes made to the registers while SLEEP1 is active will be seen at the output after a latency period.
VOUT PIN
The AD9833 offers a variety of outputs from the chip, all of which are available from the VOUT pin. The choice of outputs is the MSB of the DAC data, a sinusoidal output, or a triangle output.
The OPBITEN (D5) and mode (D1) bits in the control register are used to decide which output is available from the AD9833.
MSB of the DAC Data
The MSB of the DAC data can be output from the AD9833. By setting the OPBITEN (D5) control bit to 1, the MSB of the DAC data is available at the VOUT pin. This is useful as a coarse clock source. This square wave can also be divided by 2 before being output. The DIV2 (D3) bit in the control register controls the frequency of this output from the VOUT pin.
Sinusoidal Output
The SIN ROM is used to convert the phase information from the frequency and phase registers into amplitude information that results in a sinusoidal signal at the output. To have a sinusoidal output from the VOUT pin, set the mode (D1) bit to 0 and the OPBITEN (D5) bit to 0.
Triangle Output
The SIN ROM can be bypassed so that the truncated digital output from the NCO is sent to the DAC. In this case, the output is no longer sinusoidal. The DAC will produce a 10-bit linear triangular function. To have a triangle output from the VOUT pin, set the mode (D1) bit = 1.
Note that the SLEEP12 bit must be 0 (that is, the DAC is enabled) when using this pin.
Table 15. Outputs from the VOUT Pin
OPBITEN Bit
Mode Bit
DIV2 Bit
VOUT Pin
0
0
X1
Sinusoid
0
1
X1
Triangle
1
0
0
DAC data MSB/2
1
0
1
DAC data MSB
1
1
X1
Reserved
1 X = don’t care.
VOUT MINVOUT MAX2π4π6π02704-025
Figure 25. Triangle Output
Data Sheet AD9833
Rev. E | Page 17 of 24
APPLICATIONS INFORMATION
Because of the various output options available from the part, the AD9833 can be configured to suit a wide variety of applications.
One of the areas where the AD9833 is suitable is in modulation applications. The part can be used to perform simple modulation, such as FSK. More complex modulation schemes, such as GMSK and QPSK, can also be implemented using the AD9833.
In an FSK application, the two frequency registers of the AD9833 are loaded with different values. One frequency represents the space frequency, while the other represents the mark frequency. Using the FSELECT bit in the control register of the AD9833, the user can modulate the carrier frequency between the two values.
The AD9833 has two phase registers, which enables the part to perform PSK. With phase-shift keying, the carrier frequency is phase shifted, the phase being altered by an amount that is related to the bit stream being input to the modulator.
The AD9833 is also suitable for signal generator applications. Because the MSB of the DAC data is available at the VOUT pin, the device can be used to generate a square wave.
With its low current consumption, the part is suitable for applications in which it can be used as a local oscillator.
GROUNDING AND LAYOUT
The printed circuit board (PCB) that houses the AD9833 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes because it gives the best shielding. Digital and analog ground planes should be joined in one place only. If the AD9833 is the only device requiring an AGND-to-DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD9833. If the AD9833 is in a system where multiple devices require AGND-to-DGND connections, the connection should be made at one point only, a star ground point that should be established as close as possible to the AD9833.
Avoid running digital lines under the device as these couple noise onto the die. The analog ground plane should be allowed to run under the AD9833 to avoid noise coupling. The power supply lines to the AD9833 should use as large a track as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board.
Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but it is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, and signals are placed on the other side.
Good decoupling is important. The AD9833 should have supply bypassing of 0.1 μF ceramic capacitors in parallel with 10 μF tantalum capacitors. To achieve the best performance from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device.
AD9833 Data Sheet
Rev. E | Page 18 of 24
DATA WRITE(SEE FIGURE 28)SELECT DATASOURCESWAIT 7/8 MCLKCYCLESVOUT = VREF × 18 × RLOAD/ RSET× (1 + (SIN (2π (FREQREG ×fMCLK×t/228 + PHASEREG / 212))))DAC OUTPUTCHANGE PHASE?CHANGE FREQUENCY?CHANGE DAC OUTPUTFROM SIN TO RAMP?CHANGE OUTPUT TOA DIGITAL SIGNAL?CHANGEPSELECT?CHANGE PHASEREGISTER?CHANGEFSELECT?CHANGE FREQUENCYREGISTER?CONTROL REGISTERWRITE(SEE TABLE 6)INITIALIZATION(SEE FIGURE 27 BELOW)NONONONOYESNOYESYESNOYESYESYESYESYES02704-026
Figure 26. Flowchart for AD9833 Initialization and Operation
INITIALIZATIONAPPLY RESET(CONTROL REGISTER WRITE)RESET = 1WRITE TO FREQUENCY AND PHASE REGISTERSFREQ0 REG =fOUT0/fMCLK × 228FREQ1 REG =fOUT1/fMCLK × 228PHASE0 AND PHASE1 REG = (PHASESHIFT × 212)/2π(SEE FIGURE 28)SET RESET = 0SELECT FREQUENCY REGISTERSSELECT PHASE REGISTERS(CONTROL REGISTER WRITE)RESET BIT = 0FSELECT = SELECTED FREQUENCY REGISTERPSELECT = SELECTED PHASE REGISTER02704-027
Figure 27. Flowchart for Initialization
Data Sheet AD9833
Rev. E | Page 19 of 24
NOWRITE 14MSBs OR LSBsTO A FREQUENCY REGISTER?(CONTROL REGISTER WRITE)B28 (D13) = 0HLB (D12) = 0/1WRITE A 16-BIT WORD(SEE TABLE 10 AND TABLE 11FOR EXAMPLES)WRITE 14MSBs OR LSBsTO AFREQUENCY REGISTER?WRITE TO PHASEREGISTER?(16-BIT WRITE)D15, D14 = 11 D13 = 0/1 (CHOOSE THE PHASE REGISTER) D12 = XD11 ... D0 = PHASE DATAWRITE TO ANOTHERPHASE REGISTER?YESWRITE ANOTHER FULL28-BIT WORD TO AFREQUENCY REGISTER?WRITE TWO CONSECUTIVE16-BIT WORDS(SEE TABLE 9 FOR EXAMPLE)(CONTROL REGISTER WRITE)B28 (D13) = 1WRITE A FULL 28-BIT WORDTO A FREQUENCY REGISTER?DATA WRITENOYESYESNOYESONONYESYES02704-028
Figure 28. Flowchart for Data Writes
AD9833 Data Sheet
Rev. E | Page 20 of 24
INTERFACING TO MICROPROCESSORS
The AD9833 has a standard serial interface that allows the part to interface directly with several microprocessors. The device uses an external serial clock to write the data or control information into the device. The serial clock can have a frequency of 40 MHz maximum. The serial clock can be continuous, or it can idle high or low between write operations. When data or control informa-tion is written to the AD9833, FSYNC is taken low and is held low until the 16 bits of data are written into the AD9833. The FSYNC signal frames the 16 bits of information that are loaded into the AD9833.
AD9833 TO 68HC11/68L11 INTERFACE
Figure 29 shows the serial interface between the AD9833 and the 68HC11/68L11 microcontroller. The microcontroller is con-figured as the master by setting the MSTR bit in the SPCR to 1. This setting provides a serial clock on SCK; the MOSI output drives the serial data line SDATA. Because the microcontroller does not have a dedicated frame sync pin, the FSYNC signal is derived from a port line (PC7). The setup conditions for correct operation of the interface are as follows:
• SCK idles high between write operations (CPOL = 0)
• Data is valid on the SCK falling edge (CPHA = 1)
When data is being transmitted to the AD9833, the FSYNC line is taken low (PC7). Serial data from the 68HC11/68L11 is trans-mitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data into the AD9833, PC7 is held low after the first eight bits are transferred, and a second serial write operation is performed to the AD9833. Only after the second eight bits are transferred should FSYNC be taken high again.
AD9833FSYNCSDATASCLK68HC11/68L11PC7MOSISCK02704-030
Figure 29. 68HC11/68L11 to AD9833 Interface
AD9833 TO 80C51/80L51 INTERFACE
Figure 30 shows the serial interface between the AD9833 and the 80C51/80L51 microcontroller. The microcontroller is oper-ated in Mode 0 so that TxD of the 80C51/80L51 drives SCLK of the AD9833, and RxD drives the serial data line SDATA. The FSYNC signal is derived from a bit programmable pin on the port (P3.3 is shown in Figure 30).
When data is to be transmitted to the AD9833, P3.3 is taken low. The 80C51/80L51 transmits data in 8-bit bytes, thus only eight falling SCLK edges occur in each cycle. To load the remaining eight bits to the AD9833, P3.3 is held low after the first eight bits are transmitted, and a second write operation is initiated to transmit the second byte of data. P3.3 is taken high following the completion of the second write operation. SCLK should idle high between the two write operations.
The 80C51/80L51 outputs the serial data in a format that has the LSB first. The AD9833 accepts the MSB first (the four MSBs are the control information, the next four bits are the address, and the eight LSBs contain the data when writing to a destination register). Therefore, the transmit routine of the 80C51/80L51 must take this into account and rearrange the bits so that the MSB is output first.
AD9833FSYNCSDATASCLK80C51/80L51P3.3RxDTxD02704-031
Figure 30. 80C51/80L51 to AD9833 Interface
AD9833 TO DSP56002 INTERFACE
Figure 31 shows the interface between the AD9833 and the DSP56002. The DSP56002 is configured for normal mode asyn-chronous operation with a gated internal clock (SYN = 0, GCK = 1, SCKD = 1). The frame sync pin is generated internally (SC2 = 1), the transfers are 16 bits wide (WL1 = 1, WL0 = 0), and the frame sync signal frames the 16 bits (FSL = 0). The frame sync signal is available on the SC2 pin, but it must be inverted before it is applied to the AD9833. The interface to the DSP56000/DSP56001 is similar to that of the DSP56002.
AD9833FSYNCSDATASCLKDSP56002SC2STDSCK02704-032
Figure 31. DSP56002 to AD9833 Interface
Data Sheet AD9833
Rev. E | Page 21 of 24
EVALUATION BOARD
The AD9833 evaluation board allows designers to evaluate the high performance AD9833 DDS modulator with a minimum of effort.
SYSTEM DEMONSTRATION PLATFORM
The system demonstration platform (SDP) is a hardware and software evaluation tool for use in conjunction with product evaluation boards. The SDP board is based on the Blackfin® ADSP-BF527 processor with USB connectivity to the PC through a USB 2.0 high speed port. For more information about the SDP board, see the SDP board product page.
Note that the SDP board is sold separately from the AD9833 evaluation board.
AD9833 TO SPORT INTERFACE
The Analog Devices SDP board has a SPORT serial port that is used to control the serial inputs to the AD9833. The connections are shown in Figure 32.
AD9833FSYNCSDATASCLK02704-034SPORT_TFSSPORT_TSCLKSPORT_DTOADSP-BF527
Figure 32. SDP to AD9833 Interface
EVALUATION KIT
The DDS evaluation kit includes a populated, tested AD9833 printed circuit board (PCB). The schematics of the evaluation board are shown in Figure 34 and Figure 35.
The software provided in the evaluation kit allows the user to easily program the AD9833 (see Figure 33). The evaluation soft-ware runs on any IBM-compatible PC with Microsoft® Windows® software installed (including Windows 7). The software is com-patible with both 32-bit and 64-bit operating systems.
More information about the evaluation software is available on the software CD and on the AD9833 product page.
02704-035
Figure 33. AD9833 Evaluation Software Interface
CRYSTAL OSCILLATOR VS. EXTERNAL CLOCK
The AD9833 can operate with master clocks up to 25 MHz. A 25 MHz oscillator is included on the evaluation board. This oscillator can be removed and, if required, an external CMOS clock can be connected to the part. Options for the general oscillator include the following:
• AEL 301-Series oscillators, AEL Crystals
• SG-310SCN oscillators, Epson Electronics
POWER SUPPLY
Power to the AD9833 evaluation board can be provided from the USB connector or externally through pin connections. The power leads should be twisted to reduce ground loops.
AD9833 Data Sheet
Rev. E | Page 22 of 24
EVALUATION BOARD SCHEMATICS
02704-036
Figure 34. Evaluation Board Schematic
02704-037
Figure 35. SDP Connector Schematic
Data Sheet AD9833
Rev. E | Page 23 of 24
EVALUATION BOARD LAYOUT
02704-038
Figure 36. AD9833 Evaluation Board Component Side
02704-039
Figure 37. AD9833 Evaluation Board Silkscreen
02704-040
Figure 38. AD9833 Evaluation Board Solder Side
AD9833 Data Sheet
Rev. E | Page 24 of 24 OUTLINE DIMENSIONS
COMPLIANTTOJEDECSTANDARDSMO-187-BA
091709-A
6°
0°
0.70
0.55
0.40
5
10
1
6
0.50BSC
0.30
0.15
1.10MAX
3.10
3.00
2.90
COPLANARITY
0.10
0.23
0.13
3.10
3.00
2.90
5.15
4.90
4.65
PIN 1
IDENTIFIER
15°MAX 0.95
0.85
0.75
0.15
0.05
Figure 39. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2, 3 Temperature Range Package Description Package Option Branding
AD9833BRM −40°C to +105°C 10-Lead MSOP RM-10 DJB
AD9833BRM-REEL −40°C to +105°C 10-Lead MSOP RM-10 DJB
AD9833BRM-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 DJB
AD9833BRMZ −40°C to +105°C 10-Lead MSOP RM-10 D68
AD9833BRMZ-REEL −40°C to +105°C 10-Lead MSOP RM-10 D68
AD9833BRMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D68
AD9833WBRMZ-REEL −40°C to +105°C 10-Lead MSOP RM-10 D68
EVAL-AD9833SDZ Evaluation Board
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 The evaluation board for the AD9833 requires the system demonstration platform (SDP) board, which is sold separately. AUTOMOTIVE PRODUCTS
The AD9833WBRMZ-REEL model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore,
designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for
use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and
to obtain the specific Automotive Reliability reports for these models. ©2003–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02704-0-9/12(E)
Triple-Channel Digital Isolators
Data Sheet ADuM1300/ADuM1301
Rev. J Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES Qualified for automotive applications Low power operation 5 V operation
1.2 mA per channel maximum at 0 Mbps to 2 Mbps 3.5 mA per channel maximum at 10 Mbps 32 mA per channel maximum at 90 Mbps 3 V operation
0.8 mA per channel maximum at 0 Mbps to 2 Mbps 2.2 mA per channel maximum at 10 Mbps 20 mA per channel maximum at 90 Mbps Bidirectional communication 3 V/5 V level translation
High temperature operation: 125°C High data rate: dc to 90 Mbps (NRZ)
Precise timing characteristics 2 ns maximum pulse width distortion
2 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Output enable function
16-lead SOIC wide body package
RoHS-compliant models available
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 560 V peak TÜV approval: IEC/EN/UL/CSA 61010-1 APPLICATIONS
General-purpose multichannel isolation
SPI interface/data converter isolation
RS-232/RS-422/RS-485 transceivers Industrial field bus isolation
Automotive systems GENERAL DESCRIPTION
The ADuM130x1 are triple-channel digital isolators based on the
Analog Devices, Inc., iCoupler® technology. Combining high speed CMOS and monolithic transformer technology, these isolation components provide outstanding performance
characteristics superior to alternatives, such as optocouplers. By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding
uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the
simple iCoupler digital interfaces and stable performance
characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler devices consume one-tenth to one-sixth
of the power of optocouplers at comparable signal data rates. The ADuM130x isolators provide three independent isolation
channels in a variety of channel configurations and data rates
(see the Ordering Guide). Both models operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier. In addition, the ADuM130x provide low pulse width distortion (<2 ns for CRW grade) and tight channel-to-channel matching (<2 ns for CRW grade). Unlike other optocoupler alternatives,
the ADuM130x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and when power is not applied to one of the supplies. 1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.
FUNCTIONAL BLOCK DIAGRAMS
Figure 1. ADuM1300 Functional Block Diagram
Figure 2. ADuM1301 Functional Block Diagram
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
VDD1
GND1
VIA
VIB
VIC
NC
NC
GND1
VDD2
GND2
VOA
VOB
VOC
NC
VE2
GND2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
03787-001
DECODE ENCODE
ENCODE DECODE
ENCODE DECODE
VDD1
GND1
VIA
VIB
VOC
NC
VE1
GND1
VDD2
GND2
VOA
VOB
VIC
NC
VE2
GND2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
03787-002
ADuM1300/ADuM1301 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
Electrical Characteristics—5 V, 105°C Operation ................... 4
Electrical Characteristics—3 V, 105°C Operation ................... 6
Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V, 105°C Operation ........................................................................... 8
Electrical Characteristics—5 V, 125°C Operation ................. 11
Electrical Characteristics—3 V, 125°C Operation ................. 13
Electrical Characteristics—Mixed 5 V/3 V, 125°C Operation ... 15
Electrical Characteristics—Mixed 3 V/5 V 125°C Operation ... 17
Package Characteristics ............................................................. 19
Regulatory Information ............................................................. 19
Insulation and Safety-Related Specifications .......................... 19
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation Characteristics ......................................................... 20
Recommended Operating Conditions .................................... 20
Absolute Maximum Ratings ......................................................... 21
ESD Caution................................................................................ 21
Pin Configurations and Function Descriptions ......................... 22
Typical Performance Characteristics ........................................... 23
Applications Information .............................................................. 25
PC Board Layout ........................................................................ 25
Propagation Delay-Related Parameters ................................... 25
DC Correctness and Magnetic Field Immunity .......................... 25
Power Consumption .................................................................. 26
Insulation Lifetime ..................................................................... 27
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
Automotive Products ................................................................. 29 Rev. J | Page 2 of 32
Data Sheet ADuM1300/ADuM1301
REVISION HISTORY
4/14—Rev. I to Rev. J
Change to Table 9 ............................................................................ 19
3/12—Rev. H to Rev. I
Created Hyperlink for Safety and Regulatory Approvals Entry in Features Section ................................................................. 1 Change to PC Board Layout Section ............................................ 25 Updated Outline Dimensions ........................................................ 28 Moved Automotive Products Section ........................................... 28
5/08—Rev. G to Rev. H
Added ADuM1300W and ADuM1301W Parts ............. Universal Changes to Features List ................................................................... 1 Added Table 4 .................................................................................. 11 Added Table 5 .................................................................................. 13 Added Table 6 .................................................................................. 15 Added Table 7 .................................................................................. 17 Changes to Table 12 ........................................................................ 20 Changes to Table 13 ........................................................................ 21 Added Automotive Products Section ........................................... 27 Changes to Ordering Guide ........................................................... 28
11/07—Rev. F to Rev. G
Changes to Note 1 and Figure 2 ...................................................... 1 Added ADuM130xARW Change vs. Temperature Parameter ... 3 Added ADuM130xARW Change vs. Temperature Parameter ... 5 Added ADuM130xARW Change vs. Temperature Parameter ... 8 Changes to Figure 14 ...................................................................... 16
6/07—Rev. E to Rev. F
Updated VDE Certification Throughout ....................................... 1 Changes to Features, Note 1, Figure 1, and Figure 2 .................... 1 Changes to Regulatory Information Section ............................... 10 Added Table 10 ................................................................................ 12 Added Insulation Lifetime Section ............................................... 17 Updated Outline Dimensions ........................................................ 19 Changes to Ordering Guide ........................................................... 19
2/06—Rev. D to Rev. E
Updated Format ................................................................. Universal Added TÜV Approval ....................................................... Universal Changes to Figure 2 .......................................................................... 1
5/05—Rev. C to Rev. D
Changes to Format ............................................................. Universal Changes to Figure 2 .......................................................................... 1 Changes to Table 6 .......................................................................... 10 Changes to Ordering Guide ........................................................... 18
6/04—Rev. B to Rev. C
Changes to Format ............................................................. Universal Changes to Features .......................................................................... 1 Changes to Electrical Characteristics—5 V Operation ................ 3 Changes to Electrical Characteristics—3 V Operation ................ 5 Changes to Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V Operation ............................................................................ 7 Changes to Ordering Guide ........................................................... 18
5/04—Rev. A to Rev. B
Changes to the Format ...................................................... Universal Changes to the Features.................................................................... 1 Changes to Table 7 and Table 8 ..................................................... 14 Changes to Table 9 .......................................................................... 15 Changes to the DC Correctness and Magnetic Field Immunity Section .............................................................................................. 19 Changes to the Power Consumption Section .............................. 20 Changes to the Ordering Guide .................................................... 21
9/03—Rev. 0 to Rev. A
Edits to Regulatory Information ................................................... 13 Edits to Absolute Maximum Ratings ............................................ 15 Deleted the Package Branding Information ................................ 16
9/03—Revision 0: Initial Version
Rev. J | Page 3 of 32
ADuM1300/ADuM1301 Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V, 105°C OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. These specifications do not apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.50
0.53
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.19
0.24
mA
ADuM1300 Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
1.6
2.5
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.7
1.0
mA
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
IDD1 (10)
6.5
8.1
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.9
2.5
mA
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
IDD1 (90)
57
77
mA
45 MHz logic signal freq.
VDD2 Supply Current
IDD2 (90)
16
18
mA
45 MHz logic signal freq.
ADuM1301 Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
1.3
2.1
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
1.0
1.4
mA
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
IDD1 (10)
5.0
6.2
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
3.4
4.2
mA
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
IDD1 (90)
43
57
mA
45 MHz logic signal freq.
VDD2 Supply Current
IDD2 (90)
29
37
mA
45 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC, IE1, IE2
−10
+0.01
+10
μA
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold
VIH, VEH
2.0
V
Logic Low Input Threshold
VIL, VEL
0.8
V
Logic High Output Voltages
VOAH, VOBH, VOCH
(VDD1 or VDD2) − 0.1
5.0
V
IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.4
4.8
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL, VOCL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xARW
Minimum Pulse Width2
PW
1000
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
1
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
50
65
100
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
11
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
50
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
CL = 15 pF, CMOS signal levels Rev. J | Page 4 of 32
Data Sheet ADuM1300/ADuM1301
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
ADuM130xBRW
Minimum Pulse Width2
PW
100
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
10
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
20
32
50
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
15
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
3
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
ADuM130xCRW
Minimum Pulse Width2
PW
8.3
11.1
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
90
120
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
18
27
32
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
0.5
2
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
3
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
10
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
2
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay (High/Low to High Impedance)
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High Impedance to High/Low)
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
2.5
ns
CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V
Common-Mode Transient Immunity at Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
1.2
Mbps
Input Dynamic Supply Current per Channel8
IDDI (D)
0.19
mA/Mbps
Output Dynamic Supply Current per Channel8
IDDO (D)
0.05
mA/Mbps
1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. J | Page 5 of 32
ADuM1300/ADuM1301 Data Sheet
ELECTRICAL CHARACTERISTICS—3 V, 105°C OPERATION
All voltages are relative to their respective ground. 2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. These specifications do not apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.26
0.31
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.11
0.15
mA
ADuM1300 Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.9
1.7
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.4
0.7
mA
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
IDD1 (10)
3.4
4.9
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.1
1.6
mA
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
IDD1 (90)
31
48
mA
45 MHz logic signal freq.
VDD2 Supply Current
IDD2 (90)
8
13
mA
45 MHz logic signal freq.
ADuM1301 Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.7
1.4
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.6
0.9
mA
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
IDD1 (10)
2.6
3.7
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.8
2.5
mA
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
IDD1 (90)
24
36
mA
45 MHz logic signal freq.
VDD2 Supply Current
IDD2 (90)
16
23
mA
45 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC, IE1, IE2
−10
+0.01
+10
μA
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold
VIH, VEH
1.6
V
Logic Low Input Threshold
VIL, VEL
0.4
V
Logic High Output Voltages
VOAH, VOBH, VOCH
(VDD1 or VDD2) − 0.1
3.0
V
IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.4
2.8
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL, VOCL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xARW
Minimum Pulse Width2
PW
1000
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
1
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
50
75
100
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
11
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
50
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
CL = 15 pF, CMOS signal levels Rev. J | Page 6 of 32
Data Sheet ADuM1300/ADuM1301
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
ADuM130xBRW
Minimum Pulse Width2
PW
100
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
10
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
20
38
50
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
26
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
3
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
ADuM130xCRW
Minimum Pulse Width2
PW
8.3
11.1
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
90
120
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
20
34
45
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
0.5
2
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
3
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
16
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
2
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay (High/Low to High Impedance)
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High Impedance to High/Low)
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
3
ns
CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V
Common-Mode Transient Immunity at Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
1.1
Mbps
Input Dynamic Supply Current per Channel8
IDDI (D)
0.10
mA/Mbps
Output Dynamic Supply Current per Channel8
IDDO (D)
0.03
mA/Mbps
1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.
Rev. J | Page 7 of 32
ADuM1300/ADuM1301 Data Sheet
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V, 105°C OPERATION
All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V or VDD1 = 5 V, VDD2 = 3.0 V. These specifica-tions do not apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
5 V/3 V Operation
0.50
0.53
mA
3 V/5 V Operation
0.26
0.31
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
5 V/3 V Operation
0.11
0.15
mA
3 V/5 V Operation
0.19
0.24
mA
ADuM1300 Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
5 V/3 V Operation
1.6
2.5
mA
DC to 1 MHz logic signal freq.
3 V/5 V Operation
0.9
1.7
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
5 V/3 V Operation
0.4
0.7
mA
DC to 1 MHz logic signal freq.
3 V/5 V Operation
0.7
1.0
mA
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
IDD1 (10)
5 V/3 V Operation
6.5
8.1
mA
5 MHz logic signal freq.
3 V/5 V Operation
3.4
4.9
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
5 V/3 V Operation
1.1
1.6
mA
5 MHz logic signal freq.
3 V/5 V Operation
1.9
2.5
mA
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
IDD1 (90)
5 V/3 V Operation
57
77
mA
45 MHz logic signal freq.
3 V/5 V Operation
31
48
mA
45 MHz logic signal freq.
VDD2 Supply Current
IDD2 (90)
5 V/3 V Operation
8
13
mA
45 MHz logic signal freq.
3 V/5 V Operation
16
18
mA
45 MHz logic signal freq.
ADuM1301 Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
5 V/3 V Operation
1.3
2.1
mA
DC to 1 MHz logic signal freq.
3 V/5 V Operation
0.7
1.4
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
5 V/3 V Operation
0.6
0.9
mA
DC to 1 MHz logic signal freq.
3 V/5 V Operation
1.0
1.4
mA
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
IDD1 (10)
5 V/3 V Operation
5.0
6.2
mA
5 MHz logic signal freq.
3 V/5 V Operation
2.6
3.7
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
5 V/3 V Operation
1.8
2.5
mA
5 MHz logic signal freq.
3 V/5 V Operation
3.4
4.2
mA
5 MHz logic signal freq. Rev. J | Page 8 of 32
Data Sheet ADuM1300/ADuM1301
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
90 Mbps (CRW Grade Only)
VDD1 Supply Current
IDD1 (90)
5 V/3 V Operation
43
57
mA
45 MHz logic signal freq.
3 V/5 V Operation
24
36
mA
45 MHz logic signal freq.
VDD2 Supply Current
IDD2 (90)
5 V/3 V Operation
16
23
mA
45 MHz logic signal freq.
3 V/5 V Operation
29
37
mA
45 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC, IE1, IE2
−10
+0.01
+10
μA
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold
VIH, VEH
5 V/3 V Operation
2.0
V
3 V/5 V Operation
1.6
V
Logic Low Input Threshold
VIL, VEL
5 V/3 V Operation
0.8
V
3 V/5 V Operation
0.4
V
Logic High Output Voltages
VOAH, VOBH, VOCH
(VDD1 or VDD2) − 0.1
(VDD1 or VDD2)
V
IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.4
(VDD1 or VDD2) − 0.2
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL, VOCL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xARW
Minimum Pulse Width2
PW
1000
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
1
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
50
70
100
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
11
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
50
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
CL = 15 pF, CMOS signal levels
ADuM130xBRW
Minimum Pulse Width2
PW
100
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
10
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
15
35
50
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
6
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
3
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
22
ns
CL = 15 pF, CMOS signal levels
ADuM130xCRW
Minimum Pulse Width2
PW
8.3
11.1
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
90
120
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
20
30
40
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
0.5
2
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
3
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
14
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
2
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels Rev. J | Page 9 of 32
ADuM1300/ADuM1301 Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
For All Models
Output Disable Propagation Delay (High/Low to High Impedance)
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High Impedance to High/Low)
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
CL = 15 pF, CMOS signal levels
5 V/3 V Operation
3.0
ns
3 V/5 V Operation
2.5
ns
Common-Mode Transient Immunity at Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V
Common-Mode Transient Immunity at Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
5 V/3 V Operation
1.2
Mbps
3 V/5 V Operation
1.1
Mbps
Input Dynamic Supply Current per Channel8
IDDI (D)
5 V/3 V Operation
0.19
mA/Mbps
3 V/5 V Operation
0.10
mA/Mbps
Output Dynamic Supply Current per Channel8
IDDO (D)
5 V/3 V Operation
0.03
mA/Mbps
3 V/5 V Operation
0.05
mA/Mbps
1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.
Rev. J | Page 10 of 32
Data Sheet ADuM1300/ADuM1301
ELECTRICAL CHARACTERISTICS—5 V, 125°C OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. These specifications apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.50
0.53
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.19
0.24
mA
ADuM1300W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
1.6
2.5
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.7
1.0
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
IDD1 (10)
6.5
8.1
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.9
2.5
mA
5 MHz logic signal freq.
ADuM1301W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
1.3
2.1
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
1.0
1.4
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
IDD1 (10)
5.0
6.2
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
3.4
4.2
mA
5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC, IE1, IE2
−10
+0.01
+10
μA
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold
VIH, VEH
2.0
V
Logic Low Input Threshold
VIL, VEL
0.8
V
Logic High Output Voltages
VOAH, VOBH, VOCH
VDD1, VDD2 − 0.1
5.0
V
IOx = −20 μA, VIx = VIxH
VDD1, VDD2 − 0.4
4.8
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL, VOCL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xWSRWZ
Minimum Pulse Width2
PW
1000
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
1
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
50
65
100
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
50
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
CL = 15 pF, CMOS signal levels
ADuM130xWTRWZ
Minimum Pulse Width2
PW
100
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
10
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
18
27
32
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
15
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
3
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels Rev. J | Page 11 of 32
ADuM1300/ADuM1301 Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
For All Models
Output Disable Propagation Delay (High/Low to High Impedance)
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High Impedance to High/Low)
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
2.5
ns
CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1/VDD2, VCM = 1000 V, transient magnitude = 800 V
Common-Mode Transient Immunity at Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
1.2
Mbps
Input Dynamic Supply Current per Channel8
IDDI (D)
0.19
mA/Mbps
Output Dynamic Supply Current per Channel8
IDDO (D)
0.05
mA/Mbps
1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADUM1300W/ADUM1301W channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. J | Page 12 of 32
Data Sheet ADuM1300/ADuM1301
ELECTRICAL CHARACTERISTICS—3 V, 125°C OPERATION
All voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. These specifications apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 5.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.26
0.31
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.11
0.15
mA
ADuM1300W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.9
1.7
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.4
0.7
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
IDD1 (10)
3.4
4.9
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.1
1.6
mA
5 MHz logic signal freq.
ADuM1301W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.7
1.4
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.6
0.9
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
IDD1 (10)
2.6
3.7
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.8
2.5
mA
5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC, IE1, IE2
−10
+0.01
+10
μA
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold
VIH, VEH
1.6
V
Logic Low Input Threshold
VIL, VEL
0.4
V
Logic High Output Voltages
VOAH, VOBH, VOCH
VDD1, VDD2 − 0.1
3.0
V
IOx = −20 μA, VIx = VIxH
VDD1, VDD2 − 0.4
2.8
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL, VOCL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xWSRWZ
Minimum Pulse Width2
PW
1000
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
1
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
50
75
100
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
50
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
CL = 15 pF, CMOS signal levels
ADuM130xWTRWZ
Minimum Pulse Width2
PW
100
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
10
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
20
34
45
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
26
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
3
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels Rev. J | Page 13 of 32
ADuM1300/ADuM1301 Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
For All Models
Output Disable Propagation Delay (High/Low to High Impedance)
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High Impedance to High/Low)
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
3
ns
CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1/VDD2, VCM = 1000 V, transient magnitude = 800 V
Common-Mode Transient Immunity at Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
1.1
Mbps
Input Dynamic Supply Current per Channel8
IDDI (D)
0.10
mA/Mbps
Output Dynamic Supply Current per Channel8
IDDO (D)
0.03
mA/Mbps
1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADUM1300W/ADUM1301W channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.
Rev. J | Page 14 of 32
Data Sheet ADuM1300/ADuM1301
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V, 125°C OPERATION1
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 5 V, VDD2 = 3.0 V. These specifications apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 6.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.50
0.53
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.11
0.15
mA
ADuM1300W, Total Supply Current, Three Channels2
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
1.6
2.5
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.4
0.7
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
IDD1 (10)
6.5
8.1
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.1
1.6
mA
5 MHz logic signal freq.
ADuM1301W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
1.3
2.1
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.6
0.9
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
IDD1 (10)
5.0
6.2
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.8
2.5
mA
5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC, IE1, IE2
−10
+0.01
+10
μA
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold
VIH, VEH
2.0
V
Logic Low Input Threshold
VIL, VEL
0.8
V
Logic High Output Voltages
VOAH, VOBH, VOCH
VDD1, VDD2 − 0.1
VDD1, VDD2
V
IOx = −20 μA, VIx = VIxH
VDD1, VDD2 − 0.4
VDD1, VDD2 − 0.2
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL, VOCL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xWSRWZ
Minimum Pulse Width3
PW
1000
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate4
1
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay5
tPHL, tPLH
50
70
100
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
CL = 15 pF, CMOS signal levels
Propagation Delay Skew6
tPSK
50
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching7
tPSKCD/tPSKOD
50
ns
CL = 15 pF, CMOS signal levels
ADuM130xWTRWZ
Minimum Pulse Width2
PW
100
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
10
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
20
30
40
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
6
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
3
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
22
ns
CL = 15 pF, CMOS signal levels Rev. J | Page 15 of 32
ADuM1300/ADuM1301 Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
For All Models
Output Disable Propagation Delay (High/Low to High Impedance)
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High Impedance to High/Low)
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
3.0
ns
CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic High Output8
|CMH|
25
35
kV/μs
VIx = VDD1/VDD2, VCM = 1000 V, transient magnitude = 800 V
Common-Mode Transient Immunity at Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
1.2
Mbps
Input Dynamic Supply Current per Channel9
IDDI (D)
0.19
mA/Mbps
Output Dynamic Supply Current per Channel8
IDDO (D)
0.03
mA/Mbps
1 All voltages are relative to their respective ground.
2 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADUM1300W/ADUM1301W channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. J | Page 16 of 32
Data Sheet ADuM1300/ADuM1301
ELECTRICAL CHARACTERISTICS—MIXED 3 V/5 V, 125°C OPERATION
All voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V. These apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 7.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.26
0.31
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.19
0.24
mA
ADuM1300W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.9
1.7
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2(Q)
0.7
1.0
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
IDD1 (10)
3.4
4.9
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.9
2.5
mA
5 MHz logic signal freq.
ADuM1301W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.7
1.4
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
1.0
1.4
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
IDD1 (10)
2.6
3.7
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
3.4
4.2
mA
5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC, IE1, IE2
−10
+0.01
+10
μA
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold
VIH, VEH
1.6
V
Logic Low Input Threshold
VIL, VEL
0.4
V
Logic High Output Voltages
VOAH, VOBH, VOCH
VDD1, VDD2 − 0.1
VDD1, VDD2
V
IOx = −20 μA, VIx = VIxH
VDD1, VDD2 − 0.4
VDD1, VDD2 − 0.2
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL, VOCL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xWSRWZ
Minimum Pulse Width2
PW
1000
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
1
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
50
70
100
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
50
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
CL = 15 pF, CMOS signal levels
ADuM130xWTRWZ
Minimum Pulse Width2
PW
100
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
10
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
20
30
40
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
6
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
3
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
22
ns
CL = 15 pF, CMOS signal levels Rev. J | Page 17 of 32
ADuM1300/ADuM1301 Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
For All Models
Output Disable Propagation Delay (High/Low to High Impedance)
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High Impedance to High/Low)
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
CL = 15 pF, CMOS signal levels
5 V/3 V Operation
3.0
ns
3 V/5 V Operation
2.5
ns
Common-Mode Transient Immunity at Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1/VDD2, VCM = 1000 V, transient magnitude = 800 V
Common-Mode Transient Immunity at Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
1.1
Mbps
Input Dynamic Supply Current per Channel8
IDDI (D)
0.10
mA/Mbps
Output Dynamic Supply Current per Channel8
IDDO (D)
0.05
mA/Mbps
1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1300W/ADuM1301W channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. J | Page 18 of 32
Data Sheet ADuM1300/ADuM1301
PACKAGE CHARACTERISTICS
Table 8.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
Resistance (Input-to-Output)1
RI-O
1012
Ω
Capacitance (Input-to-Output)1
CI-O
1.7
pF
f = 1 MHz
Input Capacitance2
CI
4.0
pF
IC Junction-to-Case Thermal Resistance, Side 1
θJCI
33
°C/W
Thermocouple located at center of package underside
IC Junction-to-Case Thermal Resistance, Side 2
θJCO
28
°C/W
1 Device is considered a 2-terminal device; Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14, Pin 15, and Pin 16 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM130x are approved by the organizations listed in Table 9. Refer to Table 14 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific crossisolation waveforms and insulation levels.
Table 9.
UL
CSA
VDE
TÜV
Recognized under 1577 Component Recognition Program1
Approved under CSA Component Acceptance Notice #5A
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-122
Approved according to IEC 61010-1:2001 (2nd Edition), EN 61010-1:2001 (2nd Edition), UL 61010-1:2004 CSA C22.2.61010.1:2005
Single protection, 2500 V rms isolation voltage
Basic insulation per CSA 60950-1-03 and IEC 60950-1, 800 V rms (1131 V peak) maximum working voltage
Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (566 V peak) maximum working voltage
Reinforced insulation, 560 V peak
Reinforced insulation, 400 V rms maximum working voltage
File E214100
File 205078
File 2471900-4880-0001
Certificate U8V 05 06 56232 002
1 In accordance with UL 1577, each ADuM130x is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 μA).
2 In accordance with DIN V VDE V 0884-10, each ADuM130x is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 10.
Parameter
Symbol
Value
Unit
Conditions
Rated Dielectric Insulation Voltage
2500
V rms
1-minute duration
Minimum External Air Gap (Clearance)
L(I01)
7.7 min
mm
Measured from input terminals to output terminals, shortest distance through air
Minimum External Tracking (Creepage)
L(I02)
8.1 min
mm
Measured from input terminals to output terminals, shortest distance path along body
Minimum Internal Gap (Internal Clearance)
0.017 min
mm
Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index)
CTI
>175
V
DIN IEC 112/VDE 0303 Part 1
Isolation Group
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
Rev. J | Page 19 of 32
ADuM1300/ADuM1301 Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval for 560 V peak working voltage.
Table 11.
Description
Conditions
Symbol
Characteristic
Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
I to IV
For Rated Mains Voltage ≤ 300 V rms
I to III
For Rated Mains Voltage ≤ 400 V rms
I to II
Climatic Classification
40/105/21
Pollution Degree per DIN VDE 0110, Table 1
2
Maximum Working Insulation Voltage
VIORM
560
V peak
Input-to-Output Test Voltage, Method B1
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec, partial discharge < 5 pC
VPR
1050
V peak
Input-to-Output Test Voltage, Method A
VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC
VPR
After Environmental Tests Subgroup 1
896
V peak
After Input and/or Safety Test Subgroup 2 and Subgroup 3
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC
672
V peak
Highest Allowable Overvoltage
Transient overvoltage, tTR = 10 seconds
VTR
4000
V peak
Safety-Limiting Values
Maximum value allowed in the event of a failure (see Figure 3)
Case Temperature
TS
150
°C
Side 1 Current
IS1
265
mA
Side 2 Current
IS2
335
mA
Insulation Resistance at TS
VIO = 500 V
RS
>109
Ω
Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 12.
Parameter
Rating
Operating Temperature (TA)1
−40°C to +105°C
Operating Temperature (TA)2
−40°C to +125°C
Supply Voltages (VDD1, VDD2)1, 3
2.7 V to 5.5 V
Supply Voltages (VDD1, VDD2) 2, 3
3.0 V to 5.5 V
Input Signal Rise and Fall Times
1.0 ms
1 Does not apply to ADuM1300W and ADuM1301W automotive grade versions.
2 Applies to ADuM1300W and ADuM1301W automotive grade versions.
3 All voltages are relative to their respective ground. See the DC Correctness and Magnetic Field Immunity section for information on immunity to external magnetic fields.
CASE TEMPERATURE (°C)SAFETY-LIMITING CURRENT (mA)003503002502001501005050100150200SIDE #1SIDE #203787-003
Rev. J | Page 20 of 32
Data Sheet ADuM1300/ADuM1301
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 13.
Parameter
Rating
Storage Temperature (TST)
−65°C to +150°C
Ambient Operating Temperature (TA)1
−40°C to +105°C
Ambient Operating Temperature (TA)2
−40°C to +125°C
Supply Voltages (VDD1, VDD2)3
−0.5 V to +7.0 V
Input Voltage (VIA, VIB, VIC, VE1, VE2)3, 4
−0.5 V to VDDI + 0.5 V
Output Voltage (VOA, VOB, VOC)3, 4
−0.5 V to VDDO + 0.5 V
Average Output Current per Pin5
Side 1 (IO1)
−23 mA to +23 mA
Side 2 (IO2)
−30 mA to +30 mA
Common-Mode Transients6
−100 kV/μs to +100 kV/μs
1 Does not apply to ADuM1300W and ADuM1301W automotive grade versions.
2 Applies to ADuM1300W and ADuM1301W automotive grade versions.
3 All voltages are relative to their respective ground.
4 VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the PC Board Layout section.
5 See Figure 3 for maximum rated current values for various temperatures.
6 This refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Ratings may cause latch-up or permanent damage.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Table 14. Maximum Continuous Working Voltage1
Parameter
Max
Unit
Constraint
AC Voltage, Bipolar Waveform
565
V peak
50-year minimum lifetime
AC Voltage, Unipolar Waveform
Basic Insulation
1131
V peak
Maximum approved working voltage per IEC 60950-1
Reinforced Insulation
560
V peak
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
DC Voltage
Basic Insulation
1131
V peak
Maximum approved working voltage per IEC 60950-1
Reinforced Insulation
560
V peak
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Table 15. Truth Table (Positive Logic)
VIx Input1
VEx Input1, 2
VDDI State1
VDDO State1
VOx Output1
Notes
H
H or NC
Powered
Powered
H
L
H or NC
Powered
Powered
L
X
L
Powered
Powered
Z
X
H or NC
Unpowered
Powered
H
Outputs return to the input state within 1 μs of VDDI power restoration.
X
L
Unpowered
Powered
Z
X
X
Powered
Unpowered
Indeterminate
Outputs return to the input state within 1 μs of VDDO power restoration if the VEx state is H or NC. Outputs return to a high impedance state within 8 ns of VDDO power restoration if the VEx state is L.
1 VIx and VOx refer to the input and output signals of a given channel (A, B, or C). VEx refers to the output enable signal on the same side as the VOx outputs. VDDI and VDDO refer to the supply voltages on the input and output sides of the given channel, respectively.
2 In noisy environments, connecting VEx to an external logic high or low is recommended.
Rev. J | Page 21 of 32
ADuM1300/ADuM1301 Data Sheet
Rev. J | Page 22 of 32 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. ADuM1300 Pin Configuration Figure 5. ADuM1301 Pin Configuration
Table 16. ADuM1300 Pin Function Descriptions Pin
No. Mnemonic Description 1 VDD1 Supply Voltage for Isolator Side 1. 2 GND1 Ground 1. Ground reference for Isolator Side 1. 3 VIA Logic Input A.
4 VIB Logic Input B.
5 VIC Logic Input C.
6 NC No Connect.
7 NC No Connect.
8 GND1 Ground 1. Ground reference for Isolator Side 1. 9 GND2 Ground 2. Ground reference for Isolator Side 2. 10 VE2 Output Enable 2. Active high logic input. VOA, VOB,
and VOC outputs are enabled when VE2 is high or disconnected. VOA, VOB, and VOC outputs are disabled
when VE2 is low. In noisy environments, connecting VE2 to an external logic high or low is recommended. 11 NC No Connect.
12 VOC Logic Output C. 13 VOB Logic Output B.
14 VOA Logic Output A.
15 GND2 Ground 2. Ground reference for Isolator Side 2. 16 VDD2 Supply Voltage for Isolator Side 2. Table 17. ADuM1301 Pin Function Descriptions Pin
No. Mnemonic Description 1 VDD1 Supply Voltage for Isolator Side 1. 2 GND1 Ground 1. Ground reference for Isolator Side 1. 3 VIA Logic Input A.
4 VIB Logic Input B.
5 VOC Logic Output C. 6 NC No Connect.
7 VE1 Output Enable 1. Active high logic input. VOC output is enabled when VE1 is high or disconnected. VOC
output is disabled when VE1 is low. In noisy environ-
ments, connecting VE1 to an external logic high
or low is recommended. 8 GND1 Ground 1. Ground reference for Isolator Side 1. 9 GND2 Ground 2. Ground reference for Isolator Side 2. 10 VE2 Output Enable 2. Active high logic input. VOA and
VOB outputs are enabled when VE2 is high or discon-
nected. VOA and VOB outputs are disabled when VE2 is
low. In noisy environments, connecting VE2 to an external logic high or low is recommended.
11 NC No Connect.
12 VIC Logic Input C.
13 VOB Logic Output B.
14 VOA Logic Output A.
15 GND2 Ground 2. Ground reference for Isolator Side 2. 16 VDD2 Supply Voltage for Isolator Side 2. VDD1 1
*GND1 2
VIA 3
VIB 4
VDD2 16
15 GND2*
14 VOA
13 VOB
VIC 5 12 VOC
NC 6 11 NC
NC 7 10 VE2
*GND1 8 GND9 2*
NC = NO CONNECT
ADuM1300
TOP VIEW
(Not to Scale)
03787-004
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING
BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED.
03787-005
VDD1 1
*GND1 2
VIA 3
VIB 4
VDD2 16
GND15 2*
14 VOA
13 VOB
VOC 5 12 VIC
NC 6 11 NC
VE1 7 10 VE2
*GND1 8 GND9 2*
NC = NO CONNECT
ADuM1301
TOP VIEW
(Not to Scale)
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING
BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED.
Data Sheet ADuM1300/ADuM1301
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 6. Typical Input Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation
Figure 7. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (No Output Load)
Figure 8. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (15 pF Output Load)
Figure 9. Typical ADuM1300 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation
Figure 10. Typical ADuM1300 VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation
Figure 11. Typical ADuM1301 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation
DATA RATE (Mbps)CURRENT/CHANNEL (mA)006421412108161820402060801005V3V03787-008DATA RATE (Mbps)CURRENT/CHANNEL (mA)00243516204060801005V3V03787-009DATA RATE (Mbps)CURRENT/CHANNEL (mA)0010987654321204080601005V3V03787-010DATA RATE (Mbps)CURRENT (mA)02002010504030604060801005V3V03787-011DATA RATE (Mbps)CURRENT (mA)00421086121614402060801005V3V03787-012DATA RATE (Mbps)CURRENT (mA)001510545403530252050204060801005V3V03787-013
Rev. J | Page 23 of 32
ADuM1300/ADuM1301 Data Sheet
Figure 12. Typical ADuM1301 VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation
Figure 13. Propagation Delay vs. Temperature, C Grade
DATA RATE (Mbps)CURRENT (mA)0010520152530204060801005V3V03787-014TEMPERATURE (°C)PROPAGATION DELAY (ns)–50–252530354005075251003V5V03787-019
Rev. J | Page 24 of 32
Data Sheet ADuM1300/ADuM1301
APPLICATIONS INFORMATION
PC BOARD LAYOUT
The ADuM130x digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 14). Bypass capacitors are most conveniently connected between Pin 1 and Pin 2 for VDD1 and between Pin 15 and Pin 16 for VDD2. The capacitor value should be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should also be considered unless the ground pair on each package side is connected close to the package.
Figure 14. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage.
See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic low output may differ from the propagation delay to a logic high output.
Figure 15. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount that the propagation delay differs between channels within a single ADuM130x component.
Propagation delay skew refers to the maximum amount that the propagation delay differs between multiple ADuM130x components operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is therefore either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses for more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 15) by the watchdog timer circuit.
The ADuM130x is extremely immune to external magnetic fields. The limitation on the magnetic field immunity of the ADuM130x is set by the condition in which induced voltage in the receiving coil of the transformer is sufficiently large enough to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The 3 V operating condition of the ADuM130x is examined because it represents the most susceptible mode of operation.
The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by
V = (−dβ/dt)ΣΠrn2; n = 1, 2, … , N
where: β is magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm).
Given the geometry of the receiving coil in the ADuM130x and an imposed requirement that the induced voltage be 50% at most of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 16.
Figure 16. Maximum Allowable External Magnetic Flux Density
VDD1GND1VIAVIBVIC/VOCNCNC/VE1GND1VDD2GND2VOAVOBVOC/VICNCVE2GND203787-015INPUT (VIx)OUTPUT (VOx)tPLHtPHL50%50%03787-016MAGNETIC FIELD FREQUENCY (
Hz)100MAXIMUM ALLOWABLE MAGNETIC FLUXDENSITY (
kgauss)0.0011M100.011k10k10M0.11100M100k03787-017
Rev. J | Page 25 of 32
ADuM1300/ADuM1301 Data Sheet
For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (and has the worst-case polarity), it reduces the received pulse from >1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder.
The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM130x transformers. Figure 17 shows these allowable current magnitudes as a function of frequency for selected distances. The ADuM130x is extremely immune and can be affected only by extremely large currents operated at a high frequency very close to the component. For the 1 MHz example noted, one would have to place a 0.5 kA current 5 mm away from the ADuM130x to affect the operation of the component.
Figure 17. Maximum Allowable Current for Various Current-to-ADuM130x Spacings
Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.
POWER CONSUMPTION
The supply current at a given channel of the ADuM130x isolator is a function of the supply voltage, the data rate of the channel, and the output load of the channel.
For each input channel, the supply current is given by
IDDI = IDDI (Q) f ≤ 0.5 fr
IDDI = IDDI (D) × (2f − fr) + IDDI (Q) f > 0.5 fr
For each output channel, the supply current is given by
IDDO = IDDO (Q) f ≤ 0.5 fr
IDDO = (IDDO (D) + (0.5 × 10−3) × CL × VDDO) × (2f − fr) + IDDO (Q) f > 0.5 fr
where: IDDI (D), IDDO (D) are the input and output dynamic supply currents per channel (mA/Mbps). CL is the output load capacitance (pF). VDDO is the output supply voltage (V). f is the input logic signal frequency (MHz); it is half of the input data rate expressed in units of Mbps. fr is the input stage refresh rate (Mbps). IDDI (Q), IDDO (Q) are the specified input and output quiescent supply currents (mA).
To calculate the total VDD1 and VDD2 supply current, the supply currents for each input and output channel corresponding to VDD1 and VDD2 are calculated and totaled. Figure 6 and Figure 7 provide per-channel supply currents as a function of data rate for an unloaded output condition. Figure 8 provides per-channel supply current as a function of data rate for a 15 pF output condition. Figure 9 through Figure 12 provide total VDD1 and VDD2 supply current as a function of data rate for ADuM1300/ ADuM1301 channel configurations.
MAGNETIC FIELD FREQUENCY (Hz)MAXIMUM ALLOWABLE CURRENT (kA)10001001010.10.011k10k100M100k1M10MDISTANCE = 5mmDISTANCE = 1mDISTANCE = 100mm03787-018
Rev. J | Page 26 of 32
Data Sheet ADuM1300/ADuM1301
INSULATION LIFETIME
All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM130x.
Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Accel-eration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 14 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than the 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases.
The insulation lifetime of the ADuM130x depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 18, Figure 19, and Figure 20 illustrate these different isolation voltage waveforms, respectively.
Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the Analog Devices recommended maximum working voltage.
In the case of unipolar ac or dc voltage, the stress on the insu-lation is significantly lower, which allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 14 can be applied while main-taining the 50-year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage cases. Any cross insulation voltage waveform that does not conform to Figure 19 or Figure 20 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 14.
Note that the voltage presented in Figure 19 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V.
Figure 18. Bipolar AC Waveform
Figure 19. Unipolar AC Waveform
Figure 20. DC Waveform
0VRATED PEAK VOLTAGE03787-0210VRATED PEAK VOLTAGE03787-0220VRATED PEAK VOLTAGE03787-023
Rev. J | Page 27 of 32
ADuM1300/ADuM1301 Data Sheet
OUTLINE DIMENSIONS
Figure 21. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters (and inches)
ORDERING GUIDE
Model1, 2, 3, 4
Number of Inputs, VDD1 Side
Number of Inputs, VDD2 Side
Maximum Data Rate (Mbps)
Maximum Propagation Delay, 5 V (ns)
Maximum Pulse Width Distortion (ns)
Temperature Range
Package Option5
ADuM1300ARW
3
0
1
100
40
−40°C to +105°C
RW-16
ADuM1300CRW
3
0
90
32
2
−40°C to +105°C
RW-16
ADuM1300ARWZ
3
0
1
100
40
−40°C to +105°C
RW-16
ADuM1300BRWZ
3
0
10
50
3
−40°C to +105°C
RW-16
ADuM1300CRWZ
3
0
90
32
2
−40°C to +105°C
RW-16
ADuM1300WSRWZ
3
0
1
100
40
−40°C to +125°C
RW-16
ADuM1300WTRWZ
3
0
10
32
3
−40°C to +125°C
RW-16
ADuM1301ARW
2
1
1
100
40
−40°C to +105°C
RW-16
ADuM1301BRW
2
1
10
50
3
−40°C to +105°C
RW-16
ADuM1301CRW
2
1
90
32
2
−40°C to +105°C
RW-16
ADuM1301ARWZ
2
1
1
100
40
−40°C to +105°C
RW-16
ADuM1301BRWZ
2
1
10
50
3
−40°C to +105°C
RW-16
ADuM1301CRWZ
2
1
90
32
2
−40°C to +105°C
RW-16
ADuM1301WSRWZ
2
1
1
100
40
−40°C to +125°C
RW-16
ADuM1301WTRWZ
2
1
10
32
3
−40°C to +125°C
RW-16
EVAL-ADuMQSEBZ
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 Tape and reel are available. The addition of an -RL suffix designates a 13” (1,000 units) tape-and-reel option.
4 No tape-and-reel option is available for the ADuM1301CRW model.
5 RW-16 = 16-lead wide body SOIC.
CONTROLLINGDIMENSIONSAREINMILLIMETERS;INCHDIMENSIONS(INPARENTHESES)AREROUNDED-OFFMILLIMETEREQUIVALENTSFORREFERENCEONLYANDARENOTAPPROPRIATEFORUSEINDESIGN.COMPLIANTTOJEDECSTANDARDSMS-013-AA10.50(0.4134)10.10(0.3976)0.30(0.0118)0.10(0.0039)2.65(0.1043)2.35(0.0925)10.65(0.4193)10.00(0.3937)7.60(0.2992)7.40(0.2913)0.75(0.0295)0.25(0.0098)45°1.27(0.0500)0.40(0.0157)COPLANARITY0.100.33(0.0130)0.20(0.0079)0.51(0.0201)0.31(0.0122)SEATINGPLANE8°0°169811.27(0.0500)BSC03-27-2007-B
Rev. J | Page 28 of 32
Data Sheet ADuM1300/ADuM1301
AUTOMOTIVE PRODUCTS
The ADuM1300W/ADuM1301W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.
Rev. J | Page 29 of 32
ADuM1300/ADuM1301 Data Sheet
NOTES
Rev. J | Page 30 of 32
Data Sheet ADuM1300/ADuM1301
NOTES
Rev. J | Page 31 of 32
ADuM1300/ADuM1301 Data Sheet
NOTES
©2003–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03787-0-4/14(J)
Rev. J | Page 32 of 32
Dual-Channel Digital Isolators
Data Sheet ADuM1200/ADuM1201
Rev. I
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved. FEATURES Narrow body, RoHS-compliant, SOIC 8-lead package
Low power operation 5 V operation
1.1 mA per channel maximum @ 0 Mbps to 2 Mbps 3.7 mA per channel maximum @ 10 Mbps 8.2 mA per channel maximum @ 25 Mbps
3 V operation
0.8 mA per channel maximum @ 0 Mbps to 2 Mbps 2.2 mA per channel maximum @ 10 Mbps
4.8 mA per channel maximum @ 25 Mbps
Bidirectional communication 3 V/5 V level translation
High temperature operation: 125°C High data rate: dc to 25 Mbps (NRZ)
Precise timing characteristics 3 ns maximum pulse width distortion
3 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Qualified for automotive applications Safety and regulatory approvals
UL recognition 2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
VIORM = 560 V peak APPLICATIONS
Size-critical multichannel isolation
SPI interface/data converter isolation
RS-232/RS-422/RS-485 transceiver isolation Digital field bus isolation
Hybrid electric vehicles, battery monitor, and motor drive GENERAL DESCRIPTION
The ADuM120x1 are dual-channel digital isolators based on the Analog Devices, Inc., iCoupler® technology. Combining
high speed CMOS and monolithic transformer technologies,
these isolation components provide outstanding performance
characteristics superior to alternatives, such as optocouplers. By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with opto-
couplers. The typical optocoupler concerns regarding uncertain
current transfer ratios, nonlinear transfer functions, and temper-
ature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates. The ADuM120x isolators provide two independent isolation
channels in a variety of channel configurations and data rates
(see the Ordering Guide). Both parts operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier. In addition, the ADuM120x provide low pulse width distortion (<3 ns for CR grade) and tight channel-to-channel matching (<3 ns for CR grade). Unlike other optocoupler alternatives, the ADuM120x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions. The ADuM1200W and ADuM1201W are automotive grade
versions qualified for 125°C operation. See the Automotive Products section for more information. FUNCTIONAL BLOCK DIAGRAMS
ENCODE DECODE
ENCODE DECODE
VDD1
VIA
VIB
GND1
VDD2
VOA
VOB
GND2
1
2
3
4
8
7
6
5
04642-001
Figure 1. ADuM1200 Functional Block Diagram
ENCODE DECODE
DECODE ENCODE
VDD1
VOA
VIB
GND1
VDD2
VIA
VOB
GND2
1
2
3
4
8
7
6
5
04642-002
Figure 2. ADuM1201 Functional Block Diagram
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 2 of 28
TABLE OF CONTENTS
Features..............................................................................................1
Applications.......................................................................................1
General Description.........................................................................1
Functional Block Diagrams.............................................................1
Revision History...............................................................................3
Specifications.....................................................................................4
Electrical Characteristics—5 V, 105°C Operation...................4
Electrical Characteristics—3 V, 105°C Operation...................6
Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V, 105°C Operation...........................................................................8
Electrical Characteristics—5 V, 125°C Operation.................11
Electrical Characteristics—3 V, 125°C Operation.................13
Electrical Characteristics—Mixed 5 V/3 V, 125°C Operation15
Electrical Characteristics—Mixed 3 V/5 V, 125°C Operation17
Package Characteristics.............................................................19
Regulatory Information.............................................................19
Insulation and Safety-Related Specifications..........................19
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 Insulation Characteristics.........................................................20
Recommended Operating Conditions....................................20
Absolute Maximum Ratings.........................................................21
ESD Caution................................................................................21
Pin Configurations and Function Descriptions.........................22
Typical Performance Characteristics...........................................23
Applications Information..............................................................24
PCB Layout.................................................................................24
Propagation Delay-Related Parameters...................................24
DC Correctness and Magnetic Field Immunity...........................24
Power Consumption..................................................................25
Insulation Lifetime.....................................................................26
Outline Dimensions.......................................................................27
Ordering Guide..........................................................................27
Automotive Products.................................................................28
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 3 of 28
REVISION HISTORY
3/12—Rev. H to Rev. I
Created Hyperlink for Safety and Regulatory Approvals Entry in Features Section.................................................................1 Change to General Description Section.........................................1 Change to PCB Layout Section.....................................................24 Moved Automotive Products Section...........................................28
1/09—Rev. G to Rev. H
Changes to Table 5, Switching Specifications Parameter...........13 Changes to Table 6, Switching Specifications Parameter...........15 Changes to Table 7, Switching Specifications Parameter...........17
9/08—Rev. F to Rev. G
Changes to Table 9..........................................................................19
Changes to Table 13........................................................................21
Changes to Ordering Guide...........................................................27
3/08—Rev. E to Rev. F
Changes to Features Section............................................................1 Changes to Applications Section.....................................................1 Added Table 4..................................................................................11 Added Table 5..................................................................................13 Added Table 6..................................................................................15 Added Table 7..................................................................................17 Changes to Table 12........................................................................20 Changes to Table 13........................................................................21 Added Automotive Products Section...........................................26 Changes to Ordering Guide...........................................................27
11/07—Rev. D to Rev. E
Changes to Note 1.............................................................................1 Added ADuM120xAR Change vs. Temperature Parameter.......3 Added ADuM120xAR Change vs. Temperature Parameter.......5 Added ADuM120xAR Change vs. Temperature Parameter.......8
8/07—Rev. C to Rev. D
Updated VDE Certification Throughout.......................................1 Changes to Features, Note 1, Figure 1, and Figure 2....................1 Changes to Table 3............................................................................7 Changes to Regulatory Information Section...............................10 Added Table 10................................................................................12 Added Insulation Lifetime Section...............................................16 Updated Outline Dimensions........................................................18 Changes to Ordering Guide...........................................................18
2/06—Rev. B to Rev. C
Updated Format.................................................................Universal Added Note 1.....................................................................................1 Changes to Absolute Maximum Ratings......................................12 Changes to DC Correctness and Magnetic Field Immunity Section............................................................................15
9/04—Rev. A to Rev. B
Changes to Table 5..........................................................................10
6/04—Rev. 0 to Rev. A
Changes to Format.............................................................Universal Changes to General Description.....................................................1 Changes to Electrical Characteristics—5 V Operation................3 Changes to Electrical Characteristics—3 V Operation................5 Changes to Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V Operation............................................................................7
4/04—Revision 0: Initial Version
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 4 of 28
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V, 105°C OPERATION
All voltages are relative to their respective ground; 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V; this does not apply to the ADuM1200W and ADuM1201W automotive grade products.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.50
0.60
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.19
0.25
mA
ADuM1200 Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
1.1
1.4
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.5
0.8
mA
DC to 1 MHz logic signal freq.
10 Mbps (BR and CR Grades Only)
VDD1 Supply Current
IDD1 (10)
4.3
5.5
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.3
2.0
mA
5 MHz logic signal freq.
25 Mbps (CR Grade Only)
VDD1 Supply Current
IDD1 (25)
10
13
mA
12.5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (25)
2.8
3.4
mA
12.5 MHz logic signal freq.
ADuM1201 Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.8
1.1
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.8
1.1
mA
DC to 1 MHz logic signal freq.
10 Mbps (BR and CR Grades Only)
VDD1 Supply Current
IDD1 (10)
2.8
3.5
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
2.8
3.5
mA
5 MHz logic signal freq.
25 Mbps (CR Grade Only)
VDD1 Supply Current
IDD1 (25)
6.3
8.0
mA
12.5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (25)
6.3
8.0
mA
12.5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB
−10
+0.01
+10
μA
0 V ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold
VIH
0.7 (VDD1 or VDD2)
V
Logic Low Input Threshold
VIL
0.3 (VDD1 or VDD2)
V
Logic High Output Voltages
VOAH, VOBH
(VDD1 or VDD2) − 0.1
5.0
V
IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.5
4.8
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM120xAR
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
PW
1000
ns
Maximum Data Rate3
1
Mbps
Propagation Delay4 t
PHL, tPLH
50
150
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
Change vs. Temperature
11
ps/°C
Propagation Delay Skew5 t
PSK
100
ns
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
10
ns
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 5 of 28
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM120xBR
Minimum Pulse Width2
PW
100
ns
Maximum Data Rate3
10
Mbps
Propagation Delay4
tPHL, tPLH
20
50
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
Change vs. Temperature
5
ps/°C
Propagation Delay Skew5
tPSK
15
ns
Channel-to-Channel Matching
3
Codirectional Channels6
tPSKCD
ns
Opposing Directional Channels6
tPSKOD
15
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
2.5
ns
ADuM120xCR
Minimum Pulse Width2
PW
20
40
ns
Maximum Data Rate3
25
50
Mbps
Propagation Delay4
tPHL, tPLH
20
45
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
Change vs. Temperature
5
ps/°C
Propagation Delay Skew5
tPSK
15
ns
Channel-to-Channel Matching
3
ns
Codirectional Channels6
tPSKCD
Opposing Directional Channels6
tPSKOD
15
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
2.5
ns
For All Models
Common-Mode Transient Immunity
Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V
Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
1.2
Mbps
Dynamic Supply Current per Channel8
Input
IDDI (D)
0.19
mA/ Mbps
Output
IDDO (D)
0.05
mA/ Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the section. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.
Power ConsumptionPower Consumption
Figure 6 Figure 6
Figure 8Figure 8
Figure 9
Figure 11
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the section for guidance on calculating per-channel supply current for a given data rate.
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 6 of 28 ELECTRICAL CHARACTERISTICS—3 V, 105°C OPERATION
All voltages are relative to their respective ground; 2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V; this
does not apply to ADuM1200W and ADuM1201W automotive grade products.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q) 0.26 0.35 mA
Output Supply Current per Channel, Quiescent IDDO (Q) 0.11 0.20 mA
ADuM1200 Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 0.6 1.0 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.2 0.6 mA DC to 1 MHz logic signal freq. 10 Mbps (BR and CR Grades Only) VDD1 Supply Current IDD1 (10) 2.2 3.4 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 0.7 1.1 mA 5 MHz logic signal freq. 25 Mbps (CR Grade Only)
VDD1 Supply Current IDD1 (25) 5.2 7.7 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 1.5 2.0 mA 12.5 MHz logic signal freq. ADuM1201 Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 0.4 0.8 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.4 0.8 mA DC to 1 MHz logic signal freq. 10 Mbps (BR and CR Grades Only) VDD1 Supply Current IDD1 (10) 1.5 2.2 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 1.5 2.2 mA 5 MHz logic signal freq. 25 Mbps (CR Grade Only)
VDD1 Supply Current IDD1 (25) 3.4 4.8 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 3.4 4.8 mA 12.5 MHz logic signal freq. For All Models Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold VIH 0.7 (VDD1 or VDD2) V
Logic Low Input Threshold VIL 0.3 (VDD1 or VDD2)
Logic High Output Voltages VOAH, VOBH (VDD1 or VDD2) − 0.1 3.0 V IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.5 2.8 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL 0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.04 0.1 V IOx = 400 μA, VIx = VIxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM120xAR CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 1000 ns
Maximum Data Rate3 1 Mbps
Propagation Delay4 tPHL, tPLH 50 150 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns Change vs. Temperature 11 ps/°C
Propagation Delay Skew5 tPSK 100 ns
Channel-to-Channel Matching6 tPSKCD/tPSKOD 50 ns
Output Rise/Fall Time (10% to 90%) tR/tF 10 ns
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 7 of 28
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM120xBR
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
PW
100
ns
Maximum Data Rate3
10
Mbps
Propagation Delay4
tPHL, tPLH
20
60
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
Change vs. Temperature
5
ps/°C
Propagation Delay Skew5
tPSK
22
ns
Channel-to-Channel Matching
Codirectional Channels6
tPSKCD
3
ns
Opposing Directional Channels6
tPSKOD
22
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
3.0
ns
ADuM120xCR
Minimum Pulse Width2
PW
20
40
ns
Maximum Data Rate3
25
50
Mbps
Propagation Delay4
tPHL, tPLH
20
55
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
Change vs. Temperature
5
ps/°C
Propagation Delay Skew5
tPSK
16
ns
Channel-to-Channel Matching
Codirectional Channels6
tPSKCD
3
ns
Opposing Directional Channels6
tPSKOD
16
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
3.0
ns
For All Models
Common-Mode Transient Immunity
Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V
Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
1.1
Mbps
Dynamic Supply Current per Channel8
Input
IDDI (D)
0.10
mA/
Mbps
Output
IDDO (D)
0.03
mA/
Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the section. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through Figure 11 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.
Power ConsumptionPower Consumption
Figure 6 Figure 6
Figure 8Figure 8
Figure 9
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the section for guidance on calculating per-channel supply current for a given data rate.
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 8 of 28 ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V, 105°C OPERATION
All voltages are relative to their respective ground; 5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V. 3 V/5 V operation: 2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operating range,
unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5.0 V; or VDD1 = 5.0 V, VDD2 = 3.0 V; this does not
apply to ADuM1200W and ADuM1201W automotive grade products. Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
5 V/3 V Operation 0.50 0.6 mA
3 V/5 V Operation 0.26 0.35 mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
5 V/3 V Operation 0.11 0.20 mA
3 V/5 V Operation 0.19 0.25 mA
ADuM1200 Total Supply Current,
Two Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q)
5 V/3 V Operation 1.1 1.4 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.6 1.0 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q)
5 V/3 V Operation 0.2 0.6 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.5 0.8 mA DC to 1 MHz logic signal freq. 10 Mbps (BR and CR Grades Only) VDD1 Supply Current IDD1 (10)
5 V/3 V Operation 4.3 5.5 mA 5 MHz logic signal freq. 3 V/5 V Operation 2.2 3.4 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10)
5 V/3 V Operation 0.7 1.1 mA 5 MHz logic signal freq. 3 V/5 V Operation 1.3 2.0 mA 5 MHz logic signal freq. 25 Mbps (CR Grade Only)
VDD1 Supply Current IDD1 (25)
5 V/3 V Operation 10 13 mA 12.5 MHz logic signal freq. 3 V/5 V Operation 5.2 7.7 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25)
5 V/3 V Operation 1.5 2.0 mA 12.5 MHz logic signal freq. 3 V/5 V Operation 2.8 3.4 mA 12.5 MHz logic signal freq. ADuM1201 Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q)
5 V/3 V Operation 0.8 1.1 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 0.4 0.8 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q)
5 V/3 V Operation 0.4 0.8 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.8 1.1 mA DC to 1 MHz logic signal freq. 10 Mbps (BR and CR Grades Only) VDD1 Supply Current IDD1 (10)
5 V/3 V Operation 2.8 3.5 mA 5 MHz logic signal freq. 3 V/5 V Operation 1.5 2.2 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10)
5 V/3 V Operation 1.5 2.2 mA 5 MHz logic signal freq. 3 V/5 V Operation 2.8 3.5 mA 5 MHz logic signal freq.
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 9 of 28
Parameter Symbol Min Typ Max Unit Test Conditions
25 Mbps (CR Grade Only)
VDD1 Supply Current
IDD1 (25)
5 V/3 V Operation
6.3
8.0
mA
12.5 MHz logic signal freq.
3 V/5 V Operation
3.4
4.8
mA
12.5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (25)
5 V/3 V Operation
3.4
4.8
mA
12.5 MHz logic signal freq.
3 V/5 V Operation
6.3
8.0
mA
12.5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB
−10
+0.01
+10
μA
0 V ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold
VIH
0.7 (VDD1 or VDD2)
V
Logic Low Input Threshold
VIL
0.3 (VDD1 or VDD2)
V
Logic High Output Voltages
VOAH, VOBH
(VDD1 or VDD2) − 0.1
VDD1 or VDD2
V
IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.5
(VDD1 or VDD2) − 0.2
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM120xAR
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
PW
1000
ns
Maximum Data Rate3
1
Mbps
Propagation Delay4
tPHL, tPLH
50
150
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
Change vs. Temperature
11
ps/°C
Propagation Delay Skew5 t
PSK
50
ns
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
10
ns
ADuM120xBR
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
PW
100
ns
Maximum Data Rate3
10
Mbps
Propagation Delay4
tPHL, tPLH
15
55
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
Change vs. Temperature
5
ps/°C
Propagation Delay Skew5
tPSK
22
ns
Channel-to-Channel Matching
Codirectional Channels6
tPSKCD
3
ns
Opposing Directional Channels6
tPSKOD
22
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
5 V/3 V Operation
3.0
ns
3 V/5 V Operation
2.5
ns
ADuM120xCR
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
PW
20
40
ns
Maximum Data Rate3
25
50
Mbps
Propagation Delay4
tPHL, tPLH
20
50
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
Change vs. Temperature
5
ps/°C
Propagation Delay Skew5
tPSK
15
ns
Channel-to-Channel Matching
Codirectional Channels6
tPSKCD
3
ns
Opposing Directional Channels6
tPSKOD
15
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
5 V/3 V Operation
3.0
ns
3 V/5 V Operation
2.5
ns
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 10 of 28
Parameter Symbol Min Typ Max Unit Test Conditions
For All Models
Common-Mode Transient Immunity
Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V
Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
5 V/3 V Operation
1.2
Mbps
3 V/5 V Operation
1.1
Mbps
Input Dynamic Supply Current per Channel8
IDDI (D)
5 V/3 V Operation
0.19
mA/ Mbps
3 V/5 V Operation
0.10
mA/ Mbps
Output Dynamic Supply Current per Channel8
IDDO (D)
5 V/3 V Operation
0.03
mA/ Mbps
3 V/5 V Operation
0.05
mA/ Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the section. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.
Power ConsumptionPower Consumption
Figure 6 Figure 6
Figure 8Figure 8
Figure 9
Figure 11
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the section for guidance on calculating per-channel supply current for a given data rate.
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 11 of 28
ELECTRICAL CHARACTERISTICS—5 V, 125°C OPERATION
All voltages are relative to their respective ground; 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V; this applies to ADuM1200W and ADuM1201W automotive grade products.
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.50
0.60
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.19
0.25
mA
ADM1200W, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
1.1
1.4
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.5
0.8
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRZ and URZ Grades Only)
VDD1 Supply Current
IDD1 (10)
4.3
5.5
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.3
2.0
mA
5 MHz logic signal freq.
25 Mbps (URZ Grade Only)
VDD1 Supply Current
IDD1 (25)
10
13
mA
12.5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (25)
2.8
3.4
mA
12.5 MHz logic signal freq.
ADM1201W, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.8
1.1
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.8
1.1
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRZ and URZ Grades Only)
VDD1 Supply Current
IDD1 (10)
2.8
3.5
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
2.8
3.5
mA
5 MHz logic signal freq.
25 Mbps (URZ Grade Only)
VDD1 Supply Current
IDD1 (25)
6.3
8.0
mA
12.5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (25)
6.3
8.0
mA
12.5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB
−10
+0.01
+10
μA
0 ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold
VIH
0.7 (VDD1 or VDD2)
V
Logic Low Input Threshold
VIL
0.3 (VDD1 or VDD2)
V
Logic High Output Voltages
VOAH, VOBH
(VDD1 or VDD2) − 0.1
5.0
V
IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.5
4.8
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM120xWSRZ
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
PW
1000
ns
Maximum Data Rate3
1
Mbps
Propagation Delay4 t
PHL, tPLH
20
150
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
Propagation Delay Skew5
tPSK
100
ns
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
2.5
ns
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 12 of 28 Parameter Symbol Min Typ Max Unit Test Conditions ADuM120xWTRZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 100 ns Maximum Data Rate3 10 Mbps Propagation Delay4 tPHL, tPLH 20 50 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns
Change vs. Temperature 5 ps/°C
Propagation Delay Skew5 tPSK 15 ns Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 15 ns Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns
ADuM120xWURZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 20 40 ns Maximum Data Rate3 25 50 Mbps Propagation Delay4 tPHL, tPLH 20 45 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns
Change vs. Temperature 5 ps/°C
Propagation Delay Skew5 tPSK 15 ns Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 15 ns Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns
For All Models Common-Mode Transient Immunity Logic High Output7 |CMH| 25 35 kV/μs VIx = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V
Logic Low Output7 |CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate fr 1.2 Mbps
Dynamic Supply Current per Channel8
Input IDDI (D) 0.19 mA/ Mbps
Output IDDO (D) 0.05 mA/ Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1200W and ADuM1201W channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate.
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 13 of 28
ELECTRICAL CHARACTERISTICS—3 V, 125°C OPERATION
All voltages are relative to their respective ground; 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V; this applies to ADuM1200W and ADuM1201W automotive grade products.
Table 5.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.26
0.35
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.11
0.20
mA
ADM1200W, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.6
1.0
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.2
0.6
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRZ and URZ Grades Only)
VDD1 Supply Current
IDD1 (10)
2.2
3.4
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
0.7
1.1
mA
5 MHz logic signal freq.
25 Mbps (URZ Grade Only)
VDD1 Supply Current
IDD1 (25)
5.2
7.7
mA
12.5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (25)
1.5
2.0
mA
12.5 MHz logic signal freq.
ADM1201W, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.4
0.8
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.4
0.8
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRZ and URZ Grades Only)
VDD1 Supply Current
IDD1 (10)
1.5
2.2
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.5
2.2
mA
5 MHz logic signal freq.
25 Mbps (URZ Grade Only)
VDD1 Supply Current
IDD1 (25)
3.4
4.8
mA
12.5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (25)
3.4
4.8
mA
12.5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB
−10
+0.01
+10
μA
0 ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold
VIH
0.7 (VDD1 or VDD2)
V
Logic Low Input Threshold
VIL
0.3 (VDD1 or VDD2)
Logic High Output Voltages
VOAH, VOBH
(VDD1 or VDD2) − 0.1
3.0
V
IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.5
2.8
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM120xWSRZ
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
PW
1000
ns
Maximum Data Rate3
1
Mbps
Propagation Delay4 t
PHL, tPLH
20
150
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
Propagation Delay Skew5 t
PSK
100
ns
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
3
ns
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 14 of 28 Parameter Symbol Min Typ Max Unit Test Conditions ADuM120xWTRZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 100 ns Maximum Data Rate3 10 Mbps Propagation Delay4 tPHL, tPLH 20 60 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C
Propagation Delay Skew5 tPSK 22 ns
Channel-to-Channel Matching
Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 22 ns
Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns
ADuM120xWCR CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 20 40 ns Maximum Data Rate3 25 50 Mbps Propagation Delay4 tPHL, tPLH 20 55 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C
Propagation Delay Skew5 tPSK 16 ns Channel-to-Channel Matching
Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 16 ns Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns For All Models Common-Mode Transient Immunity Logic High Output7 |CMH| 25 35 kV/μs VIx = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V Logic Low Output7 |CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V Refresh Rate fr 1.1 Mbps
Dynamic Supply Current per Channel8
Input IDDI (D) 0.10 mA/ Mbps
Output IDDO (D) 0.03 mA/ Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1200W and ADuM1201W channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulsewidth distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulsewidth distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate.
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 15 of 28 ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V, 125°C OPERATION
All voltages are relative to their respective ground; 5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V. 3 V/5 V operation; all
minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted; all typical specifications
are at TA = 25°C; VDD1 = 5.0 V, VDD2 = 3.0 V; this applies to ADuM1200W and ADuM1201W automotive grade products. Table 6.
Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q) 0.50 0.6 mA
Output Supply Current per Channel, Quiescent
IDDO (Q) 0.11 0.20 mA
ADuM1200W, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.1 1.4 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.2 0.6 mA DC to 1 MHz logic signal freq. 10 Mbps (TRZ and URZ Grades Only) VDD1 Supply Current IDD1 (10) 4.3 5.5 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 0.7 1.1 mA 5 MHz logic signal freq. 25 Mbps (URZ Grade Only) VDD1 Supply Current IDD1 (25) 10 13 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 1.5 2.0 mA 12.5 MHz logic signal freq. ADuM1201W, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 0.8 1.1 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.4 0.8 mA DC to 1 MHz logic signal freq. 10 Mbps (TRZ and URZ Grades Only) VDD1 Supply Current IDD1 (10) 2.8 3.5 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 1.5 2.2 mA 5 MHz logic signal freq. 25 Mbps (URZ Grade Only) VDD1 Supply Current IDD1 (25) 6.3 8.0 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 3.4 4.8 mA 12.5 MHz logic signal freq. For All Models Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold VIH 0.7 (VDD1 or VDD2) V Logic Low Input Threshold VIL 0.3 (VDD1 or VDD2) V
Logic High Output Voltages VOAH, VOBH (VDD1 or VDD2) − 0.1 VDD1 or VDD2 V IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.5 (VDD1 or VDD2) − 0.2 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL 0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.04 0.1 V IOx = 400 μA, VIx = VIxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM120xWSRZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 1000 ns Maximum Data Rate3 1 Mbps
Propagation Delay4 tPHL, tPLH 15 150 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns Propagation Delay Skew5 tPSK 50 ns
Channel-to-Channel Matching6 tPSKCD/ tPSKOD 50 ns
Output Rise/Fall Time (10% to 90%) tR/tF 3 ns
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 16 of 28 Parameter Symbol Min Typ Max Unit Test Conditions ADuM120xWTRZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 100 ns Maximum Data Rate3 10 Mbps Propagation Delay4 tPHL, tPLH 15 55 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C
Propagation Delay Skew5 tPSK 22 ns
Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 22 ns
Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns ADuM120xWURZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 20 40 ns Maximum Data Rate3 25 50 Mbps Propagation Delay4 tPHL, tPLH 20 50 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C
Propagation Delay Skew5 tPSK 15 ns
Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 15 ns
Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns For All Models Common-Mode Transient Immunity Logic High Output7 |CMH| 25 35 kV/μs VIx = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V Logic Low Output7 |CML| 25 35 kV/μs VIx = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V Refresh Rate fr 1.2 Mbps
Dynamic Supply Current per Channel8
Input IDDI (D) 0.19 mA/ Mbps
Output IDDO (D) 0.03 mA/ Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1200W and ADuM1201W channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate.
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 17 of 28 ELECTRICAL CHARACTERISTICS—MIXED 3 V/5 V, 125°C OPERATION
All voltages are relative to their respective ground; 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5.0 V; this applies to ADuM1200W and ADuM1201W automotive grade products. Table 7.
Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q) 0.26 0.35 mA
Output Supply Current per Channel, Quiescent
IDDO (Q) 0.19 0.25 mA
ADuM1200W, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 0.6 1.0 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.5 0.8 mA DC to 1 MHz logic signal freq. 10 Mbps (TRZ and URZ Grades Only) VDD1 Supply Current IDD1 (10) 2.2 3.4 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 1.3 2.0 mA 5 MHz logic signal freq. 25 Mbps (URZ Grade Only) VDD1 Supply Current IDD1 (25) 5.2 7.7 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 2.8 3.4 mA 12.5 MHz logic signal freq. ADuM1201W, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 0.4 0.8 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.8 1.1 mA DC to 1 MHz logic signal freq. 10 Mbps (TRZ and URZ Grades Only) VDD1 Supply Current IDD1 (10) 1.5 2.2 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 2.8 3.5 mA 5 MHz logic signal freq. 25 Mbps (URZ Grade Only) VDD1 Supply Current IDD1 (25) 3.4 4.8 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 6.3 8.0 mA 12.5 MHz logic signal freq. For All Models Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold VIH 0.7 (VDD1 or VDD2) V Logic Low Input Threshold VIL 0.3 (VDD1 or VDD2) V
Logic High Output Voltages VOAH, VOBH (VDD1 or VDD2) − 0.1 VDD1 or VDD2 V IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.5 (VDD1 or VDD2) − 0.2 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL 0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.04 0.1 V IOx = 400 μA, VIx = VIxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM120xWSRZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 1000 ns Maximum Data Rate3 1 Mbps
Propagation Delay4 tPHL, tPLH 15 150 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns Propagation Delay Skew5 tPSK 50 ns
Channel-to-Channel Matching6 tPSKCD/
tPSKOD
50 ns Output Rise/Fall Time (10% to 90%) tR/tF 3 ns
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 18 of 28 Parameter Symbol Min Typ Max Unit Test Conditions ADuM120xWTRZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 100 ns Maximum Data Rate3 10 Mbps Propagation Delay4 tPHL, tPLH 15 55 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C
Propagation Delay Skew5 tPSK 22 ns
Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 22 ns
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns ADuM120xWURZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 20 40 ns Maximum Data Rate3 25 50 Mbps Propagation Delay4 tPHL, tPLH 20 50 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C
Propagation Delay Skew5 tPSK 15 ns
Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 15 ns
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns For All Models Common-Mode Transient Immunity Logic High Output7 |CMH| 25 35 kV/μs VIx = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V Logic Low Output7 |CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V Refresh Rate fr 1.1 Mbps Input Dynamic Supply Current per Channel8
IDDI (D) 0.10 mA/ Mbps
Output Dynamic Supply Current per Channel8
IDDO (D) 0.05 mA/ Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1200W and ADuM1201W channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate.
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 19 of 28 PACKAGE CHARACTERISTICS Table 8.
Parameter Symbol Min Typ Max Unit Test Conditions Resistance (Input-to-Output)1 RI-O 1012 Ω Capacitance (Input-to-Output)1 CI-O 1.0 pF f = 1 MHz Input Capacitance CI 4.0 pF IC Junction-to-Case Thermal Resistance, Side 1 θJCI 46 °C/W Thermocouple located at center of package underside IC Junction-to-Case Thermal Resistance, Side 2 θJCO 41 °C/W 1 The device is considered a 2-terminal device; Pin 1, Pin, 2, Pin 3, and Pin 4 are shorted together, and Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together.
REGULATORY INFORMATION
The ADuM1200/ADuM1201 and ADuM1200W/ADuM1201W are approved by the organizations listed in Table 9; refer to Table 14 and
the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.
Table 9.
UL CSA VDE Recognized Under 1577 Component Recognition Program1
Approved under CSA Component Acceptance Notice #5A; approval pending for ADuM1200W/
ADuM1201W automotive 125°C temperature grade
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-122
Single/Basic 2500 V rms Isolation Voltage Basic insulation per CSA 60950-1-03 and
IEC 60950-1, 400 V rms (566 peak) maximum working voltage Functional insulation per CSA 60950-1-03 and
IEC 60950-1, 800 V rms (1131 V peak) maximum
working voltage Reinforced insulation, 560 V peak
File E214100 File 205078 File 2471900-4880-0001
1 In accordance with UL 1577, each ADuM120x is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 μA). 2 In accordance with DIN V VDE V 0884-10, each ADuM120x is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 10.
Parameter Symbol Value Unit Conditions Rated Dielectric Insulation Voltage 2500 V rms 1 minute duration
Minimum External Air Gap (Clearance) L(I01) 4.90 min mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I02) 4.01 min mm Measured from input terminals to output terminals, shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 20 of 28
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 INSULATION CHARACTERISTICS
This isolator is suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. Note that the asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage.
Table 11.
Description
Conditions
Symbol
Characteristic
Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
I to IV
For Rated Mains Voltage ≤ 300 V rms
I to III
For Rated Mains Voltage ≤ 400 V rms
I to II
Climatic Classification
40/105/21
Pollution Degree per DIN VDE 0110, Table 1
2
Maximum Working Insulation Voltage
VIORM
560
V peak
Input-to-Output Test Voltage, Method B1
VIORM × 1.875 = VPR, 100% production test, tm = 1 second, partial discharge < 5 pC
VPR
1050
V peak
Input-to-Output Test Voltage, Method A
VIORM × 1.6 = VPR, tm = 60 seconds, partial discharge < 5 pC
VPR
After Environmental Tests Subgroup 1
896
V peak
After Input and/or Safety Test Subgroup 2 and Subgroup 3
VIORM × 1.2 = VPR, tm = 60 seconds, partial discharge < 5 pC
672
V peak
Highest Allowable Overvoltage
Transient overvoltage, tTR = 10 seconds
VTR
4000
V peak
Safety-Limiting Values
Maximum value allowed in the event of a failure (see Figure 3)
Case Temperature
TS
150
°C
Side 1 Current
IS1
160
mA
Side 2 Current
IS2
170
mA
Insulation Resistance at TS
VIO = 500 V
RS
>109
Ω
CASE TEMPERATURE (°C)SAFETY-LIMITING CURRENT (mA)002001801008060402050100150200SIDE #1SIDE #204642-003120140160
Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting Values on Case Temperature per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 12. Parameter
Rating
Operating Temperature (TA)
−40°C to +105°C
Operating Temperature (TA)2
−40°C to +125°C
Supply Voltages (VDD1, VDD2)1, 3
2.7 V to 5.5 V
Supply Voltages (VDD1, VDD2)23
3.0 V to 5.5 V
Input Signal Rise and Fall Times
1.0 ms
Does not apply to ADuM1200W and ADuM1201W automotive grade products. 2 Applies to
ADuM1200W and ADuM1201W automotive grade products. 3 All voltages are relative to their respective ground. See the DC Correctnes
s unity to externamagnetic fields.
and Magnetic Field Immunity section for information on imml
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 21 of 28
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 13.
Parameter
Rating
Storage Temperature (TST)
−55°C to +150°C
Ambient Operating Temperature (TA)1
−40°C to +105°C
Ambient Operating Temperature (TA)2
−40°C to +125°C
Supply Voltages (VDD1, VDD2)3
−0.5 V to +7.0 V
Input Voltages (VIA, VIB)3, 4
−0.5 V to VDDI + 0.5 V
Output Voltages (VOA, VOB)3, 4
−0.5 V to VDDO + 0.5 V
Average Output Current per Pin (IO)5
−11 mA to +11 mA
Common-Mode Transients (CML, CMH)6
−100 kV/μs to +100 kV/μs
1 Does not apply to ADuM1200W and ADuM1200W automotive grade products.
2 Applies to ADuM1200W and ADuM1201W automotive grade products.
3 All voltages are relative to their respective ground.
4 VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively.
5 See for maximum rated current values for various temperatures.
Figure 3
6 Refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the absolute maximum ratings can cause latch-up or permanent damage.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Table 14. Maximum Continuous Working Voltage1
Parameter
Max
Unit
Constraint
AC Voltage, Bipolar Waveform
565
V peak
50-year minimum lifetime
AC Voltage, Unipolar Waveform
Functional Insulation
1131
V peak
Maximum approved working voltage per IEC 60950-1
Basic Insulation
560
V peak
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
DC Voltage
Functional Insulation
1131
V peak
Maximum approved working voltage per IEC 60950-1
Basic Insulation
560
V peak
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 22 of 28 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 8
2 7
3 6
4 5
TOP VIEW
(Not to Scale)
ADuM1200
04642-004
VDD1
VIA
VIB
GND1
VDD2
VOA
VOB
GND2
04642-005
1 8
2 7
3 6
4 5
TOP VIEW
(Not to Scale)
ADuM1201
VDD1
VOA
VIB
GND1
VDD2
VIA
VOB
GND2
Figure 4. ADuM1200 Pin Configuration Figure 5. ADuM1201 Pin Configuration
Table 15. ADuM1200 Pin Function Descriptions
Pin
No. Mnemonic Description 1 VDD1 Supply Voltage for Isolator Side 1. 2 VIA Logic Input A.
3 VIB Logic Input B.
4 GND1 Ground 1. Ground Reference for Isolator Side 1. 5 GND2 Ground 2. Ground Reference for Isolator Side 2.
6 VOB Logic Output B.
7 VOA Logic Output A.
8 VDD2 Supply Voltage for Isolator Side 2. Table 16. ADuM1201 Pin Function Descriptions
Pin
No. Mnemonic Description 1 VDD1 Supply Voltage for Isolator Side 1. 2 VOA Logic Output A.
3 VIB Logic Input B.
4 GND1 Ground 1. Ground Reference for Isolator Side 1. 5 GND2 Ground 2. Ground Reference for Isolator Side 2. 6 VOB Logic Output B.
7 VIA Logic Input A.
8 VDD2 Supply Voltage for Isolator Side 2. Table 17. ADuM1200 Truth Table (Positive Logic)
VIA Input VIB Input VDD1 State VDD2 State VOA Output VOB Output Notes H H Powered Powered H H
L L Powered Powered L L
H L Powered Powered H L
L H Powered Powered L H
X X Unpowered Powered H H Outputs return to the input state within
1 μs of VDDI power restoration. X X Powered Unpowered Indeterminate Indeterminate Outputs return to the input state within
1 μs of VDDO power restoration. Table 18. ADuM1201 Truth Table (Positive Logic)
VIA Input VIB Input VDD1 State VDD2 State VOA Output VOB Output Notes H H Powered Powered H H
L L Powered Powered L L
H L Powered Powered H L
L H Powered Powered L H
X X Unpowered Powered Indeterminate H Outputs return to the input state within
1 μs of VDDI power restoration. X X Powered Unpowered H Indeterminate Outputs return to the input state within
1 μs of VDDO power restoration.
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 23 of 28
04642-006
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 6. Typical Input Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation
04642-007DATA RATE (
Mbps)00102030
Figure 7. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (No Output Load)
04642-0 DATA RATE (Mbps)0102030
Figure 8. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (15 pF Output Load)
04642-009DATA RATE (
Mbps)CURRENT (mA)0015105201020305V3V
Figure 9. Typical ADuM1200 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation
04642-010DATA RATE (
Mbps)CURRENT (mA)0032141020305V3V
Figure 10. Typical ADuM1200 VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation
04642-011DATA RATE (
Mbps)CURRENT (mA)00628101020305V3V4
Figure 11. Typical ADuM1201 VDD1 or VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 24 of 28 APPLICATIONS INFORMATION
PCB LAYOUT The ADuM120x digital isolators require no external interface
circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins. The capacitor value should be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and
the input power supply pin should not exceed 20 mm. See the AN-1109 Application Note for board layout guidelines. PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output can differ from the propagation delay
to a logic high output.
INPUT (VIx)
OUTPUT (VOx)
tPLH tPHL
50%
50%
04642-012
Figure 12. Propagation Delay Parameters Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount that the propagation delay differs between channels within a
single ADuM120x component. Propagation delay skew refers to the maximum amount that the propagation delay differs between multiple ADuM120x
components operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input send narrow (~1 ns) pulses to the decoder via the transformer. The
decoder is bistable and is therefore either set or reset by the pulses,
indicating input logic transitions. In the absence of logic transi-
tions of more than ~1 μs at the input, a periodic set of refresh
pulses indicative of the correct input state is sent to ensure dc
correctness at the output. If the decoder receives no internal pulses for more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output
is forced to a default state (see Table 17 and Table 18) by the
watchdog timer circuit. The ADuM120x are extremely immune to external magnetic
fields. The limitation on the magnetic field immunity of the ADuM120x is set by the condition in which induced voltage in
the receiving coil of the transformer is sufficiently large enough to either falsely set or reset the decoder. The following analysis
defines the conditions under which this can occur. The 3 V
operating condition of the ADuM120x is examined because it represents the most susceptible mode of operation. The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, therefore establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (−dβ/dt)ΣΠrn
2; n = 1, 2, … , N
where: β is the magnetic flux density (gauss).
N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm).
Given the geometry of the receiving coil in the ADuM120x and
an imposed requirement that the induced voltage be 50% at
most of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated, as shown in Figure 13.
MAGNETIC FIELD FREQUENCY (Hz)
100
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
0.001
1M
10
0.01
1k 10k 10M
0.1
1
100M 100k
04642-013
Figure 13. Maximum Allowable External Magnetic Flux Density
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 25 of 28
For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (and has the worst-case polarity), it reduces the received pulse from >1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder.
The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuM120x transformers. Figure 14 expresses these allowable current magnitudes as a function of frequency for selected distances. As seen, the ADuM120x are extremely immune and can be affected only by extremely large currents operating very close to the component at a high frequency. For the 1 MHz example, a 0.5 kA current would have to be placed 5 mm away from the ADuM120x to affect the operation of the component.
MAGNETIC FIELD FREQUENCY (Hz)MAXIMUM ALLOWABLE CURRENT (kA)10001001010.10.011k10k100M100k1M10MDISTANCE = 5mmDISTANCE = 1mDISTANCE = 100mm04642-014
Figure 14. Maximum Allowable Current for Various Current-to-ADuM120x Spacings
Note that, at combinations of strong magnetic fields and high frequencies, any loops formed by PCB traces can induce suffi-ciently large error voltages to trigger the threshold of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.
POWER CONSUMPTION
The supply current at a given channel of the ADuM120x isolator is a function of the supply voltage, the data rate of the channel, and the output load of the channel.
For each input channel, the supply current is given by
IDDI = IDDI (Q) f ≤ 0.5fr
IDDI = IDDI (D) × (2f − fr) + IDDI (Q) f > 0.5fr
For each output channel, the supply current is given by
IDDO = IDDO (Q) f ≤ 0.5fr
IDDO = (IDDO (D) + (0.5 × 10−3) × CLVDDO) × (2f − fr) + IDDO (Q) f > 0.5fr
where: IDDI (D), IDDO (D) are the input and output dynamic supply currents per channel (mA/Mbps). CL is the output load capacitance (pF). VDDO is the output supply voltage (V). f is the input logic signal frequency (MHz, half of the input data rate, NRZ signaling). fr is the input stage refresh rate (Mbps). IDDI (Q), IDDO (Q) are the specified input and output quiescent supply currents (mA).
To calculate the total IDD1 and IDD2 supply currents, the supply currents for each input and output channel corresponding to IDD1 and IDD2 are calculated and totaled. Figure 6 and Figure 7 provide per-channel supply currents as a function of data rate for an unloaded output condition. Figure 8 provides per-channel supply current as a function of data rate for a 15 pF output condition. Figure 9 through Figure 11 provide total VDD1 and VDD2 supply current as a function of data rate for ADuM1200 and ADuM1201 channel configurations.
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 26 of 28
In the case of unipolar ac or dc voltage, the stress on the insu-lation is significantly lower, which allows operation at higher working voltages yet still achieves a 50-year service life. The working voltages listed in Table 14 can be applied while main-taining the 50-year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage cases. Any cross- insulation voltage waveform that does not conform to Figure 16 or Figure 17 is to be treated as a bipolar ac waveform, and its peak voltage is to be limited to the 50-year lifetime voltage value listed in Table 14.
INSULATION LIFETIME
All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insu-lation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM120x.
Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Accel-eration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 14 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum CSA/VDE approved working volt-ages. In many cases, the approved working voltage is higher than the 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases.
Note that the voltage presented in Figure 16 is shown as sinu-soidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V. 0VRATED PEAK VOLTAGE04642-021
Figure 15. Bipolar AC Waveform
The insulation lifetime of the ADuM120x depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 15, Figure 16, and Figure 17 illustrate these different isolation voltage waveforms, respectively.
0VRATED PEAK VOLTAGE04642-022
Figure 16. Unipolar AC Waveform
Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the Analog Devices recommended maximum working voltage.
0VRATED PEAK VOLTAGE04642-023
Figure 17. DC Waveform
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 27 of 28 OUTLINE DIMENSIONS
CONTROLLINGDIMENSIONSAREINMILLIMETERS;INCHDIMENSIONS
(IN PARENTHESES)AREROUNDED-OFFMILLIMETEREQUIVALENTSFOR
REFERENCEONLYANDARENOTAPPROPRIATEFORUSEINDESIGN.
COMPLIANTTOJEDECSTANDARDSMS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25(0.0098)
0.10(0.0040)
1 4
8 5
5.00 (0.1968)
4.80 (0.1890)
4.00(0.1574)
3.80(0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51(0.0201)
0.31(0.0122)
COPLANARITY
0.10
Figure 18. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1, 2
Number
of Inputs, VDD1 Side
Number
of Inputs,
VDD2 Side
Maximum
Data Rate (Mbps)
Maximum Propagation Delay, 5 V (ns) Maximum
Pulse Width Distortion (ns)
Temperature
Range Package
Option3
ADuM1200AR 2 0 1 150 40 −40°C to +105°C R-8
ADuM1200ARZ 2 0 1 150 40 −40°C to +105°C R-8
ADuM1200ARZ-RL7 2 0 1 150 40 −40°C to +105°C R-8
ADuM1200BR 2 0 10 50 3 −40°C to +105°C R-8
ADuM1200BR-RL7 2 0 10 50 3 −40°C to +105°C R-8
ADuM1200BRZ 2 0 10 50 3 −40°C to +105°C R-8
ADuM1200BRZ-RL7 2 0 10 50 3 −40°C to +105°C R-8
ADuM1200CR 2 0 25 45 3 −40°C to +105°C R-8
ADuM1200CR-RL7 2 0 25 45 3 −40°C to +105°C R-8
ADuM1200CRZ 2 0 25 45 3 −40°C to +105°C R-8
ADuM1200CRZ-RL7 2 0 25 45 3 −40°C to +105°C R-8
ADuM1200WSRZ 2 0 1 150 40 −40°C to +125°C R-8
ADuM1200WSRZ-RL7 2 0 1 150 40 −40°C to +125°C R-8
ADuM1200WTRZ 2 0 10 50 3 −40°C to +125°C R-8
ADuM1200WTRZ-RL7 2 0 10 50 3 −40°C to +125°C R-8
ADuM1200WURZ 2 0 25 45 3 −40°C to +125°C R-8
ADuM1200WURZ-RL7 2 0 25 45 3 −40°C to +125°C R-8
ADuM1201AR 1 1 1 150 40 −40°C to +105°C R-8
ADuM1201AR-RL7 1 1 1 150 40 −40°C to +105°C R-8
ADuM1201ARZ 1 1 1 150 40 −40°C to +105°C R-8
ADuM1201ARZ-RL7 1 1 1 150 40 −40°C to +105°C R-8
ADuM1201BR 1 1 10 50 3 −40°C to +105°C R-8
ADuM1201BR-RL7 1 1 10 50 3 −40°C to +105°C R-8
ADuM1201BRZ 1 1 10 50 3 −40°C to +105°C R-8
ADuM1201BRZ-RL7 1 1 10 50 3 −40°C to +105°C R-8
ADuM1201CR 1 1 25 45 3 −40°C to +105°C R-8
ADuM1201CRZ 1 1 25 45 3 −40°C to +105°C R-8
ADuM1201CRZ-RL7 1 1 25 45 3 −40°C to +105°C R-8
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 28 of 28 Model1, 2
Number
of Inputs, VDD1 Side
Number
of Inputs, VDD2 Side
Maximum
Data Rate (Mbps)
Maximum Propagation Delay, 5 V (ns) Maximum
Pulse Width Distortion (ns)
Temperature
Range Package
Option3
ADuM1201WSRZ 1 1 1 150 40 −40°C to +125°C R-8
ADuM1201WSRZ-RL7 1 1 1 150 40 −40°C to +125°C R-8
ADuM1201WTRZ 1 1 10 50 3 −40°C to +125°C R-8
ADuM1201WTRZ-RL7 1 1 10 50 3 −40°C to +125°C R-8
ADuM1201WURZ 1 1 25 45 3 −40°C to +125°C R-8
ADuM1201WURZ-RL7 1 1 25 45 3 −40°C to +125°C R-8
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 R-8 = 8-lead narrow-body SOIC_N. AUTOMOTIVE PRODUCTS
The ADuM1200W/ADuM1201W models are available with controlled manufacturing to support the quality and reliability requirements
of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for
use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and
to obtain the specific Automotive Reliability reports for these models. ©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04642-0-3/12(I)
High Precision
5 V Reference
AD586
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
Laser trimmed to high accuracy
5.000 V ±2.0 mV (M grade)
Trimmed temperature coefficient
2 ppm/°C max, 0°C to 70°C (M grade)
5 ppm/°C max, −40°C to +85°C (B and L grades)
10 ppm/°C max, −55°C to +125°C (T grade)
Low noise, 100 nV/√Hz
Noise reduction capability
Output trim capability
MIL-STD-883-compliant versions available
Industrial temperature range SOICs available
Output capable of sourcing or sinking 10 mA
GENERAL DESCRIPTION
The AD586 represents a major advance in state-of-the-art monolithic voltage references. Using a proprietary ion-implanted buried Zener diode and laser wafer trimming of high stability thin-film resistors, the AD586 provides outstanding perform-ance at low cost.
The AD586 offers much higher performance than most other 5 V references. Because the AD586 uses an industry-standard pinout, many systems can be upgraded instantly with the AD586.
The buried Zener approach to reference design provides lower noise and drift than band gap voltage references. The AD586 offers a noise reduction pin that can be used to further reduce the noise level generated by the buried Zener.
The AD586 is recommended for use as a reference for 8-, 10-, 12-, 14-, or 16-bit DACs that require an external precision reference. The device is also ideal for successive approximation or integrating ADCs with up to 14 bits of accuracy and, in general, can offer better performance than the standard on-chip references.
The AD586J, AD586K, AD586L, and AD586M are specified for operation from 0°C to 70°C; the AD586A and AD586B are specified for −40°C to +85°C operation; and the AD586S and AD586T are specified for −55°C to +125°C operation.
The AD586J, AD586K, AD586L, and AD586M are available in an 8-lead PDIP; the AD586J, AD586K, AD586L, AD586A, and AD586B are available in an 8-lead SOIC package; and the AD586J, AD586K, AD586L, AD586S, and AD586T are available in an 8-lead CERDIP package. A1RSRZ1RZ2RFRTRIAD586GNDVINNOISE REDUCTIONVOUTTRIMNOTES1.PINS 1, 3, AND 7 ARE INTERNAL TEST POINTS.MAKE NO CONNECTIONS TO THESE POINTS.6548200529-001
Figure 1.
PRODUCT HIGHLIGHTS
1. Laser trimming of both initial accuracy and temperature coefficients results in very low errors over temperature without the use of external components. The AD586M has a maximum deviation from 5.000 V of ±2.45 mV between 0°C and 70°C, and the AD586T guarantees ±7.5 mV maximum total error between −55°C and +125°C.
2. For applications requiring higher precision, an optional fine-trim connection is provided.
3. Any system using an industry-standard pinout reference can be upgraded instantly with the AD586.
4. Output noise of the AD586 is very low, typically 4 μV p-p. A noise reduction pin is provided for additional noise filtering using an external capacitor.
5. The AD586 is available in versions compliant with MIL-STD-883. Refer to the Analog Devices Military Products Databook or the current AD586/883B data sheet for detailed specifications.
AD586
Rev. G | Page 2 of 16
TABLE OF CONTENTS
Specifications.....................................................................................3
AD586J, AD586K/AD586A, AD586L/AD586B.......................3
AD586M, AD586S, AD586T.......................................................4
Absolute Maximum Ratings............................................................5
ESD Caution..................................................................................5
Pin Configurations and Function Descriptions...........................6
Theory of Operation........................................................................7
Applying the AD586.....................................................................7
Noise Performance and Reduction............................................7
Turn-on Time................................................................................8
Dynamic Performance.................................................................8
Load Regulation............................................................................9
Temperature Performance............................................................9
Negative Reference Voltage from an AD586...........................10
Using the AD586 with Converters...........................................10
5 V Reference with Multiplying CMOS DACs or ADCs......11
Stacked Precision References for Multiple Voltages..............11
Precision Current Source..........................................................11
Precision High Current Supply................................................11
Outline Dimensions.......................................................................13
Ordering Guide..........................................................................14
REVISION HISTORY
3/05—Rev. F to Rev. G Updated Format..................................................................Universal Split Specifications Table into Table 1 and Table 2.......................3 Changes to Table 1............................................................................3 Added Figure 2 and Figure 4...........................................................6 Updated Outline Dimensions.......................................................13 Changes to Ordering Guide..........................................................14
1/04—Rev. E to Rev. F Changes to ORDERING GUIDE...................................................3
7/03—Rev. D to Rev. E Removed AD586J CHIPS..................................................Universal Updated ORDERING GUIDE........................................................3 Change to Figure 3...........................................................................4 Updated Figure 12............................................................................7 Updated OUTLINE DIMENSIONS..............................................9
4/01—Rev. C to Rev. D Changed Figure 10 to Table 1 (Maximum Output Change in mV)...............................................6
11/95—Revision 0: Initial Version
AD586
Rev. G | Page 3 of 16
SPECIFICATIONS
AD586J, AD586K/AD586A, AD586L/AD586B
@ TA = 25°C, VIN = 15 V, unless otherwise noted. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All minimum and maximum specifications are guaranteed, although only those shown in boldface are tested on all production units, unless otherwise specified.
Table 1.
AD586J
AD586K/AD586A
AD586L/AD586B
Parameter
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
OUTPUT VOLTAGE
4.980
5.020
4.995
5.005
4.9975
5.0025
V
OUTPUT VOLTAGE DRIFT1
0°C to 70°C
25
15
5
ppm/°C
−55°C to +125°C
ppm/°C
GAIN ADJUSTMENT
+6
+6
+6
%
−2
−2
−2
%
LINE REGULATION1
10.8 V < + VIN < 36 V
TMIN to TMAX
±100
±100
±100
μV/V
11.4 V < +VIN < 36 V
TMIN to TMAX
μV/V
LOAD REGULATION1
Sourcing 0 mA < IOUT < 10 mA
25°C
100
100
100
μV/mA
TMIN to TMAX
100
100
100
μV/mA
Sinking −10 mA < IOUT < 0 mA
25°C
400
400
400
μV/mA
QUIESCENT CURRENT
2
3
2
3
2
3
mA
POWER CONSUMPTION
30
30
30
mW
OUTPUT NOISE
0.1 Hz to 10 Hz
4
4
4
μV p-p
Spectral Density, 100 Hz
100
100
100
nV/√Hz
LONG-TERM STABILITY
15
15
15
ppm/1000 hr
SHORT-CIRCUIT CURRENT-TO-GROUND
45
60
45
60
45
60
mA
TEMPERATURE RANGE
Specified Performance2
0
70
0
−40
(K grade)
(A grade)
70
+85
0
−40
(L grade)
(B grade)
70
+85
°C
°C
Operating Performance3
−40
+85
−40
+85
−40
+85
°C
1 Maximum output voltage drift is guaranteed for all packages and grades. CERDIP packaged parts are also 100°C production tested.
2 Lower row shows specified performance for A and B grades.
3 The operating temperature range is defined as the temperature extremes at which the device will still function. Parts may deviate from their specified performance outside their specified temperature range.
AD586
Rev. G | Page 4 of 16
AD586M, AD586S, AD586T
@ TA = 25°C, VIN = 15 V, unless otherwise noted. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All minimum and maximum specifications are guaranteed, although only those shown in boldface are tested on all production units, unless otherwise specified.
Table 2.
AD586M
AD586S
AD586T
Parameter
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
OUTPUT VOLTAGE
4.998
5.002
4.990
5.010
4.9975
5.0025
V
OUTPUT VOLTAGE DRIFT1
0°C to 70°C
2
ppm/°C
−55°C to +125°C
20
10
ppm/°C
GAIN ADJUSTMENT
+6
+6
+6
%
−2
−2
−2
%
LINE REGULATION1
10.8 V < +VIN < 36 V
TMIN to TMAX
±100
μV/V
11.4 V < +VIN < 36 V
TMIN to TMAX
±150
±150
μV/V
LOAD REGULATION1
Sourcing 0 mA < IOUT < 10 mA
25°C
100
150
150
μV/mA
TMIN to TMAX
100
150
150
μV/mA
Sinking −10 mA < IOUT < 0 mA
25°C
400
400
400
μV/mA
QUIESCENT CURRENT
2
3
2
3
2
3
mA
POWER CONSUMPTION
30
30
30
mW
OUTPUT NOISE
0.1 Hz to 10 Hz
4
4
4
μV p-p
Spectral Density, 100 Hz
100
100
100
nV/√Hz
LONG-TERM STABILITY
15
15
15
ppm/1000 hr
SHORT-CIRCUIT CURRENT-TO-GROUND
45
60
45
60
45
60
mA
TEMPERATURE RANGE
Specified Performance2
0
70
−55
+125
−55
+125
°C
Operating Performance3
−40
+85
−55
+125
−55
+125
°C
1 Maximum output voltage drift is guaranteed for all packages and grades. CERDIP packaged parts are also 100°C production tested.
2 Lower row shows specified performance for A and B grades.
3 The operating temperature range is defined as the temperature extremes at which the device will still function. Parts may deviate from their specified performance outside their specified temperature range.
AD586
Rev. G | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
VIN to Ground
36 V
Power Dissipation (25°C)
500 mW
Storage Temperature
−65°C to +150°C
Lead Temperature (Soldering, 10 sec)
300°C
Package Thermal Resistance
θJC
22°C/W
θJA
110°C/W
Output Protection
Output safe for indefinite short to ground or VIN.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
AD586
Rev. G | Page 6 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1TP DENOTES FACTORY TEST POINT.NO CONNECTIONS, EXCEPT DUMMY PCB PAD,SHOULD BE MADE TO THESE POINTS.TP11VIN2TP13GND4NOISEREDUCTION8TP17VOUT6TRIM5AD586TOP VIEW(Not to Scale)00529-002
Figure 2. Pin Configuration (N-8)
1TP DENOTES FACTORY TEST POINT.NO CONNECTIONS, EXCEPT DUMMY PCB PAD,SHOULD BE MADE TO THESE POINTS.00529-003TP11VIN2TP13GND4NOISEREDUCTION8TP17VOUT6TRIM5AD586TOP VIEW(Not to Scale)
Figure 3. Pin Configuration (Q-8)
1TP DENOTES FACTORY TEST POINT.NO CONNECTIONS, EXCEPT DUMMY PCB PAD,SHOULD BE MADE TO THESE POINTS.00529-004TP11VIN2TP13GND4NOISEREDUCTION8TP17VOUT6TRIM5AD586TOP VIEW(Not to Scale)
Figure 4. Pin Configuration (R-8)
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
TP1
Factory Trim Pad (No Connect).
2
VIN
Input Voltage.
3
TP1
Factory Trim Pad (No Connect).
4
GND
Ground.
5
TRIM
Optional External Fine Trim. See the Applying the AD586 section.
6
VOUT
Output Voltage.
7
TP1
Factory Trim Pad (No Connect).
8
NOICE REDUCTION
Optional Noise Reduction Filter with External 1μF Capacitor to Ground.
AD586
Rev. G | Page 7 of 16
THEORY OF OPERATION
The AD586 consists of a proprietary buried Zener diode refer-ence, an amplifier to buffer the output, and several high stability thin-film resistors, as shown in the block diagram in Figure 5. This design results in a high precision monolithic 5 V output reference with initial offset of 2.0 mV or less. The temperature compensation circuitry provides the device with a temperature coefficient of under 2 ppm/°C.
Using the bias compensation resistor between the Zener output and the noninverting input to the amplifier, a capacitor can be added at the noise reduction pin (Pin 8) to form a low-pass filter and reduce the noise contribution of the Zener to the circuit. A1RSRZ1RZ2RFRTRIAD586GNDVINNOISE REDUCTIONVOUTTRIMNOTES1.PINS 1, 3, AND 7 ARE INTERNAL TEST POINTS.MAKE NO CONNECTIONS TO THESE POINTS.6548200529-001
Figure 5. Functional Block Diagram
APPLYING THE AD586
The AD586 is simple to use in virtually all precision reference applications. When power is applied to Pin 2 and Pin 4 is grounded, Pin 6 provides a 5 V output. No external components are required; the degree of desired absolute accuracy is achieved simply by selecting the required device grade. The AD586 requires less than 3 mA quiescent current from an operating supply of 12 V or 15 V.
An external fine trim may be desired to set the output level to exactly 5.000 V (calibrated to a main system reference). System calibration may also require a reference voltage that is slightly different from 5.000 V, for example, 5.12 V for binary applica-tions. In either case, the optional trim circuit shown in Figure 6 can offset the output by as much as 300 mV with minimal effect on other device characteristics. AD586GNDVINCN1μFVOTRIMOPTIONALNOISEREDUCTIONCAPACITORVINNOISEREDUCTIONOUTPUT10kΩ6524800529-005
Figure 6. Optional Fine-Trim Configuration
NOISE PERFORMANCE AND REDUCTION
The noise generated by the AD586 is typically less than 4 μV p-p over the 0.1 Hz to 10 Hz band. Noise in a 1 MHz bandwidth is approximately 200 μV p-p. The dominant source of this noise is the buried Zener, which contributes approximately 100 nV/√Hz. By comparison, contribution by the op amp is negligible. Figure 7 shows the 0.1 Hz to 10 Hz noise of a typical AD586. The noise measurement is made with a band-pass filter made of a 1-pole high-pass filter with a corner frequency at 0.1 Hz, and a 2-pole low-pass filter with a corner frequency at 12.6 Hz, to create a filter with a 9.922 Hz bandwidth.
If further noise reduction is desired, an external capacitor can be added between the noise reduction pin and ground, as shown in Figure 6. This capacitor, combined with the 4 kΩ RS and the Zener resistances, forms a low-pass filter on the output of the Zener cell. A 1 μF capacitor will have a 3 dB point at 12 Hz, and will reduce the high frequency (to 1 MHz) noise to about 160 μV p-p. Figure 8 shows the 1 MHz noise of a typical AD586, both with and without a 1 μF capacitor. 00529-0061μF5s1μF
Figure 7. 0.1 Hz to 10 Hz Noise
AD586
Rev. G | Page 8 of 16
00529-007CN =
1μFNO CN50μS200μV
Figure 8. Effect of 1 μF Noise Reduction Capacitor on Broadband Noise
TURN-ON TIME
Upon application of power (cold start), the time required for the output voltage to reach its final value within a specified error band is defined as the turn-on settling time. Two compo-nents normally associated with this are the time for the active circuits to settle, and the time for the thermal gradients on the chip to stabilize. Figure 9, Figure 10, and Figure 11 show the turn-on characteristics of the AD586. It shows the settling to be about 60 μs to 0.01%. Note the absence of any thermal tails when the horizontal scale is expanded to l ms/cm in Figure 10.
Output turn-on time is modified when an external noise reduc-tion capacitor is used. When present, this capacitor acts as an additional load to the current source of the internal Zener diode, resulting in a somewhat longer turn-on time. In the case of a 1 μF capacitor, the initial turn-on time is approximately 400 ms to 0.01% (see Figure 11). 00529-008VINVOUT10V1mV20μS
Figure 9. Electrical Turn-On 00529-009VINVOUT10V5V1mS
Figure 10. Extended Time Scale 00529-010VINVOUT10V1mV100mS
Figure 11. Turn-On with 1μF CN Characteristics
DYNAMIC PERFORMANCE
The output buffer amplifier is designed to provide the AD586 with static and dynamic load regulation superior to less com-plete references.
Many ADCs and DACs present transient current loads to the reference, and poor reference response can degrade the per-formance of the converter.
Figure 12, Figure 13, and Figure 14 display the characteristics of the AD586 output amplifier driving a 0 mA to 10 mA load. AD586VL5V0VVOUT500Ω3.5V00529-011
Figure 12. Transient Load Test Circuit
AD586
Rev. G | Page 9 of 16
00529-012VLVOUT5V50mV1μS
Figure 13. Large-Scale Transient Response 00529-013VLVOUT5V1mV2μS
Figure 14. Fine-Scale Setting for Transient Load
In some applications, a varying load may be both resistive and capacitive in nature, or the load may be connected to the AD586 by a long capacitive cable.
Figure 15 and Figure 16 display the output amplifier characteristics driving a 1000 pF, 0 mA to 10 mA load. AD586VL5V0VVOUTCL1000pF500Ω3.5V00529-014
Figure 15. Capacitive Load Transient Response Test Circuit
00529-015CL= 0CL= 1000pF5V200mV1μS
Figure 16. Output Response with Capacitive Load
LOAD REGULATION
The AD586 has excellent load regulation characteristics. Figure 17 shows that varying the load several mA changes the output by a few μV. The AD586 has somewhat better load regulation per-formance sourcing current than sinking current. –6–4–2246810LOAD (mA)0–500–10005001000ΔVOUT (μV)00529-016
Figure 17. Typical Load Regulation Characteristics
TEMPERATURE PERFORMANCE
The AD586 is designed for precision reference applications where temperature performance is critical. Extensive tempera-ture testing ensures that the device maintains a high level of performance over the operating temperature range.
Some confusion exists with defining and specifying reference voltage error over temperature. Historically, references have been characterized using a maximum deviation per degree Celsius, that is, ppm/°C. However, because of nonlinearities in temperature characteristics that originated in standard Zener references (such as “S” type characteristics), most manufacturers have begun to use a maximum limit error band approach to specify devices. This technique involves measuring the output at three or more different temperatures to specify an output volt-age error band.
AD586
Rev. G | Page 10 of 16
Figure 18 shows the typical output voltage drift for the AD586L and illustrates the test methodology. The box in Figure 18 is bounded on the sides by the operating temperature extremes and on the top and the bottom by the maximum and minimum output voltages measured over the operating temperature range. The slope of the diagonal drawn from the lower left to the upper right corner of the box determines the performance grade of the device. –200204060805.0035.000TEMPERATURE (°C) VMINVMAXVMAX–VMIN(TMAX–TMIN)×5×10–6SLOPETMINTMAXSLOPE = T.C. ===4.3ppm/°C5.0027– 5.0012(70°C– 0)×5×10–600625-017
Figure 18. Typical AD586L Temperature Drift
Each AD586J, AD586K, and AD586L grade unit is tested at 0°C, 25°C, and 70°C. Each AD586SQ and AD586TQ grade unit is tested at −55°C, +25°C, and +125°C. This approach ensures that the variations of output voltage that occur as the temperature changes within the specified range will be contained within a box whose diagonal has a slope equal to the maximum specified drift. The position of the box on the vertical scale will change from device to device as initial error and the shape of the curve vary. The maximum height of the box for the appropriate tem-perature range and device grade is shown in Table 5. Dupli-cation of these results requires a combination of high accuracy and stable temperature control in a test system. Evaluation of the AD586 will produce a curve similar to that in Figure 18, but output readings could vary depending on the test methods and equipment used.
Table 5. Maximum Output Change in mV
Maximum Output Change (mV)
Device Grade
0°C to 70°C
−40°C to +85°C
−55°C to +125°C
AD586J
8.75
AD586K
5.25
AD586L
1.75
AD586M
0.70
AD586A
9.37
AD586B
3.12
AD586S
18.00
AD586T
9.00
NEGATIVE REFERENCE VOLTAGE FROM AN AD586
The AD586 can be used to provide a precision −5.000 V output, as shown in Figure 19. The VIN pin is tied to at least a 6 V supply, the output pin is grounded, and the AD586 ground pin is con-nected through a resistor, RS, to a −15 V supply. The −5 V output is now taken from the ground pin (Pin 4) instead of VOUT. It is essential to arrange the output load and the supply resistor, RS, so that the net current through the AD586 is between 2.5 mA and 10.0 mA. The temperature characteristics and long-term stability of the device will be essentially the same as that of a unit used in the standard +5 V output configuration. AD586GND+6V→+30V2.5mA <–IL< 10mA10VRS–5VRSVOUTVINIL–15V24600529-018
Figure 19. AD586 as a Negative 5 V Reference
USING THE AD586 WITH CONVERTERS
The AD586 is an ideal reference for a wide variety of 8-, 12-, 14-, and 16-bit ADCs and DACs. Several representative examples are explained in the following sections.
AD586
Rev. G | Page 11 of 16
5 V REFERENCE WITH MULTIPLYING CMOS DACs OR ADCs
The AD586 is ideal for applications with 10- and 12-bit multiplying CMOS DACs. In the standard hookup, as shown in Figure 20, the AD586 is paired with the AD7545 12-bit multiplying DAC and the AD711 high speed BiFET op amp. The amplifier DAC configuration produces a unipolar 0 V to −5 V output range. Bipolar output applications and other operating details can be found in the individual product data sheets. AD586GNDVOUTVINAD711K0.1μF0.1μF–15V0VTO–5V+15VOUT 1AGNDDGNDDB11TODB0C133pFR268ΩRFB+15VVDDAD7545KVREF10kΩVOUTTRIM+15V20181965423127463200529-019
Figure 20. Low Power 12-Bit CMOS DAC Application
The AD586 can also be used as a precision reference for multi-ple DACs. Figure 21 shows the AD586, the AD7628 dual DAC, and the AD712 dual op amp hooked up for single-supply opera-tion to produce 0 V to −5 V outputs. Because both DACs are on the same die and share a common reference and output op amps, the DAC outputs will exhibit similar gain TCs. AD586GNDAD712OUT ADGNDAGNDDACADB0DB7DATAINPUTSOUT BDACBRFB BRFB AVREFAVREFBAD7628VINVOUTA=0TO–5VVOUTB=0TO–5VVOUT+15V+15V64471425317119202400529-020
Figure 21. AD586 as a 5 V Reference for a CMOS
STACKED PRECISION REFERENCES FOR MULTIPLE VOLTAGES
Often, a design requires several reference voltages. Three AD586s can be stacked, as shown in Figure 22, to produce 5.000 V, 10.000 V, and 15.000 V outputs. This scheme can be extended to any number of AD586s, provided the maximum load current is not exceeded. This design provides the addi-tional advantage of improved line regulation on the 5.0 V output. Changes in VIN of 18 V to 50 V produce output changes that are below the noise level of the references. 22V TO 46VAD586GNDVOUTVINTRIM10kΩAD586GNDVOUTVINTRIMAD586GNDVOUTVINTRIM10kΩ10kΩ15V10V5V24562456245600529-021
Figure 22. Multiple AD586s Stacked for Precision 5 V, 10 V, and 15 V Outputs
PRECISION CURRENT SOURCE
The design of the AD586 allows it to be easily configured as a current source. By choosing the control resistor RC in Figure 23, the user can vary the load current from the quiescent current (typically, 2 mA) to approximately 10 mA. The compliance volt-age of this circuit varies from about 5 V to 21 V, depending on the value of VIN. AD586GNDVOUTVIN5VRCIL = + IBIAS+VINRC(500Ω MIN)24600529-022
Figure 23. Precision Current Source
PRECISION HIGH CURRENT SUPPLY
For higher currents, the AD586 can easily be connected to a power PNP or power Darlington PNP device. The circuit in Figure 24 and Figure 25 can deliver up to 4 amps to the load. The 0.1 μF capacitor is required only if the load has a significant capacitive component. If the load is purely resistive, improved high frequency supply rejection results can be obtained by removing the capacitor.
AD586
Rev. G | Page 12 of 16
AD586GNDVOUTVIN5VRCIL = + IBIASRC0.1μF15V220Ω2N628526400529-023
Figure 24. Precision High Current Current Source
VOUT5V @ 4 AMPSAD586GNDVOUTVIN0.1μF15V220Ω2N628526400529-024
Figure 25. Precision High Current Voltage Source
AD586
Rev. G | Page 13 of 16
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-001-BA0.022 (0.56)0.018 (0.46)0.014 (0.36)SEATINGPLANE0.015(0.38)MIN0.210(5.33)MAXPIN 10.150 (3.81)0.130 (3.30)0.115 (2.92)0.070 (1.78)0.060 (1.52)0.045 (1.14)81450.280 (7.11)0.250 (6.35)0.240 (6.10)0.100 (2.54)BSC0.400 (10.16)0.365 (9.27)0.355 (9.02)0.060 (1.52)MAX0.430 (10.92)MAX0.014 (0.36)0.010 (0.25)0.008 (0.20)0.325 (8.26)0.310 (7.87)0.300 (7.62)0.195 (4.95)0.130 (3.30)0.115 (2.92)0.015 (0.38)GAUGEPLANE0.005 (0.13)MINCONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 26. 8-Lead Plastic Dual In-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.14580.310 (7.87)0.220 (5.59)0.005 (0.13)MIN0.055 (1.40)MAX0.100 (2.54) BSC15° 0°0.320 (8.13)0.290 (7.37)0.015 (0.38)0.008 (0.20)SEATINGPLANE0.200 (5.08)MAX0.405 (10.29) MAX0.150 (3.81)MIN0.200 (5.08)0.125 (3.18)0.023 (0.58)0.014 (0.36)0.070 (1.78)0.030 (0.76)0.060 (1.52)0.015 (0.38)PIN 1
Figure 27. 8-Lead Ceramic Dual In-Line Package [CERDIP] (Q-8) Dimensions shown in inches and (millimeters) 0.25 (0.0098)0.17 (0.0067)1.27 (0.0500)0.40 (0.0157)0.50 (0.0196)0.25 (0.0099)× 45°8°0°1.75 (0.0688)1.35 (0.0532)SEATINGPLANE0.25 (0.0098)0.10 (0.0040)41855.00 (0.1968)4.80 (0.1890)4.00 (0.1574)3.80 (0.1497)1.27 (0.0500)BSC6.20 (0.2440)5.80 (0.2284)0.51 (0.0201)0.31 (0.0122)COPLANARITY0.10CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FORREFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGNCOMPLIANT TO JEDEC STANDARDS MS-012AA
Figure 28. 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
AD586
Rev. G | Page 14 of 16
ORDERING GUIDE
Model
Initial Error
Temperature Coefficient
Temperature Range
Package Description
Package Option
Quantity Per Reel
AD586JN
20 mV
25 ppm/°C
0°C to 70°C
PDIP
N-8
AD586JNZ1
20 mV
25 ppm/°C
0°C to 70°C
PDIP
N-8
AD586JQ
20 mV
25 ppm/°C
0°C to 70°C
CERDIP
Q-8
AD586JR
20 mV
25 ppm/°C
0°C to 70°C
SOIC
R-8
AD586JR-REEL7
20 mV
25 ppm/°C
0°C to 70°C
SOIC
R-8
1,000
AD586JRZ1
20 mV
25 ppm/°C
0°C to 70°C
SOIC
R-8
AD586JRZ-REEL71
20 mV
25 ppm/°C
0°C to 70°C
SOIC
R-8
1,000
AD586KN
5 mV
15 ppm/°C
0°C to 70°C
PDIP
N-8
AD586KNZ1
5 mV
15 ppm/°C
0°C to 70°C
PDIP
N-8
AD586KQ
5 mV
15 ppm/°C
0°C to 70°C
CERDIP
Q-8
AD586KR
5 mV
15 ppm/°C
0°C to 70°C
SOIC
R-8
AD586KR-REEL
5 mV
15 ppm/°C
0°C to 70°C
SOIC
R-8
2,500
AD586KR-REEL7
5 mV
15 ppm/°C
0°C to 70°C
SOIC
R-8
1,000
AD586KRZ1
5 mV
15 ppm/°C
0°C to 70°C
SOIC
R-8
AD586KRZ-REEL1
5 mV
15 ppm/°C
0°C to 70°C
SOIC
R-8
2,500
AD586KRZ-REEL71
5 mV
15 ppm/°C
0°C to 70°C
SOIC
R-8
1,000
AD586LN
2.5 mV
5 ppm/°C
0°C to 70°C
PDIP
N-8
AD586LNZ1
2.5 mV
5 ppm/°C
0°C to 70°C
PDIP
N-8
AD586LR
2.5 mV
5 ppm/°C
0°C to 70°C
SOIC
R-8
AD586LR-REEL
2.5 mV
5 ppm/°C
0°C to 70°C
SOIC
R-8
2,500
AD586LR-REEL7
2.5 mV
5 ppm/°C
0°C to 70°C
SOIC
R-8
1,000
AD586LRZ1
2.5 mV
5 ppm/°C
0°C to 70°C
SOIC
R-8
AD586LRZ-REEL1
2.5 mV
5 ppm/°C
0°C to 70°C
SOIC
R-8
2,500
AD586LRZ-REEL71
2.5 mV
5 ppm/°C
0°C to 70°C
SOIC
R-8
1,000
AD586MN
2 mV
2 ppm/°C
0°C to 70°C
PDIP
N-8
AD586MNZ1
2 mV
2 ppm/°C
0°C to 70°C
PDIP
N-8
AD586AR
5 mV
15 ppm/°C
−40°C to +85°C
SOIC
R-8
AD586AR-REEL
5 mV
15 ppm/°C
−40°C to +85°C
SOIC
R-8
2,500
AD586ARZ1
5 mV
15 ppm/°C
−40°C to +85°C
SOIC
R-8
AD586ARZ-REEL1
5 mV
15 ppm/°C
−40°C to +85°C
SOIC
R-8
2,500
AD586ARZ-REEL71
5 mV
15 ppm/°C
−40°C to +85°C
SOIC
R-8
1,000
AD586BR
2.5 mV
5 ppm/°C
−40°C to +85°C
SOIC
R-8
AD586BR-REEL7
2.5 mV
5 ppm/°C
−40°C to +85°C
SOIC
R-8
1,000
AD586BRZ1
2.5 mV
5 ppm/°C
−40°C to +85°C
SOIC
R-8
AD586BRZ-REEL1
2.5 mV
5 ppm/°C
−40°C to +85°C
SOIC
R-8
2,500
AD586BRZ-REEL71
2.5 mV
5 ppm/°C
−40°C to +85°C
SOIC
R-8
1,000
AD586LQ
2.5 mV
5 ppm/°C
0°C to 70°C
CERDIP
Q-8
AD586SQ
10 mV
20 ppm/°C
−55°C to +125°C
CERDIP
Q-8
AD586TQ
2.5 mV
10 ppm/°C
−55°C to +125°C
CERDIP
Q-8
AD586TQ/883B2
2.5 mV
10 ppm/°C
−55°C to +125°C
CERDIP
Q-8
1 Z = Pb-free part.
2 For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or the current AD586/883B data sheet.
AD586
Rev. G | Page 15 of 16
NOTES
AD586
Rev. G | Page 16 of 16
NOTES
February 2004 Digital Audio Products
Data Manual
SLWS106H
iii
Contents
Section Title Page
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1
1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3
1.3 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−4
1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−5
1.5 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−5
2 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1
2.1 Absolute Maximum Ratings Over Operating Free-Air Temperature
Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1
2.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1
2.3 Electrical Characteristics Over Recommended Operating
Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2
2.3.1 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2
2.3.2 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−3
2.3.3 Analog Line Input to Line Output (Bypass) . . . . . . . . . . . . . 2−3
2.3.4 Stereo Headphone Output . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−4
2.3.5 Analog Reference Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−4
2.3.6 Digital I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−4
2.3.7 Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−4
2.4 Digital-Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−5
2.4.1 Audio Interface (Master Mode) . . . . . . . . . . . . . . . . . . . . . . . 2−5
2.4.2 Audio Interface (Slave-Mode) . . . . . . . . . . . . . . . . . . . . . . . . 2−6
2.4.3 Three-Wire Control Interface (SDIN) . . . . . . . . . . . . . . . . . . 2−7
2.4.4 Two-Wire Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−7
3 How to Use the TLV320AIC23B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
3.1 Control Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
3.1.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
3.1.2 2-Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
3.1.3 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2
3.2 Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5
3.2.1 Line Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5
3.2.2 Microphone Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6
3.2.3 Line Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6
3.2.4 Headphone Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6
3.2.5 Analog Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
3.2.6 Sidetone Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
3.3 Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
3.3.1 Digital Audio-Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . 3−7
iv
3.3.2 Audio Sampling Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−9
3.3.3 Digital Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 3−11
A Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A−1
v
List of Illustrations
Figure Title Page
2−1 System-Clock Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−5
2−2 Master-Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−5
2−3 Slave-Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−6
2−4 Three-Wire Control Interface Timing Requirements . . . . . . . . . . . . . . . . . . 2−7
2−5 Two-Wire Control Interface Timing Requirements . . . . . . . . . . . . . . . . . . . 2−7
3−1 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1
3−2 2-Wire Compatible Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2
3−3 Analog Line Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5
3−4 Microphone Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6
3−5 Right-Justified Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7
3−6 Left-Justified Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8
3−7 I2S Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8
3−8 DSP Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8
3−9 Digital De-Emphasis Filter Response − 44.1 kHz Sampling . . . . . . . . . . . 3−12
3−10 Digital De-Emphasis Filter Response − 48 kHz Sampling . . . . . . . . . . . . 3−12
3−11 ADC Digital Filter Response 0: USB Mode
(Group Delay = 12 Output Samples) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−13
3−12 ADC Digital Filter Ripple 0: USB
(Group Delay = 20 Output Samples) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−13
3−13 ADC Digital Filter Response 1: USB Mode Only . . . . . . . . . . . . . . . . . . . . 3−14
3−14 ADC Digital Filter Ripple 1: USB Mode Only . . . . . . . . . . . . . . . . . . . . . . . . 3−14
3−15 ADC Digital Filter Response 2: USB mode and Normal Modes
(Group Delay = 3 Output Samples) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−15
3−16 ADC Digital Filter Ripple 2: USB Mode and Normal Modes . . . . . . . . . . . 3−15
3−17 ADC Digital Filter Response 3: USB Mode Only . . . . . . . . . . . . . . . . . . . . 3−16
3−18 ADC Digital Filter Ripple 3: USB Mode Only . . . . . . . . . . . . . . . . . . . . . . . . 3−16
3−19 DAC Digital Filter Response 0: USB Mode . . . . . . . . . . . . . . . . . . . . . . . . . 3−17
3−20 DAC Digital Filter Ripple 0: USB Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−17
3−21 DAC Digital Filter Response 1: USB Mode Only . . . . . . . . . . . . . . . . . . . . 3−18
3−22 DAC Digital Filter Ripple 1: USB Mode Only . . . . . . . . . . . . . . . . . . . . . . . . 3−18
3−23 DAC Digital Filter Response 2: USB Mode and Normal Modes . . . . . . . . 3−19
3−24 DAC Digital Filter Ripple 2: USB Mode and Normal Modes . . . . . . . . . . . 3−19
3−25 DAC Digital Filter Response 3: USB Mode Only . . . . . . . . . . . . . . . . . . . . 3−20
3−26 DAC Digital Filter Ripple 3: USB Mode Only . . . . . . . . . . . . . . . . . . . . . . . . 3−20
vi
1−1
1 Introduction
The TLV320AIC23B is a high-performance stereo audio codec with highly integrated analog functionality. The
analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) within the TLV320AIC23B use multibit
sigma-delta technology with integrated oversampling digital interpolation filters. Data-transfer word lengths of 16, 20,
24, and 32 bits, with sample rates from 8 kHz to 96 kHz, are supported. The ADC sigma-delta modulator features
third-order multibit architecture with up to 90-dBA signal-to-noise ratio (SNR) at audio sampling rates up to 96 kHz,
enabling high-fidelity audio recording in a compact, power-saving design. The DAC sigma-delta modulator features
a second-order multibit architecture with up to 100-dBA SNR at audio sampling rates up to 96 kHz, enabling
high-quality digital audio-playback capability, while consuming less than 23 mW during playback only. The
TLV320AIC23B is the ideal analog input/output (I/O) choice for portable digital audio-player and recorder
applications, such as MP3 digital audio players.
Integrated analog features consist of stereo-line inputs with an analog bypass path, a stereo headphone amplifier,
with analog volume control and mute, and a complete electret-microphone-capsule biasing and buffering solution.
The headphone amplifier is capable of delivering 30 mW per channel into 32 Ω. The analog bypass path allows use
of the stereo-line inputs and the headphone amplifier with analog volume control, while completely bypassing the
codec, thus enabling further design flexibility, such as integrated FM tuners. A microphone bias-voltage output
provides a low-noise current source for electret-capsule biasing. The AIC23B has an integrated adjustable
microphone amplifier (gain adjustable from 1 to 5) and a programmable gain microphone amplifier (0 dB or 20 dB).
The microphone signal can be mixed with the output signals if a sidetone is required.
While the TLV320AIC23B supports the industry-standard oversampling rates of 256 fs and 384 fs, unique
oversampling rates of 250 fs and 272 fs are provided, which optimize interface considerations in designs using TI C54x
digital signal processors (DSPs) and universal serial bus (USB) data interfaces. A single 12-MHz crystal can supply
clocking to the DSP, USB, and codec. The TLV320AIC23B features an internal oscillator that, when connected to a
12-MHz external crystal, provides a system clock to the DSP and other peripherals at either 12 MHz or 6 MHz, using
an internal clock buffer and selectable divider. Audio sample rates of 48 kHz and compact-disc (CD) standard 44.1
kHz are supported directly from a 12-MHz master clock with 250 fs and 272 fs oversampling rates.
Low power consumption and flexible power management allow selective shutdown of codec functions, thus
extending battery life in portable applications. This design solution, coupled with the industry’s smallest package, the
TI proprietary MicroStar Junior using only 25 mm2 of board area, makes powerful portable stereo audio designs
easily realizable in a cost-effective, space-saving total analog I/O solution: the TLV320AIC23B.
1.1 Features
• High-Performance Stereo Codec
− 90-dB SNR Multibit Sigma-Delta ADC (A-weighted at 48 kHz)
− 100-dB SNR Multibit Sigma-Delta DAC (A-weighted at 48 kHz)
− 1.42 V – 3.6 V Core Digital Supply: Compatible With TI C54x DSP Core Voltages
− 2.7 V – 3.6 V Buffer and Analog Supply: Compatible Both TI C54x DSP Buffer Voltages
− 8-kHz – 96-kHz Sampling-Frequency Support
• Software Control Via TI McBSP-Compatible Multiprotocol Serial Port
− 2-wire-Compatible and SPI-Compatible Serial-Port Protocols
− Glueless Interface to TI McBSPs
• Audio-Data Input/Output Via TI McBSP-Compatible Programmable Audio Interface
− I2S-Compatible Interface Requiring Only One McBSP for both ADC and DAC
− Standard I2S, MSB, or LSB Justified-Data Transfers
− 16/20/24/32-Bit Word Lengths
MicroStar Junior is a trademark of Texas Instruments.
1−2
− Audio Master/Slave Timing Capability Optimized for TI DSPs (250/272 fs), USB mode
− Industry-Standard Master/Slave Support Provided Also (256/384 fs), Normal mode
− Glueless Interface to TI McBSPs
• Integrated Total Electret-Microphone Biasing and Buffering Solution
− Low-Noise MICBIAS pin at 3/4 AVDD for Biasing of Electret Capsules
− Integrated Buffer Amplifier With Tunable Fixed Gain of 1 to 5
− Additional Control-Register Selectable Buffer Gain of 0 dB or 20 dB
• Stereo-Line Inputs
− Integrated Programmable Gain Amplifier
− Analog Bypass Path of Codec
• ADC Multiplexed Input for Stereo-Line Inputs and Microphone
• Stereo-Line Outputs
− Analog Stereo Mixer for DAC and Analog Bypass Path
• Volume Control With Mute on Input and Output
• Highly Efficient Linear Headphone Amplifier
− 30 mW into 32 Ω From a 3.3-V Analog Supply Voltage
• Flexible Power Management Under Total Software Control
− 23-mW Power Consumption During Playback Mode
− Standby Power Consumption <150 μW
− Power-Down Power Consumption <15 μW
• Industry’s Smallest Package: 32-Pin TI Proprietary MicroStar Junior
− 25 mm2
Total Board Area
− 28-Pin TSSOP Also Is Available (62 mm2 Total Board Area)
• Ideally Suitable for Portable Solid-State Audio Players and Recorders
1−3
1.2 Functional Block Diagram
Control
Interface
Digital
Filters
Digital
Audio
Interface
Σ−Δ
DAC Σ
6 to −73 dB,
1 dB Steps
Headphone
Driver
Σ−Δ
DAC Σ
6 to −73 dB,
1 dB Steps
Headphone
Driver
CLKOUT
Divider
(1x, 1/2x)
OSC
CS
SDIN
SCLK
MODE
DVDD
BVDD
DGND
LRCIN
DIN
LRCOUT
DOUT
BCLK
AVDD
VMID
AGND
RLINEIN
LLINEIN
HPVDD
HPGND
RHPOUT
ROUT
LOUT
LHPOUT
XTI/MCLK
XTO
CLKOUT
DSPcodec
TLV320AIC23B
1.0X
1.0X
VMID
VADC
50 kΩ
50 kΩ
Σ−Δ
ADC
2:1
MUX
VDAC
Σ−Δ
ADC
2:1
MUX
Mute,
0 dB, 20 dB
VMID
50 kΩ
10 kΩ
VADC
12 to −34.5 dB,
1.5 dB Steps
1.0X
1.5X
VDAC
12 to −34 dB,
1.5 dB Steps
MICBIAS
MICIN
CLKIN
Divider
(1x, 1/2x)
Line
Mute
Line
Mute
Side Tone
Mute
Bypass
Mute
Bypass
Mute
NOTE: MCLK, BCLK, and SCLK are all asynchronous to each other.
1−4
1.3 Terminal Assignments
LRCIN
NC
1 2 3 4 5 6 7 8 9
25 24 23 22 21 20 19 18 17
10
11
12
13
14
15
16
32
31
30
29
28
27
26
DOUT
LRCOUT
HPVDD
LHPOUT
RHPOUT
HPGND
XTI/MCLK
SCLK
SDIN
MODE
CS
LLINEIN
RLINEIN
LOUT
ROUT
AVDD
AGND
VMID
MICBIAS
MICIN
NC
NC
DIN
BCLK
CLKOUT
BVDD
DGND
DVDD
XTO
NC
GQE/ZQE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
BVDD
CLKOUT
BCLK
DIN
LRCIN
DOUT
LRCOUT
HPVDD
LHPOUT
RHPOUT
HPGND
LOUT
ROUT
AVDD
DGND
DVDD
XTO
XTI/MCLK
SCLK
SDIN
MODE
CS
LLINEIN
RLINEIN
MICIN
MICBIAS
VMID
AGND
PW PACKAGE
(TOP VIEW)
NC − No internal connection
21
20
19
18
17
16
15
DIN
LRCIN
DOUT
LROUT
HPVDD
LHPOUT
RHPOUT
SCLK
SDIN
MODE
CS
LLNEIN
RUNEIN
MICIN
1
2
3
4
5
6
7
28
27
26
25
24
23
22
BCLK
CLKOUT
BVDD
DGND
DVDD
XTO
XTI/MCLK
HPGND
LOUT
ROUT
AVDD
AGND
VMID
MICBIAS
8
9
10
11
12
13
14
RHD PACKAGE
(TOP VIEW)
1−5
1.4 Ordering Information
PACKAGE
TA 32-Pin
MicroStar Junior GQE/ZQE
28-Pin
TSSOP PW
28-Pin
PQFP RHD
−10°C to 70°C TLV320AIC23BGQE/ZQE TLV320AIC23BPW TLV320AIC23BRHD
−40°C to 85°C TLV320AIC23BIGQE/ZQE TLV320AIC23BIPW TLV320AIC23BIRHD
1.5 Terminal Functions
TERMINAL
NO.
I/O DESCRIPTION
NAME GQE/
ZQE
PW RHD
AGND 5 15 12 Analog supply return
AVDD 4 14 11 Analog supply input. Voltage level is 3.3 V nominal.
BCLK 23 3 28 I/O I2S serial-bit clock. In audio master mode, the AIC23B generates this signal and sends it to the
DSP. In audio slave mode, the signal is generated by the DSP.
BVDD 21 1 26 Buffer supply input. Voltage range is from 2.7 V to 3.6 V.
CLKOUT 22 2 27 O Clock output. This is a buffered version of the XTI input and is available in 1X or 1/2X frequencies
of XTI. Bit 07 in the sample rate control register controls frequency selection.
CS 12 21 18 I Control port input latch/address select. For SPI control mode this input acts as the data latch
control. For 2-wire control mode this input defines the seventh bit in the device address field.
See Section 3.1 for details.
DIN 24 4 1 I I2S format serial data input to the sigma-delta stereo DAC
DGND 20 28 25 Digital supply return
DOUT 27 6 3 O I2S format serial data output from the sigma-delta stereo ADC
DVDD 19 27 24 Digital supply input. Voltage range is 1.4 V to 3.6 V.
HPGND 32 11 8 Analog headphone amplifier supply return
HPVDD 29 8 5 Analog headphone amplifier supply input. Voltage level is 3.3 V nominal.
LHPOUT 30 9 6 O Left stereo mixer-channel amplified headphone output. Nominal 0-dB output level is 1 VRMS.
Gain of –73 dB to 6 dB is provided in 1-dB steps.
LLINEIN 11 20 17 I Left stereo-line input channel. Nominal 0-dB input level is 1 VRMS. Gain of –34.5 dB to 12 dB is
provided in 1.5-dB steps.
LOUT 2 12 9 O Left stereo mixer-channel line output. Nominal output level is 1.0 VRMS.
LRCIN 26 5 2 I/O I2S DAC-word clock signal. In audio master mode, the AIC23B generates this framing signal
and sends it to the DSP. In audio slave mode, the signal is generated by the DSP.
LRCOUT 28 7 4 I/O I2S ADC-word clock signal. In audio master mode, the AIC23B generates this framing signal
and sends it to the DSP. In audio slave mode, the signal is generated by the DSP.
MICBIAS 7 17 14 O Buffered low-noise-voltage output suitable for electret-microphone-capsule biasing. Voltage
level is 3/4 AVDD nominal.
MICIN 8 18 15 I Buffered amplifier input suitable for use with electret-microphone capsules. Without external
resistors a default gain of 5 is provided. See Section 2.3.1.2 for details.
MODE 13 22 19 I Serial-interface-mode input. See Section 3.1 for details.
NC 1, 9
17, 25
Not Used—No internal connection
RHPOUT 31 10 7 O Right stereo mixer-channel amplified headphone output. Nominal 0-dB output level is 1 VRMS.
Gain of −73 dB to 6 dB is provided in 1-dB steps.
RLINEIN 10 19 16 I Right stereo-line input channel. Nominal 0-dB input level is 1 VRMS. Gain of –34.5 dB to 12 dB is
provided in 1.5-dB steps.
ROUT 3 13 10 O Right stereo mixer-channel line output. Nominal output level is 1.0 VRMS.
1−6
1.5 Terminal Functions (continued)
TERMINAL
NO.
I/O DESCRIPTION
NAME GQE/
ZQE
PW RHD
SCLK 15 24 21 I Control-port serial-data clock. For SPI and 2-wire control modes this is the serial-clock input.
See Section 3.1 for details.
SDIN 14 23 20 I Control-port serial-data input. For SPI and 2-wire control modes this is the serial-data input and
also is used to select the control protocol after reset. See Section 3.1 for details.
VMID 6 16 13 I Midrail voltage decoupling input. 10-μF and 0.1-μF capacitors should be connected in parallel to
this terminal for noise filtering. Voltage level is 1/2 AVDD nominal.
XTI/MCLK 16 25 22 I Crystal or external-clock input. Used for derivation of all internal clocks on the AIC23B.
XTO 18 26 23 O Crystal output. Connect to external crystal for applications where the AIC23B is the audio timing
master. Not used in applications where external clock source is used.
2−1
2 Specifications
2.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless
otherwise noted)†
Supply voltage range, AVDD to AGND, DVDD to DGND, BVDD to DGND, HPVDD to HPGND
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to + 3.63 V
Analog supply return to digital supply return, AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to + 3 .63 V
Input voltage range, all input signals: Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DVDD + 0.3 V
Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AVDD + 0.3 V
Case temperature for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Operating free-air temperature range, TA: Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −10°C to 70°C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: DVDD may not exceed BVDD + 0.3V; BVDD may not exceed AVDD + 0.3V or HPVDD + 0.3.
2.2 Recommended Operating Conditions
MIN NOM MAX UNIT
Analog supply voltage, AVDD, HPVDD (see Note 2) 2.7 3.3 3.6 V
Digital buffer supply voltage, BVDD (see Note 2) 2.7 3.3 3.6 V
Digital core supply voltage, DVDD (see Note 2) 1.42 1.5 3.6 V
Analog input voltage, full scale − 0dB (AVDD = 3.3 V) 1 VRMS
Stereo-line output load resistance 10 kΩ
Headphone-amplifier output load resistance 0 Ω
CLKOUT digital output load capacitance 20 pF
All other digital output load capacitance 10 pF
Stereo-line output load capacitance 50 pF
XTI master clock Input 18.43 MHz
ADC or DAC conversion rate 96 kHz
Operating free-air temperature, TA
Commercial −10 70
°C
Industrial −40 85
NOTE 2: Digital voltage values are with respect to DGND; analog voltage values are with respect to AGND.
2−2
2.3 Electrical Characteristics Over Recommended Operating Conditions, AVDD,
HPVDD, BVDD = 3.3 V, DVDD = 1.5 V, Slave Mode, XTI/MCLK = 256fs, fs = 48 kHz
(unless otherwise stated)
2.3.1 ADC
2.3.1.1 Line Input to ADC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input signal level (0 dB) 1 VRMS
Signal-to-noise ratio, A-weighted, 0-dB gain (see Notes 3
fs = 48 kHz (3.3 V) 85 90
dB
and 4) fs = 48 kHz (2.7 V) 90
Dynamic range, A-weighted, −60-dB full-scale input (see
AVDD = 3.3 V 85 90
dB
Note 4) AVDD = 2.7 V 90
Total harmonic distortion, −1-dB input, 0-dB gain
AVDD = 3.3 V –80
dB
AVDD = 2.7 V 80
Power supply rejection ratio 1 kHz, 100 mVpp 50 dB
ADC channel separation 1 kHz input tone 90 dB
Programmable gain 1 kHz input tone, RSOURCE < 50 Ω –34.5 12 dB
Programmable gain step size Monotonic 1.5 dB
Mute attenuation 0 dB, 1 kHz input tone 80 dB
Input resistance
12 dB Input gain 10 20
kΩ
0 dB input gain 30 35
Input capacitance 10 pF
NOTES: 3. Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz
to 20-kHz bandwidth using an audio analyzer.
4. All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter
results in higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass
filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.
2.3.1.2 Microphone Input to ADC, 0-dB Gain, fs = 8 kHz (40-KΩ Source Impedance, see Section 1.2,
Functional Block Diagram)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input signal level (0 dB) 1.0 VRMS
Signal-to-noise ratio, A-weighted, 0-dB gain (see Notes 3 and 4)
AVDD = 3.3 V 80 85
dB
AVDD = 2.7 V 84
Dynamic range, A-weighted, −60-dB full-scale input (see Note 4)
AVDD = 3.3 V 80 85
dB
AVDD = 2.7 V 84
Total harmonic distortion, −1-dB input, 0-dB gain
AVDD = 3.3 V –60
dB
AVDD = 2.7 V −60
Power supply rejection ratio 1 kHz, 100 mVpp 50 dB
Programmable gain boost 1 kHz input tone, RSOURCE < 50 Ω 20 dB
Microphone-path gain MICBOOST = 0, RSOURCE < 50 Ω 14 dB
Mute attenuation 0 dB, 1 kHz input tone 60 80 dB
Input resistance 8 14 kΩ
Input capacitance 10 pF
NOTES: 3. Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz
to 20-kHz bandwidth using an audio analyzer.
4. All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter
results in higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass
filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.
2−3
2.3.1.3 Microphone Bias
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Bias voltage 3/4 AVDD − 100 m 3/4 AVDD 3/4 AVDD + 100 m V
Bias-current source 3 mA
Output noise voltage 1 kHz to 20 kHz 25 nV/√Hz
2.3.2 DAC
2.3.2.1 Line Output, Load = 10 kΩ, 50 pF
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0-dB full-scale output voltage (FFFFFF) 1.0 VRMS
Signal-to-noise ratio, A-weighted, 0-dB gain (see Notes 3, 4, and 5)
AVDD = 3.3 V fs = 48kHz 90 100
dB
AVDD = 2.7 V fs = 48 kHz 100
Dynamic range, A-weighted (see Note 4)
AVDD = 3.3 V 85 90
dB
AVDD = 2.7 V TBD
AVDD = 3.3 V
1 kHz, 0 dB –88 –80
dB
Total harmonic distortion
1 kHz, −3 dB −92 −86
AVDD = 2.7 V
1 kHz, 0 dB −85
dB
1 kHz, −3 dB −88
Power supply rejection ratio 1 kHz, 100 mVpp 50 dB
DAC channel separation 100 dB
NOTES: 3. Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz
to 20-kHz bandwidth using an audio analyzer.
4. All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter
results in higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass
filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.
5. Ratio of output level with 1-kHz full-scale input, to the output level with all zeros into the digital input, measured A-weighted over
a 20-Hz to 20-kHz bandwidth.
2.3.3 Analog Line Input to Line Output (Bypass)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0-dB full-scale output voltage 1.0 VRMS
Signal-to-noise ratio, A-weighted, 0-dB gain (see Notes 3 and 4)
AVDD = 3.3 V 90 95
dB
AVDD = 2.7 V 95
AVDD = 3.3 V
1 kHz, 0 dB –86 –80
dB
Total harmonic distortion
1 kHz, −3 dB −92 −86
AVDD = 2.7 V
1 kHz, 0 dB −86
dB
1 kHz, −3 dB −92
Power supply rejection ratio 1 kHz, 100 mVpp 50 dB
DAC channel separation (left to right) 1 kHz, 0 dB 80 dB
NOTES: 3. Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz
to 20-kHz bandwidth using an audio analyzer.
4. All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter
results in higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass
filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.
2−4
2.3.4 Stereo Headphone Output
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0-dB full-scale output voltage 1.0 VRMS
Maximum output power, PO RL = 32 Ω 30
mW
RL = 16 Ω 40
Signal-to-noise ratio, A-weighted (see Note 4) AVDD = 3.3 V 90 97 dB
Total harmonic distortion
AVDD = 3.3 V,
PO = 10 mW 0.1
%
1 kHz output PO = 20 mW 1.0
Power supply rejection ratio 1 kHz, 100 mVpp 50 dB
Programmable gain 1 kHz output −73 6 dB
Programmable-gain step size 1 dB
Mute attenuation 1 kHz output 80 dB
NOTE 4: All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results
in higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes
out-of-band noise, which, although not audible, may affect dynamic specification values.
2.3.5 Analog Reference Levels
PARAMETER MIN TYP MAX UNIT
Reference voltage AVDD/2 − 50 mV AVDD/2 + 50 mV V
Divider resistance 40 50 60 kΩ
2.3.6 Digital I/O
PARAMETER MIN TYP MAX UNIT
VIL Input low level 0.3 × BVDD V
VIH Input high level 0.7 × BVDD V
VOL Output low level 0.1 × BVDD V
VOH Output high level 0.9 × BVDD V
2.3.7 Supply Current
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Record and playback (all active) 20 24 26
Record and playback (osc, clk, and MIC output powered down) 16 18 20
Total supply current,
Line playback only 6 7.5 9
ITOT
Record only 11 13.5 15 mA
No input signal
Analog bypass (line in to line out) 4 4.5 6
Power down, DVDD = 1.5 V, Oscillator enabled 0.8 1.5 3
AVDD = BVDD = HPVDD = 3.3 V Oscillator disabled 0.01
2−5
2.4 Digital-Interface Timing
PARAMETER MIN TYP MAX UNIT
tw(1)
System-clock pulse duration, MCLK/XTI
High 18
ns
tw(2)
Low 18
tc(1) System-clock period, MCLK/XTI 54 ns
Duty cycle, MCLK/XTI 40/60% 60/40%
tpd(1) Propagation delay, CLKOUT 0 10 ns
tc(1)
tw(1) tw(2)
tpd(1)
MCLK/XTI
CLKOUT
CLKOUT
(Div 2)
Figure 2−1. System-Clock Timing Requirements
2.4.1 Audio Interface (Master Mode)
PARAMETER MIN TYP MAX UNIT
tpd(2) Propagation delay, LRCIN/LRCOUT 0 10 ns
tpd(3) Propagation delay, DOUT 0 10 ns
tsu(1) Setup time, DIN 10 ns
th(1) Hold time, DIN 10 ns
BCLK
LRCIN
DIN
tpd(2)
tsu(1) th(1)
tpd(3)
DOUT
LRCOUT
Figure 2−2. Master-Mode Timing Requirements
2−6
2.4.2 Audio Interface (Slave-Mode)
PARAMETER MIN TYP MAX UNIT
tw(3)
Pulse duration, BCLK
High 20
ns
tw(4)
Low 20
tc(2) Clock period, BCLK 50 ns
tpd(4) Propagation delay, DOUT 0 10 ns
tsu(2) Setup time, DIN 10 ns
th(2) Hold time, DIN 10 ns
tsu(3) Setup time, LRCIN 10 ns
th(3) Hold time, LRCIN 10 ns
BCLK
LRCIN
DIN
tc(2)
tw(4) tw(3)
tsu(3)
tsu(2) th(3)
th(2)
DOUT
tpd(2)
LRCOUT
Figure 2−3. Slave-Mode Timing Requirements
2−7
2.4.3 Three-Wire Control Interface (SDIN)
PARAMETER MIN TYP MAX UNIT
tw(5)
Clock pulse duration, SCLK
High 20
ns
tw(6)
Low 20
tc(3) Clock period, SCLK 80 ns
tsu(4) Clock rising edge to CS rising edge, SCLK 60 ns
tsu(5) Setup time, SDIN to SCLK 20 ns
th(4) Hold time, SCLK to SDIN 20 ns
tw(7)
Pulse duration, CS
High 20
ns
tw(8)
Low 20
LSB
tw(8)
tc(3)
tw(5) tw(6) tsu(4)
tsu(5) th(4)
CS
SCLK
DIN
Figure 2−4. Three-Wire Control Interface Timing Requirements
2.4.4 Two-Wire Control Interface
PARAMETER MIN TYP MAX UNIT
tw(9)
Clock pulse duration, SCLK
High 1.3 μs
tw(10)
Low 600 ns
f(sf) Clock frequency, SCLK 0 400 kHz
th(5) Hold time (start condition) 600 ns
tsu(6) Setup time (start condition) 600 ns
th(6) Data hold time 900 ns
tsu(7) Data setup time 100 ns
tr Rise time, SDIN, SCLK 300 ns
tf Fall time, SDIN, SCLK 300 ns
tsu(8) Setup time (stop condition) 600 ns
tsp Pulse width of spikes suppressed by input filter 0 50 ns
SCLK
DIN
tw(9) tw(10)
th(5) th(6) tsu(7) tsu(8)
tsp
Figure 2−5. Two-Wire Control Interface Timing Requirements
2−8
3−1
3 How to Use the TLV320AIC23B
3.1 Control Interfaces
The TLV320AIC23B has many programmable features. The control interface is used to program the registers of the
device. The control interface complies with SPI (three-wire operation) and two-wire operation specifications. The
state of the MODE terminal selects the control interface type. The MODE pin must be hardwired to the required level.
MODE INTERFACE
0 2-wire
1 SPI
3.1.1 SPI
In SPI mode, SDIN carries the serial data, SCLK is the serial clock and CS latches the data word into the
TLV320AIC23B. The interface is compatible with microcontrollers and DSPs with an SPI interface.
A control word consists of 16 bits, starting with the MSB. The data bits are latched on the rising edge of SCLK. A rising
edge on CS after the 16th rising clock edge latches the data word into the AIC (see Figure 3-1).
The control word is divided into two parts. The first part is the address block, the second part is the data block:
B[15:9] Control Address Bits
B[8:0] Control Data Bits
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MSB LSB
CS
SCLK
SDIN
Figure 3−1. SPI Timing
3.1.2 2-Wire
In 2-wire mode, the data transfer uses SDIN for the serial data and SCLK for the serial clock. The start condition is
a falling edge on SDIN while SCLK is high. The seven bits following the start condition determine which device on
the 2-wire bus receives the data. R/W determines the direction of the data transfer. The TLV320AIC23B is a write only
device and responds only if R/W is 0. The device operates only as a slave device whose address is selected by setting
the state of the CS pin as follows.
CS STATE
(Default = 0)
ADDRESS
0 0011010
1 0011011
3−2
The device that recognizes the address responds by pulling SDIN low during the ninth clock cycle, acknowledging
the data transfer. The control follows in the next two eight-bit blocks. The stop condition after the data transfer is a
rising edge on SDIN when SCLK is high (see Figure 3-2).
The 16-bit control word is divided into two parts. The first part is the address block, the second part is the data block:
B[15:9] Control Address Bits
B[8:0] Control Data Bits
SCLK
SDI ADDR R/W ACK B15 − B8 ACK B7 − B0 ACK
Start Stop
1 7 8 9 1 8 9 1 8 9
Figure 3−2. 2-Wire Compatible Timing
3.1.3 Register Map
The TLV320AIC23B has the following set of registers, which are used to program the modes of operation.
ADDRESS REGISTER
0000000 Left line input channel volume control
0000001 Right line input channel volume control
0000010 Left channel headphone volume control
0000011 Right channel headphone volume control
0000100 Analog audio path control
0000101 Digital audio path control
0000110 Power down control
0000111 Digital audio interface format
0001000 Sample rate control
0001001 Digital interface activation
0001111 Reset register
Left line input channel volume control (Address: 0000000)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function LRS LIM X X LIV4 LIV3 LIV2 LIV1 LIV0
Default 0 1 0 0 1 0 1 1 1
LRS Left/right line simultaneous volume/mute update
Simultaneous update 0 = Disabled 1 = Enabled
LIM Left line input mute 0 = Normal 1 = Muted
LIV[4:0] Left line input volume control (10111 = 0 dB default)
11111 = +12 dB down to 00000 = –34.5 dB in 1.5-dB steps
X Reserved
3−3
Right Line Input Channel Volume Control (Address: 0000001)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function RLS RIM X X RIV4 RIV3 RIV2 RIV1 RIV0
Default 0 1 0 0 1 0 1 1 1
RLS Right/left line simultaneous volume/mute update
Simultaneous update 0 = Disabled 1 = Enabled
RIM Right line input mute 0 = Normal 1 = Muted
RIV[4:0] Right line input volume control (10111 = 0 dB default)
11111 = +12 dB down to 00000 = –34.5 dB in 1.5-dB steps
X Reserved
Left Channel Headphone Volume Control (Address: 0000010)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function LRS LZC LHV6 LHV5 LHV4 LHV3 LHV2 LHV1 LHV0
Default 0 1 1 1 1 1 0 0 1
LRS Left/right headphone channel simultaneous volume/mute update
Simultaneous update 0 = Disabled 1 = Enabled
LZC Left-channel zero-cross detect
Zero-cross detect 0 = Off 1 = On
LHV[6:0] Left Headphone volume control (1111001 = 0 dB default)
1111111 = +6 dB, 79 steps between +6 dB and −73 dB (mute), 0110000 = −73 dB (mute),
any thing below 0110000 does nothing − you are still muted
Right Channel Headphone Volume Control (Address: 0000011)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function RLS RZC RHV6 RHV5 RHV4 RHV3 RHV2 RHV1 RHV0
Default 0 1 1 1 1 1 0 0 1
RLS Right/left headphone channel simultaneous volume/mute Update
Simultaneous update 0 = Disabled 1 = Enabled
RZC Right-channel zero-cross detect
Zero-cross detect 0 = Off 1 = On
RHV[6:0] Right headphone volume control (1111001 = 0 dB default)
1111111 = +6 dB, 79 steps between +6 dB and −73 dB (mute), 0110000 = −73 dB (mute),
any thing below 0110000 does nothing − you are still muted
Analog Audio Path Control (Address: 0000100)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function STA2 STA1 STA0 STE DAC BYP INSEL MICM MICB
Default 0 0 0 0 0 1 0 1 0
STA[2:0] and STE
STE STA2 STA1 STA0 ADDED SIDETONE
1 1 X X 0 dB
1 0 0 0 −6 dB
1 0 0 1 −9 dB
1 0 1 0 −12 dB
1 0 1 1 −18 dB
0 X X X Disabled
DAC DAC select 0 = DAC off 1 = DAC selected
BYP Bypass 0 = Disabled 1 = Enabled
3−4
INSEL Input select for ADC 0 = Line 1 = Microphone
MICM Microphone mute 0 = Normal 1 = Muted
MICB Microphone boost 0=dB 1 = 20dB
X Reserved
Digital Audio Path Control (Address: 0000101)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function X X X X X DACM DEEMP1 DEEMP0 ADCHP
Default 0 0 0 0 0 1 0 0 0
DACM DAC soft mute 0 = Disabled 1 = Enabled
DEEMP[1:0] De-emphasis control 00 = Disabled 01 = 32 kHz 10 = 44.1 kHz 11 = 48 kHz
ADCHP ADC high-pass filter 1 = Disabled 0 = Enabled
X Reserved
Power Down Control (Address: 0000110)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function X OFF CLK OSC OUT DAC ADC MIC LINE
Default 0 0 0 0 0 0 1 1 1
OFF Device power 0 = On 1 = Off
CLK Clock 0 = On 1 = Off
OSC Oscillator 0 = On 1 = Off
OUT Outputs 0 = On 1 = Off
DAC DAC 0 = On 1 = Off
ADC ADC 0 = On 1 = Off
MIC Microphone input 0 = On 1 = Off
LINE Line input 0 = On 1 = Off
X Reserved
Digital Audio Interface Format (Address: 0000111)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function X X MS LRSWAP LRP IWL1 IWL0 FOR1 FOR0
Default 0 0 0 0 0 0 0 0 1
MS Master/slave mode 0 = Slave 1 = Master
LRSWAP DAC left/right swap 0 = Disabled 1 = Enabled
LRP DAC left/right phase 0 = Right channel on, LRCIN high
1 = Right channel on, LRCIN low
DSP mode
1 = MSB is available on 2nd BCLK rising edge after LRCIN rising edge
0 = MSB is available on 1st BCLK rising edge after LRCIN rising edge
IWL[1:0] Input bit length 00 = 16 bit 01 = 20 bit 10 = 24 bit 11 = 32 bit
FOR[1:0] Data format 11 = DSP format, frame sync followed by two data words
10 = I2S format, MSB first, left – 1 aligned
01 = MSB first, left aligned
00 = MSB first, right aligned
X Reserved
NOTES: 1. In Master mode, the TLV320AIC23B supplies the BCLK, LRCOUT, and LRCIN. In Slave mode, BCLK, LRCOUT, and LRCIN are
supplied to the TLV320AIC23B.
2. In normal mode, BCLK = MCLK/4 for all sample rates except for 88.2 kHz and 96 kHz. For 88.2 kHz and 96 kHz sample rate,
BCLK = MCLK.
3. In USB mode, bit BCLK = MCLK
3−5
Sample Rate Control (Address: 0001000)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function X CLKOUT CLKIN SR3 SR2 SR1 SR0 BOSR USB/Normal
Default 0 0 0 1 0 0 0 0 0
CLKIN Clock input divider 0 = MCLK 1 = MCLK/2
CLKOUT Clock output divider 0 = MCLK 1 = MCLK/2
SR[3:0] Sampling rate control (see Sections 3.3.2.1 AND 3.3.2.2)
BOSR Base oversampling rate
USB mode: 0 = 250 fs 1 = 272 fs
Normal mode: 0 = 256 fs 1 = 384 fs
USB/Normal Clock mode select: 0 = Normal 1 = USB
X Reserved
Digital Interface Activation (Address: 0001001)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function X RES RES X X X X X ACT
Default 0 0 0 0 0 0 0 0 0
ACT Activate interface 0 = Inactive 1 = Active
X Reserved
Reset Register (Address: 0001111)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function RES RES RES RES RES RES RES RES RES
Default 0 0 0 0 0 0 0 0 0
RES Write 000000000 to this register triggers reset
3.2 Analog Interface
3.2.1 Line Inputs
The TLV320AIC23B has line inputs for the left and the right audio channels (RLINEIN and LLINEIN). Both line inputs
have independently programmable volume controls and mutes. Active and passive filters for the two channels
prevent high frequencies from folding back into the audio band.
The line-input gain is logarithmically adjustable from 12 dB to –34.5 dB in 1.5-dB steps. The ADC full-scale range
is 1.0 VRMS at AVDD = 3.3 V. The full-scale range tracks linearly with analog supply voltage AVDD. To avoid distortions,
it is important not to exceed the full-scale range.
The gain is independently programmable on both left and right line-inputs. To reduce the number of software write
cycles required. Both channels can be locked to the same value by setting the RLS and LRS bits (see Section 3.1.3).
The line inputs are biased internally to VMID. When the line inputs are muted or the device is set to standby mode,
the line inputs are kept biased to VMID using special antithump circuitry. This reduces audible clicks that otherwise
might be heard when reactivating the inputs.
For interfacing to a CD system, the line input should be scaled to 1 VRMS to avoid clipping, using the circuit shown
in Figure 3-3.
R
2
R1
C1
C2 +
CDIN LINEIN
AGND
Where:
R1 = 5 kΩ
R2 = 5 kΩ
C1 = 47 pF
C2 = 470 nF
Figure 3−3. Analog Line Input Circuit
R1 and R2 divide the input signal by two, reducing the 2 VRMS from the CD player to the nominal 1 VRMS of the AIC23B
inputs. C1 filters high-frequency noise, and C2 removes any dc component from the signal.
3−6
3.2.2 Microphone Input
MICIN is a high-impedance, low-capacitance input that is compatible with a wide range of microphones. It has a
programmable volume control and a mute function. Active and passive filters prevent high frequencies from folding
back into the audio band.
The MICIN signal path has two gain stages. The first stage has a nominal gain of G1 = 50 k/10 k = 5. By adding an
external resistor (RMIC) in series with MICIN, the gain of the first stage can be adjusted by G1 = 50 k/(10 k + RMIC).
For example, RMIC = 40 k gives a gain of 0 dB. The second stage has a software programmable gain of 0 dB or 20
dB (see Section 3.1.3).
50 kΩ
10 kΩ
VMID
0 dB/20 dB
To ADC
MICIN
Figure 3−4. Microphone Input Circuit
The microphone input is biased internally to VMID. When the line inputs are muted, the MICIN input is kept biased
to VMID using special antithump circuitry. This reduces audible clicks that may otherwise be heard when reactivating
the input.
The MICBIAS output provides a low-noise reference voltage suitable for biasing electret type microphones and the
associated external resistor biasing network. The maximum source current capability is 3 mA. This limits the smallest
value of external biasing resistors that safely can be used.
The MICBIAS output is not active in standby mode.
3.2.3 Line Outputs
The TLV320AIC23B has two low-impedance line outputs (LLINEOUT and RLINEOUT) capable of driving line loads
with 10-kΩ and 50-pF impedances.
The DAC full-scale output voltage is 1.0 VRMS at AVDD = 3.3 V. The full-scale range tracks linearly with the analog
supply voltage AVDD. The DAC is connected to the line outputs via a low-pass filter that removes out-of-band
components. No further external filtering is required in most applications.
The DAC outputs, line inputs, and the microphone signal are summed into the line outputs. These sources can be
switched off independently. For example, in bypass mode, the line inputs are routed to the line outputs, bypassing
the ADC and the DAC. If sidetone is enabled, the microphone signal is routed to both line outputs via a four-step
programmable attenuation circuit.
The line outputs are muted by either muting the DAC (analog) or soft muting (digital) and disabling the bypass and
sidetone paths (see Section 3.1.3).
3.2.4 Headphone Output
The TLV320AIC23B has stereo headphone outputs (LHPOUT and RHPOUT), and is designed to drive 16-Ω or 32-Ω
headphones. The headphone output includes a high-quality volume control and mute function.
The headphone volume is logarithmically adjustable from 6 dB to –73 dB in 1-dB steps. Writing 000000 to the
volume-control registers (see Section 3.1.3) mutes the headphone output. When the headphone output is muted or
the device is placed in standby mode, the dc voltage is maintained at the outputs to prevent audible clicks.
A zero-cross detection circuit is provided under the control of the LZC and RZC bits. If this circuit is enabled, the
volume-control values are updated only when the input signal to the gain stage is close to the analog ground level.
3−7
This minimizes audible clicks as the volume is changed or the device is muted. This circuit has no time-out, so, if only
dc levels are being applied to the gain stage input of more than 20 mV, the gain is not updated.
The gain is independently programmable on the left and right channels. Both channels can be locked to the same
value by setting the RLS and LRS bits (see Section 3.1.3).
3.2.5 Analog Bypass Mode
The TLV320AIC23B includes a bypass mode in which the analog line inputs are directly routed to the analog line
outputs, bypassing the ADC and DAC. This is enabled by selecting the bypass bit in the analog audio path control
register[see Section 3.1.3).
For a true bypass mode, the output from the DAC and the sidetone should be disabled. The line input and headphone
output volume controls and mutes are still operational in bypass mode. Therefore the line inputs, DAC output, and
microphone input can be summed together. The maximum signal at any point in the bypass path must be no greater
than 1.0Vrms at AVDD=3.3V to avoid clipping and distortion. This amplitude tracks linearly with AVDD.
3.2.6 Sidetone Insertion
The TLV320AIC23B has a sidetone insertion made where the microphone input is routed to the line and headphone
outputs. This is useful for telephony and headset applications. The attenuation of the sidetone signal may be set to
−6 dB, −9 dB, −12 dB, −15 dB, or 0dB, by software selection (see Section 3.1.3). If this mode is used to sum the
microphone input with the DAC output and line inputs, care must be taken not to exceed signal level to avoid clipping
and distortion.
3.3 Digital Audio Interface
3.3.1 Digital Audio-Interface Modes
The TLV320AIC23B supports four audio-interface modes.
• Right justified
• Left justified
• I2S mode
• DSP mode
The four modes are MSB first and operate with a variable word width between 16 to 32 bits (except right-justified
mode, which does not support 32 bits).
The digital audio interface consists of clock signal BCLK, data signals DIN and DOUT, and synchronization signals
LRCIN and LRCOUT. BCLK is an output in master mode and an input in slave mode.
3.3.1.1 Right-Justified Mode
In right-justified mode, the LSB is available on the rising edge of BCLK, preceding a falling edge on LRCIN or LRCOUT
(see Figure 3-5).
LRCIN/
BCLK
DIN/ n n−1 1 0 n n−1
1/fs
Left Channel Right Channel
0 1 0
MSB LSB
LRCOUT
DOUT
Figure 3−5. Right-Justified Mode Timing
3.3.1.2 Left-Justified Mode
In left-justified mode, the MSB is available on the rising edge of BCLK, following a rising edge on LRCIN or LRCOUT
(see Figure 3-6)
3−8
LRCIN/
BCLK
DIN/
n n−1 1 0 n n−1
1/fs
Left Channel Right Channel
1 0 n
MSB LSB
LRCOUT
DOUT
Figure 3−6. Left-Justified Mode Timing
3.3.1.3 I2S Mode
In I2S mode, the MSB is available on the second rising edge of BCLK, after the falling edge on LRCIN or LRCOUT
(see Figure 3-7).
LRCIN/
BCLK
DIN/ n n−1 1 0 n n−1
1/fs
Left Channel Right Channel
1 0
MSB LSB
1BCLK
LRCOUT
DOUT
Figure 3−7. I2S Mode Timing
3.3.1.4 DSP Mode
The DSP mode is compatible with the McBSP ports of TI DSPs. LRCIN and LRCOUT must be connected to the Frame
Sync signal of the McBSP. A falling edge on LRCIN or LRCOUT starts the data transfer. The left-channel data consists
of the first data word, which is immediately followed by the right channel data word (see Figure 3-8). Input word length
is defined by the IWL register. Figure 3−8 shows LRP = 1 (default LRP = 0).
LRCIN/
BCLK
DIN/
n n−1 1 0 n n−1
Left Channel Right Channel
1 0
MSB LSB MSB LSB
LRCOUT
DOUT
Figure 3−8. DSP Mode Timing
3−9
3.3.2 Audio Sampling Rates
The TLV320AIC23B can operate in master or slave clock mode. In the master mode, the TLV320AIC23B clock and
sampling rates are derived from a 12-MHz MCLK signal. This 12-MHz clock signal is compatible with the USB
specification. The TLV320AIC23B can be used directly in a USB system.
In the slave mode, an appropriate MCLK or crystal frequency and the sample rate control register settings control
the TLV320AIC23B clock and sampling rates.
The settings in the sample rate control register control the clock mode and sampling rates.
Sample Rate Control (Address: 0001000)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function X CLKOUT CLKIN SR3 SR2 SR1 SR0 BOSR USB/Normal
Default 0 0 0 1 0 0 0 0 0
CLKOUT Clock output divider 0 = MCLK 1 = MCLK/2
CLKIN Clock input divider 0 = MCLK 1 = MCLK/2
SR[3:0] Sampling rate control (see Sections 3.3.2.1 and 3.3.2.2)
BOSR Base oversampling rate
USB mode: 0 = 250 fs 1 = 272 fs
Normal mode: 0 = 256 fs 1 = 384 fs
USB/Normal Clock mode select: 0 = Normal 1 = USB
X Reserved
The clock circuit of the AIC23B has two internal dividers. The first, controlled by CLKIN, applies to the sampling-rate
generator of the codec. The second, controlled by CLKOUT, applies only to the CLKOUT terminal. By setting CLKIN
to 1, the entire codec is clocked with half the frequency, effectively dividing the resulting sampling rates by two. The
following sampling-rate tables are based on CLKIN = MCLK.
3.3.2.1 USB-Mode Sampling Rates (MCLK = 12 MHz)
In the USB mode, the following ADC and DAC sampling rates are available:
SAMPLING RATE†
SAMPLING-RATE CONTROL SETTINGS
ADC
DAC
FILTER TYPE
(kHz)
(kHz)
SR3 SR2 SR1 SR0 BOSR
96 96 3 0 1 1 1 0
88.2 88.2 2 1 1 1 1 1
48 48 0 0 0 0 0 0
44.1 44.1 1 1 0 0 0 1
32 32 0 0 1 1 0 0
8.021 8.021 1 1 0 1 1 1
8 8 0 0 0 1 1 0
48 8 0 0 0 0 1 0
44.1 8.021 1 1 0 0 1 1
8 48 0 0 0 1 0 0
8.021 44.1 1 1 0 1 0 1
† The sampling rates are derived from the 12-MHz master clock. The available oversampling rates do not produce exactly 8-kHz, 44.1-kHz, and
88.2-kHz sampling rates, but 8.021 kHz, 44.117 kHz, and 88.235 kHz, respectively. See Figures 3−17 through 3−34 for filter responses
3−10
3.3.2.2 Normal-Mode Sampling Rates
In normal mode, the following ADC and DAC sampling rates, depending on the MCLK frequency, are available:
MCLK = 12.288 MHz
SAMPLING RATE SAMPLING-RATE CONTROL SETTINGS
ADC
DAC
FILTER TYPE
(kHz)
(kHz)
SR3 SR2 SR1 SR0 BOSR
96 96 2 0 1 1 1 0
48 48 1 0 0 0 0 0
32 32 1 0 1 1 0 0
8 8 1 0 0 1 1 0
48 8 1 0 0 0 1 0
8 48 1 0 0 1 0 0
MCLK = 11.2896 MHz
SAMPLING RATE SAMPLING-RATE CONTROL SETTINGS
ADC
DAC
FILTER TYPE
(kHz)
(kHz)
SR3 SR2 SR1 SR0 BOSR
88.2 88.2 2 1 1 1 1 0
44.1 44.1 1 1 0 0 0 0
8.021 8.021 1 1 0 1 1 0
44.1 8.021 1 1 0 0 1 0
8.021 44.1 1 1 0 1 0 0
MCLK = 18.432 MHz
SAMPLING RATE SAMPLING-RATE CONTROL SETTINGS
ADC
DAC
FILTER TYPE
(kHz)
(kHz)
SR3 SR2 SR1 SR0 BOSR
96 96 2 0 1 1 1 1
48 48 1 0 0 0 0 1
32 32 1 0 1 1 0 1
8 8 1 0 0 1 1 1
48 8 1 0 0 0 1 1
8 48 1 0 0 1 0 1
MCLK = 16.9344 MHz
SAMPLING RATE SAMPLING-RATE CONTROL SETTINGS
ADC
DAC
FILTER TYPE
(kHz)
(kHz)
SR3 SR2 SR1 SR0 BOSR
88.2 88.2 2 1 1 1 1 1
44.1 44.1 1 1 0 0 0 1
8.021 8.021 1 1 0 1 1 1
44.1 8.021 1 1 0 0 1 1
8.021 44.1 1 1 0 1 0 1
3−11
3.3.3 Digital Filter Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADC Filter Characteristics ( TI DSP 250 fs Mode Operation )
Passband ±0.05 dB 0.416 fs Hz
Stopband −6 dB 0.5 fs Hz
Passband ripple ±0.05 dB
Stopband attenuation f > 0.584 fs −60 dB
ADC Filter Characteristics ( TI DSP 272 fs and Normal Mode Operation )
Passband ±0.05 dB 0.4535 fs Hz
Stopband −6 dB 0.5 fs Hz
Passband ripple ±0.05 dB
Stopband attenuation f > 0.5465 fs −60 dB
ADC High-Pass Filter Characteristics
−3 dB, fs = 44.1 kHz 3.7 Hz
−3 dB, fs = 48 kHz 4.0 Hz
Corner frequency
−0.5 dB, fs = 44.1 kHz 10.4 Hz
−0.5 dB, fs = 48 kHz 11.3 Hz
−0.1 dB fs = 44.1 kHz 21.6 Hz
−0.1 dB, fs = 48 kHz 23.5 Hz
DAC Filter Characteristics (48-kHz Sampling Rate)
Passband ±0.03 dB 0.416 fs Hz
Stopband −6 dB 0.5 fs Hz
Passband ripple ±0.03 dB
Stopband attenuation f > 0.584 fs −50 dB
DAC Filter Characteristics (44.1-kHz Sampling Rate)
Passband ±0.03 dB 0.4535 fs Hz
Stopband −6 dB 0.5 fs Hz
Passband ripple ±0.03 dB
Stopband attenuation f > 0.5465 fs −50 dB
3−12
−6
−8
−10
Filter Response − dB
−4
−2
Normalized Audio Sampling Frequency
0
0 0.1 0.2 0.3
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
0.4 0.5
Figure 3−9. Digital De-Emphasis Filter Response − 44.1 kHz Sampling
−6
−8
−10
0 0.10 0.20 0.30
Filter Response − dB
−4
−2
Normalized Audio Sampling Frequency
0
0.40 0.50
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−10. Digital De-Emphasis Filter Response − 48 kHz Sampling
3−13
−70
−90
0 0.5 1 1.5
−50
−10
10
2 2.5 3
−30
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−11. ADC Digital Filter Response 0: USB Mode
(Group Delay = 12 Output Samples)
−0.04
−0.10
0 0.05 0.1 0.15 0.2 0.25 0.3
0
0.08
0.10
0.35 0.4 0.45 0.5
0.06
0.04
0.02
−0.02
−0.06
−0.08
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−12. ADC Digital Filter Ripple 0: USB
(Group Delay = 20 Output Samples)
3−14
−50
−90
0 0.5 1 1.5 2
−30
−10
10
2.5 3
−70
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−13. ADC Digital Filter Response 1: USB Mode Only
−0.04
−0.10
0 0.05 0.1 0.15 0.2 0.25 0.3
0
0.08
0.10
0.35 0.4 0.45 0.5
0.06
0.04
0.02
−0.02
−0.06
−0.08
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−14. ADC Digital Filter Ripple 1: USB Mode Only
3−15
−70
−90
0 0.5 1 1.5
−50
−10
10
2 2.5 3
−30
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−15. ADC Digital Filter Response 2: USB mode and Normal Modes
(Group Delay = 3 Output Samples)
−0.2
−0.4
0 0.05 0.1 0.15 0.2 0.25 0.3
0
0.3
0.4
0.35 0.4 0.45 0.5
0.2
0.1
−0.1
−0.3
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−16. ADC Digital Filter Ripple 2: USB Mode and Normal Modes
3−16
−50
−90
0 0.5 1 1.5
−30
−10
10
2 2.5 3
−70
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−17. ADC Digital Filter Response 3: USB Mode Only
−0.2
−0.4
0 0.05 0.10 0.15 0.20 0.25 0.30
0
0.3
0.4
0.35 0.40 0.45 0.50
0.2
0.1
−0.1
−0.3
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−18. ADC Digital Filter Ripple 3: USB Mode Only
3−17
−90
0 0.5 1 1.5
10
2 2.5 3
−10
−30
−50
−70
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−19. DAC Digital Filter Response 0: USB Mode
−0.04
−0.10
0 0.05 0.1 0.15 0.2 0.25 0.3
0
0.08
0.10
0.35 0.4 0.45 0.5
0.06
0.04
0.02
−0.02
−0.06
−0.08
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−20. DAC Digital Filter Ripple 0: USB Mode
3−18
−50
−90
0 0.5 1 1.5
−30
−10
10
2 2.5 3
−70
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−21. DAC Digital Filter Response 1: USB Mode Only
−0.04
−0.10
0 0.05 0.1 0.15 0.2 0.25 0.3
0.06
0.08
0.10
0.35 0.4 0.45 0.5
0.04
0.02
0
−0.02
−0.06
−0.08
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−22. DAC Digital Filter Ripple 1: USB Mode Only
3−19
−50
−90
0 0.5 1 1.5
−30
−10
10
2 2.5 3
−70
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−23. DAC Digital Filter Response 2: USB Mode and Normal Modes
−0.2
−0.4
0 0.05 0.1 0.15 0.2 0.25 0.3
0.2
0.3
0.4
0.35 0.4 0.45 0.5
0.1
0
−0.1
−0.3
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−24. DAC Digital Filter Ripple 2: USB Mode and Normal Modes
3−20
−70
−90
0 0.5 1 1.5
−30
−10
10
2 2.5 3
−50
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−25. DAC Digital Filter Response 3: USB Mode Only
−0.2
−0.4
0 0.05 0.1 0.15 0.2 0.25 0.3
0
0.3
0.4
0.35 0.4 0.45 0.5
0.2
0.1
−0.1
−0.3
Filter Response − dB
Normalized Audio Sampling Frequency
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3−26. DAC Digital Filter Ripple 3: USB Mode Only
The delay between the converter is a function of the sample rate. The group delays for the AIC23B are shown in the
following table. Each delay is one LR clock (1/sample rate).
Table 3−1. Group Dealys
FILTER GROUP DELAY
DAC type 0 11
DAC type 1 18
DAC type 2 5
DAC type 3 5
ADC type 0 12
ADC type 1 20
ADC type 2 3
ADC type 3 6
A−1
Appendix A
Mechanical Data
GQE/ZQE (S-PBGA-N80) PLASTIC BALL GRID ARRAY
5 6 7 8 9
J
H
G
F
E
D
1 2 3
C
B
A
4
4,00 TYP
5,10
4,90
SQ
0,50
0,50
4200461/C 10/00
Seating Plane
0,62
0,68
0,25
0,35
1,00 MAX
∅ 0,05 M 0,08
0,11
0,21
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar Junior BGA configuration
D. Falls within JEDEC MO-225
MicroStar Junior is a trademark of Texas Instruments.
A−2
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 0,10 M
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
16 20
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
8
0,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM
PINS **
0,05
4,90
5,10
Seating Plane
0°−8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
A−3
RHD (S−PQFP−N28) PLASTIC QUAD FLATPACK
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
B
0,08 C
D
4204400/A 05/02
1
28
0,05 MAX
SEATING PLANE
5,00
0,80
1,00
5,00
3,25
3,00
0,20 REF
DIE PAD
3,00
A
C
SQ
1
28
0,65
280,45
0,50
0,18
0,30
0,10 M C A B
EXPOSED THERMAL
0,435
0,435
0,18
0,18
PIN 1
INDEX AREA
IDENTIFIER
PIN 1
4
28
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. QFN (Quad Flatpack No−Lead) Package configuration.
D. The Package thermal performance may be enhanced by bonding the thermal die pad to
an external thermal plane. This pad is electrically and thermally connected to the backside
of the die and possibly selected ground leads.
E. Package complies to JEDEC MO-220.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jun-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TLV320AIC23BGQE ACTIVE BGA
MICROSTAR
JUNIOR
GQE 80 360 TBD SNPB Level-2A-235C-4 WKS 0 to 70 AIC23BG
TLV320AIC23BIGQE ACTIVE BGA
MICROSTAR
JUNIOR
GQE 80 360 TBD SNPB Level-2A-235C-4 WKS -40 to 85 AIC23BIG
TLV320AIC23BIPW ACTIVE TSSOP PW 28 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 AIC23BI
TLV320AIC23BIPWG4 ACTIVE TSSOP PW 28 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 AIC23BI
TLV320AIC23BIPWR ACTIVE TSSOP PW 28 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 AIC23BI
TLV320AIC23BIPWRG4 ACTIVE TSSOP PW 28 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 AIC23BI
TLV320AIC23BIRHD ACTIVE VQFN RHD 28 73 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 AIC23BI
TLV320AIC23BIRHDG4 ACTIVE VQFN RHD 28 73 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 AIC23BI
TLV320AIC23BIRHDR ACTIVE VQFN RHD 28 3000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 AIC23BI
TLV320AIC23BIZQE ACTIVE BGA
MICROSTAR
JUNIOR
ZQE 80 360 Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR -40 to 85 AIC23BIZ
TLV320AIC23BIZQER OBSOLETE BGA
MICROSTAR
JUNIOR
ZQE 80 TBD Call TI Call TI -40 to 85 AIC23BIZ
TLV320AIC23BPW ACTIVE TSSOP PW 28 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 AIC23B
TLV320AIC23BPWG4 ACTIVE TSSOP PW 28 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 AIC23B
TLV320AIC23BPWR ACTIVE TSSOP PW 28 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 AIC23B
TLV320AIC23BPWRG4 ACTIVE TSSOP PW 28 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM 0 to 70 AIC23B
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jun-2014
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TLV320AIC23BRHD ACTIVE VQFN RHD 28 73 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR 0 to 70 AIC23B
TLV320AIC23BRHDG4 ACTIVE VQFN RHD 28 73 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR 0 to 70 AIC23B
TLV320AIC23BRHDR ACTIVE VQFN RHD 28 3000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR 0 to 70 AIC23B
TLV320AIC23BRHDRG4 ACTIVE VQFN RHD 28 3000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR 0 to 70 AIC23B
TLV320AIC23BZQE ACTIVE BGA
MICROSTAR
JUNIOR
ZQE 80 360 Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR 0 to 70 AIC23BZ
TLV320AIC23BZQER ACTIVE BGA
MICROSTAR
JUNIOR
ZQE 80 2500 Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR 0 to 70 AIC23BZ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jun-2014
Addendum-Page 3
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV320AIC23B :
• Automotive: TLV320AIC23B-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
TLV320AIC23BIPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
TLV320AIC23BIRHDR VQFN RHD 28 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
TLV320AIC23BPWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
TLV320AIC23BRHDR VQFN RHD 28 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
TLV320AIC23BZQER BGA MI
CROSTA
R JUNI
OR
ZQE 80 2500 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-May-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV320AIC23BIPWR TSSOP PW 28 2000 367.0 367.0 38.0
TLV320AIC23BIRHDR VQFN RHD 28 3000 338.1 338.1 20.6
TLV320AIC23BPWR TSSOP PW 28 2000 367.0 367.0 38.0
TLV320AIC23BRHDR VQFN RHD 28 3000 338.1 338.1 20.6
TLV320AIC23BZQER BGA MICROSTAR
JUNIOR
ZQE 80 2500 338.1 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 8-May-2013
Pack Materials-Page 2
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Copyright © 2014, Texas Instruments Incorporated
FEATURES High accuracy; supports IEC 60687/61036/61268 and IEC 62053-21/62053-22/62053-23 On-chip digital integrator enables direct interface to current
sensors with di/dt output A PGA in the current channel allows direct interface to shunts and current transformers
Active, reactive, and apparent energy; sampled waveform; current and voltage rms Less than 0.1% error in active energy measurement over a dynamic range of 1000 to 1 at 25°C Positive-only energy accumulation mode available On-chip user programmable threshold for line voltage surge
and SAG and PSU supervisory Digital calibration for power, phase, and input offset
On-chip temperature sensor (±3°C typical)
SPI® compatible serial interface
Pulse output with programmable frequency
Interrupt request pin (IRQ) and status register Reference 2.4 V with external overdrive capability Single 5 V supply, low power (25 mW typical)
GENERAL DESCRIPTION
The ADE77531 features proprietary ADCs and DSP for high accuracy over large variations in environmental conditions and
time. The ADE7753 incorporates two second-order 16-bit -Δ
ADCs, a digital integrator (on CH1), reference circuitry, temperature sensor, and all the signal processing required to perform active, reactive, and apparent energy measurements, line-voltage period measurement, and rms calculation on the
voltage and current. The selectable on-chip digital integrator provides direct interface to di/dt current sensors such as Rogowski coils, eliminating the need for an external analog
integrator and resulting in excellent long-term stability and pre-
cise phase matching between the current and voltage channels. The ADE7753 provides a serial interface to read data, and a
pulse output frequency (CF), which is proportional to the active power. Various system calibration features, i.e., channel offset
correction, phase calibration, and power calibration, ensure
high accuracy. The part also detects short duration low or high voltage variations. The positive-only accumulation mode gives the option to accumulate energy only when positive power is detected. An internal no-load threshold ensures that the part does not exhibit
any creep when there is no load. The zero-crossing output (ZX)
produces a pulse that is synchronized to the zero-crossing point
of the line voltage. This signal is used internally in the line cycle
active and apparent energy accumulation modes, which enables
faster calibration. The interrupt status register indicates the nature of the interrupt,
and the interrupt enable register controls which event produces an output on the IRQ pin, an open-drain, active low logic output.
The ADE7753 is available in a 20-lead SSOP package. FUNCTIONAL BLOCK DIAGRAM
AVDD RESET DVDDDGND
TEMP
SENSOR
ADC
ADC
DFC
x2
ADE7753
LPF2 MULTIPLIER
INTEGRATOR
CLKIN CLKOUT DINDOUTSCLK REFIN/OUT CS IRQ AGND
APOS[15:0]
VAGAIN[11:0]
VADIV[7:0]
IRMSOS[11:0]
VRMSOS[11:0]
WGAIN[11:0]
dt
REGISTERS AND
SERIAL INTERFACE
CFNUM[11:0]
CFDEN[11:0]
2.4V
REFERENCE
4k
PHCAL[5:0]
HPF1
LPF1
02875-A-001
V1P
V1N
V2N
V2P
PGA
PGA
ZX
SAG
CF
WDIV[7:0] % %
2
|x|
Figure 1.
1U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469.
ADE7753
Rev. C | Page 2 of 60
TABLE OF CONTENTS
Features .............................................................................................. 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
Timing Characteristics ..................................................................... 6
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Terminology ...................................................................................... 8
Pin Configuration and Function Descriptions ............................. 9
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 16
Analog Inputs .............................................................................. 16
di/dt Current Sensor and Digital Integrator ............................... 17
Zero-Crossing Detection ........................................................... 18
Period Measurement .................................................................. 19
Power Supply Monitor ............................................................... 19
Line Voltage Sag Detection ....................................................... 19
Peak Detection ............................................................................ 20
ADE7753 Interrupts ................................................................... 21
Temperature Measurement ....................................................... 22
ADE7753 Analog-to-Digital Conversion ................................ 22
Channel 1 ADC .......................................................................... 23
Channel 2 ADC .......................................................................... 25
Phase Compensation .................................................................. 27
Active Power Calculation .......................................................... 28
Energy Calculation ..................................................................... 29
Power Offset Calibration ........................................................... 31
Energy-to-Frequency Conversion............................................ 31
Line Cycle Energy Accumulation Mode ................................. 33
Positive-Only Accumulation Mode ......................................... 33
No-Load Threshold .................................................................... 33
Reactive Power Calculation ...................................................... 33
Sign of Reactive Power Calculation ......................................... 35
Apparent Power Calculation ..................................................... 35
Apparent Energy Calculation ................................................... 36
Line Apparent Energy Accumulation ...................................... 37
Energies Scaling .......................................................................... 38
Calibrating an Energy Meter Based on the ADE7753 ........... 38
CLKIN Frequency ...................................................................... 48
Suspending ADE7753 Functionality ....................................... 48
Checksum Register..................................................................... 48
ADE7753 Serial Interface .......................................................... 49
ADE7753 Registers ......................................................................... 52
ADE7753 Register Descriptions ................................................... 55
Communications Register ......................................................... 55
Mode Register (0x09) ................................................................. 55
Interrupt Status Register (0x0B), Reset Interrupt Status Register (0x0C), Interrupt Enable Register (0x0A) .............. 57
CH1OS Register (0x0D) ............................................................ 58
Outline Dimensions ....................................................................... 59
Ordering Guide .......................................................................... 59
ADE7753
Rev. C | Page 3 of 60
REVISION HISTORY
1/10—Rev. B to Rev C
Changes to Figure 1 ........................................................................... 1
Changes to t6 Parameter (Table 2) ................................................... 6
Added Endnote 1 to Table 4 ............................................................. 9
Changes to Figure 32 ...................................................................... 16
Changes to Period Measurement Section .................................... 19
Changes to Temperature Measurement Section ......................... 22
Changes to Figure 51 ...................................................................... 24
Changes to Channel 1 RMS Calculation Section ........................ 25
Added Table 7 .................................................................................. 25
Changes to Channel 2 RMS Calculation Section ........................ 26
Added Table 8 .................................................................................. 26
Changes to Figure 64 ...................................................................... 29
Changes to Apparent Power Calculation Section ....................... 35
1/09—Rev. A to Rev B
Changes to Features Section ............................................................ 1
Changes to Zero-Crossing Detection Section and Period Measurement Section ..................................................................... 19
Changes to Channel 1 RMS Calculation Section, Channel 1 RMS Offset Compensation Section, and Equation 4 ................. 25
Changes to Figure 56 and Channel 2 RMS Calculation Section .............................................................................................. 26
Changes to Figure 57 ...................................................................... 27
Changes to Energy Calculation Section ....................................... 30
Changes to Energy-to-Frequency Conversion Section .............. 31
Changes to Apparent Energy Calculation Section...................... 36
Changes to Line Apparent Energy Accumulation Section ........ 37
Changes to Table 10 ........................................................................ 52
Changes to Table 12 ........................................................................ 56
Changes to Table 13 ........................................................................ 57
Changes to Ordering Guide ........................................................... 59
6/04—Rev. 0 to Rev A
Changes IEC Standards .................................................................... 1
Changes to Phase Error Between Channels Definition ............... 7
Changes to Figure 24 ...................................................................... 13
Changes to CH2OS Register .......................................................... 16
Change to the Period Measurement Section ............................... 18
Change to Temperature Measurement Section ........................... 21
Changes to Figure 69 ...................................................................... 31
Changes to Figure 71 ...................................................................... 33
Changes to the Apparent Energy Section .................................... 36
Changes to Energies Scaling Section ............................................ 37
Changes to Calibration Section ..................................................... 37
8/03—Revision 0: Initial Version
ADE7753
Rev. C | Page 4 of 60
SPECIFICATIONS
AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.579545 MHz XTAL, TMIN to TMAX = −40°C to +85°C. See the plots in the Typical Performance Characteristics section.
Table 1.
Parameter
Spec
Unit
Test Conditions/Comments
ENERGY MEASUREMENT ACCURACY
Active Power Measurement Error
CLKIN = 3.579545 MHz
Channel 1 Range = 0.5 V Full Scale
Channel 2 = 300 mV rms/60 Hz, gain = 2
Gain = 1
0.1
% typ
Over a dynamic range 1000 to 1
Gain = 2
0.1
% typ
Over a dynamic range 1000 to 1
Gain = 4
0.1
% typ
Over a dynamic range 1000 to 1
Gain = 8
0.1
% typ
Over a dynamic range 1000 to 1
Channel 1 Range = 0.25 V Full Scale
Gain = 1
0.1
% typ
Over a dynamic range 1000 to 1
Gain = 2
0.1
% typ
Over a dynamic range 1000 to 1
Gain = 4
0.1
% typ
Over a dynamic range 1000 to 1
Gain = 8
0.2
% typ
Over a dynamic range 1000 to 1
Channel 1 Range = 0.125 V Full Scale
Gain = 1
0.1
% typ
Over a dynamic range 1000 to 1
Gain = 2
0.1
% typ
Over a dynamic range 1000 to 1
Gain = 4
0.2
% typ
Over a dynamic range 1000 to 1
Gain = 8
0.2
% typ
Over a dynamic range 1000 to 1
Active Power Measurement Bandwidth
14
kHz
Phase Error 1 between Channels1
±0.05
max
Line Frequency = 45 Hz to 65 Hz, HPF on
AC Power Supply Rejection1
AVDD = DVDD = 5 V + 175 mV rms/120 Hz
Output Frequency Variation (CF)
0.2
% typ
Channel 1 = 20 mV rms, gain = 16, range = 0.5 V
Channel 2 = 300 mV rms/60 Hz, gain = 1
DC Power Supply Rejection1
AVDD = DVDD = 5 V ± 250 mV dc
Output Frequency Variation (CF)
±0.3
% typ
Channel 1 = 20 mV rms/60 Hz, gain = 16, range = 0.5 V
Channel 2 = 300 mV rms/60 Hz, gain = 1
IRMS Measurement Error
0.5
% typ
Over a dynamic range 100 to 1
IRMS Measurement Bandwidth
14
kHz
VRMS Measurement Error
0.5
% typ
Over a dynamic range 20 to 1
VRMS Measurement Bandwidth
140
Hz
ANALOG INPUTS2
See the Analog Inputs section
Maximum Signal Levels
±0.5
V max
V1P, V1N, V2N, and V2P to AGND
Input Impedance (dc)
390
k min
Bandwidth
14
kHz
CLKIN/256, CLKIN = 3.579545 MHz
Gain Error1, 2
External 2.5 V reference, gain = 1 on Channels 1 and 2
Channel 1
Range = 0.5 V Full Scale
±4
% typ
V1 = 0.5 V dc
Range = 0.25 V Full Scale
±4
% typ
V1 = 0.25 V dc
Range = 0.125 V Full Scale
±4
% typ
V1 = 0.125 V dc
Channel 2
±4
% typ
V2 = 0.5 V dc
Offset Error1
±32
mV max
Gain 1
Channel 1
±13
mV max
Gain 16
±32
mV max
Gain 1
Channel 2
±13
mV max
Gain 16
WAVEFORM SAMPLING
Sampling CLKIN/128, 3.579545 MHz/128 = 27.9 kSPS
Channel 1
See the Channel 1 Sampling section
Signal-to-Noise Plus Distortion
62
dB typ
150 mV rms/60 Hz, range = 0.5 V, gain = 2
Bandwidth(–3 dB)
14
kHz
CLKIN = 3.579545 MHz
ADE7753
Rev. C | Page 5 of 60
Parameter Spec Unit Test Conditions/Comments
Channel 2
See the Channel 2 Sampling section
Signal-to-Noise Plus Distortion
60
dB typ
150 mV rms/60 Hz, gain = 2
Bandwidth (–3 dB)
140
Hz
CLKIN = 3.579545 MHz
REFERENCE INPUT
REFIN/OUT Input Voltage Range
2.6
V max
2.4 V + 8%
2.2
V min
2.4 V – 8%
Input Capacitance
10
pF max
ON-CHIP REFERENCE
Nominal 2.4 V at REFIN/OUT pin
Reference Error
±200
mV max
Current Source
10
μA max
Output Impedance
3.4
kΩ min
Temperature Coefficient
30
ppm/°C typ
CLKIN
All specifications CLKIN of 3.579545 MHz
Input Clock Frequency
4
MHz max
1
MHz min
LOGIC INPUTS
RESET, DIN, SCLK, CLKIN, and CS
Input High Voltage, VINH
2.4
V min
DVDD = 5 V ± 10%
Input Low Voltage, VINL
0.8
V max
DVDD = 5 V ± 10%
Input Current, IIN
±3
μA max
Typically 10 nA, VIN = 0 V to DVDD
Input Capacitance, CIN
10
pF max
LOGIC OUTPUTS
SAG and IRQ
Open-drain outputs, 10 kΩ pull-up resistor
Output High Voltage, VOH
4
V min
ISOURCE = 5 mA
Output Low Voltage, VOL 0.4
V max
ISINK = 0.8 mA
ZX and DOUT
Output High Voltage, VOH
4
V min
ISOURCE = 5 mA
Output Low Voltage, VOL 0.4
V max
ISINK = 0.8 mA
CF
Output High Voltage, VOH
4
V min
ISOURCE = 5 mA
Output Low Voltage, VOL 1
V max
ISINK = 7 mA
POWER SUPPLY
For specified performance
AVDD
4.75
V min
5 V – 5%
5.25
V max
5 V + 5%
DVDD
4.75
V min
5 V – 5%
5.25
V max
5 V + 5%
AIDD
3
mA max
Typically 2.0 mA
DIDD
4
mA max
Typically 3.0 mA
1 See the Terminology section for explanation of specifications.
2 See the Analog Inputs section.
+2.1V1.6mAIOHIOl200μACL50pF02875-0-002TOOUTPUTPIN
Figure 2. Load Circuit for Timing Specifications
ADE7753
Rev. C | Page 6 of 60
TIMING CHARACTERISTICS
AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.579545 MHz XTAL, TMIN to TMAX = −40°C to +85°C. Sample tested during initial release and after any redesign or process change that could affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to 90%) and timed from a voltage level of 1.6 V. See Figure 3, Figure 4, and the ADE7753 Serial Interface section.
Table 2.
Parameter
Spec
Unit
Test Conditions/Comments
Write Timing
t1
50
ns (min)
CS falling edge to first SCLK falling edge.
t2
50
ns (min)
SCLK logic high pulse width.
t3
50
ns (min)
SCLK logic low pulse width.
t4
10
ns (min)
Valid data setup time before falling edge of SCLK.
t5
5
ns (min)
Data hold time after SCLK falling edge.
t6
4
μs (min)
Minimum time between the end of data byte transfers.
t7
50
ns (min)
Minimum time between byte transfers during a serial write.
t8
100
ns (min)
CS hold time after SCLK falling edge.
Read Timing
t91
4
μs (min)
Minimum time between read command (i.e., a write to communication register) and data read.
t10
50
ns (min)
Minimum time between data byte transfers during a multibyte read.
t11
30
ns (min)
Data access time after SCLK rising edge following a write to the communications register.
t122
100
ns (max)
Bus relinquish time after falling edge of SCLK.
10
ns (min)
t133
100
ns (max)
Bus relinquish time after rising edge of CS.
10
ns (min)
1 Minimum time between read command and data read for all registers except waveform register, which is t9 = 500 ns min.
2 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
3 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. DINSCLKCSt2t3t1t4t5t7t6t8COMMAND BYTEMOST SIGNIFICANT BYTELEAST SIGNIFICANT BYTE10A4A5A3A2A1A0DB7DB0DB7DB0t702875-0-081
Figure 3. Serial Write Timing SCLKCSt1t10t1300A4A5A3A2A1A0DB0DB7DB0DB7DINDOUTt11t11t12COMMAND BYTEMOST SIGNIFICANT BYTELEAST SIGNIFICANT BYTEt902875-0-083
Figure 4. Serial Read Timing
ADE7753
Rev. C | Page 7 of 60
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
Rating
AVDD to AGND
–0.3 V to +7 V
DVDD to DGND
–0.3 V to +7 V
DVDD to AVDD
–0.3 V to +0.3 V
Analog Input Voltage to AGND, V1P, V1N, V2P, and V2N
–6 V to +6 V
Reference Input Voltage to AGND
–0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND
–0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND
–0.3 V to DVDD + 0.3 V
Operating Temperature Range
Industrial
–40°C to +85°C
Storage Temperature Range
–65°C to +150°C
Junction Temperature
150°C
20-Lead SSOP, Power Dissipation
450 mW
θJA Thermal Impedance
112°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec)
215°C
Infrared (15 sec)
220°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
ADE7753
Rev. C | Page 8 of 60
TERMINOLOGY
Measurement Error
The error associated with the energy measurement made by the ADE7753 is defined by the following formula: %1007753×⎟⎟⎠⎞⎜⎜⎝⎛−=EnergyTrueEnergyTrueADERegisterEnergyErrorPercentage
Phase Error between Channels
The digital integrator and the high-pass filter (HPF) in Channel 1 have a non-ideal phase response. To offset this phase response and equalize the phase response between channels, two phase-correction networks are placed in Channel 1: one for the digital integrator and the other for the HPF. The phase correction networks correct the phase response of the corresponding component and ensure a phase match between Channel 1 (current) and Channel 2 (voltage) to within ±0.1° over a range of 45 Hz to 65 Hz with the digital integrator off. With the digital integrator on, the phase is corrected to within ±0.4° over a range of 45 Hz to 65 Hz.
Power Supply Rejection
This quantifies the ADE7753 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (5 V) is taken. A second reading is obtained with the same input signal levels when an ac (175 mV rms/120 Hz) signal is introduced onto the supplies. Any error introduced by this ac signal is expressed as a percentage of reading—see the Measurement Error definition.
For the dc PSR measurement, a reading at nominal supplies (5 V) is taken. A second reading is obtained with the same input signal levels when the supplies are varied ±5%. Any error introduced is again expressed as a percentage of the reading.
ADC Offset Error
The dc offset associated with the analog inputs to the ADCs. It means that with the analog inputs connected to AGND, the ADCs still see a dc analog input signal. The magnitude of the offset depends on the gain and input range selection—see the Typical Performance Characteristics section. However, when HPF1 is switched on, the offset is removed from Channel 1 (current) and the power calculation is not affected by this offset. The offsets can be removed by performing an offset calibration—see the Analog Inputs section.
Gain Error
The difference between the measured ADC output code (minus the offset) and the ideal output code—see the Channel 1 ADC and Channel 2 ADC sections. It is measured for each of the input ranges on Channel 1 (0.5 V, 0.25 V, and 0.125 V). The difference is expressed as a percentage of the ideal code.
ADE7753
Rev. C | Page 9 of 60
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V2N6V2P7AGND8REFIN/OUT9DGND10CLKINIRQSAGZXCF1514131211ADE7753TOP VIEW(Not to Scale)DVDD2AVDD3V1P4V1N5DOUTSCLKCSCLKOUT1918RESET1DIN20171602875-0-005
Figure 5. Pin Configuration (SSOP Package)
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
RESET1
Reset Pin for the ADE7753. A logic low on this pin holds the ADCs and digital circuitry (including the serial interface) in a reset condition.
2
DVDD
Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7753. The supply voltage should be maintained at 5 V ± 5% for specified operation. This pin should be decoupled to DGND with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.
3
AVDD
Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the ADE7753. The supply should be maintained at 5 V ± 5% for specified operation. Every effort should be made to minimize power supply ripple and noise at this pin by the use of proper decoupling. The typical performance graphs show the power supply rejection performance. This pin should be decoupled to AGND with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.
4, 5
V1P, V1N
Analog Inputs for Channel 1. This channel is intended for use with a di/dt current transducer such as a Rogowski coil or another current sensor such as a shunt or current transformer (CT). These inputs are fully differential voltage inputs with maximum differential input signal levels of ±0.5 V, ±0.25 V, and ±0.125 V, depending on the full-scale selection—see the Analog Inputs section. Channel 1 also has a PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins with respect to AGND is ±0.5 V. Both inputs have internal ESD protection circuitry, and, in addition, an overvoltage of ±6 V can be sustained on these inputs without risk of permanent damage.
6, 7
V2N, V2P
Analog Inputs for Channel 2. This channel is intended for use with the voltage transducer. These inputs are fully differential voltage inputs with a maximum differential signal level of ±0.5 V. Channel 2 also has a PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins with respect to AGND is ±0.5 V. Both inputs have internal ESD protection circuitry, and an overvoltage of ±6 V can be sustained on these inputs without risk of permanent damage.
8
AGND
Analog Ground Reference. This pin provides the ground reference for the analog circuitry in the ADE7753, i.e., ADCs and reference. This pin should be tied to the analog ground plane or the quietest ground reference in the system. This quiet ground reference should be used for all analog circuitry, for example, anti-aliasing filters, current and voltage transducers, etc. To keep ground noise around the ADE7753 to a minimum, the quiet ground plane should connected to the digital ground plane at only one point. It is acceptable to place the entire device on the analog ground plane.
9
REFIN/OUT
Access to the On-Chip Voltage Reference. The on-chip reference has a nominal value of 2.4 V ± 8% and a typical temperature coefficient of 30 ppm/°C. An external reference source can also be connected at this pin. In either case, this pin should be decoupled to AGND with a 1 μF ceramic capacitor.
10
DGND
Digital Ground Reference. This pin provides the ground reference for the digital circuitry in the ADE7753, i.e., multiplier, filters, and digital-to-frequency converter. Because the digital return currents in the ADE7753 are small, it is acceptable to connect this pin to the analog ground plane of the system. However, high bus capacitance on the DOUT pin could result in noisy digital current, which could affect performance.
11
CF
Calibration Frequency Logic Output. The CF logic output gives active power information. This output is intended to be used for operational and calibration purposes. The full-scale output frequency can be adjusted by writing to the CFDEN and CFNUM registers—see the Energy-to-Frequency Conversion section.
ADE7753
Rev. C | Page 10 of 60
Pin No. Mnemonic
Description
12
ZX
Voltage Waveform (Channel 2) Zero-Crossing Output. This output toggles logic high and logic low at the zero crossing of the differential signal on Channel 2—see the Zero-Crossing Detection section.
13
SAG
This open-drain logic output goes active low when either no zero crossings are detected or a low voltage threshold (Channel 2) is crossed for a specified duration—see the Line Voltage Sag Detection section.
14
IRQ
Interrupt Request Output. This is an active low open-drain logic output. Maskable interrupts include active energy register rollover, active energy register at half level, and arrivals of new waveform samples—see the ADE7753 Interrupts section.
15
CLKIN
Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7753. The clock frequency for specified operation is 3.579545 MHz. Ceramic load capacitors of between 22 pF and 33 pF should be used with the gate oscillator circuit. Refer to the crystal manufacturer’s data sheet for load capacitance requirements.
16
CLKOUT
A crystal can be connected across this pin and CLKIN as described for Pin 15 to provide a clock source for the ADE7753. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN or a crystal is being used.
17
CS
Chip Select. Part of the 4-wire SPI serial interface. This active low logic input allows the ADE7753 to share the serial bus with several other devices—see the ADE7753 Serial Interface section.
18
SCLK
Serial Clock Input for the Synchronous Serial Interface. All serial data transfers are synchronized to this clock—see the ADE7753 Serial Interface section. The SCLK has a Schmitt-trigger input for use with a clock source that has a slow edge transition time, for example, opto-isolator output.
19
DOUT
Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of SCLK. This logic output is normally in a high impedance state unless it is driving data onto the serial data bus—see the ADE7753 Serial Interface section.
20
DIN
Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of SCLK—see the ADE7753 Serial Interface section.
1 It is recommended to drive the RESET, SCLK, and CS pins with either a push-pull without an external series resistor or with an open-collector with a 10 kΩ pull-up resistor. Pull-down resistors are not recommended because under some conditions, they may interact with internal circuitry.
ADE7753
Rev. C | Page 11 of 60
TYPICAL PERFORMANCE CHARACTERISTICS FULL-SCALE CURRENT (%)ERROR (%)0.1–0.5–0.1–0.2–0.3–0.40.20.10.50.40.3011010002875-0-006+85°C, PF = 0.5+25°C, PF = 0.5GAIN = 1INTEGRATOR OFFINTERNAL REFERENCE+25°C, PF = 1–40°C, PF = 0.5
Figure 6. Active Energy Error as a Percentage of Reading (Gain = 1) over Power Factor with Internal Reference and Integrator Off FULL-SCALE CURRENT (%)ERROR (%)0.1–0.4–0.2–0.1–0.30.10.40.30.2011010002875-0-008+25°C, PF = 1GAIN = 8INTEGRATOR OFFINTERNAL REFERENCE–40°C, PF = 1+85°C, PF = 1
Figure 7. Active Energy as a Percentage of Reading (Gain = 8) over Temperature with Internal Reference and Integrator Off FULL-SCALE CURRENT (%)ERROR (%)0.1–0.6–0.2–0.40.20.80.60.4011010002875-0-009+85°C, PF = 0.5GAIN = 8INTEGRATOR OFFINTERNAL REFERENCE–40°C, PF = 0.5+25°C, PF = 1+25°C, PF = 0.5
Figure 8. Active Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with Internal Reference and Integrator Off FULL-SCALE CURRENT (%)ERROR (%)0.1–0.3–0.1–0.20.10.30.20110100GAIN = 8INTEGRATOR OFFEXTERNAL REFERENCE+85°C, PF = 102875-0-010–40°C, PF = 1+25°C, PF = 1
Figure 9. Active Energy Error as a Percentage of Reading (Gain = 8) over Temperature with External Reference and Integrator Off FULL-SCALE CURRENT (%)ERROR (%)0.1–0.6–0.2–0.40.20.60.40110100GAIN = 8INTEGRATOR OFFEXTERNAL REFERENCE+85°C, PF = 0.502875-0-011–40°C, PF = 0.5+25°C, PF = 0.5+25°C, PF = 1
Figure 10. Active Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with External Reference and Integrator Off FULL-SCALE CURRENT (%)ERROR (%)0.1–0.5–0.1–0.2–0.3–0.40.20.10.50.40.3011010002875-0-012+85°C, PF = 0.5+25°C, PF = 0.5GAIN = 1INTEGRATOR OFFINTERNAL REFERENCE+25°C, PF = 0–40°C, PF = 0.5
Figure 11. Reactive Energy Error as a Percentage of Reading (Gain = 1) over Power Factor with Internal Reference and Integrator Off
ADE7753
Rev. C | Page 12 of 60
FULL-SCALE CURRENT (%)ERROR (%)0.1–0.5–0.1–0.2–0.3–0.40.20.10.50.40.3011010002875-0-013+85°C, PF = 0.5+25°C, PF = 0.5GAIN = 1INTEGRATOR OFFEXTERNAL REFERENCE+25°C, PF = 0–40°C, PF = 0.5
Figure 12. Reactive Energy Error as a Percentage of Reading (Gain = 1) over Power Factor with External Reference and Integrator Off FULL-SCALE CURRENT (%)ERROR (%)0.1–0.20–0.10–0.05–0.150.050.200.150.10011010002875-0-014+85°C, PF = 0GAIN = 8INTEGRATOR OFFINTERNAL REFERENCE–40°C, PF = 0+25°C, PF = 0
Figure 13. Reactive Energy Error as a Percentage of Reading (Gain = 8) over Temperature with Internal Reference and Integrator Off FULL-SCALE CURRENT (%)ERROR (%)0.1–0.3–0.1–0.20.10.30.20110100GAIN = 8INTEGRATOR OFFINTERNAL REFERENCE02875-0-015+25°C, PF = 0.5+25°C, PF = 0–40°C, PF = 0.5+85°C, PF = 0.5
Figure 14. Reactive Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with Internal Reference and Integrator Off FULL-SCALE CURRENT (%)ERROR (%)0.1–0.35–0.15–0.05–0.250.050.350.250.15110100GAIN = 8INTEGRATOR OFFEXTERNAL REFERENCE02875-0-016–40°C, PF = 0+85°C, PF = 0+25°C, PF = 0
Figure 15. Reactive Energy Error as a Percentage of Reading (Gain = 8) over Temperature with External Reference and Integrator Off FULL-SCALE CURRENT (%)ERROR (%)0.1–0.5–0.1–0.2–0.3–0.40.20.10.50.40.3011010002875-0-017GAIN = 8INTEGRATOR OFFEXTERNAL REFERENCE+25°C, PF = 0+85°C, PF = 0.5–40°C, PF = 0.5+25°C, PF = 0.5
Figure 16. Reactive Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with External Reference and Integrator Off FULL-SCALE CURRENT (%)ERROR (%)0.1–0.3–0.1–0.20.10.30.20110100GAIN = 8INTEGRATOR OFFINTERNAL REFERENCE5.25V02875-0-0184.75V5.0V
Figure 17. Active Energy Error as a Percentage of Reading (Gain = 8) over Power Supply with Internal Reference and Integrator Off
ADE7753
Rev. C | Page 13 of 60
LINE FREQUENCY (Hz)ERROR (%)45–0.1–0.2–0.4–0.6–0.80.40.20.10.80.605055606502875-0-019PF = 0.5GAIN = 8INTEGRATOR OFFEXTERNAL REFERENCEPF = 1
Figure 18. Active Energy Error as a Percentage of Reading (Gain = 8) over Frequency with External Reference and Integrator Off FULL-SCALE CURRENT (%)ERROR (%)0.1–0.5–0.1–0.2–0.3–0.40.20.10.50.40.3011010002875-0-020GAIN = 8INTEGRATOR OFFINTERNAL REFERENCEPF = 1PF = 0.5
Figure 19. IRMS Error as a Percentage of Reading (Gain = 8) with Internal Reference and Integrator Off FULL-SCALE CURRENT (%)ERROR (%)0.1–1.0–0.2–0.4–0.6–0.80.40.21.00.80.6011010002875-0-022GAIN = 8INTEGRATOR ONINTERNAL REFERENCE+25°C, PF = 0.5–40°C, PF = 0.5+85°C, PF = 0.5+25°C, PF = 1
Figure 20. Active Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with Internal Reference and Integrator On FULL-SCALE CURRENT (%)ERROR (%)0.1–1.0–0.2–0.4–0.6–0.80.40.21.00.80.6011010002875-0-023GAIN = 8INTEGRATOR ONINTERNAL REFERENCE–40°C, PF = 185°C, PF = 125°C, PF = 1
Figure 21. Active Energy Error as a Percentage of Reading (Gain = 8) over Temperature with Internal Reference and Integrator On FULL-SCALE CURRENT (%)ERROR (%)0.1–1.0–0.2–0.4–0.6–0.80.40.21.00.80.6011010002875-0-024GAIN = 8INTEGRATOR ONINTERNAL REFERENCE+85°C, PF = 0.5–40°C, PF = 0.5+25°C, PF = 0.5+25°C, PF = 0
Figure 22. Reactive Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with Internal Reference and Integrator On FULL-SCALE CURRENT (%)ERROR (%)0.1–1.0–0.2–0.4–0.6–0.80.40.21.00.80.6011010002875-0-025GAIN = 8INTEGRATOR ONINTERNAL REFERENCE+85°C, PF = 0–40°C, PF = 0+25°C, PF = 0
Figure 23. Reactive Energy Error as a Percentage of Reading (Gain = 8) over Temperature with Internal Reference and Integrator On
ADE7753
Rev. C | Page 14 of 60
02875-0-026–2.0–1.5–1.0–0.500.51.01.52.02.53.0ERROR (%)4547495153555759616365FREQUENCY (Hz)GAIN = 8INTEGRATOR ONINTERNAL REFERENCEPF = 0.5PF = 1
Figure 24. Active Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with Internal Reference and Integrator On FULL-SCALE CURRENT (%)ERROR (%)0.1–0.3–0.1–0.20.10.30.20110100GAIN = 8INTEGRATOR ONINTERNAL REFERENCE5.25V02875-0-0274.75V5.0V
Figure 25. Active Energy Error as a Percentage of Reading (Gain = 8) over Power Supply with Internal Reference and Integrator On FULL-SCALE CURRENT (%)ERROR (%)0.1–0.5–0.1–0.2–0.3–0.40.20.10.50.40.3011010002875-0-028GAIN = 8INTEGRATOR ONINTERNAL REFERENCEPF = 1PF = 0.5
Figure 26. IRMS Error as a Percentage of Reading (Gain = 8) with Internal Reference and Integrator On FULL-SCALE VOLTAGEERROR (%)1–0.2–0.4–0.6–0.80.40.20.80.601010002875-0-029GAIN = 1EXTERNAL REFERENCE
Figure 27. VRMS Error as a Percentage of Reading (Gain = 1) with External Reference
02875-0-087CH1 OFFSET (0p5V_1X) (mV)HITS–15–12–9–6–303642068
Figure 28. Channel 1 Offset (Gain = 1)
ADE7753
Rev. C | Page 15 of 60
VDD10μF10μF10μF100nF100nFAVDDDVDDRESETDINDOUTSCLKCSCLKOUTCLKINIRQSAGZXCFAGNDDGNDV1PV1NV2NV2PREFIN/OUTU1ADE7753TOSPIBUS(USEDONLYFORCALIBRATION)22pF22pFY13.58MHzNOT CONNECTEDU3PS2501-1Idi/dt CURRENTSENSOR100Ω1kΩ33nF33nF100Ω1kΩ33nF33nF1kΩ33nF600kΩ110V1kΩ33nF100nFCHANNEL 1 GAIN = 8CHANNEL 2 GAIN = 1TOFREQUENCYCOUNTER02875-A-012
Figure 29. Test Circuit for Performance Curves with Integrator On CT TURN RATIO = 1800:1CHANNEL 2 GAIN = 1RB10Ω1.21ΩGAIN 1 (CH1)18NOT CONNECTEDVDD10μF1μF100nF100nFDINDOUTSCLKCSCLKOUTCLKINIRQSAGZXCFAGNDDGNDV1PV1NV2NV2PREFIN/OUTU1ADE7753TOSPIBUS(USEDONLYFORCALIBRATION)22pF22pFY13.58MHzU3PS2501-1ICURRENTTRANSFORMER1kΩ33nF1kΩ33nF1kΩ33nF600kΩ RB110V1kΩ33nF10μF100nFTOFREQUENCYCOUNTER02875-0-030AVDDDVDDRESET
Figure 30. Test Circuit for Performance Curves with Integrator Off
ADE7753
Rev. C | Page 16 of 60
THEORY OF OPERATION
ANALOG INPUTS
The ADE7753 has two fully differential voltage input channels.
The maximum differential input voltage for input pairs V1P/V1N
and V2P/V2N is ±0.5 V. In addition, the maximum signal level
on analog inputs for V1P/V1N and V2P/ V2N is ±0.5 V with respect to AGND. Each analog input channel has a programmable gain amplifier
(PGA) with possible gain selections of 1, 2, 4, 8, and 16. The
gain selections are made by writing to the gain register—see Figure 32. Bits 0 to 2 select the gain for the PGA in Channel 1, and the gain selection for the PGA in Channel 2 is made via
Bits 5 to 7. Figure 31 shows how a gain selection for Channel 1
is made using the gain register. V1P
V1N
VIN K × VIN
+
GAIN[7:0]
7 6 543210
0 0 000000
7 6543210
0 0000000
GAIN (K)
SELECTION
OFFSET ADJUST
(±50mV)
CH1OS[7:0]
BITS 0 to 5: SIGN MAGNITUDE CODED OFFSET CORRECTION
BIT 6: NOT USED
BIT 7: DIGITAL INTEGRATOR (ON = 1, OFF = 0; DEFAULT OFF)
02875-0-031
Figure 31. PGA in Channel 1
In addition to the PGA, Channel 1 also has a full-scale input
range selection for the ADC. The ADC analog input range
selection is also made using the gain register—see Figure 32. As mentioned previously, the maximum differential input voltage
is 0.5 V. However, by using Bits 3 and 4 in the gain register, the
maximum ADC input voltage can be set to 0.5 V, 0.25 V, or 0.125 V. This is achieved by adjusting the ADC reference—see
the ADE7753 Reference Circuit section. Table 5 summarizes the
maximum differential input signal level on Channel 1 for the
various ADC range and gain selections. Table 5. Maximum Input Signal Levels for Channel 1 Max Signal ADC Input Range Selection Channel 1 0.5 V 0.25 V 0.125 V 0.5 V Gain = 1 − −
0.25 V Gain = 2 Gain = 1 −
0.125 V Gain = 4 Gain = 2 Gain = 1 0.0625 V Gain = 8 Gain = 4 Gain = 2 0.0313 V Gain = 16 Gain = 8 Gain = 4 0.0156 V − Gain = 16 Gain = 8 0.00781 V − − Gain = 16 GAIN REGISTER*
CHANNEL 1 AND CHANNEL 2 PGA CONTROL
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 ADDR:
0x0F
*REGISTER CONTENTS
SHOW POWER-ON DEFAULTS
PGA 2 GAIN SELECT
000 = × 1
001 = × 2
010 = × 4
011 = × 8
100 = × 16
PGA 1 GAIN SELECT
000 = × 1
001 = × 2
010 = × 4
011 = × 8
100 = × 16
CHANNEL 1 FULL-SCALE SELECT
00 = 0.5V
01 = 0.25V
10 = 0.125V 02875-0-032
Figure 32. ADE7753 Analog Gain Register It is also possible to adjust offset errors on Channel 1 and
Channel 2 by writing to the offset correction registers, CH1OS
and CH2OS, respectively. These registers allow channel offsets in the range ±20 mV to ±50 mV (depending on the gain setting)
to be removed. Channel 1 and 2 offset registers are sign magni-
tude coded. A negative number is applied to the Channel 1
offset register, CH1OS, for a negative offset adjustment. Note that the Channel 2 offset register is inverted. A negative number is applied to CH2OS for a positive offset adjustment. It is not
necessary to perform an offset correction in an energy measure-
ment application if HPF in Channel 1 is switched on. Figure 33 shows the effect of offsets on the real power calculation. As seen from Figure 33, an offset on Channel 1 and Channel 2 contributes a dc component after multiplication. Because this dc component is extracted by LPF2 to generate the active (real) power information, the offsets contribute an error to the active power calculation. This problem is easily avoided by enabling HPF in Channel 1. By removing the offset from at least one
channel, no error component is generated at dc by the
multiplication. Error terms at cos(ωt) are removed by LPF2 and
by integration of the active power signal in the active energy register (AENERGY[23:0]) —see the Energy Calculation section.
ADE7753
Rev. C | Page 17 of 60
DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR REAL
POWER CALCULATION
FREQUENCY (RAD/S)
IOS × V
VOS × I
VOS × IOS
V × I
2
0 ω 2ω
02875-0-033
Figure 33. Effect of Channel Offsets on the Real Power Calculation The contents of the offset correction registers are 6-bit, sign and
magnitude coded. The weight of the LSB depends on the gain setting, i.e., 1, 2, 4, 8, or 16. Table 6 shows the correctable offset
span for each of the gain settings and the LSB weight (mV) for
the offset correction registers. The maximum value that can be written to the offset correction registers is ±31d—see Figure 34. Figure 34 shows the relationship between the offset correction register contents and the offset (mV) on the analog inputs for a
gain setting of 1. In order to perform an offset adjustment, the analog inputs should be first connected to AGND, and there
should be no signal on either Channel 1 or Channel 2. A read from Channel 1 or Channel 2 using the waveform register indicates the offset in the channel. This offset can be canceled by writing an equal and opposite offset value to the Channel 1
offset register, or an equal value to the Channel 2 offset register.
The offset correction can be confirmed by performing another read. Note when adjusting the offset of Channel 1, one should disable the digital integrator and the HPF. Table 6. Offset Correction Range—Channels 1 and 2 Gain Correctable Span LSB Size 1 ±50 mV 1.61 mV/LSB
2 ±37 mV 1.19 mV/LSB
4 ±30 mV 0.97 mV/LSB
8 ±26 mV 0.84 mV/LSB
16 ±24 mV 0.77 mV/LSB
CH1OS[5:0]
SIGN + 5 BITS
+50mV
OFFSET
ADJUST
0x3F
0x00
0x1F
–50mV 0mV
SIGN + 5 BITS
01,1111b
11,1111b
02875-0-034
Figure 34. Channel 1 Offset Correction Range (Gain = 1) The current and voltage rms offsets can be adjusted with the
IRMSOS and VRMSOS registers—see Channel 1 RMS Offset Compensation and Channel 2 RMS Offset Compensation
sections. di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR
A di/dt sensor detects changes in magnetic field caused by ac
current. Figure 35 shows the principle of a di/dt current sensor.
MAGNETIC FIELD CREATED BY CURRENT
(DIRECTLY PROPORTIONAL TO CURRENT)
+ EMF (ELECTROMOTIVE FORCE)
– INDUCED BY CHANGES IN
MAGNETIC FLUX DENSITY (di/dt)
02875-0-035
Figure 35. Principle of a di/dt Current Sensor The flux density of a magnetic field induced by a current is
directly proportional to the magnitude of the current. The
changes in the magnetic flux density passing through a
conductor loop generate an electromotive force (EMF) between the two ends of the loop. The EMF is a voltage signal, which is
proportional to the di/dt of the current. The voltage output
from the di/dt current sensor is determined by the mutual inductance between the current-carrying conductor and the di/dt sensor. The current signal needs to be recovered from the
di/dt signal before it can be used. An integrator is therefore
necessary to restore the signal to its original form. The ADE7753
has a built-in digital integrator to recover the current signal from the di/dt sensor. The digital integrator on Channel 1 is switched off by default when the ADE7753 is powered up.
Setting the MSB of CH1OS register turns on the integrator.
Figure 36 to Figure 39 show the magnitude and phase response of the digital integrator.
FREQUENCY (Hz)
10
GAIN (dB)
0
–10
–20
–30
–40
–50
102 103
02875-0-036
Figure 36. Combined Gain Response of the Digital Integrator and Phase Compensator
ADE7753
Rev. C | Page 18 of 60
FREQUENCY (Hz)10210302875-0-037FREQ–88.0PHASE (
Degrees)–88.5–89.0–89.5–90.0–90.5
Figure 37. Combined Phase Response of the Digital Integrator and Phase Compensator
FREQUENCY (Hz)–1.0–6.0407045GAIN (
dB)50556065–1.5–2.0–2.5–3.5–4.5–5.5–3.0–4.0–5.002875-0-038
Figure 38. Combined Gain Response of the Digital Integrator and Phase Compensator (40 Hz to 70 Hz)
–89.75–89.80–89.85–89.90–89.95–90.00FREQUENCY (Hz)PHASE (Degrees)40457050556065–90.05–89.7002875-0-039
Figure 39. Combined Phase Response of the Digital Integrator and Phase Compensator (40 Hz to 70 Hz)
Note that the integrator has a –20 dB/dec attenuation and an approximately –90° phase shift. When combined with a di/dt sensor, the resulting magnitude and phase response should be a flat gain over the frequency band of interest. The di/dt sensor has a 20 dB/dec gain associated with it. It also generates signifi-cant high frequency noise, therefore a more effective anti-aliasing filter is needed to avoid noise due to aliasing—see the Antialias Filter section.
When the digital integrator is switched off, the ADE7753 can be used directly with a conventional current sensor such as a current transformer (CT) or with a low resistance current shunt.
ZERO-CROSSING DETECTION
The ADE7753 has a zero-crossing detection circuit on Channel 2. This zero crossing is used to produce an external zero-crossing signal (ZX), and it is also used in the calibration mode—see the Calibrating an Energy Meter Based on the ADE7753 section. The zero-crossing signal is also used to initiate a temperature measurement on the ADE7753—see the Temperature Measurement section.
Figure 40 shows how the zero-crossing signal is generated from the output of LPF1. ×1,×2,×1,×8,×16ADC 2REFERENCE1LPF1f–3dB = 140Hz–63%TO+63%FSPGA2{GAIN [7:5]}V2PV2NV2ZEROCROSSZXTOMULTIPLIER2.32° @ 60Hz1.00.93ZXV2LPF102875-0-040
Figure 40. Zero-Crossing Detection on Channel 2
The ZX signal goes logic high on a positive-going zero crossing and logic low on a negative-going zero crossing on Channel 2. The zero-crossing signal ZX is generated from the output of LPF1. LPF1 has a single pole at 140 Hz (at CLKIN = 3.579545 MHz). As a result, there is a phase lag between the analog input signal V2 and the output of LPF1. The phase response of this filter is shown in the Channel 2 Sampling section. The phase lag response of LPF1 results in a time delay of approximately 1.14 ms (@ 60 Hz) between the zero crossing on the analog inputs of Channel 2 and the rising or falling edge of ZX.
The zero-crossing detection also drives the ZX flag in the interrupt status register. The ZX flag is set to Logic 0 on the rising and falling edge of the voltage waveform. It stays low until the status register is read with reset. An active low in the IRQ output also appears if the corresponding bit in the interrupt enable register is set to Logic 1.
ADE7753
Rev. C | Page 19 of 60
The flag in the interrupt status register as well as the IRQ output are reset to their default values when the interrupt status register with reset (RSTSTATUS) is read.
Zero-Crossing Timeout
The zero-crossing detection also has an associated timeout register, ZXTOUT. This unsigned, 12-bit register is decremented (1 LSB) every 128/CLKIN seconds. The register is reset to its user programmed full-scale value every time a zero crossing is detected on Channel 2. The default power on value in this register is 0xFFF. If the internal register decrements to 0 before a zero crossing is detected and the DISSAG bit in the mode register is Logic 0, the SAG pin goes active low. The absence of a zero crossing is also indicated on the IRQ pin if the ZXTO enable bit in the interrupt enable register is set to Logic 1. Irrespective of the enable bit setting, the ZXTO flag in the interrupt status register is always set when the internal ZXTOUT register is decremented to 0—see the section. ADE7753 Interrupts
The ZXOUT register can be written/read by the user and has an address of 1Dh—see the ADE7753 Serial Interface section. The resolution of the register is 128/CLKIN seconds per LSB. Thus the maximum delay for an interrupt is 0.15 second (128/CLKIN × 212).
Figure 41 shows the mechanism of the zero-crossing timeout detection when the line voltage stays at a fixed dc level for more than CLKIN/128 × ZXTOUT seconds. 12-BIT INTERNALREGISTER VALUEZXTOUTCHANNEL 2ZXTODETECTIONBIT02875-0-041
Figure 41. Zero-Crossing Timeout Detection
PERIOD MEASUREMENT
The ADE7753 also provides the period measurement of the line. The period register is an unsigned 16-bit register and is updated every period. The MSB of this register is always zero.
The resolution of this register is 2.2 μs/LSB when CLKIN = 3.579545 MHz, which represents 0.013% when the line fre-quency is 60 Hz. When the line frequency is 60 Hz, the value of the period register is approximately CLKIN/4/32/60 Hz × 16 = 7457d. The length of the register enables the measurement of line frequencies as low as 13.9 Hz.
The period register is stable at ±1 LSB when the line is established and the measurement does not change. A settling time of 1.8 seconds is associated with this filter before the measurement is stable.
POWER SUPPLY MONITOR
The ADE7753 also contains an on-chip power supply monitor. The analog supply (AVDD) is continuously monitored by the ADE7753. If the supply is less than 4 V ± 5%, then the ADE7753 goes into an inactive state, that is, no energy is accumulated when the supply voltage is below 4 V. This is useful to ensure correct device operation at power-up and during power-down. The power supply monitor has built-in hysteresis and filtering, which give a high degree of immunity to false triggering due to noisy supplies. AVDD5V4V0VADE7753POWER-ONINACTIVESTATESAGINACTIVEACTIVEINACTIVETIME02875-0-042
Figure 42. On-Chip Power Supply Monitor
As seen in Figure 42, the trigger level is nominally set at 4 V. The tolerance on this trigger level is about ±5%. The SAG pin can also be used as a power supply monitor input to the MCU. The SAG pin goes logic low when the ADE7753 is in its inactive state. The power supply and decoupling for the part should be such that the ripple at AVDD does not exceed 5 V ±5%, as specified for normal operation.
LINE VOLTAGE SAG DETECTION
In addition to the detection of the loss of the line voltage signal (zero crossing), the ADE7753 can also be programmed to detect when the absolute value of the line voltage drops below a certain peak value for a number of line cycles. This condition is illustrated in Figure 43.
ADE7753
Rev. C | Page 20 of 60
SAGCYC [7:0] =0x043 LINE CYCLESSAG RESET HIGHWHEN CHANNEL 2EXCEEDS SAGLVL [7:0]FULL SCALESAGLVL [7:0]SAGCHANNEL 202875-0-043
Figure 43. ADE7753 Sag Detection
Figure 43 shows the line voltage falling below a threshold that is set in the sag level register (SAGLVL[7:0]) for three line cycles. The quantities 0 and 1 are not valid for the SAGCYC register, and the contents represent one more than the desired number of full line cycles. For example, when the sag cycle (SAGCYC[7:0]) contains 0x04, the SAG pin goes active low at the end of the third line cycle for which the line voltage (Channel 2 signal) falls below the threshold, if the DISSAG bit in the mode register is Logic 0. As is the case when zero crossings are no longer detected, the sag event is also recorded by setting the SAG flag in the interrupt status register. If the SAG enable bit is set to Logic 1, the IRQ logic output goes active low—see the section. The ADE7753 InterruptsSAG pin goes logic high again when the absolute value of the signal on Channel 2 exceeds the sag level set in the sag level register. This is shown in when the Figure 43SAG pin goes high again during the fifth line cycle from the time when the signal on Channel 2 first dropped below the threshold level.
Sag Level Set
The contents of the sag level register (1 byte) are compared to the absolute value of the most significant byte output from LPF1 after it is shifted left by one bit, thus, for example, the nominal maximum code from LPF1 with a full-scale signal on Channel 2 is 0x2518—see the Channel 2 Sampling section. Shifting one bit left gives 0x4A30. Therefore writing 0x4A to the SAG level register puts the sag detection level at full scale. Writing 0x00 or 0x01 puts the sag detection level at 0. The SAG level register is compared to the most significant byte of a waveform sample after the shift left and detection is made when the contents of the sag level register are greater.
PEAK DETECTION
The ADE7753 can also be programmed to detect when the absolute value of the voltage or current channel exceeds a specified peak value. Figure 44 illustrates the behavior of the peak detection for the voltage channel. Both Channel 1 and Channel 2 are monitored at the same time.
PKV RESET LOWWHEN RSTSTATUSREGISTER IS READVPKLVL[7:0]V2READ RSTSTATUSREGISTERPKV INTERRUPTFLAG (BIT 8 OFSTATUS REGISTER)02875-0-088
Figure 44. ADE7753 Peak Level Detection
Figure 44 shows a line voltage exceeding a threshold that is set in the voltage peak register (VPKLVL[7:0]). The voltage peak event is recorded by setting the PKV flag in the interrupt status register. If the PKV enable bit is set to Logic 1 in the interrupt mask register, the IRQ logic output goes active low. Similarly, the current peak event is recorded by setting the PKI flag in the interrupt status register—see the section. ADE7753 Interrupts
Peak Level Set
The contents of the VPKLVL and IPKLVL registers are respectively compared to the absolute value of Channel 1 and Channel 2 after they are multiplied by 2. Thus, for example, the nominal maximum code from the Channel 1 ADC with a full-scale signal is 0x2851EC—see the Channel 1 Sampling section. Multiplying by 2 gives 0x50A3D8. Therefore, writing 0x50 to the IPKLVL register, for example, puts the Channel 1 peak detection level at full scale and sets the current peak detection to its least sensitive value. Writing 0x00 puts the Channel 1 detection level at 0. The detection is done by comparing the contents of the IPKLVL register to the incoming Channel 1 sample. The IRQ pin indicates that the peak level is exceeded if the PKI or PKV bits are set in the interrupt enable register (IRQEN[15:0]) at Address 0x0A.
Peak Level Record
The ADE7753 records the maximum absolute value reached by Channel 1 and Channel 2 in two different registers—IPEAK and VPEAK, respectively. VPEAK and IPEAK are 24-bit unsigned registers. These registers are updated each time the absolute value of the waveform sample from the corresponding channel is above the value stored in the VPEAK or IPEAK register. The contents of the VPEAK register correspond to 2× the maximum absolute value observed on the Channel 2 input. The contents of IPEAK represent the maximum absolute value observed on the Channel 1 input. Reading the RSTVPEAK and RSTIPEAK registers clears their respective contents after the read operation.
ADE7753
Rev. C | Page 21 of 60
Using the ADE7753 Interrupts with an MCU
ADE7753 INTERRUPTS
Figure 46 shows a timing diagram with a suggested implemen-tation of ADE7753 interrupt management using an MCU. At time t1, the IRQ line goes active low indicating that one or more interrupt events have occurred in the ADE7753. The IRQ logic output should be tied to a negative edge-triggered external interrupt on the MCU. On detection of the negative edge, the MCU should be configured to start executing its interrupt service routine (ISR). On entering the ISR, all interrupts should be disabled by using the global interrupt enable bit. At this point, the MCU external interrupt flag can be cleared to capture interrupt events that occur during the current ISR. When the MCU interrupt flag is cleared, a read from the status register with reset is carried out. This causes the IRQ line to be reset logic high (t2)—see the section. The status register contents are used to determine the source of the interrupt(s) and therefore the appropriate action to be taken. If a subsequent interrupt event occurs during the ISR, that event is recorded by the MCU external interrupt flag being set again (t3). On returning from the ISR, the global interrupt mask is cleared (same instruction cycle), and the external interrupt flag causes the MCU to jump to its ISR once a gain. This ensures that the MCU does not miss any external interrupts. Interrupt Timing
ADE7753 interrupts are managed through the interrupt status register (STATUS[15:0]) and the interrupt enable register (IRQEN[15:0]). When an interrupt event occurs in the ADE7753, the corresponding flag in the status register is set to Logic 1—see the Interrupt Status Register section. If the enable bit for this interrupt in the interrupt enable register is Logic 1, then the IRQ logic output goes active low. The flag bits in the status register are set irrespective of the state of the enable bits.
To determine the source of the interrupt, the system master (MCU) should perform a read from the status register with reset (RSTSTATUS[15:0]). This is achieved by carrying out a read from Address 0x0C. The IRQ output goes logic high on completion of the interrupt status register read command—see the section. When carrying out a read with reset, the ADE7753 is designed to ensure that no interrupt events are missed. If an interrupt event occurs just as the status register is being read, the event is not lost and the Interrupt TimingIRQ logic output is guaranteed to go high for the duration of the interrupt status register data transfer before going logic low again to indicate the pending interrupt. See the next section for a more detailed description. IRQGLOBALINTERRUPTMASK SETISR RETURNGLOBAL INTERRUPTMASK RESETCLEAR MCUINTERRUPTFLAGREADSTATUS WITHRESET (0x05)ISR ACTION(BASED ON STATUS CONTENTS)MCUINTERRUPTFLAG SETMCUPROGRAMSEQUENCE02875-0-044t1t2t3JUMPTOISRJUMPTOISR
Figure 45. ADE7753 Interrupt Management
SCLKDINDOUTIRQt11t11t9t1READ STATUS REGISTER COMMANDSTATUS REGISTER CONTENTSDB7DB7DB0CS00000101DB002875-0-045
Figure 46. ADE7753 Interrupt Timing
ADE7753
Rev. C | Page 22 of 60
Interrupt Timing
The ADE7753 Serial Interface section should be reviewed first before reviewing the interrupt timing. As previously described, when the IRQ output goes low, the MCU ISR must read the interrupt status register to determine the source of the interrupt. When reading the status register contents, the IRQ output is set high on the last falling edge of SCLK of the first byte transfer (read interrupt status register command). The IRQ output is held high until the last bit of the next 15-bit transfer is shifted out (interrupt status register contents)—see . If an interrupt is pending at this time, the Figure 45IRQ output goes low again. If no interrupt is pending, the IRQ output stays high.
TEMPERATURE MEASUREMENT
The ADE7753 also includes an on-chip temperature sensor. A temperature measurement can be made by setting Bit 5 in the mode register. When Bit 5 is set logic high in the mode register, the ADE7753 initiates a temperature measurement on the next zero crossing. When the zero crossing on Channel 2 is detected, the voltage output from the temperature sensing circuit is connected to ADC1 (Channel 1) for digitizing. The resulting code is processed and placed in the temperature register (TEMP[7:0]) approximately 26 μs later (96/CLKIN seconds). If enabled in the interrupt enable register (Bit 5), the IRQ output goes active low when the temperature conversion is finished.
The contents of the temperature register are signed (twos complement) with a resolution of approximately 1.5 LSB/°C. The temperature register produces a code of 0x00 when the ambient temperature is approximately −25°C. The temperature measurement is uncalibrated in the ADE7753 and has an offset tolerance as high as ±25°C.
ADE7753 ANALOG-TO-DIGITAL CONVERSION
The analog-to-digital conversion in the ADE7753 is carried out using two second-order Σ-Δ ADCs. For simplicity, the block diagram in Figure 47 shows a first-order Σ-Δ ADC. The converter is made up of the Σ-Δ modulator and the digital low-pass filter. 24DIGITALLOW-PASSFILTERRCANALOGLOW-PASS FILTER+–VREF1-BIT DACINTEGRATORMCLK/4LATCHEDCOMPARATOR.....10100101.....+–02875-0-046
Figure 47. First-Order Σ-Δ ADC
A Σ-Δ modulator converts the input signal into a continuous serial stream of 1s and 0s at a rate determined by the sampling clock. In the ADE7753, the sampling clock is equal to CLKIN/4. The 1-bit DAC in the feedback loop is driven by the serial data stream. The DAC output is subtracted from the input signal. If the loop gain is high enough, the average value of the DAC out-put (and therefore the bit stream) can approach that of the input signal level. For any given input value in a single sampling interval, the data from the 1-bit ADC is virtually meaningless. Only when a large number of samples are averaged is a meaningful result obtained. This averaging is carried out in the second part of the ADC, the digital low-pass filter. By averaging a large number of bits from the modulator, the low-pass filter can produce 24-bit data-words that are proportional to the input signal level.
The Σ-Δ converter uses two techniques to achieve high resolution from what is essentially a 1-bit conversion technique. The first is oversampling. Oversampling means that the signal is sampled at a rate (frequency), which is many times higher than the bandwidth of interest. For example, the sampling rate in the ADE7753 is CLKIN/4 (894 kHz) and the band of interest is 40 Hz to 2 kHz. Oversampling has the effect of spreading the quantization noise (noise due to sampling) over a wider bandwidth. With the noise spread more thinly over a wider bandwidth, the quantization noise in the band of interest is lowered—see Figure 48. However, oversampling alone is not efficient enough to improve the signal-to-noise ratio (SNR) in the band of interest. For example, an oversampling ratio of 4 is required just to increase the SNR by only 6 dB (1 bit). To keep the oversampling ratio at a reasonable level, it is possible to shape the quantization noise so that the majority of the noise lies at the higher frequencies. In the Σ-Δ modulator, the noise is shaped by the integrator, which has a high-pass-type response for the quantization noise. The result is that most of the noise is at the higher frequencies where it can be removed by the digital low-pass filter. This noise shaping is shown in Figure 48. 44708942NOISESIGNALDIGITALFILTERANTILALIASFILTER (RC)SAMPLINGFREQUENCYHIGH RESOLUTIONOUTPUT FROM DIGITALLPFSHAPEDNOISE44708942NOISESIGNALFREQUENCY (kHz)FREQUENCY (kHz)02875-0-047
Figure 48. Noise Reduction Due to Oversampling and Noise Shaping in the Analog Modulator
ADE7753
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Antialias Filter
ADE7753 Reference Circuit
Figure 50 shows a simplified version of the reference output circuitry. The nominal reference voltage at the REFIN/OUT pin is 2.42 V. This is the reference voltage used for the ADCs in the ADE7753. However, Channel 1 has three input range selections that are selected by dividing down the reference value used for the ADC in Channel 1. The reference value used for Channel 1 is divided down to ½ and ¼ of the nominal value by using an internal resistor divider, as shown in Figure 50.
Figure 47 also shows an analog low-pass filter (RC) on the input to the modulator. This filter is present to prevent aliasing. Aliasing is an artifact of all sampled systems. Aliasing means that frequency components in the input signal to the ADC, which are higher than half the sampling rate of the ADC, appear in the sampled signal at a frequency below half the sampling rate. Figure 49 illustrates the effect. Frequency components (arrows shown in black) above half the sampling frequency (also know as the Nyquist frequency, i.e., 447 kHz) are imaged or folded back down below 447 kHz. This happens with all ADCs regardless of the architecture. In the example shown, only frequencies near the sampling frequency, i.e., 894 kHz, move into the band of interest for metering, i.e., 40 Hz to 2 kHz. This allows the use of a very simple LPF (low-pass filter) to attenuate high frequency (near 900 kHz) noise, and prevents distortion in the band of interest. For conventional current sensors, a simple RC filter (single-pole LPF) with a corner frequency of 10 kHz produces an attenuation of approximately 40 dB at 894 kHz—see Figure 49. The 20 dB per decade attenuation is usually sufficient to eliminate the effects of aliasing for conventional current sensors. However, for a di/dt sensor such as a Rogowski coil, the sensor has a 20 dB per decade gain. This neutralizes the –20 dB per decade attenuation produced by one simple LPF. Therefore, when using a di/dt sensor, care should be taken to offset the 20 dB per decade gain. One simple approach is to cascade two RC filters to produce the –40 dB per decade attenuation needed. 60μAPTAT2.5V1.7kΩ12.5kΩ12.5kΩ12.5kΩ12.5kΩREFIN/OUT2.42VMAXIMUMLOAD = 10μAOUTPUTIMPEDANCE6kΩREFERENCE INPUTTO ADC CHANNEL 1(RANGE SELECT)2.42V, 1.21V, 0.6V02875-0-049
Figure 50. ADE7753 Reference Circuit Output
The REFIN/OUT pin can be overdriven by an external source, for example, an external 2.5 V reference. Note that the nominal reference value supplied to the ADCs is now 2.5 V, not 2.42 V, which has the effect of increasing the nominal analog input signal range by 2.5/2.42 × 100% = 3% or from 0.5 V to 0.5165 V. SAMPLINGFREQUENCYIMAGEFREQUENCIESALIASING EFFECTS02447894FREQUENCY (kHz)02875-0-048
The voltage of the ADE7753 reference drifts slightly with temperature—see the ADE7753 Specifications for the temperature coefficient specification (in ppm/°C). The value of the temperature drift varies from part to part. Since the reference is used for the ADCs in both Channels 1 and 2, any x% drift in the reference results in 2×% deviation of the meter accuracy. The reference drift resulting from temperature changes is usually very small and it is typically much smaller than the drift of other components on a meter. However, if guaranteed temperature performance is needed, one needs to use an external voltage reference. Alternatively, the meter can be calibrated at multiple temperatures. Real-time compensation can be achieved easily by using the on-chip temperature sensor.
Figure 49. ADC and Signal Processing in Channel 1 Outline Dimensions
ADC Transfer Function
The following expression relates the output of the LPF in the Σ-Δ ADC to the analog input signal level. Both ADCs in the ADE7753 are designed to produce the same output code for the same input signal level.
CHANNEL 1 ADC 144,2620492.3)(××=OUTINVVADCCode (1)
Figure 51 shows the ADC and signal processing chain for Channel 1. In waveform sampling mode, the ADC outputs a signed twos complement 24-bit data-word at a maximum of 27.9 kSPS (CLKIN/128). With the specified full-scale analog input signal of 0.5 V (or 0.25 V or 0.125 V—see the Analog Inputs section) the ADC produces an output code that is approximately between 0x2851EC (+2,642,412d) and 0xD7AE14 (–2,642,412d)—see Figure 51.
Therefore with a full-scale signal on the input of 0.5 V and an internal reference of 2.42 V, the ADC output code is nominally 165,151 or 2851Fh. The maximum code from the ADC is ±262,144; this is equivalent to an input signal level of ±0.794 V. However, for specified performance, it is recommended that the full-scale input signal level of 0.5 V not be exceeded.
ADE7753
Rev. C | Page 24 of 60
⋅1,⋅2,⋅4,⋅8,⋅16ANALOGINPUTRANGEDIGITALINTEGRATOR*dtHPFADC 1REFERENCE2.42V, 1.21V, 0.6VV10V0.5V, 0.25V,0.125V, 62.5mV,31.3mV, 15.6mV,CHANNEL 1(CURRENT WAVEFORM)DATA RANGEACTIVE AND REACTIVEPOWER CALCULATIONWAVEFORM SAMPLEREGISTERCURRENT RMS (IRMS)CALCULATION50HzV1PV1NPGA1V1{GAIN[4:3]}{GAIN[2:0]}*WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATEDDEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE INTEGRATOR HAS A –20dB/DECADEFREQUENCY RESPONSE. WHEN DISABLED, THE OUTPUT WILL NOT BE FURTHER ATTENUATED.ADC OUTPUTWORD RANGE0xD7AE140x000000x2851EC0xD7AE140x0000000x2851ECCHANNEL 1(CURRENT WAVEFORM)DATA RANGE AFTERINTEGRATOR (50Hz)0xEI08C40x0000000x1EF73C60HzCHANNEL 1(CURRENT WAVEFORM)DATA RANGE AFTERINTEGRATOR (60Hz)0xE631F80x0000000x19CE0802875-0-052
Figure 51. ADC and Signal Processing in Channel 1
Channel 1 Sampling
The waveform samples can also be routed to the waveform register (MODE[14:13] = 1,0) to be read by the system master (MCU). In waveform sampling mode, the WSMP bit (Bit 3) in the interrupt enable register must also be set to Logic 1. The active, apparent power, and energy calculation remain uninterrupted during waveform sampling.
When in waveform sampling mode, one of four output sample rates can be chosen by using Bits 11 and 12 of the mode register (WAVSEL1,0). The output sample rate can be 27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS—see the Mode Register (0x09) section. The interrupt request output, IRQ, signals a new sample availability by going active low. The timing is shown in . The 24-bit waveform samples are transferred from the ADE7753 one byte (eight bits) at a time, with the most significant byte shifted out first. The 24-bit data-word is right justified—see the section. The interrupt request output Figure 52ADE7753 Serial InterfaceIRQ stays low until the interrupt routine reads the reset status register—see the section. ADE7753 Interrupts
CHANNEL 1 DATA(24 BITS)READ FROM WAVEFORMSIGN0IRQSCLKDINDOUT0001 HEX02875-0-050
Figure 52. Waveform Sampling Channel 1
Channel 1 RMS Calculation
Root mean square (rms) value of a continuous signal V(t) is defined as
VRMS = ∫×=TrmsdttVTV02)(1 (2)
For time sampling signals, rms calculation involves squaring the signal, taking the average and obtaining the square root:
VRMS = Σ=×=NirmsiVNV12)(1 (3)
The ADE7753 simultaneously calculates the rms values for Channel 1 and Channel 2 in different registers. Figure 53 shows the detail of the signal processing chain for the rms calculation on Channel 1. The Channel 1 rms value is processed from the samples used in the Channel 1 waveform sampling mode. The Channel 1 rms value is stored in an unsigned 24-bit register (IRMS). One LSB of the Channel 1 rms register is equivalent to one LSB of a Channel 1 waveform sample. The update rate of the Channel 1 rms measurement is CLKIN/4.
ADE7753
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IRMS(t)LPF3HPF1CHANNEL 10x1C82B30x00+IRMSOS[11:0]IRMSCURRENT SIGNAL (i(t))226225sgn22721721621502875-0-00510x2851EC0x000xD7AE142424
Figure 53. Channel 1 RMS Signal Processing
With the specified full-scale analog input signal of 0.5 V, the ADC produces an output code that is approximately ±2,642,412d—see the Channel 1 ADC section. The equivalent rms value of a full-scale ac signal are 1,868,467d (0x1C82B3). The current rms measurement provided in the ADE7753 is accurate to within 0.5% for signal input between full scale and full scale/100. Table 7 shows the settling time for the IRMS measurement, which is the time it takes for the rms register to reflect the value at the input to the current channel. The conversion from the register value to amps must be done externally in the microprocessor using an amps/LSB constant. To minimize noise, synchronize the reading of the rms register with the zero crossing of the voltage input and take the average of a number of readings.
Table 7.
95%
100%
Integrator Off
219 ms
895 ms
Integrator On
78.5 ms
1340 ms
Channel 1 RMS Offset Compensation
The ADE7753 incorporates a Channel 1 rms offset compensa-tion register (IRMSOS). This is a 12-bit signed register that can be used to remove offset in the Channel 1 rms calculation. An offset could exist in the rms calculation due to input noises that are integrated in the dc component of V2(t). The offset calibration allows the content of the IRMS register to match the theoretical value even when the Channel 1 input is low.
One LSB of the Channel 1 rms offset is equivalent to 32,768 LSB of the square of the Channel 1 rms register. Assuming that the maximum value from the Channel 1 rms calculation is 1,868,467d with full-scale ac inputs, then 1 LSB of the Channel 1 rms offset represents 0.46% of measurement error at –60 dB down of full scale.
IRMS = 3276820×+IRMSOSIRMS (4)
where IRMS0 is the rms measurement without offset correction. To measure the offset of the rms measurement, two data points are needed from non-zero input values, for example, the base current, Ib, and Imax/100. The offset can be calculated from these measurements.
CHANNEL 2 ADC
Channel 2 Sampling
In Channel 2 waveform sampling mode (MODE[14:13] = 1,1 and WSMP = 1), the ADC output code scaling for Channel 2 is not the same as Channel 1. The Channel 2 waveform sample is a 16-bit word and sign extended to 24 bits. For normal operation, the differential voltage signal between V2P and V2N should not exceed 0.5 V. With maximum voltage input (±0.5 V at PGA gain of 1), the output from the ADC swings between 0x2852 and 0xD7AE (±10,322d). However, before being passed to the wave-form register, the ADC output is passed through a single-pole, low-pass filter with a cutoff frequency of 140 Hz. The plots in Figure 54 show the magnitude and phase response of this filter. FREQUENCY (Hz)0101102103PHASE (
Degrees)–20–10–40–50–60–30–70–80–900–18GAIN (
dB)60Hz,–0.73dB50Hz,–0.52dB60Hz,–23.2°50Hz,–19.7°–8–10–14–12–16–2–4–602875-0-053
Figure 54. Magnitude and Phase Response of LPF1
The LPF1 has the effect of attenuating the signal. For example, if the line frequency is 60 Hz, then the signal at the output of LPF1 is attenuated by about 8%. dBHzHzfH73.0919.01406011)(2−==⎟⎟⎠⎞⎜⎜⎝⎛+= (5)
Note LPF1 does not affect the active power calculation. The signal processing chain in Channel 2 is illustrated in Figure 55.
ADE7753
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V1ADC 20VANALOGINPUT RANGE0.5V, 0.25, 0.125,62.5mV, 31.25mVREFERENCELPF1ACTIVEANDREACTIVEENERGYCALCULATIONVRMSCALCULATIONANDWAVEFORMSAMPLING(PEAK/SAG/ZX)PGA2×1,×2,×4,×8,×16{GAIN [7:5]}V2PV2NV22.42V0x28520x25810xDAE80xD7AE0x0000LPF OUTPUTWORD RANGE02875-0-054
Figure 55. ADC and Signal Processing in Channel 2
VRMS[23:0]LPF3|x|LPF1CHANNEL 20x17D3380x00++VRMOS[11:0]VOLTAGE SIGNAL (V(t))29sgn2822212002875-0-00550x25180x00xDAE8
Figure 56. Channel 2 RMS Signal Processing
Channel 2 has only one analog input range (0.5 V differential). Like Channel 1, Channel 2 has a PGA with gain selections of 1, 2, 4, 8, and 16. For energy measurement, the output of the ADC is passed directly to the multiplier and is not filtered. An HPF is not required to remove any dc offset since it is only required to remove the offset from one channel to eliminate errors due to offsets in the power calculation. When in waveform sampling mode, one of four output sample rates can be chosen by using Bits 11 and 12 of the mode register. The available output sample rates are 27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS—see the Mode Register (0x09) section. The interrupt request output IRQ signals that a sample is available by going active low. The timing is the same as that for Channel 1, as shown in . Figure 52
Channel 2 RMS Calculation
Figure 56 shows the details of the signal processing chain for the rms estimation on Channel 2. This Channel 2 rms estimation is done in the ADE7753 using the mean absolute value calculation, as shown in Figure 56. The Channel 2 rms value is processed from the samples used in the Channel 2 waveform sampling mode. The rms value is slightly attenuated because of LPF1. Channel 2 rms value is stored in the unsigned 24-bit VRMS register. The update rate of the Channel 2 rms measurement is CLKIN/4.
With the specified full-scale ac analog input signal of 0.5 V, the output from the LPF1 swings between 0x2518 and 0xDAE8 at 60 Hz—see the Channel 2 ADC section. The equivalent rms value of this full-scale ac signal is approximately 1,561,400 (0x17D338) in the VRMS register. The voltage rms measure-ment provided in the ADE7753 is accurate to within ±0.5% for signal input between full scale and full scale/20. Table 8 shows the settling time for the VRMS measurement, which is the time it takes for the rms register to reflect the value at the input to the voltage channel. The conversion from the register value to volts must be done externally in the microprocessor using a volts/LSB constant. Since the low-pass filtering used for calculating the rms value is imperfect, there is some ripple noise from 2ω term present in the rms measurement. To minimize the noise effect in the reading, synchronize the rms reading with the zero crossings of the voltage input.
Table 8.
95%
100%
220 ms
670 ms
Channel 2 RMS Offset Compensation
The ADE7753 incorporates a Channel 2 rms offset compensation register (VRMSOS). This is a 12-bit signed register that can be used to remove offset in the Channel 2 rms calculation. An offset could exist in the rms calculation due to input noises and dc offset in the input samples. The offset calibration allows the contents of the VRMS register to be maintained at 0 when no voltage is applied. One LSB of the Channel 2 rms offset is equivalent to one LSB of the rms register. Assuming that the maximum value from the Channel 2 rms calculation is 1,561,400d with full-scale ac inputs, then one LSB of the Channel 2 rms offset represents 0.064% of measurement error at –60 dB down of full scale.
VRMS = VRMS0 + VRMSOS (6)
where VRMS0 is the rms measurement without offset correction. The voltage rms offset compensation should be done by testing the rms results at two non-zero input levels. One measurement can be done close to full scale and the other at approximately full scale/10. The voltage offset compensation can be derived
ADE7753
Rev. C | Page 27 of 60
from these measurements. If the voltage rms offset register does not have enough range, the CH2OS register can also be used.
PHASE COMPENSATION
When the HPF is disabled, the phase error between Channel 1 and Channel 2 is 0 from dc to 3.5 kHz. When HPF is enabled, Channel 1 has the phase response illustrated in Figure 58 and Figure 59. Also shown in Figure 60 is the magnitude response of the filter. As can be seen from the plots, the phase response is almost 0 from 45 Hz to 1 kHz. This is all that is required in typical energy measurement applications. However, despite being internally phase compensated, the ADE7753 must work with transducers, which could have inherent phase errors. For example, a phase error of 0.1° to 0.3° is not uncommon for a current transformer (CT). These phase errors can vary from part to part, and they must be corrected in order to perform accurate power calculations. The errors associated with phase mismatch are particularly noticeable at low power factors. The ADE7753 provides a means of digitally calibrating these small phase errors. The ADE7753 allows a small time delay or time advance to be introduced into the signal processing chain to compensate for small phase errors. Because the compensation is in time, this technique should be used only for small phase errors in the range of 0.1° to 0.5°. Correcting large phase errors using a time shift technique can introduce significant phase errors at higher harmonics.
The phase calibration register (PHCAL[5:0]) is a twos comple-ment signed single-byte register that has values ranging from 0x21 (–31d) to 0x1F (31d).
The register is centered at 0x0D, so that writing 0x0D to the register gives 0 delay. By changing the PHCAL register, the time delay in the Channel 2 signal path can change from –102.12 μs to +39.96 μs (CLKIN = 3.579545 MHz). One LSB is equivalent to 2.22 μs (CLKIN/8) time delay or advance. A line frequency of 60 Hz gives a phase resolution of 0.048° at the fundamental (i.e., 360° × 2.22 μs × 60 Hz). Figure 57 illustrates how the phase compensation is used to remove a 0.1° phase lead in Channel 1 due to the external transducer. To cancel the lead (0.1°) in Channel 1, a phase lead must also be introduced into Channel 2. The resolution of the phase adjustment allows the introduction of a phase lead in increment of 0.048°. The phase lead is achieved by introducing a time advance into Channel 2. A time advance of 4.48 μs is made by writing −2 (0x0B) to the time delay block, thus reducing the amount of time delay by 4.48 μs, or equiva-lently, a phase lead of approximately 0.1° at line frequency of 60 Hz. 0x0B represents –2 because the register is centered with 0 at 0x0D. 110100150PGA1V1PV1NV1ADC 1HPF24PGA2V2PV2NV2ADC 2DELAY BLOCK2.24μs/LSB24LPF2V2V160Hz0.1°V1V2CHANNEL 2 DELAYREDUCED BY 4.48μs(0.1°LEAD AT 60Hz)0Bh IN PHCAL [5.0]PHCAL [5:0]--100μs TO +34μs60Hz02875-0-056
Figure 57. Phase Calibration
FREQUENCY (Hz)PHASE (Degrees)0.90.80.70.60.50.40.30.20.10–0.110210310402875-0-057
Figure 58. Combined Phase Response of the HPF and Phase Compensation (10 Hz to 1 kHz)
FREQUENCY (Hz)0.2040PHASE (
Degrees)0.180.160.140.120.100.0800.020.040.0645505560657002875-0-058
Figure 59. Combined Phase Response of the HPF and Phase Compensation (40 Hz to 70 Hz)
ADE7753
Rev. C | Page 28 of 60
FREQUENCY (Hz)0.4ERROR (%)545658606264660.30.20.10.0–0.1–0.2–0.3–0.402875-0-059
Figure 60. Combined Gain Response of the HPF and Phase Compensation
ACTIVE POWER CALCULATION
Power is defined as the rate of energy flow from source to load. It is defined as the product of the voltage and current wave-forms. The resulting waveform is called the instantaneous power signal and is equal to the rate of energy flow at every instant of time. The unit of power is the watt or joules/sec. Equation 9 gives an expression for the instantaneous power signal in an ac system.
v(t) = )sin(2tVω× (7)
i(t) = )sin(2tIω× (8)
where: V is the rms voltage. I is the rms current.
)()()(titvtp×=
)2cos()(tVIVItpω−= (9)
The average power over an integral number of line cycles (n) is given by the expression in Equation 10.
P = ∫=nTVIdttpnT0)(1 (10)
where: T is the line cycle period. P is referred to as the active or real power.
Note that the active power is equal to the dc component of the instantaneous power signal p(t) in Equation 8, i.e., VI. This is the relationship used to calculate active power in the ADE7753. The instantaneous power signal p(t) is generated by multiplying the current and voltage signals. The dc component of the instantaneous power signal is then extracted by LPF2 (low-pass filter) to obtain the active power information. This process is illustrated in Figure 61. INSTANTANEOUSPOWER SIGNALp(t) = v×i-v×i×cos(2ωt)ACTIVEREALPOWERSIGNAL=v×i0x19999AVI0xCCCCD0x00000CURRENTi(t) = 2×i×sin(ωt)VOLTAGEv(t) = 2×v×sin(ωt)02875-0-060
Figure 61. Active Power Calculation
Since LPF2 does not have an ideal “brick wall” frequency response—see Figure 62, the active power signal has some ripple due to the instantaneous power signal. This ripple is sinusoidal and has a frequency equal to twice the line frequency. Because the ripple is sinusoidal in nature, it is removed when the active power signal is integrated to calculate energy—see the Energy Calculation section. FREQUENCY (Hz)–241dB–2031030100–12–16–8–4002875-0-061
Figure 62. Frequency Response of LPF2
ADE7753
Rev. C | Page 29 of 60
APOS[15:0]WGAIN[11:0]WDIV[7:0]LPF2CURRENTCHANNELVOLTAGECHANNELOUTPUT LPF2TIME (nT)4CLKINTACTIVEPOWERSIGNAL++AENERGY [23:0]OUTPUTSFROMTHELPF2AREACCUMULATED(INTEGRATED)INTHEINTERNALACTIVEENERGYREGISTERUPPER24BITSAREACCESSIBLETHROUGHAENERGY[23:0]REGISTER230480WAVEFORMREGISTERVALUES02875-0-063%
Figure 63. ADE7753 Active Energy Calculation
Figure 63 shows the signal processing chain for the active power calculation in the ADE7753. As explained, the active power is calculated by low-pass filtering the instantaneous power signal. Note that when reading the waveform samples from the output of LPF2, the gain of the active energy can be adjusted by using the multiplier and watt gain register (WGAIN[11:0]). The gain is adjusted by writing a twos complement 12-bit word to the watt gain register. Equation 11 shows how the gain adjustment is related to the contents of the watt gain register: ⎟⎟⎠⎞⎜⎜⎝⎛⎭⎬⎫⎩⎨⎧+×=1221WGAINPowerActiveWGAINOutput (11)
For example, when 0x7FF is written to the watt gain register, the power output is scaled up by 50%. 0x7FF = 2047d, 2047/212 = 0.5. Similarly, 0x800 = –2048d (signed twos complement) and power output is scaled by –50%. Each LSB scales the power output by 0.0244%. Figure 64 shows the maximum code (in hex) output range for the active power signal (LPF2). Note that the output range changes depending on the contents of the watt gain register. The minimum output range is given when the watt gain register contents are equal to 0x800, and the maximum range is given by writing 0x7FF to the watt gain register. This can be used to calibrate the active power (or energy) calculation in the ADE7753. 0x1333330xCCCCD0x666660xF9999A0xF333330xECCCCD0x00000ACTIVE POWER OUTPUTPOSITIVEPOWERNEGATIVEPOWER0x0000x7FF0x800{WGAIN[11:0]}ACTIVE POWERCALIBRATION RANGE02875-0-062
Figure 64. Active Power Calculation Output Range
ENERGY CALCULATION
As stated earlier, power is defined as the rate of energy flow. This relationship can be expressed mathematically in Equation 12. dtdEP= (12)
where: P is power. E is energy.
Conversely, energy is given as the integral of power.
∫=PdtE (13)
ADE7753
Rev. C | Page 30 of 60
FORWAVEFORM
ACCUMULATIOIN
1
24
24
LPF2
V
I
0x19999
0x19999A
0x000000
INSTANTANEOUS
POWER SIGNAL – p(t)
FORWAVEF0RM
SAMPLING
32
0xCCCCD
CURRENT SIGNAL – i(t)
HPF
VOLTAGESIGNAL– v(t)
MULTIPLIER
+ +
APOS [15:0]
sgn 26 25 2-6 2-7 2-8
02875-0-064
WGAIN[11:0]
Figure 65. Active Power Signal Processing
The ADE7753 achieves the integration of the active power signal by continuously accumulating the active power signal in an internal nonreadable 49-bit energy register. The active energy register
(AENERGY[23:0]) represents the upper 24 bits of this internal
register. This discrete time accumulation or summation is equivalent to integration in continuous time. Equation 14
expresses the relationship. ⎭ ⎬ ⎫
⎩ ⎨ ⎧
= × = ∫ Σ
∞
→0 =1
) ( ) (
t n
T nTpLimdttpE (14)
where: n is the discrete time sample number.
T is the sample period. The discrete time sample period (T) for the accumulation register in the ADE7753 is 1.1μs (4/CLKIN). As well as
calculating the energy, this integration removes any sinusoidal components that might be in the active power signal. Figure 65
shows this discrete time integration or accumulation. The active power signal in the waveform register is continuously added to the internal active energy register. This addition is a signed addition; therefore negative energy is subtracted from the active energy contents. The exception to this is when POAM is
selected in the MODE[15:0] register. In this case, only positive
energy contributes to the active energy accumulation—see the
Positive-Only Accumulation Mode section. The output of the multiplier is divided by WDIV. If the value in the WDIV register is equal to 0, then the internal active energy register is divided by 1. WDIV is an 8-bit unsigned register.
After dividing by WDIV, the active energy is accumulated in a
49-bit internal energy accumulation register. The upper 24 bits
of this register are accessible through a read to the active energy register (AENERGY[23:0]). A read to the RAENERGY register
returns the content of the AENERGY register and the upper 24 bits of the internal register are cleared. As shown in Figure 65, the active power signal is accumulated in an internal 49-bit signed
register. The active power signal can be read from the waveform register by setting MODE[14:13] = 0,0 and setting the WSMP
bit (Bit 3) in the interrupt enable register to 1. Like the Channel 1 and Channel 2 waveform sampling modes, the waveform date is available at sample rates of 27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS—see Figure 52.
Figure 66 shows this energy accumulation for full-scale signals (sinusoidal) on the analog inputs. The three curves displayed
illustrate the minimum period of time it takes the energy register to roll over when the active power gain register contents are
0x7FF, 0x000, and 0x800. The watt gain register is used to carry
out power calibration in the ADE7753. As shown, the fastest
integration time occurs when the watt gain register is set to maximum full scale, i.e., 0x7FF. 0x00,0000
0x7F,FFFF
0x3F,FFFF
0x40,0000
0x80,0000
AENERGY [23:0]
4 6.2 8 12.5
TIME (minutes)
WGAIN = 0x7FF
WGAIN = 0x000
WGAIN = 0x800
02875-0-065
Figure 66. Energy Register Rollover Time for Full-Scale Power (Minimum and Maximum Power Gain) Note that the energy register contents rolls over to full-scale
negative (0x800000) and continues to increase in value when
the power or energy flow is positive—see Figure 66. Conversely, if the power is negative, the energy register underflows to full-
scale positive (0x7FFFFF) and continues to decrease in value. By using the interrupt enable register, the ADE7753 can be
configured to issue an interrupt (IRQ) when the active energy register is greater than half-full (positive or negative) or when an overflow or underflow occurs. Integration Time under Steady Load As mentioned in the last section, the discrete time sample period (T) for the accumulation register is 1.1 μs (4/CLKIN).
With full-scale sinusoidal signals on the analog inputs and the
WGAIN register set to 0x000, the average word value from each
LPF2 is 0xCCCCD—see Figure 61. The maximum positive
value that can be stored in the internal 49-bit register is 248 or
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0xFFFF,FFFF,FFFF before it overflows. The integration time under these conditions with WDIV = 0 is calculated as follows:
Time = xCCCCD0FFFFFFFF,xFFFF,0× 1.12 μs = 375.8 s = 6.26 min(15)
When WDIV is set to a value different from 0, the integration time varies, as shown in Equation 16.
WDIVTimeTimeWDIV×==0 (16)
POWER OFFSET CALIBRATION
The ADE7753 also incorporates an active power offset register (APOS[15:0]). This is a signed twos complement 16-bit register that can be used to remove offsets in the active power calculation—see Figure 65. An offset could exist in the power calculation due to crosstalk between channels on the PCB or in the IC itself. The offset calibration allows the contents of the active power register to be maintained at 0 when no power is being consumed.
The 256 LSBs (APOS = 0x0100) written to the active power offset register are equivalent to 1 LSB in the waveform sample register. Assuming the average value, output from LPF2 is 0xCCCCD (838,861d) when inputs on Channels 1 and 2 are both at full scale. At −60 dB down on Channel 1 (1/1000 of the Channel 1 full-scale input), the average word value output from LPF2 is 838.861 (838,861/1,000). One LSB in the LPF2 output has a measurement error of 1/838.861 × 100% = 0.119% of the average value. The active power offset register has a resolution equal to 1/256 LSB of the waveform register, therefore the power offset correction resolution is 0.00047%/LSB (0.119%/256) at –60 dB.
ENERGY-TO-FREQUENCY CONVERSION
ADE7753 also provides energy-to-frequency conversion for calibration purposes. After initial calibration at manufacturing, the manufacturer or end customer often verify the energy meter calibration. One convenient way to verify the meter calibration is for the manufacturer to provide an output frequency, which is proportional to the energy or active power under steady load conditions. This output frequency can provide a simple, single-wire, optically isolated interface to external calibration equipment. Figure 67 illustrates the energy-to-frequency conversion in the ADE7753. CFNUM[11:0]CF110CFDEN[11:0]110AENERGY[48:0]48002875-0-066%DFC
Figure 67. ADE7753 Energy-to-Frequency Conversion
A digital-to-frequency converter (DFC) is used to generate the CF pulsed output. The DFC generates a pulse each time 1 LSB in the active energy register is accumulated. An output pulse is generated when (CFDEN + 1)/(CFNUM + 1) number of pulses are generated at the DFC output. Under steady load conditions, the output frequency is proportional to the active power.
The maximum output frequency, with ac input signals at full scale and CFNUM = 0x00 and CFDEN = 0x00, is approximately 23 kHz.
The ADE7753 incorporates two registers, CFNUM[11:0] and CFDEN[11:0], to set the CF frequency. These are unsigned 12-bit registers, which can be used to adjust the CF frequency to a wide range of values. These frequency-scaling registers are 12-bit registers, which can scale the output frequency by 1/212 to 1 with a step of 1/212.
If the value 0 is written to any of these registers, the value 1 would be applied to the register. The ratio (CFNUM + 1)/ (CFDEN + 1) should be smaller than 1 to ensure proper operation. If the ratio of the registers (CFNUM + 1)/(CFDEN + 1) is greater than 1, the register values would be adjusted to a ratio (CFNUM + 1)/(CFDEN + 1) of 1. For example, if the output frequency is 1.562 kHz while the contents of CFDEN are 0 (0x000), then the output frequency can be set to 6.1 Hz by writing 0xFF to the CFDEN register.
When CFNUM and CFDEN are both set to one, the CF pulse width is fixed at 16 CLKIN/4 clock cycles, approximately 18 μs with a CLKIN of 3.579545 MHz. If the CF pulse output is longer than 180 ms for an active energy frequency of less than 5.56 Hz, the pulse width is fixed at 90 ms. Otherwise, the pulse width is 50% of the duty cycle.
The output frequency has a slight ripple at a frequency equal to twice the line frequency. This is due to imperfect filtering of the instantaneous power signal to generate the active power signal—see the Active Power Calculation section. Equation 9 from the Active Power Calculation section gives an expression for the instantaneous power signal. This is filtered by LPF2, which has a magnitude response given by Equation 17. 29.811)(2ffH+= (17)
The active power signal (output of LPF2) can be rewritten as
p(t) = VI −⎥⎥⎥⎥⎥⎦⎤⎢⎢⎢⎢⎢⎣⎡⎟⎠⎞⎜⎝⎛+29.81L2fVI× cos(4πfLt) (18)
where fL is the line frequency, for example, 60 Hz.
From Equation 13,
E(t) = VIt − ⎥⎥⎥⎥⎥⎦⎤⎢⎢⎢⎢⎢⎣⎡⎟⎠⎞⎜⎝⎛+π29.814LL2ffVI× sin(4πfLt) (19)
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From Equation 19 it can be seen that there is a small ripple in the energy calculation due to a sin(2 ωt) component. This is shown graphically in Figure 68. The active energy calculation is shown by the dashed straight line and is equal to V × I × t. The sinusoidal ripple in the active energy calculation is also shown.
Since the average value of a sinusoid is 0, this ripple does not contribute to the energy calculation over time. However, the ripple can be observed in the frequency output, especially at higher output frequencies. The ripple gets larger as a percentage of the frequency at larger loads and higher output frequencies. The reason is simply that at higher output frequencies the integration or averaging time in the energy-to-frequency conversion process is shorter. As a consequence, some of the sinusoidal ripple is observable in the frequency output. Choosing a lower output frequency at CF for calibration can significantly reduce the ripple. Also, averaging the output frequency by using a longer gate time for the counter achieves the same results. VI–sin(4×π×fL×t)4×π×fL(1+2×fL/8.9Hz)E(t)tVlt02875-0-067
Figure 68. Output Frequency Ripple
WDIV[7:0]APOS[15:0]WGAIN[11:0]LPF1++LAENERGY [23:0]ACCUMULATE ACTIVEENERGY IN INTERNALREGISTER AND UPDATETHE LAENERGY REGISTERAT THE END OF LINECYCLINE CYCLESOUTPUTFROMLPF2FROMCHANNEL 2ADC230LINECYC [15:0]48002875-0-068%ZERO CROSSDETECTIONCALIBRATIONCONTROL
Figure 69. Energy Calculation Line Cycle Energy Accumulation Mode
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LINE CYCLE ENERGY ACCUMULATION MODE
In line cycle energy accumulation mode, the energy accumula-tion of the ADE7753 can be synchronized to the Channel 2 zero crossing so that active energy can be accumulated over an integral number of half line cycles. The advantage of summing the active energy over an integer number of line cycles is that the sinusoidal component in the active energy is reduced to 0. This eliminates any ripple in the energy calculation. Energy is calculated more accurately and in a shorter time because the integration period can be shortened. By using the line cycle energy accumulation mode, the energy calibration can be greatly simplified, and the time required to calibrate the meter can be significantly reduced. The ADE7753 is placed in line cycle energy accumulation mode by setting Bit 7 (CYCMODE) in the mode register. In line cycle energy accumulation mode, the ADE7753 accumulates the active power signal in the LAENERGY register (Address 0x04) for an integral number of line cycles, as shown in Figure 69. The number of half line cycles is specified in the LINECYC register (Address 0x1C). The ADE7753 can accumulate active power for up to 65,535 half line cycles. Because the active power is integrated on an integral number of line cycles, at the end of a line cycle energy accumu-lation cycle the CYCEND flag in the interrupt status register is set (Bit 2). If the CYCEND enable bit in the interrupt enable register is enabled, the IRQ output also goes active low. Thus the IRQ line can also be used to signal the completion of the line cycle energy accumulation. Another calibration cycle can start as long as the CYCMODE bit in the mode register is set.
From Equations 13 and 18,
E(t) = ∫∫⎪⎪⎭⎪⎪⎬⎫⎪⎪⎩⎪⎪⎨⎧⎟⎠⎞⎜⎝⎛+−nTnTfVIdtVI020cos9.81(2πft)dt (20)
where: n is an integer. T is the line cycle period.
Since the sinusoidal component is integrated over an integer number of line cycles, its value is always 0. Therefore,
E = + 0 (21) ∫nTVIdt0
E(t) = VInT (22)
Note that in this mode, the 16-bit LINECYC register can hold a maximum value of 65,535. In other words, the line energy accumulation mode can be used to accumulate active energy for a maximum duration over 65,535 half line cycles. At 60 Hz line frequency, it translates to a total duration of 65,535/120 Hz = 546 seconds.
POSITIVE-ONLY ACCUMULATION MODE
In positive-only accumulation mode, the energy accumulation is done only for positive power, ignoring any occurrence of negative power above or below the no-load threshold, as shown in Figure 70. The CF pulse also reflects this accumulation method when in this mode. The ADE7753 is placed in positive-only accumulation mode by setting the MSB of the mode register (MODE[15]). The default setting for this mode is off. Transitions in the direction of power flow, going from negative to positive or positive to negative, set the IRQ pin