Consent Manager Tag v2.0 (for TCF 2.0) -->
Farnell PDF
Wi-Fi Media Streaming Modules - Analog Devices
Wi-Fi Media Streaming Modules - Analog Devices
- Revenir à l'accueil
Farnell Element 14 :
See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…
Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.
Puce électronique / Microchip :
Sans fil - Wireless :
Texas instrument :
Ordinateurs :
Logiciels :
Tutoriels :
Autres documentations :
![[TXT]](http://www.audentia-gestion.fr/icons/text.gif)
Farnell-NA555-NE555-..> 08-Sep-2014 07:33 1.5M
Farnell-AD9834-Rev-D..> 08-Sep-2014 07:32 1.2M
Farnell-MSP430F15x-M..> 08-Sep-2014 07:32 1.3M
Farnell-AD736-Rev-I-..> 08-Sep-2014 07:31 1.3M
Farnell-AD8307-Data-..> 08-Sep-2014 07:30 1.3M
Farnell-Single-Chip-..> 08-Sep-2014 07:30 1.5M
Farnell-Quadruple-2-..> 08-Sep-2014 07:29 1.5M
Farnell-ADE7758-Rev-..> 08-Sep-2014 07:28 1.7M
Farnell-MAX3221-Rev-..> 08-Sep-2014 07:28 1.8M
Farnell-USB-to-Seria..> 08-Sep-2014 07:27 2.0M
Farnell-AD8313-Analo..> 08-Sep-2014 07:26 2.0M
Farnell-SN54HC164-SN..> 08-Sep-2014 07:25 2.0M
Farnell-AD8310-Analo..> 08-Sep-2014 07:24 2.1M
Farnell-AD8361-Rev-D..> 08-Sep-2014 07:23 2.1M
Farnell-2N3906-Fairc..> 08-Sep-2014 07:22 2.1M
Farnell-AD584-Rev-C-..> 08-Sep-2014 07:20 2.2M
Farnell-ADE7753-Rev-..> 08-Sep-2014 07:20 2.3M
Farnell-TLV320AIC23B..> 08-Sep-2014 07:18 2.4M
Farnell-AD586BRZ-Ana..> 08-Sep-2014 07:17 1.6M
Farnell-STM32F405xxS..> 27-Aug-2014 18:27 1.8M
Farnell-MSP430-Hardw..> 29-Jul-2014 10:36 1.1M
Farnell-LM324-Texas-..> 29-Jul-2014 10:32 1.5M
Farnell-LM386-Low-Vo..> 29-Jul-2014 10:32 1.5M
Farnell-NE5532-Texas..> 29-Jul-2014 10:32 1.5M
Farnell-Hex-Inverter..> 29-Jul-2014 10:31 875K
Farnell-AT90USBKey-H..> 29-Jul-2014 10:31 902K
Farnell-AT89C5131-Ha..> 29-Jul-2014 10:31 1.2M
Farnell-MSP-EXP430F5..> 29-Jul-2014 10:31 1.2M
Farnell-Explorer-16-..> 29-Jul-2014 10:31 1.3M
Farnell-TMP006EVM-Us..> 29-Jul-2014 10:30 1.3M
Farnell-Gertboard-Us..> 29-Jul-2014 10:30 1.4M
Farnell-LMP91051-Use..> 29-Jul-2014 10:30 1.4M
Farnell-Thermometre-..> 29-Jul-2014 10:30 1.4M
Farnell-user-manuel-..> 29-Jul-2014 10:29 1.5M
Farnell-fx-3650P-fx-..> 29-Jul-2014 10:29 1.5M
Farnell-2-GBPS-Diffe..> 28-Jul-2014 17:42 2.7M
Farnell-LMT88-2.4V-1..> 28-Jul-2014 17:42 2.8M
Farnell-Octal-Genera..> 28-Jul-2014 17:42 2.8M
Farnell-Dual-MOSFET-..> 28-Jul-2014 17:41 2.8M
Farnell-TLV320AIC325..> 28-Jul-2014 17:41 2.9M
Farnell-SN54LV4053A-..> 28-Jul-2014 17:20 5.9M
Farnell-TAS1020B-USB..> 28-Jul-2014 17:19 6.2M
Farnell-TPS40060-Wid..> 28-Jul-2014 17:19 6.3M
Farnell-TL082-Wide-B..> 28-Jul-2014 17:16 6.3M
Farnell-RF-short-tra..> 28-Jul-2014 17:16 6.3M
Farnell-maxim-integr..> 28-Jul-2014 17:14 6.4M
Farnell-TSV6390-TSV6..> 28-Jul-2014 17:14 6.4M
Farnell-Fast-Charge-..> 28-Jul-2014 17:12 6.4M
Farnell-NVE-datashee..> 28-Jul-2014 17:12 6.5M
Farnell-Excalibur-Hi..> 28-Jul-2014 17:10 2.4M
Farnell-Excalibur-Hi..> 28-Jul-2014 17:10 2.4M
Farnell-REF102-10V-P..> 28-Jul-2014 17:09 2.4M
Farnell-TMS320F28055..> 28-Jul-2014 17:09 2.7M
Farnell-MULTICOMP-Ra..> 22-Jul-2014 12:35 5.9M
Farnell-RASPBERRY-PI..> 22-Jul-2014 12:35 5.9M
Farnell-Dremel-Exper..> 22-Jul-2014 12:34 1.6M
Farnell-STM32F103x8-..> 22-Jul-2014 12:33 1.6M
Farnell-BD6xxx-PDF.htm 22-Jul-2014 12:33 1.6M
Farnell-L78S-STMicro..> 22-Jul-2014 12:32 1.6M
Farnell-RaspiCam-Doc..> 22-Jul-2014 12:32 1.6M
Farnell-SB520-SB5100..> 22-Jul-2014 12:32 1.6M
Farnell-iServer-Micr..> 22-Jul-2014 12:32 1.6M
Farnell-LUMINARY-MIC..> 22-Jul-2014 12:31 3.6M
Farnell-TEXAS-INSTRU..> 22-Jul-2014 12:31 2.4M
Farnell-TEXAS-INSTRU..> 22-Jul-2014 12:30 4.6M
Farnell-CLASS 1-or-2..> 22-Jul-2014 12:30 4.7M
Farnell-TEXAS-INSTRU..> 22-Jul-2014 12:29 4.8M
Farnell-Evaluating-t..> 22-Jul-2014 12:28 4.9M
Farnell-LM3S6952-Mic..> 22-Jul-2014 12:27 5.9M
Farnell-Keyboard-Mou..> 22-Jul-2014 12:27 5.9M
Farnell-Full-Datashe..> 15-Jul-2014 17:08 951K
Farnell-pmbta13_pmbt..> 15-Jul-2014 17:06 959K
Farnell-EE-SPX303N-4..> 15-Jul-2014 17:06 969K
Farnell-Datasheet-NX..> 15-Jul-2014 17:06 1.0M
Farnell-Datasheet-Fa..> 15-Jul-2014 17:05 1.0M
Farnell-MIDAS-un-tra..> 15-Jul-2014 17:05 1.0M
Farnell-SERIAL-TFT-M..> 15-Jul-2014 17:05 1.0M
Farnell-MCOC1-Farnel..> 15-Jul-2014 17:05 1.0M
Farnell-TMR-2-series..> 15-Jul-2014 16:48 787K
Farnell-DC-DC-Conver..> 15-Jul-2014 16:48 781K
Farnell-Full-Datashe..> 15-Jul-2014 16:47 803K
Farnell-TMLM-Series-..> 15-Jul-2014 16:47 810K
Farnell-TEL-5-Series..> 15-Jul-2014 16:47 814K
Farnell-TXL-series-t..> 15-Jul-2014 16:47 829K
Farnell-TEP-150WI-Se..> 15-Jul-2014 16:47 837K
Farnell-AC-DC-Power-..> 15-Jul-2014 16:47 845K
Farnell-TIS-Instruct..> 15-Jul-2014 16:47 845K
Farnell-TOS-tracopow..> 15-Jul-2014 16:47 852K
Farnell-TCL-DC-traco..> 15-Jul-2014 16:46 858K
Farnell-TIS-series-t..> 15-Jul-2014 16:46 875K
Farnell-TMR-2-Series..> 15-Jul-2014 16:46 897K
Farnell-TMR-3-WI-Ser..> 15-Jul-2014 16:46 939K
Farnell-TEN-8-WI-Ser..> 15-Jul-2014 16:46 939K
Farnell-Full-Datashe..> 15-Jul-2014 16:46 947K
Farnell-HIP4081A-Int..> 07-Jul-2014 19:47 1.0M
Farnell-ISL6251-ISL6..> 07-Jul-2014 19:47 1.1M
Farnell-DG411-DG412-..> 07-Jul-2014 19:47 1.0M
Farnell-3367-ARALDIT..> 07-Jul-2014 19:46 1.2M
Farnell-ICM7228-Inte..> 07-Jul-2014 19:46 1.1M
Farnell-Data-Sheet-K..> 07-Jul-2014 19:46 1.2M
Farnell-Silica-Gel-M..> 07-Jul-2014 19:46 1.2M
Farnell-TKC2-Dusters..> 07-Jul-2014 19:46 1.2M
Farnell-CRC-HANDCLEA..> 07-Jul-2014 19:46 1.2M
Farnell-760G-French-..> 07-Jul-2014 19:45 1.2M
Farnell-Decapant-KF-..> 07-Jul-2014 19:45 1.2M
Farnell-1734-ARALDIT..> 07-Jul-2014 19:45 1.2M
Farnell-Araldite-Fus..> 07-Jul-2014 19:45 1.2M
Farnell-fiche-de-don..> 07-Jul-2014 19:44 1.4M
Farnell-safety-data-..> 07-Jul-2014 19:44 1.4M
Farnell-A-4-Hardener..> 07-Jul-2014 19:44 1.4M
Farnell-CC-Debugger-..> 07-Jul-2014 19:44 1.5M
Farnell-MSP430-Hardw..> 07-Jul-2014 19:43 1.8M
Farnell-SmartRF06-Ev..> 07-Jul-2014 19:43 1.6M
Farnell-CC2531-USB-H..> 07-Jul-2014 19:43 1.8M
Farnell-Alimentation..> 07-Jul-2014 19:43 1.8M
Farnell-BK889B-PONT-..> 07-Jul-2014 19:42 1.8M
Farnell-User-Guide-M..> 07-Jul-2014 19:41 2.0M
Farnell-T672-3000-Se..> 07-Jul-2014 19:41 2.0M
Farnell-0050375063-D..> 18-Jul-2014 17:03 2.5M
Farnell-Mini-Fit-Jr-..> 18-Jul-2014 17:03 2.5M
Farnell-43031-0002-M..> 18-Jul-2014 17:03 2.5M
Farnell-0433751001-D..> 18-Jul-2014 17:02 2.5M
Farnell-Cube-3D-Prin..> 18-Jul-2014 17:02 2.5M
Farnell-MTX-Compact-..> 18-Jul-2014 17:01 2.5M
Farnell-MTX-3250-MTX..> 18-Jul-2014 17:01 2.5M
Farnell-ATtiny26-L-A..> 18-Jul-2014 17:00 2.6M
Farnell-MCP3421-Micr..> 18-Jul-2014 17:00 1.2M
Farnell-LM19-Texas-I..> 18-Jul-2014 17:00 1.2M
Farnell-Data-Sheet-S..> 18-Jul-2014 17:00 1.2M
Farnell-LMH6518-Texa..> 18-Jul-2014 16:59 1.3M
Farnell-AD7719-Low-V..> 18-Jul-2014 16:59 1.4M
Farnell-DAC8143-Data..> 18-Jul-2014 16:59 1.5M
Farnell-BGA7124-400-..> 18-Jul-2014 16:59 1.5M
Farnell-SICK-OPTIC-E..> 18-Jul-2014 16:58 1.5M
Farnell-LT3757-Linea..> 18-Jul-2014 16:58 1.6M
Farnell-LT1961-Linea..> 18-Jul-2014 16:58 1.6M
Farnell-PIC18F2420-2..> 18-Jul-2014 16:57 2.5M
Farnell-DS3231-DS-PD..> 18-Jul-2014 16:57 2.5M
Farnell-RDS-80-PDF.htm 18-Jul-2014 16:57 1.3M
Farnell-AD8300-Data-..> 18-Jul-2014 16:56 1.3M
Farnell-LT6233-Linea..> 18-Jul-2014 16:56 1.3M
Farnell-MAX1365-MAX1..> 18-Jul-2014 16:56 1.4M
Farnell-XPSAF5130-PD..> 18-Jul-2014 16:56 1.4M
Farnell-DP83846A-DsP..> 18-Jul-2014 16:55 1.5M
Farnell-Dremel-Exper..> 18-Jul-2014 16:55 1.6M
Farnell-MCOC1-Farnel..> 16-Jul-2014 09:04 1.0M
Farnell-SL3S1203_121..> 16-Jul-2014 09:04 1.1M
Farnell-PN512-Full-N..> 16-Jul-2014 09:03 1.4M
Farnell-SL3S4011_402..> 16-Jul-2014 09:03 1.1M
Farnell-LPC408x-7x 3..> 16-Jul-2014 09:03 1.6M
Farnell-PCF8574-PCF8..> 16-Jul-2014 09:03 1.7M
Farnell-LPC81xM-32-b..> 16-Jul-2014 09:02 2.0M
Farnell-LPC1769-68-6..> 16-Jul-2014 09:02 1.9M
Farnell-Download-dat..> 16-Jul-2014 09:02 2.2M
Farnell-LPC3220-30-4..> 16-Jul-2014 09:02 2.2M
Farnell-LPC11U3x-32-..> 16-Jul-2014 09:01 2.4M
Farnell-SL3ICS1002-1..> 16-Jul-2014 09:01 2.5M
Farnell-T672-3000-Se..> 08-Jul-2014 18:59 2.0M
Farnell-tesa®pack63..> 08-Jul-2014 18:56 2.0M
Farnell-Encodeur-USB..> 08-Jul-2014 18:56 2.0M
Farnell-CC2530ZDK-Us..> 08-Jul-2014 18:55 2.1M
Farnell-2020-Manuel-..> 08-Jul-2014 18:55 2.1M
Farnell-Synchronous-..> 08-Jul-2014 18:54 2.1M
Farnell-Arithmetic-L..> 08-Jul-2014 18:54 2.1M
Farnell-NA555-NE555-..> 08-Jul-2014 18:53 2.2M
Farnell-4-Bit-Magnit..> 08-Jul-2014 18:53 2.2M
Farnell-LM555-Timer-..> 08-Jul-2014 18:53 2.2M
Farnell-L293d-Texas-..> 08-Jul-2014 18:53 2.2M
Farnell-SN54HC244-SN..> 08-Jul-2014 18:52 2.3M
Farnell-MAX232-MAX23..> 08-Jul-2014 18:52 2.3M
Farnell-High-precisi..> 08-Jul-2014 18:51 2.3M
Farnell-SMU-Instrume..> 08-Jul-2014 18:51 2.3M
Farnell-900-Series-B..> 08-Jul-2014 18:50 2.3M
Farnell-BA-Series-Oh..> 08-Jul-2014 18:50 2.3M
Farnell-UTS-Series-S..> 08-Jul-2014 18:49 2.5M
Farnell-270-Series-O..> 08-Jul-2014 18:49 2.3M
Farnell-UTS-Series-S..> 08-Jul-2014 18:49 2.8M
Farnell-Tiva-C-Serie..> 08-Jul-2014 18:49 2.6M
Farnell-UTO-Souriau-..> 08-Jul-2014 18:48 2.8M
Farnell-Clipper-Seri..> 08-Jul-2014 18:48 2.8M
Farnell-SOURIAU-Cont..> 08-Jul-2014 18:47 3.0M
Farnell-851-Series-P..> 08-Jul-2014 18:47 3.0M
Farnell-SL59830-Inte..> 06-Jul-2014 10:07 1.0M
Farnell-ALF1210-PDF.htm 06-Jul-2014 10:06 4.0M
Farnell-AD7171-16-Bi..> 06-Jul-2014 10:06 1.0M
Farnell-Low-Noise-24..> 06-Jul-2014 10:05 1.0M
Farnell-ESCON-Featur..> 06-Jul-2014 10:05 938K
Farnell-74LCX573-Fai..> 06-Jul-2014 10:05 1.9M
Farnell-1N4148WS-Fai..> 06-Jul-2014 10:04 1.9M
Farnell-FAN6756-Fair..> 06-Jul-2014 10:04 850K
Farnell-Datasheet-Fa..> 06-Jul-2014 10:04 861K
Farnell-ES1F-ES1J-fi..> 06-Jul-2014 10:04 867K
Farnell-QRE1113-Fair..> 06-Jul-2014 10:03 879K
Farnell-2N7002DW-Fai..> 06-Jul-2014 10:03 886K
Farnell-FDC2512-Fair..> 06-Jul-2014 10:03 886K
Farnell-FDV301N-Digi..> 06-Jul-2014 10:03 886K
Farnell-S1A-Fairchil..> 06-Jul-2014 10:03 896K
Farnell-BAV99-Fairch..> 06-Jul-2014 10:03 896K
Farnell-74AC00-74ACT..> 06-Jul-2014 10:03 911K
Farnell-NaPiOn-Panas..> 06-Jul-2014 10:02 911K
Farnell-LQ-RELAYS-AL..> 06-Jul-2014 10:02 924K
Farnell-ev-relays-ae..> 06-Jul-2014 10:02 926K
Farnell-ESCON-Featur..> 06-Jul-2014 10:02 931K
Farnell-Amplifier-In..> 06-Jul-2014 10:02 940K
Farnell-Serial-File-..> 06-Jul-2014 10:02 941K
Farnell-Both-the-Del..> 06-Jul-2014 10:01 948K
Farnell-Videk-PDF.htm 06-Jul-2014 10:01 948K
Farnell-EPCOS-173438..> 04-Jul-2014 10:43 3.3M
Farnell-Sensorless-C..> 04-Jul-2014 10:42 3.3M
Farnell-197.31-KB-Te..> 04-Jul-2014 10:42 3.3M
Farnell-PIC12F609-61..> 04-Jul-2014 10:41 3.7M
Farnell-PADO-semi-au..> 04-Jul-2014 10:41 3.7M
Farnell-03-iec-runds..> 04-Jul-2014 10:40 3.7M
Farnell-ACC-Silicone..> 04-Jul-2014 10:40 3.7M
Farnell-Series-TDS10..> 04-Jul-2014 10:39 4.0M
Farnell-03-iec-runds..> 04-Jul-2014 10:40 3.7M
Farnell-0430300011-D..> 14-Jun-2014 18:13 2.0M
Farnell-06-6544-8-PD..> 26-Mar-2014 17:56 2.7M
Farnell-3M-Polyimide..> 21-Mar-2014 08:09 3.9M
Farnell-3M-VolitionT..> 25-Mar-2014 08:18 3.3M
Farnell-10BQ060-PDF.htm 14-Jun-2014 09:50 2.4M
Farnell-10TPB47M-End..> 14-Jun-2014 18:16 3.4M
Farnell-12mm-Size-In..> 14-Jun-2014 09:50 2.4M
Farnell-24AA024-24LC..> 23-Jun-2014 10:26 3.1M
Farnell-50A-High-Pow..> 20-Mar-2014 17:31 2.9M
Farnell-197.31-KB-Te..> 04-Jul-2014 10:42 3.3M
Farnell-1907-2006-PD..> 26-Mar-2014 17:56 2.7M
Farnell-5910-PDF.htm 25-Mar-2014 08:15 3.0M
Farnell-6517b-Electr..> 29-Mar-2014 11:12 3.3M
Farnell-A-True-Syste..> 29-Mar-2014 11:13 3.3M
Farnell-ACC-Silicone..> 04-Jul-2014 10:40 3.7M
Farnell-AD524-PDF.htm 20-Mar-2014 17:33 2.8M
Farnell-ADL6507-PDF.htm 14-Jun-2014 18:19 3.4M
Farnell-ADSP-21362-A..> 20-Mar-2014 17:34 2.8M
Farnell-ALF1210-PDF.htm 04-Jul-2014 10:39 4.0M
Farnell-ALF1225-12-V..> 01-Apr-2014 07:40 3.4M
Farnell-ALF2412-24-V..> 01-Apr-2014 07:39 3.4M
Farnell-AN10361-Phil..> 23-Jun-2014 10:29 2.1M
Farnell-ARADUR-HY-13..> 26-Mar-2014 17:55 2.8M
Farnell-ARALDITE-201..> 21-Mar-2014 08:12 3.7M
Farnell-ARALDITE-CW-..> 26-Mar-2014 17:56 2.7M
Farnell-ATMEL-8-bit-..> 19-Mar-2014 18:04 2.1M
Farnell-ATMEL-8-bit-..> 11-Mar-2014 07:55 2.1M
Farnell-ATmega640-VA..> 14-Jun-2014 09:49 2.5M
Farnell-ATtiny20-PDF..> 25-Mar-2014 08:19 3.6M
Farnell-ATtiny26-L-A..> 13-Jun-2014 18:40 1.8M
Farnell-Alimentation..> 14-Jun-2014 18:24 2.5M
Farnell-Alimentation..> 01-Apr-2014 07:42 3.4M
Farnell-Amplificateu..> 29-Mar-2014 11:11 3.3M
Farnell-An-Improved-..> 14-Jun-2014 09:49 2.5M
Farnell-Atmel-ATmega..> 19-Mar-2014 18:03 2.2M
Farnell-Avvertenze-e..> 14-Jun-2014 18:20 3.3M
Farnell-BC846DS-NXP-..> 13-Jun-2014 18:42 1.6M
Farnell-BC847DS-NXP-..> 23-Jun-2014 10:24 3.3M
Farnell-BF545A-BF545..> 23-Jun-2014 10:28 2.1M
Farnell-BK2650A-BK26..> 29-Mar-2014 11:10 3.3M
Farnell-BT151-650R-N..> 13-Jun-2014 18:40 1.7M
Farnell-BTA204-800C-..> 13-Jun-2014 18:42 1.6M
Farnell-BUJD203AX-NX..> 13-Jun-2014 18:41 1.7M
Farnell-BYV29F-600-N..> 13-Jun-2014 18:42 1.6M
Farnell-BYV79E-serie..> 10-Mar-2014 16:19 1.6M
Farnell-BZX384-serie..> 23-Jun-2014 10:29 2.1M
Farnell-Battery-GBA-..> 14-Jun-2014 18:13 2.0M
Farnell-C.A-6150-C.A..> 14-Jun-2014 18:24 2.5M
Farnell-C.A 8332B-C...> 01-Apr-2014 07:40 3.4M
Farnell-CC2560-Bluet..> 29-Mar-2014 11:14 2.8M
Farnell-CD4536B-Type..> 14-Jun-2014 18:13 2.0M
Farnell-CIRRUS-LOGIC..> 10-Mar-2014 17:20 2.1M
Farnell-CS5532-34-BS..> 01-Apr-2014 07:39 3.5M
Farnell-Cannon-ZD-PD..> 11-Mar-2014 08:13 2.8M
Farnell-Ceramic-tran..> 14-Jun-2014 18:19 3.4M
Farnell-Circuit-Note..> 26-Mar-2014 18:00 2.8M
Farnell-Circuit-Note..> 26-Mar-2014 18:00 2.8M
Farnell-Cles-electro..> 21-Mar-2014 08:13 3.9M
Farnell-Conception-d..> 11-Mar-2014 07:49 2.4M
Farnell-Connectors-N..> 14-Jun-2014 18:12 2.1M
Farnell-Construction..> 14-Jun-2014 18:25 2.5M
Farnell-Controle-de-..> 11-Mar-2014 08:16 2.8M
Farnell-Cordless-dri..> 14-Jun-2014 18:13 2.0M
Farnell-Current-Tran..> 26-Mar-2014 17:58 2.7M
Farnell-Current-Tran..> 26-Mar-2014 17:58 2.7M
Farnell-Current-Tran..> 26-Mar-2014 17:59 2.7M
Farnell-Current-Tran..> 26-Mar-2014 17:59 2.7M
Farnell-DC-Fan-type-..> 14-Jun-2014 09:48 2.5M
Farnell-DC-Fan-type-..> 14-Jun-2014 09:51 1.8M
Farnell-Davum-TMC-PD..> 14-Jun-2014 18:27 2.4M
Farnell-De-la-puissa..> 29-Mar-2014 11:10 3.3M
Farnell-Directive-re..> 25-Mar-2014 08:16 3.0M
Farnell-Documentatio..> 14-Jun-2014 18:26 2.5M
Farnell-Download-dat..> 13-Jun-2014 18:40 1.8M
Farnell-ECO-Series-T..> 20-Mar-2014 08:14 2.5M
Farnell-ELMA-PDF.htm 29-Mar-2014 11:13 3.3M
Farnell-EMC1182-PDF.htm 25-Mar-2014 08:17 3.0M
Farnell-EPCOS-173438..> 04-Jul-2014 10:43 3.3M
Farnell-EPCOS-Sample..> 11-Mar-2014 07:53 2.2M
Farnell-ES2333-PDF.htm 11-Mar-2014 08:14 2.8M
Farnell-Ed.081002-DA..> 19-Mar-2014 18:02 2.5M
Farnell-F28069-Picco..> 14-Jun-2014 18:14 2.0M
Farnell-F42202-PDF.htm 19-Mar-2014 18:00 2.5M
Farnell-FDS-ITW-Spra..> 14-Jun-2014 18:22 3.3M
Farnell-FICHE-DE-DON..> 10-Mar-2014 16:17 1.6M
Farnell-Fastrack-Sup..> 23-Jun-2014 10:25 3.3M
Farnell-Ferric-Chlor..> 29-Mar-2014 11:14 2.8M
Farnell-Fiche-de-don..> 14-Jun-2014 09:47 2.5M
Farnell-Fiche-de-don..> 14-Jun-2014 18:26 2.5M
Farnell-Fluke-1730-E..> 14-Jun-2014 18:23 2.5M
Farnell-GALVA-A-FROI..> 26-Mar-2014 17:56 2.7M
Farnell-GALVA-MAT-Re..> 26-Mar-2014 17:57 2.7M
Farnell-GN-RELAYS-AG..> 20-Mar-2014 08:11 2.6M
Farnell-HC49-4H-Crys..> 14-Jun-2014 18:20 3.3M
Farnell-HFE1600-Data..> 14-Jun-2014 18:22 3.3M
Farnell-HI-70300-Sol..> 14-Jun-2014 18:27 2.4M
Farnell-HUNTSMAN-Adv..> 10-Mar-2014 16:17 1.7M
Farnell-Haute-vitess..> 11-Mar-2014 08:17 2.4M
Farnell-IP4252CZ16-8..> 13-Jun-2014 18:41 1.7M
Farnell-Instructions..> 19-Mar-2014 18:01 2.5M
Farnell-KSZ8851SNL-S..> 23-Jun-2014 10:28 2.1M
Farnell-L-efficacite..> 11-Mar-2014 07:52 2.3M
Farnell-LCW-CQ7P.CC-..> 25-Mar-2014 08:19 3.2M
Farnell-LME49725-Pow..> 14-Jun-2014 09:49 2.5M
Farnell-LOCTITE-542-..> 25-Mar-2014 08:15 3.0M
Farnell-LOCTITE-3463..> 25-Mar-2014 08:19 3.0M
Farnell-LUXEON-Guide..> 11-Mar-2014 07:52 2.3M
Farnell-Leaded-Trans..> 23-Jun-2014 10:26 3.2M
Farnell-Les-derniers..> 11-Mar-2014 07:50 2.3M
Farnell-Loctite3455-..> 25-Mar-2014 08:16 3.0M
Farnell-Low-cost-Enc..> 13-Jun-2014 18:42 1.7M
Farnell-Lubrifiant-a..> 26-Mar-2014 18:00 2.7M
Farnell-MC3510-PDF.htm 25-Mar-2014 08:17 3.0M
Farnell-MC21605-PDF.htm 11-Mar-2014 08:14 2.8M
Farnell-MCF532x-7x-E..> 29-Mar-2014 11:14 2.8M
Farnell-MICREL-KSZ88..> 11-Mar-2014 07:54 2.2M
Farnell-MICROCHIP-PI..> 19-Mar-2014 18:02 2.5M
Farnell-MOLEX-39-00-..> 10-Mar-2014 17:19 1.9M
Farnell-MOLEX-43020-..> 10-Mar-2014 17:21 1.9M
Farnell-MOLEX-43160-..> 10-Mar-2014 17:21 1.9M
Farnell-MOLEX-87439-..> 10-Mar-2014 17:21 1.9M
Farnell-MPXV7002-Rev..> 20-Mar-2014 17:33 2.8M
Farnell-MX670-MX675-..> 14-Jun-2014 09:46 2.5M
Farnell-Microchip-MC..> 13-Jun-2014 18:27 1.8M
Farnell-Microship-PI..> 11-Mar-2014 07:53 2.2M
Farnell-Midas-Active..> 14-Jun-2014 18:17 3.4M
Farnell-Midas-MCCOG4..> 14-Jun-2014 18:11 2.1M
Farnell-Miniature-Ci..> 26-Mar-2014 17:55 2.8M
Farnell-Mistral-PDF.htm 14-Jun-2014 18:12 2.1M
Farnell-Molex-83421-..> 14-Jun-2014 18:17 3.4M
Farnell-Molex-COMMER..> 14-Jun-2014 18:16 3.4M
Farnell-Molex-Crimp-..> 10-Mar-2014 16:27 1.7M
Farnell-Multi-Functi..> 20-Mar-2014 17:38 3.0M
Farnell-NTE_SEMICOND..> 11-Mar-2014 07:52 2.3M
Farnell-NXP-74VHC126..> 10-Mar-2014 16:17 1.6M
Farnell-NXP-BT136-60..> 11-Mar-2014 07:52 2.3M
Farnell-NXP-PBSS9110..> 10-Mar-2014 17:21 1.9M
Farnell-NXP-PCA9555 ..> 11-Mar-2014 07:54 2.2M
Farnell-NXP-PMBFJ620..> 10-Mar-2014 16:16 1.7M
Farnell-NXP-PSMN1R7-..> 10-Mar-2014 16:17 1.6M
Farnell-NXP-PSMN7R0-..> 10-Mar-2014 17:19 2.1M
Farnell-NXP-TEA1703T..> 11-Mar-2014 08:15 2.8M
Farnell-Nilï¬-sk-E-..> 14-Jun-2014 09:47 2.5M
Farnell-Novembre-201..> 20-Mar-2014 17:38 3.3M
Farnell-OMRON-Master..> 10-Mar-2014 16:26 1.8M
Farnell-OSLON-SSL-Ce..> 19-Mar-2014 18:03 2.1M
Farnell-OXPCIE958-FB..> 13-Jun-2014 18:40 1.8M
Farnell-PADO-semi-au..> 04-Jul-2014 10:41 3.7M
Farnell-PBSS5160T-60..> 19-Mar-2014 18:03 2.1M
Farnell-PDTA143X-ser..> 20-Mar-2014 08:12 2.6M
Farnell-PDTB123TT-NX..> 13-Jun-2014 18:43 1.5M
Farnell-PESD5V0F1BL-..> 13-Jun-2014 18:43 1.5M
Farnell-PESD9X5.0L-P..> 13-Jun-2014 18:43 1.6M
Farnell-PIC12F609-61..> 04-Jul-2014 10:41 3.7M
Farnell-PIC18F2455-2..> 23-Jun-2014 10:27 3.1M
Farnell-PIC24FJ256GB..> 14-Jun-2014 09:51 2.4M
Farnell-PMBT3906-PNP..> 13-Jun-2014 18:44 1.5M
Farnell-PMBT4403-PNP..> 23-Jun-2014 10:27 3.1M
Farnell-PMEG4002EL-N..> 14-Jun-2014 18:18 3.4M
Farnell-PMEG4010CEH-..> 13-Jun-2014 18:43 1.6M
Farnell-Panasonic-15..> 23-Jun-2014 10:29 2.1M
Farnell-Panasonic-EC..> 20-Mar-2014 17:36 2.6M
Farnell-Panasonic-EZ..> 20-Mar-2014 08:10 2.6M
Farnell-Panasonic-Id..> 20-Mar-2014 17:35 2.6M
Farnell-Panasonic-Ne..> 20-Mar-2014 17:36 2.6M
Farnell-Panasonic-Ra..> 20-Mar-2014 17:37 2.6M
Farnell-Panasonic-TS..> 20-Mar-2014 08:12 2.6M
Farnell-Panasonic-Y3..> 20-Mar-2014 08:11 2.6M
Farnell-Pico-Spox-Wi..> 10-Mar-2014 16:16 1.7M
Farnell-Pompes-Charg..> 24-Apr-2014 20:23 3.3M
Farnell-Ponts-RLC-po..> 14-Jun-2014 18:23 3.3M
Farnell-Portable-Ana..> 29-Mar-2014 11:16 2.8M
Farnell-Premier-Farn..> 21-Mar-2014 08:11 3.8M
Farnell-Produit-3430..> 14-Jun-2014 09:48 2.5M
Farnell-Proskit-SS-3..> 10-Mar-2014 16:26 1.8M
Farnell-Puissance-ut..> 11-Mar-2014 07:49 2.4M
Farnell-Q48-PDF.htm 23-Jun-2014 10:29 2.1M
Farnell-Radial-Lead-..> 20-Mar-2014 08:12 2.6M
Farnell-Realiser-un-..> 11-Mar-2014 07:51 2.3M
Farnell-Reglement-RE..> 21-Mar-2014 08:08 3.9M
Farnell-Repartiteurs..> 14-Jun-2014 18:26 2.5M
Farnell-S-TRI-SWT860..> 21-Mar-2014 08:11 3.8M
Farnell-SB175-Connec..> 11-Mar-2014 08:14 2.8M
Farnell-SMBJ-Transil..> 29-Mar-2014 11:12 3.3M
Farnell-SOT-23-Multi..> 11-Mar-2014 07:51 2.3M
Farnell-SPLC780A1-16..> 14-Jun-2014 18:25 2.5M
Farnell-SSC7102-Micr..> 23-Jun-2014 10:25 3.2M
Farnell-SVPE-series-..> 14-Jun-2014 18:15 2.0M
Farnell-Sensorless-C..> 04-Jul-2014 10:42 3.3M
Farnell-Septembre-20..> 20-Mar-2014 17:46 3.7M
Farnell-Serie-PicoSc..> 19-Mar-2014 18:01 2.5M
Farnell-Serie-Standa..> 14-Jun-2014 18:23 3.3M
Farnell-Series-2600B..> 20-Mar-2014 17:30 3.0M
Farnell-Series-TDS10..> 04-Jul-2014 10:39 4.0M
Farnell-Signal-PCB-R..> 14-Jun-2014 18:11 2.1M
Farnell-Strangkuhlko..> 21-Mar-2014 08:09 3.9M
Farnell-Supercapacit..> 26-Mar-2014 17:57 2.7M
Farnell-TDK-Lambda-H..> 14-Jun-2014 18:21 3.3M
Farnell-TEKTRONIX-DP..> 10-Mar-2014 17:20 2.0M
Farnell-Tektronix-AC..> 13-Jun-2014 18:44 1.5M
Farnell-Telemetres-l..> 20-Mar-2014 17:46 3.7M
Farnell-Termometros-..> 14-Jun-2014 18:14 2.0M
Farnell-The-essentia..> 10-Mar-2014 16:27 1.7M
Farnell-U2270B-PDF.htm 14-Jun-2014 18:15 3.4M
Farnell-USB-Buccanee..> 14-Jun-2014 09:48 2.5M
Farnell-USB1T11A-PDF..> 19-Mar-2014 18:03 2.1M
Farnell-V4N-PDF.htm 14-Jun-2014 18:11 2.1M
Farnell-WetTantalum-..> 11-Mar-2014 08:14 2.8M
Farnell-XPS-AC-Octop..> 14-Jun-2014 18:11 2.1M
Farnell-XPS-MC16-XPS..> 11-Mar-2014 08:15 2.8M
Farnell-YAGEO-DATA-S..> 11-Mar-2014 08:13 2.8M
Farnell-ZigBee-ou-le..> 11-Mar-2014 07:50 2.4M
Farnell-celpac-SUL84..> 21-Mar-2014 08:11 3.8M
Farnell-china_rohs_o..> 21-Mar-2014 10:04 3.9M
Farnell-cree-Xlamp-X..> 20-Mar-2014 17:34 2.8M
Farnell-cree-Xlamp-X..> 20-Mar-2014 17:35 2.7M
Farnell-cree-Xlamp-X..> 20-Mar-2014 17:31 2.9M
Farnell-cree-Xlamp-m..> 20-Mar-2014 17:32 2.9M
Farnell-cree-Xlamp-m..> 20-Mar-2014 17:32 2.9M
Farnell-ir1150s_fr.p..> 29-Mar-2014 11:11 3.3M
Farnell-manual-bus-p..> 10-Mar-2014 16:29 1.9M
Farnell-propose-plus..> 11-Mar-2014 08:19 2.8M
Farnell-techfirst_se..> 21-Mar-2014 08:08 3.9M
Farnell-testo-205-20..> 20-Mar-2014 17:37 3.0M
Farnell-testo-470-Fo..> 20-Mar-2014 17:38 3.0M
Farnell-uC-OS-III-Br..> 10-Mar-2014 17:20 2.0M
Sefram-7866HD.pdf-PD..> 29-Mar-2014 11:46 472K
Sefram-CAT_ENREGISTR..> 29-Mar-2014 11:46 461K
Sefram-CAT_MESUREURS..> 29-Mar-2014 11:46 435K
Sefram-GUIDE_SIMPLIF..> 29-Mar-2014 11:46 481K
Sefram-GUIDE_SIMPLIF..> 29-Mar-2014 11:46 442K
Sefram-GUIDE_SIMPLIF..> 29-Mar-2014 11:46 422K
Sefram-SP270.pdf-PDF..> 29-Mar-2014 11:46 464K
Wi-Fi Media Streaming Modules
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Roku
assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. www.rokulabs.com © Roku 2005.
SPI
PAR.
I2C
Ethernet
10/100
SDRAM
16MB
Antennas
Flash
4MB
I2S
/AC97
RS232
Clocks
400MHZ
Processor
Control Header
ITU-R 656
WiFi
802.11
APPLICATIONS
Add Internet Radio, PC/MAC music library, JPEG, OSD
and music service features to:
• Music systems
• AV receivers
• TVs
• Radios
• DVD Players
FEATURES
• 3.3V RS232, I2C, Parallel, or SPI control
• Easy command protocol suitable for use by a low
cost microcontroller. Allows listing of available
internet radio stations, listing of digital music
libraries, audio playback, TCP/IP access, and
more.
• End-user web access and control
• ITU-R 656 for JPEG or OSD
• Models with built in WIFI 802.11b or 80211g, or
10/100 Auto MDIX Auto Polarity Ethernet
• WiFi drivers and certification
• Microsoft PlaysForSure certification
• Decoded Audio is output over I2S DSP style
synchronous serial port or AC97 interface
• 4Mbytes of program store, field upgradeable
• 16Mbytes of SDRAM
• Real time clock
• I2S/AC97 clock can be internal (supports
48KHz/32Khz and 44.1KHz) or externally
supplied.
• Single 3.3V power supply
• International language support
CODECS SUPPORT
• MP3, WMA, AAC
• WAV, AIFF, LPCM
• JPEG
DIGITAL RIGHTS SUPPORT
• WM DRM10
• Rhapsody
PROTOCOLS
• UPnP AV
• Apple DAAP & OpenTalk
• Rhapsody
• IP / UDP / TCP
• telnet
• SlimServer
• HTTP / HTML
• XML, SOAP
• Internet Radio (mp3, pls, m3u, asx, wma)
• Live365
• PlaysForSure
SUPPORTED SERVICES
• Rhapsody
• Napster
• MSN Music
• Walmart.com
• Musicmatch
• MusicNow
• Live365
• More…
FUNCTIONAL BLOCK DIAGRAM
MB301 / MB302 / MB303 / MB 304 Overview
Wi-Fi Media Streaming Modules
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Roku
assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. www.rokulabs.com © Roku 2005.
Overview
The MB30x Wi-Fi Media Streaming Module allows the easy addition of powerful networked digital music and
display features to your product. Based on Roku’s award winning SoundBridge technology, the MB30x is a proven
and drop-in solution for adding Internet radio, music streaming, JPEG or even an On Screen Display to your
products.
By issuing commands to the streaming module over any of the control links (3.3 volt RS232, SPI, I2C, or Parallel),
you can play internet radio or digital music or stream JPEGs over a home network. The streaming module handles
the complicated work behind the scenes with its embedded and powerful Wi-Fi and network media processor.
Web Control
End users have the option of controlling and configuring the MB30x from a laptop, PC, or Mac. An icon that
represents the networked device containing the MB30x will automatically appear in the PC or Mac UI, since the
MB30x will broadcast its existence via UPnP or Rendezvous (Open Talk).
When the end-user clicks the MB30x icon, it will open a web UI for the device. From this UI, the end user can
configure options, select music to play, pause or resume play, and many other functions.
Example Operating Modes
The MB30x offers a robust control interface that allows client devices infinite control over the details of digital media
streaming, if they so desire. On the other hand, some devices may wish to add digital media support without
investing development time on a new user interface or complex operating modes. For these clients, the MB30x
provides powerful yet simple control commands that take care of all the details. The following examples show
some different usage scenarios that clients could support depending on the level of control and customization
desired:
Mode 1: Internet Radio Presets Only
In this mode, the user can only play internet radio stations. The user initiates playback by pressing a "preset
button" on the remote or front panel interface. The device μC then sends the PlayInternetRadioPreset command
to the streaming module to begin playback. The streaming module comes configured with the presets set to
popular internet radio stations, however, these can be changed using Web Control or streaming module
commands.
Mode 2: Use built-in UI
The streaming module includes a string-based user interface that supports its full range of features, including
internet radio, networked music library browsing, searching, and playback, and WiFi setup and configuration. This
UI supports displays ranging from 1 to 24 lines in height, automatically configuring its UI to the target device,
whether it has a single line VFD, a two line LCD, or is a TV with 24 lines of display space. In this mode, the
streaming module generates and sends the μC text strings to display, and then the μC displays the strings to the
user and sends user responses back the streaming module.
Mode 3: Custom UI
Your device can implement any arbitrary user interface you wish. To connect the user interface to the streaming
module, there is a rich set of control commands that allows you to browse and search all networked music libraries
and internet radio stations. Because the streaming module abstracts the complicated aspects of talking to different
server types, network drivers, protocol stacks, digital rights management and so on, you can concentrate on
building a unique UI with powerful digital music features.
Mode 4: Stand alone mode
In this mode there is no host processor. The streaming module is controlled entirely from the Ethernet or Wireless
interface using either Telnet or the built in web page.
Wi-Fi Media Streaming Modules
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Roku
assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. www.rokulabs.com © Roku 2005.
Command Summary
The following are examples of the types of commands that can be issued to the MB30x via the serial port. This list
is not exhaustive.
Command Name Summary
ListServers The MB30x automatically discovers many types of music servers
on a user’s Local Area Network, such as UPnP AV (like Microsoft’s
WMC), Rhapsody, MusicMatch, iTunes, and more. This command
returns the list of currently known servers in a format suitable for
display to a user.
ListSongs There are a number of commands for browsing the content of a
music server, including ListSongs, ListAlbums, ListArtists,
ListComposers, and ListGenres. The streaming module client can
select songs, albums, artists, etc., by name or by index, and can
even browse by a combination of filters, like songs by artist in a
particular genre.
ListInternetRadioPresets The streaming module stores a list of 15 of the user’s favorite
internet radio presets for easy access, and comes pre-populated
with popular radio stations. This command returns a list of friendly
names for each preset, suitable for display to the user. The user
can change their favorites by using their web browser or by using
an streaming module command (SetInternetRadioPreset).
SearchSongs On servers that support it, the streaming module can search for
content on a music server with the commands SearchSongs,
SearchArtists, SearchAlbums, SearchComposers, and SearchAll.
GetSongInfo The streaming module client can retrieve detailed song information,
as provided by the music server, including song title, artist, album,
genre, bit rate, file format, file size, and song length.
QueueAndPlay The usual way to start music playback, QueueAndPlay creates a
playlist from the current list of browsed or searched songs and
begins playback at the specified song index.
NowPlayingQueue NowPlayingQueue allows the user to add additional songs to the
current list of playing songs. (As opposed to QueueAndPlay, which
destroys the current playlist of songs before creating a new one,
NowPlayingQueue will add additional songs to the already existing
list.)
Play All simple transport actions are available as streaming module
commands such as Play, Pause, Next, Previous, Stop, Shuffle, and
Repeat. These commands affect playback of the current Now
Playing playlist.
SubscribeTransportUpdateEvents The streaming module client can subscribe to notifications of any
change in the transport state, to give the user instant feedback.
Transport states include Paused, Playing, Buffering, Resuming,
Stopped, PlaybackError, etc.
ListWiFiNetworks Returns a list of the names (SSIDs) of wireless networks detected
by the on-board Wi-Fi adapter.
ConnectSSID Sets the wireless network (SSID) to connect to.
SetWiFiPassword Sets the password for connection to a wireless network.
GetWiFiSignalStrength Gets the real-time signal strength of the wireless network the
streaming module is currently connected to.
Wi-Fi Media Streaming Modules
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Roku
assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. www.rokulabs.com © Roku 2005.
Module physical dimensions
4 inches by 2.8 inches
Pin out
30X2 2mm connector, suitable for soldering to your board connecting via a header.
pin Description pin Description
1 VCC (3.3V) 2 VCC (3.3V)
3 Ground 4 Ground
5 Ethernet TX+ 6 Ethernet TX-
7 Ground 8 Ethernet Center Tap
9 Ethernet RX+ 10 Ethernet RX-
11 Ground 12 Ground
13 IR Input (38KHz) 14 RS232 TX (3.3V)
15 RS232 RX (3.3V) 16 SPISS_L/PAR_ACK_L
17 SPI MOSI 18 SPI MISO
19 SPI CLK 20 PAR_RD_L/SPI_REQ_L
21 PAR_WR_L/SPI_ACK_L 22 ATTN_L
23 I2S/AC97 TXDATA 24 I2S/AC97 RXDATA
25 I2S/AC97 MCLK 26 I2S/AC97 BITCLK
27 External I2S/AC97 Clock 28 I2S/AC97 FRAME
29 3.3V Battery input for RTC 30 DAC_RST_L/ SPI DAC CS output
31 Ground 32 RESET_L input/output
33 VCC (3.3V) 34 VCC (3.3V)
35 LED0 (ETH 10/100) 36 PAR_D0
37 LED1 (ETH LINK/ACT) 38 PAR_D1
39 LED2 (WIFI LED1) 40 PAR_D2_PPD9
41 LED3 (WIFI LED2) 42 PAR_D3_PPD8
43 I2C_SCL 44 PAR_D4_PPD7
45 I2C_SDA 46 PAR_D5_PPD6
47 No Connect 48 PAR_D6_PPD5
49 Ground 50 PAR_D7_PPD4
51 Frame 52 PPD3
53 HSync 54 PPD2
55 VSync 56 PPD1
57 Ground 58 PPD0
59 PPCLK 60 Ground
PC/Mac Music Servers Supported:
1. Microsoft Windows Media Connect
2. Real Network’s Rhapsody
3. UPnP AV
4. Apple iTunes
5. Yahoo MusicMatch
6. WinAmp with TwonkyVision plug-in
7. SlimServer
8. mt-DAAP
Wi-Fi Media Streaming Modules
This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Roku
assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. www.rokulabs.com © Roku 2005.
RX/TX
RS232
IR
RJ45
IR Rec
Demod
DAC
SPDIF
I2S
/AC97
RS232
DB9
Debug
40 x 2 LCD
Front Panel
Buttons
SPI
I2C
PAR
uC
MB303
ITU-R 656
FLASH
Video
Encoder
S-VIDEO
& Comp.
ESB-EVAL Evaluation Board
The ESB-EVAL implements a complete network music player in only a few hundred lines of C code. Includes the
MB304 Network Music Module, microcontroller, LCD Display, IR receiver, and remote control. Schematics and ‘C’
source code included.
The module has been pre-screened at the FCC lab, in order to make it easier for you to get your product to market
faster.
The provided source code demonstrates the three streaming module usage modes: Mode 1: Internet Radio
Presets Only, Mode 2: Use built-in UI, and Mode 3: Custom UI.
Sales Information
For information contact: esb-sales@rokulabs.com
Part
Number
Network Type Price
100,000
per
year
Availability
MB301 Ethernet 10/100 May 05
MB302 Wi-Fi B May 05
MB303 Wi-Fi B + 10/100 May 05
MB304 Wi-Fi G June 05
MB305 Wi-Fi G + 10/100 June 05
ESB-EVAL Eval Board April 05
Revision date: 4/8/2005 4:20 PM
82-001925-01
a
ADMC401
DSP Motor Controller
Developer’s
Reference Manual
Revision 2.0
2 March 2000
ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
2
Table of Contents
1. INTRODUCTION..............................................................................................................................6
2. REFERENCED DOCUMENTS ........................................................................................................6
3. UPGRADE INFORMATION............................................................................................................7
4. GETTING STARTED .......................................................................................................................7
5. IMPORTANT SAFETY INFORMATION.......................................................................................7
6. SOFTWARE DEVELOPMENT........................................................................................................9
6.1 EVALUATION KIT SOFTWARE....................................................................................................... 11
6.2 GETTING STARTED WITH THE MOTION CONTROL DEBUGGER ........................................................ 12
6.2.1 Saving the Debugger Windows Configuration ..................................................................... 22
6.2.2 Modifying Your Program Directly From the Disassembly Window...................................... 23
6.2.3 Automatic Program Exit Function ...................................................................................... 23
6.2.4 Troubleshooting.................................................................................................................. 24
6.2.5 Error Messages .................................................................................................................. 24
6.3 PROGRAMMING SERIAL PROMS WITH MAKEPROM.................................................................... 26
6.4 USING INCLUDE FILES IN YOUR CODE........................................................................................... 27
7. ADMC401 HARDWARE OVERVIEW.......................................................................................... 28
7.1 MOTOR CONTROL PERIPHERAL REGISTERS................................................................................... 28
7.2 ADDRESS AND DATA BUS............................................................................................................. 28
8. MEMORY MAP.............................................................................................................................. 29
8.1 (MMAP = BMODE= 1 CONFIGURATION) ................................................................................... 29
8.2 (MMAP = BMODE= 0 CONFIGURATION) ................................................................................... 29
9. ON-CHIP ROM MONITOR OPERATION ................................................................................... 30
9.1 POWER-UP / RESET SEQUENCE ..................................................................................................... 30
9.2 SPORT1..................................................................................................................................... 30
9.3 THE ROM CODE MONITOR .......................................................................................................... 30
10. SOURCE CODE LIBRARY........................................................................................................ 35
11. BOOTING FROM EXTERNAL EPROM WITH MMAP=BMODE=0.................................... 36
12. INTERRUPT OPERATION........................................................................................................ 40
12.1 USING PUT_VECTOR................................................................................................................ 42
12.2 PERIPHERAL INTERRUPT CONSIDERATIONS ................................................................................... 42
13. WATCHDOG TIMER OPERATION......................................................................................... 43
14. SOFTWARE PERIPHERAL RESET FUNCTION.................................................................... 44
15. SROM/EEPROM RESET FUNCTION ...................................................................................... 44
16. TUTORIAL.................................................................................................................................. 45
16.1 EXAMPLE 1: SIMPLE CONFIGURATION EXAMPLE ........................................................................... 45
ADMC401 DSP Motor Controller
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
3
17. APPENDICES .............................................................................................................................. 47
Figures
Figure 1. The Software Development Process .............................................................................................9
Figure 2. Debugger Target Selection Dialog Box ...................................................................................... 12
Figure 3. Debugger Disassembly Window................................................................................................. 13
Figure 4. Loading an Executable File .................................................................................................... 14
Figure 5. Using the Find Text Window ..................................................................................................... 14
Figure 6. Finding Symbols in the Program................................................................................................ 15
Figure 7. Browsing the List of Symbols .................................................................................................... 15
Figure 8. The GoTo Address Box........................................................................................................... 16
Figure 9. Selecting Breaks from the Debug Menu................................................................................. 16
Figure 10. The Breaks Dialog Box ......................................................................................................... 16
Figure 11. Running the Program............................................................................................................ 17
Figure 12. Halting and Single-Stepping ................................................................................................. 18
Figure 13. Selecting a Register from the Registers Menu ..................................................................... 18
Figure 14. Viewing the PWM Registers................................................................................................. 19
Figure 15. Viewing the Program Memory (PM).................................................................................... 19
Figure 16. Selecting Format of Data Memory ....................................................................................... 20
Figure 17. Viewing the Memory Map .................................................................................................... 20
Figure 18. Dumping Memory ................................................................................................................. 20
Figure 19. Fill Memory........................................................................................................................... 21
Figure 20. Plot Memory Configuration Dialog ...................................................................................... 21
Figure 21. Plot Memory Output ............................................................................................................. 21
Figure 22. Motion Control Debugger Version........................................................................................... 22
Figure 23. Required Timing for Interfacing to an External Device............................................................ 32
Figure 24. Monitor Operation at Reset...................................................................................................... 34
Figure 25. Watchdog Timer Register ........................................................................................................ 43
Figure 26. Boot Load Timing (XC17128E, AT17C128, or 37LV128)....................................................... 57
Figure 27. UART Protocol........................................................................................................................ 60
ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
4
Tables
Table 1. Summary of Debugger HotKeys .................................................................................................. 22
Table 2. ADMC401 Evaluation Board Memory Map (MMAP = BMODE = 1 Configuration)................... 29
Table 3. Two Byte Sequence for each Monitor Supported Interface........................................................... 31
Table 4. Interrupt Vector Addresses by Priority ........................................................................................ 40
Table 5. SROM / EEPROM Pin Connections............................................................................................ 55
Table 6. SROM boot loader error codes. ................................................................................................... 56
Table 7. File Syntax For All Boot Load Interfaces..................................................................................... 58
Table 8. Available Commands (Debugger Interface)................................................................................. 62
Table 9. Data Memory Write Command ................................................................................................... 62
Table 10. Data Memory Read Command .................................................................................................. 62
Table 11. 16-Bit Program Memory Write Command................................................................................. 62
Table 12. 16-Bit Program Memory Read Command.................................................................................. 63
Table 13. 24-Bit Program Memory Write Command................................................................................. 63
Table 14. 24-Bit Program Memory Read Command.................................................................................. 63
Table 15. Monitor Variables for Executing User Code .............................................................................. 64
Table 16. DM Write Commands to Start Program at 0x0060 .................................................................... 64
ADMC401 DSP Motor Controller
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
5
Appendices
Appendix A. System Specification File..................................................................................................... 47
Appendix B. Architecture Description File ............................................................................................... 48
Appendix C. ADMC401 Include File (ADMC401.H) ............................................................................... 49
Appendix D. Constant Include File (Constant.h) ...................................................................................... 52
Appendix E. Macro Include File (Macro.h) .............................................................................................. 54
Appendix F. SROM/EEPROM Boot Loader Protocol................................................................................ 55
Appendix G. UART Boot Loader Protocol ................................................................................................ 59
Appendix H. UART Debugger Protocol .................................................................................................... 61
Appendix I. Synchronous Master Boot Load Protocol ............................................................................... 65
Appendix J. Synchronous Master Debugger Protocol ................................................................................ 66
Appendix K. Synchronous Slave Boot Loader Protocol ............................................................................. 67
Appendix L. Synchronous Slave Debugger Protocol ................................................................................. 68
ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
6
1. Introduction
The ADMC401 is a single chip DSP motor controller optimized for standalone motor control applications.
The device combines a 26MHz fixed point ADSP-2171 core with on-chip memory, two serial ports, a
programmable timer, and a set of on-chip motor control peripherals. In addition, the address and data bus
of the DSP core are connected to package leads allowing external memory and peripheral expansion.
Together with the list of referenced documents, this manual provides the information necessary to
understand and evaluate the processors’ architecture and to develop an ADMC401-based system.
2. Referenced Documents
Reference 1. ADMC401 Single Chip DSP Motor Controller Data Sheet, Analog Devices.
Reference 2. ADSP-2100 Family User’s Manual, Third Edition, 9/95, Analog Devices.
See “ADSP-2100 Family User’s Manual” on the Analog Devices web site at
http://www.analog.com/support/product_documentation/dsp_prdoc.html
Reference 3. ADSP-2100 Family Assembler Tools & Simulator Manual, Second Edition, 11/94,
Analog Devices.
See “ADSP-2100 Assembler Tools Manual” on the Analog Devices web site at
http://www.analog.com/support/product_documentation/dsp_prdoc.html
Reference 4. ADSP-2100 Family C Tools Manual, Second Edition, 11/94, Analog Devices.
See “ADSP-2100 C Tools Manual” on the Analog Devices web site at
http://www.analog.com/support/product_documentation/dsp_prdoc.html
Reference 5. Digital Signal Processing Applications using the ADSP-2100 Family, Volume 1,
Analog Devices, 1992.
See “Using the ADSP-2100 Family Volume 1” on the Analog Devices web site at
http://www.analog.com/support/product_documentation/dsp_prdoc.html
Reference 6 Visual DSP Debugger Guide & Reference, First Edition, July 6, 1998, Analog
Devices.
See “Visual DSP 6.0 Debugger Guide” on the Analog Devices web site at
http://www.analog.com/support/product_documentation/dsp_prdoc.html
ADMC401 DSP Motor Controller
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
7
3. Upgrade Information
Each evaluation kit is shipped with a software version that is fully functional for basic DSP development
operations such as assembling, linking, debugging, and serial PROM formatting. This version is powerful
enough to fill the needs of most users. Those who want to use the software simulator or write C code may
add the standard development software for the ADSP-2100 Family (part number ADDS-21XX-PC-1).
NOTE: While it is possible to use the C compiler to generate code for the 2171 based motor control DSPs,
the efficiency of this code is questionable. Due to the overhead needed by the C compiler, and the memory
constraints of the 2171 based motor control DSPs, C code development is not recommended by the Motion
Control Group. The C compiler does not come with direct support for the 2171 based motor control DSPs.
In addition to the features found in the software shipped with the evaluation kit the ADSP-2100 Family
Development Software adds:
· System Builder
Define your target system hardware in an architecture description file. The linker and the simulators
use this information to know how much memory is in your system, which memory is RAM and which
is ROM, which memory is internal to the processor and which is external, and what memory-mapped
peripherals you have. You don’t need this tool since the kit software includes an architecture
description file for the ADMC401. If you need to modify the file, you can do this simply by editing the
file and following the syntax contained therein. You should not need to modify the file unless you want
to create your own memory segments.
· Simulators
Run an instruction level simulation of any ADSP-2100 Family processor. All of the ADSP-2100
Family Simulators provide an interactive, instruction-level simulation, displaying the cycle-by-cycle
operation of different portions of the processor and system hardware through a window-based graphical
user interface. NOTE: The simulators model only 21xx family general purpose DSPs. None of the
motor control peripherals are modeled.
· Librarian, C Compiler, C Runtime Library, C Debugger
The C level software tools that come with the ADSP-2100 Family development software may be used to
develop user code but it is not recommended by the Motion Control Group (see the NOTE above).
4. Getting Started
Start by reading the release notes which accompany the evaluation kit you received. They describe what is
new in the latest release and how to install the development software on the disks that accompany each
board. In addition to the software development tools, documentation and demonstration software will also
be installed. Take the time to become familiar with the documentation so that you know where to find
information when needed. Also familiarize yourself with the documents referenced by this document.
Because the ADMC401 is a combination of an ADSP-2171 DSP core and a set of motor control peripherals,
needed technical information may be located in the ADSP-2100 Family User’s Manual, the ADMC401 data
sheet, application notes, or in this document.
5. Important Safety Information
The Motion Control Debugger should be used in a live system only with extreme caution. Your software
should first be developed with an ADMC401 evaluation kit or target board that is not connected to a motor.
ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
8
WARNING: PWM SIGNALS TO THE MOTOR REMAIN ACTIVE AT A BREAKPOINT!
If you want the motor shut down then use the HALT function to stop your program from executing. The
halt function performs a peripheral reset when halting your program. The halt function is executed by
selecting Halt from the Debug menu or by clicking the Halt button . DO NOT use breakpoints with a
live system because the PWM stage will remain active.
ADMC401 DSP Motor Controller
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
9
6. Software Development
Figure 1 shows the software development process that a user will follow to create an ADMC401 application.
The software tools used, shown in boxes in Figure 1, run on an IBM compatible PC. The System Builder,
Assembler, Linker, C Compiler, and PROM splitter, and MAKEPROM utility must be run in a DOS
window. The Motion Control Debugger and Simulator are invoked from Windows 95 or Windows NT.
Although ADMC401 specific information is contained in this document, the basic tool operations are
discussed in the references. The System Builder, Assembler, Linker, and PROM splitter are discussed in
Reference 3. The C Compiler is discussed in Reference 4. The Simulators are discussed in Reference 6. The
Motion Control Debugger is discussed in this document and in the latest version of its release notes. The
MAKEPROM utility is discussed in this document. The tools shown as optional are not needed by most
users and, therefore, are not included in the ADMC401 evaluation kit. They can be acquired by ordering
the standard development software for the ADSP-2100 Family (part number ADDS-21XX-PC-1). The
operation of this optional software is described in Italic font.
System
Architecture
File
System
Specification
File
System
Builder
C Source
Files
Linker
ANSI
C Compiler
Libraries
Executable
File
Assembler
Assembler
Source
Files
STEP 1:
Describe
Architecture
STEP 2:
Generate
Code
Software Simulator
ADMCxxx
Evaluation
Board
Motion Control
Debugger
Target Board
MAKEPROM
(SROM or EEPROM)
Motion Control
Debugger
STEP 3:
Debug
Software
STEP 4:
Final
Version for
Production
User File or Hardware Software Development Tool Hardware Development Tool
Optional Software Development Tool
PROM Splitter
Figure 1. The Software Development Process
ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
10
(Optional software) The software development process begins with the task of defining the target system
architecture. To do this you use the system builder. You must write a system specification file as input to
the system builder; this file describes the target hardware configuration and memory map. The system
builder reads the file and generates an architecture description file which passes this information to the
linker and simulator.
The above step may be skipped if you choose to use the ADMC401 architecture description file that is
installed when the development software is installed. The system specification file that was used to create
this architecture description file is also installed and can be used as a starting point for your own target
hardware. These files are also available in Appendix A and Appendix B. If you do not have the system
builder tool and wish to make a change to the .ach file you can edit it since it is a text file. Just mimic the
syntax observable within the file.
You begin code generation by creating assembly language source code modules. An assembly code module
is a unit of assembly language comprising a main program, subroutine, or data variable declarations.
Include files are provided in the appendices that contain things like ADMC401 specific constants and
macros that can be used in your code. These files can be included in source routines to provide a simple
interface to the ADMC401’s motor peripheral registers, and interrupt vector table addresses. These files are
also installed along with the development software and used in the tutorial given in this document. They
can be found in the main installation directory in a subdirectory called TgtFiles.
(Optional software) Each code module is assembled separately by the assembler into ADSP-2171 machine
code. Alternatively, the C compiler can be used to generate machine code from C source code.
The linker reads the target hardware information from the architecture description file to determine
placement of code and data fragments. In the assembly modules you may specify each code/data fragment
as completely relocatable, relocatable within a defined memory segment, or non-relocatable (placed at an
absolute address). Non-relocatable code or data modules are placed at the specified memory address,
provided the memory area has the correct attributes. Relocatable objects are placed in memory by the
linker.
Using the architecture description file and assembled code modules, the linker determines the placement of
relocatable code and data modules, and places all modules in memory locations with the correct attributes
(CODE or DATA, RAM or ROM). The linker generates a memory image file containing a single
executable program which may be loaded into a simulator, or downloaded to the evaluation kit or target
hardware, using the Motion Control Debugger, for testing.
(Optional software) The simulator provides windows that display different portions of the hardware
environment. To replicate the target hardware, the simulator configures its memory according to the
architecture description file. To simulate ADMC401 code you must use the ADSP-2101 simulator because
the ADSP-2171 simulator does not support the memory map of the ADMC401. ADMC401 peripherals are
not supported on any of the ADSP-21XX family simulators. You can configure the peripheral registers as
I/O ports on the simulator to verify that you are initializing them correctly, but you can’t view the
operation of the peripherals. For this reason it is recommended that you use the simulator only for basic
DSP core programming issues and that you use the ADMC401 evaluation kit with the Motion Control
Debugger for true application development.
The Motion Control Debugger allows you to download your executable file to an ADMC401 processor
board or your own target hardware, to debug your code, and to test your application directly over a standard
UART interface. Similar to the simulators, the debugger displays the hardware environment of the
ADMC401 through a series of windows. However, with the debugger you have full access to all of the
registers and memory on the ADMC401.
ADMC401 DSP Motor Controller
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
11
As Figure 1 shows, the software development process is an iterative one as you continue to debug and add to
your application code. Once your code is stable you have the option of programming a serial ROM or
EEPROM, or a byte-wide EPROM so that your code is boot loaded automatically to the ADMC401 on
power-up or reset.
The serial ROM boot load interface is provided by the on-chip ROM monitor program. To use this interface
you must format your executable file using the MAKEPROM utility which takes your executable file and
converts it into a PROM programmer compatible file that has the correct boot loader protocol. Use of the
MAKEPROM utility is discussed later in this document.
The byte-wide EPROM method of booting takes advantage of the built in boot memory interface of the
ADMC401 core. This interface is available when the BMODE and MMAP pins are tied low. To use this
interface you must format your executable file using the PROM splitter tool. Use of the PROM splitter is
discussed later in this document.
In addition to the methods of booting described above you also have the option of booting from an external
UART. This interface is also provided by the on-chip ROM monitor and is discussed later in this
document.
6.1 Evaluation Kit Software
If you have any older versions of the Motion Control Development Tools installed on your computer, you
must fully uninstall them before installing this version.
If you have any older versions of the Analog Devices 16 bit DSP development tools, such as ADSP 21XX,
or VDSP, it is strongly recommended that you upgrade to the latest VisualDSP tool set before installing the
Motion Control Development Tools.
Whether you are installing from CD-ROM or downloading from the WEB, the executable file,
SETUP.EXE, will install the development tools, applications notes, developer’s reference manual, and
example software onto your computer. You will be prompted for instructions during the installation.
If asked whether you want to install the 16 bit DSP tools, you should answer YES only if you have NOT
already installed some version of the Analog Devices 16 bit DSP development tools, such as VisualDSP.
If you answer YES, a subset of these tools (assembler, linker, librarian, and prom splitter) will be installed
onto your computer. If you already have these tools on your computer, then you should answer NO to this
prompt.
When prompted to select targets, select the ADMC401 and any other targets that you are installing at this
time.
After installation you will have a directory structure, similar to the following, added to your PC. This
example shows what the directory structure looks like if you choose the default directories.
Drive:\Program Files\Analog Devices\Motion Control Development Tools Main installation directory
The following subdirectories are contained in the main installation directory.
Documentation\ReleaseNotes Release notes (if applicable)
Documentation\ReferenceManuals Developer's reference and user manuals
Documentation\ApplicationNotes Application notes (if applicable)
Documentation\DataSheets Data sheets
Examples Demonstration/Evaluation software
Bin Debugger executables
TgtFiles Target specific files (.h, .ach,.sys)
SrcLib Source code for library functions
WindowFiles Saved windows configurations
Uninstall.isu Used to uninstall software
ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
12
21XX\Makeprom.exe Makeprom utility program
If you install the 16 bit tools, the files listed below will have been installed. In addition, your autoexec.bat
file will have been updated so that your PATH variable includes the directory: Drive:\Program
Files\AnalogDevices\Motion Control Debugger\21XX\
21XX\Spl21.exe ADSP-21XX Family Splitter
21XX\Asm21.exe ADSP-21XX Family Assembler
21XX\Ld21.exe ADSP-21XX Family Linker
21XX\Asmpp.exe ADSP-21XX Family Pre-Processor
21XX\Asm2.exe ADSP-21XX Family Assembler Driver
21XX\Lib21.exe ADSP-21XX Family Librarian
NOTE: For more example software and the latest documentation always consult the Analog Devices Motor
Control website at http://www.analog.com/motorcontrol
6.2 Getting Started with the Motion Control Debugger
The following steps will help you get started using the Motion Control Debugger. They can be performed
alone, or in conjunction with the tutorial in section 16.
The Debugger provides a toolbar, a menu, and several shortcut keys. Many of the steps listed below
describe two or three different ways of doing the same thing. This is not meant to confuse, but to allow you
to choose the method with which you are most accustomed.
Install the Motion Control Development Tools. Refer to the release notes that came with the installation
CD.
Connect the ADMC401 board to a communication port on your computer using a standard 9 pin male-tofemale
serial cable.
Apply power to the target board, and press the hardware-reset button.
Run the Debugger. To start the debugger under Windows 95/NT select it from the start menu (Programs->
ADI Motion Control -> Debugger). The Target Selection Dialog Box (Figure 2) will appear, displaying
default values for the communications port, baud rate, clock (crystal) frequency, target, and platform.
Figure 2. Debugger Target Selection Dialog Box
Create New Platform
Delete Platform
Platform
Name
ADMC401 DSP Motor Controller
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
13
Select a Target. Use the Debug_Target field to select the Debug Target that you wish to communicate
with. The Platform field enables you to save multiple configurations for the same target, by defining new
platforms, in case you have more than one evaluation board for the same chip. Select the COMM PORT
that is connected to the processor board, and select the desired BAUD RATE for the port. Select the
appropriate CLKIN RATE, and click OK. If you select CANCEL, you will exit the Debugger.
Attach to the Target. The Debugger will now attempt to attach to the target using the parameters you have
selected. When the Debugger has successfully attached to the target, the disassembly window (shown
below) will appear with the start location at 0x0060 highlighted. This is the point at which user code will
begin execution when a run or single step command is executed, so the beginning of your program must be
linked at 0x0060. You now have full emulation capability of your target design.
Figure 3. Debugger Disassembly Window
The greater-than sign (>) next to the address field of a code line represents the processor’s program counter
(PC) register. The program counter (PC) register points to the instruction that the processor is going to
execute next.
The processor status is shown at the bottom of the main window. The processor is currently in the state
“Reset”.
Program Counter
Processor Status
ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
14
Load a Program. A DSP program
may consist of program memory (PM)
blocks, data memory (DM) blocks, and
flash program memory (FM) blocks.
To load a program containing these
block types, select Load Program from
the File menu and navigate to the
directory containing your executable
file (.exe). Double click the desired
executable program and the debugger
will load the PM Blocks, DM Blocks,
and symbols.
Figure 4. Loading an Executable File
View the User Program. To view the program, use the page up, page down, up arrow, and down arrow
keys in the disassembly window. If the disassembly window hides behind another window, you can bring it
to the front by selecting Disassembly from the Window menu, or by clicking the Disassembly Window button
. To go back to displaying the current program counter (PC) address, press the F12 key.
Search for a Symbol. To find the line of
code where a symbol is defined, select
Find from the Search menu, or press Ctrl-
F, or click the Find button , and then
enter the symbol name.
Figure 5. Using the Find Text Window
ADMC401 DSP Motor Controller
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
15
The disassembly window will display the code where that symbol is defined or referenced, without
modifying the program counter (PC) register. To find the next occurrence of the symbol, select Find
Again from the Search menu, or press the F3 key, or click the Find Again button .
Go To a Symbol. To select from the list of all
symbols, and display the code where that symbol is
defined or referenced, select Go To from the Search
menu, or press Ctrl-G, or click the Go To button
, and then click the Browse button. Select the
symbol from the list displayed. The disassembly
window will display the code where that symbol is
defined or referenced without modifying the
program counter (PC) register.
Figure 6. Finding Symbols in the Program
Figure 7. Browsing the List of Symbols
ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
16
Go To an Address. To display the code at a particular
address, select Go To from the Search menu, or press
Ctrl-G, or click the Go To button , and then enter the
desired address. Hexadecimal numbers must be prefixed
with “0x”, and octal numbers with “0”. Decimal
numbers must be entered starting with the most
significant non-zero digit.
Display Additional Files.
To display a file in its own
window, select Open from
the File menu or click the
Open button , and then
navigate to the desired file.
Set a Breakpoint. To set a
breakpoint, select Breaks
from the Debug menu and
add the desired line of code
to the list displayed, or
click the Break button
while the desired line of
code is highlighted. If you
prefer a shortcut method,
double click the desired
line of code, or move the
cursor to the line and press
the F9 key.
Clear a Breakpoint. To clear a break point, select
Breaks from the Debug menu. Either delete the
desired line of code from the list, or click the Toggle
Break button with the line of code highlighted. If
you prefer a shortcut method, either double click the
line of code where the break point is set, or move
the cursor to the line and press the F9 key.
Clear All Breakpoints. To clear all break points,
select Breaks from the Debug menu and then select
Clear All and OK, or simply click the Clear Breaks
button .
Figure 8. The GoTo Address Box
Figure 9. Selecting Breaks from the Debug Menu
Figure 10. The Breaks Dialog Box
ADMC401 DSP Motor Controller
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
17
Run the Program. To run
your program, select Run from
the Debug menu, or press the
F5 key, or click on the Run
button . Observe the
processor status at the bottom
of the main window change
from “Reset” to “Running”.
WARNING! PWM SIGNALS TO THE MOTOR REMAIN ACTIVE AT A BREAKPOINT! If you want
the motor shut down then use the HALT function to stop your program from executing. The HALT function
performs a peripheral reset when halting your program. The HALT function is executed by selecting Halt
from the Debug menu or by clicking the Halt button . DO NOT use breakpoints with a live system, as
the PWM stage will remain active.
Figure 11. Running the Program
ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
18
Halt the Program. To halt a program while it is running, select Halt from the Debug menu, or press the F6
key, or click the Halt button . Observe the processor status at the bottom of the main window change
from “Running” to “Halted”. The disassembly window will display the location at which your code halted.
The greater-than sign signifies the location in the program counter (PC) register.
Single Step. To single step through your code, select Step Into from the Debug menu, or press the F11 key,
or click on the Single Step button . Observe the processor status change from “Halted” to “Stepping” to
“Halted” again.
Figure 12. Halting and Single-Stepping
Figure 13. Selecting a Register from the Registers Menu
ADMC401 DSP Motor Controller
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
19
View Registers. To view register values while debugging your code, select them from the Register
menu. Register values are updated each time the program is halted or a breakpoint is reached. Stacks
are also selected from the Register menu. Figure 14 shows an example of viewing the PWM registers.
For a more customized register
window, select Custom from the
Register menu. This allows you to
select the specific registers you
want to view and places them all in
the same window. Some targetspecific
registers are available only
from Custom selection.
View Memory. Viewing of
program or data memory
can be selected from the
Memory menu.
Clicking the right mouse
button while the cursor is in
a memory window will
bring up a menu that allows
you to change the format of
the data displayed. Figure
16 shows data memory
displayed in fractional
format, as the user is
selecting hexadecimal
format.
Figure 14. Viewing the PWM Registers
Figure 15. Viewing the Program Memory (PM)
ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
20
You can also select
tracking from this menu.
This allows you to track
the data pointed to by a
DAG or PC register.
View Memory Map. To see the memory map for the
target you are running select Memory Map from the
Memory menu.
Dump Memory. To dump memory to the output
window or to a file, select Dump from the Memory
menu and fill in the dialog box.
Figure 16. Selecting Format of Data Memory
Figure 17. Viewing the Memory Map
Figure 18. Dumping Memory
ADMC401 DSP Motor Controller
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
21
Fill Memory. To fill memory with a specified value,
select Fill from the Memory menu and fill in the dialog
box. Memory can also be filled from a file.
Plot Memory. To plot memory, select Plot from
the Memory menu and fill in the dialog box. The
plot will be displayed in its own window. Clicking
the right mouse button while the cursor is in a plot
window will bring up a menu that allows you to
configure the plot in different ways.
Software Reset. To execute a soft reset of the
processor, select Reset from the Debug menu, or
press the F7 key, or click the Reset button .
Observe the processor status change to “Reset”.
Restart. To restart your program,
select Reset from the Debug menu
and then Run.
Reload. To reload the most
recently loaded executable file,
select it from the most recently
loaded list found on the File menu.
Alternatively, you can press the F4
key. There are up to 4 files listed
on the most recently loaded list.
Pressing the F4 key will always
load the first file on that list.
Figure 19. Fill Memory
Figure 20. Plot Memory Configuration Dialog
Figure 21. Plot Memory Output
ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
22
Display Version. To display which version of the
Motion Control Debugger you have installed, select
About Debugger from the Help menu, or click the About
button .
Exit the Debugger. To exit the debugger, select Exit
from the File menu, or press the Ctrl-E key
combination.
NOTE: The reset and halt functions perform a peripheral reset which puts the peripheral blocks in their
power-up state (disabled). Loading an executable file will also perform a peripheral reset.
HotKey Function
F3 Find again
F4 Reload most recently loaded program
F5 Run
F6 Halt
F7 Software reset
F9 Toggle breakpoint
F11 Single step
F12 Update all windows
Ctrl-L Load program
Ctrl-O Open file
Ctrl-E Exit debugger
Ctrl-F Find
Ctrl-G Goto address or symbol
Table 1. Summary of Debugger HotKeys
6.2.1 Saving the Debugger Windows Configuration
The debugger will automatically save the current configuration of all open windows before it exits. The
next time you start the debugger the windows will be restored to the way you last left them. In addition, it is
possible to save multiple window configurations. For example, you could have one configuration that you
use to debug the PWM portion of your application, and another that you use to debug the ADC portion.
The debugger saves the windows configuration in a motion control window (.mcw) file. The default file
used is “default.mcw”. All window configuration files are saved in the WindowFiles directory found in the
main installation directory. To force a save of the current windows configuration select SaveWindows from
the File menu. The current windows configuration will be saved to the currently selected file. To save to a
different file select SaveWindowsAs from the File menu. This will change the currently selected file to this
new file you’ve chosen and then save the configuration. You can save multiple window configuration files
in the WindowFiles directory. To load a previously saved window configuration file select LoadWindows
from the File menu. The filename for the currently selected window configuration is saved in the registry
so it can be reloaded the next time the debugger is started.
Figure 22. Motion Control Debugger Version
ADMC401 DSP Motor Controller
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
23
NOTE: Do not remove or edit the currently selected .mcw file in the WindowFiles directory. If you do the
debugger might crash or you might receive a warning that the windows configuration file cannot be opened.
If this happens you must reinstall the debugger software. This will restore the default.mcw file.
Motion Control Windows files (.mcw) are not portable between versions of the debugger software. If you
upgrade to a new version of the debugger software you must recreate your windows configuration. Because
of this requirement the debugger software installation script will delete all .mcw files from the WindowFiles
directory and copy in the new default.mcw file.
6.2.2 Modifying Your Program Directly From the Disassembly Window
The disassembly window shows the contents of program memory in disassembled format. When you load
your program executable (.exe) file you will see it displayed in the disassembly window. The standard
method of changing your program is to edit the original source code and then assemble, link, and reload the
file with the debugger.
Alternatively, you can modify your program by typing assembly language directly into the disassembly
window. This can be extremely helpful for making quick changes while testing. For example, if you are
trying to find the correct value for a delay loop it is much quicker and easier to enter the new constant
directly into your program in the disassembly window and rerun the program rather than to recompile and
reload your code each time you want to try a new value. Once the correct value has been determined you
can enter it into your source code file. As another example, suppose you suspect a certain line of code
might be causing a bug in your program. You can quickly modify that line of code or enter a NOP in that
location and rerun the program. To reverse the changes you made simply reload your executable file using
the F4 key.
Remember that any changes you make in the disassembly window will be lost if you reset or power down
the processor, or if you load another program. It’s a good idea to keep your source files up to date with any
changes you want to keep. For a quick record of the changes you have made you can dump program
memory to a file. Select Assembly as the format and the file will contain the code in disassembled format
similar to the disassembly window.
When typing in the disassembly window you can use any symbols that are currently loaded. This means
you can call routines and load variables by name rather than address. You can also refer to any of the
memory mapped peripheral registers by name. You cannot refer to symbols directly until you have loaded a
program because that’s when the internal symbol table used by the debugger is created.
6.2.3 Automatic Program Exit Function
Typically, when the debugger runs a user’s DSP program the only way to pass control back to the debugger
is by hitting a breakpoint or by executing a Halt from the debugger. The user usually creates an infinite
loop in the program so that the DSP will continue to run until the Halt is executed.
As another option, you may insert an automatic exit back to the debugger by jumping to the Exit library
function. Exit.dsp performs the same DSP functions as the debugger’s Halt function so it’s effect is to
return control back to the debugger automatically when the user’s program has finished. You will see the
debugger halt when this happens. If you try to continue running the program it will just return back to the
debugger immediately. You can execute a reset or reload the program to run it again. To use the Exit
function, assemble and link the exit.dsp file (found in the SrcLib directory) with your code. You can then
insert a JUMP EXIT wherever you wish the program to return to the debugger.
ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
24
6.2.4 Troubleshooting
The following is a list of remedies to problems you may encounter when using the Motion Control
Debugger.
a. If the debugger is not responding, your target could be in run mode. Try selecting Halt from the
Debug pulldown menu.
b. If the debugger is hung, try resetting the target board. If the debugger is not responding, invoke the
‘Close Program’ dialog box by pressing Alt-Ctrl-Delete, select Debugapp, and click ‘End Task’.
Also, End any tasks called “Motion Control Debugger”. Next press Reset on the target board and
restart the debugger.
c. If the debugger hangs, you could be writing to a part of data memory that is being used by the
debugger. See the ADMC401 memory map in this document which shows the data memory
locations that are reserved by the monitor and make sure you are not using that memory. If you
created a .map file with the -x option when you linked your program, it will show you where your
program resides in memory.
d. The debugger uses the SPORT1 transmit and receive interrupts. Keep them enabled in your code
and do not modify the corresponding interrupt vectors at locations 0x0020 and 0x0024. Failure to
do this can cause the debugger to hang.
e. The debugger also uses locations 0x0001 and 0x0002 in the interrupt vector table. Do not modify
these locations, or the debugger will hang.
f. If the debugger frequently hangs, and your PC is located in an electrically noisy environment, try
lowering the baud rate. This can be done in the Target Selection Dialog Box, when you first start
the Debugger. Lowering the baud rate will slow down the debugger, but may alleviate the
problem.
6.2.5 Error Messages
The following is a list of error messages that may be encountered while running the debugger. Following
each error message is an explanation for the error and possible steps to take to correct the problem. If the
problem can not be fixed contact the Motion Control Group for help.
ERROR_MCG0001:: Com line status change or power failure
The debugger has detected a change in the serial communications. Exit the debugger. If the
debugger is not responding, invoke the ‘Close Program’ dialog box by pressing Alt-Ctrl-Delete,
select Debugapp, and click ‘End Task’. Reset the board, and then restart the debugger.
ERROR_MCG0002:: Target communication not established
The debugger is unable to communicate with the ROM Monitor Program. Exit the debugger. If
the debugger is not responding, invoke the ‘Close Program’ dialog box by pressing Alt-Ctrl-Delete,
select Debugapp, and click ‘End Task’. Check all connections, reset the board, and then restart the
debugger. If you have the debugger installed for multiple targets make sure you are running the
correct one. Also, make sure the clock frequency for the board is correct. The clock frequency is
displayed in the target selection box when you start the Motion Control Debugger.
ERROR_MCG0003:: Serial line status error. Check continuity of serial cable and connections.
The wrong com port could be connected to the target. The serial cable could be unconnected or
broken. A board connector could be broken. Exit the debugger. If the debugger is not responding,
invoke the ‘Close Program’ dialog box by pressing Alt-Ctrl-Delete, select Debugapp, and click
ADMC401 DSP Motor Controller
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
25
‘End Task’. Verify the connection, reconnect or fix the serial line and reset the board. Re-run the
debugger and verify the comm port selections in the target selection box.
ERROR_MCG0004:: Unable to open com port
The com port is being used by another application, or by a previous debugger session that hasn’t
`terminated properly. Exit all other applications that might be using the com port. Exit the
debugger. If the debugger is not responding, invoke the ‘Close Program’ dialog box by pressing
Alt-Ctrl-Delete, select Debugapp, and click ‘End Task’. If there are other occurrences of
Debugapp, exit them the same way. End any tasks with the name “Debugapp” or “…Motion
Control Debugger…”. Reset the board then restart the debugger.
ERROR_MCG0005:: Registry parameters not found
The registry has been corrupted. Uninstall, then Reinstall the development software on your PC.
ERROR_MCG0006:: Failed to open registry
The registry has been corrupted. Uninstall, then Reinstall the development software on your PC.
ERROR_MCG0007:: Detected a board reset or power failure.
You have performed a H/W reset of the board, or there was a power failure, while the debugger
was running. Acknowledge the error windows that pop up, then select Reset from the debug menu.
If the debugger is not responding, invoke the ‘Close Program’ dialog box by pressing Alt-Ctrl-
Delete, select Debugapp, and click ‘End Task’. Reset the board, then restart the debugger.
ERROR_MCG0008:: Error loading the monitor tasks
The development software might be corrupted. Try reinstalling the software on your PC.
ERROR_MCG0009:: Invalid target response
The debugger can’t reconnect with the ROM Monitor Program after running a user program.
Make sure you have the SPORT1 interrupts enabled in your code, you do not corrupt the SPORT1
interrupt vectors, and you do not corrupt any of the SPORT1 configuration registers.
ERROR_MCG0010:: Unable to read target memory while target is running
You’ve tried to access memory while your program is running. Halt the program and try again.
ERROR_MCG0011:: Unable to write to target memory while target is running
You’ve tried to access memory while your program is running. Halt the program and try again.
ERROR_MCG0012:: Unable to find the DSP monitor task files
The files might be corrupted. Reinstall the development software on your PC.
ERROR_MCG0013:: Target is running
Cannot perform operation while the target is running. Halt the target first.
ERROR_MCG0014:: Target communication not established after reset
The debugger is unable to communicate with the ROM monitor program. Exit the debugger. If
the debugger is not responding, invoke the ‘Close Program’ dialog box by pressing Alt-Ctrl-Delete,
select Debugapp, and click ‘End Task’. Reset the board, and then restart the debugger. If you
have the debugger installed for multiple targets make sure you are running the correct one.
ERROR_MCG0015:: Target communication Failure
The debugger is unable to communicate with the ROM Monitor Program using the parameters
specified in the target selection box which appears when you start the debugger.. Exit the
debugger. If the debugger is not responding, invoke the ‘Close Program’ dialog box by pressing
Alt-Ctrl-Delete, select Debugapp, and click ‘End Task’. Reset the board, and then restart the
ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
26
debugger. If the problem persists it could be due to noise or a hardware fault. Try lowering the
baud rate in the target selection box, which appears when you start the debugger.
ERROR_MCG0016:: Communications Failure.
The debugger cannot communicate with the target board. The most common cause of this is
failure to press the hardware reset button, or to cycle power on the target before starting the
debugger. Each time you start the debugger you must first reset the target. If you get an
“ERROR_MCG0003:: Serial line status error” prior to this error, then there is a problem with the
com port connection. The serial cable might be disconnected or you might be configured for the
wrong com port. Verify the communication parameters in the target selection box which appears
when you start the debugger.. Also, check the serial cable connection. This error can also occur if
the SPORT1 interrupts become unmasked in the IMASK register or if the SPORT1 interrupt
vectors at locations 0x20 and 0x24 are destroyed (for example if you load something at these
locations). This error can also occur if you accidentally reset the target while the debugger is
running. Another possible cause is noise on the serial line, which can happen when you run the
debugger in a fully loaded motor application.
The debugger can sometimes recover from this error. Try pressing the h/w reset button and then
clicking Retry. This combination may have to be performed several times to recover. If the
debugger is not responding, invoke the ‘Close Program’ dialog box by pressing Alt-Ctrl-Delete,
select Debugapp, and click ‘End Task’. Reset the target, and then restart the debugger.
ERROR_MCG0017:: The target never acknowledged the halt!
Possibly the SPORT1 interrupts were disabled by the user program.
When you issue a halt command to the debugger (click the Halt button), the debugger sends a halt
command to the target over the SPORT1 serial connection. In order for the target to receive this
command, the SPORT1 interrupts must be enabled and the SPORT1 received interrupt must be
serviced. Possibly your program masked the SPORT1 interrupts in the IMASK register. This is a
common problem. To run with the debugger your program must keep the SPORT1 interrupts
unmasked in the IMASK register (IMASK=6) and keep the SPORT1 interrupt vectors at locations
0x20 and 0x24 uncorrupted. If your program spends a lot of time in interrupt service routines, you
should add the line “IMASK=6” at the top of your interrupt service routine. This will override the
automatic setting of IMASK=0 that is done when a non-nested interrupt is serviced. This will
allow the debugger to halt the target in an interrupt service routine. Another possible cause of this
error may occur if your program spends so much time in higher priority interrupt service routines
that the SPORT1 receive interrupt is never serviced.
6.3 Programming Serial PROMs with MAKEPROM
By using the Makeprom utility and a standard PROM programmer, a user’s code may be programmed into
a serial PROM for boot loading the ADMC401 at reset. The Makeprom utility will convert an executable
file (.EXE) into a binary file (.DBS) for use with the PROM programmer. The binary file created is
automatically formatted to work with the boot loader of the ADMC401. The boot loading protocol is
compatible with the Xilinx XC17128E SROM, the Atmel AT17C128 EEPROM, and the Microchip
37LV128 EPROM. The Makeprom Utility (MAKEPROM.EXE) is installed with the Motion Control
Development Tools software. It runs from an MS-DOS window similar to the other development tools.
Follow these steps to create a serial device containing your executable image:
1. Your executable code must be linked to start executing at the beginning of user program memory
(0x0060), to which the boot loader will jump after loading the executable program. Consequently, you
are required to have a minimum of 1 block of code linked into program memory for the boot loader to
succeed. You are not required to have data linked into data memory. However, if this is the case, the
boot loader will automatically write 4 zeros at the start of data memory (0x3800). NOTE: Do not try
loading the interrupt vector table during a boot load. This would overwrite the default interrupt vector
ADMC401 DSP Motor Controller
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
27
table, which is needed by the boot loader. Instead you should modify the interrupt vector table from
within your program by using the library routine PUT_VECTOR. (See the putvctr.dsp file in the
SrcLib directory.
2. Run Makeprom which has the following syntax:
usage: Makeprom -i -t [-o ] [-c]
-i Input file
-t Target (e.g. ADMC401)
-o Output file (default = input_file.dbs)
-c Display checksums
-x Create text file. (default = binary)
-h Header disable. Suppresses SROM/EEPROM header
-m Mirror image disable. Data will be MSB…LSB.
3. Load the output file into your PROM programmer and select one of the devices listed above. The data
format of the file is absolute binary. NOTE: Make sure the polarity option is set to program an active
low reset ( RESET /OE).
4. Program the device and place it in the SROM/EEPROM socket of the processor or target board.
5. On power-up or reset, your executable code will be loaded at the start of user memory and executed.
6.4 Using Include Files in Your Code
Include files are useful for reusing code and data items that are shared between programs without having to
duplicate them in each program. The ADMC401 development software contains a number of include files
which can be used throughout your code. For example, the ADMC401.h file contains constants set equal to
the memory-mapped registers and interrupt vector table addresses. If you include this file you can refer to
the ADMC401 registers and interrupt vector table locations by name instead of by address. The code
snippet below illustrates how to use the ADMC401.h include file for setting up the PWMSYNC interrupt
vector table entry. PWMSYNC_INT_ADDR and PUT_VECTOR are constants defined in ADMC401.h.
#include ;
Initialize_Interrupts:
I4 = PWMSYNC_INT_ADDR;
MR0 = ^YOUR_PWMSYNC_ISR
CALL PUT_VECTOR;
IMPORTANT: The last line of an include file must contain a carriage return or subsequent include
statements will be ignored. Also, always use the #include directive instead of the .INCLUDE directive.
#include allows you to put precompiler directives in your include files while .INCLUDE doesn’t.
ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
28
7. ADMC401 Hardware Overview
The ADMC401 uses several ADSP-21XX family resources including: an ADSP-2171 core, 2K of on-chip
program RAM, 2K of on-chip program ROM, 1K of on-chip data RAM, two serial ports, and a
programmable timer. The operation of each of these units is described fully in Reference 2.
7.1 Motor Control Peripheral Registers
In addition to the ADSP-2171 core peripherals, the ADMC401 contains a set of motor control peripherals
that are controlled through registers that are memory-mapped into the core’s data memory. The operation
of the peripherals is described in Reference 1.
7.2 Address and Data Bus
The ADMC401 provides the 14-bit address bus and 24-bit data bus on external pins for memory and
peripheral expansion. See Reference 1 for details about this capability.
ADMC401 DSP Motor Controller
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
29
8. Memory Map
8.1 (MMAP = BMODE= 1 Configuration)
The following table shows the memory map for the ADMC401 evaluation board when the MMAP and
BMODE pins are both connected to a logic 1. This is the mode that enables the ROM monitor Programs
and thus allows use of the Motion Control Debugger, as well as programs to be boot loaded from serial
ROM or EEPROM. If you are booting the ADMC401 in any other mode other than MMAP = BMODE =
1, consult References 1 and 2 for proper operation.
There are a few memory restrictions when using the evaluation board in the MMAP = BMODE = 1
configuration. For proper operation of the Motion Control Debugger and SROM boot loader, never link
programs into the Data Memory RAM locations marked “Reserved by Monitor”. In addition, the debugger
uses locations 0x0001, 0x0002, 0x0020, and 0x0024 of the interrupt vector table. Do not modify these
locations when running with the debugger.
Program Memory
Address Range Memory Type Function
0x0000 - 0x005F Internal RAM Interrupt Vector Table
0x0060 - 0x07FF Internal RAM User Program Space
0x0800 - 0x0FFF ROM Monitor
0x1000 - 0x3FFF External RAM User Program Space
Data Memory
Address Range Memory Type Function
0x0000 - 0x1FFF External RAM User Data Space
0x2000 - 0x23FF Memory Mapped Peripheral Registers
0x2400 - 0x37FF External RAM User Data Space
0x3800 - 0x3B5F Internal RAM User Data Space
0x3B60 - 0x3BFF Internal RAM Reserved by Monitor
0x3C00 - 0x3FFF Memory Mapped DSP Core Registers
Table 2. ADMC401 Evaluation Board Memory Map (MMAP = BMODE = 1 Configuration)
8.2 (MMAP = BMODE= 0 Configuration)
When the MMAP and BMODE pins are tied low, the processor boots from an external EPROM using its
boot memory interface. In this mode the on-chip ROM is disabled, so there is no access to the monitor
program. The memory map when running in this mode is identical to that shown in Table 2, except that
there is no DM RAM reserved by the monitor, because the monitor is not running. In this mode the user
application has access to the entire PM and DM address space.
ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
30
9. On-Chip ROM Monitor Operation
The ADMC401 has a 2K ROM which contains a monitor program that supports boot loading and
debugging of user code. This monitor only operates when MMAP=BMODE=1. This section describes
the functions of the on-chip ROM monitor.
9.1 Power-up / Reset Sequence
When the MMAP and BMODE pins are tied to a logic 1, the on-chip ROM is enabled. A reset starts
execution of the monitor program at location 0x800.
9.2 SPORT1
The ADMC401 has two synchronous serial ports, SPORT0 and SPORT1, that support a variety of serial
data communication protocols. Both SPORTs are identical to the serial ports described in Reference 2
and so can be programmed by user code to support the timing and framing options described therein. In
addition, the ADMC401 contains added circuitry on SPORT1 that, when combined with software in the
ROM monitor, will emulate a UART. The monitor program contained in the ADMC401 ROM uses
SPORT1 as it’s interface to external devices for booting and debugging user code. After boot loading, a
user application can reconfigure SPORT1 for general serial port operation.
9.3 The ROM code Monitor
The monitor program's basic function is to do one of two things at reset:
1. Download and execute a user program. Four boot load protocols are supported:
· Synchronous EEPROM/SROM.
· Asynchronous UART (SCI compatible) with Autobaud feature.
· Synchronous Master (internal SCLK) with Autobaud feature.
· Synchronous Slave (external SCLK) with Autobaud feature.
2. Or, enter the debugger interface in which commands are received and processed from a host. There
are three protocols supported in this mode:
· Asynchronous UART (SCI compatible) with Autobaud feature.
· Synchronous Master (internal clock) with Autobaud feature.
· Synchronous Slave (external clock) with Autobaud feature.
The Analog Devices Motion Control Debugger uses the UART protocol to connect to the debugger
interface on the ADMC401.
Typically, an application is developed and debugged using the Motion Control Debugger. Once the
application is stable, it is programmed into serial ROM (SROM), EEPROM, or some other external device
and boot loaded to the ADMC401 on reset.
For users of the Motion Control Debugger to initially download and debug their programs, it is not
necessary to understand the UART protocol used because the communications between the debugger and
the ADMC401 are transparent to the user. Also, for users that will be programming the supported
SROMs or EEPROMs for boot loading their programs, it is not necessary to understand the synchronous
protocol used because the MAKEPROM utility will automatically format a user’s executable file into the
correct syntax for this protocol. But for those who want to boot load a program or use the debugger
interface from some other external device, the protocols listed above are further specified below and in the
appendices.
ADMC401 DSP Motor Controller
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
31
At startup the monitor first performs initialization and copies a default interrupt vector table to locations
0x0000 - 0x005F of program memory RAM. The section on interrupt operation in this document contains
information about how the ADMC401 processes interrupts and what is provided for a default interrupt
vector table by the ROM monitor. Following initialization, the monitor tries to boot load and execute a
user program from an SROM or EEPROM connected to SPORT1 through the DR1A pin. If successful,
execution of the user’s code then starts at location 0x0060. The SROM/EEPROM boot load interface is
discussed further in Appendix F.
If the monitor fails to detect an SROM or EEPROM on DR1A, it switches the input on SPORT1 to the
DR1B pin and waits to receive a two byte sequence from an external device. The two byte sequence tells
the monitor which protocol to use, at what baud rate, and whether it is to attempt a boot load or to run the
debugger interface. These two bytes are received asynchronously (no clock is required), MSB first.
The first byte in the sequence is called the autobaud byte. It is used to calculate the baud rate at which to
communicate with the external device. This is known as the autobaud feature. The external device must
send an autobaud byte equal to 0x70 at the desired baud rate. The ADMC401 will lock onto this baud rate
automatically and initialize SPORT1 to communicate at this rate. The maximum baud rate that the
ADMC401 can lock onto is 300 kHz for a 26 MHz CLKOUT.
The second byte in the sequence is called the header byte. It tells the monitor what type of interface it is
connected to. The protocols supported and their corresponding two byte sequence are listed in Table 3.
Autobaud Byte Header Byte Protocol
0x70 0x70 UART Debugger Interface
0x70 0x71 UART Boot Load (SCI compatible)
0x70 0x72 Synchronous Master Debugger Interface (Internal SCLK)
0x70 0x73 Synchronous Master Boot Load (Internal SCLK)
0x70 0x74 Synchronous Slave Debugger Interface (External SCLK)
0x70 0x75 Synchronous Slave Boot Load (External SCLK)
Table 3. Two Byte Sequence for each Monitor Supported Interface
Once the monitor has received the header byte it will configure SPORT1 for the correct protocol and then
will either execute the boot loader or the debugger interface depending upon which interface has been
selected.
The required timing from reset of the two byte sequence in order for an external device to connect to one
of the interfaces described in Table 3 is shown in Figure 23. The example shown is for the UART boot
load interface. All other interfaces are the same except the corresponding header byte, and the slave
interfaces would use an external SCLK. Note that this is not the same as the timing for the
SROM/EEPROM boot load interface which is shown in Appendix F.
ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
32
RESET pin
01110000 01110001 0101
2000
cycles
SCLK1
DR1B pin
(data from external device)
Required
timing
Allow SROM
boot to fall
Send
autobaud
byte
Allow monitor
to set
baud rate
Send header
byte
Allow monitor
to synch with
interface
Send rest
of data
0x70 0x71
#PM blocks, PM start
address, etc.
Monitor turns on SCLK
for SROM boot attempt
SROM boot attempt
times out
Monitor turns internal SCLk
on for UART boot load
cycles
CLKOUT
SCLK
10 x
cycles
CLKOUT
SCLK
10 x
cycles
CLKOUT
SCLK
10 x
cycles
CLKOUT
SCLK
10 x
Example Shown: UART Boot Load. Timing of the byte sequence is the same for all interfaces.
Figure 23. Required Timing for Interfacing to an External Device
The debugger interface provides full emulation-like capability of the ADMC401 without the use of a
separate emulator pod. Through a set of commands an external device can read and write the
ADMC401’s registers and memory, and can control the execution of code on the processor.
Each boot load interface allows a user’s program to be loaded and executed from an external device at
reset in much the same way as the SROM/EEPROM boot loader interface.
Detailed descriptions for each of the protocols described in this section can be found in Appendix G
through Appendix L.
The operation of the monitor at reset is summarized in the following flowchart.
ADMC401 DSP Motor Controller
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
33
A
RESET
Configure SPORT1 for SROM boot
SCLK1 = CLKOUT (1.0 MHz @ 26 MHz)
Reset SROM (toggles RFS1
Load program/data memory from SROM
Compute checksum on program and data
Compare checksum to that received from SROM
SROM Boot Load
SROM boot load
successful?
Valid Header Byte
Received?*
Run User Program
(Execution starts at 0x0060)
Output Error
Code on DT1**
No
Turn off SCLK1
Switch input to DR1B
Receive 2 Byte Autobaud Sequence
1st byte: Autobaud byte = 0x70
Calculate baud rate on 1st byte
2nd byte: Header byte
SROM boot load
times out?
No
Yes
No
Yes
* See Table 3.
** See Table 6 in Appendix F: SROM Boot Loader Error Codes.
B
Yes
ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
34
*- See Appendix H.
** - See Table 7
Figure 24. Monitor Operation at Reset
.
A
UART Debugger
Interface
Header Byte = 0x70 Header Byte = 0x71
UART Boot
Loader
Header Byte = 0x72
Synchronous Master
Debugger Interface
Header Byte = 0x73
Synchronous Master
Boot Loader
Header Byte = 0x74
Synchronous Slave
Debugger Interface
Header Byte = 0x75
Synchronous Slave
Boot Loader
SCLK1 on at 3 times
autobaud rate
SCLK1 on at 3 times
autobaud rate
SCLK1 on at
autobaud rate
SCLK1 on at
autobaud rate
SCLK1 is external SCLK1 is external
Monitor Serial
Communication Loop
Executed*
Monitor Serial
Communication Loop
Executed*
Monitor Serial
Communication Loop
Executed*
Load file through
SPORT1 configured
as UART. Use
load file syntax.**
Run User Program
at 0x0060
PM or DM
Checksum Failure?
B
Load file through
SPORT1 configured
as SPORT. Use
load file syntax.**
Run User Program
at 0x0060
PM or DM
Checksum Failure?
Load file through
SPORT1 configured
as SPORT. Use
load file syntax.**
Run User Program
at 0x0060
PM or DM
Checksum Failure?
Yes Yes Yes
No No No
Echoes Header Byte Echoes Header Byte
ADMC401 DSP Motor Controller
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
35
10. Source Code Library
The SrcLib directory, contained in the main installation directory of the Motion Control Development
Tools software, contains source code for a number of math and motor control functions that can be called
from user programs. Each library routine contains a commented header which describes the function as
well as the registers it uses. To use a library function, assemble and link the source code file (.dsp)
together with your program files and call the label, given in the .ENTRY directive at the top of the file,
from your program.
In addition to the source code being available in the SrcLib directory, the PUT_VECTOR routine, used to
insert vectors in the interrupt vector table, is also contained in the on-chip ROM. You can call
PUT_VECTOR by including the admc401.h file in the routine where the call is made. A constant is
declared in the .h file which contains the address of PUT_VECTOR in the ROM.
The PUT_VECTOR routine source code is provided in the SrcLib directory for those who wish to link and
call the routine from RAM.
NOTE: The files in this directory are provided for backward compatibility for users of the originally
released part who may already be using these routines. In many instances these files have been obsoleted
by new files, available on the web, and so are not supported. For all new users who want the latest library
routines, consult the application code page of the Analog Devices Motor Control website at
http://www.analog.com/motorcontrol.
ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
36
11. Booting from External EPROM with MMAP=BMODE=0
In addition to booting the ADMC401 using the interfaces provided by the on-chip ROM monitor program,
the ADMC401 may also be booted from an external byte-wide EPROM using its built-in boot memory
interface. To use the ADMC401 in this mode connect the MMAP and BMODE pins to a logic 0. This
disables the on-chip ROM and enables the built-in boot memory interface of the processor. When in this
mode up to 15K of program and/or data memory locations can be loaded from EPROM at reset.
Following the boot load procedure execution of the user program is automatically started at address
0x0000 in PM RAM.
A low cost byte-wide EPROM such as the 27C64 or 27C512 can be used in this mode. It is important to
note that because the on-chip ROM monitor is disabled in this mode, you do not have access to any of the
debug capabilities provided by the monitor such as the Motion Control Debugger. Therefore, use this
mode only as an alternative to the other booting methods, for boot loading final applications in an
embedded system.
To format your program into a file that can be burned into EPROM you use the PROM splitter tool. The
PROM splitter formats your program into the proper syntax for the boot memory interface, and creates a
file in the right format for burning into an EPROM.
To format your program invoke the PROM splitter with the following command:
SPL21 imagefile PROMfile -loader [-s] [-i]
where: imagefile is your executable file (the .EXE output from the linker)
PROMfile is the output file to be burned into the EPROM
The -loader switch enables multiple page boot loading. The -s and -i are optional file format switches
that create an output file in Motorola S record or Intel Hex record format respectively. If no switch is
given the default is Motorola S record.
Using the -loader switch causes the PROM splitter to scan the input .EXE file for external PM RAM
segments and internal or external DM RAM segments. It creates as many boot pages as necessary to store
the code and data, regardless of how many pages are declared in the system architecture file. In addition,
small loader routines are placed at the beginning of each page. After page 0 is booted, code and data
segments are copied by the page 0 loader routine to the appropriate destinations. Page 0 then forces a
software boot of page 1, whose loader performs the same operation. Successive boots continue until your
entire program is loaded, up to a maximum memory space of 15K locations.
The amount of program and data memory to be loaded from EPROM is limited in this mode to 15K total
locations, whether they be program memory or data memory. Although program memory is 3 bytes wide
and data memory is 2 bytes wide, they both occupy the same amount of space on the EPROM because
each location, whether it be PM or DM, is stored in 4 bytes on the EPROM. Therefore, the total memory
that can be booted in this mode is 64K / 4 - 1K = 15K locations. The 1K is for overhead created by the
loader routines.
NOTE: If you need to boot load more than 15K combined locations of PM and DM RAM you cannot use
this method of boot loading. Use one of the other methods of boot loading provided by the on-chip ROM
monitor (enabled by BMODE=MMAP=1).
The PROM splitter generates three output files PROMfile.bnu, PROMfile.bnm, and PROMfile.bnl. Of
these, however, only the PROMfile.bnm file is used in burning the EPROM.
ADMC401 DSP Motor Controller
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
37
IMPORTANT: In order for your program to boot successfully in this mode you must have an interrupt
vector table containing a JUMP to the start of your main program linked at location 0x0000 in the
.MODULE statement. You must also insert JUMPs to your interrupt service routines in the interrupt
vector locations for each interrupt you will be enabling. For all other interrupt vector locations an RTI
instruction can be inserted so that any unexpected interrupts will simply return rather than result in some
unexpected behavior. The following is an example interrupt vector table. As can be seen, the first location
is a jump to the beginning of the main program at label STARTUP, and interrupt vectors have been
created for the PWMSYNC and PWMTRIP interrupts.
{-------------------------------------------------------------}
.MODULE/RAM/ABS=0 interrupt_vector_table;
.EXTERNAL startup, pwmsync_isr, pwmtrip_isr;
.VAR/DM/RAM/SEG=USER_DM3 TEMP_I4_SAVE;
#include ;
ivt: JUMP startup;
{execution starts here at powerup/reset}
NOP;
NOP;
NOP;
DM(TEMP_I4_SAVE)=I4;
I4=DM(PICVECTOR);
JUMP (I4);
NOP;
RTI;
NOP;NOP;NOP;
RTI;
NOP;NOP;NOP;
RTI; {SPORT0 TRANSMIT}
NOP;NOP;NOP;
RTI; {SPORT0 RECEIVE}
NOP;NOP;NOP;
RTI; {Software Interrupt 1}
NOP;NOP;NOP;
NOP; {Software Interrupt 0}
RTI;NOP;NOP;
RTI; {SPORT1 TRANSMIT}
NOP;NOP;NOP;
RTI; {SPORT1 RECEIVE}
NOP;NOP;NOP;
RTI; {Timer}
NOP;NOP;NOP;
RTI; {Powerdown}
NOP;NOP;NOP;
ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
38
I4=DM(TEMP_I4_SAVE); {ADC end of conversion}
RTI; {insert vector here}
NOP;
NOP;
I4=DM(TEMP_I4_SAVE); {PWMSYNC}
jump PWMSYNC_ISR; {insert vector here}
NOP;
NOP;
I4=DM(TEMP_I4_SAVE); {EIU loop timer timeout}
RTI; {insert vector here}
NOP;
NOP;
I4=DM(TEMP_I4_SAVE); {PIO4 to PIO11}
RTI; {insert vector here}
NOP;
NOP;
I4=DM(TEMP_I4_SAVE); {EIU counter error}
RTI; {insert vector here}
NOP;
NOP;
I4=DM(TEMP_I4_SAVE); {ETU}
RTI; {insert vector here}
NOP;
NOP;
I4=DM(TEMP_I4_SAVE); {PIO 0}
RTI; {insert vector here}
NOP;
NOP;
I4=DM(TEMP_I4_SAVE); {PIO 1}
RTI; {insert vector here}
NOP;
NOP;
I4=DM(TEMP_I4_SAVE); {PIO 2}
RTI; {insert vector here}
NOP;
NOP;
I4=DM(TEMP_I4_SAVE); {PIO 3}
RTI; {insert vector here}
NOP;
NOP;
I4=DM(TEMP_I4_SAVE); {PWMTRIP}
jump PWMTRIP_ISR; {insert vector here}
NOP;
NOP;
{-------------------------------------------------------}
.ENDMOD;
ADMC401 DSP Motor Controller
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
39
The following is an example procedure for creating a bootable EPROM for the program Example1. The
ivt.dsp file contains the interrupt vector table shown above. The code contained in the example1.dsp file
is unimportant for this example. You can replace the example1.dsp program with your own program.
1. Assemble and link the Example1 program by executing the following commands at the DOS prompt.
asm21 ivt.dsp -2171 -l -dADMC401
asm21 example1.dsp -2171 -l -dADMC401
ld21 ivt example1 -a admc401 -g -e example1 -x example1
2. Invoke the PROM splitter by executing the following command at the DOS prompt.
spl21 example1 example1 -loader -i
3. Load the file example1.bnm that is created into your PROM programmer. Select a 27C512 device
and Intel Hex as the input format.
4. Program the EPROM.
5. Plug the EPROM into the EPROM socket on the ADMC401 evaluation board or on your own target
board. Make sure the MMAP and BMODE pins are tied low (via jumpers on the evaluation board).
6. Boot the program by powering on or resetting the ADMC401.
For more information on the PROM splitter see Reference 3.
ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
40
12. Interrupt Operation
Interrupts work as described for an ADSP-2171 core in Reference 2 with the following exceptions:
· Peripheral interrupts (Vector addresses 0x0030 - 0x0058) are internally wired to IRQ2
(vector at 0x0004). Software further determines which interrupt is activated and jumps to
the appropriate interrupt service routine.
The interrupt controller allows the processor core to respond to ten possible interrupts with minimum
overhead. The ADMC401 supports nine internal interrupts from the timer, the two serial ports, the
software interrupts, powerdown, and reset. The tenth interrupt, IRQ2 on the 2171 core, is actually wired
internally to the ADMC401 peripheral interrupt controller (PIC). This peripheral interrupt is generated
by any of the sources listed at addresses 0x0030 - 0x0058 in Table 4.
All interrupts are internally prioritized and individually maskable, except for the Powerdown interrupt
which is non-maskable. The interrupt vector addresses and priorities are shown in Table 4. (Interrupts
can be masked or unmasked with the IMASK register.) Individual interrupt requests are logically ANDed
with the bits in IMASK; the highest priority unmasked interrupt is then selected. Peripheral interrupts are
individually maskable in the same way with the PICMASK register. The ADMC401 masks all interrupts
for one instruction cycle following the execution of an instruction that modifies the IMASK register. This
does not affect autobuffering.
Interrupt Source Interrupt Vector Address
RESET Startup (or Power Up with
PUCR = 1)
0x0000 (Highest Priority)
1Peripheral Interrupt ( IRQ2 ) 0x0004
Power- Down (non-maskable) 0x002C
ADC End-of-Conversion 0x0030
PWMSYNC 0x0034
EIU Loop Timer Timeout 0x0038
PIO Interrupt (PIO4 to PIO11) 0x003C
EIU Counter Error 0x0040
Event Timer Unit Interrupt 0x0044
PIO0 Interrupt 0x0048
PIO1 Interrupt 0x004C
PIO2 Interrupt 0x0050
PIO3 Interrupt 0x0054
PWMTRIP Interrupt 0x0058
SPORT0 Transmit 0x0010
SPORT0 Receive 0x0014
Software Interrupt 1 0x0018
Software Interrupt 0 0x001C
SPORT1 Transmit or IRQ1 0x0020
SPORT1 Receive or IRQ0 0x0024
Timer 0x0028 (Lowest Priority)
1peripheral interrupt ( IRQ2 ) starts execution at 0x0004, from which it jumps to an interrupt
vector address from 0x0030 - 0x0058 as appropriate.
Table 4. Interrupt Vector Addresses by Priority
ADMC401 DSP Motor Controller
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
41
The interrupt control register, ICNTL, allows the external interrupts to be either edge or level-sensitive.
Since the IRQ2 line is a combination of all peripheral interrupt sources they will all be set to edge or
level-sensitive. The ICNTL register also allows interrupts to be processed sequentially or nested with
higher priority interrupts taking precedence. Since the peripheral interrupts are all on the same level
( IRQ2 ) they can only be nested by manually unmasking them with the IMASK and PICMASK registers
from inside the interrupt service routine.
The IFC register is a write-only register that is used to force and clear interrupts from software.
On-chip stacks preserve the processor status and are automatically maintained during interrupt handling.
The stacks are 12 levels deep to allow interrupt nesting. A set of shadow registers is provided for single
cycle context switching.
The following instructions allow global enabling or disabling of interrupts regardless of the state of
IMASK. Disabling the interrupts does not affect autobuffering.
ENA INTS;
DIS INTS;
When you reset the processor, interrupt servicing is disabled.
During initialization the ADMC401 monitor creates a default interrupt vector table at location 0.
Interrupt vector locations are spaced four locations apart which allows short interrupt service routines to
be coded in place, with no jump to the service routine required. For interrupt service routines with more
than four instructions, a jump (or vector) to the interrupt service routine must be placed at the interrupt
vector location. The PUT_VECTOR library routine can be used to perform this task. As a default,
interrupt vector locations that are not in use contain RTI instructions so that inadvertent activation of the
interrupt will only cause it to return and not to jump to some unknown instruction.
For peripheral interrupts the default code at location 0x0004 is slightly different, and so is shown below:
Location_0x0004: DM(I4_SAVE) = I4;
I4 = DM(PICVECTOR);
JUMP (I4);
And the peripheral interrupt locations that are entered by the JUMP (I4) statement contain the following
default code:
Location_0x0034: I4 = DM(I4_SAVE);
RTI;
Note that this default code restores I4 to its value before the interrupt. The user should replace the RTI
with a JUMP to their interrupt service routine. See the section “Using Put_Vector” for instructions on
how to place vectors to your routines in the interrupt vector table.
The default interrupt vector table contains code at locations 0x0001 and 0x0002 and at the SPORT1
transmit and receive interrupt vector locations (0x0020 and 0x0024) which is used when in debug mode to
talk to the Motion Control Debugger. These locations must not be changed when operating in this mode
or the debugger may crash. Also, the SPORT1 transmit and receive interrupts must be kept enabled by
your code in order to run it with the debugger.
ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
42
12.1 Using PUT_VECTOR
The PUT_VECTOR routine can be called to replace the default RTI in the interrupt vector table with a
JUMP to your interrupt service routine. PUT_VECTOR is contained in the ROM and can be called by
including the admc401.h file. If you wish to run PUT_VECTOR from RAM the source code is contained
in the SrcLib directory. The following example illustrates how to use PUT_VECTOR.
Given the following default interrupt vector table code for the PWMSYNC interrupt:
Location_0x0034: I4 = DM(I4_SAVE);
RTI;
the following call to PUT_VECTOR in your initialization code:
I4 = PWMSYNC_INT_ADDR;
MR0 = ^YOUR_PWMSYNC_ISR
CALL PUT_VECTOR;
would change the code at 0x0034 to:
Location_0x0034: I4 = DM(I4_SAVE);
JUMP YOUR_PWMSYNC_ISR;
In this example YOUR_PWMSYNC_ISR is the label at the start of your PWMSYNC interrupt service
routine. PWMSYNC_INT_ADDR is a constant equal to 0x0035 in the ADMC401.h file that you would
include in your code module.
12.2 Peripheral Interrupt Considerations
The user should be aware of the following considerations of peripheral interrupt operations:
· The PWMSYNC interrupt is detected on a low to high transition on the PWMSYNC pulse.
· The PWMTRIP interrupt is detected on a high to low transition on the PWMTRIP pin.
Additionally, each of the 12 PIO lines can be configured as a PWM trip source based on the settings
in the PIOPWM register. In this mode, a low-level transition on the PIO pin will cause a PWM trip
interrupt.
· At reset all PIO lines are configured as PWM trip sources (PIOPWM = 0xFFF). Because all PIO
lines are also configured as inputs and have internal pull-down resistors, any unconnected PIO lines
will cause a PWM trip. Therefore, prior to using the PWM unit, it is imperative that the PIO state be
correctly configured for the particular application. If no PIO lines are to be used as PWM trip
sources, the PIOPWM register must be cleared to zero prior to using the PWM unit.
· A PIO interrupt is detected based on the settings in the PIOLEVEL, PIOMODE, and PIOINTEN
registers. When a PIO interrupt is detected for PIO4 - PIO11, a flag bit is set in the PIOFLAG
register. The user’s interrupt service routine starting at 0x003C must read the PIOFLAG register to
determine which PIO pin is the source of the interrupt.
· PIO0 - PIO3 each have their own dedicated interrupt vector so the added PIOFLAG processing is not
required for these interrupts.
· Reading the PIOFLAG register clears all bits in the register so it’s up to the user’s code to save the
PIOFLAG value to allow later processing of any simultaneous PIO interrupts that may have occurred.
ADMC401 DSP Motor Controller
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
43
13. Watchdog Timer Operation
The watchdog timer is used to time critical control loops and to reset the peripherals and DSP if a loop
takes too long to complete. The watchdog timer is enabled by writing a value to the watchdog timer
register, WDTIMER, shown in Figure 25. A counter in the watchdog hardware counts down from this
value at the peripheral clock rate (CLKIN). If the DSP “hangs”, the counter will count down to zero and
the watchdog timer hardware will force a DSP and peripheral reset. Under normal operation a section of
DSP code at the end of the control loop would reset the counter to its initial value, preventing it from
reaching zero. Thus only under incorrect operation of the DSP would the watchdog timer trip.
Once the watchdog timer has been enabled, to prevent it from timing out, the user need only include the
following line of code at the end of the control loop:
DM(WDTIMER) = AX0;
The value in AX0 is irrelevant. Once the watchdog timer is enabled, rewriting to WDTIMER will reset
the timer to the original value that was written when the watchdog timer was initially enabled.
When a watchdog trip occurs and the peripheral block is reset, all peripheral registers are zeroed and thus
the PWM signals to the motor are shut down. The WDFLAG (bit 1 of the SYSSTAT register) is set when
a watchdog trip occurs. The DSP can read this flag during its boot up sequence to determine if the reset
came from a watchdog trip. The watchdog remains disabled while the WDFLAG is set. Writing a
nonzero value to the WDTIMER register will reset the WDFLAG bit and enable the watchdog timer.
Writing zero to the WDTIMER register will reset the WDFLAG bit and disable the watchdog timer.
The watchdog timer is disabled on power-up.
WDTIMER (W)
15 14 13 12 11 10 8 7 6 5 4 3 2 1 0
TIMEOUT (# of CLKINcycles)
9
DM(0x2018)
Figure 25. Watchdog Timer Register
ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
44
14. Software Peripheral Reset Function
A full reset of the peripherals can be performed from software by executing the following code:
PER_RST: SET FL2;
TOGGLE FL2;
TOGGLE FL2;
RTS;
This resets all peripheral registers to their power on state and turns off PWM signals to the motor. This
routine is available in the source code library.
15. SROM/EEPROM Reset Function
When UARTEN (bit 5 of the MODECTRL register) is set, the FL1 port of the DSP core is internally
connected to the external RFS1 pin. In this mode, this pin becomes an output and is intended to be used
to reset the external serial ROM device. This is accomplished by toggling the FL1 flag using the
following code segment:
SROMRESET: SET FL1;
TOGGLE FL1;
TOGGLE FL1;
RTS;
ADMC401 DSP Motor Controller
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
45
16. Tutorial
The following tutorial leads the user through a demonstration example on the ADMC401 evaluation kit.
For additional software examples and the latest updates consult the Analog Devices motor control website
at http://www.analog.com/motorcontrol.
The example source code files for this tutorial are installed during the Motion Control Development Tools
installation. The example is installed automatically into the subdirectory
Drive:\Progra~\Analog~1\Motion~1\Examples\ADMC401\Example1
· EXAMPLE1: This example sets up the PWM system of the
ADMC401 and produces constant duty cycle outputs on the
six PWM output pins. In addition, the lower three PWM
signals are chopped with a 1 MHz signal. No additional
hardware is required to run this example on the ADMC401
evaluation kit using the debugger. This file is a
good template from which it is possible to build more
complex programs.
16.1 Example 1: Simple Configuration Example
This demonstration example is located in the \Example1 subdirectory. It is a simple program that can be
used to validate the operation of the ADMC401 evaluation kit. It can also be used as a learning tool for
the Motion Control Debugger and as a template from which more complex programs can be developed.
The subdirectory contains the following files:
· example1.dsp Assembly language source code
· build.bat Batch file to assemble and link the example file to create
the executable module. The executable module can be loaded
using the debugger.
In addition, the following files are used from the Tgtfiles subdirectory:
· ADMC401.h Include file of device specific constant definitions
· ADMC401.ach Architecture file used by linker
This demo program may be summarized with the following pseudocode.
STARTUP: Initialize PWM registers for 10 kHz, 1us dead time,
1.5 us pulse deletion. Enable high frequency chopping
on the low-side PWM signals at 1.0 MHz and enable all
PWM outputs. Use PUT_VECTOR routine to place jumps in
the interrupt vector table to the appropriate routines
for both the PWMSYNC and PWMTRIP interrupts.
Enable both PWMSYNC and PWMTRIP interrupts by
writing to the PICMASK register of the ADMC401. Clear
any pending interrupts, disable interrupt nesting and
set level sensitivity using IFC and ICNTL registers.
Enable peripheral interrupt ( IRQ2 ) on ADMC401 using
IMASK register.
MAINLOOP: Do nothing. Wait for either PWMSYNC or PWMTRIP
interrupt.
ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
46
PWMSYNC_ISR: At each PWMSYNC interrupt, execute this code. In this
example, the three PWM registers PWMCHA, PWMCHB and
PWMCHC are written with constant values.
PWMTRIP_ISR: At each PWMTRIP interrupt, execute this code. In
this example, do nothing.
Running the batch file build.bat will create some additional files. These include the object file (.obj), the
code file (.cde) and the initialization file (.int) created by the assembler and the map listing file (.map),
the symbol table file (.sym) and the executable file (.exe) created by the linker. The executable file
EXAMPLE1.EXE can be run on the evaluation kit using the debugger. See the section “Getting Started
with the Motion Control Debugger” for instructions on how to load and run the program.
ADMC401 DSP Motor Controller Appendix A. System Specification File
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
47
17. Appendices
Appendix A. System Specification File
{ For the ADMC401 the following line must be ADSP2101 when you run the System Builder. Then you
must edit the .ACH file that is generated and change the target to ADSP2171. The System Builder won't
take a target of ADSP2171 in this case because for the ADMC401 data RAM has been modified to start at
location 0x3800 instead of 0x3000 as for the basic 2171 core. }
.ADSP2101;
.MMAP0;
{ User Program Memory Area }
.SEG/PM/RAM/ABS=H#0/CODE/DATA VECTOR[96];
.SEG/PM/RAM/ABS=H#60/CODE/DATA USER_PM1[1952];
.SEG/PM/RAM/ABS=H#1000/CODE/DATA USER_PM2[12288];
{ ROM Code Program Memory Area }
.SEG/PM/ROM/ABS=H#800/CODE ROMCODE[2048];
{ User Data Memory Area }
.SEG/DM/RAM/ABS=H#0000/DATA USER_DM1[8192];
.SEG/DM/RAM/ABS=H#2400/DATA USER_DM2[3072]; {hole at 0x3000-0x37FF on
eval board}
.SEG/DM/RAM/ABS=H#3800/DATA USER_DM3[864];
.SEG/DM/RAM/ABS=H#3B60/DATA ROMDATA[160]; {never put data here,
monitor reserved}
.ENDSYS;
Appendix B. Architecture Description File ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
48
Appendix B. Architecture Description File
$ADMC401
$ADSP2171
$MMAP0
$0000 005F paxVECTOR t
$0060 07FF paxUSER_PM1 t
$1000 3FFF paxUSER_PM2 t
$0800 0FFF pomROMCODE t
$0000 1FFF dadUSER_DM1 t
$2400 2FFF dadUSER_DM2 t
$3800 3BFF dadUSER_DM3 t
$
ADMC401 DSP Motor Controller Appendix C. ADMC401 Include File (ADMC401.H)
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
49
Appendix C. ADMC401 Include File (ADMC401.H)
#ifndef ADMC401_INCLUDE
#define ADMC401_INCLUDE
{
This include file defines important ADMC401 addresses. The names
defined below can be used in user programs by "including" this file.
This file defines:
- names for the peripheral registers of the ADMC401
- names for the memory mapped core registers of the ADMC401
- interrupt vector table addresses
}
{ peripheral registers of the ADMC401 }
.CONST PWMTM = 0x2008; {PWM timer register}
.CONST PWMDT = 0x2009; {PWM dead time register}
.CONST PWMPD = 0x200A; {PWM pulse deletion}
.CONST PWMGATE = 0x200B; {PWM gate register}
.CONST PWMCHA = 0x200C; {PWM channel A register}
.CONST PWMCHB = 0x200D; {PWM channel B register}
.CONST PWMCHC = 0x200E; {PWM channel C register}
.CONST PWMSEG = 0x200F; {PWM segment selection}
.CONST AUXCH0 = 0x2010; {Auxiliary PWM channel 0 duty cycle}
.CONST AUXCH1 = 0x2011; {Auxiliary PWM channel 1 duty cycle}
.CONST AUXTM0 = 0x2012; {Auxiliary PWM channel 0 period}
.CONST AUXTM1 = 0x2013; {Auxiliary PWM channel 1 period}
.CONST MODECTRL = 0x2015; {MODE control register}
.CONST SYSSTAT = 0x2016; {System status register}
.CONST WDTIMER = 0x2018; {Watchdog timer register}
.CONST PICVECTOR = 0x201C; {ISR address }
.CONST PICMASK = 0x201D; {IRD mask register }
.CONST EIUCNT = 0x2020; {Encoder count register }
.CONST EIUMAXCNT = 0x2021; {Encoder max count register }
.CONST EIUSTAT = 0x2022; {Encoder status register }
.CONST EIUCTRL = 0x2023; {Encoder control register }
.CONST EIUPERIOD = 0x2024; {Encoder loop timer period register}
.CONST EIUSCALE = 0x2025; {Encoder loop timer scale register}
.CONST EIUTIMER = 0x2026; {Encoder loop timer}
.CONST EETCNT = 0x2027; {Latched value of EIUCNT register}
.CONST EIUFILTER = 0x2028; {EIU filter control register}
.CONST EIZLATCH = 0x2029; {EIZ latch register}
.CONST EISLATCH = 0x202A; {EIS latch register}
.CONST ADC0 = 0x2030; {ADC0 register }
.CONST ADC1 = 0x2031; {ADC1 register }
.CONST ADC2 = 0x2032; {ADC2 register }
.CONST ADC3 = 0x2033; {ADC3 register }
.CONST ADC4 = 0x2034; {ADC4 register }
.CONST ADC5 = 0x2035; {ADC5 register }
.CONST ADC6 = 0x2036; {ADC6 register }
.CONST ADC7 = 0x2037; {ADC7 register }
.CONST ADCCTRL = 0x2038; {ADC control register }
.CONST ADCSTAT = 0x2039; {ADC status register }
.CONST ADCXTRA = 0x203B; {extra ADC data register }
.CONST ADCOTR = 0x203C; {ADC out of range register }
.CONST PIOLEVEL = 0x2040; {PIO level control register }
.CONST PIOMODE = 0x2041; {PIO mode control register }
Appendix C. ADMC401 Include File (ADMC401.H) ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
50
.CONST PIOPWM = 0x2042; {PIO PWMTRIP control register }
.CONST PIODIR = 0x2044; {PIO direction register }
.CONST PIODATA = 0x2045; {PIO data register}
.CONST PIOINTEN = 0x2046; {PIO interrupt enable register }
.CONST PIOFLAG = 0x2047; {PIO interrupt flag register }
.CONST ETUA0 = 0x2050; {ETU0 Event A capture register }
.CONST ETUB0 = 0x2051; {ETU0 Event B capture register }
.CONST ETUAA0 = 0x2052; {ETU0 Event AA capture register }
.CONST ETUA1 = 0x2053; {ETU1 Event A capture register}
.CONST ETUB1 = 0x2054; {ETU1 Event B capture register}
.CONST ETUAA1 = 0x2055; {ETU1 Event AA capture register}
.CONST ETUTIME = 0x2056; {ETU timer value}
.CONST ETUCONFIG = 0x205C; {ETU configuration register }
.CONST ETUDIVIDE = 0x205D; {ETU clock divide register }
.CONST ETUSTAT = 0x205E; {ETU status register }
.CONST ETUCTRL = 0x205F; {ETU control register }
.CONST PWMSYNCWT = 0x2060; {PWMSYNC width register}
.CONST PWMSWT = 0x2061; {PWM software trip register}
.CONST EETN = 0x2070; {EET pulse decimator register }
.CONST EETDIV = 0x2071; {EET timer decimator register }
.CONST EETDELTAT = 0x2072; {EET delta timer register }
.CONST EETT = 0x2073; {EET timer period register }
.CONST EETSTAT = 0x2074; {EET overflow status register }
{ memory mapped core registers of the ADMC401 }
.CONST SYSCNTL = 0x3fff;
.CONST MEMWAIT = 0x3ffe;
.CONST TPERIOD = 0x3ffd;
.CONST TCOUNT = 0x3ffc;
.CONST TSCALE = 0x3ffb;
.CONST Sport0_Rx_Words1 = 0x3ffa;
.CONST Sport0_Rx_Words0 = 0x3ff9;
.CONST Sport0_Tx_Words1 = 0x3ff8;
.CONST Sport0_Tx_Words0 = 0x3ff7;
.CONST Sport0_Ctrl_Reg = 0x3ff6;
.CONST Sport0_Sclkdiv = 0x3ff5;
.CONST Sport0_Rfsdiv = 0x3ff4;
.CONST Sport0_Autobuf_Ctrl = 0x3ff3;
.CONST Sport1_Ctrl_Reg = 0x3ff2;
.CONST Sport1_Sclkdiv = 0x3ff1;
.CONST Sport1_Rfsdiv = 0x3ff0;
.CONST Sport1_Autobuf_Ctrl = 0x3fef;
{ interrupt vector table addresses for ADMC401 }
.CONST ADC_INT_ADDR = 0x30+1; {ADC INTERRUPT }
.CONST PWMSYNC_INT_ADDR = 0x34+1; {PWMSYNC interrupt }
.CONST EIUTIMER_INT_ADDR = 0x38+1; {EIU timer interrupt }
.CONST PIO_INT_ADDR = 0x3C+1; {PIO4 - PIO11 interrupt }
.CONST EIUERROR_INT_ADDR = 0x40+1; {EIU error interrupt }
.CONST ETU_INT_ADDR = 0x44+1; {ETU interrupt }
.CONST PIO0_INT_ADDR = 0x48+1; {PIO0 interrupt }
.CONST PIO1_INT_ADDR = 0x4C+1; {PIO1 interrupt }
.CONST PIO2_INT_ADDR = 0x50+1; {PIO2 interrupt }
.CONST PIO3_INT_ADDR = 0x54+1; {PIO3 interrupt }
.CONST PWMTRIP_INT_ADDR = 0x58+1; {PWMTRIP interrupt}
.CONST TX0_INT_ADDR = 0x10; {SPORT0 transmit interrupt}
.CONST RX0_INT_ADDR = 0x14; {SPORT0 receive interrupt}
.CONST SW1_INT_ADDR = 0x18; {software interrupt 1}
ADMC401 DSP Motor Controller Appendix C. ADMC401 Include File (ADMC401.H)
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
51
.CONST SW0_INT_ADDR = 0x1C+1; {software interrupt 0}
.CONST TX1_INT_ADDR = 0x20; {SPORT1 transmit interrupt}
.CONST RX1_INT_ADDR = 0x24; {SPORT1 receive interrupt}
.CONST TIMER_INT_ADDR = 0x28; {Timer interrupt}
{ ROM addresses }
.CONST PUT_VECTOR = 0x0D8E; {PUT_VECTOR routine in ROM}
.CONST HALT_FLAG = 0x3B68; {used by exit library
function}
.CONST IDE_SP = 0x0C9E; {used by exit library function}
#endif
Appendix D. Constant Include File (Constant.h) ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
52
Appendix D. Constant Include File (Constant.h)
{This include file contains many useful constants. To use include the file in the
module where you want to use the constants. Then refer to the constants by the names
given below in your code.
VERSION # 1.2 08/07/97
Name Date Description
---- -------- -----------
MOD/HISTORY: Correction made to some constants P.Kettle 1/15/98
CALLED BY:
}
#ifndef CONSTANT_INCLUDE
#define CONSTANT_INCLUDE
.CONST OnePiOverTwo = 0x4000; { Hex equivalent of 1pi/2 }
.CONST OnePiOverFour = 0x2000; { Hex equivalent of 1pi/4 }
.CONST OnePiOverTwelve = 0x0AAA; { Hex equivalent of 1pi/12 }
.CONST OnePiOverThree = 0x2AAA; { Hex equivalent of 1pi/3 }
.CONST PiOverTwo = 0x4000; { Hex equivalent of pi/2 }
.CONST PiOverFour = 0x2000; { Hex equivalent of pi/4 }
.CONST PiOverTwelve = 0x0AAA; { Hex equivalent of pi/12 }
.CONST PiOverThree = 0x2AAA; { Hex equivalent of pi/3 }
.CONST TwoPiOverThree = 0x5555; { Hex equivalent of 2pi/3 }
.CONST ThreePiOverThree = 0x7FFF; { Hex equivalent of 3pi/3 }
.CONST FourPiOverThree = 0xAAAA; { Hex equivalent of 4pi/3 }
.CONST FivePiOverThree = 0xD555;{ Hex equivalent of 5pi/3 }
.CONST NOnePiOverThree = -OnePiOverThree-1; { Hex equivalent of -1pi/3 }
.CONST NTwoPiOverThree = -TwoPiOverThree-1; { Hex equivalent of -2pi/3 }
.CONST NThreePiOverThree = -ThreePiOverThree-1; { Hex equivalent of -2pi/3 }
.CONST HALF = 0x4000;
.CONST OnePiOverSix = 0x1555; { Hex equivalent of 1pi/6 }
.CONST PiOverSix = 0x1555; { Hex equivalent of pi/6 }
.CONST TwoPiOverSix = 0x2AAA; { Hex equivalent of 2pi/6 }
.CONST ThreePiOverSix = 0x4000; { Hex equivalent of 3pi/6 }
.CONST FourPiOverSix = 0x5555; { Hex equivalent of 4pi/6 }
.CONST FivePiOverSix = 0x6AAA; { Hex equivalent of 5pi/6 }
.CONST SixPiOverSix = 0x7FFF; { Hex equivalent of 6pi/6 }
.CONST SevenPiOverSix = 0x9555; { Hex equivalent of 7pi/6 }
.CONST EightPiOverSix = 0xAAAA; { Hex equivalent of 8pi/6 }
.CONST NinePiOverSix = 0xC000;{ Hex equivalent of 9pi/6 }
.CONST TenPiOverSix = 0xD555;{ Hex equivalent of 10pi/6}
.CONST ElevenPiOverSix = 0xEAAA; { Hex equivalent of 11pi/6}
.CONST TwelvePiOverSix = 0xFFFF;{ Hex equivalent of 12pi/6}
.CONST Pi = 0x7FFF; { Hex equivalent of pi }
.CONST NPi = 0x8000; { Hex equivalent of -pi }
.CONST Zero = 0x0;
.CONST NULL = 0x0;
.CONST TwoPiOverTwelve = 2*PiOverTwelve;{ Hex equivalent of 2pi/12}
.CONST ThreePiOverTwelve = 3*PiOverTwelve;{ Hex equivalent of 3pi/12}
.CONST FourPiOverTwelve = 4*PiOverTwelve;{ Hex equivalent of 4pi/12}
.CONST FivePiOverTwelve = 5*PiOverTwelve;{ Hex equivalent of 5pi/12}
ADMC401 DSP Motor Controller Appendix D. Constant Include File (Constant.h)
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
53
.CONST SixPiOverTwelve = 6*PiOverTwelve; { Hex equivalent of 6pi/12}
.CONST SevenPiOverTwelve = 7*PiOverTwelve; { Hex equivalent of 7pi/12}
.CONST EightPiOverTwelve = 8*PiOverTwelve; { Hex equivalent of 8pi/12}
.CONST NinePiOverTwelve = 9*PiOverTwelve; { Hex equivalent of 9pi/12}
.CONST TenPiOverTwelve = 10*PiOverTwelve; { Hex equivalent of 10pi/12}
.CONST ElevenPiOverTwelve = 11*PiOverTwelve; { Hex equivalent of 11pi/12}
.CONST TwelvePiOverTwelve = 12*PiOverTwelve; { Hex equivalent of 12pi/12}
.CONST ThirteenPiOverTwelve = 13*PiOverTwelve; { Hex equivalent of 13pi/12}
.CONST FourteenPiOverTwelve = 14*PiOverTwelve; { Hex equivalent of 14pi/12}
.CONST FifteenPiOverTwelve = 15*PiOverTwelve; { Hex equivalent of 15pi/12}
.CONST SixteenPiOverTwelve = 16*PiOverTwelve; { Hex equivalent of 16pi/12}
.CONST SeventeenPiOverTwelve = 17*PiOverTwelve; { Hex equivalent of 17pi/12}
.CONST EighteenPiOverTwelve = 18*PiOverTwelve; { Hex equivalent of 18pi/12}
.CONST NineteenPiOverTwelve = 19*PiOverTwelve; { Hex equivalent of 19pi/12}
.CONST NOnePiOverTwelve = -1*0x0AAA; { Hex equivalent of 1pi/12}
.CONST NTwoPiOverTwelve = -2*PiOverTwelve; { Hex equivalent of 2pi/12}
.CONST NThreePiOverTwelve = -3*PiOverTwelve; { Hex equivalent of 3pi/12}
.CONST NFourPiOverTwelve = -4*PiOverTwelve; { Hex equivalent of 4pi/12}
.CONST NFivePiOverTwelve = -5*PiOverTwelve; { Hex equivalent of 5pi/12}
.CONST NSixPiOverTwelve = -6*PiOverTwelve; { Hex equivalent of 6pi/12}
.CONST NSevenPiOverTwelve = -7*PiOverTwelve; { Hex equivalent of 7pi/12}
.CONST NEightPiOverTwelve = -8*PiOverTwelve; { Hex equivalent of 8pi/12}
.CONST NNinePiOverTwelve = -9*PiOverTwelve; { Hex equivalent of 9pi/12}
.CONST NTenPiOverTwelve = -10*PiOverTwelve; { Hex equivalent of 10pi/12}
.CONST NElevenPiOverTwelve = -11*PiOverTwelve; { Hex equivalent of 11pi/12}
.CONST NTwelvePiOverTwelve = -12*PiOverTwelve; { Hex equivalent of 12pi/12}
.CONST NThirteenPiOverTwelve = -13*PiOverTwelve; { Hex equivalent of 13pi/12}
.CONST NFourteenPiOverTwelve = -14*PiOverTwelve; { Hex equivalent of 14pi/12}
.CONST NFifteenPiOverTwelve = -15*PiOverTwelve; { Hex equivalent of 15pi/12}
.CONST NSixteenPiOverTwelve = -16*PiOverTwelve; { Hex equivalent of 16pi/12}
.CONST NSeventeenPiOverTwelve = -17*PiOverTwelve; { Hex equivalent of 17pi/12}
.CONST NEighteenPiOverTwelve = -18*PiOverTwelve; { Hex equivalent of 18pi/12}
.CONST NNineteenPiOverTwelve = -19*PiOverTwelve; { Hex equivalent of 19pi/12}
#endif
Appendix E. Macro Include File (Macro.h) ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
54
Appendix E. Macro Include File (Macro.h)
{VERSION # 1.008/07/97
Name Date Description
---- -------- -----------
MOD/HISTORY: none
CALLED BY:
}
#ifndef MACRO_INCLUDE
#define MACRO_INCLUDE
.MACRO Write_dm(%0,%1);
ar=%1;
dm(%0)=ar;
.ENDMACRO;
.MACRO Copy_dm(%0,%1);
ar=dm(%0);
dm(%1)=ar;
.ENDMACRO;
.MACRO SetVect(%0,%1);
I4 = %0;
MR0 =^%1;
CALL PUT_VECTOR;
.ENDMACRO;
.MACRO Sin(%0);
PUSH STS;
DIS M_MODE, DIS AR_SAT;
ax0 =%0;
M5 = 1;
L5 = 0;
call ADMC_SIN;
POP STS;
.ENDMACRO;
.MACRO Cos(%0);
PUSH STS;
DIS M_MODE, DIS AR_SAT;
ax0 =%0;
M5 = 1;
L5 = 0;
call ADMC_COS;
POP STS;
.ENDMACRO;
.MACRO PWM_DAC(%0,%1);
ar=%0;
sr = LSHIFT ar BY -8 (LO); {Value to be written in ar }
ay0=0x80; {Shift to 8 LSBs and add }
ar=sr0+ay0; {offset of 0x80 = 2.5V }
ay0= 0xff;
ar = ar AND ay0;
DM(%1) = ar; {Write value to PWMTIM0 }
.ENDMACRO;
#endif
ADMC401 DSP Motor Controller Appendix F. SROM/EEPROM Boot Loader Protocol
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
55
Appendix F. SROM/EEPROM Boot Loader Protocol
The SROM/EEPROM boot loader interface was designed to be used with a Xilinx XC17128E serial
configuration PROM, or Atmel AT17C128 EEPROM, or Microchip 37LV128 OTP EPROM. If using any
of these devices, the MAKEPROM utility can be used to format an executable file into a .DBS file that can
be programmed into the device. The MAKEPROM utility automatically formats the code and data to boot
properly from the device. If the ADMC401 is successful in loading a user program from the
SROM/EEPROM, then execution of the program will start at 0x0060.
The SROM/EEPROM boot loader can be used with devices other than those listed above if they adhere to
the same timing and protocol given in this appendix.
The SROM/EEPROM boot loader uses a two-wire (data and clock) serial protocol in which the
ADMC401 provides a clock to the device equal to 1/26 of CLKOUT.
On the ADMC401 processor board the device socket is connected as follows:
PIN # SROM/EEPROM pin Connected to
1 DATA DR1A pin on ADMC401
2 CLK SCLK1 pin on ADMC401
3 RESET /OE RFS1 pin on ADMC401
4 CE GND
5 GND GND
6 CEO Floating
7 VPP/SER_EN VCC (+5V)
8 VCC VCC (+5V)
Table 5. SROM / EEPROM Pin Connections
The ROM monitor program resets the DR1SEL bit of the MODECTRL register (see Reference 1) to
connect the DR1A pin (the device’s data line) to the DR1 input of SPORT1. It then sets the UARTEN bit
which connects the DR1 and RFS1 inputs together so that the first word in the input data will act as the
receive frame sync. UARTEN also connects FL1 to the RFS1 pin to be used as a reset signal for the
SROM/EEPROM. SPORT1 is then configured for synchronous communications as follows:
SPORT1 control register = 0x5E07
· internal serial clock (SCLK) used
· external receive frame synch (RFS) enabled
· RFS required on 1st word only
· active high RFS
· alternate receive framing used
· right justify, zero-fill unused MSBs
· serial word length is 8 bits
SPORT1 SCLKDIV register = 12 (1 MHz SCLK freq. @ 26MHz DSP CLKOUT)
FL1 is reset, causing the SROM/EEPROM to be reset, then FL1 is set, causing data to be clocked from the
device in a continuous stream. When the SPORT receives the RFS (the leading edge of the first header
byte 0xFF), it starts receiving a continuous stream of bits. When each byte is accumulated, an interrupt is
generated and the byte is loaded by the DSP. The DSP can immediately start accepting data; however, it
will wait up to 1000 cycles (38.5 us @ 26MHz) to receive the first header byte. This allows for different
startup times if a different device is being used to download the data. The data receive line must be held
low until the first header byte is received. The format of the data expected by the boot loader is given in
Appendix F. SROM/EEPROM Boot Loader Protocol ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
56
Table 7. The format is the same for the other boot load interfaces except that the SROM header bytes are
not used. The MAKEPROM utility automatically converts a user’s executable file into a PROM
programmer file having this format. The boot load timing from reset (RFS1) is summarized in
Figure 26.
The program memory and data memory are loaded according to the blocks defined in the boot load file
syntax (Table 7). Both the program and data memory portions of the boot load file contain checksums
that are used by the monitor to verify correct loading. The PM checksum is calculated by the monitor by
accumulating, in the MR0 register, the upper 16 bits of each PM location received. The lower 8 bits are
accumulated in the MR1 register. When all locations have been received, the MR1 register is masked
with 0xFF, removing any overflow from the lower 8 bits. The MR0 register is then compared to the upper
16 bits of the received checksum and the MR1 register is compared to the lower 8 bits of the received
checksum. The DM checksum is calculated in the same way as the upper 16 bits of the PM checksum.
Note: When boot loading from an SROM, the ADMC401 receives data MSB first. The Atmel, Xilinx,
and Microchip devices transmit LSB first. Therefore, the MAKEPROM program bit-reverses all data
before writing it to the programmer file (.dbs). For example, the SROM header bytes FF, AA, 33 would
look like FF, 55, CC in the .dbs file.
If the monitor times out (i.e., receives no data on DR1A) it will switch the SPORT1 input to DR1B and try
to communicate over the other interfaces.
If the monitor receives data on DR1A, but that data results in an error, the monitor will output an error
code on DT1 and then will restart itself, thus trying to reboot.
Possible errors and their codes are detailed in the following table:
Error Code Description
0x50 SROM PM Header does not match 0xFF, 0xAA, 0x33.
0x51 SROM PM Checksum Error
0x52 SROM DM Header does not match 0xFF, 0xAA, 0x33.
0x53 SROM DM Checksum Error
Table 6. SROM boot loader error codes.
If the monitor successfully loads the program and data memories without error then it starts execution of
the program at location 0x0060.
ADMC401 DSP Motor Controller Appendix F. SROM/EEPROM Boot Loader Protocol
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
57
SCLK 16.8 ms
(1 MHz @ 26 MHz CLKOUT)
17.0 ms
8.0 ms
32.0 ms 8.0 ms 8.0 ms 8.0 ms
RFS1 pin
(SROM/EEPROM reset from ADMC401)
DRA1 pin/ RFS1 (internal)
(Data from device) 4 ZEROs 0xFF 0xAA 0x33 #PM blocks
Program Memory Header Record
RFS
RESET pin
Figure 26. Boot Load Timing (XC17128E, AT17C128, or 37LV128)
Appendix F. SROM/EEPROM Boot Loader Protocol ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
58
0x00 (SROM only*)
0x00 (SROM only*)
0x00 (SROM only*)
0x00 (SROM only*)
0xFF (SROM only*)
0xAA (SROM only*)
0x33 (SROM only*)
Number of PM Blocks
PM Start Address Block 1 (MSB)
PM Start Address Block 1 (LSB)
Number of PM Lines in Block 1 (MSB)
Number of PM Lines in Block 1 (LSB)
.
. Block 1 Code
.
PM Start Address Block N (MSB)
PM Start Address Block N (LSB)
Number of PM Lines in Block N (MSB)
Number of PM Lines in Block N (LSB)
.
. Block N Code
.
PM Checksum (Upper Byte)
PM Checksum (Middle Byte)
PM Checksum (Lower Byte)
0x00 (SROM only*)
0x00 (SROM only*)
0x00 (SROM only*)
0x00 (SROM only*)
0xFF (SROM only*)
0xAA (SROM only*)
0x33 (SROM only*)
Number of DM Blocks
DM Start Address Block 1 (MSB)
DM Start Address Block 1 (LSB)
Number of DM Lines in Block 1 (MSB)
Number of DM Lines in Block 1 (LSB)
.
. Block 1 Data
.
DM Start Address Block N (MSB)
DM Start Address Block N (LSB)
Number of DM Lines in Block N (MSB)
Number of DM Lines in Block N (LSB)
.
. Block N Data
.
DM Checksum (Upper Byte)
DM Checksum (Lower Byte)
* - The 4 zeros up front and bytes FF, AA, 33 are only used in the SROM boot load file syntax. All other
boot load interfaces omit these bytes.
Table 7. File Syntax For All Boot Load Interfaces
ADMC401 DSP Motor Controller Appendix G. UART Boot Loader Protocol
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
59
Appendix G. UART Boot Loader Protocol
The UART boot loader interface can be used with any external device that can be configured as a UART
and can adhere to the timing and protocol given in this appendix. This interface is compatible with the
Motorola M68HC11 SCI port. If the ADMC401 is successful in loading a user program over the UART
boot loader interface, then execution of the program will start at 0x0060.
The UART boot loader uses the standard asynchronous protocol using only the data receive (RXD) and
data transmit (TXD) lines. To communicate in this mode, an external device need only connect its
transmit data line to DR1B and its receive data line to DT1. The ADMC401 processor board uses an RS-
232 line driver chip to convert from the SPORT1 data receive (DR1B) and data transmit (DT1) TTL
signals to the RS-232 standard.
Following a failure of the SROM/EEPROM boot loader, the ROM monitor program switches the input on
SPORT1 to DR1B and waits for two bytes of information. These two bytes are received asynchronously
(no clock is required), MSB first. The first byte received is called the autobaud byte. It is used to
calculate the baud rate at which the data is arriving. This is known as the autobaud feature. The
ADMC401 will lock onto the baud rate of the external device automatically if it sends a byte equal to
0x70. The maximum baud rate that the ADMC401 can lock onto is 300 kHz at a 26 MHz CLKOUT. The
second byte received is called the header byte. It tells the monitor what type of interface it is connected to.
For the UART boot loader, a header byte equal to 0x71 must be sent. The required timing for this
interface is shown in Figure 23.
After the monitor verifies that it is connected to a device that is ready to boot load a program as a UART,
it sets up SPORT1 as follows:
SPORT1 control register = 0x5E4F
· internal serial clock (SCLK) used
· external receive frame synch (RFS) enabled
· RFS required on 1st word only
· active low RFS (start bit acts as RFS)
· alternate receive framing used
· right justify, zero-fill unused MSBs
· serial word length is 16 bits
The autobaud feature determines the SPORT1 SCLKDIV register value. SCLKDIV is set to a value that
represents the baud rate at which the autobaud byte was received, multiplied by 3. The incoming data is
sampled at 3 times the baud rate to minimize data errors.
Each byte received is represented by 11 bits (1 start bit, 8 data bits, and 2 stop bits, no parity) as shown in
Figure 27. Since the incoming data is sampled at three times the baud rate each bit is represented by 3 bits
in the received data. Thus each 11-bit word transmitted to the ADMC401 is received as a 33-bit word
(actually the last stop bit is dropped to make 32 bits). In the ADMC401 the 32 bits are received as two
16-bit serial word transfers. Words are transmitted and received LSB first. The ADMC401 monitor
extracts the byte of information from the 32 bits of received data.
As data is received, it is loaded into memory in the same manner as with the other boot load interfaces.
The format of the data is given in Table 7. Each data byte received, starting with the header byte, is
echoed back over DT1. The autobaud byte is not echoed back. The external device may use this echo as a
means of synchronization and verification that the data has been received correctly. As with the other
boot load interfaces, the monitor calculates a checksum for the program and data memory words. If the
monitor detects a checksum miscompare it will restart itself as if a reset has occurred.
Appendix G. UART Boot Loader Protocol ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
60
If the monitor successfully loads the program and data memories without error then it starts execution of
the program at location 0x0060.
0 1 0 1 1 0 1 0 0 1 1
000 111 000 111 111 000 111 000 000 111 111
Start
Bit
LSB Data Bits MSB Stop
Bits
Data received by ADMC401
(Sampled at 3 times the baud rate.)
Figure 27. UART Protocol
ADMC401 DSP Motor Controller Appendix H. UART Debugger Protocol
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
61
Appendix H. UART Debugger Protocol
In the UART Debugger mode the monitor emulates a standard UART and processes commands received
over SPORT1 from an external device. For example, in the case of the Motion Control Debugger, the
external device is a PC. While this interface is designed to be used with the Motion Control Debugger it
can also be used with any external device that can adhere to the timing and protocol detailed in this
appendix.
The UART debugger interface uses the same protocol as the UART boot loader interface discussed above.
The timing required to connect to this interface is shown in Figure 23. Similar to the UART boot loader,
the monitor receives two bytes of information (after failing the SROM/EEPROM boot load). However,
this time the header byte must be equal to 0x70. Once the monitor verifies that it is connected to a device
that wants to communicate over the UART debugger interface, it sets up SPORT1 identically to the UART
boot loader interface. The difference here is that when in debug mode the data received must adhere to
the command protocol discussed below.
Debug Mode Commands
The following commands are available when in debug mode:
· data memory write
· data memory read
· 16-bit program memory write
· 16-bit program memory read
· 24-bit program memory write
· 24-bit program memory read
Not only can these commands be used to read and write to the ADMC401 memories, the data memory
write command can also be used to modify any memory-mapped registers. In addition it can be used to set
variables in the monitor to start the execution of user code (see Starting User Code).
Each of the commands consists of a unique 8 byte sequence that is sent to the ADMC401. For each byte
that is received, the ADMC401 will transmit a corresponding response byte. The external device has the
option of reading this known response as a means of synchronizing with the ADMC401. While not
required, this is recommended.
It is important to note that when the data memory write command is used to modify memory-mapped
registers, the register will be modified after the 7th byte of the command is received. The 8th byte is still
required to stay synchronized, but this is its only purpose. In some cases, it is advantageous to write only
7 bytes of the data memory write command to the ADMC401 and then re-synchronize with it after the
register modification takes place (see Synchronizing Communication). One such example is changing
SPORT1’s baud rate in the SCLKDIV register. If an 8 byte command were used, the baud rate would
actually change while the 8th byte is being transferred, resulting in unpredictable behavior.
The ADMC401 monitor command syntax is given in Table 9 through Table 14. For each command byte,
0 is the first byte sent over the interface. Bytes listed as “dummy bytes” can be any value because the
monitor ignores them. Whatever byte is sent, will be echoed back verbatim.
Appendix H. UART Debugger Protocol ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
62
Command Code Command
0 Data memory write
1 Data memory read
2 16-bit program memory write
3 16-bit program memory read
4 24-bit program memory write
5 24-bit program memory read
Table 8. Available Commands (Debugger Interface)
BYTE Description Expected Response
0 0x00 (dummy byte) Byte 0 is echoed back
1 Lower Byte of DM Data Word Byte 1 is echoed back
2 Upper Byte of DM Data Word Byte 2 is echoed back
3 Lower Byte of DM Destination Address Byte 3 is echoed back
4 Upper Byte of DM Destination Address Byte 4 is echoed back
5 0x00 (Command code - from Table 8) Byte 5 is echoed back
6 0x00 (dummy byte) 0xAA
7 0x00 (dummy byte) 0x55
Table 9. Data Memory Write Command
BYTE Description Expected Response
0 0x00 (dummy byte) Byte 0 is echoed back
1 0x00 (dummy byte) Byte 1 is echoed back
2 0x00 (dummy byte) Byte 2 is echoed back
3 Lower Byte of DM Address Byte 3 is echoed back
4 Upper Byte of DM Address Byte 4 is echoed back
5 0x01 (Command code - from Table 8) Byte 5 is echoed back
6 0x00 (dummy byte) Lower byte of DM word
7 0x00 (dummy byte) Upper byte of DM word
Table 10. Data Memory Read Command
BYTE Description Expected Response
0 0x00 (dummy byte) Byte 0 is echoed back
1 Middle Byte of PM Data Word Byte 1 is echoed back
2 Upper Byte of PM Data Word Byte 2 is echoed back
3 Lower Byte of PM Destination Address Byte 3 is echoed back
4 Upper Byte of PM Destination Address Byte 4 is echoed back
5 0x02 (Command code - from Table 8) Byte 5 is echoed back
6 0x00 (dummy byte) 0xAA
7 0x00 (dummy byte) 0x55
Table 11. 16-Bit Program Memory Write Command
ADMC401 DSP Motor Controller Appendix H. UART Debugger Protocol
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
63
BYTE Description Expected Response
0 0x00 (dummy byte) Byte 0 is echoed back
1 0x00 (dummy byte) Byte 1 is echoed back
2 0x00 (dummy byte) Byte 2 is echoed back
3 Lower Byte of PM Address Byte 3 is echoed back
4 Upper Byte of PM Address Byte 4 is echoed back
5 0x03 (Command code - from Table 8) Byte 5 is echoed back
6 0x00 (dummy byte) Lower byte of PM data word
7 0x00 (dummy byte) Upper byte of PM data word
Table 12. 16-Bit Program Memory Read Command
BYTE Description Expected Response
0 Lower Byte of PM Data Word byte 0 is echoed back
1 Middle Byte of PM Data Word byte 1 is echoed back
2 Upper Byte of PM Data Word byte 2 is echoed back
3 Lower Byte of PM Destination Address byte 3 is echoed back
4 Upper Byte of PM Destination Address byte 4 is echoed back
5 0x04 (Command code - from Table 8) byte 5 is echoed back
6 0x00 (dummy byte) 0xAA
7 0x00 (dummy byte) 0x55
Table 13. 24-Bit Program Memory Write Command
BYTE Description Expected Response
0 0x00 (dummy byte) byte 0 is echoed back
1 0x00 (dummy byte) byte 1 is echoed back
2 0x00 (dummy byte) byte 2 is echoed back
3 Lower Byte of PM Address byte 3 is echoed back
4 Upper Byte of PM Address byte 4 is echoed back
5 0x05 (Command code - from Table 8) Lower byte of PM word
6 0x00 (dummy byte) Middle byte of PM word
7 0x00 (dummy byte) Upper byte of PM word
Table 14. 24-Bit Program Memory Read Command
Starting User Code
A user program can be started on the ADMC401 by writing the program’s starting address to the
START_ADR variable and then writing the code 0xABCD to the EXECUTE_FLAG variable, both
contained in the monitor’s data memory. This can be done with two data memory write commands to the
addresses contained in Table 15. For example, Table 16 shows the two-command sequence that an
external device would send to the ADMC401 to start a user program at 0x0060 in program memory. As
can be seen, the second data memory write is only a 7-byte command. This is because the ADMC401
actually writes the value following the 7th byte thus causing the execution of the user program. There is
no need to send an 8th byte because it would never be received by the ADMC401.
Appendix H. UART Debugger Protocol ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
64
Variable Address Description
START_ADR 0x3BC0 START_ADR contains location where execution will begin
EXECUTE_FLAG 0x3BC1 0xABCD written here causes execution to begin
Table 15. Monitor Variables for Executing User Code
BYTE Description Expected Response
0 0x00 0x00
1 0x60 0x60
2 0x00 0x00
3 0xC0 0xC0
4 0x3B 0x3B
5 0x00 0x00
6 0x00 0xAA
7 0x00 0x55
0 0x00 0x00
1 0xCD 0xCD
2 0xAB 0xAB
3 0xC1 0xC1
4 0x3B 0x3B
5 0x00 0x00
6 0x00 0xAA
Table 16. DM Write Commands to Start Program at 0x0060
Synchronizing Communication
For the ADMC401 to properly handle incoming commands it must be synchronous with an external
device. In other words, it must know when it is receiving the first word of a command. This step must be
performed prior to issuing the first of any commands in debug mode. The external device can
synchronize with the ADMC401 by using the monitor protocol given above and detecting when it receives
the two byte sequence 0xAA, 0x55 from the ADMC401. At this point both devices know that the next
byte sent will be the first byte of a command. It is only necessary to synchronize once at the beginning of a
series of debug commands as long as 8 bytes are sent for each command.
The easiest way to synchronize is to continually transmit a byte and receive its echo. When the received
echo of two subsequent bytes is 0xAA, 0x55, the synchronization is complete. The byte that is continually
sent to the ADMC401 for this purpose can be any byte except 0x00 - 0x05, 0xAA, or 0x55.
ADMC401 DSP Motor Controller Appendix I. Synchronous Master Boot Load Protocol
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
65
Appendix I. Synchronous Master Boot Load Protocol
The synchronous master boot load interface allows an external device to boot load the ADMC401
synchronously using the SCLK on the ADMC401. The ADMC401 acts as the master, controlling the
clock, while the external device acts as the slave. SPORT1 is configured as a synchronous serial port.
The timing required to connect to this interface is shown in Figure 23. The ADMC401 switches to this
interface when it receives a two-byte sequence of 0x70, 0x73 after failing an SROM/EEPROM boot load.
The ADMC401 turns on SCLK1 at the rate at which it receives the autobaud byte 0x70. It then receives
the data to be loaded in the order given in Table 7. If the ADMC401 is successful in loading a user
program over this interface, then execution of the program will start at 0x0060.
Once the monitor verifies the header byte is 0x73, it sets up SPORT1 as follows:
SPORT1 control register = 0x7E07
· internal serial clock (SCLK) used
· external receive frame synch (RFS) enabled
· internal transmit frame synch (TFS) enabled
· RFS and TFS required on every word
· active high RFS and TFS
· alternate receive and transmit framing used
· right justify, zero-fill unused MSBs
· serial word length is 8 bits
The autobaud feature determines the SPORT1 SCLKDIV register value. SCLKDIV is set to a value that
represents the clock rate at which the autobaud byte was received. The data received is sampled at this
rate, not at 3 times the rate as for the UART, and each word is 1 byte in length. Words are transmitted and
received MSB first.
As data is received, it is loaded into memory in the same manner as with the other boot load interfaces.
The format of the data is given in Table 7. Each data byte received, starting with the number of PM data
words byte, is echoed back over DT1. The autobaud and header bytes are not echoed back. The external
device may use this echo as a means of synchronization and verification that the data has been received
correctly. As with the other boot load interfaces, the monitor calculates a checksum for the program and
data memory words. If the monitor detects a checksum miscompare it will restart itself as if a reset has
occurred.
If the monitor successfully loads the program and data memories without error, then it starts execution of
the program at location 0x0060.
Appendix J. Synchronous Master Debugger ProtocolADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
66
Appendix J. Synchronous Master Debugger Protocol
The synchronous master debugger interface allows an external device to connect to the debugger interface
on the ADMC401 synchronously, using the SCLK on the ADMC401. The ADMC401 acts as the master,
controlling the clock, while the external device acts as the slave. SPORT1 is configured as a synchronous
serial port.
The timing required to connect to this interface is shown in Figure 23. The ADMC401 switches to this
interface when it receives a two-byte sequence of 0x70, 0x72 after failing an SROM/EEPROM boot load.
The ADMC401 turns on SCLK1 at the rate at which it receives the autobaud byte 0x70. It then processes
commands received over SPORT1 from the external device.
Once the monitor verifies the header byte is 0x72, it sets up SPORT1 as follows:
SPORT1 control register = 0x7E07
· internal serial clock (SCLK) used
· external receive frame synch (RFS) enabled
· internal transmit frame synch (TFS) enabled
· RFS and TFS required on every word
· active high RFS and TFS
· alternate receive and transmit framing used
· right justify, zero-fill unused MSBs
· serial word length is 8 bits
The autobaud feature determines the SPORT1 SCLKDIV register value. SCLKDIV is set to a value that
represents the clock rate at which the autobaud byte was received. The data received is sampled at this
rate, not at 3 times the rate as for the UART, and each word is 1 byte in length. Words are transmitted
and received MSB first.
A complete description of the available commands is given in Appendix H.
ADMC401 DSP Motor Controller Appendix K. Synchronous Slave Boot Loader Protocol
Developer’s Reference Manual
2 March 2000 Rev. 2.0
82-001925-01
67
Appendix K. Synchronous Slave Boot Loader Protocol
The synchronous slave boot load interface allows an external device to boot load the ADMC401
synchronously, using its own SCLK. The external device acts as the master, controlling the clock, while
the ADMC401 acts as the slave. SPORT1 is configured as a synchronous serial port.
The timing required to connect to this interface is shown in Figure 23. The ADMC401 switches to this
interface when it receives a two-byte sequence of 0x70, 0x75 after failing an SROM/EEPROM boot load.
The ADMC401 configures SPORT1 to use the external clock connected to SCLK1. It then receives the
data to be loaded in the order given in Table 7. If the ADMC401 is successful in loading a user program
over this interface, then execution of the program will start at 0x0060.
Once the monitor verifies the header byte is 0x75, it sets up SPORT1 as follows:
SPORT1 control register = 0x3E07
· external serial clock (SCLK) used
· external receive frame synch (RFS) enabled
· internal transmit frame synch (TFS) enabled
· RFS and TFS required on every word
· active high RFS and TFS
· alternate receive and transmit framing used
· right justify, zero-fill unused MSBs
· serial word length is 8 bits
Words are transmitted and received MSB first. As data is received, it is loaded into memory in the same
manner as with the other boot load interfaces. The format of the data is given in Table 7. Each data byte
received, starting with the number of PM data words byte, is echoed back over DT1. The autobaud and
header bytes are not echoed back. The external device may use this echo as a means of synchronization
and verification that the data has been received correctly. As with the other boot load interfaces, the
monitor calculates a checksum for the program and data memory words. If the monitor detects a
checksum miscompare it will restart itself as if a reset has occurred.
If the monitor successfully loads the program and data memories without error, then it starts execution of
the program at location 0x0060.
Appendix L. Synchronous Slave Debugger Protocol ADMC401 DSP Motor Controller
Developer’s Reference Manual
Rev. 2.0 2 March 2000
82-001925-01
68
Appendix L. Synchronous Slave Debugger Protocol
The synchronous slave debugger interface allows an external device to connect to the debugger interface
on the ADMC401 synchronously, using its own SCLK. The external device acts as the master,
controlling the clock, while the ADMC401 acts as the slave. SPORT1 is configured as a synchronous
serial port.
The timing required to connect to this interface is shown in Figure 23. The ADMC401 switches to this
interface when it receives a two-byte sequence of 0x70, 0x74 after failing an SROM/EEPROM boot load.
The ADMC401 configures SPORT1 to use the external clock connected to SCLK1. It then processes
commands received over SPORT1 from the external device.
Once the monitor verifies the header byte is 0x74, it sets up SPORT1 as follows:
SPORT1 control register = 0x3E07
· external serial clock (SCLK) used
· external receive frame synch (RFS) enabled
· internal transmit frame synch (TFS) enabled
· RFS and TFS required on every word
· active high RFS and TFS
· alternate receive and transmit framing used
· right justify, zero-fill unused MSBs
· serial word length is 8 bits
Words are transmitted and received MSB first. A complete description of the available commands is given
in Appendix H
CHAPTER
12 The Fast Fourier Transform
There are several ways to calculate the Discrete Fourier Transform (DFT), such as solving
simultaneous linear equations or the correlation method described in Chapter 8. The Fast
Fourier Transform (FFT) is another method for calculating the DFT. While it produces the same
result as the other approaches, it is incredibly more efficient, often reducing the computation time
by hundreds. This is the same improvement as flying in a jet aircraft versus walking! If the
FFT were not available, many of the techniques described in this book would not be practical.
While the FFT only requires a few dozen lines of code, it is one of the most complicated
algorithms in DSP. But don't despair! You can easily use published FFT routines without fully
understanding the internal workings.
Real DFT Using the Complex DFT
J.W. Cooley and J.W. Tukey are given credit for bringing the FFT to the world
in their paper: "An algorithm for the machine calculation of complex Fourier
Series," Mathematics Computation, Vol. 19, 1965, pp 297-301. In retrospect,
others had discovered the technique many years before. For instance, the great
German mathematician Karl Friedrich Gauss (1777-1855) had used the method
more than a century earlier. This early work was largely forgotten because it
lacked the tool to make it practical: the digital computer. Cooley and Tukey
are honored because they discovered the FFT at the right time, the beginning
of the computer revolution.
The FFT is based on the complex DFT, a more sophisticated version of the real
DFT discussed in the last four chapters. These transforms are named for the
way each represents data, that is, using complex numbers or using real
numbers. The term complex does not mean that this representation is difficult
or complicated, but that a specific type of mathematics is used. Complex
mathematics often is difficult and complicated, but that isn't where the name
comes from. Chapter 29 discusses the complex DFT and provides the
background needed to understand the details of the FFT algorithm. The
226 The Scientist and Engineer's Guide to Digital Signal Processing
FIGURE 12-1
Comparing the real and complex DFTs. The real DFT takes an N point time domain signal and
creates two N/2% 1 point frequency domain signals. The complex DFT takes two N point time
domain signals and creates two N point frequency domain signals. The crosshatched regions shows
the values common to the two transforms.
Real DFT
Complex DFT
Time Domain
Time Domain
Frequency Domain
Frequency Domain
0 N-1
0 N-1
0 N-1
0 N/2
0 N/2
0
0
N-1
N-1
N/2
N/2
Real Part
Imaginary Part
Real Part
Imaginary Part
Real Part
Imaginary Part
Time Domain Signal
topic of this chapter is simpler: how to use the FFT to calculate the real DFT,
without drowning in a mire of advanced mathematics.
Since the FFT is an algorithm for calculating the complex DFT, it is
important to understand how to transfer real DFT data into and out of the
complex DFT format. Figure 12-1 compares how the real DFT and the
complex DFT store data. The real DFT transforms an N point time domain
signal into two N/2 % 1 point frequency domain signals. The time domain
signal is called just that: the time domain signal. The two signals in the
frequency domain are called the real part and the imaginary part, holding
the amplitudes of the cosine waves and sine waves, respectively. This
should be very familiar from past chapters.
In comparison, the complex DFT transforms two N point time domain signals
into two N point frequency domain signals. The two time domain signals are
called the real part and the imaginary part, just as are the frequency domain
signals. In spite of their names, all of the values in these arrays are just
ordinary numbers. (If you are familiar with complex numbers: the j's are not
included in the array values; they are a part of the mathematics. Recall that the
operator, Im( ), returns a real number).
Chapter 12- The Fast Fourier Transform 227
6000 'NEGATIVE FREQUENCY GENERATION
6010 'This subroutine creates the complex frequency domain from the real frequency domain.
6020 'Upon entry to this subroutine, N% contains the number of points in the signals, and
6030 'REX[ ] and IMX[ ] contain the real frequency domain in samples 0 to N%/2.
6040 'On return, REX[ ] and IMX[ ] contain the complex frequency domain in samples 0 to N%-1.
6050 '
6060 FOR K% = (N%/2+1) TO (N%-1)
6070 REX[K%] = REX[N%-K%]
6080 IMX[K%] = -IMX[N%-K%]
6090 NEXT K%
6100 '
6110 RETURN
TABLE 12-1
Suppose you have an N point signal, and need to calculate the real DFT by
means of the Complex DFT (such as by using the FFT algorithm). First, move
the N point signal into the real part of the complex DFT's time domain, and
then set all of the samples in the imaginary part to zero. Calculation of the
complex DFT results in a real and an imaginary signal in the frequency
domain, each composed of N points. Samples 0 through N/2 of these signals
correspond to the real DFT's spectrum.
As discussed in Chapter 10, the DFT's frequency domain is periodic when the
negative frequencies are included (see Fig. 10-9). The choice of a single
period is arbitrary; it can be chosen between -1.0 and 0, -0.5 and 0.5, 0 and
1.0, or any other one unit interval referenced to the sampling rate. The
complex DFT's frequency spectrum includes the negative frequencies in the 0
to 1.0 arrangement. In other words, one full period stretches from sample 0 to
sample N&1 , corresponding with 0 to 1.0 times the sampling rate. The positive
frequencies sit between sample 0 and N/2 , corresponding with 0 to 0.5. The
other samples, between N/2% 1 and N&1 , contain the negative frequency
values (which are usually ignored).
Calculating a real Inverse DFT using a complex Inverse DFT is slightly
harder. This is because you need to insure that the negative frequencies are
loaded in the proper format. Remember, points 0 through N/2 in the
complex DFT are the same as in the real DFT, for both the real and the
imaginary parts. For the real part, point N/2% 1 is the same as point
N/2& 1 , point N/2% 2 is the same as point N/2& 2 , etc. This continues to
point N&1 being the same as point 1. The same basic pattern is used for
the imaginary part, except the sign is changed. That is, point N/2% 1 is the
negative of point N/2& 1 , point N/2% 2 is the negative of point N/2& 2 , etc.
Notice that samples 0 and N/2 do not have a matching point in this
duplication scheme. Use Fig. 10-9 as a guide to understanding this
symmetry. In practice, you load the real DFT's frequency spectrum into
samples 0 to N/2 of the complex DFT's arrays, and then use a subroutine to
generate the negative frequencies between samples N/2% 1 and N&1 . Table
12-1 shows such a program. To check that the proper symmetry is present,
after taking the inverse FFT, look at the imaginary part of the time domain.
It will contain all zeros if everything is correct (except for a few parts-permillion
of noise, using single precision calculations).
228 The Scientist and Engineer's Guide to Digital Signal Processing
FIGURE 12-2
The FFT decomposition. An N point signal is decomposed into N signals each containing a single point.
Each stage uses an interlace decomposition, separating the even and odd numbered samples.
1 signal of
16 points
2 signals of
8 points
4 signals of
4 points
8 signals of
2 points
16 signals of
1 point
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 2 4 6 8 10 12 14 1 3 5 7 9 11 13 15
0 4 8 12 2 6 10 14 1 5 9 13 3 7 11 15
0 8 4 12 2 10 6 14 1 9 5 13 3 11 7 15
0 8 4 12 2 10 6 14 1 9 5 13 3 11 7 15
How the FFT works
The FFT is a complicated algorithm, and its details are usually left to those that
specialize in such things. This section describes the general operation of the
FFT, but skirts a key issue: the use of complex numbers. If you have a
background in complex mathematics, you can read between the lines to
understand the true nature of the algorithm. Don't worry if the details elude
you; few scientists and engineers that use the FFT could write the program
from scratch.
In complex notation, the time and frequency domains each contain one signal
made up of N complex points. Each of these complex points is composed of
two numbers, the real part and the imaginary part. For example, when we talk
about complex sample X[42] , it refers to the combination of ReX[42] and
ImX[42]. In other words, each complex variable holds two numbers. When
two complex variables are multiplied, the four individual components must be
combined to form the two components of the product (such as in Eq. 9-1). The
following discussion on "How the FFT works" uses this jargon of complex
notation. That is, the singular terms: signal, point, sample, and value, refer
to the combination of the real part and the imaginary part.
The FFT operates by decomposing an N point time domain signal into N
time domain signals each composed of a single point. The second step is to
calculate the N frequency spectra corresponding to these N time domain
signals. Lastly, the N spectra are synthesized into a single frequency
spectrum.
Figure 12-2 shows an example of the time domain decomposition used in the
FFT. In this example, a 16 point signal is decomposed through four
Chapter 12- The Fast Fourier Transform 229
Sample numbers Sample numbers
in normal order after bit reversal
Decimal Binary Decimal Binary
0 0000 0 0000
1 0001 8 1000
2 0010 4 0100
3 0011 12 1100
4 0100 2 0010
5 0101 10 1010
6 0110 6 0100
7 0111 14 1110
8 1000 1 0001
9 1001 9 1001
10 1010 5 0101
11 1011 13 1101
12 1100 3 0011
13 1101 11 1011
14 1110 7 0111
15 1111 15 1111
FIGURE 12-3
The FFT bit reversal sorting. The FFT time domain decomposition can be implemented by
sorting the samples according to bit reversed order.
separate stages. The first stage breaks the 16 point signal into two signals each
consisting of 8 points. The second stage decomposes the data into four signals
of 4 points. This pattern continues until there are N signals composed of a
single point. An interlaced decomposition is used each time a signal is
broken in two, that is, the signal is separated into its even and odd numbered
samples. The best way to understand this is by inspecting Fig. 12-2 until you
grasp the pattern. There are Log stages required in this decomposition, i.e., 2N
a 16 point signal (24) requires 4 stages, a 512 point signal (27) requires 7
stages, a 4096 point signal (212) requires 12 stages, etc. Remember this value,
Log ; it will be referenced many times in this chapter. 2N
Now that you understand the structure of the decomposition, it can be greatly
simplified. The decomposition is nothing more than a reordering of the
samples in the signal. Figure 12-3 shows the rearrangement pattern required.
On the left, the sample numbers of the original signal are listed along with
their binary equivalents. On the right, the rearranged sample numbers are
listed, also along with their binary equivalents. The important idea is that the
binary numbers are the reversals of each other. For example, sample 3 (0011)
is exchanged with sample number 12 (1100). Likewise, sample number 14
(1110) is swapped with sample number 7 (0111), and so forth. The FFT time
domain decomposition is usually carried out by a bit reversal sorting
algorithm. This involves rearranging the order of the N time domain samples
by counting in binary with the bits flipped left-for-right (such as in the far right
column in Fig. 12-3).
230 The Scientist and Engineer's Guide to Digital Signal Processing
a b c d
a 0 b 0 c 0 d 0
A B C D
A B C D A B C D
e f g h
0 e 0 f 0 g 0 h
E F G H
F G H E F G H
× sinusoid
Time Domain Frequency Domain
E
FIGURE 12-4
The FFT synthesis. When a time domain signal is diluted with zeros, the frequency domain is
duplicated. If the time domain signal is also shifted by one sample during the dilution, the spectrum
will additionally be multiplied by a sinusoid.
The next step in the FFT algorithm is to find the frequency spectra of the
1 point time domain signals. Nothing could be easier; the frequency
spectrum of a 1 point signal is equal to itself. This means that nothing is
required to do this step. Although there is no work involved, don't forget
that each of the 1 point signals is now a frequency spectrum, and not a time
domain signal.
The last step in the FFT is to combine the N frequency spectra in the exact
reverse order that the time domain decomposition took place. This is where the
algorithm gets messy. Unfortunately, the bit reversal shortcut is not
applicable, and we must go back one stage at a time. In the first stage, 16
frequency spectra (1 point each) are synthesized into 8 frequency spectra (2
points each). In the second stage, the 8 frequency spectra (2 points each) are
synthesized into 4 frequency spectra (4 points each), and so on. The last stage
results in the output of the FFT, a 16 point frequency spectrum.
Figure 12-4 shows how two frequency spectra, each composed of 4 points,
are combined into a single frequency spectrum of 8 points. This synthesis
must undo the interlaced decomposition done in the time domain. In other
words, the frequency domain operation must correspond to the time domain
procedure of combining two 4 point signals by interlacing. Consider two
time domain signals, abcd and efgh. An 8 point time domain signal can be
formed by two steps: dilute each 4 point signal with zeros to make it an
Chapter 12- The Fast Fourier Transform 231
+ + + + + + + +
Eight Point Frequency Spectrum
Odd- Four Point
Frequency Spectrum
Even- Four Point
Frequency Spectrum
xS xS xS xS
FIGURE 12-5
FFT synthesis flow diagram. This shows
the method of combining two 4 point
frequency spectra into a single 8 point
frequency spectrum. The ×S operation
means that the signal is multiplied by a
sinusoid with an appropriately selected
frequency.
2 point input
2 point output
xS
FIGURE 12-6
The FFT butterfly. This is the basic
calculation element in the FFT, taking
two complex points and converting
them into two other complex points.
8 point signal, and then add the signals together. That is, abcd becomes
a0b0c0d0, and efgh becomes 0e0f0g0h. Adding these two 8 point signals
produces aebfcgdh. As shown in Fig. 12-4, diluting the time domain with zeros
corresponds to a duplication of the frequency spectrum. Therefore, the
frequency spectra are combined in the FFT by duplicating them, and then
adding the duplicated spectra together.
In order to match up when added, the two time domain signals are diluted with
zeros in a slightly different way. In one signal, the odd points are zero, while
in the other signal, the even points are zero. In other words, one of the time
domain signals (0e0f0g0h in Fig. 12-4) is shifted to the right by one sample.
This time domain shift corresponds to multiplying the spectrum by a sinusoid.
To see this, recall that a shift in the time domain is equivalent to convolving
the signal with a shifted delta function. This multiplies the signal's spectrum
with the spectrum of the shifted delta function. The spectrum of a shifted delta
function is a sinusoid (see Fig 11-2).
Figure 12-5 shows a flow diagram for combining two 4 point spectra into a
single 8 point spectrum. To reduce the situation even more, notice that Fig. 12-
5 is formed from the basic pattern in Fig 12-6 repeated over and over.
232 The Scientist and Engineer's Guide to Digital Signal Processing
Time Domain Data
Frequency Domain Data
Bit Reversal
Data Sorting
Overhead
Overhead
Calculation
Decomposition
Synthesis
Time
Domain
Frequency
Domain
Butterfly
FIGURE 12-7
Flow diagram of the FFT. This is based
on three steps: (1) decompose an N point
time domain signal into N signals each
containing a single point, (2) find the
spectrum of each of the N point signals
(nothing required), and (3) synthesize the
N frequency spectra into a single
frequency spectrum.
Loop for each Butterfly
Loop for Leach sub-DFT
Loop for Log2N stages
This simple flow diagram is called a butterfly due to its winged appearance.
The butterfly is the basic computational element of the FFT, transforming two
complex points into two other complex points.
Figure 12-7 shows the structure of the entire FFT. The time domain
decomposition is accomplished with a bit reversal sorting algorithm.
Transforming the decomposed data into the frequency domain involves nothing
and therefore does not appear in the figure.
The frequency domain synthesis requires three loops. The outer loop runs
through the Log stages (i.e., each level in Fig. 12-2, starting from the bottom 2N
and moving to the top). The middle loop moves through each of the individual
frequency spectra in the stage being worked on (i.e., each of the boxes on any
one level in Fig. 12-2). The innermost loop uses the butterfly to calculate the
points in each frequency spectra (i.e., looping through the samples inside any
one box in Fig. 12-2). The overhead boxes in Fig. 12-7 determine the
beginning and ending indexes for the loops, as well as calculating the sinusoids
needed in the butterflies. Now we come to the heart of this chapter, the actual
FFT programs.
Chapter 12- The Fast Fourier Transform 233
5000 'COMPLEX DFT BY CORRELATION
5010 'Upon entry, N% contains the number of points in the DFT, and
5020 'XR[ ] and XI[ ] contain the real and imaginary parts of the time domain.
5030 'Upon return, REX[ ] and IMX[ ] contain the frequency domain data.
5040 'All signals run from 0 to N%-1.
5050 '
5060 PI = 3.14159265 'Set constants
5070 '
5080 FOR K% = 0 TO N%-1 'Zero REX[ ] and IMX[ ], so they can be used
5090 REX[K%] = 0 'as accumulators during the correlation
5100 IMX[K%] = 0
5110 NEXT K%
5120 '
5130 FOR K% = 0 TO N%-1 'Loop for each value in frequency domain
5140 FOR I% = 0 TO N%-1 'Correlate with the complex sinusoid, SR & SI
5150 '
5160 SR = COS(2*PI*K%*I%/N%) 'Calculate complex sinusoid
5170 SI = -SIN(2*PI*K%*I%/N%)
5180 REX[K%] = REX[K%] + XR[I%]*SR - XI[I%]*SI
5190 IMX[K%] = IMX[K%] + XR[I%]*SI + XI[I%]*SR
5200 '
5210 NEXT I%
5220 NEXT K%
5230 '
5240 RETURN
TABLE 12-2
FFT Programs
As discussed in Chapter 8, the real DFT can be calculated by correlating
the time domain signal with sine and cosine waves (see Table 8-2). Table
12-2 shows a program to calculate the complex DFT by the same method.
In an apples-to-apples comparison, this is the program that the FFT
improves upon.
Tables 12-3 and 12-4 show two different FFT programs, one in FORTRAN and
one in BASIC. First we will look at the BASIC routine in Table 12-4. This
subroutine produces exactly the same output as the correlation technique in
Table 12-2, except it does it much faster. The block diagram in Fig. 12-7 can
be used to identify the different sections of this program. Data are passed to
this FFT subroutine in the arrays: REX[ ] and IMX[ ], each running from
sample 0 to N&1 . Upon return from the subroutine, REX[ ] and IMX[ ] are
overwritten with the frequency domain data. This is another way that the FFT
is highly optimized; the same arrays are used for the input, intermediate
storage, and output. This efficient use of memory is important for designing
fast hardware to calculate the FFT. The term in-place computation is used
to describe this memory usage.
While all FFT programs produce the same numerical result, there are subtle
variations in programming that you need to look out for. Several of these
234 The Scientist and Engineer's Guide to Digital Signal Processing
TABLE 12-3
The Fast Fourier Transform in FORTRAN.
Data are passed to this subroutine in the
variables X( ) and M. The integer, M, is the
base two logarithm of the length of the DFT,
i.e., M = 8 for a 256 point DFT, M = 12 for a
4096 point DFT, etc. The complex array, X( ),
holds the time domain data upon entering the
DFT. Upon return from this subroutine, X( ) is
overwritten with the frequency domain data.
Take note: this subroutine requires that the
input and output signals run from X(1) through
X(N), rather than the customary X(0) through
X(N-1).
SUBROUTINE FFT(X,M)
COMPLEX X(4096),U,S,T
PI=3.14159265
N=2**M
DO 20 L=1,M
LE=2**(M+1-L)
LE2=LE/2
U=(1.0,0.0)
S=CMPLX(COS(PI/FLOAT(LE2)),-SIN(PI/FLOAT(LE2)))
DO 20 J=1,LE2
DO 10 I=J,N,LE
IP=I+LE2
T=X(I)+X(IP)
X(IP)=(X(I)-X(IP))*U
10 X(I)=T
20 U=U*S
ND2=N/2
NM1=N-1
J=1
DO 50 I=1,NM1
IF(I.GE.J) GO TO 30
T=X(J)
X(J)=X(I)
X(I)=T
30 K=ND2
40 IF(K.GE.J) GO TO 50
J=J-K
K=K/2
GO TO 40
50 J=J+K
RETURN
END
of these differences are illustrated by the FORTRAN program listed in Table
12-3. This program uses an algorithm called decimation in frequency, while
the previously described algorithm is called decimation in time. In a
decimation in frequency algorithm, the bit reversal sorting is done after the
three nested loops. There are also FFT routines that completely eliminate the
bit reversal sorting. None of these variations significantly improve the
performance of the FFT, and you shouldn't worry about which one you are
using.
The important differences between FFT algorithms concern how data are
passed to and from the subroutines. In the BASIC program, data enter and
leave the subroutine in the arrays REX[ ] and IMX[ ], with the samples
running from index 0 to N&1 . In the FORTRAN program, data are passed
in the complex array X( ), with the samples running from 1 to N. Since this
is an array of complex variables, each sample in X( ) consists of two
numbers, a real part and an imaginary part. The length of the DFT must
also be passed to these subroutines. In the BASIC program, the variable
N% is used for this purpose. In comparison, the FORTRAN program uses
the variable M, which is defined to equal Log . For instance, M will be 2N
Chapter 12- The Fast Fourier Transform 235
TABLE 12-4
The Fast Fourier Transform in BASIC.
1000 'THE FAST FOURIER TRANSFORM
1010 'Upon entry, N% contains the number of points in the DFT, REX[ ] and
1020 'IMX[ ] contain the real and imaginary parts of the input. Upon return,
1030 'REX[ ] and IMX[ ] contain the DFT output. All signals run from 0 to N%-1.
1040 '
1050 PI = 3.14159265 'Set constants
1060 NM1% = N%-1
1070 ND2% = N%/2
1080 M% = CINT(LOG(N%)/LOG(2))
1090 J% = ND2%
1100 '
1110 FOR I% = 1 TO N%-2 'Bit reversal sorting
1120 IF I% >= J% THEN GOTO 1190
1130 TR = REX[J%]
1140 TI = IMX[J%]
1150 REX[J%] = REX[I%]
1160 IMX[J%] = IMX[I%]
1170 REX[I%] = TR
1180 IMX[I%] = TI
1190 K% = ND2%
1200 IF K% > J% THEN GOTO 1240
1210 J% = J%-K%
1220 K% = K%/2
1230 GOTO 1200
1240 J% = J%+K%
1250 NEXT I%
1260 '
1270 FOR L% = 1 TO M% 'Loop for each stage
1280 LE% = CINT(2^L%)
1290 LE2% = LE%/2
1300 UR = 1
1310 UI = 0
1320 SR = COS(PI/LE2%) 'Calculate sine & cosine values
1330 SI = -SIN(PI/LE2%)
1340 FOR J% = 1 TO LE2% 'Loop for each sub DFT
1350 JM1% = J%-1
1360 FOR I% = JM1% TO NM1% STEP LE% 'Loop for each butterfly
1370 IP% = I%+LE2%
1380 TR = REX[IP%]*UR - IMX[IP%]*UI 'Butterfly calculation
1390 TI = REX[IP%]*UI + IMX[IP%]*UR
1400 REX[IP%] = REX[I%]-TR
1410 IMX[IP%] = IMX[I%]-TI
1420 REX[I%] = REX[I%]+TR
1430 IMX[I%] = IMX[I%]+TI
1440 NEXT I%
1450 TR = UR
1460 UR = TR*SR - UI*SI
1470 UI = TR*SI + UI*SR
1480 NEXT J%
1490 NEXT L%
1500 '
1510 RETURN
236 The Scientist and Engineer's Guide to Digital Signal Processing
2000 'INVERSE FAST FOURIER TRANSFORM SUBROUTINE
2010 'Upon entry, N% contains the number of points in the IDFT, REX[ ] and
2020 'IMX[ ] contain the real and imaginary parts of the complex frequency domain.
2030 'Upon return, REX[ ] and IMX[ ] contain the complex time domain.
2040 'All signals run from 0 to N%-1.
2050 '
2060 FOR K% = 0 TO N%-1 'Change the sign of IMX[ ]
2070 IMX[K%] = -IMX[K%]
2080 NEXT K%
2090 '
2100 GOSUB 1000 'Calculate forward FFT (Table 12-3)
2110 '
2120 FOR I% = 0 TO N%-1 'Divide the time domain by N% and
2130 REX[I%] = REX[I%]/N% 'change the sign of IMX[ ]
2140 IMX[I%] = -IMX[I%]/N%
2150 NEXT I%
2160 '
2170 RETURN
TABLE 12-5
8 for a 256 point DFT, 12 for a 4096 point DFT, etc. The point is, the
programmer who writes an FFT subroutine has many options for interfacing
with the host program. Arrays that run from 1 to N, such as in the
FORTRAN program, are especially aggravating. Most of the DSP literature
(including this book) explains algorithms assuming the arrays run from
sample 0 to N&1 . For instance, if the arrays run from 1 to N, the symmetry
in the frequency domain is around points 1 and N/2% 1 , rather than points
0 and N/2 ,
Using the complex DFT to calculate the real DFT has another interesting
advantage. The complex DFT is more symmetrical between the time and
frequency domains than the real DFT. That is, the duality is stronger. Among
other things, this means that the Inverse DFT is nearly identical to the Forward
DFT. In fact, the easiest way to calculate an Inverse FFT is to calculate a
Forward FFT, and then adjust the data. Table 12-5 shows a subroutine for
calculating the Inverse FFT in this manner.
Suppose you copy one of these FFT algorithms into your computer program and
start it running. How do you know if it is operating properly? Two tricks are
commonly used for debugging. First, start with some arbitrary time domain
signal, such as from a random number generator, and run it through the FFT.
Next, run the resultant frequency spectrum through the Inverse FFT and
compare the result with the original signal. They should be identical, except
round-off noise (a few parts-per-million for single precision).
The second test of proper operation is that the signals have the correct
symmetry. When the imaginary part of the time domain signal is composed
of all zeros (the normal case), the frequency domain of the complex DFT
will be symmetrical around samples 0 and N/2 , as previously described.
Chapter 12- The Fast Fourier Transform 237
EQUATION 12-1
DFT execution time. The time required
to calculate a DFT by correlation is
proportional to the length of the DFT
squared.
ExecutionTime ’ kDFT N2
EQUATION 12-2
FFT execution time. The time required
to calculate a DFT using the FFT is
proportional to N multiplied by the
logarithm of N.
ExecutionTime ’ kFFT N log2N
Likewise, when this correct symmetry is present in the frequency domain, the
Inverse DFT will produce a time domain that has an imaginary part composes
of all zeros (plus round-off noise). These debugging techniques are essential
for using the FFT; become familiar with them.
Speed and Precision Comparisons
When the DFT is calculated by correlation (as in Table 12-2), the program uses
two nested loops, each running through N points. This means that the total
number of operations is proportional to N times N. The time to complete the
program is thus given by:
where N is the number of points in the DFT and kDFT is a constant of
proportionality. If the sine and cosine values are calculated within the nested
loops, kDFT is equal to about 25 microseconds on a Pentium at 100 MHz. If
you precalculate the sine and cosine values and store them in a look-up-table,
kDFT drops to about 7 microseconds. For example, a 1024 point DFT will
require about 25 seconds, or nearly 25 milliseconds per point. That's slow!
Using this same strategy we can derive the execution time for the FFT. The
time required for the bit reversal is negligible. In each of the Log stages 2N
there are N/2 butterfly computations. This means the execution time for the
program is approximated by:
The value of kFFT is about 10 microseconds on a 100 MHz Pentium system. A
1024 point FFT requires about 70 milliseconds to execute, or 70 microseconds
per point. This is more than 300 times faster than the DFT calculated by
correlation!
Not only is NLog less than , it increases much more slowly as N 2N N 2
becomes larger. For example, a 32 point FFT is about ten times faster than
the correlation method. However, a 4096 point FFT is one-thousand times
faster. For small values of N (say, 32 to 128), the FFT is important. For
large values of N (1024 and above), the FFT is absolutely critical. Figure
12-8 compares the execution times of the two algorithms in a graphical
form.
238 The Scientist and Engineer's Guide to Digital Signal Processing
Number points in DFT
8 16 32 64 128 256 512 1024 2048 4096
0.001
0.01
0.1
1
10
100
1000
FFT
correlation
correlation
w/LUT
FIGURE 12-8
Execution times for calculating the DFT. The
correlation method refers to the algorithm
described in Table 12-2. This method can be
made faster by precalculating the sine and
cosine values and storing them in a look-up
table (LUT). The FFT (Table 12-3) is the
fastest algorithm when the DFT is greater than
16 points long. The times shown are for a
Pentium processor at 100 MHz.
Execution time (seconds)
Number of points in DFT
16 32 64 128 256 512 1024
0
10
20
30
40
50
60
70
FFT
correlation
FIGURE 12-9
DFT precision. Since the FFT calculates the
DFT faster than the correlation method, it also
calculates it with less round-off error.
Error (parts per million)
The FFT has another advantage besides raw speed. The FFT is calculated more
precisely because the fewer number of calculations results in less round-off
error. This can be demonstrated by taking the FFT of an arbitrary signal, and
then running the frequency spectrum through an Inverse FFT. This
reconstructs the original time domain signal, except for the addition of roundoff
noise from the calculations. A single number characterizing this noise can
be obtained by calculating the standard deviation of the difference between the
two signals. For comparison, this same procedure can be repeated using a DFT
calculated by correlation, and a corresponding Inverse DFT. How does the
round-off noise of the FFT compare to the DFT by correlation? See for
yourself in Fig. 12-9.
Further Speed Increases
There are several techniques for making the FFT even faster; however, the
improvements are only about 20-40%. In one of these methods, the time
Chapter 12- The Fast Fourier Transform 239
4000 'INVERSE FFT FOR REAL SIGNALS
4010 'Upon entry, N% contains the number of points in the IDFT, REX[ ] and
4020 'IMX[ ] contain the real and imaginary parts of the frequency domain running from
4030 'index 0 to N%/2. The remaining samples in REX[ ] and IMX[ ] are ignored.
4040 'Upon return, REX[ ] contains the real time domain, IMX[ ] contains zeros.
4050 '
4060 '
4070 FOR K% = (N%/2+1) TO (N%-1) 'Make frequency domain symmetrical
4080 REX[K%] = REX[N%-K%] '(as in Table 12-1)
4090 IMX[K%] = -IMX[N%-K%]
4100 NEXT K%
4110 '
4120 FOR K% = 0 TO N%-1 'Add real and imaginary parts together
4130 REX[K%] = REX[K%]+IMX[K%]
4140 NEXT K%
4150 '
4160 GOSUB 3000 'Calculate forward real DFT (TABLE 12-6)
4170 '
4180 FOR I% = 0 TO N%-1 'Add real and imaginary parts together
4190 REX[I%] = (REX[I%]+IMX[I%])/N% 'and divide the time domain by N%
4200 IMX[I%] = 0
4210 NEXT I%
4220 '
4230 RETURN
TABLE 12-6
domain decomposition is stopped two stages early, when each signals is
composed of only four points. Instead of calculating the last two stages, highly
optimized code is used to jump directly into the frequency domain, using the
simplicity of four point sine and cosine waves.
Another popular algorithm eliminates the wasted calculations associated with
the imaginary part of the time domain being zero, and the frequency spectrum
being symmetrical. In other words, the FFT is modified to calculate the real
DFT, instead of the complex DFT. These algorithms are called the real FFT
and the real Inverse FFT (or similar names). Expect them to be about 30%
faster than the conventional FFT routines. Tables 12-6 and 12-7 show programs
for these algorithms.
There are two small disadvantages in using the real FFT. First, the code is
about twice as long. While your computer doesn't care, you must take the time
to convert someone else's program to run on your computer. Second, debugging
these programs is slightly harder because you cannot use symmetry as a check
for proper operation. These algorithms force the imaginary part of the time
domain to be zero, and the frequency domain to have left-right symmetry. For
debugging, check that these programs produce the same output as the
conventional FFT algorithms.
Figures 12-10 and 12-11 illustrate how the real FFT works. In Fig. 12-10,
(a) and (b) show a time domain signal that consists of a pulse in the real part,
and all zeros in the imaginary part. Figures (c) and (d) show the corresponding
frequency spectrum. As previously described, the frequency domain's real part
has an even symmetry around sample 0 and sample N/2 , while the imaginary
part has an odd symmetry around these same points.
240 The Scientist and Engineer's Guide to Digital Signal Processing
Sample number
0 16 32 48 64
-1
0
1
2
63
a. Real part
Freqeuncy
0 16 32 48
-8
-4
0
4
8
c. Real part (even symmetry)
63
Frequency
0 16 32 48
-8
-4
0
4
8
d. Imaginary part (odd symmetry)
63
Time Domain Frequency Domain
Sample number
0 16 32 48 64
-1
0
1
2
63
b. Imaginary part
FIGURE 12-10
Real part symmetry of the DFT.
Amplitude
Amplitude Amplitude
Amplitude
Now consider Fig. 12-11, where the pulse is in the imaginary part of the time
domain, and the real part is all zeros. The symmetry in the frequency domain
is reversed; the real part is odd, while the imaginary part is even. This
situation will be discussed in Chapter 29. For now, take it for granted that this
is how the complex DFT behaves.
What if there is a signal in both parts of the time domain? By additivity, the
frequency domain will be the sum of the two frequency spectra. Now the key
element: a frequency spectrum composed of these two types of symmetry can
be perfectly separated into the two component signals. This is achieved by the
even/odd decomposition discussed in Chapter 6. In other words, two real
DFT's can be calculated for the price of single FFT. One of the signals is
placed in the real part of the time domain, and the other signal is placed in the
imaginary part. After calculating the complex DFT (via the FFT, of course),
the spectra are separated using the even/odd decomposition. When two or more
signals need to be passed through the FFT, this technique reduces the execution
time by about 40%. The improvement isn't a full factor of two because of the
calculation time required for the even/odd decomposition. This is a relatively
simple technique with few pitfalls, nothing like writing an FFT routine from
scratch.
Chapter 12- The Fast Fourier Transform 241
Sample number
0 16 32 48 64
-1
0
1
2
63
a. Real part
Frequency
0 16 32 48
-8
-4
0
4
8
c. Real part (odd symmetry)
63
Frequency
0 16 32 48
-8
-4
0
4
8
d. Imaginary part (even symmetry)
63
Time Domain Frequency Domain
Sample number
0 16 32 48 64
-1
0
1
2
63
b. Imaginary part
FIGURE 12-11
Imaginary part symmetry of the DFT.
Amplitude
Amplitude Amplitude
Amplitude
The next step is to modify the algorithm to calculate a single DFT faster. It's
ugly, but here is how it is done. The input signal is broken in half by using an
interlaced decomposition. The N/2 even points are placed into the real part of
the time domain signal, while the N/2 odd points go into the imaginary part.
An N/2 point FFT is then calculated, requiring about one-half the time as an
N point FFT. The resulting frequency domain is then separated by the
even/odd decomposition, resulting in the frequency spectra of the two interlaced
time domain signals. These two frequency spectra are then combined into a
single spectrum, just as in the last synthesis stage of the FFT.
To close this chapter, consider that the FFT is to Digital Signal Processing
what the transistor is to electronics. It is a foundation of the technology;
everyone in the field knows its characteristics and how to use it. However,
only a small number of specialists really understand the details of the internal
workings.
242 The Scientist and Engineer's Guide to Digital Signal Processing
3000 'FFT FOR REAL SIGNALS
3010 'Upon entry, N% contains the number of points in the DFT, REX[ ] contains
3020 'the real input signal, while values in IMX[ ] are ignored. Upon return,
3030 'REX[ ] and IMX[ ] contain the DFT output. All signals run from 0 to N%-1.
3040 '
3050 NH% = N%/2-1 'Separate even and odd points
3060 FOR I% = 0 TO NH%
3070 REX(I%) = REX(2*I%)
3080 IMX(I%) = REX(2*I%+1)
3090 NEXT I%
3100 '
3110 N% = N%/2 'Calculate N%/2 point FFT
3120 GOSUB 1000 '(GOSUB 1000 is the FFT in Table 12-3)
3130 N% = N%*2
3140 '
3150 NM1% = N%-1 'Even/odd frequency domain decomposition
3160 ND2% = N%/2
3170 N4% = N%/4-1
3180 FOR I% = 1 TO N4%
3190 IM% = ND2%-I%
3200 IP2% = I%+ND2%
3210 IPM% = IM%+ND2%
3220 REX(IP2%) = (IMX(I%) + IMX(IM%))/2
3230 REX(IPM%) = REX(IP2%)
3240 IMX(IP2%) = -(REX(I%) - REX(IM%))/2
3250 IMX(IPM%) = -IMX(IP2%)
3260 REX(I%) = (REX(I%) + REX(IM%))/2
3270 REX(IM%) = REX(I%)
3280 IMX(I%) = (IMX(I%) - IMX(IM%))/2
3290 IMX(IM%) = -IMX(I%)
3300 NEXT I%
3310 REX(N%*3/4) = IMX(N%/4)
3320 REX(ND2%) = IMX(0)
3330 IMX(N%*3/4) = 0
3340 IMX(ND2%) = 0
3350 IMX(N%/4) = 0
3360 IMX(0) = 0
3370 '
3380 PI = 3.14159265 'Complete the last FFT stage
3390 L% = CINT(LOG(N%)/LOG(2))
3400 LE% = CINT(2^L%)
3410 LE2% = LE%/2
3420 UR = 1
3430 UI = 0
3440 SR = COS(PI/LE2%)
3450 SI = -SIN(PI/LE2%)
3460 FOR J% = 1 TO LE2%
3470 JM1% = J%-1
3480 FOR I% = JM1% TO NM1% STEP LE%
3490 IP% = I%+LE2%
3500 TR = REX[IP%]*UR - IMX[IP%]*UI
3510 TI = REX[IP%]*UI + IMX[IP%]*UR
3520 REX[IP%] = REX[I%]-TR
3530 IMX[IP%] = IMX[I%]-TI
3540 REX[I%] = REX[I%]+TR
3550 IMX[I%] = IMX[I%]+TI
3560 NEXT I%
3570 TR = UR
3580 UR = TR*SR - UI*SI
3590 UI = TR*SI + UI*SR
3600 NEXT J%
3610 RETURN TABLE 12-7
CHAPTER
15
EQUATION 15-1
Equation of the moving average filter. In
this equation, x[ ] is the input signal, y[ ] is
the output signal, and M is the number of
points used in the moving average. This
equation only uses points on one side of the
output sample being calculated.
y[i ] ’ 1
M
j M&1
j’ 0
x [ i %j ]
y [80] ’ x [80] % x [81] % x [82] % x [83] % x [84]
5
Moving Average Filters
The moving average is the most common filter in DSP, mainly because it is the easiest digital
filter to understand and use. In spite of its simplicity, the moving average filter is optimal for
a common task: reducing random noise while retaining a sharp step response. This makes it the
premier filter for time domain encoded signals. However, the moving average is the worst filter
for frequency domain encoded signals, with little ability to separate one band of frequencies from
another. Relatives of the moving average filter include the Gaussian, Blackman, and multiplepass
moving average. These have slightly better performance in the frequency domain, at the
expense of increased computation time.
Implementation by Convolution
As the name implies, the moving average filter operates by averaging a number
of points from the input signal to produce each point in the output signal. In
equation form, this is written:
Where x [ ] is the input signal, y [ ] is the output signal, and M is the number
of points in the average. For example, in a 5 point moving average filter, point
80 in the output signal is given by:
278 The Scientist and Engineer's Guide to Digital Signal Processing
y [80] ’ x [78] % x [79] % x [80] % x [81] % x [82]
5
100 'MOVING AVERAGE FILTER
110 'This program filters 5000 samples with a 101 point moving
120 'average filter, resulting in 4900 samples of filtered data.
130 '
140 DIM X[4999] 'X[ ] holds the input signal
150 DIM Y[4999] 'Y[ ] holds the output signal
160 '
170 GOSUB XXXX 'Mythical subroutine to load X[ ]
180 '
190 FOR I% = 50 TO 4949 'Loop for each point in the output signal
200 Y[I%] = 0 'Zero, so it can be used as an accumulator
210 FOR J% = -50 TO 50 'Calculate the summation
220 Y[I%] = Y[I%] + X(I%+J%]
230 NEXT J%
240 Y[I%] = Y[I%]/101 'Complete the average by dividing
250 NEXT I%
260 '
270 END
TABLE 15-1
As an alternative, the group of points from the input signal can be chosen
symmetrically around the output point:
This corresponds to changing the summation in Eq. 15-1 from: j ’ 0 to M&1 ,
to: j ’ &(M&1) /2 to (M&1) /2 . For instance, in an 11 point moving average
filter, the index, j, can run from 0 to 11 (one side averaging) or -5 to 5
(symmetrical averaging). Symmetrical averaging requires that M be an odd
number. Programming is slightly easier with the points on only one side;
however, this produces a relative shift between the input and output signals.
You should recognize that the moving average filter is a convolution using a
very simple filter kernel. For example, a 5 point filter has the filter kernel:
þ 0, 0, 1/5, 1/5, 1/5, 1/5, 1/5, 0, 0 þ . That is, the moving average filter is a
convolution of the input signal with a rectangular pulse having an area of one.
Table 15-1 shows a program to implement the moving average filter.
Noise Reduction vs. Step Response
Many scientists and engineers feel guilty about using the moving average filter.
Because it is so very simple, the moving average filter is often the first thing
tried when faced with a problem. Even if the problem is completely solved,
there is still the feeling that something more should be done. This situation is
truly ironic. Not only is the moving average filter very good for many
applications, it is optimal for a common problem, reducing random white noise
while keeping the sharpest step response.
Chapter 15- Moving Average Filters 279
Sample number
0 100 200 300 400 500
-1
0
1
2
a. Original signal
Sample number
0 100 200 300 400 500
-1
0
1
2
b. 11 point moving average
FIGURE 15-1
Example of a moving average filter. In (a), a
rectangular pulse is buried in random noise. In
(b) and (c), this signal is filtered with 11 and 51
point moving average filters, respectively. As
the number of points in the filter increases, the
noise becomes lower; however, the edges
becoming less sharp. The moving average filter
is the optimal solution for this problem,
providing the lowest noise possible for a given
edge sharpness.
Sample number
0 100 200 300 400 500
-1
0
1
2
c. 51 point moving average
Amplitude Amplitude
Amplitude
Figure 15-1 shows an example of how this works. The signal in (a) is a pulse
buried in random noise. In (b) and (c), the smoothing action of the moving
average filter decreases the amplitude of the random noise (good), but also
reduces the sharpness of the edges (bad). Of all the possible linear filters that
could be used, the moving average produces the lowest noise for a given edge
sharpness. The amount of noise reduction is equal to the square-root of the
number of points in the average. For example, a 100 point moving average
filter reduces the noise by a factor of 10.
To understand why the moving average if the best solution, imagine we want
to design a filter with a fixed edge sharpness. For example, let's assume we fix
the edge sharpness by specifying that there are eleven points in the rise of the
step response. This requires that the filter kernel have eleven points. The
optimization question is: how do we choose the eleven values in the filter
kernel to minimize the noise on the output signal? Since the noise we are
trying to reduce is random, none of the input points is special; each is just as
noisy as its neighbor. Therefore, it is useless to give preferential treatment to
any one of the input points by assigning it a larger coefficient in the filter
kernel. The lowest noise is obtained when all the input samples are treated
equally, i.e., the moving average filter. (Later in this chapter we show that
other filters are essentially as good. The point is, no filter is better than the
simple moving average).
280 The Scientist and Engineer's Guide to Digital Signal Processing
EQUATION 15-2
Frequency response of an M point moving
average filter. The frequency, f, runs between
0 and 0.5. For f ’ 0, use: H[ f ] ’ 1
H [ f ] ’ sin(Bf M )
M sin(Bf )
Frequency
0 0.1 0.2 0.3 0.4 0.5
0.0
0.2
0.4
0.6
0.8
1.0
1.2
3 point
11 point
31 point
FIGURE 15-2
Frequency response of the moving average
filter. The moving average is a very poor
low-pass filter, due to its slow roll-off and
poor stopband attenuation. These curves are
generated by Eq. 15-2.
Amplitude
Frequency Response
Figure 15-2 shows the frequency response of the moving average filter. It is
mathematically described by the Fourier transform of the rectangular pulse, as
discussed in Chapter 11:
The roll-off is very slow and the stopband attenuation is ghastly. Clearly, the
moving average filter cannot separate one band of frequencies from another.
Remember, good performance in the time domain results in poor performance
in the frequency domain, and vice versa. In short, the moving average is an
exceptionally good smoothing filter (the action in the time domain), but an
exceptionally bad low-pass filter (the action in the frequency domain).
Relatives of the Moving Average Filter
In a perfect world, filter designers would only have to deal with time
domain or frequency domain encoded information, but never a mixture of
the two in the same signal. Unfortunately, there are some applications
where both domains are simultaneously important. For instance, television
signals fall into this nasty category. Video information is encoded in the
time domain, that is, the shape of the waveform corresponds to the patterns
of brightness in the image. However, during transmission the video signal
is treated according to its frequency composition, such as its total
bandwidth, how the carrier waves for sound & color are added, elimination
& restoration of the DC component, etc. As another example, electromagnetic
interference is best understood in the frequency domain, even if
Chapter 15- Moving Average Filters 281
Sample number
0 6 12 18 24
0.0
0.1
0.2
2 pass
4 pass
1 pass
a. Filter kernel
Sample number
0 6 12 18 24
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1 pass
4 pass
2 pass
b. Step response
Frequency
0 0.1 0.2 0.3 0.4 0.5
-120
-100
-80
-60
-40
-20
0
20
40
1 pass
2 pass
4 pass
d. Frequency response (dB)
FIGURE 15-3
Characteristics of multiple-pass moving average filters. Figure (a) shows the filter kernels resulting from
passing a seven point moving average filter over the data once, twice and four times. Figure (b) shows the
corresponding step responses, while (c) and (d) show the corresponding frequency responses.
FFT
Integrate 20 Log( )
Amplitude Amplitude
Frequency
0 0.1 0.2 0.3 0.4 0.5
0.00
0.25
0.50
0.75
1.00
1.25
1 pass
2 pass
4 pass
c. Frequency response
Amplitude (dB) Amplitude
the signal's information is encoded in the time domain. For instance, the
temperature monitor in a scientific experiment might be contaminated with 60
hertz from the power lines, 30 kHz from a switching power supply, or 1320
kHz from a local AM radio station. Relatives of the moving average filter
have better frequency domain performance, and can be useful in these mixed
domain applications.
Multiple-pass moving average filters involve passing the input signal
through a moving average filter two or more times. Figure 15-3a shows the
overall filter kernel resulting from one, two and four passes. Two passes are
equivalent to using a triangular filter kernel (a rectangular filter kernel
convolved with itself). After four or more passes, the equivalent filter kernel
looks like a Gaussian (recall the Central Limit Theorem). As shown in (b),
multiple passes produce an "s" shaped step response, as compared to the
straight line of the single pass. The frequency responses in (c) and (d) are
given by Eq. 15-2 multiplied by itself for each pass. That is, each time domain
convolution results in a multiplication of the frequency spectra.
282 The Scientist and Engineer's Guide to Digital Signal Processing
Figure 15-4 shows the frequency response of two other relatives of the moving
average filter. When a pure Gaussian is used as a filter kernel, the frequency
response is also a Gaussian, as discussed in Chapter 11. The Gaussian is
important because it is the impulse response of many natural and manmade
systems. For example, a brief pulse of light entering a long fiber optic
transmission line will exit as a Gaussian pulse, due to the different paths taken
by the photons within the fiber. The Gaussian filter kernel is also used
extensively in image processing because it has unique properties that allow
fast two-dimensional convolutions (see Chapter 24). The second frequency
response in Fig. 15-4 corresponds to using a Blackman window as a filter
kernel. (The term window has no meaning here; it is simply part of the
accepted name of this curve). The exact shape of the Blackman window is
given in Chapter 16 (Eq. 16-2, Fig. 16-2); however, it looks much like a
Gaussian.
How are these relatives of the moving average filter better than the moving
average filter itself? Three ways: First, and most important, these filters have
better stopband attenuation than the moving average filter. Second, the filter
kernels taper to a smaller amplitude near the ends. Recall that each point in
the output signal is a weighted sum of a group of samples from the input. If the
filter kernel tapers, samples in the input signal that are farther away are given
less weight than those close by. Third, the step responses are smooth curves,
rather than the abrupt straight line of the moving average. These last two are
usually of limited benefit, although you might find applications where they are
genuine advantages.
The moving average filter and its relatives are all about the same at reducing
random noise while maintaining a sharp step response. The ambiguity lies in
how the risetime of the step response is measured. If the risetime is measured
from 0% to 100% of the step, the moving average filter is the best you can do,
as previously shown. In comparison, measuring the risetime from 10% to 90%
makes the Blackman window better than the moving average filter. The point
is, this is just theoretical squabbling; consider these filters equal in this
parameter.
The biggest difference in these filters is execution speed. Using a recursive
algorithm (described next), the moving average filter will run like lightning in
your computer. In fact, it is the fastest digital filter available. Multiple passes
of the moving average will be correspondingly slower, but still very quick. In
comparison, the Gaussian and Blackman filters are excruciatingly slow,
because they must use convolution. Think a factor of ten times the number of
points in the filter kernel (based on multiplication being about 10 times slower
than addition). For example, expect a 100 point Gaussian to be 1000 times
slower than a moving average using recursion.
Recursive Implementation
A tremendous advantage of the moving average filter is that it can be
implemented with an algorithm that is very fast. To understand this
Chapter 15- Moving Average Filters 283
FIGURE 15-4
Frequency response of the Blackman window
and Gaussian filter kernels. Both these filters
provide better stopband attenuation than the
moving average filter. This has no advantage in
removing random noise from time domain
encoded signals, but it can be useful in mixed
domain problems. The disadvantage of these
filters is that they must use convolution, a
terribly slow algorithm.
Frequency
0 0.1 0.2 0.3 0.4 0.5
-140
-120
-100
-80
-60
-40
-20
0
20
Gaussian
Blackman
Amplitude (dB)
y [50] ’ x [47] % x [48] % x [49] % x [50] % x [51] % x [52] % x [53]
y [51] ’ x [48] % x [49] % x [50] % x [51] % x [52] % x [53] % x [54]
y [51] ’ y [50] % x [54] & x [47]
EQUATION 15-3
Recursive implementation of the moving
average filter. In this equation, x[ ] is the
input signal, y[ ] is the output signal, M is the
number of points in the moving average (an
odd number). Before this equation can be
used, the first point in the signal must be
calculated using a standard summation.
y [i ] ’ y [i &1] % x [i %p] & x [i &q]
q ’ p % 1
where: p ’ (M&1) /2
algorithm, imagine passing an input signal, x [ ], through a seven point moving
average filter to form an output signal, y [ ]. Now look at how two adjacent
output points, y [50] and y [51], are calculated:
These are nearly the same calculation; points x [48] through x [53] must be
added for y [50], and again for y [51]. If y [50] has already been calculated, the
most efficient way to calculate y [51] is:
Once y [51] has been found using y [50], then y [52] can be calculated from
sample y [51], and so on. After the first point is calculated in y [ ], all of the
other points can be found with only a single addition and subtraction per point.
This can be expressed in the equation:
Notice that this equation use two sources of data to calculate each point in the
output: points from the input and previously calculated points from the output.
This is called a recursive equation, meaning that the result of one calculation
284 The Scientist and Engineer's Guide to Digital Signal Processing
100 'MOVING AVERAGE FILTER IMPLEMENTED BY RECURSION
110 'This program filters 5000 samples with a 101 point moving
120 'average filter, resulting in 4900 samples of filtered data.
130 'A double precision accumulator is used to prevent round-off drift.
140 '
150 DIM X[4999] 'X[ ] holds the input signal
160 DIM Y[4999] 'Y[ ] holds the output signal
170 DEFDBL ACC 'Define the variable ACC to be double precision
180 '
190 GOSUB XXXX 'Mythical subroutine to load X[ ]
200 '
210 ACC = 0 'Find Y[50] by averaging points X[0] to X[100]
220 FOR I% = 0 TO 100
230 ACC = ACC + X[I%]
240 NEXT I%
250 Y[[50] = ACC/101
260 ' 'Recursive moving average filter (Eq. 15-3)
270 FOR I% = 51 TO 4949
280 ACC = ACC + X[I%+50] - X[I%-51]
290 Y[I%] = ACC
300 NEXT I%
310 '
320 END
TABLE 15-2
CHAPTER
6 Convolution
Convolution is a mathematical way of combining two signals to form a third signal. It is the
single most important technique in Digital Signal Processing. Using the strategy of impulse
decomposition, systems are described by a signal called the impulse response. Convolution is
important because it relates the three signals of interest: the input signal, the output signal, and
the impulse response. This chapter presents convolution from two different viewpoints, called
the input side algorithm and the output side algorithm. Convolution provides the mathematical
framework for DSP; there is nothing more important in this book.
The Delta Function and Impulse Response
The previous chapter describes how a signal can be decomposed into a group
of components called impulses. An impulse is a signal composed of all zeros,
except a single nonzero point. In effect, impulse decomposition provides a way
to analyze signals one sample at a time. The previous chapter also presented
the fundamental concept of DSP: the input signal is decomposed into simple
additive components, each of these components is passed through a linear
system, and the resulting output components are synthesized (added). The
signal resulting from this divide-and-conquer procedure is identical to that
obtained by directly passing the original signal through the system. While
many different decompositions are possible, two form the backbone of signal
processing: impulse decomposition and Fourier decomposition. When impulse
decomposition is used, the procedure can be described by a mathematical
operation called convolution. In this chapter (and most of the following ones)
we will only be dealing with discrete signals. Convolution also applies to
continuous signals, but the mathematics is more complicated. We will look at
how continious signals are processed in Chapter 13.
Figure 6-1 defines two important terms used in DSP. The first is the delta
function, symbolized by the Greek letter delta, *[n]. The delta function is
a normalized impulse, that is, sample number zero has a value of one, while
108 The Scientist and Engineer's Guide to Digital Signal Processing
all other samples have a value of zero. For this reason, the delta function is
frequently called the unit impulse.
The second term defined in Fig. 6-1 is the impulse response. As the name
suggests, the impulse response is the signal that exits a system when a delta
function (unit impulse) is the input. If two systems are different in any way,
they will have different impulse responses. Just as the input and output signals
are often called x[n] and y[n] , the impulse response is usually given the
symbol, h[n]. Of course, this can be changed if a more descriptive name is
available, for instance, f [n] might be used to identify the impulse response of
a filter.
Any impulse can be represented as a shifted and scaled delta function.
Consider a signal, a[n] , composed of all zeros except sample number 8,
which has a value of -3. This is the same as a delta function shifted to the
right by 8 samples, and multiplied by -3. In equation form:
a[n] ’ &3*[n&8]. Make sure you understand this notation, it is used in
nearly all DSP equations.
If the input to a system is an impulse, such as &3*[n&8] , what is the system's
output? This is where the properties of homogeneity and shift invariance are
used. Scaling and shifting the input results in an identical scaling and shifting
of the output. If *[n] results in h[n] , it follows that &3*[n&8] results in
&3h[n&8] . In words, the output is a version of the impulse response that has
been shifted and scaled by the same amount as the delta function on the input.
If you know a system's impulse response, you immediately know how it will
react to any impulse.
Convolution
Let's summarize this way of understanding how a system changes an input
signal into an output signal. First, the input signal can be decomposed into a
set of impulses, each of which can be viewed as a scaled and shifted delta
function. Second, the output resulting from each impulse is a scaled and shifted
version of the impulse response. Third, the overall output signal can be found
by adding these scaled and shifted impulse responses. In other words, if we
know a system's impulse response, then we can calculate what the output will
be for any possible input signal. This means we know everything about the
system. There is nothing more that can be learned about a linear system's
characteristics. (However, in later chapters we will show that this information
can be represented in different forms).
The impulse response goes by a different name in some applications. If the
system being considered is a filter, the impulse response is called the filter
kernel, the convolution kernel, or simply, the kernel. In image processing,
the impulse response is called the point spread function. While these terms
are used in slightly different ways, they all mean the same thing, the signal
produced by a system when the input is a delta function.
Chapter 6- Convolution 109
System
-2 -1 0 1 2 3 4 5 6
-1
0
1
2
-2 -1 0 1 2 3 4 5 6
-1
0
1
2
*[n] h[n]
Delta Impulse
Response
Linear
Function
FIGURE 6-1
Definition of delta function and impulse response. The delta function is a normalized impulse. All of
its samples have a value of zero, except for sample number zero, which has a value of one. The Greek
letter delta, *[n] , is used to identify the delta function. The impulse response of a linear system, usually
denoted by h[n] , is the output of the system when the input is a delta function.
x[n] h[n] = y[n]
x[n] y[n]
Linear
System
h[n]
FIGURE 6-2
How convolution is used in DSP. The
output signal from a linear system is
equal to the input signal convolved
with the system's impulse response.
Convolution is denoted by a star when
writing equations.
Convolution is a formal mathematical operation, just as multiplication,
addition, and integration. Addition takes two numbers and produces a third
number, while convolution takes two signals and produces a third signal.
Convolution is used in the mathematics of many fields, such as probability and
statistics. In linear systems, convolution is used to describe the relationship
between three signals of interest: the input signal, the impulse response, and the
output signal.
Figure 6-2 shows the notation when convolution is used with linear systems.
An input signal, x[n] , enters a linear system with an impulse response, h[n] ,
resulting in an output signal, y[n] . In equation form: x[n] t h[n] ’ y[n] .
Expressed in words, the input signal convolved with the impulse response is
equal to the output signal. Just as addition is represented by the plus, +, and
multiplication by the cross, ×, convolution is represented by the star, t. It is
unfortunate that most programming languages also use the star to indicate
multiplication. A star in a computer program means multiplication, while a star
in an equation means convolution.
110 The Scientist and Engineer's Guide to Digital Signal Processing
Sample number
0 10 20 30 40 50 60 70 80 90 100 110
-2
-1
0
1
2
3
4
S
0 10 20 30
-0.25
0.00
0.25
0.50
0.75
1.00
1.25
S
0 10 20 30
-0.02
0.00
0.02
0.04
0.06
0.08
a. Low-pass Filter
b. High-pass Filter
Sample number
0 10 20 30 40 50 60 70 80
-2
-1
0
1
2
3
4
Sample number
0 10 20 30 40 50 60 70 80 90 100 110
-2
-1
0
1
2
3
4
Sample number
0 10 20 30 40 50 60 70 80
-2
-1
0
1
2
3
4
Sample number
Sample number
Input Signal Impulse Response Output Signal
Amplitude Amplitude
Amplitude Amplitude
Amplitude Amplitude
FIGURE 6-3
Examples of low-pass and high-pass filtering using convolution. In this example, the input signal
is a few cycles of a sine wave plus a slowly rising ramp. These two components are separated by
using properly selected impulse responses.
Figure 6-3 shows convolution being used for low-pass and high-pass filtering.
The example input signal is the sum of two components: three cycles of a sine
wave (representing a high frequency), plus a slowly rising ramp (composed of
low frequencies). In (a), the impulse response for the low-pass filter is a
smooth arch, resulting in only the slowly changing ramp waveform being
passed to the output. Similarly, the high-pass filter, (b), allows only the more
rapidly changing sinusoid to pass.
Figure 6-4 illustrates two additional examples of how convolution is used to
process signals. The inverting attenuator, (a), flips the signal top-for-bottom,
and reduces its amplitude. The discrete derivative (also called the first
difference), shown in (b), results in an output signal related to the slope of the
input signal.
Notice the lengths of the signals in Figs. 6-3 and 6-4. The input signals are
81 samples long, while each impulse response is composed of 31 samples.
In most DSP applications, the input signal is hundreds, thousands, or even
millions of samples in length. The impulse response is usually much shorter,
say, a few points to a few hundred points. The mathematics behind
convolution doesn't restrict how long these signals are. It does, however,
specify the length of the output signal. The length of the output signal is
Chapter 6- Convolution 111
S
0 10 20 30
-2.00
-1.00
0.00
1.00
2.00
S
0 10 20 30
-2.00
-1.00
0.00
1.00
2.00
a. Inverting Attenuator
b. Discrete Derivative
Sample number
0 10 20 30 40 50 60 70 80 90 100 110
-2
-1
0
1
2
3
4
Sample number
0 10 20 30 40 50 60 70 80 90 100 110
-2
-1
0
1
2
3
4
Sample number
0 10 20 30 40 50 60 70 80
-2
-1
0
1
2
3
4
Sample number
0 10 20 30 40 50 60 70 80
-2
-1
0
1
2
3
4
Input Signal Impulse Response Output Signal
Sample number
Sample number
Amplitude Amplitude
Amplitude Amplitude
Amplitude Amplitude
FIGURE 6-4
Examples of signals being processed using convolution. Many signal processing tasks use very
simple impulse responses. As shown in these examples, dramatic changes can be achieved with only
a few nonzero points.
equal to the length of the input signal, plus the length of the impulse
response, minus one. For the signals in Figs. 6-3 and 6-4, each output
signal is: 81% 31& 1 ’ 111 samples long. The input signal runs from sample
0 to 80, the impulse response from sample 0 to 30, and the output signal
from sample 0 to 110.
Now we come to the detailed mathematics of convolution. As used in Digital
Signal Processing, convolution can be understood in two separate ways. The
first looks at convolution from the viewpoint of the input signal. This
involves analyzing how each sample in the input signal contributes to many
points in the output signal. The second way looks at convolution from the
viewpoint of the output signal. This examines how each sample in the
output signal has received information from many points in the input signal.
Keep in mind that these two perspectives are different ways of thinking
about the same mathematical operation. The first viewpoint is important
because it provides a conceptual understanding of how convolution pertains
to DSP. The second viewpoint describes the mathematics of convolution.
This typifies one of the most difficult tasks you will encounter in DSP:
making your conceptual understanding fit with the jumble of mathematics
used to communicate the ideas.
112 The Scientist and Engineer's Guide to Digital Signal Processing
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
0 1 2 3 4 5 6 7 8
-3
-2
-1
0
1
2
3
0 1 2 3
-3
-2
-1
0
1
2
3
x[n] h[n] y[n]
FIGURE 6-5
Example convolution problem. A nine point input signal, convolved with a four point impulse response, results
in a twelve point output signal. Each point in the input signal contributes a scaled and shifted impulse response
to the output signal. These nine scaled and shifted impulse responses are shown in Fig. 6-6.
Now examine sample x[8] , the last point in the input signal. This sample is at
index number eight, and has a value of -0.5. As shown in the lower-right graph
of Fig. 6-6, x[8] results in an impulse response that has been shifted to the right
by eight points and multiplied by -0.5. Place holding zeros have been added at
points 0-7. Lastly, examine the effect of points x[0] and x[7] . Both these
samples have a value of zero, and therefore produce output components
consisting of all zeros.
The Input Side Algorithm
Figure 6-5 shows a simple convolution problem: a 9 point input signal, x[n] ,
is passed through a system with a 4 point impulse response, h[n] , resulting
in a 9% 4& 1 ’ 12 point output signal, y[n] . In mathematical terms, x[n] is
convolved with h[n] to produce y[n] . This first viewpoint of convolution is
based on the fundamental concept of DSP: decompose the input, pass the
components through the system, and synthesize the output. In this example,
each of the nine samples in the input signal will contribute a scaled and
shifted version of the impulse response to the output signal. These nine
signals are shown in Fig. 6-6. Adding these nine signals produces the
output signal, y[n] .
Let's look at several of these nine signals in detail. We will start with sample
number four in the input signal, i.e., x[4] . This sample is at index number four,
and has a value of 1.4. When the signal is decomposed, this turns into an
impulse represented as: 1.4*[n&4]. After passing through the system, the
resulting output component will be: 1.4 h[n&4]. This signal is shown in the
center box of the nine signals in Fig. 6-6. Notice that this is the impulse
response, h[n] , multiplied by 1.4, and shifted four samples to the right. Zeros
have been added at samples 0-3 and at samples 8-11 to serve as place holders.
To make this more clear, Fig. 6-6 uses squares to represent the data points that
come from the shifted and scaled impulse response, and diamonds for the added
zeros.
Chapter 6- Convolution 113
FIGURE 6-6
Output signal components for the convolution in Fig. 6-5. In these signals, each point that results from a scaled
and shifted impulse response is represented by a square marker. The remaining data points, represented by
diamonds, are zeros that have been added as place holders.
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
contribution
from x[ ] h[n- ]
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
contribution
from x[ ] h[n- ]
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
contribution
from x[ ] h[n- ]
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
contribution
from x[ ] h[n- ]
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
contribution
from x[ ] h[n- ]
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
contribution
from x[ ] h[n- ]
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
contribution
from x[ ] h[n- ]
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
contribution
from x[ ] h[n- ]
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
contribution
from x[ ] h[n- ]
0 0 1 1 2 2
3 3 4 4 5 5
6 6 7 7 8 8
In this example, x[n] is a nine point signal and h[n] is a four point signal. In
our next example, shown in Fig. 6-7, we will reverse the situation by making x[n]
a four point signal, and h[n] a nine point signal. The same two waveforms are
used, they are just swapped. As shown by the output signal components, the
four samples in x[n] result in four shifted and scaled versions of the nine point
impulse response. Just as before, leading and trailing zeros are added as place
holders.
But wait just one moment! The output signal in Fig. 6-7 is identical to the
output signal in Fig. 6-5. This isn't a mistake, but an important property.
Convolution is commutative: a[n]tb[n] ’ b[n]ta[n] . The mathematics does
not care which is the input signal and which is the impulse response, only
that two signals are convolved with each other. Although the mathematics
may allow it, exchanging the two signals has no physical meaning in system
theory. The input signal and impulse response are two totally different
things and exchanging them doesn't make sense. What the commutative
property provides is a mathematical tool for manipulating equations to
achieve various results.
114 The Scientist and Engineer's Guide to Digital Signal Processing
TABLE 6-1
100 'CONVOLUTION USING THE INPUT SIDE ALGORITHM
110 '
120 DIM X[80] 'The input signal, 81 points
130 DIM H[30] 'The impulse response, 31 points
140 DIM Y[110] 'The output signal, 111 points
150 '
160 GOSUB XXXX 'Mythical subroutine to load X[ ] and H[ ]
170 '
180 FOR I% = 0 TO 110 'Zero the output array
190 Y(I%) = 0
200 NEXT I%
210 '
220 FOR I% = 0 TO 80 'Loop for each point in X[ ]
230 FOR J% = 0 TO 30 'Loop for each point in H[ ]
240 Y[I%+J%] = Y[I%+J%] + X[I%]tH[J%]
250 NEXT J%
260 NEXT I% '(remember, t is multiplication in programs!)
270 '
280 GOSUB XXXX 'Mythical subroutine to store Y[ ]
290 '
300 END
A program for calculating convolutions using the input side algorithm is shown
in Table 6-1. Remember, the programs in this book are meant to convey
algorithms in the simplest form, even at the expense of good programming
style. For instance, all of the input and output is handled in mythical
subroutines (lines 160 and 280), meaning we do not define how these
operations are conducted. Do not skip over these programs; they are a key
part of the material and you need to understand them in detail.
The program convolves an 81 point input signal, held in array X[ ], with a 31
point impulse response, held in array H[ ], resulting in a 111 point output
signal, held in array Y[ ]. These are the same lengths shown in Figs. 6-3 and
6-4. Notice that the names of these arrays use upper case letters. This is a
violation of the naming conventions previously discussed, because upper case
letters are reserved for frequency domain signals. Unfortunately, the simple
BASIC used in this book does not allow lower case variable names. Also
notice that line 240 uses a star for multiplication. Remember, a star in a
program means multiplication, while a star in an equation means convolution.
A star in text (such as documentation or program comments) can mean either.
The mythical subroutine in line 160 places the input signal into X[ ] and the
impulse response into H[ ]. Lines 180-200 set all of the values in Y[ ] to
zero. This is necessary because Y[ ] is used as an accumulator to sum the
output components as they are calculated. Lines 220 to 260 are the heart of
the program. The FOR statement in line 220 controls a loop that steps through
each point in the input signal, X[ ]. For each sample in the input signal, an
inner loop (lines 230-250) calculates a scaled and shifted version of the
impulse response, and adds it to the array accumulating the output signal,
Y[ ]. This nested loop structure (one loop within another loop) is a key
characteristic of convolution programs; become familiar with it.
Chapter 6- Convolution 115
FIGURE 6-7
A second example of convolution. The waveforms for the input signal and impulse response
are exchanged from the example of Fig. 6-5. Since convolution is commutative, the output
signals for the two examples are identical.
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
0 1 2 3 4 5 6 7 8
-3
-2
-1
0
1
2
3
0 1 2 3
-3
-2
-1
0
1
2
3
x[n] h[n] y[n]
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
contribution
from x[ ] h[n- ]
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
contribution
from x[ ] h[n- ]
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
contribution
from x[ ] h[n- ]
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
contribution
from x[ ] h[n- ]
0 0 1 1
2 2 3 3
Output signal components
Keeping the indexing straight in line 240 can drive you crazy! Let's say we
are halfway through the execution of this program, so that we have just
begun action on sample X[40], i.e., I% = 40. The inner loop runs through
each point in the impulse response doing three things. First, the impulse
response is scaled by multiplying it by the value of the input sample. If this
were the only action taken by the inner loop, line 240 could be written,
Y[J%] = X[40]tH[J%]. Second, the scaled impulse is shifted 40 samples
to the right by adding this number to the index used in the output signal.
This second action would change line 240 to: Y[40+J%] = X[40]tH[J%].
Third, Y[ ] must accumulate (synthesize) all the signals resulting from each
sample in the input signal. Therefore, the new information must be added
to the information that is already in the array. This results in the final
command: Y[40+J%] = Y[40+J%] + X[40]tH[J%]. Study this carefully;
it is very confusing, but very important.
116 The Scientist and Engineer's Guide to Digital Signal Processing
The Output Side Algorithm
The first viewpoint of convolution analyzes how each sample in the input
signal affects many samples in the output signal. In this second viewpoint,
we reverse this by looking at individual samples in the output signal, and
finding the contributing points from the input. This is important from both
mathematical and practical standpoints. Suppose that we are given some
input signal and impulse response, and want to find the convolution of the
two. The most straightforward method would be to write a program that
loops through the output signal, calculating one sample on each loop cycle.
Likewise, equations are written in the form: y[n] ’ some combination of
other variables. That is, sample n in the output signal is equal to some
combination of the many values in the input signal and impulse response.
This requires a knowledge of how each sample in the output signal can be
calculated independently of all other samples in the output signal. The
output side algorithm provides this information.
Let's look at an example of how a single point in the output signal is influenced
by several points from the input. The example point we will use is y[6] in Fig.
6-5. This point is equal to the sum of all the sixth points in the nine output
components, shown in Fig. 6-6. Now, look closely at these nine output
components and identify which can affect y[6] . That is, find which of these
nine signals contains a nonzero sample at the sixth position. Five of the output
components only have added zeros (the diamond markers) at the sixth sample,
and can therefore be ignored. Only four of the output components are capable
of having a nonzero value in the sixth position. These are the output
components generated from the input samples: x[3], x[4], x[5], and x[6] . By
adding the sixth sample from each of these output components, y[6] is
determined as: y[6] ’ x[3]h[3] % x[4]h[2] % x[5]h[1] % x[6]h[0] . That is, four
samples from the input signal are multiplied by the four samples in the impulse
response, and the products added.
Figure 6-8 illustrates the output side algorithm as a convolution machine, a
flow diagram of how convolution occurs. Think of the input signal, x[n] , and
the output signal, y[n] , as fixed on the page. The convolution machine,
everything inside the dashed box, is free to move left and right as needed. The
convolution machine is positioned so that its output is aligned with the output
sample being calculated. Four samples from the input signal fall into the inputs
of the convolution machine. These values are multiplied by the indicated
samples in the impulse response, and the products are added. This produces the
value for the output signal, which drops into its proper place. For example,
y[6] i s s h own b e i n g c a l c u l a t e d f r om t h e f o u r i n p u t s amp l e s :
x[3], x[4], x[5], and x[6] .
To calculate y[7] , the convolution machine moves one sample to the right. This
results in another four samples entering the machine, x[4] through x[7] , and the
value for y[7] dropping into the proper place. This process is repeated for all
points in the output signal needing to be calculated.
Chapter 6- Convolution 117
0 1 2 3 4 5 6 7 8
-3
-2
-1
0
1
2
3
-3 -2 -1 0
3.0
2.0
1.0
0.0
1.0
2.0
3.0
x[n]
y[n]
h[n] 0
-1
-2
-3
2
3
1
(flipped)
FIGURE 6-8
The convolution machine. This is a flow diagram showing how each sample in the output signal
is influenced by the input signal and impulse response. See the text for details.
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
The arrangement of the impulse response inside the convolution machine is
very important. The impulse response is flipped left-for-right. This places
sample number zero on the right, and increasingly positive sample numbers
running to the left. Compare this to the normal impulse response in Fig. 6-5
to understand the geometry of this flip. Why is this flip needed? It simply
falls out of the mathematics. The impulse response describes how each point
in the input signal affects the output signal. This results in each point in the
output signal being affected by points in the input signal weighted by a flipped
impulse response.
118 The Scientist and Engineer's Guide to Digital Signal Processing
FIGURE 6-9
The convolution machine in action. Figures (a) through (d) show the convolution machine
set to calculate four different output signal samples, y[0], y[3], y[8], and y[11].
0 1 2 3 4 5 6 7 8
-3
-2
-1
0
1
2
3
-3 -2 -1 0
3.0
2.0
1.0
0.0
1.0
2.0
3.0
x[n]
y[n]
h[n] 0
-1
-2
-3
2
3
1
(flipped)
a. Set to calculate y[0]
0 1 2 3 4 5 6 7 8
-3
-2
-1
0
1
2
3
-3 -2 -1 0
3.0
2.0
1.0
0.0
1.0
2.0
3.0
x[n]
y[n]
h[n] 0
-1
-2
-3
2
3
1
(flipped)
b. Set to calculate y[3]
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
Figure 6-9 shows the convolution machine being used to calculate several
samples in the output signal. This diagram also illustrates a real nuisance in
convolution. In (a), the convolution machine is located fully to the left with its
output aimed at y[0] . In this position, it is trying to receive input from
samples: x[&3], x[&2], x[&1], and x[0] . The problem is, three of these samples:
x[&3], x[&2], and x[&1] , do not exist! This same dilemma arises in (d), where
the convolution machine tries to accept samples to the right of the defined input
signal, points x[9], x[10], and x[11] .
One way to handle this problem is by inventing the nonexistent samples. This
involves adding samples to the ends of the input signal, with each of the added
samples having a value of zero. This is called padding the signal with zeros.
Instead of trying to access a nonexistent value, the convolution machine
receives a sample that has a value of zero. Since this zero is eliminated
during the multiplication, the result is mathematically the same as ignoring the
nonexistent inputs.
Chapter 6- Convolution 119
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
0 1 2 3 4 5 6 7 8 9 10 11
-3
-2
-1
0
1
2
3
0 1 2 3 4 5 6 7 8
-3
-2
-1
0
1
2
3
-3 -2 -1 0
3.0
2.0
1.0
0.0
1.0
2.0
3.0
x[n]
y[n]
h[n] 0
-1
-2
-3
2
3
1
(flipped)
c. Set to calculate y[8]
0 1 2 3 4 5 6 7 8
-3
-2
-1
0
1
2
3
-3 -2 -1 0
3.0
2.0
1.0
0.0
1.0
2.0
3.0
x[n]
y[n]
h[n] 0
-1
-2
-3
2
3
1
(flipped)
d. Set to calculate y[11]
Figure 6-9 (continued)
The important part is that the far left and far right samples in the output signal
are based on incomplete information. In DSP jargon, the impulse response
is not fully immersed in the input signal. If the impulse response is M
points in length, the first and last M&1 samples in the output signal are based
on less information than the samples between. This is analogous to an
electronic circuit requiring a certain amount of time to stabilize after the power
is applied. The difference is that this transient is easy to ignore in electronics,
but very prominent in DSP.
Figure 6-10 shows an example of the trouble these end effects can cause. The
input signal is a sine wave plus a DC component. The desire is to remove the
DC part of the signal, while leaving the sine wave intact. This calls for a highpass
filter, such as the impulse response shown in the figure. The problem is,
the first and last 30 points are a mess! The shape of these end regions can be
understood by imagining the input signal padded with 30 zeros on the left side,
samples x[&1] through x[&30] , and 30 zeros on the right, samples x[81]
through x[110] . The output signal can then be viewed as a filtered version
of this longer waveform. These "end effect" problems are widespread in
120 The Scientist and Engineer's Guide to Digital Signal Processing
EQUATION 6-1
The convolution summation. This is the
formal definition of convolution, written in
the shorthand: y [n] ’ x [n] t h[n]. In this
equation, h[n] is an M point signal with
indexes running from 0 to M-1.
y [i ] ’ jM&1
j ’0
h[ j ] x [i&j ]
DSP. As a general rule, expect that the beginning and ending samples in
processed signals will be quite useless.
Now the math. Using the convolution machine as a guideline, we can write the
standard equation for convolution. If x[n] is an N point signal running from 0
to N-1, and h[n] is an M point signal running from 0 to M-1, the convolution
of the two: y[n] ’ x[n] t h[n], is an N+M-1 point signal running from 0 to
N+M-2, given by:
This equation is called the convolution sum. It allows each point in the
output signal to be calculated independently of all other points in the output
signal. The index, i, determines which sample in the output signal is being
calculated, and therefore corresponds to the left-right position of the
convolution machine. In computer programs performing convolution, a loop
makes this index run through each sample in the output signal. To
calculate one of the output samples, the index, j, is used inside of the
convolution machine. As j runs through 0 to M-1, each sample in the
impulse response, h[ j], is multiplied by the proper sample from the input
signal, x[i& j ]. All these products are added to produce the output sample
being calculated. Study Eq. 6-1 until you fully understand how it is
implemented by the convolution machine. Much of DSP is based on this
equation. (Don't be confused by the n in y[n] ’ x[n] t h[n]. This is merely
a place holder to indicate that some variable is the index into the array.
Sometimes the equations are written: y[ ] ’ x[ ] t h[ ], just to avoid having
to bring in a meaningless symbol).
Table 6-2 shows a program for performing convolutions using the output side
algorithm, a direct use of Eq. 6-1. This program produces the same output
signal as the program for the input side algorithm, shown previously in Table
6-1. Notice the main difference between these two programs: the input side
algorithm loops through each sample in the input signal (line 220 of Table 6-
1), while the output side algorithm loops through each sample in the output
signal (line 180 of Table 6-2).
Here is a detailed operation of this program. The FOR-NEXT loop in lines 180
to 250 steps through each sample in the output signal, using I% as the index.
For each of these values, an inner loop, composed of lines 200 to 230,
calculates the value of the output sample, Y[I%]. The value of Y[I%] is set
to zero in line 190, allowing it to accumulate the products inside of the
convolution machine. The FOR-NEXT loop in lines 200 to 240 provide a
direct implementation of Eq. 6-1. The index, J%, steps through each
Chapter 6- Convolution 121
sample in the impulse response. Line 230 provides the multiplication of each
sample in the impulse response, H[J%], with the appropriate sample from the
input signal, X[I%-J%], and adds the result to the accumulator.
In line 230, the sample taken from the input signal is: X[I%-J%]. Lines 210
and 220 prevent this from being outside the defined array, X[0] to X[80]. In
other words, this program handles undefined samples in the input signal by
ignoring them. Another alternative would be to define the input signal's array
from X[-30] to X[110], allowing 30 zeros to be padded on each side of the true
data. As a third alternative, the FOR-NEXT loop in line 180 could be changed
to run from 30 to 80, rather than 0 to 110. That is, the program would only
calculate the samples in the output signal where the impulse response is fully
immersed in the input signal. The important thing is that you must use one of
these three techniques. If you don't, the program will crash when it tries to read
the out-of-bounds data.
S
0 10 20 30
-0.5
0.0
0.5
1.0
1.5
Sample number
0 10 20 30 40 50 60 70 80
-4
-2
0
2
4
Sample number
0 10 20 30 40 50 60 70 80 90 100 110
-4
-2
0
2
4
Input signal Impulse response Output signal
unusable usable unusable
Sample number
Amplitude
Amplitude
Amplitude
FIGURE 6-10
End effects in convolution. When an input signal is convolved with an M point impulse response,
the first and last M-1 points in the output signal may not be usable. In this example, the impulse
response is a high-pass filter used to remove the DC component from the input signal.
100 'CONVOLUTION USING THE OUTPUT SIDE ALGORITHM
110 '
120 DIM X[80] 'The input signal, 81 points
130 DIM H[30] 'The impulse response, 31 points
140 DIM Y[110] 'The output signal, 111 points
150 '
160 GOSUB XXXX 'Mythical subroutine to load X[ ] and H[ ]
170 '
180 FOR I% = 0 TO 110 'Loop for each point in Y[ ]
190 Y[I%] = 0 'Zero the sample in the output array
200 FOR J% = 0 TO 30 'Loop for each point in H[ ]
210 IF (I%-J% < 0) THEN GOTO 240
220 IF (I%-J% > 80) THEN GOTO 240
230 Y(I%) = Y(I%) + H(J%) t X(I%-J%)
240 NEXT J%
250 NEXT I%
260 '
270 GOSUB XXXX 'Mythical subroutine to store Y[ ]
280 '
290 END
TABLE 6-2
122 The Scientist and Engineer's Guide to Digital Signal Processing
The Sum of Weighted Inputs
The characteristics of a linear system are completely described by its impulse
response. This is the basis of the input side algorithm: each point in the input
signal contributes a scaled and shifted version of the impulse response to the
output signal. The mathematical consequences of this lead to the output side
algorithm: each point in the output signal receives a contribution from many
points in the input signal, multiplied by a flipped impulse response. While this
is all true, it doesn't provide the full story on why convolution is important in
signal processing.
Look back at the convolution machine in Fig. 6-8, and ignore that the signal
inside the dotted box is an impulse response. Think of it as a set of weighing
coefficients that happen to be embedded in the flow diagram. In this view,
each sample in the output signal is equal to a sum of weighted inputs. Each
sample in the output is influenced by a region of samples in the input signal,
as determined by what the weighing coefficients are chosen to be. For
example, imagine there are ten weighing coefficients, each with a value of onetenth.
This makes each sample in the output signal the average of ten samples
from the input.
Taking this further, the weighing coefficients do not need to be restricted to the
left side of the output sample being calculated. For instance, Fig. 6-8 shows y[6]
being calculated from: x[3], x[4], x[5], and x[6] . Viewing the convolution
machine as a sum of weighted inputs, the weighing coefficients could be chosen
symmetrically around the output sample. For example, y[6] might receive
contributions from: x[4], x[5], x[6], x[7], and x[8] . Using the same indexing
notation as in Fig. 6-8, the weighing coefficients for these five inputs would be
held in: h[2], h[1], h[0], h[&1], and h[&2] . In other words, the impulse
response that corresponds to our selection of symmetrical weighing coefficients
requires the use of negative indexes. We will return to this in the next chapter.
Mathematically, there is only one concept here: convolution as defined by Eq.
6-1. However, science and engineering problems approach this single concept
from two distinct directions. Sometimes you will want to think of a system in
terms of what its impulse response looks like. Other times you will understand
the system as a set of weighing coefficients. You need to become familiar with
both views, and how to toggle between them.
Digital Signal Processors
Digital Signal Processing is carried out by mathematical operations. In comparison, word
processing and similar programs merely rearrange stored data. This means that computers
designed for business and other general applications are not optimized for algorithms such as
digital filtering and Fourier analysis. Digital Signal Processors are microprocessors specifically
designed to handle Digital Signal Processing tasks. These devices have seen tremendous growth
in the last decade, finding use in everything from cellular telephones to advanced scientific
instruments. In fact, hardware engineers use "DSP" to mean Digital Signal Processor, just as
algorithm developers use "DSP" to mean Digital Signal Processing. This chapter looks at how
DSPs are different from other types of microprocessors, how to decide if a DSP is right for your
application, and how to get started in this exciting new field. In the next chapter we will take a
more detailed look at one of these sophisticated products: the Analog Devices SHARC® family.
How DSPs are Different from Other Microprocessors
In the 1960s it was predicted that artificial intelligence would revolutionize the
way humans interact with computers and other machines. It was believed that
by the end of the century we would have robots cleaning our houses, computers
driving our cars, and voice interfaces controlling the storage and retrieval of
information. This hasn't happened; these abstract tasks are far more
complicated than expected, and very difficult to carry out with the step-by-step
logic provided by digital computers.
However, the last forty years have shown that computers are extremely capable
in two broad areas, (1) data manipulation, such as word processing and
database management, and (2) mathematical calculation, used in science,
engineering, and Digital Signal Processing. All microprocessors can perform
both tasks; however, it is difficult (expensive) to make a device that is
optimized for both. There are technical tradeoffs in the hardware design, such
as the size of the instruction set and how interrupts are handled. Even
504 The Scientist and Engineer's Guide to Digital Signal Processing
Data Manipulation Math Calculation
Word processing, database
management, spread sheets,
operating sytems, etc.
Digital Signal Processing,
motion control, scientific and
engineering simulations, etc.
data movement (A º B)
value testing (If A=B then ...)
addition (A+B=C )
multiplication (A×B=C )
Typical
Applications
Main
Operations
FIGURE 28-1
Data manipulation versus mathematical calculation. Digital computers are useful for two general
tasks: data manipulation and mathematical calculation. Data manipulation is based on moving
data and testing inequalities, while mathematical calculation uses multiplication and addition.
more important, there are marketing issues involved: development and
manufacturing cost, competitive position, product lifetime, and so on. As a
broad generalization, these factors have made traditional microprocessors, such
as the Pentium®, primarily directed at data manipulation. Similarly, DSPs are
designed to perform the mathematical calculations needed in Digital Signal
Processing.
Figure 28-1 lists the most important differences between these two
categories. Data manipulation involves storing and sorting information.
For instance, consider a word processing program. The basic task is to
store the information (typed in by the operator), organize the information
(cut and paste, spell checking, page layout, etc.), and then retrieve the
information (such as saving the document on a floppy disk or printing it
with a laser printer). These tasks are accomplished by moving data from
one location to another, and testing for inequalities (A=B, AB THEN ...). Second, if the two entries
are not in alphabetical order, switch them so that they are (AWB). When
this two step process is repeated many times on all adjacent pairs, the list
will eventually become alphabetized.
As another example, consider how a document is printed from a word
processor. The computer continually tests the input device (mouse or keyboard)
for the binary code that indicates "print the document." When this code is
detected, the program moves the data from the computer's memory to the
printer. Here we have the same two basic operations: moving data and
inequality testing. While mathematics is occasionally used in this type of
Chapter 28- Digital Signal Processors 505
y[n] ’ a0 x[n] % a1 x[n&1] % a2 x[n&2] % a3 x[n&3] % a4 x[n&4] % þ
×a0
×a1
×a2
×a3
×a4
×a5
×a6
×a7
Input Signal, x[ ]
Output signal, y[ ]
x[n]
x[n-1]
x[n-2]
x[n-3]
y[n]
FIGURE 28-2
FIR digital filter. In FIR filtering, each
sample in the output signal, y[n], is found
by multiplying samples from the input
signal, x[n], x[n-1], x[n-2], ..., by the filter
kernel coefficients, a0, a1, a2, a3 ..., and
summing the products.
application, it is infrequent and does not significantly affect the overall
execution speed.
In comparison, the execution speed of most DSP algorithms is limited almost
completely by the number of multiplications and additions required. For
example, Fig. 28-2 shows the implementation of an FIR digital filter, the most
common DSP technique. Using the standard notation, the input signal is
referred to by x[ ], while the output signal is denoted by y[ ]. Our task is to
calculate the sample at location n in the output signal, i.e., y[n] . An FIR filter
performs this calculation by multiplying appropriate samples from the input
signal by a group of coefficients, denoted by: a , and then adding 0, a1, a2, a3,þ
the products. In equation form, y[n] is found by:
This is simply saying that the input signal has been convolved with a filter
kernel (i.e., an impulse response) consisting of: a . Depending on 0, a1, a2, a3,þ
the application, there may only be a few coefficients in the filter kernel, or
many thousands. While there is some data transfer and inequality evaluation
in this algorithm, such as to keep track of the intermediate results and control
the loops, the math operations dominate the execution time.
506 The Scientist and Engineer's Guide to Digital Signal Processing
In addition to preforming mathematical calculations very rapidly, DSPs must
also have a predictable execution time. Suppose you launch your desktop
computer on some task, say, converting a word-processing document from one
form to another. It doesn't matter if the processing takes ten milliseconds or
ten seconds; you simply wait for the action to be completed before you give the
computer its next assignment.
In comparison, most DSPs are used in applications where the processing is
continuous, not having a defined start or end. For instance, consider an
engineer designing a DSP system for an audio signal, such as a hearing aid.
If the digital signal is being received at 20,000 samples per second, the DSP
must be able to maintain a sustained throughput of 20,000 samples per second.
However, there are important reasons not to make it any faster than necessary.
As the speed increases, so does the cost, the power consumption, the design
difficulty, and so on. This makes an accurate knowledge of the execution time
critical for selecting the proper device, as well as the algorithms that can be
applied.
Circular Buffering
Digital Signal Processors are designed to quickly carry out FIR filters and
similar techniques. To understand the hardware, we must first understand the
algorithms. In this section we will make a detailed list of the steps needed to
implement an FIR filter. In the next section we will see how DSPs are
designed to perform these steps as efficiently as possible.
To start, we need to distinguish between off-line processing and real-time
processing. In off-line processing, the entire input signal resides in the
computer at the same time. For example, a geophysicist might use a
seismometer to record the ground movement during an earthquake. After the
shaking is over, the information may be read into a computer and analyzed in
some way. Another example of off-line processing is medical imaging, such
as computed tomography and MRI. The data set is acquired while the patient
is inside the machine, but the image reconstruction may be delayed until a later
time. The key point is that all of the information is simultaneously available
to the processing program. This is common in scientific research and
engineering, but not in consumer products. Off-line processing is the realm of
personal computers and mainframes.
In real-time processing, the output signal is produced at the same time that the
input signal is being acquired. For example, this is needed in telephone
communication, hearing aids, and radar. These applications must have the
information immediately available, although it can be delayed by a short
amount. For instance, a 10 millisecond delay in a telephone call cannot be
detected by the speaker or listener. Likewise, it makes no difference if a
radar signal is delayed by a few seconds before being displayed to the
operator. Real-time applications input a sample, perform the algorithm, and
output a sample, over-and-over. Alternatively, they may input a group
Chapter 28- Digital Signal Processors 507
x[n-3]
x[n-2]
x[n-1]
x[n]
x[n-6]
x[n-5]
x[n-4]
x[n-7]
20040
20041
20042
20043
20044
20045
20046
20047
20048
20049
-0.225767
-0.269847
-0.228918
-0.113940
-0.048679
-0.222977
-0.371370
-0.462791
ADDRESS VALUE
newest sample
oldest sample
MEMORY STORED
x[n-4]
x[n-3]
x[n-2]
x[n-1]
x[n-7]
x[n-6]
x[n-5]
x[n]
20040
20041
20042
20043
20044
20045
20046
20047
20048
20049
-0.225767
-0.269847
-0.228918
-0.113940
-0.062222
-0.222977
-0.371370
-0.462791
ADDRESS VALUE
newest sample
oldest sample
MEMORY STORED
a. Circular buffer at some instant b. Circular buffer after next sample
FIGURE 28-3
Circular buffer operation. Circular buffers are used to store the most recent values of a continually
updated signal. This illustration shows how an eight sample circular buffer might appear at some
instant in time (a), and how it would appear one sample later (b).
of samples, perform the algorithm, and output a group of samples. This is the
world of Digital Signal Processors.
Now look back at Fig. 28-2 and imagine that this is an FIR filter being
implemented in real-time. To calculate the output sample, we must have access
to a certain number of the most recent samples from the input. For example,
suppose we use eight coefficients in this filter, a . This means we 0, a1, þ a7
must know the value of the eight most recent samples from the input signal,
x[n], x[n&1], þ x[n&7] . These eight samples must be stored in memory and
continually updated as new samples are acquired. What is the best way to
manage these stored samples? The answer is circular buffering.
Figure 28-3 illustrates an eight sample circular buffer. We have placed this
circular buffer in eight consecutive memory locations, 20041 to 20048. Figure
(a) shows how the eight samples from the input might be stored at one
particular instant in time, while (b) shows the changes after the next sample
is acquired. The idea of circular buffering is that the end of this linear array is
connected to its beginning; memory location 20041 is viewed as being next to
20048, just as 20044 is next to 20045. You keep track of the array by a
pointer (a variable whose value is an address) that indicates where the most
recent sample resides. For instance, in (a) the pointer contains the address
20044, while in (b) it contains 20045. When a new sample is acquired, it
replaces the oldest sample in the array, and the pointer is moved one address
ahead. Circular buffers are efficient because only one value needs to be
changed when a new sample is acquired.
Four parameters are needed to manage a circular buffer. First, there must be
a pointer that indicates the start of the circular buffer in memory (in this
example, 20041). Second, there must be a pointer indicating the end of the
508 The Scientist and Engineer's Guide to Digital Signal Processing
1. Obtain a sample with the ADC; generate an interrupt
2. Detect and manage the interrupt
3. Move the sample into the input signal's circular buffer
4. Update the pointer for the input signal's circular buffer
5. Zero the accumulator
6. Control the loop through each of the coefficients
7. Fetch the coefficient from the coefficient's circular buffer
8. Update the pointer for the coefficient's circular buffer
9. Fetch the sample from the input signal's circular buffer
10. Update the pointer for the input signal's circular buffer
11. Multiply the coefficient by the sample
12. Add the product to the accumulator
13. Move the output sample (accumulator) to a holding buffer
14. Move the output sample from the holding buffer to the DAC
TABLE 28-1
FIR filter steps.
array (e.g., 20048), or a variable that holds its length (e.g., 8). Third, the step
size of the memory addressing must be specified. In Fig. 28-3 the step size is
one, for example: address 20043 contains one sample, address 20044 contains
the next sample, and so on. This is frequently not the case. For instance, the
addressing may refer to bytes, and each sample may require two or four bytes
to hold its value. In these cases, the step size would need to be two or four,
respectively.
These three values define the size and configuration of the circular buffer, and
will not change during the program operation. The fourth value, the pointer to
the most recent sample, must be modified as each new sample is acquired. In
other words, there must be program logic that controls how this fourth value is
updated based on the value of the first three values. While this logic is quite
simple, it must be very fast. This is the whole point of this discussion; DSPs
should be optimized at managing circular buffers to achieve the highest
possible execution speed.
As an aside, circular buffering is also useful in off-line processing. Consider
a program where both the input and the output signals are completely contained
in memory. Circular buffering isn't needed for a convolution calculation,
because every sample can be immediately accessed. However, many algorithms
are implemented in stages, with an intermediate signal being created between
each stage. For instance, a recursive filter carried out as a series of biquads
operates in this way. The brute force method is to store the entire length of
each intermediate signal in memory. Circular buffering provides another
option: store only those intermediate samples needed for the calculation at
hand. This reduces the required amount of memory, at the expense of a more
complicated algorithm. The important idea is that circular buffers are useful
for off-line processing, but critical for real-time applications.
Now we can look at the steps needed to implement an FIR filter using circular
buffers for both the input signal and the coefficients. This list may seem trivial
and overexamined- it's not! The efficient handling of these individual tasks is
what separates a DSP from a traditional microprocessor. For each new sample,
all the following steps need to be taken:
Chapter 28- Digital Signal Processors 509
The goal is to make these steps execute quickly. Since steps 6-12 will be
repeated many times (once for each coefficient in the filter), special attention
must be given to these operations. Traditional microprocessors must generally
carry out these 14 steps in serial (one after another), while DSPs are designed
to perform them in parallel. In some cases, all of the operations within the
loop (steps 6-12) can be completed in a single clock cycle. Let's look at the
internal architecture that allows this magnificent performance.
Architecture of the Digital Signal Processor
One of the biggest bottlenecks in executing DSP algorithms is transferring
information to and from memory. This includes data, such as samples from the
input signal and the filter coefficients, as well as program instructions, the
binary codes that go into the program sequencer. For example, suppose we
need to multiply two numbers that reside somewhere in memory. To do this,
we must fetch three binary values from memory, the numbers to be multiplied,
plus the program instruction describing what to do.
Figure 28-4a shows how this seemingly simple task is done in a traditional
microprocessor. This is often called a Von Neumann architecture, after the
brilliant American mathematician John Von Neumann (1903-1957). Von
Neumann guided the mathematics of many important discoveries of the early
twentieth century. His many achievements include: developing the concept of
a stored program computer, formalizing the mathematics of quantum mechanics,
and work on the atomic bomb. If it was new and exciting, Von Neumann was
there!
As shown in (a), a Von Neumann architecture contains a single memory and a
single bus for transferring data into and out of the central processing unit
(CPU). Multiplying two numbers requires at least three clock cycles, one to
transfer each of the three numbers over the bus from the memory to the CPU.
We don't count the time to transfer the result back to memory, because we
assume that it remains in the CPU for additional manipulation (such as the sum
of products in an FIR filter). The Von Neumann design is quite satisfactory
when you are content to execute all of the required tasks in serial. In fact,
most computers today are of the Von Neumann design. We only need other
architectures when very fast processing is required, and we are willing to pay
the price of increased complexity.
This leads us to the Harvard architecture, shown in (b). This is named for
the work done at Harvard University in the 1940s under the leadership of
Howard Aiken (1900-1973). As shown in this illustration, Aiken insisted on
separate memories for data and program instructions, with separate buses for
each. Since the buses operate independently, program instructions and data can
be fetched at the same time, improving the speed over the single bus design.
Most present day DSPs use this dual bus architecture.
Figure (c) illustrates the next level of sophistication, the Super Harvard
Architecture. This term was coined by Analog Devices to describe the
510 The Scientist and Engineer's Guide to Digital Signal Processing
internal operation of their ADSP-2106x and new ADSP-211xx families of
Digital Signal Processors. These are called SHARC® DSPs, a contraction of
the longer term, Super Harvard ARChitecture. The idea is to build upon the
Harvard architecture by adding features to improve the throughput. While the
SHARC DSPs are optimized in dozens of ways, two areas are important
enough to be included in Fig. 28-4c: an instruction cache, and an I/O
controller.
First, let's look at how the instruction cache improves the performance of the
Harvard architecture. A handicap of the basic Harvard design is that the data
memory bus is busier than the program memory bus. When two numbers are
multiplied, two binary values (the numbers) must be passed over the data
memory bus, while only one binary value (the program instruction) is passed
over the program memory bus. To improve upon this situation, we start by
relocating part of the "data" to program memory. For instance, we might place
the filter coefficients in program memory, while keeping the input signal in data
memory. (This relocated data is called "secondary data" in the illustration).
At first glance, this doesn't seem to help the situation; now we must transfer
one value over the data memory bus (the input signal sample), but two values
over the program memory bus (the program instruction and the coefficient). In
fact, if we were executing random instructions, this situation would be no better
at all.
However, DSP algorithms generally spend most of their execution time in
loops, such as instructions 6-12 of Table 28-1. This means that the same set
of program instructions will continually pass from program memory to the
CPU. The Super Harvard architecture takes advantage of this situation by
including an instruction cache in the CPU. This is a small memory that
contains about 32 of the most recent program instructions. The first time
through a loop, the program instructions must be passed over the program
memory bus. This results in slower operation because of the conflict with the
coefficients that must also be fetched along this path. However, on additional
executions of the loop, the program instructions can be pulled from the
instruction cache. This means that all of the memory to CPU information
transfers can be accomplished in a single cycle: the sample from the input
signal comes over the data memory bus, the coefficient comes over the program
memory bus, and the program instruction comes from the instruction cache. In
the jargon of the field, this efficient transfer of data is called a high memoryaccess
bandwidth.
Figure 28-5 presents a more detailed view of the SHARC architecture,
showing the I/O controller connected to data memory. This is how the
signals enter and exit the system. For instance, the SHARC DSPs provides
both serial and parallel communications ports. These are extremely high
speed connections. For example, at a 40 MHz clock speed, there are two
serial ports that operate at 40 Mbits/second each, while six parallel ports
each provide a 40 Mbytes/second data transfer. When all six parallel
ports are used together, the data transfer rate is an incredible 240
Mbytes/second.
Chapter 28- Digital Signal Processors 511
Memory
data and
instructions
Program
Memory
Data
Memory
instructions and
secondary data data only
Program
Memory
Data
Memory
instructions only data only
a. Von Neumann Architecture ( )
b. Harvard Architecture ( )
c. Super Harvard Architecture ( )
address bus CPU
data bus
PM address bus
PM data bus
PM address bus
PM data bus
DM address bus
DM data bus
CPU
DM address bus
DM data bus
single memory
dual memory
dual memory, instruction cache, I/O controller
Instruction
Cache
CPU
I/O
Controller
data
FIGURE 28-4
Microprocessor architecture. The Von Neumann architecture
uses a single memory to hold both data and instructions. In
comparison, the Harvard architecture uses separate memories
for data and instructions, providing higher speed. The Super
Harvard Architecture improves upon the Harvard design by
adding an instruction cache and a dedicated I/O controller.
This is fast enough to transfer the entire text of this book in only 2
milliseconds! Just as important, dedicated hardware allows these data streams
to be transferred directly into memory (Direct Memory Access, or DMA),
without having to pass through the CPU's registers. In other words, tasks 1 &
14 on our list happen independently and simultaneously with the other tasks;
no cycles are stolen from the CPU. The main buses (program memory bus and
data memory bus) are also accessible from outside the chip, providing an
additional interface to off-chip memory and peripherals. This allows the
SHARC DSPs to use a four Gigaword (16 Gbyte) memory, accessible at 40
Mwords/second (160 Mbytes/second), for 32 bit data. Wow!
This type of high speed I/O is a key characteristic of DSPs. The overriding
goal is to move the data in, perform the math, and move the data out before the
next sample is available. Everything else is secondary. Some DSPs have onboard
analog-to-digital and digital-to-analog converters, a feature called mixed
signal. However, all DSPs can interface with external converters through
serial or parallel ports.
512 The Scientist and Engineer's Guide to Digital Signal Processing
Now let's look inside the CPU. At the top of the diagram are two blocks
labeled Data Address Generator (DAG), one for each of the two
memories. These control the addresses sent to the program and data
memories, specifying where the information is to be read from or written to.
In simpler microprocessors this task is handled as an inherent part of the
program sequencer, and is quite transparent to the programmer. However,
DSPs are designed to operate with circular buffers, and benefit from the
extra hardware to manage them efficiently. This avoids needing to use
precious CPU clock cycles to keep track of how the data are stored. For
instance, in the SHARC DSPs, each of the two DAGs can control eight
circular buffers. This means that each DAG holds 32 variables (4 per
buffer), plus the required logic.
Why so many circular buffers? Some DSP algorithms are best carried out in
stages. For instance, IIR filters are more stable if implemented as a cascade
of biquads (a stage containing two poles and up to two zeros). Multiple stages
require multiple circular buffers for the fastest operation. The DAGs in the
SHARC DSPs are also designed to efficiently carry out the Fast Fourier
transform. In this mode, the DAGs are configured to generate bit-reversed
addresses into the circular buffers, a necessary part of the FFT algorithm. In
addition, an abundance of circular buffers greatly simplifies DSP code
generation- both for the human programmer as well as high-level language
compilers, such as C.
The data register section of the CPU is used in the same way as in traditional
microprocessors. In the ADSP-2106x SHARC DSPs, there are 16 general
purpose registers of 40 bits each. These can hold intermediate calculations,
prepare data for the math processor, serve as a buffer for data transfer, hold
flags for program control, and so on. If needed, these registers can also be
used to control loops and counters; however, the SHARC DSPs have extra
hardware registers to carry out many of these functions.
The math processing is broken into three sections, a multiplier, an
arithmetic logic unit (ALU), and a barrel shifter. The multiplier takes
the values from two registers, multiplies them, and places the result into
another register. The ALU performs addition, subtraction, absolute value,
logical operations (AND, OR, XOR, NOT), conversion between fixed and
floating point formats, and similar functions. Elementary binary operations
are carried out by the barrel shifter, such as shifting, rotating, extracting
and depositing segments, and so on. A powerful feature of the SHARC
family is that the multiplier and the ALU can be accessed in parallel. In a
single clock cycle, data from registers 0-7 can be passed to the multiplier,
data from registers 8-15 can be passed to the ALU, and the two results
returned to any of the 16 registers.
There are also many important features of the SHARC family architecture that
aren't shown in this simplified illustration. For instance, an 80 bit
accumulator is built into the multiplier to reduce the round-off error
associated with multiple fixed-point math operations. Another interesting
Chapter 28- Digital Signal Processors 513
Program
Memory
Data
Memory
instructions and
secondary data data only
Address
PM Data
Generator
Address
DM Data
Generator
Data
Registers
Muliplier
ALU
Shifter
PM address bus DM address bus
PM data bus DM data bus
Program Sequencer
Instruction
Cache
I/O Controller
(DMA)
High speed I/O
(serial, parallel,
ADC, DAC, etc.)
FIGURE 28-5
Typical DSP architecture. Digital Signal Processors are designed to implement tasks in parallel. This
simplified diagram is of the Analog Devices SHARC DSP. Compare this architecture with the tasks
needed to implement an FIR filter, as listed in Table 28-1. All of the steps within the loop can be
executed in a single clock cycle.
feature is the use of shadow registers for all the CPU's key registers. These
are duplicate registers that can be switched with their counterparts in a single
clock cycle. They are used for fast context switching, the ability to handle
interrupts quickly. When an interrupt occurs in traditional microprocessors, all
the internal data must be saved before the interrupt can be handled. This
usually involves pushing all of the occupied registers onto the stack, one at a
time. In comparison, an interrupt in the SHARC family is handled by moving
the internal data into the shadow registers in a single clock cycle. When the
interrupt routine is completed, the registers are just as quickly restored. This
feature allows step 4 on our list (managing the sample-ready interrupt) to be
handled very quickly and efficiently.
Now we come to the critical performance of the architecture, how many of the
operations within the loop (steps 6-12 of Table 28-1) can be carried out at the
same time. Because of its highly parallel nature, the SHARC DSP can
simultaneously carry out all of these tasks. Specifically, within a single clock
cycle, it can perform a multiply (step 11), an addition (step 12), two data
moves (steps 7 and 9), update two circular buffer pointers (steps 8 and 10), and
514 The Scientist and Engineer's Guide to Digital Signal Processing
control the loop (step 6). There will be extra clock cycles associated with
beginning and ending the loop (steps 3, 4, 5 and 13, plus moving initial values
into place); however, these tasks are also handled very efficiently. If the loop
is executed more than a few times, this overhead will be negligible. As an
example, suppose you write an efficient FIR filter program using 100
coefficients. You can expect it to require about 105 to 110 clock cycles per
sample to execute (i.e., 100 coefficient loops plus overhead). This is very
impressive; a traditional microprocessor requires many thousands of clock
cycles for this algorithm.
Fixed versus Floating Point
Digital Signal Processing can be divided into two categories, fixed point and
floating point. These refer to the format used to store and manipulate
numbers within the devices. Fixed point DSPs usually represent each number
with a minimum of 16 bits, although a different length can be used. For
instance, Motorola manufactures a family of fixed point DSPs that use 24 bits.
There are four common ways that these 216 ’ 65,536 possible bit patterns can
represent a number. In unsigned integer, the stored number can take on any
integer value from 0 to 65,535. Similarly, signed integer uses two's
complement to make the range include negative numbers, from -32,768 to
32,767. With unsigned fraction notation, the 65,536 levels are spread
uniformly between 0 and 1. Lastly, the signed fraction format allows
negative numbers, equally spaced between -1 and 1.
In comparison, floating point DSPs typically use a minimum of 32 bits to
store each value. This results in many more bit patterns than for fixed
point, 232 ’ 4,294,967,296 to be exact. A key feature of floating point notation
is that the represented numbers are not uniformly spaced. In the most common
format (ANSI/IEEE Std. 754-1985), the largest and smallest numbers are
±3.4×1038 and ±1.2×10 , respectively. The represented values are unequally &38
spaced between these two extremes, such that the gap between any two
numbers is about ten-million times smaller than the value of the numbers.
This is important because it places large gaps between large numbers, but small
gaps between small numbers. Floating point notation is discussed in more
detail in Chapter 4.
All floating point DSPs can also handle fixed point numbers, a necessity to
implement counters, loops, and signals coming from the ADC and going to the
DAC. However, this doesn't mean that fixed point math will be carried out as
quickly as the floating point operations; it depends on the internal architecture.
For instance, the SHARC DSPs are optimized for both floating point and fixed
point operations, and executes them with equal efficiency. For this reason, the
SHARC devices are often referred to as "32-bit DSPs," rather than just
"Floating Point."
Figure 28-6 illustrates the primary trade-offs between fixed and floating point
DSPs. In Chapter 3 we stressed that fixed point arithmetic is much
Chapter 28- Digital Signal Processors 515
Precision Product Cost
Development Time
Floating Point Fixed Point
FIGURE 28-6 Dynamic Range
Fixed versus floating point. Fixed point DSPs
are generally cheaper, while floating point
devices have better precision, higher dynamic
range, and a shorter development cycle.
faster than floating point in general purpose computers. However, with DSPs
the speed is about the same, a result of the hardware being highly optimized for
math operations. The internal architecture of a floating point DSP is more
complicated than for a fixed point device. All the registers and data buses must
be 32 bits wide instead of only 16; the multiplier and ALU must be able to
quickly perform floating point arithmetic, the instruction set must be larger (so
that they can handle both floating and fixed point numbers), and so on.
Floating point (32 bit) has better precision and a higher dynamic range than
fixed point (16 bit) . In addition, floating point programs often have a shorter
development cycle, since the programmer doesn't generally need to worry about
issues such as overflow, underflow, and round-off error.
On the other hand, fixed point DSPs have traditionally been cheaper than
floating point devices. Nothing changes more rapidly than the price of
electronics; anything you find in a book will be out-of-date before it is
printed. Nevertheless, cost is a key factor in understanding how DSPs are
evolving, and we need to give you a general idea. When this book was
completed in 1999, fixed point DSPs sold for between $5 and $100, while
floating point devices were in the range of $10 to $300. This difference in
cost can be viewed as a measure of the relative complexity between the
devices. If you want to find out what the prices are today, you need to look
today.
Now let's turn our attention to performance; what can a 32-bit floating point
system do that a 16-bit fixed point can't? The answer to this question is
signal-to-noise ratio. Suppose we store a number in a 32 bit floating point
format. As previously mentioned, the gap between this number and its adjacent
neighbor is about one ten-millionth of the value of the number. To store the
number, it must be round up or down by a maximum of one-half the gap size.
In other words, each time we store a number in floating point notation, we add
noise to the signal.
The same thing happens when a number is stored as a 16-bit fixed point value,
except that the added noise is much worse. This is because the gaps between
adjacent numbers are much larger. For instance, suppose we store the number
10,000 as a signed integer (running from -32,768 to 32,767). The gap between
numbers is one ten-thousandth of the value of the number we are storing. If we
516 The Scientist and Engineer's Guide to Digital Signal Processing
want to store the number 1000, the gap between numbers is only one onethousandth
of the value.
Noise in signals is usually represented by its standard deviation. This was
discussed in detail in Chapter 2. For here, the important fact is that the
standard deviation of this quantization noise is about one-third of the gap
size. This means that the signal-to-noise ratio for storing a floating point
number is about 30 million to one, while for a fixed point number it is only
about ten-thousand to one. In other words, floating point has roughly 30,000
times less quantization noise than fixed point.
This brings up an important way that DSPs are different from traditional
microprocessors. Suppose we implement an FIR filter in fixed point. To do
this, we loop through each coefficient, multiply it by the appropriate sample
from the input signal, and add the product to an accumulator. Here's the
problem. In traditional microprocessors, this accumulator is just another 16 bit
fixed point variable. To avoid overflow, we need to scale the values being
added, and will correspondingly add quantization noise on each step. In the
worst case, this quantization noise will simply add, greatly lowering the signalto-
noise ratio of the system. For instance, in a 500 coefficient FIR filter, the
noise on each output sample may be 500 times the noise on each input sample.
The signal-to-noise ratio of ten-thousand to one has dropped to a ghastly
twenty to one. Although this is an extreme case, it illustrates the main point:
when many operations are carried out on each sample, it's bad, really bad. See
Chapter 3 for more details.
DSPs handle this problem by using an extended precision accumulator.
This is a special register that has 2-3 times as many bits as the other memory
locations. For example, in a 16 bit DSP it may have 32 to 40 bits, while in the
SHARC DSPs it contains 80 bits for fixed point use. This extended range
virtually eliminates round-off noise while the accumulation is in progress. The
only round-off error suffered is when the accumulator is scaled and stored in
the 16 bit memory. This strategy works very well, although it does limit how
some algorithms must be carried out. In comparison, floating point has such
low quantization noise that these techniques are usually not necessary.
In addition to having lower quantization noise, floating point systems are also
easier to develop algorithms for. Most DSP techniques are based on repeated
multiplications and additions. In fixed point, the possibility of an overflow or
underflow needs to be considered after each operation. The programmer needs
to continually understand the amplitude of the numbers, how the quantization
errors are accumulating, and what scaling needs to take place. In comparison,
these issues do not arise in floating point; the numbers take care of themselves
(except in rare cases).
To give you a better understanding of this issue, Fig. 28-7 shows a table from
the SHARC user manual. This describes the ways that multiplication can be
carried out for both fixed and floating point formats. First, look at how
floating point numbers can be multiplied; there is only one way! That
Chapter 28- Digital Signal Processors 517
Rn
MRF
MRB
Rn
Rn
MRF
MRB
Rn
Rn
MRF
MRB
Rn
Rn
MRF
MRB
Rn
Rn
MRF
MRB
MRF
MRB
MRxF
MRxB
Rn
= MRF
= MRB
= MRF
= MRB
= MRF
= MRB
= MRF
= MRB
= SAT MRF
= SAT MRB
= SAT MRF
= SAT MRB
= RND MRF
= RND MRB
= RND MRF
= RND MRB
= 0
= Rn
= MRxF
MRxB
= Rx * Ry
+ Rx * Ry
- Rx * Ry
S S F
U U I
FR
S
S
(SI)
(UI)
(SF)
(UF)
(SF)
(UF)
)
S F
U U I
FR
)
S F
U U I
FR
)
Fn = Fx * Fy
Fixed Point Floating Point
(
(
(
FIGURE 28-7
Fixed versus floating point instructions. These are the multiplication instructions used in
the SHARC DSPs. While only a single command is needed for floating point, many
options are needed for fixed point. See the text for an explanation of these options.
is, Fn = Fx * Fy, where Fn, Fx, and Fy are any of the 16 data registers. It
could not be any simpler. In comparison, look at all the possible commands for
fixed point multiplication. These are the many options needed to efficiently
handle the problems of round-off, scaling, and format.
In Fig. 28-7, Rn, Rx, and Ry refer to any of the 16 data registers, and MRF
and MRB are 80 bit accumulators. The vertical lines indicate options. For
instance, the top-left entry in this table means that all the following are valid
commands: Rn = Rx * Ry, MRF = Rx * Ry, and MRB = Rx * Ry. In other
words, the value of any two registers can be multiplied and placed into another
register, or into one of the extended precision accumulators. This table also
shows that the numbers may be either signed or unsigned (S or U), and may be
fractional or integer (F or I). The RND and SAT options are ways of
controlling rounding and register overflow.
518 The Scientist and Engineer's Guide to Digital Signal Processing
There are other details and options in the table, but they are not important for
our present discussion. The important idea is that the fixed point programmer
must understand dozens of ways to carry out the very basic task of
multiplication. In contrast, the floating point programmer can spend his time
concentrating on the algorithm.
Given these tradeoffs between fixed and floating point, how do you choose
which to use? Here are some things to consider. First, look at how many bits
are used in the ADC and DAC. In many applications, 12-14 bits per sample
is the crossover for using fixed versus floating point. For instance, television
and other video signals typically use 8 bit ADC and DAC, and the precision of
fixed point is acceptable. In comparison, professional audio applications can
sample with as high as 20 or 24 bits, and almost certainly need floating point
to capture the large dynamic range.
The next thing to look at is the complexity of the algorithm that will be run.
If it is relatively simple, think fixed point; if it is more complicated, think
floating point. For example, FIR filtering and other operations in the time
domain only require a few dozen lines of code, making them suitable for fixed
point. In contrast, frequency domain algorithms, such as spectral analysis and
FFT convolution, are very detailed and can be much more difficult to program.
While they can be written in fixed point, the development time will be greatly
reduced if floating point is used.
Lastly, think about the money: how important is the cost of the product, and
how important is the cost of the development? When fixed point is chosen, the
cost of the product will be reduced, but the development cost will probably be
higher due to the more difficult algorithms. In the reverse manner, floating
point will generally result in a quicker and cheaper development cycle, but a
more expensive final product.
Figure 28-8 shows some of the major trends in DSPs. Figure (a) illustrates the
impact that Digital Signal Processors have had on the embedded market. These
are applications that use a microprocessor to directly operate and control some
larger system, such as a cellular telephone, microwave oven, or automotive
instrument display panel. The name "microcontroller" is often used in
referring to these devices, to distinguish them from the microprocessors used
in personal computers. As shown in (a), about 38% of embedded designers
have already started using DSPs, and another 49% are considering the switch.
The high throughput and computational power of DSPs often makes them an
ideal choice for embedded designs.
As illustrated in (b), about twice as many engineers currently use fixed
point as use floating point DSPs. However, this depends greatly on the
application. Fixed point is more popular in competitive consumer products
where the cost of the electronics must be kept very low. A good example
of this is cellular telephones. When you are in competition to sell millions
of your product, a cost difference of only a few dollars can be the difference
between success and failure. In comparison, floating point is more common
when greater performance is needed and cost is not important. For
Chapter 28- Digital Signal Processors 519
No Plans
Floating Point
Next Year
in 2000
Next
Fixed Point
Migrate
Migrate
Migrate
Design
b. DSP currently used
c. Migration to floating point
Considering
Changed
Considering
Have Already
Not
a. Changing from uProc to DSP
FIGURE 28-8
Major trends in DSPs. As illustrated in (a), about 38% of embedded designers have already switched from
conventional microprocessors to DSPs, and another 49% are considering the change. In (b), about twice as
many engineers use fixed point as use floating point DSPs. This is mainly driven by consumer products that
must have low cost electronics, such as cellular telephones. However, as shown in (c), floating point is the
fastest growing segment; over one-half of engineers currently using 16 bit devices plan to migrate to floating
point DSPs
instance, suppose you are designing a medical imaging system, such a
computed tomography scanner. Only a few hundred of the model will ever
be sold, at a price of several hundred-thousand dollars each. For this
application, the cost of the DSP is insignificant, but the performance is
critical. In spite of the larger number of fixed point DSPs being used, the
floating point market is the fastest growing segment. As shown in (c), over
one-half of engineers using 16-bits devices plan to migrate to floating point
at some time in the near future.
Before leaving this topic, we should reemphasize that floating point and fixed
point usually use 32 bits and 16 bits, respectively, but not always. For
520 The Scientist and Engineer's Guide to Digital Signal Processing
instance, the SHARC family can represent numbers in 32-bit fixed point, a
mode that is common in digital audio applications. This makes the 232
quantization levels spaced uniformly over a relatively small range, say,
between -1 and 1. In comparison, floating point notation places the 232
quantization levels logarithmically over a huge range, typically ±3.4×1038.
This gives 32-bit fixed point better precision, that is, the quantization error on
any one sample will be lower. However, 32-bit floating point has a higher
dynamic range, meaning there is a greater difference between the largest
number and the smallest number that can be represented.
C versus Assembly
DSPs are programmed in the same languages as other scientific and engineering
applications, usually assembly or C. Programs written in assembly can execute
faster, while programs written in C are easier to develop and maintain. In
traditional applications, such as programs run on personal computers and
mainframes, C is almost always the first choice. If assembly is used at all, it
is restricted to short subroutines that must run with the utmost speed. This is
shown graphically in Fig. 28-9a; for every traditional programmer that works
in assembly, there are approximately ten that use C.
However, DSP programs are different from traditional software tasks in two
important respects. First, the programs are usually much shorter, say, onehundred
lines versus ten-thousand lines. Second, the execution speed is
often a critical part of the application. After all, that's why someone uses
a DSP in the first place, for its blinding speed. These two factors motivate
many software engineers to switch from C to assembly for programming
Digital Signal Processors. This is illustrated in (b); nearly as many DSP
programmers use assembly as use C.
Figure (c) takes this further by looking at the revenue produced by DSP
products. For every dollar made with a DSP programmed in C, two dollars are
made with a DSP programmed in assembly. The reason for this is simple;
money is made by outperforming the competition. From a pure performance
standpoint, such as execution speed and manufacturing cost, assembly almost
always has the advantage over C. For instance, C code usually requires a
larger memory than assembly, resulting in more expensive hardware. However,
the DSP market is continually changing. As the market grows, manufacturers
will respond by designing DSPs that are optimized for programming in C. For
instance, C is much more efficient when there is a large, general purpose
register set and a unified memory space. These future improvements will
minimize the difference in execution time between C and assembly, and allow
C to be used in more applications.
To better understand this decision between C and assembly, let's look at
a typical DSP task programmed in each language. The example we will
use is the calculation of the dot product of the two arrays, x [ ] and y [ ].
This is a simple mathematical operation, we multiply each coefficient in one
Chapter 28- Digital Signal Processors 521
Assembly
C
b. DSP Programmers
Assembly
C
a. Traditional Programmers
Assembly
C
FIGURE 28-9 c. DSP Revenue
Programming in C versus assembly. As
shown in (a), only about 10% of traditional
programmers (such as those that work on
personal computers and mainframes) use
assembly. However, as illustrated in (b),
assembly is much more common in Digital
Signal Processors. This is because DSP
programs must operate as fast as possible,
and are usually quite short. Figure (c) shows
that assembly is even more common in
products that generate a high revenue.
TABLE 28-2
Dot product in C. This progam calculates
the dot product of two arrays, x[ ] and y[ ],
and stores the result in the variable, result.
001 #define LEN 20
002 float dm x[LEN];
003 float pm y[LEN];
004 float result;
005
006 main()
007
008 {
009 int n;
010 float s;
011 for (n=0;n pi/2 x = pi -x }
ay0=ax0; { store sign of result in ay0}
sin_approx:
I5=^sin_coeff; {Pointer to coeff. buffer}
my1=ar; {Coeffs in 4.12 format}
mf=ar*my1 (rnd), mx1=pm(i5,m5); {mf = x**2}
mr=mx1*my1 (ss), mx1=pm(i5,m5); {mr = c1*x}
cntr=3;
do approx1 until ce;
mr=mr+mx1*mf (SS); {Do summation }
approx1: mf=ar*mf (RND), mx1=PM(I5,M5);
mr=mr+mx1*mf (SS);
sr=ASHIFT mr1 by 3 (HI);
sr=sr or LSHIFT mr0 by 3 (LO); {Convert to 1.15 format}
ar=pass sr1;
if LT ar=pass ay1; {Saturate if needed}
af=pass ay0;
if LT ar=-ar; {Negate output if needed}
rts;
Atan_:
I5 = ^ATN_COEFF; {point to coefficients}
ay0=0;
ax1=mr1;
ar=pass mr1;
if GE jump posi; {Check for positive input}
ar=-mr0; {Make negative number positive}
a Basic trigonometric subroutines for the ADMC300 AN300-10
© Analog Devices Inc., January 2000 Page 6 of 11
mr0=ar;
ar=ay0-mr1+c-1;
mr1=ar;
posi: sr=LSHIFT mr0 by -1 (LO); {Produce 1.15 value in SR0}
ar=sr0;
ay1=mr1;
af=pass mr1;
if EQ jump noinv; {If input < 1, no need to invert}
se=exp mr1 (HI); {Invert input}
sr=norm mr1 (HI);
sr=sr or NORM mr0 (LO);
ax0=sr1;
si=0x0001;
sr=NORM si (HI);
ay1=sr1;
ay0=sr0;
divs ay1,ax0;
divq ax0; divq ax0; divq ax0;
divq ax0; divq ax0; divq ax0;
divq ax0; divq ax0; divq ax0;
divq ax0; divq ax0; divq ax0;
divq ax0; divq ax0; divq ax0;
ar=ay0;
noinv: my0=ar;
mf=ar*my0 (RND), my1=PM(I5,M5);
mr=ar*my1 (SS), mx1=PM(I5,M5);
cntr=3;
do approx2 until CE;
mr=mr+mx1*mf (SS), mx1=PM(I5,M5);
approx2: mf=ar*mf (RND);
mr=mr+mx1*mf (SS);
ar=mr1;
ay0=0x4000;
af=pass ay1;
if NE ar=ay0-mr1;
af=pass ax1;
if LT ar=-ar;
rts;
1.6 Access to the library: the header file
The library may be accessed by including the header file “trigono.h” in the application code.
The header file is intended to provide function-like calls to the routines presented in the previous section. It
defines the calls shown in Error! Reference source not found.. The file is self-explaining and needs no
further comments.
It is worth adding a few comments about efficiency of these routines. The first macro simply sets the DAG
registers M5 and L5 to its correct values. The user may however just replace the macro with one of its
instructions when the application code modifies just one of these registers. The sine and cosine subroutines
expect the argument to be placed into ax0. This is what the macros do. However, if the angle is already
stored in ax0, the user may just place an instruction call Sin_; instead of Sin(ax0) in order to avoid an
additional instruction ax0 = ax0; in the expanded code. Similarly, a instruction Atan(mr1, mr0) should be
avoided or replaced by the direct call to the subroutine Atan_.
.MACRO Set_DAG_registers_for_trigonometric;
M5 = 1;
L5 = 0;
.ENDMACRO;
.MACRO Sin(%0);
ax0 = %0;
call Sin_;
.ENDMACRO;
.MACRO Cos(%0);
ax0 = %0;
a Basic trigonometric subroutines for the ADMC300 AN300-10
© Analog Devices Inc., January 2000 Page 7 of 11
call Cos_;
.ENDMACRO;
.MACRO Atan(%0, %1);
mr1= %0;
mr0= %1;
call Atan_;
.ENDMACRO;
2 Software Example: Testing the Trigonometric Functions
2.1 The main program: main.dsp
The example demonstrates how to use the routines. All it does is to cycle through the whole range of
definition of the sine function and converting the results by means of the digital to analog converter. The
application has been adapted from two previous notes6,7. This section will only explain the few and
intuitive modifications to those applications.
The file “main.dsp” contains the initialisation and PWM Sync and Trip interrupt service routines. To
activate, build the executable file using the attached build.bat either within your DOS prompt or clicking
on it from Windows Explorer. This will create the object files and the main.exe example file. This file
may be run on the Motion Control Debugger.
In the following, a brief description of the additional code (put in evidence by bold characters) is given.
Start of code – declaring start location in program memory
.MODULE/RAM/SEG=USER_PM1/ABS=0x60 Main_Program;
Next, the general systems constants and PWM configuration constants (main.h – see the next section) are
included. Also included are the PWM library, the DAC interface library and the trigonometric library.
{***************************************************************************************
* Include General System Parameters and Libraries *
***************************************************************************************}
#include ;
#include ;
#include ;
#include ;
The argument variable Theta is defined hereafter.
{***************************************************************************************
* Local Variables Defined in this Module *
***************************************************************************************}
.VAR/DM/RAM/SEG=USER_DM Theta; { Current angle }
.INIT Theta : 0x0000;
First, the PWM block is set up to generate interrupts every 100μs (see “main.h” in the next Section). The
variable Theta, which stores the argument of the trigonometric functions, is set to zero. Before using the
trigonometric functions, it is necessary to initialise certain registers of the data-address-generator (DAG) of
the DSP core. This will be discussed in more detail in the next section. However, note that this is done only
once in this example. If those registers are modified in other parts of the user’s code, then it must be repeated
before a call to a trigonometric function.
The main loop just waits for interrupts..
6 AN300-03: Three-Phase Sine-Wave Generation using the PWM Unit of the ADMC300
7 AN300-06: Using the Serial Digital to Analog Converter of the ADMC Connector Board
a Basic trigonometric subroutines for the ADMC300 AN300-10
© Analog Devices Inc., January 2000 Page 8 of 11
{********************************************************************************************}
{ Start of program code }
{********************************************************************************************}
Startup:
PWM_Init(PWMSYNC_ISR, PWMTRIP_ISR);
DAC_Init;
IFC = 0x80; { Clear any pending IRQ2 inter. }
ay0 = 0x200; { unmask irq2 interrupts. }
ar = IMASK;
ar = ar or ay0;
IMASK = ar; { IRQ2 ints fully enabled here }
ar = pass 0;
DM(Theta)= ar;
Set_DAG_registers_for_trigonometric;
Main: { Wait for interrupt to occur }
jump Main;
rts;
The interrupt service routine simply shows how to make use of the trigonometric routines. It invokes the three
routines (the integer part of the Atan_ function is set to zero – it is intended to illustrate the possibility of
constant arguments). The result of Sin, Cos and Atan (in register ar) are stored in channels 1, 2 and 3
respectively and send to the DAC (refer to the above mentioned application note AN300-6 for details). Then
Theta is incremented, so that the whole range of definition of the sine functions is swept. Refer to Section 1.2
for the used formats of inputs and outputs. After 65536 interrupts (corresponding to approx. 6.55s) the whole
period is completed. Since only the fractional part of the arctan argument is used, this function will generate
the output from 0 to π/4 (hexadecimal 0x2000).
{********************************************************************************************}
{ PWM Interrupt Service Routine }
{********************************************************************************************}
PWMSYNC_ISR:
ax0 = dm(Theta);
Sin(ax0);
DAC_Put(1, ar);
Cos(ax0);
DAC_Put(2, ar);
Atan(0, ax0);
DAC_Put(3, ar);
DAC_Update;
ax1= DM(Theta);
ar= ax1 +1;
DM(Theta)= ar;
rti;
2.2 The main include file: main.h
This file contains the definitions of ADMC300 constants, general purpose macros and the configuration
parameters of the system and library routines. It should be included in every application. For more
information refer to the Library Documentation File.
This file is mostly self-explaining. As already mentioned, the trigonometric library does not require any
configuration parameters. The following defines the parameters for the PWM ISR used in this example.
{********************************************************************************************}
{ Library: PWM block }
{ file : PWM300.dsp }
{ Application Note: Usage of the ADMC300 Pulse Width Modulation Block }
.CONST PWM_freq = 10000; {Desired PWM switching frequency [Hz] }
.CONST PWM_deadtime = 1000; {Desired deadtime [nsec] }
.CONST PWM_minpulse = 1000; {Desired minimal pulse time [nsec] }
.CONST PWM_syncpulse = 1540; {Desired sync pulse time [nsec] }
{********************************************************************************************}
a Basic trigonometric subroutines for the ADMC300 AN300-10
© Analog Devices Inc., January 2000 Page 9 of 11
2.3 Example output
The signals that are generated by this demonstration program is shown in the following figure. Note that
the use of only the fractional part for the arctan function limits it’s output to the range of 0 to 0.25
(corresponding to ¼π = arctan(1)). Refer to section 1.2 for details on the format of inputs and outputs.
Figure 1 Produced output of the example program.
The waveforms represent the signals on the DAC outputs 1 (sine), 2 (cosine) and 3 (arctangent).
3 Precision of the routines
3.1 Sine and Cosine functions
The following figure plots the obtained error of the implemented sine function (16 bit fixed point
arithmetic) versus the result of floating point calculations. The graph is limited to the 1st quadrant for the
usual symmetry properties and may obviously be extended to the cosine function as well. Its maximum is
found to be of approx. 0.016%, resulting in a precision of 12.7 bits for the sine and cosine functions.
a Basic trigonometric subroutines for the ADMC300 AN300-10
© Analog Devices Inc., January 2000 Page 10 of 11
Figure 2 Error of sine function in the 1st quadrant (0 to ½π). The x-axis is scaled to 1.15 format.
3.2 Arctangent function
The following figures plot the obtained error of the implemented arctangent function (16 bit fixed point
arithmetic) versus the result of floating point calculations. The analysis has been split into the two cases
of the argument laying in the range of 0 to 1 (increments of 2-14 - Figure 3) and in the range from 1 to
2048 (steps of 0.5 - Figure 4). The maximum error is found to be of approx. 0.0059%, resulting in a
precision of 14 bits for the arctangent function. The result may obviously be extended to negative values
for the usual symmetry properties.
Figure 3 Error of arctangent function in the range of 0 to 1. The y-axis is scaled to 1.15 format.
a Basic trigonometric subroutines for the ADMC300 AN300-10
© Analog Devices Inc., January 2000 Page 11 of 11
Figure 4 Error of arctangent function in the range of 1 to 2048. The y-axis is scaled to 1.15 format.
4 Differences between library and ADMC300 “ROM-Utilities”
The main purpose of this application note is to document, to analyse and to standardise the trigonometric
functions on this part. The routines presented herein do not differ from the ones present in the ROM of the
ADMC300, except for the atan_ routine, which now uses I5, M5 and L5 instead of I4, M4 and L4. This
choice has been made in order to use the same pointers for all of the trigonometric functions. However,
the ones present in the ROM may still be used.
Introduction to Digital Filters
Digital filters are used for two general purposes: (1) separation of signals that have been
combined, and (2) restoration of signals that have been distorted in some way. Analog
(electronic) filters can be used for these same tasks; however, digital filters can achieve far
superior results. The most popular digital filters are described and compared in the next seven
chapters. This introductory chapter describes the parameters you want to look for when learning
about each of these filters.
Filter Basics
Digital filters are a very important part of DSP. In fact, their extraordinary
performance is one of the key reasons that DSP has become so popular. As
mentioned in the introduction, filters have two uses: signal separation and
signal restoration. Signal separation is needed when a signal has been
contaminated with interference, noise, or other signals. For example, imagine
a device for measuring the electrical activity of a baby's heart (EKG) while
still in the womb. The raw signal will likely be corrupted by the breathing and
heartbeat of the mother. A filter might be used to separate these signals so that
they can be individually analyzed.
Signal restoration is used when a signal has been distorted in some way. For
example, an audio recording made with poor equipment may be filtered to
better represent the sound as it actually occurred. Another example is the
deblurring of an image acquired with an improperly focused lens, or a shaky
camera.
These problems can be attacked with either analog or digital filters. Which
is better? Analog filters are cheap, fast, and have a large dynamic range in
both amplitude and frequency. Digital filters, in comparison, are vastly
superior in the level of performance that can be achieved. For example, a
low-pass digital filter presented in Chapter 16 has a gain of 1 +/- 0.0002 from
DC to 1000 hertz, and a gain of less than 0.0002 for frequencies above
262 The Scientist and Engineer's Guide to Digital Signal Processing
1001 hertz. The entire transition occurs within only 1 hertz. Don't expect
this from an op amp circuit! Digital filters can achieve thousands of times
better performance than analog filters. This makes a dramatic difference in
how filtering problems are approached. With analog filters, the emphasis
is on handling limitations of the electronics, such as the accuracy and
stability of the resistors and capacitors. In comparison, digital filters are
so good that the performance of the filter is frequently ignored. The
emphasis shifts to the limitations of the signals, and the theoretical issues
regarding their processing.
It is common in DSP to say that a filter's input and output signals are in the
time domain. This is because signals are usually created by sampling at
regular intervals of time. But this is not the only way sampling can take place.
The second most common way of sampling is at equal intervals in space. For
example, imagine taking simultaneous readings from an array of strain sensors
mounted at one centimeter increments along the length of an aircraft wing.
Many other domains are possible; however, time and space are by far the most
common. When you see the term time domain in DSP, remember that it may
actually refer to samples taken over time, or it may be a general reference to
any domain that the samples are taken in.
As shown in Fig. 14-1, every linear filter has an impulse response, a step
response and a frequency response. Each of these responses contains
complete information about the filter, but in a different form. If one of the
three is specified, the other two are fixed and can be directly calculated. All
three of these representations are important, because they describe how the
filter will react under different circumstances.
The most straightforward way to implement a digital filter is by convolving the
input signal with the digital filter's impulse response. All possible linear filters
can be made in this manner. (This should be obvious. If it isn't, you probably
don't have the background to understand this section on filter design. Try
reviewing the previous section on DSP fundamentals). When the impulse
response is used in this way, filter designers give it a special name: the filter
kernel.
There is also another way to make digital filters, called recursion. When
a filter is implemented by convolution, each sample in the output is
calculated by weighting the samples in the input, and adding them together.
Recursive filters are an extension of this, using previously calculated values
from the output, besides points from the input. Instead of using a filter
kernel, recursive filters are defined by a set of recursion coefficients. This
method will be discussed in detail in Chapter 19. For now, the important
point is that all linear filters have an impulse response, even if you don't
use it to implement the filter. To find the impulse response of a recursive
filter, simply feed in an impulse, and see what comes out. The impulse
responses of recursive filters are composed of sinusoids that exponentially
decay in amplitude. In principle, this makes their impulse responses
infinitely long. However, the amplitude eventually drops below the round-off
noise of the system, and the remaining samples can be ignored. Because
Chapter 14- Introduction to Digital Filters 263
Frequency
0 0.1 0.2 0.3 0.4 0.5
-0.5
0.0
0.5
1.0
1.5
c. Frequency response
Sample number
0 32 64 96 128
-0.1
0.0
0.1
0.2
127
a. Impulse response
0.3
Sample number
0 32 64 96 128
-0.5
0.0
0.5
1.0
1.5
127
b. Step response
Frequency
0 0.1 0.2 0.3 0.4 0.5
-60
-40
-20
0
20
40
d. Frequency response (in dB)
FIGURE 14-1
Filter parameters. Every linear filter has an impulse response, a step response, and a frequency response. The
step response, (b), can be found by discrete integration of the impulse response, (a). The frequency response
can be found from the impulse response by using the Fast Fourier Transform (FFT), and can be displayed either
on a linear scale, (c), or in decibels, (d).
FFT
Integrate 20 Log( )
Amplitude
Amplitude (dB) Amplitude
Amplitude
of this characteristic, recursive filters are also called Infinite Impulse
Response or IIR filters. In comparison, filters carried out by convolution are
called Finite Impulse Response or FIR filters.
As you know, the impulse response is the output of a system when the input is
an impulse. In this same manner, the step response is the output when the
input is a step (also called an edge, and an edge response). Since the step is
the integral of the impulse, the step response is the integral of the impulse
response. This provides two ways to find the step response: (1) feed a step
waveform into the filter and see what comes out, or (2) integrate the impulse
response. (To be mathematically correct: integration is used with continuous
signals, while discrete integration, i.e., a running sum, is used with discrete
signals). The frequency response can be found by taking the DFT (using the
FFT algorithm) of the impulse response. This will be reviewed later in this
264 The Scientist and Engineer's Guide to Digital Signal Processing
dB ’ 10 log10
P2
P1
dB ’ 20 log10
A2
A1
EQUATION 14-1
Definition of decibels. Decibels are a
way of expressing a ratio between two
signals. Ratios of power (P1 & P2) use a
different equation from ratios of
amplitude (A1 & A2).
chapter. The frequency response can be plotted on a linear vertical axis, such
as in (c), or on a logarithmic scale (decibels), as shown in (d). The linear
scale is best at showing the passband ripple and roll-off, while the decibel scale
is needed to show the stopband attenuation.
Don't remember decibels? Here is a quick review. A bel (in honor of
Alexander Graham Bell) means that the power is changed by a factor of ten.
For example, an electronic circuit that has 3 bels of amplification produces an
output signal with 10×10×10 ’ 1000 times the power of the input. A decibel
(dB) is one-tenth of a bel. Therefore, the decibel values of: -20dB, -10dB,
0dB, 10dB & 20dB, mean the power ratios: 0.01, 0.1, 1, 10, & 100,
respectively. In other words, every ten decibels mean that the power has
changed by a factor of ten.
Here's the catch: you usually want to work with a signal's amplitude, not
its power. For example, imagine an amplifier with 20dB of gain. By
definition, this means that the power in the signal has increased by a factor
of 100. Since amplitude is proportional to the square-root of power, the
amplitude of the output is 10 times the amplitude of the input. While 20dB
means a factor of 100 in power, it only means a factor of 10 in amplitude.
Every twenty decibels mean that the amplitude has changed by a factor of
ten. In equation form:
The above equations use the base 10 logarithm; however, many computer
languages only provide a function for the base e logarithm (the natural log,
written log or ). The natural log can be use by modifying the above e x ln x
equations: dB ’ 4.342945 log and . e (P2 /P1) dB ’ 8.685890 loge (A2 /A1)
Since decibels are a way of expressing the ratio between two signals, they are
ideal for describing the gain of a system, i.e., the ratio between the output and
the input signal. However, engineers also use decibels to specify the amplitude
(or power) of a single signal, by referencing it to some standard. For example,
the term: dBV means that the signal is being referenced to a 1 volt rms signal.
Likewise, dBm indicates a reference signal producing 1 mW into a 600 ohms
load (about 0.78 volts rms).
If you understand nothing else about decibels, remember two things: First,
-3dB means that the amplitude is reduced to 0.707 (and the power is
Chapter 14- Introduction to Digital Filters 265
60dB = 1000
40dB = 100
20dB = 10
0dB = 1
-20dB = 0.1
-40dB = 0.01
-60dB = 0.001
therefore reduced to 0.5). Second, memorize the following conversions
between decibels and amplitude ratios:
How Information is Represented in Signals
The most important part of any DSP task is understanding how information is
contained in the signals you are working with. There are many ways that
information can be contained in a signal. This is especially true if the signal
is manmade. For instance, consider all of the modulation schemes that have
been devised: AM, FM, single-sideband, pulse-code modulation, pulse-width
modulation, etc. The list goes on and on. Fortunately, there are only two
ways that are common for information to be represented in naturally occurring
signals. We will call these: information represented in the time domain,
and information represented in the frequency domain.
Information represented in the time domain describes when something occurs
and what the amplitude of the occurrence is. For example, imagine an
experiment to study the light output from the sun. The light output is measured
and recorded once each second. Each sample in the signal indicates what is
happening at that instant, and the level of the event. If a solar flare occurs, the
signal directly provides information on the time it occurred, the duration, the
development over time, etc. Each sample contains information that is
interpretable without reference to any other sample. Even if you have only one
sample from this signal, you still know something about what you are
measuring. This is the simplest way for information to be contained in a
signal.
In contrast, information represented in the frequency domain is more
indirect. Many things in our universe show periodic motion. For example,
a wine glass struck with a fingernail will vibrate, producing a ringing
sound; the pendulum of a grandfather clock swings back and forth; stars
and planets rotate on their axis and revolve around each other, and so forth.
By measuring the frequency, phase, and amplitude of this periodic motion,
information can often be obtained about the system producing the motion.
Suppose we sample the sound produced by the ringing wine glass. The
fundamental frequency and harmonics of the periodic vibration relate to the
mass and elasticity of the material. A single sample, in itself, contains no
information about the periodic motion, and therefore no information about
the wine glass. The information is contained in the relationship between
many points in the signal.
266 The Scientist and Engineer's Guide to Digital Signal Processing
This brings us to the importance of the step and frequency responses. The step
response describes how information represented in the time domain is being
modified by the system. In contrast, the frequency response shows how
information represented in the frequency domain is being changed. This
distinction is absolutely critical in filter design because it is not possible to
optimize a filter for both applications. Good performance in the time domain
results in poor performance in the frequency domain, and vice versa. If you are
designing a filter to remove noise from an EKG signal (information represented
in the time domain), the step response is the important parameter, and the
frequency response is of little concern. If your task is to design a digital filter
for a hearing aid (with the information in the frequency domain), the frequency
response is all important, while the step response doesn't matter. Now let's
look at what makes a filter optimal for time domain or frequency domain
applications.
Time Domain Parameters
It may not be obvious why the step response is of such concern in time domain
filters. You may be wondering why the impulse response isn't the important
parameter. The answer lies in the way that the human mind understands and
processes information. Remember that the step, impulse and frequency
responses all contain identical information, just in different arrangements. The
step response is useful in time domain analysis because it matches the way
humans view the information contained in the signals.
For example, suppose you are given a signal of some unknown origin and
asked to analyze it. The first thing you will do is divide the signal into
regions of similar characteristics. You can't stop from doing this; your
mind will do it automatically. Some of the regions may be smooth; others
may have large amplitude peaks; others may be noisy. This segmentation
is accomplished by identifying the points that separate the regions. This is
where the step function comes in. The step function is the purest way of
representing a division between two dissimilar regions. It can mark when
an event starts, or when an event ends. It tells you that whatever is on the
left is somehow different from whatever is on the right. This is how the
human mind views time domain information: a group of step functions
dividing the information into regions of similar characteristics. The step
response, in turn, is important because it describes how the dividing lines
are being modified by the filter.
The step response parameters that are important in filter design are shown
in Fig. 14-2. To distinguish events in a signal, the duration of the step
response must be shorter than the spacing of the events. This dictates that
the step response should be as fast (the DSP jargon) as possible. This is
shown in Figs. (a) & (b). The most common way to specify the risetime
(more jargon) is to quote the number of samples between the 10% and 90%
amplitude levels. Why isn't a very fast risetime always possible? There are
many reasons, noise reduction, inherent limitations of the data acquisition
system, avoiding aliasing, etc.
Chapter 14- Introduction to Digital Filters 267
Sample number
0 16 32 48 64
-0.5
0.0
0.5
1.0
1.5
a. Slow step response
Sample number
0 16 32 48 64
-0.5
0.0
0.5
1.0
1.5
b. Fast step response
Sample number
0 16 32 48 64
-0.5
0.0
0.5
1.0
1.5
e. Nonlinear phase
Sample number
0 16 32 48 64
-0.5
0.0
0.5
1.0
1.5
f. Linear phase
FIGURE 14-2
Parameters for evaluating time domain performance. The step response is used to measure how well a filter
performs in the time domain. Three parameters are important: (1) transition speed (risetime), shown in (a) and
(b), (2) overshoot, shown in (c) and (d), and (3) phase linearity (symmetry between the top and bottom halves
of the step), shown in (e) and (f).
Sample number
0 16 32 48 64
-0.5
0.0
0.5
1.0
1.5
d. No overshoot
Sample number
0 16 32 48 64
-0.5
0.0
0.5
1.0
1.5
c. Overshoot
POOR GOOD
Amplitude
Amplitude
Amplitude Amplitude
Amplitude Amplitude
Figures (c) and (d) shows the next parameter that is important: overshoot in
the step response. Overshoot must generally be eliminated because it changes
the amplitude of samples in the signal; this is a basic distortion of
the information contained in the time domain. This can be summed up in
268 The Scientist and Engineer's Guide to Digital Signal Processing
Frequency
a. Low-pass
Frequency
c. Band-pass
Frequency
b. High-pass
Frequency
d. Band-reject
passband
stopband
transition
band
FIGURE 14-3
The four common frequency responses.
Frequency domain filters are generally
used to pass certain frequencies (the
passband), while blocking others (the
stopband). Four responses are the most
common: low-pass, high-pass, band-pass,
and band-reject.
Amplitude
Amplitude Amplitude
Amplitude
one question: Is the overshoot you observe in a signal coming from the thing
you are trying to measure, or from the filter you have used?
Finally, it is often desired that the upper half of the step response be
symmetrical with the lower half, as illustrated in (e) and (f). This symmetry
is needed to make the rising edges look the same as the falling edges. This
symmetry is called linear phase, because the frequency response has a phase
that is a straight line (discussed in Chapter 19). Make sure you understand
these three parameters; they are the key to evaluating time domain filters.
Frequency Domain Parameters
Figure 14-3 shows the four basic frequency responses. The purpose of
these filters is to allow some frequencies to pass unaltered, while
completely blocking other frequencies. The passband refers to those
frequencies that are passed, while the stopband contains those frequencies
that are blocked. The transition band is between. A fast roll-off means
that the transition band is very narrow. The division between the passband
and transition band is called the cutoff frequency. In analog filter design,
the cutoff frequency is usually defined to be where the amplitude is reduced
to 0.707 (i.e., -3dB). Digital filters are less standardized, and it is
common to see 99%, 90%, 70.7%, and 50% amplitude levels defined to be
the cutoff frequency.
Figure 14-4 shows three parameters that measure how well a filter performs
in the frequency domain. To separate closely spaced frequencies, the filter
must have a fast roll-off, as illustrated in (a) and (b). For the passband
frequencies to move through the filter unaltered, there must be no passband
ripple, as shown in (c) and (d). Lastly, to adequately block the stopband
frequencies, it is necessary to have good stopband attenuation, displayed
in (e) and (f).
Chapter 14- Introduction to Digital Filters 269
Frequency
0 0.1 0.2 0.3 0.4 0.5
-0.5
0.0
0.5
1.0
1.5
a. Slow roll-off
Frequency
0 0.1 0.2 0.3 0.4 0.5
-0.5
0.0
0.5
1.0
1.5
b. Fast roll-off
Frequency
0 0.1 0.2 0.3 0.4 0.5
-120
-100
-80
-60
-40
-20
0
20
40
e. Poor stopband attenuation
Frequency
0 0.1 0.2 0.3 0.4 0.5
-120
-100
-80
-60
-40
-20
0
20
40
f. Good stopband attenuation
FIGURE 14-4
Parameters for evaluating frequency domain performance. The frequency responses shown are for low-pass
filters. Three parameters are important: (1) roll-off sharpness, shown in (a) and (b), (2) passband ripple, shown
in (c) and (d), and (3) stopband attenuation, shown in (e) and (f).
Frequency
0 0.1 0.2 0.3 0.4 0.5
-0.5
0.0
0.5
1.0
1.5
d. Flat passband
Frequency
0 0.1 0.2 0.3 0.4 0.5
-0.5
0.0
0.5
1.0
1.5
c. Ripple in passband
POOR GOOD
Amplitude (dB)
Amplitude (dB)
Amplitude Amplitude
Amplitude Amplitude
Why is there nothing about the phase in these parameters? First, the phase
isn't important in most frequency domain applications. For example, the phase
of an audio signal is almost completely random, and contains little useful
information. Second, if the phase is important, it is very easy to make digital
270 The Scientist and Engineer's Guide to Digital Signal Processing
filters with a perfect phase response, i.e., all frequencies pass through the filter
with a zero phase shift (also discussed in Chapter 19). In comparison, analog
filters are ghastly in this respect.
Previous chapters have described how the DFT converts a system's impulse
response into its frequency response. Here is a brief review. The quickest
way to calculate the DFT is by means of the FFT algorithm presented in
Chapter 12. Starting with a filter kernel N samples long, the FFT calculates
the frequency spectrum consisting of an N point real part and an N point
imaginary part. Only samples 0 to N/2 of the FFT's real and imaginary parts
contain useful information; the remaining points are duplicates (negative
frequencies) and can be ignored. Since the real and imaginary parts are
difficult for humans to understand, they are usually converted into polar
notation as described in Chapter 8. This provides the magnitude and phase
signals, each running from sample 0 to sample N/2 (i.e., N/2%1 samples in
each signal). For example, an impulse response of 256 points will result in a
frequency response running from point 0 to 128. Sample 0 represents DC, i.e.,
zero frequency. Sample 128 represents one-half of the sampling rate.
Remember, no frequencies higher than one-half of the sampling rate can appear
in sampled data.
The number of samples used to represent the impulse response can be
arbitrarily large. For instance, suppose you want to find the frequency
response of a filter kernel that consists of 80 points. Since the FFT only works
with signals that are a power of two, you need to add 48 zeros to the signal to
bring it to a length of 128 samples. This padding with zeros does not change
the impulse response. To understand why this is so, think about what happens
to these added zeros when the input signal is convolved with the system's
impulse response. The added zeros simply vanish in the convolution, and do
not affect the outcome.
Taking this a step further, you could add many zeros to the impulse response
to make it, say, 256, 512, or 1024 points long. The important idea is that
longer impulse responses result in a closer spacing of the data points in the
frequency response. That is, there are more samples spread between DC and
one-half of the sampling rate. Taking this to the extreme, if the impulse
response is padded with an infinite number of zeros, the data points in the
frequency response are infinitesimally close together, i.e., a continuous line.
In other words, the frequency response of a filter is really a continuous signal
between DC and one-half of the sampling rate. The output of the DFT is a
sampling of this continuous line. What length of impulse response should you
use when calculating a filter's frequency response? As a first thought, try
N’1024 , but don't be afraid to change it if needed (such as insufficient
resolution or excessive computation time).
Keep in mind that the "good" and "bad" parameters discussed in this chapter
are only generalizations. Many signals don't fall neatly into categories. For
example, consider an EKG signal contaminated with 60 hertz interference.
The information is encoded in the time domain, but the interference is best
dealt with in the frequency domain. The best design for this application is
Chapter 14- Introduction to Digital Filters 271
Sample number
0 10 20 30 40 50
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
a. Original filter kernel
Frequency
0 0.1 0.2 0.3 0.4 0.5
0.0
0.5
1.0
1.5
b. Original frequency response
FIGURE 14-5
Example of spectral inversion. The low-pass filter kernel in (a) has the frequency response shown in (b). A
high-pass filter kernel, (c), is formed by changing the sign of each sample in (a), and adding one to the sample
at the center of symmetry. This action in the time domain inverts the frequency spectrum (i.e., flips it top-forbottom),
as shown by the high-pass frequency response in (d).
Frequency
0 0.1 0.2 0.3 0.4 0.5
0.0
0.5
1.0
1.5
d. Inverted frequency response
Flipped
top-for-bottom
Sample number
0 10 20 30 40 50
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
c. Filter kernel with spectral inversion
Time Domain Frequency Domain
Amplitude Amplitude
Amplitude Amplitude
bound to have trade-offs, and might go against the conventional wisdom of this
chapter. Remember the number one rule of education: A paragraph in a book
doesn't give you a license to stop thinking.
High-Pass, Band-Pass and Band-Reject Filters
High-pass, band-pass and band-reject filters are designed by starting with a
low-pass filter, and then converting it into the desired response. For this
reason, most discussions on filter design only give examples of low-pass
filters. There are two methods for the low-pass to high-pass conversion:
spectral inversion and spectral reversal. Both are equally useful.
An example of spectral inversion is shown in 14-5. Figure (a) shows a lowpass
filter kernel called a windowed-sinc (the topic of Chapter 16). This filter
kernel is 51 points in length, although many of samples have a value
so small that they appear to be zero in this graph. The corresponding
272 The Scientist and Engineer's Guide to Digital Signal Processing
x[n] y[n]
x[n] *[n] - h[n] y[n]
h[n]
*[n]
Low-pass
All-pass
b. High-pass High-pass
in a single stage
a. High-pass by
adding parallel stages
FIGURE 14-6
Block diagram of spectral inversion. In
(a), the input signal, x[n] , is applied to two
systems in parallel, having impulse
responses of h[n] and *[n] . As shown in
(b), the combined system has an impulse
response of *[n]& h[n] . This means that
the frequency response of the combined
system is the inversion of the frequency
response of h[n] .
frequency response is shown in (b), found by adding 13 zeros to the filter
kernel and taking a 64 point FFT. Two things must be done to change the
low-pass filter kernel into a high-pass filter kernel. First, change the sign of
each sample in the filter kernel. Second, add one to the sample at the center
of symmetry. This results in the high-pass filter kernel shown in (c), with the
frequency response shown in (d). Spectral inversion flips the frequency
response top-for-bottom, changing the passbands into stopbands, and the
stopbands into passbands. In other words, it changes a filter from low-pass to
high-pass, high-pass to low-pass, band-pass to band-reject, or band-reject to
band-pass.
Figure 14-6 shows why this two step modification to the time domain results
in an inverted frequency spectrum. In (a), the input signal, x[n] , is applied to
two systems in parallel. One of these systems is a low-pass filter, with an
impulse response given by h[n] . The other system does nothing to the signal,
and therefore has an impulse response that is a delta function, *[n] . The
overall output, y[n] , is equal to the output of the all-pass system minus the
output of the low-pass system. Since the low frequency components are
subtracted from the original signal, only the high frequency components appear
in the output. Thus, a high-pass filter is formed.
This could be performed as a two step operation in a computer program:
run the signal through a low-pass filter, and then subtract the filtered signal
from the original. However, the entire operation can be performed in a
signal stage by combining the two filter kernels. As described in Chapter
Chapter 14- Introduction to Digital Filters 273
Sample number
0 10 20 30 40 50
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
a. Original filter kernel
Frequency
0 0.1 0.2 0.3 0.4 0.5
0.0
0.5
1.0
1.5
b. Original frequency response
FIGURE 14-7
Example of spectral reversal. The low-pass filter kernel in (a) has the frequency response shown in (b). A
high-pass filter kernel, (c), is formed by changing the sign of every other sample in (a). This action in the time
domain results in the frequency domain being flipped left-for-right, resulting in the high-pass frequency
response shown in (d).
Frequency
0 0.1 0.2 0.3 0.4 0.5
0.0
0.5
1.0
1.5
d. Reversed frequency response
Flipped
left-for-right
Sample number
0 10 20 30 40 50
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
c. Filter kernel with spectral reversal
Time Domain Frequency Domain
Amplitude Amplitude
Amplitude Amplitude
7, parallel systems with added outputs can be combined into a single stage by
adding their impulse responses. As shown in (b), the filter kernel for the highpass
filter is given by: *[n] & h[n]. That is, change the sign of all the samples,
and then add one to the sample at the center of symmetry.
For this technique to work, the low-frequency components exiting the low-pass
filter must have the same phase as the low-frequency components exiting the
all-pass system. Otherwise a complete subtraction cannot take place. This
places two restrictions on the method: (1) the original filter kernel must have
left-right symmetry (i.e., a zero or linear phase), and (2) the impulse must be
added at the center of symmetry.
The second method for low-pass to high-pass conversion, spectral reversal, is
illustrated in Fig. 14-7. Just as before, the low-pass filter kernel in (a)
corresponds to the frequency response in (b). The high-pass filter kernel, (c),
is formed by changing the sign of every other sample in (a). As shown in
(d), this flips the frequency domain left-for-right: 0 becomes 0.5 and 0.5
274 The Scientist and Engineer's Guide to Digital Signal Processing
h1x[n] [n] h2[n] y[n]
h1[n] h2x[n] [n] y[n]
Band-pass
a. Band-pass by Low-pass High-pass
cascading stages
b. Band-pass
in a single stage
FIGURE 14-8
Designing a band-pass filter. As shown
in (a), a band-pass filter can be formed
by cascading a low-pass filter and a
high-pass filter. This can be reduced to
a single stage, shown in (b). The filter
kernel of the single stage is equal to the
convolution of the low-pass and highpass
filter kernels.
becomes 0. The cutoff frequency of the example low-pass filter is 0.15,
resulting in the cutoff frequency of the high-pass filter being 0.35.
Changing the sign of every other sample is equivalent to multiplying the filter
kernel by a sinusoid with a frequency of 0.5. As discussed in Chapter 10, this
has the effect of shifting the frequency domain by 0.5. Look at (b) and imagine
the negative frequencies between -0.5 and 0 that are of mirror image of the
frequencies between 0 and 0.5. The frequencies that appear in (d) are the
negative frequencies from (b) shifted by 0.5.
Lastly, Figs. 14-8 and 14-9 show how low-pass and high-pass filter kernels can
be combined to form band-pass and band-reject filters. In short, adding the
filter kernels produces a band-reject filter, while convolving the filter kernels
produces a band-pass filter. These are based on the way cascaded and
parallel systems are be combined, as discussed in Chapter 7. Multiple
combination of these techniques can also be used. For instance, a band-pass
filter can be designed by adding the two filter kernels to form a stop-pass
filter, and then use spectral inversion or spectral reversal as previously
described. All these techniques work very well with few surprises.
Filter Classification
Table 14-1 summarizes how digital filters are classified by their use and by
their implementation. The use of a digital filter can be broken into three
categories: time domain, frequency domain and custom. As previously
described, time domain filters are used when the information is encoded in the
shape of the signal's waveform. Time domain filtering is used for such
actions as: smoothing, DC removal, waveform shaping, etc. In contrast,
frequency domain filters are used when the information is contained in the
Chapter 14- Introduction to Digital Filters 275
x[n] y[n]
x[n] h1[n] + h2[n] y[n]
h1[n]
h2[n]
Low-pass
High-pass
b. Band-reject Band-reject
in a single stage
a. Band-reject by
adding parallel stages
FIGURE 14-9
Designing a band-reject filter. As shown
in (a), a band-reject filter is formed by
the parallel combination of a low-pass
filter and a high-pass filter with their
outputs added. Figure (b) shows this
reduced to a single stage, with the filter
kernel found by adding the low-pass
and high-pass filter kernels.
Recursion
Time Domain
Frequency Domain
Finite Impulse Response (FIR) Infinite Impulse Response (IIR)
Moving average (Ch. 15) Single pole (Ch. 19)
Windowed-sinc (Ch. 16) Chebyshev (Ch. 20)
Custom FIR custom (Ch. 17) Iterative design (Ch. 26)
(Deconvolution)
Convolution
FILTER IMPLEMENTED BY:
(smoothing, DC removal)
(separating frequencies)
FILTER USED FOR:
TABLE 14-1
Filter classification. Filters can be divided by their use, and how they are implemented.
amplitude, frequency, and phase of the component sinusoids. The goal of these
filters is to separate one band of frequencies from another. Custom filters are
used when a special action is required by the filter, something more elaborate
than the four basic responses (high-pass, low-pass, band-pass and band-reject).
For instance, Chapter 17 describes how custom filters can be used for
deconvolution, a way of counteracting an unwanted convolution.
276 The Scientist and Engineer's Guide to Digital Signal Processing
Digital filters can be implemented in two ways, by convolution (also called
finite impulse response or FIR) and by recursion (also called infinite impulse
response or IIR). Filters carried out by convolution can have far better
performance than filters using recursion, but execute much more slowly.
The next six chapters describe digital filters according to the classifications in
Table 14-1. First, we will look at filters carried out by convolution. The
moving average (Chapter 15) is used in the time domain, the windowed-sinc
(Chapter 16) is used in the frequency domain, and FIR custom (Chapter 17) is
used when something special is needed. To finish the discussion of FIR filters,
Chapter 18 presents a technique called FFT convolution. This is an algorithm
for increasing the speed of convolution, allowing FIR filters to execute faster.
Next, we look at recursive filters. The single pole recursive filter (Chapter 19)
is used in the time domain, while the Chebyshev (Chapter 20) is used in the
frequency domain. Recursive filters having a custom response are designed by
iterative techniques. For this reason, we will delay their discussion until
Chapter 26, where they will be presented with another type of iterative
procedure: the neural network.
As shown in Table 14-1, convolution and recursion are rival techniques; you
must use one or the other for a particular application. How do you choose?
Chapter 21 presents a head-to-head comparison of the two, in both the time and
frequency domains.
The Complex Fourier Transform
Although complex numbers are fundamentally disconnected from our reality, they can be used to
solve science and engineering problems in two ways. First, the parameters from a real world
problem can be substituted into a complex form, as presented in the last chapter. The second
method is much more elegant and powerful, a way of making the complex numbers
mathematically equivalent to the physical problem. This approach leads to the complex Fourier
transform, a more sophisticated version of the real Fourier transform discussed in Chapter 8.
The complex Fourier transform is important in itself, but also as a stepping stone to more
powerful complex techniques, such as the Laplace and z-transforms. These complex transforms
are the foundation of theoretical DSP.
The Real DFT
All four members of the Fourier transform family (DFT, DTFT, Fourier
Transform & Fourier Series) can be carried out with either real numbers or
complex numbers. Since DSP is mainly concerned with the DFT, we will use
it as an example. Before jumping into the complex math, let's review the real
DFT with a special emphasis on things that are awkward with the mathematics.
In Chapter 8 we defined the real version of the Discrete Fourier Transform
according to the equations:
In words, an N sample time domain signal, x [n] , is decomposed into a set
of N/2%1 cosine waves, and N/2%1 sine waves, with frequencies given by the
568 The Scientist and Engineer's Guide to Digital Signal Processing
index, k. The amplitudes of the cosine waves are contained in ReX[k ], while
the amplitudes of the sine waves are contained in Im X[k] . These equations
operate by correlating the respective cosine or sine wave with the time domain
signal. In spite of using the names: real part and imaginary part, there are no
complex numbers in these equations. There isn't a j anywhere in sight! We
have also included the normalization factor, 2/N in these equations.
Remember, this can be placed in front of either the synthesis or analysis
equation, or be handled as a separate step (as described by Eq. 8-3). These
equations should be very familiar from previous chapters. If they aren't, go
back and brush up on these concepts before continuing. If you don't understand
the real DFT, you will never be able to understand the complex DFT.
Even though the real DFT uses only real numbers, substitution allows the
frequency domain to be represented using complex numbers. As suggested by
the names of the arrays, ReX[k ] becomes the real part of the complex
frequency spectrum, and Im X[k] becomes the imaginary part. In other words,
we place a j with each value in the imaginary part, and add the result to the
real part. However, do not make the mistake of thinking that this is the
"complex DFT." This is nothing more than the real DFT with complex
substitution.
While the real DFT is adequate for many applications in science and
engineering, it is mathematically awkward in three respects. First, it can only
take advantage of complex numbers through the use of substitution. This
makes mathematicians uncomfortable; they want to say: "this equals that," not
simply: "this represents that." For instance, imagine we are given the
mathematical statement: A equals B. We immediately know countless
consequences: 5A’ 5B, 1%A ’ 1%B, A/ x ’ B/ x, etc. Now suppose we are
given the statement: A represents B. Without additional information, we know
absolutely nothing! When things are equal, we have access to four-thousand
years of mathematics. When things only represent each other, we must start
from scratch with new definitions. For example, when sinusoids are
represented by complex numbers, we allow addition and subtraction, but
prohibit multiplication and division.
The second thing handled poorly by the real Fourier transform is the negative
frequency portion of the spectrum. As you recall from Chapter 10, sine and
cosine waves can be described as having a positive frequency or a negative
frequency. Since the two views are identical, the real Fourier transform
ignores the negative frequencies. However, there are applications where the
negative frequencies are important. This occurs when negative frequency
components are forced to move into the positive frequency portion of the
spectrum. The ghosts take human form, so to speak. For instance, this is what
happens in aliasing, circular convolution, and amplitude modulation. Since the
real Fourier transform doesn't use negative frequencies, its ability to deal with
these situations is very limited.
Our third complaint is the special handing of ReX [0] and ReX [N/2], the
first and last points in the frequency spectrum. Suppose we start with an N
Chapter 31- The Complex Fourier Transform 569
EQUATION 31-2
Euler's relation. e jx ’ cos(x) % j sin (x)
EQUATION 31-3
Euler's relation for
sine & cosine.
sin (x) ’ e jx & e &jx
2j
cos (x) ’ e jx % e &jx
2
sin(Tt ) ’ 1
2
je j (&T)t & 1
2
je jTt
EQUATION 31-4
Sinusoids as complex numbers. Using
complex numbers, cosine and sine waves
can be written as the sum of a positive
and a negative frequency.
cos(Tt ) ’ 1
2
e j (&T)t % 1
2
e jTt
point signal, x [n]. Taking the DFT provides the frequency spectrum contained
in ReX [k] and ImX [k] , where k runs from 0 to N/2. However, these are not
the amplitudes needed to reconstruct the time domain waveform; samples
ReX [0] and ReX [N/2] must first be divided by two. (See Eq. 8-3 to refresh
your memory). This is easily carried out in computer programs, but
inconvenient to deal with in equations.
The complex Fourier transform is an elegant solution to these problems. It is
natural for complex numbers and negative frequencies to go hand-in-hand.
Let's see how it works.
Mathematical Equivalence
Our first step is to show how sine and cosine waves can be written in an
equation with complex numbers. The key to this is Euler's relation, presented
in the last chapter:
At first glance, this doesn't appear to be much help; one complex expression is
equal to another complex expression. Nevertheless, a little algebra can
rearrange the relation into two other forms:
This result is extremely important, we have developed a way of writing
equations between complex numbers and ordinary sinusoids. Although Eq. 31-
3 is the standard form of the identity, it will be more useful for this discussion
if we change a few terms around:
Each expression is the sum of two exponentials: one containing a positive
frequency (T), and the other containing a negative frequency (-T). In other
words, when sine and cosine waves are written as complex numbers, the
570 The Scientist and Engineer's Guide to Digital Signal Processing
EQUATION 31-5
The forward complex DFT. Both the
time domain, x [n], and the frequency
domain, X[k], are arrays of complex
numbers, with k and n running from 0
to N-1. This equation is in polar form,
the most common for DSP.
X[k] ’ 1
N
j N& 1
n’ 0
x [n] e &j 2B kn /N
X[k] ’ 1
N
j N& 1
n’ 0
x[n] cos (2Bkn/N) & j sin (2Bkn/N)
EQUATION 31-6
The forward complex DFT
(rectangular form).
negative portion of the frequency spectrum is automatically included. The
positive and negative frequencies are treated with an equal status; it requires
one-half of each to form a complete waveform.
The Complex DFT
The forward complex DFT, written in polar form, is given by:
Alternatively, Euler's relation can be used to rewrite the forward transform in
rectangular form:
To start, compare this equation of the complex Fourier transform with the
equation of the real Fourier transform, Eq. 31-1. At first glance, they appear
to be identical, with only small amount of algebra being required to turn Eq.
31-6 into Eq. 31-1. However, this is very misleading; the differences between
these two equations are very subtle and easy to overlook, but tremendously
important. Let's go through the differences in detail.
First, the real Fourier transform converts a real time domain signal, x [n], into
two real frequency domain signals, ReX[k ] & ImX[k ]. By using complex
substitution, the frequency domain can be represented by a single complex
array, X[k] . In the complex Fourier transform, both x [n] & X[k] are arrays
of complex numbers. A practical note: Even though the time domain is
complex, there is nothing that requires us to use the imaginary part. Suppose
we want to process a real signal, such as a series of voltage measurements
taken over time. This group of data becomes the real part of the time domain
signal, while the imaginary part is composed of zeros.
Second, the real Fourier transform only deals with positive frequencies.
That is, the frequency domain index, k, only runs from 0 to N/2. In
comparison, the complex Fourier transform includes both positive and
negative frequencies. This means k runs from 0 to N-1. The frequencies
between 0 and N/2 are positive, while the frequencies between N/2 and N-1
are negative. Remember, the frequency spectrum of a discrete signal is
periodic, making the negative frequencies between N/2 and N-1 the same as
Chapter 31- The Complex Fourier Transform 571
between -N/2 and 0. The samples at 0 and N/2 straddle the line between
positive and negative. If you need to refresh your memory on this, look
back at Chapters 10 and 12.
Third, in the real Fourier transform with substitution, a j was added to the sine
wave terms, allowing the frequency spectrum to be represented by complex
numbers. To convert back to ordinary sine and cosine waves, we can simply
drop the j. This is the sloppiness that comes when one thing only represents
another thing. In comparison, the complex DFT, Eq. 31-5, is a formal
mathematical equation with j being an integral part. In this view, we cannot
arbitrary add or remove a j any more than we can add or remove any other
variable in the equation.
Forth, the real Fourier transform has a scaling factor of two in front, while the
complex Fourier transform does not. Say we take the real DFT of a cosine
wave with an amplitude of one. The spectral value corresponding to the cosine
wave is also one. Now, let's repeat the process using the complex DFT. In
this case, the cosine wave corresponds to two spectral values, a positive and a
negative frequency. Both these frequencies have a value of ½. In other words,
a positive frequency with an amplitude of ½, combines with a negative
frequency with an amplitude of ½, producing a cosine wave with an amplitude
of one.
Fifth, the real Fourier transform requires special handling of two frequency
domain samples: ReX [0] & ReX [N/2], but the complex Fourier transform does
not. Suppose we start with a time domain signal, and take the DFT to find the
frequency domain signal. To reverse the process, we take the Inverse DFT of
the frequency domain signal, reconstructing the original time domain signal.
However, there is scaling required to make the reconstructed signal be identical
to the original signal. For the complex Fourier transform, a factor of 1/N must
be introduced somewhere along the way. This can be tacked-on to the forward
transform, the inverse transform, or kept as a separate step between the two.
For the real Fourier transform, an additional factor of two is required (2/N), as
described above. However, the real Fourier transform also requires an
additional scaling step: ReX [0] and ReX [N/2] must be divided by two
somewhere along the way. Put in other words, a scaling factor of 1/N is used
with these two samples, while 2/N is used for the remainder of the spectrum.
As previously stated, this awkward step is one of our complaints about the real
Fourier transform.
Why are the real and complex DFTs different in how these two points are
handled? To answer this, remember that a cosine (or sine) wave in the time
domain becomes split between a positive and a negative frequency in the
complex DFT's spectrum. However, there are two exceptions to this, the
spectral values at 0 and N/2. These correspond to zero frequency (DC) and
the Nyquist frequency (one-half the sampling rate). Since these points
straddle the positive and negative portions of the spectrum, they do not have
a matching point. Because they are not combined with another value, they
inherently have only one-half the contribution to the time domain as the
other frequencies.
572 The Scientist and Engineer's Guide to Digital Signal Processing
x[n] ’ j N& 1
k’ 0
X[k ]e j 2B kn /N
EQUATION 31-7
The inverse complex DFT. This is
matching equation to the forward
complex DFT in Eq. 31-5.
Im X[ ]
Re X[ ]
Frequency
-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
-1.0
-0.5
0.0
0.5
1.0
Frequency
-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
-1.0
-0.5
0.0
0.5
1.0
2 1
3
4
FIGURE 31-1
Complex frequency spectrum. These
curves correspond to an entirely real
time domain signal, because the real
part of the spectrum has an even
symmetry, and the imaginary part has
an odd symmetry. The two square
markers in the real part correspond to
a cosine wave with an amplitude of
one, and a frequency of 0.23. The
two round markers in the imaginary
part correspond to a sine wave with an
amplitude of one, and a frequency of
0.23.
Amplitude Amplitude
Figure 31-1 illustrates the complex DFT's frequency spectrum. This figure
assumes the time domain is entirely real, that is, its imaginary part is zero.
We will discuss the idea of imaginary time domain signals shortly. There
are two common ways of displaying a complex frequency spectrum. As
shown here, zero frequency can be placed in the center, with positive
frequencies to the right and negative frequencies to the left. This is the best
way to think about the complete spectrum, and is the only way that an
aperiodic spectrum can be displayed.
The problem is that the spectrum of a discrete signal is periodic (such as with
the DFT and the DTFT). This means that everything between -0.5 and 0.5
repeats itself an infinite number of times to the left and to the right. In this
case, the spectrum between 0 and 1.0 contains the same information as from -
0.5 to 0.5. When graphs are made, such as Fig. 31-1, the -0.5 to 0.5
convention is usually used. However, many equations and programs use the 0
to 1.0 form. For instance, in Eqs. 31-5 and 31-6 the frequency index, k, runs
from 0 to N-1 (coinciding with 0 to 1.0). However, we could write it to run
from -N/2 to N/2-1 (coinciding with -0.5 to 0.5), if we desired.
Using the spectrum in Fig. 31-1 as a guide, we can examine how the inverse
complex DFT reconstructs the time domain signal. The inverse complex DFT,
written in polar form, is given by:
Chapter 31- The Complex Fourier Transform 573
x[n] ’ j N& 1
k’ 0
ReX[k] cos(2Bkn/N ) % j sin (2Bkn/N)
EQUATION 31-8
The inverse complex DFT.
This is Eq. 31-7 rewritten to
show how each value in the
frequency spectrum affects
the time domain.
& j N& 1
k’ 0
ImX[k] sin (2Bkn/N) & j cos (2Bkn/N)
½ cos(2B0.23n) % ½ j sin (2B0.23n)
½ cos(2B(&0.23) n) % ½ j sin (2B(&0.23)n)
½ cos(2B0.23n) & ½ j sin (2B0.23n)
Using Euler's relation, this can be written in rectangular form as:
The compact form of Eq. 31-7 is how the inverse DFT is usually written,
although the expanded version in Eq. 31-9 can be easier to understand. In
words, each value in the real part of the frequency domain contributes a real
cosine wave and an imaginary sine wave to the time domain. Likewise, each
value in the imaginary part of the frequency domain contributes a real sine
wave and an imaginary cosine wave. The time domain is found by adding all
these real and imaginary sinusoids. The important concept is that each value
in the frequency domain produces both a real sinusoid and an imaginary
sinusoid in the time domain.
For example, imagine we want to reconstruct a unity amplitude cosine wave at
a frequency of 2Bk/N . This requires a positive frequency and a negative
frequency, both from the real part of the frequency spectrum. The two square
markers in Fig. 31-1 are an example of this, with the frequency set at:
k /N ’ 0.23 . The positive frequency at 0.23 (labeled 1 in Fig. 31-1) contributes
a cosine wave and an imaginary sine wave to the time domain:
Likewise, the negative frequency at -0.23 (labeled 2 in Fig. 31-1) also
contributes a cosine and an imaginary sine wave to the time domain:
The negative sign within the cosine and sine terms can be eliminated by the
relations: cos(&x) ’ cos(x) and sin(&x) ’ &sin(x) . This allows the negative
frequency's contribution to be rewritten:
574 The Scientist and Engineer's Guide to Digital Signal Processing
½ cos(2B0.23n) % ½ j sin (2B0.23n )
cos(2B0.23n)
contribution from positive frequency !
contribution from negative frequency !
resultant time domain signal !
½ cos(2B0.23n) & ½ j sin (2B0.23n )
contribution from positive frequency ! & ½ sin(2B0.23n) & ½ j cos (2B0.23n )
& sin (2B0.23n)
contribution from negative frequency !
resultant time domain signal !
& ½ sin (2B0.23n) % ½ j cos(2B0.23n )
Adding the contributions from the positive and the negative frequencies
reconstructs the time domain signal:
In this same way, we can synthesize a sine wave in the time domain. In this
case, we need a positive and negative frequency from the imaginary part of the
frequency spectrum. This is shown by the round markers in Fig. 31-1. From
Eq. 31-8, these spectral values contribute a sine wave and an imaginary cosine
wave to the time domain. The imaginary cosine waves cancel, while the real
sine waves add:
Notice that a negative sine wave is generated, even though the positive
frequency had a value that was positive. This sign inversion is an inherent part
of the mathematics of the complex DFT. As you recall, this same sign
inversion is commonly used in the real DFT. That is, a positive value in the
imaginary part of the frequency spectrum corresponds to a negative sine wave.
Most authors include this sign inversion in the definition of the real Fourier
transform to make it consistent with its complex counterpart. The point is, this
sign inversion must be used in the complex Fourier transform, but is merely an
option in the real Fourier transform.
The symmetry of the complex Fourier transform is very important. As
illustrated in Fig. 31-1, a real time domain signal corresponds to a frequency
spectrum with an even real part, and an odd imaginary part. In other words,
the negative and positive frequencies have the same sign in the real part (such
as points 1 and 2 in Fig. 31-1), but opposite signs in the imaginary part (points
3 and 4).
This brings up another topic: the imaginary part of the time domain. Until now
we have assumed that the time domain is completely real, that is, the imaginary
part is zero. However, the complex Fourier transform does not require this.
Chapter 31- The Complex Fourier Transform 575
What is the physical meaning of an imaginary time domain signal? Usually,
there is none. This is just something allowed by the complex mathematics,
without a correspondence to the world we live in. However, there are
applications where it can be used or manipulated for a mathematical
purpose.
An example of this is presented in Chapter 12. The imaginary part of the time
domain produces a frequency spectrum with an odd real part, and an even
imaginary part. This is just the opposite of the spectrum produced by the real
part of the time domain (Fig. 31-1). When the time domain contains both a real
part and an imaginary part, the frequency spectrum is the sum of the two
spectra, had they been calculated individually. Chapter 12 describes how this
can be used to make the FFT algorithm calculate the frequency spectra of two
real signals at once. One signal is placed in the real part of the time domain,
while the other is place in the imaginary part. After the FFT calculation, the
spectra of the two signals are separated by an even/odd decomposition.
The Family of Fourier Transforms
Just as the DFT has a real and complex version, so do the other members of the
Fourier transform family. This produces the zoo of equations shown in Table
31-1. Rather than studying these equations individually, try to understand them
as a well organized and symmetrical group. The following comments describe
the organization of the Fourier transform family. It is detailed, repetitive, and
boring. Nevertheless, this is the background needed to understand theoretical
DSP. Study it well.
1. Four Fourier Transforms
A time domain signal can be either continuous or discrete, and it can be either
periodic or aperiodic. This defines four types of Fourier transforms: the
Discrete Fourier Transform (discrete, periodic), the Discrete Time
Fourier Transform (discrete, aperiodic), the Fourier Series (continuous,
periodic), and the Fourier Transform (continuous, aperiodic). Don't try to
understand the reasoning behind these names, there isn't any.
If a signal is discrete in one domain, it will be periodic in the other. Likewise,
if a signal is continuous in one domain, will be aperiodic in the other.
Continuous signals are represented by parenthesis, ( ), while discrete signals
are represented by brackets, [ ]. There is no notation to indicate if a signal is
periodic or aperiodic.
2. Real versus Complex
Each of these four transforms has a complex version and a real version. The
complex versions have a complex time domain signal and a complex frequency
domain signal. The real versions have a real time domain signal and two real
frequency domain signals. Both positive and negative frequencies are used in
the complex cases, while only positive frequencies are used for the real
transforms. The complex transforms are usually written in an exponential
576 The Scientist and Engineer's Guide to Digital Signal Processing
form; however, Euler's relation can be used to change them into a cosine and
sine form if needed.
3. Analysis and Synthesis
Each transform has an analysis equation (also called the forward transform)
and a synthesis equation (also called the inverse transform). The analysis
equations describe how to calculate each value in the frequency domain based
on all of the values in the time domain. The synthesis equations describe how
to calculate each value in the time domain based on all of the values in the
frequency domain.
4. Time Domain Notation
Continuous time domain signals are called x (t ), while discrete time domain
signals are called x[n] . For the complex transforms, these signals are complex.
For the real transforms, these signals are real. All of the time domain signals
extend from minus infinity to positive infinity. However, if the time domain is
periodic, we are only concerned with a single cycle, because the rest is
redundant. The variables, T and N, denote the periods of continuous and
discrete signals in the time domain, respectively.
5. Frequency Domain Notation
Continuous frequency domain signals are called X(T) if dt hey are complex, an ReX(T)
& ImX(T) if they ared real. Discrete frequency domain signals are calle X[k]
if they are complex, and ReX [k ] & ImX [k ] if they are real. The complex
transforms have negative frequencies that extend from minus infinity to zero,
and positive frequencies that extend from zero to positive infinity. The real
transforms only use positive frequencies. If the frequency domain is periodic,
we are only concerned with a single cycle, because the rest is redundant. For
continuous frequency domains, the independent variable, T, makes one complete
period from -B to B. In the discrete case, we use the period where k runs from
0 to N-1
6. The Analysis Equations
The analysis equations operate by correlation, i.e., multiplying the time
domain signal by a sinusoid and integrating (continuous time domain) or
summing (discrete time domain) over the appropriate time domain section.
If the time domain signal is aperiodic, the appropriate section is from minus
infinity to positive infinity. If the time domain signal is periodic, the
appropriate section is over any one complete period. The equations shown
here are written with the integration (or summation) over the period: 0 to
T (or 0 to N-1). However, any other complete period would give identical
results, i.e., -T to 0, -T/2 to T/2, etc.
7. The Synthesis Equations
The synthesis equations describe how an individual value in the time domain
is calculated from all the points in the frequency domain. This is done by
multiplying the frequency domain by a sinusoid, and integrating (continuous
frequency domain) or summing (discrete frequency domain) over the
appropriate frequency domain section. If the frequency domain is complex and
aperiodic, the appropriate section is negative infinity to positive infinity. If the
Chapter 31- The Complex Fourier Transform 577
Using f instead of T by the relation: T’ 2Bf
Integrating over other periods, such as: -T to 0, -T/2 to T/2, or 0 to T
Moving all or part of the scaling factor to the synthesis equation
Replacing the period with the fundamental frequency, f0
’ 1/T
Using other variable names, for example, T can become S in the DTFT,
and Re X [k] & Im Xs [k] can become ak & bk in the Fourier Serie
frequency domain is complex and periodic, the appropriate section is over one
complete cycle, i.e., -B to B (continuous frequency domain), or 0 to N-1
(discrete frequency domain). If the frequency domain is real and aperiodic, the
appropriate section is zero to positive infinity, that is, only the positive
frequencies. Lastly, if the frequency domain is real and periodic, the
appropriate section is over the one-half cycle containing the positive
frequencies, either 0 to B (continuous frequency domain) or 0 to N/2 (discrete
frequency domain).
8. Scaling
To make the analysis and synthesis equations undo each other, a scaling factor
must be placed on one or the other equation. In Table 31-1, we have placed
the scaling factors with the analysis equations. In the complex case, these
scaling factors are: 1/N, 1/T, or 1/2B. Since the real transforms do not use
negative frequencies, the scaling factors are twice as large: 2/N, 2/T, or 1/B.
The real transforms also include a negative sign in the calculation of the
imaginary part of the frequency spectrum (an option used to make the real
transforms more consistent with the complex transforms). Lastly, the synthesis
equations for the real DFT and the real Fourier Series have special scaling
instructions involving Re X(0 ) and Re X [N/2] .
9. Variations
These equations may look different in other publications. Here are a few
variations to watch out for:
Why the Complex Fourier Transform is Used
It is painfully obvious from this chapter that the complex DFT is much more
complicated than the real DFT. Are the benefits of the complex DFT really
worth the effort to learn the intricate mathematics? The answer to this
question depends on who you are, and what you plan on using DSP for. A
basic premise of this book is that most practical DSP techniques can be
understood and used without resorting to complex transforms. If you are
learning DSP to assist in your non-DSP research or engineering, the
complex DFT is probably overkill.
Nevertheless, complex mathematics is the primary language of those that
specialize in DSP. If you do not understand this language, you cannot
communicate with professionals in the field. This includes the ability to
understand the DSP literature: books, papers, technical articles, etc. Why are
complex techniques so popular with the professional DSP crowd?
578 The Scientist and Engineer's Guide to Digital Signal Processing
Discrete Fourier Transform (DFT)
x[n] ’ j N&1
k’ 0
X[k] e j 2Bk n/N x[n] ’ j N/2
k’ 0
ReX[k] cos(2Bkn/N )
X[k] ’ 1
N
j N&1
n’ 0
x[n] e &j 2Bkn/N
ImX[k] ’
&2
N
j N&1
n’ 0
x[n] sin (2Bkn/N )
& ImX[k] sin (2Bkn/N )
ReX[k] ’ 2
N
j N&1
n’ 0
x[n] cos(2Bkn/N )
complex transform real transform
synthesis
analysis
synthesis
analysis
Time domain:
x[n] is complex, discrete and periodic
n runs over one period, from 0 to N-1
Frequency domain:
X[k] is complex, discrete and periodic
k runs over one period, from 0 to N-1
k = 0 to N/2 are positive frequencies
k = N/2 to N-1 are negative frequencies
Time domain:
x[n] is real, discrete and periodic
n runs over one period, from 0 to N-1
Frequency domain:
Re X[k] is real, discrete and periodic
Im X[k] is real, discrete and periodic
k runs over one-half period, from 0 to N/2
Note: Before using the synthesis equation, the values
for Re X[0] and Re X[N/2] must be divided by two.
Discrete Time Fourier Transform (DTFT)
x[n] ’ m
2B
0
X(T) e jTn dT x[n] ’ m
B
0
ReX(T) cos(Tn)
X(T) ’ 1
2B j%4
n ’&4
x[n] e &jTn
ImX(T) ’
&1
B j%4
n’&4
x[n] sin (Tn)
& ImX (T) sin(Tn)dT
ReX(T) ’ 1
B j%4
n’&4
x[n]cos(Tn)
complex transform real transform
synthesis
analysis
synthesis
analysis
Time domain:
x[n] is complex, discrete and aperiodic
n runs from negative to positive infinity
Frequency domain:
X(T) is complex, continuous, and periodic
T runs over a single period, from 0 to 2B
T = 0 to B are positive frequencies
T = B to 2B are negative frequencies
Time domain:
x[n] is real, discrete and aperiodic
n runs from negative to positive infinity
Frequency domain:
Re X(T) is real, continuous and periodic
Im X(T) is real, continuous and periodic
T runs over one-half period, from 0 to B
TABLE 31-1 The Fourier Transforms
Chapter 31- The Complex Fourier Transform 579
Fourier Series
x(t ) ’ j%4
k’ &4
X[k] e j 2Bkt /T x(t ) ’ j%4
k’ 0
ReX[k] cos(2Bkt /T )
X[k] ’ 1
T mT
0
x(t ) e &j 2Bkt /T dt
& ImX[k] sin (2Bkt /T )
ReX[k] ’ 2
T mT
0
x(t ) cos(2Bkt /T ) dt
complex transform real transform
synthesis
analysis
synthesis
analysis
Time domain:
x(t) is complex, continuous and periodic
t runs over one period, from 0 to T
Frequency domain:
X[k] is complex, discrete, and aperiodic
k runs from negative to positive infinity
k > 0 are positive frequencies
k < 0 are negative frequencies
Time domain:
x(t) is real, continuous, and periodic
t runs over one period, from 0 to T
Frequency domain:
Re X[k] is real, discrete and aperiodic
Im X[k] is real, discrete and aperiodic
k runs from zero to positive infinity
Note: Before using the synthesis equation, the value for
Re X[0] must be divided by two.
ImX[k] ’
&2
T mT
0
x(t ) sin (2Bkt /T ) dt
Fourier Transform
x(t ) ’ m
%4
&4
X(T) e jTt dT x(t ) ’ m
%4
0
ReX(T) cos(Tt)
X(T) ’ 1
2B m
%4
&4
x(t ) e &jTt dt
& ImX(T) sin (Tt) dt
ReX(T) ’ 1
B m
%4
&4
x(t ) cos(Tt) dt
complex transform real transform
synthesis
analysis
synthesis
analysis
Time domain:
x(t) is complex, continious and aperiodic
t runs from negative to positive infinity
Frequency domain:
X(T) is complex, continious, and aperiodic
T runs from negative to positive infinity
T > 0 are positive frequencies
T < 0 are negative frequencies
Time domain:
x(t) is real, continuous, and aperiodic
t runs from negative to positive infinity
Frequency domain:
Re X[T] is real, continuous and aperiodic
Im X[T] is real, continuous and aperiodic
T runs from zero to positive infinity
TABLE 31-1 The Fourier Transforms
ImX(T) ’
&1
B m
%4
&4
x(t ) sin (Tt) dt
580 The Scientist and Engineer's Guide to Digital Signal Processing
There are several reasons we have already mentioned: compact equations,
symmetry between the analysis and synthesis equations, symmetry between the
time and frequency domains, inclusion of negative frequencies, a stepping stone
to the Laplace and z-transforms, etc.
There is also a more philosophical reason we have not discussed, something
called truth. We started this chapter by listing several ways that the real
Fourier transform is awkward. When the complex Fourier transform was
introduced, the problems vanished. Wonderful, we said, the complex Fourier
transform has solved the difficulties.
While this is true, it does not give the complex Fourier transform its proper
due. Look at this situation this way. In spite of its abstract nature, the complex
Fourier transform properly describes how physical systems behave. When we
restrict the mathematics to be real numbers, problems arise. In other words,
these problems are not solved by the complex Fourier transform, they are
introduced by the real Fourier transform. In the world of mathematics, the
complex Fourier transform is a greater truth than the real Fourier transform.
This holds great appeal to mathematicians and academicians, a group that
strives to expand human knowledge, rather than simply solving a particular
problem at hand.
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 1 of 16
a
Basic Mathematical
Subroutines for the ADMC300
AN300-09
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 2 of 16
Table of Contents
SUMMARY...................................................................................................................... 3
1 THE MATHEMATICAL LIBRARY ROUTINES ........................................................ 3
1.1 Using the Mathematical Routines .................................................................................................................3
1.2 Formats of inputs and outputs and usage of DSP core registers ................................................................4
1.3 Square Root.....................................................................................................................................................4
1.4 Logarithm........................................................................................................................................................6
1.4.1 Common Logarithm (Base 10) ................................................................................................................6
1.4.2 Natural Logarithm....................................................................................................................................6
1.5 Reciprocal........................................................................................................................................................8
2.2 Division........................................................................................................................................................8
1.6 Access to the library: the header file.............................................................................................................9
2 SOFTWARE EXAMPLE: TESTING THE MATHEMATICAL FUNCTIONS ........... 10
2.1 The main program: main.dsp......................................................................................................................10
2.2 The main include file: main.h ......................................................................................................................12
2.3 Example outputs ...........................................................................................................................................13
2.3.1 Square Root ...........................................................................................................................................13
2.3.2 Logarithm ..............................................................................................................................................14
2.3.3 Division..................................................................................................................................................15
2.3.4 Reciprocal ..............................................................................................................................................15
3 DIFFERENCES BETWEEN LIBRARY AND ADMC300 “ROM-UTILITIES” ......... 16
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 3 of 16
Summary
This application note illustrates the usage of some basic trigonometric subroutines such as sine and
cosine. They are implemented in a library-like module for easy access. The realisation follows the one
described in chapter 4 of the DSP applications handbook1. Then, a software example will be described
that may be downloaded from the accompanying zipped files. Finally, some data will be shown
concerning the accuracy of the algorithms.
1 The Mathematical Library Routines
1.1 Using the Mathematical Routines
The routines are developed as an easy-to-use library, which has to be linked to the user’s application. The
library consists of two files. The file “mathfun.dsp” contains the assembly code for the subroutines. This
package has to be compiled and can then be linked to an application. The user simply has to include the
header file “mathfun.h”, which provides function-like calls to the routines. The following table
summarises the set of macros that are defined in this library. Note that every function stores the result in
the sr1 register, except for the division routine which makes the results available in ar.
Operation Usage Operands
Initialisation Set_DAG_registers_for_math_function; none
Square Root Square_Root (integer_part, fractional_part);
integer_part = dreg2 or constant
fractional_part = dreg3 or constant
Logarithm Base 10 Log10(integer_part, fractional_part);
integer_part = dreg2 or constant
fractional_part = dreg3 or constant
Natural Logarithm LogN(integer_part, fractional_part);
integer_part = dreg2 or constant
fractional_part = dreg3 or constant
Reciprocal Inverse(integer_part, fractional_part);
integer_part = dreg2 or constant
fractional_part = dreg3 or constant
Signed Division Signed_Division(integer_part, fractional_part);
integer_part = dreg2 or constant
fractional_part = dreg3 or constant
Table 1: Implemented routines
The routines do not require any configuration constants from the main include-file “main.h” that comes
with every application note. For more information about the general structure of the application notes and
including libraries into user applications refer to the Library Documentation File. Section 2 shows an
example of usage of this library. In the following sections each routine is explained in detail with the
relevant segments of code which is found in either “mathfun.h” or “mathfun.dsp”. For more information
see the comments in those files.
1 a ”Digital Signal Applications using the ADSP-2100 Family”, Volume 1, Prentice Hall, 1992
2 Any data register of the ADSP-2171 core except mr0
3 Any data register of the ADSP-2171 core except mr1
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 4 of 16
1.2 Formats of inputs and outputs and usage of DSP core registers
The implementation of the macros listed in the previous section is based on the subroutines of Table 2.
Note that the first four accept input in the unsigned 16.16 format and that the output is in various single
precision format. The division routine expects a signed double precision value (for instance 1.31 or 8.24
…). Its output is in the ar register in a format that is determined by the input.
It may also be noted that the DAG registers M5 and L5 must be set to 1 and 0 respectively and that they
are not modified by the mathematical routines. The already mentioned call to
Set_DAG_registers_for_math_function prepares these registers for the functions. It now becomes clear
that this routine is necessary only once if M5 and/or L5 are not modified in another part of the user’s
code, as shown in the example in section 2.
Refer to the above-mentioned DSP applications handbook for more details on the routines described in
the previous sections.
Subroutine Input Output Modified Registers Other registers
(Must be set)
sqrt_(x) MR1, MR0 unsigned
16.16 Format
0 ≤ X <65536
SR1 in unsigned
8.8 format
AX0,AX1,AY0,AY1,AF,AR,
MY0, MY1,MX0,MF, MR,
SE, SR, I5
M5=1
L5=0
Log10_(x) MR1, MR0 unsigned
16.16 format
0 ≤ X <65536
SR1 in signed 4.12
format
AX0, AX1,AY0,AR,
MY1, MX0, MX1, MF, MR,
SE, SR, I5
M5=1
L5=0
Ln_(x) MR1, MR0 unsigned
16.16 format
0 ≤ X <65536
SR1 in signed
5.11 format
AX0, AX1,AY0,AR,
MY1, MX0, MX1, MF, MR,
SE, SR, I5
M5=1
L5=0
inv_(x) MR1, MR0 16.16
Format 1 ≤ x <32768
SR1 in signed 1.15
format
AX0,AY1, AY0,
MR1, MR0,
SR1, SR0
---
div_(x) Dividend NL.NR format
Divisor DL.DR format
AR in signed (NL
–DL+1).(NR-DR-
1) format
AX0, AX1, AR, AF, AY0, AY1
---
Table 2: Input and output format, modified registers for the mathematical routines
1.3 Square Root
The following equation approximates the square root of the input value x, where 0.5 ≤ x ≤1:
0.0560605 0.1037903
0.5* ( ) 0.7274475 0.672455 0.553406 0.2682495
5
2 3 4
+ +
= − + − +
x
sqrt x x x x x
( 1)
Text Box 1.2 shows the part of subroutine for getting square root when the original input falls into the
equation valid range between 0.5 and 1.0.
In the square root subroutine, the input is in 16.16 format, with unsigned integer in MR1 register and full
fraction in MR0 register. Therefore, the valid input range for the square root subroutine is between 0 and
65536 (0xFFFF.FFFF). If the input value is out of the range between 0.5 and 1.0, the square root
subroutine will scale the input in MR1 and MR0 registers by shift operation so that the scaled value will
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 5 of 16
fall into the valid equation range as input to equation ( 1) for computation. Obviously, the square root of
the scaled input obtained from equation ( 1) must be multiplied by the square root of the scaling value to
produce the square root of the original input as implemented in the following segment.
.VAR/PM/RAM/SEG=USER_PM1 sqrt_coeff[5];
.INIT sqrt_coeff : 0x5D1D00, 0xA9ED00, 0x46D600, 0xDDAA00, 0x072D00;
sqrt_: AX1=MR1; { store for knowing MSB }
AR = PASS MR1;
IF GE JUMP calculation; {MSB = 1 ?}
SR = LSHIFT MR1 BY -1 (HI); { left shift by 1 }
SR = SR OR LSHIFT MR0 BY -1 (LO);
MR1 = SR1; MR0 = SR0;
calculation: I5 = ^sqrt_coeff; {pointer to coeff. buffer}
SE=EXP MR1 (HI); {Check for redundant bits}
SE=EXP MR0 (LO);
AX0=SE, SR=Norm MR1 (HI);
SR=SR OR NORM MR0 (LO);
MY0=SR1, AR=PASS SR1;
IF EQ RTS;
MR=0;
MR1=base; {Load constant value}
MF=AR*MY0 (RND), MX0=PM(I5,M5); {MF =x*x}
MR=MR+MX0*MY0 (SS), MX0=PM(I5,M5); {MR = base + C1*x}
CNTR=4;
DO approx UNTIL CE;
MR=MR+MX0*MF (SS), MX0=PM(I5,M5);
approx: MF=AR*MF (RND);
AY0=15;
MY0=MR1, AR=AX0+AY0; {SE + 15 = 0?}
IF NE JUMP scale; {No, compute scaling value}
SR=ASHIFT MR1 BY -6 (HI);
Jump modification;
The next segment shows that the scaling value (1 2) 15 = ÷ + SE s is calculated where SE is the exponent
detector value of the original input. If (SE+15) is negative, it means that original input is less than 0.5
and the approximated result of the scaled input is to be multiplied by the scaling number of
15 (1 2) ÷ + SE . Otherwise, the original value is larger than 1.0 and the approximated square root of the
scaled input is multiplied with the reciprocal of the scaling number in order to get the result of the original
input. It should be realised that equation ( 1) is for calculation of 0.5*Square_Root(x) and it is one of the
factors under consideration when the subroutine Square_Root(x) shifts the result to get 8.8 format for the
output of the original input.
scale: MR=0;
MR1=sqrt2a; {Load 1/sqrt2(2)}
MY1=MR1, AR=ABS AR;
AY0=AR;
AR=AY0-1;
IF EQ JUMP pwr_ok;
CNTR=AR; {Compute S=(1/sqrt2(2))^(ABS(SE+15)) }
DO compute UNTIL CE;
compute: MR=MR1*MY1 (RND);
pwr_ok: IF NEG JUMP frac; {If (SE+15) is negative, ...}
AY1=0x0080; {Load a 1 in 9.23 format}
AY0=0; {calculate 1/S, if (SE+15) positive }
DIVS AY1, MR1;
DIVQ MR1; DIVQ MR1; DIVQ MR1;
DIVQ MR1; DIVQ MR1; DIVQ MR1;
DIVQ MR1; DIVQ MR1; DIVQ MR1;
DIVQ MR1; DIVQ MR1; DIVQ MR1;
DIVQ MR1; DIVQ MR1; DIVQ MR1;
MX0=AY0;
MR=0;
MR0=0x2000;
MR=MR+MX0*MY0 (US); { 9.23 format in result }
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 6 of 16
SR=ASHIFT MR1 BY 2 (HI); { to compensate the coefficient scaling }
SR=SR OR LSHIFT MR0 BY 2 (LO); { and get 8.8 format }
Jump modification;
frac: MR=MR1*MY0 (RND);
SR=ASHIFT MR1 BY -6 (HI); { compensate coefficient scaling }
{ and get 8.8 format}
modification: AR = PASS AX1;
IF GE RTS; { MSB = 1? }
MY1 = sqrt_2; { if yes, the original left shifted 1 bit }
MR = SR1 * MY1(uu); { multiplied by sqrt2(2) to get final result }
SR1 = MR1;
RTS;
1.4 Logarithm
1.4.1 Common Logarithm (Base 10)
The following equation approximates the common logarithm of the input value 11, is shown here. If the input
falls outside of this valid range, the output will reach saturation and ALU overflow bit AC in the ASTAT
register will be set. The integer part of the input is stored in MR1 register in signed 16.0 twos complement
format, while the fractional part of the input in MR0 in 0.16 format. The final result is in signed 1.15
format in SR1 register.
inv_: AR = PASS MR1;
IF GE JUMP dps1; { x >= 0 ?? }
JUMP dps2;
dps1: AY1 = 0x1; AY0 = 0x0; { x > 1 ?? }
AR = MR0-AY0;
SR0=AR, AR = MR1-AY1+C-1;
JUMP overflow;
dps2: SR1 = 0xFFFF; SR0 = 0x0; { x < -1 }
AY1 = MR1; AY0 = MR0;
AR = SR0-AY0;
AR = SR1-AY1+C-1;
overflow: IF GT JUMP inv_1; { if ABS(x)<=1, overflow }
SR1 = 0x7FFF;
AR = PASS AY1;
IF GT JUMP Returning;
SR1 = 0x8000;
Returning: ASTAT=0x4; { set AV }
RTS;
inv_1: AY1=0x4000; { if ABS(x)>1, division start here }
AY0=0; { numerator = 1 }
SE=EXP MR1 (HI); {Check for redundant bits}
SR=NORM MR1 (HI);
SR=SR OR NORM MR0 (LO);
DIVS AY1, SR1;
DIVQ SR1; DIVQ SR1; DIVQ SR1;
DIVQ SR1; DIVQ SR1; DIVQ SR1;
DIVQ SR1; DIVQ SR1; DIVQ SR1;
DIVQ SR1; DIVQ SR1; DIVQ SR1;
DIVQ SR1; DIVQ SR1; DIVQ SR1;
MR1= AY0; { in 1.15 format }
AX0=-14; AY1=SE;
AR = AX0 - AY1;
SE = AR;
SR = ASHIFT MR1 (HI); { Output in SR1 in 1.15 format }
RTS;
2.2 Division
A single-precision division subroutine is implemented hereafter, with a 32-bit signed dividend
(numerator) and a 16-bit signed divisor (denominator) to yield a 16-bit quotient. The dividend is in
NL.NR format and divisor is in DL.DR format. The quotient will be in (NL-DL+1).(NR-DR-1) format.
For example, if the divisor is in 1.31 format and divisor 1.15 format, the quotient will be in 1.15 format.
Some format manipulation may be necessary to guarantee the validity of the quotient, otherwise, the
output may saturate and AV in ASTAT register is set. For example, if both operands are positive and
fully fractional with dividend and divisor in 1.31 and 1.15 signed format respectively, the result is fully
fractional in 1.15 format and therefore the dividend must be smaller than the divisor for a valid result.
This subroutine can not be used for integer division or unsigned division.
div_: AX1=AY1,AF=AX0-AY1;
AR=ABS AX0;
if NE JUMP test_2;
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 9 of 16
AR=0x7FFF;
AF=PASS AY1;
if LT AR= NOT AR; {return +/- infinity}
ASTAT=0x4; {Division by Zero }
RTS;
test_2: {Division by -1}
if NOT AV JUMP test_3;
AR = -AY1; {Return -x }
RTS;
test_3: {x=y therefore return 1}
AF=PASS AF;
if NE JUMP test_4;
AR=0x7FFF;
ASTAT=0x0;
RTS;
test_4:
AX1=AY1,AR=ABS AX0;
AF=ABS AX1;
AF=AF-AR;
if LT JUMP do_div;
AR=0x7FFF;
AF=PASS AY1;
if LT AR= NOT AR; {return - infinity}
AF=PASS AX0;
if LT AR= NOT AR; {return - * - infinity}
ASTAT=0x4; {Division Overflow}
RTS;
do_div:
DIVS AY1,AX0;
CNTR=15;
do do_div01 until ce;
do_div01: DIVQ AX0;
AR=AY0;
AF=PASS AX0;
if LT AR=-AR;
RTS;
1.6 Access to the library: the header file
The library may be accessed by including the header file “mathfun.h” into the application code.
The header file is intended to provide function-like calls to the routines presented in the previous section. It
defines the calls shown in Table 1. The file is self-explaining and needs no further comments.
It is worth adding a few comments about efficiency of these routines. The first macro simply sets the DAG
registers M5 and L5 to its correct values. The user may however just replace the macro with one of its
instructions when the application code modifies just one of these registers. The sine and cosine subroutines
expect the argument to be placed into certain registers. This is what the macros do. However, if the argument
is already in the correct registers, the macro call inserts obsolete instruction. In this case, it is more efficient
to replace the macro call by a call instruction to the corresponding subroutine.
.MACRO Set_DAG_registers_for_math_function;
M5 = 1;
L5 = 0;
.ENDMACRO;
.MACRO Square_Root(%0, %1);
MR1 = %0;
MR0 = %1;
call sqrt_;
.ENDMACRO;
.MACRO Log10(%0, %1);
MR1 = %0;
MR0 = %1;
call Log10_;
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 10 of 16
.ENDMACRO;
.MACRO LogN(%0, %1);
MR1 = %0;
MR0 = %1;
call ln_;
.ENDMACRO;
.MACRO Inverse(%0, %1);
MR1 = %0;
MR0 = %1;
call inv_;
.ENDMACRO;
.MACRO Signed_Division(%0,%1,%2);
AY1 = %0;
AY0 = %1;
AX0 = %2;
call div_;
.ENDMACRO;
.MACRO Atan(%0, %1);
mr1= %0;
mr0= %1;
call Atan_;
.ENDMACRO;
2 Software Example: Testing the Mathematical Functions
2.1 The main program: main.dsp
The example demonstrates how to use the routines. All it does is to cycle through parts of the range of
definition of the functions and converting the results by means of the digital to analog converter. The
application has been adapted from two previous notes4,5. This section will only explain the few and
intuitive modifications to those applications.
The file “main.dsp” contains the initialisation and PWM Sync and Trip interrupt service routines. To
activate, build the executable file using the attached build.bat either within your DOS prompt or clicking
on it from Windows Explorer. This will create the object files and the main.exe example file. This file
may be run on the Motion Control Debugger.
In the following, a brief description of the additional code (put in evidence by bold characters) is given.
Start of code – declaring start location in program memory
.MODULE/RAM/SEG=USER_PM1/ABS=0x60 Main_Program;
Next, the general systems constants and PWM configuration constants (main.h – see the next section) are
included. Also included are the PWM library, the DAC interface library, the trigonometric library and the
mathematical library.
{***************************************************************************************
* Include General System Parameters and Libraries *
***************************************************************************************}
#include ;
#include ;
#include ;
#include ;
4 AN300-03: Three-Phase Sine-Wave Generation using the PWM Unit of the ADMC300
5 AN300-06: Using the Serial Digital to Analog Converter of the ADMC Connector Board
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 11 of 16
#include ;
The argument variable Theta is defined hereafter.
{***************************************************************************************
* Local Variables Defined in this Module *
***************************************************************************************}
.VAR/DM/RAM/SEG=USER_DM Theta; { Current angle }
.INIT Theta : 0x0000;
First, the PWM block is set up to generate interrupts every 100μs (see “main.h” in the next Section). The
variable Theta, which stores the argument of the trigonometric functions, is set to zero. Before using the
trigonometric functions, it is necessary to initialise certain registers of the data-address-generator (DAG) of
the DSP core. This will be discussed in more detail in the next section. However, note that this is done only
once in this example. If those registers are modified in other parts of the user’s code, then it must be repeated
before a call to a trigonometric function.
The main loop just waits for interrupts.
{********************************************************************************************}
{ Start of program code }
{********************************************************************************************}
Startup:
PWM_Init(PWMSYNC_ISR, PWMTRIP_ISR);
DAC_Init;
IFC = 0x80; { Clear any pending IRQ2 inter. }
ay0 = 0x200; { unmask irq2 interrupts. }
ar = IMASK;
ar = ar or ay0;
IMASK = ar; { IRQ2 ints fully enabled here }
ar = pass 0;
DM(Theta)= ar;
Set_DAG_registers_for_trigonometric;
Main: { Wait for interrupt to occur }
jump Main;
rts;
The interrupt service routine simply shows how to use the described functions. Variable Theta is incremented
in every interrupt service and is used as input for testing the mathematical functions. This main routine is
very similar to the one used in Application Note: AN300-10.
{********************************************************************************************}
{ PWM Interrupt Service Routine }
{********************************************************************************************}
PWMSYNC_ISR:
AX1 = DM(THETA);
COS(ax1);
DAC_PUT(1, AR); { output cos(x) }
MY0 = 0x4000;
MR = AR * MY0(SS);
AY0 = 0x4000;
AR = MR1 + AY0;
SR = LSHIFT AR BY 1 (LO);
Square_Root(SR1, SR0);
SR = LSHIFT SR1 BY 7 (HI);
DAC_PUT(2, SR1); { output ABS(cos(x/2) }
SR1 = DM(THETA);
SR0 = 0;
Square_Root(SR1, SR0);
SR = LSHIFT SR1 BY -1 (HI); { output Square_Root(x) }
DAC_PUT(3, SR1);
AX1 = DM(THETA); { log10(x), fractional input }
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 12 of 16
LOG10(0x0000,AX1);
DAC_PUT(4, SR1);
AX1 = DM(THETA); { Log10(x), integer input }
LOG10(AX1, 0x0000);
DAC_PUT(5, SR1);
AX1 = DM(THETA); { LogN(x), fractional input }
LogN(0x0000,AX1);
DAC_PUT(6, SR1);
AX1 = DM(THETA); { LogN(x), integer input }
LogN(AX1, 0x0000);
DAC_PUT(7, SR1);
{ tan(x) for division test }
{ AX0= DM(THETA);
AY1 = 0x1FFF; AR=ABS AX0;
AR = AR - AY1;
IF GT JUMP No_div;
cos(AX0);
AX1 = AR;
sin(AX0);
Signed_Division(AR,0x0000,AX1);
Jump PUT;
No_div: AR = 0;
PUT: DAC_PUT(8, AR);
}
SR1 = DM(THETA); { Inverse(x) }
SR = ASHIFT SR1 by -11 (HI);
Inverse(SR1, SR0);
DAC_PUT(8, SR1);
DAC_Update;
ax1= DM(Theta);
ar= ax1 +1;
DM(Theta)= ar;
RTI;
2.2 The main include file: main.h
This file contains the definitions of ADMC300 constants, general-purpose macros and the configuration
parameters of the system and library routines. It should be included in every application. For more
information refer to the Library Documentation File.
This file is mostly self-explaining. As already mentioned, the trigonometric library does not require any
configuration parameters. The following defines the parameters for the PWM ISR used in this example.
{********************************************************************************************}
{ Library: PWM block }
{ file : PWM300.dsp }
{ Application Note: Usage of the ADMC300 Pulse Width Modulation Block }
.CONST PWM_freq = 10000; {Desired PWM switching frequency [Hz] }
.CONST PWM_deadtime = 1000; {Desired deadtime [nsec] }
.CONST PWM_minpulse = 1000; {Desired minimal pulse time [nsec] }
.CONST PWM_syncpulse = 1540; {Desired sync pulse time [nsec] }
{********************************************************************************************}
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 13 of 16
2.3 Example outputs
2.3.1 Square Root
The example applies the square root function to perform the calculation of equation (4.1). The result is
directed to the digital to analog converters on the connection board. Figure 1 shows the output waveforms
of cos(x) and cos(x / 2) .
It is well known that
2
cos( ) 1
cos( ) / 2) = + x
x ( 6)
Figure 1: cos(x) and cos(x / 2)
The valid input to the square root function is from 0x0000.0000 to 0xFFFF.FFFF in MR registers. For the
D/A converter, digital value 0 is corresponding to 2.5v, -1 to 0V and +1 to 5V in the DAC outputs.
Figure 2: Square _ Root(x)
Figure 2 shows the result in another test when x is increased from 0x0000.0000 to 0xFFFF.0000. The
output is in a range of 0x00.00 and 0xFF.00.
a Basic Mathematical Subroutines for the ADMC300 AN300-09
© Analog Devices Inc., January 2000 Page 14 of 16
2.3.2 Logarithm
2.3.2.1 Common logarithm
Figure 3 shows the results of calculating log10(x) for an input range 0= 0 THEN PHASE[K%] = PHASE[K%] + PI
300 NEXT K%
310 '
320 '
330 ' 'Polar-to-rectangular conversion, Eq. 8-7
340 FOR K% = 0 TO 256
350 REX[K%] = MAG[K%] * COS( PHASE[K%] )
360 IMX[K%] = MAG[K%] * SIN( PHASE[K%] )
370 NEXT K%
380 '
390 END
TABLE 8-3
Nuisance 2: Divide by zero error
When converting from rectangular to polar notation, it is very common to
find frequencies where the real part is zero and the imaginary part is some
nonzero value. This simply means that the phase is exactly 90 or -90
degrees. Try to tell your computer this! When your program tries to
calculate the phase from: Phase X[k] ’ arctan( Im X[k] / Re X[k]) , a divide by
zero error occurs. Even if the program execution doesn't halt, the phase
you obtain for this frequency won't be correct. To avoid this problem, the
real part must be tested for being zero before the division. If it is zero, the
imaginary part must be tested for being positive or negative, to determine
whether to set the phase to B/2 or -B/2, respectively. Lastly, the division
needs to be bypassed. Nothing difficult in all these steps, just the potential
for aggravation. An alternative way to handle this problem is shown in
line 250 of Table 8-3. If the real part is zero, change it to a negligibly
small number to keep the math processor happy during the division.
Nuisance 3: Incorrect arctan
Consider a frequency domain sample where ReX[k] ’ 1 and Im X[k] ’ 1.
Equation 8-6 provides the corresponding polar values of Mag X[k] ’ 1.414 and
Phase X[k] ’ 45E. Now consider another sample where ReX[k] ’ &1 and
166 The Scientist and Engineer's Guide to Digital Signal Processing
FIGURE 8-11
The phase of small magnitude signals. At frequencies where the magnitude drops to a very low value, round-off
noise can cause wild excursions of the phase. Don't make the mistake of thinking this is a meaningful signal.
Frequency
0 0.1 0.2 0.3 0.4 0.5
0.0
0.5
1.0
1.5
a. Mag X[ ]
Frequency
0 0.1 0.2 0.3 0.4 0.5
-5
-4
-3
-2
-1
0
1
2
3
4
5
b. Phase X[ ]
Amplitude
Phase (radians)
Im X[k] ’ &1. Again, Eq. 8-6 provides the values of Mag X[k] ’ 1.414 and
Phase X[k] ’ 45E. The problem is, the phase is wrong! It should be &135E.
This error occurs whenever the real part is negative. This problem can be
corrected by testing the real and imaginary parts after the phase has been
calculated. If both the real and imaginary parts are negative, subtract 180E
(or B radians) from the calculated phase. If the real part is negative and the
imaginary part is positive, add 180E (or B radians). Lines 340 and 350 of the
program in Table 8-3 show how this is done. If you fail to catch this problem,
the calculated value of the phase will only run between -B/2 and B/2, rather
than between -B and B. Drill this into your mind. If you see the phase only
extending to ±1.5708, you have forgotten to correct the ambiguity in the
arctangent calculation.
Nuisance 4: Phase of very small magnitudes
Imagine the following scenario. You are grinding away at some DSP task, and
suddenly notice that part of the phase doesn't look right. It might be noisy,
jumping all over, or just plain wrong. After spending the next hour looking
through hundreds of lines of computer code, you find the answer. The
corresponding values in the magnitude are so small that they are buried in
round-off noise. If the magnitude is negligibly small, the phase doesn't have
any meaning, and can assume unusual values. An example of this is shown in
Fig. 8-11. It is usually obvious when an amplitude signal is lost in noise; the
values are so small that you are forced to suspect that the values are
meaningless. The phase is different. When a polar signal is contaminated
with noise, the values in the phase are random numbers between -B and B.
Unfortunately, this often looks like a real signal, rather than the nonsense it
really is.
Nuisance 5: 2B ambiguity of the phase
Look again at Fig. 8-10d, and notice the several discontinuities in the data.
Every time a point looks as if it is going to dip below -3.14592, it snaps
back to 3.141592. This is a result of the periodic nature of sinusoids. For
Chapter 8- The Discrete Fourier Transform 167
FIGURE 8-12
Example of phase unwrapping. The top curve
shows a typical phase signal obtained from a
rectangular-to-polar conversion routine. Each
value in the signal must be between -B and B
(i.e., -3.14159 and 3.14159). As shown in the
lower curve, the phase can be unwrapped by
adding or subtracting integer multiplies of 2B
from each sample, where the integer is chosen
to minimize the discontinuities between points.
Frequency
0 0.1 0.2 0.3 0.4 0.5
-40
-30
-20
-10
0
10
wrapped
unwrapped
Phase (radians)
100 ' PHASE UNWRAPPING
110 '
120 DIM PHASE[256] 'PHASE[ ] holds the original phase
130 DIM UWPHASE[256] 'UWPHASE[ ] holds the unwrapped phase
140 '
150 PI = 3.14159265
160 '
170 GOSUB XXXX 'Mythical subroutine to load data into PHASE[ ]
180 '
190 UWPHASE[0] = 0 'The first point of all phase signals is zero
200 '
210 ' 'Go through the unwrapping algorithm
220 FOR K% = 1 TO 256
230 C% = CINT( (UWPHASE[K%-1] - PHASE[K%]) / (2 * PI) )
240 UWPHASE[K%] = PHASE[K%] + C%*2*PI
250 NEXT K%
260 '
270 END
TABLE 8-4
example, a phase shift of q is exactly the same as a phase shift of q + 2p , q + 4p ,
q + 6p , etc. Any sinusoid is unchanged when you add an integer multiple of
2B to the phase. The apparent discontinuities in the signal are a result of the
computer algorithm picking its favorite choice from an infinite number of
equivalent possibilities. The smallest possible value is always chosen, keeping
the phase between -B and B.
It is often easier to understand the phase if it does not have these
discontinuities, even if it means that the phase extends above B, or below -B.
This is called unwrapping the phase, and an example is shown in Fig. 8-12.
As shown by the program in Table 8-4, a multiple of 2B is added or subtracted
from each value of the phase. The exact value is determined by an algorithm
that minimizes the difference between adjacent samples.
Nuisance 6: The magnitude is always positive (B ambiguity of the phase)
Figure 8-13 shows a frequency domain signal in rectangular and polar form.
The real part is smooth and quite easy to understand, while the imaginary
part is entirely zero. In comparison, the polar signals contain abrupt
168 The Scientist and Engineer's Guide to Digital Signal Processing
Frequency
0 0.1 0.2 0.3 0.4 0.5
-1
0
1
2
3
a. Re X[ ]
Frequency
0 0.1 0.2 0.3 0.4 0.5
-1
0
1
2
3
c. Mag X[ ]
Frequency
0 0.1 0.2 0.3 0.4 0.5
-5
-4
-3
-2
-1
0
1
2
3
4
5
d. Phase X[ ]
Rectangular Polar
FIGURE 8-13
Example signals in rectangular and polar form. Since the magnitude must always be positive (by definition),
the magnitude and phase may contain abrupt discontinuities and sharp corners. Figure (d) also shows
another nuisance: random noise can cause the phase to rapidly oscillate between B or -B.
Frequency
0 0.1 0.2 0.3 0.4 0.5
-3
-2
-1
0
1
2
3
b. Im X[ ]
Amplitude
Amplitude Amplitude
Phase (radians)
discontinuities and sharp corners. This is because the magnitude must always
be positive, by definition. Whenever the real part dips below zero, the
magnitude remains positive by changing the phase by B (or -B, which is the
same thing). While this is not a problem for the mathematics, the irregular
curves can be difficult to interpret.
One solution is to allow the magnitude to have negative values. In the example
of Fig. 8-13, this would make the magnitude appear the same as the real part,
while the phase would be entirely zero. There is nothing wrong with this if it
helps your understanding. Just be careful not to call a signal with negative
values the "magnitude" since this violates its formal definition. In this book we
use the weasel words: unwrapped magnitude to indicate a "magnitude" that is
allowed to have negative values.
Nuisance 7: Spikes between B and -B
Since B and -B represent the same phase shift, round-off noise can cause
adjacent points in the phase to rapidly switch between the two values. As
shown in Fig. 8-13d, this can produce sharp breaks and spikes in an otherwise
smooth curve. Don't be fooled, the phase isn't really this discontinuous.
Low Power, 12.65 mW, 2.3 V to 5.5 V,
Programmable Waveform Generator
Data Sheet AD9833
Rev. E Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2012 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
Digitally programmable frequency and phase
12.65 mW power consumption at 3 V
0 MHz to 12.5 MHz output frequency range
28-bit resolution: 0.1 Hz at 25 MHz reference clock
Sinusoidal, triangular, and square wave outputs
2.3 V to 5.5 V power supply
No external components required
3-wire SPI interface
Extended temperature range: −40°C to +105°C
Power-down option
10-lead MSOP package
Qualified for automotive applications
APPLICATIONS
Frequency stimulus/waveform generation
Liquid and gas flow measurement
Sensory applications: proximity, motion, and defect detection
Line loss/attenuation
Test and medical equipment
Sweep/clock generators
Time domain reflectometry (TDR) applications
GENERAL DESCRIPTION
The AD9833 is a low power, programmable waveform generator capable of producing sine, triangular, and square wave outputs. Waveform generation is required in various types of sensing, actuation, and time domain reflectometry (TDR) applications. The output frequency and phase are software programmable, allowing easy tuning. No external components are needed. The frequency registers are 28 bits wide: with a 25 MHz clock rate, resolution of 0.1 Hz can be achieved; with a 1 MHz clock rate, the AD9833 can be tuned to 0.004 Hz resolution.
The AD9833 is written to via a 3-wire serial interface. This serial interface operates at clock rates up to 40 MHz and is compatible with DSP and microcontroller standards. The device operates with a power supply from 2.3 V to 5.5 V.
The AD9833 has a power-down function (SLEEP). This function allows sections of the device that are not being used to be powered down, thus minimizing the current consumption of the part. For example, the DAC can be powered down when a clock output is being generated.
The AD9833 is available in a 10-lead MSOP package.
FUNCTIONAL BLOCK DIAGRAM
SERIAL INTERFACEANDCONTROL LOGICSCLKSDATAFSYNCCONTROL REGISTERPHASE1 REGPHASE0 REGMUXSINROM10-BITDACMUXFREQ0 REGFREQ1 REG12ON-BOARDREFERENCEAGNDDGNDVDDAD9833PHASEACCUMULATOR(28-BIT)REGULATORCAP/2.5V2.5VAVDD/DVDDMUXDIVIDEBY 2MSBMUXFULL-SCALECONTROLCOMPVOUTR200ΩMCLK02704-001
Figure 1.
AD9833 Data Sheet
Rev. E | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Terminology .................................................................................... 10
Theory of Operation ...................................................................... 11
Circuit Description ......................................................................... 12
Numerically Controlled Oscillator Plus Phase Modulator ... 12
Sin ROM ...................................................................................... 12
Digital-to-Analog Converter (DAC) ....................................... 12
Regulator...................................................................................... 12
Functional Description .................................................................. 13
Serial Interface ............................................................................ 13
Powering Up the AD9833 ......................................................... 13
Latency Period ............................................................................ 13
Control Register ......................................................................... 13
Frequency and Phase Registers ................................................ 15
Reset Function ............................................................................ 16
Sleep Function ............................................................................ 16
VOUT Pin ................................................................................... 16
Applications Information .............................................................. 17
Grounding and Layout .............................................................. 17
Interfacing to Microprocessors ..................................................... 20
AD9833 to 68HC11/68L11 Interface ....................................... 20
AD9833 to 80C51/80L51 Interface .......................................... 20
AD9833 to DSP56002 Interface ............................................... 20
Evaluation Board ............................................................................ 21
System Demonstration Platform .............................................. 21
AD9833 to SPORT Interface ..................................................... 21
Evaluation Kit ............................................................................. 21
Crystal Oscillator vs. External Clock ....................................... 21
Power Supply ............................................................................... 21
Evaluation Board Schematics ................................................... 22
Evaluation Board Layout ........................................................... 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
Automotive Products ................................................................. 24
REVISION HISTORY
9/12—Rev. D to Rev. E
Changed Input Current, IINH/IINL from 10 mA to 10 μA.............. 3
4/11—Rev. C to Rev. D
Change to Figure 13 ......................................................................... 8
Changes to Table 9 .......................................................................... 15
Deleted AD9833 to ADSP-2101/ADSP-2103 Interface Section .............................................................................................. 20
Changes to Evaluation Board Section .......................................... 21
Added System Demonstration Platform Section, AD9833 to SPORT Interface Section, and Evaluation Kit Section .......... 21
Changes to Crystal Oscillator vs. External Clock Section and Power Supply Section ............................................................. 21
Added Figure 32 and Figure 33; Renumbered Figures Sequentially ..................................................................................... 21
Deleted Prototyping Area Section and Figure 33 ....................... 22
Added Evaluation Board Schematics Section, Figure 34, and Figure 35 ................................................................................... 22
Deleted Table 16 .............................................................................. 23
Added Evaluation Board Layout Section, Figure 36, Figure 37, and Figure 38 ................................................................ 23
Changes to Ordering Guide .......................................................... 24
9/10—Rev. B to Rev. C
Changed 20 mW to 12.65 mW in Data Sheet Title and Features List ................................................................................ 1
Changes to Figure 6 Caption and Figure 7..................................... 7
6/10—Rev. A to Rev. B
Changes to Features Section ............................................................ 1
Changes to Serial Interface Section.............................................. 13
Changes to VOUT Pin Section ..................................................... 16
Changes to Grounding and Layout Section ................................ 17
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
Added Automotive Products Section .......................................... 24
6/03—Rev. 0 to Rev. A
Updated Ordering Guide ................................................................. 4
Data Sheet AD9833
Rev. E | Page 3 of 24
SPECIFICATIONS
VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, RSET = 6.8 kΩ for VOUT, unless otherwise noted.
Table 1.
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
SIGNAL DAC SPECIFICATIONS
Resolution
10
Bits
Update Rate
25
MSPS
VOUT Maximum
0.65
V
VOUT Minimum
38
mV
VOUT Temperature Coefficient
200
ppm/°C
DC Accuracy
Integral Nonlinearity
±1.0
LSB
Differential Nonlinearity
±0.5
LSB
DDS SPECIFICATIONS (SFDR)
Dynamic Specifications
Signal-to-Noise Ratio (SNR)
55
60
dB
fMCLK = 25 MHz, fOUT = fMCLK/4096
Total Harmonic Distortion (THD)
−66
−56
dBc
fMCLK = 25 MHz, fOUT = fMCLK/4096
Spurious-Free Dynamic Range (SFDR)
Wideband (0 to Nyquist)
−60
dBc
fMCLK = 25 MHz, fOUT = fMCLK/50
Narrow-Band (±200 kHz)
−78
dBc
fMCLK = 25 MHz, fOUT = fMCLK/50
Clock Feedthrough
−60
dBc
Wake-Up Time
1
ms
LOGIC INPUTS
Input High Voltage, VINH
1.7
V
2.3 V to 2.7 V power supply
2.0
V
2.7 V to 3.6 V power supply
2.8
V
4.5 V to 5.5 V power supply
Input Low Voltage, VINL
0.5
V
2.3 V to 2.7 V power supply
0.7
V
2.7 V to 3.6 V power supply
0.8
V
4.5 V to 5.5 V power supply
Input Current, IINH/IINL
10
μA
Input Capacitance, CIN
3
pF
POWER SUPPLIES
fMCLK = 25 MHz, fOUT = fMCLK/4096
VDD
2.3
5.5
V
IDD
4.5
5.5
mA
IDD code dependent; see Figure 7
Low Power Sleep Mode
0.5
mA
DAC powered down, MCLK running
1 Operating temperature range is −40°C to +105°C; typical specifications are at 25°C.
VOUTCOMP12AD983310-BIT DACSINROM20pF10nFVDDREGULATOR100nFCAP/2.5V02704-002
Figure 2. Test Circuit Used to Test Specifications
AD9833 Data Sheet
Rev. E | Page 4 of 24
TIMING CHARACTERISTICS
VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.1
Table 2.
Parameter
Limit at TMIN to TMAX
Unit
Description
t1
40
ns min
MCLK period
t2
16
ns min
MCLK high duration
t3
16
ns min
MCLK low duration
t4
25
ns min
SCLK period
t5
10
ns min
SCLK high duration
t6
10
ns min
SCLK low duration
t7
5
ns min
FSYNC to SCLK falling edge setup time
t8 min
10
ns min
FSYNC to SCLK hold time
t8 max
t4 − 5
ns max
t9
5
ns min
Data setup time
t10
3
ns min
Data hold time
t11
5
ns min
SCLK high to FSYNC falling edge setup time
1 Guaranteed by design, not production tested.
Timing Diagrams
t2t1MCLKt302704-003
Figure 3. Master Clock
t5t4t6t7t8t10t941D51DD0D1D2D14SCLKFSYNCSDATAD15t1102704-004
Figure 4. Serial Timing
Data Sheet AD9833
Rev. E | Page 5 of 24
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
Rating
VDD to AGND
−0.3 V to +6 V
VDD to DGND
−0.3 V to +6 V
AGND to DGND
−0.3 V to +0.3 V
CAP/2.5V
2.75 V
Digital I/O Voltage to DGND
−0.3 V to VDD + 0.3 V
Analog I/O Voltage to AGND
−0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version)
−40°C to +105°C
Storage Temperature Range
−65°C to +150°C
Maximum Junction Temperature
150°C
MSOP Package
θJA Thermal Impedance
206°C/W
θJC Thermal Impedance
44°C/W
Lead Temperature, Soldering (10 sec)
300°C
IR Reflow, Peak Temperature
220°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
AD9833 Data Sheet
Rev. E | Page 6 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
COMP1VDD2CAP/2.5V3DGND4MCLK5VOUT10AGND9FSYNC8SCLK7SDATA6AD9833TOP VIEW(Not to Scale)02704-005
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
COMP
DAC Bias Pin. This pin is used for decoupling the DAC bias voltage.
2
VDD
Positive Power Supply for the Analog and Digital Interface Sections. The on-board 2.5 V regulator is also supplied from VDD. VDD can have a value from 2.3 V to 5.5 V. A 0.1 μF and a 10 μF decoupling capacitor should be connected between VDD and AGND.
3
CAP/2.5V
The digital circuitry operates from a 2.5 V power supply. This 2.5 V is generated from VDD using an on-board regulator when VDD exceeds 2.7 V. The regulator requires a decoupling capacitor of 100 nF typical, which is connected from CAP/2.5V to DGND. If VDD is less than or equal to 2.7 V, CAP/2.5V should be tied directly to VDD.
4
DGND
Digital Ground.
5
MCLK
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The output frequency accuracy and phase noise are determined by this clock.
6
SDATA
Serial Data Input. The 16-bit serial data-word is applied to this input.
7
SCLK
Serial Clock Input. Data is clocked into the AD9833 on each falling edge of SCLK.
8
FSYNC
Active Low Control Input. FSYNC is the frame synchronization signal for the input data. When FSYNC is taken low, the internal logic is informed that a new word is being loaded into the device.
9
AGND
Analog Ground.
10
VOUT
Voltage Output. The analog and digital output from the AD9833 is available at this pin. An external load resistor is not required because the device has a 200 Ω resistor on board.
Data Sheet AD9833
Rev. E | Page 7 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
MCLK FREQUENCY (MHz)IDD (mA)5.55.03.03.54.04.50510152025TA = 25°C02704-006VDD = 5VVDD = 3V
Figure 6. Typical Current Consumption (IDD) vs. MCLK Frequency for fOUT = MCLK/10
01234561001k10k100k1M10MIDD (
mA)fOUT (Hz)VDD = 5VVDD = 3V02704-007
Figure 7. Typical IDD vs. fOUT for fMCLK = 25 MHz
0510152025MCLK FREQUENCY (MHz)SFDR (dBc)–65–60–90–70–75–80–85MCLK/7MCLK/50VDD = 3VTA= 25°C02704-008
Figure 8. Narrow-Band SFDR vs. MCLK Frequency
–45–40–705791113151719212325–50–55–60–65MCLK FREQUENCY (MHz)SFDR (dBc)MCLK/7MCLK/50VDD = 3VTA= 25°C02704-009
Figure 9. Wideband SFDR vs. MCLK Frequency
fOUT/fMCLK–30–90–80–70–60–50–40SFDR (
dB)0–20–10fMCLK =1MHzfMCLK =10MHz0.0010.010.1110100fMCLK =25MHzVDD = 3VTA= 25°C02704-010fMCLK =18MHz
Figure 10. Wideband SFDR vs. fOUT/fMCLK for Various MCLK Frequencies
MCLK FREQUENCY (MHz)1.05.010.012.525.0SNR (
dB)–60–65–70–50–55–40–45VDD = 3VTA= 25°CfOUT= MCLK/409602704-011
Figure 11. SNR vs. MCLK Frequency
AD9833 Data Sheet
Rev. E | Page 8 of 24
5001000700650600550850750800900950–4025105TEMPERATURE (°C)WAKE-UP TIME (μs)VDD = 5.5V02704-012VDD = 2.3V
Figure 12. Wake-Up Time vs. Temperature
–4025105TEMPERATURE (°C)VREF (V)LOWER RANGEUPPER RANGE1.1501.1251.1001.1751.2001.2501.22502704-013
Figure 13. VREF vs. Temperature
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–100100kRWB 100ST 100 SECVWB 3002704-014
Figure 14. Power vs. Frequency, fMCLK = 10 MHz, fOUT = 2.4 kHz, Frequency Word = 0x000FBA9
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–1005MRWB 1kST 50 SECVWB 30002704-015
Figure 15. Power vs. Frequency, fMCLK = 10 MHz, fOUT = 1.43 MHz = fMCLK/7, Frequency Word = 0x2492492
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–1005MRWB 1kST 50 SECVWB 30002704-016
Figure 16. Power vs. Frequency, fMCLK = 10 MHz, fOUT = 3.33 MHz = fMCLK/3, Frequency Word = 0x5555555
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–100100kRWB 100ST 100 SECVWB 3002704-017
Figure 17. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 6 kHz, Frequency Word = 0x000FBA9
Data Sheet AD9833
Rev. E | Page 9 of 24
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–1001MRWB 300ST 100 SECVWB 10002704-018
Figure 18. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 60 kHz, Frequency Word = 0x009D495
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–10012.5MRWB 1kST 100 SECVWB 30002704-019
Figure 19. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 600 kHz, Frequency Word = 0x0624DD3
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–10012.5MRWB 1kST 100 SECVWB 30002704-020
Figure 20. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 2.4 MHz, Frequency Word = 0x189374D
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–10012.5MRWB 1kST 100 SECVWB 30002704-021
Figure 21. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 3.857 MHz = fMCLK/7, Frequency Word = 0x2492492
FREQUENCY (Hz)POWER (dB)0–20–50–90–100–80–70–60–40–30–10012.5MRWB 1kST 100 SECVWB 30002704-022
Figure 22. Power vs. Frequency, fMCLK = 25 MHz, fOUT = 8.333 MHz = fMCLK/3, Frequency Word = 0x5555555
AD9833 Data Sheet
Rev. E | Page 10 of 24
TERMINOLOGY
Integral Nonlinearity (INL)
INL is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The end-points of the transfer function are zero scale, a point 0.5 LSB below the first code transition (000 … 00 to 000 … 01), and full scale, a point 0.5 LSB above the last code transition (111 … 10 to 111 … 11). The error is expressed in LSBs.
Differential Nonlinearity (DNL)
DNL is the difference between the measured and ideal 1 LSB change between two adjacent codes in the DAC. A specified DNL of ±1 LSB maximum ensures monotonicity.
Output Compliance
Output compliance refers to the maximum voltage that can be generated at the output of the DAC to meet the specifications. When voltages greater than that specified for the output compli-ance are generated, the AD9833 may not meet the specifications listed in the data sheet.
Spurious-Free Dynamic Range (SFDR)
Along with the frequency of interest, harmonics of the funda-mental frequency and images of these frequencies are present at the output of a DDS device. SFDR refers to the largest spur or harmonic present in the band of interest. The wideband SFDR gives the magnitude of the largest spur or harmonic relative to the magnitude of the fundamental frequency in the zero to Nyquist bandwidth. The narrow-band SFDR gives the attenuation of the largest spur or harmonic in a bandwidth of ±200 kHz about the fundamental frequency.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the rms value of the fundamental. For the AD9833, THD is defined as
12625242322log20THDVVVVVV++++=
where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through sixth harmonics.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency. The value for SNR is expressed in decibels.
Clock Feedthrough
There is feedthrough from the MCLK input to the analog output. Clock feedthrough refers to the magnitude of the MCLK signal relative to the fundamental frequency in the output spectrum of the AD9833.
Data Sheet AD9833
Rev. E | Page 11 of 24 THEORY OF OPERATION
Sine waves are typically thought of in terms of their magnitude form: a(t) = sin(ωt). However, these sine waves are nonlinear and not easy to generate except through piecewise construction. On the other hand, the angular information is linear in nature. That
is, the phase angle rotates through a fixed angle for each unit of
time. The angular rate depends on the frequency of the signal
by the traditional rate of ω = 2πf.
MAGNITUDE
PHASE
+1
0
–1
2p
0
2π 4π
6π
2π 4π 6π
02704-023
Figure 23. Sine Wave
Knowing that the phase of a sine wave is linear and given a
reference interval (clock period), the phase rotation for that period can be determined.
ΔPhase = ωΔt
Solving for ω, ω = ΔPhase/Δt = 2πf
Solving for f and substituting the reference clock frequency for the reference period (1/fMCLK = Δt)
f = ΔPhase × fMCLK∕2π
The AD9833 builds the output based on this simple equation. A
simple DDS chip can implement this equation with three major
subcircuits: numerically controlled oscillator (NCO) and phase
modulator, SIN ROM, and digital-to-analog converter (DAC). Each subcircuit is described in the Circuit Description section.
AD9833 Data Sheet
Rev. E | Page 12 of 24
CIRCUIT DESCRIPTION
The AD9833 is a fully integrated direct digital synthesis (DDS) chip. The chip requires one reference clock, one low precision resistor, and decoupling capacitors to provide digitally created sine waves up to 12.5 MHz. In addition to the generation of this RF signal, the chip is fully capable of a broad range of simple and complex modulation schemes. These modulation schemes are fully implemented in the digital domain, allowing accurate and simple realization of complex modulation algorithms using DSP techniques.
The internal circuitry of the AD9833 consists of the following main sections: a numerically controlled oscillator (NCO), frequency and phase modulators, SIN ROM, a DAC, and a regulator.
NUMERICALLY CONTROLLED OSCILLATOR PLUS PHASE MODULATOR
This consists of two frequency select registers, a phase accumulator, two phase offset registers, and a phase offset adder. The main component of the NCO is a 28-bit phase accumulator. Continuous time signals have a phase range of 0 to 2π. Outside this range of numbers, the sinusoid functions repeat themselves in a periodic manner. The digital implementation is no different. The accumulator simply scales the range of phase numbers into a multibit digital word. The phase accumulator in the AD9833 is implemented with 28 bits. Therefore, in the AD9833, 2π = 228. Likewise, the ΔPhase term is scaled into this range of numbers:
0 < ΔPhase < 228 − 1
With these substitutions, the previous equation becomes
f = ΔPhase × fMCLK∕228
where 0 < ΔPhase < 228 − 1.
The input to the phase accumulator can be selected from either the FREQ0 register or the FREQ1 register and is controlled by the FSELECT bit. NCOs inherently generate continuous phase signals, thus avoiding any output discontinuity when switching between frequencies.
Following the NCO, a phase offset can be added to perform phase modulation using the 12-bit phase registers. The contents of one of these phase registers are added to the most significant bits of the NCO. The AD9833 has two phase registers; their resolution is 2π/4096.
SIN ROM
To make the output from the NCO useful, it must be converted from phase information into a sinusoidal value. Because phase information maps directly into amplitude, the SIN ROM uses the digital phase information as an address to a lookup table and converts the phase information into amplitude. Although the NCO contains a 28-bit phase accumulator, the output of the NCO is truncated to 12 bits. Using the full resolution of the phase accumulator is impractical and unnecessary, because this would require a lookup table of 228 entries. It is necessary only to have sufficient phase resolution such that the errors due to truncation are smaller than the resolution of the 10-bit DAC. This requires that the SIN ROM have two bits of phase resolution more than the 10-bit DAC.
The SIN ROM is enabled using the mode bit (D1) in the control register (see Table 15).
DIGITAL-TO-ANALOG CONVERTER (DAC)
The AD9833 includes a high impedance, current source 10-bit DAC. The DAC receives the digital words from the SIN ROM and converts them into the corresponding analog voltages.
The DAC is configured for single-ended operation. An external load resistor is not required because the device has a 200 Ω resistor on board. The DAC generates an output voltage of typically 0.6 V p-p.
REGULATOR
VDD provides the power supply required for the analog section and the digital section of the AD9833. This supply can have a value of 2.3 V to 5.5 V.
The internal digital section of the AD9833 is operated at 2.5 V. An on-board regulator steps down the voltage applied at VDD to 2.5 V. When the applied voltage at the VDD pin of the AD9833 is less than or equal to 2.7 V, the CAP/2.5V and VDD pins should be tied together, thus bypassing the on-board regulator.
Data Sheet AD9833
Rev. E | Page 13 of 24
FUNCTIONAL DESCRIPTION
SERIAL INTERFACE
The AD9833 has a standard 3-wire serial interface that is compatible with the SPI, QSPI™, MICROWIRE®, and DSP interface standards.
Data is loaded into the device as a 16-bit word under the control of a serial clock input, SCLK. The timing diagram for this operation is given in .
The FSYNC input is a level-triggered input that acts as a frame synchronization and chip enable. Data can be transferred into the device only when FSYNC is low. To start the serial data transfer, FSYNC should be taken low, observing the minimum FSYNC-to-SCLK falling edge setup time, t7. After FSYNC goes low, serial data is shifted into the input shift register of the device on the falling edges of SCLK for 16 clock pulses. FSYNC may be taken high after the 16th falling edge of SCLK, observing the minimum SCLK falling edge to FSYNC rising edge time, t8. Alternatively, FSYNC can be kept low for a multiple of 16 SCLK pulses and then brought high at the end of the data transfer. In this way, a continuous stream of 16-bit words can be loaded while FSYNC is held low; FSYNC goes high only after the 16th SCLK falling edge of the last word loaded.
The SCLK can be continuous, or it can idle high or low between write operations. In either case, it must be high when FSYNC goes low (t11).
For an example of how to program the AD9833, see the AN-1070 Application Note on the Analog Devices, Inc., website.
POWERING UP THE AD9833
The flowchart in Figure 26 shows the operating routine for the AD9833. When the AD9833 is powered up, the part should be reset. This resets the appropriate internal registers to 0 to provide an analog output of midscale.
To avoid spurious DAC outputs during AD9833 initialization, the reset bit should be set to 1 until the part is ready to begin generating an output. A reset does not reset the phase, frequency, or control registers. These registers will contain invalid data and, therefore, should be set to known values by the user. The reset bit should then be set to 0 to begin generating an output. The data appears on the DAC output seven or eight MCLK cycles after the reset bit is set to 0.
LATENCY PERIOD
A latency period is associated with each asynchronous write operation in the AD9833. If a selected frequency or phase register is loaded with a new word, there is a delay of seven or eight MCLK cycles before the analog output changes. The delay can be seven or eight cycles, depending on the position of the MCLK rising edge when the data is loaded into the destination register.
CONTROL REGISTER
The AD9833 contains a 16-bit control register that allows the user to configure the operation of the AD9833. All control bits other than the mode bit are sampled on the internal falling edge of MCLK.
Table 6 describes the individual bits of the control register. The different functions and the various output options of the AD9833 are described in more detail in the Frequency and Phase Registers section.
To inform the AD9833 that the contents of the control register will be altered, D15 and D14 must be set to 0, as shown in Table 5.
Table 5. Control Register Bits
D15
D14
D13
D0
0
0
Control Bits
SINROMPHASEACCUMULATOR(28-BIT)AD9833(LOW POWER)10-BIT DAC0MUX1SLEEP12SLEEP1RESETMODE + OPBITENDIV2OPBITENVOUT1MUX0DIGITALOUTPUT(ENABLE)DIVIDEBY 2DB150DB140DB13B28DB12HLBDB11FSELECTDB10PSELECTDB90DB8RESETDB7SLEEP1DB6SLEEP12DB5OPBITENDB40DB3DIV2DB20DB1MODEDB0002704-024
Figure 24. Function of Control Bits
AD9833 Data Sheet
Rev. E | Page 14 of 24
Table 6. Description of Bits in the Control Register
Bit
Name
Function
D13
B28
Two write operations are required to load a complete word into either of the frequency registers. B28 = 1 allows a complete word to be loaded into a frequency register in two consecutive writes. The first write contains the 14 LSBs of the frequency word, and the next write contains the 14 MSBs. The first two bits of each 16-bit word define the frequency register to which the word is loaded and should, therefore, be the same for both of the consecutive writes. See Table 8 for the appropriate addresses. The write to the frequency register occurs after both words have been loaded; therefore, the register never holds an intermediate value. An example of a complete 28-bit write is shown in Table 9. When B28 = 0, the 28-bit frequency register operates as two 14-bit registers, one containing the 14 MSBs and the other containing the 14 LSBs. This means that the 14 MSBs of the frequency word can be altered independent of the 14 LSBs, and vice versa. To alter the 14 MSBs or the 14 LSBs, a single write is made to the appropriate frequency address. The control bit D12 (HLB) informs the AD9833 whether the bits to be altered are the 14 MSBs or 14 LSBs.
D12
HLB
This control bit allows the user to continuously load the MSBs or LSBs of a frequency register while ignoring the remaining 14 bits. This is useful if the complete 28-bit resolution is not required. HLB is used in conjunction with D13 (B28). This control bit indicates whether the 14 bits being loaded are being transferred to the 14 MSBs or 14 LSBs of the addressed frequency register. D13 (B28) must be set to 0 to be able to change the MSBs and LSBs of a frequency word separately. When D13 (B28) = 1, this control bit is ignored. HLB = 1 allows a write to the 14 MSBs of the addressed frequency register. HLB = 0 allows a write to the 14 LSBs of the addressed frequency register.
D11
FSELECT
The FSELECT bit defines whether the FREQ0 register or the FREQ1 register is used in the phase accumulator.
D10
PSELECT
The PSELECT bit defines whether the PHASE0 register or the PHASE1 register data is added to the output of the phase accumulator.
D9
Reserved
This bit should be set to 0.
D8
Reset
Reset = 1 resets internal registers to 0, which corresponds to an analog output of midscale. Reset = 0 disables reset. This function is explained further in Table 13.
D7
SLEEP1
When SLEEP1 = 1, the internal MCLK clock is disabled, and the DAC output remains at its present value because the NCO is no longer accumulating. When SLEEP1 = 0, MCLK is enabled. This function is explained further in Table 14.
D6
SLEEP12
SLEEP12 = 1 powers down the on-chip DAC. This is useful when the AD9833 is used to output the MSB of the DAC data.
SLEEP12 = 0 implies that the DAC is active. This function is explained further in Table 14.
D5
OPBITEN
The function of this bit, in association with D1 (mode), is to control what is output at the VOUT pin. This is explained further in Table 15. When OPBITEN = 1, the output of the DAC is no longer available at the VOUT pin. Instead, the MSB (or MSB/2) of the DAC data is connected to the VOUT pin. This is useful as a coarse clock source. The DIV2 bit controls whether it is the MSB or MSB/2 that is output. When OPBITEN = 0, the DAC is connected to VOUT. The mode bit determines whether it is a sinusoidal or a ramp output that is available.
D4
Reserved
This bit must be set to 0.
D3
DIV2
DIV2 is used in association with D5 (OPBITEN). This is explained further in Table 15. When DIV2 = 1, the MSB of the DAC data is passed directly to the VOUT pin. When DIV2 = 0, the MSB/2 of the DAC data is output at the VOUT pin.
D2
Reserved
This bit must be set to 0.
D1
Mode
This bit is used in association with OPBITEN (D5). The function of this bit is to control what is output at the VOUT pin when the on-chip DAC is connected to VOUT. This bit should be set to 0 if the control bit OPBITEN = 1. This is explained further in Table 15. When mode = 1, the SIN ROM is bypassed, resulting in a triangle output from the DAC. When mode = 0, the SIN ROM is used to convert the phase information into amplitude information, which results in a sinusoidal signal at the output.
D0
Reserved
This bit must be set to 0.
Data Sheet AD9833
Rev. E | Page 15 of 24 FREQUENCY AND PHASE REGISTERS
The AD9833 contains two frequency registers and two phase
registers, which are described in Table 7. Table 7. Frequency and Phase Registers
Register Size Description FREQ0 28 bits Frequency Register 0. When the FSELECT
bit = 0, this register defines the output
frequency as a fraction of the MCLK
frequency.
FREQ1 28 bits Frequency Register 1. When the FSELECT
bit = 1, this register defines the output
frequency as a fraction of the MCLK
frequency.
PHASE0 12 bits Phase Offset Register 0. When the PSELECT
bit = 0, the contents of this register are
added to the output of the phase
accumulator. PHASE1 12 bits Phase Offset Register 1. When the PSELECT
bit = 1, the contents of this register are
added to the output of the phase
accumulator. The analog output from the AD9833 is
fMCLK/228 × FREQREG
where FREQREG is the value loaded into the selected frequency
register. This signal is phase shifted by 2π/4096 × PHASEREG where PHASEREG is the value contained in the selected phase register. Consideration must be given to the relationship of the
selected output frequency and the reference clock frequency to avoid unwanted output anomalies. The flowchart in Figure 28 shows the routine for writing to the
frequency and phase registers of the AD9833. Writing to a Frequency Register
When writing to a frequency register, Bit D15 and Bit D14 give
the address of the frequency register.
Table 8. Frequency Register Bits
D15 D14 D13 D0
0 1 MSB 14 FREQ0 REG bits LSB
1 0 MSB 14 FREQ1 REG bits LSB
If the user wants to change the entire contents of a frequency
register, two consecutive writes to the same address must be
performed because the frequency registers are 28 bits wide. The
first write contains the 14 LSBs, and the second write contains the 14 MSBs. For this mode of operation, the B28 (D13) control
bit should be set to 1. An example of a 28-bit write is shown in Table 9. Table 9. Writing 0xFFFC000 to the FREQ0 Register SDATA Input Result of Input Word 0010 0000 0000 0000 Control word write (D15, D14 = 00), B28 (D13) = 1, HLB (D12) = X 0100 0000 0000 0000 FREQ0 register write
(D15, D14 = 01), 14 LSBs = 0x0000
0111 1111 1111 1111 FREQ0 register write
(D15, D14 = 01), 14 MSBs = 0x3FFF
In some applications, the user does not need to alter all 28 bits
of the frequency register. With coarse tuning, only the 14 MSBs
are altered, while with fine tuning, only the 14 LSBs are altered.
By setting the B28 (D13) control bit to 0, the 28-bit frequency
register operates as two, 14-bit registers, one containing the 14 MSBs
and the other containing the 14 LSBs. This means that the 14 MSBs of the frequency word can be altered independent of the 14 LSBs,
and vice versa. Bit HLB (D12) in the control register identifies
which 14 bits are being altered. Examples of this are shown in
Table 10 and Table 11. Table 10. Writing 0x3FFF to the 14 LSBs of the FREQ1 Register SDATA Input Result of Input Word 0000 0000 0000 0000 Control word write (D15, D14 = 00), B28 (D13) = 0; HLB (D12) = 0, that is, LSBs
1011 1111 1111 1111 FREQ1 REG write (D15, D14 = 10), 14 LSBs = 0x3FFF
Table 11. Writing 0x00FF to the 14 MSBs of the FREQ0 Register SDATA Input Result of Input Word 0001 0000 0000 0000 Control word write (D15, D14 = 00),
B28 (D13) = 0, HLB (D12) = 1, that is, MSBs 0100 0000 1111 1111 FREQ0 REG write (D15, D14 = 01), 14 MSBs = 0x00FF
Writing to a Phase Register
When writing to a phase register, Bit D15 and Bit D14 are set to 11.
Bit D13 identifies which phase register is being loaded. Table 12. Phase Register Bits
D15 D14 D13 D12 D11 D0
1 1 0 X MSB 12 PHASE0 bits LSB
1 1 1 X MSB 12 PHASE1 bits LSB
AD9833 Data Sheet
Rev. E | Page 16 of 24
RESET FUNCTION
The reset function resets appropriate internal registers to 0 to provide an analog output of midscale. Reset does not reset the phase, frequency, or control registers. When the AD9833 is powered up, the part should be reset. To reset the AD9833, set the reset bit to 1. To take the part out of reset, set the bit to 0. A signal appears at the DAC to output eight MCLK cycles after reset is set to 0.
Table 13. Applying the Reset Function
Reset Bit
Result
0
No reset applied
1
Internal registers reset
SLEEP FUNCTION
Sections of the AD9833 that are not in use can be powered down to minimize power consumption. This is done using the sleep function. The parts of the chip that can be powered down are the internal clock and the DAC. The bits required for the sleep function are outlined in Table 14.
Table 14. Applying the Sleep Function
SLEEP1 Bit
SLEEP12 Bit
Result
0
0
No power-down
0
1
DAC powered down
1
0
Internal clock disabled
1
1
Both the DAC powered down and the internal clock disabled
DAC Powered Down
This is useful when the AD9833 is used to output the MSB of the DAC data only. In this case, the DAC is not required; therefore, it can be powered down to reduce power consumption.
Internal Clock Disabled
When the internal clock of the AD9833 is disabled, the DAC output remains at its present value because the NCO is no longer accumulating. New frequency, phase, and control words can be written to the part when the SLEEP1 control bit is active. The synchronizing clock is still active, which means that the selected frequency and phase registers can also be changed using the control bits. Setting the SLEEP1 bit to 0 enables the MCLK. Any changes made to the registers while SLEEP1 is active will be seen at the output after a latency period.
VOUT PIN
The AD9833 offers a variety of outputs from the chip, all of which are available from the VOUT pin. The choice of outputs is the MSB of the DAC data, a sinusoidal output, or a triangle output.
The OPBITEN (D5) and mode (D1) bits in the control register are used to decide which output is available from the AD9833.
MSB of the DAC Data
The MSB of the DAC data can be output from the AD9833. By setting the OPBITEN (D5) control bit to 1, the MSB of the DAC data is available at the VOUT pin. This is useful as a coarse clock source. This square wave can also be divided by 2 before being output. The DIV2 (D3) bit in the control register controls the frequency of this output from the VOUT pin.
Sinusoidal Output
The SIN ROM is used to convert the phase information from the frequency and phase registers into amplitude information that results in a sinusoidal signal at the output. To have a sinusoidal output from the VOUT pin, set the mode (D1) bit to 0 and the OPBITEN (D5) bit to 0.
Triangle Output
The SIN ROM can be bypassed so that the truncated digital output from the NCO is sent to the DAC. In this case, the output is no longer sinusoidal. The DAC will produce a 10-bit linear triangular function. To have a triangle output from the VOUT pin, set the mode (D1) bit = 1.
Note that the SLEEP12 bit must be 0 (that is, the DAC is enabled) when using this pin.
Table 15. Outputs from the VOUT Pin
OPBITEN Bit
Mode Bit
DIV2 Bit
VOUT Pin
0
0
X1
Sinusoid
0
1
X1
Triangle
1
0
0
DAC data MSB/2
1
0
1
DAC data MSB
1
1
X1
Reserved
1 X = don’t care.
VOUT MINVOUT MAX2π4π6π02704-025
Figure 25. Triangle Output
Data Sheet AD9833
Rev. E | Page 17 of 24
APPLICATIONS INFORMATION
Because of the various output options available from the part, the AD9833 can be configured to suit a wide variety of applications.
One of the areas where the AD9833 is suitable is in modulation applications. The part can be used to perform simple modulation, such as FSK. More complex modulation schemes, such as GMSK and QPSK, can also be implemented using the AD9833.
In an FSK application, the two frequency registers of the AD9833 are loaded with different values. One frequency represents the space frequency, while the other represents the mark frequency. Using the FSELECT bit in the control register of the AD9833, the user can modulate the carrier frequency between the two values.
The AD9833 has two phase registers, which enables the part to perform PSK. With phase-shift keying, the carrier frequency is phase shifted, the phase being altered by an amount that is related to the bit stream being input to the modulator.
The AD9833 is also suitable for signal generator applications. Because the MSB of the DAC data is available at the VOUT pin, the device can be used to generate a square wave.
With its low current consumption, the part is suitable for applications in which it can be used as a local oscillator.
GROUNDING AND LAYOUT
The printed circuit board (PCB) that houses the AD9833 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes because it gives the best shielding. Digital and analog ground planes should be joined in one place only. If the AD9833 is the only device requiring an AGND-to-DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD9833. If the AD9833 is in a system where multiple devices require AGND-to-DGND connections, the connection should be made at one point only, a star ground point that should be established as close as possible to the AD9833.
Avoid running digital lines under the device as these couple noise onto the die. The analog ground plane should be allowed to run under the AD9833 to avoid noise coupling. The power supply lines to the AD9833 should use as large a track as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board.
Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but it is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, and signals are placed on the other side.
Good decoupling is important. The AD9833 should have supply bypassing of 0.1 μF ceramic capacitors in parallel with 10 μF tantalum capacitors. To achieve the best performance from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device.
AD9833 Data Sheet
Rev. E | Page 18 of 24
DATA WRITE(SEE FIGURE 28)SELECT DATASOURCESWAIT 7/8 MCLKCYCLESVOUT = VREF × 18 × RLOAD/ RSET× (1 + (SIN (2π (FREQREG ×fMCLK×t/228 + PHASEREG / 212))))DAC OUTPUTCHANGE PHASE?CHANGE FREQUENCY?CHANGE DAC OUTPUTFROM SIN TO RAMP?CHANGE OUTPUT TOA DIGITAL SIGNAL?CHANGEPSELECT?CHANGE PHASEREGISTER?CHANGEFSELECT?CHANGE FREQUENCYREGISTER?CONTROL REGISTERWRITE(SEE TABLE 6)INITIALIZATION(SEE FIGURE 27 BELOW)NONONONOYESNOYESYESNOYESYESYESYESYES02704-026
Figure 26. Flowchart for AD9833 Initialization and Operation
INITIALIZATIONAPPLY RESET(CONTROL REGISTER WRITE)RESET = 1WRITE TO FREQUENCY AND PHASE REGISTERSFREQ0 REG =fOUT0/fMCLK × 228FREQ1 REG =fOUT1/fMCLK × 228PHASE0 AND PHASE1 REG = (PHASESHIFT × 212)/2π(SEE FIGURE 28)SET RESET = 0SELECT FREQUENCY REGISTERSSELECT PHASE REGISTERS(CONTROL REGISTER WRITE)RESET BIT = 0FSELECT = SELECTED FREQUENCY REGISTERPSELECT = SELECTED PHASE REGISTER02704-027
Figure 27. Flowchart for Initialization
Data Sheet AD9833
Rev. E | Page 19 of 24
NOWRITE 14MSBs OR LSBsTO A FREQUENCY REGISTER?(CONTROL REGISTER WRITE)B28 (D13) = 0HLB (D12) = 0/1WRITE A 16-BIT WORD(SEE TABLE 10 AND TABLE 11FOR EXAMPLES)WRITE 14MSBs OR LSBsTO AFREQUENCY REGISTER?WRITE TO PHASEREGISTER?(16-BIT WRITE)D15, D14 = 11 D13 = 0/1 (CHOOSE THE PHASE REGISTER) D12 = XD11 ... D0 = PHASE DATAWRITE TO ANOTHERPHASE REGISTER?YESWRITE ANOTHER FULL28-BIT WORD TO AFREQUENCY REGISTER?WRITE TWO CONSECUTIVE16-BIT WORDS(SEE TABLE 9 FOR EXAMPLE)(CONTROL REGISTER WRITE)B28 (D13) = 1WRITE A FULL 28-BIT WORDTO A FREQUENCY REGISTER?DATA WRITENOYESYESNOYESONONYESYES02704-028
Figure 28. Flowchart for Data Writes
AD9833 Data Sheet
Rev. E | Page 20 of 24
INTERFACING TO MICROPROCESSORS
The AD9833 has a standard serial interface that allows the part to interface directly with several microprocessors. The device uses an external serial clock to write the data or control information into the device. The serial clock can have a frequency of 40 MHz maximum. The serial clock can be continuous, or it can idle high or low between write operations. When data or control informa-tion is written to the AD9833, FSYNC is taken low and is held low until the 16 bits of data are written into the AD9833. The FSYNC signal frames the 16 bits of information that are loaded into the AD9833.
AD9833 TO 68HC11/68L11 INTERFACE
Figure 29 shows the serial interface between the AD9833 and the 68HC11/68L11 microcontroller. The microcontroller is con-figured as the master by setting the MSTR bit in the SPCR to 1. This setting provides a serial clock on SCK; the MOSI output drives the serial data line SDATA. Because the microcontroller does not have a dedicated frame sync pin, the FSYNC signal is derived from a port line (PC7). The setup conditions for correct operation of the interface are as follows:
• SCK idles high between write operations (CPOL = 0)
• Data is valid on the SCK falling edge (CPHA = 1)
When data is being transmitted to the AD9833, the FSYNC line is taken low (PC7). Serial data from the 68HC11/68L11 is trans-mitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data into the AD9833, PC7 is held low after the first eight bits are transferred, and a second serial write operation is performed to the AD9833. Only after the second eight bits are transferred should FSYNC be taken high again.
AD9833FSYNCSDATASCLK68HC11/68L11PC7MOSISCK02704-030
Figure 29. 68HC11/68L11 to AD9833 Interface
AD9833 TO 80C51/80L51 INTERFACE
Figure 30 shows the serial interface between the AD9833 and the 80C51/80L51 microcontroller. The microcontroller is oper-ated in Mode 0 so that TxD of the 80C51/80L51 drives SCLK of the AD9833, and RxD drives the serial data line SDATA. The FSYNC signal is derived from a bit programmable pin on the port (P3.3 is shown in Figure 30).
When data is to be transmitted to the AD9833, P3.3 is taken low. The 80C51/80L51 transmits data in 8-bit bytes, thus only eight falling SCLK edges occur in each cycle. To load the remaining eight bits to the AD9833, P3.3 is held low after the first eight bits are transmitted, and a second write operation is initiated to transmit the second byte of data. P3.3 is taken high following the completion of the second write operation. SCLK should idle high between the two write operations.
The 80C51/80L51 outputs the serial data in a format that has the LSB first. The AD9833 accepts the MSB first (the four MSBs are the control information, the next four bits are the address, and the eight LSBs contain the data when writing to a destination register). Therefore, the transmit routine of the 80C51/80L51 must take this into account and rearrange the bits so that the MSB is output first.
AD9833FSYNCSDATASCLK80C51/80L51P3.3RxDTxD02704-031
Figure 30. 80C51/80L51 to AD9833 Interface
AD9833 TO DSP56002 INTERFACE
Figure 31 shows the interface between the AD9833 and the DSP56002. The DSP56002 is configured for normal mode asyn-chronous operation with a gated internal clock (SYN = 0, GCK = 1, SCKD = 1). The frame sync pin is generated internally (SC2 = 1), the transfers are 16 bits wide (WL1 = 1, WL0 = 0), and the frame sync signal frames the 16 bits (FSL = 0). The frame sync signal is available on the SC2 pin, but it must be inverted before it is applied to the AD9833. The interface to the DSP56000/DSP56001 is similar to that of the DSP56002.
AD9833FSYNCSDATASCLKDSP56002SC2STDSCK02704-032
Figure 31. DSP56002 to AD9833 Interface
Data Sheet AD9833
Rev. E | Page 21 of 24
EVALUATION BOARD
The AD9833 evaluation board allows designers to evaluate the high performance AD9833 DDS modulator with a minimum of effort.
SYSTEM DEMONSTRATION PLATFORM
The system demonstration platform (SDP) is a hardware and software evaluation tool for use in conjunction with product evaluation boards. The SDP board is based on the Blackfin® ADSP-BF527 processor with USB connectivity to the PC through a USB 2.0 high speed port. For more information about the SDP board, see the SDP board product page.
Note that the SDP board is sold separately from the AD9833 evaluation board.
AD9833 TO SPORT INTERFACE
The Analog Devices SDP board has a SPORT serial port that is used to control the serial inputs to the AD9833. The connections are shown in Figure 32.
AD9833FSYNCSDATASCLK02704-034SPORT_TFSSPORT_TSCLKSPORT_DTOADSP-BF527
Figure 32. SDP to AD9833 Interface
EVALUATION KIT
The DDS evaluation kit includes a populated, tested AD9833 printed circuit board (PCB). The schematics of the evaluation board are shown in Figure 34 and Figure 35.
The software provided in the evaluation kit allows the user to easily program the AD9833 (see Figure 33). The evaluation soft-ware runs on any IBM-compatible PC with Microsoft® Windows® software installed (including Windows 7). The software is com-patible with both 32-bit and 64-bit operating systems.
More information about the evaluation software is available on the software CD and on the AD9833 product page.
02704-035
Figure 33. AD9833 Evaluation Software Interface
CRYSTAL OSCILLATOR VS. EXTERNAL CLOCK
The AD9833 can operate with master clocks up to 25 MHz. A 25 MHz oscillator is included on the evaluation board. This oscillator can be removed and, if required, an external CMOS clock can be connected to the part. Options for the general oscillator include the following:
• AEL 301-Series oscillators, AEL Crystals
• SG-310SCN oscillators, Epson Electronics
POWER SUPPLY
Power to the AD9833 evaluation board can be provided from the USB connector or externally through pin connections. The power leads should be twisted to reduce ground loops.
AD9833 Data Sheet
Rev. E | Page 22 of 24
EVALUATION BOARD SCHEMATICS
02704-036
Figure 34. Evaluation Board Schematic
02704-037
Figure 35. SDP Connector Schematic
Data Sheet AD9833
Rev. E | Page 23 of 24
EVALUATION BOARD LAYOUT
02704-038
Figure 36. AD9833 Evaluation Board Component Side
02704-039
Figure 37. AD9833 Evaluation Board Silkscreen
02704-040
Figure 38. AD9833 Evaluation Board Solder Side
AD9833 Data Sheet
Rev. E | Page 24 of 24 OUTLINE DIMENSIONS
COMPLIANTTOJEDECSTANDARDSMO-187-BA
091709-A
6°
0°
0.70
0.55
0.40
5
10
1
6
0.50BSC
0.30
0.15
1.10MAX
3.10
3.00
2.90
COPLANARITY
0.10
0.23
0.13
3.10
3.00
2.90
5.15
4.90
4.65
PIN 1
IDENTIFIER
15°MAX 0.95
0.85
0.75
0.15
0.05
Figure 39. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2, 3 Temperature Range Package Description Package Option Branding
AD9833BRM −40°C to +105°C 10-Lead MSOP RM-10 DJB
AD9833BRM-REEL −40°C to +105°C 10-Lead MSOP RM-10 DJB
AD9833BRM-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 DJB
AD9833BRMZ −40°C to +105°C 10-Lead MSOP RM-10 D68
AD9833BRMZ-REEL −40°C to +105°C 10-Lead MSOP RM-10 D68
AD9833BRMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D68
AD9833WBRMZ-REEL −40°C to +105°C 10-Lead MSOP RM-10 D68
EVAL-AD9833SDZ Evaluation Board
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 The evaluation board for the AD9833 requires the system demonstration platform (SDP) board, which is sold separately. AUTOMOTIVE PRODUCTS
The AD9833WBRMZ-REEL model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore,
designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for
use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and
to obtain the specific Automotive Reliability reports for these models. ©2003–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02704-0-9/12(E)
Triple-Channel Digital Isolators
Data Sheet ADuM1300/ADuM1301
Rev. J Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES Qualified for automotive applications Low power operation 5 V operation
1.2 mA per channel maximum at 0 Mbps to 2 Mbps 3.5 mA per channel maximum at 10 Mbps 32 mA per channel maximum at 90 Mbps 3 V operation
0.8 mA per channel maximum at 0 Mbps to 2 Mbps 2.2 mA per channel maximum at 10 Mbps 20 mA per channel maximum at 90 Mbps Bidirectional communication 3 V/5 V level translation
High temperature operation: 125°C High data rate: dc to 90 Mbps (NRZ)
Precise timing characteristics 2 ns maximum pulse width distortion
2 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Output enable function
16-lead SOIC wide body package
RoHS-compliant models available
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 560 V peak TÜV approval: IEC/EN/UL/CSA 61010-1 APPLICATIONS
General-purpose multichannel isolation
SPI interface/data converter isolation
RS-232/RS-422/RS-485 transceivers Industrial field bus isolation
Automotive systems GENERAL DESCRIPTION
The ADuM130x1 are triple-channel digital isolators based on the
Analog Devices, Inc., iCoupler® technology. Combining high speed CMOS and monolithic transformer technology, these isolation components provide outstanding performance
characteristics superior to alternatives, such as optocouplers. By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding
uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the
simple iCoupler digital interfaces and stable performance
characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler devices consume one-tenth to one-sixth
of the power of optocouplers at comparable signal data rates. The ADuM130x isolators provide three independent isolation
channels in a variety of channel configurations and data rates
(see the Ordering Guide). Both models operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier. In addition, the ADuM130x provide low pulse width distortion (<2 ns for CRW grade) and tight channel-to-channel matching (<2 ns for CRW grade). Unlike other optocoupler alternatives,
the ADuM130x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and when power is not applied to one of the supplies. 1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.
FUNCTIONAL BLOCK DIAGRAMS
Figure 1. ADuM1300 Functional Block Diagram
Figure 2. ADuM1301 Functional Block Diagram
ENCODE DECODE
ENCODE DECODE
ENCODE DECODE
VDD1
GND1
VIA
VIB
VIC
NC
NC
GND1
VDD2
GND2
VOA
VOB
VOC
NC
VE2
GND2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
03787-001
DECODE ENCODE
ENCODE DECODE
ENCODE DECODE
VDD1
GND1
VIA
VIB
VOC
NC
VE1
GND1
VDD2
GND2
VOA
VOB
VIC
NC
VE2
GND2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
03787-002
ADuM1300/ADuM1301 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 3
Specifications ..................................................................................... 4
Electrical Characteristics—5 V, 105°C Operation ................... 4
Electrical Characteristics—3 V, 105°C Operation ................... 6
Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V, 105°C Operation ........................................................................... 8
Electrical Characteristics—5 V, 125°C Operation ................. 11
Electrical Characteristics—3 V, 125°C Operation ................. 13
Electrical Characteristics—Mixed 5 V/3 V, 125°C Operation ... 15
Electrical Characteristics—Mixed 3 V/5 V 125°C Operation ... 17
Package Characteristics ............................................................. 19
Regulatory Information ............................................................. 19
Insulation and Safety-Related Specifications .......................... 19
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation Characteristics ......................................................... 20
Recommended Operating Conditions .................................... 20
Absolute Maximum Ratings ......................................................... 21
ESD Caution................................................................................ 21
Pin Configurations and Function Descriptions ......................... 22
Typical Performance Characteristics ........................................... 23
Applications Information .............................................................. 25
PC Board Layout ........................................................................ 25
Propagation Delay-Related Parameters ................................... 25
DC Correctness and Magnetic Field Immunity .......................... 25
Power Consumption .................................................................. 26
Insulation Lifetime ..................................................................... 27
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
Automotive Products ................................................................. 29 Rev. J | Page 2 of 32
Data Sheet ADuM1300/ADuM1301
REVISION HISTORY
4/14—Rev. I to Rev. J
Change to Table 9 ............................................................................ 19
3/12—Rev. H to Rev. I
Created Hyperlink for Safety and Regulatory Approvals Entry in Features Section ................................................................. 1 Change to PC Board Layout Section ............................................ 25 Updated Outline Dimensions ........................................................ 28 Moved Automotive Products Section ........................................... 28
5/08—Rev. G to Rev. H
Added ADuM1300W and ADuM1301W Parts ............. Universal Changes to Features List ................................................................... 1 Added Table 4 .................................................................................. 11 Added Table 5 .................................................................................. 13 Added Table 6 .................................................................................. 15 Added Table 7 .................................................................................. 17 Changes to Table 12 ........................................................................ 20 Changes to Table 13 ........................................................................ 21 Added Automotive Products Section ........................................... 27 Changes to Ordering Guide ........................................................... 28
11/07—Rev. F to Rev. G
Changes to Note 1 and Figure 2 ...................................................... 1 Added ADuM130xARW Change vs. Temperature Parameter ... 3 Added ADuM130xARW Change vs. Temperature Parameter ... 5 Added ADuM130xARW Change vs. Temperature Parameter ... 8 Changes to Figure 14 ...................................................................... 16
6/07—Rev. E to Rev. F
Updated VDE Certification Throughout ....................................... 1 Changes to Features, Note 1, Figure 1, and Figure 2 .................... 1 Changes to Regulatory Information Section ............................... 10 Added Table 10 ................................................................................ 12 Added Insulation Lifetime Section ............................................... 17 Updated Outline Dimensions ........................................................ 19 Changes to Ordering Guide ........................................................... 19
2/06—Rev. D to Rev. E
Updated Format ................................................................. Universal Added TÜV Approval ....................................................... Universal Changes to Figure 2 .......................................................................... 1
5/05—Rev. C to Rev. D
Changes to Format ............................................................. Universal Changes to Figure 2 .......................................................................... 1 Changes to Table 6 .......................................................................... 10 Changes to Ordering Guide ........................................................... 18
6/04—Rev. B to Rev. C
Changes to Format ............................................................. Universal Changes to Features .......................................................................... 1 Changes to Electrical Characteristics—5 V Operation ................ 3 Changes to Electrical Characteristics—3 V Operation ................ 5 Changes to Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V Operation ............................................................................ 7 Changes to Ordering Guide ........................................................... 18
5/04—Rev. A to Rev. B
Changes to the Format ...................................................... Universal Changes to the Features.................................................................... 1 Changes to Table 7 and Table 8 ..................................................... 14 Changes to Table 9 .......................................................................... 15 Changes to the DC Correctness and Magnetic Field Immunity Section .............................................................................................. 19 Changes to the Power Consumption Section .............................. 20 Changes to the Ordering Guide .................................................... 21
9/03—Rev. 0 to Rev. A
Edits to Regulatory Information ................................................... 13 Edits to Absolute Maximum Ratings ............................................ 15 Deleted the Package Branding Information ................................ 16
9/03—Revision 0: Initial Version
Rev. J | Page 3 of 32
ADuM1300/ADuM1301 Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V, 105°C OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. These specifications do not apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.50
0.53
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.19
0.24
mA
ADuM1300 Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
1.6
2.5
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.7
1.0
mA
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
IDD1 (10)
6.5
8.1
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.9
2.5
mA
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
IDD1 (90)
57
77
mA
45 MHz logic signal freq.
VDD2 Supply Current
IDD2 (90)
16
18
mA
45 MHz logic signal freq.
ADuM1301 Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
1.3
2.1
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
1.0
1.4
mA
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
IDD1 (10)
5.0
6.2
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
3.4
4.2
mA
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
IDD1 (90)
43
57
mA
45 MHz logic signal freq.
VDD2 Supply Current
IDD2 (90)
29
37
mA
45 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC, IE1, IE2
−10
+0.01
+10
μA
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold
VIH, VEH
2.0
V
Logic Low Input Threshold
VIL, VEL
0.8
V
Logic High Output Voltages
VOAH, VOBH, VOCH
(VDD1 or VDD2) − 0.1
5.0
V
IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.4
4.8
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL, VOCL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xARW
Minimum Pulse Width2
PW
1000
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
1
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
50
65
100
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
11
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
50
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
CL = 15 pF, CMOS signal levels Rev. J | Page 4 of 32
Data Sheet ADuM1300/ADuM1301
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
ADuM130xBRW
Minimum Pulse Width2
PW
100
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
10
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
20
32
50
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
15
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
3
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
ADuM130xCRW
Minimum Pulse Width2
PW
8.3
11.1
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
90
120
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
18
27
32
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
0.5
2
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
3
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
10
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
2
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay (High/Low to High Impedance)
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High Impedance to High/Low)
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
2.5
ns
CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V
Common-Mode Transient Immunity at Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
1.2
Mbps
Input Dynamic Supply Current per Channel8
IDDI (D)
0.19
mA/Mbps
Output Dynamic Supply Current per Channel8
IDDO (D)
0.05
mA/Mbps
1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. J | Page 5 of 32
ADuM1300/ADuM1301 Data Sheet
ELECTRICAL CHARACTERISTICS—3 V, 105°C OPERATION
All voltages are relative to their respective ground. 2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. These specifications do not apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.26
0.31
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.11
0.15
mA
ADuM1300 Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.9
1.7
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.4
0.7
mA
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
IDD1 (10)
3.4
4.9
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.1
1.6
mA
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
IDD1 (90)
31
48
mA
45 MHz logic signal freq.
VDD2 Supply Current
IDD2 (90)
8
13
mA
45 MHz logic signal freq.
ADuM1301 Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.7
1.4
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.6
0.9
mA
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
IDD1 (10)
2.6
3.7
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.8
2.5
mA
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
IDD1 (90)
24
36
mA
45 MHz logic signal freq.
VDD2 Supply Current
IDD2 (90)
16
23
mA
45 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC, IE1, IE2
−10
+0.01
+10
μA
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold
VIH, VEH
1.6
V
Logic Low Input Threshold
VIL, VEL
0.4
V
Logic High Output Voltages
VOAH, VOBH, VOCH
(VDD1 or VDD2) − 0.1
3.0
V
IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.4
2.8
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL, VOCL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xARW
Minimum Pulse Width2
PW
1000
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
1
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
50
75
100
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
11
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
50
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
CL = 15 pF, CMOS signal levels Rev. J | Page 6 of 32
Data Sheet ADuM1300/ADuM1301
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
ADuM130xBRW
Minimum Pulse Width2
PW
100
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
10
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
20
38
50
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
26
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
3
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels
ADuM130xCRW
Minimum Pulse Width2
PW
8.3
11.1
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
90
120
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
20
34
45
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
0.5
2
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
3
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
16
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
2
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay (High/Low to High Impedance)
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High Impedance to High/Low)
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
3
ns
CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V
Common-Mode Transient Immunity at Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
1.1
Mbps
Input Dynamic Supply Current per Channel8
IDDI (D)
0.10
mA/Mbps
Output Dynamic Supply Current per Channel8
IDDO (D)
0.03
mA/Mbps
1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.
Rev. J | Page 7 of 32
ADuM1300/ADuM1301 Data Sheet
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V, 105°C OPERATION
All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V or VDD1 = 5 V, VDD2 = 3.0 V. These specifica-tions do not apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
5 V/3 V Operation
0.50
0.53
mA
3 V/5 V Operation
0.26
0.31
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
5 V/3 V Operation
0.11
0.15
mA
3 V/5 V Operation
0.19
0.24
mA
ADuM1300 Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
5 V/3 V Operation
1.6
2.5
mA
DC to 1 MHz logic signal freq.
3 V/5 V Operation
0.9
1.7
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
5 V/3 V Operation
0.4
0.7
mA
DC to 1 MHz logic signal freq.
3 V/5 V Operation
0.7
1.0
mA
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
IDD1 (10)
5 V/3 V Operation
6.5
8.1
mA
5 MHz logic signal freq.
3 V/5 V Operation
3.4
4.9
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
5 V/3 V Operation
1.1
1.6
mA
5 MHz logic signal freq.
3 V/5 V Operation
1.9
2.5
mA
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
VDD1 Supply Current
IDD1 (90)
5 V/3 V Operation
57
77
mA
45 MHz logic signal freq.
3 V/5 V Operation
31
48
mA
45 MHz logic signal freq.
VDD2 Supply Current
IDD2 (90)
5 V/3 V Operation
8
13
mA
45 MHz logic signal freq.
3 V/5 V Operation
16
18
mA
45 MHz logic signal freq.
ADuM1301 Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
5 V/3 V Operation
1.3
2.1
mA
DC to 1 MHz logic signal freq.
3 V/5 V Operation
0.7
1.4
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
5 V/3 V Operation
0.6
0.9
mA
DC to 1 MHz logic signal freq.
3 V/5 V Operation
1.0
1.4
mA
DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
VDD1 Supply Current
IDD1 (10)
5 V/3 V Operation
5.0
6.2
mA
5 MHz logic signal freq.
3 V/5 V Operation
2.6
3.7
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
5 V/3 V Operation
1.8
2.5
mA
5 MHz logic signal freq.
3 V/5 V Operation
3.4
4.2
mA
5 MHz logic signal freq. Rev. J | Page 8 of 32
Data Sheet ADuM1300/ADuM1301
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
90 Mbps (CRW Grade Only)
VDD1 Supply Current
IDD1 (90)
5 V/3 V Operation
43
57
mA
45 MHz logic signal freq.
3 V/5 V Operation
24
36
mA
45 MHz logic signal freq.
VDD2 Supply Current
IDD2 (90)
5 V/3 V Operation
16
23
mA
45 MHz logic signal freq.
3 V/5 V Operation
29
37
mA
45 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC, IE1, IE2
−10
+0.01
+10
μA
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold
VIH, VEH
5 V/3 V Operation
2.0
V
3 V/5 V Operation
1.6
V
Logic Low Input Threshold
VIL, VEL
5 V/3 V Operation
0.8
V
3 V/5 V Operation
0.4
V
Logic High Output Voltages
VOAH, VOBH, VOCH
(VDD1 or VDD2) − 0.1
(VDD1 or VDD2)
V
IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.4
(VDD1 or VDD2) − 0.2
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL, VOCL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xARW
Minimum Pulse Width2
PW
1000
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
1
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
50
70
100
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
11
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
50
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
CL = 15 pF, CMOS signal levels
ADuM130xBRW
Minimum Pulse Width2
PW
100
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
10
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
15
35
50
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
6
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
3
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
22
ns
CL = 15 pF, CMOS signal levels
ADuM130xCRW
Minimum Pulse Width2
PW
8.3
11.1
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
90
120
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
20
30
40
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
0.5
2
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
3
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
14
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
2
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
5
ns
CL = 15 pF, CMOS signal levels Rev. J | Page 9 of 32
ADuM1300/ADuM1301 Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
For All Models
Output Disable Propagation Delay (High/Low to High Impedance)
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High Impedance to High/Low)
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
CL = 15 pF, CMOS signal levels
5 V/3 V Operation
3.0
ns
3 V/5 V Operation
2.5
ns
Common-Mode Transient Immunity at Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V
Common-Mode Transient Immunity at Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
5 V/3 V Operation
1.2
Mbps
3 V/5 V Operation
1.1
Mbps
Input Dynamic Supply Current per Channel8
IDDI (D)
5 V/3 V Operation
0.19
mA/Mbps
3 V/5 V Operation
0.10
mA/Mbps
Output Dynamic Supply Current per Channel8
IDDO (D)
5 V/3 V Operation
0.03
mA/Mbps
3 V/5 V Operation
0.05
mA/Mbps
1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1300/ADuM1301 channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.
Rev. J | Page 10 of 32
Data Sheet ADuM1300/ADuM1301
ELECTRICAL CHARACTERISTICS—5 V, 125°C OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. These specifications apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.50
0.53
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.19
0.24
mA
ADuM1300W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
1.6
2.5
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.7
1.0
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
IDD1 (10)
6.5
8.1
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.9
2.5
mA
5 MHz logic signal freq.
ADuM1301W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
1.3
2.1
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
1.0
1.4
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
IDD1 (10)
5.0
6.2
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
3.4
4.2
mA
5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC, IE1, IE2
−10
+0.01
+10
μA
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold
VIH, VEH
2.0
V
Logic Low Input Threshold
VIL, VEL
0.8
V
Logic High Output Voltages
VOAH, VOBH, VOCH
VDD1, VDD2 − 0.1
5.0
V
IOx = −20 μA, VIx = VIxH
VDD1, VDD2 − 0.4
4.8
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL, VOCL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xWSRWZ
Minimum Pulse Width2
PW
1000
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
1
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
50
65
100
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
50
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
CL = 15 pF, CMOS signal levels
ADuM130xWTRWZ
Minimum Pulse Width2
PW
100
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
10
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
18
27
32
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
15
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
3
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels Rev. J | Page 11 of 32
ADuM1300/ADuM1301 Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
For All Models
Output Disable Propagation Delay (High/Low to High Impedance)
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High Impedance to High/Low)
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
2.5
ns
CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1/VDD2, VCM = 1000 V, transient magnitude = 800 V
Common-Mode Transient Immunity at Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
1.2
Mbps
Input Dynamic Supply Current per Channel8
IDDI (D)
0.19
mA/Mbps
Output Dynamic Supply Current per Channel8
IDDO (D)
0.05
mA/Mbps
1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADUM1300W/ADUM1301W channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. J | Page 12 of 32
Data Sheet ADuM1300/ADuM1301
ELECTRICAL CHARACTERISTICS—3 V, 125°C OPERATION
All voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. These specifications apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 5.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.26
0.31
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.11
0.15
mA
ADuM1300W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.9
1.7
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.4
0.7
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
IDD1 (10)
3.4
4.9
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.1
1.6
mA
5 MHz logic signal freq.
ADuM1301W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.7
1.4
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.6
0.9
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
IDD1 (10)
2.6
3.7
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.8
2.5
mA
5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC, IE1, IE2
−10
+0.01
+10
μA
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold
VIH, VEH
1.6
V
Logic Low Input Threshold
VIL, VEL
0.4
V
Logic High Output Voltages
VOAH, VOBH, VOCH
VDD1, VDD2 − 0.1
3.0
V
IOx = −20 μA, VIx = VIxH
VDD1, VDD2 − 0.4
2.8
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL, VOCL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xWSRWZ
Minimum Pulse Width2
PW
1000
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
1
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
50
75
100
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
50
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
CL = 15 pF, CMOS signal levels
ADuM130xWTRWZ
Minimum Pulse Width2
PW
100
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
10
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
20
34
45
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
26
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
3
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
6
ns
CL = 15 pF, CMOS signal levels Rev. J | Page 13 of 32
ADuM1300/ADuM1301 Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
For All Models
Output Disable Propagation Delay (High/Low to High Impedance)
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High Impedance to High/Low)
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
3
ns
CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1/VDD2, VCM = 1000 V, transient magnitude = 800 V
Common-Mode Transient Immunity at Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
1.1
Mbps
Input Dynamic Supply Current per Channel8
IDDI (D)
0.10
mA/Mbps
Output Dynamic Supply Current per Channel8
IDDO (D)
0.03
mA/Mbps
1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADUM1300W/ADUM1301W channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.
Rev. J | Page 14 of 32
Data Sheet ADuM1300/ADuM1301
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V, 125°C OPERATION1
All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 5 V, VDD2 = 3.0 V. These specifications apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 6.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.50
0.53
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.11
0.15
mA
ADuM1300W, Total Supply Current, Three Channels2
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
1.6
2.5
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.4
0.7
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
IDD1 (10)
6.5
8.1
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.1
1.6
mA
5 MHz logic signal freq.
ADuM1301W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
1.3
2.1
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.6
0.9
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
IDD1 (10)
5.0
6.2
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.8
2.5
mA
5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC, IE1, IE2
−10
+0.01
+10
μA
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold
VIH, VEH
2.0
V
Logic Low Input Threshold
VIL, VEL
0.8
V
Logic High Output Voltages
VOAH, VOBH, VOCH
VDD1, VDD2 − 0.1
VDD1, VDD2
V
IOx = −20 μA, VIx = VIxH
VDD1, VDD2 − 0.4
VDD1, VDD2 − 0.2
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL, VOCL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xWSRWZ
Minimum Pulse Width3
PW
1000
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate4
1
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay5
tPHL, tPLH
50
70
100
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
CL = 15 pF, CMOS signal levels
Propagation Delay Skew6
tPSK
50
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching7
tPSKCD/tPSKOD
50
ns
CL = 15 pF, CMOS signal levels
ADuM130xWTRWZ
Minimum Pulse Width2
PW
100
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
10
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
20
30
40
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
6
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
3
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
22
ns
CL = 15 pF, CMOS signal levels Rev. J | Page 15 of 32
ADuM1300/ADuM1301 Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
For All Models
Output Disable Propagation Delay (High/Low to High Impedance)
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High Impedance to High/Low)
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
3.0
ns
CL = 15 pF, CMOS signal levels
Common-Mode Transient Immunity at Logic High Output8
|CMH|
25
35
kV/μs
VIx = VDD1/VDD2, VCM = 1000 V, transient magnitude = 800 V
Common-Mode Transient Immunity at Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
1.2
Mbps
Input Dynamic Supply Current per Channel9
IDDI (D)
0.19
mA/Mbps
Output Dynamic Supply Current per Channel8
IDDO (D)
0.03
mA/Mbps
1 All voltages are relative to their respective ground.
2 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADUM1300W/ADUM1301W channel configurations.
3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
6 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
7 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. J | Page 16 of 32
Data Sheet ADuM1300/ADuM1301
ELECTRICAL CHARACTERISTICS—MIXED 3 V/5 V, 125°C OPERATION
All voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V. These apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 7.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.26
0.31
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.19
0.24
mA
ADuM1300W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.9
1.7
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2(Q)
0.7
1.0
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
IDD1 (10)
3.4
4.9
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.9
2.5
mA
5 MHz logic signal freq.
ADuM1301W, Total Supply Current, Three Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.7
1.4
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
1.0
1.4
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
VDD1 Supply Current
IDD1 (10)
2.6
3.7
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
3.4
4.2
mA
5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB, IIC, IE1, IE2
−10
+0.01
+10
μA
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2, 0 V ≤ VE1, VE2 ≤ VDD1 or VDD2
Logic High Input Threshold
VIH, VEH
1.6
V
Logic Low Input Threshold
VIL, VEL
0.4
V
Logic High Output Voltages
VOAH, VOBH, VOCH
VDD1, VDD2 − 0.1
VDD1, VDD2
V
IOx = −20 μA, VIx = VIxH
VDD1, VDD2 − 0.4
VDD1, VDD2 − 0.2
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL, VOCL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM130xWSRWZ
Minimum Pulse Width2
PW
1000
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
1
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
50
70
100
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
50
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
CL = 15 pF, CMOS signal levels
ADuM130xWTRWZ
Minimum Pulse Width2
PW
100
ns
CL = 15 pF, CMOS signal levels
Maximum Data Rate3
10
Mbps
CL = 15 pF, CMOS signal levels
Propagation Delay4
tPHL, tPLH
20
30
40
ns
CL = 15 pF, CMOS signal levels
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
CL = 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/°C
CL = 15 pF, CMOS signal levels
Propagation Delay Skew5
tPSK
6
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional Channels6
tPSKCD
3
ns
CL = 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-Directional Channels6
tPSKOD
22
ns
CL = 15 pF, CMOS signal levels Rev. J | Page 17 of 32
ADuM1300/ADuM1301 Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
For All Models
Output Disable Propagation Delay (High/Low to High Impedance)
tPHZ, tPLH
6
8
ns
CL = 15 pF, CMOS signal levels
Output Enable Propagation Delay (High Impedance to High/Low)
tPZH, tPZL
6
8
ns
CL = 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%)
tR/tF
CL = 15 pF, CMOS signal levels
5 V/3 V Operation
3.0
ns
3 V/5 V Operation
2.5
ns
Common-Mode Transient Immunity at Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1/VDD2, VCM = 1000 V, transient magnitude = 800 V
Common-Mode Transient Immunity at Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
1.1
Mbps
Input Dynamic Supply Current per Channel8
IDDI (D)
0.10
mA/Mbps
Output Dynamic Supply Current per Channel8
IDDO (D)
0.05
mA/Mbps
1 The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1300W/ADuM1301W channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate. Rev. J | Page 18 of 32
Data Sheet ADuM1300/ADuM1301
PACKAGE CHARACTERISTICS
Table 8.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
Resistance (Input-to-Output)1
RI-O
1012
Ω
Capacitance (Input-to-Output)1
CI-O
1.7
pF
f = 1 MHz
Input Capacitance2
CI
4.0
pF
IC Junction-to-Case Thermal Resistance, Side 1
θJCI
33
°C/W
Thermocouple located at center of package underside
IC Junction-to-Case Thermal Resistance, Side 2
θJCO
28
°C/W
1 Device is considered a 2-terminal device; Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14, Pin 15, and Pin 16 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM130x are approved by the organizations listed in Table 9. Refer to Table 14 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific crossisolation waveforms and insulation levels.
Table 9.
UL
CSA
VDE
TÜV
Recognized under 1577 Component Recognition Program1
Approved under CSA Component Acceptance Notice #5A
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-122
Approved according to IEC 61010-1:2001 (2nd Edition), EN 61010-1:2001 (2nd Edition), UL 61010-1:2004 CSA C22.2.61010.1:2005
Single protection, 2500 V rms isolation voltage
Basic insulation per CSA 60950-1-03 and IEC 60950-1, 800 V rms (1131 V peak) maximum working voltage
Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (566 V peak) maximum working voltage
Reinforced insulation, 560 V peak
Reinforced insulation, 400 V rms maximum working voltage
File E214100
File 205078
File 2471900-4880-0001
Certificate U8V 05 06 56232 002
1 In accordance with UL 1577, each ADuM130x is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 μA).
2 In accordance with DIN V VDE V 0884-10, each ADuM130x is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 10.
Parameter
Symbol
Value
Unit
Conditions
Rated Dielectric Insulation Voltage
2500
V rms
1-minute duration
Minimum External Air Gap (Clearance)
L(I01)
7.7 min
mm
Measured from input terminals to output terminals, shortest distance through air
Minimum External Tracking (Creepage)
L(I02)
8.1 min
mm
Measured from input terminals to output terminals, shortest distance path along body
Minimum Internal Gap (Internal Clearance)
0.017 min
mm
Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index)
CTI
>175
V
DIN IEC 112/VDE 0303 Part 1
Isolation Group
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
Rev. J | Page 19 of 32
ADuM1300/ADuM1301 Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval for 560 V peak working voltage.
Table 11.
Description
Conditions
Symbol
Characteristic
Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
I to IV
For Rated Mains Voltage ≤ 300 V rms
I to III
For Rated Mains Voltage ≤ 400 V rms
I to II
Climatic Classification
40/105/21
Pollution Degree per DIN VDE 0110, Table 1
2
Maximum Working Insulation Voltage
VIORM
560
V peak
Input-to-Output Test Voltage, Method B1
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec, partial discharge < 5 pC
VPR
1050
V peak
Input-to-Output Test Voltage, Method A
VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC
VPR
After Environmental Tests Subgroup 1
896
V peak
After Input and/or Safety Test Subgroup 2 and Subgroup 3
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC
672
V peak
Highest Allowable Overvoltage
Transient overvoltage, tTR = 10 seconds
VTR
4000
V peak
Safety-Limiting Values
Maximum value allowed in the event of a failure (see Figure 3)
Case Temperature
TS
150
°C
Side 1 Current
IS1
265
mA
Side 2 Current
IS2
335
mA
Insulation Resistance at TS
VIO = 500 V
RS
>109
Ω
Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 12.
Parameter
Rating
Operating Temperature (TA)1
−40°C to +105°C
Operating Temperature (TA)2
−40°C to +125°C
Supply Voltages (VDD1, VDD2)1, 3
2.7 V to 5.5 V
Supply Voltages (VDD1, VDD2) 2, 3
3.0 V to 5.5 V
Input Signal Rise and Fall Times
1.0 ms
1 Does not apply to ADuM1300W and ADuM1301W automotive grade versions.
2 Applies to ADuM1300W and ADuM1301W automotive grade versions.
3 All voltages are relative to their respective ground. See the DC Correctness and Magnetic Field Immunity section for information on immunity to external magnetic fields.
CASE TEMPERATURE (°C)SAFETY-LIMITING CURRENT (mA)003503002502001501005050100150200SIDE #1SIDE #203787-003
Rev. J | Page 20 of 32
Data Sheet ADuM1300/ADuM1301
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 13.
Parameter
Rating
Storage Temperature (TST)
−65°C to +150°C
Ambient Operating Temperature (TA)1
−40°C to +105°C
Ambient Operating Temperature (TA)2
−40°C to +125°C
Supply Voltages (VDD1, VDD2)3
−0.5 V to +7.0 V
Input Voltage (VIA, VIB, VIC, VE1, VE2)3, 4
−0.5 V to VDDI + 0.5 V
Output Voltage (VOA, VOB, VOC)3, 4
−0.5 V to VDDO + 0.5 V
Average Output Current per Pin5
Side 1 (IO1)
−23 mA to +23 mA
Side 2 (IO2)
−30 mA to +30 mA
Common-Mode Transients6
−100 kV/μs to +100 kV/μs
1 Does not apply to ADuM1300W and ADuM1301W automotive grade versions.
2 Applies to ADuM1300W and ADuM1301W automotive grade versions.
3 All voltages are relative to their respective ground.
4 VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the PC Board Layout section.
5 See Figure 3 for maximum rated current values for various temperatures.
6 This refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Ratings may cause latch-up or permanent damage.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Table 14. Maximum Continuous Working Voltage1
Parameter
Max
Unit
Constraint
AC Voltage, Bipolar Waveform
565
V peak
50-year minimum lifetime
AC Voltage, Unipolar Waveform
Basic Insulation
1131
V peak
Maximum approved working voltage per IEC 60950-1
Reinforced Insulation
560
V peak
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
DC Voltage
Basic Insulation
1131
V peak
Maximum approved working voltage per IEC 60950-1
Reinforced Insulation
560
V peak
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Table 15. Truth Table (Positive Logic)
VIx Input1
VEx Input1, 2
VDDI State1
VDDO State1
VOx Output1
Notes
H
H or NC
Powered
Powered
H
L
H or NC
Powered
Powered
L
X
L
Powered
Powered
Z
X
H or NC
Unpowered
Powered
H
Outputs return to the input state within 1 μs of VDDI power restoration.
X
L
Unpowered
Powered
Z
X
X
Powered
Unpowered
Indeterminate
Outputs return to the input state within 1 μs of VDDO power restoration if the VEx state is H or NC. Outputs return to a high impedance state within 8 ns of VDDO power restoration if the VEx state is L.
1 VIx and VOx refer to the input and output signals of a given channel (A, B, or C). VEx refers to the output enable signal on the same side as the VOx outputs. VDDI and VDDO refer to the supply voltages on the input and output sides of the given channel, respectively.
2 In noisy environments, connecting VEx to an external logic high or low is recommended.
Rev. J | Page 21 of 32
ADuM1300/ADuM1301 Data Sheet
Rev. J | Page 22 of 32 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. ADuM1300 Pin Configuration Figure 5. ADuM1301 Pin Configuration
Table 16. ADuM1300 Pin Function Descriptions Pin
No. Mnemonic Description 1 VDD1 Supply Voltage for Isolator Side 1. 2 GND1 Ground 1. Ground reference for Isolator Side 1. 3 VIA Logic Input A.
4 VIB Logic Input B.
5 VIC Logic Input C.
6 NC No Connect.
7 NC No Connect.
8 GND1 Ground 1. Ground reference for Isolator Side 1. 9 GND2 Ground 2. Ground reference for Isolator Side 2. 10 VE2 Output Enable 2. Active high logic input. VOA, VOB,
and VOC outputs are enabled when VE2 is high or disconnected. VOA, VOB, and VOC outputs are disabled
when VE2 is low. In noisy environments, connecting VE2 to an external logic high or low is recommended. 11 NC No Connect.
12 VOC Logic Output C. 13 VOB Logic Output B.
14 VOA Logic Output A.
15 GND2 Ground 2. Ground reference for Isolator Side 2. 16 VDD2 Supply Voltage for Isolator Side 2. Table 17. ADuM1301 Pin Function Descriptions Pin
No. Mnemonic Description 1 VDD1 Supply Voltage for Isolator Side 1. 2 GND1 Ground 1. Ground reference for Isolator Side 1. 3 VIA Logic Input A.
4 VIB Logic Input B.
5 VOC Logic Output C. 6 NC No Connect.
7 VE1 Output Enable 1. Active high logic input. VOC output is enabled when VE1 is high or disconnected. VOC
output is disabled when VE1 is low. In noisy environ-
ments, connecting VE1 to an external logic high
or low is recommended. 8 GND1 Ground 1. Ground reference for Isolator Side 1. 9 GND2 Ground 2. Ground reference for Isolator Side 2. 10 VE2 Output Enable 2. Active high logic input. VOA and
VOB outputs are enabled when VE2 is high or discon-
nected. VOA and VOB outputs are disabled when VE2 is
low. In noisy environments, connecting VE2 to an external logic high or low is recommended.
11 NC No Connect.
12 VIC Logic Input C.
13 VOB Logic Output B.
14 VOA Logic Output A.
15 GND2 Ground 2. Ground reference for Isolator Side 2. 16 VDD2 Supply Voltage for Isolator Side 2. VDD1 1
*GND1 2
VIA 3
VIB 4
VDD2 16
15 GND2*
14 VOA
13 VOB
VIC 5 12 VOC
NC 6 11 NC
NC 7 10 VE2
*GND1 8 GND9 2*
NC = NO CONNECT
ADuM1300
TOP VIEW
(Not to Scale)
03787-004
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING
BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED.
03787-005
VDD1 1
*GND1 2
VIA 3
VIB 4
VDD2 16
GND15 2*
14 VOA
13 VOB
VOC 5 12 VIC
NC 6 11 NC
VE1 7 10 VE2
*GND1 8 GND9 2*
NC = NO CONNECT
ADuM1301
TOP VIEW
(Not to Scale)
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING
BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED.
Data Sheet ADuM1300/ADuM1301
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 6. Typical Input Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation
Figure 7. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (No Output Load)
Figure 8. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (15 pF Output Load)
Figure 9. Typical ADuM1300 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation
Figure 10. Typical ADuM1300 VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation
Figure 11. Typical ADuM1301 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation
DATA RATE (Mbps)CURRENT/CHANNEL (mA)006421412108161820402060801005V3V03787-008DATA RATE (Mbps)CURRENT/CHANNEL (mA)00243516204060801005V3V03787-009DATA RATE (Mbps)CURRENT/CHANNEL (mA)0010987654321204080601005V3V03787-010DATA RATE (Mbps)CURRENT (mA)02002010504030604060801005V3V03787-011DATA RATE (Mbps)CURRENT (mA)00421086121614402060801005V3V03787-012DATA RATE (Mbps)CURRENT (mA)001510545403530252050204060801005V3V03787-013
Rev. J | Page 23 of 32
ADuM1300/ADuM1301 Data Sheet
Figure 12. Typical ADuM1301 VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation
Figure 13. Propagation Delay vs. Temperature, C Grade
DATA RATE (Mbps)CURRENT (mA)0010520152530204060801005V3V03787-014TEMPERATURE (°C)PROPAGATION DELAY (ns)–50–252530354005075251003V5V03787-019
Rev. J | Page 24 of 32
Data Sheet ADuM1300/ADuM1301
APPLICATIONS INFORMATION
PC BOARD LAYOUT
The ADuM130x digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 14). Bypass capacitors are most conveniently connected between Pin 1 and Pin 2 for VDD1 and between Pin 15 and Pin 16 for VDD2. The capacitor value should be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should also be considered unless the ground pair on each package side is connected close to the package.
Figure 14. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this could cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage.
See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic low output may differ from the propagation delay to a logic high output.
Figure 15. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount that the propagation delay differs between channels within a single ADuM130x component.
Propagation delay skew refers to the maximum amount that the propagation delay differs between multiple ADuM130x components operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is therefore either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 μs, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses for more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 15) by the watchdog timer circuit.
The ADuM130x is extremely immune to external magnetic fields. The limitation on the magnetic field immunity of the ADuM130x is set by the condition in which induced voltage in the receiving coil of the transformer is sufficiently large enough to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The 3 V operating condition of the ADuM130x is examined because it represents the most susceptible mode of operation.
The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by
V = (−dβ/dt)ΣΠrn2; n = 1, 2, … , N
where: β is magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm).
Given the geometry of the receiving coil in the ADuM130x and an imposed requirement that the induced voltage be 50% at most of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 16.
Figure 16. Maximum Allowable External Magnetic Flux Density
VDD1GND1VIAVIBVIC/VOCNCNC/VE1GND1VDD2GND2VOAVOBVOC/VICNCVE2GND203787-015INPUT (VIx)OUTPUT (VOx)tPLHtPHL50%50%03787-016MAGNETIC FIELD FREQUENCY (
Hz)100MAXIMUM ALLOWABLE MAGNETIC FLUXDENSITY (
kgauss)0.0011M100.011k10k10M0.11100M100k03787-017
Rev. J | Page 25 of 32
ADuM1300/ADuM1301 Data Sheet
For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (and has the worst-case polarity), it reduces the received pulse from >1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder.
The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM130x transformers. Figure 17 shows these allowable current magnitudes as a function of frequency for selected distances. The ADuM130x is extremely immune and can be affected only by extremely large currents operated at a high frequency very close to the component. For the 1 MHz example noted, one would have to place a 0.5 kA current 5 mm away from the ADuM130x to affect the operation of the component.
Figure 17. Maximum Allowable Current for Various Current-to-ADuM130x Spacings
Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.
POWER CONSUMPTION
The supply current at a given channel of the ADuM130x isolator is a function of the supply voltage, the data rate of the channel, and the output load of the channel.
For each input channel, the supply current is given by
IDDI = IDDI (Q) f ≤ 0.5 fr
IDDI = IDDI (D) × (2f − fr) + IDDI (Q) f > 0.5 fr
For each output channel, the supply current is given by
IDDO = IDDO (Q) f ≤ 0.5 fr
IDDO = (IDDO (D) + (0.5 × 10−3) × CL × VDDO) × (2f − fr) + IDDO (Q) f > 0.5 fr
where: IDDI (D), IDDO (D) are the input and output dynamic supply currents per channel (mA/Mbps). CL is the output load capacitance (pF). VDDO is the output supply voltage (V). f is the input logic signal frequency (MHz); it is half of the input data rate expressed in units of Mbps. fr is the input stage refresh rate (Mbps). IDDI (Q), IDDO (Q) are the specified input and output quiescent supply currents (mA).
To calculate the total VDD1 and VDD2 supply current, the supply currents for each input and output channel corresponding to VDD1 and VDD2 are calculated and totaled. Figure 6 and Figure 7 provide per-channel supply currents as a function of data rate for an unloaded output condition. Figure 8 provides per-channel supply current as a function of data rate for a 15 pF output condition. Figure 9 through Figure 12 provide total VDD1 and VDD2 supply current as a function of data rate for ADuM1300/ ADuM1301 channel configurations.
MAGNETIC FIELD FREQUENCY (Hz)MAXIMUM ALLOWABLE CURRENT (kA)10001001010.10.011k10k100M100k1M10MDISTANCE = 5mmDISTANCE = 1mDISTANCE = 100mm03787-018
Rev. J | Page 26 of 32
Data Sheet ADuM1300/ADuM1301
INSULATION LIFETIME
All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM130x.
Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Accel-eration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 14 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than the 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases.
The insulation lifetime of the ADuM130x depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 18, Figure 19, and Figure 20 illustrate these different isolation voltage waveforms, respectively.
Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the Analog Devices recommended maximum working voltage.
In the case of unipolar ac or dc voltage, the stress on the insu-lation is significantly lower, which allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 14 can be applied while main-taining the 50-year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage cases. Any cross insulation voltage waveform that does not conform to Figure 19 or Figure 20 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 14.
Note that the voltage presented in Figure 19 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V.
Figure 18. Bipolar AC Waveform
Figure 19. Unipolar AC Waveform
Figure 20. DC Waveform
0VRATED PEAK VOLTAGE03787-0210VRATED PEAK VOLTAGE03787-0220VRATED PEAK VOLTAGE03787-023
Rev. J | Page 27 of 32
ADuM1300/ADuM1301 Data Sheet
OUTLINE DIMENSIONS
Figure 21. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters (and inches)
ORDERING GUIDE
Model1, 2, 3, 4
Number of Inputs, VDD1 Side
Number of Inputs, VDD2 Side
Maximum Data Rate (Mbps)
Maximum Propagation Delay, 5 V (ns)
Maximum Pulse Width Distortion (ns)
Temperature Range
Package Option5
ADuM1300ARW
3
0
1
100
40
−40°C to +105°C
RW-16
ADuM1300CRW
3
0
90
32
2
−40°C to +105°C
RW-16
ADuM1300ARWZ
3
0
1
100
40
−40°C to +105°C
RW-16
ADuM1300BRWZ
3
0
10
50
3
−40°C to +105°C
RW-16
ADuM1300CRWZ
3
0
90
32
2
−40°C to +105°C
RW-16
ADuM1300WSRWZ
3
0
1
100
40
−40°C to +125°C
RW-16
ADuM1300WTRWZ
3
0
10
32
3
−40°C to +125°C
RW-16
ADuM1301ARW
2
1
1
100
40
−40°C to +105°C
RW-16
ADuM1301BRW
2
1
10
50
3
−40°C to +105°C
RW-16
ADuM1301CRW
2
1
90
32
2
−40°C to +105°C
RW-16
ADuM1301ARWZ
2
1
1
100
40
−40°C to +105°C
RW-16
ADuM1301BRWZ
2
1
10
50
3
−40°C to +105°C
RW-16
ADuM1301CRWZ
2
1
90
32
2
−40°C to +105°C
RW-16
ADuM1301WSRWZ
2
1
1
100
40
−40°C to +125°C
RW-16
ADuM1301WTRWZ
2
1
10
32
3
−40°C to +125°C
RW-16
EVAL-ADuMQSEBZ
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 Tape and reel are available. The addition of an -RL suffix designates a 13” (1,000 units) tape-and-reel option.
4 No tape-and-reel option is available for the ADuM1301CRW model.
5 RW-16 = 16-lead wide body SOIC.
CONTROLLINGDIMENSIONSAREINMILLIMETERS;INCHDIMENSIONS(INPARENTHESES)AREROUNDED-OFFMILLIMETEREQUIVALENTSFORREFERENCEONLYANDARENOTAPPROPRIATEFORUSEINDESIGN.COMPLIANTTOJEDECSTANDARDSMS-013-AA10.50(0.4134)10.10(0.3976)0.30(0.0118)0.10(0.0039)2.65(0.1043)2.35(0.0925)10.65(0.4193)10.00(0.3937)7.60(0.2992)7.40(0.2913)0.75(0.0295)0.25(0.0098)45°1.27(0.0500)0.40(0.0157)COPLANARITY0.100.33(0.0130)0.20(0.0079)0.51(0.0201)0.31(0.0122)SEATINGPLANE8°0°169811.27(0.0500)BSC03-27-2007-B
Rev. J | Page 28 of 32
Data Sheet ADuM1300/ADuM1301
AUTOMOTIVE PRODUCTS
The ADuM1300W/ADuM1301W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models.
Rev. J | Page 29 of 32
ADuM1300/ADuM1301 Data Sheet
NOTES
Rev. J | Page 30 of 32
Data Sheet ADuM1300/ADuM1301
NOTES
Rev. J | Page 31 of 32
ADuM1300/ADuM1301 Data Sheet
NOTES
©2003–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03787-0-4/14(J)
Rev. J | Page 32 of 32
Dual-Channel Digital Isolators
Data Sheet ADuM1200/ADuM1201
Rev. I
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved. FEATURES Narrow body, RoHS-compliant, SOIC 8-lead package
Low power operation 5 V operation
1.1 mA per channel maximum @ 0 Mbps to 2 Mbps 3.7 mA per channel maximum @ 10 Mbps 8.2 mA per channel maximum @ 25 Mbps
3 V operation
0.8 mA per channel maximum @ 0 Mbps to 2 Mbps 2.2 mA per channel maximum @ 10 Mbps
4.8 mA per channel maximum @ 25 Mbps
Bidirectional communication 3 V/5 V level translation
High temperature operation: 125°C High data rate: dc to 25 Mbps (NRZ)
Precise timing characteristics 3 ns maximum pulse width distortion
3 ns maximum channel-to-channel matching
High common-mode transient immunity: >25 kV/μs
Qualified for automotive applications Safety and regulatory approvals
UL recognition 2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
VIORM = 560 V peak APPLICATIONS
Size-critical multichannel isolation
SPI interface/data converter isolation
RS-232/RS-422/RS-485 transceiver isolation Digital field bus isolation
Hybrid electric vehicles, battery monitor, and motor drive GENERAL DESCRIPTION
The ADuM120x1 are dual-channel digital isolators based on the Analog Devices, Inc., iCoupler® technology. Combining
high speed CMOS and monolithic transformer technologies,
these isolation components provide outstanding performance
characteristics superior to alternatives, such as optocouplers. By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with opto-
couplers. The typical optocoupler concerns regarding uncertain
current transfer ratios, nonlinear transfer functions, and temper-
ature and lifetime effects are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products. Furthermore, iCoupler devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates. The ADuM120x isolators provide two independent isolation
channels in a variety of channel configurations and data rates
(see the Ordering Guide). Both parts operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling a
voltage translation functionality across the isolation barrier. In addition, the ADuM120x provide low pulse width distortion (<3 ns for CR grade) and tight channel-to-channel matching (<3 ns for CR grade). Unlike other optocoupler alternatives, the ADuM120x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions. The ADuM1200W and ADuM1201W are automotive grade
versions qualified for 125°C operation. See the Automotive Products section for more information. FUNCTIONAL BLOCK DIAGRAMS
ENCODE DECODE
ENCODE DECODE
VDD1
VIA
VIB
GND1
VDD2
VOA
VOB
GND2
1
2
3
4
8
7
6
5
04642-001
Figure 1. ADuM1200 Functional Block Diagram
ENCODE DECODE
DECODE ENCODE
VDD1
VOA
VIB
GND1
VDD2
VIA
VOB
GND2
1
2
3
4
8
7
6
5
04642-002
Figure 2. ADuM1201 Functional Block Diagram
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329.
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 2 of 28
TABLE OF CONTENTS
Features..............................................................................................1
Applications.......................................................................................1
General Description.........................................................................1
Functional Block Diagrams.............................................................1
Revision History...............................................................................3
Specifications.....................................................................................4
Electrical Characteristics—5 V, 105°C Operation...................4
Electrical Characteristics—3 V, 105°C Operation...................6
Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V, 105°C Operation...........................................................................8
Electrical Characteristics—5 V, 125°C Operation.................11
Electrical Characteristics—3 V, 125°C Operation.................13
Electrical Characteristics—Mixed 5 V/3 V, 125°C Operation15
Electrical Characteristics—Mixed 3 V/5 V, 125°C Operation17
Package Characteristics.............................................................19
Regulatory Information.............................................................19
Insulation and Safety-Related Specifications..........................19
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 Insulation Characteristics.........................................................20
Recommended Operating Conditions....................................20
Absolute Maximum Ratings.........................................................21
ESD Caution................................................................................21
Pin Configurations and Function Descriptions.........................22
Typical Performance Characteristics...........................................23
Applications Information..............................................................24
PCB Layout.................................................................................24
Propagation Delay-Related Parameters...................................24
DC Correctness and Magnetic Field Immunity...........................24
Power Consumption..................................................................25
Insulation Lifetime.....................................................................26
Outline Dimensions.......................................................................27
Ordering Guide..........................................................................27
Automotive Products.................................................................28
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 3 of 28
REVISION HISTORY
3/12—Rev. H to Rev. I
Created Hyperlink for Safety and Regulatory Approvals Entry in Features Section.................................................................1 Change to General Description Section.........................................1 Change to PCB Layout Section.....................................................24 Moved Automotive Products Section...........................................28
1/09—Rev. G to Rev. H
Changes to Table 5, Switching Specifications Parameter...........13 Changes to Table 6, Switching Specifications Parameter...........15 Changes to Table 7, Switching Specifications Parameter...........17
9/08—Rev. F to Rev. G
Changes to Table 9..........................................................................19
Changes to Table 13........................................................................21
Changes to Ordering Guide...........................................................27
3/08—Rev. E to Rev. F
Changes to Features Section............................................................1 Changes to Applications Section.....................................................1 Added Table 4..................................................................................11 Added Table 5..................................................................................13 Added Table 6..................................................................................15 Added Table 7..................................................................................17 Changes to Table 12........................................................................20 Changes to Table 13........................................................................21 Added Automotive Products Section...........................................26 Changes to Ordering Guide...........................................................27
11/07—Rev. D to Rev. E
Changes to Note 1.............................................................................1 Added ADuM120xAR Change vs. Temperature Parameter.......3 Added ADuM120xAR Change vs. Temperature Parameter.......5 Added ADuM120xAR Change vs. Temperature Parameter.......8
8/07—Rev. C to Rev. D
Updated VDE Certification Throughout.......................................1 Changes to Features, Note 1, Figure 1, and Figure 2....................1 Changes to Table 3............................................................................7 Changes to Regulatory Information Section...............................10 Added Table 10................................................................................12 Added Insulation Lifetime Section...............................................16 Updated Outline Dimensions........................................................18 Changes to Ordering Guide...........................................................18
2/06—Rev. B to Rev. C
Updated Format.................................................................Universal Added Note 1.....................................................................................1 Changes to Absolute Maximum Ratings......................................12 Changes to DC Correctness and Magnetic Field Immunity Section............................................................................15
9/04—Rev. A to Rev. B
Changes to Table 5..........................................................................10
6/04—Rev. 0 to Rev. A
Changes to Format.............................................................Universal Changes to General Description.....................................................1 Changes to Electrical Characteristics—5 V Operation................3 Changes to Electrical Characteristics—3 V Operation................5 Changes to Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V Operation............................................................................7
4/04—Revision 0: Initial Version
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 4 of 28
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V, 105°C OPERATION
All voltages are relative to their respective ground; 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V; this does not apply to the ADuM1200W and ADuM1201W automotive grade products.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.50
0.60
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.19
0.25
mA
ADuM1200 Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
1.1
1.4
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.5
0.8
mA
DC to 1 MHz logic signal freq.
10 Mbps (BR and CR Grades Only)
VDD1 Supply Current
IDD1 (10)
4.3
5.5
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.3
2.0
mA
5 MHz logic signal freq.
25 Mbps (CR Grade Only)
VDD1 Supply Current
IDD1 (25)
10
13
mA
12.5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (25)
2.8
3.4
mA
12.5 MHz logic signal freq.
ADuM1201 Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.8
1.1
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.8
1.1
mA
DC to 1 MHz logic signal freq.
10 Mbps (BR and CR Grades Only)
VDD1 Supply Current
IDD1 (10)
2.8
3.5
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
2.8
3.5
mA
5 MHz logic signal freq.
25 Mbps (CR Grade Only)
VDD1 Supply Current
IDD1 (25)
6.3
8.0
mA
12.5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (25)
6.3
8.0
mA
12.5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB
−10
+0.01
+10
μA
0 V ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold
VIH
0.7 (VDD1 or VDD2)
V
Logic Low Input Threshold
VIL
0.3 (VDD1 or VDD2)
V
Logic High Output Voltages
VOAH, VOBH
(VDD1 or VDD2) − 0.1
5.0
V
IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.5
4.8
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM120xAR
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
PW
1000
ns
Maximum Data Rate3
1
Mbps
Propagation Delay4 t
PHL, tPLH
50
150
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
Change vs. Temperature
11
ps/°C
Propagation Delay Skew5 t
PSK
100
ns
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
10
ns
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 5 of 28
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM120xBR
Minimum Pulse Width2
PW
100
ns
Maximum Data Rate3
10
Mbps
Propagation Delay4
tPHL, tPLH
20
50
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
Change vs. Temperature
5
ps/°C
Propagation Delay Skew5
tPSK
15
ns
Channel-to-Channel Matching
3
Codirectional Channels6
tPSKCD
ns
Opposing Directional Channels6
tPSKOD
15
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
2.5
ns
ADuM120xCR
Minimum Pulse Width2
PW
20
40
ns
Maximum Data Rate3
25
50
Mbps
Propagation Delay4
tPHL, tPLH
20
45
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
Change vs. Temperature
5
ps/°C
Propagation Delay Skew5
tPSK
15
ns
Channel-to-Channel Matching
3
ns
Codirectional Channels6
tPSKCD
Opposing Directional Channels6
tPSKOD
15
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
2.5
ns
For All Models
Common-Mode Transient Immunity
Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V
Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
1.2
Mbps
Dynamic Supply Current per Channel8
Input
IDDI (D)
0.19
mA/ Mbps
Output
IDDO (D)
0.05
mA/ Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the section. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.
Power ConsumptionPower Consumption
Figure 6 Figure 6
Figure 8Figure 8
Figure 9
Figure 11
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the section for guidance on calculating per-channel supply current for a given data rate.
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 6 of 28 ELECTRICAL CHARACTERISTICS—3 V, 105°C OPERATION
All voltages are relative to their respective ground; 2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V; this
does not apply to ADuM1200W and ADuM1201W automotive grade products.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent IDDI (Q) 0.26 0.35 mA
Output Supply Current per Channel, Quiescent IDDO (Q) 0.11 0.20 mA
ADuM1200 Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 0.6 1.0 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.2 0.6 mA DC to 1 MHz logic signal freq. 10 Mbps (BR and CR Grades Only) VDD1 Supply Current IDD1 (10) 2.2 3.4 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 0.7 1.1 mA 5 MHz logic signal freq. 25 Mbps (CR Grade Only)
VDD1 Supply Current IDD1 (25) 5.2 7.7 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 1.5 2.0 mA 12.5 MHz logic signal freq. ADuM1201 Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 0.4 0.8 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.4 0.8 mA DC to 1 MHz logic signal freq. 10 Mbps (BR and CR Grades Only) VDD1 Supply Current IDD1 (10) 1.5 2.2 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 1.5 2.2 mA 5 MHz logic signal freq. 25 Mbps (CR Grade Only)
VDD1 Supply Current IDD1 (25) 3.4 4.8 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 3.4 4.8 mA 12.5 MHz logic signal freq. For All Models Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold VIH 0.7 (VDD1 or VDD2) V
Logic Low Input Threshold VIL 0.3 (VDD1 or VDD2)
Logic High Output Voltages VOAH, VOBH (VDD1 or VDD2) − 0.1 3.0 V IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.5 2.8 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL 0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.04 0.1 V IOx = 400 μA, VIx = VIxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM120xAR CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 1000 ns
Maximum Data Rate3 1 Mbps
Propagation Delay4 tPHL, tPLH 50 150 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns Change vs. Temperature 11 ps/°C
Propagation Delay Skew5 tPSK 100 ns
Channel-to-Channel Matching6 tPSKCD/tPSKOD 50 ns
Output Rise/Fall Time (10% to 90%) tR/tF 10 ns
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 7 of 28
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM120xBR
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
PW
100
ns
Maximum Data Rate3
10
Mbps
Propagation Delay4
tPHL, tPLH
20
60
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
Change vs. Temperature
5
ps/°C
Propagation Delay Skew5
tPSK
22
ns
Channel-to-Channel Matching
Codirectional Channels6
tPSKCD
3
ns
Opposing Directional Channels6
tPSKOD
22
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
3.0
ns
ADuM120xCR
Minimum Pulse Width2
PW
20
40
ns
Maximum Data Rate3
25
50
Mbps
Propagation Delay4
tPHL, tPLH
20
55
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
Change vs. Temperature
5
ps/°C
Propagation Delay Skew5
tPSK
16
ns
Channel-to-Channel Matching
Codirectional Channels6
tPSKCD
3
ns
Opposing Directional Channels6
tPSKOD
16
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
3.0
ns
For All Models
Common-Mode Transient Immunity
Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V
Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
1.1
Mbps
Dynamic Supply Current per Channel8
Input
IDDI (D)
0.10
mA/
Mbps
Output
IDDO (D)
0.03
mA/
Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the section. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through Figure 11 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.
Power ConsumptionPower Consumption
Figure 6 Figure 6
Figure 8Figure 8
Figure 9
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the section for guidance on calculating per-channel supply current for a given data rate.
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 8 of 28 ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V, 105°C OPERATION
All voltages are relative to their respective ground; 5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V. 3 V/5 V operation: 2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operating range,
unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5.0 V; or VDD1 = 5.0 V, VDD2 = 3.0 V; this does not
apply to ADuM1200W and ADuM1201W automotive grade products. Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
5 V/3 V Operation 0.50 0.6 mA
3 V/5 V Operation 0.26 0.35 mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
5 V/3 V Operation 0.11 0.20 mA
3 V/5 V Operation 0.19 0.25 mA
ADuM1200 Total Supply Current,
Two Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q)
5 V/3 V Operation 1.1 1.4 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.6 1.0 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q)
5 V/3 V Operation 0.2 0.6 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.5 0.8 mA DC to 1 MHz logic signal freq. 10 Mbps (BR and CR Grades Only) VDD1 Supply Current IDD1 (10)
5 V/3 V Operation 4.3 5.5 mA 5 MHz logic signal freq. 3 V/5 V Operation 2.2 3.4 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10)
5 V/3 V Operation 0.7 1.1 mA 5 MHz logic signal freq. 3 V/5 V Operation 1.3 2.0 mA 5 MHz logic signal freq. 25 Mbps (CR Grade Only)
VDD1 Supply Current IDD1 (25)
5 V/3 V Operation 10 13 mA 12.5 MHz logic signal freq. 3 V/5 V Operation 5.2 7.7 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25)
5 V/3 V Operation 1.5 2.0 mA 12.5 MHz logic signal freq. 3 V/5 V Operation 2.8 3.4 mA 12.5 MHz logic signal freq. ADuM1201 Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q)
5 V/3 V Operation 0.8 1.1 mA DC to 1 MHz logic signal freq.
3 V/5 V Operation 0.4 0.8 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q)
5 V/3 V Operation 0.4 0.8 mA DC to 1 MHz logic signal freq. 3 V/5 V Operation 0.8 1.1 mA DC to 1 MHz logic signal freq. 10 Mbps (BR and CR Grades Only) VDD1 Supply Current IDD1 (10)
5 V/3 V Operation 2.8 3.5 mA 5 MHz logic signal freq. 3 V/5 V Operation 1.5 2.2 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10)
5 V/3 V Operation 1.5 2.2 mA 5 MHz logic signal freq. 3 V/5 V Operation 2.8 3.5 mA 5 MHz logic signal freq.
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 9 of 28
Parameter Symbol Min Typ Max Unit Test Conditions
25 Mbps (CR Grade Only)
VDD1 Supply Current
IDD1 (25)
5 V/3 V Operation
6.3
8.0
mA
12.5 MHz logic signal freq.
3 V/5 V Operation
3.4
4.8
mA
12.5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (25)
5 V/3 V Operation
3.4
4.8
mA
12.5 MHz logic signal freq.
3 V/5 V Operation
6.3
8.0
mA
12.5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB
−10
+0.01
+10
μA
0 V ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold
VIH
0.7 (VDD1 or VDD2)
V
Logic Low Input Threshold
VIL
0.3 (VDD1 or VDD2)
V
Logic High Output Voltages
VOAH, VOBH
(VDD1 or VDD2) − 0.1
VDD1 or VDD2
V
IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.5
(VDD1 or VDD2) − 0.2
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM120xAR
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
PW
1000
ns
Maximum Data Rate3
1
Mbps
Propagation Delay4
tPHL, tPLH
50
150
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
Change vs. Temperature
11
ps/°C
Propagation Delay Skew5 t
PSK
50
ns
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
10
ns
ADuM120xBR
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
PW
100
ns
Maximum Data Rate3
10
Mbps
Propagation Delay4
tPHL, tPLH
15
55
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
Change vs. Temperature
5
ps/°C
Propagation Delay Skew5
tPSK
22
ns
Channel-to-Channel Matching
Codirectional Channels6
tPSKCD
3
ns
Opposing Directional Channels6
tPSKOD
22
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
5 V/3 V Operation
3.0
ns
3 V/5 V Operation
2.5
ns
ADuM120xCR
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
PW
20
40
ns
Maximum Data Rate3
25
50
Mbps
Propagation Delay4
tPHL, tPLH
20
50
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
3
ns
Change vs. Temperature
5
ps/°C
Propagation Delay Skew5
tPSK
15
ns
Channel-to-Channel Matching
Codirectional Channels6
tPSKCD
3
ns
Opposing Directional Channels6
tPSKOD
15
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
5 V/3 V Operation
3.0
ns
3 V/5 V Operation
2.5
ns
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 10 of 28
Parameter Symbol Min Typ Max Unit Test Conditions
For All Models
Common-Mode Transient Immunity
Logic High Output7
|CMH|
25
35
kV/μs
VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V
Logic Low Output7
|CML|
25
35
kV/μs
VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate
fr
5 V/3 V Operation
1.2
Mbps
3 V/5 V Operation
1.1
Mbps
Input Dynamic Supply Current per Channel8
IDDI (D)
5 V/3 V Operation
0.19
mA/ Mbps
3 V/5 V Operation
0.10
mA/ Mbps
Output Dynamic Supply Current per Channel8
IDDO (D)
5 V/3 V Operation
0.03
mA/ Mbps
3 V/5 V Operation
0.05
mA/ Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the section. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See through for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1200 and ADuM1201 channel configurations.
Power ConsumptionPower Consumption
Figure 6 Figure 6
Figure 8Figure 8
Figure 9
Figure 11
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the section for guidance on calculating per-channel supply current for a given data rate.
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 11 of 28
ELECTRICAL CHARACTERISTICS—5 V, 125°C OPERATION
All voltages are relative to their respective ground; 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V; this applies to ADuM1200W and ADuM1201W automotive grade products.
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.50
0.60
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.19
0.25
mA
ADM1200W, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
1.1
1.4
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.5
0.8
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRZ and URZ Grades Only)
VDD1 Supply Current
IDD1 (10)
4.3
5.5
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.3
2.0
mA
5 MHz logic signal freq.
25 Mbps (URZ Grade Only)
VDD1 Supply Current
IDD1 (25)
10
13
mA
12.5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (25)
2.8
3.4
mA
12.5 MHz logic signal freq.
ADM1201W, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.8
1.1
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.8
1.1
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRZ and URZ Grades Only)
VDD1 Supply Current
IDD1 (10)
2.8
3.5
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
2.8
3.5
mA
5 MHz logic signal freq.
25 Mbps (URZ Grade Only)
VDD1 Supply Current
IDD1 (25)
6.3
8.0
mA
12.5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (25)
6.3
8.0
mA
12.5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB
−10
+0.01
+10
μA
0 ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold
VIH
0.7 (VDD1 or VDD2)
V
Logic Low Input Threshold
VIL
0.3 (VDD1 or VDD2)
V
Logic High Output Voltages
VOAH, VOBH
(VDD1 or VDD2) − 0.1
5.0
V
IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.5
4.8
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM120xWSRZ
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
PW
1000
ns
Maximum Data Rate3
1
Mbps
Propagation Delay4 t
PHL, tPLH
20
150
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
Propagation Delay Skew5
tPSK
100
ns
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
2.5
ns
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 12 of 28 Parameter Symbol Min Typ Max Unit Test Conditions ADuM120xWTRZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 100 ns Maximum Data Rate3 10 Mbps Propagation Delay4 tPHL, tPLH 20 50 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns
Change vs. Temperature 5 ps/°C
Propagation Delay Skew5 tPSK 15 ns Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 15 ns Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns
ADuM120xWURZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 20 40 ns Maximum Data Rate3 25 50 Mbps Propagation Delay4 tPHL, tPLH 20 45 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns
Change vs. Temperature 5 ps/°C
Propagation Delay Skew5 tPSK 15 ns Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 15 ns Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns
For All Models Common-Mode Transient Immunity Logic High Output7 |CMH| 25 35 kV/μs VIx = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V
Logic Low Output7 |CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
Refresh Rate fr 1.2 Mbps
Dynamic Supply Current per Channel8
Input IDDI (D) 0.19 mA/ Mbps
Output IDDO (D) 0.05 mA/ Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1200W and ADuM1201W channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate.
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 13 of 28
ELECTRICAL CHARACTERISTICS—3 V, 125°C OPERATION
All voltages are relative to their respective ground; 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V; this applies to ADuM1200W and ADuM1201W automotive grade products.
Table 5.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q)
0.26
0.35
mA
Output Supply Current per Channel, Quiescent
IDDO (Q)
0.11
0.20
mA
ADM1200W, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.6
1.0
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.2
0.6
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRZ and URZ Grades Only)
VDD1 Supply Current
IDD1 (10)
2.2
3.4
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
0.7
1.1
mA
5 MHz logic signal freq.
25 Mbps (URZ Grade Only)
VDD1 Supply Current
IDD1 (25)
5.2
7.7
mA
12.5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (25)
1.5
2.0
mA
12.5 MHz logic signal freq.
ADM1201W, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current
IDD1 (Q)
0.4
0.8
mA
DC to 1 MHz logic signal freq.
VDD2 Supply Current
IDD2 (Q)
0.4
0.8
mA
DC to 1 MHz logic signal freq.
10 Mbps (TRZ and URZ Grades Only)
VDD1 Supply Current
IDD1 (10)
1.5
2.2
mA
5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (10)
1.5
2.2
mA
5 MHz logic signal freq.
25 Mbps (URZ Grade Only)
VDD1 Supply Current
IDD1 (25)
3.4
4.8
mA
12.5 MHz logic signal freq.
VDD2 Supply Current
IDD2 (25)
3.4
4.8
mA
12.5 MHz logic signal freq.
For All Models
Input Currents
IIA, IIB
−10
+0.01
+10
μA
0 ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold
VIH
0.7 (VDD1 or VDD2)
V
Logic Low Input Threshold
VIL
0.3 (VDD1 or VDD2)
Logic High Output Voltages
VOAH, VOBH
(VDD1 or VDD2) − 0.1
3.0
V
IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.5
2.8
V
IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL
0.0
0.1
V
IOx = 20 μA, VIx = VIxL
0.04
0.1
V
IOx = 400 μA, VIx = VIxL
0.2
0.4
V
IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM120xWSRZ
CL = 15 pF, CMOS signal levels
Minimum Pulse Width2
PW
1000
ns
Maximum Data Rate3
1
Mbps
Propagation Delay4 t
PHL, tPLH
20
150
ns
Pulse Width Distortion, |tPLH − tPHL|4
PWD
40
ns
Propagation Delay Skew5 t
PSK
100
ns
Channel-to-Channel Matching6
tPSKCD/tPSKOD
50
ns
Output Rise/Fall Time (10% to 90%)
tR/tF
3
ns
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 14 of 28 Parameter Symbol Min Typ Max Unit Test Conditions ADuM120xWTRZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 100 ns Maximum Data Rate3 10 Mbps Propagation Delay4 tPHL, tPLH 20 60 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C
Propagation Delay Skew5 tPSK 22 ns
Channel-to-Channel Matching
Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 22 ns
Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns
ADuM120xWCR CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 20 40 ns Maximum Data Rate3 25 50 Mbps Propagation Delay4 tPHL, tPLH 20 55 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C
Propagation Delay Skew5 tPSK 16 ns Channel-to-Channel Matching
Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 16 ns Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns For All Models Common-Mode Transient Immunity Logic High Output7 |CMH| 25 35 kV/μs VIx = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V Logic Low Output7 |CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V Refresh Rate fr 1.1 Mbps
Dynamic Supply Current per Channel8
Input IDDI (D) 0.10 mA/ Mbps
Output IDDO (D) 0.03 mA/ Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1200W and ADuM1201W channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulsewidth distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulsewidth distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate.
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 15 of 28 ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V, 125°C OPERATION
All voltages are relative to their respective ground; 5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V. 3 V/5 V operation; all
minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted; all typical specifications
are at TA = 25°C; VDD1 = 5.0 V, VDD2 = 3.0 V; this applies to ADuM1200W and ADuM1201W automotive grade products. Table 6.
Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q) 0.50 0.6 mA
Output Supply Current per Channel, Quiescent
IDDO (Q) 0.11 0.20 mA
ADuM1200W, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 1.1 1.4 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.2 0.6 mA DC to 1 MHz logic signal freq. 10 Mbps (TRZ and URZ Grades Only) VDD1 Supply Current IDD1 (10) 4.3 5.5 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 0.7 1.1 mA 5 MHz logic signal freq. 25 Mbps (URZ Grade Only) VDD1 Supply Current IDD1 (25) 10 13 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 1.5 2.0 mA 12.5 MHz logic signal freq. ADuM1201W, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 0.8 1.1 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.4 0.8 mA DC to 1 MHz logic signal freq. 10 Mbps (TRZ and URZ Grades Only) VDD1 Supply Current IDD1 (10) 2.8 3.5 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 1.5 2.2 mA 5 MHz logic signal freq. 25 Mbps (URZ Grade Only) VDD1 Supply Current IDD1 (25) 6.3 8.0 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 3.4 4.8 mA 12.5 MHz logic signal freq. For All Models Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold VIH 0.7 (VDD1 or VDD2) V Logic Low Input Threshold VIL 0.3 (VDD1 or VDD2) V
Logic High Output Voltages VOAH, VOBH (VDD1 or VDD2) − 0.1 VDD1 or VDD2 V IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.5 (VDD1 or VDD2) − 0.2 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL 0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.04 0.1 V IOx = 400 μA, VIx = VIxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM120xWSRZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 1000 ns Maximum Data Rate3 1 Mbps
Propagation Delay4 tPHL, tPLH 15 150 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns Propagation Delay Skew5 tPSK 50 ns
Channel-to-Channel Matching6 tPSKCD/ tPSKOD 50 ns
Output Rise/Fall Time (10% to 90%) tR/tF 3 ns
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 16 of 28 Parameter Symbol Min Typ Max Unit Test Conditions ADuM120xWTRZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 100 ns Maximum Data Rate3 10 Mbps Propagation Delay4 tPHL, tPLH 15 55 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C
Propagation Delay Skew5 tPSK 22 ns
Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 22 ns
Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns ADuM120xWURZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 20 40 ns Maximum Data Rate3 25 50 Mbps Propagation Delay4 tPHL, tPLH 20 50 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C
Propagation Delay Skew5 tPSK 15 ns
Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 15 ns
Output Rise/Fall Time (10% to 90%) tR/tF 3.0 ns For All Models Common-Mode Transient Immunity Logic High Output7 |CMH| 25 35 kV/μs VIx = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V Logic Low Output7 |CML| 25 35 kV/μs VIx = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V Refresh Rate fr 1.2 Mbps
Dynamic Supply Current per Channel8
Input IDDI (D) 0.19 mA/ Mbps
Output IDDO (D) 0.03 mA/ Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1200W and ADuM1201W channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate.
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 17 of 28 ELECTRICAL CHARACTERISTICS—MIXED 3 V/5 V, 125°C OPERATION
All voltages are relative to their respective ground; 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted; all typical specifications are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5.0 V; this applies to ADuM1200W and ADuM1201W automotive grade products. Table 7.
Parameter Symbol Min Typ Max Unit Test Conditions DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
IDDI (Q) 0.26 0.35 mA
Output Supply Current per Channel, Quiescent
IDDO (Q) 0.19 0.25 mA
ADuM1200W, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 0.6 1.0 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.5 0.8 mA DC to 1 MHz logic signal freq. 10 Mbps (TRZ and URZ Grades Only) VDD1 Supply Current IDD1 (10) 2.2 3.4 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 1.3 2.0 mA 5 MHz logic signal freq. 25 Mbps (URZ Grade Only) VDD1 Supply Current IDD1 (25) 5.2 7.7 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 2.8 3.4 mA 12.5 MHz logic signal freq. ADuM1201W, Total Supply Current, Two Channels1
DC to 2 Mbps
VDD1 Supply Current IDD1 (Q) 0.4 0.8 mA DC to 1 MHz logic signal freq. VDD2 Supply Current IDD2 (Q) 0.8 1.1 mA DC to 1 MHz logic signal freq. 10 Mbps (TRZ and URZ Grades Only) VDD1 Supply Current IDD1 (10) 1.5 2.2 mA 5 MHz logic signal freq. VDD2 Supply Current IDD2 (10) 2.8 3.5 mA 5 MHz logic signal freq. 25 Mbps (URZ Grade Only) VDD1 Supply Current IDD1 (25) 3.4 4.8 mA 12.5 MHz logic signal freq. VDD2 Supply Current IDD2 (25) 6.3 8.0 mA 12.5 MHz logic signal freq. For All Models Input Currents IIA, IIB −10 +0.01 +10 μA 0 V ≤ VIA, VIB ≤ (VDD1 or VDD2)
Logic High Input Threshold VIH 0.7 (VDD1 or VDD2) V Logic Low Input Threshold VIL 0.3 (VDD1 or VDD2) V
Logic High Output Voltages VOAH, VOBH (VDD1 or VDD2) − 0.1 VDD1 or VDD2 V IOx = −20 μA, VIx = VIxH
(VDD1 or VDD2) − 0.5 (VDD1 or VDD2) − 0.2 V IOx = −4 mA, VIx = VIxH
Logic Low Output Voltages VOAL, VOBL 0.0 0.1 V IOx = 20 μA, VIx = VIxL
0.04 0.1 V IOx = 400 μA, VIx = VIxL
0.2 0.4 V IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS
ADuM120xWSRZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 1000 ns Maximum Data Rate3 1 Mbps
Propagation Delay4 tPHL, tPLH 15 150 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 40 ns Propagation Delay Skew5 tPSK 50 ns
Channel-to-Channel Matching6 tPSKCD/
tPSKOD
50 ns Output Rise/Fall Time (10% to 90%) tR/tF 3 ns
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 18 of 28 Parameter Symbol Min Typ Max Unit Test Conditions ADuM120xWTRZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 100 ns Maximum Data Rate3 10 Mbps Propagation Delay4 tPHL, tPLH 15 55 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C
Propagation Delay Skew5 tPSK 22 ns
Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 22 ns
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns ADuM120xWURZ CL = 15 pF, CMOS signal levels Minimum Pulse Width2 PW 20 40 ns Maximum Data Rate3 25 50 Mbps Propagation Delay4 tPHL, tPLH 20 50 ns
Pulse Width Distortion, |tPLH − tPHL|4 PWD 3 ns Change vs. Temperature 5 ps/°C
Propagation Delay Skew5 tPSK 15 ns
Channel-to-Channel Matching Codirectional Channels6 tPSKCD 3 ns Opposing Directional Channels6 tPSKOD 15 ns
Output Rise/Fall Time (10% to 90%) tR/tF 2.5 ns For All Models Common-Mode Transient Immunity Logic High Output7 |CMH| 25 35 kV/μs VIx = VDD1, VDD2, VCM = 1000 V, transient magnitude = 800 V Logic Low Output7 |CML| 25 35 kV/μs VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V Refresh Rate fr 1.1 Mbps Input Dynamic Supply Current per Channel8
IDDI (D) 0.10 mA/ Mbps
Output Dynamic Supply Current per Channel8
IDDO (D) 0.05 mA/ Mbps
1 The supply current values are for both channels combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11 for total IDD1 and IDD2 supply currents as a function of data rate for ADuM1200W and ADuM1201W channel configurations.
2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed.
8 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply current for a given data rate.
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 19 of 28 PACKAGE CHARACTERISTICS Table 8.
Parameter Symbol Min Typ Max Unit Test Conditions Resistance (Input-to-Output)1 RI-O 1012 Ω Capacitance (Input-to-Output)1 CI-O 1.0 pF f = 1 MHz Input Capacitance CI 4.0 pF IC Junction-to-Case Thermal Resistance, Side 1 θJCI 46 °C/W Thermocouple located at center of package underside IC Junction-to-Case Thermal Resistance, Side 2 θJCO 41 °C/W 1 The device is considered a 2-terminal device; Pin 1, Pin, 2, Pin 3, and Pin 4 are shorted together, and Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together.
REGULATORY INFORMATION
The ADuM1200/ADuM1201 and ADuM1200W/ADuM1201W are approved by the organizations listed in Table 9; refer to Table 14 and
the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.
Table 9.
UL CSA VDE Recognized Under 1577 Component Recognition Program1
Approved under CSA Component Acceptance Notice #5A; approval pending for ADuM1200W/
ADuM1201W automotive 125°C temperature grade
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-122
Single/Basic 2500 V rms Isolation Voltage Basic insulation per CSA 60950-1-03 and
IEC 60950-1, 400 V rms (566 peak) maximum working voltage Functional insulation per CSA 60950-1-03 and
IEC 60950-1, 800 V rms (1131 V peak) maximum
working voltage Reinforced insulation, 560 V peak
File E214100 File 205078 File 2471900-4880-0001
1 In accordance with UL 1577, each ADuM120x is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 μA). 2 In accordance with DIN V VDE V 0884-10, each ADuM120x is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 10.
Parameter Symbol Value Unit Conditions Rated Dielectric Insulation Voltage 2500 V rms 1 minute duration
Minimum External Air Gap (Clearance) L(I01) 4.90 min mm Measured from input terminals to output terminals, shortest distance through air Minimum External Tracking (Creepage) L(I02) 4.01 min mm Measured from input terminals to output terminals, shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 20 of 28
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 INSULATION CHARACTERISTICS
This isolator is suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. Note that the asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage.
Table 11.
Description
Conditions
Symbol
Characteristic
Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
I to IV
For Rated Mains Voltage ≤ 300 V rms
I to III
For Rated Mains Voltage ≤ 400 V rms
I to II
Climatic Classification
40/105/21
Pollution Degree per DIN VDE 0110, Table 1
2
Maximum Working Insulation Voltage
VIORM
560
V peak
Input-to-Output Test Voltage, Method B1
VIORM × 1.875 = VPR, 100% production test, tm = 1 second, partial discharge < 5 pC
VPR
1050
V peak
Input-to-Output Test Voltage, Method A
VIORM × 1.6 = VPR, tm = 60 seconds, partial discharge < 5 pC
VPR
After Environmental Tests Subgroup 1
896
V peak
After Input and/or Safety Test Subgroup 2 and Subgroup 3
VIORM × 1.2 = VPR, tm = 60 seconds, partial discharge < 5 pC
672
V peak
Highest Allowable Overvoltage
Transient overvoltage, tTR = 10 seconds
VTR
4000
V peak
Safety-Limiting Values
Maximum value allowed in the event of a failure (see Figure 3)
Case Temperature
TS
150
°C
Side 1 Current
IS1
160
mA
Side 2 Current
IS2
170
mA
Insulation Resistance at TS
VIO = 500 V
RS
>109
Ω
CASE TEMPERATURE (°C)SAFETY-LIMITING CURRENT (mA)002001801008060402050100150200SIDE #1SIDE #204642-003120140160
Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting Values on Case Temperature per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 12. Parameter
Rating
Operating Temperature (TA)
−40°C to +105°C
Operating Temperature (TA)2
−40°C to +125°C
Supply Voltages (VDD1, VDD2)1, 3
2.7 V to 5.5 V
Supply Voltages (VDD1, VDD2)23
3.0 V to 5.5 V
Input Signal Rise and Fall Times
1.0 ms
Does not apply to ADuM1200W and ADuM1201W automotive grade products. 2 Applies to
ADuM1200W and ADuM1201W automotive grade products. 3 All voltages are relative to their respective ground. See the DC Correctnes
s unity to externamagnetic fields.
and Magnetic Field Immunity section for information on imml
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 21 of 28
ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25°C, unless otherwise noted.
Table 13.
Parameter
Rating
Storage Temperature (TST)
−55°C to +150°C
Ambient Operating Temperature (TA)1
−40°C to +105°C
Ambient Operating Temperature (TA)2
−40°C to +125°C
Supply Voltages (VDD1, VDD2)3
−0.5 V to +7.0 V
Input Voltages (VIA, VIB)3, 4
−0.5 V to VDDI + 0.5 V
Output Voltages (VOA, VOB)3, 4
−0.5 V to VDDO + 0.5 V
Average Output Current per Pin (IO)5
−11 mA to +11 mA
Common-Mode Transients (CML, CMH)6
−100 kV/μs to +100 kV/μs
1 Does not apply to ADuM1200W and ADuM1200W automotive grade products.
2 Applies to ADuM1200W and ADuM1201W automotive grade products.
3 All voltages are relative to their respective ground.
4 VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively.
5 See for maximum rated current values for various temperatures.
Figure 3
6 Refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the absolute maximum ratings can cause latch-up or permanent damage.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Table 14. Maximum Continuous Working Voltage1
Parameter
Max
Unit
Constraint
AC Voltage, Bipolar Waveform
565
V peak
50-year minimum lifetime
AC Voltage, Unipolar Waveform
Functional Insulation
1131
V peak
Maximum approved working voltage per IEC 60950-1
Basic Insulation
560
V peak
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
DC Voltage
Functional Insulation
1131
V peak
Maximum approved working voltage per IEC 60950-1
Basic Insulation
560
V peak
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 22 of 28 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 8
2 7
3 6
4 5
TOP VIEW
(Not to Scale)
ADuM1200
04642-004
VDD1
VIA
VIB
GND1
VDD2
VOA
VOB
GND2
04642-005
1 8
2 7
3 6
4 5
TOP VIEW
(Not to Scale)
ADuM1201
VDD1
VOA
VIB
GND1
VDD2
VIA
VOB
GND2
Figure 4. ADuM1200 Pin Configuration Figure 5. ADuM1201 Pin Configuration
Table 15. ADuM1200 Pin Function Descriptions
Pin
No. Mnemonic Description 1 VDD1 Supply Voltage for Isolator Side 1. 2 VIA Logic Input A.
3 VIB Logic Input B.
4 GND1 Ground 1. Ground Reference for Isolator Side 1. 5 GND2 Ground 2. Ground Reference for Isolator Side 2.
6 VOB Logic Output B.
7 VOA Logic Output A.
8 VDD2 Supply Voltage for Isolator Side 2. Table 16. ADuM1201 Pin Function Descriptions
Pin
No. Mnemonic Description 1 VDD1 Supply Voltage for Isolator Side 1. 2 VOA Logic Output A.
3 VIB Logic Input B.
4 GND1 Ground 1. Ground Reference for Isolator Side 1. 5 GND2 Ground 2. Ground Reference for Isolator Side 2. 6 VOB Logic Output B.
7 VIA Logic Input A.
8 VDD2 Supply Voltage for Isolator Side 2. Table 17. ADuM1200 Truth Table (Positive Logic)
VIA Input VIB Input VDD1 State VDD2 State VOA Output VOB Output Notes H H Powered Powered H H
L L Powered Powered L L
H L Powered Powered H L
L H Powered Powered L H
X X Unpowered Powered H H Outputs return to the input state within
1 μs of VDDI power restoration. X X Powered Unpowered Indeterminate Indeterminate Outputs return to the input state within
1 μs of VDDO power restoration. Table 18. ADuM1201 Truth Table (Positive Logic)
VIA Input VIB Input VDD1 State VDD2 State VOA Output VOB Output Notes H H Powered Powered H H
L L Powered Powered L L
H L Powered Powered H L
L H Powered Powered L H
X X Unpowered Powered Indeterminate H Outputs return to the input state within
1 μs of VDDI power restoration. X X Powered Unpowered H Indeterminate Outputs return to the input state within
1 μs of VDDO power restoration.
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 23 of 28
04642-006
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 6. Typical Input Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation
04642-007DATA RATE (
Mbps)00102030
Figure 7. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (No Output Load)
04642-0 DATA RATE (Mbps)0102030
Figure 8. Typical Output Supply Current per Channel vs. Data Rate for 5 V and 3 V Operation (15 pF Output Load)
04642-009DATA RATE (
Mbps)CURRENT (mA)0015105201020305V3V
Figure 9. Typical ADuM1200 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation
04642-010DATA RATE (
Mbps)CURRENT (mA)0032141020305V3V
Figure 10. Typical ADuM1200 VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation
04642-011DATA RATE (
Mbps)CURRENT (mA)00628101020305V3V4
Figure 11. Typical ADuM1201 VDD1 or VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 24 of 28 APPLICATIONS INFORMATION
PCB LAYOUT The ADuM120x digital isolators require no external interface
circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins. The capacitor value should be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and
the input power supply pin should not exceed 20 mm. See the AN-1109 Application Note for board layout guidelines. PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output can differ from the propagation delay
to a logic high output.
INPUT (VIx)
OUTPUT (VOx)
tPLH tPHL
50%
50%
04642-012
Figure 12. Propagation Delay Parameters Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount that the propagation delay differs between channels within a
single ADuM120x component. Propagation delay skew refers to the maximum amount that the propagation delay differs between multiple ADuM120x
components operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input send narrow (~1 ns) pulses to the decoder via the transformer. The
decoder is bistable and is therefore either set or reset by the pulses,
indicating input logic transitions. In the absence of logic transi-
tions of more than ~1 μs at the input, a periodic set of refresh
pulses indicative of the correct input state is sent to ensure dc
correctness at the output. If the decoder receives no internal pulses for more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output
is forced to a default state (see Table 17 and Table 18) by the
watchdog timer circuit. The ADuM120x are extremely immune to external magnetic
fields. The limitation on the magnetic field immunity of the ADuM120x is set by the condition in which induced voltage in
the receiving coil of the transformer is sufficiently large enough to either falsely set or reset the decoder. The following analysis
defines the conditions under which this can occur. The 3 V
operating condition of the ADuM120x is examined because it represents the most susceptible mode of operation. The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, therefore establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (−dβ/dt)ΣΠrn
2; n = 1, 2, … , N
where: β is the magnetic flux density (gauss).
N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm).
Given the geometry of the receiving coil in the ADuM120x and
an imposed requirement that the induced voltage be 50% at
most of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated, as shown in Figure 13.
MAGNETIC FIELD FREQUENCY (Hz)
100
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
0.001
1M
10
0.01
1k 10k 10M
0.1
1
100M 100k
04642-013
Figure 13. Maximum Allowable External Magnetic Flux Density
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 25 of 28
For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (and has the worst-case polarity), it reduces the received pulse from >1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder.
The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuM120x transformers. Figure 14 expresses these allowable current magnitudes as a function of frequency for selected distances. As seen, the ADuM120x are extremely immune and can be affected only by extremely large currents operating very close to the component at a high frequency. For the 1 MHz example, a 0.5 kA current would have to be placed 5 mm away from the ADuM120x to affect the operation of the component.
MAGNETIC FIELD FREQUENCY (Hz)MAXIMUM ALLOWABLE CURRENT (kA)10001001010.10.011k10k100M100k1M10MDISTANCE = 5mmDISTANCE = 1mDISTANCE = 100mm04642-014
Figure 14. Maximum Allowable Current for Various Current-to-ADuM120x Spacings
Note that, at combinations of strong magnetic fields and high frequencies, any loops formed by PCB traces can induce suffi-ciently large error voltages to trigger the threshold of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.
POWER CONSUMPTION
The supply current at a given channel of the ADuM120x isolator is a function of the supply voltage, the data rate of the channel, and the output load of the channel.
For each input channel, the supply current is given by
IDDI = IDDI (Q) f ≤ 0.5fr
IDDI = IDDI (D) × (2f − fr) + IDDI (Q) f > 0.5fr
For each output channel, the supply current is given by
IDDO = IDDO (Q) f ≤ 0.5fr
IDDO = (IDDO (D) + (0.5 × 10−3) × CLVDDO) × (2f − fr) + IDDO (Q) f > 0.5fr
where: IDDI (D), IDDO (D) are the input and output dynamic supply currents per channel (mA/Mbps). CL is the output load capacitance (pF). VDDO is the output supply voltage (V). f is the input logic signal frequency (MHz, half of the input data rate, NRZ signaling). fr is the input stage refresh rate (Mbps). IDDI (Q), IDDO (Q) are the specified input and output quiescent supply currents (mA).
To calculate the total IDD1 and IDD2 supply currents, the supply currents for each input and output channel corresponding to IDD1 and IDD2 are calculated and totaled. Figure 6 and Figure 7 provide per-channel supply currents as a function of data rate for an unloaded output condition. Figure 8 provides per-channel supply current as a function of data rate for a 15 pF output condition. Figure 9 through Figure 11 provide total VDD1 and VDD2 supply current as a function of data rate for ADuM1200 and ADuM1201 channel configurations.
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 26 of 28
In the case of unipolar ac or dc voltage, the stress on the insu-lation is significantly lower, which allows operation at higher working voltages yet still achieves a 50-year service life. The working voltages listed in Table 14 can be applied while main-taining the 50-year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage cases. Any cross- insulation voltage waveform that does not conform to Figure 16 or Figure 17 is to be treated as a bipolar ac waveform, and its peak voltage is to be limited to the 50-year lifetime voltage value listed in Table 14.
INSULATION LIFETIME
All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insu-lation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM120x.
Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Accel-eration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 14 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum CSA/VDE approved working volt-ages. In many cases, the approved working voltage is higher than the 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases.
Note that the voltage presented in Figure 16 is shown as sinu-soidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V. 0VRATED PEAK VOLTAGE04642-021
Figure 15. Bipolar AC Waveform
The insulation lifetime of the ADuM120x depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 15, Figure 16, and Figure 17 illustrate these different isolation voltage waveforms, respectively.
0VRATED PEAK VOLTAGE04642-022
Figure 16. Unipolar AC Waveform
Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the Analog Devices recommended maximum working voltage.
0VRATED PEAK VOLTAGE04642-023
Figure 17. DC Waveform
Data Sheet ADuM1200/ADuM1201
Rev. I | Page 27 of 28 OUTLINE DIMENSIONS
CONTROLLINGDIMENSIONSAREINMILLIMETERS;INCHDIMENSIONS
(IN PARENTHESES)AREROUNDED-OFFMILLIMETEREQUIVALENTSFOR
REFERENCEONLYANDARENOTAPPROPRIATEFORUSEINDESIGN.
COMPLIANTTOJEDECSTANDARDSMS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25(0.0098)
0.10(0.0040)
1 4
8 5
5.00 (0.1968)
4.80 (0.1890)
4.00(0.1574)
3.80(0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51(0.0201)
0.31(0.0122)
COPLANARITY
0.10
Figure 18. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1, 2
Number
of Inputs, VDD1 Side
Number
of Inputs,
VDD2 Side
Maximum
Data Rate (Mbps)
Maximum Propagation Delay, 5 V (ns) Maximum
Pulse Width Distortion (ns)
Temperature
Range Package
Option3
ADuM1200AR 2 0 1 150 40 −40°C to +105°C R-8
ADuM1200ARZ 2 0 1 150 40 −40°C to +105°C R-8
ADuM1200ARZ-RL7 2 0 1 150 40 −40°C to +105°C R-8
ADuM1200BR 2 0 10 50 3 −40°C to +105°C R-8
ADuM1200BR-RL7 2 0 10 50 3 −40°C to +105°C R-8
ADuM1200BRZ 2 0 10 50 3 −40°C to +105°C R-8
ADuM1200BRZ-RL7 2 0 10 50 3 −40°C to +105°C R-8
ADuM1200CR 2 0 25 45 3 −40°C to +105°C R-8
ADuM1200CR-RL7 2 0 25 45 3 −40°C to +105°C R-8
ADuM1200CRZ 2 0 25 45 3 −40°C to +105°C R-8
ADuM1200CRZ-RL7 2 0 25 45 3 −40°C to +105°C R-8
ADuM1200WSRZ 2 0 1 150 40 −40°C to +125°C R-8
ADuM1200WSRZ-RL7 2 0 1 150 40 −40°C to +125°C R-8
ADuM1200WTRZ 2 0 10 50 3 −40°C to +125°C R-8
ADuM1200WTRZ-RL7 2 0 10 50 3 −40°C to +125°C R-8
ADuM1200WURZ 2 0 25 45 3 −40°C to +125°C R-8
ADuM1200WURZ-RL7 2 0 25 45 3 −40°C to +125°C R-8
ADuM1201AR 1 1 1 150 40 −40°C to +105°C R-8
ADuM1201AR-RL7 1 1 1 150 40 −40°C to +105°C R-8
ADuM1201ARZ 1 1 1 150 40 −40°C to +105°C R-8
ADuM1201ARZ-RL7 1 1 1 150 40 −40°C to +105°C R-8
ADuM1201BR 1 1 10 50 3 −40°C to +105°C R-8
ADuM1201BR-RL7 1 1 10 50 3 −40°C to +105°C R-8
ADuM1201BRZ 1 1 10 50 3 −40°C to +105°C R-8
ADuM1201BRZ-RL7 1 1 10 50 3 −40°C to +105°C R-8
ADuM1201CR 1 1 25 45 3 −40°C to +105°C R-8
ADuM1201CRZ 1 1 25 45 3 −40°C to +105°C R-8
ADuM1201CRZ-RL7 1 1 25 45 3 −40°C to +105°C R-8
ADuM1200/ADuM1201 Data Sheet
Rev. I | Page 28 of 28 Model1, 2
Number
of Inputs, VDD1 Side
Number
of Inputs, VDD2 Side
Maximum
Data Rate (Mbps)
Maximum Propagation Delay, 5 V (ns) Maximum
Pulse Width Distortion (ns)
Temperature
Range Package
Option3
ADuM1201WSRZ 1 1 1 150 40 −40°C to +125°C R-8
ADuM1201WSRZ-RL7 1 1 1 150 40 −40°C to +125°C R-8
ADuM1201WTRZ 1 1 10 50 3 −40°C to +125°C R-8
ADuM1201WTRZ-RL7 1 1 10 50 3 −40°C to +125°C R-8
ADuM1201WURZ 1 1 25 45 3 −40°C to +125°C R-8
ADuM1201WURZ-RL7 1 1 25 45 3 −40°C to +125°C R-8
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 R-8 = 8-lead narrow-body SOIC_N. AUTOMOTIVE PRODUCTS
The ADuM1200W/ADuM1201W models are available with controlled manufacturing to support the quality and reliability requirements
of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for
use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and
to obtain the specific Automotive Reliability reports for these models. ©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04642-0-3/12(I)
High Precision
5 V Reference
AD586
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
Laser trimmed to high accuracy
5.000 V ±2.0 mV (M grade)
Trimmed temperature coefficient
2 ppm/°C max, 0°C to 70°C (M grade)
5 ppm/°C max, −40°C to +85°C (B and L grades)
10 ppm/°C max, −55°C to +125°C (T grade)
Low noise, 100 nV/√Hz
Noise reduction capability
Output trim capability
MIL-STD-883-compliant versions available
Industrial temperature range SOICs available
Output capable of sourcing or sinking 10 mA
GENERAL DESCRIPTION
The AD586 represents a major advance in state-of-the-art monolithic voltage references. Using a proprietary ion-implanted buried Zener diode and laser wafer trimming of high stability thin-film resistors, the AD586 provides outstanding perform-ance at low cost.
The AD586 offers much higher performance than most other 5 V references. Because the AD586 uses an industry-standard pinout, many systems can be upgraded instantly with the AD586.
The buried Zener approach to reference design provides lower noise and drift than band gap voltage references. The AD586 offers a noise reduction pin that can be used to further reduce the noise level generated by the buried Zener.
The AD586 is recommended for use as a reference for 8-, 10-, 12-, 14-, or 16-bit DACs that require an external precision reference. The device is also ideal for successive approximation or integrating ADCs with up to 14 bits of accuracy and, in general, can offer better performance than the standard on-chip references.
The AD586J, AD586K, AD586L, and AD586M are specified for operation from 0°C to 70°C; the AD586A and AD586B are specified for −40°C to +85°C operation; and the AD586S and AD586T are specified for −55°C to +125°C operation.
The AD586J, AD586K, AD586L, and AD586M are available in an 8-lead PDIP; the AD586J, AD586K, AD586L, AD586A, and AD586B are available in an 8-lead SOIC package; and the AD586J, AD586K, AD586L, AD586S, and AD586T are available in an 8-lead CERDIP package. A1RSRZ1RZ2RFRTRIAD586GNDVINNOISE REDUCTIONVOUTTRIMNOTES1.PINS 1, 3, AND 7 ARE INTERNAL TEST POINTS.MAKE NO CONNECTIONS TO THESE POINTS.6548200529-001
Figure 1.
PRODUCT HIGHLIGHTS
1. Laser trimming of both initial accuracy and temperature coefficients results in very low errors over temperature without the use of external components. The AD586M has a maximum deviation from 5.000 V of ±2.45 mV between 0°C and 70°C, and the AD586T guarantees ±7.5 mV maximum total error between −55°C and +125°C.
2. For applications requiring higher precision, an optional fine-trim connection is provided.
3. Any system using an industry-standard pinout reference can be upgraded instantly with the AD586.
4. Output noise of the AD586 is very low, typically 4 μV p-p. A noise reduction pin is provided for additional noise filtering using an external capacitor.
5. The AD586 is available in versions compliant with MIL-STD-883. Refer to the Analog Devices Military Products Databook or the current AD586/883B data sheet for detailed specifications.
AD586
Rev. G | Page 2 of 16
TABLE OF CONTENTS
Specifications.....................................................................................3
AD586J, AD586K/AD586A, AD586L/AD586B.......................3
AD586M, AD586S, AD586T.......................................................4
Absolute Maximum Ratings............................................................5
ESD Caution..................................................................................5
Pin Configurations and Function Descriptions...........................6
Theory of Operation........................................................................7
Applying the AD586.....................................................................7
Noise Performance and Reduction............................................7
Turn-on Time................................................................................8
Dynamic Performance.................................................................8
Load Regulation............................................................................9
Temperature Performance............................................................9
Negative Reference Voltage from an AD586...........................10
Using the AD586 with Converters...........................................10
5 V Reference with Multiplying CMOS DACs or ADCs......11
Stacked Precision References for Multiple Voltages..............11
Precision Current Source..........................................................11
Precision High Current Supply................................................11
Outline Dimensions.......................................................................13
Ordering Guide..........................................................................14
REVISION HISTORY
3/05—Rev. F to Rev. G Updated Format..................................................................Universal Split Specifications Table into Table 1 and Table 2.......................3 Changes to Table 1............................................................................3 Added Figure 2 and Figure 4...........................................................6 Updated Outline Dimensions.......................................................13 Changes to Ordering Guide..........................................................14
1/04—Rev. E to Rev. F Changes to ORDERING GUIDE...................................................3
7/03—Rev. D to Rev. E Removed AD586J CHIPS..................................................Universal Updated ORDERING GUIDE........................................................3 Change to Figure 3...........................................................................4 Updated Figure 12............................................................................7 Updated OUTLINE DIMENSIONS..............................................9
4/01—Rev. C to Rev. D Changed Figure 10 to Table 1 (Maximum Output Change in mV)...............................................6
11/95—Revision 0: Initial Version
AD586
Rev. G | Page 3 of 16
SPECIFICATIONS
AD586J, AD586K/AD586A, AD586L/AD586B
@ TA = 25°C, VIN = 15 V, unless otherwise noted. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All minimum and maximum specifications are guaranteed, although only those shown in boldface are tested on all production units, unless otherwise specified.
Table 1.
AD586J
AD586K/AD586A
AD586L/AD586B
Parameter
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
OUTPUT VOLTAGE
4.980
5.020
4.995
5.005
4.9975
5.0025
V
OUTPUT VOLTAGE DRIFT1
0°C to 70°C
25
15
5
ppm/°C
−55°C to +125°C
ppm/°C
GAIN ADJUSTMENT
+6
+6
+6
%
−2
−2
−2
%
LINE REGULATION1
10.8 V < + VIN < 36 V
TMIN to TMAX
±100
±100
±100
μV/V
11.4 V < +VIN < 36 V
TMIN to TMAX
μV/V
LOAD REGULATION1
Sourcing 0 mA < IOUT < 10 mA
25°C
100
100
100
μV/mA
TMIN to TMAX
100
100
100
μV/mA
Sinking −10 mA < IOUT < 0 mA
25°C
400
400
400
μV/mA
QUIESCENT CURRENT
2
3
2
3
2
3
mA
POWER CONSUMPTION
30
30
30
mW
OUTPUT NOISE
0.1 Hz to 10 Hz
4
4
4
μV p-p
Spectral Density, 100 Hz
100
100
100
nV/√Hz
LONG-TERM STABILITY
15
15
15
ppm/1000 hr
SHORT-CIRCUIT CURRENT-TO-GROUND
45
60
45
60
45
60
mA
TEMPERATURE RANGE
Specified Performance2
0
70
0
−40
(K grade)
(A grade)
70
+85
0
−40
(L grade)
(B grade)
70
+85
°C
°C
Operating Performance3
−40
+85
−40
+85
−40
+85
°C
1 Maximum output voltage drift is guaranteed for all packages and grades. CERDIP packaged parts are also 100°C production tested.
2 Lower row shows specified performance for A and B grades.
3 The operating temperature range is defined as the temperature extremes at which the device will still function. Parts may deviate from their specified performance outside their specified temperature range.
AD586
Rev. G | Page 4 of 16
AD586M, AD586S, AD586T
@ TA = 25°C, VIN = 15 V, unless otherwise noted. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All minimum and maximum specifications are guaranteed, although only those shown in boldface are tested on all production units, unless otherwise specified.
Table 2.
AD586M
AD586S
AD586T
Parameter
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
OUTPUT VOLTAGE
4.998
5.002
4.990
5.010
4.9975
5.0025
V
OUTPUT VOLTAGE DRIFT1
0°C to 70°C
2
ppm/°C
−55°C to +125°C
20
10
ppm/°C
GAIN ADJUSTMENT
+6
+6
+6
%
−2
−2
−2
%
LINE REGULATION1
10.8 V < +VIN < 36 V
TMIN to TMAX
±100
μV/V
11.4 V < +VIN < 36 V
TMIN to TMAX
±150
±150
μV/V
LOAD REGULATION1
Sourcing 0 mA < IOUT < 10 mA
25°C
100
150
150
μV/mA
TMIN to TMAX
100
150
150
μV/mA
Sinking −10 mA < IOUT < 0 mA
25°C
400
400
400
μV/mA
QUIESCENT CURRENT
2
3
2
3
2
3
mA
POWER CONSUMPTION
30
30
30
mW
OUTPUT NOISE
0.1 Hz to 10 Hz
4
4
4
μV p-p
Spectral Density, 100 Hz
100
100
100
nV/√Hz
LONG-TERM STABILITY
15
15
15
ppm/1000 hr
SHORT-CIRCUIT CURRENT-TO-GROUND
45
60
45
60
45
60
mA
TEMPERATURE RANGE
Specified Performance2
0
70
−55
+125
−55
+125
°C
Operating Performance3
−40
+85
−55
+125
−55
+125
°C
1 Maximum output voltage drift is guaranteed for all packages and grades. CERDIP packaged parts are also 100°C production tested.
2 Lower row shows specified performance for A and B grades.
3 The operating temperature range is defined as the temperature extremes at which the device will still function. Parts may deviate from their specified performance outside their specified temperature range.
AD586
Rev. G | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
VIN to Ground
36 V
Power Dissipation (25°C)
500 mW
Storage Temperature
−65°C to +150°C
Lead Temperature (Soldering, 10 sec)
300°C
Package Thermal Resistance
θJC
22°C/W
θJA
110°C/W
Output Protection
Output safe for indefinite short to ground or VIN.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
AD586
Rev. G | Page 6 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1TP DENOTES FACTORY TEST POINT.NO CONNECTIONS, EXCEPT DUMMY PCB PAD,SHOULD BE MADE TO THESE POINTS.TP11VIN2TP13GND4NOISEREDUCTION8TP17VOUT6TRIM5AD586TOP VIEW(Not to Scale)00529-002
Figure 2. Pin Configuration (N-8)
1TP DENOTES FACTORY TEST POINT.NO CONNECTIONS, EXCEPT DUMMY PCB PAD,SHOULD BE MADE TO THESE POINTS.00529-003TP11VIN2TP13GND4NOISEREDUCTION8TP17VOUT6TRIM5AD586TOP VIEW(Not to Scale)
Figure 3. Pin Configuration (Q-8)
1TP DENOTES FACTORY TEST POINT.NO CONNECTIONS, EXCEPT DUMMY PCB PAD,SHOULD BE MADE TO THESE POINTS.00529-004TP11VIN2TP13GND4NOISEREDUCTION8TP17VOUT6TRIM5AD586TOP VIEW(Not to Scale)
Figure 4. Pin Configuration (R-8)
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
TP1
Factory Trim Pad (No Connect).
2
VIN
Input Voltage.
3
TP1
Factory Trim Pad (No Connect).
4
GND
Ground.
5
TRIM
Optional External Fine Trim. See the Applying the AD586 section.
6
VOUT
Output Voltage.
7
TP1
Factory Trim Pad (No Connect).
8
NOICE REDUCTION
Optional Noise Reduction Filter with External 1μF Capacitor to Ground.
AD586
Rev. G | Page 7 of 16
THEORY OF OPERATION
The AD586 consists of a proprietary buried Zener diode refer-ence, an amplifier to buffer the output, and several high stability thin-film resistors, as shown in the block diagram in Figure 5. This design results in a high precision monolithic 5 V output reference with initial offset of 2.0 mV or less. The temperature compensation circuitry provides the device with a temperature coefficient of under 2 ppm/°C.
Using the bias compensation resistor between the Zener output and the noninverting input to the amplifier, a capacitor can be added at the noise reduction pin (Pin 8) to form a low-pass filter and reduce the noise contribution of the Zener to the circuit. A1RSRZ1RZ2RFRTRIAD586GNDVINNOISE REDUCTIONVOUTTRIMNOTES1.PINS 1, 3, AND 7 ARE INTERNAL TEST POINTS.MAKE NO CONNECTIONS TO THESE POINTS.6548200529-001
Figure 5. Functional Block Diagram
APPLYING THE AD586
The AD586 is simple to use in virtually all precision reference applications. When power is applied to Pin 2 and Pin 4 is grounded, Pin 6 provides a 5 V output. No external components are required; the degree of desired absolute accuracy is achieved simply by selecting the required device grade. The AD586 requires less than 3 mA quiescent current from an operating supp