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Farnell Element 14 :

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Everything You Need To Know About Arduino

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Tutorial 01 for Arduino: Getting Acquainted with Arduino

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The Cube® 3D Printer

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What's easier- DIY Dentistry or our new our website features?

 

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Ben Heck's Getting Started with the BeagleBone Black Trailer

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Ben Heck's Home-Brew Solder Reflow Oven 2.0 Trailer

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Get Started with Pi Episode 3 - Online with Raspberry Pi

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Discover Simulink Promo -- Exclusive element14 Webinar

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Ben Heck's TV Proximity Sensor Trailer

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Ben Heck's PlayStation 4 Teardown Trailer

See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…

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Get Started with Pi Episode 4 - Your First Raspberry Pi Project

Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.

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Ben Heck Anti-Pickpocket Wallet Trailer

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Molex Earphones - The 14 Holiday Products of Newark element14 Promotion

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Tripp Lite Surge Protector - The 14 Holiday Products of Newark element14 Promotion

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Microchip ChipKIT Pi - The 14 Holiday Products of Newark element14 Promotion

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Beagle Bone Black - The 14 Holiday Products of Newark element14 Promotion

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3M E26, LED Lamps - The 14 Holiday Products of Newark element14 Promotion

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3M Colored Duct Tape - The 14 Holiday Products of Newark element14 Promotion

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Tenma Soldering Station - The 14 Holiday Products of Newark element14 Promotion

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Duratool Screwdriver Kit - The 14 Holiday Products of Newark element14 Promotion

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Cubify 3D Cube - The 14 Holiday Products of Newark element14 Promotion

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Bud Boardganizer - The 14 Holiday Products of Newark element14 Promotion

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Raspberry Pi Starter Kit - The 14 Holiday Products of Newark element14 Promotion

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Fluke 323 True-rms Clamp Meter - The 14 Holiday Products of Newark element14 Promotion

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Dymo RHINO 6000 Label Printer - The 14 Holiday Products of Newark element14 Promotion

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3M LED Advanced Lights A-19 - The 14 Holiday Products of Newark element14 Promotion

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Innovative LPS Resistor Features Very High Power Dissipation

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Charge Injection Evaluation Board for DG508B Multiplexer Demo

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Ben Heck The Great Glue Gun Trailer Part 2

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Introducing element14 TV

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Ben Heck Time to Meet Your Maker Trailer

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Détecteur de composants

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Recherche intégrée

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Ben Builds an Accessibility Guitar Trailer Part 1

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Ben Builds an Accessibility Guitar - Part 2 Trailer

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PiFace Control and Display Introduction

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Flashmob Farnell

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Express Yourself in 3D with Cube 3D Printers from Newark element14

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Farnell YouTube Channel Move

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Farnell: Design with the best

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French Farnell Quest

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Altera - 3 Ways to Quickly Adapt to Changing Ethernet Protocols

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Cy-Net3 Network Module

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MC AT - Professional and Precision Series Thin Film Chip Resistors

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Solderless LED Connector

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PSA-T Series Spectrum Analyser: PSA1301T/ PSA2701T

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3-axis Universal Motion Controller For Stepper Motor Drivers: TMC429

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Voltage Level Translation

Puce électronique / Microchip :

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Microchip - 8-bit Wireless Development Kit

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 2 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 3 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 1 of 3

Sans fil - Wireless :

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Microchip - 8-bit Wireless Development Kit

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Wireless Power Solutions - Wurth Electronics, Texas Instruments, CadSoft and element14

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Analog Devices - Remote Water Quality Monitoring via a Low Power, Wireless Network

Texas instrument :

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Texas Instruments - Automotive LED Headlights

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Texas Instruments - Digital Power Solutions

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Texas Instruments - Industrial Sensor Solutions

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Texas Instruments - Wireless Pen Input Demo (Mobile World Congress)

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Texas Instruments - Industrial Automation System Components

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Texas Instruments - TMS320C66x - Industry's first 10-GHz fixed/floating point DSP

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Texas Instruments - TMS320C66x KeyStone Multicore Architecture

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Texas Instruments - Industrial Interfaces

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Texas Instruments - Concerto™ MCUs - Connectivity without compromise

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Texas Instruments - Stellaris Robot Chronos

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Texas Instruments - DRV8412-C2-KIT, Brushed DC and Stepper Motor Control Kit

Ordinateurs :

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Ask Ben Heck - Connect Raspberry Pi to Car Computer

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Ben's Portable Raspberry Pi Computer Trailer

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Ben's Raspberry Pi Portable Computer Trailer 2

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Ben Heck's Pocket Computer Trailer

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Ask Ben Heck - Atari Computer

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Ask Ben Heck - Using Computer Monitors for External Displays

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Raspberry Pi Partnership with BBC Computer Literacy Project - Answers from co-founder Eben Upton

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Installing RaspBMC on your Raspberry Pi with the Farnell element14 Accessory kit

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Raspberry Pi Served - Joey Hudy

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Happy Birthday Raspberry Pi

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Raspberry Pi board B product overview

Logiciels :

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Ask Ben Heck - Best Opensource or Free CAD Software

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Tektronix FPGAView™ software makes debugging of FPGAs faster than ever!

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Ask Ben Heck - Best Open-Source Schematic Capture and PCB Layout Software

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Introduction to Cadsoft EAGLE PCB Design Software in Chinese

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Altera - Developing Software for Embedded Systems on FPGAs

Tutoriels :

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Ben Heck The Great Glue Gun Trailer Part 1

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the knode tutorial - element14

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Ben's Autodesk 123D Tutorial Trailer

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Ben's CadSoft EAGLE Tutorial Trailer

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Ben Heck's Soldering Tutorial Trailer

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Ben Heck's AVR Dev Board tutorial

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Ben Heck's Pinball Tutorial Trailer

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Ben Heck's Interface Tutorial Trailer

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First Stage with Python and PiFace Digital

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Cypress - Getting Started with PSoC® 3 - Part 2

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Energy Harvesting Challenge

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New Features of CadSoft EAGLE v6

Autres documentations :

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a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 1 of 18 a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 2 of 18 Table of Contents SUMMARY...................................................................................................................... 3 1 DEAD TIME EFFECTS AND THEIR COMPENSATION .......................................... 3 2 IMPLEMENTATION OF THE FEED FORWARD DEAD TIME COMPENSATION .. 5 2.1 Using the dt_comp routines ...........................................................................................................................5 2.2 Using the dt_comp routine.............................................................................................................................6 2.3 The program code...........................................................................................................................................7 3 EXAMPLE: TESTING THE VALIDITY OF THE FEED FORWARD DEAD TIME COMPENSATION........................................................................................................... 7 3.1 The construction of an inverter .....................................................................................................................7 3.2 The software program used to test the feed forward dead time compensation.........................................8 3.3 The main include file: main.h ......................................................................................................................12 3.4 The program offset.dsp and its header offset.h..........................................................................................12 3.5 Experimental results.....................................................................................................................................16 4 REFERENCES ....................................................................................................... 18 a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 3 of 18 Summary Due to the finite switching time, in order to prevent the appearance of short circuits, the power devices of an inverter must be commanded introducing a delay between their active times. This delay, called dead time because in this period no power device is active, introduces small voltage errors, which are sufficient to produce distorted motor currents, oscillations of the motor torque and therefore even the motor controllability may be lost [1]. This paper presents one method to compensate the effects of the dead time, the experimental hardware on which this method was tested and the assembly program associated with it. 1 Dead Time effects and their compensation Consider a voltage inverter with a motor connected at its output terminals (Figure 1). d V T1 T 2 T 3 T 4 T 5 T 6 D1 D2 D4 D6 D3 D5 0 1 ≥ s i 1 v Figure 1: Voltage source inverter The effects of the dead time may be examined by considering only the first phase of the inverter. On this phase it is desired to obtain the reference PWM signal * 1 v presented in Figure 2a. The signals used to command the power devices are assumed to be active LOW, which means that when they are LOW, the power devices conduct (Figures 2b and 2c). The output signal obtained at the motor terminal depends on the sense of the current flowing in this phase: In the case of the current flowing from inverter to the motor (assumed positive sense), when T2 conducts, the phase terminal is linked to the GND and the voltage 1 v is 0. During the dead time period, when both power devices are turned OFF, the current continues to flow into the motor using the reverse recovery diode D2, so 1 v will continue to be 0. When the upper power device T1 conducts, the phase terminal is connected to d V and 1 v is equal to d V . During the second half cycle, the phenomenon repeats itself a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 4 of 18 symmetrically. The final behaviour of 1 v is presented in Figure 2d. It may be observed that the average value of 1 v is less than the reference value by an amount determined by the dead time: d s V T DT v = v − ⋅ * 1 1 (1) DT DT 2 DT 2 s T * 1 v T1 T 2 0 1 1 ≥ s i v when 0 1 1 < s i v when a) b) c) d) e) d V d V * 1 T Figure 2: The influence of the dead time over the output phase voltage In the case of the current flowing from the motor to the inverter, when T2 conducts, the phase terminal is linked to the GND and the voltage 1 v is 0. During the dead time period, the current continues to flow from the motor using the reverse recovery diode D1, so 1 v will become equal to d V . When the upper power device T1 conducts, the phase terminal is connected to d V and 1 v will continue to be equal to d V . During the second half, the phenomenon repeats itself symmetrically. The final behaviour of 1 v is presented in Figure 2e. It may be observed that the average value of 1 v is greater than the reference value by an amount determined by the dead time: a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 5 of 18 d s V T DT v = v + ⋅ * 1 1 (2) Equations (1) and (2) provide the first method to compensate for the dead time: the feed-forward compensation. In relation of the current sense, the inverter phase will be commanded with a reference voltage ** 1 v such that the voltage 1 v at the inverter terminal will become equal with the reference voltage * 1 v : d s V T DT v = v + ⋅ * 1 ** 1 when i ≥ 0 (3) d s V T DT v = v − ⋅ * 1 ** 1 when i < 0 . These expressions mean that when the phase current is positive, the duty cycle * 1 T correspondent to * 1 v has to be increased by the dead time and when the phase current is negative, the duty cycle has to be decreased by the dead time. The only drawback of this method appears when the current changes its sign, because this moment cannot be foreseen. It is easily seen that when the sign is not correctly applied, an error of two times the dead time is introduced. Another method to compensate the dead time is the following: The actual inverter voltages are measured on every phase. The compensation is done adding to the reference phase voltage * 1 v a term proportional to the voltage error on that phase: ( 1) ( 1) [ ( ) ( )] 1 * 1 * 1 ** 1 v k + = v k + + K ⋅ v k − v k (4) where: - ** ( 1) 1 v k + is the voltage which will be commanded on the first inverter phase; - * ( 1) 1 v k + is the reference voltage which would have been commanded if the dead time compensation had not been considered; -K is the gain of the compensator, usually less than or equal to 1; - * ( ) 1 v k is the reference voltage which would have been commanded during the previous PWM cycle if the dead time compensation had not been considered; - ( ) 1 v k is the inverter phase voltage measured during the previous PWM cycle. The drawback of this method is that all the inverter phase voltages have to be measured. It is possible to measure only two inverter phases if the PWM modulation is space vector type or sinusoidal. 2 Implementation of the feed forward dead time compensation 2.1 Using the dt_comp routines The routines are developed as an easy-to-use library, which has to be linked to the user’s application. The library consists of two files. The file “dt_comp.dsp” contains the assembly code of the subroutines. The block has to be compiled and then linked to an application. The user has to include the header file dt_comp.h, which provides the function-like calls to the subroutines. The example file in Section 3 will demonstrate the usage of all the routines. a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 6 of 18 Operation Usage Compute On-times compensating the dead time DeadTime_Comp(StatorCurrent_struct, Dutycycles_struct) Table 1 Implemented routine The input vector StatorCurrents_struct consists of three elements, the three inverter phase currents. Because their sum is always zero, only two of them need to be measured. They have to be scaled because the DSP uses fixed point formats. The scaling factor is 2⋅ Imax , where max I represents the maximum current which may be placed at the input pin of the A/D converter. The 2 factor is used to prevent overflows when the currents are used in arithmetical operations. The vector Dutycycles_struct is an input and also an output: It represents the duty cycles for each phase, previously computed by the PWM modulator. After the compensation, they represent the duty cycles effectively commanded to the inverter. Their values have to be between 0 and PWMTM, the number which controls the PWM switching frequency. DeadTime_comp represents a macro, which must be introduced into the program code if the dead time compensation is desired. The format of inputs and outputs are explained in more detail in the next section. The routines do not require any configuration constants from the main include-file “main.h” that comes with every application note. For more information about the general structure of the application notes and including libraries into user applications refer to the Library Documentation File. Section 2.2 shows an example of usage of this library. In the following sections each routine is explained in detail with the relevant segments of code which is found in either “dt_comp.h” or “dt_comp.dsp”. For more information see the comments in those files. 2.2 Using the dt_comp routine The macro listed in the Table 1 is based on a subroutine called DeadTime_Comp_. It is described in detail in the next section. The following table gives an overview of what DSP registers are used in this macro: Macro Input1 and modified DAG registers Output2 Modified core registers DeadTime_Comp I1 = ^ StatorCurrents_struct; M1, M2 = 1; L1, L2 = 0; I2 = ^ Dutycycles_struct; M3 = 0; N/A AX0, AY0, AY1, MR, AR Table2. DSP core registers used in the macro This macro has to be placed in the main program after the PWM reference duty cycles are computed, but prior to the program that saves them into the duty cycle registers PWMCHA, PWMCHB, PWMCHC. 1 ^vector stands for ‘address of vector’. 2 N/A: The output values are stored in the output vector in the Data memory. No DSP core register is used. a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 7 of 18 2.3 The program code The following code contained in the file dt_comp.dsp describes the routine DeadTime_Comp_ mentioned in the previous section. The routine is organised as a loop managed by the loop counter cntr. At each iteration, one phase current from the buffer StatorCurrents_struct is tested and the compensation is done function of its sign. In the end, the new duty cycle number is tested to ensure it is positive and less than the maximum admissible value, PWMTM. The last instruction saves the number back into the buffer Dutycycles_struct. DeadTime_Comp_: AY0 = DM(PWMDT); { dead time normalized } AY1 = dm(PWMTM); CNTR = 3; do dead_loop until ce; ax0 = DM(I1, M1); { ax0 = Isk, k=1,2,3 } mr1 = DM(I2, M3); { load Ta, Tb, Tc } AR = MR1 + AY0; none = pass ax0; {chek sign of the currents } IF LT AR = MR1 - AY0; none = pass AR; if lt AR = PASS 0; { no negative values admitted} af = AR - AY1; if gt ar = pass ay1; { protection against overflows} dead_loop: DM(I2, M2) = ar; rts; 3 Example: Testing the validity of the feed forward dead time compensation 3.1 The construction of the inverter The proposed compensation method was implemented on the ADMC331 Processor Board mounted on an ADMC Connector Board. As inverter power part was used an evaluation platform produced by International Rectifier, IRPT2056D Driver-Plus Board. It is a three phase 230VAC 3HP board and it integrates all the processing components needed for a 3 HP motor drive. It is equipped with an IRPT2056A IGBT power module and an IR2133J driver. The Analog Devices’ ADMC PWM isolation board linked the Connector Board to the Power Board. This board produces an electric isolation between the digital part and the inverter power part and also inverts the signals used to drive the power devices (74HC240). Because the signals used by the driver IR2133J are active LOW and because of the inverting line driver HC240, the PWM outputs of the ADMC331 are set to be active HIGH. Therefore the jumper JP51 is in position 1-2. 1 See the ADMC331 Processor Board manual, Motion Control Group, Analog Devices, 1998 a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 8 of 18 The inverter is driving an induction motor with the following characteristics: .13HP, 230V, 60Hz, 1725rpm, produced by Baldor. Because the power part is supplied with 110V, the maximum frequency the motor may be run in the constant torque regime is: c f 3 110 2 60 3 230 2 ⋅ = ⋅ f Hz c 28.7 230 110 60 = ⋅ = Because the compensation needs the value of the inverter phase currents, two of them were sensed using current transducers HA 10-NP produced by LEM. They are capable to measure up to 20A and this value is used to scale down the measured values: I 20A max = . Also, an operational amplifier LM348 is used to obtain the signal into the range of A/D converter of ADMC331: 0.3V÷3.5V. On the ADMC331 Processor Board there are 5KHz filters that have an anti-aliasing role. A block structure of the inverter is presented in Figure 3. ADMCConnector Board ADMC331 Processor Board IRPT2056D Driver Plus Board ADMC PWM Isolation Board .13HP Induction Motor 2xHP10-NP s1 I s 2 I Figure 3. Inverter Block structure 3.2 The software program used to test the feed forward dead time compensation The purpose of this program is to demonstrate the improvement offered by the feed forward dead time compensation. It reads two motor currents, commands the motor to run at 14Hz, half of the cut frequency c f and compensates for the dead time. The file main.dsp contains the root program. The batch file build.bat compiles every file of the project, links them together and builds the executable file main.exe. It may be applied either within DOS prompt or clicking on it from Windows Explorer. Main.exe may be run on the Motion Control Debugger. A brief description of the program will be given in the following: Start of code - declaring start location in program memory .MODULE/RAM/SEG=USER_PM1/ABS=0x30 Main_Program; a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 9 of 18 Next, the general systems constants and PWM configuration constants (main.h – see the next section) are included. Also included are the PWM library2, the DAC interface3 and the space vector modulation4 module definitions. The header file offset.h declares some macros used to measure the offset introduced by the current transducers and autocal.h declares the macros used to calibrate the ADMC331 A/D converter. {*************************************************************************************** * Include General System Parameters and Libraries * ***************************************************************************************} #include ; #include ; #include ; #include ; #include ; #include ; #include ; #include ; #include ; { Application Specific Module } #include ; #include ; #include ; Constants used in this program {*************************************************************************************** * Constants Defined in the Module * ***************************************************************************************} .CONST CUT_FREQ = 28; {the cutting frequency of the tested motor} .CONST Delta = 32768*2*CUT_FREQ/PWM_freq; {the increment of the angle} .CONST TwoPiOverThree = 0xffff / 3; { Hex equivalent of 2pi/3 } .CONST ALLOFF = 0x3F; { Used to disable IGBTies into PWMSEG } Here is where all the vectors for the program are declared. The buffer StatorCurrents_struct represents the three stator currents. The PWM duty cycles are stored in the buffer Dutycycles_struct and they are initialised with 0.It may be seen that the variables which identify the current offsets, Is1Offset and Is2Offset are declared circular because programming becomes easier. The average of the readings is computed on 32bit precision, so every buffer consists of 2 words. {*************************************************************************************** * Local Variables Defined in this Module * ***************************************************************************************} .VAR/DM/RAM/SEG=USER_DM AD_IN; { Volts/Hertz Command (0-1) } 2 see AN331-03: Three-Phase Sine-Wave Generation using the PWM Unit of the ADMC331 3 see AN331-06: Using the Serial Digital to Analog Converter of the ADMC Connector Board 4 see AN331-17: Implementing Space Vector Modulation with the ADMC331 a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 10 of 18 .INIT AD_IN : 0x3A0A; { Corresponds to 0.906/2 } .VAR/DM/RAM/SEG=USER_DM Theta; { Current angle } .INIT Theta : 0x0000; .VAR/DM/RAM/SEG=USER_DM Vdq_ref[2]; { rotor ref.frame } .VAR/DM/RAM/CIRC/SEG=USER_DM Valphabeta_ref[2]; { alphabeta frame } .VAR/RAM/DM/SEG=USER_DM OnTime_struct[1*4]; .INIT OnTime_struct: 0x0000, 0x0000, 0x0000, 0x0000; .VAR/RAM/DM/SEG=USER_DM Dutycycles_struct[1*3]; .INIT Dutycycles_struct: 0x0000, 0x0000, 0x0000; .VAR/DM/RAM/SEG=USER_DM VrefA; { Voltage demands } .VAR/DM/RAM/SEG=USER_DM VrefB; .VAR/DM/RAM/SEG=USER_DM VrefC; .INIT VrefA : 0x0000; .INIT VrefB : 0x0000; .INIT VrefC : 0x0000; .VAR/DM/RAM/SEG=USER_DM StatorCurrents_struct[1*3]; { stator currents } .VAR/DM/RAM/SEG=USER_DM Is1Offset[1]; .VAR/DM/RAM/SEG=USER_DM Is2Offset[1]; When the program begins, the PWM output signals are disabled. Then, the power module is reset and the PWM block is set up to generate interrupts every 100μsec (see main.h in the next section). There is initialised the D/A serial converter1 and there is unmasked the IRQ2 interrupt (the interrupt which manages the peripheral interrupts on ADMC331). The main loop just waits for interrupts. {********************************************************************************************} { Start of program code } {********************************************************************************************} Startup: Write_DM(PWMSEG, ALLOFF); { the IGBTies are disabled } IR_reset_PIO3; { Reset PowIRTrain Module } PWM_Init(PWMSYNC_ISR, PWMTRIP_ISR); DAC_Init; { Initialize the DAC-Module } IFC = 0x80; { Clear any pending IRQ2 inter. } ay0 = 0x200; { unmask irq2 interrupts. } ar = IMASK; ar = ar or ay0; 1 See ADMC Connector board user’s manual for further details a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 11 of 18 IMASK = ar; { IRQ2 ints fully enabled here } ADC_Init; { ADC Counter will Operate at the DSP CLKOUT Frequency } AutoCal_Init; { Initialize the Auto Calibration Routine } Offset_Init; { offset.h } Main: { Wait for interrupt to occur } jump Main; During the PWM_SYNC interrupt there are executed some routines which determine the internal offset of the A/D converter1, the external offsets introduced by the current transducers and the measurement of the currents. The successive routines generate three PWM signals of 14Hz obtained applying a continuous space vector modulation2. The dead time compensation is placed at the end of this block. Finally, the signals that will be provided to the D/A converter are computed. {********************************************************************************************} { PWM Interrupt Service Routine } {********************************************************************************************} PWMSYNC_ISR: Auto_Calibrate; { autocal.h } OffsetDetermination(ADC1, ADC2, Is1Offset, Is2Offset); { offset.h } ReadCurrents(Is1Offset, Is2Offset, StatorCurrents_struct, ADC1, ADC2); { offset.h } DAC_Pause; { Required only when I1, M1 or L1 is used} ar = DM (AD_IN ); mr = 0; {Clear mr } mr1 = dm(Theta); {Preload Theta} my0 = Delta; mr = mr + ar*my0 (SS); {Compute new angle & store} dm(Theta) = mr1; DM(Vdq_ref )= ar; {Set constant Vdq reference (AD_IN,0)} ar = pass 0; DM(Vdq_ref+1)= ar; refframe_Set_DAG_registers_for_transformations; refframe_Forward_Park_angle(Vdq_ref,Valphabeta_ref,mr1); {generate Vreference in alpha-beta frame} SVPWM_Calc_Ontimes(Valphabeta_ref, OnTime_struct); { use SVPWM routines} SVPWM_Calc_Dutycycles(OnTime_struct, Dutycycles_struct); DeadTime_Comp(StatorCurrents_struct, Dutycycles_struct); SVPWM_Update_DutyCycles(Dutycycles_struct); Dac_Resume; my0 = DM(Theta); DAC_Put(1, my0); { output on DACs, amplified by multiplication } mx0 = 0x8; my0 = DM(Dutycycles_struct ); mr = mx0 * my0 (SS); Dac_Put(2, mr0); my0 = DM(Dutycycles_struct+1); mr = mx0 * my0 (SS); Dac_Put(3, mr0); 1 See AN331-05: ADC-system on the ADMC331. 2 See AN331-17: Implementing Space Vector Modulation with ADMC331 a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 12 of 18 AX0 = dm(Dutycycles_struct); AY0 = Half_PWMTM; AR = AX0 - AY0; MY0 = 0x6523; {2/PWMTM=2/1296*2^15/2^6*2^15} MR = AR * MY0 (SS); SR = ASHIFT MR1 BY 6 (HI); SR = SR OR LSHIFT MR0 BY 6 (LO); DAC_Put(4, SR1); sr1 = DM(StatorCurrents_struct); sr = ASHIFT sr1 BY 5 (HI); DAC_Put(5,sr1); sr1 = DM(StatorCurrents_struct+1); sr = ASHIFT sr1 BY 5 (HI); DAC_Put(6, sr1); SR1 = DM(StatorCurrents_struct+2); sr = ASHIFT sr1 BY 5 (HI); DAC_Put(7, sr1); DAC_Update; RTI; 3.3 The main include file: main.h This file contains the definitions of ADMC331 constants, general-purpose macros, the configuration parameters of the system and library routines. It should be included in every application. For more information refer to the Library Documentation File. This file is mostly self-explaining. As already mentioned, the dt_comp library does not require any configuration parameters. The following table presents the parameters used to initialise the PWM block .It may be emphasized the dead time period set at 6μsec, a large value for the power devices used on the IRPT2056D. {********************************************************************************************} { Library: PWM block } { file : PWM331.dsp } { Application Note: Usage of the ADMC331 Pulse Width Modulation Block } .CONST PWM_freq = 10000; {Desired PWM switching frequency [Hz] } .CONST PWM_deadtime = 6000; {Desired deadtime [nsec] } .CONST PWM_minpulse = 1000; {Desired minimal pulse time [nsec] } .CONST PWM_syncpulse = 1540; {Desired sync pulse time [nsec] } .CONST Half_PWMTM = 1000*Cry_clock/PWM_freq/2; {********************************************************************************************} 3.4 The program offset.dsp and its header offset.h The current transducers introduce an offset that has to be evaluated, otherwise the sign of the currents would be determined with large errors. For this reason, at the beginning of the program, for a certain number of PWM cycles (in this particular case 128, but may be more or less depending on the system) there are measured the A/D channels corresponding to the two phase currents, V1 and V2. The average of all measurements constitutes the offset of that current. Of course, this procedure may be applied at every channel, if the signal is zero at the beginning of the program. The header file offset.h contains the macros that are used during this process. Generally, they call subroutines presented in the file offset.dsp. This file begins declaring the variables OffsetCounter, TempOffset1 and TempOffset2 used in these routines. a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 13 of 18 {*************************************************************************************** * Global Variables Defined in this Module * ***************************************************************************************} .VAR/DM/RAM/SEG=USER_DM OffsetCounter[1]; .GLOBAL OffsetCounter; .VAR/DM/RAM/CIRC/SEG=USER_DM TempOffset1[2]; .GLOBAL TempOffset1; .VAR/DM/RAM/CIRC/SEG=USER_DM TempOffset2[2]; .GLOBAL TempOffset2; The subroutine Offset_Init_ initialises the variables used to evaluate the offsets of the current transducers. OffsetCounter is set to 128 because the offsets are considered the average of 128 measurements. {************************************************************************************* * Type: Routine * * Call: Call Offset_Init_; * * This subroutine initializes the variables initializes variables used to * * evaluate the offsets of the current sensors * * Inputs : None * * Ouputs :None * * Modified: AR * ***************************************************************************************} Offset_Init_: AR = Offset_Average; dm(OffsetCounter) = AR; AR = 0x0; dm(TempOffset1) = AR; dm(TempOffset1+1) = AR; dm(TempOffset2) = AR; dm(TempOffset2+1) = AR; rts; The subroutine EvaluateIs_offset_ computes the average of the measurements of a particular A/D channel. {*************************************************************************************** * Type: Routine * * Call: Call EvaluateIs_offset_; * * This subroutine computes the average of the measurements of one A/D channel * * Inputs : AR = the lecture of the A/D channel * I1 = placed at the begining of the buffer which is averaged * * M1 = 0, L1 = 0 * * Ouputs :None * * Modified: AY1, AY0, AR, SR, AX0 * ***************************************************************************************} EvaluateIs_offset_: AY1 = dm(I1, M1); a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 14 of 18 AY0 = dm(I1, M1); AR = 0x4000 - AR; SR = ASHIFT AR BY -7 (HI); AR = SR0 + AY0; AX0 = AR, AR = SR1 + AY1 + C; dm(I1, M1) = AR; dm(I1, M1) = AX0; RTS; . In the file offset.h there is a macro Offset_Init that initialises the address generators at the current offsets buffers and then calls the subroutine Offset_Init_ from offset.dsp. {*************************************************************************************** * Type: Macro * * Call: Offset_Init; * * This macro initializes variables used to evaluate the offsets of the current sensors * * Input: none * * Output: none * * Modified: AR * ***************************************************************************************} .MACRO Offset_Init; CALL Offset_Init_; .ENDMACRO; The macro EvaluateIs_offset reads one A/D channel and computes the average offset of that channel calling the subroutine EvaluateIs_offset_. {*************************************************************************************** * Type: Macro * * Call: EvaluateIs_offset; * * Routine to compute the offset of one phase * * Input: %0=the targeted AD channel * * %1=the offset structure dedicated to the phase * * %1=most significant word * * %1+1=less significant word * * Output: Current Offset structure * * Modified: * ***************************************************************************************} .MACRO EvaluateIs_offset(%0, %1); ADC_Read(%0); I1 = ^%1; M1 = 1; L1 = %%1; a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 15 of 18 CALL EvaluateIs_offset_; .ENDMACRO; The macro OffsetDetermination computes the offsets of the both A/D channels that measure the phase currents. {*************************************************************************************** * Type: Macro * * Call: OffsetDetermination * * Routine to compute the offsets introduced by the current sensors * * Input: %0=ADC1 * * %1=ADC2 * * %2=Is1Offset * * %3=Is2Offset * * Output: Current Offsets structure * * Modified: * ***************************************************************************************} .MACRO OffsetDetermination(%0, %1, %2, %3); AY0 = dm(OffsetCounter); AR = AY0 - 1; IF LT JUMP SaveOffsets; dm(OffsetCounter) = AR; EvaluateIs_offset(%0, TempOffset1); EvaluateIs_offset(%1, TempOffset2); RTI; SaveOffsets: AF = AR + 1; IF NE JUMP ExitOffsetDet; dm(OffsetCounter) = AR; AR = dm(TempOffset1); dm(%2) = AR; AR = dm(TempOffset2); dm(%3) = AR; ExitOffsetDet: .ENDMACRO; The macro ReadCurrents reads the two phase currents, corrects them with the offset and finally computes the third phase current. It may be noted that the output of the A/D converter is always a positive number. Because of the presence of an inverting operational amplifier in the hardware, in order to obtain values between –1/2 and +1/2 (in fixed point the currents are scaled by 2⋅ Imax ) the outputs of the A/D converter have to be offset by 1/2 (0x4000). {*************************************************************************************** * Type: Macro * * Call: ReadCurrents; * a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 16 of 18 * This macro reads ADC1(Is1), ADC2(Is2) and then evaluates Is1, Is2 and Is3 * * Input: %0 = offset of the first phase current * * %1 = offset of the second phase current * * %2 = the buffer of the 3 phase currents * * %3 = ADC1 * * %4 = ADC2 * * Output: none * * Modified: AY0, AR, MY0, MR, SR ,AF * ***************************************************************************************} .MACRO ReadCurrents(%0, %1, %2, %3, %4); ADC_Read(%3); { read Is1/Imax } AR = 0x4000 - AR; AY0 = dm(%0); AR = AR - AY0; dm(%2) = AR; { Is1/2Imax } ADC_Read(%4); { read Is2/Imax } AR = 0x4000 - AR; AY0 = dm(%1); AR = AR - AY0; dm(%2+1) = AR; { Is2/2Imax } AR = -AR; AY0 = dm(%2); { Is1/2Imax } AR = AR - AY0; dm(%2+2) = AR; { Is3/2Imax=-Is2/2Imax-Is1/2Imax} .ENDMACRO; 3.5 Experimental results First of all, experiments without the dead time compensation were made. Figure 4 represents the inverter phase voltage compared to the reference voltage that is desired at the inverter terminal and the phase current. It may be seen that the behavior presented in chapter 1 is verified in practice: When the phase current is positive, the real inverter phase voltage is less than the commanded one by an amount determined by the dead time and when the phase current is negative, the real inverter phase voltage is greater than the commanded. At last, Figure 5 displays the inverter phase voltage and the phase current obtained with the feed forward dead time compensation. It may be observed that the voltage still presents some distortions caused by the nature of feed forwarding: it is supposed that the current measured during the previous PWM cycle maintains its sign into the next PWM cycle; when the current changes the sign, this moment cannot be foreseen and the error is doubled. These voltage deformations cause also deformations in the current behaviour, and they may be prevented only implementing current controllers in a more accurate control strategy, like field-oriented control. a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 17 of 18 Figure 4. Reference and real inverter phase voltages and the phase current a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 18 of 18 Figure 5. Inverter phase voltage and phase current after the dead time compensation 4 References [1] Pulse dead time compensator for PWM voltage inverters, David Leggate, Russel J. Kerkman, Industrial Electronics, Control, and Instrumentation, 1995, Proceedings of the 1995 IEEE IECON 21st International Conference on Volume: 1, Page(s): 474 -481 vol.1. SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 􀀀 Wide Operating Voltage Range of 2 V to 6 V 􀀀 Typical Switch Enable Time of 18 ns 􀀀 Low Power Consumption, 20-μA Max ICC 􀀀 Low Input Current of 1 μA Max 􀀀 High Degree of Linearity 􀀀 High On-Off Output-Voltage Ratio 􀀀 Low Crosstalk Between Switches 􀀀 Low On-State Impedance . . . 50-Ω TYP at VCC = 6 V 􀀀 Individual Switch Controls description/ordering information The SN74HC4066 is a silicon-gate CMOS quadruple analog switch designed to handle both analog and digital signals. Each switch permits signals with amplitudes of up to 6 V (peak) to be transmitted in either direction. Each switch section has its own enable input control (C). A high-level voltage applied to C turns on the associated switch section. Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP – N Tube of 25 SN74HC4066N SN74HC4066N Tube of 50 SN74HC4066D SOIC – D Reel of 2500 SN74HC4066DR HC4066 Reel of 250 SN74HC4066DT –40°C to 85°C SOP – NS Reel of 2000 SN74HC4066NSR HC4066 SSOP – DB Reel of 2000 SN74HC4066DBR HC4066 Tube of 90 SN74HC4066PW TSSOP – PW Reel of 2000 SN74HC4066PWR HC4066 Reel of 250 SN74HC4066PWT † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each switch) INPUT CONTROL (C) SWITCH L OFF H ON PRODUCTION DATA information is current as of publication date. Copyright  2003, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1A 1B 2B 2A 2C 3C GND VCC 1C 4C 4A 4B 3B 3A D, DB, N, NS, OR PW PACKAGE (TOP VIEW) SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 logic diagram, each switch (positive logic) A VCC VCC B One of Four Switches C absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Control-input diode current, II (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA I/O port diode current, II (VI < 0 or VI/O > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA On-state switch current (VI/O = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground unless otherwise specified. 2. The package thermal impedance is calculated in accordance with JESD 51-7. SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 recommended operating conditions (see Note 3) MIN NOM MAX UNIT VCC Supply voltage 2† 5 6 V VI/O I/O port voltage 0 VCC V VCC = 2 V 1.5 VCC VIH High-level input voltage, control inputs VCC = 4.5 V 3.15 VCC V VCC = 6 V 4.2 VCC VCC = 2 V 0 0.3 VIL Low-level input voltage, control inputs VCC = 4.5 V 0 0.9 V VCC = 6 V 0 1.2 VCC = 2 V 1000 Δt/Δv Input transition rise/fall time VCC = 4.5 V 500 ns VCC = 6 V 400 TA Operating free-air temperature –40 85 °C † With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital signals be transmitted at these low supply voltages. NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS V TA = 25􀀀C VCC MIN MAX UNIT MIN TYP MAX I A V 0t V 2 V 150 ron On-state switch resistance IT = –1 mA, VI = 0 to VCC, 4.5 V 50 85 106 Ω VC = VIH (see Figure 1) 6 V 30 V V GND V V 2 V 320 ron(p) Peak on-state resistance VI = VCC or GND, VC = VIH, ( ) 4.5 V 70 170 215 Ω IT = –1 mA 6 V 50 II Control input current VC = 0 or VCC 6 V ±0.1 ±100 ±1000 nA Isoff Off-state switch leakage current VI = VCC or 0, VO = VCC or 0, VC = VIL (see Figure 2) 6 V ±0.1 ±5 μA Ison On-state switch leakage current VI = VCC or 0, VC = VIH (see Figure 3) 6 V ±0.1 ±5 μA ICC Supply current VI = 0 or VCC, IO = 0 6 V 2 20 μA Ci Input capacitance A or B 5 V 9 pF C 3 10 10 Cf Feed-through capacitance A to B VI = 0 0.5 pF Co Output capacitance A or B 5 V 9 pF SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended operating free-air temperature range PARAMETER FROM TO TEST VCC TA = 25􀀀C MIN MAX UNIT (INPUT) (OUTPUT) CONDITIONS MIN TYP MAX t P ti C 50 F 2 V 10 60 75 tPLH, Propagation A or B B or A CL = pF 4.5 V 4 12 15 ns tPHL delay time (see Figure 4) 6 V 3 10 13 t S it h RL = 1 kΩ, 2 V 70 180 225 tPZH, tPZL Switch turn-on time C A or B CL = 50 pF 4.5 V 21 36 45 ns L (see Figure 5) 6 V 18 31 38 t S it h RL = 1 kΩ, 2 V 50 200 250 tPLZ, Switch C A or B CL = 50 pF 4.5 V 25 40 50 ns tPHZ turn-off time L (see Figure 5) 6 V 22 34 43 Control CL = 15 pF, RL = 1 kΩ 2 V 15 fI input frequency C A or B kΩ, VC = VCC or GND, V V /2 4.5 V 30 MHz VO = VCC/(see Figure 6) 6 V 30 Control feed-through C A or B CL = 50 pF, Rin = RL = 600 Ω, VC = VCC or GND 4.5 V 15 mV noise GND, fin = 1 MHz (see Figure 7) 6 V 20 (rms) operating characteristics, VCC = 4.5 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance per gate CL = 50 pF, f = 1 MHz 45 pF Minimum through bandwidth, A to B or B to A† [20 log (VO/VI)] = –3 dB CL = 50 pF, VC = VCC RL = 600 Ω, (see Figure 8) 30 MHz Crosstalk between any switches‡ CL = 10 pF, fin = 1 MHz RL = 50 Ω, (see Figure 9) 45 dB Feed through, switch off, A to B or B to A‡ CL = 50 pF, fin = 1 MHz RL = 600 Ω, (see Figure 10) 42 dB Amplitude distortion rate, A to B or B to A CL = 50 pF, fin = 1 kHz RL = 10 kΩ, (see Figure 11) 0.05% † Adjust the input amplitude for output = 0 dBm at f = 1 MHz. Input signal must be a sine wave. ‡ Adjust the input amplitude for input = 0 dBm at f = 1 MHz. Input signal must be a sine wave. SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PARAMETER MEASUREMENT INFORMATION VCC VI = VCC VC = VIH + 1.0 mA – VO ron 􀀀 VI–O 10–3 􀀀 VI–O VCC GND (ON) V Figure 1. On-State Resistance Test Circuit VCC VC = VIL A B VS = VA – VB CONDITION 1: VA = 0, VB = VCC CONDITION 2: VA = VCC, VB = 0 VCC GND A (OFF) Figure 2. Off-State Switch Leakage-Current Test Circuit SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION VCC VC = VIH A B VCC Open VA = VCC TO GND VCC GND A (ON) Figure 3. On-State Leakage-Current Test Circuit VCC VC = VIH VI VO 50 pF TEST CIRCUIT tPLH tPHL 50% 50% VCC 0 V 50% 50% VOH VOL VI A or B VO B or A VOLTAGE WAVEFORMS 50 Ω tr 90% 10% tf 10% 90% VCC GND (ON) Figure 4. Propagation Delay Time, Signal Input to Signal Output SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PARAMETER MEASUREMENT INFORMATION CL GND 50 pF VCC VI VO TEST CIRCUIT tPLZ 50% VOLTAGE WAVEFORMS RL 1 kΩ 10% S1 VC 50 Ω S2 tPZH tPHZ 50% 50% 50% 90% tPZL tPZH tPLZ tPHZ GND VCC GND VCC TEST S1 S2 VCC GND VCC GND tPZL 50% VCC VO 50% 0 V VOL VOH VC (tPZL, tPZH) (tPLZ, tPHZ) VCC VCC VO 0 V VOL VOH VC VCC 0 V VOL VOH VCC 0 V VOL VOH Figure 5. Switching Time (tPZL, tPLZ, tPZH, tPHZ), Control to Signal Output SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION VCC GND VO RL 1 kΩ CL 15 pF VCC VC 50 Ω VI = VCC VCC VC 0 V VCC/2 Figure 6. Control-Input Frequency VCC GND VO RL 600 Ω CL 50 pF VCC VC 50 Ω VI VCC/2 Rin 600 Ω VCC/2 tr tf 90% 10% (f = 1 MHz) tr = tf = 6 ns 90% 10% VCC VC 0 V Figure 7. Control Feed-Through Noise VO VCC 50 Ω fin VCC/2 VC = VCC 0.1 μF VI VI (VI = 0 dBm at f = 1 MHz) VCC GND (ON) RL 600 Ω CL 50 pF Figure 8. Minimum Through Bandwidth SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PARAMETER MEASUREMENT INFORMATION VO1 RL 600 Ω CL 50 pF VCC 50 Ω fin VCC/2 VC = VCC 0.1 μF VI VI (VI = 0 dBm at f = 1 MHz) VO2 VCC Rin 600 Ω VCC/2 VC = GND Rin 600 Ω VCC GND (ON) VCC GND (OFF) RL 600 Ω CL 50 pF Figure 9. Crosstalk Between Any Two Switches VO VCC 50 Ω fin VC = GND 0.1 μF VI VI (VI = 0 dBm at f = 1 MHz) VCC GND (OFF) Rin 600 Ω RL 600 Ω CL 50 pF VCC/2 VCC/2 Figure 10. Feed Through, Switch Off VI (VI = 0 dBm at f = 1 kHz) VO RL 10 kΩ CL 50 pF VCC VCC/2 VC = VCC 10 μF VI fin VCC GND (ON) Figure 11. Amplitude-Distortion Rate PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN74HC4066D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066DBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI -40 to 85 SN74HC4066DBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066DBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066DT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC4066N SN74HC4066NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC4066N SN74HC4066NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI -40 to 85 SN74HC4066PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066PWT ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 2 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN74HC4066DBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74HC4066DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC4066DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC4066NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74HC4066PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HC4066PWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC4066DBR SSOP DB 14 2000 367.0 367.0 38.0 SN74HC4066DR SOIC D 14 2500 367.0 367.0 38.0 SN74HC4066DT SOIC D 14 250 367.0 367.0 38.0 SN74HC4066NSR SO NS 14 2000 367.0 367.0 38.0 SN74HC4066PWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74HC4066PWT TSSOP PW 14 250 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01 28 PINS SHOWN Gage Plane 8,20 7,40 0,55 0,95 0,25 38 12,90 12,30 28 10,50 24 8,50 Seating Plane 7,90 9,90 30 10,50 9,90 0,38 5,60 5,00 15 0,22 14 A 28 1 16 20 6,50 6,50 14 0,05 MIN 5,90 5,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 0,15 M 0°–8° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. 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This application note describe the use of a tracebuffer structure where values treated in the DSP can be saved in a data-array and used for internal of external modification interfaced though the Motion Control Debugger system. 1 The Tracebuffer Structure A data-array structure is defined to enable saving arrays of values in data-memory (DM). This array of memory locations can be addressed by the use of the pointer-system on the 2171 core. With this structure defined, further treating or evaluation of the internal data-calculations can be analyzed and checked for errors. Using the Motion Control Debugger the values can be either be plotted directly or dumped for analyzing the data-array in other external programs In the chosen structure any number of pointer arrays in DM can be enabled and individually initialized for locations in DM. The structure will furthermore allow the user to under-sample the writing to the buffer. Initialize the Tracebuffer Though macro Is the Sample Ratio = Sample number? Is Flag enabled ? Is there still space in the Buffer Full ? YES No YES No Update Buffer and increment pointer and counter End Macro; Macro Call YES No Figure 1 - Flowchart for the Buffer writing The flow chart illustrate the structure of the trace buffer writing. Initialization is done in the startup sequence. After this, the Flag is checked - is the flag set then the corresponding tracebuffer is enabled. Secondly the buffer is checked for available spaces. If the DM locations defined for memory write aren't full it is safe to go on. If the buffer is full return. Finally the sample-ratio is checked. If a sample-ratio is a Using a Tracebuffer with the ADMCF32X ANF32X-34 © Analog Devices Inc., March 2000 Page 4 of 11 declared different from zero then check if the sample-number is equal to the sample-ratio. If it is write the chosen variable to the data-array. If not, return to the subroutine. The structure of the buffer is circular and to optimize the flexibility the format is provided as a complete macro setting with locked data-array format. 1.1 The Tracebuffer Data-Array To enable the tracebuffer array in DM it is necessary to define a given circular buffer with associated pointer. The circular buffer is structured as: First location : Statement of flag - ON/OFF Second location : Pointer to next free address Third location : Sample ratio (specified by the user) Fourth location : Sample number (used during the re-sampling of values) Fifth location : Counter for the buffer. Sixth to XXX locations : Placement for the values Every time the macro is called, Ex. in the PWMSYNC_ISR, a new value is added to the buffer if there are available space left and the sample number is equal to the under-sample ratio. DM(Address) Flag (ON/OFF) DM(Address+1) Pointer to next free address .. Sample ratio .. Sample number .. Counter for Buffer .. First Data-placement .. Value(1) .. Value(2) .. .. .. .. .. .. .. Value (Buffer size -2) .. Value (Buffer size -1) .. Value (Buffer size) Figure 2 - Tracebuffer - locations in DM Figure 2 illustrates how the values are placed in the allocated DM locations. Here values are stored at specific addresses in order to analyze these off-line. First value Placed in the buffer N = numbers in tracebuffer Buffer full a Using a Tracebuffer with the ADMCF32X ANF32X-34 © Analog Devices Inc., March 2000 Page 5 of 11 2 Implementation of the Tracebuffer Library Routines 2.1 Usage of the tracebuffer routines The routines are developed as an easy-to-use library, which has to be linked to the user’s application. The library consists of two files. The file “T_buffer.dsp” contains the assembly code for the subroutines. This package has to be compiled and can then be linked to an application. The user has to include the header file “T_buffer.h”, which provides the function-like macros for this routine. The following table summarizes the set of macros that are defined in this library. Operation Usage Input Output Initialization Buffer_Init("name", sample ratio); Name & Sample ratio None Activate Buffer_ON("name"); Name None Deactivate Buffer_OFF("name"); Name None Record Buffer_Record("name", value); Name & Value None Table 1: Implemented routines The four-macro settings allow the user to setup any given DM-locations for trace-buffer availability. Specifying the selected buffer and record value enables the flexibility of writing any number to a known position in memory. 2.2 Usage of the DSP registers Table 2 gives an overview of the DSP core registers that are modified by the four macros mentioned above. Obviously, also the "input" values are modified. Usage Modified registers Buffer_Init("name", sample ratio); ax0 Buffer_OFF("name"); ax0 Buffer_ON("name"); ax0 Buffer_Record("name", value); ax0, ax1, ay0, ar, I5, M5 Table 2: Usage of DSP core registers for the subroutines a Using a Tracebuffer with the ADMCF32X ANF32X-34 © Analog Devices Inc., March 2000 Page 6 of 11 2.3 Access to the library: the header file Including the header file "t_buffer.h" into the application code may access the library. The header file is intended to provide function-like macros to the Trace buffer routines. It defines the calls shown in Table 1. The file is mostly self-explaining but some comments have to be added. The sample ratio is here defined as how often is a new value can be written to the buffer. First macro is the Buffer_Init macro. This macro initializes the five first location of the circular buffer in respect to "name of the buffer" and the sample-ratio. Furthermore the sample-number and the internal counter is cleared. The second and third macro Buffer_ON and Buffer_OFF just enables or disables writing to the buffers. In this case the first location in the buffer ( the flag ) are set/or cleared. {******************************************************************************** * * * Type: Macro * * * * Call: Buffer_Init("Buffer", sampleratio) * * Description : Initialize the tracebuffer * * * * Undersample ratio 0 = every time * * 1 = every 1.time * * 2 = every 2.time ..... * * * * Ouputs : none * * * * Modified: ax0 * * * ********************************************************************************} .MACRO Buffer_Init(%0,%1); ax0 = %1; { Sample ratio } dm(%0+2)= ax0; ax0 =^%0+5; { Store start value } dm(%0+1)= ax0; { first location for data } ax0 = 0x0000; dm(%0) = ax0; { Clear Flag - Non-Active } dm(%0+3)= ax0; { Clear sample number } dm(%0+4)= ax0; { Clear counter for this buffer } .ENDMACRO; {******************************************************************************** * * * Type: Macro * * * * Call: Buffer_ON("buffer") * * * * Description : Enable tracebuffer "Buffer" * * Ouputs : none * * * * Modified : ax0 * * * ********************************************************************************} .MACRO Buffer_ON(%0); ax0 = 1; dm(%0) = ax0; .ENDMACRO; a Using a Tracebuffer with the ADMCF32X ANF32X-34 © Analog Devices Inc., March 2000 Page 7 of 11 {******************************************************************************** * * * Type: Macro * * * * Call: Buffer_OFF("buffer") * * * * Description : Disable tracebuffer "Buffer" * * Ouputs : none * * * * Modified : ax0 * * * ********************************************************************************} .MACRO Buffer_OFF(%0); ax0 = 0; dm(%0) = ax0; .ENDMACRO; 2.4 The program macro The following code contained in the file “t_buffer.h” defines the macrocode used for the Tracebuffer. In many cases this piece of code is placed in the "t_buffer.dsp"-file but here the flexibility advances by placing the program-code directly in the macro. It should be mentioned that this way of using the tracebuffer enables flexibility but takes up more memory. The following code implements the tracebuffer routines. Refer to the flowchart in section 1 for the structure of the buffers. Input to the tracebuffer are any numbers computed in the DSP. Underneath is the code for the Buffer_Record.. It just need to be said that since the buffer is structured as a circular buffer the data-placement for each of the "buffer-handle" values are placed from buffer-location 1 to 5 (here %0….%0+4) {******************************************************************************** * * * Type: Macro * * * * all: Buffer_Record(buffer,data) * * * * Description : Place data in buffer memory * * Ouputs : none * * * * Modified: M5, I5, ar, ax1, ax0, ay0 * * * ********************************************************************************} .MACRO Buffer_Record(%0,%1); .Local Continue1,Continue2,Continue3,End; { Local routines in Macro } M5 = 1; { modify factor = 1 } ax1 = %1; I5 = ^%0; { load start value for pointer } ar = dm(%0); { temporary storage } ar= tstbit 0 of ar; if NE jump Continue1; Jump end; Continue1: ax0 = %%0; ay0 = dm(%0+4); ar = ax0 - ay0; if gt jump Continue2; ax0 = 0x0000; dm(%0) = ax0; Jump end; a Using a Tracebuffer with the ADMCF32X ANF32X-34 © Analog Devices Inc., March 2000 Page 8 of 11 Continue2: { is sample_num equal to ratio? } ax0 = dm(%0+3); ay0 = dm(%0+2); ar = ax0 - ay0; if eq jump Continue3; ar = ax0 + 1; dm(%0+3) = ar; Jump end; Continue3: { write into buffer } I5 = dm(%0+1); { load backup value for pointer } dm(I5,M5) = ax1; { Value updated to Buffer } ax0 = dm(%0+4); { increment count } ar = ax0 + 1; dm(%0+4) = ar; ax0 = 0x0000; { clear sample_num } dm(%0+3) = ax0; dm(%0+1) = I5; end: .ENDMACRO; 3 Software Example: Tracebuffer 3.1 Usage of the Tracebuffer routine an example This example demonstrates how two values are written to Buffer1 and Buffer2. In this case the memorylocations used as buffers are set to 2*105-locations (100 location of calculated data). The values written to these two buffer-arrays are values computed for three 120-degree phase shifted reference voltages. 3.2 The main program: main.dsp The file “main.dsp” contains the initialisation and PWM Sync and Trip interrupt service routines. To activate, build the executable file using the attached build.bat either within your DOS prompt or clicking on it from Windows Explorer. This will create the object files and the main.exe example file. This file may be run on the Motion Control Debugger. The program can be booted from Flash but in this tracebuffer case it is not effectuated since the DM can not be read without the Motion Control Debugger. Every module besides from the Main_program module is by default placed in either one of the three USERFLASH memory banks. In the following, a brief description of the code is given. Start of code – declaring start location in program memory or FLASH memory. Comments are placed depending on whether the program should run in PMRAM or Flash memory. {************************************************************************************** * Application: Starting from FLASH (out-comment the one not used) **************************************************************************************} !.MODULE/RAM/SEG=USERFLASH1/ABS=0x2200 Main_Program; {************************************************************************************** * Application: Starting from RAM (out-comment the one not used) **************************************************************************************} .MODULE/RAM/SEG=USER_PM1/ABS=0x30 Main_Program; a Using a Tracebuffer with the ADMCF32X ANF32X-34 © Analog Devices Inc., March 2000 Page 9 of 11 Next, the general systems constants and PWM configuration constants (main.h – see the next section) are included. Also included are the PWM library and the T_BUFFER library definitions {******************************************************************************** * Include General System Parameters and Libraries * ********************************************************************************} #include ; #include ; #include ; #include ; {******************************************************************************** * Local Variables Defined in this Module * ********************************************************************************} .VAR/DM/RAM/SEG=USER_DM AD_IN; { Volts/Hertz Command (0-1) } .VAR/DM/RAM/SEG=USER_DM Theta; { Current angle } .VAR/DM/RAM/SEG=USER_DM VrefA; { Voltage demands } .VAR/DM/RAM/SEG=USER_DM VrefB; .VAR/DM/RAM/SEG=USER_DM VrefC; .VAR/DM/RAM/CIRC/SEG=USER_DM Buffer1[105]; { Tracebuffer } .VAR/DM/RAM/CIRC/SEG=USER_DM Buffer2[105]; { Tracebuffer } ar = 0x7FFF; dm(AD_IN) = ar; ar = 0x0000; dm(Theta) = ar; dm(VrefA) = ar; dm(VrefB) = ar; dm(VrefC) = ar; Some Variables are defined hereafter. These are used to calculate the three reference voltages. For further information see ANF32X-3. The two circular buffers are defined - here the size is 105 locations (5 locations are used for handling the buffer) this number is arbitrary - just depending on the memory locations occupied by these buffers. The first thing that is done in the initialisation block (Startup) is checking a selected PIO line for level. If the PIO-pin is high jump to an ERASE BOOT FROM FLASH BIT routine in ROM and return. If not, just go ahead with normal operation. This small macro is done to enable re-coding of the FLASH memory. For further information (See Reference Manual). In this example the PIO-pin 6 is chosen as erase pin. The initialisation of the PWM block is executed. Note how the interrupt vectors for the PWMSync and PWMTrip service routines are passed as arguments. Then the interrupt IRQ2 is enabled by setting the corresponding bit in the IMASK register. Two Tracebuffers are initialised with 1x under-sampling Then the Tracebuffers are activated by setting the flag (Buffer_ON(Buffer1) & Buffer_ON(Buffer2)). After that, the program enters a loop, which just waits for interrupts. {******************************************************************************** * Start of program code * ********************************************************************************} Startup: FLASH_erase_PIO(6); { Select PIO6 as clearing PIO } { Remember that sport1 is muxed with the PIO-lines } { If the bit is high Clear Memory and Boot from } { Flash bit } PWM_Init(PWMSYNC_ISR, PWMTRIP_ISR); IFC = 0x80; { Clear any pending IRQ2 inter. } ay0 = 0x200; { unmask irq2 interrupts. } ar = IMASK; ar = ar or ay0; IMASK = ar; { IRQ2 ints fully enabled here } Buffer_Init(Buffer1, 1); { 1x undersampling } Buffer_Init(Buffer2, 1); { 1X undersampling } Buffer_ON(Buffer1); { Activate the Buffer } Buffer_ON(Buffer2); { Activate the Buffer } Main: { Wait for interrupt to occur } jump Main; rts; a Using a Tracebuffer with the ADMCF32X ANF32X-34 © Analog Devices Inc., March 2000 Page 10 of 11 In the PWMSYNC_ISR the DAGS are first set up for trigonometric functionality. Three reference voltages VrefA,B and C are calculated on base of the trigonometric functions in the Trigonometric-library ( See ANF32X-10 ). The PWM block is update with these control signals and finally the two Tracebuffers Buffer1 and Buffer2 are updated. Here the variables VrefA and VrefB are stored in the two data-arrays. PWMSYNC_ISR: Set_DAG_registers_for_trigonometric; my0 = DM(AD_IN); mr = 0; { Clear mr } mr1 = dm(Theta); { Preload Theta } mx0 = Delta; mr = mr + mx0*my0 (SS); { Compute new angle & store } dm(Theta) = mr1; Sin(mr1); { Result in ar register } mr = ar*my0 (SS); { Multiply by Scale for VrefA } dm(VrefA) = mr1; ax1 = dm(Theta); { Compute angle of phase B } ay1 = TwoPioverThree; ar = ax1 - ay1; Sin(ar); { Result in ar register } mr = ar*my0 (SS); { Multiply by Scale for VrefB } dm(VrefB) = mr1; ax1 = dm(Theta); { Compute angle of phase C } ay1 = TwoPioverThree; ar = ax1 + ay1; Sin(ar); { Result in ar register } mr = ar*my0 (SS); { Multiply by Scale for VrefC } dm(VrefC) = mr1; ax0 = DM(VrefA); ax1 = DM(VrefB); ay0 = DM(VrefC); ay1= DM(Theta); PWM_update_demanded_Voltage(ax0,ax1,ay0); {******************************************************************************* * Update tracebuffers * *******************************************************************************} ax0 = DM(VrefA); Buffer_Record(Buffer1,ax0); ax0 = DM(VrefB); Buffer_Record(Buffer2,ax0); RTI; It has to be mentioned that the Buffer_Record macro uses some DSP registers (see T_buffer.h) for that reason the proposed way of writing to the buffer is as defined above. 4 Experimental results The experimental results illustrated beneath are two plots of VrefA and VrefB. These values are written into Buffer1 and Buffer2 and then plotted though the Motion Control Debugger. As can be seen on Figure 3 the two waveforms are plotted as a function of the given number in Buffer1 and 2. From the figures the scaling can also be seen - here the numbers are represented in decimal. Selecting another scaling of these reference-voltages will re-scale these plots. a Using a Tracebuffer with the ADMCF32X ANF32X-34 © Analog Devices Inc., March 2000 Page 11 of 11 Figure 3 - Plot from the Motion Control Debugger using the Internal Plot Function. www.analog.com Developing VisualAudio Modules Copyright Information © 2006 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc. Trademark and Service Mark Notice The Analog Devices logo, VisualDSP++, VisualAudio, SHARC, Blackfin, and EZ-KIT Lite are registered trademarks of Analog Devices, Inc. All other brand and product names are trademarks or service marks of their respective owners. 2 of 51 Contents Contents..............................................................................................................................................................................................................3 Preface.................................................................................................................................................................................................................4 Purpose of This Manual................................................................................................................................................................................4 Custom Audio Modules....................................................................................................................................................................................5 Overview.........................................................................................................................................................................................................5 Numerics on the Blackfin and SHARC.......................................................................................................................................................9 Example 1A – Mono Parametric Scaling....................................................................................................................................................9 Example 1B – Render Function in ASM.................................................................................................................................................19 Scratch Buffers............................................................................................................................................................................................22 Auxiliary Memory for Module Instances................................................................................................................................................22 Pointer Aliasing Rules................................................................................................................................................................................25 Meta-Variables and Expressions...............................................................................................................................................................26 Modifying Module Parameters.................................................................................................................................................................27 Expression Language Details.....................................................................................................................................................................28 Modules With Data of Varying Size.........................................................................................................................................................33 Modules With a Variable Number of Pins...............................................................................................................................................34 Frequency Domain Processing.................................................................................................................................................................36 Other Features of the XML File................................................................................................................................................................36 Custom Bypass Functions..........................................................................................................................................................................38 SHARC SIMD Considerations..................................................................................................................................................................38 Adjusting Modules from Other Modules................................................................................................................................................39 Dynamically Changing a Module’s Render Function............................................................................................................................39 Compatibility between Blackfin and SHARC Modules.........................................................................................................................39 Reference Section............................................................................................................................................................................................41 AudioProcessing.h Structures...................................................................................................................................................................41 Module Memory Sections.........................................................................................................................................................................44 Summary of Naming Conventions...........................................................................................................................................................45 Inspector Control Types............................................................................................................................................................................47 XML Format................................................................................................................................................................................................50 Index.................................................................................................................................................................................................................51 3 of 51 Preface PURPOSE OF THIS MANUAL The VisualAudio Designer Users’ Guide explains how to use VisualAudio to develop audio processing software for a wide variety of products. The guide describes the graphical interface, provides step-by-step procedures for completing tasks, and contains detailed technical information on how to integrate the generated code into your final product. Intended Audience The primary audience for this manual is a programmer who is familiar with Analog Devices, Inc. processors. This manual assumes that the audience can use the VisualDSP++ development environment to develop, build, and debug Digital Signal Processing (DSP) applications for the SHARC or Blackfin processor. 4 of 51 Custom Audio Modules This document explains how to write an audio processing module for VisualAudio for SHARC processors in the 26x and 36x families, as well as for Blackfin processors in the 53x and 56x families. Audio modules allow audio processing (sometimes called “post-processing”) to be implemented by making use of a number of smaller, self-contained processing blocks. The topics are organized as follows. • “Overview” • “Numerics on SHARC and Blackfin” • “Example 1A – Mono parameter scaling” • “Example 1B – Render function in ASM” • “Scratch Buffers” • “Auxiliary Memory for Module Instances” • “Pointer Aliasing Rules” • “Meta-variables and Expressions” • “Modifying Module Parameters” • “Expression Language Details” • “Modules with Data of Varying Size” • “Modules with Variable Numbers of Pins” • “Other Features of the XML File” • Custom Bypass Functions” • “SHARC SIMD Considerations” • “Adjusting Modules from Other Modules” • “Dynamically Changing a Module’s Render Function” • “Compatibility between Blackfin and SHARC Modules” OVERVIEW This section includes a brief philosophical review of what motivated certain design decisions, a discussion about the quasi-object orientation inherent in the module concept, a description of usage scenarios and a high-level description of the parts of a module. Design Philosophy The module format was designed with the following goals in mind. • Minimal run-time processor footprint • CPU efficiency • Straightforward to write and use Several key features help accomplish these goals. • VisualAudio does as much work as possible at compile and assembly time to enable the production DSP code to be lean, while still providing a flexible environment for creating and deploying modules. • Modules process a block of samples at a time to ensure that the cost of loading and storing state and parameters is incurred only once per block instead of once per sample. • VisualAudio supports interleaved stereo connections between modules to enable a common use of Single-Instruction, Multiple-Data (SIMD) on the SHARC DSP. This signal type is also supported on the Blackfin, primarily for compatibility with system designs originating on SHARCs. 5 of 51 • VisualAudio supports signals at both the audio sampling rate and a lower “control rate.” This allows slowly-changing control signals to use less memory and MIPS. • VisualAudio supports a variety of frequency domain signal types, as well as a user-settable FFT size and hop factor for “overlap-add” and “overlap-save” style processing. • Some of the spirit of object-oriented programming is borrowed, while a lean approach is maintained. Note that C++ is not used. • To keep the CPU usage (MIPS) of a module relatively constant, a module instance should perform roughly the same operations every time it runs. Assume the module’s worst case CPU usage. The exception is when there are clear modes. In this case, the user can plan in advance the combination of module modes that will be in use at a particular time. • In keeping with the goals of near-constant CPU usage and minimal memory usage, parameter calculation (such as filter design) is normally pushed forward to design time, and implemented outside the DSP runtime (for example within VisualAudio Designer). Therefore, modules usually do not contain design or initialization code on the DSP. Instead, module instances are normally initialized and designed via static initialization of their state structures (in code generated by VisualAudio Designer or by the user).1 Module Terminology Each type of processing module is represented by its own module class. These are instantiable; multiple instances of each class may exist at the same time. We use the term module when the distinction between the class and the instance is clear from context. Examples of modules include “Scaler N Smoothed” and “Delay).” The behavior of modules is adjusted via render variables. These are variables that exist on the DSP as part of the module instance structure. In addition, VisualAudio Designer presents high-level interface variables for each module. Interface variables are those exposed via module inspectors within VisualAudio Designer. An interface variable may correspond directly to a render variable. Alternatively, an interface variable may be mapped to a render variable through some function; for example, translating a delay time in milliseconds to a sample delay. Other possibilities include more complicated dependencies, where one or more interface variables touch one or more render variables. Render variables are defined in associated .h files detailing the instance structure of each module; interface variables are defined in associated .xml files. Interface variables are sometimes referred to as high-level variables, while render variables are sometimes referred to as low-level variables. There are three kinds of render variables, differing in restrictions on when they are set: • Constants are typically set only at design time (i.e. their value doesn’t usually change at run time.) • Parameters are typically set at design or tuning time from VisualAudio Designer, or by DSP control code • States can be set by the module’s render function itself, as well as by VisualAudio Designer in tuning mode or by DSP control code. Within VisualAudio Designer, these restrictions are enforced. On the DSP itself, it is up to the user to abide by these guidelines as appropriate. The term render variable is used to distinguish it from a meta-variable, which exists only in VisualAudio Designer’s representation of the module, not on the DSP. Thus, the set of interface variables contains some render variables and some meta-variables. Modules are interconnected via pins. Pins may be designated as either input or output. Either may be of type stereo_pcm, mono_pcm or control. The stereo_pcm and mono_pcm pins are collectively referred to as “audio rate pins,” or simply “audio 1 In stand-alone usage (without VisualAudio Designer) or when modules are implemented in terms of other modules, allocation can be either dynamic or static and initialization DSP code is often included. 6 of 51 pins.” Control rate pins are referred to as “control pins” and are of type control. Frequency domain pins may be of the following types: spectrum_real, spectrum_complex, spectrum_half_real and spectrum_half_complex. These are explained in more detail later. There are two kinds of modules: those that have a fixed number of pins, and those in which the number of input and/or output pins varies from instance to instance. A module class may have outputs, but no inputs, in which case it can be thought of as a signal generator (such as a sine wave generator). Or, it can have inputs, but no outputs, and report its results in a state variable (such as a VU meter). Finally, a module can have neither outputs nor inputs, and can do its work entirely in terms of side effects to itself (modifying its own state) or to other modules (modifying the render variables of other modules). Such a module could be used, for example, in testing other modules, when strictly-repeatable sample-synchronous updates are needed. Render functions must never write to their inputs. To see why this is true, consider a module whose output fans out to several other modules. If the first module wrote to its input, it would corrupt the input to the second module. However, the VisualAudio Designer routing algorithm knows the overall connection between audio modules and may reuse the same patch buffer for the input and output of a module, when it is safe. For more details, see Pointer Aliasing Rules below. Module Usage Scenarios There are two ways that VisualAudio modules can be used: • In a drag-and-drop fashion from VisualAudio Designer - Memory allocation, parameter setting and calling of the render function are handled automatically. • As C-callable functions in a stand-alone library - Memory allocation, parameter setting and calling of the render function are all handled by the user’s C or assembly code. Even if a module is used in drag-and-drop fashion, its render variables may be modified in the DSP program’s control code (sometimes referred to as “user control code.”) Similarly, a module used in a drag-and-drop fashion may include, in its implementation, a render function that calls other render functions using the stand-alone style. This document contains information on developing modules that may be used in either style of usage. For more information on usage, see the document VisualAudio Module Library Usage Guide. For more information on the particular modules supplied by VisualAudio, see VisualAudio Module Library Reference for Blackfin and VisualAudio Module Library Reference for SHARC. Module Modes When used within a layout generated by VisualAudio Designer1, a module may be in one of four modes. These can be set at runtime with the following function: AMFSetModuleStatus(AMF_Module *module, AMF_ModuleStatus status) The possible status values and their meanings are given below. • AMFModuleStatus_ACTIVE. The module processes its inputs and writes its outputs via its render function each time it is run. This is the default mode. Note that a module may have several alternative render functions, but one must be specified as the default. • AMFModuleStatus_INACTIVE. The module is not run. This implies that its outputs are not written, leaving their contents undefined. • AMFModuleStatus_MUTED. The module's outputs are zeroed each time it is run. This behavior is provided automatically. You need not write any code to implement this mode. 1 More specifically, when used with the VisualAudio Layout Support library. 7 of 51 • AMFModuleStatus_BYPASSED. The module performs the bypass function, which means that its input(s) are copied to its output(s) each time it is run. The default algorithm copies audio inputs to audio outputs, copies signal inputs to signal outputs, and mutes unused outputs. Where there is a mono/stereo mismatch, stereo is converted to mono by adding the channels and dividing by two; mono is converted to stereo by duplicating the channel. Alternatively, the module designer may provide a custom bypass function. For more information, see How to Write a Custom Bypass Function below. The default bypass algorithm copies the Nth input pin of a given type to the Nth output pin of the same type. For example, the 3rd control pin input is copied to the 3rd control pin output. If there are more output pins than input pins, the remainder are muted. Note that for the purposes of bypass, stereo and mono pins are considered the same type. If a mono input matches a stereo output, the mono input is duplicated on both channels. If a stereo input matches a mono output, the stereo channels are added and divided by 2. Parts of a Module A module consists of these parts: • A header (.h) file that defines the run-time interface to the module, including the instance structure typedef. The name of this file must be the same as the module name with .h (for example, AMF_Scaler.h). • The module’s run-time DSP code, in source or binary form (e.g., to protect any intellectual property). The VisualAudio Module Library is delivered in binary form as a VisualDSP++ .dlb file, and the source is also included. If delivered in source form, the module must contain the following two parts: • The module’s render function, which implements the module’s primary function • The module’s class object, which describes the module to the run-time system • A .xml file that describes the module to VisualAudio Designer in detail. This file is not required if the module is never used with VisualAudio Designer. The name of this file must be the same as the module name, with .xml appended (for example, AMF_Scaler.xml where “AMF” stands for Audio Module Format). The .xml file includes information about what files constitute the module’s run-time and header files, as well as information about the module’s parameters, and may also include simple design formulas. How to Add a Module to VisualAudio Designer To make a custom SHARC module available to VisualAudio Designer, create a directory (we’ll call it xxx) and put the XML, include, source files and object files1 in sub-directories. For the SHARC, the subdirectories should be: • XML files in xxx\SHARC\XML\ • Header files in xxx\SHARC\Include\ • Source files in xxx\SHARC\Source\ • Object files in xxx\SHARC\Lib For the Blackfin, they should be: • XML files in xxx\Blackfin\XML\ • Header files in xxx\Blackfin\Include\ • Source files in xxx\Blackfin\Source\ • Object files in xxx\Blackfin\Lib Where xxx is your Modules directory. You must then add your Modules directory to the list of directories searched by VisualAudio Designer. See the VisualAudio Designer User's Guide for details. 1 Third parties can protect their IP by delivering it as a library (a .dlb). Alternatively, they can deliver it is as a pre-compiled or pre-assembled object file (a .doj). 8 of 51 You must add your custom module source files to the VisualDSP++ project (.dpj) file for your platform. In contrast, when a module is included in object form (.dlb or .doj), it is automatically added to the linker list via the VALinkerCmds.txt file. NUMERICS ON THE BLACKFIN AND SHARC The primary difference between Blackfin and SHARC modules is the use of floating point on the SHARC. On the Blackfin, floating point is not available in hardware; hence Blackfin modules typically operate in fixed point. The basic VisualAudio signal type on the Blackfin is fract32, a 32-bit 1.31 format fraction. The basic VisualAudio signal type on the SHARC is a float, a 32-bit floating point number. To ease the task of moving between SHARC and Blackfin, VisualAudio defines a type AMF_Signal, which is fract32 for Blackfin and float for SHARC. Most SHARC modules use floating point internally. However, extended precision SHARC modules may use fixed point internally. Most Blackfin modules use fixed point internally. A number of conventions have been established for fixed-point processing on the Blackfin. We recommend that custom modules obey these conventions for maximum compatibility: The default format for fixed point coefficients is 1.31. Coefficients which perform a “volume scaling” can be 16 bits (typically 1.15 format), so that faster 16x32 multiplication can be used (as opposed to 32x32), since a volume-like scale tends not to need to be represented with an extremely high precision. Smoothing of 16-bit coefficients may need to be performed at 32 bits (to allow the smoothing to move at very slow smoothing rates), but the top 16 bits can still be used for doing the volume scaling cheaply. Headroom in signals is assumed to be managed by the layout creator, not by the module or by VisualAudio. Therefore, except where noted, a Blackfin module assumes 1.31 input and output signals, and for compatibility a SHARC module assumes signals where 1.0f corresponds to maximum amplitude (though clipping to +/- 1.0 is only implemented at the output). Saturating arithmetic is used in fixed point modules. In fixed point modules, multiplications implemented to “31-bit” precision (i.e. discarding the low order product as a speed optimization) may be used as a satisfactory substitute for full 32x32 multiplications. 16 bit types (fract16 and int16 ) as module variables are not supported on the SHARC in VisualAudio. The module implementer is responsible for creating correct alignment in the module state structure, if necessary (via padding and/or ordering). This is an issue only with Blackfin modules. The structures allocated by VisualAudio Designer can be assumed to be aligned to 32-bit boundaries. EXAMPLE 1A – MONO PARAMETRIC SCALING The following example shows a parametric scaling of a mono signal, for both SHARC and Blackfin versions of VisualAudio Example 1A Header File: AMF_Scaler.h The example module’s header file is shown below, for the SHARC or Blackfin version of VisualAudio: /***** Begin AMF_Scaler.h *******/ // Include header file with base class definitions: #include "AudioProcessing.h" // Instance structure typedef 9 of 51 typedef struct { AMF_Module b; // Parameters AMF_Signal amplitude; } AMF_Scaler; // Class object declaration extern const AMF_ModuleClass AMFClassScaler; /**** End AMF_Scaler.h *****/ Notice that the instance structure begins with an embedded struct of type AMF_Module. All module instance structures must begin in this manner (this allows any module’s struct to be interpreted as an AMF_Module, hence implementing a form of inheritance). This struct is followed by a single render variable, amplitude. The structure for the Blackfin and SHARC versions of the module are identical, except for the definition of AMF_Signal as fract32 instead of float in AudioProcessing.h. Example 1A Code File: AMF_Scaler.c The example module’s C code file is AMF_Scaler.c. The first half of the C file for the SHARC version of the module is listed below and analyzed in detail, with comparisons to the Blackfin version as necessary. /****** Begin AMF_Scaler.c *********/ #include "AMF_Scaler.h" // The module's header file #pragma optimize_for_speed // VisualDSP++ directive SEG_MOD_FAST_CODE void AMF_Scaler_Render( AMF_Scaler *restrict instance, AMF_Signal * restrict * buffers, int tickSize) { int i; AMF_Signal *in = buffers[0]; AMF_Signal *out = buffers[1]; AMF_Signal amplitude = instance->amplitude; #pragma SIMD_for for (i=0; iamplitude; #pragma SIMD_for for (i=0; iamplitude; for (i=0; i tag with value 2. To make it easy to supply values for the type vector, the following macros are supplied: #define AMF_StereoPin(whichPin) \ (AMFPinType_STEREO<<(whichPin*4)) #define AMF_ControlPin(whichPin) \ (AMFPinType_CONTROL<<(whichPin*4)) #define AMF_MonoPin(whichPin) (0) #define AMF_SpectrumRealPin(whichPin) \ (AMFPinType_SPECTRUM_REAL<<(whichPin*4)) #define AMF_SpectrumComplexPin(whichPin) \ (AMFPinType_SPECTRUM_COMPLEX<<(whichPin*4)) #define AMF_SpectrumHalfRealPin(whichPin) \ (AMFPinType_SPECTRUM_HALF_REAL<<(whichPin*4)) #define AMF_SpectrumHalfComplexPin(whichPin) \ (AMFPinType_SPECTRUM_HALF_COMPLEX<<(whichPin*4)) Type descriptors can then be assembled by bitwise OR’ing of these macros. Note that the whichPin argument is zero-based. For example, if a module has one mono input followed by one stereo input, its input type designator could be written as: (AMF_MonoPin(0) | AMF_StereoPin(1)) Alternatively, it could be written directly as 0x10. If there are more than eight pins, then the high order nibble is assumed to be sticky and applies to all pins beyond eight. However, there are situations where this convention is inadequate, such as when a pin greater than the 8th has a type differing from the 8th. For these situations, an indirect form is available as follows: 13 of 51 If the AMF_ModuleClass flags field includes the bit AMFModuleClassFlag_INDIRECT_INPUT_PIN_TYPE, then the input type descriptor is actually a pointer to an array of sufficient length to support bit vectors for all input pins. Similarly, if the flags include the bit AMFModuleClassFlag_INDIRECT_OUTPUT_PIN_TYPE, then the output type descriptor is actually a pointer to an array of sufficient length to support bit vectors for all input pins. In modules with variable number of pins (described in a later section of this document), the input and output type descriptors are in the instance, rather than the class. Example 1A XML File: AMF_Scaler.xml The .xml file describes the module to VisualAudio Designer. In this discussion, we assume a minimal familiarity with XML. Please note that all module xml element type attributes (i.e. type = “string”, type = “float” etc.) are optional as of VisualAudio 1.6 and therefore, are not shown in the examples below. When creating a custom module, we recommend copying the XML file from an existing module, renaming the XML file, and modifying it. At the outermost level, the XML file looks like this: . . . It begins by telling the XML parser where to find the VisualAudio Designer schema, which is used to validate the file.1 Validating the file ensures that it has all the information needed by VisualAudio Designer, that it is structured correctly, that the fields are listed in the proper order, and that it contains legal values for the required fields. The actual module definition is inside the body of the tag, which includes the information detailed below. Module Fields A module has several different self-description tags • The