Farnell PDF LM158, LM258, LM358 - Farnell Element 14

LM158, LM258, LM358-STMicroelectronics - Farnell Element 14 - Revenir à l'accueil

 

 

Branding Farnell element14 (France)

 

Farnell Element 14 :

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Everything You Need To Know About Arduino

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Tutorial 01 for Arduino: Getting Acquainted with Arduino

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The Cube® 3D Printer

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What's easier- DIY Dentistry or our new our website features?

 

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Ben Heck's Getting Started with the BeagleBone Black Trailer

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Ben Heck's Home-Brew Solder Reflow Oven 2.0 Trailer

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Get Started with Pi Episode 3 - Online with Raspberry Pi

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Discover Simulink Promo -- Exclusive element14 Webinar

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Ben Heck's TV Proximity Sensor Trailer

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Ben Heck's PlayStation 4 Teardown Trailer

See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…

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Get Started with Pi Episode 4 - Your First Raspberry Pi Project

Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.

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Ben Heck Anti-Pickpocket Wallet Trailer

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Molex Earphones - The 14 Holiday Products of Newark element14 Promotion

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Tripp Lite Surge Protector - The 14 Holiday Products of Newark element14 Promotion

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Microchip ChipKIT Pi - The 14 Holiday Products of Newark element14 Promotion

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Beagle Bone Black - The 14 Holiday Products of Newark element14 Promotion

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3M E26, LED Lamps - The 14 Holiday Products of Newark element14 Promotion

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3M Colored Duct Tape - The 14 Holiday Products of Newark element14 Promotion

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Tenma Soldering Station - The 14 Holiday Products of Newark element14 Promotion

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Duratool Screwdriver Kit - The 14 Holiday Products of Newark element14 Promotion

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Cubify 3D Cube - The 14 Holiday Products of Newark element14 Promotion

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Bud Boardganizer - The 14 Holiday Products of Newark element14 Promotion

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Raspberry Pi Starter Kit - The 14 Holiday Products of Newark element14 Promotion

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Fluke 323 True-rms Clamp Meter - The 14 Holiday Products of Newark element14 Promotion

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Dymo RHINO 6000 Label Printer - The 14 Holiday Products of Newark element14 Promotion

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3M LED Advanced Lights A-19 - The 14 Holiday Products of Newark element14 Promotion

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Innovative LPS Resistor Features Very High Power Dissipation

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Charge Injection Evaluation Board for DG508B Multiplexer Demo

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Ben Heck The Great Glue Gun Trailer Part 2

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Introducing element14 TV

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Ben Heck Time to Meet Your Maker Trailer

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Détecteur de composants

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Recherche intégrée

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Ben Builds an Accessibility Guitar Trailer Part 1

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Ben Builds an Accessibility Guitar - Part 2 Trailer

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PiFace Control and Display Introduction

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Flashmob Farnell

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Express Yourself in 3D with Cube 3D Printers from Newark element14

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Farnell YouTube Channel Move

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Farnell: Design with the best

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French Farnell Quest

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Altera - 3 Ways to Quickly Adapt to Changing Ethernet Protocols

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Cy-Net3 Network Module

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MC AT - Professional and Precision Series Thin Film Chip Resistors

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Solderless LED Connector

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PSA-T Series Spectrum Analyser: PSA1301T/ PSA2701T

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3-axis Universal Motion Controller For Stepper Motor Drivers: TMC429

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Voltage Level Translation

Puce électronique / Microchip :

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Microchip - 8-bit Wireless Development Kit

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 2 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 3 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 1 of 3

Sans fil - Wireless :

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Microchip - 8-bit Wireless Development Kit

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Wireless Power Solutions - Wurth Electronics, Texas Instruments, CadSoft and element14

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Analog Devices - Remote Water Quality Monitoring via a Low Power, Wireless Network

Texas instrument :

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Texas Instruments - Automotive LED Headlights

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Texas Instruments - Digital Power Solutions

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Texas Instruments - Industrial Sensor Solutions

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Texas Instruments - Wireless Pen Input Demo (Mobile World Congress)

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Texas Instruments - Industrial Automation System Components

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Texas Instruments - TMS320C66x - Industry's first 10-GHz fixed/floating point DSP

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Texas Instruments - TMS320C66x KeyStone Multicore Architecture

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Texas Instruments - Industrial Interfaces

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Texas Instruments - Concerto™ MCUs - Connectivity without compromise

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Texas Instruments - Stellaris Robot Chronos

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Texas Instruments - DRV8412-C2-KIT, Brushed DC and Stepper Motor Control Kit

Ordinateurs :

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Ask Ben Heck - Connect Raspberry Pi to Car Computer

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Ben's Portable Raspberry Pi Computer Trailer

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Ben's Raspberry Pi Portable Computer Trailer 2

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Ben Heck's Pocket Computer Trailer

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Ask Ben Heck - Atari Computer

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Ask Ben Heck - Using Computer Monitors for External Displays

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Raspberry Pi Partnership with BBC Computer Literacy Project - Answers from co-founder Eben Upton

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Installing RaspBMC on your Raspberry Pi with the Farnell element14 Accessory kit

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Raspberry Pi Served - Joey Hudy

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Happy Birthday Raspberry Pi

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Raspberry Pi board B product overview

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Ask Ben Heck - Best Opensource or Free CAD Software

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Tektronix FPGAView™ software makes debugging of FPGAs faster than ever!

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Ask Ben Heck - Best Open-Source Schematic Capture and PCB Layout Software

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Introduction to Cadsoft EAGLE PCB Design Software in Chinese

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Altera - Developing Software for Embedded Systems on FPGAs

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Ben Heck The Great Glue Gun Trailer Part 1

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the knode tutorial - element14

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Ben's Autodesk 123D Tutorial Trailer

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Ben's CadSoft EAGLE Tutorial Trailer

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Ben Heck's AVR Dev Board tutorial

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Ben Heck's Interface Tutorial Trailer

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Energy Harvesting Challenge

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New Features of CadSoft EAGLE v6

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LM158, LM258, LM358 Low-power dual operational amplifiers Datasheet - production data Features • Internally frequency-compensated • Large DC voltage gain: 100 dB • Wide bandwidth (unity gain): 1.1 MHz (temperature compensated) • Very low supply current per operator essentially independent of supply voltage • Low input bias current: 20 nA (temperature compensated) • Low input offset voltage: 2 mV • Low input offset current: 2 nA • Input common-mode voltage range includes negative rails • Differential input voltage range equal to the power supply voltage • Large output voltage swing 0 V to (VCC + -1.5 V) Description These circuits consist of two independent, high-gain, internally frequency-compensated op-amps, specifically designed to operate from a single power supply over a wide range of voltages. The low-power supply drain is independent of the magnitude of the power supply voltage. Application areas include transducer amplifiers, DC gain blocks and all the conventional op-amp circuits, which can now be more easily implemented in single power supply systems. For example, these circuits can be directly supplied with the standard +5 V, which is used in logic systems and will easily provide the required interface electronics with no additional power supply. In linear mode, the input common-mode voltage range includes ground and the output voltage can also swing to ground, even though operated from only a single power supply voltage. DIP8 (Plastic package) SO8 and MiniSO8 (Plastic micropackage) TSSOP8 (Thin shrink small outline package) Pin connections (Top view) 1 2 3 Out1 In1- In1+ Vcc- 4 8 7 6 Vcc+ Out2 In2- 5 In2+ DFN8 2 x 2 mm (Plastic micropackage) www.st.com Contents LM158, LM258, LM358 2/22 DocID2163 Rev 11 Contents 1 Schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1 DIP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2 SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3 MiniSO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.4 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.5 DFN8 2 x 2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DocID2163 Rev 11 3/22 LM158, LM258, LM358 Schematic diagram 22 1 Schematic diagram Figure 1. Schematic diagram (1/2 LM158) 6μA 4μA 100μA Q2 Q3 Q1 Q4 Inverting input Non-inverting input Q8 Q9 Q10 Q11 Q12 50μA Q13 Output Q7 Q6 Q5 R SC VCC CC GND Absolute maximum ratings LM158, LM258, LM358 4/22 DocID2163 Rev 11 2 Absolute maximum ratings Table 1. Absolute maximum ratings Symbol Parameter LM158,A LM258,A LM358,A Unit VCC Supply voltage +/-16 or 32 V Vi Input voltage 32 V Vid Differential input voltage 32 V Output short-circuit duration (1) 1. Short-circuits from the output to VCC can cause excessive heating if VCC > 15 V. The maximum output current is approximately 40 mA independent of the magnitude of VCC. Destructive dissipation can result from simultaneous short circuits on all amplifiers. Infinite Iin Input current (2) 2. This input current only exists when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP transistor becoming forward-biased and thereby acting as input diode clamp. In addition to this diode action, there is NPN parasitic action on the IC chip. This transistor action can cause the output voltages of the Op-amps to go to the VCC voltage level (or to ground for a large overdrive) for the time during which an input is driven negative. This is not destructive and normal output is restored for input voltages above -0.3 V. 5 mA in DC or 50 mA in AC (duty cycle = 10%, T=1s) mA Toper Operating free-air temperature range -55 to +125 -40 to +105 0 to +70 °C Tstg Storage temperature range -65 to +150 °C Tj Maximum junction temperature 150 °C Rthja Thermal resistance junction to ambient(3) SO8 MiniSO8 TSSOP8 DIP8 DFN8 2x2 3. Short-circuits can cause excessive heating and destructive dissipation. Rth are typical values. 125 190 120 85 57 °C/W Rthjc Thermal resistance junction to case (3) SO8 MiniSO8 TSSOP8 DIP8 40 39 37 41 °C/W ESD HBM: human body model(4) 4. Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a 1.5 kW resistor between two pins of the device. This is done for all couples of connected pin combinations while the other pins are floating. 300 V MM: machine model(5) 5. Machine model: a 200 pF capacitor is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5 W). This is done for all couples of connected pin combinations while the other pins are floating. 200 V CDM: charged device model(6) 6. Charged device model: all pins and the package are charged together to the specified voltage and then discharged directly to the ground through only one pin. This is done for all pins. 1.5 kV DocID2163 Rev 11 5/22 LM158, LM258, LM358 Operating conditions 22 3 Operating conditions Table 2. Operating conditions Symbol Parameter Value Unit VCC Supply voltage 3 to 30 V Vicm Common mode input voltage range(1) 1. When used in comparator, the functionality is guaranteed as long as at least one input remains within the operating common mode voltage range. VCC - -0.3 to VCC + -1.5 V Toper Operating free air temperature range LM158 LM258 LM358 -55 to +125 -40 to +105 0 to +70 °C Electrical characteristics LM158, LM258, LM358 6/22 DocID2163 Rev 11 4 Electrical characteristics Table 3. Electrical characteristics for VCC + = +5 V, VCC - = Ground, Vo = 1.4 V, Tamb = +25°C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit Vio Input offset voltage (1) LM158A LM258A, LM358A LM158, LM258 LM358 1 2 2357 mV Tmin £ Tamb £ Tmax LM158A, LM258A, LM358A LM158, LM258 LM358 479 DVio Input offset voltage drift LM158A, LM258A, LM358A LM158, LM258, LM358 77 15 30 μV/°C Iio Input offset current LM158A, LM258A, LM358A LM158, LM258, LM358 Tmin £ Tamb £ Tmax LM158A, LM258A, LM358A LM158, LM258, LM358 22 10 30 30 40 nA DIio Input offset current drift LM158A, LM258A, LM358A LM158, LM258, LM358 10 10 200 300 pA/°C Iib Input bias current (2) LM158A, LM258A, LM358A LM158, LM258, LM358 Tmin £ Tamb £ Tmax LM158A, LM258A, LM358A LM158, LM258, LM358 20 20 50 150 100 200 nA Avd Large signal voltage gain VCC += +15 V, RL = 2 kW, Vo = 1.4 V to 11.4 V Tmin £ Tamb £ Tmax 50 25 100 V/mV SVR Supply voltage rejection ratio VCC + = 5 V to 30 V, Rs £ 10 kW Tmin £ Tamb £ Tmax 65 65 100 dB ICC Supply current, all amp, no load Tmin £ Tamb £ Tmax VCC + = +5 V Tmin £ Tamb £ Tmax VCC + = +30 V 0.7 1.2 2 mA Vicm Input common mode voltage range VCC += +30 V (3) Tmin £ Tamb £ Tmax 0 0 VCC + -1.5 VCC + -2 V DocID2163 Rev 11 7/22 LM158, LM258, LM358 Electrical characteristics 22 CMR Common mode rejection ratio Rs £ 10 kW Tmin £ Tamb £ Tmax 70 60 85 dB Isource Output current source VCC + = +15 V, Vo = +2 V, Vid = +1 V 20 40 60 mA Isink Output sink current VCC + = +15 V, Vo = +2 V, Vid = -1 V VCC + = +15 V, Vo = +0.2 V, Vid = -1 V 10 12 20 50 mA μA VOH High level output voltage RL = 2 kW, VCC + = 30 V Tmin £ Tamb £ Tmax RL = 10 kW, VCC + = 30 V Tmin £ Tamb £ Tmax 26 26 27 27 27 28 V VOL Low level output voltage RL = 10 kW Tmin £ Tamb £ Tmax 5 20 20 mV SR Slew rate VCC + = 15 V, Vi = 0.5 to 3 V, RL = 2 kW, CL = 100 pF, unity gain 0.3 0.6 V/μs GBP Gain bandwidth product VCC + = 30 V, f = 100 kHz, Vin = 10 mV, RL = 2 kW, CL = 100 pF 0.7 1.1 MHz THD Total harmonic distortion f = 1 kHz, Av = 20 dB, RL = 2 kW, Vo = 2 Vpp, CL = 100 pF, VO = 2 Vpp 0.02 % en Equivalent input noise voltage f = 1 kHz, Rs = 100 W, VCC + = 30 V 55 Vo1/Vo2 Channel separation(4) 1 kHz £ f £ 20 kHz 120 dB 1. Vo = 1.4 V, Rs = 0 W, 5 V < VCC + < 30 V, 0 < Vic < VCC + - 1.5 V 2. The direction of the input current is out of the IC. This current is essentially constant, independent of the state of the output so there is no change in the load on the input lines. 3. The input common-mode voltage of either input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of the common-mode voltage range is VCC + - 1.5 V, but either or both inputs can go to +32 V without damage. 4. Due to the proximity of external components, ensure that stray capacitance between these external parts does not cause coupling. Typically, this can be detected because this type of capacitance increases at higher frequencies. Table 3. Electrical characteristics for VCC + = +5 V, VCC - = Ground, Vo = 1.4 V, Tamb = +25°C (unless otherwise specified) (continued) Symbol Parameter Min. Typ. Max. Unit nV Hz ----------- Electrical characteristics LM158, LM258, LM358 8/22 DocID2163 Rev 11 Figure 2. Open-loop frequency response Figure 3. Large signal frequency response VOLTAGE GAIN (dB) 1.0 10 100 1k 10k 100k 1M 10M VCC = +10 to +15 V & FREQUENCY (Hz) 10 M􀀷 VI VCC/2 VCC = 30 V & -55°C 0.1 􀁍F VCC VO - + -55°C Tamb +125°C 140 120 100 80 60 40 20 0 Tamb +125°C - + OUTPUT SWING (Vpp) 1k 10k 100k 1M FREQUENCY (Hz) 100 k􀀷 VI 1 k􀀷 VO 20 15 10 5 0 2 k􀀷 +15 V +7 V Figure 4. Voltage follower pulse response with VCC = 15 V Figure 5. Voltage follower pulse response with VCC = 30 V INPUT VOLTAGE (V) TIME (􀁍s) RL 2 k􀀷 OUTPUT VOLTAGE (V) 4 3 2 1 0 3 2 1 VCC = +15 V 0 10 20 30 40 Input Output 50 pF + - OUTPUT VOLTAGE (mV) 0 1 2 3 4 5 6 7 8 TIME (􀁍s) eI Tamb = +25°C VCC = 30 V 500 450 400 350 300 250 eO Figure 6. Input current Figure 7. Output voltage vs sink current INPUT CURRENT (mA) TEMPERATURE (°C) -55 -35 -15 5 25 45 65 85 105 125 90 80 70 60 50 40 30 20 10 0 VCC = +30 V VCC = +15 V VCC = +5 V VI = 0 V - + OUTPUT VOLTAGE (v) 0.001 0.01 0.1 1 10 100 OUTPUT SINK CURRENT (mA) VO VCC/2 VCC = +5 V VCC = +15 V VCC = +30 V VCC IO 10 1 0.1 0.01 Tamb = + 25°C DocID2163 Rev 11 9/22 LM158, LM258, LM358 Electrical characteristics 22 Figure 8. Output voltage vs source current Figure 9. Current limiting + - OUTPUT VOLTAGE REFERENCED TO VCC+ (V) 0.001 0.01 0.1 1 10 100 OUTPUT SOURCE CURRENT (mA) VO Independent of VCC VCC/2 IO 8 5 2 1 Tamb = + 25°C VCC 7 6 4 3 - + OUTPUT CURRENT (mA) -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE °C IO 90 80 50 40 30 20 10 0 70 60 Figure 10. Input voltage range Figure 11. Open-loop gain Figure 12. Supply current Figure 13. Input current Negative Positive INPUT VOLTAGE (V) 0 5 10 15 POWER SUPPLY VOLTAGE (±V) 10 5 15 VOLTAGE GAIN (dB) POSITIVE SUPPLY VOLTAGE (V) 0 10 20 30 40 120 40 160 80 RL = 20 k􀀷 RL = 2 k􀀷 - + SUPPLY CURRENT (mA) 0 10 20 30 POSITIVE SUPPLY VOLTAGE (V) mA VCC ID Tamb = 0°C to +125°C 4 3 2 1 Tamb = -55°C INPUT CURRENT (nA) 0 10 20 30 POSITIVE SUPPLY VOLTAGE (V) 100 75 50 25 Tamb = +25°C Electrical characteristics LM158, LM258, LM358 10/22 DocID2163 Rev 11 Figure 14. Gain bandwidth product Figure 15. Power supply rejection ratio GAIN BANDWIDTH PRODUCT (MHz) -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (°C) 1.05 0.45 0.3 0.15 VCC = ± 15 V 1.2 0.9 0.75 0.6 1.35 1.5 0 POWER SUPPLY REJECTION RATIO (dB) SVR -55 -35 -15 5 25 45 65 85 105 125 100 80 75 70 105 95 90 85 110 115 65 TEMPERATURE (°C) 60 Figure 16. Common-mode rejection ratio Figure 17. Phase margin vs. capacitive load COMMON MODE REJECTION RATIO (dB) -55 -35 -15 5 25 45 65 85 105 125 100 80 75 70 105 95 90 85 110 115 65 TEMPERATURE (°C) 60 Phase Margin at Vcc=15V and Vicm=7.5V Vs. Iout and Capacitive load value DocID2163 Rev 11 11/22 LM158, LM258, LM358 Typical applications 22 5 Typical applications Single supply voltage VCC = +5 VDC. Figure 18. AC-coupled inverting amplifier Figure 19. Non-inverting DC amplifier 1/2 LM158 ~ 0 2VPP R 10k L Co eo R 6.2k B R 100k f R1 CI 10k eI VCC R2 100k C1 10F R3 100k A =- R V R1 f (as shown AV = -10) R1 10k R2 1M 1/2 LM158 10k eI eO +5V e O (V) (mV) 0 AV= 1 + R2 R1 (As shown AV = 101) Figure 20. AC-coupled non-inverting amplifier Figure 21. DC summing amplifier 1/2 LM158 ~ 0 2VPP R 10k L Co eo R 6.2k B C1 0.1F eI VCC (as shown AV = 11) A = 1 +R2 V R1 R1 100k R2 1M CI R3 1M R4 100k R5 100k C2 10F 1/2 LM158 eO e 4 e 3 e 2 e 1 100k 100k 100k 100k 100k 100k eo = e1 + e2 - e3 - e4 where (e1 + e2) ≥ (e3 + e4) to keep eo ≥ 0V Figure 22. High input Z, DC differential amplifier Figure 23. High input Z adjustable gain DC instrumentation amplifier R1 100k R2 100k R4 100k R3 100k +V2 +V1 Vo 1/2 LM158 1/2 LM158 if R1 = R5 and R3 = R4 = R6 = R7 eo = [1 + ] ( (e2 + e1) As shown eo = 101 (e2 + e1) 2R1 R2 ----------- R3 100k eO 1/2 LM158 R1 100k e 1 R7 100k R6 100k R5 100k e 2 R2 2k Gain adjust R4 100k 1/2 LM158 1/2 LM158 if R1 = R5 and R3 = R4 = R6 = R7 eo = [ 1 + ] ( (e2 + e1) As shown eo = 101 (e2 + e1) 2R1 R2 ----------- Typical applications LM158, LM258, LM358 12/22 DocID2163 Rev 11 Figure 24. Using symmetrical amplifiers to reduce input current Figure 25. Low drift peak detector Figure 26. Active band-pass filter 1/2 LM158 IB 2N 929 0.001F IB 3M IB I eo I e I IB IB Input current compensation 1.5M 1/2 LM158 IB 2N 929 0.001F IB 3R 3M IB Input current compensation eo IB e I 1/2 LM158 Zo ZI C 1F 2IB R 1M 2IB 1/2 LM158 1/2 LM158 1/2 LM158 R8 100k C3 10F R7 100k R5 470k C1 330pF Vo VCC R6 470k C2 330pF R4 10M R1 100k R2 100k +V1 R3 100k 1/2 LM158 1/2 LM158 DocID2163 Rev 11 13/22 LM158, LM258, LM358 Package information 22 6 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Package information LM158, LM258, LM358 14/22 DocID2163 Rev 11 6.1 DIP8 package information Figure 27. DIP8 package mechanical drawing Table 4. DIP8 package mechanical data Ref. Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 5.33 0.210 A1 0.38 0.015 A2 2.92 3.30 4.95 0.115 0.130 0.195 b 0.36 0.46 0.56 0.014 0.018 0.022 b2 1.14 1.52 1.78 0.045 0.060 0.070 c 0.20 0.25 0.36 0.008 0.010 0.014 D 9.02 9.27 10.16 0.355 0.365 0.400 E 7.62 7.87 8.26 0.300 0.310 0.325 E1 6.10 6.35 7.11 0.240 0.250 0.280 e 2.54 0.100 eA 7.62 0.300 eB 10.92 0.430 L 2.92 3.30 3.81 0.115 0.130 0.150 DocID2163 Rev 11 15/22 LM158, LM258, LM358 Package information 22 6.2 SO8 package information Figure 28. SO8 package mechanical drawing Table 5. SO8 package mechanical data Ref. Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 1.75 0.069 A1 0.10 0.25 0.004 0.010 A2 1.25 0.049 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.010 D 4.80 4.90 5.00 0.189 0.193 0.197 E 5.80 6.00 6.20 0.228 0.236 0.244 E1 3.80 3.90 4.00 0.150 0.154 0.157 e 1.27 0.050 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 L1 1.04 0.040 k 1° 8° 1° 8° ccc 0.10 0.004 Package information LM158, LM258, LM358 16/22 DocID2163 Rev 11 6.3 MiniSO8 package information Figure 29. MiniSO8 package mechanical drawing Table 6. MiniSO8 package mechanical data Ref. Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 1.1 0.043 A1 0 0.15 0 0.006 A2 0.75 0.85 0.95 0.030 0.033 0.037 b 0.22 0.40 0.009 0.016 c 0.08 0.23 0.003 0.009 D 2.80 3.00 3.20 0.11 0.118 0.126 E 4.65 4.90 5.15 0.183 0.193 0.203 E1 2.80 3.00 3.10 0.11 0.118 0.122 e 0.65 0.026 L 0.40 0.60 0.80 0.016 0.024 0.031 L1 0.95 0.037 L2 0.25 0.010 k 0° 8° 0° 8° ccc 0.10 0.004 DocID2163 Rev 11 17/22 LM158, LM258, LM358 Package information 22 6.4 TSSOP8 package information Figure 30. TSSOP8 package mechanical drawing Table 7. TSSOP8 package mechanical data Ref. Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 1.2 0.047 A1 0.05 0.15 0.002 0.006 A2 0.80 1.00 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.008 D 2.90 3.00 3.10 0.114 0.118 0.122 E 6.20 6.40 6.60 0.244 0.252 0.260 E1 4.30 4.40 4.50 0.169 0.173 0.177 e 0.65 0.0256 k 0° 8° 0° 8° L 0.45 0.60 0.75 0.018 0.024 0.030 L1 1 0.039 aaa 0.1 0.004 Package information LM158, LM258, LM358 18/22 DocID2163 Rev 11 6.5 DFN8 2 x 2 package mechanical data Figure 31. DFN8 2 x 2 package mechanical drawing Table 8. DFN8 2 x 2 x 0.6 mm package mechanical data (pitch 0.5 mm) Ref. Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 0.51 0.55 0.60 0.020 0.022 0.024 A1 0.05 0.002 A3 0.15 0.006 b 0.18 0.25 0.30 0.007 0.010 0.012 D 1.85 2.00 2.15 0.073 0.079 0.085 D2 1.45 1.60 1.70 0.057 0.063 0.067 E 1.85 2.00 2.15 0.073 0.079 0.085 E2 0.75 0.90 1.00 0.030 0.035 0.039 e 0.50 0.020 L 0.50 0.020 ddd 0.08 0.003 DocID2163 Rev 11 19/22 LM158, LM258, LM358 Package information 22 Figure 32. DFN8 2 x 2 footprint recommendation Ordering information LM158, LM258, LM358 20/22 DocID2163 Rev 11 7 Ordering information Table 9. Order codes Order code Temperature range Package Packaging Marking LM158N -55°C, +125°C DIP8 Tube LM158N LM158QT DFN8 2x2 Tape and reel K4A LM158DT SO8 158 LM258AN LM258N -40°C, +105°C DIP8 Tube LM258A LM258N LM258ADT SO8 Tape and reel 258A LM258AYDT(1) SO8 Automotive grade 258AY LM258D LM258DT SO8 Tube or tape and reel 258 Tape and reel LM258PT LM258APT TSSOP8 258 258A LM258YPT(2) LM258AYPT(2) TSSOP8 Automotive grade 258Y 258AY LM258AST LM258ST MiniSO8 K408 K416 LM258QT DFN8 2x2 K4C LM358N LM358AN 0°C, +70°C DIP8 Tube LM358N LM358AN LM358D LM358DT SO8 Tube or tape and reel 358 LM358YDT(1) SO8 Automotive grade Tape and reel 358Y LM358AD LM358ADT SO8 Tube or tape and reel 358A LM358PT LM358APT TSSOP8 Tape and reel 358 358A LM358YPT(2) LM358AYPT(2) TSSOP8 Automotive grade 358Y 358AY LM358ST LM358AST MiniSO8 K405 K404 LM358QT DFN8 2x2 K4E 1. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 & Q 002 or equivalent are qualified. 2. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 & Q 002 or equivalent are on-going. DocID2163 Rev 11 21/22 LM158, LM258, LM358 Revision history 22 8 Revision history Table 10. Document revision history Date Revision Changes 01-Jul- 2003 1 First release. 02-Jan-2005 2 Rthja and Tj parameters added in AMR Table 1 on page 4. 01-Jul-2005 3 ESD protection inserted in Table 1 on page 4. 05-Oct-2006 4 Added Figure 17: Phase margin vs. capacitive load. 30-Nov-2006 5 Added missing ordering information. 25-Apr-2007 6 Removed LM158A, LM258A and LM358A from document title. Corrected error in MiniSO-8 package data. L1 is 0.004 inch. Added automotive grade order codes in Section 7 on page 20. 12-Feb-2008 7 Corrected VCC max (30 V instead of 32 V) in operating conditions. Changed presentation of electrical characteristics table. Deleted Vopp parameter in electrical characteristics table. Corrected miniSO-8 package information. Corrected temperature range for automotive grade order codes. Updated automotive grade footnotes in order codes table. 26-Aug-2008 8 Added limitations on input current in Table 1: Absolute maximum ratings. Corrected title for Figure 11. Added E and L1 parameters in Table 5: SO8 package mechanical data. Changed Figure 30. 02-Sep-2011 9 In Chapter 6: Package information, added: – DFN8 2 x 2 mm package mechanical drawing – DFN8 2 x 2 mm recommended footprint – DFN8 2 x 2 mm order codes. 06-Apr-2012 10 Removed order codes LM158YD, LM258AYD, LM258YD and LM358YD from Table 9: Order codes. 11-Jun-2013 11 Table 9: Order codes: removed order codes LM158D, LM158YDT, LM258YDT, and LM258AD; added automotive grade qualification to order codes LM258ATDT and LM358YDT; updated marking for order codes LM158DT and LM258D/LM258DT; updated temperature range, packages, and packaging for several order codes. LM158, LM258, LM358 22/22 DocID2163 Rev 11 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. 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WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2013 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com L78 Positive voltage regulator ICs Datasheet - production data Features • Output current up to 1.5 A • Output voltages of 5; 6; 8; 8.5; 9; 12; 15; 18; 24 V • Thermal overload protection • Short circuit protection • Output transition SOA protection • 2 % output voltage tolerance (A version) • Guaranteed in extended temperature range (A version) Description The L78 series of three-terminal positive regulators is available in TO-220, TO-220FP, D²PAK and DPAK packages and several fixed output voltages, making it useful in a wide range of applications. These regulators can provide local on-card regulation, eliminating the distribution problems associated with single point regulation. Each type embeds internal current limiting, thermal shutdown and safe area protection, making it essentially indestructible. If adequate heat sinking is provided, they can deliver over 1 A output current. Although designed primarily as fixed voltage regulators, these devices can be used with external components to obtain adjustable voltage and currents. TO-220 TO-220FP DPAK D²PAK www.st.com Contents Positive voltage regulator ICs 2/58 DocID2143 Rev 32 Contents 1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1 Design consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 Typical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 DocID2143 Rev 32 3/58 Positive voltage regulator ICs List of tables 58 List of tables Table 1. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Electrical characteristics of L7805A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4. Electrical characteristics of L7806A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 5. Electrical characteristics of L7808A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 6. Electrical characteristics of L7809A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 7. Electrical characteristics of L7812A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 8. Electrical characteristics of L7815A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 9. Electrical characteristics of L7824A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 10. Electrical characteristics of L7805C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 11. Electrical characteristics of L7806C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 12. Electrical characteristics of L7808C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 13. Electrical characteristics of L7885C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 14. Electrical characteristics of L7809C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 15. Electrical characteristics of L7812C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 16. Electrical characteristics of L7815C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 17. Electrical characteristics of L7818C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 18. Electrical characteristics of L7824C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 19. TO-220 (dual gauge) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 20. TO-220 SG (single gauge) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 21. TO-220FP mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 22. DPAK mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 23. D²PAK (SMD 2L STD-ST) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 24. D²PAK (SMD 2L Wooseok-subcon.) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 25. DPAK and D²PAK tape and reel mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 26. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 27. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 List of figures Positive voltage regulator ICs 4/58 DocID2143 Rev 32 List of figures Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Schematic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. Application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5. DC parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6. Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7. Ripple rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8. Fixed output regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 9. Current regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 10. Circuit for increasing output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 11. Adjustable output regulator (7 to 30 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 12. 0.5 to 10 V regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 13. High current voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 14. High output current with short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 15. Tracking voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 16. Split power supply (± 15 V - 1 A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 17. Negative output voltage circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 18. Switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 19. High input voltage circuit (configuration 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 20. High input voltage circuit (configuration 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 21. High input and output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 22. Reducing power dissipation with dropping resistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 23. Remote shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 24. Power AM modulator (unity voltage gain, IO £ 0.5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 25. Adjustable output voltage with temperature compensation . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 26. Light controllers (VO(min) = VXX + VBE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 27. Protection against input short-circuit with high capacitance loads . . . . . . . . . . . . . . . . . . . 34 Figure 28. Dropout voltage vs. junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 29. Peak output current vs. input/output differential voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 30. Supply voltage rejection vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 31. Output voltage vs. junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 32. Output impedance vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 33. Quiescent current vs. junction temp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 34. Load transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 35. Line transient response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 36. Quiescent current vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 37. TO-220 (dual gauge) drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 38. TO-220 SG (single gauge) drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 39. TO-220FP drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 40. DPAK drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 41. DPAK footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 42. D²PAK (SMD 2L STD-ST) type A drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 43. D²PAK (SMD 2L Wooseok-subcon.) drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 44. D²PAK (SMD 2L Wooseok-subcon.) footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 45. Tube for TO-220 (dual gauge) (mm.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 46. Tube for TO-220 (single gauge) (mm.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 47. Tape for DPAK and D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 48. Reel for DPAK and D2PAK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 DocID2143 Rev 32 5/58 Positive voltage regulator ICs Diagram 58 1 Diagram Figure 1. Block diagram Pin configuration Positive voltage regulator ICs 6/58 DocID2143 Rev 32 2 Pin configuration Figure 2. Pin connections (top view) Figure 3. Schematic diagram DocID2143 Rev 32 7/58 Positive voltage regulator ICs Maximum ratings 58 3 Maximum ratings Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. Table 1. Absolute maximum ratings Symbol Parameter Value Unit VI DC input voltage for VO= 5 to 18 V 35 V for VO= 20, 24 V 40 IO Output current Internally limited PD Power dissipation Internally limited TSTG Storage temperature range -65 to 150 °C TOP Operating junction temperature range for L78xxC, L78xxAC 0 to 125 °C for L78xxAB -40 to 125 Table 2. Thermal data Symbol Parameter D²PAK DPAK TO-220 TO-220FP Unit RthJC Thermal resistance junction-case 3 8 5 5 °C/W RthJA Thermal resistance junction-ambient 62.5 100 50 60 °C/W Figure 4. Application circuits Test circuits Positive voltage regulator ICs 8/58 DocID2143 Rev 32 4 Test circuits Figure 5. DC parameter Figure 6. Load regulation Figure 7. Ripple rejection DocID2143 Rev 32 9/58 Positive voltage regulator ICs Electrical characteristics 58 5 Electrical characteristics VI = 10 V, IO = 1 A, TJ = 0 to 125 °C (L7805AC), TJ = -40 to 125 °C (L7805AB), unless otherwise specified(a). a. Minimum load current for regulation is 5 mA. Table 3. Electrical characteristics of L7805A Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 4.9 5 5.1 V VO Output voltage IO = 5 mA to 1 A, VI = 7.5 to 18 V 4.8 5 5.2 V VO Output voltage IO = 1 A, VI = 18 to 20 V, TJ = 25°C 4.8 5 5.2 V ΔVO (1) Line regulation VI = 7.5 to 25 V, IO = 500 mA, TJ = 25°C 7 50 mV VI = 8 to 12 V 10 50 mV VI = 8 to 12 V, TJ = 25°C 2 25 mV VI = 7.3 to 20 V, TJ = 25°C 7 50 mV ΔVO (1) Load regulation IO = 5 mA to 1 A 25 100 IO = 5 mA to 1.5 A, TJ = 25°C 30 100 mV IO = 250 to 750 mA 8 50 Iq Quiescent current TJ = 25°C 4.3 6 mA 6 mA ΔIq Quiescent current change VI = 8 to 23 V, IO = 500 mA 0.8 mA VI = 7.5 to 20 V, TJ = 25°C 0.8 mA IO = 5 mA to 1 A 0.5 mA SVR Supply voltage rejection VI = 8 to 18 V, f = 120 Hz, IO = 500 mA 68 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V eN Output noise voltage TA = 25°C, B =10 Hz to 100 kHz 10 μV/VO RO Output resistance f = 1 kHz 17 mΩ Isc Short circuit current VI = 35 V, TA = 25°C 0.2 A Iscp Short circuit peak current TJ = 25°C 2.2 A ΔVO/ΔT Output voltage drift -1.1 mV/°C 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. Electrical characteristics Positive voltage regulator ICs 10/58 DocID2143 Rev 32 VI = 11 V, IO = 1 A, TJ = 0 to 125 °C (L7806AC), TJ = -40 to 125 °C (L7806AB), unless otherwise specified(b). b. Minimum load current for regulation is 5 mA. Table 4. Electrical characteristics of L7806A Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 5.88 6 6.12 V VO Output voltage IO = 5 mA to 1 A, VI = 8.6 to 19 V 5.76 6 6.24 V VO Output voltage IO = 1 A, VI = 19 to 21 V, TJ = 25°C 5.76 6 6.24 V ΔVO (1) Line regulation VI = 8.6 to 25 V, IO = 500 mA, TJ = 25°C 9 60 mV VI = 9 to 13 V 11 60 mV VI = 9 to 13 V, TJ = 25°C 3 30 mV VI = 8.3 to 21 V, TJ = 25°C 9 60 mV ΔVO (1) Load regulation IO = 5 mA to 1 A 25 100 IO = 5 mA to 1.5 A, TJ = 25°C 30 100 mV IO = 250 to 750 mA 10 50 Iq Quiescent current TJ = 25°C 4.3 6 mA 6 mA ΔIq Quiescent current change VI = 9 to 24 V, IO = 500 mA 0.8 mA VI = 8.6 to 21 V, TJ = 25°C 0.8 mA IO = 5 mA to 1 A 0.5 mA SVR Supply voltage rejection VI = 9 to 19 V, f = 120 Hz, IO = 500 mA 65 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V eN Output noise voltage TA = 25°C, B =10 Hz to 100 kHz 10 μV/VO RO Output resistance f = 1 kHz 17 mΩ Isc Short circuit current VI = 35 V, TA = 25°C 0.2 A Iscp Short circuit peak current TJ = 25°C 2.2 A ΔVO/ΔT Output voltage drift -0.8 mV/°C 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. DocID2143 Rev 32 11/58 Positive voltage regulator ICs Electrical characteristics 58 VI = 14 V, IO = 1 A, TJ = 0 to 125 °C (L7808AC), TJ = -40 to 125 °C (L7808AB), unless otherwise specified(c). c. Minimum load current for regulation is 5 mA. Table 5. Electrical characteristics of L7808A Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 7.84 8 8.16 V VO Output voltage IO = 5 mA to 1 A, VI = 10.6 to 21 V 7.7 8 8.3 V VO Output voltage IO = 1 A, VI = 21 to 23 V, TJ = 25°C 7.7 8 8.3 V ΔVO (1) Line regulation VI = 10.6 to 25 V, IO = 500 mA, TJ = 25°C 12 80 mV VI = 11 to 17 V 15 80 mV VI = 11 to 17 V, TJ = 25°C 5 40 mV VI = 10.4 to 23 V, TJ = 25°C 12 80 mV ΔVO (1) Load regulation IO = 5 mA to 1 A 25 100 IO = 5 mA to 1.5 A, TJ = 25°C 30 100 mV IO = 250 to 750 mA 10 50 Iq Quiescent current TJ = 25°C 4.3 6 mA 6 mA ΔIq Quiescent current change VI = 11 to 23 V, IO = 500 mA 0.8 mA VI = 10.6 to 23 V, TJ = 25°C 0.8 mA IO = 5 mA to 1 A 0.5 mA SVR Supply voltage rejection VI = 11.5 to 21.5 V, f = 120 Hz, IO = 500 mA 62 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V eN Output noise voltage TA = 25°C, B =10 Hz to 100 kHz 10 μV/VO RO Output resistance f = 1 kHz 18 mΩ Isc Short circuit current VI = 35 V, TA = 25°C 0.2 A Iscp Short circuit peak current TJ = 25°C 2.2 A ΔVO/ΔT Output voltage drift -0.8 mV/°C 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. Electrical characteristics Positive voltage regulator ICs 12/58 DocID2143 Rev 32 VI = 15 V, IO = 1 A, TJ = 0 to 125 °C (L7809AC), TJ = -40 to 125 °C (L7809AB), unless otherwise specified(d). d. Minimum load current for regulation is 5 mA. Table 6. Electrical characteristics of L7809A Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 8.82 9 9.18 V VO Output voltage IO = 5 mA to 1 A, VI = 10.6 to 22 V 8.65 9 9.35 V VO Output voltage IO = 1 A, VI = 22 to 24 V, TJ = 25°C 8.65 9 9.35 V ΔVO (1) Line regulation VI = 10.6 to 25 V, IO = 500 mA, TJ = 25°C 12 90 mV VI = 11 to 17 V 15 90 mV VI = 11 to 17 V, TJ = 25°C 5 45 mV VI = 11.4 to 23 V, TJ = 25°C 12 90 mV ΔVO (1) Load regulation IO = 5 mA to 1 A 25 100 IO = 5 mA to 1.5 A, TJ = 25°C 30 100 mV IO = 250 to 750 mA 10 50 Iq Quiescent current TJ = 25°C 4.3 6 mA 6 mA ΔIq Quiescent current change VI = 11 to 25 V, IO = 500 mA 0.8 mA VI = 10.6 to 23 V, TJ = 25°C 0.8 mA IO = 5 mA to 1 A 0.5 mA SVR Supply voltage rejection VI = 11.5 to 21.5 V, f = 120 Hz, IO = 500 mA 61 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V eN Output noise voltage TA = 25°C, B =10 Hz to 100 kHz 10 μV/VO RO Output resistance f = 1 kHz 18 mΩ Isc Short circuit current VI = 35 V, TA = 25°C 0.2 A Iscp Short circuit peak current TJ = 25°C 2.2 A ΔVO/ΔT Output voltage drift -0.8 mV/°C 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. DocID2143 Rev 32 13/58 Positive voltage regulator ICs Electrical characteristics 58 VI = 19 V, IO = 1 A, TJ = 0 to 125 °C (L7812AC), TJ = -40 to 125 °C (L7812AB), unless otherwise specified(e). e. Minimum load current for regulation is 5 mA. Table 7. Electrical characteristics of L7812A Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 11.75 12 12.25 V VO Output voltage IO = 5 mA to 1 A, VI = 14.8 to 25 V 11.5 12 12.5 V VO Output voltage IO = 1 A, VI = 25 to 27 V, TJ = 25°C 11.5 12 12.5 V ΔVO (1) Line regulation VI = 14.8 to 30 V, IO = 500 mA, TJ = 25°C 13 120 mV VI = 16 to 12 V 16 120 mV VI = 16 to 12 V, TJ = 25°C 6 60 mV VI = 14.5 to 27 V, TJ = 25°C 13 120 mV ΔVO (1) Load regulation IO = 5 mA to 1 A 25 100 IO = 5 mA to 1.5 A, TJ = 25°C 30 100 mV IO = 250 to 750 mA 10 50 Iq Quiescent current TJ = 25°C 4.4 6 mA 6 mA ΔIq Quiescent current change VI = 15 to 30 V, IO = 500 mA 0.8 mA VI = 14.8 to 27 V, TJ = 25°C 0.8 mA IO = 5 mA to 1 A 0.5 mA SVR Supply voltage rejection VI = 15 to 25 V, f = 120 Hz, IO = 500 mA 60 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V eN Output noise voltage TA = 25°C, B = 10 Hz to 100 kHz 10 μV/VO RO Output resistance f = 1 kHz 18 mΩ Isc Short circuit current VI = 35 V, TA = 25°C 0.2 A Iscp Short circuit peak current TJ = 25°C 2.2 A ΔVO/ΔT Output voltage drift -1 mV/°C 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. Electrical characteristics Positive voltage regulator ICs 14/58 DocID2143 Rev 32 VI = 23 V, IO = 1 A, TJ = 0 to 125 °C (L7815AC), TJ = -40 to 125 °C (L7815AB), unless otherwise specified(f). f. Minimum load current for regulation is 5 mA. Table 8. Electrical characteristics of L7815A Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 14.7 15 15.3 V VO Output voltage IO = 5 mA to 1 A, VI = 17.9 to 28 V 14.4 15 15.6 V VO Output voltage IO = 1 A, VI = 28 to 30 V, TJ = 25°C 14.4 15 15.6 V ΔVO (1) Line regulation VI = 17.9 to 30 V, IO = 500 mA, TJ = 25°C 13 150 mV VI = 20 to 26 V 16 150 mV VI = 20 to 26 V, TJ = 25°C 6 75 mV VI = 17.5 to 30 V, TJ = 25°C 13 150 mV ΔVO (1) Load regulation IO = 5 mA to 1 A 25 100 IO = 5 mA to 1.5 A, TJ = 25°C 30 100 mV IO = 250 to 750 mA 10 50 Iq Quiescent current TJ = 25°C 4.4 6 mA 6 mA ΔIq Quiescent current change VI = 17.5 to 30 V, IO = 500 mA 0.8 mA VI = 17.5 to 30 V, TJ = 25°C 0.8 mA IO = 5 mA to 1 A 0.5 mA SVR Supply voltage rejection VI = 18.5 to 28.5 V, f = 120 Hz, IO = 500 mA 58 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V eN Output noise voltage TA = 25°C, B = 10Hz to 100 kHz 10 μV/VO RO Output resistance f = 1 kHz 19 mΩ Isc Short circuit current VI = 35 V, TA = 25°C 0.2 A Iscp Short circuit peak current TJ = 25°C 2.2 A ΔVO/ΔT Output voltage drift -1 mV/°C 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. DocID2143 Rev 32 15/58 Positive voltage regulator ICs Electrical characteristics 58 VI = 33 V, IO = 1 A, TJ = 0 to 125 °C (L7824AC), TJ = -40 to 125 °C (L7824AB), unless otherwise specified(g). g. Minimum load current for regulation is 5 mA. Table 9. Electrical characteristics of L7824A Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 23.5 24 24.5 V VO Output voltage IO = 5 mA to 1 A, VI = 27.3 to 37 V 23 24 25 V VO Output voltage IO = 1 A, VI = 37 to 38 V, TJ = 25°C 23 24 25 V ΔVO (1) Line regulation VI = 27 to 38 V, IO = 500 mA, TJ = 25°C 31 240 mV VI = 30 to 36 V 35 200 mV VI = 30 to 36 V, TJ = 25°C 14 120 mV VI = 26.7 to 38 V, TJ = 25°C 31 240 mV ΔVO (1) Load regulation IO = 5 mA to 1 A 25 100 IO = 5 mA to 1.5 A, TJ = 25°C 30 100 mV IO = 250 to 750 mA 10 50 Iq Quiescent current TJ = 25°C 4.6 6 mA 6 mA ΔIq Quiescent current change VI = 27.3 to 38 V, IO = 500 mA 0.8 mA VI = 27.3 to 38 V, TJ = 25°C 0.8 mA IO = 5 mA to 1 A 0.5 mA SVR Supply voltage rejection VI = 28 to 38 V, f = 120 Hz, IO = 500 mA 54 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V eN Output noise voltage TA = 25°C, B = 10 Hz to 100 kHz 10 μV/VO RO Output resistance f = 1 kHz 20 mΩ Isc Short circuit current VI = 35 V, TA = 25°C 0.2 A Iscp Short circuit peak current TJ = 25°C 2.2 A ΔVO/ΔT Output voltage drift -1.5 mV/°C 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. Electrical characteristics Positive voltage regulator ICs 16/58 DocID2143 Rev 32 Refer to the test circuits, TJ = 0 to 125 °C, VI = 10 V, IO = 500 mA, CI = 0.33 μF, CO = 0.1 μF unless otherwise specified(h). h. Minimum load current for regulation is 5 mA. Table 10. Electrical characteristics of L7805C Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 4.8 5 5.2 V VO Output voltage IO = 5 mA to 1 A, VI = 7 to 18 V 4.75 5 5.25 V VO Output voltage IO = 1 A, VI = 18 to 20V, TJ = 25°C 4.75 5 5.25 V ΔVO (1) Line regulation VI = 7 to 25 V, TJ = 25°C 3 100 mV VI = 8 to 12 V, TJ = 25°C 1 50 ΔVO (1) Load regulation IO = 5 mA to 1.5 A, TJ = 25°C 100 mV IO = 250 to 750 mA, TJ = 25°C 50 Id Quiescent current TJ = 25°C 8 mA ΔId Quiescent current change IO = 5 mA to 1 A 0.5 mA VI = 7 to 23 V 0.8 ΔVO/ΔT Output voltage drift IO = 5 mA -1.1 mV/°C eN Output noise voltage B = 10 Hz to 100 kHz, TJ = 25°C 40 μV/VO SVR Supply voltage rejection VI = 8 to 18 V, f = 120 Hz 62 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V RO Output resistance f = 1 kHz 17 mΩ Isc Short circuit current VI = 35 V, TJ = 25°C 0.75 A Iscp Short circuit peak current TJ = 25°C 2.2 A 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. DocID2143 Rev 32 17/58 Positive voltage regulator ICs Electrical characteristics 58 Refer to the test circuits, TJ = 0 to 125 °C, VI = 11 V, IO = 500 mA, CI = 0.33 μF, CO = 0.1 μF unless otherwise specified(i). i. Minimum load current for regulation is 5 mA. Table 11. Electrical characteristics of L7806C Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 5.75 6 6.25 V VO Output voltage IO = 5 mA to 1 A, VI = 8 to 19 V 5.7 6 6.3 V VO Output voltage IO = 1 A, VI = 19 to 21 V, TJ = 25°C 5.7 6 6.3 V ΔVO (1) Line regulation VI = 8 to 25 V, TJ = 25°C 120 mV VI = 9 to 13 V, TJ = 25°C 60 ΔVO (1) Load regulation IO = 5 mA to 1.5 A, TJ = 25°C 120 mV IO = 250 to 750 mA, TJ = 25°C 60 Id Quiescent current TJ = 25°C 8 mA ΔId Quiescent current change IO = 5 mA to 1 A 0.5 mA VI = 8 to 24 V 1.3 ΔVO/ΔT Output voltage drift IO = 5 mA -0.8 mV/°C eN Output noise voltage B = 10 Hz to 100 kHz, TJ = 25°C 45 μV/VO SVR Supply voltage rejection VI = 9 to 19 V, f = 120 Hz 59 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V RO Output resistance f = 1 kHz 19 mΩ Isc Short circuit current VI = 35 V, TJ = 25°C 0.55 A Iscp Short circuit peak current TJ = 25°C 2.2 A 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. Electrical characteristics Positive voltage regulator ICs 18/58 DocID2143 Rev 32 Refer to the test circuits, TJ = 0 to 125 °C, VI = 14 V, IO = 500 mA, CI = 0.33 μF, CO = 0.1 μF unless otherwise specified(j). j. Minimum load current for regulation is 5 mA. Table 12. Electrical characteristics of L7808C Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 7.7 8 8.3 V VO Output voltage IO = 5 mA to 1 A, VI = 10.5 to 21 V 7.6 8 8.4 V VO Output voltage IO = 1 A, VI = 21 to 25 V, TJ = 25°C 7.6 8 8.4 V ΔVO (1) Line regulation VI = 10.5 to 25 V, TJ = 25°C 160 mV VI = 11 to 17 V, TJ = 25°C 80 ΔVO (1) Load regulation IO = 5 mA to 1.5 A, TJ = 25°C 160 mV IO = 250 to 750 mA, TJ = 25°C 80 Id Quiescent current TJ = 25°C 8 mA ΔId Quiescent current change IO = 5 mA to 1 A 0.5 mA VI = 10.5 to 25 V 1 ΔVO/ΔT Output voltage drift IO = 5 mA -0.8 mV/°C eN Output noise voltage B = 10 Hz to 100 kHz, TJ = 25°C 52 μV/VO SVR Supply voltage rejection VI = 11.5 to 21.5 V, f = 120 Hz 56 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V RO Output resistance f = 1 kHz 16 mΩ Isc Short circuit current VI = 35 V, TJ = 25°C 0.45 A Iscp Short circuit peak current TJ = 25°C 2.2 A 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. DocID2143 Rev 32 19/58 Positive voltage regulator ICs Electrical characteristics 58 Refer to the test circuits, TJ = 0 to 125 °C, VI = 14.5 V, IO = 500 mA, CI = 0.33 μF, CO = 0.1 μF unless otherwise specified(k). k. Minimum load current for regulation is 5 mA. Table 13. Electrical characteristics of L7885C Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 8.2 8.5 8.8 V VO Output voltage IO = 5 mA to 1 A, VI = 11 to 21.5 V 8.1 8.5 8.9 V VO Output voltage IO = 1 A, VI = 21.5 to 26 V, TJ = 25°C 8.1 8.5 8.9 V ΔVO (1) Line regulation VI = 11 to 27 V, TJ = 25°C 160 mV VI = 11.5 to 17.5 V, TJ = 25°C 80 ΔVO (1) Load regulation IO = 5 mA to 1.5 A, TJ = 25°C 160 mV IO = 250 to 750 mA, TJ = 25°C 80 Id Quiescent current TJ = 25°C 8 mA ΔId Quiescent current change IO = 5 mA to 1 A 0.5 mA VI = 11 to 26 V 1 ΔVO/ΔT Output voltage drift IO = 5 mA -0.8 mV/°C eN Output noise voltage B = 10 Hz to 100 kHz, TJ = 25°C 55 μV/VO SVR Supply voltage rejection VI = 12 to 22 V, f = 120 Hz 56 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V RO Output resistance f = 1 kHz 16 mΩ Isc Short circuit current VI = 35 V, TJ = 25°C 0.45 A Iscp Short circuit peak current TJ = 25°C 2.2 A 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. Electrical characteristics Positive voltage regulator ICs 20/58 DocID2143 Rev 32 Refer to the test circuits, TJ = 0 to 125 °C, VI = 15 V, IO = 500 mA, CI = 0.33 μF, CO = 0.1 μF unless otherwise specified(l). l. Minimum load current for regulation is 5 mA. Table 14. Electrical characteristics of L7809C Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 8.64 9 9.36 V VO Output voltage IO = 5 mA to 1 A, VI = 11.5 to 22 V 8.55 9 9.45 V VO Output voltage IO = 1 A, VI = 22 to 26 V, TJ = 25°C 8.55 9 9.45 V ΔVO (1) Line regulation VI = 11.5 to 26 V, TJ = 25°C 180 mV VI = 12 to 18 V, TJ = 25°C 90 ΔVO (1) Load regulation IO = 5 mA to 1.5 A, TJ = 25°C 180 mV IO = 250 to 750 mA, TJ = 25°C 90 Id Quiescent current TJ = 25°C 8 mA ΔId Quiescent current change IO = 5 mA to 1 A 0.5 mA VI = 11.5 to 26 V 1 ΔVO/ΔT Output voltage drift IO = 5 mA -1 mV/°C eN Output noise voltage B = 10 Hz to 100 kHz, TJ = 25°C 70 μV/VO SVR Supply voltage rejection VI = 12 to 23 V, f = 120 Hz 55 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V RO Output resistance f = 1 kHz 17 mΩ Isc Short circuit current VI = 35 V, TJ = 25°C 0.40 A Iscp Short circuit peak current TJ = 25°C 2.2 A 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. DocID2143 Rev 32 21/58 Positive voltage regulator ICs Electrical characteristics 58 Refer to the test circuits, TJ = 0 to 125 °C, VI = 19 V, IO = 500 mA, CI = 0.33 μF, CO = 0.1 μF unless otherwise specified(m). m. Minimum load current for regulation is 5 mA. Table 15. Electrical characteristics of L7812C Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 11.5 12 12.5 V VO Output voltage IO = 5 mA to 1 A, VI = 14.5 to 25 V 11.4 12 12.6 V VO Output voltage IO = 1 A, VI = 25 to 27 V, TJ = 25°C 11.4 12 12.6 V ΔVO (1) Line regulation VI = 14.5 to 30 V, TJ = 25°C 240 mV VI = 16 to 22 V, TJ = 25°C 120 ΔVO (1) Load regulation IO = 5 mA to 1.5 A, TJ = 25°C 240 mV IO = 250 to 750 mA, TJ = 25°C 120 Id Quiescent current TJ = 25°C 8 mA ΔId Quiescent current change IO = 5 mA to 1 A 0.5 mA VI = 14.5 to 30 V 1 ΔVO/ΔT Output voltage drift IO = 5 mA -1 mV/°C eN Output noise voltage B = 10 Hz to 100 kHz, TJ = 25°C 75 μV/VO SVR Supply voltage rejection VI = 15 to 25 V, f = 120 Hz 55 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V RO Output resistance f = 1 kHz 18 mΩ Isc Short circuit current VI = 35 V, TJ = 25°C 0.35 A Iscp Short circuit peak current TJ = 25°C 2.2 A 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. Electrical characteristics Positive voltage regulator ICs 22/58 DocID2143 Rev 32 Refer to the test circuits, TJ = 0 to 125 °C, VI = 23 V, IO = 500 mA, CI = 0.33 μF, CO = 0.1 μF unless otherwise specified(n). n. Minimum load current for regulation is 5 mA. Table 16. Electrical characteristics of L7815C Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 14.4 15 15.6 V VO Output voltage IO = 5 mA to 1 A, VI = 17.5 to 28 V 14.25 15 15.75 V VO Output voltage IO = 1 A, VI = 28 to 30 V, TJ = 25°C 14.25 15 15.75 V ΔVO (1) Line regulation VI = 17.5 to 30 V, TJ = 25°C 300 mV VI = 20 to 26 V, TJ = 25°C 150 ΔVO (1) Load regulation IO = 5 mA to 1.5 A, TJ = 25°C 300 mV IO = 250 to 750 mA, TJ = 25°C 150 Id Quiescent current TJ = 25°C 8 mA ΔId Quiescent current change IO = 5 mA to 1A 0.5 mA VI = 17.5 to 30 V 1 ΔVO/ΔT Output voltage drift IO = 5 mA -1 mV/°C eN Output noise voltage B = 10 Hz to 100kHz, TJ = 25°C 90 μV/VO SVR Supply voltage rejection VI = 18.5 to 28.5 V, f = 120 Hz 54 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V RO Output resistance f = 1 kHz 19 mΩ Isc Short circuit current VI = 35 V, TJ = 25°C 0.23 A Iscp Short circuit peak current TJ = 25°C 2.2 A 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. DocID2143 Rev 32 23/58 Positive voltage regulator ICs Electrical characteristics 58 Refer to the test circuits, TJ = 0 to 125 °C, VI = 26 V, IO = 500 mA, CI = 0.33 μF, CO = 0.1 μF unless otherwise specified(o). o. Minimum load current for regulation is 5 mA. Table 17. Electrical characteristics of L7818C Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 17.3 18 18.7 V VO Output voltage IO = 5 mA to 1 A, VI = 21 to 31 V 17.1 18 18.9 V VO Output voltage IO = 1 A, VI = 31 to 33 V, TJ = 25°C 17.1 18 18.9 V ΔVO (1) Line regulation VI = 21 to 33 V, TJ = 25°C 360 mV VI = 24 to 30 V, TJ = 25°C 180 ΔVO (1) Load regulation IO = 5 mA to 1.5 A, TJ = 25°C 360 mV IO = 250 to 750 mA, TJ = 25°C 180 Id Quiescent current TJ = 25°C 8 mA ΔId Quiescent current change IO = 5 mA to 1 A 0.5 mA VI = 21 to 33 V 1 ΔVO/ΔT Output voltage drift IO = 5 mA -1 mV/°C eN Output noise voltage B = 10 Hz to 100 kHz, TJ = 25°C 110 μV/VO SVR Supply voltage rejection VI = 22 to 32 V, f = 120 Hz 53 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V RO Output resistance f = 1 kHz 22 mΩ Isc Short circuit current VI = 35 V, TJ = 25°C 0.20 A Iscp Short circuit peak current TJ = 25°C 2.1 A 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. Electrical characteristics Positive voltage regulator ICs 24/58 DocID2143 Rev 32 Refer to the test circuits, TJ = 0 to 125 °C, VI = 33 V, IO = 500 mA, CI = 0.33 μF, CO = 0.1 μF unless otherwise specified(p). p. Minimum load current for regulation is 5 mA. Table 18. Electrical characteristics of L7824C Symbol Parameter Test conditions Min. Typ. Max. Unit VO Output voltage TJ = 25°C 23 24 25 V VO Output voltage IO = 5 mA to 1 A, VI = 27 to 37 V 22.8 24 25.2 V VO Output voltage IO = 1 A, VI = 37 to 38 V, TJ = 25°C 22.8 24 25.2 V ΔVO (1) Line regulation VI = 27 to 38 V, TJ = 25°C 480 mV VI = 30 to 36 V, TJ = 25°C 240 ΔVO (1) Load regulation IO = 5 mA to 1.5 A, TJ = 25°C 480 mV IO = 250 to 750 mA, TJ = 25°C 240 Id Quiescent current TJ = 25°C 8 mA ΔId Quiescent current change IO = 5 mA to 1 A 0.5 mA VI = 27 to 38 V 1 ΔVO/ΔT Output voltage drift IO = 5 mA -1.5 mV/°C eN Output noise voltage B = 10 Hz to 100 kHz, TJ = 25°C 170 μV/VO SVR Supply voltage rejection VI = 28 to 38 V, f = 120 Hz 50 dB Vd Dropout voltage IO = 1 A, TJ = 25°C 2 V RO Output resistance f = 1 kHz 28 mΩ Isc Short circuit current VI = 35 V, TJ = 25°C 0.15 A Iscp Short circuit peak current TJ = 25°C 2.1 A 1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty cycle is used. DocID2143 Rev 32 25/58 Positive voltage regulator ICs Application information 58 6 Application information 6.1 Design consideration The L78 Series of fixed voltage regulators are designed with thermal overload protection that shuts down the circuit when subjected to an excessive power overload condition, internal short-circuit protection that limits the maximum current the circuit will pass, and output transistor safe-area compensation that reduces the output short-circuit current as the voltage across the pass transistor is increased. In many low current applications, compensation capacitors are not required. However, it is recommended that the regulator input be bypassed with capacitor if the regulator is connected to the power supply filter with long lengths, or if the output load capacitance is large. An input bypass capacitor should be selected to provide good high frequency characteristics to insure stable operation under all load conditions. A 0.33 μF or larger tantalum, mylar or other capacitor having low internal impedance at high frequencies should be chosen. The bypass capacitor should be mounted with the shortest possible leads directly across the regulators input terminals. Normally good construction techniques should be used to minimize ground loops and lead resistance drops since the regulator has no external sense lead. The addition of an operational amplifier allows adjustment to higher or intermediate values while retaining regulation characteristics. The minimum voltage obtained with the arrangement is 2 V greater than the regulator voltage. The circuit of Figure 13 can be modified to provide supply protection against short circuit by adding a short circuit sense resistor, RSC, and an additional PNP transistor. The current sensing PNP must be able to handle the short circuit current of the three terminal regulator Therefore a four ampere plastic power transistor is specified. Figure 8. Fixed output regulator 1. Although no output capacitor is need for stability, it does improve transient response. 2. Required if regulator is located an appreciable distance from power supply filter. Application information Positive voltage regulator ICs 26/58 DocID2143 Rev 32 Figure 9. Current regulator 􀀬􀀲 􀀠􀀠􀀃􀀃􀀹􀀻􀀻􀀻􀀻􀀒􀀵􀀔􀀎􀀬􀁇 Figure 10. Circuit for increasing output voltage 􀀬􀀵􀀔 􀀃􀀘􀀃􀀬􀁇 􀀹􀀲􀀃􀀃􀀠􀀠􀀃􀀹􀀻􀀻􀀻􀀻􀀋􀀋􀀔􀀔􀀎􀀎􀀵􀀵􀀕􀀒􀀵􀀔􀀌􀀌􀀎􀀎􀀬􀁇􀀵􀀕 􀅻 DocID2143 Rev 32 27/58 Positive voltage regulator ICs Application information 58 Figure 11. Adjustable output regulator (7 to 30 V) Figure 12. 0.5 to 10 V regulator VO=VXXR4/R1 Application information Positive voltage regulator ICs 28/58 DocID2143 Rev 32 Figure 13. High current voltage regulator 􀀵􀀔 􀀬􀀲􀀃􀀠􀀃􀀬􀀵􀀨􀀪􀀃􀀎􀀃􀀴􀀔􀀃􀀋􀀬􀀵􀀨􀀪􀀃􀁂􀀹􀁂􀀥􀁂􀀨􀁂􀀴􀁂􀀔􀁂􀀌 􀀹􀀥􀀨􀀴􀀔 􀀵􀀔􀀃􀀠􀀃􀁂􀁂􀁂􀁂􀁂􀁂􀁂􀁂􀁂􀁂􀁂􀁂􀁂􀁂 􀀬􀀵􀀨􀀴􀀐􀀋􀀬􀀴􀀔􀀒􀁅􀀴􀀔􀀌 Figure 14. High output current with short circuit protection 􀀵􀀶􀀶􀀦􀀦􀀠􀀹􀀥􀀥􀀨􀀨􀀴􀀴􀀕􀀕􀀒􀀬􀀶􀀶􀀦􀀦 DocID2143 Rev 32 29/58 Positive voltage regulator ICs Application information 58 * Against potential latch-up problems. Figure 15. Tracking voltage regulator Figure 16. Split power supply (± 15 V - 1 A) Application information Positive voltage regulator ICs 30/58 DocID2143 Rev 32 Figure 17. Negative output voltage circuit Figure 18. Switching regulator Figure 19. High input voltage circuit (configuration 1) 􀀹􀀬􀀱􀀃􀀠􀀃􀀹􀀬􀀃􀀐􀀃􀀋􀀋􀀹􀀹􀀽􀀃􀀎􀀃􀀹􀀥􀀥􀀨􀀨􀀌 DocID2143 Rev 32 31/58 Positive voltage regulator ICs Application information 58 Figure 20. High input voltage circuit (configuration 2) Figure 21. High input and output voltage 􀀹􀀲􀀃􀀠􀀃􀀹􀀻􀀻􀀻􀀻􀀃􀀎􀀃􀀹􀀽􀀔 Figure 22. Reducing power dissipation with dropping resistor 􀀹􀀹 􀀐􀀐􀀹􀀹 􀀐􀀹 􀀵􀀃􀀠􀀃􀁂􀁂􀀬􀀬􀁂􀁂􀀋􀀋􀁐􀁐􀁂􀁂􀁂􀁌􀁌􀁑􀁑􀁂􀁂􀀌􀀌 􀁂􀁂􀁂􀁂􀀻􀀻􀁂􀀻􀀻􀁂􀁂􀁂􀁂􀁂􀀧􀁂􀁂􀀵􀁂􀁂􀀲􀁂􀁂􀀳􀁂􀀋􀀋􀁐􀁐􀁂􀁂􀁄􀁄􀁂􀁂􀁛􀁛􀁂􀀌􀀌􀁂 􀀬􀀲􀀋􀁐􀁄􀁛􀁛􀀌􀀌􀀎􀀬􀁇􀀋􀀋􀁐􀁐􀁄􀁄􀁛􀁛􀀌􀀌 Application information Positive voltage regulator ICs 32/58 DocID2143 Rev 32 Note: The circuit performs well up to 100 kHz. Figure 23. Remote shutdown Figure 24. Power AM modulator (unity voltage gain, IO ≤ 0.5) DocID2143 Rev 32 33/58 Positive voltage regulator ICs Application information 58 Note: Q2 is connected as a diode in order to compensate the variation of the Q1 VBE with the temperature. C allows a slow rise time of the VO. Figure 25. Adjustable output voltage with temperature compensation 􀀹􀀲􀀃􀀠􀀃􀀹􀀻􀀻􀀃􀀋􀀔􀀎􀀵􀀕􀀒􀀵􀀔􀀌􀀃􀀎􀀃􀀹􀀥􀀨 Figure 26. Light controllers (VO(min) = VXX + VBE) 􀀹􀀲􀀃􀁉􀁄􀁏􀁏􀁖􀀃􀁚􀁋􀁈􀁑􀀃􀁗􀁋􀁈􀀃􀁏􀁌􀁊􀁋􀁗􀀃􀁊􀁒􀁈􀁖􀀃􀁘􀁓 􀀹􀀲􀀃􀁕􀁌􀁖􀁈􀁖􀀃􀁚􀁋􀁈􀁑􀀃􀁗􀁋􀁈􀀃􀁏􀁌􀁊􀁋􀁗􀀃􀁊􀁒􀁈􀁖􀀃􀁘􀁓 Application information Positive voltage regulator ICs 34/58 DocID2143 Rev 32 Note: Application with high capacitance loads and an output voltage greater than 6 volts need an external diode (see Figure 22 on page 31) to protect the device against input short circuit. In this case the input voltage falls rapidly while the output voltage decrease slowly. The capacitance discharges by means of the base-emitter junction of the series pass transistor in the regulator. If the energy is sufficiently high, the transistor may be destroyed. The external diode by-passes the current from the IC to ground. Figure 27. Protection against input short-circuit with high capacitance loads DocID2143 Rev 32 35/58 Positive voltage regulator ICs Typical performance 58 7 Typical performance Figure 28. Dropout voltage vs. junction temperature Figure 29. Peak output current vs. input/output differential voltage Figure 30. Supply voltage rejection vs. frequency Figure 31. Output voltage vs. junction temperature Typical performance Positive voltage regulator ICs 36/58 DocID2143 Rev 32 Figure 32. Output impedance vs. frequency Figure 33. Quiescent current vs. junction temp. Figure 34. Load transient response Figure 35. Line transient response Figure 36. Quiescent current vs. input voltage DocID2143 Rev 32 37/58 Positive voltage regulator ICs Package mechanical data 58 8 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Package mechanical data Positive voltage regulator ICs 38/58 DocID2143 Rev 32 Figure 37. TO-220 (dual gauge) drawing 􀀓􀀓􀀔􀀘􀀜􀀛􀀛􀁂􀁗􀁜􀁓􀁈􀀤􀁂􀀵􀁈􀁙􀁂􀀷 DocID2143 Rev 32 39/58 Positive voltage regulator ICs Package mechanical data 58 Table 19. TO-220 (dual gauge) mechanical data Dim. mm Min. Typ. Max. A 4.40 4.60 b 0.61 0.88 b1 1.14 1.70 c 0.48 0.70 D 15.25 15.75 D1 1.27 E 10 10.40 e 2.40 2.70 e1 4.95 5.15 F 1.23 1.32 H1 6.20 6.60 J1 2.40 2.72 L 13 14 L1 3.50 3.93 L20 16.40 L30 28.90 ∅P 3.75 3.85 Q 2.65 2.95 Package mechanical data Positive voltage regulator ICs 40/58 DocID2143 Rev 32 Figure 38. TO-220 SG (single gauge) drawing 􀀛􀀔􀀚􀀗􀀙􀀕􀀚􀁂􀁕􀁈􀁙􀀧 DocID2143 Rev 32 41/58 Positive voltage regulator ICs Package mechanical data 58 Table 20. TO-220 SG (single gauge) mechanical data Dim. mm Min. Typ. Max. A 4.40 4.60 b 0.61 0.88 b1 1.14 1.70 c 0.48 0.70 D 15.25 15.75 E 10 10.40 e 2.40 2.70 e1 4.95 5.15 F 0.51 0.60 H1 6.20 6.60 J1 2.40 2.72 L 13 14 L1 3.50 3.93 L20 16.40 L30 28.90 ∅P 3.75 3.85 Q 2.65 2.95 Package mechanical data Positive voltage regulator ICs 42/58 DocID2143 Rev 32 Figure 39. TO-220FP drawing 7012510A-H DocID2143 Rev 32 43/58 Positive voltage regulator ICs Package mechanical data 58 Table 21. TO-220FP mechanical data Dim. mm. Min. Typ. Max. A 4.40 4.60 B 2.5 2.7 D 2.5 2.75 E 0.45 0.70 F 0.75 1 F1 1.15 1.50 F2 1.15 1.50 G 4.95 5.2 G1 2.4 2.7 H 10.0 10.40 L2 16 L3 28.6 30.6 L4 9.8 10.6 L5 2.9 3.6 L6 15.9 16.4 L7 9 9.3 DIA. 3 3.2 Package mechanical data Positive voltage regulator ICs 44/58 DocID2143 Rev 32 Figure 40. DPAK drawing 0068772_K DocID2143 Rev 32 45/58 Positive voltage regulator ICs Package mechanical data 58 Table 22. DPAK mechanical data Dim. mm Min. Typ. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 5.10 E 6.40 6.60 E1 4.70 e 2.28 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 (L1) 2.80 L2 0.80 L4 0.60 1.00 R 0.20 V2 0° 8° Package mechanical data Positive voltage regulator ICs 46/58 DocID2143 Rev 32 Figure 41. DPAK footprint (q) q. All dimensions are in millimeters Footprint_REV_K DocID2143 Rev 32 47/58 Positive voltage regulator ICs Package mechanical data 58 Figure 42. D²PAK (SMD 2L STD-ST) type A drawing 0079457_T Package mechanical data Positive voltage regulator ICs 48/58 DocID2143 Rev 32 Table 23. D²PAK (SMD 2L STD-ST) mechanical data Dim. mm Min. Typ. Max. A 4.40 4.60 A1 0.03 0.23 b 0.70 0.93 b2 1.14 1.70 c 0.45 0.60 c2 1.23 1.36 D 8.95 9.35 D1 7.50 E 10 10.40 E1 8.50 e 2.54 e1 4.88 5.28 H 15 15.85 J1 2.49 2.69 L 2.29 2.79 L1 1.27 1.40 L2 1.30 1.75 R 0.4 V2 0° 8° DocID2143 Rev 32 49/58 Positive voltage regulator ICs Package mechanical data 58 Figure 43. D²PAK (SMD 2L Wooseok-subcon.) drawing 0079457_T Package mechanical data Positive voltage regulator ICs 50/58 DocID2143 Rev 32 Table 24. D²PAK (SMD 2L Wooseok-subcon.) mechanical data Dim. mm Min. Typ. Max. A 4.30 4.70 A1 0 0.20 b 0.70 0.90 b2 1.17 1.37 c 0.45 0.50 0.60 c2 1.25 1.30 1.40 D 9 9.20 9.40 D1 7.50 E 10 10.40 E1 8.50 e 2.54 e1 4.88 5.08 H 15 15.30 J1 2.20 2.60 L 1.79 2.79 L1 1 1.40 L2 1.20 1.60 R 0.30 V2 0° 3° DocID2143 Rev 32 51/58 Positive voltage regulator ICs Package mechanical data 58 Figure 44. D²PAK (SMD 2L Wooseok-subcon.) footprint Packaging mechanical data Positive voltage regulator ICs 52/58 DocID2143 Rev 32 9 Packaging mechanical data Figure 45. Tube for TO-220 (dual gauge) (mm.) Figure 46. Tube for TO-220 (single gauge) (mm.) DocID2143 Rev 32 53/58 Positive voltage regulator ICs Packaging mechanical data 58 Figure 47. Tape for DPAK and D2PAK Figure 48. Reel for DPAK and D2PAK A0 P1 D1 P0 F W E D B0 K0 T User direction of feed P2 10 pitches cumulative tolerance on tape +/- 0.2 mm User direction of feed R Bending radius B1 For machine ref. only including draft and radii concentric around B0 AM08852v1 Top cover tape A D B Full radius G measured at hub C N REEL DIMENSIONS 40mm min. Access hole At sl ot location T Tape slot in core for tape start 25 mm min. width AM08851v2 Packaging mechanical data Positive voltage regulator ICs 54/58 DocID2143 Rev 32 Table 25. DPAK and D²PAK tape and reel mechanical data Tape Reel Dim. mm Dim. mm Min. Max. Min. Max. A0 6.8 7 A 330 B0 10.4 10.6 B 1.5 B1 12.1 C 12.8 13.2 D 1.5 1.6 D 20.2 D1 1.5 G 16.4 18.4 E 1.65 1.85 N 50 F 7.4 7.6 T 22.4 K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 DocID2143 Rev 32 55/58 Positive voltage regulator ICs Order codes 58 10 Order codes Table 26. Order codes Part numbers Order codes TO-220 (single gauge) TO-220 (dual gauge) DPAK D²PAK TO-220FP Output voltages L7805C L7805CV L7805CDT-TR L7805CD2T-TR L7805CP 5 V L7805CV-DG 5 V L7805AB L7805ABV L7805ABD2T-TR L7805ABP 5 V L7805ABV-DG 5 V L7805AC L7805ACV L7805ACD2T-TR L7805ACP 5 V L7805ACV-DG 5 V L7806C L7806CV L7806CD2T-TR 6 V L7806CV-DG 6 V L7806AB L7806ABV L7806ABD2T-TR 6 V L7806ABV-DG 6 V L7806AC L7806ACV 6 V L7806ACV-DG 6 V L7808C L7808CV L7808CD2T-TR 8 V L7808CV-DG 8 V L7808AB L7808ABV L7808ABD2T-TR 8 V L7808ABV-DG 8 V L7808AC L7808ACV 8 V L7808ACV-DG 8 V L7885C L7885CV 8.5 V L7809C L7809CV L7809CD2T-TR L7809CP 9 V L7809CV-DG 9 V L7809AB L7809ABV L7809ABD2T-TR 9 V L7809ABV-DG 9 V L7809AC L7809ACV 9 V L7812C L7812CV L7812CD2T-TR L7812CP 12 V L7812CV-DG 12 V L7812AB L7812ABV L7812ABD2T-TR 12 V L7812ABV-DG 12 V L7812AC L7812ACV L7812ACD2T-TR 12 V L7812ACV-DG 12 V Order codes Positive voltage regulator ICs 56/58 DocID2143 Rev 32 L7815C L7815CV L7815CD2T-TR L7815CP 15 V L7815CV-DG 15 V L7815AB L7815ABV L7815ABD2T-TR 15 V L7815ABV-DG 15 V L7815AC L7815ACV L7815ACD2T-TR 15 V L7815ACV-DG 15 V L7818C L7818CV 18 V L7818CV-DG 18 V L7824C L7824CV L7824CD2T-TR L7824CP 24 V L7824CV-DG 24 V L7824AB L7824ABV 24 V L7824ABV-DG 24 V L7824AC L7824ACV 24 V L7824ACV-DG 24 V Table 26. Order codes (continued) Part numbers Order codes TO-220 (single gauge) TO-220 (dual gauge) DPAK D²PAK TO-220FP Output voltages DocID2143 Rev 32 57/58 Positive voltage regulator ICs Revision history 58 11 Revision history Table 27. Document revision history Date Revision Changes 21-Jun-2004 12 Document updating. 03-Aug-2006 13 Order codes has been updated and new template. 19-Jan-2007 14 D²PAK mechanical data has been updated and add footprint data. 31-May-2007 15 Order codes has been updated. 29-Aug-2007 16 Added Table 1 in cover page. 11-Dec-2007 17 Modified: Table 26. 06-Feb-2008 18 Added: TO-220 mechanical data Figure 38 on page 38 , Figure 39 on page 39, and Table 23 on page 37. Modified: Table 26 on page 55. 18-Mar-2008 19 Added: Table 29: DPAK mechanical data on page 50, Table 30: Tape and reel DPAK mechanical data on page 52. Modified: Table 26 on page 55. 26-Jan-2010 20 Modified Table 1 on page 1 and Table 23 on page 37, added: Figure 38 on page 38 and Figure 39 on page 39, Figure 45 on page 52 and Figure 46 on page 52. 04-Mar-2010 21 Added notes Figure 38 on page 38. 08-Sep-2010 22 Modified Table 26 on page 55. 23-Nov-2010 23 Added: TJ = 25 °C test condition in ΔVO on Table 3, 4, 5, 6, 7, 8 and Table 9. 16-Sep-2011 24 Modified title on page 1. 30-Nov-2011 25 Added: order codes L7805CV-DG, L7806CV-DG, L7808ABV-DG, L7812CV-DG and L7815CV-DG Table 26 on page 55. 08-Feb-2012 26 Added: order codes L7805ACV-DG, L7805ABV-DG, L7806ABV-DG, L7808CVDG, L7809CV-DG, L7812ACV-DG, L7818CV-DG, L7824CV-DG Table 26 on page 55. 27-Mar-2012 27 Added: order codes L7812ABV-DG, L7815ABV-DG Table 26 on page 55. 27-Apr-2012 28 Modified: VI = 10.4 to 23 V ==> VI = 11.4 to 23 V test conditon value Line regulation Table 6 on page 12. 10-May-2012 29 Added: order codes L7806ACV-DG, L7808ACV-DG, L7815ACV-DG, L7824ABV-DG and L7824ACV-DG Table 26 on page 55. 19-Sep-2012 30 Modified load regulation units from V to mV in Table 3 to Table 9. 12-Mar-2013 31 Modified: VO output voltage at 25 °C min. value 14.4 V Table 16 on page 22. 04-Mar-2014 32 Part numbers L78xx, L78xxC, L78xxAB, L78xxAC changed to L78. Removed TO-3 package. Updated the description in cover page, Section 2: Pin configuration, Section 3: Maximum ratings, Section 4: Test circuits, Section 5: Electrical characteristics, Section 6: Application information, Section 8: Package mechanical data and Table 26: Order codes. Added Section 9: Packaging mechanical data. Minor text changes. Positive voltage regulator ICs 58/58 DocID2143 Rev 32 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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All other names are the property of their respective owners. © 2014 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com STM32F405xx STM32F407xx ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera Datasheet - production data Features • Core: ARM 32-bit Cortex™-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/ 1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions • Memories – Up to 1 Mbyte of Flash memory – Up to 192+4 Kbytes of SRAM including 64- Kbyte of CCM (core coupled memory) data RAM – Flexible static memory controller supporting Compact Flash, SRAM, PSRAM, NOR and NAND memories • LCD parallel interface, 8080/6800 modes • Clock, reset and supply management – 1.8 V to 3.6 V application supply and I/Os – POR, PDR, PVD and BOR – 4-to-26 MHz crystal oscillator – Internal 16 MHz factory-trimmed RC (1% accuracy) – 32 kHz oscillator for RTC with calibration – Internal 32 kHz RC with calibration • Low power – Sleep, Stop and Standby modes – VBAT supply for RTC, 20×32 bit backup registers + optional 4 KB backup SRAM • 3×12-bit, 2.4 MSPS A/D converters: up to 24 channels and 7.2 MSPS in triple interleaved mode • 2×12-bit D/A converters • General-purpose DMA: 16-stream DMA controller with FIFOs and burst support • Up to 17 timers: up to twelve 16-bit and two 32- bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input • Debug mode – Serial wire debug (SWD) & JTAG interfaces – Cortex-M4 Embedded Trace Macrocell™ • Up to 140 I/O ports with interrupt capability – Up to 136 fast I/Os up to 84 MHz – Up to 138 5 V-tolerant I/Os • Up to 15 communication interfaces – Up to 3 × I2C interfaces (SMBus/PMBus) – Up to 4 USARTs/2 UARTs (10.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem control) – Up to 3 SPIs (42 Mbits/s), 2 with muxed full-duplex I2S to achieve audio class accuracy via internal audio PLL or external clock – 2 × CAN interfaces (2.0B Active) – SDIO interface • Advanced connectivity – USB 2.0 full-speed device/host/OTG controller with on-chip PHY – USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI – 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII • 8- to 14-bit parallel camera interface up to 54 Mbytes/s • True random number generator • CRC calculation unit • 96-bit unique ID • RTC: subsecond accuracy, hardware calendar LQFP64 (10 × 10 mm) LQFP100 (14 × 14 mm) LQFP144 (20 × 20 mm) FBGA UFBGA176 (10 × 10 mm) LQFP176 (24 × 24 mm) WLCSP90 Table 1. Device summary Reference Part number STM32F405xx STM32F405RG, STM32F405VG, STM32F405ZG, STM32F405OG, STM32F405OE STM32F407xx STM32F407VG, STM32F407IG, STM32F407ZG, STM32F407VE, STM32F407ZE, STM32F407IE www.st.com Contents STM32F405xx, STM32F407xx 2/185 DocID022152 Rev 4 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.1 ARM® Cortex™-M4F core with embedded Flash and SRAM . . . . . . . . 19 2.2.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . 19 2.2.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.5 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 20 2.2.6 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.7 Multi-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.8 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.9 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.10 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 22 2.2.11 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.12 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.13 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.15 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.16 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2.17 Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 28 2.2.18 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . 28 2.2.19 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.2.20 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.21 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.22 Inter-integrated circuit interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2.23 Universal synchronous/asynchronous receiver transmitters (USART) . 33 2.2.24 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.25 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.26 Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.2.27 Secure digital input/output interface (SDIO) . . . . . . . . . . . . . . . . . . . . . 35 2.2.28 Ethernet MAC interface with dedicated DMA and IEEE 1588 support . 35 2.2.29 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DocID022152 Rev 4 3/185 STM32F405xx, STM32F407xx Contents 2.2.30 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . 36 2.2.31 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . 36 2.2.32 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.33 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.34 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.35 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.36 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.2.37 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.2.38 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.2.39 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.3.2 VCAP_1/VCAP_2 external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3.3 Operating conditions at power-up / power-down (regulator ON) . . . . . . 80 5.3.4 Operating conditions at power-up / power-down (regulator OFF) . . . . . 80 5.3.5 Embedded reset and power control block characteristics . . . . . . . . . . . 80 5.3.6 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.3.7 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 5.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . 102 Contents STM32F405xx, STM32F407xx 4/185 DocID022152 Rev 4 5.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 108 5.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.3.17 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 5.3.18 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.3.19 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 5.3.20 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 5.3.23 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.3.24 DAC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 5.3.25 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 5.3.26 Camera interface (DCMI) timing specifications . . . . . . . . . . . . . . . . . . 155 5.3.27 SD/SDIO MMC card host interface (SDIO) characteristics . . . . . . . . . 156 5.3.28 RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Appendix A Application block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 A.1 USB OTG full speed (FS) interface solutions . . . . . . . . . . . . . . . . . . . . . 171 A.2 USB OTG high speed (HS) interface solutions . . . . . . . . . . . . . . . . . . . . 173 A.3 Ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 DocID022152 Rev 4 5/185 STM32F405xx, STM32F407xx List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. STM32F405xx and STM32F407xx: features and peripheral counts. . . . . . . . . . . . . . . . . . 13 Table 3. Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 4. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 5. USART feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 6. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 7. STM32F40x pin and ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 8. FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 9. Alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 10. STM32F40x register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 11. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 12. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 13. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 14. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 15. Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . . 79 Table 16. VCAP_1/VCAP_2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 17. Operating conditions at power-up / power-down (regulator ON) . . . . . . . . . . . . . . . . . . . . 80 Table 18. Operating conditions at power-up / power-down (regulator OFF). . . . . . . . . . . . . . . . . . . . 80 Table 19. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 20. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM . . . . . . . . . . . . . . . . . . . 83 Table 21. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 22. Typical and maximum current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 23. Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 24. Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 88 Table 25. Typical and maximum current consumptions in VBAT mode. . . . . . . . . . . . . . . . . . . . . . . . 89 Table 26. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table 27. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 28. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 29. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 30. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 31. HSE 4-26 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 32. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 33. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 34. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table 35. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 36. PLLI2S (audio PLL) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Table 37. SSCG parameters constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 38. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 39. Flash memory programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Table 40. Flash memory programming with VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 41. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Table 42. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Table 43. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 44. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 45. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 46. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 List of tables STM32F405xx, STM32F407xx 6/185 DocID022152 Rev 4 Table 47. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 48. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 49. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 50. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 51. Characteristics of TIMx connected to the APB1 domain . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 52. Characteristics of TIMx connected to the APB2 domain . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 53. I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 54. SCL frequency (fPCLK1= 42 MHz.,VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 55. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 56. I2S dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 57. USB OTG FS startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 58. USB OTG FS DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 59. USB OTG FS electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 60. USB HS DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 61. USB HS clock timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 62. ULPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 63. Ethernet DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 64. Dynamic characteristics: Ehternet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 65. Dynamic characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 66. Dynamic characteristics: Ethernet MAC signals for MII . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Table 67. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 68. ADC accuracy at fADC = 30 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Table 69. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 70. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 71. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 72. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 73. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 74. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 138 Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 139 Table 77. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Table 78. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Table 79. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Table 80. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Table 81. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 145 Table 82. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Table 83. Switching characteristics for PC Card/CF read and write cycles in attribute/common space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 84. Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Table 85. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Table 86. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 87. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 88. Dynamic characteristics: SD / MMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Table 89. RTC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Table 90. WLCSP90 - 0.400 mm pitch wafer level chip size package mechanical data . . . . . . . . . 159 Table 91. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . 160 Table 92. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . 162 Table 93. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 164 Table 94. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Table 95. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data . . . . . . . 167 DocID022152 Rev 4 7/185 STM32F405xx, STM32F407xx List of tables Table 96. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Table 97. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Table 98. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 List of figures STM32F405xx, STM32F407xx 8/185 DocID022152 Rev 4 List of figures Figure 1. Compatible board design between STM32F10xx/STM32F4xx for LQFP64. . . . . . . . . . . . 15 Figure 2. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 3. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 4. Compatible board design between STM32F2xx and STM32F4xx for LQFP176 and BGA176 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 5. STM32F40x block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 6. Multi-AHB matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 7. Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 24 Figure 8. PDR_ON and NRST control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 9. Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 10. Startup in regulator OFF mode: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 11. Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 28 Figure 12. STM32F40x LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 13. STM32F40x LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 14. STM32F40x LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 15. STM32F40x LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 16. STM32F40x UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 17. STM32F40x WLCSP90 ballout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 18. STM32F40x memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 19. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 20. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 21. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 22. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 23. External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 24. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF . . . . 85 Figure 25. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals ON . . . . . 85 Figure 26. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF . . . 86 Figure 27. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals ON . . . . 86 Figure 28. Typical VBAT current consumption (LSE and RTC ON/backup RAM OFF) . . . . . . . . . . . . 89 Figure 29. Typical VBAT current consumption (LSE and RTC ON/backup RAM ON) . . . . . . . . . . . . . 90 Figure 30. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 31. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 32. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Figure 33. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 34. ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 35. PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Figure 36. PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Figure 37. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Figure 38. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Figure 39. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 DocID022152 Rev 4 9/185 STM32F405xx, STM32F407xx List of figures Figure 40. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Figure 41. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Figure 42. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Figure 43. I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Figure 44. I2S master timing diagram (Philips protocol)(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Figure 45. USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 124 Figure 46. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Figure 47. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Figure 48. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Figure 49. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Figure 50. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 51. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Figure 52. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 133 Figure 53. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 133 Figure 54. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 138 Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 139 Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 140 Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 141 Figure 59. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Figure 60. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 145 Figure 62. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Figure 63. PC Card/CompactFlash controller waveforms for common memory read access . . . . . . 148 Figure 64. PC Card/CompactFlash controller waveforms for common memory write access . . . . . . 148 Figure 65. PC Card/CompactFlash controller waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Figure 66. PC Card/CompactFlash controller waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Figure 67. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 150 Figure 68. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 151 Figure 69. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Figure 70. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Figure 71. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 154 Figure 72. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 154 Figure 73. DCMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Figure 74. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Figure 75. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Figure 76. WLCSP90 - 0.400 mm pitch wafer level chip size package outline . . . . . . . . . . . . . . . . . 159 Figure 77. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 160 Figure 78. LQFP64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Figure 79. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 162 Figure 80. LQFP100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Figure 81. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 164 Figure 82. LQFP144 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Figure 83. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Figure 84. LQFP176 24 x 24 mm, 176-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 167 Figure 85. LQFP176 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Figure 86. USB controller configured as peripheral-only and used in Full speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Figure 87. USB controller configured as host-only and used in full speed mode. . . . . . . . . . . . . . . . 171 List of figures STM32F405xx, STM32F407xx 10/185 DocID022152 Rev 4 Figure 88. USB controller configured in dual mode and used in full speed mode . . . . . . . . . . . . . . . 172 Figure 89. USB controller configured as peripheral, host, or dual-mode and used in high speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Figure 90. MII mode using a 25 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Figure 91. RMII with a 50 MHz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Figure 92. RMII with a 25 MHz crystal and PHY with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 DocID022152 Rev 4 11/185 STM32F405xx, STM32F407xx Introduction 1 Introduction This datasheet provides the description of the STM32F405xx and STM32F407xx lines of microcontrollers. For more details on the whole STMicroelectronics STM32™ family, please refer to Section 2.1: Full compatibility throughout the family. The STM32F405xx and STM32F407xx datasheet should be read in conjunction with the STM32F4xx reference manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the Cortex™-M4 core, please refer to the Cortex™-M4 programming manual (PM0214) available from www.st.com. Description STM32F405xx, STM32F407xx 12/185 DocID022152 Rev 4 2 Description The STM32F405xx and STM32F407xx family is based on the high-performance ARM® Cortex™-M4 32-bit RISC core operating at a frequency of up to 168 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all ARM singleprecision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security. The Cortex-M4 core with FPU will be referred to as Cortex-M4F throughout this document. The STM32F405xx and STM32F407xx family incorporates high-speed embedded memories (Flash memory up to 1 Mbyte, up to 192 Kbytes of SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, three AHB buses and a 32-bit multi-AHB bus matrix. All devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve general-purpose 16-bit timers including two PWM timers for motor control, two general-purpose 32-bit timers. a true random number generator (RNG). They also feature standard and advanced communication interfaces. • Up to three I2Cs • Three SPIs, two I2Ss full duplex. To achieve audio class accuracy, the I2S peripherals can be clocked via a dedicated internal audio PLL or via an external clock to allow synchronization. • Four USARTs plus two UARTs • An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the ULPI), • Two CANs • An SDIO/MMC interface • Ethernet and the camera interface available on STM32F407xx devices only. New advanced peripherals include an SDIO, an enhanced flexible static memory control (FSMC) interface (for devices offered in packages of 100 pins and more), a camera interface for CMOS sensors. Refer to Table 2: STM32F405xx and STM32F407xx: features and peripheral counts for the list of peripherals available on each part number. The STM32F405xx and STM32F407xx family operates in the –40 to +105 °C temperature range from a 1.8 to 3.6 V power supply. The supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range using an external power supply supervisor: refer to Section : Internal reset OFF. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F405xx and STM32F407xx family offers devices in various packages ranging from 64 pins to 176 pins. The set of included peripherals changes with the device chosen. These features make the STM32F405xx and STM32F407xx microcontroller family suitable for a wide range of applications: • Motor drive and application control • Medical equipment • Industrial applications: PLC, inverters, circuit breakers • Printers, and scanners • Alarm systems, video intercom, and HVAC • Home audio appliances STM32F405xx, STM32F407xx Description DocID022152 Rev 4 13/185 Figure 5 shows the general block diagram of the device family. Table 2. STM32F405xx and STM32F407xx: features and peripheral counts Peripherals STM32F405RG STM32F405OG STM32F405VG STM32F405ZG STM32F405OE STM32F407Vx STM32F407Zx STM32F407Ix Flash memory in Kbytes 1024 512 512 1024 512 1024 512 1024 SRAM in Kbytes System 192(112+16+64) Backup 4 FSMC memory controller No Yes(1) Ethernet No Yes Timers Generalpurpose 10 Advanced -control 2 Basic 2 IWDG Yes WWDG Yes RTC Yes Random number generator Yes Description STM32F405xx, STM32F407xx 14/185 DocID022152 Rev 4 Communi cation interfaces SPI / I2S 3/2 (full duplex)(2) I2C 3 USART/ UART 4/2 USB OTG FS Yes USB OTG HS Yes CAN 2 SDIO Yes Camera interface No Yes GPIOs 51 72 82 114 72 82 114 140 12-bit ADC Number of channels 3 16 13 16 24 13 16 24 24 12-bit DAC Number of channels Yes 2 Maximum CPU frequency 168 MHz Operating voltage 1.8 to 3.6 V(3) Operating temperatures Ambient temperatures: –40 to +85 °C /–40 to +105 °C Junction temperature: –40 to + 125 °C Package LQFP64 WLCSP90 LQFP100 LQFP144 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 1. For the LQFP100 and WLCSP90 packages, only FSMC Bank1 or Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. 2. The SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode. 3. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). Table 2. STM32F405xx and STM32F407xx: features and peripheral counts Peripherals STM32F405RG STM32F405OG STM32F405VG STM32F405ZG STM32F405OE STM32F407Vx STM32F407Zx STM32F407Ix DocID022152 Rev 4 15/185 STM32F405xx, STM32F407xx Description 2.1 Full compatibility throughout the family The STM32F405xx and STM32F407xx are part of the STM32F4 family. They are fully pinto- pin, software and feature compatible with the STM32F2xx devices, allowing the user to try different memory densities, peripherals, and performances (FPU, higher frequency) for a greater degree of freedom during the development cycle. The STM32F405xx and STM32F407xx devices maintain a close compatibility with the whole STM32F10xxx family. All functional pins are pin-to-pin compatible. The STM32F405xx and STM32F407xx, however, are not drop-in replacements for the STM32F10xxx devices: the two families do not have the same power scheme, and so their power pins are different. Nonetheless, transition from the STM32F10xxx to the STM32F40x family remains simple as only a few pins are impacted. Figure 4, Figure 3, Figure 2, and Figure 1 give compatible board designs between the STM32F40x, STM32F2xxx, and STM32F10xxx families. Figure 1. Compatible board design between STM32F10xx/STM32F4xx for LQFP64 31 1 16 17 32 48 33 64 49 47 VSS VSS VSS VSS 0 Ω resistor or soldering bridge present for the STM32F10xx configuration, not present in the STM32F4xx configuration ai18489 Description STM32F405xx, STM32F407xx 16/185 DocID022152 Rev 4 Figure 2. Compatible board design STM32F10xx/STM32F2xx/STM32F4xx for LQFP100 package Figure 3. Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package 20 49 1 25 26 50 75 51 100 76 73 19 VSS VSS VDD VSS VSS VSS 0 ΩΩ resistor or soldering bridge present for the STM32F10xxx configuration, not present in the STM32F4xx configuration ai18488c 99 (VSS) VDD VSS Two 0 Ω resistors connected to: - VSS for the STM32F10xx - VSS for the STM32F4xx VSS for STM32F10xx VDD for STM32F4xx - VSS, VDD or NC for the STM32F2xx ai18487d 31 71 1 36 37 72 108 73 144 109 VSS 0 Ω resistor or soldering bridge present for the STM32F10xx configuration, not present in the STM32F4xx configuration 106 VSS 30 Two 0 Ω resistors connected to: - VSS for the STM32F10xx - VDD or signal from external power supply supervisor for the STM32F4xx VDD VSS VSS VSS 143 (PDR_ON) VDD VSS VSS for STM32F10xx VDD for STM32F4xx - VSS, VDD or NC for the STM32F2xx Signal from external power supply supervisor DocID022152 Rev 4 17/185 STM32F405xx, STM32F407xx Description Figure 4. Compatible board design between STM32F2xx and STM32F4xx for LQFP176 and BGA176 packages MS19919V3 1 44 45 88 132 89 176 133 Two 0 Ω resistors connected to: - VSS, VDD or NC for the STM32F2xx - VDD or signal from external power supply supervisor for the STM32F4xx 171 (PDR_ON) VDDVSS Signal from external power supply supervisor Description STM32F405xx, STM32F407xx 18/185 DocID022152 Rev 4 2.2 Device overview Figure 5. STM32F40x block diagram 1. The timers connected to APB2 are clocked from TIMxCLK up to 168 MHz, while the timers connected to APB1 are clocked from TIMxCLK either up to 84 MHz or 168 MHz, depending on TIMPRE bit configuration in the RCC_DCKCFGR register. 2. The camera interface and ethernet are available only on STM32F407xx devices. MS19920V3 GPIO PORT A AHB/APB2 140 AF PA[15:0] TIM1 / PWM 4 compl. channels (TIM1_CH1[1:4]N, 4 channels (TIM1_CH1[1:4]ETR, BKIN as AF RX, TX, CK, CTS, RTS as AF MOSI, MISO, SCK, NSS as AF APB 1 30M Hz 8 analog inputs common to the 3 ADCs VDDREF_ADC MOSI/SD, MISO/SD_ext, SCK/CK NSS/WS, MCK as AF TX, RX DAC1_OUT as AF ITF WWDG 4 KB BKPSRAM RTC_AF1 OSC32_IN OSC32_OUT VDDA, VSSA NRST 16b SDIO / MMC D[7:0] CMD, CK as AF VBAT = 1.65 to 3.6 V DMA2 SCL, SDA, SMBA as AF JTAG & SW ARM Cortex-M4 168 MHz ETM NVIC MPU TRACECLK TRACED[3:0] Ethernet MAC 10/100 DMA/ FIFO MII or RMII as AF MDIO as AF USB OTG HS DP, DM ULPI:CK, D[7:0], DIR, STP, NXT ID, VBUS, SOF DMA2 8 Streams FIFO ART ACCEL/ CACHE SRAM 112 KB CLK, NE [3:0], A[23:0], D[31:0], OEN, WEN, NBL[3:0], NL, NREG, NWAIT/IORDY, CD INTN, NIIS16 as AF RNG Camera interface HSYNC, VSYNC PUIXCLK, D[13:0] PHY USB OTG FS DP DM ID, VBUS, SOF FIFO AHB1 168 MHz PHY FIFO @VDDA @VDDA POR/PDR BOR Supply supervision @VDDA PVD Int POR reset XTAL 32 kHz MAN AGT RTC RC HS FCLK RC LS PWR interface IWDG @VBAT AWU Reset & clock control P L L1&2 PCLKx VDD = 1.8 to 3.6 V VSS VCAP1, VCPA2 Voltage regulator 3.3 to 1.2 V VDD Power managmt Backup register RTC_AF1 AHB bus-matrix 8S7M LS 2 channels as AF DAC1 DAC2 Flash up to 1 MB SRAM, PSRAM, NOR Flash, PC Card (ATA), NAND Flash External memory controller (FSMC) TIM6 TIM7 TIM2 TIM3 TIM4 TIM5 TIM12 TIM13 TIM14 USART2 USART3 UART4 UART5 SP3/I2S3 I2C1/SMBUS I2C2/SMBUS I2C3/SMBUS bxCAN1 bxCAN2 SPI1 EXT IT. WKUP D-BUS FIFO FPU APB142 MHz (max) SRAM 16 KB CCM data RAM 64 KB AHB3 AHB2 168 MHz NJTRST, JTDI, JTCK/SWCLK JTDO/SWD, JTDO I-BUS S-BUS DMA/ FIFO DMA1 8 Streams FIFO PB[15:0] PC[15:0] PD[15:0] PE[15:0] PF[15:0] PG[15:0] PH[15:0] PI[11:0] GPIO PORT B GPIO PORT C GPIO PORT D GPIO PORT E GPIO PORT F GPIO PORT G GPIO PORT H GPIO PORT I TIM8 / PWM 16b 4 compl. channels (TIM1_CH1[1:4]N, 4 channels (TIM1_CH1[1:4]ETR, BKIN as AF 1 channel as AF 1 channel as AF RX, TX, CK, CTS, RTS as AF 8 analog inputs common to the ADC1 & 2 8 analog inputs for ADC3 DAC2_OUT as AF 16b 16b SCL, SDA, SMBA as AF SCL, SDA, SMBA as AF MOSI/SD, MISO/SD_ext, SCK/CK NSS/WS, MCK as AF TX, RX RX, TX as AF RX, TX as AF RX, TX as AF CTS, RTS as AF RX, TX as AF CTS, RTS as AF 1 channel as AF smcard irDA smcard irDA 16b 16b 16b 1 channel as AF 2 channels as AF 32b 16b 16b 32b 4 channels 4 channels, ETR as AF 4 channels, ETR as AF 4 channels, ETR as AF DMA1 AHB/APB1 LS OSC_IN OSC_OUT HCLKx XTAL OSC 4- 16MHz FIFO SP2/I2S2 NIORD, IOWR, INT[2:3] ADC3 ADC2 ADC1 Temperature sensor IF TIM9 16b TIM10 16b TIM11 16b smcard irDA USART1 irDA smcard USART6 APB2 84 MHz @VDD @VDD @VDDA DocID022152 Rev 4 19/185 STM32F405xx, STM32F407xx Description 2.2.1 ARM® Cortex™-M4F core with embedded Flash and SRAM The ARM Cortex-M4F processor is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The ARM Cortex-M4F 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution. Its single precision FPU (floating point unit) speeds up software development by using metalanguage development tools, while avoiding saturation. The STM32F405xx and STM32F407xx family is compatible with all ARM tools and software. Figure 5 shows the general block diagram of the STM32F40x family. Note: Cortex-M4F is binary compatible with Cortex-M3. 2.2.2 Adaptive real-time memory accelerator (ART Accelerator™) The ART Accelerator™ is a memory accelerator which is optimized for STM32 industrystandard ARM® Cortex™-M4F processors. It balances the inherent performance advantage of the ARM Cortex-M4F over Flash memory technologies, which normally requires the processor to wait for the Flash memory at higher frequencies. To release the processor full 210 DMIPS performance at this frequency, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 128-bit Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 168 MHz. 2.2.3 Memory protection unit The memory protection unit (MPU) is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 2.2.4 Embedded Flash memory The STM32F40x devices embed a Flash memory of 512 Kbytes or 1 Mbytes available for storing programs and data. Description STM32F405xx, STM32F407xx 20/185 DocID022152 Rev 4 2.2.5 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a software signature during runtime, to be compared with a reference signature generated at link-time and stored at a given memory location. 2.2.6 Embedded SRAM All STM32F40x products embed: • Up to 192 Kbytes of system SRAM including 64 Kbytes of CCM (core coupled memory) data RAM RAM memory is accessed (read/write) at CPU clock speed with 0 wait states. • 4 Kbytes of backup SRAM This area is accessible only from the CPU. Its content is protected against possible unwanted write accesses, and is retained in Standby or VBAT mode. 2.2.7 Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs, Ethernet, USB HS) and the slaves (Flash memory, RAM, FSMC, AHB and APB peripherals) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. DocID022152 Rev 4 21/185 STM32F405xx, STM32F407xx Description Figure 6. Multi-AHB matrix 2.2.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: • SPI and I2S • I2C • USART • General-purpose, basic and advanced-control timers TIMx • DAC • SDIO • Camera interface (DCMI) • ADC. ARM Cortex-M4 GP DMA1 GP DMA2 MAC Ethernet USB OTG HS Bus matrix-S S0 S1 S2 S3 S4 S5 S6 S7 ICODE DCODE ACCEL Flash memory SRAM1 112 Kbyte SRAM2 16 Kbyte AHB1 peripherals AHB2 FSMC Static MemCtl M0 M1 M2 M3 M4 M5 M6 I-bus D-bus S-bus DMA_PI DMA_MEM1 DMA_MEM2 DMA_P2 ETHERNET_M USB_HS_M ai18490c CCM data RAM 64-Kbyte APB1 APB2 peripherals Description STM32F405xx, STM32F407xx 22/185 DocID022152 Rev 4 2.2.9 Flexible static memory controller (FSMC) The FSMC is embedded in the STM32F405xx and STM32F407xx family. It has four Chip Select outputs supporting the following modes: PCCard/Compact Flash, SRAM, PSRAM, NOR Flash and NAND Flash. Functionality overview: • Write FIFO • Maximum FSMC_CLK frequency for synchronous accesses is 60 MHz. LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 2.2.10 Nested vectored interrupt controller (NVIC) The STM32F405xx and STM32F407xx embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 82 maskable interrupt channels plus the 16 interrupt lines of the Cortex™-M4F. • Closely coupled NVIC gives low-latency interrupt processing • Interrupt entry vector table address passed directly to the core • Allows early processing of interrupts • Processing of late arriving, higher-priority interrupts • Support tail chaining • Processor state automatically saved • Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimum interrupt latency. 2.2.11 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 140 GPIOs can be connected to the 16 external interrupt lines. 2.2.12 Clocks and startup On reset the 16 MHz internal RC oscillator is selected as the default CPU clock. The 16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy over the full temperature range. The application can then select as system clock either the RC oscillator or an external 4-26 MHz clock source. This clock can be monitored for failure. If a failure is detected, the system automatically switches back to the internal RC oscillator and a software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing to increase the frequency up to 168 MHz. Similarly, full interrupt management of the PLL DocID022152 Rev 4 23/185 STM32F405xx, STM32F407xx Description clock entry is available when necessary (for example if an indirectly used external oscillator fails). Several prescalers allow the configuration of the three AHB buses, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the three AHB buses is 168 MHz while the maximum frequency of the high-speed APB domains is 84 MHz. The maximum allowed frequency of the low-speed APB domain is 42 MHz. The devices embed a dedicated PLL (PLLI2S) which allows to achieve audio class performance. In this case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to 192 kHz. 2.2.13 Boot modes At startup, boot pins are used to select one out of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM The boot loader is located in system memory. It is used to reprogram the Flash memory by using USART1 (PA9/PA10), USART3 (PC10/PC11 or PB10/PB11), CAN2 (PB5/PB13), USB OTG FS in Device mode (PA11/PA12) through DFU (device firmware upgrade). 2.2.14 Power supply schemes • VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through VDD pins. • VSSA, VDDA = 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. • VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Refer to Figure 21: Power supply scheme for more details. Note: VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). Refer to Table 2 in order to identify the packages supporting this option. 2.2.15 Power supply supervisor Internal reset ON On packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On all other packages, the power supply supervisor is always enabled. The device has an integrated power-on reset (POR) / power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is reached, the option byte loading process starts, either to confirm or modify default BOR threshold levels, or to disable BOR permanently. Three BOR thresholds are available through option bytes. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for an external reset circuit. Description STM32F405xx, STM32F407xx 24/185 DocID022152 Rev 4 The device also features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Internal reset OFF This feature is available only on packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled with the PDR_ON pin. An external power supply supervisor should monitor VDD and should maintain the device in reset mode as long as VDD is below a specified threshold. PDR_ON should be connected to this external power supply supervisor. Refer to Figure 7: Power supply supervisor interconnection with internal reset OFF. Figure 7. Power supply supervisor interconnection with internal reset OFF 1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range. The VDD specified threshold, below which the device must be maintained under reset, is 1.8 V (see Figure 7). This supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range. A comprehensive set of power-saving mode allows to design low-power applications. When the internal reset is OFF, the following integrated features are no more supported: • The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled • The brownout reset (BOR) circuitry is disabled • The embedded programmable voltage detector (PVD) is disabled • VBAT functionality is no more available and VBAT pin should be connected to VDD All packages, except for the LQFP64 and LQFP100, allow to disable the internal reset through the PDR_ON signal. MS31383V3 NRST VDD PDR_ON External VDD power supply supervisor Ext. reset controller active when VDD < 1.7 V or 1.8 V (1) VDD Application reset signal (optional) DocID022152 Rev 4 25/185 STM32F405xx, STM32F407xx Description Figure 8. PDR_ON and NRST control with internal reset OFF 1. PDR = 1.7 V for reduce temperature range; PDR = 1.8 V for all temperature range. 2.2.16 Voltage regulator The regulator has four operating modes: • Regulator ON – Main regulator mode (MR) – Low power regulator (LPR) – Power-down • Regulator OFF Regulator ON On packages embedding the BYPASS_REG pin, the regulator is enabled by holding BYPASS_REG low. On all other packages, the regulator is always enabled. There are three power modes configured by software when regulator is ON: • MR is used in the nominal regulation mode (With different voltage scaling in Run) In Main regulator mode (MR mode), different voltage scaling are provided to reach the best compromise between maximum frequency and dynamic power consumption. Refer to Table 14: General operating conditions. • LPR is used in the Stop modes The LP regulator mode is configured by software when entering Stop mode. • Power-down is used in Standby mode. The Power-down mode is activated only when entering in Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption. The contents of the registers and SRAM are lost) MS19009V6 VDD time PDR = 1.7 V or 1.8 V (1) time NRST PDR_ON PDR_ON Reset by other source than power supply supervisor Description STM32F405xx, STM32F407xx 26/185 DocID022152 Rev 4 Two external ceramic capacitors should be connected on VCAP_1 & VCAP_2 pin. Refer to Figure 21: Power supply scheme and Figure 16: VCAP_1/VCAP_2 operating conditions. All packages have regulator ON feature. Regulator OFF This feature is available only on packages featuring the BYPASS_REG pin. The regulator is disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply externally a V12 voltage source through VCAP_1 and VCAP_2 pins. Since the internal voltage scaling is not manage internally, the external voltage value must be aligned with the targetted maximum frequency. Refer to Table 14: General operating conditions. The two 2.2 μF ceramic capacitors should be replaced by two 100 nF decoupling capacitors. Refer to Figure 21: Power supply scheme When the regulator is OFF, there is no more internal monitoring on V12. An external power supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin should be used for this purpose, and act as power-on reset on V12 power domain. In regulator OFF mode the following features are no more supported: • PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power domain which is not reset by the NRST pin. • As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required. Figure 9. Regulator OFF ai18498V4 External VCAP_1/2 power supply supervisor Ext. reset controller active when VCAP_1/2 < Min V12 V12 VCAP_1 VCAP_2 BYPASS_REG VDD PA0 NRST Application reset signal (optional) VDD V12 DocID022152 Rev 4 27/185 STM32F405xx, STM32F407xx Description The following conditions must be respected: • VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains. • If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for VDD to reach 1.8 V, then PA0 should be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach V12 minimum value and until VDD reaches 1.8 V (see Figure 10). • Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower than the time for VDD to reach 1.8 V, then PA0 could be asserted low externally (see Figure 11). • If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.8 V, then a reset must be asserted on PA0 pin. Note: The minimum value of V12 depends on the maximum frequency targeted in the application (see Table 14: General operating conditions). Figure 10. Startup in regulator OFF mode: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization 1. This figure is valid both whatever the internal reset mode (onON or OFFoff). 2. PDR = 1.7 V for reduced temperature range; PDR = 1.8 V for all temperature ranges. ai18491e VDD time Min V12 PDR = 1.7 V or 1.8 V (2) VCAP_1/VCAP_2 V12 NRST time Description STM32F405xx, STM32F407xx 28/185 DocID022152 Rev 4 Figure 11. Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization 1. This figure is valid both whatever the internal reset mode (onON or offOFF). 2. PDR = 1.7 V for a reduced temperature range; PDR = 1.8 V for all temperature ranges. 2.2.17 Regulator ON/OFF and internal reset ON/OFF availability 2.2.18 Real-time clock (RTC), backup SRAM and backup registers The backup domain of the STM32F405xx and STM32F407xx includes: • The real-time clock (RTC) • 4 Kbytes of backup SRAM • 20 backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binarycoded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are performed automatically. The RTC provides a programmable alarm and programmable periodic interrupts with wakeup from Stop and Standby modes. The sub-seconds value is also available in binary format. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC VDD time Min V12 VCAP_1/VCAP_2 V12 PA0 asserted externally NRST time ai18492d PDR = 1.7 V or 1.8 V (2) Table 3. Regulator ON/OFF and internal reset ON/OFF availability Regulator ON Regulator OFF Internal reset ON Internal reset OFF LQFP64 LQFP100 Yes No Yes No LQFP144 LQFP176 Yes PDR_ON set to VDD Yes PDR_ON connected to an external power supply supervisor WLCSP90 UFBGA176 Yes BYPASS_REG set to VSS Yes BYPASS_REG set to VDD DocID022152 Rev 4 29/185 STM32F405xx, STM32F407xx Description has a typical frequency of 32 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. Two alarm registers are used to generate an alarm at a specific time and calendar fields can be independently masked for alarm comparison. To generate a periodic interrupt, a 16-bit programmable binary auto-reload downcounter with programmable resolution is available and allows automatic wakeup and periodic alarms from every 120 μs to every 36 hours. A 20-bit prescaler is used for the time base clock. It is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. The 4-Kbyte backup SRAM is an EEPROM-like memory area. It can be used to store data which need to be retained in VBAT and standby mode. This memory area is disabled by default to minimize power consumption (see Section 2.2.19: Low-power modes). It can be enabled by software. The backup registers are 32-bit registers used to store 80 bytes of user application data when VDD power is not present. Backup registers are not reset by a system, a power reset, or when the device wakes up from the Standby mode (see Section 2.2.19: Low-power modes). Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date. Like backup SRAM, the RTC and backup registers are supplied through a switch that is powered either from the VDD supply when present or from the VBAT pin. 2.2.19 Low-power modes The STM32F405xx and STM32F407xx support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Stop mode The Stop mode achieves the lowest power consumption while retaining the contents of SRAM and registers. All clocks in the V12 domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup). • Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire V12 domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Description STM32F405xx, STM32F407xx 30/185 DocID022152 Rev 4 Standby mode, the SRAM and register contents are lost except for registers in the backup domain and the backup SRAM when selected. The device exits the Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm / wakeup / tamper /time stamp event occurs. The standby mode is not supported when the embedded voltage regulator is bypassed and the V12 domain is controlled by an external power. 2.2.20 VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery, an external supercapacitor, or from VDD when no external battery and an external supercapacitor are present. VBAT operation is activated when VDD is not present. The VBAT pin supplies the RTC, the backup registers and the backup SRAM. Note: When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. When PDR_ON pin is not connected to VDD (internal reset OFF), the VBAT functionality is no more available and VBAT pin should be connected to VDD. 2.2.21 Timers and watchdogs The STM32F405xx and STM32F407xx devices include two advanced-control timers, eight general-purpose timers, two basic timers and two watchdog timers. All timer counters can be frozen in debug mode. Table 4 compares the features of the advanced-control, general-purpose and basic timers. Table 4. Timer feature comparison Timer type Timer Counter resolutio n Counter type Prescaler factor DMA request generatio n Capture/ compare channels Complementar y output Max interface clock (MHz) Max timer clock (MHz) Advanced -control TIM1, TIM8 16-bit Up, Down, Up/dow n Any integer between 1 and 65536 Yes 4 Yes 84 168 DocID022152 Rev 4 31/185 STM32F405xx, STM32F407xx Description Advanced-control timers (TIM1, TIM8) The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead times. They can also be considered as complete general-purpose timers. Their 4 independent channels can be used for: • Input capture • Output compare • PWM generation (edge- or center-aligned modes) • One-pulse mode output If configured as standard 16-bit timers, they have the same features as the general-purpose TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0- 100%). The advanced-control timer can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining. TIM1 and TIM8 support independent DMA request generation. General purpose TIM2, TIM5 32-bit Up, Down, Up/dow n Any integer between 1 and 65536 Yes 4 No 42 84 TIM3, TIM4 16-bit Up, Down, Up/dow n Any integer between 1 and 65536 Yes 4 No 42 84 TIM9 16-bit Up Any integer between 1 and 65536 No 2 No 84 168 TIM10 , TIM11 16-bit Up Any integer between 1 and 65536 No 1 No 84 168 TIM12 16-bit Up Any integer between 1 and 65536 No 2 No 42 84 TIM13 , TIM14 16-bit Up Any integer between 1 and 65536 No 1 No 42 84 Basic TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 42 84 Table 4. Timer feature comparison (continued) Timer type Timer Counter resolutio n Counter type Prescaler factor DMA request generatio n Capture/ compare channels Complementar y output Max interface clock (MHz) Max timer clock (MHz) Description STM32F405xx, STM32F407xx 32/185 DocID022152 Rev 4 General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F40x devices (see Table 4 for differences). • TIM2, TIM3, TIM4, TIM5 The STM32F40x include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3, and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16- bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input capture/output compare/PWMs on the largest packages. The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the Timer Link feature for synchronization or event chaining. Any of these general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 4 hall-effect sensors. • TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14 These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9 and TIM12 have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases. Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger and waveform generation. They can also be used as a generic 16-bit time base. TIM6 and TIM7 support independent DMA request generation. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. DocID022152 Rev 4 33/185 STM32F405xx, STM32F407xx Description SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard downcounter. It features: • A 24-bit downcounter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0 • Programmable clock source. 2.2.22 Inter-integrated circuit interface (I²C) Up to three I²C bus interfaces can operate in multimaster and slave modes. They can support the Standard-mode (up to 100 kHz) and Fast-mode (up to 400 kHz) . They support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus. 2.2.23 Universal synchronous/asynchronous receiver transmitters (USART) The STM32F405xx and STM32F407xx embed four universal synchronous/asynchronous receiver transmitters (USART1, USART2, USART3 and USART6) and two universal asynchronous receiver transmitters (UART4 and UART5). These six interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART1 and USART6 interfaces are able to communicate at speeds of up to 10.5 Mbit/s. The other available interfaces communicate at up to 5.25 Mbit/s. USART1, USART2, USART3 and USART6 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller. Description STM32F405xx, STM32F407xx 34/185 DocID022152 Rev 4 2.2.24 Serial peripheral interface (SPI) The STM32F40x feature up to three SPIs in slave and master modes in full-duplex and simplex communication modes. SPI1 can communicate at up to 42 Mbits/s, SPI2 and SPI3 can communicate at up to 21 Mbit/s. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. The SPI interface can be configured to operate in TI mode for communications in master mode and slave mode. 2.2.25 Inter-integrated sound (I2S) Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can be operated in master or slave mode, in full duplex and half-duplex communication modes, and can be configured to operate with a 16-/32-bit resolution as an input or output channel. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. All I2Sx can be served by the DMA controller. 2.2.26 Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I2S application. It allows to achieve error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. Table 5. USART feature comparison USART name Standard features Modem (RTS/ CTS) LIN SPI master irDA Smartcard (ISO 7816) Max. baud rate in Mbit/s (oversampling by 16) Max. baud rate in Mbit/s (oversampling by 8) APB mapping USART1 X X X X X X 5.25 10.5 APB2 (max. 84 MHz) USART2 X X X X X X 2.62 5.25 APB1 (max. 42 MHz) USART3 X X X X X X 2.62 5.25 APB1 (max. 42 MHz) UART4 X - X - X - 2.62 5.25 APB1 (max. 42 MHz) UART5 X - X - X - 2.62 5.25 APB1 (max. 42 MHz) USART6 X X X X X X 5.25 10.5 APB2 (max. 84 MHz) DocID022152 Rev 4 35/185 STM32F405xx, STM32F407xx Description The PLLI2S configuration can be modified to manage an I2S sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces. The audio PLL can be programmed with very low error to obtain sampling rates ranging from 8 KHz to 192 KHz. In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S flow with an external PLL (or Codec output). 2.2.27 Secure digital input/output interface (SDIO) An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 48 MHz, and is compliant with the SD Memory Card Specification Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1. 2.2.28 Ethernet MAC interface with dedicated DMA and IEEE 1588 support Peripheral available only on the STM32F407xx devices. The STM32F407xx devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for ethernet LAN communications through an industry-standard mediumindependent interface (MII) or a reduced medium-independent interface (RMII). The STM32F407xx requires an external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.). the PHY is connected to the STM32F407xx MII port using 17 signals for MII or 9 signals for RMII, and can be clocked using the 25 MHz (MII) from the STM32F407xx. The STM32F407xx includes the following features: • Supports 10 and 100 Mbit/s rates • Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM and the descriptors (see the STM32F40x reference manual for details) • Tagged MAC frame support (VLAN support) • Half-duplex (CSMA/CD) and full-duplex operation • MAC control sublayer (control frames) support • 32-bit CRC generation and removal • Several address filtering modes for physical and multicast address (multicast and group addresses) • 32-bit status code for each transmitted or received frame • Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive FIFO are both 2 Kbytes. • Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008 (PTP V2) with the time stamp comparator connected to the TIM2 input • Triggers interrupt when system time becomes greater than target time Description STM32F405xx, STM32F407xx 36/185 DocID022152 Rev 4 2.2.29 Controller area network (bxCAN) The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one CAN is used). 256 bytes of SRAM are allocated for each CAN. 2.2.30 Universal serial bus on-the-go full-speed (OTG_FS) The STM32F405xx and STM32F407xx embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: • Combined Rx and Tx FIFO size of 320 × 35 bits with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 4 bidirectional endpoints • 8 host channels with periodic OUT support • HNP/SNP/IP inside (no need for any external resistor) • For OTG/Host modes, a power switch is needed in case bus-powered devices are connected 2.2.31 Universal serial bus on-the-go high-speed (OTG_HS) The STM32F405xx and STM32F407xx devices embed a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral. The USB OTG HS supports both full-speed and high-speed operations. It integrates the transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI) for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an external PHY device connected to the ULPI is required. The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL connected to the HSE oscillator. The major features are: • Combined Rx and Tx FIFO size of 1 Kbit × 35 with dynamic FIFO sizing • Supports the session request protocol (SRP) and host negotiation protocol (HNP) • 6 bidirectional endpoints • 12 host channels with periodic OUT support • Internal FS OTG PHY support • External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is connected to the microcontroller ULPI port through 12 signals. It can be clocked using the 60 MHz output. • Internal USB DMA • HNP/SNP/IP inside (no need for any external resistor) • for OTG/Host modes, a power switch is needed in case bus-powered devices are connected DocID022152 Rev 4 37/185 STM32F405xx, STM32F407xx Description 2.2.32 Digital camera interface (DCMI) The camera interface is not available in STM32F405xx devices. STM32F407xx products embed a camera interface that can connect with camera modules and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera interface can sustain a data transfer rate up to 54 Mbyte/s at 54 MHz. It features: • Programmable polarity for the input pixel clock and synchronization signals • Parallel data communication can be 8-, 10-, 12- or 14-bit • Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2 progressive video, RGB 565 progressive video or compressed data (like JPEG) • Supports continuous mode or snapshot (a single frame) mode • Capability to automatically crop the image 2.2.33 Random number generator (RNG) All STM32F405xx and STM32F407xx products embed an RNG that delivers 32-bit random numbers generated by an integrated analog circuit. 2.2.34 General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed selection to better manage internal noise, power consumption and electromagnetic emission. The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing to the I/Os registers. Fast I/O handling allowing maximum I/O toggling up to 84 MHz. 2.2.35 Analog-to-digital converters (ADCs) Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: • Simultaneous sample and hold • Interleaved sample and hold The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1, TIM2, TIM3, TIM4, TIM5, or TIM8 timer. 2.2.36 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 1.8 V and 3.6 V. The temperature sensor is internally Description STM32F405xx, STM32F407xx 38/185 DocID022152 Rev 4 connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. As the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. If an accurate temperature reading is needed, then an external temperature sensor part should be used. 2.2.37 Digital-to-analog converter (DAC) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. This dual digital Interface supports the following features: • two DAC converters: one for each output channel • 8-bit or 12-bit monotonic output • left or right data alignment in 12-bit mode • synchronized update capability • noise-wave generation • triangular-wave generation • dual DAC channel independent or simultaneous conversions • DMA capability for each channel • external triggers for conversion • input voltage reference VREF+ Eight DAC trigger inputs are used in the device. The DAC channels are triggered through the timer update outputs that are also connected to different DMA streams. 2.2.38 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 2.2.39 Embedded Trace Macrocell™ The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F40x through a small number of ETM pins to an external hardware trace port analyser (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer that runs the debugger software. TPA hardware is commercially available from common development tool vendors. The Embedded Trace Macrocell operates with third party debugger software tools. DocID022152 Rev 4 39/185 STM32F405xx, STM32F407xx Pinouts and pin description 3 Pinouts and pin description Figure 12. STM32F40x LQFP64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VBAT PC14 PC15 NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0_WKUP PA1 PA2 VDD PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 VDD VCAP_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VCAP_1 VDD LQFP64 ai18493b PC13 PH0 PH1 VSS Pinouts and pin description STM32F405xx, STM32F407xx 40/185 DocID022152 Rev 4 Figure 13. STM32F40x LQFP100 pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 123456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PE2 PE3 PE4 PE5 PE6 VBAT PC14 PC15 VSS VDD PH0 NRST PC0 PC1 PC2 PC3 VDD VSSA VREF+ VDDA PA0 PA1 PA2 VDD VSS VCAP_2 PA13 PA12 PA 11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VDD VDD VSS PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ai18495c LQFP100 PC13 PH1 DocID022152 Rev 4 41/185 STM32F405xx, STM32F407xx Pinouts and pin description Figure 14. STM32F40x LQFP144 pinout VDD PDR_ON PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD VSS PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD VSS PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 PE2 VDD PE3 VSS PE4 PE5 PA13 PE6 PA12 VBAT PA11 PC13 PA10 PC14 PA9 PC15 PA8 PF0 PC9 PF1 PC8 PF2 PC7 PF3 PC6 PF4 VDD PF5 VSS VSS PG8 VDD PG7 PF6 PG6 PF7 PG5 PF8 PG4 PF9 PG3 PF10 PG2 PH0 PD15 PH1 PD14 NRST VDD PC0 VSS PC1 PD13 PC2 PD12 PC3 PD11 VSSA VDD PD10 PD9 VREF+ PD8 VDDA PB15 PA0 PB14 PA1 PB13 PA2 PB12 PA3 VSS VDD PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VDD PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 VSS VDD PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VCAP_1 VDD 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 109 123456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 72 LQFP144 120 119 118 117 116 115 114 113 112 111 110 61 62 63 64 65 66 67 68 69 70 71 26 27 28 29 30 31 32 33 34 35 36 83 82 81 80 79 78 77 76 75 74 73 ai18496b VCAP_2 VSS Pinouts and pin description STM32F405xx, STM32F407xx 42/185 DocID022152 Rev 4 Figure 15. STM32F40x LQFP176 pinout MS19916V3 PDR_ON PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PI7 PI6 PE2 PE3 PE4 PE5 PA13 PE6 PA12 VBAT PA11 PI8 PA10 PC14 PA9 PC15 PA8 PF0 PC9 PF1 PC8 PF2 PC7 PF3 PC6 PF4 PF5 PG8 PG7 PF6 PG6 PF7 PG5 PF8 PG4 PF9 PG3 PF10 PG2 PH0 PD15 PH1 PD14 NRST V PC0 V PC1 PD13 PC2 PD12 PC3 PD11 PD10 PD9 VREF+ PD8 PB15 PA0 PB14 PA1 PB13 PA2 PB12 PA3 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PF11 PF12 VSS PF13 PF14 PF15 PG0 PG1 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 141 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 80 LQFP176 152 151 150 149 148 147 146 145 144 143 142 69 70 71 72 73 74 75 76 77 78 79 26 27 28 29 30 31 32 33 34 35 36 107 106 105 104 103 102 101 100 99 98 89 PI4 PA15 PA14 PI3 PI2 PI5 140 139 138 137 136 135 134 133 PH4 PH5 PH6 PH7 PH8 PH9 PH10 PH11 88 81 82 83 84 85 86 87 PI1 PI0 PH15 PH14 PH13 PH12 96 95 94 93 92 91 90 97 37 38 39 40 41 42 43 44 PC13 PI9 PI10 PI11 VSS PH2 PH3 VDD VSS VDD VDDA VSSA VDDA BYPASS_REG VDD VDD VSS VDD VCAP_1 VDD VSS VDD VCAP_2 VSS VDD VSS VDD VSS VDD VSS VDD VDD VSS VDD VSS VDD DocID022152 Rev 4 43/185 STM32F405xx, STM32F407xx Pinouts and pin description Figure 16. STM32F40x UFBGA176 ballout 1. This figure shows the package top view. ai18497b 1 2 3 9 10 11 12 13 14 15 A PE3 PE2 PE1 PE0 PB8 PB5 PG14 PG13 PB4 PB3 PD7 PC12 PA15 PA14 PA13 B PE4 PE5 PE6 PB9 PB7 PB6 PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 PA12 C VBAT PI7 PI6 PI5 VDD PDR_ON VDD VDD VDD PG9 PD5 PD1 PI3 PI2 PA11 D PC13 PI8 PI9 PI4 BOOT0 VSS VSS VSS PD4 PD3 PD2 PH15 PI1 PA10 E PC14 PF0 PI10 PI11 PH13 PH14 PI0 PA9 F PC15 VSS VDD PH2 VSS VSS VSS VSS VSS VSS VCAP_2 PC9 PA8 G PH0 VSS VDD PH3 VSS VSS VSS VSS VSS VSS VDD PC8 PC7 H PH1 PF2 PF1 PH4 VSS VSS VSS VSS VSS VSS VDD PG8 PC6 J NRST PF3 PF4 PH5 VSS VSS VSS VSS VSS VDD VDD PG7 PG6 K PF7 PF6 PF5 VDD VSS VSS VSS VSS VSS PH12 PG5 PG4 PG3 L PF10 PF9 PF8 BYPASS_ REG PH11 PH10 PD15 PG2 M VSSA PC0 PC1 PC2 PC3 PB2 PG1 VSS VSS VCAP_1 PH6 PH8 PH9 PD14 PD13 N VREF- PA1 PA0 PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10 P VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8 R VDDA PA3 PA7 PB1 PB0 PF11 PF14 PE7 PE10 PE12 PE15 PB10 PB11 PB14 PB15 VSS 4 5 6 7 8 Pinouts and pin description STM32F405xx, STM32F407xx 44/185 DocID022152 Rev 4 Figure 17. STM32F40x WLCSP90 ballout 1. This figure shows the package bump view. A VBAT PC13 PDR_ON PB4 PD7 PD4 PC12 B PC15 VDD PB7 PB3 PD6 PD2 PA15 C PA0 VSS PB6 PD5 PD1 PC11 PI0 D PC2 PB8 PA13 E PC3 VSS F PH1 PA1 G NRST H VSSA J PA2 PA 4 PA7 PB2 PE11 PB11 PB12 MS30402V1 1 PA14 PI1 PA12 PA10 PA9 PC0 PC9 PC8 PH0 PB13 PC6 PD14 PD12 PE8 PE12 BYPASS_ REG PD9 PD8 PE9 PB14 10 9 8 7 6 5 4 3 2 VDD PC14 VCAP_2 PA11 PB5 PD0 PC10 PA8 VSS VDD VSS VDD PC7 VDD PE10 PE14 VCAP_1 PD15 PE13 PE15 PD10 PD11 PA3 PA6 PB1 PB10 PB15 PB9 BOOT0 VDDA PA5 PB0 PE7 Table 6. Legend/abbreviations used in the pinout table Name Abbreviation Definition Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name Pin type S Supply pin I Input only pin I/O Input / output pin I/O structure FT 5 V tolerant I/O TTa 3.3 V tolerant I/O directly connected to ADC B Dedicated BOOT0 pin RST Bidirectional reset pin with embedded weak pull-up resistor Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Alternate functions Functions selected through GPIOx_AFR registers Additional functions Functions directly selected/enabled through peripheral registers DocID022152 Rev 4 45/185 STM32F405xx, STM32F407xx Pinouts and pin description Table 7. STM32F40x pin and ball definitions Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 - - 1 1 A2 1 PE2 I/O FT TRACECLK/ FSMC_A23 / ETH_MII_TXD3 / EVENTOUT - - 2 2 A1 2 PE3 I/O FT TRACED0/FSMC_A19 / EVENTOUT - - 3 3 B1 3 PE4 I/O FT TRACED1/FSMC_A20 / DCMI_D4/ EVENTOUT - - 4 4 B2 4 PE5 I/O FT TRACED2 / FSMC_A21 / TIM9_CH1 / DCMI_D6 / EVENTOUT - - 5 5 B3 5 PE6 I/O FT TRACED3 / FSMC_A22 / TIM9_CH2 / DCMI_D7 / EVENTOUT 1 A10 6 6 C1 6 VBAT S - - - - D2 7 PI8 I/O FT (2)( 3) EVENTOUT RTC_TAMP1, RTC_TAMP2, RTC_TS 2 A9 7 7 D1 8 PC13 I/O FT (2) (3) EVENTOUT RTC_OUT, RTC_TAMP1, RTC_TS 3 B10 8 8 E1 9 PC14/OSC32_IN (PC14) I/O FT (2)( 3) EVENTOUT OSC32_IN(4) 4 B9 9 9 F1 10 PC15/ OSC32_OUT (PC15) I/O FT (2)( 3) EVENTOUT OSC32_OUT(4) - - - - D3 11 PI9 I/O FT CAN1_RX / EVENTOUT - - - - E3 12 PI10 I/O FT ETH_MII_RX_ER / EVENTOUT - - - - E4 13 PI11 I/O FT OTG_HS_ULPI_DIR / EVENTOUT - - - - F2 14 VSS S - - - - F3 15 VDD S - - - 10 E2 16 PF0 I/O FT FSMC_A0 / I2C2_SDA / EVENTOUT Pinouts and pin description STM32F405xx, STM32F407xx 46/185 DocID022152 Rev 4 - - - 11 H3 17 PF1 I/O FT FSMC_A1 / I2C2_SCL / EVENTOUT - - - 12 H2 18 PF2 I/O FT FSMC_A2 / I2C2_SMBA / EVENTOUT - - - 13 J2 19 PF3 I/O FT (4) FSMC_A3/EVENTOUT ADC3_IN9 - - - 14 J3 20 PF4 I/O FT (4) FSMC_A4/EVENTOUT ADC3_IN14 - - - 15 K3 21 PF5 I/O FT (4) FSMC_A5/EVENTOUT ADC3_IN15 - C9 10 16 G2 22 VSS S - B8 11 17 G3 23 VDD S - - - 18 K2 24 PF6 I/O FT (4) TIM10_CH1 / FSMC_NIORD/ EVENTOUT ADC3_IN4 - - - 19 K1 25 PF7 I/O FT (4) TIM11_CH1/FSMC_NREG / EVENTOUT ADC3_IN5 - - - 20 L3 26 PF8 I/O FT (4) TIM13_CH1 / FSMC_NIOWR/ EVENTOUT ADC3_IN6 - - - 21 L2 27 PF9 I/O FT (4) TIM14_CH1 / FSMC_CD/ EVENTOUT ADC3_IN7 - - - 22 L1 28 PF10 I/O FT (4) FSMC_INTR/ EVENTOUT ADC3_IN8 5 F10 12 23 G1 29 PH0/OSC_IN (PH0) I/O FT EVENTOUT OSC_IN(4) 6 F9 13 24 H1 30 PH1/OSC_OUT (PH1) I/O FT EVENTOUT OSC_OUT(4) 7 G10 14 25 J1 31 NRST I/O RS T 8 E10 15 26 M2 32 PC0 I/O FT (4) OTG_HS_ULPI_STP/ EVENTOUT ADC123_IN10 9 - 16 27 M3 33 PC1 I/O FT (4) ETH_MDC/ EVENTOUT ADC123_IN11 10 D10 17 28 M4 34 PC2 I/O FT (4) SPI2_MISO / OTG_HS_ULPI_DIR / ETH_MII_TXD2 /I2S2ext_SD/ EVENTOUT ADC123_IN12 Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 DocID022152 Rev 4 47/185 STM32F405xx, STM32F407xx Pinouts and pin description 11 E9 18 29 M5 35 PC3 I/O FT (4) SPI2_MOSI / I2S2_SD / OTG_HS_ULPI_NXT / ETH_MII_TX_CLK/ EVENTOUT ADC123_IN13 - - 19 30 G3 36 VDD S 12 H10 20 31 M1 37 VSSA S - - - - N1 - VREF– S - - 21 32 P1 38 VREF+ S 13 G9 22 33 R1 39 VDDA S 14 C10 23 34 N3 40 PA0/WKUP (PA0) I/O FT (5) USART2_CTS/ UART4_TX/ ETH_MII_CRS / TIM2_CH1_ETR/ TIM5_CH1 / TIM8_ETR/ EVENTOUT ADC123_IN0/WKUP(4 ) 15 F8 24 35 N2 41 PA1 I/O FT (4) USART2_RTS / UART4_RX/ ETH_RMII_REF_CLK / ETH_MII_RX_CLK / TIM5_CH2 / TIM2_CH2/ EVENTOUT ADC123_IN1 16 J10 25 36 P2 42 PA2 I/O FT (4) USART2_TX/TIM5_CH3 / TIM9_CH1 / TIM2_CH3 / ETH_MDIO/ EVENTOUT ADC123_IN2 - - - - F4 43 PH2 I/O FT ETH_MII_CRS/EVENTOU T - - - - G4 44 PH3 I/O FT ETH_MII_COL/EVENTOU T - - - - H4 45 PH4 I/O FT I2C2_SCL / OTG_HS_ULPI_NXT/ EVENTOUT - - - - J4 46 PH5 I/O FT I2C2_SDA/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 Pinouts and pin description STM32F405xx, STM32F407xx 48/185 DocID022152 Rev 4 17 H9 26 37 R2 47 PA3 I/O FT (4) USART2_RX/TIM5_CH4 / TIM9_CH2 / TIM2_CH4 / OTG_HS_ULPI_D0 / ETH_MII_COL/ EVENTOUT ADC123_IN3 18 E5 27 38 - - VSS S D9 L4 48 BYPASS_REG I FT 19 E4 28 39 K4 49 VDD S 20 J9 29 40 N4 50 PA4 I/O TTa (4) SPI1_NSS / SPI3_NSS / USART2_CK / DCMI_HSYNC / OTG_HS_SOF/ I2S3_WS/ EVENTOUT ADC12_IN4 /DAC_OUT1 21 G8 30 41 P4 51 PA5 I/O TTa (4) SPI1_SCK/ OTG_HS_ULPI_CK / TIM2_CH1_ETR/ TIM8_CH1N/ EVENTOUT ADC12_IN5/DAC_OU T2 22 H8 31 42 P3 52 PA6 I/O FT (4) SPI1_MISO / TIM8_BKIN/TIM13_CH1 / DCMI_PIXCLK / TIM3_CH1 / TIM1_BKIN/ EVENTOUT ADC12_IN6 23 J8 32 43 R3 53 PA7 I/O FT (4) SPI1_MOSI/ TIM8_CH1N / TIM14_CH1/TIM3_CH2/ ETH_MII_RX_DV / TIM1_CH1N / ETH_RMII_CRS_DV/ EVENTOUT ADC12_IN7 24 - 33 44 N5 54 PC4 I/O FT (4) ETH_RMII_RX_D0 / ETH_MII_RX_D0/ EVENTOUT ADC12_IN14 25 - 34 45 P5 55 PC5 I/O FT (4) ETH_RMII_RX_D1 / ETH_MII_RX_D1/ EVENTOUT ADC12_IN15 26 G7 35 46 R5 56 PB0 I/O FT (4) TIM3_CH3 / TIM8_CH2N/ OTG_HS_ULPI_D1/ ETH_MII_RXD2 / TIM1_CH2N/ EVENTOUT ADC12_IN8 Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 DocID022152 Rev 4 49/185 STM32F405xx, STM32F407xx Pinouts and pin description 27 H7 36 47 R4 57 PB1 I/O FT (4) TIM3_CH4 / TIM8_CH3N/ OTG_HS_ULPI_D2/ ETH_MII_RXD3 / TIM1_CH3N/ EVENTOUT ADC12_IN9 28 J7 37 48 M6 58 PB2/BOOT1 (PB2) I/O FT EVENTOUT - - - 49 R6 59 PF11 I/O FT DCMI_D12/ EVENTOUT - - - 50 P6 60 PF12 I/O FT FSMC_A6/ EVENTOUT - - - 51 M8 61 VSS S - - - 52 N8 62 VDD S - - - 53 N6 63 PF13 I/O FT FSMC_A7/ EVENTOUT - - - 54 R7 64 PF14 I/O FT FSMC_A8/ EVENTOUT - - - 55 P7 65 PF15 I/O FT FSMC_A9/ EVENTOUT - - - 56 N7 66 PG0 I/O FT FSMC_A10/ EVENTOUT - - - 57 M7 67 PG1 I/O FT FSMC_A11/ EVENTOUT - G6 38 58 R8 68 PE7 I/O FT FSMC_D4/TIM1_ETR/ EVENTOUT - H6 39 59 P8 69 PE8 I/O FT FSMC_D5/ TIM1_CH1N/ EVENTOUT - J6 40 60 P9 70 PE9 I/O FT FSMC_D6/TIM1_CH1/ EVENTOUT - - - 61 M9 71 VSS S - - - 62 N9 72 VDD S - F6 41 63 R9 73 PE10 I/O FT FSMC_D7/TIM1_CH2N/ EVENTOUT - J5 42 64 P10 74 PE11 I/O FT FSMC_D8/TIM1_CH2/ EVENTOUT - H5 43 65 R10 75 PE12 I/O FT FSMC_D9/TIM1_CH3N/ EVENTOUT - G5 44 66 N11 76 PE13 I/O FT FSMC_D10/TIM1_CH3/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 Pinouts and pin description STM32F405xx, STM32F407xx 50/185 DocID022152 Rev 4 - F5 45 67 P11 77 PE14 I/O FT FSMC_D11/TIM1_CH4/ EVENTOUT - G4 46 68 R11 78 PE15 I/O FT FSMC_D12/TIM1_BKIN/ EVENTOUT 29 H4 47 69 R12 79 PB10 I/O FT SPI2_SCK / I2S2_CK / I2C2_SCL/ USART3_TX / OTG_HS_ULPI_D3 / ETH_MII_RX_ER / TIM2_CH3/ EVENTOUT 30 J4 48 70 R13 80 PB11 I/O FT I2C2_SDA/USART3_RX/ OTG_HS_ULPI_D4 / ETH_RMII_TX_EN/ ETH_MII_TX_EN / TIM2_CH4/ EVENTOUT 31 F4 49 71 M10 81 VCAP_1 S 32 - 50 72 N10 82 VDD S - - - - M11 83 PH6 I/O FT I2C2_SMBA / TIM12_CH1 / ETH_MII_RXD2/ EVENTOUT - - - - N12 84 PH7 I/O FT I2C3_SCL / ETH_MII_RXD3/ EVENTOUT - - - - M12 85 PH8 I/O FT I2C3_SDA / DCMI_HSYNC/ EVENTOUT - - - - M13 86 PH9 I/O FT I2C3_SMBA / TIM12_CH2/ DCMI_D0/ EVENTOUT - - - - L13 87 PH10 I/O FT TIM5_CH1 / DCMI_D1/ EVENTOUT - - - - L12 88 PH11 I/O FT TIM5_CH2 / DCMI_D2/ EVENTOUT - - - - K12 89 PH12 I/O FT TIM5_CH3 / DCMI_D3/ EVENTOUT - - - - H12 90 VSS S - - - - J12 91 VDD S Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 DocID022152 Rev 4 51/185 STM32F405xx, STM32F407xx Pinouts and pin description 33 J3 51 73 P12 92 PB12 I/O FT SPI2_NSS / I2S2_WS / I2C2_SMBA/ USART3_CK/ TIM1_BKIN / CAN2_RX / OTG_HS_ULPI_D5/ ETH_RMII_TXD0 / ETH_MII_TXD0/ OTG_HS_ID/ EVENTOUT 34 J1 52 74 P13 93 PB13 I/O FT SPI2_SCK / I2S2_CK / USART3_CTS/ TIM1_CH1N /CAN2_TX / OTG_HS_ULPI_D6 / ETH_RMII_TXD1 / ETH_MII_TXD1/ EVENTOUT OTG_HS_VBUS 35 J2 53 75 R14 94 PB14 I/O FT SPI2_MISO/ TIM1_CH2N / TIM12_CH1 / OTG_HS_DM/ USART3_RTS / TIM8_CH2N/I2S2ext_SD/ EVENTOUT 36 H1 54 76 R15 95 PB15 I/O FT SPI2_MOSI / I2S2_SD/ TIM1_CH3N / TIM8_CH3N / TIM12_CH2 / OTG_HS_DP/ EVENTOUT RTC_REFIN - H2 55 77 P15 96 PD8 I/O FT FSMC_D13 / USART3_TX/ EVENTOUT - H3 56 78 P14 97 PD9 I/O FT FSMC_D14 / USART3_RX/ EVENTOUT - G3 57 79 N15 98 PD10 I/O FT FSMC_D15 / USART3_CK/ EVENTOUT - G1 58 80 N14 99 PD11 I/O FT FSMC_CLE / FSMC_A16/USART3_CT S/ EVENTOUT - G2 59 81 N13 100 PD12 I/O FT FSMC_ALE/ FSMC_A17/TIM4_CH1 / USART3_RTS/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 Pinouts and pin description STM32F405xx, STM32F407xx 52/185 DocID022152 Rev 4 - - 60 82 M15 101 PD13 I/O FT FSMC_A18/TIM4_CH2/ EVENTOUT - - - 83 - 102 VSS S - - - 84 J13 103 VDD S - F2 61 85 M14 104 PD14 I/O FT FSMC_D0/TIM4_CH3/ EVENTOUT/ EVENTOUT - F1 62 86 L14 105 PD15 I/O FT FSMC_D1/TIM4_CH4/ EVENTOUT - - - 87 L15 106 PG2 I/O FT FSMC_A12/ EVENTOUT - - - 88 K15 107 PG3 I/O FT FSMC_A13/ EVENTOUT - - - 89 K14 108 PG4 I/O FT FSMC_A14/ EVENTOUT - - - 90 K13 109 PG5 I/O FT FSMC_A15/ EVENTOUT - - - 91 J15 110 PG6 I/O FT FSMC_INT2/ EVENTOUT - - - 92 J14 111 PG7 I/O FT FSMC_INT3 /USART6_CK/ EVENTOUT - - - 93 H14 112 PG8 I/O FT USART6_RTS / ETH_PPS_OUT/ EVENTOUT - - - 94 G12 113 VSS S - - - 95 H13 114 VDD S 37 F3 63 96 H15 115 PC6 I/O FT I2S2_MCK / TIM8_CH1/SDIO_D6 / USART6_TX / DCMI_D0/TIM3_CH1/ EVENTOUT 38 E1 64 97 G15 116 PC7 I/O FT I2S3_MCK / TIM8_CH2/SDIO_D7 / USART6_RX / DCMI_D1/TIM3_CH2/ EVENTOUT 39 E2 65 98 G14 117 PC8 I/O FT TIM8_CH3/SDIO_D0 /TIM3_CH3/ USART6_CK / DCMI_D2/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 DocID022152 Rev 4 53/185 STM32F405xx, STM32F407xx Pinouts and pin description 40 E3 66 99 F14 118 PC9 I/O FT I2S_CKIN/ MCO2 / TIM8_CH4/SDIO_D1 / /I2C3_SDA / DCMI_D3 / TIM3_CH4/ EVENTOUT 41 D1 67 100 F15 119 PA8 I/O FT MCO1 / USART1_CK/ TIM1_CH1/ I2C3_SCL/ OTG_FS_SOF/ EVENTOUT 42 D2 68 101 E15 120 PA9 I/O FT USART1_TX/ TIM1_CH2 / I2C3_SMBA / DCMI_D0/ EVENTOUT OTG_FS_VBUS 43 D3 69 102 D15 121 PA10 I/O FT USART1_RX/ TIM1_CH3/ OTG_FS_ID/DCMI_D1/ EVENTOUT 44 C1 70 103 C15 122 PA11 I/O FT USART1_CTS / CAN1_RX / TIM1_CH4 / OTG_FS_DM/ EVENTOUT 45 C2 71 104 B15 123 PA12 I/O FT USART1_RTS / CAN1_TX/ TIM1_ETR/ OTG_FS_DP/ EVENTOUT 46 D4 72 105 A15 124 PA13 (JTMS-SWDIO) I/O FT JTMS-SWDIO/ EVENTOUT 47 B1 73 106 F13 125 VCAP_2 S - E7 74 107 F12 126 VSS S 48 E6 75 108 G13 127 VDD S - - - - E12 128 PH13 I/O FT TIM8_CH1N / CAN1_TX/ EVENTOUT - - - - E13 129 PH14 I/O FT TIM8_CH2N / DCMI_D4/ EVENTOUT - - - - D13 130 PH15 I/O FT TIM8_CH3N / DCMI_D11/ EVENTOUT - C3 - - E14 131 PI0 I/O FT TIM5_CH4 / SPI2_NSS / I2S2_WS / DCMI_D13/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 Pinouts and pin description STM32F405xx, STM32F407xx 54/185 DocID022152 Rev 4 - B2 - - D14 132 PI1 I/O FT SPI2_SCK / I2S2_CK / DCMI_D8/ EVENTOUT - - - - C14 133 PI2 I/O FT TIM8_CH4 /SPI2_MISO / DCMI_D9 / I2S2ext_SD/ EVENTOUT - - - - C13 134 PI3 I/O FT TIM8_ETR / SPI2_MOSI / I2S2_SD / DCMI_D10/ EVENTOUT - - - - D9 135 VSS S - - - - C9 136 VDD S 49 A2 76 109 A14 137 PA14 (JTCK/SWCLK) I/O FT JTCK-SWCLK/ EVENTOUT 50 B3 77 110 A13 138 PA15 (JTDI) I/O FT JTDI/ SPI3_NSS/ I2S3_WS/TIM2_CH1_ET R / SPI1_NSS / EVENTOUT 51 D5 78 111 B14 139 PC10 I/O FT SPI3_SCK / I2S3_CK/ UART4_TX/SDIO_D2 / DCMI_D8 / USART3_TX/ EVENTOUT 52 C4 79 112 B13 140 PC11 I/O FT UART4_RX/ SPI3_MISO / SDIO_D3 / DCMI_D4/USART3_RX / I2S3ext_SD/ EVENTOUT 53 A3 80 113 A12 141 PC12 I/O FT UART5_TX/SDIO_CK / DCMI_D9 / SPI3_MOSI /I2S3_SD / USART3_CK/ EVENTOUT - D6 81 114 B12 142 PD0 I/O FT FSMC_D2/CAN1_RX/ EVENTOUT - C5 82 115 C12 143 PD1 I/O FT FSMC_D3 / CAN1_TX/ EVENTOUT 54 B4 83 116 D12 144 PD2 I/O FT TIM3_ETR/UART5_RX/ SDIO_CMD / DCMI_D11/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 DocID022152 Rev 4 55/185 STM32F405xx, STM32F407xx Pinouts and pin description - - 84 117 D11 145 PD3 I/O FT FSMC_CLK/ USART2_CTS/ EVENTOUT - A4 85 118 D10 146 PD4 I/O FT FSMC_NOE/ USART2_RTS/ EVENTOUT - C6 86 119 C11 147 PD5 I/O FT FSMC_NWE/USART2_TX / EVENTOUT - - - 120 D8 148 VSS S - - - 121 C8 149 VDD S - B5 87 122 B11 150 PD6 I/O FT FSMC_NWAIT/ USART2_RX/ EVENTOUT - A5 88 123 A11 151 PD7 I/O FT USART2_CK/FSMC_NE1/ FSMC_NCE2/ EVENTOUT - - - 124 C10 152 PG9 I/O FT USART6_RX / FSMC_NE2/FSMC_NCE3 / EVENTOUT - - - 125 B10 153 PG10 I/O FT FSMC_NCE4_1/ FSMC_NE3/ EVENTOUT - - - 126 B9 154 PG11 I/O FT FSMC_NCE4_2 / ETH_MII_TX_EN/ ETH _RMII_TX_EN/ EVENTOUT - - - 127 B8 155 PG12 I/O FT FSMC_NE4 / USART6_RTS/ EVENTOUT - - - 128 A8 156 PG13 I/O FT FSMC_A24 / USART6_CTS /ETH_MII_TXD0/ ETH_RMII_TXD0/ EVENTOUT - - - 129 A7 157 PG14 I/O FT FSMC_A25 / USART6_TX /ETH_MII_TXD1/ ETH_RMII_TXD1/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 Pinouts and pin description STM32F405xx, STM32F407xx 56/185 DocID022152 Rev 4 - E8 - 130 D7 158 VSS S - F7 - 131 C7 159 VDD S - - - 132 B7 160 PG15 I/O FT USART6_CTS / DCMI_D13/ EVENTOUT 55 B6 89 133 A10 161 PB3 (JTDO/ TRACESWO) I/O FT JTDO/ TRACESWO/ SPI3_SCK / I2S3_CK / TIM2_CH2 / SPI1_SCK/ EVENTOUT 56 A6 90 134 A9 162 PB4 (NJTRST) I/O FT NJTRST/ SPI3_MISO / TIM3_CH1 / SPI1_MISO / I2S3ext_SD/ EVENTOUT 57 D7 91 135 A6 163 PB5 I/O FT I2C1_SMBA/ CAN2_RX / OTG_HS_ULPI_D7 / ETH_PPS_OUT/TIM3_CH 2 / SPI1_MOSI/ SPI3_MOSI / DCMI_D10 / I2S3_SD/ EVENTOUT 58 C7 92 136 B6 164 PB6 I/O FT I2C1_SCL/ TIM4_CH1 / CAN2_TX / DCMI_D5/USART1_TX/ EVENTOUT 59 B7 93 137 B5 165 PB7 I/O FT I2C1_SDA / FSMC_NL / DCMI_VSYNC / USART1_RX/ TIM4_CH2/ EVENTOUT 60 A7 94 138 D6 166 BOOT0 I B VPP 61 D8 95 139 A5 167 PB8 I/O FT TIM4_CH3/SDIO_D4/ TIM10_CH1 / DCMI_D6 / ETH_MII_TXD3 / I2C1_SCL/ CAN1_RX/ EVENTOUT 62 C8 96 140 B4 168 PB9 I/O FT SPI2_NSS/ I2S2_WS / TIM4_CH4/ TIM11_CH1/ SDIO_D5 / DCMI_D7 / I2C1_SDA / CAN1_TX/ EVENTOUT Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 DocID022152 Rev 4 57/185 STM32F405xx, STM32F407xx Pinouts and pin description - - 97 141 A4 169 PE0 I/O FT TIM4_ETR / FSMC_NBL0 / DCMI_D2/ EVENTOUT - - 98 142 A3 170 PE1 I/O FT FSMC_NBL1 / DCMI_D3/ EVENTOUT 63 - 99 - D5 - VSS S - A8 - 143 C6 171 PDR_ON I FT 64 A1 10 0 144 C5 172 VDD S - - - - D4 173 PI4 I/O FT TIM8_BKIN / DCMI_D5/ EVENTOUT - - - - C4 174 PI5 I/O FT TIM8_CH1 / DCMI_VSYNC/ EVENTOUT - - - - C3 175 PI6 I/O FT TIM8_CH2 / DCMI_D6/ EVENTOUT - - - - C2 176 PI7 I/O FT TIM8_CH3 / DCMI_D7/ EVENTOUT 1. Function availability depends on the chosen device. 2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF. - These I/Os must not be used as a current source (e.g. to drive an LED). 3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F4xx reference manual, available from the STMicroelectronics website: www.st.com. 4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1). 5. If the device is delivered in an UFBGA176 or WLCSP90 and the BYPASS_REG pin is set to VDD (Regulator off/internal reset ON mode), then PA0 is used as an internal Reset (active low). Table 7. STM32F40x pin and ball definitions (continued) Pin number Pin name (function after reset)(1) Pin type I / O structure Notes Alternate functions Additional functions LQFP64 WLCSP90 LQFP100 LQFP144 UFBGA176 LQFP176 Table 8. FSMC pin definition Pins(1) FSMC LQFP100(2) WLCSP90 (2) CF NOR/PSRAM/ SRAM NOR/PSRAM Mux NAND 16 bit PE2 A23 A23 Yes PE3 A19 A19 Yes Pinouts and pin description STM32F405xx, STM32F407xx 58/185 DocID022152 Rev 4 PE4 A20 A20 Yes PE5 A21 A21 Yes PE6 A22 A22 Yes PF0 A0 A0 - - PF1 A1 A1 - - PF2 A2 A2 - - PF3 A3 A3 - - PF4 A4 A4 - - PF5 A5 A5 - - PF6 NIORD - - PF7 NREG - - PF8 NIOWR - - PF9 CD - - PF10 INTR - - PF12 A6 A6 - - PF13 A7 A7 - - PF14 A8 A8 - - PF15 A9 A9 - - PG0 A10 A10 - - PG1 A11 - - PE7 D4 D4 DA4 D4 Yes Yes PE8 D5 D5 DA5 D5 Yes Yes PE9 D6 D6 DA6 D6 Yes Yes PE10 D7 D7 DA7 D7 Yes Yes PE11 D8 D8 DA8 D8 Yes Yes PE12 D9 D9 DA9 D9 Yes Yes PE13 D10 D10 DA10 D10 Yes Yes PE14 D11 D11 DA11 D11 Yes Yes PE15 D12 D12 DA12 D12 Yes Yes PD8 D13 D13 DA13 D13 Yes Yes PD9 D14 D14 DA14 D14 Yes Yes PD10 D15 D15 DA15 D15 Yes Yes PD11 A16 A16 CLE Yes Yes Table 8. FSMC pin definition (continued) Pins(1) FSMC LQFP100(2) WLCSP90 (2) CF NOR/PSRAM/ SRAM NOR/PSRAM Mux NAND 16 bit DocID022152 Rev 4 59/185 STM32F405xx, STM32F407xx Pinouts and pin description PD12 A17 A17 ALE Yes Yes PD13 A18 A18 Yes PD14 D0 D0 DA0 D0 Yes Yes PD15 D1 D1 DA1 D1 Yes Yes PG2 A12 - - PG3 A13 - - PG4 A14 - - PG5 A15 - - PG6 INT2 - - PG7 INT3 - - PD0 D2 D2 DA2 D2 Yes Yes PD1 D3 D3 DA3 D3 Yes Yes PD3 CLK CLK Yes PD4 NOE NOE NOE NOE Yes Yes PD5 NWE NWE NWE NWE Yes Yes PD6 NWAIT NWAIT NWAIT NWAIT Yes Yes PD7 NE1 NE1 NCE2 Yes Yes PG9 NE2 NE2 NCE3 - - PG10 NCE4_1 NE3 NE3 - - PG11 NCE4_2 - - PG12 NE4 NE4 - - PG13 A24 A24 - - PG14 A25 A25 - - PB7 NADV NADV Yes Yes PE0 NBL0 NBL0 Yes PE1 NBL1 NBL1 Yes 1. Full FSMC features are available on LQFP144, LQFP176, and UFBGA176. The features available on smaller packages are given in the dedicated package column. 2. Ports F and G are not available in devices delivered in 100-pin packages. Table 8. FSMC pin definition (continued) Pins(1) FSMC LQFP100(2) WLCSP90 (2) CF NOR/PSRAM/ SRAM NOR/PSRAM Mux NAND 16 bit Pinouts and pin description STM32F405xx, STM32F407xx 60/185 DocID022152 Rev 4 Table 9. Alternate function mapping Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Port A PA0 TIM2_CH1_E TR TIM 5_CH1 TIM8_ETR USART2_CTS UART4_TX ETH_MII_CRS EVENTOUT PA1 TIM2_CH2 TIM5_CH2 USART2_RTS UART4_RX ETH_MII _RX_CLK ETH_RMII__REF _CLK EVENTOUT PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 USART2_TX ETH_MDIO EVENTOUT PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 USART2_RX OTG_HS_ULPI_ D0 ETH _MII_COL EVENTOUT PA4 SPI1_NSS SPI3_NSS I2S3_WS USART2_CK OTG_HS_SO F DCMI_HSYN C EVENTOUT PA5 TIM2_CH1_E TR TIM8_CH1N SPI1_SCK OTG_HS_ULPI_ CK EVENTOUT PA6 TIM1_BKIN TIM3_CH1 TIM8_BKIN SPI1_MISO TIM13_CH1 DCMI_PIXCK EVENTOUT PA7 TIM1_CH1N TIM3_CH2 TIM8_CH1N SPI1_MOSI TIM14_CH1 ETH_MII _RX_DV ETH_RMII _CRS_DV EVENTOUT PA8 MCO1 TIM1_CH1 I2C3_SCL USART1_CK OTG_FS_SOF EVENTOUT PA9 TIM1_CH2 I2C3_SMB A USART1_TX DCMI_D0 EVENTOUT PA10 TIM1_CH3 USART1_RX OTG_FS_ID DCMI_D1 EVENTOUT PA11 TIM1_CH4 USART1_CTS CAN1_RX OTG_FS_DM EVENTOUT PA12 TIM1_ETR USART1_RTS CAN1_TX OTG_FS_DP EVENTOUT PA13 JTMSSWDIO EVENTOUT PA14 JTCKSWCLK EVENTOUT PA15 JTDI TIM 2_CH1 TIM 2_ETR SPI1_NSS SPI3_NSS/ I2S3_WS EVENTOUT STM32F405xx, STM32F407xx Pinouts and pin description DocID022152 Rev 4 61/185 Port B PB0 TIM1_CH2N TIM3_CH3 TIM8_CH2N OTG_HS_ULPI_ D1 ETH _MII_RXD2 EVENTOUT PB1 TIM1_CH3N TIM3_CH4 TIM8_CH3N OTG_HS_ULPI_ D2 ETH _MII_RXD3 EVENTOUT PB2 EVENTOUT PB3 JTDO/ TRACES WO TIM2_CH2 SPI1_SCK SPI3_SCK I2S3_CK EVENTOUT PB4 NJTRST TIM3_CH1 SPI1_MISO SPI3_MISO I2S3ext_SD EVENTOUT PB5 TIM3_CH2 I2C1_SMB A SPI1_MOSI SPI3_MOSI I2S3_SD CAN2_RX OTG_HS_ULPI_ D7 ETH _PPS_OUT DCMI_D10 EVENTOUT PB6 TIM4_CH1 I2C1_SCL USART1_TX CAN2_TX DCMI_D5 EVENTOUT PB7 TIM4_CH2 I2C1_SDA USART1_RX FSMC_NL DCMI_VSYN C EVENTOUT PB8 TIM4_CH3 TIM10_CH1 I2C1_SCL CAN1_RX ETH _MII_TXD3 SDIO_D4 DCMI_D6 EVENTOUT PB9 TIM4_CH4 TIM11_CH1 I2C1_SDA SPI2_NSS I2S2_WS CAN1_TX SDIO_D5 DCMI_D7 EVENTOUT PB10 TIM2_CH3 I2C2_SCL SPI2_SCK I2S2_CK USART3_TX OTG_HS_ULPI_ D3 ETH_ MII_RX_ER EVENTOUT PB11 TIM2_CH4 I2C2_SDA USART3_RX OTG_HS_ULPI_ D4 ETH _MII_TX_EN ETH _RMII_TX_EN EVENTOUT PB12 TIM1_BKIN I2C2_SMB A SPI2_NSS I2S2_WS USART3_CK CAN2_RX OTG_HS_ULPI_ D5 ETH _MII_TXD0 ETH _RMII_TXD0 OTG_HS_ID EVENTOUT PB13 TIM1_CH1N SPI2_SCK I2S2_CK USART3_CTS CAN2_TX OTG_HS_ULPI_ D6 ETH _MII_TXD1 ETH _RMII_TXD1 EVENTOUT PB14 TIM1_CH2N TIM8_CH2N SPI2_MISO I2S2ext_SD USART3_RTS TIM12_CH1 OTG_HS_DM EVENTOUT PB15 RTC_ REFIN TIM1_CH3N TIM8_CH3N SPI2_MOSI I2S2_SD TIM12_CH2 OTG_HS_DP EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Pinouts and pin description STM32F405xx, STM32F407xx 62/185 DocID022152 Rev 4 Port C PC0 OTG_HS_ULPI_ STP EVENTOUT PC1 ETH_MDC EVENTOUT PC2 SPI2_MISO I2S2ext_SD OTG_HS_ULPI_ DIR ETH _MII_TXD2 EVENTOUT PC3 SPI2_MOSI I2S2_SD OTG_HS_ULPI_ NXT ETH _MII_TX_CLK EVENTOUT PC4 ETH_MII_RXD0 ETH_RMII_RXD0 EVENTOUT PC5 ETH _MII_RXD1 ETH _RMII_RXD1 EVENTOUT PC6 TIM3_CH1 TIM8_CH1 I2S2_MCK USART6_TX SDIO_D6 DCMI_D0 EVENTOUT PC7 TIM3_CH2 TIM8_CH2 I2S3_MCK USART6_RX SDIO_D7 DCMI_D1 EVENTOUT PC8 TIM3_CH3 TIM8_CH3 USART6_CK SDIO_D0 DCMI_D2 EVENTOUT PC9 MCO2 TIM3_CH4 TIM8_CH4 I2C3_SDA I2S_CKIN SDIO_D1 DCMI_D3 EVENTOUT PC10 SPI3_SCK/ I2S3_CK USART3_TX/ UART4_TX SDIO_D2 DCMI_D8 EVENTOUT PC11 I2S3ext_SD SPI3_MISO/ USART3_RX UART4_RX SDIO_D3 DCMI_D4 EVENTOUT PC12 SPI3_MOSI I2S3_SD USART3_CK UART5_TX SDIO_CK DCMI_D9 EVENTOUT PC13 EVENTOUT PC14 EVENTOUT PC15 EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI STM32F405xx, STM32F407xx Pinouts and pin description DocID022152 Rev 4 63/185 Port D PD0 CAN1_RX FSMC_D2 EVENTOUT PD1 CAN1_TX FSMC_D3 EVENTOUT PD2 TIM3_ETR UART5_RX SDIO_CMD DCMI_D11 EVENTOUT PD3 USART2_CTS FSMC_CLK EVENTOUT PD4 USART2_RTS FSMC_NOE EVENTOUT PD5 USART2_TX FSMC_NWE EVENTOUT PD6 USART2_RX FSMC_NWAIT EVENTOUT PD7 USART2_CK FSMC_NE1/ FSMC_NCE2 EVENTOUT PD8 USART3_TX FSMC_D13 EVENTOUT PD9 USART3_RX FSMC_D14 EVENTOUT PD10 USART3_CK FSMC_D15 EVENTOUT PD11 USART3_CTS FSMC_A16 EVENTOUT PD12 TIM4_CH1 USART3_RTS FSMC_A17 EVENTOUT PD13 TIM4_CH2 FSMC_A18 EVENTOUT PD14 TIM4_CH3 FSMC_D0 EVENTOUT PD15 TIM4_CH4 FSMC_D1 EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Pinouts and pin description STM32F405xx, STM32F407xx 64/185 DocID022152 Rev 4 Port E PE0 TIM4_ETR FSMC_NBL0 DCMI_D2 EVENTOUT PE1 FSMC_NBL1 DCMI_D3 EVENTOUT PE2 TRACECL K ETH _MII_TXD3 FSMC_A23 EVENTOUT PE3 TRACED0 FSMC_A19 EVENTOUT PE4 TRACED1 FSMC_A20 DCMI_D4 EVENTOUT PE5 TRACED2 TIM9_CH1 FSMC_A21 DCMI_D6 EVENTOUT PE6 TRACED3 TIM9_CH2 FSMC_A22 DCMI_D7 EVENTOUT PE7 TIM1_ETR FSMC_D4 EVENTOUT PE8 TIM1_CH1N FSMC_D5 EVENTOUT PE9 TIM1_CH1 FSMC_D6 EVENTOUT PE10 TIM1_CH2N FSMC_D7 EVENTOUT PE11 TIM1_CH2 FSMC_D8 EVENTOUT PE12 TIM1_CH3N FSMC_D9 EVENTOUT PE13 TIM1_CH3 FSMC_D10 EVENTOUT PE14 TIM1_CH4 FSMC_D11 EVENTOUT PE15 TIM1_BKIN FSMC_D12 EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI STM32F405xx, STM32F407xx Pinouts and pin description DocID022152 Rev 4 65/185 Port F PF0 I2C2_SDA FSMC_A0 EVENTOUT PF1 I2C2_SCL FSMC_A1 EVENTOUT PF2 I2C2_ SMBA FSMC_A2 EVENTOUT PF3 FSMC_A3 EVENTOUT PF4 FSMC_A4 EVENTOUT PF5 FSMC_A5 EVENTOUT PF6 TIM10_CH1 FSMC_NIORD EVENTOUT PF7 TIM11_CH1 FSMC_NREG EVENTOUT PF8 TIM13_CH1 FSMC_ NIOWR EVENTOUT PF9 TIM14_CH1 FSMC_CD EVENTOUT PF10 FSMC_INTR EVENTOUT PF11 DCMI_D12 EVENTOUT PF12 FSMC_A6 EVENTOUT PF13 FSMC_A7 EVENTOUT PF14 FSMC_A8 EVENTOUT PF15 FSMC_A9 EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Pinouts and pin description STM32F405xx, STM32F407xx 66/185 DocID022152 Rev 4 Port G PG0 FSMC_A10 EVENTOUT PG1 FSMC_A11 EVENTOUT PG2 FSMC_A12 EVENTOUT PG3 FSMC_A13 EVENTOUT PG4 FSMC_A14 EVENTOUT PG5 FSMC_A15 EVENTOUT PG6 FSMC_INT2 EVENTOUT PG7 USART6_CK FSMC_INT3 EVENTOUT PG8 USART6_ RTS ETH _PPS_OUT EVENTOUT PG9 USART6_RX FSMC_NE2/ FSMC_NCE3 EVENTOUT PG10 FSMC_ NCE4_1/ FSMC_NE3 EVENTOUT PG11 ETH _MII_TX_EN ETH _RMII_ TX_EN FSMC_NCE4_ 2 EVENTOUT PG12 USART6_ RTS FSMC_NE4 EVENTOUT PG13 UART6_CTS ETH _MII_TXD0 ETH _RMII_TXD0 FSMC_A24 EVENTOUT PG14 USART6_TX ETH _MII_TXD1 ETH _RMII_TXD1 FSMC_A25 EVENTOUT PG15 USART6_ CTS DCMI_D13 EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI STM32F405xx, STM32F407xx Pinouts and pin description DocID022152 Rev 4 67/185 Port H PH0 EVENTOUT PH1 EVENTOUT PH2 ETH _MII_CRS EVENTOUT PH3 ETH _MII_COL EVENTOUT PH4 I2C2_SCL OTG_HS_ULPI_ NXT EVENTOUT PH5 I2C2_SDA EVENTOUT PH6 I2C2_SMB A TIM12_CH1 ETH _MII_RXD2 EVENTOUT PH7 I2C3_SCL ETH _MII_RXD3 EVENTOUT PH8 I2C3_SDA DCMI_HSYN C EVENTOUT PH9 I2C3_SMB A TIM12_CH2 DCMI_D0 EVENTOUT PH10 TIM5_CH1 DCMI_D1 EVENTOUT PH11 TIM5_CH2 DCMI_D2 EVENTOUT PH12 TIM5_CH3 DCMI_D3 EVENTOUT PH13 TIM8_CH1N CAN1_TX EVENTOUT PH14 TIM8_CH2N DCMI_D4 EVENTOUT PH15 TIM8_CH3N DCMI_D11 EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI Pinouts and pin description STM32F405xx, STM32F407xx 68/185 DocID022152 Rev 4 Port I PI0 TIM5_CH4 SPI2_NSS I2S2_WS DCMI_D13 EVENTOUT PI1 SPI2_SCK I2S2_CK DCMI_D8 EVENTOUT PI2 TIM8_CH4 SPI2_MISO I2S2ext_SD DCMI_D9 EVENTOUT PI3 TIM8_ETR SPI2_MOSI I2S2_SD DCMI_D10 EVENTOUT PI4 TIM8_BKIN DCMI_D5 EVENTOUT PI5 TIM8_CH1 DCMI_ VSYNC EVENTOUT PI6 TIM8_CH2 DCMI_D6 EVENTOUT PI7 TIM8_CH3 DCMI_D7 EVENTOUT PI8 EVENTOUT PI9 CAN1_RX EVENTOUT PI10 ETH _MII_RX_ER EVENTOUT PI11 OTG_HS_ULPI_ DIR EVENTOUT Table 9. Alternate function mapping (continued) Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SYS TIM1/2 TIM3/4/5 TIM8/9/10/1 1 I2C1/2/3 SPI1/SPI2/ I2S2/I2S2ext SPI3/I2Sext/ I2S3 USART1/2/3/ I2S3ext UART4/5/ USART6 CAN1/ CAN2/ TIM12/13/14 OTG_FS/ OTG_HS ETH FSMC/SDIO/ OTG_FS DCMI DocID022152 Rev 4 69/185 STM32F405xx, STM32F407xx Memory mapping 4 Memory mapping The memory map is shown in Figure 18. Figure 18. STM32F40x memory map 512-Mbyte block 7 Cortex-M4's internal peripherals 512-Mbyte block 6 Not used 512-Mbyte block 5 FSMC registers 512-Mbyte block 4 FSMC bank 3 & bank4 512-Mbyte block 3 FSMC bank1 & bank2 512-Mbyte block 2 Peripherals 512-Mbyte block 1 SRAM 0x0000 0000 0x1FFF FFFF 0x2000 0000 0x3FFF FFFF 0x4000 0000 0x5FFF FFFF 0x6000 0000 0x7FFF FFFF 0x8000 0000 0x9FFF FFFF 0xA000 0000 0xBFFF FFFF 0xC000 0000 0xDFFF FFFF 0xE000 0000 0xFFFF FFFF 512-Mbyte block 0 Code Flash 0x0810 0000 - 0x0FFF FFFF 0x1FFF 0000 - 0x1FFF 7A0F 0x1FFF C000 - 0x1FFF C007 0x0800 0000 - 0x080F FFFF 0x0010 0000 - 0x07FF FFFF 0x0000 0000 - 0x000F FFFF System memory + OTP Reserved Reserved Aliased to Flash, system memory or SRAM depending on the BOOT pins SRAM (16 KB aliased by bit-banding) Reserved 0x2000 0000 - 0x2001 BFFF 0x2001 C000 - 0x2001 FFFF 0x2002 0000 - 0x3FFF FFFF 0x4000 0000 Reserved 0x4000 7FFF 0x4000 7800 - 0x4000 FFFF 0x4001 0000 0x4001 57FF 0x4002 000 Reserved 0x5006 0C00 - 0x5FFF FFFF 0x6000 0000 AHB3 0xA000 0FFF 0xA000 1000 - 0xDFFF FFFF ai18513f Option Bytes Reserved 0x4001 5800 - 0x4001 FFFF 0x5006 0BFF AHB2 0x5000 0000 Reserved 0x4008 0000 - 0x4FFF FFFF AHB1 SRAM (112 KB aliased by bit-banding) Reserved 0x1FFF C008 - 0x1FFF FFFF Reserved 0x1FFF 7A10 - 0x1FFF 7FFF CCM data RAM (64 KB data SRAM) 0x1000 0000 - 0x1000 FFFF Reserved 0x1001 0000 - 0x1FFE FFFF Reserved APB2 0x4007 FFFF APB1 CORTEX-M4 internal peripherals 0xE000 0000 - 0xE00F FFFF Reserved 0xE010 0000 - 0xFFFF FFFF Memory mapping STM32F405xx, STM32F407xx 70/185 DocID022152 Rev 4 Table 10. STM32F40x register boundary addresses Bus Boundary address Peripheral 0xE00F FFFF - 0xFFFF FFFF Reserved Cortex-M4 0xE000 0000 - 0xE00F FFFF Cortex-M4 internal peripherals 0xA000 1000 - 0xDFFF FFFF Reserved AHB3 0xA000 0000 - 0xA000 0FFF FSMC control register 0x9000 0000 - 0x9FFF FFFF FSMC bank 4 0x8000 0000 - 0x8FFF FFFF FSMC bank 3 0x7000 0000 - 0x7FFF FFFF FSMC bank 2 0x6000 0000 - 0x6FFF FFFF FSMC bank 1 0x5006 0C00- 0x5FFF FFFF Reserved AHB2 0x5006 0800 - 0x5006 0BFF RNG 0x5005 0400 - 0x5006 07FF Reserved 0x5005 0000 - 0x5005 03FF DCMI 0x5004 0000- 0x5004 FFFF Reserved 0x5000 0000 - 0x5003 FFFF USB OTG FS 0x4008 0000- 0x4FFF FFFF Reserved DocID022152 Rev 4 71/185 STM32F405xx, STM32F407xx Memory mapping AHB1 0x4004 0000 - 0x4007 FFFF USB OTG HS 0x4002 9400 - 0x4003 FFFF Reserved 0x4002 9000 - 0x4002 93FF ETHERNET MAC 0x4002 8C00 - 0x4002 8FFF 0x4002 8800 - 0x4002 8BFF 0x4002 8400 - 0x4002 87FF 0x4002 8000 - 0x4002 83FF 0x4002 6800 - 0x4002 7FFF Reserved 0x4002 6400 - 0x4002 67FF DMA2 0x4002 6000 - 0x4002 63FF DMA1 0x4002 5000 - 0x4002 5FFF Reserved 0x4002 4000 - 0x4002 4FFF BKPSRAM 0x4002 3C00 - 0x4002 3FFF Flash interface register 0x4002 3800 - 0x4002 3BFF RCC 0x4002 3400 - 0x4002 37FF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2400 - 0x4002 2FFF Reserved 0x4002 2000 - 0x4002 23FF GPIOI 0x4002 1C00 - 0x4002 1FFF GPIOH 0x4002 1800 - 0x4002 1BFF GPIOG 0x4002 1400 - 0x4002 17FF GPIOF 0x4002 1000 - 0x4002 13FF GPIOE 0x4002 0C00 - 0x4002 0FFF GPIOD 0x4002 0800 - 0x4002 0BFF GPIOC 0x4002 0400 - 0x4002 07FF GPIOB 0x4002 0000 - 0x4002 03FF GPIOA 0x4001 5800- 0x4001 FFFF Reserved Table 10. STM32F40x register boundary addresses (continued) Bus Boundary address Peripheral Memory mapping STM32F405xx, STM32F407xx 72/185 DocID022152 Rev 4 APB2 0x4001 4C00 - 0x4001 57FF Reserved 0x4001 4800 - 0x4001 4BFF TIM11 0x4001 4400 - 0x4001 47FF TIM10 0x4001 4000 - 0x4001 43FF TIM9 0x4001 3C00 - 0x4001 3FFF EXTI 0x4001 3800 - 0x4001 3BFF SYSCFG 0x4001 3400 - 0x4001 37FF Reserved 0x4001 3000 - 0x4001 33FF SPI1 0x4001 2C00 - 0x4001 2FFF SDIO 0x4001 2400 - 0x4001 2BFF Reserved 0x4001 2000 - 0x4001 23FF ADC1 - ADC2 - ADC3 0x4001 1800 - 0x4001 1FFF Reserved 0x4001 1400 - 0x4001 17FF USART6 0x4001 1000 - 0x4001 13FF USART1 0x4001 0800 - 0x4001 0FFF Reserved 0x4001 0400 - 0x4001 07FF TIM8 0x4001 0000 - 0x4001 03FF TIM1 0x4000 7800- 0x4000 FFFF Reserved Table 10. STM32F40x register boundary addresses (continued) Bus Boundary address Peripheral DocID022152 Rev 4 73/185 STM32F405xx, STM32F407xx Memory mapping APB1 0x4000 7800 - 0x4000 7FFF Reserved 0x4000 7400 - 0x4000 77FF DAC 0x4000 7000 - 0x4000 73FF PWR 0x4000 6C00 - 0x4000 6FFF Reserved 0x4000 6800 - 0x4000 6BFF CAN2 0x4000 6400 - 0x4000 67FF CAN1 0x4000 6000 - 0x4000 63FF Reserved 0x4000 5C00 - 0x4000 5FFF I2C3 0x4000 5800 - 0x4000 5BFF I2C2 0x4000 5400 - 0x4000 57FF I2C1 0x4000 5000 - 0x4000 53FF UART5 0x4000 4C00 - 0x4000 4FFF UART4 0x4000 4800 - 0x4000 4BFF USART3 0x4000 4400 - 0x4000 47FF USART2 0x4000 4000 - 0x4000 43FF I2S3ext 0x4000 3C00 - 0x4000 3FFF SPI3 / I2S3 0x4000 3800 - 0x4000 3BFF SPI2 / I2S2 0x4000 3400 - 0x4000 37FF I2S2ext 0x4000 3000 - 0x4000 33FF IWDG 0x4000 2C00 - 0x4000 2FFF WWDG 0x4000 2800 - 0x4000 2BFF RTC & BKP Registers 0x4000 2400 - 0x4000 27FF Reserved 0x4000 2000 - 0x4000 23FF TIM14 0x4000 1C00 - 0x4000 1FFF TIM13 0x4000 1800 - 0x4000 1BFF TIM12 0x4000 1400 - 0x4000 17FF TIM7 0x4000 1000 - 0x4000 13FF TIM6 0x4000 0C00 - 0x4000 0FFF TIM5 0x4000 0800 - 0x4000 0BFF TIM4 0x4000 0400 - 0x4000 07FF TIM3 0x4000 0000 - 0x4000 03FF TIM2 Table 10. STM32F40x register boundary addresses (continued) Bus Boundary address Peripheral Electrical characteristics STM32F405xx, STM32F407xx 74/185 DocID022152 Rev 4 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 1.8 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2Σ). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 19. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 20. Figure 19. Pin loading conditions Figure 20. Pin input voltage MS19011V1 C = 50 pF STM32F pin OSC_OUT (Hi-Z when using HSE or LSE) MS19010V1 STM32F pin VIN OSC_OUT (Hi-Z when using HSE or LSE) DocID022152 Rev 4 75/185 STM32F405xx, STM32F407xx Electrical characteristics 5.1.6 Power supply scheme Figure 21. Power supply scheme 1. Each power supply pair must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB to ensure the good functionality of the device. 2. To connect BYPASS_REG and PDR_ON pins, refer to Section 2.2.16: Voltage regulator and Table 2.2.15: Power supply supervisor. 3. The two 2.2 μF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF. 4. The 4.7 μF ceramic capacitor must be connected to one of the VDD pin. 5. VDDA=VDD and VSSA=VSS. MS19911V2 Backup circuitry (OSC32K,RTC, Wakeup logic Backup registers, backup RAM) Kernel logic (CPU, digital & RAM) Analog: RCs, PLL,.. Power switch VBAT GPIOs OUT IN 15 × 100 nF + 1 × 4.7 μF VBAT = 1.65 to 3.6V Voltage regulator VDDA ADC Level shifter IO Logic VDD 100 nF + 1 μF Flash memory VCAP_1 2 × 2.2 μF VCAP_2 BYPASS_REG PDR_ON Reset controller VDD 1/2/...14/15 VSS 1/2/...14/15 VDD VREF+ VREFVSSA VREF 100 nF + 1 μF Electrical characteristics STM32F405xx, STM32F407xx 76/185 DocID022152 Rev 4 5.1.7 Current consumption measurement Figure 22. Current consumption measurement scheme 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics, Table 12: Current characteristics, and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ai14126 VBAT VDD VDDA IDD_VBAT IDD Table 11. Voltage characteristics Symbol Ratings Min Max Unit VDD–VSS External main supply voltage (including VDDA, VDD)(1) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. –0.3 4.0 V VIN Input voltage on five-volt tolerant pin(2) 2. VIN maximum value must always be respected. Refer to Table 12 for the values of the maximum allowed injected current. VSS–0.3 VDD+4 Input voltage on any other pin VSS–0.3 4.0 |ΔVDDx| Variations between different VDD power pins - 50 mV |VSSX − VSS| Variations between all the different ground pins - 50 VESD(HBM) Electrostatic discharge voltage (human body model) see Section 5.3.14: Absolute maximum ratings (electrical sensitivity) DocID022152 Rev 4 77/185 STM32F405xx, STM32F407xx Electrical characteristics 5.3 Operating conditions 5.3.1 General operating conditions Table 12. Current characteristics Symbol Ratings Max. Unit IVDD Total current into VDD power lines (source)(1) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 150 mA IVSS Total current out of VSS ground lines (sink)(1) 150 IIO Output current sunk by any I/O and control pin 25 Output current source by any I/Os and control pin 25 IINJ(PIN) (2) 2. Negative injection disturbs the analog performance of the device. See note in Section 5.3.20: 12-bit ADC characteristics. Injected current on five-volt tolerant I/O(3) 3. Positive injection is not possible on these I/Os. A negative injection is induced by VINVDD while a negative injection is induced by VIN 25 MHz. 4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part. 5. When analog peripheral blocks such as ADCs, DACs, HSE, LSE, HSI, or LSI are ON, an additional power consumption should be considered. 6. In this case HCLK = system clock/2. Electrical characteristics STM32F405xx, STM32F407xx 84/185 DocID022152 Rev 4 Table 21. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) Symbol Parameter Conditions fHCLK Typ Max(1) Unit TA = 25 °C TA = 85 °C TA = 105 °C IDD Supply current in Run mode External clock(2), all peripherals enabled(3)(4) 168 MHz 93 109 117 mA 144 MHz 76 89 96 120 MHz 67 79 86 90 MHz 53 65 73 60 MHz 37 49 56 30 MHz 20 32 39 25 MHz 16 27 35 16 MHz 11 23 30 8 MHz 6 18 25 4 MHz 4 16 23 2 MHz 3 15 22 External clock(2), all peripherals disabled(3)(4) 168 MHz 46 61 69 144 MHz 40 52 60 120 MHz 37 48 56 90 MHz 30 42 50 60 MHz 22 33 41 30 MHz 12 24 31 25 MHz 10 21 29 16 MHz 7 19 26 8 MHz 4 16 23 4 MHz 3 15 22 2 MHz 2 14 21 1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled. 2. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz. 3. When analog peripheral blocks such as (ADCs, DACs, HSE, LSE, HSI,LSI) are on, an additional power consumption should be considered. 4. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for the analog part. DocID022152 Rev 4 85/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 24. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals OFF Figure 25. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator ON) or RAM, and peripherals ON MS19974V1 0 5 10 15 20 25 30 35 40 45 50 0 20 40 60 80 100 120 140 160 180 IDD RUN( mA) CPU Frequency (MHz -45 °C 0 °C 25 °C 55 °C 85 °C 105 °C MS19975V1 0 10 20 30 40 50 60 70 80 90 100 0 20 40 60 80 100 120 140 160 180 IDD RUN( mA) CPU Frequency (MHz -45°C 0°C 25°C 55°C 85°C 105°C Electrical characteristics STM32F405xx, STM32F407xx 86/185 DocID022152 Rev 4 Figure 26. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals OFF Figure 27. Typical current consumption versus temperature, Run mode, code with data processing running from Flash (ART accelerator OFF) or RAM, and peripherals ON MS19976V1 0 10 20 30 40 50 60 0 20 40 60 80 100 120 140 160 180 IDD RUN( mA) CPU Frequency (MHz -45°C 0°C 25°C 55°C 85°C 105°C MS19977V1 0 20 40 60 80 100 120 0 20 40 60 80 100 120 140 160 180 IDD RUN( mA) CPU Frequency (MHz -45°C 0°C 25°C 55°C 85°C 105°C DocID022152 Rev 4 87/185 STM32F405xx, STM32F407xx Electrical characteristics Table 22. Typical and maximum current consumption in Sleep mode Symbol Parameter Conditions fHCLK Typ Max(1) T Unit A = 25 °C TA = 85 °C TA = 105 °C IDD Supply current in Sleep mode External clock(2), all peripherals enabled(3) 168 MHz 59 77 84 mA 144 MHz 46 61 67 120 MHz 38 53 60 90 MHz 30 44 51 60 MHz 20 34 41 30 MHz 11 24 31 25 MHz 8 21 28 16 MHz 6 18 25 8 MHz 3 16 23 4 MHz 2 15 22 2 MHz 2 14 21 External clock(2), all peripherals disabled 168 MHz 12 27 35 144 MHz 9 22 29 120 MHz 8 20 28 90 MHz 7 19 26 60 MHz 5 17 24 30 MHz 3 16 23 25 MHz 2 15 22 16 MHz 2 14 21 8 MHz 1 14 21 4 MHz 1 13 21 2 MHz 1 13 21 1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled. 2. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz. 3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is ON (ADON bit is set in the ADC_CR2 register). Electrical characteristics STM32F405xx, STM32F407xx 88/185 DocID022152 Rev 4 Table 23. Typical and maximum current consumptions in Stop mode Symbol Parameter Conditions Typ Max T Unit A = 25 °C TA = 25 °C TA = 85 °C TA = 105 °C IDD_STOP Supply current in Stop mode with main regulator in Run mode Flash in Stop mode, low-speed and highspeed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.45 1.5 11.00 20.00 mA Flash in Deep power down mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.40 1.5 11.00 20.00 Supply current in Stop mode with main regulator in Low Power mode Flash in Stop mode, low-speed and highspeed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.31 1.1 8.00 15.00 Flash in Deep power down mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.28 1.1 8.00 15.00 Table 24. Typical and maximum current consumptions in Standby mode Symbol Parameter Conditions Typ Max(1) TA = 25 °C Unit TA = 85 °C TA = 105 °C VDD = 1.8 V VDD= 2.4 V VDD = 3.3 V VDD = 3.6 V IDD_STBY Supply current in Standby mode Backup SRAM ON, lowspeed oscillator and RTC ON 3.0 3.4 4.0 20 36 μA Backup SRAM OFF, lowspeed oscillator and RTC ON 2.4 2.7 3.3 16 32 Backup SRAM ON, RTC OFF 2.4 2.6 3.0 12.5 24.8 Backup SRAM OFF, RTC OFF 1.7 1.9 2.2 9.8 19.2 1. Based on characterization, not tested in production. DocID022152 Rev 4 89/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 28. Typical VBAT current consumption (LSE and RTC ON/backup RAM OFF) Table 25. Typical and maximum current consumptions in VBAT mode Symbol Parameter Conditions Typ Max(1) Unit TA = 25 °C TA = 85 °C TA = 105 °C VBAT = 1.8 V VBAT= 2.4 V VBAT = 3.3 V VBAT = 3.6 V IDD_VBA T Backup domain supply current Backup SRAM ON, low-speed oscillator and RTC ON 1.29 1.42 1.68 6 11 μA Backup SRAM OFF, low-speed oscillator and RTC ON 0.62 0.73 0.96 3 5 Backup SRAM ON, RTC OFF 0.79 0.81 0.86 5 10 Backup SRAM OFF, RTC OFF 0.10 0.10 0.10 2 4 1. Based on characterization, not tested in production. MS19990V1 0 0.5 1 1.5 2 2.5 3 3.5 0 10 20 30 40 50 60 70 80 90 100 IVBAT in (μA) Temperature in (°C) 1.65V 1.8V 2V 2.4V 2.7V 3V 3.3V 3.6V Electrical characteristics STM32F405xx, STM32F407xx 90/185 DocID022152 Rev 4 Figure 29. Typical VBAT current consumption (LSE and RTC ON/backup RAM ON) I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 47: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption measured previously (see Table 27: Peripheral current consumption), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the MCU MS19991V1 0 1 2 3 4 5 6 0 10 20 30 40 50 60 70 80 90 100 IVBAT in (μA) Temperature in (°C) 1.65V 1.8V 2V 2.4V 2.7V 3V 3.3V 3.6V DocID022152 Rev 4 91/185 STM32F405xx, STM32F407xx Electrical characteristics supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: where ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDD is the MCU supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. ISW = VDD × fSW × C Electrical characteristics STM32F405xx, STM32F407xx 92/185 DocID022152 Rev 4 Table 26. Switching output I/O current consumption Symbol Parameter Conditions(1) I/O toggling frequency (fSW) Typ Unit IDDIO I/O switching current VDD = 3.3 V(2) C = CINT 2 MHz 0.02 mA 8 MHz 0.14 25 MHz 0.51 50 MHz 0.86 60 MHz 1.30 VDD = 3.3 V CEXT = 0 pF C = CINT + CEXT+ CS 2 MHz 0.10 8 MHz 0.38 25 MHz 1.18 50 MHz 2.47 60 MHz 2.86 VDD = 3.3 V CEXT = 10 pF C = CINT + CEXT+ CS 2 MHz 0.17 8 MHz 0.66 25 MHz 1.70 50 MHz 2.65 60 MHz 3.48 VDD = 3.3 V CEXT = 22 pF C = CINT + CEXT+ CS 2 MHz 0.23 8 MHz 0.95 25 MHz 3.20 50 MHz 4.69 60 MHz 8.06 VDD = 3.3 V CEXT = 33 pF C = CINT + CEXT+ CS 2 MHz 0.30 8 MHz 1.22 25 MHz 3.90 50 MHz 8.82 60 MHz -(3) 1. CS is the PCB board capacitance including the pad pin. CS = 7 pF (estimated value). 2. This test is performed by cutting the LQFP package pin (pad removal). 3. At 60 MHz, C maximum load is specified 30 pF. DocID022152 Rev 4 93/185 STM32F405xx, STM32F407xx Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 27. The MCU is placed under the following conditions: • At startup, all I/O pins are configured as analog pins by firmware. • All peripherals are disabled unless otherwise mentioned • The code is running from Flash memory and the Flash memory access time is equal to 5 wait states at 168 MHz. • The code is running from Flash memory and the Flash memory access time is equal to 4 wait states at 144 MHz, and the power scale mode is set to 2. • ART accelerator and Cache off. • The given value is calculated by measuring the difference of current consumption – with all peripherals clocked off – with one peripheral clocked on (with only the clock applied) • When the peripherals are enabled: HCLK is the system clock, fPCLK1 = fHCLK/4, and fPCLK2 = fHCLK/2. • The typical values are obtained for VDD = 3.3 V and TA= 25 °C, unless otherwise specified. Table 27. Peripheral current consumption Peripheral(1) 168 MHz 144 MHz Unit AHB1 GPIO A 0.49 0.36 mA GPIO B 0.45 0.33 GPIO C 0.45 0.34 GPIO D 0.45 0.34 GPIO E 0.47 0.35 GPIO F 0.45 0.33 GPIO G 0.44 0.33 GPIO H 0.45 0.34 GPIO I 0.44 0.33 OTG_HS + ULPI 4.57 3.55 CRC 0.07 0.06 BKPSRAM 0.11 0.08 DMA1 6.15 4.75 DMA2 6.24 4.8 ETH_MAC + ETH_MAC_TX ETH_MAC_RX ETH_MAC_PTP 3.28 2.54 AHB2 OTG_FS 4.59 3.69 mA DCMI 1.04 0.80 Electrical characteristics STM32F405xx, STM32F407xx 94/185 DocID022152 Rev 4 AHB3 FSMC 2.18 1.67 mA APB1 TIM2 0.80 0.61 TIM3 0.58 0.44 TIM4 0.62 0.48 TIM5 0.79 0.61 TIM6 0.15 0.11 TIM7 0.16 0.12 TIM12 0.33 0.26 TIM13 0.27 0.21 TIM14 0.27 0.21 PWR 0.04 0.03 USART2 0.17 0.13 USART3 0.17 0.13 UART4 0.17 0.13 UART5 0.17 0.13 I2C1 0.17 0.13 I2C2 0.18 0.13 I2C3 0.18 0.13 SPI2/I2S2(2) 0.17/0.16 0.13/0.12 SPI3/I2S3(2) 0.16/0.14 0.12/0.12 CAN1 0.27 0.21 CAN2 0.26 0.20 DAC 0.14 0.10 DAC channel 1(3) 0.91 0.89 DAC channel 2(4) 0.91 0.89 DAC channel 1 and 2(3)(4) 1.69 1.68 WWDG 0.04 0.04 Table 27. Peripheral current consumption (continued) Peripheral(1) 168 MHz 144 MHz Unit DocID022152 Rev 4 95/185 STM32F405xx, STM32F407xx Electrical characteristics 5.3.7 Wakeup time from low-power mode The wakeup times given in Table 28 is measured on a wakeup phase with a 16 MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: • Stop or Standby mode: the clock source is the RC oscillator • Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. APB2 SDIO 0.64 0.54 mA TIM1 1.47 1.14 TIM8 1.58 1.22 TIM9 0.68 0.54 TIM10 0.45 0.36 TIM11 0.47 0.38 ADC1(5) 2.20 2.10 ADC2(5) 2.04 1.93 ADC3(5) 2.10 2.00 SPI1 0.14 0.12 USART1 0.34 0.27 USART6 0.34 0.28 1. HSE oscillator with 4 MHz crystal and PLL are ON. 2. I2SMOD bit set in SPI_I2SCFGR register, and then the I2SE bit set to enable I2S peripheral. 3. EN1 bit is set in DAC_CR register. 4. EN2 bit is set in DAC_CR register. 5. ADON bit set in ADC_CR2 register. Table 27. Peripheral current consumption (continued) Peripheral(1) 168 MHz 144 MHz Unit Table 28. Low-power mode wakeup timings Symbol Parameter Min(1) Typ(1) Max(1) Unit tWUSLEEP (2) Wakeup from Sleep mode - 1 - μs tWUSTOP (2) Wakeup from Stop mode (regulator in Run mode) - 13 - Wakeup from Stop mode (regulator in low power mode) - 17 40 μs Wakeup from Stop mode (regulator in low power mode and Flash memory in Deep power down mode) - 110 - tWUSTDBY (2)(3) Wakeup from Standby mode 260 375 480 μs 1. Based on characterization, not tested in production. 2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction. 3. tWUSTDBY minimum and maximum values are given at 105 °C and –45 °C, respectively. Electrical characteristics STM32F405xx, STM32F407xx 96/185 DocID022152 Rev 4 5.3.8 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 29 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 14. Low-speed external user clock generated from an external source The characteristics given in Table 30 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 14. Table 29. High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit fHSE_ext External user clock source frequency(1) 1 - 50 MHz VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD V VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD tw(HSE) tw(HSE) OSC_IN high or low time(1) 1. Guaranteed by design, not tested in production. 5 - - ns tr(HSE) tf(HSE) OSC_IN rise or fall time(1) - - 10 Cin(HSE) OSC_IN input capacitance(1) - 5 - pF DuCy(HSE) Duty cycle 45 - 55 % IL OSC_IN Input leakage current VSS ≤ VIN ≤ VDD - - ±1 μA Table 30. Low-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit fLSE_ext User External clock source frequency(1) - 32.768 1000 kHz VLSEH OSC32_IN input pin high level voltage 0.7VDD - VDD V VLSEL OSC32_IN input pin low level voltage VSS - 0.3VDD tw(LSE) tf(LSE) OSC32_IN high or low time(1) 450 - - ns tr(LSE) tf(LSE) OSC32_IN rise or fall time(1) - - 50 Cin(LSE) OSC32_IN input capacitance(1) - 5 - pF DuCy(LSE) Duty cycle 30 - 70 % IL OSC32_IN Input leakage current VSS ≤ VIN ≤ VDD - - ±1 μA 1. Guaranteed by design, not tested in production. DocID022152 Rev 4 97/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 30. High-speed external clock source AC timing diagram Figure 31. Low-speed external clock source AC timing diagram High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 26 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 31. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). ai17528 OSC_IN External STM32F clock source VHSEH tf(HSE) tW(HSE) IL 90% 10% THSE tr(HSE) tW(HSE) t fHSE_ext VHSEL ai17529 External OSC32_IN STM32F clock source VLSEH tf(LSE) tW(LSE) IL 90% 10% TLSE tr(LSE) tW(LSE) t fLSE_ext VLSEL Electrical characteristics STM32F405xx, STM32F407xx 98/185 DocID022152 Rev 4 For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 32). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Note: For information on electing the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 32. Typical application with an 8 MHz crystal 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 32. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 31. HSE 4-26 MHz oscillator characteristics(1) (2) 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization, not tested in production. Symbol Parameter Conditions Min Typ Max Unit fOSC_IN Oscillator frequency 4 - 26 MHz RF Feedback resistor - 200 - kΩ IDD HSE current consumption VDD=3.3 V, ESR= 30 Ω, CL=5 pF@25 MHz - 449 - μA VDD=3.3 V, ESR= 30 Ω, CL=10 pF@25 MHz - 532 - gm Oscillator transconductance Startup 5 - - mA/V tSU(HSE (3) 3. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Startup time VDD is stabilized - 2 - ms ai17530 OSC_OUT OSC_IN fHSE CL1 RF STM32F 8 MHz resonator Resonator with integrated capacitors Bias controlled gain CL2 REXT(1) DocID022152 Rev 4 99/185 STM32F405xx, STM32F407xx Electrical characteristics Note: For information on electing the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 33. Typical application with a 32.768 kHz crystal 5.3.9 Internal clock source characteristics The parameters given in Table 33 and Table 34 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. High-speed internal (HSI) RC oscillator Table 32. LSE oscillator characteristics (fLSE = 32.768 kHz) (1) 1. Guaranteed by design, not tested in production. Symbol Parameter Conditions Min Typ Max Unit RF Feedback resistor - 18.4 - MΩ IDD LSE current consumption - - 1 μA gm Oscillator Transconductance 2.8 - - μA/V tSU(LSE) (2) 2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer startup time VDD is stabilized - 2 - s ai17531 OSC32_OUT OSC32_IN fLSE CL1 RF STM32F 32.768 kHz resonator Resonator with integrated capacitors Bias controlled gain CL2 Table 33. HSI oscillator characteristics (1) Symbol Parameter Conditions Min Typ Max Unit fHSI Frequency - 16 - MHz ACCHSI Accuracy of the HSI oscillator User-trimmed with the RCC_CR register - - 1 % Factorycalibrated TA = –40 to 105 °C(2) –8 - 4.5 % TA = –10 to 85 °C(2) –4 - 4 % TA = 25 °C –1 - 1 % tsu(HSI) (3) HSI oscillator startup time - 2.2 4 μs IDD(HSI) HSI oscillator power consumption - 60 80 μA Electrical characteristics STM32F405xx, STM32F407xx 100/185 DocID022152 Rev 4 Low-speed internal (LSI) RC oscillator Figure 34. ACCLSI versus temperature 5.3.10 PLL characteristics The parameters given in Table 35 and Table 36 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 14. 1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified. 2. Based on characterization, not tested in production. 3. Guaranteed by design, not tested in production. Table 34. LSI oscillator characteristics (1) 1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified. Symbol Parameter Min Typ Max Unit fLSI (2) 2. Based on characterization, not tested in production. Frequency 17 32 47 kHz tsu(LSI) (3) 3. Guaranteed by design, not tested in production. LSI oscillator startup time - 15 40 μs IDD(LSI) (3) LSI oscillator power consumption - 0.4 0.6 μA MS19013V1 -40 -30 -20 -10 0 10 20 30 40 50 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Normalized deviati on (%) Temperature (°C) max avg min DocID022152 Rev 4 101/185 STM32F405xx, STM32F407xx Electrical characteristics Table 35. Main PLL characteristics Symbol Parameter Conditions Min Typ Max Unit fPLL_IN PLL input clock(1) 0.95(2) 1 2.10 MHz fPLL_OUT PLL multiplier output clock 24 - 168 MHz fPLL48_OUT 48 MHz PLL multiplier output clock - 48 75 MHz fVCO_OUT PLL VCO output 192 - 432 MHz tLOCK PLL lock time VCO freq = 192 MHz 75 - 200 μs VCO freq = 432 MHz 100 - 300 Jitter(3) Cycle-to-cycle jitter System clock 120 MHz RMS - 25 - ps peak to peak - ±150 - Period Jitter RMS - 15 - peak to peak - ±200 - Main clock output (MCO) for RMII Ethernet Cycle to cycle at 50 MHz on 1000 samples - 32 - Main clock output (MCO) for MII Ethernet Cycle to cycle at 25 MHz on 1000 samples - 40 - Bit Time CAN jitter Cycle to cycle at 1 MHz on 1000 samples - 330 - IDD(PLL) (4) PLL power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLL) (4) PLL power consumption on VDDA VCO freq = 192 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA 1. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared between PLL and PLLI2S. 2. Guaranteed by design, not tested in production. 3. The use of 2 PLLs in parallel could degraded the Jitter up to +30%. 4. Based on characterization, not tested in production. Table 36. PLLI2S (audio PLL) characteristics Symbol Parameter Conditions Min Typ Max Unit fPLLI2S_IN PLLI2S input clock(1) 0.95(2) 1 2.10 MHz fPLLI2S_OUT PLLI2S multiplier output clock - - 216 MHz fVCO_OUT PLLI2S VCO output 192 - 432 MHz tLOCK PLLI2S lock time VCO freq = 192 MHz 75 - 200 μs VCO freq = 432 MHz 100 - 300 Electrical characteristics STM32F405xx, STM32F407xx 102/185 DocID022152 Rev 4 5.3.11 PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 43: EMI characteristics). It is available only on the main PLL. Equation 1 The frequency modulation period (MODEPER) is given by the equation below: fPLL_IN and fMod must be expressed in Hz. As an example: If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by equation 1: Jitter(3) Master I2S clock jitter Cycle to cycle at 12.288 MHz on 48KHz period, N=432, R=5 RMS - 90 - peak to peak - ±280 - ps Average frequency of 12.288 MHz N = 432, R = 5 on 1000 samples - 90 - ps WS I2S clock jitter Cycle to cycle at 48 KHz on 1000 samples - 400 - ps IDD(PLLI2S) (4) PLLI2S power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.75 mA IDDA(PLLI2S) (4) PLLI2S power consumption on VDDA VCO freq = 192 MHz VCO freq = 432 MHz 0.30 0.55 - 0.40 0.85 mA 1. Take care of using the appropriate division factor M to have the specified PLL input clock values. 2. Guaranteed by design, not tested in production. 3. Value given with main PLL running. 4. Based on characterization, not tested in production. Table 36. PLLI2S (audio PLL) characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit Table 37. SSCG parameters constraint Symbol Parameter Min Typ Max(1) Unit fMod Modulation frequency - - 10 KHz md Peak modulation depth 0.25 - 2 % MODEPER * INCSTEP - - 215−1 - 1. Guaranteed by design, not tested in production. MODEPER = round[fPLL_IN ⁄ (4 × fMod)] MODEPER round 106 4 10 3 = [ ⁄ ( × )] = 250 DocID022152 Rev 4 103/185 STM32F405xx, STM32F407xx Electrical characteristics Equation 2 Equation 2 allows to calculate the increment step (INCSTEP): fVCO_OUT must be expressed in MHz. With a modulation depth (md) = ±2 % (4 % peak to peak), and PLLN = 240 (in MHz): An amplitude quantization error may be generated because the linear modulation profile is obtained by taking the quantized values (rounded to the nearest integer) of MODPER and INCSTEP. As a result, the achieved modulation depth is quantized. The percentage quantized modulation depth is given by the following formula: As a result: Figure 35 and Figure 36 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. Figure 35. PLL output clock waveforms in center spread mode INCSTEP = round[((215 – 1) × md × PLLN) ⁄ (100 × 5 × MODEPER)] INCSTEP = round[((215 – 1) × 2 × 240) ⁄ (100 × 5 × 250)] = 126md(quantitazed)% mdquantized% = (MODEPER × INCSTEP × 100 × 5) ⁄ ((215 – 1) × PLLN) mdquantized% = (250 × 126 × 100 × 5) ⁄ ((215 – 1) × 240) = 2.002%(peak) Frequency (PLL_OUT) Time F0 tmode md ai17291 md 2 x tmode Electrical characteristics STM32F405xx, STM32F407xx 104/185 DocID022152 Rev 4 Figure 36. PLL output clock waveforms in down spread mode 5.3.12 Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified. The devices are shipped to customers with the Flash memory erased. Time ai17292 Frequency (PLL_OUT) F0 2 x md tmode 2 x tmode Table 38. Flash memory characteristics Symbol Parameter Conditions Min Typ Max Unit IDD Supply current Write / Erase 8-bit mode, VDD = 1.8 V - 5 - Write / Erase 16-bit mode, VDD = 2.1 V - 8 - mA Write / Erase 32-bit mode, VDD = 3.3 V - 12 - Table 39. Flash memory programming Symbol Parameter Conditions Min(1) Typ Max(1) Unit tprog Word programming time Program/erase parallelism (PSIZE) = x 8/16/32 - 16 100(2) μs tERASE16KB Sector (16 KB) erase time Program/erase parallelism (PSIZE) = x 8 - 400 800 Program/erase parallelism ms (PSIZE) = x 16 - 300 600 Program/erase parallelism (PSIZE) = x 32 - 250 500 DocID022152 Rev 4 105/185 STM32F405xx, STM32F407xx Electrical characteristics tERASE64KB Sector (64 KB) erase time Program/erase parallelism (PSIZE) = x 8 - 1200 2400 Program/erase parallelism ms (PSIZE) = x 16 - 700 1400 Program/erase parallelism (PSIZE) = x 32 - 550 1100 tERASE128KB Sector (128 KB) erase time Program/erase parallelism (PSIZE) = x 8 - 2 4 Program/erase parallelism s (PSIZE) = x 16 - 1.3 2.6 Program/erase parallelism (PSIZE) = x 32 - 1 2 tME Mass erase time Program/erase parallelism (PSIZE) = x 8 - 16 32 Program/erase parallelism s (PSIZE) = x 16 - 11 22 Program/erase parallelism (PSIZE) = x 32 - 8 16 Vprog Programming voltage 32-bit program operation 2.7 - 3.6 V 16-bit program operation 2.1 - 3.6 V 8-bit program operation 1.8 - 3.6 V 1. Based on characterization, not tested in production. 2. The maximum programming time is measured after 100K erase operations. Table 39. Flash memory programming (continued) Symbol Parameter Conditions Min(1) Typ Max(1) Unit Electrical characteristics STM32F405xx, STM32F407xx 106/185 DocID022152 Rev 4 5.3.13 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. Table 40. Flash memory programming with VPP Symbol Parameter Conditions Min(1) Typ Max(1) 1. Guaranteed by design, not tested in production. Unit tprog Double word programming TA = 0 to +40 °C VDD = 3.3 V VPP = 8.5 V - 16 100(2) 2. The maximum programming time is measured after 100K erase operations. μs tERASE16KB Sector (16 KB) erase time - 230 - tERASE64KB Sector (64 KB) erase time - 490 - ms tERASE128KB Sector (128 KB) erase time - 875 - tME Mass erase time - 6.9 - s Vprog Programming voltage 2.7 - 3.6 V VPP VPP voltage range 7 - 9 V IPP Minimum current sunk on the VPP pin 10 - - mA tVPP (3) 3. VPP should only be connected during programming/erasing. Cumulative time during which VPP is applied - - 1 hour Table 41. Flash memory endurance and data retention Symbol Parameter Conditions Value Unit Min(1) 1. Based on characterization, not tested in production. NEND Endurance TA = –40 to +85 °C (6 suffix versions) TA = –40 to +105 °C (7 suffix versions) 10 kcycles tRET Data retention 1 kcycle(2) at TA = 85 °C 2. Cycling performed over the whole temperature range. 30 1 kcycle(2) at TA = 105 °C 10 Years 10 kcycles(2) at TA = 55 °C 20 DocID022152 Rev 4 107/185 STM32F405xx, STM32F407xx Electrical characteristics A device reset allows normal operations to be resumed. The test results are given in Table 42. They are based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: • Corrupted program counter • Unexpected reset • Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC? code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. Table 42. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD = 3.3 V, LQFP176, TA = +25 °C, fHCLK = 168 MHz, conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, LQFP176, TA = +25 °C, fHCLK = 168 MHz, conforms to IEC 61000-4-2 4A Electrical characteristics STM32F405xx, STM32F407xx 108/185 DocID022152 Rev 4 5.3.14 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Static latchup Two complementary static tests are required on six parts to assess the latchup performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latchup standard. Table 43. EMI characteristics Symbol Parameter Conditions Monitored frequency band Max vs. [fHSE/fCPU] Unit 25/168 MHz SEMI Peak level VDD = 3.3 V, TA = 25 °C, LQFP176 package, conforming to SAE J1752/3 EEMBC, code running from Flash with ART accelerator enabled 0.1 to 30 MHz 32 30 to 130 MHz 25 dBμV 130 MHz to 1GHz 29 SAE EMI Level 4 - VDD = 3.3 V, TA = 25 °C, LQFP176 package, conforming to SAE J1752/3 EEMBC, code running from Flash with ART accelerator and PLL spread spectrum enabled 0.1 to 30 MHz 19 30 to 130 MHz 16 dBμV 130 MHz to 1GHz 18 SAE EMI level 3.5 - Table 44. ESD absolute maximum ratings Symbol Ratings Conditions Class Maximum value(1) Unit VESD(HBM) Electrostatic discharge voltage (human body model) TA = +25 °C conforming to JESD22-A114 2 2000(2) V VESD(CDM) Electrostatic discharge voltage (charge device model) TA = +25 °C conforming to JESD22-C101 II 500 1. Based on characterization results, not tested in production. 2. On VBAT pin, VESD(HBM) is limited to 1000 V. DocID022152 Rev 4 109/185 STM32F405xx, STM32F407xx Electrical characteristics 5.3.15 I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibilty to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of 5 uA/+0 uA range), or other functional failure (for example reset, oscillator frequency deviation). Negative induced leakage current is caused by negative injection and positive induced leakage current by positive injection. The test results are given in Table 46. 5.3.16 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 47 are derived from tests performed under the conditions summarized in Table 14. All I/Os are CMOS and TTL compliant. Table 45. Electrical sensitivities Symbol Parameter Conditions Class LU Static latch-up class TA = +105 °C conforming to JESD78A II level A Table 46. I/O current injection susceptibility Symbol Description Functional susceptibility Negative Unit injection Positive injection IINJ (1) 1. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Injected current on all FT pins –5 +0 mA Injected current on any other pin –5 +5 Electrical characteristics STM32F405xx, STM32F407xx 110/185 DocID022152 Rev 4 All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can sink or source up to ±3mA. When using the PC13 to PC15 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF. Table 47. I/O static characteristics Symbol Parameter Conditions Min Typ Max Unit VIL Input low level voltage TTL ports 2.7 V ≤ VDD ≤ 3.6 V - - 0.8 V VIH (1) Input high level voltage 2.0 - - VIL Input low level voltage CMOS ports 1.8 V ≤ VDD ≤ 3.6 V - - 0.3VDD VIH (1) Input high level voltage 0.7VDD - - - - Vhys I/O Schmitt trigger voltage hysteresis(2) - 200 - IO FT Schmitt trigger voltage mV hysteresis(2) 5% VDD (3) - - Ilkg I/O input leakage current (4) VSS ≤ VIN ≤ VDD - - ±1 μA I/O FT input leakage current (4) VIN = 5 V - - 3 RPU Weak pull-up equivalent resistor(5) All pins except for PA10 and PB12 VIN = VSS 30 40 50 kΩ PA10 and PB12 8 11 15 RPD Weak pull-down equivalent resistor All pins except for PA10 and PB12 VIN = VDD 30 40 50 PA10 and PB12 8 11 15 CIO (6) I/O pin capacitance 5 pF 1. Tested in production. 2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production. 3. With a minimum of 100 mV. 4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order). 6. Guaranteed by design, not tested in production. DocID022152 Rev 4 111/185 STM32F405xx, STM32F407xx Electrical characteristics In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2. In particular: • The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 12). • The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 12). Output voltage levels Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. All I/Os are CMOS and TTL compliant. Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 37 and Table 49, respectively. Table 48. Output voltage characteristics(1) 1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED). Symbol Parameter Conditions Min Max Unit VOL (2) 2. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. Output low level voltage for an I/O pin when 8 pins are sunk at same time CMOS port IIO = +8 mA 2.7 V < VDD < 3.6 V - 0.4 V VOH (3) 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. Output high level voltage for an I/O pin when 8 pins are sourced at same time VDD–0.4 - VOL (2) Output low level voltage for an I/O pin when 8 pins are sunk at same time TTL port IIO =+ 8mA 2.7 V < VDD < 3.6 V - 0.4 V VOH (3) Output high level voltage for an I/O pin when 8 pins are sourced at same time 2.4 - VOL (2)(4) 4. Based on characterization data, not tested in production. Output low level voltage for an I/O pin when 8 pins are sunk at same time IIO = +20 mA 2.7 V < VDD < 3.6 V - 1.3 V VOH (3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time VDD–1.3 - VOL (2)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time IIO = +6 mA 2 V < VDD < 2.7 V - 0.4 V VOH (3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time VDD–0.4 - Electrical characteristics STM32F405xx, STM32F407xx 112/185 DocID022152 Rev 4 Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 49. I/O AC characteristics(1)(2)(3) OSPEEDRy [1:0] bit value(1) Symbol Parameter Conditions Min Typ Max Unit 00 fmax(IO)out Maximum frequency(4) CL = 50 pF, VDD > 2.70 V - - 2 MHz CL = 50 pF, VDD > 1.8 V - - 2 CL = 10 pF, VDD > 2.70 V - - TBD CL = 10 pF, VDD > 1.8 V - - TBD tf(IO)out Output high to low level fall time CL = 50 pF, VDD = 1.8 V to 3.6 V - - TBD ns tr(IO)out Output low to high level rise time - - TBD 01 fmax(IO)out Maximum frequency(4) CL = 50 pF, VDD > 2.70 V - - 25 MHz CL = 50 pF, VDD > 1.8 V - - 12.5(5) CL = 10 pF, VDD > 2.70 V - - 50(5) CL = 10 pF, VDD > 1.8 V - - TBD tf(IO)out Output high to low level fall time CL = 50 pF, VDD < 2.7 V - - TBD ns CL = 10 pF, VDD > 2.7 V - - TBD tr(IO)out Output low to high level rise time CL = 50 pF, VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD 10 fmax(IO)out Maximum frequency(4) CL = 40 pF, VDD > 2.70 V - - 50(5) MHz CL = 40 pF, VDD > 1.8 V - - 25 CL = 10 pF, VDD > 2.70 V - - 100(5) CL = 10 pF, VDD > 1.8 V - - TBD tf(IO)out Output high to low level fall time CL = 50 pF, 2.4 < VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD ns tr(IO)out Output low to high level rise time CL = 50 pF, 2.4 < VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD DocID022152 Rev 4 113/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 37. I/O AC characteristics definition 5.3.17 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 47). Unless otherwise specified, the parameters given in Table 50 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 14. 11 Fmax(IO)ou t Maximum frequency(4) CL = 30 pF, VDD > 2.70 V - - 100(5) MHz CL = 30 pF, VDD > 1.8 V - - 50(5) CL = 10 pF, VDD > 2.70 V - - 200(5) CL = 10 pF, VDD > 1.8 V - - TBD tf(IO)out Output high to low level fall time CL = 20 pF, 2.4 < VDD < 2.7 V - - TBD ns CL = 10 pF, VDD > 2.7 V - - TBD tr(IO)out Output low to high level rise time CL = 20 pF, 2.4 < VDD < 2.7 V - - TBD CL = 10 pF, VDD > 2.7 V - - TBD - tEXTIpw Pulse width of external signals detected by the EXTI controller 10 - - ns 1. Based on characterization data, not tested in production. 2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F20/21xxx reference manual for a description of the GPIOx_SPEEDR GPIO port output speed register. 3. TBD stands for “to be defined”. 4. The maximum frequency is defined in Figure 37. 5. For maximum frequencies above 50 MHz, the compensation cell should be used. Table 49. I/O AC characteristics(1)(2)(3) (continued) OSPEEDRy [1:0] bit value(1) Symbol Parameter Conditions Min Typ Max Unit ai14131 10% 90% 50% tr(IO)out OUTPUT EXTERNAL ON 50pF Maximum frequency is achieved if (tr + tf) ≤ 2/3)T and if the duty cycle is (45-55%) 10% 50% 90% when loaded by 50pF T tr(IO)out Electrical characteristics STM32F405xx, STM32F407xx 114/185 DocID022152 Rev 4 Figure 38. Recommended NRST pin protection 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 50. Otherwise the reset is not taken into account by the device. 5.3.18 TIM timer characteristics The parameters given in Table 51 and Table 52 are guaranteed by design. Refer to Section 5.3.16: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 50. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit VIL(NRST) (1) 1. Guaranteed by design, not tested in production. NRST Input low level voltage TTL ports 2.7 V ≤ VDD ≤ 3.6 V - - 0.8 V VIH(NRST) (1) NRST Input high level voltage 2 - - VIL(NRST) (1) NRST Input low level voltage CMOS ports 1.8 V ≤ VDD ≤ 3.6 V - 0.3VDD VIH(NRST) (1) NRST Input high level voltage 0.7VDD - Vhys(NRST) NRST Schmitt trigger voltage hysteresis - 200 - mV RPU Weak pull-up equivalent resistor(2) 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). VIN = VSS 30 40 50 kΩ VF(NRST) (1) NRST Input filtered pulse - - 100 ns VNF(NRST) (1) NRST Input not filtered pulse VDD > 2.7 V 300 - - ns TNRST_OUT Generated reset pulse duration Internal Reset source 20 - - μs ai14132c STM32Fxxx NRST(2) RPU VDD Filter Internal Reset 0.1 μF External reset circuit(1) DocID022152 Rev 4 115/185 STM32F405xx, STM32F407xx Electrical characteristics Table 51. Characteristics of TIMx connected to the APB1 domain(1) 1. TIMx is used as a general term to refer to the TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, and TIM12 timers. Symbol Parameter Conditions Min Max Unit tres(TIM) Timer resolution time AHB/APB1 prescaler distinct from 1, fTIMxCLK = 84 MHz 1 - tTIMxCLK 11.9 - ns AHB/APB1 prescaler = 1, fTIMxCLK = 42 MHz 1 - tTIMxCLK 23.8 - ns fEXT Timer external clock frequency on CH1 to CH4 fTIMxCLK = 84 MHz APB1= 42 MHz 0 fTIMxCLK/2 MHz 0 42 MHz ResTIM Timer resolution - 16/32 bit tCOUNTER 16-bit counter clock period when internal clock is selected 1 65536 tTIMxCLK 0.0119 780 μs 32-bit counter clock period when internal clock is selected 1 - tTIMxCLK 0.0119 51130563 μs tMAX_COUNT Maximum possible count - 65536 × 65536 tTIMxCLK - 51.1 s Electrical characteristics STM32F405xx, STM32F407xx 116/185 DocID022152 Rev 4 5.3.19 Communications interfaces I2C interface characteristics The STM32F405xx and STM32F407xx I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 53. Refer also to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 52. Characteristics of TIMx connected to the APB2 domain(1) 1. TIMx is used as a general term to refer to the TIM1, TIM8, TIM9, TIM10, and TIM11 timers. Symbol Parameter Conditions Min Max Unit tres(TIM) Timer resolution time AHB/APB2 prescaler distinct from 1, fTIMxCLK = 168 MHz 1 - tTIMxCLK 5.95 - ns AHB/APB2 prescaler = 1, fTIMxCLK = 84 MHz 1 - tTIMxCLK 11.9 - ns fEXT Timer external clock frequency on CH1 to CH4 fTIMxCLK = 168 MHz APB2 = 84 MHz 0 fTIMxCLK/2 MHz 0 84 MHz ResTIM Timer resolution - 16 bit tCOUNTER 16-bit counter clock period when internal clock is selected 1 65536 tTIMxCLK tMAX_COUNT Maximum possible count - 32768 tTIMxCLK Table 53. I2C characteristics Symbol Parameter Standard mode I2C(1) Fast mode I2C(1)(2) Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - μs tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - ns th(SDA) SDA data hold time 0(3) - 0 900(4) tr(SDA) tr(SCL) SDA and SCL rise time - 1000 20 + 0.1Cb 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 DocID022152 Rev 4 117/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 39. I2C bus AC waveforms and measurement circuit 1. Rs= series protection resistor. 2. Rp = external pull-up resistor. 3. VDD_I2C is the I2C bus power supply. th(STA) Start condition hold time 4.0 - 0.6 - μs tsu(STA) Repeated Start condition setup time 4.7 - 0.6 - tsu(STO) Stop condition setup time 4.0 - 0.6 - μs tw(STO:STA) Stop to Start condition time (bus free) 4.7 - 1.3 - μs Cb Capacitive load for each bus line - 400 - 400 pF 1. Guaranteed by design, not tested in production. 2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to achieve fast mode I2C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode clock. 3. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 4. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal. Table 53. I2C characteristics (continued) Symbol Parameter Standard mode I2C(1) Fast mode I2C(1)(2) Unit Min Max Min Max ai14979c S TAR T SD A RP I²C bus VDD_I2C STM32Fxx SDA SCL tf(SDA) tr(SDA) SCL th(STA) tw(SCLH) tw(SCLL) tsu(SDA) tr(SCL) tf(SCL) th(SDA) S TAR T REPEATED t S TAR T su(STA) tsu(STO) S TOP tw(STO:STA) VDD_I2C RP RS RS Electrical characteristics STM32F405xx, STM32F407xx 118/185 DocID022152 Rev 4 SPI interface characteristics Unless otherwise specified, the parameters given in Table 55 for SPI are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14 with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 54. SCL frequency (fPCLK1= 42 MHz.,VDD = 3.3 V)(1)(2) 1. RP = External pull-up resistance, fSCL = I2C speed, 2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external components used to design the application. fSCL (kHz) I2C_CCR value RP = 4.7 kΩ 400 0x8019 300 0x8021 200 0x8032 100 0x0096 50 0x012C 20 0x02EE Table 55. SPI dynamic characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fSCK SPI clock frequency Master mode, SPI1, 2.7V < VDD < 3.6V - - 42 MHz Slave mode, SPI1, 2.7V < VDD < 3.6V 42 1/tc(SCK) Master mode, SPI1/2/3, 1.7V < VDD < 3.6V - - 21 Slave mode, SPI1/2/3, 1.7V < VDD < 3.6V 21 Duty(SCK) Duty cycle of SPI clock frequency Slave mode 30 50 70 % DocID022152 Rev 4 119/185 STM32F405xx, STM32F407xx Electrical characteristics tw(SCKH) SCK high and low time Master mode, SPI presc = 2, 2.7V < VDD < 3.6V TPCLK-0.5 TPCLK TPCLK+0.5 ns tw(SCKL) Master mode, SPI presc = 2, 1.7V < VDD < 3.6V TPCLK-2 TPCLK TPCLK+2 tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4 x TPCLK - - th(NSS) NSS hold time Slave mode, SPI presc = 2 2 x TPCLK tsu(MI) Data input setup time Master mode 6.5 - - tsu(SI) Slave mode 2.5 - - th(MI) Data input hold time Master mode 2.5 - - th(SI) Slave mode 4 - - ta(SO) (2) Data output access time Slave mode, SPI presc = 2 0 - 4 x TPCLK tdis(SO) (3) Data output disable time Slave mode, SPI1, 2.7V < VDD < 3.6V 0 - 7.5 Slave mode, SPI1/2/3 1.7V < VDD < 3.6V 0 - 16.5 tv(SO) th(SO) Data output valid/hold time Slave mode (after enable edge), SPI1, 2.7V < VDD < 3.6V - 11 13 Slave mode (after enable edge), SPI2/3, 2.7V < VDD < 3.6V - 12 16.5 Slave mode (after enable edge), SPI1, 1.7V < VDD < 3.6V - 15.5 19 Slave mode (after enable edge), SPI2/3, 1.7V < VDD < 3.6V - 18 20.5 tv(MO) Data output valid time Master mode (after enable edge), SPI1 , 2.7V < VDD < 3.6V - - 2.5 Master mode (after enable edge), SPI1/2/3 , 1.7V < VDD < 3.6V - - 4.5 th(MO) Data output hold time Master mode (after enable edge) 0 - - 1. Data based on characterization results, not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z. Table 55. SPI dynamic characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit Electrical characteristics STM32F405xx, STM32F407xx 120/185 DocID022152 Rev 4 Figure 40. SPI timing diagram - slave mode and CPHA = 0 Figure 41. SPI timing diagram - slave mode and CPHA = 1 ai14134c SCK Input CPHA=0 MOSI INPUT MISO OUT PUT CPHA=0 MSB O UT MSB IN BIT6 OUT LSB IN LSB OUT CPOL=0 CPOL=1 BIT1 IN NSS input tSU(NSS) tc(SCK) th(NSS) ta(SO) tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK) tdis(SO) tsu(SI) th(SI) ai14135 SCK Input CPHA=1 MOSI INPUT MISO OUT PUT CPHA=1 MSB O UT MSB IN BIT6 OUT LSB IN LSB OUT CPOL=0 CPOL=1 BIT1 IN tSU(NSS) tc(SCK) th(NSS) ta(SO) tw(SCKH) tw(SCKL) tv(SO) th(SO) tr(SCK) tf(SCK) tdis(SO) tsu(SI) th(SI) NSS input DocID022152 Rev 4 121/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 42. SPI timing diagram - master mode ai14136 SCK Input CPHA=0 MOSI OUTUT MISO INPUT CPHA=0 MSBIN MSB OUT BIT6 IN LSB OUT LSB IN CPOL=0 CPOL=1 BIT1 OUT NSS input tc(SCK) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) th(MI) High SCK Input CPHA=1 CPHA=1 CPOL=0 CPOL=1 tsu(MI) tv(MO) th(MO) Electrical characteristics STM32F405xx, STM32F407xx 122/185 DocID022152 Rev 4 I2S interface characteristics Unless otherwise specified, the parameters given in Table 56 for the i2S interface are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 VDD Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CK, SD, WS). Note: Refer to the I2S section of RM0090 reference manual for more details on the sampling frequency (FS). fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The value of these parameters might be slightly impacted by the source clock accuracy. DCK depends mainly on the value of ODD bit. The digital contribution leads to a minimum value of I2SDIV / (2 x I2SDIV + ODD) and a maximum value of (I2SDIV + ODD) / (2 x I2SDIV + ODD). FS maximum value is supported for each mode/condition. Table 56. I2S dynamic characteristics(1) Symbol Parameter Conditions Min Max Unit fMCK I2S main clock output - 256 x 8K 256 x FS (2) MHz fCK I2S clock frequency Master data: 32 bits - 64 x FS MHz Slave data: 32 bits - 64 x FS DCK I2S clock frequency duty cycle Slave receiver 30 70 % tv(WS) WS valid time Master mode 0 6 ns th(WS) WS hold time Master mode 0 - tsu(WS) WS setup time Slave mode 1 - th(WS) WS hold time Slave mode 0 - tsu(SD_MR) Data input setup time Master receiver 7.5 - tsu(SD_SR) Slave receiver 2 - th(SD_MR) Data input hold time Master receiver 0 - th(SD_SR) Slave receiver 0 - tv(SD_ST) th(SD_ST) Data output valid time Slave transmitter (after enable edge) - 27 tv(SD_MT) Master transmitter (after enable edge) - 20 th(SD_MT) Data output hold time Master transmitter (after enable edge) 2.5 - 1. Data based on characterization results, not tested in production. 2. The maximum value of 256 x FS is 42 MHz (APB1 maximum frequency). DocID022152 Rev 4 123/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 43. I2S slave timing diagram (Philips protocol) 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 44. I2S master timing diagram (Philips protocol)(1) 1. Based on characterization, not tested in production. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. USB OTG FS characteristics This interface is present in both the USB OTG HS and USB OTG FS controllers. CK Input CPOL = 0 CPOL = 1 tc(CK) WS input SDtransmit SDreceive tw(CKH) tw(CKL) tsu(WS) tv(SD_ST) th(SD_ST) th(WS) tsu(SD_SR) th(SD_SR) MSB receive Bitn receive LSB receive MSB transmit Bitn transmit LSB transmit ai14881b LSB receive(2) LSB transmit(2) CK output CPOL = 0 CPOL = 1 tc(CK) WS output SDreceive SDtransmit tw(CKH) tw(CKL) tsu(SD_MR) tv(SD_MT) th(SD_MT) th(WS) th(SD_MR) MSB receive Bitn receive LSB receive MSB transmit Bitn transmit LSB transmit ai14884b tf(CK) tr(CK) tv(WS) LSB receive(2) LSB transmit(2) Electrical characteristics STM32F405xx, STM32F407xx 124/185 DocID022152 Rev 4 Figure 45. USB OTG FS timings: definition of data signal rise and fall time Table 57. USB OTG FS startup time Symbol Parameter Max Unit tSTARTUP (1) 1. Guaranteed by design, not tested in production. USB OTG FS transceiver startup time 1 μs Table 58. USB OTG FS DC electrical characteristics Symbol Parameter Conditions Min.(1) 1. All the voltages are measured from the local ground potential. Typ. Max.(1) Unit Input levels VDD USB OTG FS operating voltage 3.0(2) 2. The STM32F405xx and STM32F407xx USB OTG FS functionality is ensured down to 2.7 V but not the full USB OTG FS electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. - 3.6 V VDI (3) 3. Guaranteed by design, not tested in production. Differential input sensitivity I(USB_FS_DP/DM, USB_HS_DP/DM) 0.2 - - VCM V (3) Differential common mode range Includes VDI range 0.8 - 2.5 VSE (3) Single ended receiver threshold 1.3 - 2.0 Output levels VOL Static output level low RL of 1.5 kΩ to 3.6 V(4) 4. RL is the load connected on the USB OTG FS drivers - - 0.3 V VOH Static output level high RL of 15 kΩ to VSS (4) 2.8 - 3.6 RPD PA11, PA12, PB14, PB15 (USB_FS_DP/DM, USB_HS_DP/DM) VIN = VDD 17 21 24 kΩ PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) 0.65 1.1 2.0 RPU PA12, PB15 (USB_FS_DP, USB_HS_DP) VIN = VSS 1.5 1.8 2.1 PA9, PB13 (OTG_FS_VBUS, OTG_HS_VBUS) VIN = VSS 0.25 0.37 0.55 ai14137 tf Differen tial Data L ines VSS VCRS tr Crossover points DocID022152 Rev 4 125/185 STM32F405xx, STM32F407xx Electrical characteristics USB HS characteristics Unless otherwise specified, the parameters given in Table 62 for ULPI are derived from tests performed under the ambient temperature, fHCLK frequency summarized in Table 61 and VDD supply voltage conditions summarized in Table 60, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD. Refer to Section Section 5.3.16: I/O port characteristics for more details on the input/outputcharacteristics. Table 59. USB OTG FS electrical characteristics(1) 1. Guaranteed by design, not tested in production. Driver characteristics Symbol Parameter Conditions Min Max Unit tr Rise time(2) 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). CL = 50 pF 4 20 ns tf Fall time(2) CL = 50 pF 4 20 ns trfm Rise/ fall time matching tr/tf 90 110 % VCRS Output signal crossover voltage 1.3 2.0 V Table 60. USB HS DC electrical characteristics Symbol Parameter Min.(1) 1. All the voltages are measured from the local ground potential. Max.(1) Unit Input level VDD USB OTG HS operating voltage 2.7 3.6 V Table 61. USB HS clock timing parameters(1) Parameter Symbol Min Nominal Max Unit fHCLK value to guarantee proper operation of USB HS interface 30 MHz Frequency (first transition) 8-bit ±10% FSTART_8BIT 54 60 66 MHz Frequency (steady state) ±500 ppm FSTEADY 59.97 60 60.03 MHz Duty cycle (first transition) 8-bit ±10% DSTART_8BIT 40 50 60 % Duty cycle (steady state) ±500 ppm DSTEADY 49.975 50 50.025 % Time to reach the steady state frequency and duty cycle after the first transition TSTEADY - - 1.4 ms Clock startup time after the de-assertion of SuspendM Peripheral TSTART_DEV - - 5.6 ms Host TSTART_HOST - - - PHY preparation time after the first transition of the input clock TPREP - - - μs Electrical characteristics STM32F405xx, STM32F407xx 126/185 DocID022152 Rev 4 Figure 46. ULPI timing diagram Ethernet characteristics Unless otherwise specified, the parameters given in Table 64, Table 65 and Table 66 for SMI, RMII and MII are derived from tests performed under the ambient temperature, fHCLK frequency summarized in Table 14 and VDD supply voltage conditions summarized in Table 63, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD. Refer to Section 5.3.16: I/O port characteristics for more details on the input/output characteristics. 1. Guaranteed by design, not tested in production. Table 62. ULPI timing Parameter Symbol Value(1) 1. VDD = 2.7 V to 3.6 V and TA = –40 to 85 °C. Unit Min. Max. Control in (ULPI_DIR) setup time tSC - 2.0 ns Control in (ULPI_NXT) setup time - 1.5 Control in (ULPI_DIR, ULPI_NXT) hold time tHC 0 - Data in setup time tSD - 2.0 Data in hold time tHD 0 - Control out (ULPI_STP) setup time and hold time tDC - 9.2 Data out available from clock rising edge tDD - 10.7 Clock Control In (ULPI_DIR, ULPI_NXT) data In (8-bit) Control out (ULPI_STP) data out (8-bit) tDD tDC tSD tHD tSC tHC ai17361c tDC DocID022152 Rev 4 127/185 STM32F405xx, STM32F407xx Electrical characteristics Table 64 gives the list of Ethernet MAC signals for the SMI (station management interface) and Figure 47 shows the corresponding timing diagram. Figure 47. Ethernet SMI timing diagram Table 65 gives the list of Ethernet MAC signals for the RMII and Figure 48 shows the corresponding timing diagram. Figure 48. Ethernet RMII timing diagram Table 63. Ethernet DC electrical characteristics Symbol Parameter Min.(1) 1. All the voltages are measured from the local ground potential. Max.(1) Unit Input level VDD Ethernet operating voltage 2.7 3.6 V Table 64. Dynamic characteristics: Ehternet MAC signals for SMI(1) 1. Data based on characterization results, not tested in production. Symbol Parameter Min Typ Max Unit tMDC MDC cycle time( 2.38 MHz) 411 420 425 ns Td(MDIO) Write data valid time 6 10 13 tsu(MDIO) Read data setup time 12 - - th(MDIO) Read data hold time 0 - - MS31384V1 ETH_MDC ETH_MDIO(O) ETH_MDIO(I) tMDC td(MDIO) tsu(MDIO) th(MDIO) RMII_REF_CLK RMII_TX_EN RMII_TXD[1:0] RMII_RXD[1:0] RMII_CRS_DV td(TXEN) td(TXD) tsu(RXD) tsu(CRS) tih(RXD) tih(CRS) ai15667 Electrical characteristics STM32F405xx, STM32F407xx 128/185 DocID022152 Rev 4 Table 66 gives the list of Ethernet MAC signals for MII and Figure 48 shows the corresponding timing diagram. Figure 49. Ethernet MII timing diagram Table 65. Dynamic characteristics: Ethernet MAC signals for RMII Symbol Rating Min Typ Max Unit tsu(RXD) Receive data setup time 2 - - ns tih(RXD) Receive data hold time 1 - - ns tsu(CRS) Carrier sense set-up time 0.5 - - ns tih(CRS) Carrier sense hold time 2 - - ns td(TXEN) Transmit enable valid delay time 8 9.5 11 ns td(TXD) Transmit data valid delay time 8.5 10 11.5 ns Table 66. Dynamic characteristics: Ethernet MAC signals for MII(1) 1. Data based on characterization results, not tested in production. Symbol Parameter Min Typ Max Unit tsu(RXD) Receive data setup time 9 - ns tih(RXD) Receive data hold time 10 - tsu(DV) Data valid setup time 9 - tih(DV) Data valid hold time 8 - tsu(ER) Error setup time 6 - tih(ER) Error hold time 8 - td(TXEN) Transmit enable valid delay time 0 10 14 td(TXD) Transmit data valid delay time 0 10 15 MII_RX_CLK MII_RXD[3:0] MII_RX_DV MII_RX_ER td(TXEN) td(TXD) tsu(RXD) tsu(ER) tsu(DV) tih(RXD) tih(ER) tih(DV) ai15668 MII_TX_CLK MII_TX_EN MII_TXD[3:0] DocID022152 Rev 4 129/185 STM32F405xx, STM32F407xx Electrical characteristics CAN (controller area network) interface Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CANTX and CANRX). 5.3.20 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 67 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 14. Table 67. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply 1.8(1) - 3.6 V VREF+ Positive reference voltage 1.8(1)(2)(3) - VDDA V fADC ADC clock frequency VDDA = 1.8(1)(3) to 2.4 V 0.6 15 18 MHz VDDA = 2.4 to 3.6 V(3) 0.6 30 36 MHz fTRIG (4) External trigger frequency fADC = 30 MHz, 12-bit resolution - - 1764 kHz - - 17 1/fADC VAIN Conversion voltage range(5) 0 (VSSA or VREFtied to ground) - VREF+ V RAIN (4) External input impedance See Equation 1 for details - - 50 κΩ RADC (4)(6) Sampling switch resistance - - 6 κΩ CADC (4) Internal sample and hold capacitor - 4 - pF tlat (4) Injection trigger conversion latency fADC = 30 MHz - - 0.100 μs - - 3(7) 1/fADC tlatr (4) Regular trigger conversion latency fADC = 30 MHz - - 0.067 μs - - 2(7) 1/fADC tS (4) Sampling time fADC = 30 MHz 0.100 - 16 μs 3 - 480 1/fADC tSTAB (4) Power-up time - 2 3 μs Electrical characteristics STM32F405xx, STM32F407xx 130/185 DocID022152 Rev 4 Equation 1: RAIN max formula The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of sampling periods defined in the ADC_SMPR1 register. tCONV (4) Total conversion time (including sampling time) fADC = 30 MHz 12-bit resolution 0.50 - 16.40 μs fADC = 30 MHz 10-bit resolution 0.43 - 16.34 μs fADC = 30 MHz 8-bit resolution 0.37 - 16.27 μs fADC = 30 MHz 6-bit resolution 0.30 - 16.20 μs 9 to 492 (tS for sampling +n-bit resolution for successive approximation) 1/fADC fS (4) Sampling rate (fADC = 30 MHz, and tS = 3 ADC cycles) 12-bit resolution Single ADC - - 2 Msps 12-bit resolution Interleave Dual ADC mode - - 3.75 Msps 12-bit resolution Interleave Triple ADC mode - - 6 Msps IVREF+ (4) ADC VREF DC current consumption in conversion mode - 300 500 μA IVDDA (4) ADC VDDA DC current consumption in conversion mode - 1.6 1.8 mA 1. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). 2. It is recommended to maintain the voltage difference between VREF+ and VDDA below 1.8 V. 3. VDDA -VREF+ < 1.2 V. 4. Based on characterization, not tested in production. 5. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA. 6. RADC maximum value is given for VDD=1.8 V, and minimum value for VDD=3.3 V. 7. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 67. Table 67. ADC characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit RAIN (k – 0.5) fADC CADC 2N + 2 × × ln( ) = -------------------------------------------------------------- – RADC DocID022152 Rev 4 131/185 STM32F405xx, STM32F407xx Electrical characteristics a Note: ADC accuracy vs. negative injection current: injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.16 does not affect the ADC accuracy. Figure 50. ADC accuracy characteristics 1. See also Table 68. 2. Example of an actual transfer curve. 3. Ideal transfer curve. 4. End point correlation line. 5. ET = Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO = Offset Error: deviation between the first actual transition and the first ideal one. Table 68. ADC accuracy at fADC = 30 MHz(1) 1. Better performance could be achieved in restricted VDD, frequency and temperature ranges. Symbol Parameter Test conditions Typ Max(2) 2. Based on characterization, not tested in production. Unit ET Total unadjusted error fPCLK2 = 60 MHz, fADC = 30 MHz, RAIN < 10 kΩ, VDDA = 1.8(3) to 3.6 V 3. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). ±2 ±5 LSB EO Offset error ±1.5 ±2.5 EG Gain error ±1.5 ±3 ED Differential linearity error ±1 ±2 EL Integral linearity error ±1.5 ±3 ai14395c EO EG 1L SBIDEAL 4095 4094 4093 5 4 3 2 1 0 7 6 1 2 3 456 7 4093 4094 4095 4096 (1) (2) ET ED EL (3) VSSA VDDA VREF+ 4096 (or depending on package)] VDDA 4096 [1LSB IDEAL = Electrical characteristics STM32F405xx, STM32F407xx 132/185 DocID022152 Rev 4 EG = Gain Error: deviation between the last ideal transition and the last actual one. ED = Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL = Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. Figure 51. Typical connection diagram using the ADC 1. Refer to Table 67 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 5 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. ai17534 VDD STM32F AINx IL±1 μA 0.6 V VT RAIN (1) Cparasitic VAIN 0.6 V VT RADC (1) CADC(1) 12-bit converter Sample and hold ADC converter DocID022152 Rev 4 133/185 STM32F405xx, STM32F407xx Electrical characteristics General PCB design guidelines Power supply decoupling should be performed as shown in Figure 52 or Figure 53, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 52. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ and VREF– inputs are both available on UFBGA176. VREF+ is also available on LQFP100, LQFP144, and LQFP176. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. Figure 53. Power supply and reference decoupling (VREF+ connected to VDDA) 1. VREF+ and VREF– inputs are both available on UFBGA176. VREF+ is also available on LQFP100, LQFP144, and LQFP176. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. VREF+ STM32F VDDA VSSA/V REF- 1 μF // 10 nF 1 μF // 10 nF ai17535 (See note 1) (See note 1) VREF+/VDDA STM32F 1 μF // 10 nF VREF–/VSSA ai17536 (See note 1) (See note 1) Electrical characteristics STM32F405xx, STM32F407xx 134/185 DocID022152 Rev 4 5.3.21 Temperature sensor characteristics 5.3.22 VBAT monitoring characteristics Table 69. Temperature sensor characteristics Symbol Parameter Min Typ Max Unit TL (1) VSENSE linearity with temperature - ±1 ±2 °C Avg_Slope(1) Average slope - 2.5 mV/°C V25 (1) Voltage at 25 °C - 0.76 V tSTART (2) Startup time - 6 10 μs TS_temp (3)(2) ADC sampling time when reading the temperature (1 °C accuracy) 10 - - μs 1. Based on characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. Shortest sampling time can be determined in the application by multiple iterations. Table 70. Temperature sensor calibration values Symbol Parameter Memory address TS_CAL1 TS ADC raw data acquired at temperature of 30 °C, VDDA=3.3 V 0x1FFF 7A2C - 0x1FFF 7A2D TS_CAL2 TS ADC raw data acquired at temperature of 110 °C, VDDA=3.3 V 0x1FFF 7A2E - 0x1FFF 7A2F Table 71. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 50 - KΩ Q Ratio on VBAT measurement - 2 - Er(1) Error on Q –1 - +1 % TS_vbat (2)(2) ADC sampling time when reading the VBAT 1 mV accuracy 5 - - μs 1. Guaranteed by design, not tested in production. 2. Shortest sampling time can be determined in the application by multiple iterations. DocID022152 Rev 4 135/185 STM32F405xx, STM32F407xx Electrical characteristics 5.3.23 Embedded reference voltage The parameters given in Table 72 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. 5.3.24 DAC electrical characteristics Table 72. Embedded internal reference voltage Symbol Parameter Conditions Min Typ Max Unit VREFINT Internal reference voltage –40 °C < TA < +105 °C 1.18 1.21 1.24 V TS_vrefint (1) ADC sampling time when reading the internal reference voltage 10 - - μs VRERINT_s (2) Internal reference voltage spread over the temperature range VDD = 3 V - 3 5 mV TCoeff (2) Temperature coefficient - 30 50 ppm/°C tSTART (2) Startup time - 6 10 μs 1. Shortest sampling time can be determined in the application by multiple iterations. 2. Guaranteed by design, not tested in production. Table 73. Internal reference voltage calibration values Symbol Parameter Memory address VREFIN_CAL Raw data acquired at temperature of 30 °C, VDDA=3.3 V 0x1FFF 7A2A - 0x1FFF 7A2B Table 74. DAC characteristics Symbol Parameter Min Typ Max Unit Comments VDDA Analog supply voltage 1.8(1) - 3.6 V VREF+ Reference supply voltage 1.8(1) - 3.6 V VREF+ ≤ VDDA VSSA Ground 0 - 0 V RLOAD (2) Resistive load with buffer ON 5 - - kΩ RO (2) Impedance output with buffer OFF - - 15 kΩ When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 MΩ CLOAD (2) Capacitive load - - 50 pF Maximum capacitive load at DAC_OUT pin (when the buffer is ON). DAC_OUT min(2) Lower DAC_OUT voltage with buffer ON 0.2 - - V It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x1C7) to (0xE38) at VREF+ = 1.8 V DAC_OUT max(2) Higher DAC_OUT voltage with buffer ON - - VDDA – 0.2 V Electrical characteristics STM32F405xx, STM32F407xx 136/185 DocID022152 Rev 4 DAC_OUT min(2) Lower DAC_OUT voltage with buffer OFF - 0.5 - mV It gives the maximum output DAC_OUT excursion of the DAC. max(2) Higher DAC_OUT voltage with buffer OFF - - VREF+ – 1LSB V IVREF+ (4) DAC DC VREF current consumption in quiescent mode (Standby mode) - 170 240 μA With no load, worst code (0x800) at VREF+ = 3.6 V in terms of DC consumption on the inputs - 50 75 With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs IDDA (4) DAC DC VDDA current consumption in quiescent mode(3) - 280 380 μA With no load, middle code (0x800) on the inputs - 475 625 μA With no load, worst code (0xF1C) at VREF+ = 3.6 V in terms of DC consumption on the inputs DNL(4) Differential non linearity Difference between two consecutive code-1LSB) - - ±0.5 LSB Given for the DAC in 10-bit configuration. - - ±2 LSB Given for the DAC in 12-bit configuration. INL(4) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) - - ±1 LSB Given for the DAC in 10-bit configuration. - - ±4 LSB Given for the DAC in 12-bit configuration. Offset(4) Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) - - ±10 mV Given for the DAC in 12-bit configuration - - ±3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V - - ±12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V Gain error(4) Gain error - - ±0.5 % Given for the DAC in 12-bit configuration tSETTLING (4) Settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when DAC_OUT reaches final value ±4LSB - 3 6 μs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ THD(4) Total Harmonic Distortion Buffer ON - - - dB CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ Table 74. DAC characteristics (continued) Symbol Parameter Min Typ Max Unit Comments DocID022152 Rev 4 137/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 54. 12-bit buffered /non-buffered DAC 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 5.3.25 FSMC characteristics Unless otherwise specified, the parameters given in Table 75 to Table 86 for the FSMC interface are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 14, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section Section 5.3.16: I/O port characteristics for more details on the input/output characteristics. Update rate(2) Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) - - 1 MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ tWAKEUP (4) Wakeup time from off state (Setting the ENx bit in the DAC Control register) - 6.5 10 μs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ input code between lowest and highest possible ones. PSRR+ (2) Power supply rejection ratio (to VDDA) (static DC measurement) - –67 –40 dB No RLOAD, CLOAD = 50 pF 1. VDD/VDDA minimum value of 1.7 V is obtained when the device operates in reduced temperature range, and with the use of an external power supply supervisor (refer to Section : Internal reset OFF). 2. Guaranteed by design, not tested in production. 3. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic consumption occurs. 4. Guaranteed by characterization, not tested in production. Table 74. DAC characteristics (continued) Symbol Parameter Min Typ Max Unit Comments RLOAD CLOAD Buffered/Non-buffered DAC DACx_OUT Buffer(1) 12-bit digital to analog converter ai17157 Electrical characteristics STM32F405xx, STM32F407xx 138/185 DocID022152 Rev 4 Asynchronous waveforms and timings Figure 55 through Figure 58 represent asynchronous waveforms and Table 75 through Table 78 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: • AddressSetupTime = 1 • AddressHoldTime = 0x1 • DataSetupTime = 0x1 • BusTurnAroundDuration = 0x0 In all timing tables, the THCLK is the HCLK clock period. Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 2THCLK–0.5 2 THCLK+1 ns tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 0.5 3 ns tw(NOE) FSMC_NOE low time 2THCLK–2 2THCLK+ 2 ns th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time 0 - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 4.5 ns th(A_NOE) Address hold time after FSMC_NOE high 4 - ns Data FSMC_NE FSMC_NBL[1:0] FSMC_D[15:0] tv(BL_NE) t h(Data_NE) FSMC_NOE FSMC_A[25:0] Address tv(A_NE) FSMC_NWE tsu(Data_NE) tw(NE) ai14991c tv(NOE_NE) t w(NOE) t h(NE_NOE) th(Data_NOE) t h(A_NOE) t h(BL_NOE) tsu(Data_NOE) FSMC_NADV(1) t v(NADV_NE) tw(NADV) DocID022152 Rev 4 139/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 56. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 1.5 ns th(BL_NOE) FSMC_BL hold time after FSMC_NOE high 0 - ns tsu(Data_NE) Data to FSMC_NEx high setup time THCLK+4 - ns tsu(Data_NOE) Data to FSMC_NOEx high setup time THCLK+4 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns th(Data_NE) Data hold time after FSMC_NEx high 0 - ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 2 ns tw(NADV) FSMC_NADV low time - THCLK ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 3THCLK 3THCLK+ 4 ns tv(NWE_NE) FSMC_NEx low to FSMC_NWE low THCLK–0.5 THCLK+0.5 ns tw(NWE) FSMC_NWE low time THCLK–1 THCLK+2 ns th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time THCLK–1 - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 0 ns Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2) NBL Data FSMC_NEx FSMC_NBL[1:0] FSMC_D[15:0] tv(BL_NE) th(Data_NWE) FSMC_NOE FSMC_A[25:0] Address tv(A_NE) tw(NWE) FSMC_NWE tv(NWE_NE) t h(NE_NWE) th(A_NWE) th(BL_NWE) tv(Data_NE) tw(NE) ai14990 FSMC_NADV(1) t v(NADV_NE) tw(NADV) Electrical characteristics STM32F405xx, STM32F407xx 140/185 DocID022152 Rev 4 Figure 57. Asynchronous multiplexed PSRAM/NOR read waveforms th(A_NWE) Address hold time after FSMC_NWE high THCLK– 2 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 1.5 ns th(BL_NWE) FSMC_BL hold time after FSMC_NWE high THCLK– 1 - ns tv(Data_NE) Data to FSMC_NEx low to Data valid - THCLK+3 ns th(Data_NWE) Data hold time after FSMC_NWE high THCLK–1 - ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 2 ns tw(NADV) FSMC_NADV low time - THCLK+0.5 ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 77. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 3THCLK–1 3THCLK+1 ns tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 2THCLK–0.5 2THCLK+0.5 ns tw(NOE) FSMC_NOE low time THCLK–1 THCLK+1 ns th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time 0 - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 3 ns Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) NBL Data FSMC_NBL[1:0] FSMC_AD[15:0] tv(BL_NE) th(Data_NE) FSMC_A[25:16] Address tv(A_NE) FSMC_NWE t v(A_NE) ai14892b Address FSMC_NADV t v(NADV_NE) tw(NADV) tsu(Data_NE) th(AD_NADV) FSMC_NE FSMC_NOE tw(NE) t w(NOE) tv(NOE_NE) t h(NE_NOE) th(A_NOE) th(BL_NOE) tsu(Data_NOE) th(Data_NOE) DocID022152 Rev 4 141/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 1 2 ns tw(NADV) FSMC_NADV low time THCLK– 2 THCLK+1 ns th(AD_NADV) FSMC_AD(adress) valid hold time after FSMC_NADV high) THCLK - ns th(A_NOE) Address hold time after FSMC_NOE high THCLK–1 - ns th(BL_NOE) FSMC_BL time after FSMC_NOE high 0 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 2 ns tsu(Data_NE) Data to FSMC_NEx high setup time THCLK+4 - ns tsu(Data_NOE) Data to FSMC_NOE high setup time THCLK+4 - ns th(Data_NE) Data hold time after FSMC_NEx high 0 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 78. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 4THCLK–0.5 4THCLK+3 ns tv(NWE_NE) FSMC_NEx low to FSMC_NWE low THCLK–0.5 THCLK -0.5 ns tw(NWE) FSMC_NWE low tim e 2THCLK–0.5 2THCLK+3 ns Table 77. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) (continued) NBL Data FSMC_NEx FSMC_NBL[1:0] FSMC_AD[15:0] tv(BL_NE) th(Data_NWE) FSMC_NOE FSMC_A[25:16] Address tv(A_NE) tw(NWE) FSMC_NWE tv(NWE_NE) t h(NE_NWE) th(A_NWE) th(BL_NWE) t v(A_NE) tw(NE) ai14891B Address FSMC_NADV t v(NADV_NE) tw(NADV) t v(Data_NADV) th(AD_NADV) Electrical characteristics STM32F405xx, STM32F407xx 142/185 DocID022152 Rev 4 Synchronous waveforms and timings Figure 59 through Figure 62 represent synchronous waveforms and Table 80 through Table 82 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: • BurstAccessMode = FSMC_BurstAccessMode_Enable; • MemoryType = FSMC_MemoryType_CRAM; • WriteBurst = FSMC_WriteBurst_Enable; • CLKDivision = 1; (0 is not supported, see the STM32F40xxx/41xxx reference manual) • DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM In all timing tables, the THCLK is the HCLK clock period (with maximum FSMC_CLK = 60 MHz). th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time THCLK - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 0 ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 1 2 ns tw(NADV) FSMC_NADV low time THCLK– 2 THCLK+ 1 ns th(AD_NADV) FSMC_AD(address) valid hold time after FSMC_NADV high) THCLK–2 - ns th(A_NWE) Address hold time after FSMC_NWE high THCLK - ns th(BL_NWE) FSMC_BL hold time after FSMC_NWE high THCLK–2 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 1.5 ns tv(Data_NADV) FSMC_NADV high to Data valid - THCLK–0.5 ns th(Data_NWE) Data hold time after FSMC_NWE high THCLK - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 78. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) DocID022152 Rev 4 143/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 59. Synchronous multiplexed NOR/PSRAM read timings Table 79. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period 2THCLK - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 0 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 2 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 2 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 2 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 0 - ns td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - 0 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 2 - ns td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid - 4.5 ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns tsu(ADV-CLKH) FSMC_A/D[15:0] valid data before FSMC_CLK high 6 - ns FSMC_CLK FSMC_NEx FSMC_NADV FSMC_A[25:16] FSMC_NOE FSMC_AD[15:0] AD[15:0] D1 D2 FSMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tw(CLK) tw(CLK) Data latency = 0 BUSTURN = 0 td(CLKL-NExL) td(CLKL-NExH) td(CLKL-NADVL) td(CLKL-AV) td(CLKL-NADVH) td(CLKL-AIV) td(CLKL-NOEL) td(CLKL-NOEH) td(CLKL-ADV) td(CLKL-ADIV) tsu(ADV-CLKH) th(CLKH-ADV) tsu(ADV-CLKH) th(CLKH-ADV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14893g Electrical characteristics STM32F405xx, STM32F407xx 144/185 DocID022152 Rev 4 Figure 60. Synchronous multiplexed PSRAM write timings th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high 0 - ns tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 4 - ns th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 0 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 80. Synchronous multiplexed PSRAM write timings(1)(2) Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period 2THCLK - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 1 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 0 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 0 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns Table 79. Synchronous multiplexed NOR/PSRAM read timings(1)(2) (continued) FSMC_CLK FSMC_NEx FSMC_NADV FSMC_A[25:16] FSMC_NWE FSMC_AD[15:0] AD[15:0] D1 D2 FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tw(CLK) tw(CLK) Data latency = 0 BUSTURN = 0 td(CLKL-NExL) td(CLKL-NExH) td(CLKL-NADVL) td(CLKL-AV) td(CLKL-NADVH) td(CLKL-AIV) td(CLKL-NWEL) td(CLKL-NWEH) td(CLKL-NBLH) td(CLKL-ADV) td(CLKL-ADIV) td(CLKL-Data) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14992g td(CLKL-Data) FSMC_NBL DocID022152 Rev 4 145/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 61. Synchronous non-multiplexed NOR/PSRAM read timings td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 8 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 0.5 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 0 - ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns td(CLKL-DATA) FSMC_A/D[15:0] valid data after FSMC_CLK low - 3 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 0 - ns tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 4 - ns th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 0 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 81. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period 2THCLK –0.5 - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 0.5 ns Table 80. Synchronous multiplexed PSRAM write timings(1)(2) FSMC_CLK FSMC_NEx FSMC_A[25:0] FSMC_NOE FSMC_D[15:0] D1 D2 FSMC_NWAIT (WAITCFG = 1b, WAITPOL + 0b) FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tw(CLK) tw(CLK) Data latency = 0 BUSTURN = 0 td(CLKL-NExL) td(CLKL-NExH) td(CLKL-AV) td(CLKL-AIV) td(CLKL-NOEL) td(CLKL-NOEH) tsu(DV-CLKH) th(CLKH-DV) tsu(DV-CLKH) th(CLKH-DV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) tsu(NWAITV-CLKH) t h(CLKH-NWAITV) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14894f FSMC_NADV td(CLKL-NADVL) td(CLKL-NADVH) Electrical characteristics STM32F405xx, STM32F407xx 146/185 DocID022152 Rev 4 Figure 62. Synchronous non-multiplexed PSRAM write timings td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 0 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 2 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 3 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 2 - ns td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - 0.5 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 1.5 - ns tsu(DV-CLKH) FSMC_D[15:0] valid data before FSMC_CLK high 6 - ns th(CLKH-DV) FSMC_D[15:0] valid data after FSMC_CLK high 3 - ns tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 4 - ns th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 0 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Table 81. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) (continued) FSMC_CLK FSMC_NEx FSMC_A[25:0] FSMC_NWE FSMC_D[15:0] D1 D2 FSMC_NWAIT (WAITCFG = 0b, WAITPOL + 0b) tw(CLK) tw(CLK) Data latency = 0 BUSTURN = 0 td(CLKL-NExL) td(CLKL-NExH) td(CLKL-AV) td(CLKL-AIV) td(CLKL-NWEL) td(CLKL-NWEH) td(CLKL-Data) tsu(NWAITV-CLKH) th(CLKH-NWAITV) ai14993g FSMC_NADV td(CLKL-NADVL) td(CLKL-NADVH) td(CLKL-Data) FSMC_NBL td(CLKL-NBLH) DocID022152 Rev 4 147/185 STM32F405xx, STM32F407xx Electrical characteristics PC Card/CompactFlash controller waveforms and timings Figure 63 through Figure 68 represent synchronous waveforms, and Table 83 and Table 84 provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: • COM.FSMC_SetupTime = 0x04; • COM.FSMC_WaitSetupTime = 0x07; • COM.FSMC_HoldSetupTime = 0x04; • COM.FSMC_HiZSetupTime = 0x00; • ATT.FSMC_SetupTime = 0x04; • ATT.FSMC_WaitSetupTime = 0x07; • ATT.FSMC_HoldSetupTime = 0x04; • ATT.FSMC_HiZSetupTime = 0x00; • IO.FSMC_SetupTime = 0x04; • IO.FSMC_WaitSetupTime = 0x07; • IO.FSMC_HoldSetupTime = 0x04; • IO.FSMC_HiZSetupTime = 0x00; • TCLRSetupTime = 0; • TARSetupTime = 0. In all timing tables, the THCLK is the HCLK clock period. Table 82. Synchronous non-multiplexed PSRAM write timings(1)(2) 1. CL = 30 pF. 2. Based on characterization, not tested in production. Symbol Parameter Min Max Unit tw(CLK) FSMC_CLK period 2THCLK - ns td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2) - 1 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 7 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 6 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 6 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 2 - ns td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low - 3 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 3 - ns tsu(NWAIT-CLKH) FSMC_NWAIT valid before FSMC_CLK high 4 - ns th(CLKH-NWAIT) FSMC_NWAIT valid after FSMC_CLK high 0 - ns Electrical characteristics STM32F405xx, STM32F407xx 148/185 DocID022152 Rev 4 Figure 63. PC Card/CompactFlash controller waveforms for common memory read access 1. FSMC_NCE4_2 remains high (inactive during 8-bit access. Figure 64. PC Card/CompactFlash controller waveforms for common memory write access FSMC_NWE tw(NOE) FSMC_NOE FSMC_D[15:0] FSMC_A[10:0] FSMC_NCE4_2(1) FSMC_NCE4_1 FSMC_NREG FSMC_NIOWR FSMC_NIORD td(NCE4_1-NOE) tsu(D-NOE) th(NOE-D) tv(NCEx-A) td(NREG-NCEx) td(NIORD-NCEx) th(NCEx-AI) th(NCEx-NREG) th(NCEx-NIORD) th(NCEx-NIOWR) ai14895b td(NCE4_1-NWE) tw(NWE) th(NWE-D) tv(NCE4_1-A) td(NREG-NCE4_1) td(NIORD-NCE4_1) th(NCE4_1-AI) MEMxHIZ =1 tv(NWE-D) th(NCE4_1-NREG) th(NCE4_1-NIORD) th(NCE4_1-NIOWR) ai14896b FSMC_NWE FSMC_NOE FSMC_D[15:0] FSMC_A[10:0] FSMC_NCE4_1 FSMC_NREG FSMC_NIOWR FSMC_NIORD td(NWE-NCE4_1) td(D-NWE) FSMC_NCE4_2 High DocID022152 Rev 4 149/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 65. PC Card/CompactFlash controller waveforms for attribute memory read access 1. Only data bits 0...7 are read (bits 8...15 are disregarded). td(NCE4_1-NOE) tw(NOE) tsu(D-NOE) th(NOE-D) tv(NCE4_1-A) th(NCE4_1-AI) td(NREG-NCE4_1) th(NCE4_1-NREG) ai14897b FSMC_NWE FSMC_NOE FSMC_D[15:0](1) FSMC_A[10:0] FSMC_NCE4_2 FSMC_NCE4_1 FSMC_NREG FSMC_NIOWR FSMC_NIORD td(NOE-NCE4_1) High Electrical characteristics STM32F405xx, STM32F407xx 150/185 DocID022152 Rev 4 Figure 66. PC Card/CompactFlash controller waveforms for attribute memory write access 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). Figure 67. PC Card/CompactFlash controller waveforms for I/O space read access tw(NWE) tv(NCE4_1-A) td(NREG-NCE4_1) th(NCE4_1-AI) th(NCE4_1-NREG) tv(NWE-D) ai14898b FSMC_NWE FSMC_NOE FSMC_D[7:0](1) FSMC_A[10:0] FSMC_NCE4_2 FSMC_NCE4_1 FSMC_NREG FSMC_NIOWR FSMC_NIORD td(NWE-NCE4_1) High td(NCE4_1-NWE) td(NIORD-NCE4_1) tw(NIORD) tsu(D-NIORD) td(NIORD-D) tv(NCEx-A) th(NCE4_1-AI) ai14899B FSMC_NWE FSMC_NOE FSMC_D[15:0] FSMC_A[10:0] FSMC_NCE4_2 FSMC_NCE4_1 FSMC_NREG FSMC_NIOWR FSMC_NIORD DocID022152 Rev 4 151/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 68. PC Card/CompactFlash controller waveforms for I/O space write access td(NCE4_1-NIOWR) tw(NIOWR) tv(NCEx-A) th(NCE4_1-AI) th(NIOWR-D) ATTxHIZ =1 tv(NIOWR-D) ai14900c FSMC_NWE FSMC_NOE FSMC_D[15:0] FSMC_A[10:0] FSMC_NCE4_2 FSMC_NCE4_1 FSMC_NREG FSMC_NIOWR FSMC_NIORD Table 83. Switching characteristics for PC Card/CF read and write cycles in attribute/common space(1)(2) Symbol Parameter Min Max Unit tv(NCEx-A) FSMC_Ncex low to FSMC_Ay valid - 0 ns th(NCEx_AI) FSMC_NCEx high to FSMC_Ax invalid 4 - ns td(NREG-NCEx) FSMC_NCEx low to FSMC_NREG valid - 3.5 ns th(NCEx-NREG) FSMC_NCEx high to FSMC_NREG invalid THCLK+4 - ns td(NCEx-NWE) FSMC_NCEx low to FSMC_NWE low - 5THCLK+0.5 ns td(NCEx-NOE) FSMC_NCEx low to FSMC_NOE low - 5THCLK +0.5 ns tw(NOE) FSMC_NOE low width 8THCLK–1 8THCLK+1 ns td(NOE_NCEx) FSMC_NOE high to FSMC_NCEx high 5THCLK+2.5 - ns tsu (D-NOE) FSMC_D[15:0] valid data before FSMC_NOE high 4.5 - ns th(N0E-D) FSMC_N0E high to FSMC_D[15:0] invalid 3 - ns tw(NWE) FSMC_NWE low width 8THCLK–0.5 8THCLK+ 3 ns td(NWE_NCEx) FSMC_NWE high to FSMC_NCEx high 5THCLK–1 - ns td(NCEx-NWE) FSMC_NCEx low to FSMC_NWE low - 5THCLK+ 1 ns tv(NWE-D) FSMC_NWE low to FSMC_D[15:0] valid - 0 ns th (NWE-D) FSMC_NWE high to FSMC_D[15:0] invalid 8THCLK –1 - ns td (D-NWE) FSMC_D[15:0] valid before FSMC_NWE high 13THCLK –1 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. Electrical characteristics STM32F405xx, STM32F407xx 152/185 DocID022152 Rev 4 NAND controller waveforms and timings Figure 69 through Figure 72 represent synchronous waveforms, and Table 85 and Table 86 provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: • COM.FSMC_SetupTime = 0x01; • COM.FSMC_WaitSetupTime = 0x03; • COM.FSMC_HoldSetupTime = 0x02; • COM.FSMC_HiZSetupTime = 0x01; • ATT.FSMC_SetupTime = 0x01; • ATT.FSMC_WaitSetupTime = 0x03; • ATT.FSMC_HoldSetupTime = 0x02; • ATT.FSMC_HiZSetupTime = 0x01; • Bank = FSMC_Bank_NAND; • MemoryDataWidth = FSMC_MemoryDataWidth_16b; • ECC = FSMC_ECC_Enable; • ECCPageSize = FSMC_ECCPageSize_512Bytes; • TCLRSetupTime = 0; • TARSetupTime = 0. In all timing tables, the THCLK is the HCLK clock period. Table 84. Switching characteristics for PC Card/CF read and write cycles in I/O space(1)(2) Symbol Parameter Min Max Unit tw(NIOWR) FSMC_NIOWR low width 8THCLK –1 - ns tv(NIOWR-D) FSMC_NIOWR low to FSMC_D[15:0] valid - 5THCLK– 1 ns th(NIOWR-D) FSMC_NIOWR high to FSMC_D[15:0] invalid 8THCLK– 2 - ns td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid - 5THCLK+ 2.5 ns th(NCEx-NIOWR) FSMC_NCEx high to FSMC_NIOWR invalid 5THCLK–1.5 - ns td(NIORD-NCEx) FSMC_NCEx low to FSMC_NIORD valid - 5THCLK+ 2 ns th(NCEx-NIORD) FSMC_NCEx high to FSMC_NIORD) valid 5THCLK– 1.5 - ns tw(NIORD) FSMC_NIORD low width 8THCLK–0.5 - ns tsu(D-NIORD) FSMC_D[15:0] valid before FSMC_NIORD high 9 - ns td(NIORD-D) FSMC_D[15:0] valid after FSMC_NIORD high 0 - ns 1. CL = 30 pF. 2. Based on characterization, not tested in production. DocID022152 Rev 4 153/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 69. NAND controller waveforms for read access Figure 70. NAND controller waveforms for write access FSMC_NWE FSMC_NOE (NRE) FSMC_D[15:0] tsu(D-NOE) th(NOE-D) ai14901c ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NCEx td(ALE-NOE) th(NOE-ALE) tv(NWE-D) th(NWE-D) ai14902c FSMC_NWE FSMC_NOE (NRE) FSMC_D[15:0] ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NCEx td(ALE-NWE) th(NWE-ALE) Electrical characteristics STM32F405xx, STM32F407xx 154/185 DocID022152 Rev 4 Figure 71. NAND controller waveforms for common memory read access Figure 72. NAND controller waveforms for common memory write access Table 85. Switching characteristics for NAND Flash read cycles(1) 1. CL = 30 pF. Symbol Parameter Min Max Unit tw(N0E) FSMC_NOE low width 4THCLK– 0.5 4THCLK+ 3 ns tsu(D-NOE) FSMC_D[15-0] valid data before FSMC_NOE high 10 - ns th(NOE-D) FSMC_D[15-0] valid data after FSMC_NOE high 0 - ns td(ALE-NOE) FSMC_ALE valid before FSMC_NOE low - 3THCLK ns th(NOE-ALE) FSMC_NWE high to FSMC_ALE invalid 3THCLK– 2 - ns FSMC_NWE FSMC_NOE FSMC_D[15:0] tw(NOE) tsu(D-NOE) th(NOE-D) ai14912c ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NCEx td(ALE-NOE) th(NOE-ALE) tw(NWE) tv(NWE-D) th(NWE-D) ai14913c FSMC_NWE FSMC_NOE FSMC_D[15:0] td(D-NWE) ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NCEx td(ALE-NOE) th(NOE-ALE) DocID022152 Rev 4 155/185 STM32F405xx, STM32F407xx Electrical characteristics 5.3.26 Camera interface (DCMI) timing specifications Unless otherwise specified, the parameters given in Table 87 for DCMI are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 13, with the following configuration: • PCK polarity: falling • VSYNC and HSYNC polarity: high • Data format: 14 bits Figure 73. DCMI timing diagram Table 86. Switching characteristics for NAND Flash write cycles(1) 1. CL = 30 pF. Symbol Parameter Min Max Unit tw(NWE) FSMC_NWE low width 4THCLK–1 4THCLK+ 3 ns tv(NWE-D) FSMC_NWE low to FSMC_D[15-0] valid - 0 ns th(NWE-D) FSMC_NWE high to FSMC_D[15-0] invalid 3THCLK –2 - ns td(D-NWE) FSMC_D[15-0] valid before FSMC_NWE high 5THCLK–3 - ns td(ALE-NWE) FSMC_ALE valid before FSMC_NWE low - 3THCLK ns th(NWE-ALE) FSMC_NWE high to FSMC_ALE invalid 3THCLK–2 - ns Table 87. DCMI characteristics(1) Symbol Parameter Min Max Unit Frequency ratio DCMI_PIXCLK/fHCLK - 0.4 DCMI_PIXCLK Pixel clock input - 54 MHz Dpixel Pixel clock input duty cycle 30 70 % MS32414V1 Pixel clock tsu(VSYNC) tsu(HSYNC) HSYNC VSYNC DATA[0:13] 1/DCMI_PIXCLK th(HSYNC) th(HSYNC) tsu(DATA) th(DATA) Electrical characteristics STM32F405xx, STM32F407xx 156/185 DocID022152 Rev 4 5.3.27 SD/SDIO MMC card host interface (SDIO) characteristics Unless otherwise specified, the parameters given in Table 88 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14 with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5VDD Refer to Section 5.3.16: I/O port characteristics for more details on the input/output characteristics. Figure 74. SDIO high-speed mode tsu(DATA) Data input setup time 2.5 - ns th(DATA) Data hold time 1 - tsu(HSYNC), tsu(VSYNC) HSYNC/VSYNC input setup time 2 - th(HSYNC), th(VSYNC) HSYNC/VSYNC input hold time 0.5 - 1. Data based on characterization results, not tested in production. Table 87. DCMI characteristics(1) (continued) Symbol Parameter Min Max Unit tW(CKH) CK D, CMD (output) D, CMD (input) tC tW(CKL) tOV tOH tISU tIH tf tr ai14887 DocID022152 Rev 4 157/185 STM32F405xx, STM32F407xx Electrical characteristics Figure 75. SD default mode 5.3.28 RTC characteristics CK D, CMD (output) tOVD tOHD ai14888 Table 88. Dynamic characteristics: SD / MMC characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fPP Clock frequency in data transfer mode 0 48 MHz SDIO_CK/fPCLK2 frequency ratio - - 8/3 - tW(CKL) Clock low time fpp = 48 MHz 8.5 9 - ns tW(CKH) Clock high time fpp = 48 MHz 8.3 10 - CMD, D inputs (referenced to CK) in MMC and SD HS mode tISU Input setup time HS fpp = 48 MHz 3 - - ns tIH Input hold time HS fpp = 48 MHz 0 - - CMD, D outputs (referenced to CK) in MMC and SD HS mode tOV Output valid time HS fpp = 48 MHz - 4.5 6 ns tOH Output hold time HS fpp = 48 MHz 1 - - CMD, D inputs (referenced to CK) in SD default mode tISUD Input setup time SD fpp = 24 MHz 1.5 - - ns tIHD Input hold time SD fpp = 24 MHz 0.5 - - CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time SD fpp = 24 MHz - 4.5 7 ns tOHD Output hold default time SD fpp = 24 MHz 0.5 - - 1. Data based on characterization results, not tested in production. Table 89. RTC characteristics Symbol Parameter Conditions Min Max - fPCLK1/RTCCLK frequency ratio Any read/write operation from/to an RTC register 4 - Package characteristics STM32F405xx, STM32F407xx 158/185 DocID022152 Rev 4 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID022152 Rev 4 159/185 STM32F405xx, STM32F407xx Package characteristics Figure 76. WLCSP90 - 0.400 mm pitch wafer level chip size package outline Bump side Side view Detail A Wafer back side A1 ball location A1 Detail A rotated by 90 °C eee D A0JW_ME Seating plane A2 A b E e e1 e G F e2 Table 90. WLCSP90 - 0.400 mm pitch wafer level chip size package mechanical data Symbol millimeters inches(1) Min Typ Max Min Typ Max A 0.520 0.570 0.620 0.0205 0.0224 0.0244 A1 0.165 0.190 0.215 0.0065 0.0075 0.0085 A2 0.350 0.380 0.410 0.0138 0.015 0.0161 b 0.240 0.270 0.300 0.0094 0.0106 0.0118 D 4.178 4.218 4.258 0.1645 0.1661 0.1676 E 3.964 3.969 4.004 0.1561 0.1563 0.1576 e 0.400 0.0157 e1 3.600 0.1417 e2 3.200 0.126 F 0.312 0.0123 G 0.385 0.0152 eee 0.050 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Package characteristics STM32F405xx, STM32F407xx 160/185 DocID022152 Rev 4 Figure 77. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline 1. Drawing is not to scale. ai14398b A A2 A1 c L1 L E E1 D D1 e b Table 91. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data Symbol millimeters inches(1) Min Typ Max Min Typ Max A 1.600 0.0630 A1 0.050 0.150 0.0020 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 D 12.000 0.4724 D1 10.000 0.3937 E 12.000 0.4724 E1 10.000 0.3937 e 0.500 0.0197 θ 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 1.000 0.0394 N Number of pins 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. DocID022152 Rev 4 161/185 STM32F405xx, STM32F407xx Package characteristics Figure 78. LQFP64 recommended footprint 1. Drawing is not to scale. 2. Dimensions are in millimeters. 48 49 32 64 17 1 16 1.2 0.3 33 10.3 12.7 10.3 0.5 7.8 12.7 ai14909 Package characteristics STM32F405xx, STM32F407xx 162/185 DocID022152 Rev 4 Figure 79. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline 1. Drawing is not to scale. IDENTIFICATION e PIN 1 GAUGE PLANE 0.25 mm SEATING PLANE D D1 D3 E3 E1 E K ccc C C 1 25 100 26 76 75 51 50 1L_ME_V4 A2 A A1 L1 L c b A1 Table 92. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data(1) Symbol millimeters inches Min Typ Max Min Typ Max A 1.600 0.0630 A1 0.050 0.150 0.0020 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 12.000 0.4724 E 15.80v 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 12.000 0.4724 e 0.500 0.0197 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 1.000 0.0394 k 0° 3.5° 7° 0° 3.5° 7° ccc 0.080 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. DocID022152 Rev 4 163/185 STM32F405xx, STM32F407xx Package characteristics Figure 80. LQFP100 recommended footprint 1. Drawing is not to scale. 2. Dimensions are in millimeters. 75 51 76 50 0.5 0.3 16.7 14.3 100 26 12.3 25 1.2 16.7 1 ai14906 Package characteristics STM32F405xx, STM32F407xx 164/185 DocID022152 Rev 4 Figure 81. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline 1. Drawing is not to scale. D1 D3 D E3 E1 E e Pin 1 identification 73 72 37 36 109 144 108 1 A A2A1 b c A1 L L1 k Seating plane C ccc C 0.25 mm gage plane ME_1A Table 93. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data Symbol millimeters inches(1) Min Typ Max Min Typ Max A 1.600 0.0630 A1 0.050 0.150 0.0020 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.874 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 17.500 0.689 E 21.800 22.000 22.200 0.8583 0.8661 0.8740 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 17.500 0.6890 e 0.500 0.0197 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 1.000 0.0394 DocID022152 Rev 4 165/185 STM32F405xx, STM32F407xx Package characteristics Figure 82. LQFP144 recommended footprint 1. Drawing is not to scale. 2. Dimensions are in millimeters. k 0° 3.5° 7° 0° 3.5° 7° ccc 0.080 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Table 93. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data Symbol millimeters inches(1) Min Typ Max Min Typ Max ai14905c 0.5 0.35 19.9 17.85 22.6 1.35 22.6 19.9 1 36 37 72 108 73 109 144 Package characteristics STM32F405xx, STM32F407xx 166/185 DocID022152 Rev 4 Figure 83. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline 1. Drawing is not to scale. Table 94. UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data Symbol millimeters inches(1) 1. Values in inches are converted from mm and rounded to 4 decimal digits. Min Typ Max Min Typ Max A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.002 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 b 0.230 0.280 0.330 0.0091 0.0110 0.0130 D 9.900 10.000 10.100 0.3898 0.3937 0.3976 E 9.900 10.000 10.100 0.3898 0.3937 0.3976 e 0.650 0.0256 F 0.425 0.450 0.475 0.0167 0.0177 0.0187 ddd 0.080 0.0031 eee 0.150 0.0059 fff 0.080 0.0031 A0E7_ME_V4 Seating plane A2 ddd C A1 A e F F e R A 15 1 BOTTOM VIEW E D TOP VIEW Øb (176 + 25 balls) B A Ø eee M B Ø fff M C C A C A1 ball identifier A1 ball index area DocID022152 Rev 4 167/185 STM32F405xx, STM32F407xx Package characteristics Figure 84. LQFP176 24 x 24 mm, 176-pin low-profile quad flat package outline 1. Drawing is not to scale. ccc C C Seating plane A A2 A1 c 0.25 mm gauge plane HD D A1 L L1 k 89 88 E HE 45 44 e 1 176 Pin 1 identification b 133 132 1T_ME ZD ZE Table 95. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data Symbol millimeters inches(1) Min Typ Max Min Typ Max A 1.600 0.0630 A1 0.050 0.150 0.0020 A2 1.350 1.450 0.0531 0.0060 b 0.170 0.270 0.0067 0.0106 C 0.090 0.200 0.0035 0.0079 D 23.900 24.100 0.9409 0.9488 E 23.900 24.100 0.9409 0.9488 e 0.500 0.0197 HD 25.900 26.100 1.0200 1.0276 HE 25.900 26.100 1.0200 1.0276 L 0.450 0.750 0.0177 0.0295 L1 1.000 0.0394 ZD 1.250 0.0492 ZE 1.250 0.0492 Package characteristics STM32F405xx, STM32F407xx 168/185 DocID022152 Rev 4 Figure 85. LQFP176 recommended footprint 1. Dimensions are expressed in millimeters. ccc 0.080 0.0031 k 0 ° 7 ° 0 ° 7 ° 1. Values in inches are converted from mm and rounded to 4 decimal digits. Table 95. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package mechanical data Symbol millimeters inches(1) Min Typ Max Min Typ Max 1T_FP_V1 133 132 1.2 0.3 0.5 89 88 1.2 44 45 21.8 26.7 1 176 26.7 21.8 DocID022152 Rev 4 169/185 STM32F405xx, STM32F407xx Package characteristics 6.2 Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x ΘJA) Where: • TA max is the maximum ambient temperature in °C, • ΘJA is the package junction-to-ambient thermal resistance, in °C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. Table 96. Package thermal characteristics Symbol Parameter Value Unit ΘJA Thermal resistance junction-ambient LQFP64 - 10 × 10 mm / 0.5 mm pitch 46 °C/W Thermal resistance junction-ambient LQFP100 - 14 × 14 mm / 0.5 mm pitch 43 Thermal resistance junction-ambient LQFP144 - 20 × 20 mm / 0.5 mm pitch 40 Thermal resistance junction-ambient LQFP176 - 24 × 24 mm / 0.5 mm pitch 38 Thermal resistance junction-ambient UFBGA176 - 10× 10 mm / 0.65 mm pitch 39 Thermal resistance junction-ambient WLCSP90 - 0.400 mm pitch 38.1 Part numbering STM32F405xx, STM32F407xx 170/185 DocID022152 Rev 4 7 Part numbering For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. Table 97. Ordering information scheme Example: STM32 F 405 R E T 6 xxx Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 405 = STM32F40x, connectivity 407= STM32F40x, connectivity, camera interface, Ethernet Pin count R = 64 pins O = 90 pins V = 100 pins Z = 144 pins I = 176 pins Flash memory size E = 512 Kbytes of Flash memory G = 1024 Kbytes of Flash memory Package T = LQFP H = UFBGA Y = WLCSP Temperature range 6 = Industrial temperature range, –40 to 85 °C. 7 = Industrial temperature range, –40 to 105 °C. Options xxx = programmed parts TR = tape and reel DocID022152 Rev 4 171/185 STM32F405xx, STM32F407xx Application block diagrams Appendix A Application block diagrams A.1 USB OTG full speed (FS) interface solutions Figure 86. USB controller configured as peripheral-only and used in Full speed mode 1. External voltage regulator only needed when building a VBUS powered device. 2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller. Figure 87. USB controller configured as host-only and used in full speed mode 1. The current limiter is required only if the application has to support a VBUS powered device. A basic power switch can be used if 5 V are available on the application board. 2. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller. STM32F4xx 5V to VDD Volatge regulator (1) VDD VBUS DP VSS PA12/PB15 PA11//PB14 USB Std-B connector DM OSC_IN OSC_OUT MS19000V5 STM32F4xx VDD VBUS DP VSS USB Std-A connector DM GPIO+IRQ GPIO EN Overcurrent 5 V Pwr OSC_IN OSC_OUT MS19001V4 Current limiter power switch(1) PA12/PB15 PA11//PB14 Application block diagrams STM32F405xx, STM32F407xx 172/185 DocID022152 Rev 4 Figure 88. USB controller configured in dual mode and used in full speed mode 1. External voltage regulator only needed when building a VBUS powered device. 2. The current limiter is required only if the application has to support a VBUS powered device. A basic power switch can be used if 5 V are available on the application board. 3. The ID pin is required in dual role only. 4. The same application can be developed using the OTG HS in FS mode to achieve enhanced performance thanks to the large Rx/Tx FIFO and to a dedicated DMA controller. STM32F4xx VDD VBUS DP VSS PA9/PB13 PA12/PB15 PA11/PB14 USB micro-AB connector DM GPIO+IRQ GPIO EN Overcurrent 5 V Pwr 5 V to VDD voltage regulator (1) VDD ID(3) PA10/PB12 OSC_IN OSC_OUT MS19002V3 Current limiter power switch(2) DocID022152 Rev 4 173/185 STM32F405xx, STM32F407xx Application block diagrams A.2 USB OTG high speed (HS) interface solutions Figure 89. USB controller configured as peripheral, host, or dual-mode and used in high speed mode 1. It is possible to use MCO1 or MCO2 to save a crystal. It is however not mandatory to clock the STM32F40x with a 24 or 26 MHz crystal when using USB HS. The above figure only shows an example of a possible connection. 2. The ID pin is required in dual role only. DP STM32F4xx DM VBUS VSS DM DP ID(2) USB USB HS OTG Ctrl FS PHY ULPI High speed OTG PHY ULPI_CLK ULPI_D[7:0] ULPI_DIR ULPI_STP ULPI_NXT not connected connector MCO1 or MCO2 24 or 26 MHz XT(1) PLL XT1 XI MS19005V2 Application block diagrams STM32F405xx, STM32F407xx 174/185 DocID022152 Rev 4 A.3 Ethernet interface solutions Figure 90. MII mode using a 25 MHz crystal 1. fHCLK must be greater than 25 MHz. 2. Pulse per second when using IEEE1588 PTP optional signal. Figure 91. RMII with a 50 MHz oscillator 1. fHCLK must be greater than 25 MHz. MCU Ethernet MAC 10/100 Ethernet PHY 10/100 PLL HCLK XT1 PHY_CLK 25 MHz MII_RX_CLK MII_RXD[3:0] MII_RX_DV MII_RX_ER MII_TX_CLK MII_TX_EN MII_TXD[3:0] MII_CRS MII_COL MDIO MDC HCLK(1) PPS_OUT(2) XTAL 25 MHz STM32 OSC TIM2 Timestamp comparator Timer input trigger IEEE1588 PTP MII = 15 pins MII + MDC = 17 pins MS19968V1 MCO1/MCO2 MCU Ethernet MAC 10/100 Ethernet PHY 10/100 PLL HCLK PHY_CLK 50 MHz XT1 RMII_RXD[1:0] RMII_CRX_DV RMII_REF_CLK RMII_TX_EN RMII_TXD[1:0] MDIO MDC HCLK(1) STM32 OSC 50 MHz TIM2 Timestamp comparator Timer input trigger IEEE1588 PTP RMII = 7 pins RMII + MDC = 9 pins MS19969V1 /2 or /20 2.5 or 25 MHz synchronous 50 MHz 50 MHz DocID022152 Rev 4 175/185 STM32F405xx, STM32F407xx Application block diagrams Figure 92. RMII with a 25 MHz crystal and PHY with PLL 1. fHCLK must be greater than 25 MHz. 2. The 25 MHz (PHY_CLK) must be derived directly from the HSE oscillator, before the PLL block. MCU Ethernet MAC 10/100 Ethernet PHY 10/100 PLL HCLK PHY_CLK 25 MHz XT1 RMII_RXD[1:0] RMII_CRX_DV RMII_REF_CLK RMII_TX_EN RMII_TXD[1:0] MDIO MDC HCLK(1) STM32F TIM2 Timestamp comparator Timer input trigger IEEE1588 PTP RMII = 7 pins RMII + MDC = 9 pins MS19970V1 /2 or /20 2.5 or 25 MHz synchronous 50 MHz XTAL 25 MHz OSC PLL REF_CLK MCO1/MCO2 Revision history STM32F405xx, STM32F407xx 176/185 DocID022152 Rev 4 8 Revision history Table 98. Document revision history Date Revision Changes 15-Sep-2011 1 Initial release. 24-Jan-2012 2 Added WLCSP90 package on cover page. Renamed USART4 and USART5 into UART4 and UART5, respectively. Updated number of USB OTG HS and FS in Table 2: STM32F405xx and STM32F407xx: features and peripheral counts. Updated Figure 3: Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package and Figure 4: Compatible board design between STM32F2xx and STM32F4xx for LQFP176 and BGA176 packages, and removed note 1 and 2. Updated Section 2.2.9: Flexible static memory controller (FSMC). Modified I/Os used to reprogram the Flash memory for CAN2 and USB OTG FS in Section 2.2.13: Boot modes. Updated note in Section 2.2.14: Power supply schemes. PDR_ON no more available on LQFP100 package. Updated Section 2.2.16: Voltage regulator. Updated condition to obtain a minimum supply voltage of 1.7 V in the whole document. Renamed USART4/5 to UART4/5 and added LIN and IrDA feature for UART4 and UART5 in Table 5: USART feature comparison. Removed support of I2C for OTG PHY in Section 2.2.30: Universal serial bus on-the-go full-speed (OTG_FS). Added Table 6: Legend/abbreviations used in the pinout table. Table 7: STM32F40x pin and ball definitions: replaced VSS_3, VSS_4, and VSS_8 by VSS; reformatted Table 7: STM32F40x pin and ball definitions to better highlight I/O structure, and alternate functions versus additional functions; signal corresponding to LQFP100 pin 99 changed from PDR_ON to VSS; EVENTOUT added in the list of alternate functions for all I/Os; ADC3_IN8 added as alternate function for PF10; FSMC_CLE and FSMC_ALE added as alternate functions for PD11 and PD12, respectively; PH10 alternate function TIM15_CH1_ETR renamed TIM5_CH1; updated PA4 and PA5 I/O structure to TTa. Removed OTG_HS_SCL, OTG_HS_SDA, OTG_FS_INTN in Table 7: STM32F40x pin and ball definitions and Table 9: Alternate function mapping. Changed TCM data RAM to CCM data RAM in Figure 18: STM32F40x memory map. Added IVDD and IVSS maximum values in Table 12: Current characteristics. Added Note 1 related to fHCLK, updated Note 2 in Table 14: General operating conditions, and added maximum power dissipation values. Updated Table 15: Limitations depending on the operating power supply range. DocID022152 Rev 4 177/185 STM32F405xx, STM32F407xx Revision history 24-Jan-2012 2 (continued) Added V12 in Table 19: Embedded reset and power control block characteristics. Updated Table 21: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) and Table 20: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM. Added Figure , Figure 25, Figure 26, and Figure 27. Updated Table 22: Typical and maximum current consumption in Sleep mode and removed Note 1. Updated Table 23: Typical and maximum current consumptions in Stop mode and Table 24: Typical and maximum current consumptions in Standby mode, Table 25: Typical and maximum current consumptions in VBAT mode, and Table 26: Switching output I/O current consumption. Section : On-chip peripheral current consumption: modified conditions, and updated Table 27: Peripheral current consumption and Note 2. Changed fHSE_ext to 50 MHz and tr(HSE)/tf(HSE) maximum value in Table 29: High-speed external user clock characteristics. Added Cin(LSE) in Table 30: Low-speed external user clock characteristics. Updated maximum PLL input clock frequency, removed related note, and deleted jitter for MCO for RMII Ethernet typical value in Table 35: Main PLL characteristics. Updated maximum PLLI2S input clock frequency and removed related note in Table 36: PLLI2S (audio PLL) characteristics. Updated Section : Flash memory to specify that the devices are shipped to customers with the Flash memory erased. Updated Table 38: Flash memory characteristics, and added tME in Table 39: Flash memory programming. Updated Table 42: EMS characteristics, and Table 43: EMI characteristics. Updated Table 56: I2S dynamic characteristics Updated Figure 46: ULPI timing diagram and Table 62: ULPI timing. Added tCOUNTER and tMAX_COUNT in Table 51: Characteristics of TIMx connected to the APB1 domain and Table 52: Characteristics of TIMx connected to the APB2 domain. Updated Table 65: Dynamic characteristics: Ethernet MAC signals for RMII. Removed USB-IF certification in Section : USB OTG FS characteristics. Table 98. Document revision history (continued) Date Revision Changes Revision history STM32F405xx, STM32F407xx 178/185 DocID022152 Rev 4 24-Jan-2012 2 (continued) Updated Table 61: USB HS clock timing parameters Updated Table 67: ADC characteristics. Updated Table 68: ADC accuracy at fADC = 30 MHz. Updated Note 1 in Table 74: DAC characteristics. Section 5.3.25: FSMC characteristics: updated Table 75 toTable 86, changed CL value to 30 pF, and modified FSMC configuration for asynchronous timings and waveforms. Updated Figure 60: Synchronous multiplexed PSRAM write timings. Updated Table 96: Package thermal characteristics. Appendix A.1: USB OTG full speed (FS) interface solutions: modified Figure 86: USB controller configured as peripheral-only and used in Full speed mode added Note 2, updated Figure 87: USB controller configured as host-only and used in full speed mode and added Note 2, changed Figure 88: USB controller configured in dual mode and used in full speed mode and added Note 3. Appendix A.2: USB OTG high speed (HS) interface solutions: removed figures USB OTG HS device-only connection in FS mode and USB OTG HS host-only connection in FS mode, and updated Figure 89: USB controller configured as peripheral, host, or dual-mode and used in high speed mode and added Note 2. Added Appendix A.3: Ethernet interface solutions. Table 98. Document revision history (continued) Date Revision Changes DocID022152 Rev 4 179/185 STM32F405xx, STM32F407xx Revision history 31-May-2012 3 Updated Figure 5: STM32F40x block diagram and Figure 7: Power supply supervisor interconnection with internal reset OFF Added SDIO, added notes related to FSMC and SPI/I2S in Table 2: STM32F405xx and STM32F407xx: features and peripheral counts. Starting from Silicon revision Z, USB OTG full-speed interface is now available for all STM32F405xx devices. Added full information on WLCSP90 package together with corresponding part numbers. Changed number of AHB buses to 3. Modified available Flash memory sizes in Section 2.2.4: Embedded Flash memory. Modified number of maskable interrupt channels in Section 2.2.10: Nested vectored interrupt controller (NVIC). Updated case of Regulator ON/internal reset ON, Regulator ON/internal reset OFF, and Regulator OFF/internal reset ON in Section 2.2.16: Voltage regulator. Updated standby mode description in Section 2.2.19: Low-power modes. Added Note 1 below Figure 16: STM32F40x UFBGA176 ballout. Added Note 1 below Figure 17: STM32F40x WLCSP90 ballout. Updated Table 7: STM32F40x pin and ball definitions. Added Table 8: FSMC pin definition. Removed OTG_HS_INTN alternate function in Table 7: STM32F40x pin and ball definitions and Table 9: Alternate function mapping. Removed I2S2_WS on PB6/AF5 in Table 9: Alternate function mapping. Replaced JTRST by NJTRST, removed ETH_RMII _TX_CLK, and modified I2S3ext_SD on PC11 in Table 9: Alternate function mapping. Added Table 10: STM32F40x register boundary addresses. Updated Figure 18: STM32F40x memory map. Updated VDDA and VREF+ decoupling capacitor in Figure 21: Power supply scheme. Added power dissipation maximum value for WLCSP90 in Table 14: General operating conditions. Updated VPOR/PDR in Table 19: Embedded reset and power control block characteristics. Updated notes in Table 21: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled), Table 20: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM, and Table 22: Typical and maximum current consumption in Sleep mode. Updated maximum current consumption at TA = 25 °n Table 23: Typical and maximum current consumptions in Stop mode. Table 98. Document revision history (continued) Date Revision Changes Revision history STM32F405xx, STM32F407xx 180/185 DocID022152 Rev 4 31-May-2012 3 (continued) Removed fHSE_ext typical value in Table 29: High-speed external user clock characteristics. Updated Table 31: HSE 4-26 MHz oscillator characteristics and Table 32: LSE oscillator characteristics (fLSE = 32.768 kHz). Added fPLL48_OUT maximum value in Table 35: Main PLL characteristics. Modified equation 1 and 2 in Section 5.3.11: PLL spread spectrum clock generation (SSCG) characteristics. Updated Table 38: Flash memory characteristics, Table 39: Flash memory programming, and Table 40: Flash memory programming with VPP. Updated Section : Output driving current. Table 53: I2C characteristics: Note 4 updated and applied to th(SDA) in Fast mode, and removed note 4 related to th(SDA) minimum value. Updated Table 67: ADC characteristics. Updated note concerning ADC accuracy vs. negative injection current below Table 68: ADC accuracy at fADC = 30 MHz. Added WLCSP90 thermal resistance in Table 96: Package thermal characteristics. Updated Table 90: WLCSP90 - 0.400 mm pitch wafer level chip size package mechanical data. Updated Figure 83: UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline and Table 94: UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data. Added Figure 85: LQFP176 recommended footprint. Removed 256 and 768 Kbyte Flash memory density from Table 97: Ordering information scheme. Table 98. Document revision history (continued) Date Revision Changes DocID022152 Rev 4 181/185 STM32F405xx, STM32F407xx Revision history 04-Jun-2013 4 Modified Note 1 below Table 2: STM32F405xx and STM32F407xx: features and peripheral counts. Updated Figure 4 title. Updated Note 3 below Figure 21: Power supply scheme. Changed simplex mode into half-duplex mode in Section 2.2.25: Interintegrated sound (I2S). Replaced DAC1_OUT and DAC2_OUT by DAC_OUT1 and DAC_OUT2, respectively. Updated pin 36 signal in Figure 15: STM32F40x LQFP176 pinout. Changed pin number from F8 to D4 for PA13 pin in Table 7: STM32F40x pin and ball definitions. Replaced TIM2_CH1/TIM2_ETR by TIM2_CH1_ETR for PA0 and PA5 pins in Table 9: Alternate function mapping. Changed system memory into System memory + OTP in Figure 18: STM32F40x memory map. Added Note 1 below Table 16: VCAP_1/VCAP_2 operating conditions. Updated IDDA description in Table 74: DAC characteristics. Removed PA9/PB13 connection to VBUS in Figure 86: USB controller configured as peripheral-only and used in Full speed mode and Figure 87: USB controller configured as host-only and used in full speed mode. Updated SPI throughput on front page and Section 2.2.24: Serial peripheral interface (SPI) Updated operating voltages in Table 2: STM32F405xx and STM32F407xx: features and peripheral counts Updated note in Section 2.2.14: Power supply schemes Updated Section 2.2.15: Power supply supervisor Updated “Regulator ON” paragraph in Section 2.2.16: Voltage regulator Removed note in Section 2.2.19: Low-power modes Corrected wrong reference manual in Section 2.2.28: Ethernet MAC interface with dedicated DMA and IEEE 1588 support Updated Table 15: Limitations depending on the operating power supply range Updated Table 24: Typical and maximum current consumptions in Standby mode Updated Table 25: Typical and maximum current consumptions in VBAT mode Updated Table 36: PLLI2S (audio PLL) characteristics Updated Table 43: EMI characteristics Updated Table 48: Output voltage characteristics Updated Table 50: NRST pin characteristics Updated Table 55: SPI dynamic characteristics Updated Table 56: I2S dynamic characteristics Deleted Table 59 Updated Table 62: ULPI timing Updated Figure 47: Ethernet SMI timing diagram Table 98. Document revision history (continued) Date Revision Changes Revision history STM32F405xx, STM32F407xx 182/185 DocID022152 Rev 4 04-Jun-2013 4 (continued) Updated Figure 83: UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm, package outline Updated Table 94: UFBGA176+25 - ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data Updated Figure 5: STM32F40x block diagram Updated Section 2: Description Updated footnote (3) in Table 2: STM32F405xx and STM32F407xx: features and peripheral counts Updated Figure 3: Compatible board design between STM32F10xx/STM32F2xx/STM32F4xx for LQFP144 package Updated Figure 4: Compatible board design between STM32F2xx and STM32F4xx for LQFP176 and BGA176 packages Updated Section 2.2.14: Power supply schemes Updated Section 2.2.15: Power supply supervisor Updated Section 2.2.16: Voltage regulator, including figures. Updated Table 14: General operating conditions, including footnote (2). Updated Table 15: Limitations depending on the operating power supply range, including footnote (3). Updated footnote (1) in Table 67: ADC characteristics. Updated footnote (3) in Table 68: ADC accuracy at fADC = 30 MHz. Updated footnote (1) in Table 74: DAC characteristics. Updated Figure 9: Regulator OFF. Updated Figure 7: Power supply supervisor interconnection with internal reset OFF. Added Section 2.2.17: Regulator ON/OFF and internal reset ON/OFF availability. Updated footnote (2) of Figure 21: Power supply scheme. Replaced respectively “I2S3S_WS" by "I2S3_WS”, “I2S3S_CK” by “I2S3_CK” and “FSMC_BLN1” by “FSMC_NBL1” in Table 9: Alternate function mapping. Added “EVENTOUT” as alternate function “AF15” for pin PC13, PC14, PC15, PH0, PH1, PI8 in Table 9: Alternate function mapping Replaced “DCMI_12” by “DCMI_D12” in Table 7: STM32F40x pin and ball definitions. Removed the following sentence from Section : I2C interface characteristics: ”Unless otherwise specified, the parameters given in Table 53 are derived from tests performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 14.”. In Table 7: STM32F40x pin and ball definitions on page 45: – For pin PC13, replaced “RTC_AF1” by “RTC_OUT, RTC_TAMP1, RTC_TS” – for pin PI8, replaced “RTC_AF2” by “RTC_TAMP1, RTC_TAMP2, RTC_TS”. – for pin PB15, added RTC_REFIN in Alternate functions column. In Table 9: Alternate function mapping on page 60, for port PB15, replaced “RTC_50Hz” by “RTC_REFIN”. Table 98. Document revision history (continued) Date Revision Changes DocID022152 Rev 4 183/185 STM32F405xx, STM32F407xx Revision history 04-Jun-2013 4 (continued) Updated Figure 6: Multi-AHB matrix. Updated Figure 7: Power supply supervisor interconnection with internal reset OFF Changed 1.2 V to V12 in Section : Regulator OFF Updated LQFP176 pin 48. Updated Section 1: Introduction. Updated Section 2: Description. Updated operating voltage in Table 2: STM32F405xx and STM32F407xx: features and peripheral counts. Updated Note 1. Updated Section 2.2.15: Power supply supervisor. Updated Section 2.2.16: Voltage regulator. Updated Figure 9: Regulator OFF. Updated Table 3: Regulator ON/OFF and internal reset ON/OFF availability. Updated Section 2.2.19: Low-power modes. Updated Section 2.2.20: VBAT operation. Updated Section 2.2.22: Inter-integrated circuit interface (I²C) . Updated pin 48 in Figure 15: STM32F40x LQFP176 pinout. Updated Table 6: Legend/abbreviations used in the pinout table. Updated Table 7: STM32F40x pin and ball definitions. Updated Table 14: General operating conditions. Updated Table 15: Limitations depending on the operating power supply range. Updated Section 5.3.7: Wakeup time from low-power mode. Updated Table 33: HSI oscillator characteristics. Updated Section 5.3.15: I/O current injection characteristics. Updated Table 47: I/O static characteristics. Updated Table 50: NRST pin characteristics. Updated Table 53: I2C characteristics. Updated Figure 39: I2C bus AC waveforms and measurement circuit. Updated Section 5.3.19: Communications interfaces. Updated Table 67: ADC characteristics. Added Table 70: Temperature sensor calibration values. Added Table 73: Internal reference voltage calibration values. Updated Section 5.3.25: FSMC characteristics. Updated Section 5.3.27: SD/SDIO MMC card host interface (SDIO) characteristics. Updated Table 23: Typical and maximum current consumptions in Stop mode. Updated Section : SPI interface characteristics included Table 55. Updated Section : I2S interface characteristics included Table 56. Updated Table 64: Dynamic characteristics: Ehternet MAC signals for SMI. Updated Table 66: Dynamic characteristics: Ethernet MAC signals for MII. Table 98. Document revision history (continued) Date Revision Changes Revision history STM32F405xx, STM32F407xx 184/185 DocID022152 Rev 4 04-Jun-2013 4 (continued) Updated Table 64: Dynamic characteristics: Ehternet MAC signals for SMI. Updated Table 66: Dynamic characteristics: Ethernet MAC signals for MII. Updated Table 79: Synchronous multiplexed NOR/PSRAM read timings. Updated Table 80: Synchronous multiplexed PSRAM write timings. Updated Table 81: Synchronous non-multiplexed NOR/PSRAM read timings. Updated Table 82: Synchronous non-multiplexed PSRAM write timings. Updated Section 5.3.26: Camera interface (DCMI) timing specifications including Table 87: DCMI characteristics and addition of Figure 73: DCMI timing diagram. Updated Section 5.3.27: SD/SDIO MMC card host interface (SDIO) characteristics including Table 88. Updated Chapter Figure 9. Table 98. Document revision history (continued) Date Revision Changes DocID022152 Rev 4 185/185 STM32F405xx, STM32F407xx Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2013 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 1IN+ 1IN− FEEDBACK DTC CT RT GND C1 2IN+ 2IN− REF OUTPUT CTRL VCC C2 E2 E1 D, DB, N, NS, OR PW PACKAGE (TOP VIEW) TL494 www.ti.com SLVS074F –JANUARY 1983–REVISED JANUARY 2014 TL494 Pulse-Width-Modulation Control Circuits Check for Samples: TL494 1FEATURES DESCRIPTION • Complete PWM Power-Control Circuitry The TL494 device incorporates all the functions • Uncommitted Outputs for 200-mA Sink or required in the construction of a pulse-width- modulation (PWM) control circuit on a single chip. Source Current Designed primarily for power-supply control, this • Output Control Selects Single-Ended or device offers the flexibility to tailor the power-supply Push-Pull Operation control circuitry to a specific application. • Internal Circuitry Prohibits Double Pulse at The TL494 device contains two error amplifiers, an Either Output on-chip adjustable oscillator, a dead-time control • Variable Dead Time Provides Control Over (DTC) comparator, a pulse-steering control flip-flop, a Total Range 5-V, 5%-precision regulator, and output-control circuits. • Internal Regulator Provides a Stable 5-V Reference Supply With 5% Tolerance The error amplifiers exhibit a common-mode voltage • Circuit Architecture Allows Easy range from –0.3 V to VCC – 2 V. The dead-time Synchronization control comparator has a fixed offset that provides approximately 5% dead time. The on-chip oscillator can be bypassed by terminating RT to the reference output and providing a sawtooth input to CT, or it can drive the common circuits in synchronous multiple-rail power supplies. The uncommitted output transistors provide either common-emitter or emitter-follower output capability. The TL494 device provides for push-pull or singleended output operation, which can be selected through the output-control function. The architecture of this device prohibits the possibility of either output being pulsed twice during push-pull operation. The TL494C device is characterized for operation from 0°C to 70°C. The TL494I device is characterized for operation from –40°C to 85°C. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 1983–2014, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. GND VCC Reference Regulator C1 Pulse-Steering Flip-Flop C1 1D DTC CT RT PWM Comparator + − Error Amplifier 1 ≈ 0.1 V Dead-Time Control Comparator Oscillator OUTPUT CTRL (see Function Table) 0.7 mA E1 C2 E2 + − Error Amplifier 2 1IN+ 1IN− 2IN+ 2IN− FEEDBACK REF 6 5 4 1 2 16 15 3 13 8 9 11 10 12 14 7 Q1 ≈ 0.7 V Q2 TL494 SLVS074F –JANUARY 1983–REVISED JANUARY 2014 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Function Table INPUT TO OUTPUT FUNCTION OUTPUT CTRL VI = GND Single-ended or parallel output VI = Vref Normal push-pull operation Functional Block Diagram 2 Submit Documentation Feedback Copyright © 1983–2014, Texas Instruments Incorporated Product Folder Links :TL494 TL494 www.ti.com SLVS074F –JANUARY 1983–REVISED JANUARY 2014 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply voltage(2) 41 V VI Amplifier input voltage VCC + 0.3 V VO Collector output voltage 41 V IO Collector output current 250 mA D package 73 DB package 82 θJA Package thermal impedance(3) (4) N package 67 °C/W NS package 64 PW package 108 Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C Tstg Storage temperature range –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to the network ground terminal. (3) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. (4) The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions MIN MAX UNIT VCC Supply voltage 7 40 V VI Amplifier input voltage –0.3 VCC – 2 V VO Collector output voltage 40 V Collector output current (each transistor) 200 mA Current into feedback terminal 0.3 mA fOSC Oscillator frequency 1 300 kHz CT Timing capacitor 0.47 10000 nF RT Timing resistor 1.8 500 kΩ TL494C 0 70 TA Operating free-air temperature °C TL494I –40 85 Copyright © 1983–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links :TL494    N n1 (xnX)2 N1  TL494 SLVS074F –JANUARY 1983–REVISED JANUARY 2014 www.ti.com Electrical Characteristics over recommended operating free-air temperature range, VCC = 15 V, f = 10 kHz (unless otherwise noted) Reference Section TL494C, TL494I PARAMETER TEST CONDITIONS(1) UNIT MIN TYP(2) MAX Output voltage (REF) IO = 1 mA 4.75 5 5.25 V Input regulation VCC = 7 V to 40 V 2 25 mV Output regulation IO = 1 mA to 10 mA 1 15 mV Output voltage change with temperature ΔTA = MIN to MAX 2 10 mV/V Short-circuit output current(3) REF = 0 V 25 mA (1) For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. (2) All typical values, except for parameter changes with temperature, are at TA = 25°C. (3) Duration of short circuit should not exceed one second. Oscillator Section CT = 0.01 μF, RT = 12 kΩ (see Figure 1) TL494C, TL494I PARAMETER TEST CONDITIONS(1) UNIT MIN TYP(2) MAX Frequency 10 kHz Standard deviation of frequency(3) All values of VCC, CT, RT, and TA constant 100 Hz/kHz Frequency change with voltage VCC = 7 V to 40 V, TA = 25°C 1 Hz/kHz Frequency change with temperature(4) ΔTA = MIN to MAX 10 Hz/kHz (1) For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. (2) All typical values, except for parameter changes with temperature, are at TA = 25°C. (3) Standard deviation is a measure of the statistical distribution about the mean as derived from the formula: (4) Temperature coefficient of timing capacitor and timing resistor are not taken into account. Error-Amplifier Section See Figure 2 TL494C, TL494I PARAMETER TEST CONDITIONS UNIT MIN TYP(1) MAX Input offset voltage VO (FEEDBACK) = 2.5 V 2 10 mV Input offset current VO (FEEDBACK) = 2.5 V 25 250 nA Input bias current VO (FEEDBACK) = 2.5 V 0.2 1 μA Common-mode input voltage range VCC = 7 V to 40 V –0.3 to VCC – 2 V Open-loop voltage amplification ΔVO = 3 V, VO = 0.5 V to 3.5 V, RL = 2 kΩ 70 95 dB Unity-gain bandwidth VO = 0.5 V to 3.5 V, RL = 2 kΩ 800 kHz Common-mode rejection ratio ΔVO = 40 V, TA = 25°C 65 80 dB Output sink current (FEEDBACK) VID = –15 mV to –5 V, V (FEEDBACK) = 0.7 V 0.3 0.7 mA Output source current (FEEDBACK) VID = 15 mV to 5 V, V (FEEDBACK) = 3.5 V –2 mA (1) All typical values, except for parameter changes with temperature, are at TA = 25°C. 4 Submit Documentation Feedback Copyright © 1983–2014, Texas Instruments Incorporated Product Folder Links :TL494 TL494 www.ti.com SLVS074F –JANUARY 1983–REVISED JANUARY 2014 Electrical Characteristics over recommended operating free-air temperature range, VCC = 15 V, f = 10 kHz (unless otherwise noted) Output Section PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT Collector off-state current VCE = 40 V, VCC = 40 V 2 100 μA Emitter off-state current VCC = VC = 40 V, VE = 0 –100 μA Common emitter VE = 0, IC = 200 mA 1.1 1.3 Collector-emitter saturation voltage V Emitter follower VO(C1 or C2) = 15 V, IE = –200 mA 1.5 2.5 Output control input current VI = Vref 3.5 mA (1) All typical values, except for temperature coefficient, are at TA = 25°C. Dead-Time Control Section See Figure 1 PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT Input bias current (DEAD-TIME CTRL) VI = 0 to 5.25 V –2 –10 μA Maximum duty cycle, each output VI (DEAD-TIME CTRL) = 0, CT = 0.01 μF, 45 % RT = 12 kΩ Zero duty cycle 3 3.3 Input threshold voltage (DEAD-TIME CTRL) V Maximum duty cycle 0 (1) All typical values, except for temperature coefficient, are at TA = 25°C. PWM Comparator Section See Figure 1 PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT Input threshold voltage (FEEDBACK) Zero duty cyle 4 4.5 V Input sink current (FEEDBACK) V (FEEDBACK) = 0.7 V 0.3 0.7 mA (1) All typical values, except for temperature coefficient, are at TA = 25°C. Total Device PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT RT = Vref, VCC = 15 V 6 10 Standby supply current All other inputs and outputs open mA VCC = 40 V 9 15 Average supply current VI (DEAD-TIME CTRL) = 2 V, See Figure 1 7.5 mA (1) All typical values, except for temperature coefficient, are at TA = 25°C. Switching Characteristics TA = 25°C PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT Rise time 100 200 ns Common-emitter configuration, See Figure 3 Fall time 25 100 ns Rise time 100 200 ns Emitter-follower configuration, See Figure 4 Fall time 40 100 ns (1) All typical values, except for temperature coefficient, are at TA = 25°C. Copyright © 1983–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links :TL494 Test Inputs DTC FEEDBACK RT CT GND 50 kW 12 kW 0.01 mF VCC OUTPUT REF CTRL E2 C2 E1 C1 Output 1 Output 2 150 W 2 W 150 W 2 W VCC = 15 V TEST CIRCUIT 1IN+ VCC VCC 0 V 0 V Voltage at C1 Voltage at C2 Voltage at CT DTC FEEDBACK 0 V 0.7 V 0% MAX 0% Threshold Voltage Threshold Voltage VOLTAGE WAVEFORMS Duty Cycle Error Amplifiers 7 14 12 8 9 11 10 4 3 6 5 1 2 16 15 13 1IN− 2IN− 2IN+ TL494 SLVS074F –JANUARY 1983–REVISED JANUARY 2014 www.ti.com Parameter Measurement Information Figure 1. Operational Test Circuit and Waveforms 6 Submit Documentation Feedback Copyright © 1983–2014, Texas Instruments Incorporated Product Folder Links :TL494 Output Each Output Circuit 68 W 2 W 15 V CL = 15 pF (See Note A) 90% 10% 90% 10% tr tf TEST CIRCUIT OUTPUT VOLTAGE WAVEFORM NOTE A: CL includes probe and jig capacitance. Output Each Output Circuit 68 W 2 W 15 V CL = 15 pF (See Note A) 90% 10% 90% 10% tf tr TEST CIRCUIT OUTPUT VOLTAGE WAVEFORM NOTE A: CL includes probe and jig capacitance. + − + − VI Vref FEEDBACK Amplifier Under Test Other Amplifier TL494 www.ti.com SLVS074F –JANUARY 1983–REVISED JANUARY 2014 Parameter Measurement Information Figure 2. Amplifier Characteristics Figure 3. Common-Emitter Configuration Figure 4. Emitter-Follower Configuration Copyright © 1983–2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links :TL494 10 0 100 20 1 10 100 1 M A − Amplifier Voltage Amplification − dB 30 f − Frequency − Hz 1 k VCC = 15 V !VO = 3 V TA = 25°C 10 k 40 50 60 70 80 90 100 k Df = 1% (1) 40 10 100 1 k 4 k 10 k 40 k 100 k 400 k 1 M f − Oscillator Frequency and Frequency Variation − Hz 400 1 k 4 k 10 k 40 k 100 k RT − Timing Resistance − ! 0.1 μF −2% −1% 0% 0.01 μF 0.001 μF VCC = 15 V TA = 25°C CT = 1 μF TL494 SLVS074F –JANUARY 1983–REVISED JANUARY 2014 www.ti.com Typical Characteristics (1) Frequency variation (Δf) is the change in oscillator frequency that occurs over the full temperature range. Figure 5. Oscillator Frequency and Frequency Variation vs Timing Resistance Figure 6. Amplifier Voltage Amplification vs Frequency 8 Submit Documentation Feedback Copyright © 1983–2014, Texas Instruments Incorporated Product Folder Links :TL494 TL494 www.ti.com SLVS074F –JANUARY 1983–REVISED JANUARY 2014 REVISION HISTORY Changes from Revision E (February 2005) to Revision F Page • Updated document to new TI data sheet format - no specification changes. ...................................................................... 1 • Removed Ordering Information table. ................................................................................................................................... 1 • Added ESD warning. ............................................................................................................................................................ 2 Copyright © 1983–2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links :TL494 PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TL494CD ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL494C TL494CDG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL494C TL494CDR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 TL494C TL494CDRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL494C TL494CDRG3 PREVIEW SOIC D 16 TBD Call TI Call TI 0 to 70 TL494C TL494CDRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL494C TL494CJ OBSOLETE CDIP J 16 TBD Call TI Call TI TL494CN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TL494CN TL494CNE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TL494CN TL494CNSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL494 TL494CNSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TL494 TL494CPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T494 TL494CPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T494 TL494CPWLE OBSOLETE TSSOP PW 16 TBD Call TI Call TI TL494CPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T494 TL494CPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 T494 TL494ID ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL494I TL494IDG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL494I PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TL494IDR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 TL494I TL494IDRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL494I TL494IDRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL494I TL494IN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TL494IN TL494INE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TL494IN TL494MJ OBSOLETE CDIP J 16 TBD Call TI Call TI -55 to 125 TL494MJB OBSOLETE CDIP J 16 TBD Call TI Call TI -55 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 3 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant TL494CDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TL494CDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TL494CDRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TL494CPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TL494IDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TL494IDRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Feb-2014 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TL494CDR SOIC D 16 2500 367.0 367.0 38.0 TL494CDR SOIC D 16 2500 333.2 345.9 28.6 TL494CDRG4 SOIC D 16 2500 333.2 345.9 28.6 TL494CPWR TSSOP PW 16 2000 367.0 367.0 35.0 TL494IDR SOIC D 16 2500 333.2 345.9 28.6 TL494IDRG4 SOIC D 16 2500 333.2 345.9 28.6 PACKAGE MATERIALS INFORMATION www.ti.com 11-Feb-2014 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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Caractéristiques sujettes à modifications sans préavis. Proud to serve you celduc r e l a i s page 1 / 5F/GB S/MON/SO967460/B/01/03/2005 Relais statique monophasé de puissance Power Solid State Relay SO967460 okpac ❏ Relais statique synchrone spécialement adapté aux charges résistives. Zero Cross Solid State Relay specially designed for resistive loads. ❏ Sortie thyristors technologie TMS2 (*) permettant une longue durée de vie : 24 à 600VAC 75A. Back to back thyristors on output with TMS2 (*) technology for a long lifetime expectancy : 24 to 600VAC 75A. ❏ Large plage de contrôle: 3,5 - 32VDC avec un courant de commande régulé. LED de visualisation sur l'entrée de couleur verte. Protection aux surtensions sur l'entrée intégrée. Large control range: 3.5-32VDC with input current limiter. Green LED visualization on the input. Input over-voltage protection. ❏ Protection IP20 sur demande par l'ajout de volets. IP20 protection flaps on request (option). ❏ Construit en conformité aux normes EN60947-4-3 (IEC947-4-3) et EN60950/VDE0805 (Isolement renforcé) -UL-cUL Designed in conformity with EN60947-4-3 (IEC947-4-3) and EN60950/VDE0805 (Reinforced Insulation) -UL-cUL Output : 24-600VAC 75A Input : 3,5-32VDC Typical application: 30kW resistor (AC-51 load) on 400 VAC avec protection IP20/ with IP20 flaps Entrée control + * 1/L1 et 2/T2 peuvent être inversées/ 1/L1 T2 can be changed * le relais doit être monté sur dissipateur thermique / SSR must be mounted on a heatsink 24-600VAC - CHARGE/LOAD protection réseau line protection 4/A2- 3/A1+ 1/L1 2/T1 LED ZC sans protection IP20/ without IP20 flaps (*) : Thermo mechanical Stress Solution - 1/L1 et 2/T1 peuvent être inversées. 1/L1 and 2/T1 can be swapped. - Le relais être monté sur dissipateur thermique. SSR must be mounted on heatsink Application typique: Resistance 30 kW (Catégorie AC-51) en 400 VAC 3,5-32VDC Volets IP20 sur demande/ with IP20 flaps on request Dimensions : r e l a i s Rue Ampère B.P. 4 42290 SORBIERS - FRANCE E-Mail : celduc-relais@celduc.com Fax +33 (0) 4 77 53 85 51 Service Commercial France Tél. : +33 (0) 4 77 53 90 20 Sales Dept.For Europe Tel. : +33 (0) 4 77 53 90 21 Sales Dept. Asia : Tél. +33 (0) 4 77 53 90 19 www.celduc.com celduc Caractéristiques d'entrée / Control characteristics (at 25°C) DC Paramètre / Parameter Symbol Min Typ Max Unit Tension de commande / Control voltage Uc 3,5 5-12-24 32 V Courant de commande / Control current (@ Uc ) Ic <10 <13 <13 mA Tension de non fonctionnement / Release voltage Uc off 2 V LED d'entrée / Input LED verte / green Tension Inverse / Reverse voltage Urv 32 V Tension de transil d'entrée / Clamping voltage (Transil) Uclamp 36 V Immunité / Input immunity : EN61000-4-4 2kV Immunité / Input immunity : EN61000-4-5 2KV Caractéristiques de sortie / Output characteristics (at 25°C) Paramètre / Parameter Conditions Symbol Min Typ. Max Unit Plage de tension utilisation / Operating voltage range Ue 24 400 600 V rms Tension de crête / Peak voltage Up 1200 V Niveau de synchronisme / Zero cross level Usync 35 V Tension minimum amorçage / Latching voltage Ie nom Ua 10 V Courant nominal / nominal current (AC-51) Ie AC-51 75 90 A rms Courant surcharge / Non repetitive overload current tp=10ms (Fig. 3) Itsm 1000 1200 A Chute directe à l'état passant / On state voltage drop @ 25°C Vt 0,9 V Résistance dynamique / On state dynamic resistance rt 4,5 mΩ Puissance dissipée (max) / Output power dissipation (max value) Pd 0,9x0,9xIe + 0,0045xIe2 W Résistance thermique jonction/semelle Thermal resistance between junction to case Rthj/c 0,4 K/W Courant de fuite à l'état bloqué / Off state leakage current @Ue typ, 50Hz Ilk 1 mA Courant minimum de charge / Minimum load current Iemin 5 mA Temps de fermeture / Turn on time @Ue typ, 50Hz ton max 10 ms Temps d'ouverture / Turn off time @Ue typ, 50Hz toff max 10 ms Fréquence utilisation/ Operating frequency range F mains f 0,1 50-60 800 Hz dv/dt à l'état bloqué / Off state dv/dt dv/dt 500 V/μs di/dt max / Maximum di/dt non repetitive di/dt 50 A/μs I2t (<10ms) I2t 5000 7200 A2s Immunité / Conducted immunity level IEC/EN61000-4-4 (bursts) 2kV criterion B Immunité / Conducted immunity level IEC/EN61000-4-5 (surge) 2kV criterion A with external VDR Protection court-circuit / Short circuit protection voir/see page 5 Example Fuse Ferraz URC63A or fast Breaker Input : Ic = f( Uc) page 2 / 5F/GB S/MON/SO967460/B/01/03/2005 okpac Caractéristiques générales / General characteristics (at 25°C) Symbol Isolement entrée/sortie - Input to output insulation Ui 4000 VRMS Isolation sortie/ semelle - Output to case insulation Ui 4000 VRMS Résistance Isolement / Insulation resistance Ri 1000 (@500VDC) MΩ Tenue aux tensions de chocs / Rated impulse voltage Uimp 4000 V Degré de protection / Protection level / CEI529 IP00 Degré de pollution / Pollution degree - 2 Vibrations / Vibration withstand 10 -55 Hz according to CEI68 double amplitude 1,5 mm Tenue aux chocs / Shocks withstand according to CEI68 - 30/50 g Température de fonctionnement / Ambient temperature (no icing, no condensation) - -40 /+100 °C Température de stockage/ Storage temperature (no icing, no condensation) -40/+125 °C Humidité relative / Ambient humidity HR 40 to 85 % Poids/ Weight 80 g Conformité / Conformity EN60947-4-3 (IEC947-4-3) Conformité / Conformity VDE0805/EN60950 UL/cUL plastique du boitier / Housing Material PA 6 UL94VO Semelle / Base plate Aluminium, nickel-plated 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 0 2 4 6 8 10 12 14 Uc (VDc) Ic (mA) r e l a i s Rue Ampère B.P. 4 42290 SORBIERS - FRANCE E-Mail : celduc-relais@celduc.com Fax +33 (0) 4 77 53 85 51 Service Commercial France Tél. : +33 (0) 4 77 53 90 20 Sales Dept.For Europe Tel. : +33 (0) 4 77 53 90 21 Sales Dept. Asia : Tél. +33 (0) 4 77 53 90 19 www.celduc.com celduc page 3 / 5F/GB S/MON/SO967460/B/01/03/2005 okpac Surcharge de courant non répétitive sans tension réappliquée / No repetive surge current without voltage reapplied. Surcharge de courant répétitive avec tension réappliquée Repetive surge current with voltage reapplied. 0,01 0,1 1 10 0 500 1000 1500 t (s) Itsm (Apeak) Surcharge de courant :Itsm (Apeak)=f(t) pour modéle 75A/ Surge current : Itsm (Apeak) = f(t) for 75A Fig.3: 1 2 fig 3 : Courants de surcharges / Overload currents 6K/W correspond à un relais monté sur un adaptateur DIN celduc type 1LD12020 6K/W corresponds to a relay mounted on a DIN rail adaptator like celduc 1LD12020 Fig. 2 Courbes thermiques & Choix dissipateur thermique / Thermal curves and heatsink choice 0 10 20 30 40 50 60 70 80 90 0 10 20 30 40 50 60 70 80 90 100 110 Courant de charge / RMS load current (A) Puissance Dissipée / Power Dissipation (W) 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 110 Température ambiante / Ambient temperature (°C) 1,1K/W 6K/W 2,1K/W 1,5K/W Full on State 50% on State 0,95K/W 0,75K/W 0,55K/W 0,3K/W −> Warning ! semiconductor relays don't provide any galvanic insulation between the load and the mains. Always use in conjunction with an adapted circuit breaker with isolation feature or a similar device in order to ensure a reliable insulation in the event of wrong function and when the relay must be insulated from the mains (maintenance ; if not used for a long duration ...). 1 -Itsm non répétitif sans tension réappliquée est donné pour la détermination des protections. 1 - No repetitive Itsm is given without voltage reapplied . This curve is used to define the protection (fuses). 2 -Itsm répétitif est donné pour des surcharges de courant (Tj initiale=70°C). Attention : la répétition de ces surcharges de courant diminue la durée de vie du relais. 2 - Repetitive Itsm is given for inrush current with initial Tj = 70°C. In normal operation , this curve musn't be exceeded. Be careful, the repetition of the surge current decreases the life expectancy of the SSR. −> Attention ! les relais à semi-conducteurs ne procurent pas d'isolation galvanique entre le réseau et la charge. Ils doivent être utilisés associés à un disjoncteur avec propriété de sectionnement ou similaire, afin d'assurer un sectionnement fiable en amont de la ligne dans l'hypothèse d'une défaillance et pour tous les cas où le relais doit être isolé du réseau (maintenance ; non utilisation sur une longue durée...). r e l a i s Rue Ampère B.P. 4 42290 SORBIERS - FRANCE E-Mail : celduc-relais@celduc.com Fax +33 (0) 4 77 53 85 51 Service Commercial France Tél. : +33 (0) 4 77 53 90 20 Sales Dept.For Europe Tel. : +33 (0) 4 77 53 90 21 Sales Dept. Asia : Tél. +33 (0) 4 77 53 90 19 www.celduc.com page 4 / 5F/GB S/MON/SO967460/B/01/03/2005 okpac okpac Raccordement d'entrée / Control wiring Nombre de fils / Number of wires Modèle de tournevis / Screwdriver type Couple de serrage recommandé 1 2 Recommended Torque Fil rigide (sans embout) SOLID (No ferrule) Fil multibrins (avec embout) FINE STRANDED (With ferrule) Fil rigide (sans embout) SOLID (No ferrule) Fil multibrins (avec embout) FINE STRANDED (With ferrule) M4 N.m 0,75 ... 2,5 mm2 AWG18....AWG14 0,75 ... 2,5 mm2 AWG18....AWG14 0,75 ... 2,5 mm2 AWG18....AWG14 0,75 ... 2,5 mm2 AWG18....AWG14 POZIDRIV 2 1,2 okpac Raccordement de puissance / Power wiring Nombre de fils / Number of wires Modèle de tournevis / Screwdriver type Couple de serrage recommandé 1 2 Recommended Torque Fil rigide (sans embout) SOLID (No ferrule) Fil multibrins (avec embout) FINE STRANDED (With ferrule) Fil rigide (sans embout) SOLID (No ferrule) Fil multibrins (avec embout) FINE STRANDED (With ferrule) M5 N.m 1,5 ... 10 mm2 AWG16....AWG8 1,5 ... 6 mm2 AWG16....AWG10 1,5 ... 10 mm2 AWG16....AWG8 1,5 ... 6 mm2 AWG16....AWG10 POZIDRIV 2 2 Raccordement / Connections celduc Options : Volets IP20 1K453000 = référence d'un volet sans le montage 1LK00500 = 1 volet (côté puissance) + 1 montage celduc 1LK00600 = 2 volets (puissance & commande) + montages celduc Option : IP20 flaps 1K453000 : Flap reference without mounting 1LK00500 = 1 flap (on output) + 1 celduc mounting 1LK00600 = 2 flaps (input & output) + 2 celduc mounting FASTONS : Nous consulter / Consult us Directement avec fils avec ou sans embouts/ Direct connection with wires with or without ferrules Avec cosses/ With ring terminals Puissance avec cosses / Power with ring terminals. W max =12,6mm 16 mm2 (AWG6) 25 mm2 (AWG4) 35mm2 (AWG2 /AWG3) 50mm2 (AWG0 /AWG1) Des cosses et kits d'adaptation peuvent être fournis : voir relais forte puissance et documentation connexion forte puissance/ Suitable ring terminals and special kit for high current can be delivered: see high power SSR and data-sheet for power connexion. r e l a i s Rue Ampère B.P. 4 42290 SORBIERS - FRANCE E-Mail : celduc-relais@celduc.com Fax +33 (0) 4 77 53 85 51 Service Commercial France Tél. : +33 (0) 4 77 53 90 20 Sales Dept.For Europe Tel. : +33 (0) 4 77 53 90 21 Sales Dept. Asia : Tél. +33 (0) 4 77 53 90 19 www.celduc.com S/MON/SO967460/B/01/03/2005 okpac Montage /Mounting: −> Les relais statiques de la gamme okpac doivent être montés sur dissipateur thermique. Une gamme étendue de dissipateurs est disponible. Voir exemples ci dessous et la gamme "WF" sur www.celduc.com. okpac SSRs must be mounted on heatsinks. A large range of heatsinks is available. See below some examples and "WF" range on www.celduc.com. −> Pour le montage du relais sur dissipateur utiliser de la graisse thermique ou un "thermal pad" haute performance spécifié par celduc .Une version autocollante précollée sur le relais est aussi disponible: nous consulter / For heatsink mounting, it is necessary to use thermal grease or thermal pad with high conductibility specified by celduc. An adhesive model mounted by celduc on the SSR is also available: please contact us. Application typiques / Typical LOADS −> Le produit SO9 est défini principalement pour charge résistive AC-51 (chauffage). Pour les autres charges, consulter notre guide de choix. SO9 product is specially designed for AC-51 résistive load (heating). For other loads, consult our selection guide Protection /Protection : −> La protection d'un relais statique contre les court-circuits de la charge peut être faite par fusibles rapides avec des I2t = 1/2 I2t du relais . Un test en laboratoire a été effectué sur les fusibles de marque FERRAZ. Une protection par MCB ( disjoncteurs modulaires miniatures) est aussi possible. Voir notre note application ( protection SSR) et utiliser des relais avec I2t >5000A2s To protect the SSR against a short-circuit of the load , use a fuse with a I2t value = 1/2 I2t value specified page 2. A test has been made with FERRAZ fuses . It is possible to protect SSR by MCB ( miniature circuit breaker). In this case, see application note ( SSR protection) and use a SSR with high I2t value (5000A2s minimum). EMC : −> Immunité : Nous spécifions dans nos notices le niveau d'immunité de nos produits selon les normes essentielles pour ce type de produit, c'est à dire EN61000-4-4 &5. Immunity : We give in our data-sheets the immunity level of our SSRs according to the main standards for these products: EN61000-4-4 &5. −> Emission: Nos relais statiques sont principalement conçus et conformes pour la classe d'appareils A (Industrie). L'utilisation du produit dans des environnements domestiques peut amener l'utilisateur à employer des moyens d'atténuation supplémentaires. En effet, les relais statiques sont des dispositifs complexes qui doivent être interconnectés avec d'autres materiels (charges, cables, etc) pour former un système. Etant donné que les autres materiels ou interconnexions ne sont pas de la responsabilité de celduc, il est de la responsabilité du réalisateur du système de s'assurer que les systèmes contenant des relais statiques satisfont aux prescriptions de toutes les règles et règlements applicables au niveau des systèmes. Consulter celduc qui peut vous conseiller ou réaliser des essais dans son laboratoire sur votre application. Emission: celduc SSRs are mainly designed in compliance with standards for class A equipment (Industry). Use of this product in domestic environments may cause radio interference. In this case the user may be required to employ additionnal devices to reduce noise. SSRs are complex devices that must be interconnected with other equipment (loads, cables, etc.) to form a system. Because the other equipment or the interconnections may not be under the control of celduc, it shall be the responsability of the system integrator to ensure that systems containing SSRs comply with the requirement of any rules and regulations applicable at the system level. Consult celduc for advices. Tests can be preformed in our laboratory. Thermal pad : 5TH21000 WF151200 (2-2,5 K/W) WF108110 ( 1,1 K/W) Installation des volets IP20 / IP20 flaps mounting Poussez et fermer. Push and close M4x12mm 1,2N.m Thermal grease or pad page 5 / 5F/GB celduc 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 1B 2B 3B 4B 5B 6B 7B 8B GND 1C 2C 3C 4C 5C 6C 7C 8C COM DW OR N PACKAGE (TOP VIEW) ULN2803A www.ti.com SLRS049F –FEBRUARY 1997–REVISED JANUARY 2014 ULN2803A Darlington Transistor Arrays Check for Samples: ULN2803A 1FEATURES DESCRIPTION • 500-mA-Rated Collector Current The ULN2803A device is a high-voltage, high-current (Single Output) Darlington transistor array. The device consists of eight npn Darlington pairs that feature high-voltage • High-Voltage Outputs: 50 V outputs with common-cathode clamp diodes for • Output Clamp Diodes switching inductive loads. The collector-current rating • Inputs Compatible With Various of each Darlington pair is 500 mA. The Darlington Types of Logic pairs may be connected in parallel for higher current capability. • Relay-Driver Applications • Compatible with ULN2800A Series Applications include relay drivers, hammer drivers, lamp drivers, display drivers (LED and gas discharge), line drivers, and logic buffers. The ULN2803A device has a 2.7-kΩ series base resistor for each Darlington pair for operation directly with TTL or 5-V CMOS devices. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 1997–2014, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 2.7 k! 7.2 k! 3 k! COM Output C E Input B 8C 7C 6C 5C 4C 3C 2C 7 6 5 4 3 2 1 7B 6B 5B 4B 3B 2B 1B 11 12 13 14 15 16 17 COM 8 8B 10 1C 18 ULN2803A SLRS049F –FEBRUARY 1997–REVISED JANUARY 2014 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Logic Diagram Schematic (Each Darlington Pair) 2 Submit Documentation Feedback Copyright © 1997–2014, Texas Instruments Incorporated Product Folder Links :ULN2803A ULN2803A www.ti.com SLRS049F –FEBRUARY 1997–REVISED JANUARY 2014 Absolute Maximum Ratings(1) at 25°C free-air temperature (unless otherwise noted) VALUE UNIT Collector-emitter voltage 50 V Input voltage(2) 30 V Peak collector current 500 mA Output clamp current 500 mA Total substrate-terminal current –2.5 A D package 73.14 θJA Package thermal impedance(3) (4) °C/W DW package 62.66 TJ Operating virtual junction temperature 150 °C Tstg Storage temperature range –65 to 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, unless otherwise noted, are with respect to the emitter/substrate terminal GND. (3) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. (4) The package thermal impedance is calculated in accordance with JESD 51-7. Electrical Characteristics at TA = 25°C free-air temperature (unless otherwise noted) ULN2002A PARAMETER TEST CONDITIONS UNIT MIN TYP MAX I VCE = 50 V, CEX Collector cutoff current see Figure 1 II = 0 50 μA I VCE = 50 V, IC = 500 μA, I(off) Off-state input current T 50 65 μA A = 70°C see Figure 2 II(on) Input current VI = 3.85 V, See Figure 3 0.93 1.35 mA IC = 200 mA 2.4 V VCE = 2 V, I(on) On-state input voltage see Figure 4 IC = 250 mA 2.7 V IC = 300 mA 3 II = 250 μA, IC = 100 mA 0.9 1.1 see Figure 5 V II = 350 μA, CE(sat) Collector-emitter saturation voltage see Figure 5 IC = 200 mA 1 1.3 V II = 500 μA, IC = 350 mA 1.3 1.6 see Figure 5 IR Clamp diode reverse current VR = 50 V, see Figure 6 50 μA VF Clamp diode forward voltage IF = 350 mA see Figure 7 1.7 2 V Ci Input capacitance VI = 0, f = 1 MHz 15 25 pF Switching Characteristics TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low- to high-level output VS = 50 V, CL = 15 pF, RL = 163 Ω, 130 See Figure 8 ns tPHL Propagation delay time, high- to low-level output 20 VOH High-level output voltage after switching VS = 50 V, IO = 300 mA, See Figure 9 VS – 20 mV Copyright © 1997–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links :ULN2803A Open VF IF Open VCE II IC hFE = IC II VR Open IR Open VCE IC VI Open II VI Open Open VCE IC II(off) Open VCE ICEX Open ULN2803A SLRS049F –FEBRUARY 1997–REVISED JANUARY 2014 www.ti.com Parameter Measurement Information Figure 1. ICEX Test Circuit Figure 2. II(off) Test Circuit Figure 3. II(on) Test Circuit Figure 4. VI(on) Test Circuit Figure 5. hFE, VCE(sat) Test Circuit Figure 6. IR Test Circuit Figure 7. VF Test Circuit 4 Submit Documentation Feedback Copyright © 1997–2014, Texas Instruments Incorporated Product Folder Links :ULN2803A Pulse Generator (see Note A) Input Open VS = 50 V RL = 163 ! CL = 15 pF (see Note B) Output tPHL tPLH 0.5 μs <5 ns <10 ns 90% 50% 10% 10% 90% 50% 50% 50% VIH Input (see Note C) Output 0 Test Circuit Voltage Waveforms VOH ULN2803A www.ti.com SLRS049F –FEBRUARY 1997–REVISED JANUARY 2014 Parameter Measurement Information (continued) A. The pulse generator has the following characteristics: PRR = 12.5 kHz, ZO = 50 Ω. B. CL includes probe and jig capacitance. C. VIH = 3 V Figure 8. Propagation Delay-Times Copyright © 1997–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links :ULN2803A Pulse Generator (see Note A) Input VS 163 ! CL = 15 pF (see Note B) Output 40 μs <5 ns <10 ns 90% 1.5 V 10% 10% 90% 1.5 V VIH Input (see Note C) Output 0 2 mH VOH Test Circuit Voltage Waveforms ULN2803A SLRS049F –FEBRUARY 1997–REVISED JANUARY 2014 www.ti.com Parameter Measurement Information (continued) A. The pulse generator has the following characteristics: PRR = 12.5 kHz, ZO = 50 Ω. B. CL includes probe and jig capacitance. C. VIH = 3 V Figure 9. Latch-Up Test 6 Submit Documentation Feedback Copyright © 1997–2014, Texas Instruments Incorporated Product Folder Links :ULN2803A ULN2803A www.ti.com SLRS049F –FEBRUARY 1997–REVISED JANUARY 2014 REVISION HISTORY Changes from Revision E (July 2006) to Revision F Page • Updated document to new TI data sheet format - no specification changes. ...................................................................... 1 • Deleted Ordering Information table. ...................................................................................................................................... 1 • Added ESD warning. ............................................................................................................................................................ 2 Copyright © 1997–2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links :ULN2803A PACKAGE OPTION ADDENDUM www.ti.com 27-Jan-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples ULN2803ADW ACTIVE SOIC DW 18 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ULN2803A ULN2803ADWG4 ACTIVE SOIC DW 18 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ULN2803A ULN2803ADWR ACTIVE SOIC DW 18 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ULN2803A ULN2803ADWRG4 ACTIVE SOIC DW 18 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ULN2803A ULN2803AN ACTIVE PDIP N 18 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 ULN2803AN ULN2803ANE4 ACTIVE PDIP N 18 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 ULN2803AN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. PACKAGE OPTION ADDENDUM www.ti.com 27-Jan-2014 Addendum-Page 2 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant ULN2803ADWR SOIC DW 18 2000 330.0 24.4 10.9 12.0 2.7 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 27-Jan-2014 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ULN2803ADWR SOIC DW 18 2000 370.0 355.0 55.0 PACKAGE MATERIALS INFORMATION www.ti.com 27-Jan-2014 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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The devices require only four small 0.1μF external chargepump capacitors. The MAX3222, MAX3232, and MAX3241 are guaranteed to run at data rates of 120kbps while maintaining RS-232 output levels. The MAX3237 is guaranteed to run at data rates of 250kbps in the normal operating mode and 1Mbps in the MegaBaud™ operating mode, while maintaining RS-232 output levels. The MAX3222/MAX3232 have 2 receivers and 2 drivers. The MAX3222 features a 1μA shutdown mode that reduces power consumption and extends battery life in portable systems. Its receivers remain active in shutdown mode, allowing external devices such as modems to be monitored using only 1μA supply current. The MAX3222 and MAX3232 are pin, package, and functionally compatible with the industry-standard MAX242 and MAX232, respectively. The MAX3241 is a complete serial port (3 drivers/ 5 receivers) designed for notebook and subnotebook computers. The MAX3237 (5 drivers/3 receivers) is ideal for fast modem applications. Both these devices feature a shutdown mode in which all receivers can remain active while using only 1μA supply current. Receivers R1 (MAX3237/MAX3241) and R2 (MAX3241) have extra outputs in addition to their standard outputs. These extra outputs are always active, allowing external devices such as a modem to be monitored without forward biasing the protection diodes in circuitry that may have VCC completely removed. The MAX3222, MAX3232, and MAX3241 are available in space-saving TSSOP and SSOP packages. ________________________Applications Notebook, Subnotebook, and Palmtop Computers High-Speed Modems Battery-Powered Equipment Hand-Held Equipment Peripherals Printers __Next Generation Device Features ♦ For Smaller Packaging: MAX3228E/MAX3229E: +2.5V to +5.5V RS-232 Transceivers in UCSP™ ♦ For Integrated ESD Protection: MAX3222E/MAX3232E/MAX3237E/MAX3241E*/ MAX3246E: ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers ♦ For Low-Voltage or Data Cable Applications: MAX3380E/MAX3381E: +2.35V to +5.5V, 1μA, 2Tx/2Rx RS-232 Transceivers with ±15kV ESD-Protected I/O and Logic Pins 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 SHDN VCC GND C1- T1OUT V+ C1+ EN TOP VIEW R1IN R1OUT T1IN T2OUT T2IN VC2- C2+ R2IN 9 10 R2OUT DIP/SO MAX3222 + MAX3222 _________________Pin Configurations _______________Ordering Information MegaBaud and UCSP are trademarks of Maxim Integrated Products, Inc. *Covered by U.S. Patent numbers 4,636,930; 4,679,134; 4,777,577; 4,797,899; 4,809,152; 4,897,774; 4,999,761; and other patents pending. Typical Operating Circuits appear at end of data sheet. Pin Configurations continued at end of data sheet. Ordering Information continued at end of data sheet. +Denotes lead-free package. PART TEMP RANGE PIN-PACKAGE PKG CODE MAX3222CUP+ 0°C to +70°C 20 TSSOP U20+2 MAX3222CAP+ 0°C to +70°C 20 SSOP A20+1 MAX3222CWN+ 0°C to +70°C 18 SO W18+1 MAX3222CPN+ 0°C to +70°C 18 Plastic Dip P18+5 VCC = 5.0V MAX3222/MAX3232/MAX3237/MAX3241 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors 2 _______________________________________________________________________________________ ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +5.5V, C1–C4 = 0.1μF (Note 2), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 1: V+ and V- can have a maximum magnitude of 7V, but their absolute difference cannot exceed 13V. VCC...........................................................................-0.3V to +6V V+ (Note 1) ...............................................................-0.3V to +7V V- (Note 1) ................................................................+0.3V to -7V V+ + V- (Note 1)...................................................................+13V Input Voltages T_IN, SHDN, EN ...................................................-0.3V to +6V MBAUD...................................................-0.3V to (VCC + 0.3V) R_IN .................................................................................±25V Output Voltages T_OUT...........................................................................±13.2V R_OUT....................................................-0.3V to (VCC + 0.3V) Short-Circuit Duration T_OUT ....................................................................Continuous Continuous Power Dissipation (TA = +70°C) 16-Pin TSSOP (derate 6.7mW/°C above +70°C).............533mW 16-Pin Narrow SO (derate 8.70mW/°C above +70°C) ....696mW 16-Pin Wide SO (derate 9.52mW/°C above +70°C)........762mW 16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)...842mW 18-Pin SO (derate 9.52mW/°C above +70°C)..............762mW 18-Pin Plastic DIP (derate 11.11mW/°C above +70°C) ..889mW 20-Pin SSOP (derate 7.00mW/°C above +70°C) .........559mW 20-Pin TSSOP (derate 8.0mW/°C above +70°C).............640mW 28-Pin TSSOP (derate 8.7mW/°C above +70°C).............696mW 28-Pin SSOP (derate 9.52mW/°C above +70°C) .........762mW 28-Pin SO (derate 12.50mW/°C above +70°C) .....................1W Operating Temperature Ranges MAX32_ _C_ _.....................................................0°C to +70°C MAX32_ _E_ _ .................................................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C IOUT = -1.0mA IOUT = 1.6mA Receivers disabled T_IN, EN, SHDN, MBAUD T_IN, EN, SHDN, MBAUD CONDITIONS V 0.8 1.5 Input Threshold Low 0.6 1.2 Input Voltage Range -25 25 V 0.5 2.0 VCC Power-Supply Current Output Voltage High VCC - 0.6 VCC - 0.1 V Output Voltage Low 0.4 V Output Leakage Current ±0.05 ±10 μA Input Leakage Current ±0.01 ±1.0 μA 0.8 V Input Logic Threshold Low (Note 3) PARAMETER MIN TYP MAX UNITS TA = +25°C TA = +25°C V 1.8 2.4 Input Threshold High 1.5 2.4 VCC = 3.3V VCC = 5.0V 2.0 V 2.4 Input Logic Threshold High (Note 3) No load, VCC = 3.3V or 5.0V, TA = +25°C mA 0.3 1.0 MAX3222/MAX3232/ MAX3241 MAX3237 Shutdown Supply Current SHDN = GND, TA = +25°C 1.0 10 μA VCC = 3.3V VCC = 5.0V VCC = 3.3V VCC = 5.0V DC CHARACTERISTICS LOGIC INPUTS AND RECEIVER OUTPUTS RECEIVER INPUTS MAX3222/MAX3232/MAX3237/MAX3241 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors _______________________________________________________________________________________ 3 TIMING CHARACTERISTICS—MAX3222/MAX3232/MAX3241 (VCC = +3.0V to +5.5V, C1–C4 = 0.1μF (Note 2), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +5.5V, C1–C4 = 0.1μF (Note 2), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) T1IN = T2IN = GND, T3IN = VCC, T3OUT loaded with 3kΩ to GND, T1OUT and T2OUT loaded with 2.5mA each CONDITIONS Transmitter Output Voltage ±5.0 V Input Hysteresis 0.3 V PARAMETER MIN TYP MAX UNITS Output Voltage Swing All transmitter outputs loaded with 3kΩ to ground ±5.0 ±5.4 V Output Short-Circuit Current ±35 ±60 mA Output Resistance VCC = V+ = V- = 0V, VOUT = ±2V 300 10M Ω VOUT = ±12V, VCC = 0V or 3V to 5.5V, transmitters disabled Output Leakage Current ±25 μA tPHL RL = 3kΩ, CL = 1000pF, one transmitter switching tPLH | tPHL - tPLH | | tPHL - tPLH | Normal operation Normal operation CONDITIONS 0.3 μs 0.3 Receiver Propagation Delay Maximum Data Rate 120 235 kbps Receiver Skew 300 ns Transmitter Skew 300 ns Receiver Output Disable Time 200 ns Receiver Output Enable Time 200 ns PARAMETER MIN TYP MAX UNITS VCC = 3.3V, RL = 3kΩ to 7kΩ, 6 30 +3V to -3V or -3V to +3V, TA = +25°C, one transmitter switching V/μs 4 30 Transition-Region Slew Rate R_IN to R_OUT, CL = 150pF CL = 150pF to 1000pF CL = 150pF to 2500pF Input Resistance TA = +25°C 3 5 7 kΩ MOUSE DRIVEABILITY (MAX3241) TRANSMITTER OUTPUTS MAX3222/MAX3232/MAX3237/MAX3241 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors 4 _______________________________________________________________________________________ __________________________________________Typical Operating Characteristics (VCC = +3.3V, 235kbps data rate, 0.1μF capacitors, all transmitters loaded with 3kΩ, TA = +25°C, unless otherwise noted.) RL = 3kΩ, CL = 1000pF, one transmitter switching, MBAUD = GND Normal operation CONDITIONS Receiver Output Disable Time Normal operation 200 ns | tPHL - tPLH |, MBAUD = GND 100 ns 0.15 250 μs 0.15 Receiver Propagation Delay Receiver Output Enable Time 200 ns PARAMETER MIN TYP MAX UNITS TIMING CHARACTERISTICS—MAX3237 (VCC = +3.0V to +5.5V, C1–C4 = 0.1μF (Note 2), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) VCC = 3.0V to 4.5V, RL = 3kΩ, CL = 250pF, one transmitter switching, MBAUD = VCC 1000 VCC = 4.5V to 5.5V, RL = 3kΩ, CL = 1000pF, one transmitter switching, MBAUD = VCC kbps 1000 Maximum Data Rate R_IN to R_OUT, CL = 150pF | tPHL - tPLH |, MBAUD = VCC 25 ns Transmitter Skew Receiver Skew | tPHL - tPLH | 50 ns 6 30 V/μs 4 30 tPHL tPLH CL = 150pF to 2500pF, MBAUD = GND CL = 150pF to 1000pF MBAUD = GND VCC = 3.3V, RL = 3Ω to 7kΩ, +3V to -3V or -3V to +3V, TA = +25°C Transition-Region Slew Rate MBAUD = VCC 24 150 Note 2: MAX3222/MAX3232/MAX3241: C1–C4 = 0.1μF tested at 3.3V ±10%; C1 = 0.047μF, C2–C4 = 0.33μF tested at 5.0V ±10%. MAX3237: C1–C4 = 0.1μF tested at 3.3V ±5%; C1–C4 = 0.22μF tested at 3.3V ±10%; C1 = 0.047μF, C2–C4 = 0.33μF tested at 5.0V ±10%. Note 3: Transmitter input hysteresis is typically 250mV. -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 0 MAX3222/MAX3232 TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE MAX3222-01 LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (V) 1000 2000 3000 4000 5000 VOUT+ VOUT- 0 2 4 6 8 10 12 14 16 18 20 22 150 MAX3222/MAX3232 SLEW RATE vs. LOAD CAPACITANCE MAX3222-02 LOAD CAPACITANCE (pF) SLEW RATE (V/μs) 1000 2000 3000 4000 5000 FOR DATA RATES UP TO 235kbps +SLEW -SLEW 0 5 10 15 20 25 30 35 40 0 MAX3222/MAX3232 SUPPLY CURRENT vs. LOAD CAPACITANCE WHEN TRANSMITTING DATA MAX3222-03 LOAD CAPACITANCE (pF) SUPPLY CURRENT (mA) 1000 2000 3000 4000 5000 235kbps 120kbps 20kbps MAX3222/MAX3232/MAX3237/MAX3241 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors _______________________________________________________________________________________ 5 -7.5 -5.0 -2.5 0 2.5 5.0 7.5 0 MAX3241 TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE MAX3222-04 LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (V) 1000 2000 3000 4000 5000 VOUT+ 1 TRANSMITTER AT 235kbps 2 TRANSMITTERS AT 30kbps VOUTALL OUTPUTS LOADED WITH 3kΩ +CL 0.1μF CHARGE-PUMP CAPACITORS 4 FOR ALL DATA RATES UP TO 235kbps 6 8 10 12 14 16 18 20 22 24 0 MAX3241 SLEW RATE vs. LOAD CAPACITANCE MAX3222-05 LOAD CAPACITANCE (pF) SLEW RATE (V/μs) 1000 2000 3000 4000 5000 +SLEW -SLEW 0 5 10 15 20 25 30 35 45 40 0 MAX3241 SUPPLY CURRENT vs. LOAD CAPACITANCE WHEN TRANSMITTING DATA MAX3222-06 LOAD CAPACITANCE (pF) SUPPLY CURRENT (mA) 1000 2000 3000 4000 5000 235kbps 120kbps 20kbps -7.5 -5.0 -2.5 0 2.5 5.0 7.5 0 MAX3237 TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE (MBAUD = GND) MAX3222-07 LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (V) 1000 2000 3000 4000 5000 1 TRANSMITTER AT 240kbps 4 TRANSMITTERS AT 15kbps 3kΩ + CL LOADS VCC = 3.3V 0 10 20 30 50 40 60 70 0 MAX3237 SLEW RATE vs. LOAD CAPACITANCE (MBAUD = VCC) MAX3222-10 LOAD CAPACITANCE (pF) SLEW RATE (V/μs) 500 1000 1500 2000 -SLEW, 1Mbps +SLEW, 1Mbps 1 TRANSMITTER AT FULL DATA RATE 4 TRANSMITTERS AT 1/16 DATA RATE 3kΩ + CL LOAD EACH OUTPUT VCC = 3.3V -SLEW, 2Mbps +SLEW, 2Mbps -7.5 -5.0 -2.5 0 2.5 5.0 7.5 0 MAX3237 TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE (MBAUD = VCC) MAX3222-08 LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (V) 500 1000 1500 2000 1 TRANSMITTER AT FULL DATA RATE 4 TRANSMITTERS AT 1/16 DATA RATE 3kΩ + CL LOAD, EACH OUTPUT VCC = 3.3V 2Mbps 1.5Mbps 1Mbps 2Mbps 1Mbps 1.5Mbps 0 10 20 30 40 50 60 0 MAX3237 SUPPLY CURRENT vs. LOAD CAPACITANCE (MBAUD = GND) MAX3222-11 LOAD CAPACITANCE (pF) SUPPLY CURRENT (mA) 1000 2000 3000 4000 5000 240kbps 120kbps 20kbps 1 TRANSMITTER AT FULL DATA RATE 4 TRANSMITTERS AT 1/16 DATA RATE 3kΩ + CL LOADS VCC = 3.3V 0 2 4 6 8 10 12 0 MAX3237 SLEW RATE vs. LOAD CAPACITANCE (MBAUD = GND) MAX3222-09 LOAD CAPACITANCE (pF) SLEW RATE (V/μs) 1000 2000 3000 4000 5000 +SLEW -SLEW 1 TRANSMITTER AT 240kbps 4 TRANSMITTERS AT 15kbps 3kΩ + CL LOADS VCC = 3.3V 0 10 30 20 40 50 60 70 0 MAX3237 SKEW vs. LOAD CAPACITANCE (tPLH - tPHL) MAX3222-12 LOAD CAPACITANCE (pF) 500 1000 1500 2000 2500 MAX MIN AVERAGE; 10 PARTS SKEW (ns) 1 TRANSMITTER AT 512kbps 4 TRANSMITTERS AT 32kbps 3kΩ + CL LOADS VCC = 3.3V MBAUD = VCC _____________________________Typical Operating Characteristics (continued) (VCC = +3.3V, 235kbps data rate, 0.1μF capacitors, all transmitters loaded with 3kΩ, TA = +25°C, unless otherwise noted.) MAX3222/MAX3232/MAX3237/MAX3241 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors 6 _______________________________________________________________________________________ — FUNCTION — MAX3222 Noninverting Complementary Receiver Outputs. Always active. DIP/SO SSOP — 11, 14 1 1 Receiver Enable. Active low. 2 2 Positive Terminal of Voltage-Doubler Charge-Pump Capacitor 6 6 Negative Terminal of Inverting Charge-Pump Capacitor 5 5 Positive Terminal of Inverting Charge-Pump Capacitor 4 4 Negative Terminal of Voltage-Doubler Charge-Pump Capacitor 3 3 +5.5V Generated by the Charge Pump 11, 12 12, 13 TTL/CMOS Transmitter Inputs 10, 13 10, 15 TTL/CMOS Receiver Outputs 9, 14 9, 16 RS-232 Receiver Inputs 8, 15 8, 17 RS-232 Transmitter Outputs 7 7 -5.5V Generated by the Charge Pump 18 20 Shutdown Control. Active low. 17 19 +3.0V to +5.5V Supply Voltage 16 18 Ground No Connection MAX3232 MAX3237 — 16 — 13 1 28 5 3 4 1 3 25 2 27 10, 11 17, 19, 22, 23, 24 9, 12 18, 20, 21 8, 13 8, 9, 11 7, 14 5, 6, 7, 10, 12 6 4 — 14 16 26 15 2 — — NAME EN C1+ C2- C2+ C1- V+ T_IN R_OUT R_IN T_OUT VSHDN VCC GND R_OUTB N.C. MAX3241 20, 21 23 28 2 1 24 27 12, 13, 14 15–19 4–8 9, 10, 11 3 22 26 25 — PIN — — MegaBaud Control Input. Connect to GND for normal operation; connect to VCC for 1Mbps transmission rates. — 15 — MBAUD ______________________________________________________________Pin Description MAX3222/MAX3232/MAX3237/MAX3241 _______________Detailed Description Dual Charge-Pump Voltage Converter The MAX3222/MAX3232/MAX3237/MAX3241’s internal power supply consists of a regulated dual charge pump that provides output voltages of +5.5V (doubling charge pump) and -5.5V (inverting charge pump), regardless of the input voltage (VCC) over the 3.0V to 5.5V range. The charge pumps operate in a discontinuous mode; if the output voltages are less than 5.5V, the charge pumps are enabled, and if the output voltages exceed 5.5V, the charge pumps are disabled. Each charge pump requires a flying capacitor (C1, C2) and a reservoir capacitor (C3, C4) to generate the V+ and V- supplies. RS-232 Transmitters The transmitters are inverting level translators that convert CMOS-logic levels to 5.0V EIA/TIA-232 levels. The MAX3222/MAX3232/MAX3241 transmitters guarantee a 120kbps data rate with worst-case loads of 3kΩ in parallel with 1000pF, providing compatibility with PC-to- PC communication software (such as LapLink™). Typically, these three devices can operate at data rates of 235kbps. Transmitters can be paralleled to drive multiple receivers or mice. The MAX3222/MAX3237/MAX3241’s output stage is turned off (high impedance) when the device is in shutdown mode. When the power is off, the MAX3222/ MAX3232/MAX3237/MAX3241 permit the outputs to be driven up to ±12V. The transmitter inputs do not have pullup resistors. Connect unused inputs to GND or VCC. MAX3237 MegaBaud Operation In normal operating mode (MBAUD = GND), the MAX3237 transmitters guarantee a 250kbps data rate with worst-case loads of 3kΩ in parallel with 1000pF. This provides compatibility with PC-to-PC communication software, such as LapLink. For higher speed serial communications, the MAX3237 features MegaBaud operation. In MegaBaud operating mode (MBAUD = VCC), the MAX3237 transmitters guarantee a 1Mbps data rate with worst-case loads of 3kΩ in parallel with 250pF for 3.0V < VCC < 4.5V. For 5V ±10% operation, the MAX3237 transmitters guarantee a 1Mbps data rate into worst-case loads of 3kΩ in parallel with 1000pF. MAX3222 MAX3232 MAX3237 MAX3241 5kΩ R_ OUT R_ IN EN* C2- C2+ C1- C1+ VV+ VCC C4 C1 C3 C2 0.1μF VCC SHDN* T_ IN T_ OUT GND VCC 0V 7kΩ 150pF MAX3222 MAX3232 MAX3237 MAX3241 5kΩ R_ OUT R_ IN EN* C2- C2+ C1- C1+ VV+ VCC C4 C1 C3 C2 0.1μF VCC SHDN* T_ IN T_ OUT GND VCC 0V 3kΩ 2500pF MINIMUM SLEW-RATE TEST CIRCUIT MAXIMUM SLEW-RATE TEST CIRCUIT *MAX3222/MAX3237/MAX3241 ONLY Figure 1. Slew-Rate Test Circuits LapLink is a trademark of Traveling Software, Inc. 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors _______________________________________________________________________________________ 7 MAX3222/MAX3232/MAX3237/MAX3241 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors 8 _______________________________________________________________________________________ RS-232 Receivers The receivers convert RS-232 signals to CMOS-logic output levels. The MAX3222/MAX3237/MAX3241 receivers have inverting three-state outputs. In shutdown, the receivers can be active or inactive (Table 1). The complementary outputs on the MAX3237 (R1OUTB) and the MAX3241 (R1OUTB, R2OUTB) are always active, regardless of the state of EN or SHDN. This allows for Ring Indicator applications without forward biasing other devices connected to the receiver outputs. This is ideal for systems where VCC is set to 0V in shutdown to accommodate peripherals, such as UARTs (Figure 2). MAX3222/MAX3237/MAX3241 Shutdown Mode Supply current falls to less than 1μA in shutdown mode (SHDN = low). When shut down, the device’s charge pumps are turned off, V+ is pulled down to VCC, V- is pulled to ground, and the transmitter outputs are disabled (high impedance). The time required to exit shutdown is typically 100μs, as shown in Figure 3. Connect SHDN to VCC if the shutdown mode is not used. SHDN has no effect on R_OUT or R_OUTB. MAX3222/MAX3237/MAX3241 Enable Control The inverting receiver outputs (R_OUT) are put into a high-impedance state when EN is high. The complementary outputs R1OUTB and R2OUTB are always active, regardless of the state of EN and SHDN (Table 1). EN has no effect on T_OUT. __________Applications Information Capacitor Selection The capacitor type used for C1–C4 is not critical for proper operation; polarized or nonpolarized capacitors can be used. The charge pump requires 0.1μF capacitors for 3.3V operation. For other supply voltages, refer to Table 2 for required capacitor values. Do not use values lower than those listed in Table 2. Increasing the capacitor values (e.g., by a factor of 2) reduces ripple on the transmitter outputs and slightly reduces power consumption. C2, C3, and C4 can be increased without changing C1’s value. However, do not increase C1 without also increasing the values of C2, C3, and C4, to maintain the proper ratios (C1 to the other capacitors). When using the minimum required capacitor values, make sure the capacitor value does not degrade excessively with temperature. If in doubt, use capacitors with a higher nominal value. The capacitor’s equivalent series resistance (ESR), which usually rises at low temperatures, influences the amount of ripple on V+ and V-. MAX3237 MAX3241 T1OUT R1OUTB Tx UART VCC T1IN LOGIC TRANSITION DETECTOR R1OUT R1IN EN = VCC SHDN = GND VCC TO μP Rx PREVIOUS RS-232 Tx UART PROTECTION DIODE PROTECTION DIODE SHDN = GND VCC VCC GND Rx 5kΩ a) OLDER RS-232: POWERED-DOWN UART DRAWS CURRENT FROM ACTIVE RECEIVER OUTPUT IN SHUTDOWN. b) NEW MAX3237/MAX3241: EN SHUTS DOWN RECEIVER OUTPUTS (EXCEPT FOR B OUTPUTS), SO NO CURRENT FLOWS TO UART IN SHUTDOWN. B OUTPUTS INDICATE RECEIVER ACTIVITY DURING SHUTDOWN WITH EN HIGH. GND 5kΩ Figure 2. Detection of RS-232 Activity when the UART and Interface are Shut Down; Comparison of MAX3237/MAX3241 (b) with Previous Transceivers (a). MAX3222/MAX3232/MAX3237/MAX3241 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors _______________________________________________________________________________________ 9 Power-Supply Decoupling In most circumstances, a 0.1μF bypass capacitor is adequate. In applications that are sensitive to powersupply noise, decouple VCC to ground with a capacitor of the same value as charge-pump capacitor C1. Connect bypass capacitors as close to the IC as possible. Operation Down to 2.7V Transmitter outputs will meet EIA/TIA-562 levels of ±3.7V with supply voltages as low as 2.7V. Transmitter Outputs when Exiting Shutdown Figure 3 shows two transmitter outputs when exiting shutdown mode. As they become active, the two transmitter outputs are shown going to opposite RS-232 levels (one transmitter input is high, the other is low). Each transmitter is loaded with 3kΩ in parallel with 2500pF. The transmitter outputs display no ringing or undesirable transients as they come out of shutdown. Note that the transmitters are enabled only when the magnitude of V- exceeds approximately 3V. Mouse Driveability The MAX3241 has been specifically designed to power serial mice while operating from low-voltage power supplies. It has been tested with leading mouse brands from manufacturers such as Microsoft and Logitech. The MAX3241 successfully drove all serial mice tested and met their respective current and voltage requirements. Figure 4a shows the transmitter output voltages under increasing load current at 3.0V. Figure 4b shows a typical mouse connection using the MAX3241. Table 1. MAX3222/MAX3237/MAX3241 Shutdown and Enable Control Truth Table Table 2. Required Minimum Capacitor Values 5V/div VCC = 3.3V C1–C4 = 0.1μF 2V/div T2 50μs/div T1 Figure 3. Transmitter Outputs when Exiting Shutdown or Powering Up VCC (V) C1 (μF) 4.5 to 5.5 0.047 3.0 to 5.5 0.1 C2, C3, C4 (μF) MAX3222/MAX3232/MAX3241 0.33 0.47 1 Active 0 1 1 Active SHDN 0 1 High-Z 0 0 High-Z EN T_OUT High-Z Active High-Z Active R_OUT R_OUTB (MAX3237/ MAX3241) Active Active Active Active 3.0 to 3.6 0.22 3.15 to 3.6 0.1 MAX3237 0.22 0.1 4.5 to 5.5 0.047 3.0 to 5.5 0.22 0.33 1.0 3.0 to 3.6 0.1 0.1 MAX3222/MAX3232/MAX3237/MAX3241 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors 10 ______________________________________________________________________________________ MAX3241 23 EN 15 R5OUT 16 R4OUT 17 R3OUT 18 R2OUT 19 R1OUT 20 R2OUTB 21 R1OUTB 5kΩ 5kΩ 5kΩ 5kΩ 5kΩ R5IN 8 R4IN 7 6 R2IN 5 R1IN 4 SHDN 22 GND 25 12 T3IN 13 T2IN 14 T1IN 2 C2- 1 C2+ 24 C1- 28 C1+ T3OUT 11 +V COMPUTER SERIAL PORT MOUSE +V -V GND Tx T2OUT 10 T1OUT 9 V- 3 V+ VCC 27 VCC C4 C1 C3 C2 0.1μF VCC = 3V to 5.5V 26 R3IN Figure 4b. Mouse Driver Test Circuit -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 MAX3222-04 LOAD CURRENT PER TRANSMITTER (mA) TRANSMITTER OUTPUT VOLTAGE (V) VOUT+ VCC = 3.0V VOUTVOUT+ VCC VOUTT1 T2 T3 Figure 4a. MAX3241 Transmitter Output Voltage vs. Load Current per Transmitter MAX3222/MAX3232/MAX3237/MAX3241 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors ______________________________________________________________________________________ 11 High Data Rates The MAX3222/MAX3232/MAX3241 maintain the RS-232 ±5.0V minimum transmitter output voltage even at high data rates. Figure 5 shows a transmitter loopback test circuit. Figure 6 shows a loopback test result at 120kbps, and Figure 7 shows the same test at 235kbps. For Figure 6, all transmitters were driven simultaneously at 120kbps into RS-232 loads in parallel with 1000pF. For Figure 7, a single transmitter was driven at 235kbps, and all transmitters were loaded with an RS-232 receiver in parallel with 1000pF. The MAX3237 maintains the RS-232 ±5.0V minimum transmitter output voltage at data rates up to 1Mbps. Figure 8 shows a loopback test result at 1Mbps with MBAUD = VCC. For Figure 8, all transmitters were loaded with an RS-232 receiver in parallel with 250pF. MAX3222 MAX3232 MAX3237 MAX3241 5kΩ R_ OUT R_ IN EN* C2- C2+ C1- C1+ VV+ VCC C4 C1 C3 C2 0.1μF VCC SHDN* T_ IN T_ OUT GND VCC 0V 1000pF *MAX3222/MAX3237/MAX3241 ONLY T1IN R1OUT VCC = 3.3V T1OUT 5V/div 5V/div 5V/div 5μs/div Figure 5. Loopback Test Circuit Figure 6. MAX3241 Loopback Test Result at 120kbps T1IN R1OUT VCC = 3.3V T1OUT 5V/div 5V/div 2μs/div 5V/div Figure 7. MAX3241 Loopback Test Result at 235kbps +5V 0V +5V 0V -5V +5V 0V T_IN T_OUT = R_IN 5kΩ + 250pF R_OUT 150pF 200ns/div VCC = 3.3V Figure 8. MAX3237 Loopback Test Result at 1000kbps (MBAUD = VCC) MAX3222/MAX3232/MAX3237/MAX3241 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors 12 ______________________________________________________________________________________ __________________________________________________Typical Operating Circuits MAX3222 10 R2OUT 1 13 R1OUT R2IN 9 18 GND 16 RS-232 OUTPUTS TTL/CMOS INPUTS 11 T2IN 12 T1IN C2- 6 5 C2+ 4 C1- 2 C1+ R1IN 14 T2OUT 8 T1OUT 15 V- 7 V+ VCC 3 17 C1 0.1μF C2 0.1μF 0.1μF +3.3V RS-232 INPUTS TTL/CMOS OUTPUTS EN SHDN C3* 0.1μF C4 0.1μF PIN NUMBERS REFER TO DIP/SO PACKAGES. * C3 CAN BE RETURNED TO EITHER VCC OR GROUND. MAX3232 9 R2OUT 12 R1OUT R2IN 8 GND 15 RS-232 OUTPUTS TTL/CMOS INPUTS 10 T2IN 11 T1IN C2- 5 4 C2+ 3 C1- 1 C1+ R1IN 13 T2OUT 7 T1OUT 14 V- 6 V+ VCC 2 C4 0.1μF 16 0.1μF 0.1μF 0.1μF +3.3V RS-232 INPUTS TTL/CMOS OUTPUTS C3* 0.1μF * C3 CAN BE RETURNED TO EITHER VCC OR GROUND. SEE TABLE 2 FOR CAPACITOR SELECTION 5kΩ 5kΩ 5kΩ 5kΩ Interconnection with 3V and 5V Logic The MAX3222/MAX3232/MAX3237/MAX3241 can directly interface with various 5V logic families, including ACT and HCT CMOS. See Table 3 for more information on possible combinations of interconnections. Table 3. Logic-Family Compatibility with Various Supply Voltages Compatible with ACT and HCT CMOS, and with TTL. Incompatible with AC, HC, and CD4000 CMOS. 5 3.3 SYSTEM POWERSUPPLY VOLTAGE (V) Compatible with all TTL and CMOS-logic families. 5 5 Compatible with all CMOS families. 3.3 3.3 COMPATIBILITY MAX32_ _ VCC SUPPLY VOLTAGE (V) MAX3222/MAX3232/MAX3237/MAX3241 _____________________________________Typical Operating Circuits (continued) MAX3241 23 EN 15 R5OUT 16 R4OUT 17 R3OUT 18 R2OUT 19 R1OUT 20 R2OUTB 21 R1OUTB TTL/CMOS OUTPUTS 5kΩ 5kΩ 5kΩ 5kΩ 5kΩ R5IN 8 * C3 CAN BE RETURNED TO EITHER VCC OR GROUND. R4IN 7 R3IN 6 R2IN 5 R1IN 4 RS-232 INPUTS SHDN 22 GND 25 RS-232 OUTPUTS TTL/CMOS INPUTS 12 T3IN 13 T2IN 14 T1IN C2- 2 1 C2+ 24 C1- 28 C1+ T3OUT 11 T2OUT 10 T1OUT 9 V- 3 V+ VCC 27 C4 0.1μF C3* 0.1μF 0.1μF 0.1μF 0.1μF +3.3V 26 MAX3237 13 EN 18 R3OUT 20 R2OUT 21 R1OUT 16 R1OUTB LOGIC OUTPUTS 5kΩ 5kΩ 5kΩ * C3 CAN BE RETURNED TO EITHER VCC OR GROUND. R3IN 11 R2IN 9 R1IN 8 RS-232 INPUTS GND 2 RS-232 OUTPUTS LOGIC INPUTS 22 T3IN 23 T2IN 24 T1IN C2- 3 1 C2+ 25 C1- 28 C1+ T3OUT 7 T2OUT 6 T1OUT 5 T1 T2 T3 R1 R2 R3 V- 4 V+ VCC 27 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF 26 MBAUD 15 17 T5IN 19 T4IN T5OUT 12 T4OUT 10 SHDN 14 T4 T5 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors ______________________________________________________________________________________ 13 MAX3222/MAX3232/MAX3237/MAX3241 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors 14 ______________________________________________________________________________________ _____________________________________________Pin Configurations (continued) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC GND T1OUT C2+ R1IN C1- V+ C1+ MAX3232 R1OUT T1IN T2IN R2IN R2OUT T2OUT VC2- DIP/SO/SSOP/TSSOP + TOP VIEW 20 19 18 17 16 15 14 13 1 2 3 8 12 10 11 4 5 6 7 SHDN VCC GND C1- T1OUT V+ C1+ EN R1IN R1OUT T1IN T2IN T2OUT VC2- C2+ R2IN 9 R2OUT SSOP/TSSOP + N.C. N.C. MAX3222 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C1+ V+ VCC C1- T1IN T2IN MBAUD T3IN R1OUT R2OUT T4IN R3OUT T5IN R1OUTB SHDN EN T5OUT R3IN T4OUT R2IN R1IN T3OUT T2OUT T1OUT VC2- GND C2+ SSOP MAX3237 + 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C1+ V+ VCC GND C1- EN R5OUT SHDN R1OUTB R2OUTB R1OUT R2OUT R3OUT R4OUT T1IN T2IN T3IN T3OUT T2OUT T1OUT R5IN R4IN R3IN R2IN R1IN VC2- C2+ SO/SSOP/TSSOP MAX3241 + MAX3222/MAX3232/MAX3237/MAX3241 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors ______________________________________________________________________________________ 15 ______3V-Powered EIA/TIA-232 and EIA/TIA-562 Transceivers from Maxim Ordering Information (continued) *Dice are tested at TA = +25°C, DC parameters only. +Denotes lead-free package. 0.1μF capacitors, 1 complementary receiver, MegaBaud operation MAX3237 3.0 to 5.5 5/3 3 250/1000 232 0.1μF capacitors, AutoShutdown, complementary receiver, drives mice MAX3243 3.0 to 5.5 3/5 1 120 232 MAX3232 3.0 to 5.5 2/2 N/A 120 232 0.1μF capacitors MAX3223 3.0 to 5.5 2/2 2 120 232 0.1μF capacitors, AutoShutdown MAX3222 3.0 to 5.5 2/2 2 120 232 0.1μF capacitors 232 562 232 562 232 EIA/ TIA-232 OR 562 2.7 to 3.6 AutoShutdown, complementary receiver, drives mice, transient detection MAX3212 3/5 5 235 MAX563 3.0 to 3.6 2/2 2 230 0.1μF capacitors Operates directly from batteries without a voltage regulator MAX218 1.8 to 4.25 2/2 2 120 No. OF RECEIVERS ACTIVE IN SHUTDOWN POWERSUPPLY VOLTAGE (V) MAX562 2.7 to 5.25 3/5 5 230 Wide supply range MAX212 3.0 to 3.6 3/5 5 120 Drives mice FEATURES GUARANTEED DATA RATE (kbps) No. OF TRANSMITTERS/ RECEIVERS PART 0.1μF capacitors, 2 complementary receivers, drives mice MAX3241 3.0 to 5.5 3/5 5 120 232 PART TEMP RANGE PIN-PACKAGE PKG CODE MAX3222EUP+ -40°C to +85°C 20 TSSOP U20+2 MAX3222EAP+ -40°C to +85°C 20 SSOP A20+1 MAX3222EWN+ -40°C to +85°C 18 SO W18+1 MAX3222EPN+ -40°C to +85°C 18 Plastic Dip P18+5 MAX3222C/D 0°C to +70°C Dice* — MAX3232CUE+ 0°C to +70°C 16 TSSOP U16+1 MAX3232CSE+ 0°C to +70°C 16 Narrow SO S16+1 MAX3232CWE+ 0°C to +70°C 16 Wide SO W16+1 MAX3232CPE+ 0°C to +70°C 16 Plastic DIP P16+1 MAX3232EUE+ -40°C to +85°C 16 TSSOP U16+1 MAX3232ESE+ -40°C to +85°C 16 Narrow SO S16+5 PART TEMP RANGE PIN-PACKAGE PKG CODE MAX3232EWE+ -40°C to +85°C 16 Wide SO W16+1 MAX3232EPE+ -40°C to +85°C 16 Plastic DIP P16+1 MAX3232CAE+ 0°C to +70°C 16 SSOP A28+2 MAX3237CAI+ 0°C to +70°C 28 SSOP A28+1 MAX3237ENI+ -40°C to +85°C 28 SSOP A28+1 MAX3241CAI+ 0°C to +70°C 28 SSOP A28+1 MAX3241CWI+ 0°C to +70°C 28 SO W28+6 MAX3241EUI+ -40°C to +85°C 28 TSSOP U28+2 MAX3241EAI+ -40°C to +85°C 28 SSOP A28+1 MAX3241EWI+ -40°C to +85°C 28 SO W28+6 MAX3222/MAX3232/MAX3237/MAX3241 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors 16 ______________________________________________________________________________________ ___________________Chip Topography ___________________Chip Information T2IN T1IN 0.127" (3.225mm) 0.087" (2.209mm) T2OUT R2IN R2OUT R1OUT R1IN T1OUT V+ C1+ VCC SHDN EN C1- C2+ C2- VGND MAX3222 TRANSISTOR COUNT: 339 SUBSTRATE CONNECTED TO GND MAX3222 339 MAX3232 339 MAX3237 1212 MAX3241 894 PART TRANSISTOR COUNT 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 © 2007 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX3222/MAX3232/MAX3237/MAX3241 TSSOP4.40mm.EPS Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Revision History Pages changed at Rev 7: 1, 15, 16, 17 Precision Micropower, Low Dropout Voltage References Data Sheet REF19x Series Rev. L Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1996–2011 Analog Devices, Inc. All rights reserved. FEATURES Temperature coefficient: 5 ppm/°C maximum High output current: 30 mA Low supply current: 45 μA maximum Initial accuracy: ±2 mV maximum1 Sleep mode: 15 μA maximum Low dropout voltage Load regulation: 4 ppm/mA Line regulation: 4 ppm/V Short-circuit protection APPLICATIONS Portable instruments ADCs and DACs Smart sensors Solar powered applications Loop-current-powered instruments GENERAL DESCRIPTION The REF19x series precision band gap voltage references use a patented temperature drift curvature correction circuit and laser trimming of highly stable, thin-film resistors to achieve a very low temperature coefficient and high initial accuracy. The REF19x series is made up of micropower, low dropout voltage (LDV) devices, providing stable output voltage from supplies as low as 100 mV above the output voltage and consuming less than 45 μA of supply current. In sleep mode, which is enabled by applying a low TTL or CMOS level to the SLEEP pin, the output is turned off and supply current is further reduced to less than 15 μA. The REF19x series references are specified over the extended industrial temperature range (−40°C to +85°C) with typical performance specifications over −40°C to +125°C for applications, such as automotive. All electrical grades are available in an 8-lead SOIC package; the PDIP and TSSOP packages are available only in the lowest electrical grade. TEST PINS Test Pin 1 and Test Pin 5 are reserved for in-package Zener zap. To achieve the highest level of accuracy at the output, the Zener zapping technique is used to trim the output voltage. Because each unit may require a different amount of adjustment, the resistance value at the test pins varies widely from pin to pin and from part to part. The user should leave Pin 1 and Pin 5 unconnected. REF19xSERIESTOP VIEW(Not to Scale)TP1VS2SLEEP3GND4NCNCOUTPUTTP876500371-001NOTES1.NC = NO CONNECT.2.TP PINS ARE FACTORY TESTPOINTS, NO USER CONNECTION. Figure 1. 8-Lead SOIC_N and TSSOP Pin Configuration (S Suffix and RU Suffix) REF19xSERIESTOP VIEW(Not to Scale)TP1VS2SLEEP3GND4NCNCOUTPUTTP876500371-002NOTES1.NC = NO CONNECT.2.TP PINS ARE FACTORY TESTPOINTS, NO USER CONNECTION. Figure 2. 8-Lead PDIP Pin Configuration (P Suffix) Table 1. Nominal Output Voltage Part Number Nominal Output Voltage (V) REF191 2.048 REF192 2.50 REF193 3.00 REF194 4.50 REF195 5.00 REF196 3.30 REF198 4.096 1 Initial accuracy does not include shift due to solder heat effect (see the Applications Information section). FEATURES l VERY LOW NOISE: 4.5nV/ÖHz at 10kHz l FAST SETTLING TIME: OPA627—550ns to 0.01% OPA637—450ns to 0.01% l LOW VOS: 100mV max l LOW DRIFT: 0.8mV/°C max l LOW IB: 5pA max l OPA627: Unity-Gain Stable l OPA637: Stable in Gain ³ 5 OPA627 OPA637 DESCRIPTION The OPA627 and OPA637 Difet operational amplifiers provide a new level of performance in a precision FET op amp. When compared to the popular OPA111 op amp, the OPA627/637 has lower noise, lower offset voltage, and much higher speed. It is useful in a broad range of precision and high speed analog circuitry. The OPA627/637 is fabricated on a high-speed, dielectrically- isolated complementary NPN/PNP process. It operates over a wide range of power supply voltage— ±4.5V to ±18V. Laser-trimmed Difet input circuitry provides high accuracy and low-noise performance comparable with the best bipolar-input op amps. High frequency complementary transistors allow increased circuit bandwidth, attaining dynamic performance not possible with previous precision FET op amps. The OPA627 is unity-gain stable. The OPA637 is stable in gains equal to or greater than five. Difet fabrication achieves extremely low input bias currents without compromising input voltage noise performance. Low input bias current is maintained over a wide input common-mode voltage range with unique cascode circuitry. The OPA627/637 is available in plastic DIP, SOIC and metal TO-99 packages. Industrial and military temperature range models are available. Difet ®, Burr-Brown Corp. ® Precision High-Speed Difet ® OPERATIONAL AMPLIFIERS APPLICATIONS l PRECISION INSTRUMENTATION l FAST DATA ACQUISITION l DAC OUTPUT AMPLIFIER l OPTOELECTRONICS l SONAR, ULTRASOUND l HIGH-IMPEDANCE SENSOR AMPS l HIGH-PERFORMANCE AUDIO CIRCUITRY l ACTIVE FILTERS Trim 5 Trim 1 +In 3 –In 2 Output 6 7 +VS –VS 4 ©1989 Burr-Brown Corporation PDS-998H Printed in U.S.A. March, 1998 International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 OPA627 OPA627 SBOS165 2 ® OPA627, 637 SPECIFICATIONS ELECTRICAL At TA = +25°C, and VS = ±15V, unless otherwise noted. OPA627BM, BP, SM OPA627AM, AP, AU OPA637BM, BP, SM OPA637AM, AP, AU PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS OFFSET VOLTAGE (1) Input Offset Voltage 40 100 130 250 mV AP, BP, AU Grades 100 250 280 500 mV Average Drift 0.4 0.8 1.2 2 mV/°C AP, BP, AU Grades 0.8 2 2.5 mV/°C Power Supply Rejection VS = ±4.5 to ±18V 106 120 100 116 dB INPUT BIAS CURRENT (2) Input Bias Current VCM = 0V 1 5 2 10 pA Over Specified Temperature VCM = 0V 1 2 nA SM Grade VCM = 0V 50 nA Over Common-Mode Voltage VCM = ±10V 1 2 pA Input Offset Current VCM = 0V 0.5 5 1 10 pA Over Specified Temperature VCM = 0V 1 2 nA SM Grade 50 nA NOISE Input Voltage Noise Noise Density: f = 10Hz 15 40 20 nV/ÖHz f = 100Hz 8 20 10 nV/ÖHz f = 1kHz 5.2 8 5.6 nV/ÖHz f = 10kHz 4.5 6 4.8 nV/ÖHz Voltage Noise, BW = 0.1Hz to 10Hz 0.6 1.6 0.8 mVp-p Input Bias Current Noise Noise Density, f = 100Hz 1.6 2.5 2.5 fA/ÖHz Current Noise, BW = 0.1Hz to 10Hz 30 60 48 fAp-p INPUT IMPEDANCE Differential 1013 || 8 * W || pF Common-Mode 1013 || 7 * W || pF INPUT VOLTAGE RANGE Common-Mode Input Range ±11 ±11.5 * * V Over Specified Temperature ±10.5 ±11 * * V Common-Mode Rejection VCM = ±10.5V 106 116 100 110 dB OPEN-LOOP GAIN Open-Loop Voltage Gain VO = ±10V, RL = 1kW 112 120 106 116 dB Over Specified Temperature VO = ±10V, RL = 1kW 106 117 100 110 dB SM Grade VO = ±10V, RL = 1kW 100 114 dB FREQUENCY RESPONSE Slew Rate: OPA627 G = –1, 10V Step 40 55 * * V/ms OPA637 G = –4, 10V Step 100 135 * * V/ms Settling Time: OPA627 0.01% G = –1, 10V Step 550 * ns 0.1% G = –1, 10V Step 450 * ns OPA637 0.01% G = –4, 10V Step 450 * ns 0.1% G = –4, 10V Step 300 * ns Gain-Bandwidth Product: OPA627 G = 1 16 * MHz OPA637 G = 10 80 * MHz Total Harmonic Distortion + Noise G = +1, f = 1kHz 0.00003 * % POWER SUPPLY Specified Operating Voltage ±15 * V Operating Voltage Range ±4.5 ±18 * * V Current ±7 ±7.5 * * mA OUTPUT Voltage Output RL = 1kW ±11.5 ±12.3 * * Over Specified Temperature ±11 ±11.5 * * V Current Output VO = ±10V ±45 * mA Short-Circuit Current ±35 +70/–55 ±100 * * * mA Output Impedance, Open-Loop 1MHz 55 * W TEMPERATURE RANGE Specification: AP, BP, AM, BM, AU –25 +85 * * °C SM –55 +125 °C Storage: AM, BM, SM –60 +150 * * °C AP, BP, AU –40 +125 * * °C qJ-A: AM, BM, SM 200 * °C/W AP, BP 100 * °C/W AU 160 °C/W * Specifications same as “B” grade. NOTES: (1) Offset voltage measured fully warmed-up. (2) High-speed test at TJ = +25°C. See Typical Performance Curves for warmed-up performance. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. 3 ® OPA627, 637 PIN CONFIGURATIONS Top View DIP/SOIC Offset Trim –In +In –V No Internal Connection +V Output S Offset Trim S 1 2 3 4 8 7 6 5 Top View TO-99 Offset Trim –In Output +In Offset Trim –VS +VS No Internal Connection Case connected to –VS. 8 1 2 3 4 5 6 7 ABSOLUTE MAXIMUM RATINGS(1) Supply Voltage .................................................................................. ±18V Input Voltage Range .............................................. +VS + 2V to –VS – 2V Differential Input Range ....................................................... Total VS + 4V Power Dissipation ........................................................................ 1000mW Operating Temperature M Package .................................................................. –55°C to +125°C P, U Package ............................................................. –40°C to +125°C Storage Temperature M Package .................................................................. –65°C to +150°C P, U Package ............................................................. –40°C to +125°C Junction Temperature M Package .................................................................................. +175°C P, U Package ............................................................................. +150°C Lead Temperature (soldering, 10s) ............................................... +300°C SOlC (soldering, 3s) ................................................................... +260°C NOTE: (1) Stresses above these ratings may cause permanent damage. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PACKAGE DRAWING TEMPERATURE PRODUCT PACKAGE NUMBER(1) RANGE OPA627AP Plastic DIP 006 –25°C to +85°C OPA627BP Plastic DIP 006 –25°C to +85°C OPA627AU SOIC 182 –25°C to +85°C OPA627AM TO-99 Metal 001 –25°C to +85°C OPA627BM TO-99 Metal 001 –25°C to +85°C OPA627SM TO-99 Metal 001 –55°C to +125°C OPA637AP Plastic DIP 006 –25°C to +85°C OPA637BP Plastic DIP 006 –25°C to +85°C OPA637AU SOIC 182 –25°C to +85°C OPA637AM TO-99 Metal 001 –25°C to +85°C OPA637BM TO-99 Metal 001 –25°C to +85°C OPA637SM TO-99 Metal 001 –55°C to +125°C NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. 4 ® OPA627, 637 TYPICAL PERFORMANCE CURVES At TA = +25°C, and VS = ±15V, unless otherwise noted. INPUT VOLTAGE NOISE SPECTRAL DENSITY 1k 100 10 1 1 Frequency (Hz) Voltage Noise (nV/ Ö Hz) 10 100 1k 10k 100k 1M 10M VOLTAGE NOISE vs SOURCE RESISTANCE Source Resistance ( W ) 1k 100 10 1 100 OPA627 + Resistor Resistor Noise Only Spot Noise at 10kHz Voltage Noise (nV/ Ö Hz) 1k 10k 100k 1M 10M 100M Comparison with OPA27 Bipolar Op Amp + Resistor – + RS OPA627 GAIN/PHASE vs FREQUENCY Phase (Degrees) Gain (dB) 30 20 10 0 –10 –90 –120 –150 –180 –210 1 Phase Gain Frequency (MHz) 10 100 75° Phase Margin OPA637 GAIN/PHASE vs FREQUENCY Phase (Degrees) Gain (dB) 30 20 10 0 –10 –90 –120 –150 –180 –210 1 10 100 Phase Gain Frequency (MHz) TOTAL INPUT VOLTAGE NOISE vs BANDWIDTH 100 10 1 0.1 0.01 1 10 100 1k 10k 100k 1M 10M Bandwidth (Hz) Input Voltage Noise (μV) Noise Bandwidth: 0.1Hz to indicated frequency. RMS p-p OPEN-LOOP GAIN vs FREQUENCY Frequency (Hz) Voltage Gain (dB) 1 10 100 1k 10k 100k 1M 10M 100M 140 120 100 80 60 40 20 0 –20 OPA637 OPA627 5 ® OPA627, 637 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, and VS = ±15V, unless otherwise noted. OPEN-LOOP GAIN vs TEMPERATURE Voltage Gain (dB) Temperature (°C) 125 120 115 110 105 –75 –50 –25 0 25 50 75 100 125 OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY Frequency (Hz) Output Resistance (W) 100 80 60 40 20 0 2 20 200 2k 20k 200k 2M 20M COMMON-MODE REJECTION vs FREQUENCY Frequency (Hz) Common-Mode Rejection Ratio (dB) 140 120 100 80 60 40 20 0 1 10 100 1k 10k 100k 1M 10M OPA627 OPA637 COMMON-MODE REJECTION vs INPUT COMMON MODE VOLTAGE 130 120 110 100 90 80 Common-Mode Rejection (dB) Common-Mode Voltage (V) –15 –10 –5 0 5 10 15 POWER-SUPPLY REJECTION vs FREQUENCY Frequency (Hz) Power-Supply Rejection (dB) 140 120 100 80 60 40 20 0 1 –VS PSRR 627 and 637 +VS PSRR 627 637 10 100 1k 10k 100k 1M 10M POWER-SUPPLY REJECTION AND COMMON-MODE REJECTION vs TEMPERATURE Temperature (°C) CMR and PSR (dB) 125 120 115 110 105 –75 PSR CMR –50 –25 0 25 50 75 100 125 6 ® OPA627, 637 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, and VS = ±15V, unless otherwise noted. SUPPLY CURRENT vs TEMPERATURE Temperature (°C) Supply Current (mA) 8 7.5 7 6.5 6 –75 –50 –25 0 25 50 75 100 125 OUTPUT CURRENT LIMIT vs TEMPERATURE Output Current (mA) 100 80 60 40 20 0 –75 –50 –25 0 25 50 75 100 125 Temperature (°C) –IL at VO = –10V –IL at VO = 0V +IL at VO = +10V +IL at VO = 0V OPA627 GAIN-BANDWIDTH AND SLEW RATE vs TEMPERATURE Temperature (°C) Gain-Bandwidth (MHz) 24 20 16 12 8 –75 Slew Rate GBW 60 55 50 Slew Rate (V/μs) –50 –25 0 25 50 75 100 125 OPA637 GAIN-BANDWIDTH AND SLEW RATE vs TEMPERATURE Temperature (°C) Gain-Bandwidth (MHz) 120 100 80 60 40 –75 Slew Rate (V/μs) 160 140 120 100 80 Slew Rate GBW –50 –25 0 25 50 75 100 125 OPA627 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY Frequency (Hz) THD+N (%) 20 100 1k 10k 20k 0.1 0.01 0.001 0.0001 0.00001 G = +10 G = +1 Measurement BW: 80kHz – + – + 100pF 100pF G = +1 G = +10 VI VI 549 5k 600 600 VO = ±10V VO = ±10V W W W W OPA637 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY Frequency (Hz) THD+N (%) 20 100 1k 10k 20k 1 0.1 0.01 0.001 0.0001 G = +10 G = +50 – + 100pF G = +10 VI 549 5k 600 VO = ±10V W W W – + 100pF G = +50 VI 102 5k 600 VO = ±10V W W W Measurement BW: 80kHz 7 ® OPA627, 637 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, and VS = ±15V, unless otherwise noted. INPUT BIAS AND OFFSET CURRENT vs JUNCTION TEMPERATURE Junction Temperature (°C) Input Current (pA) 10k 1k 100 10 1 0.1 –50 –25 0 25 50 75 100 125 150 IB IOS INPUT BIAS CURRENT vs POWER SUPPLY VOLTAGE Supply Voltage (±VS) Input Bias Current (pA) 20 15 10 5 0 ±4 ±6 ±8 ±10 ±12 ±14 ±16 ±18 NOTE: Measured fully warmed-up. TO-99 with 0807HS Heat Sink TO-99 Plastic DIP, SOIC INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE Common-Mode Voltage (V) Input Bias Current Multiplier 1.2 1.1 1 0.9 0.8 –15 –10 –5 0 5 10 15 Beyond Linear Common-Mode Range Beyond Linear Common-Mode Range INPUT OFFSET VOLTAGE WARM-UP vs TIME Time From Power Turn-On (Min) Offset Voltage Change (μV) 50 25 0 –25 –50 0 1 2 3 4 5 6 MAX OUTPUT VOLTAGE vs FREQUENCY Frequency (Hz) Output Voltage (Vp-p) 30 20 10 0 100k 1M 10M 100M OPA627 OPA637 SETTLING TIME vs CLOSED-LOOP GAIN 100 10 1 0.1 –1 –10 –100 –1000 Closed-Loop Gain (V/V) Settling Time (μs) Error Band: ±0.01% OPA637 OPA627 8 ® OPA627, 637 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, and VS = ±15V, unless otherwise noted. FIGURE 1. Circuits with Noise Gain Less than Five Require the OPA627 for Proper Stability. SETTLING TIME vs ERROR BAND 1500 1000 500 0 0.001 0.01 0.1 1 10 Error Band (%) Settling Time (ns) OPA637 G = –4 OPA627 G = –1 – + CF RI RF 2kW +5V –5V OPA627 OPA637 RI 2kW 500W RF 2kW 2kW CF 6pF 4pF SETTLING TIME vs LOAD CAPACITANCE 0 150 200 300 400 500 Load Capacitance (pF) 3 2 1 0 Settling Time (μs) Error Band: ±0.01% OPA637 G = –4 OPA627 G = –1 APPLICATIONS INFORMATION The OPA627 is unity-gain stable. The OPA637 may be used to achieve higher speed and bandwidth in circuits with noise gain greater than five. Noise gain refers to the closed-loop gain of a circuit as if the non-inverting op amp input were being driven. For example, the OPA637 may be used in a non-inverting amplifier with gain greater than five, or an inverting amplifier of gain greater than four. When choosing between the OPA627 or OPA637, it is important to consider the high frequency noise gain of your circuit configuration. Circuits with a feedback capacitor (Figure 1) place the op amp in unity noise-gain at high frequency. These applications must use the OPA627 for proper stability. An exception is the circuit in Figure 2, where a small feedback capacitance is used to compensate for the input capacitance at the op amp’s inverting input. In this case, the closed-loop noise gain remains constant with frequency, so if the closed-loop gain is equal to five or greater, the OPA637 may be used. – + – + – + – + – + – + Buffer Bandwidth Limiting Integrator Filter RI RF < 4R Inverting Amp G < |–4| RI RF < 4RI Non-Inverting Amp G < 5 OPA627 OPA627 OPA627 OPA627 OPA627 OPA627 9 ® OPA627, 637 – + C2 C1 R2 R1 OPA637 C1 = CIN + CSTRAY C2 = R1 C1 R2 OFFSET VOLTAGE ADJUSTMENT The OPA627/637 is laser-trimmed for low offset voltage and drift, so many circuits will not require external adjustment. Figure 3 shows the optional connection of an external potentiometer to adjust offset voltage. This adjustment should not be used to compensate for offsets created elsewhere in a system (such as in later amplification stages or in an A/D converter) because this could introduce excessive temperature drift. Generally, the offset drift will change by approximately 4mV/°C for 1mV of change in the offset voltage due to an offset adjustment (as shown on Figure 3). FIGURE 2. Circuits with Noise Gain Equal to or Greater than Five May Use the OPA637. amp contributes little additional noise. Below 1kW, op amp noise dominates over the resistor noise, but compares favorably with precision bipolar op amps. CIRCUIT LAYOUT As with any high speed, wide bandwidth circuit, careful layout will ensure best performance. Make short, direct interconnections and avoid stray wiring capacitance—especially at the input pins and feedback circuitry. The case (TO-99 metal package only) is internally connected to the negative power supply as it is with most common op amps. Pin 8 of the plastic DIP, SOIC, and TO-99 packages has no internal connection. Power supply connections should be bypassed with good high frequency capacitors positioned close to the op amp pins. In most cases 0.1mF ceramic capacitors are adequate. The OPA627/637 is capable of high output current (in excess of 45mA). Applications with low impedance loads or capacitive loads with fast transient signals demand large currents from the power supplies. Larger bypass capacitors such as 1mF solid tantalum capacitors may improve dynamic performance in these applications. NOISE PERFORMANCE Some bipolar op amps may provide lower voltage noise performance, but both voltage noise and bias current noise contribute to the total noise of a system. The OPA627/637 is unique in providing very low voltage noise and very low current noise. This provides optimum noise performance over a wide range of sources, including reactive source impedances. This can be seen in the performance curve showing the noise of a source resistor combined with the noise of an OPA627. Above a 2kW source resistance, the op FIGURE 4. Connection of Input Guard for Lowest IB. Board Layout for Input Guarding: Guard top and bottom of board. Alternate—use Teflon® standoff for sensitive input pins. Teflon® E.I. du Pont de Nemours & Co. – + 2 In 3 Non-inverting 6 OPA627 Out – + 2 3 In Inverting 6 OPA627 Out – + 2 In 3 Buffer 6 OPA627 Out 3 2 4 5 6 7 8 No Internal Connection 1 TO-99 Bottom View To Guard Drive – + 2 3 7 1 5 6 +VS –VS OPA627/637 100kW 10kW to 1MW Potentiometer (100kW preferred) ±10mV Typical Trim Range 4 FIGURE 3. Optional Offset Voltage Trim Circuit. 10 ® OPA627, 637 takes approximately 500ns. When the output is driven into the positive limit, recovery takes approximately 6ms. Output recovery of the OPA627 can be improved using the output clamp circuit shown in Figure 5. Diodes at the inverting input prevent degradation of input bias current. INPUT BIAS CURRENT Difet fabrication of the OPA627/637 provides very low input bias current. Since the gate current of a FET doubles approximately every 10°C, to achieve lowest input bias current, the die temperature should be kept as low as possible. The high speed and therefore higher quiescent current of the OPA627/637 can lead to higher chip temperature. A simple press-on heat sink such as the Burr-Brown model 807HS (TO-99 metal package) can reduce chip temperature by approximately 15°C, lowering the IB to one-third its warmed-up value. The 807HS heat sink can also reduce lowfrequency voltage noise caused by air currents and thermoelectric effects. See the data sheet on the 807HS for details. Temperature rise in the plastic DIP and SOIC packages can be minimized by soldering the device to the circuit board. Wide copper traces will also help dissipate heat. The OPA627/637 may also be operated at reduced power supply voltage to minimize power dissipation and temperature rise. Using ±5V power supplies reduces power dissipation to one-third of that at ±15V. This reduces the IB of TO- 99 metal package devices to approximately one-fourth the value at ±15V. Leakage currents between printed circuit board traces can easily exceed the input bias current of the OPA627/637. A circuit board “guard” pattern (Figure 4) reduces leakage effects. By surrounding critical high impedance input circuitry with a low impedance circuit connection at the same potential, leakage current will flow harmlessly to the lowimpedance node. The case (TO-99 metal package only) is internally connected to –VS. Input bias current may also be degraded by improper handling or cleaning. Contamination from handling parts and circuit boards may be removed with cleaning solvents and deionized water. Each rinsing operation should be followed by a 30-minute bake at 85°C. Many FET-input op amps exhibit large changes in input bias current with changes in input voltage. Input stage cascode circuitry makes the input bias current of the OPA627/637 virtually constant with wide common-mode voltage changes. This is ideal for accurate high inputimpedance buffer applications. PHASE-REVERSAL PROTECTION The OPA627/637 has internal phase-reversal protection. Many FET-input op amps exhibit a phase reversal when the input is driven beyond its linear common-mode range. This is most often encountered in non-inverting circuits when the input is driven below –12V, causing the output to reverse into the positive rail. The input circuitry of the OPA627/637 does not induce phase reversal with excessive commonmode voltage, so the output limits into the appropriate rail. OUTPUT OVERLOAD When the inputs to the OPA627/637 are overdriven, the output voltage of the OPA627/637 smoothly limits at approximately 2.5V from the positive and negative power supplies. If driven to the negative swing limit, recovery +VS 5kW (2) HP 5082-2811 1kW 5kW –VS VO Diode Bridge BB: PWS740-3 ZD1 : 10V IN961 Clamps output at VO = ±11.5V RI VI – + RF ZD1 OPA627 FIGURE 5. Clamp Circuit for Improved Overload Recovery. CAPACITIVE LOADS As with any high-speed op amp, best dynamic performance can be achieved by minimizing the capacitive load. Since a load capacitance presents a decreasing impedance at higher frequency, a load capacitance which is easily driven by a slow op amp can cause a high-speed op amp to perform poorly. See the typical curves showing settling times as a function of capacitive load. The lower bandwidth of the OPA627 makes it the better choice for driving large capacitive loads. Figure 6 shows a circuit for driving very large load capacitance. This circuit’s two-pole response can also be used to sharply limit system bandwidth. This is often useful in reducing the noise of systems which do not require the full bandwidth of the OPA627. FIGURE 6. Driving Large Capacitive Loads. R1 – + RF 1kW OPA627 CF G = +1 BW 1MHz 200pF For Approximate Butterworth Response: CF = 2 RO CL RF RF >> RO G = 1+ RF R1 ³ Optional Gain Gain > 1 f–3dB = 1 2p Ö RF RO CF CL CL 5nF RO 20W 11 ® OPA627, 637 INPUT PROTECTION The inputs of the OPA627/637 are protected for voltages between +VS + 2V and –VS – 2V. If the input voltage can exceed these limits, the amplifier should be protected. The diode clamps shown in Figure 7a will prevent the input voltage from exceeding one forward diode voltage drop beyond the power supplies—well within the safe limits. If the input source can deliver current in excess of the maximum forward current of the protection diodes, use a series resistor, RS, to limit the current. Be aware that adding resistance to the input will increase noise. The 4nV/ÖHz theoretical thermal noise of a 1kW resistor will add to the 4.5nV/ÖHz noise of the OPA627/637 (by the square-root of the sum of the squares), producing a total noise of 6nV/ÖHz. Resistors below 100W add negligible noise. Leakage current in the protection diodes can increase the total input bias current of the circuit. The specified maximum leakage current for commonly used diodes such as the 1N4148 is approximately 25nA—more than a thousand times larger than the input bias current of the OPA627/637. Leakage current of these diodes is typically much lower and may be adequate in many applications. Light falling on the junction of the protection diodes can dramatically increase leakage current, so common glass-packaged diodes should be shielded from ambient light. Very low leakage can be achieved by using a diode-connected FET as shown. The 2N4117A is specified at 1pA and its metal case shields the junction from light. Sometimes input protection is required on I/V converters of inverting amplifiers (Figure 7b). Although in normal operation, the voltage at the summing junction will be near zero (equal to the offset voltage of the amplifier), large input transients may cause this node to exceed 2V beyond the power supplies. In this case, the summing junction should be protected with diode clamps connected to ground. Even with the low voltage present at the summing junction, common signal diodes may have excessive leakage current. Since the reverse voltage on these diodes is clamped, a diode-connected signal transistor can be used as an inexpensive low leakage diode (Figure 7b). FIGURE 7. Input Protection Circuits. – + –VS +VS Optional RS VO D: IN4148 — 25nA Leakage 2N4117A — 1pA Leakage (a) = – + IIN VO D D D (b) D D: 2N3904 = NC Siliconix OPA627 OPA627 FPO When used as a unity-gain buffer, large common-mode input voltage steps produce transient variations in input-stage currents. This causes the rising edge to be slower and falling edges to be faster than nominal slew rates observed in higher-gain circuits. (A) (B) LARGE SIGNAL RESPONSE SMALL SIGNAL RESPONSE FIGURE 8. OPA627 Dynamic Performance, G = +1. – + OPA627 G = 1 12 ® OPA627, 637 When driven with a very fast input step (left), common-mode transients cause a slight variation in input stage currents which will reduce output slew rate. If the input step slew rate is reduced (right), output slew rate will increase slightly. FIGURE 9. OPA627 Dynamic Performance, G = –1. NOTE: (1) Optimum value will depend on circuit board layout and stray capacitance at the inverting input. LARGE SIGNAL RESPONSE +10 0 –10 VOUT (V) +10 0 –10 (C) (D) OPA637 LARGE SIGNAL RESPONSE OPA637 SMALL SIGNAL RESPONSE FPO FIGURE 10. OPA637 Dynamic Response, G = 5. –10 0 +10 –100 0 +100 (E) (F) VOUT (V) – + OPA627 G = –1 2kW 2kW 6pF(1) VOUT – + OPA637 G = 5 2kW 500W 4pF(1) VOUT NOTE: (1) Optimum value will depend on circuit board layout and capacitance at inverting input. VOUT (V) VOUT (mV) 13 ® OPA627, 637 OPA627 OPA637 RI, R1 2kW 500W CF 6pF 4pF Error Band ±0.5mV ±0.2mV (0.01%) NOTE: CF is selected for best settling time performance depending on test fixture layout. Once optimum value is determined, a fixed capacitor may be used. FIGURE 12. High Speed Instrumentation Amplifier, Gain = 100. –In +In + – OPA637 Differential Voltage Gain = 1 + 2RF/RG 2 3 – + – + INA105 Differential Amplifier 1 6 5 Output Gain = 100 CMRR 116dB Bandwidth 1MHz OPA637 25kW 25kW 25kW 25kW Input Common-Mode Range = ±5V » » 3pF RF 5kW RF 5kW RG 101W – + ±5V Out +15V 2kW CF 2kW Error Out RI RI 51W –15V HP- 5082- 2835 High Quality Pulse Generator / FIGURE 11. Settling Time and Slew Rate Test Circuit. FIGURE 14. Composite Amplifier for Wide Bandwidth. This composite amplifier uses the OPA603 current-feedback op amp to provide extended bandwidth and slew rate at high closed-loop gain. The feedback loop is closed around the composite amp, preserving the precision input characteristics of the OPA627/637. Use separate power supply bypass capacitors for each op amp. GAIN A1 R1 R2 R3 R4 –3dB SLEW RATE (V/V) OP AMP (W) (kW) (W) (kW) (MHz) (V/ms) 100 OPA627 50.5(1) 4.99 20 1 15 700 1000 OPA637 49.9 4.99 12 1 11 500 NOTE: (1) Closest 1/2% value. *Minimize capacitance at this node. FIGURE 13. High Speed Instrumentation Amplifier, Gain = 1000. + – OPA603 – + A1 R3 R1 R4 R2 VI VO * RL ³ 150W for ±10V Out –In +In + – OPA637 Differential Voltage Gain = (1 + 2RF/RG) • 10 2 3 – + – + INA106 Differential Amplifier 1 6 5 Output Gain = 1000 CMRR 116dB Bandwidth 400kHz OPA637 10kW 10kW 100kW 100kW Input Common-Mode Range = ±10V » » 3pF RF 5kW RF 5kW RG 101W PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples OPA627AM NRND TO-99 LMC 8 20 Green (RoHS & no Sb/Br) AU N / A for Pkg Type OPA627AM OPA627AP ACTIVE PDIP P 8 50 TBD Call TI Call TI OPA627AP OPA627APG4 ACTIVE PDIP P 8 50 TBD Call TI Call TI OPA627AP OPA627AU ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 OPA 627AU OPA627AU/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 OPA 627AU OPA627AU/2K5E4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 OPA 627AU OPA627AUE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 OPA 627AU OPA627AUG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 OPA 627AU OPA627BM NRND TO-99 LMC 8 1 Green (RoHS & no Sb/Br) AU N / A for Pkg Type OPA627BM OPA627BP ACTIVE PDIP P 8 50 TBD Call TI Call TI OPA627BP OPA627BPG4 ACTIVE PDIP P 8 50 TBD Call TI Call TI OPA627BP OPA627SM NRND TO-99 LMC 8 20 Green (RoHS & no Sb/Br) AU N / A for Pkg Type OPA627SM OPA637AM NRND TO-99 LMC 8 20 Green (RoHS & no Sb/Br) AU N / A for Pkg Type OPA637AM OPA637AM2 OBSOLETE TO-99 LMC 8 TBD Call TI Call TI OPA637AP ACTIVE PDIP P 8 50 TBD Call TI Call TI OPA637AP OPA637APG4 ACTIVE PDIP P 8 50 TBD Call TI Call TI OPA637AP OPA637AU ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 OPA 637AU OPA637AU/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 OPA 637AU OPA637AUE4 OBSOLETE SOIC D 8 TBD Call TI Call TI -25 to 85 PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples OPA637AUG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 OPA 637AU OPA637BM NRND TO-99 LMC 8 20 Green (RoHS & no Sb/Br) AU N / A for Pkg Type OPA637BM OPA637BM1 OBSOLETE TO-99 LMC 8 TBD Call TI Call TI OPA637BP ACTIVE PDIP P 8 50 TBD Call TI Call TI OPA637BP OPA637BPG4 ACTIVE PDIP P 8 50 TBD Call TI Call TI OPA637BP OPA637SM NRND TO-99 LMC 8 20 Green (RoHS & no Sb/Br) AU N / A for Pkg Type OPA637SM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 3 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant OPA627AU/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA637AU/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA627AU/2K5 SOIC D 8 2500 367.0 367.0 35.0 OPA637AU/2K5 SOIC D 8 2500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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For small orders, phone 1-800-835-8769. General Description The MAX4661/MAX4662/MAX4663 quad analog switches feature low on-resistance of 2.5½ max. On-resistance is matched between switches to 0.5W max and is flat (0.5W max) over the specified signal range. Each switch can handle Rail-to-Rail® analog signals. Offleakage current is only 5nA max at TA = +85°C. These analog switches are ideal in low-distortion applications and are the preferred solution over mechanical relays in automatic test equipment or applications where current switching is required. They have lower power requirements, use less board space, and are more reliable than mechanical relays. The MAX4661 has four normally closed (NC) switches, and the MAX4662 has four normally open (NO) switches. The MAX4663 has two NC and two NO switches, and features guaranteed break-before-make switching. These devices operate from a single +4.5V to +36V supply or from dual ±4.5V to ±20V supplies. A separate logic supply pin guarantees TTL/CMOS-logic compatibility when operating across the entire supply voltage range. Applications Reed Relay Replacement Avionics Test Equipment ADC Systems Communication Systems Sample-and-Hold Circuits PBX, PABX Systems Data Acquisition Systems Audio-Signal Routing Features © Low On-Resistance (2.5W max) © Guaranteed RON Match Between Channels (0.5W max) © Guaranteed RON Flatness over Specified Signal Range (0.5W max) © Rail-to-Rail Signal Handling © Guaranteed Break-Before-Make (MAX4663) © > 2kV ESD Protection per Method 3015.7 © +4.5V to +36V Single-Supply Operation ±4.5V to ±20V Dual-Supply Operation © TTL/CMOS-Compatible Control Inputs MAX4661/MAX4662/MAX4663 2.5W, Quad, SPST, CMOS Analog Switches ________________________________________________________________ Maxim Integrated Products 1 19-1516; Rev 0; 7/99 PART MAX4661CAE MAX4661CWE MAX4661CPE 0°C to +70°C 0°C to +70°C 0°C to +70°C TEMP. RANGE PIN-PACKAGE 16 SSOP 16 Wide SO 16 Plastic DIP Ordering Information continued at end of data sheet. Ordering Information MAX4661EAE -40°C to +85°C 16 SSOP MAX4661EWE -40°C to +85°C 16 Wide SO MAX4661EPE -40°C to +85°C 16 Plastic DIP SWITCHES SHOWN FOR LOGIC “0” INPUT SSOP/SO/DIP MAX4662 LOGIC SWITCH 0 1 OFF ON TOP VIEW SSOP/SO/DIP MAX4661 LOGIC SWITCH 0 1 ON OFF SSOP/SO/DIP MAX4663 LOGIC SWITCHES 1, 4 0 1 OFF ON SWITCHES 2, 3 ON OFF 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 IN2 COM2 NC2 V- V+ NO1 COM1 IN1 MAX4663 VL NC3 COM3 IN4 IN3 COM4 NO4 GND 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 IN2 COM2 NC2 V- V+ NC1 COM1 IN1 MAX4661 VL NC3 COM3 IN4 IN3 COM4 NC4 GND 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 IN2 COM2 NO2 V- V+ NO1 COM1 IN1 MAX4662 VL NO3 COM3 IN4 IN3 COM4 NO4 GND Pin Configurations/Functional Diagrams/Truth Tables Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. MAX4661/MAX4662/MAX4663 2.5W, Quad, SPST, CMOS Analog Switches 2 _______________________________________________________________________________________ ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. V+ to GND ..............................................................-0.3V to +44V V- to GND ..............................................................+0.3V to -44V V+ to V-...................................................................-0.3V to +44V VL to GND .......................................(GND - 0.3V) to (V+ + 0.3V) All Other Pins to GND (Note 1) .............(V- - 0.3V) to (V+ + 0.3V) Continuous Current (COM_, NO_, NC_) ........................±200mA Peak Current (COM_, NO_, NC_) (pulsed at 1ms, 10% duty cycle)................................ ±300mA Continuous Power Dissipation (TA = +70°C) SSOP (derate 7.1mW/°C above +70°C) .......................571mW Wide SO (derate 9.52mW/°C above +70°C).................762mW Plastic DIP (derate 10.53mW/°C above +70°C) ...........842mW Operating Temperature Ranges MAX466_C_E ......................................................0°C to +70°C MAX466_E_E ....................................................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C -5 5 -5 5 -20 20 TA = TMIN to TMAX V TA = +25°C V- V+ VCOM_, VNO_, VNC_ Input Voltage Range (Note 3) IN_ = 0.8V, all others = 2.4V IN_ = 2.4V, all others = 0.8V ICOM_ = 10mA, VNO_ or VNC_ = ±10V TA = +25°C TA = +25°C TA = +25°C CONDITIONS Logic Input Voltage Low VIN_L 0.8 ½ 0.1 0.5 ÆRON COM_ to NO_ or NC_ On-Resistance Match Between Channels (Notes 3, 4) ½ 1.7 2.5 RON COM_ to NO or NC_ On-Resistance Logic Input Voltage High VIN_H 2.4 V IIN_L -0.5 0.001 0.5 Input Current with Input Voltage Low IIN_H -0.5 0.001 0.5 μA Input Current with Input Voltage High ½ 0.1 0.5 RFLAT(ON) COM_ to NO_ or NC_ On-Resistance Flatness (Notes 3, 5) nA -0.5 0.01 0.5 INO_, INC_ Off-Leakage Current (NO_ or NC_) (Note 6) nA -0.5 0.01 0.5 ICOM_(OFF) COM Off-Leakage Current (Note 6) nA -1 0.01 1 ICOM_(ON) COM On-Leakage Current (Note 6) PARAMETER SYMBOL MIN TYP MAX UNITS ICOM_ = 10mA, VNO_ or VNC_= ±10V ICOM_ = 10mA; VNO_ or VNC_ = -5V, 0, 5V TA = +25°C VCOM_ = ±10V, VNO_ or VNC_= –+ 10V VCOM_ = ±10V, VNO_ or VNC_ = –+ 10V VCOM_ = ±10V, VNO_ or VNC_= ±10V or floating TA = +25°C TA = TMIN to TMAX 2.7 0.6 TA = TMIN to TMAX 0.6 TA = TMIN to TMAX TA = TMIN to TMAX TA = TMIN to TMAX ELECTRICAL CHARACTERISTICS—Dual Supplies (V+ = +15V, V- = -15V, VL = +5V, VIN_H = +2.4V, VIN_L = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) μA V ANALOG SWITCH LOGIC INPUT Note 1: Signals on NC_, NO_, COM_, or IN_ exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current rating. MAX4661/MAX4662/MAX4663 2.5W, Quad, SPST, CMOS Analog Switches _______________________________________________________________________________________ 3 VIN = 0 or 5V μA TA = +25°C -0.5 0.001 0.5 Positive Supply Current I+ TA = +25°C f = 1MHz, Figure 7 RL = 50½, CL = 5pF, f = 1MHz, Figure 6 TA = TMIN to TMAX -5 5 RL = 50½, CL = 5pF, f = 1MHz, Figure 5 VCOM_ = ±10V, Figure 3, TA = +25°C VIN = 0 or 5V TA = +25°C f = 1MHz, Figure 7 CONDITIONS Power-Supply Range ±4.5 ±20.0 V pF dB On-Capacitance CCOM f = 1MHz, Figure 8 250 pF COM_ Off-Capacitance CCOM 55 -0.5 0.001 0.5 Logic Supply Current IL -0.5 0.001 0.5 Negative Supply Current INC_ or NO_ Capacitance COFF pF Crosstalk (Note 8) VCT -59 Off-Isolation (Note 7) VISO -56 dB tOPEN 5 30 ns Break-Before-Make Time (MAX4663 only) -0.5 0.001 0.5 Ground Current IGND 130 275 100 175 PARAMETER SYMBOL MIN TYP MAX UNITS VIN = 0 or 5V VIN = 0 or 5V TA = +25°C TA = TMIN to TMAX -5 5 -5 5 TA = TMIN to TMAX -5 5 ELECTRICAL CHARACTERISTICS—Dual Supplies (continued) (V+ = +15V, V- = -15V, VL = +5V, VIN_H = +2.4V, VIN_L = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) μA μA μA TA = TMIN to TMAX 55 ns 400 Turn-On Time tON VCOM_ = ±10V, Figure 2 ns 300 Turn-Off Time tOFF VCOM_ = ±10V, Figure 2 CL = 1.0nF, VGEN = 0, RGEN = 0, Figure 4 Charge Injection Q 300 pC POWER SUPPLY SWITCH DYNAMIC CHARACTERISTICS TA = +25°C TA = TMIN to TMAX TA = +25°C TA = TMIN to TMAX MAX4661/MAX4662/MAX4663 2.5W, Quad, SPST, CMOS Analog Switches 4 _______________________________________________________________________________________ -5 5 -5 5 -20 20 TA = TMIN to TMAX V TA = +25°C GND V+ VCOM_, VNO_, VNC_ Input Voltage Range (Note 3) IN_ = 0.8V, all others = 2.4V +4.5 +36.0 IN_ = 2.4V, all others = 0.8V ICOM_ = 10mA, VNO_ or VNC_ = 10V TA = +25°C TA = +25°C TA = +25°C CONDITIONS Power-Supply Range VIN = 0 or 5V VIN = 0 or 5V -0.5 0.001 0.5 Logic Supply Current IL μA -0.5 0.001 0.5 Positive Supply Current I+ V μA VIN = 0 or 5V -0.5 0.001 0.5 Ground Current IGND μA TA = +25°C TA = +25°C TA = TMIN to TMAX TA = +25°C TA = TMIN to TMAX TA = TMIN to TMAX -5 5 -5 5 -5 5 Logic Input Voltage Low VIN_L 0.8 ½ 0.03 0.4 ÆRON COM_ to NO_ or NC_ On-Resistance Match Between Channels (Notes 3, 4) ½ 3 4 RON COM_ to NO or NC_ On-Resistance Logic Input Voltage High VIN_H 2.4 V IIN_L -0.5 0.001 0.5 Input Current with Input Voltage Low IIN_H -0.5 0.001 0.5 μA Input Current with Input Voltage High ½ 0.1 0.7 RFLAT(ON) COM_ to NO_ or NC_ On-Resistance Flatness (Notes 3, 5) nA I -0.5 0.01 0.5 NO_ INC_ Off-Leakage Current (NO_ or NC_) (Notes 6, 9) nA -0.5 0.01 0.5 ICOM_(OFF) COM Off-Leakage Current (Notes 6, 9) nA -1 0.01 1 ICOM_(ON) COM On-Leakage Current (Notes 6, 9) PARAMETER SYMBOL MIN TYP MAX UNITS ICOM_ = 10mA, VNO_ or = VNC_= 10V ICOM_ = 10mA; VNO_ or VNC_ = 3V, 6V, 9V TA = +25°C VCOM_ = 1V, 10V; VNO_ or VNC_ = 10V, 1V VNO_ or VNC_ = 10V, 1V; VCOM_ = 1V, 10V VCOM_ = 1V ,10V; VNO_ or VNC_ = 1V, 10V, or floating TA = +25°C TA = TMIN to TMAX 5 0.5 TA = TMIN to TMAX 0.8 TA = TMIN to TMAX TA = TMIN to TMAX TA = TMIN to TMAX ELECTRICAL CHARACTERISTICS—Single Supply (V+ = +12V, V- = 0, VL = +5V, VIN_H = +2.4V, VIN_L = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) μA V ANALOG SWITCH LOGIC INPUT POWER SUPPLY MAX4661/MAX4662/MAX4663 2.5W, Quad, SPST, CMOS Analog Switches _______________________________________________________________________________________ 5 ELECTRICAL CHARACTERISTICS—Single Supply (continued) (V+ = +12V, V- = 0, VL = +5V, VIN_H = +2.4V, VIN_L = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) Note 2: The algebraic convention, where the most negative value is a minimum and the most positive value a maximum, is used in this data sheet. Note 3: Guaranteed by design. Note 4: DRON = RON(MAX) - RON(MIN). Note 5: Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal range. Note 6: Leakage parameters are 100% tested at maximum-rated hot temperature and guaranteed by correlation at +25°C. Note 7: Off-isolation = 20log10 [VCOM / (VNC or VNO)], VCOM = output, VNC or VNO = input to off switch. Note 8: Between any two switches. Note 9: Leakage testing at single supply is guaranteed by testing with dual supplies. 200 400 On-Capacitance CCOM f = 1MHz, Figure 8 140 pF COM Off-Capacitance CCOM f = 1MHz, Figure 7 85 pF NC_ or NO_ Capacitance COFF f = 1MHz, Figure 7 85 pF RL = 50½, CL = 5pF, f = 1MHz, Figure 6 VCOM_ = 10V, Figure 3, TA = +25°C PARAMETER SYMBOL MIN TYP MAX UNITS Crosstalk (Note 8) VCT -60 dB Break-Before-Make Time (MAX4663 only) (Note 3) tOPEN 5 125 ns 100 250 CONDITIONS Turn-On Time (Note 3) tON 500 ns VCOM_ = 10V, Figure 2 VCOM_ = 10V, Figure 2 Turn-Off Time (Note 3) tOFF 350 ns TA = +25°C TA = TMIN to TMAX TA = +25°C TA = TMIN to TMAX CL = 1.0nF, VGEN = 0, RGEN = 0, Figure 4 Charge Injection Q 20 pC SWITCH DYNAMIC CHARACTERISTICS MAX4661/MAX4662/MAX4663 2.5W, Quad, SPST, CMOS Analog Switches 6 _______________________________________________________________________________________ Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) 0 1.0 0.5 2.0 1.5 3.0 2.5 3.5 4.5 4.0 5.0 -20 -15 -10 -5 0 5 10 15 20 ON-RESISTANCE vs. VCOM (DUAL SUPPLIES) MAX4661/2/3-01 VCOM (V) RON (W) V+, V- = ±5V V+, V- = ±15V V+, V- = ±20V 0 0.50 0.25 1.00 0.75 1.50 1.25 1.75 2.25 2.00 2.50 -15 -10 -5 0 5 10 15 ON-RESISTANCE vs. VCOM AND TEMPERATURE (DUAL SUPPLIES) MAX4661/2/3-02 VCOM (V) RON (W) TA = +85°C TA = +25°C V+, V- = ±15V TA = -40°C 0 3 2 1 4 5 6 7 8 9 10 0 2 4 6 8 10 12 14 16 18 20 22 24 ON-RESISTANCE vs. VCOM (SINGLE SUPPLY) MAX4661/2/3-03 VCOM (V) RON (W) V+ = 5V V+ = 12V V+ = 24V 0 1.50 1.00 0.50 2.00 2.50 3.50 3.00 4.00 0 1 2 3 4 5 6 7 8 9 10 11 12 ON-RESISTANCE vs. VCOM AND TEMPERATURE (SINGLE SUPPLY) MAX4661/2/3-04 VCOM (V) RON (W) TA = +85°C TA = +25°C TA = -40°C V+ = +12V V- = GND 0.1m 0.01 1m 10 1 0.1 1k 10k 100 100k -40 -20 0 20 40 60 80 100 ON/OFF-LEAKAGE CURRENT vs. TEMPERATURE MAX4661/2/3-05 TEMPERATURE (°C) LEAKAGE (pA) ON-LEAKAGE OFF-LEAKAGE V+ = +15V V- = -15V -200 0 -100 200 100 300 400 -20 -15 -10 -5 0 5 10 15 20 CHARGE INJECTION vs. VCOM MAX4661/2/3-06 VCOM (V) Q (pC) V- = -15V V+ = +15V V- = GND V+ = 12V 0.1 I+ I- 0.01 0.001 100 10 1 10k 100k 1k -40 -20 0 20 40 60 80 100 POWER-SUPPLY CURRENT vs. TEMPERATURE MAX4661/2/3-07 TEMPERATURE (°C) I+, I- (nA) V+ = +15V V- = -15V -10 -100 0.1 1 10 100 FREQUENCY RESPONSE -70 -90 -30 -50 0 -60 -80 -20 -40 MAX4661/2/3-08 FREQUENCY (MHz) LOSS (dB) 90 180 -720 -450 -630 -90 -270 -360 -540 -0 -180 PHASE (degrees) OFF-ISOLATION ON-PHASE ON-RESPONSE V+ = +15V V- = -15V INPUT = OdBm 50W IN AND OUT MAX4661/MAX4662/MAX4663 2.5W, Quad, SPST, CMOS Analog Switches _______________________________________________________________________________________ 7 NAME FUNCTION MAX4661 1, 16, 9, 8 IN1, IN2, IN3, IN4 Logic-Control Digital Inputs 2, 15, 10, 7 COM1, COM2, COM3, COM4 Analog Switch Common Terminals 3, 14, 11, 6 NC1, NC2, NC3, NC4 Analog Switch Normally Closed Terminals 4 VNegative Analog Supply-Voltage Input. Connect to GND for singlesupply operation. — NC2, NC3 Analog Switch Normally Closed Terminals — NO1, NO4 Analog Switch Normally Open Terminals — NO1, NO2, NO3, NO4 Analog Switch Normally Open Terminals 13 V+ Positive Analog Supply Input 12 VL Logic-Supply Input 5 GND Ground Pin Description MAX4662 1, 16, 9, 8 2, 15, 10, 7 — 4 — — 3, 14, 11, 6 13 12 5 MAX4663 1, 16, 9, 8 PIN 2, 15, 10, 7 — 4 14, 11 3, 6 — 13 12 5 Applications Information Overvoltage Protection Proper power-supply sequencing is recommended for all CMOS devices. Do not exceed the absolute maximum ratings because stresses beyond the listed ratings can cause permanent damage to the devices. Always sequence V+ on first, then V-, followed by the logic inputs, NO, or COM. If power-supply sequencing is not possible, add two small-signal diodes (D1, D2) in series with the supply pins and a Schottky diode between V+ and VL for overvoltage protection (Figure 1). Adding diodes reduces the analog signal range to one diode drop below V+ and one diode drop above V-, but does not affect the devices’ low switch resistance and low leakage characteristics. Device operation is unchanged, and the difference between V+ and Vshould not exceed 44V. Off-Isolation at High Frequencies In 50½ systems, the high-frequency on-response of these parts extends from DC to above 100MHz with a typical loss of -2dB. When the switch is turned off, however, it behaves like a capacitor and off-isolation decreases with increasing frequency. (Above 300MHz, the switch actually passes more signal turned off than turned on.) This effect is more pronounced with higher source and load impedances. Above 5MHz, circuit board layout becomes critical and it becomes difficult to characterize the response of the switch independent of the circuit. The graphs shown in the Typical Operating Characteristics were taken using a 50½ source and load connected with BNC connectors to a circuit board deemed “average”; that is, designed with isolation in mind, but not using stripline or other special RF circuit techniques. For critical applications above 5MHz, use the MAX440, MAX441, and MAX442, which are fully characterized up to 160MHz. COM_ VV+ VL NO_ * INTERNAL PROTECTION DIODES D2 D1 -15V +15V MAX4661 MAX4662 MAX4663 * * * * Figure 1. Overvoltage Protection Using External Blocking Diodes MAX4661/MAX4662/MAX4663 2.5W, Quad, SPST, CMOS Analog Switches 8 _______________________________________________________________________________________ 50% 0.9 · V0UT1 +3V 0V 0V LOGIC INPUT SWITCH OUTPUT 2 (VOUT2) 0V 0.9 · VOUT2 tD tD LOGIC INPUT V- -15V RL2 GND CL INCLUDES FIXTURE AND STRAY CAPACITANCE. COM2 IN1, 2 COM1 VOUT2 V+ +15V CL2 VCOM1 RL1 VOUT1 CL1 RL = 100W CL = 35pF NO NC SWITCH OUTPUT 1 (VOUT1) MAX4663 VCOM2 Figure 3. Break-Before-Make Interval (MAX4663 only) tr < 20ns tf < 20ns 50% 0 LOGIC INPUT V- -15V RL 100W NO_ OR NC_ GND CL INCLUDES FIXTURE AND STRAY CAPACITANCE. VO = VCOM ( RL RL + RON) SWITCH INPUT IN_ +3V tOFF 0 COM_ SWITCH OUTPUT 0.9V0 0.9V0 tON VO SWITCH OUTPUT LOGIC INPUT LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES THAT HAVE THE OPPOSITE LOGIC SENSE. VL V+ CL 35pF +5V +15V VCOM_ VO 0 REPEAT TEST FOR EACH SWITCH. FOR LOAD CONDITIONS, SEE Electrical Characteristics. MAX4661 MAX4662 MAX4663 Figure 2. Switching-Time Test Circuit MAX4661/MAX4662/MAX4663 2.5W, Quad, SPST, CMOS Analog Switches _______________________________________________________________________________________ 9 VGEN GND NC OR NO CL VO -15V VV+ VO VIN OFF ON OFF DVO Q = (DVO)(CL) COM +5V VIN DEPENDS ON SWITCH CONFIGURATION; INPUT POLARITY DETERMINED BY SENSE OF SWITCH. OFF ON OFF VIN VIN = +3V +15V RGEN IN VL MAX4661 MAX4662 MAX4663 Figure 4. Charge-Injection Test Circuit IN 0 OR 3.0V SIGNAL GENERATOR 0dBm +15V VL ANALYZER NC OR NO RL GND COM -15V V- +5V COM V+ MAX4661 MAX4662 MAX4663 Figure 5. Off-Isolation Test Circuit SIGNAL GENERATOR 0dBm +15V ANALYZER N_2 RL GND COM1 V- -15V 3.0V IN1 N_1 VL 50W COM2 +5V IN2 0 OR 3.0V N.C. V+ MAX4661 MAX4662 MAX4663 Figure 6. Crosstalk Test Circuit MAX4661/MAX4662/MAX4663 2.5W, Quad, SPST, CMOS Analog Switches 10 ______________________________________________________________________________________ CAPACITANCE METER NC OR NO COM GND V- -15V IN 0 OR 3.0V +15V VL +5V f = 1MHz V+ MAX4661 MAX4662 MAX4663 Figure 7. Switch Off-Capacitance Test Circuit CAPACITANCE METER NC OR NO COM GND V- -15V IN 0 OR 3.0V +15V VL +5V f = 1MHz V+ MAX4661 MAX4662 MAX4663 Figure 8. Switch On-Capacitance Test Circuit Chip Information TRANSISTOR COUNT: 108 Ordering Information (continued) PART TEMP. RANGE PIN-PACKAGE MAX4662CAE 0°C to +70°C 16 SSOP MAX4662CWE 0°C to +70°C 16 Wide SO MAX4662CPE 0°C to +70°C 16 Plastic DIP MAX4662EAE -40°C to +85°C 16 SSOP MAX4662EWE -40°C to +85°C 16 Wide SO MAX4662EPE -40°C to +85°C 16 Plastic DIP MAX4663CAE 0°C to +70°C 16 SSOP MAX4663CWE 0°C to +70°C 16 Wide SO MAX4663CPE 0°C to +70°C 16 Plastic DIP MAX4663EAE -40°C to +85°C 16 SSOP MAX4663EWE -40°C to +85°C 16 Wide SO MAX4663EPE -40°C to +85°C 16 Plastic DIP MAX4661/MAX4662/MAX4663 2.5W, Quad, SPST, CMOS Analog Switches ______________________________________________________________________________________ 11 Package Information SSOP.EPS MAX4661/MAX4662/MAX46663 2.5W, Quad, SPST, CMOS Analog Switches Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. Package Information (continued) SOICW.EPS Copyright © 2010 Future Technology Devices International Limited 1 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Future Technology Devices International Ltd. FT232R USB UART IC The FT232R is a USB to serial UART interface with the following advanced features: Single chip USB to asynchronous serial data transfer interface. Entire USB protocol handled on the chip. No USB specific firmware programming required. Fully integrated 1024 bit EEPROM storing device descriptors and CBUS I/O configuration. Fully integrated USB termination resistors. Fully integrated clock generation with no external crystal required plus optional clock output selection enabling a glue-less interface to external MCU or FPGA. Data transfer rates from 300 baud to 3 Mbaud (RS422, RS485, RS232 ) at TTL levels. 128 byte receive buffer and 256 byte transmit buffer utilising buffer smoothing technology to allow for high data throughput. FTDI‟s royalty-free Virtual Com Port (VCP) and Direct (D2XX) drivers eliminate the requirement for USB driver development in most cases. Unique USB FTDIChip-ID™ feature. Configurable CBUS I/O pins. Transmit and receive LED drive signals. UART interface support for 7 or 8 data bits, 1 or 2 stop bits and odd / even / mark / space / no parity FIFO receive and transmit buffers for high data throughput. Synchronous and asynchronous bit bang interface options with RD# and WR# strobes. Device supplied pre-programmed with unique USB serial number. Supports bus powered, self powered and high-power bus powered USB configurations. Integrated +3.3V level converter for USB I/O. Integrated level converter on UART and CBUS for interfacing to between +1.8V and +5V logic. True 5V/3.3V/2.8V/1.8V CMOS drive output and TTL input. Configurable I/O pin output drive strength. Integrated power-on-reset circuit. Fully integrated AVCC supply filtering - no external filtering required. UART signal inversion option. +3.3V (using external oscillator) to +5.25V (internal oscillator) Single Supply Operation. Low operating and USB suspend current. Low USB bandwidth consumption. UHCI/OHCI/EHCI host controller compatible. USB 2.0 Full Speed compatible. -40°C to 85°C extended operating temperature range. Available in compact Pb-free 28 Pin SSOP and QFN-32 packages (both RoHS compliant). Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. Future Technology Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product. Your statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminary information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by the publication of this document. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow G41 1HH United Kingdom. Scotland Registered Company Number: SC136640 Copyright © 2010 Future Technology Devices International Limited 2 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 1 Typical Applications USB to RS232/RS422/RS485 Converters Upgrading Legacy Peripherals to USB Cellular and Cordless Phone USB data transfer cables and interfaces Interfacing MCU/PLD/FPGA based designs to USB USB Audio and Low Bandwidth Video data transfer PDA to USB data transfer USB Smart Card Readers USB Instrumentation USB Industrial Control USB MP3 Player Interface USB FLASH Card Reader and Writers Set Top Box PC - USB interface USB Digital Camera Interface USB Hardware Modems USB Wireless Modems USB Bar Code Readers USB Software and Hardware Encryption Dongles 1.1 Driver Support Royalty free VIRTUAL COM PORT (VCP) DRIVERS for... Windows 98, 98SE, ME, 2000, Server 2003, XP and Server 2008 Windows 7 32,64-bit Windows XP and XP 64-bit Windows Vista and Vista 64-bit Windows XP Embedded Windows CE 4.2, 5.0 and 6.0 Mac OS 8/9, OS-X Linux 2.4 and greater Royalty free D2XX Direct Drivers (USB Drivers + DLL S/W Interface) Windows 98, 98SE, ME, 2000, Server 2003, XP and Server 2008 Windows 7 32,64-bit Windows XP and XP 64-bit Windows Vista and Vista 64-bit Windows XP Embedded Windows CE 4.2, 5.0 and 6.0 Linux 2.4 and greater The drivers listed above are all available to download for free from FTDI website (www.ftdichip.com). Various 3rd party drivers are also available for other operating systems - see FTDI website (www.ftdichip.com) for details. For driver installation, please refer to http://www.ftdichip.com/Documents/InstallGuides.htm 1.2 Part Numbers Part Number Package FT232RQ-xxxx 32 Pin QFN FT232RL-xxxx 28 Pin SSOP Note: Packing codes for xxxx is: - Reel: Taped and Reel, (SSOP is 2,000pcs per reel, QFN is 6,000pcs per reel). - Tube: Tube packing, 47pcs per tube (SSOP only) - Tray: Tray packing, 490pcs per tray (QFN only) For example: FT232RQ-Reel is 6,000pcs taped and reel packing Copyright © 2010 Future Technology Devices International Limited 3 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 1.3 USB Compliant The FT232R is fully compliant with the USB 2.0 specification and has been given the USB-IF Test-ID (TID) 40680004 (Rev B) and 40770018 (Rev C). Copyright © 2010 Future Technology Devices International Limited 4 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 2 FT232R Block Diagram Figure 2.1 FT232R Block Diagram For a description of each function please refer to Section 4. x4 ClockMultiplierUARTFIFO ControllerSerial InterfaceEngine( SIE )USBProtocol EngineBaud RateGeneratorUART ControllerwithProgrammableSignal Inversion3.3 VoltLDORegulatorUSBTransceiverwithIntegratedSeriesResistorsand 1.5KPull-upUSB DPLLInternal12MHzOscillator48MHz48MHzOCSI(optional)OSCO(optional)USBDPUSBDM3V3OUTVCCDBUS0DBUS1DBUS2DBUS3DBUS4DBUS5DBUS6DBUS7CBUS0CBUS2CBUS3SLEEP#RESET#TESTGNDResetGenerator3V3OUTCBUS1FIFO RX BufferFIFO TX BufferInternalEEPROMTo USB Transeiver CellCBUS4 Copyright © 2010 Future Technology Devices International Limited 5 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Table of Contents 1 Typical Applications ........................................................................ 2 1.1 Driver Support .................................................................................... 2 1.2 Part Numbers...................................................................................... 2 Note: Packing codes for xxxx is: .................................................................. 2 1.3 USB Compliant .................................................................................... 3 2 FT232R Block Diagram .................................................................... 4 3 Device Pin Out and Signal Description ............................................ 7 3.1 28-LD SSOP Package .......................................................................... 7 3.2 SSOP Package Pin Out Description ...................................................... 7 3.3 QFN-32 Package ............................................................................... 10 3.4 QFN-32 Package Signal Description .................................................. 10 3.5 CBUS Signal Options ......................................................................... 13 4 Function Description ..................................................................... 14 4.1 Key Features ..................................................................................... 14 4.2 Functional Block Descriptions ........................................................... 15 5 Devices Characteristics and Ratings .............................................. 17 5.1 Absolute Maximum Ratings............................................................... 17 5.2 DC Characteristics............................................................................. 18 5.3 EEPROM Reliability Characteristics ................................................... 21 5.4 Internal Clock Characteristics ........................................................... 21 6 USB Power Configurations ............................................................ 23 6.1 USB Bus Powered Configuration ...................................................... 23 6.2 Self Powered Configuration .............................................................. 24 6.3 USB Bus Powered with Power Switching Configuration .................... 25 6.4 USB Bus Powered with Selectable External Logic Supply .................. 26 7 Application Examples .................................................................... 27 7.1 USB to RS232 Converter ................................................................... 27 7.2 USB to RS485 Coverter ..................................................................... 28 7.3 USB to RS422 Converter ................................................................... 29 7.4 USB to MCU UART Interface .............................................................. 30 7.5 LED Interface .................................................................................... 31 7.6 Using the External Oscillator ............................................................ 32 8 Internal EEPROM Configuration .................................................... 33 9 Package Parameters ..................................................................... 35 9.1 SSOP-28 Package Dimensions .......................................................... 35 Copyright © 2010 Future Technology Devices International Limited 6 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 9.2 QFN-32 Package Dimensions ............................................................ 36 9.3 QFN-32 Package Typical Pad Layout ................................................. 37 9.4 QFN-32 Package Typical Solder Paste Diagram ................................. 37 9.5 Solder Reflow Profile ........................................................................ 38 10 Contact Information ................................................................... 39 Appendix A – References ........................................................................... 40 Appendix B - List of Figures and Tables ..................................................... 41 Appendix C - Revision History .................................................................... 43 Copyright © 2010 Future Technology Devices International Limited 7 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 3 Device Pin Out and Signal Description 3.1 28-LD SSOP Package Figure 3.1 SSOP Package Pin Out and Schematic Symbol 3.2 SSOP Package Pin Out Description Note: The convention used throughout this document for active low signals is the signal name followed by a # Pin No. Name Type Description 15 USBDP I/O USB Data Signal Plus, incorporating internal series resistor and 1.5kΩ pull up resistor to 3.3V. 16 USBDM I/O USB Data Signal Minus, incorporating internal series resistor. Table 3.1 USB Interface Group Pin No. Name Type Description 4 VCCIO PWR +1.8V to +5.25V supply to the UART Interface and CBUS group pins (1...3, 5, 6, 9...14, 22, 23). In USB bus powered designs connect this pin to 3V3OUT pin to drive out at +3.3V levels, or connect to VCC to drive out at 5V CMOS level. This pin can also be supplied with an external +1.8V to +2.8V supply in order to drive outputs at lower levels. It should be noted that in this case this supply should originate from the same source as the supply to VCC. This means that in bus powered designs a regulator which is supplied by the +5V on the USB bus should be used. 7, 18, 21 GND PWR Device ground supply pins USBDPUSBDM3V3OUTGNDRESET#VCCGNDNCAGNDTESTOSCIOSCOCBUS1CBUS0TXDRTS#RXDDTR#VCCIORI#GNDNCDSR#DCD#CTS#CBUS4CBUS2CBUS31141528FT232RLAGNDGNDGNDGNDTEST2571821263V3OUTVCCIO417NCRESET#NC24198TXDRXDRTS#CTS#DTR#DSR#DCD#RI#1531129106CBUS0CBUS3CBUS2CBUS123221314201615USBDPUSBDMVCCOSCI27OSCO28CBUS412FTDIFT232RLYYXX-AXXXXXXXXXXXX Copyright © 2010 Future Technology Devices International Limited 8 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Pin No. Name Type Description 17 3V3OUT Output +3.3V output from integrated LDO regulator. This pin should be decoupled to ground using a 100nF capacitor. The main use of this pin is to provide the internal +3.3V supply to the USB transceiver cell and the internal 1.5kΩ pull up resistor on USBDP. Up to 50mA can be drawn from this pin to power external logic if required. This pin can also be used to supply the VCCIO pin. 20 VCC PWR +3.3V to +5.25V supply to the device core. (see Note 1) 25 AGND PWR Device analogue ground supply for internal clock multiplier Table 3.2 Power and Ground Group Pin No. Name Type Description 8, 24 NC NC No internal connection 19 RESET# Input Active low reset pin. This can be used by an external device to reset the FT232R. If not required can be left unconnected, or pulled up to VCC. 26 TEST Input Puts the device into IC test mode. Must be tied to GND for normal operation, otherwise the device will appear to fail. 27 OSCI Input Input 12MHz Oscillator Cell. Optional – Can be left unconnected for normal operation. (see Note 2) 28 OSCO Output Output from 12MHZ Oscillator Cell. Optional – Can be left unconnected for normal operation if internal Oscillator is used. (see Note 2) Table 3.3 Miscellaneous Signal Group Pin No. Name Type Description 1 TXD Output Transmit Asynchronous Data Output. 2 DTR# Output Data Terminal Ready Control Output / Handshake Signal. 3 RTS# Output Request to Send Control Output / Handshake Signal. 5 RXD Input Receiving Asynchronous Data Input. 6 RI# Input Ring Indicator Control Input. When remote wake up is enabled in the internal EEPROM taking RI# low (20ms active low pulse) can be used to resume the PC USB host controller from suspend. 9 DSR# Input Data Set Ready Control Input / Handshake Signal. 10 DCD# Input Data Carrier Detect Control Input. 11 CTS# Input Clear To Send Control Input / Handshake Signal. 12 CBUS4 I/O Configurable CBUS output only Pin. Function of this pin is configured in the device internal EEPROM. Factory default configuration is SLEEP#. See CBUS Signal Options, Table 3.9. 13 CBUS2 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory default configuration is TXDEN. See CBUS Signal Options, Table 3.9. Copyright © 2010 Future Technology Devices International Limited 9 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Pin No. Name Type Description 14 CBUS3 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory default configuration is PWREN#. See CBUS Signal Options, Table 3.9. PWREN# should be used with a 10kΩ resistor pull up. 22 CBUS1 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory default configuration is RXLED#. See CBUS Signal Options, Table 3.9. 23 CBUS0 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory default configuration is TXLED#. See CBUS Signal Options, Table 3.9. Table 3.4 UART Interface and CUSB Group (see note 3) Notes: 1. The minimum operating voltage VCC must be +4.0V (could use VBUS=+5V) when using the internal clock generator. Operation at +3.3V is possible using an external crystal oscillator. 2. For details on how to use an external crystal, ceramic resonator, or oscillator with the FT232R, please refer Section 7.6 3. When used in Input Mode, the input pins are pulled to VCCIO via internal 200kΩ resistors. These pins can be programmed to gently pull low during USB suspend (PWREN# = “1”) by setting an option in the internal EEPROM. Copyright © 2010 Future Technology Devices International Limited 10 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 3.3 QFN-32 Package Figure 3.2 QFN-32 Package Pin Out and schematic symbol 3.4 QFN-32 Package Signal Description Pin No. Name Type Description 14 USBDP I/O USB Data Signal Plus, incorporating internal series resistor and 1.5kΩ pull up resistor to +3.3V. 15 USBDM I/O USB Data Signal Minus, incorporating internal series resistor. Table 3.5 USB Interface Group Pin No. Name Type Description 1 VCCIO PWR +1.8V to +5.25V supply for the UART Interface and CBUS group pins (2, 3, 6,7,8,9,10 11, 21, 22, 30,31,32). In USB bus powered designs connect this pin to 3V3OUT to drive out at +3.3V levels, or connect to VCC to drive out at +5V CMOS level. This pin can also be supplied with an external +1.8V to +2.8V supply in order to drive out at lower levels. It should be noted that in this case this supply should originate from the same source as the supply to VCC. This means that in bus powered designs a regulator which is supplied by the +5V on the USB bus should be used. 4, 17, 20 GND PWR Device ground supply pins. FT232RQ3225241716981YYXX-A1891234567810111213141516171920212223242526272829303132USBDPUSBDM3V3OUTRESET#VCCNCAGNDTESTOSCIOSCOCBUS1CBUS0TXDRTS#RXDDTR#VCCIORI#GNDNCDSR#DCD#CTS#CBUS4CBUS2CBUS3GNDGNDNCNCNCNCIFT232RQAGNDGNDGNDGNDTEST2441720263V3OUTVCCIO116NCRESET#NC231813TXDRXDRTS#CTS#DTR#DSR#DCD#RI#30232831673CBUS0CBUS3CBUS2CBUS122211011191514USBDPUSBDMVCCOSCI27OSCO28CBUS49NC12NC5NC29NC25FTDXXXXXXX Copyright © 2010 Future Technology Devices International Limited 11 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Pin No. Name Type Description 16 3V3OUT Output +3.3V output from integrated LDO regulator. This pin should be decoupled to ground using a 100nF capacitor. The purpose of this output is to provide the internal +3.3V supply to the USB transceiver cell and the internal 1.5kΩ pull up resistor on USBDP. Up to 50mA can be drawn from this pin to power external logic if required. This pin can also be used to supply the VCCIO pin. 19 VCC PWR +3.3V to +5.25V supply to the device core. (See Note 1). 24 AGND PWR Device analogue ground supply for internal clock multiplier. Table 3.6 Power and Ground Group Pin No. Name Type Description 5, 12, 13, 23, 25, 29 NC NC No internal connection. Do not connect. 18 RESET# Input Active low reset. Can be used by an external device to reset the FT232R. If not required can be left unconnected, or pulled up to VCC. 26 TEST Input Puts the device into IC test mode. Must be tied to GND for normal operation, otherwise the device will appear to fail. 27 OSCI Input Input 12MHz Oscillator Cell. Optional – Can be left unconnected for normal operation. (See Note 2). 28 OSCO Output Output from 12MHZ Oscillator Cell. Optional – Can be left unconnected for normal operation if internal Oscillator is used. (See Note 2). Table 3.7 Miscellaneous Signal Group Pin No. Name Type Description 30 TXD Output Transmit Asynchronous Data Output. 31 DTR# Output Data Terminal Ready Control Output / Handshake Signal. 32 RTS# Output Request to Send Control Output / Handshake Signal. 2 RXD Input Receiving Asynchronous Data Input. 3 RI# Input Ring Indicator Control Input. When remote wake up is enabled in the internal EEPROM taking RI# low (20ms active low pulse) can be used to resume the PC USB host controller from suspend. 6 DSR# Input Data Set Ready Control Input / Handshake Signal. 7 DCD# Input Data Carrier Detect Control Input. 8 CTS# Input Clear To Send Control Input / Handshake Signal. 9 CBUS4 I/O Configurable CBUS output only Pin. Function of this pin is configured in the device internal EEPROM. Factory default configuration is SLEEP#. See CBUS Signal Options, Table 3.9. 10 CBUS2 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory default configuration is TXDEN. See CBUS Signal Options, Table 3.9. Copyright © 2010 Future Technology Devices International Limited 12 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Pin No. Name Type Description 11 CBUS3 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory default configuration is PWREN#. See CBUS Signal Options, Table 3.9. PWREN# should be used with a 10kΩ resistor pull up. 21 CBUS1 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory default configuration is RXLED#. See CBUS Signal Options, Table 3.9. 22 CBUS0 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory default configuration is TXLED#. See CBUS Signal Options, Table 3.9. Table 3.8 UART Interface and CBUS Group (see note 3) Notes: 1. The minimum operating voltage VCC must be +4.0V (could use VBUS=+5V) when using the internal clock generator. Operation at +3.3V is possible using an external crystal oscillator. 2. For details on how to use an external crystal, ceramic resonator, or oscillator with the FT232R, please refer to Section 7.6. 3. When used in Input Mode, the input pins are pulled to VCCIO via internal 200kΩ resistors. These pins can be programmed to gently pull low during USB suspend (PWREN# = “1”) by setting an option in the internal EEPROM. Copyright © 2010 Future Technology Devices International Limited 13 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 3.5 CBUS Signal Options The following options can be configured on the CBUS I/O pins. CBUS signal options are common to both package versions of the FT232R. These options can be configured in the internal EEPROM using the software utility FT_PPROG or MPROG, which can be downloaded from the FTDI Utilities (www.ftdichip.com). The default configuration is described in Section 8. CBUS Signal Option Available On CBUS Pin Description TXDEN CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 Enable transmit data for RS485 PWREN# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 Output is low after the device has been configured by USB, then high during USB suspend mode. This output can be used to control power to external logic P-Channel logic level MOSFET switch. Enable the interface pull-down option when using the PWREN# in this way.* TXLED# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 Transmit data LED drive: Data from USB Host to FT232R. Pulses low when transmitting data via USB. See Section 7.5 for more details. RXLED# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 Receive data LED drive: Data from FT232R to USB Host. Pulses low when receiving data via USB. See Section 7.5 for more details. TX&RXLED# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 LED drive – pulses low when transmitting or receiving data via USB. See Section 7.5 for more details. SLEEP# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 Goes low during USB suspend mode. Typically used to power down an external TTL to RS232 level converter IC in USB to RS232 converter designs. CLK48 CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 48MHz ±0.7% Clock output. ** CLK24 CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 24 MHz Clock output.** CLK12 CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 12 MHz Clock output.** CLK6 CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 6 MHz ±0.7% Clock output. ** CBitBangI/O CBUS0, CBUS1, CBUS2, CBUS3 CBUS bit bang mode option. Allows up to 4 of the CBUS pins to be used as general purpose I/O. Configured individually for CBUS0, CBUS1, CBUS2 and CBUS3 in the internal EEPROM. A separate application note, AN232R-01, available from FTDI website (www.ftdichip.com) describes in more detail how to use CBUS bit bang mode. BitBangWRn CBUS0, CBUS1, CBUS2, CBUS3 Synchronous and asynchronous bit bang mode WR# strobe output. BitBangRDn CBUS0, CBUS1, CBUS2, CBUS3 Synchronous and asynchronous bit bang mode RD# strobe output. Table 3.9 CBUS Configuration Control * PWREN# must be used with a 10kΩ resistor pull up. **When in USB suspend mode the outputs clocks are also suspended. Copyright © 2010 Future Technology Devices International Limited 14 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 4 Function Description The FT232R is a USB to serial UART interface device which simplifies USB to serial designs and reduces external component count by fully integrating an external EEPROM, USB termination resistors and an integrated clock circuit which requires no external crystal, into the device. It has been designed to operate efficiently with a USB host controller by using as little as possible of the total USB bandwidth available. 4.1 Key Features Functional Integration. Fully integrated EEPROM, USB termination resistors, clock generation, AVCC filtering, POR and LDO regulator. Configurable CBUS I/O Pin Options. The fully integrated EEPROM allows configuration of the Control Bus (CBUS) functionality, signal inversion and drive strength selection. There are 5 configurable CBUS I/O pins. These configurable options are 1. TXDEN - transmit enable for RS485 designs. 2. PWREN# - Power control for high power, bus powered designs. 3. TXLED# - for pulsing an LED upon transmission of data. 4. RXLED# - for pulsing an LED upon receiving data. 5. TX&RXLED# - which will pulse an LED upon transmission OR reception of data. 6. SLEEP# - indicates that the device going into USB suspend mode. 7. CLK48 / CLK24 / CLK12 / CLK6 - 48MHz, 24MHz, 12MHz, and 6MHz clock output signal options. The CBUS pins can also be individually configured as GPIO pins, similar to asynchronous bit bang mode. It is possible to use this mode while the UART interface is being used, thus providing up to 4 general purpose I/O pins which are available during normal operation. An application note, AN232R-01, available from FTDI website (www.ftdichip.com) describes this feature. The CBUS lines can be configured with any one of these output options by setting bits in the internal EEPROM. The device is supplied with the most commonly used pin definitions pre-programmed - see Section 8 for details. Asynchronous Bit Bang Mode with RD# and WR# Strobes. The FT232R supports FTDI‟s previous chip generation bit-bang mode. In bit-bang mode, the eight UART lines can be switched from the regular interface mode to an 8-bit general purpose I/O port. Data packets can be sent to the device and they will be sequentially sent to the interface at a rate controlled by an internal timer (equivalent to the baud rate pre-scaler). With the FT232R device this mode has been enhanced by outputting the internal RD# and WR# strobes signals which can be used to allow external logic to be clocked by accesses to the bit-bang I/O bus. This option will be described more fully in a separate application note available from FTDI website (www.ftdichip.com). Synchronous Bit Bang Mode. The FT232R supports synchronous bit bang mode. This mode differs from asynchronous bit bang mode in that the interface pins are only read when the device is written to. This makes it easier for the controlling program to measure the response to an output stimulus as the data returned is synchronous to the output data. An application note, AN232R-01, available from FTDI website (www.ftdichip.com) describes this feature. FTDIChip-ID™. The FT232R also includes the new FTDIChip-ID™ security dongle feature. This FTDIChip-ID™ feature allows a unique number to be burnt into each device during manufacture. This number cannot be reprogrammed. This number is only readable over USB and forms a basis of a security dongle which can be used to protect any customer application software being copied. This allows the possibility of using the FT232R in a dongle for software licensing. Further to this, a renewable license scheme can be implemented based on the FTDIChip-ID™ number when encrypted with other information. This encrypted number can be stored in the user area of the FT232R internal EEPROM, and can be decrypted, then compared with the protected FTDIChip-ID™ to verify that a license is valid. Web based applications can be used to maintain product licensing this way. An application note, AN232R-02, available from FTDI website (www.ftdichip.com) describes this feature. The FT232R is capable of operating at a voltage supply between +3.3V and +5V with a nominal operational mode current of 15mA and a nominal USB suspend mode current of 70μA. This allows greater margin for peripheral designs to meet the USB suspend mode current limit of 2.5mA. An integrated level converter within the UART interface allows the FT232R to interface to UART logic running at +1.8V, 2.5V, +3.3V or +5V. Copyright © 2010 Future Technology Devices International Limited 15 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 4.2 Functional Block Descriptions The following paragraphs detail each function within the FT232R. Please refer to the block diagram shown in Figure 2.1 Internal EEPROM. The internal EEPROM in the FT232R is used to store USB Vendor ID (VID), Product ID (PID), device serial number, product description string and various other USB configuration descriptors. The internal EEPROM is also used to configure the CBUS pin functions. The FT232R is supplied with the internal EEPROM pre-programmed as described in Section 8. A user area of the internal EEPROM is available to system designers to allow storing additional data. The internal EEPROM descriptors can be programmed in circuit, over USB without any additional voltage requirement. It can be programmed using the FTDI utility software called MPROG, which can be downloaded from FTDI Utilities on the FTDI website (www.ftdichip.com). +3.3V LDO Regulator. The +3.3V LDO regulator generates the +3.3V reference voltage for driving the USB transceiver cell output buffers. It requires an external decoupling capacitor to be attached to the 3V3OUT regulator output pin. It also provides +3.3V power to the 1.5kΩ internal pull up resistor on USBDP. The main function of the LDO is to power the USB Transceiver and the Reset Generator Cells rather than to power external logic. However, it can be used to supply external circuitry requiring a +3.3V nominal supply with a maximum current of 50mA. USB Transceiver. The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface to the USB cable. The output drivers provide +3.3V level slew rate control signalling, whilst a differential input receiver and two single ended input receivers provide USB data in, Single-Ended-0 (SE0) and USB reset detection conditions respectfully. This function also incorporates the internal USB series termination resistors on the USB data lines and a 1.5kΩ pull up resistor on USBDP. USB DPLL. The USB DPLL cell locks on to the incoming NRZI USB data and generates recovered clock and data signals for the Serial Interface Engine (SIE) block. Internal 12MHz Oscillator - The Internal 12MHz Oscillator cell generates a 12MHz reference clock. This provides an input to the x4 Clock Multiplier function. The 12MHz Oscillator is also used as the reference clock for the SIE, USB Protocol Engine and UART FIFO controller blocks. Clock Multiplier / Divider. The Clock Multiplier / Divider takes the 12MHz input from the Internal Oscillator function and generates the 48MHz, 24MHz, 12MHz and 6MHz reference clock signals. The 48Mz clock reference is used by the USB DPLL and the Baud Rate Generator blocks. Serial Interface Engine (SIE). The Serial Interface Engine (SIE) block performs the parallel to serial and serial to parallel conversion of the USB data. In accordance with the USB 2.0 specification, it performs bit stuffing/un-stuffing and CRC5/CRC16 generation. It also checks the CRC on the USB data stream. USB Protocol Engine. The USB Protocol Engine manages the data stream from the device USB control endpoint. It handles the low level USB protocol requests generated by the USB host controller and the commands for controlling the functional parameters of the UART in accordance with the USB 2.0 specification chapter 9. FIFO RX Buffer (128 bytes). Data sent from the USB host controller to the UART via the USB data OUT endpoint is stored in the FIFO RX (receive) buffer. Data is removed from the buffer to the UART transmit register under control of the UART FIFO controller. (Rx relative to the USB interface). FIFO TX Buffer (256 bytes). Data from the UART receive register is stored in the TX buffer. The USB host controller removes data from the FIFO TX Buffer by sending a USB request for data from the device data IN endpoint. (Tx relative to the USB interface). UART FIFO Controller. The UART FIFO controller handles the transfer of data between the FIFO RX and TX buffers and the UART transmit and receive registers. UART Controller with Programmable Signal Inversion and High Drive. Together with the UART FIFO Controller the UART Controller handles the transfer of data between the FIFO RX and FIFO TX buffers and the UART transmit and receive registers. It performs asynchronous 7 or 8 bit parallel to serial and serial to parallel conversion of the data on the RS232 (or RS422 or RS485) interface. Control signals supported by UART mode include RTS, CTS, DSR, DTR, DCD and RI. The UART Controller also provides a transmitter enable control signal pin option (TXDEN) to assist with interfacing to RS485 transceivers. RTS/CTS, DSR/DTR and XON / XOFF handshaking options are also supported. Handshaking is handled in hardware to ensure fast response times. The UART interface also supports the RS232 BREAK setting and detection conditions. Copyright © 2010 Future Technology Devices International Limited 16 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Additionally, the UART signals can each be individually inverted and have a configurable high drive strength capability. Both these features are configurable in the EEPROM. Baud Rate Generator - The Baud Rate Generator provides a 16x clock input to the UART Controller from the 48MHz reference clock. It consists of a 14 bit pre-scaler and 3 register bits which provide fine tuning of the baud rate (used to divide by a number plus a fraction or “sub-integer”). This determines the baud rate of the UART, which is programmable from 183 baud to 3 Mbaud. The FT232R supports all standard baud rates and non-standard baud rates from 183 Baud up to 3 Mbaud. Achievable non-standard baud rates are calculated as follows - Baud Rate = 3000000 / (n + x) where „n‟ can be any integer between 2 and 16,384 ( = 214 ) and „x’ can be a sub-integer of the value 0, 0.125, 0.25, 0.375, 0.5, 0.625, 0.75, or 0.875. When n = 1, x = 0, i.e. baud rate divisors with values between 1 and 2 are not possible. This gives achievable baud rates in the range 183.1 baud to 3,000,000 baud. When a non-standard baud rate is required simply pass the required baud rate value to the driver as normal, and the FTDI driver will calculate the required divisor, and set the baud rate. See FTDI application note AN232B-05 on the FTDI website (www.ftdichip.com) for more details. RESET Generator - The integrated Reset Generator Cell provides a reliable power-on reset to the device internal circuitry at power up. The RESET# input pin allows an external device to reset the FT232R. RESET# can be tied to VCC or left unconnected if not being used. Copyright © 2010 Future Technology Devices International Limited 17 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 5 Devices Characteristics and Ratings 5.1 Absolute Maximum Ratings The absolute maximum ratings for the FT232R devices are as follows. These are in accordance with the Absolute Maximum Rating System (IEC 60134). Exceeding these may cause permanent damage to the device. Parameter Value Unit Storage Temperature -65°C to 150°C Degrees C Floor Life (Out of Bag) At Factory Ambient (30°C / 60% Relative Humidity) 168 Hours (IPC/JEDEC J-STD-033A MSL Level 3 Compliant)* Hours Ambient Temperature (Power Applied) -40°C to 85°C Degrees C MTTF FT232RL 11162037 hours MTTF FT232RQ 4464815 hours VCC Supply Voltage -0.5 to +6.00 V DC Input Voltage – USBDP and USBDM -0.5 to +3.8 V DC Input Voltage – High Impedance Bidirectionals -0.5 to + (VCC +0.5) V DC Input Voltage – All Other Inputs -0.5 to + (VCC +0.5) V DC Output Current – Outputs 24 mA DC Output Current – Low Impedance Bidirectionals 24 mA Power Dissipation (VCC = 5.25V) 500 mW Table 5.1 Absolute Maximum Ratings * If devices are stored out of the packaging beyond this time limit the devices should be baked before use. The devices should be ramped up to a temperature of +125°C and baked for up to 17 hours. Copyright © 2010 Future Technology Devices International Limited 18 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 5.2 DC Characteristics DC Characteristics (Ambient Temperature = -40°C to +85°C) Parameter Description Minimum Typical Maximum Units Conditions VCC1 VCC Operating Supply Voltage 4.0 --- 5.25 V Using Internal Oscillator VCC1 VCC Operating Supply Voltage 3.3 --- 5.25 V Using External Crystal VCC2 VCCIO Operating Supply Voltage 1.8 --- 5.25 V Icc1 Operating Supply Current --- 15 --- mA Normal Operation Icc2 Operating Supply Current 50 70 100 μA USB Suspend 3V3 3.3v regulator output 3.0 3.3 3.6 V Table 5.2 Operating Voltage and Current Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 3.2 4.1 4.9 V I source = 2mA Vol Output Voltage Low 0.3 0.4 0.6 V I sink = 2mA Vin Input Switching Threshold 1.0 1.2 1.5 V ** VHys Input Switching Hysteresis 20 25 30 mV ** Table 5.3 UART and CBUS I/O Pin Characteristics (VCCIO = +5.0V, Standard Drive Level) Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 2.2 2.7 3.2 V I source = 1mA Vol Output Voltage Low 0.3 0.4 0.5 V I sink = 2mA Vin Input Switching Threshold 1.0 1.2 1.5 V ** VHys Input Switching Hysteresis 20 25 30 mV ** Table 5.4 UART and CBUS I/O Pin Characteristics (VCCIO = +3.3V, Standard Drive Level) Copyright © 2010 Future Technology Devices International Limited 19 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 2.1 2.6 2.8 V I source = 1mA Vol Output Voltage Low 0.3 0.4 0.5 V I sink = 2mA Vin Input Switching Threshold 1.0 1.2 1.5 V ** VHys Input Switching Hysteresis 20 25 30 mV ** Table 5.5 UART and CBUS I/O Pin Characteristics (VCCIO = +2.8V, Standard Drive Level) Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 1.32 1.62 1.8 V I source = 0.2mA Vol Output Voltage Low 0.06 0.1 0.18 V I sink = 0.5mA Vin Input Switching Threshold 1.0 1.2 1.5 V ** VHys Input Switching Hysteresis 20 25 30 mV ** Table 5.6 UART and CBUS I/O Pin Characteristics (VCCIO = +1.8V, Standard Drive Level) Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 3.2 4.1 4.9 V I source = 6mA Vol Output Voltage Low 0.3 0.4 0.6 V I sink = 6mA Vin Input Switching Threshold 1.0 1.2 1.5 V ** VHys Input Switching Hysteresis 20 25 30 mV ** Table 5.7 UART and CBUS I/O Pin Characteristics (VCCIO = +5.0V, High Drive Level) Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 2.2 2.8 3.2 V I source = 3mA Vol Output Voltage Low 0.3 0.4 0.6 V I sink = 8mA Vin Input Switching Threshold 1.0 1.2 1.5 V ** VHys Input Switching Hysteresis 20 25 30 mV ** Table 5.8 UART and CBUS I/O Pin Characteristics (VCCIO = +3.3V, High Drive Level) Copyright © 2010 Future Technology Devices International Limited 20 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 2.1 2.6 2.8 V I source = 3mA Vol Output Voltage Low 0.3 0.4 0.6 V I sink = 8mA Vin Input Switching Threshold 1.0 1.2 1.5 V ** VHys Input Switching Hysteresis 20 25 30 mV ** Table 5.9 UART and CBUS I/O Pin Characteristics (VCCIO = +2.8V, High Drive Level) Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 1.35 1.67 1.8 V I source = 0.4mA Vol Output Voltage Low 0.12 0.18 0.35 V I sink = 3mA Vin Input Switching Threshold 1.0 1.2 1.5 V ** VHys Input Switching Hysteresis 20 25 30 mV ** Table 5.10 UART and CBUS I/O Pin Characteristics (VCCIO = +1.8V, High Drive Level) ** Only input pins have an internal 200KΩ pull-up resistor to VCCIO Parameter Description Minimum Typical Maximum Units Conditions Vin Input Switching Threshold 1.3 1.6 1.9 V VHys Input Switching Hysteresis 50 55 60 mV Table 5.11 RESET# and TEST Pin Characteristics Copyright © 2010 Future Technology Devices International Limited 21 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Parameter Description Minimum Typical Maximum Units Conditions UVoh I/O Pins Static Output (High) 2.8 3.6 V RI = 1.5kΩ to 3V3OUT (D+) RI = 15KΩ to GND (D-) UVol I/O Pins Static Output (Low) 0 0.3 V RI = 1.5kΩ to 3V3OUT (D+) RI = 15kΩ to GND (D-) UVse Single Ended Rx Threshold 0.8 2.0 V UCom Differential Common Mode 0.8 2.5 V UVDif Differential Input Sensitivity 0.2 V UDrvZ Driver Output Impedance 26 29 44 Ohms See Note 1 Table 5.12 USB I/O Pin (USBDP, USBDM) Characteristics 5.3 EEPROM Reliability Characteristics The internal 1024 Bit EEPROM has the following reliability characteristics: Parameter Value Unit Data Retention 10 Years Read / Write Cycle 10,000 Cycles Table 5.13 EEPROM Characteristics 5.4 Internal Clock Characteristics The internal Clock Oscillator has the following characteristics: Parameter Value Unit Minimum Typical Maximum Frequency of Operation (see Note 1) 11.98 12.00 12.02 MHz Clock Period 83.19 83.33 83.47 ns Duty Cycle 45 50 55 % Table 5.14 Internal Clock Characteristics Note 1: Equivalent to +/-1667ppm Copyright © 2010 Future Technology Devices International Limited 22 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 2.1 2.8 3.2 V I source = 3mA Vol Output Voltage Low 0.3 0.4 0.6 V I sink = 8mA Vin Input Switching Threshold 1.0 1.2 1.5 V Table 5.15 OSCI, OSCO Pin Characteristics – see Note 1 Note1: When supplied, the FT232R is configured to use its internal clock oscillator. These characteristics only apply when an external oscillator or crystal is used. Copyright © 2010 Future Technology Devices International Limited 23 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 6 USB Power Configurations The following sections illustrate possible USB power configurations for the FT232R. The illustrations have omitted pin numbers for ease of understanding since the pins differ between the FT232RL and FT232RQ package options. All USB power configurations illustrated apply to both package options for the FT232R device. Please refer to Section 3 for the package option pin-out and signal descriptions. 6.1 USB Bus Powered Configuration Figure 6.1 Bus Powered Configuration Figure 6.1 Illustrates the FT232R in a typical USB bus powered design configuration. A USB bus powered device gets its power from the USB bus. Basic rules for USB bus power devices are as follows – i) On plug-in to USB, the device should draw no more current than 100mA. ii) In USB Suspend mode the device should draw no more than 2.5mA. iii) A bus powered high power USB device (one that draws more than 100mA) should use one of the CBUS pins configured as PWREN# and use it to keep the current below 100mA on plug-in and 2.5mA on USB suspend. iv) A device that consumes more than 100mA cannot be plugged into a USB bus powered hub. v) No device can draw more than 500mA from the USB bus. The power descriptors in the internal EEPROM of the FT232R should be programmed to match the current drawn by the device. A ferrite bead is connected in series with the USB power supply to reduce EMI noise from the FT232R and associated circuitry being radiated down the USB cable to the USB host. The value of the Ferrite Bead depends on the total current drawn by the application. A suitable range of Ferrite Beads is available from Steward (www.steward.com), for example Steward Part # MI0805K400R-10. Note: If using PWREN# (available using the CBUS) the pin should be pulled to VCCIO using a 10kΩ resistor. FT232RAGNDGNDGNDGNDTEST100nF3V3OUTVCCIONCRESET#NC+100nF10nFVccTXDRXDRTS#CTS#DTR#DSR#DCD#RI#CBUS0CBUS3CBUS2CBUS1USBDPUSBDMVCC12345OSCIOSCOCBUS4FerriteBead+4.7uFSHIELDGNDGNDGNDGNDVcc Copyright © 2010 Future Technology Devices International Limited 24 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 6.2 Self Powered Configuration Figure 6.2 Self Powered Configuration Figure 6.2 illustrates the FT232R in a typical USB self powered configuration. A USB self powered device gets its power from its own power supply, VCC, and does not draw current from the USB bus. The basic rules for USB self powered devices are as follows – i) A self powered device should not force current down the USB bus when the USB host or hub controller is powered down. ii) A self powered device can use as much current as it needs during normal operation and USB suspend as it has its own power supply. iii) A self powered device can be used with any USB host, a bus powered USB hub or a self powered USB hub. The power descriptor in the internal EEPROM of the FT232R should be programmed to a value of zero (self powered). In order to comply with the first requirement above, the USB bus power (pin 1) is used to control the RESET# pin of the FT232R device. When the USB host or hub is powered up an internal 1.5kΩ resistor on USBDP is pulled up to +3.3V (generated using the 4K7 and 10k resistor network), thus identifying the device as a full speed device to the USB host or hub. When the USB host or hub is powered off, RESET# will be low and the FT232R is held in reset. Since RESET# is low, the internal 1.5kΩ resistor is not pulled up to any power supply (hub or host is powered down), so no current flows down USBDP via the 1.5kΩ pull-up resistor. Failure to do this may cause some USB host or hub controllers to power up erratically. Figure 6.2 illustrates a self powered design which has a +4V to +5.25V supply. Note: 1. When the FT232R is in reset, the UART interface I/O pins are tri-stated. Input pins have internal 200kΩ pull-up resistors to VCCIO, so they will gently pull high unless driven by some external logic. 2. When using internal FT232R oscillator the VCC supply voltage range must be +4.0V to 5.25V. 3. When using external oscillator the VCC supply voltage range must be +3.3V to 5.25V Any design which interfaces to +3.3 V or +1.8V would be having a +3.3V or +1.8V supply to VCCIO. Copyright © 2010 Future Technology Devices International Limited 25 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 6.3 USB Bus Powered with Power Switching Configuration FT232R GND GND 100nF VCC USBDM USBDP VCCIO NC RESET# NC OSCI OSCO 3V3OUT A G N D G N D G N D G N D T E S T TXD RXD RTS# CTS# DTR# DSR# DCD# RI# CBUS0 CBUS1 CBUS2 CBUS3 CBUS4 1 2 3 4 GND SHIELD GND 100nF 4.7uF + 5 10nF + Ferrite Bead s d g P-Channel Power MOSFET PWREN# 1K Switched 5V Power To External Logic Soft Start Circuit 0.1uF 0.1uF 5V VCC 5V VCC 5V VCC 10K Figure 6.3 Bus Powered with Power Switching Configuration A requirement of USB bus powered applications, is when in USB suspend mode, the application draws a total current of less than 2.5mA. This requirement includes external logic. Some external logic has the ability to power itself down into a low current state by monitoring the PWREN# signal. For external logic that cannot power itself down in this way, the FT232R provides a simple but effective method of turning off power during the USB suspend mode. Figure 6.3 shows an example of using a discrete P-Channel MOSFET to control the power to external logic. A suitable device to do this is an International Rectifier (www.irf.com) IRLML6402, or equivalent. It is recommended that a “soft start” circuit consisting of a 1kΩ series resistor and a 0.1μF capacitor is used to limit the current surge when the MOSFET turns on. Without the soft start circuit it is possible that the transient power surge, caused when the MOSFET switches on, will reset the FT232R or the USB host/hub controller. The soft start circuit example shown in Figure 6.3 powers up with a slew rate of approximaely12.5V/ms. Thus supply voltage to external logic transitions from GND to +5V in approximately 400 microseconds. As an alternative to the MOSFET, a dedicated power switch IC with inbuilt “soft-start” can be used. A suitable power switch IC for such an application is the Micrel (www.micrel.com) MIC2025-2BM or equivalent. With power switching controlled designs the following should be noted: i) The external logic to which the power is being switched should have its own reset circuitry to automatically reset the logic when power is re-applied when moving out of suspend mode. ii) Set the Pull-down on Suspend option in the internal FT232R EEPROM. iii) One of the CBUS Pins should be configured as PWREN# in the internal FT232R EEPROM, and used to switch the power supply to the external circuitry. This should be pulled high through a 10 kΩ resistor. iv) For USB high-power bus powered applications (one that consumes greater than 100mA, and up to 500mA of current from the USB bus), the power consumption of the application must be set in the Max Power field in the internal FT232R EEPROM. A high-power bus powered application uses the descriptor in the internal FT232R EEPROM to inform the system of its power requirements. v) PWREN# gets its VCC from VCCIO. For designs using 3V3 logic, ensure VCCIO is not powered down using the external logic. In this case use the +3V3OUT. Copyright © 2010 Future Technology Devices International Limited 26 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 6.4 USB Bus Powered with Selectable External Logic Supply FT232R A G N D G N D G N D G N D T E S T 100nF 3V3OUT VCCIO NC RESET# NC 10nF TXD RXD RTS# CTS# DTR# DSR# DCD# RI# CBUS0 CBUS3 CBUS2 CBUS1 USBDP USBDM 1 VCC 2 3 4 5 OSCI OSCO CBUS4 Ferrite Bead + SHIELD GND GND GND 3.3V or 5V Supply to External Logic 100nF + 100nF Vcc 4.7uF GND 1 Jumper SLEEP# PWREN# 2 3 Vcc VCCIO 10K VCCIO Figure 6.4 USB Bus Powered with +3.3V or +5V External Logic Power Supply Figure 6.4 illustrates a USB bus power application with selectable external logic supply. The external logic can be selected between +3.3V and +5V using the jumper switch. This jumper is used to allow the FT232R to be interfaced with a +3.3V or +5V logic devices. The VCCIO pin is either supplied with +5V from the USB bus (jumper pins1 and 2 connected), or from the +3.3V output from the FT232R 3V3OUT pin (jumper pins 2 and 3 connected). The supply to VCCIO is also used to supply external logic. With bus powered applications, the following should be noted: i) To comply with the 2.5mA current supply limit during USB suspend mode, PWREN# or SLEEP# signals should be used to power down external logic in this mode. If this is not possible, use the configuration shown in Section 6.3. ii) The maximum current sourced from the USB bus during normal operation should not exceed 100mA, otherwise a bus powered design with power switching (Section 6.3) should be used. Another possible configuration could use a discrete low dropout (LDO) regulator which is supplied by the 5V on the USB bus to supply between +1.8V and +2.8V to the VCCIO pin and to the external logic. In this case VCC would be supplied with the +5V from the USB bus and the VCCIO would be supplied from the output of the LDO regulator. This results in the FT232R I/O pins driving out at between +1.8V and +2.8V logic levels. For a USB bus powered application, it is important to consider the following when selecting the regulator: i) The regulator must be capable of sustaining its output voltage with an input voltage of +4.35V. An Low Drop Out (LDO) regulator should be selected. ii) The quiescent current of the regulator must be low enough to meet the total current requirement of <= 2.5mA during USB suspend mode. A suitable series of LDO regulators that meets these requirements is the MicroChip/Telcom (www.microchip.com) TC55 series of devices. These devices can supply up to 250mA current and have a quiescent current of under 1μA. Copyright © 2010 Future Technology Devices International Limited 27 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 7 Application Examples The following sections illustrate possible applications of the FT232R. The illustrations have omitted pin numbers for ease of understanding since the pins differ between the FT232RL and FT232RQ package options. 7.1 USB to RS232 Converter FT232R GND GND 100nF VCC USBDM USBDP VCCIO NC RESET# NC OSCI OSCO 3V3OUT A G N D G N D G N D G N D T E S T TXD RXD RTS# CTS# DTR# DSR# DCD# RI# CBUS0 CBUS1 CBUS2 CBUS3 CBUS4 1 2 3 4 GND SHIELD GND 100nF 4.7uF + 5 10nF + Ferrite Bead VCC VCC SLEEP# GPIO2 GPIO3 TXD RXD RTS# CTS# DTR# DSR# DCD# RI# RS232 LEVEL CONVERTER TXDATA RXDATA RTS CTS DTR DSR DCD RI TXLED# RXLED# VCC VCC 270R 270R GND RI DTR CTS TXDATA RTS RXDATA DSR DCD DB9M SHIELD 10 5 9 48 3 7 2 6 1 SHDN# Figure 7.1 Application Example showing USB to RS232 Converter An example of using the FT232R as a USB to RS232 converter is illustrated in Figure 7.1. In this application, a TTL to RS232 Level Converter IC is used on the serial UART interface of the FT232R to convert the TTL levels of the FT232R to RS232 levels. This level shift can be done using the popular “213” series of TTL to RS232 level converters. These “213” devices typically have 4 transmitters and 5 receivers in a 28-LD SSOP package and feature an in-built voltage converter to convert the +5V (nominal) VCC to the +/- 9 volts required by RS232. A useful feature of these devices is the SHDN# pin which can be used to power down the device to a low quiescent current during USB suspend mode. A suitable level shifting device is the Sipex SP213EHCA which is capable of RS232 communication at up to 500k baud. If a lower baud rate is acceptable, then several pin compatible alternatives are available such as the Sipex SP213ECA, the Maxim MAX213CAI and the Analogue Devices ADM213E, which are all suitable for communication at up to 115.2k baud. If a higher baud rate is required, the Maxim MAX3245CAI device is capable of RS232 communication rates up to 1Mbaud. Note that the MAX3245 is not pin compatible with the 213 series devices and that the SHDN pin on the MAX device is active high and should be connect to PWREN# pin instead of SLEEP# pin. In example shown, the CBUS0 and CBUS1 have been configured as TXLED# and RXLED# and are being used to drive two LEDs. Copyright © 2010 Future Technology Devices International Limited 28 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 7.2 USB to RS485 Coverter FT232R GND GND 100nF VCC USBDM USBDP VCCIO NC RESET# NC OSCI OSCO 3V3OUT A G N D G N D G N D G N D T E S T TXD RXD RTS# CTS# DTR# DSR# DCD# RI# CBUS0 CBUS1 CBUS2 CBUS3 CBUS4 1 2 3 4 GND SHIELD GND 100nF 4.7uF + 5 10nF + Ferrite Bead Vcc Vcc TXD RXD GND DB9M SHIELD 10 TXDEN GPO PWREN# GPIO0 GPIO1 VCCIO 10K RS485 LEVEL CONVERTER Vcc SP481 5 1 2 3 4 Link 120R 7 6 Figure 7.2 Application Example Showing USB to RS485 Converter An example of using the FT232R as a USB to RS485 converter is shown in Figure 7.2. In this application, a TTL to RS485 level converter IC is used on the serial UART interface of the FT232R to convert the TTL levels of the FT232R to RS485 levels. This example uses the Sipex SP481 device. Equivalent devices are available from Maxim and Analogue Devices. The SP481 is a RS485 device in a compact 8 pin SOP package. It has separate enables on both the transmitter and receiver. With RS485, the transmitter is only enabled when a character is being transmitted from the UART. The TXDEN signal CBUS pin option on the FT232R is provided for exactly this purpose and so the transmitter enable is wired to CBUS2 which has been configured as TXDEN. Similarly, CBUS3 has been configured as PWREN#. This signal is used to control the SP481‟s receiver enable. The receiver enable is active low, so it is wired to the PWREN# pin to disable the receiver when in USB suspend mode. CBUS2 = TXDEN and CBUS3 = PWREN# are the default device configurations of the FT232R pins. RS485 is a multi-drop network; so many devices can communicate with each other over a two wire cable interface. The RS485 cable requires to be terminated at each end of the cable. A link (which provides the 120Ω termination) allows the cable to be terminated if the SP481 is physically positioned at either end of the cable. In this example the data transmitted by the FT232R is also present on the receive path of the SP481.This is a common feature of RS485 and requires the application software to remove the transmitted data from the received data stream. With the FT232R it is possible to do this entirely in hardware by modifying the example shown in Figure 7.2 by logically OR‟ing the FT232R TXDEN and the SP481 receiver output and connecting the output of the OR gate to the RXD of the FT232R. Note that the TXDEN is activated 1 bit period before the start bit. TXDEN is deactivated at the same time as the stop bit. This is not configurable. Copyright © 2010 Future Technology Devices International Limited 29 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 7.3 USB to RS422 Converter FT232R GND GND 100nF VCC USBDM USBDP VCCIO NC RESET# NC OSCI OSCO 3V3OUT A G N D G N D G N D G N D T E S T TXD RXD RTS# CTS# DTR# DSR# DCD# RI# CBUS0 CBUS1 CBUS2 CBUS3 CBUS4- 1 2 3 4 GND SHIELD GND 100nF 4.7uF + 5 10nF + Ferrite Bead Vcc Vcc PWREN# RS422 LEVEL CONVERTER Vcc SP491 5 3 4 6 7 TXDM TXDP RXDP RXDM 120R 10 9 11 12 SLEEP# RS422 LEVEL CONVERTER SP491 3 4 6 7 Vcc Vcc 10K 2 5 120R 11 12 9 10 RTSM RTSP CTSP CTSM GND DB9M SHIELD TXDM TXDP RXDP RXDM RTSM RTSP CTSP CTSM 2 Figure 7.3 USB to RS422 Converter Configuration An example of using the FT232R as a USB to RS422 converter is shown in Figure 7.3. In this application, two TTL to RS422 Level Converter ICs are used on the serial UART interface of the FT232R to convert the TTL levels of the FT232R to RS422 levels. There are many suitable level converter devices available. This example uses Sipex SP491 devices which have enables on both the transmitter and receiver. Since the SP491 transmitter enable is active high, it is connected to a CBUS pin in SLEEP# configuration. The SP491 receiver enable is active low and is therefore connected to a CBUS pin PWREN# configuration. This ensures that when both the SP491 transmitters and receivers are enabled then the device is active, and when the device is in USB suspend mode, the SP491 transmitters and receivers are disabled. If a similar application is used, but the design is USB BUS powered, it may be necessary to use a P-Channel logic level MOSFET (controlled by PWREN#) in the VCC line of the SP491 devices to ensure that the USB standby current of 2.5mA is met. The SP491 is specified to transmit and receive data at a rate of up to 5 Mbaud. In this example the maximum data rate is limited to 3 Mbaud by the FT232R. Copyright © 2010 Future Technology Devices International Limited 30 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 7.4 USB to MCU UART Interface FT232R GND GND 100nF VCC USBDM USBDP VCCIO NC RESET# NC OSCI OSCO 3V3OUT A G N D G N D G N D G N D T E S T TXD RXD RTS# CTS# DTR# DSR# DCD# RI# CBUS0 CBUS1 CBUS2 CBUS3 CBUS4 1 2 3 4 GND SHIELD GND 100nF 4.7uF + 5 10nF + Ferrite Bead Vcc Vcc PWREN# Vcc 12MHz OUT 10K Microcontroller CLK_IN I/O RTS# RXD TXD CTS# Vcc Figure 7.4 USB to MCU UART Interface An example of using the FT232R as a USB to Microcontroller (MCU) UART interface is shown in Figure 7.4. In this application the FT232R uses TXD and RXD for transmission and reception of data, and RTS# / CTS# signals for hardware handshaking. Also in this example CBUS0 has been configured as a 12MHz output to clock the MCU. Optionally, RI# could be connected to another I/O pin on the MCU and used to wake up the USB host controller from suspend mode. If the MCU is handling power management functions, then a CBUS pin can be configured as PWREN# and would also be connected to an I/O pin of the MCU. Copyright © 2010 Future Technology Devices International Limited 31 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 7.5 LED Interface Any of the CBUS I/O pins can be configured to drive an LED. The FT232R has 3 configuration options for driving LEDs from the CBUS. These are TXLED#, RXLED#, and TX&RXLED#. Refer to Section 3.5 for configuration options. FT232R CBUS[0...4] CBUS[0...4] VCCIO TX TXLED# RXLED# RX 270R 270R Figure 7.5 Dual LED Configuration An example of using the FT232R to drive LEDs is shown in Figure 7.5. In this application one of the CBUS pins is used to indicate transmission of data (TXLED#) and another is used to indicate receiving data (RXLED#). When data is being transmitted or received the respective pins will drive from tri-state to low in order to provide indication on the LEDs of data transfer. A digital one-shot is used so that even a small percentage of data transfer is visible to the end user. FT232R CBUS[0...4] TX&RXLED# 270R VCCIO LED Figure 7.6 Single LED Configuration Another example of using the FT232R to drive LEDs is shown in Figure 7.6. In this example one of the CBUS pins is used to indicate when data is being transmitted or received by the device (TX&RXLED). In this configuration the FT232R will drive only a single LED. Copyright © 2010 Future Technology Devices International Limited 32 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 7.6 Using the External Oscillator The FT232R defaults to operating using its own internal oscillator. This requires that the device is powered with VCC(min)=+4.0V. This supply voltage can be taken from the USB VBUS. Applications which require using an external oscillator, VCC= +3.3V, must do so in the following order: 1. When device powered for the very first time, it must have VCC > +4.0V. This supply is available from the USB VBUS supply = +5.0V. 2. The EEPROM must then be programmed to enable external oscillator. This EEPROM modification cannot be done using the FTDI programming utility, MPROG. The EEPROM can only be re-configured from a custom application. Please refer to the following applications note on how to do this: http://www.ftdichip.com/Documents/AppNotes/AN_100_Using_The_FT232_245R_With_External_Osc(FT_000067).pdf 3. The FT232R can then be powered from VCC=+3.3V and an external oscillator. This can be done using a link to switch the VCC supply. The FT232R will fail to operate when the internal oscillator has been disabled, but no external oscillator has been connected. Copyright © 2010 Future Technology Devices International Limited 33 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 8 Internal EEPROM Configuration Following a power-on reset or a USB reset the FT232R will scan its internal EEPROM and read the USB configuration descriptors stored there. The default factory programmed values of the internal EEPROM are shown in Table 8.1. Parameter Value Notes USB Vendor ID (VID) 0403h FTDI default VID (hex) USB Product UD (PID) 6001h FTDI default PID (hex) Serial Number Enabled? Yes Serial Number See Note A unique serial number is generated and programmed into the EEPROM during device final test. Pull down I/O Pins in USB Suspend Disabled Enabling this option will make the device pull down on the UART interface lines when in USB suspend mode (PWREN# is high). Manufacturer Name FTDI Product Description FT232R USB UART Max Bus Power Current 90mA Power Source Bus Powered Device Type FT232R USB Version 0200 Returns USB 2.0 device description to the host. Note: The device is a USB 2.0 Full Speed device (12Mb/s) as opposed to a USB 2.0 High Speed device (480Mb/s). Remote Wake Up Enabled Taking RI# low will wake up the USB host controller from suspend in approximately 20 ms. High Current I/Os Disabled Enables the high drive level on the UART and CBUS I/O pins. Load VCP Driver Enabled Makes the device load the VCP driver interface for the device. CBUS0 TXLED# Default configuration of CBUS0 – Transmit LED drive. CBUS1 RXLED# Default configuration of CBUS1 – Receive LED drive. CBUS2 TXDEN Default configuration of CBUS2 – Transmit data enable for RS485 CBUS3 PWREN# Default configuration of CBUS3 – Power enable. Low after USB enumeration, high during USB suspend mode. Copyright © 2010 Future Technology Devices International Limited 34 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Parameter Value Notes CBUS4 SLEEP# Default configuration of CBUS4 – Low during USB suspend mode. Invert TXD Disabled Signal on this pin becomes TXD# if enable. Invert RXD Disabled Signal on this pin becomes RXD# if enable. Invert RTS# Disabled Signal on this pin becomes RTS if enable. Invert CTS# Disabled Signal on this pin becomes CTS if enable. Invert DTR# Disabled Signal on this pin becomes DTR if enable. Invert DSR# Disabled Signal on this pin becomes DSR if enable. Invert DCD# Disabled Signal on this pin becomes DCD if enable. Invert RI# Disabled Signal on this pin becomes RI if enable. Table 8.1 Default Internal EEPROM Configuration The internal EEPROM in the FT232R can be programmed over USB using the FTDI utility program MPROG. MPROG can be downloaded from FTDI Utilities on the FTDI website (www.ftdichip.com). Version 2.8a or later is required for the FT232R chip. Users who do not have their own USB Vendor ID but who would like to use a unique Product ID in their design can apply to FTDI for a free block of unique PIDs. Contact FTDI support for this service. Copyright © 2010 Future Technology Devices International Limited 35 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 9 Package Parameters The FT232R is available in two different packages. The FT232RL is the SSOP-28 option and the FT232RQ is the QFN-32 package option. The solder reflow profile for both packages is described in Section 9.5. 9.1 SSOP-28 Package Dimensions Figure 9.1 SSOP-28 Package Dimensions The FT232RL is supplied in a RoHS compliant 28 pin SSOP package. The package is lead (Pb) free and uses a „green‟ compound. The package is fully compliant with European Union directive 2002/95/EC. This package is nominally 5.30mm x 10.20mm body (7.80mm x 10.20mm including pins). The pins are on a 0.65 mm pitch. The above mechanical drawing shows the SSOP-28 package. All dimensions are in millimetres. The date code format is YYXX where XX = 2 digit week number, YY = 2 digit year number. This is followed by the revision number. The code XXXXXXXXXXXX is the manufacturing LOT code. This only applies to devices manufactured after April 2009. 12° Typ0° - 8°0.25 0.75 +/-0.200.092.00 Max1.75+/- 0.100.05 Min1.25 +/-0.12FT232RLYYXX-A1141528FTDI5.30 +/-0.307.80 +/-0.40 10.20 +/-0.301.02 Typ.0.30 +/-0.0120.65 +/-0.026XXXXXXXXXXXX Copyright © 2010 Future Technology Devices International Limited 36 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 9.2 QFN-32 Package Dimensions Figure 9.2 QFN-32 Package Dimensions The FT232RQ is supplied in a RoHS compliant leadless QFN-32 package. The package is lead ( Pb ) free, and uses a „green‟ compound. The package is fully compliant with European Union directive 2002/95/EC. This package is nominally 5.00mm x 5.00mm. The solder pads are on a 0.50mm pitch. The above mechanical drawing shows the QFN-32 package. All dimensions are in millimetres. The centre pad on the base of the FT232RQ is not internally connected, and can be left unconnected, or connected to ground (recommended). The date code format is YYXX where XX = 2 digit week number, YY = 2 digit year number. The code XXXXXXX is the manufacturing LOT code. This only applies to devices manufactured after April 2009. Indicates Pin #1 (Laser Marked)FT232RQ3225241716981YYXX-A5.000 +/-0.0755.000 +/-0.0753.200 +/-0.1003.200 +/-0.1000.5000.250 +/-0.0500.500 +/-0.0500.150 MaxPin #1 ID0.900 +/-0.1000.200 0.0502134567823242221201918172526272829303132161514131211109Note: The pin #1 ID is connected internally to the device’s central heat sink area . It is recommended to ground the central heat sink area of the device. 0.200 MinDimensions in mm.Central Heat Sink AreaFTDIXXXXXXX Copyright © 2010 Future Technology Devices International Limited 37 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 9.3 QFN-32 Package Typical Pad Layout Figure 9.3 Typical Pad Layout for QFN-32 Package 9.4 QFN-32 Package Typical Solder Paste Diagram 2.5 +/- 0.0375 2.5 +/- 0.0375 Figure 9.4 Typical Solder Paste Diagram for QFN-32 Package 1 17 25 0.500 0.30 0.200 Min 0.500 +/-0.050 0.150 Max 0.20 0.100 3.200 +/-0.100 3.200 +/-0.100 2.50 2.50 Optional GND Connection Optional GND Connection 9 Copyright © 2010 Future Technology Devices International Limited 38 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 9.5 Solder Reflow Profile The FT232R is supplied in Pb free 28 LD SSOP and QFN-32 packages. The recommended solder reflow profile for both package options is shown in Figure 9.5. Figure 9.5 FT232R Solder Reflow Profile The recommended values for the solder reflow profile are detailed in Table 9.1. Values are shown for both a completely Pb free solder process (i.e. the FT232R is used with Pb free solder), and for a non-Pb free solder process (i.e. the FT232R is used with non-Pb free solder). Profile Feature Pb Free Solder Process Non-Pb Free Solder Process Average Ramp Up Rate (Ts to Tp) 3°C / second Max. 3°C / Second Max. Preheat - Temperature Min (Ts Min.) - Temperature Max (Ts Max.) - Time (ts Min to ts Max) 150°C 200°C 60 to 120 seconds 100°C 150°C 60 to 120 seconds Time Maintained Above Critical Temperature TL: - Temperature (TL) - Time (tL) 217°C 60 to 150 seconds 183°C 60 to 150 seconds Peak Temperature (Tp) 260°C 240°C Time within 5°C of actual Peak Temperature (tp) 20 to 40 seconds 20 to 40 seconds Ramp Down Rate 6°C / second Max. 6°C / second Max. Time for T= 25°C to Peak Temperature, Tp 8 minutes Max. 6 minutes Max. Table 9.1 Reflow Profile Parameter Values Critical Zone: whenT is in the rangeT to TTemperature, T ( Degrees C)Time, t (seconds)25PT = 25º C to TtpTpTLtPreheatStLRamp UpLpRampDownT MaxST MinS Copyright © 2010 Future Technology Devices International Limited 39 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 10 Contact Information Head Office – Glasgow, UK Future Technology Devices International Limited Unit 1, 2 Seaward Place Centurion Business Park Glasgow, G41 1HH United Kingdom Tel: +44 (0) 141 429 2777 Fax: +44 (0) 141 429 2758 E-mail (Sales) sales1@ftdichip.com E-mail (Support) support1@ftdichip.com E-mail (General Enquiries) admin1@ftdichip.com Web Site URL http://www.ftdichip.com Web Shop URL http://www.ftdichip.com Branch Office – Taipei, Taiwan Future Technology Devices International Limited (Taiwan) 2F, No 516, Sec. 1 NeiHu Road Taipei 114 Taiwan, R.O.C. Tel: +886 (0) 2 8791 3570 Fax: +886 (0) 2 8791 3576 E-mail (Sales) tw.sales1@ftdichip.com E-mail (Support) tw.support1@ftdichip.com E-mail (General Enquiries) tw.admin1@ftdichip.com Web Site URL http://www.ftdichip.com Branch Office – Hillsboro, Oregon, USA Future Technology Devices International Limited (USA) 7235 NW Evergreen Parkway, Suite 600 Hillsboro, OR 97123-5803 USA Tel: +1 (503) 547 0988 Fax: +1 (503) 547 0987 E-Mail (Sales) us.sales@ftdichip.com E-Mail (Support) us.admin@ftdichip.com Web Site URL http://www.ftdichip.com Branch Office – Shanghai, China Future Technology Devices International Limited (China) Room 408, 317 Xianxia Road, ChangNing District, ShangHai, China Tel: +86 (21) 62351596 Fax: +86(21) 62351595 E-Mail (Sales): cn.sales@ftdichip.com E-Mail (Support): cn.support@ftdichip.com E-Mail (General Enquiries): cn.admin1@ftdichip.com Web Site URL: http://www.ftdichip.com Distributor and Sales Representatives Please visit the Sales Network page of the FTDI Web site for the contact details of our distributor(s) and sales representative(s) in your country. Copyright © 2010 Future Technology Devices International Limited 40 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Appendix A – References Useful Application Notes http://www.ftdichip.com/Documents/AppNotes/AN232R-01_FT232RBitBangModes.pdf http://www.ftdichip.com/Documents/AppNotes/AN_107_AdvancedDriverOptions_AN_000073.pdf http://www.ftdichip.com/Documents/AppNotes/AN232R-02_FT232RChipID.pdf http://www.ftdichip.com/Documents/AppNotes/AN_121_FTDI_Device_EEPROM_User_Area_Usage.pdf http://www.ftdichip.com/Documents/AppNotes/AN_120_Aliasing_VCP_Baud_Rates.pdf http://www.ftdichip.com/Documents/AppNotes/AN_100_Using_The_FT232_245R_With_External_Osc(FT_000067).pdf http://www.ftdichip.com/Resources/Utilities/AN_126_User_Guide_For_FT232_Factory%20test%20utility.pdf http://www.ftdichip.com/Documents/AppNotes/AN232B-05_BaudRates.pdf http://www.ftdichip.com/Documents/InstallGuides.htm Copyright © 2010 Future Technology Devices International Limited 41 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Appendix B - List of Figures and Tables List of Figures Figure 2.1 FT232R Block Diagram ................................................................................................... 4 Figure 3.1 SSOP Package Pin Out and Schematic Symbol .......................................................... 7 Figure 3.2 QFN-32 Package Pin Out and schematic symbol .............................................................. 10 Figure 6.1 Bus Powered Configuration ........................................................................................... 23 Figure 6.2 Self Powered Configuration ........................................................................................... 24 Figure 6.4 USB Bus Powered with +3.3V or +5V External Logic Power Supply .................................... 26 Figure 7.1 Application Example showing USB to RS232 Converter ..................................................... 27 Figure 7.2 Application Example Showing USB to RS485 Converter .................................................... 28 Figure 7.3 USB to RS422 Converter Configuration ........................................................................... 29 Figure 7.4 USB to MCU UART Interface .......................................................................................... 30 Figure 7.5 Dual LED Configuration ................................................................................................ 31 Figure 7.6 Single LED Configuration .............................................................................................. 31 Figure 9.1 SSOP-28 Package Dimensions ....................................................................................... 35 Figure 9.2 QFN-32 Package Dimensions ......................................................................................... 36 Figure 9.3 Typical Pad Layout for QFN-32 Package .......................................................................... 37 Figure 9.4 Typical Solder Paste Diagram for QFN-32 Package ........................................................... 37 Figure 9.5 FT232R Solder Reflow Profile ........................................................................................ 38 List of Tables Table 3.1 USB Interface Group ....................................................................................................... 7 Table 3.2 Power and Ground Group ................................................................................................. 8 Table 3.3 Miscellaneous Signal Group .............................................................................................. 8 Table 3.4 UART Interface and CUSB Group (see note 3) .................................................................... 9 Table 3.5 USB Interface Group ..................................................................................................... 10 Table 3.6 Power and Ground Group ............................................................................................... 11 Table 3.7 Miscellaneous Signal Group ............................................................................................ 11 Table 3.8 UART Interface and CBUS Group (see note 3) .................................................................. 12 Table 3.9 CBUS Configuration Control ........................................................................................... 13 Table 5.1 Absolute Maximum Ratings ............................................................................................ 17 Table 5.2 Operating Voltage and Current ....................................................................................... 18 Table 5.3 UART and CBUS I/O Pin Characteristics (VCCIO = +5.0V, Standard Drive Level) .................. 18 Table 5.4 UART and CBUS I/O Pin Characteristics (VCCIO = +3.3V, Standard Drive Level) .................. 18 Table 5.5 UART and CBUS I/O Pin Characteristics (VCCIO = +2.8V, Standard Drive Level) .................. 19 Table 5.6 UART and CBUS I/O Pin Characteristics (VCCIO = +1.8V, Standard Drive Level) .................. 19 Table 5.7 UART and CBUS I/O Pin Characteristics (VCCIO = +5.0V, High Drive Level) ......................... 19 Table 5.8 UART and CBUS I/O Pin Characteristics (VCCIO = +3.3V, High Drive Level) ......................... 19 Table 5.9 UART and CBUS I/O Pin Characteristics (VCCIO = +2.8V, High Drive Level) ......................... 20 Table 5.10 UART and CBUS I/O Pin Characteristics (VCCIO = +1.8V, High Drive Level) ....................... 20 Copyright © 2010 Future Technology Devices International Limited 42 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Table 5.11 RESET# and TEST Pin Characteristics ............................................................................ 20 Table 5.12 USB I/O Pin (USBDP, USBDM) Characteristics ................................................................. 21 Table 5.13 EEPROM Characteristics ............................................................................................... 21 Table 5.14 Internal Clock Characteristics ....................................................................................... 21 Table 5.15 OSCI, OSCO Pin Characteristics – see Note 1 ................................................................. 22 Table 8.1 Default Internal EEPROM Configuration ............................................................................ 34 Table 9.1 Reflow Profile Parameter Values ..................................................................................... 38 Copyright © 2010 Future Technology Devices International Limited 43 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Appendix C - Revision History Document Title: USB UART IC FT232R Document Reference No.: FT_000053 Clearance No.: FTDI# 38 Product Page: http://www.ftdichip.com/FTProducts.htm Document Feedback: Send Feedback Version 0.90 Initial Datasheet Created August 2005 Version 0.96 Revised Pre-release datasheet October 2005 Version 1.00 Full datasheet released December 2005 Version 1.02 Minor revisions to datasheet December 2005 Version 1.03 Manufacturer ID added to default EEPROM configuration; Buffer sizes added January 2006 Version 1.04 QFN-32 Pad layout and solder paste diagrams added January 2006 Version 2.00 Reformatted, updated package info, added notes for 3.3V operation; June 2008 Part numbers, TID; added UART and CBUS characteristics for +1.8V; Corrected RESET#; Added MTTF data; Corrected the input switching threshold and input hysteresis values for VCCIO=5V Version 2.01 Corrected pin-out number in table3.2 for GND pin18. Improved graphics on some Figures. Add packing details. Changed USB suspend current spec from 500uA to 2.5mA Corrected Figure 9.2 QFN dimensions. August 2008 Version 2.02 Corrected Tape and Reel quantities. Added comment “PWREN# should be used with a 10kΩ resistor pull up”. Replaced TXDEN# with TXDEN since it is active high in various places. Added lot number to the device markings. Added 3V3 regulator output tolerance. Clarified VCC operation and added section headed “Using an external Oscillator” Updated company contact information. April 2009 Version 2.03 Corrected the RX/TX buffer definitions to be relative to the USB interface June 2009 Version 2.04 Additional dimensions added to QFN solder profile June 2009 Version 2.05 Modified package dimensions to 5.0 x 5.0 +/-0.075mm. December 2009 and Solder paste diagram to 2.50 x 2.50 +/-0.0375mm Added Windows 7 32, 64 bit driver support Added FT_PROG utility references Added Appendix A-references.Figure 2.1 updated. Updated USB-IF TID for Rev B Version 2.06 Updated section 6.2, Figure 6.2 and the note, May 2010 Updated section 5.3, Table 5.13, EEPROM data retention time Version 2.07 Added USB Certification Logos July 2010 Version 2.08 Updated USB-IF TID for Rev C April 2011 Version 2.09 Corrected Rev C TID number April 2011 Version 2.10 Table 3.9, added clock output frequency within ±0.7% March 2012 Edited Table 3.9, TXLED# and TXLED# Description Added feedback links LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 1 August 2013 LM78XX / LM78XXA 3-Terminal 1 A Positive Voltage Regulator Features • Output Current up to 1 A • Output Voltages: 5, 6, 8, 9, 10, 12, 15, 18, 24 V • Thermal Overload Protection • Short-Circuit Protection • Output Transistor Safe Operating Area Protection Ordering Information(1) Note: 1. Above output voltage tolerance is available at 25°C. Product Number Output Voltage Tolerance Package Operating Temperature Packing Method LM7805CT ±4% TO-220 (Single Gauge) -40°C to +125°C Rail LM7806CT LM7808CT LM7809CT LM7810CT LM7812CT LM7815CT LM7818CT LM7824CT LM7805ACT ±2% 0°C to +125°C LM7809ACT LM7810ACT LM7812ACT LM7815ACT Description The LM78XX series of three-terminal positive regulators is available in the TO-220 package and with several fixed output voltages, making them useful in a wide range of applications. Each type employs internal current limiting, thermal shut-down, and safe operating area protection. If adequate heat sinking is provided, they can deliver over 1 A output current. Although designed primarily as fixedvoltage regulators, these devices can be used with external components for adjustable voltages and currents. 1 1. Input 2. GND 3. Output GND TO-220 (Single Gauge) LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 2 Block Diagram Figure 1. Block Diagram Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Values are at TA = 25°C unless otherwise noted. Symbol Parameter Value Unit VI Input Voltage VO = 5 V to 18 V 35 V VO = 24 V 40 RθJC Thermal Resistance, Junction-Case (TO-220) 5 °C/W RθJA Thermal Resistance, Junction-Air (TO-220) 65 °C/W TOPR Operating Temperature Range LM78xx -40 to +125 °C LM78xxA 0 to +125 TSTG Storage Temperature Range - 65 to +150 °C Starting Circuit Input 1 Reference Voltage Current Generator SOA Protection Thermal Protection Series Pass Element Error Amplifier Output 3 GND 2 LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 3 Electrical Characteristics (LM7805) Refer to the test circuit, -40°C < TJ < 125°C, IO = 500 mA, VI = 10 V, CI = 0.1 μF, unless otherwise specified. Notes: 2. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 3. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 4.80 5.00 5.20 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 7 V to 20 V 4.75 5.00 5.25 Regline Line Regulation(2) TJ = +25°C VI = 7 V to 25 V 4.0 100.0 mV VI = 8 V to 12 V 1.6 50.0 Regload Load Regulation(2) TJ = +25°C IO = 5 mA to 1.5 A 9.0 100.0 mV IO = 250 mA to 750 mA 4.0 50.0 IQ Quiescent Current TJ =+25°C 5.0 8.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.03 0.50 mA VI = 7 V to 25 V 0.30 1.30 ΔVO/ΔT Output Voltage Drift(3) IO = 5 mA -0.8 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 42.0 μV/VO RR Ripple Rejection(3) f = 120 Hz, VI = 8 V to 18 V 62.0 73.0 dB VDROP Dropout Voltage TJ = +25°C, IO = 1 A 2.0 V RO Output Resistance(3) f = 1 kHz 15.0 mΩ ISC Short-Circuit Current TJ = +25°C, VI = 35 V 230 mA IPK Peak Current(3) TJ = +25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 4 Electrical Characteristics (LM7806) Refer to the test circuit, -40°C < TJ < 125°C, IO = 500 mA, VI = 11 V, CI = 0.33 μF,CO = 0.1 μF, unless otherwise specified. Notes: 4. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 5. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 5.75 6.00 6.25 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 8.0 V to 21 V 5.70 6.00 6.30 Regline Line Regulation(4) TJ = +25°C VI = 8 V to 25 V 5.0 120 mV VI = 9 V to 13 V 1.5 60.0 Regload Load Regulation(4) TJ = +25°C IO = 5 mA to 1.5 A 9.0 120.0 mV IO = 250 mA to 750 mA 3.0 60.0 IQ Quiescent Current TJ =+25°C 5.0 8.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.5 mA VI = 8 V to 25 V 1.3 ΔVO/ΔT Output Voltage Drift(5) IO = 5 mA -0.8 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 45.0 μV/VO RR Ripple Rejection(5) f = 120 Hz, VI = 8 V to 18 V 62.0 73.0 dB VDROP Dropout Voltage TJ = +25°C, IO = 1 A 2.0 V RO Output Resistance(5) f = 1 kHz 19.0 mΩ ISC Short-Circuit Current TJ = +25°C, VI = 35 V 250 mA IPK Peak Current(5) TJ = +25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 5 Electrical Characteristics (LM7808) Refer to the test circuit, -40°C < TJ < 125°C, IO = 500 mA, VI = 14 V, CI = 0.33 μF, CO = 0.1 μF, unless otherwise specified. Notes: 6. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 7. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 7.7 8.0 8.3 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 10.5 V to 23 V 7.6 8.0 8.4 Regline Line Regulation(6) TJ = +25°C VI = 10.5 V to 25 V 5.0 160.0 mV VI = 11.5 V to 17 V 2.0 80.0 Regload Load Regulation(6) TJ = +25°C IO = 5 mA to 1.5 A 10.0 160.0 mV IO = 250 mA to 750 mA 5.0 80.0 IQ Quiescent Current TJ =+25°C 5.0 8.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.05 0.50 mA VI = 10.5 V to 25 V 0.5 1.0 ΔVO/ΔT Output Voltage Drift(7) IO = 5 mA -0.8 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 52.0 μV/VO RR Ripple Rejection(7) f = 120 Hz, VI = 11.5 V to 21.5 V 56.0 73.0 dB VDROP Dropout Voltage IO = 1 A, TJ = +25°C 2.0 V RO Output Resistance(7) f = 1 kHz 17.0 mΩ ISC Short-Circuit Current VI = 35 V, TJ = +25°C 230 mA IPK Peak Current(7) TJ = +25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 6 Electrical Characteristics (LM7809) Refer to the test circuit, -40°C < TJ < 125°C, IO = 500 mA, VI = 15 V, CI = 0.33 μF,CO = 0.1 μF, unless otherwise specified. Notes: 8. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 9. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 8.65 9.00 9.35 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 11.5 V to 24 V 8.60 9.00 9.40 Regline Line Regulation(8) TJ = +25°C VI = 11.5 V to 25 V 6.0 180.0 mV VI = 12 V to 17 V 2.0 90.0 Regload Load Regulation(8) TJ = +25°C IO = 5 mA to 1.5 A 12.0 180.0 mV IO = 250 mA to 750 mA 4.0 90.0 IQ Quiescent Current TJ =+25°C 5.0 8.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.5 mA VI = 11.5 V to 26 V 1.3 ΔVO/ΔT Output Voltage Drift(9) IO = 5 mA -1.0 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 58.0 μV/VO RR Ripple Rejection(9) f = 120 Hz, VI = 13 V to 23 V 56.0 71.0 dB VDROP Dropout Voltage IO = 1 A, TJ = +25°C 2.0 V RO Output Resistance(9) f = 1 kHz 17.0 mΩ ISC Short-Circuit Current VI = 35 V, TJ = +25°C 250 mA IPK Peak Current(9) TJ = +25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 7 Electrical Characteristics (LM7810) Refer to the test circuit, -40°C < TJ < 125°C, IO = 500 mA, VI = 16 V, CI = 0.33 μF,CO = 0.1 μF, unless otherwise specified. Notes: 10. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 11. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 9.6 10.0 10.4 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 12.5 V to 25 V 9.5 10.0 10.5 Regline Line Regulation(10) TJ = +25°C VI = 12.5 V to 25 V 10 200 mV VI = 13 V to 25 V 3 100 Regload Load Regulation(10) TJ = +25°C IO = 5 mA to 1.5 A 12 200 mV IO = 250 mA to 750 mA 4 400 IQ Quiescent Current TJ =+25°C 5.1 8.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.5 mA VI = 12.5 V to 29 V 1.0 ΔVO/ΔT Output Voltage Drift(11) IO = 5 mA -1.0 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 58.0 μV/VO RR Ripple Rejection(11) f = 120 Hz, VI = 13 V to 23 V 56.0 71.0 dB VDROP Dropout Voltage IO = 1 A, TJ = +25°C 2.0 V RO Output Resistance(11) f = 1 kHz 17.0 mΩ ISC Short-Circuit Current VI = 35 V, TJ = +25°C 250 mA IPK Peak Current(11) TJ = +25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 8 Electrical Characteristics (LM7812) Refer to the test circuit, -40°C < TJ < 125°C, IO = 500 mA, VI = 19 V, CI = 0.33 μF,CO = 0.1 μF, unless otherwise specified. Notes: 12. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 13. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 11.5 12.0 12.5 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 14.5 V to 27 V 11.4 12.0 12.6 Regline Line Regulation(12) TJ = +25°C VI = 14.5 V to 30 V 10 240 mV VI = 16 V to 22 V 3 120 Regload Load Regulation(12) TJ = +25°C IO = 5 mA to 1.5 A 11 240 mV IO = 250 mA to 750 mA 5 120 IQ Quiescent Current TJ =+25°C 5.1 8.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.1 0.5 mA VI = 14.5 V to 30 V 0.5 1.0 ΔVO/ΔT Output Voltage Drift(13) IO = 5 mA -1.0 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 76.0 μV/VO RR Ripple Rejection(13) f = 120 Hz, VI = 15 V to 25 V 55.0 71.0 dB VDROP Dropout Voltage IO = 1 A, TJ = +25°C 2.0 V RO Output Resistance(13) f = 1 kHz 18.0 mΩ ISC Short-Circuit Current VI = 35 V, TJ = +25°C 230 mA IPK Peak Current(13) TJ = +25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 9 Electrical Characteristics (LM7815) Refer to the test circuit, -40°C < TJ < 125°C, IO = 500 mA, VI = 23 V, CI = 0.33 μF,CO = 0.1 μF, unless otherwise specified. Notes: 14. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 15. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 14.40 15.00 15.60 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 17.5 V to 30 V 14.25 15.00 15.75 Regline Line Regulation(14) TJ = +25°C VI = 17.5 V to 30 V 11 300 mV VI = 20 V to 26 V 3 150 Regload Load Regulation(14) TJ = +25°C IO = 5 mA to 1.5 A 12 300 mV IO = 250 mA to 750 mA 4 150 IQ Quiescent Current TJ =+25°C 5.2 8.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.5 mA VI = 17.5 V to 30 V 1.0 ΔVO/ΔT Output Voltage Drift(15) IO = 5 mA -1.0 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 90.0 μV/VO RR Ripple Rejection(15) f = 120 Hz, VI = 18.5 V to 28.5 V 54.0 70.0 dB VDROP Dropout Voltage IO = 1 A, TJ =+25°C 2.0 V RO Output Resistance(15) f = 1 kHz 19.0 mΩ ISC Short-Circuit Current VI = 35 V, TJ = +25°C 250 mA IPK Peak Current(15) TJ = +25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 10 Electrical Characteristics (LM7818) Refer to the test circuit, -40°C < TJ < 125°C, IO = 500 mA, VI = 27 V, CI = 0.33 μF, CO = 0.1 μF, unless otherwise specified. Notes: 16. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 17. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 17.3 18.0 18.7 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 21 V to 33 V 17.1 18.0 18.9 Regline Line Regulation(16) TJ = +25°C VI = 21 V to 33 V 15 360 mV VI = 24 V to 30 V 5 180 Regload Load Regulation(16) TJ = +25°C IO = 5 mA to 1.5 A 15 360 mV IO = 250 mA to 750 mA 5 180 IQ Quiescent Current TJ =+25°C 5.2 8.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.5 mA VI = 21 V to 33 V 1.0 ΔVO/ΔT Output Voltage Drift(17) IO = 5 mA -1.0 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 110 μV/VO RR Ripple Rejection(17) f = 120 Hz, VI = 22 V to 32 V 53.0 69.0 dB VDROP Dropout Voltage IO = 1 A, TJ =+25°C 2.0 V RO Output Resistance(17) f = 1 kHz 22.0 mΩ ISC Short-Circuit Current VI = 35 V, TJ =+25°C 250 mA IPK Peak Current(17) TJ =+25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 11 Electrical Characteristics (LM7824) Refer to the test circuit, -40°C < TJ < 125°C, IO = 500 mA, VI = 33 V, CI = 0.33 μF, CO = 0.1 μF, unless otherwise specified. Notes: 18. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 19. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 23.00 24.00 25.00 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 27 V to 38 V 22.80 24.00 25.25 Regline Line Regulation(18) TJ = +25°C VI = 27 V to 38 V 17 480 mV VI = 30 V to 36 V 6 240 Regload Load Regulation(18) TJ = +25°C IO = 5 mA to 1.5 A 15 480 mV IO = 250 mA to 750 mA 5 240 IQ Quiescent Current TJ =+25°C 5.2 8.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.1 0.5 mA VI = 27 V to 38 V 0.5 1.0 ΔVO/ΔT Output Voltage Drift(19) IO = 5 mA -1.5 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 6.0 μV/VO RR Ripple Rejection(19) f = 120 Hz, VI = 28 V to 38 V 50.0 67.0 dB VDROP Dropout Voltage IO = 1 A, TJ = +25°C 2.0 V RO Output Resistance(19) f = 1 kHz 28.0 mΩ ISC Short-Circuit Current VI = 35 V, TJ = +25°C 230 mA IPK Peak Current(19) TJ = +25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 12 Electrical Characteristics (LM7805A) Refer to the test circuit, 0°C < TJ < 125°C, IO = 1 A, VI = 10 V, CI = 0.33 μF, CO = 0.1 μF, unless otherwise specified. Notes: 20. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 21. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 4.9 5.0 5.1 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 7.5 V to 20 V 4.8 5.0 5.2 Regline Line Regulation(20) VI = 7.5 V to 25 V, IO = 500 mA 5.0 50.0 mV VI = 8 V to 12 V 3.0 50.0 TJ = +25°C VI = 7.3 V to 20 V 5.0 50.0 VI = 8 V to 12 V 1.5 25.0 Regload Load Regulation(20) TJ = +25°C, IO = 5 mA to 1.5 A 9.0 100.0 IO = 5 mA to 1 A 9.0 100.0 mV IO = 250 mA to 750 mA 4.0 50.0 IQ Quiescent Current TJ =+25°C 5.0 6.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.5 VI = 8 V to 25 V, IO = 500 mA 0.8 mA VI = 7.5 V to 20 V, TJ = +25°C 0.8 ΔVO/ΔT Output Voltage Drift(21) IO = 5 mA -0.8 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 10.0 μV/VO RR Ripple Rejection(21) f = 120 Hz, VO = 500 mA, VI =8 V to 18 V 68.0 dB VDROP Dropout Voltage IO = 1 A, TJ =+25°C 2.0 V RO Output Resistance(21) f = 1 kHz 17.0 mΩ ISC Short-Circuit Current VI = 35 V, TJ =+25°C 250 mA IPK Peak Current(21) TJ =+25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 13 Electrical Characteristics (LM7809A) Refer to the test circuit, 0°C < TJ < 125°C, IO = 1 A, VI = 15 V, CI = 0.33 μF,CO = 0.1 μF, unless otherwise specified. Notes: 22. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 23. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 8.82 9.00 9.16 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 11.2 V to 24 V 8.65 9.00 9.35 Regline Line Regulation(22) VI = 11.7 V to 25 V, IO = 500 mA 6.0 90.0 mV VI = 12.5 V to 19 V 4.0 45.0 TJ = +25°C VI = 11.5 V to 24 V 6.0 90.0 VI = 12.5 V to 19 V 2.0 45.0 Regload Load Regulation(22) TJ = +25°C, IO = 5 mA to 1.5 A 12.0 100.0 IO = 5 mA to 1 A 12.0 100.0 mV IO = 250 mA to 750 mA 5.0 50.0 IQ Quiescent Current TJ = +25°C 5.0 6.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.5 VI = 12 V to 25 V, IO = 500 mA 0.8 mA VI = 11.7 V to 25 V, TJ = +25°C 0.8 ΔVO/ΔT Output Voltage Drift(23) IO = 5 mA -1.0 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 10.0 μV/VO RR Ripple Rejection(23) f = 120 Hz, VO = 500 mA, VI =12 V to 22 V 62.0 dB VDROP Dropout Voltage IO = 1 A, TJ = +25°C 2.0 V RO Output Resistance(23) f = 1 kHz 17.0 mΩ ISC Short-Circuit Current VI = 35 V, TJ = +25°C 250 mA IPK Peak Current(23) TJ = +25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 14 Electrical Characteristics (LM7810A) Refer to the test circuit, 0°C < TJ < 125°C, IO = 1 A, VI = 16 V, CI = 0.33 μF, CO = 0.1 μF, unless otherwise specified. Notes: 24. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 25. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 9.8 10.0 10.2 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 12.8 V to 25 V 9.6 10.0 10.4 Regline Line Regulation(24) VI = 12.8 V to 26 V, IO = 500 mA 8.0 100.0 mV VI = 13 V to 20 V 4.0 50.0 TJ = +25°C VI = 12.5 V to 25 V 8.0 100.0 VI = 13 V to 20 V 3.0 50.0 Regload Load Regulation(24) TJ = +25°C, IO = 5 mA to 1.5 A 12.0 100.0 IO = 5 mA to 1 A 12.0 100.0 mV IO = 250 mA to 750 mA 5.0 50.0 IQ Quiescent Current TJ =+25°C 5.0 6.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.5 VI = 12.8 V to 25 V, IO = 500 mA 0.8 mA VI = 13 V to 26 V, TJ = +25°C 0.5 ΔVO/ΔT Output Voltage Drift(25) IO = 5 mA -1.0 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 10.0 μV/VO RR Ripple Rejection(25) f = 120 Hz, VO = 500 mA, VI =14 V to 24 V 62.0 dB VDROP Dropout Voltage IO = 1 A, TJ =+25°C 2.0 V RO Output Resistance(25) f = 1 kHz 17.0 mΩ ISC Short-Circuit Current VI = 35 V, TJ =+25°C 250 mA IPK Peak Current(25) TJ =+25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 15 Electrical Characteristics (LM7812A) Refer to the test circuit, 0°C < TJ < 125°C, IO = 1 A, VI = 19 V, CI = 0.33 μF, CO = 0.1 μF, unless otherwise specified. Notes: 26. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 27. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 11.75 12.00 12.25 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 14.8 V to 27 V 11.50 12.00 12.50 Regline Line Regulation(26) VI = 14.8 V to 30 V, IO = 500 mA 10.0 120.0 mV VI = 16 V to 22 V 4.0 120.0 TJ = +25°C VI = 14.5 V to 27 V 10.0 120.0 VI = 16 V to 22 V 3.0 60.0 Regload Load Regulation(26) TJ = +25°C, IO = 5 mA to 1.5 A 12.0 100.0 IO = 5 mA to 1 A 12.0 100.0 mV IO = 250 mA to 750 mA 5.0 50.0 IQ Quiescent Current TJ = +25°C 5.0 6.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.5 VI = 14 V to 27 V, IO = 500 mA 0.8 mA VI = 15 V to 30 V, TJ = +25°C 0.8 ΔVO/ΔT Output Voltage Drift(27) IO = 5 mA -1.0 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 10.0 μV/VO RR Ripple Rejection(27) f = 120 Hz, VO = 500 mA, VI =14 V to 24 V 60.0 dB VDROP Dropout Voltage IO = 1 A, TJ = +25°C 2.0 V RO Output Resistance(27) f = 1 kHz 18.0 mΩ ISC Short-Circuit Current VI = 35 V, TJ = +25°C 250 mA IPK Peak Current(27) TJ = +25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 16 Electrical Characteristics (LM7815A) Refer to the test circuit, 0°C < TJ < 125°C, IO = 1 A, VI = 23 V, CI = 0.33 μF, CO = 0.1 μF, unless otherwise specified. Notes: 28. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 29. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 14.75 15.00 15.30 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 17.7 V to 30 V 14.40 15.00 15.60 Regline Line Regulation(28) VI = 17.4 V to 30 V, IO = 500 mA 10.0 150.0 mV VI = 20 V to 26 V 5.0 150.0 TJ = +25°C VI = 17.5 V to 30 V 11.0 150.0 VI = 20 V to 26 V 3.0 75.0 Regload Load Regulation(28) TJ = +25°C, IO = 5 mA to 1.5 A 12.0 100.0 IO = 5 mA to 1 A 12.0 100.0 mV IO = 250 mA to 750 mA 5.0 50.0 IQ Quiescent Current TJ =+25°C 5.2 6.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.5 VI = 17.5 V to 30 V, IO = 500 mA 0.8 mA VI = 17.5 V to 30 V, TJ = +25°C 0.8 ΔVO/ΔT Output Voltage Drift(29) IO = 5 mA -1.0 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 10.0 μV/VO RR Ripple Rejection(29) f = 120 Hz, VO = 500 mA, VI =18.5 V to 28.5 V 58.0 dB VDROP Dropout Voltage IO = 1 A, TJ =+25°C 2.0 V RO Output Resistance(29) f = 1 kHz 19.0 mΩ ISC Short-Circuit Current VI = 35 V, TJ =+25°C 250 mA IPK Peak Current(29) TJ =+25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 17 Typical Performance Characteristics Figure 2. Quiescent Current Figure 3. Peak Output Current Figure 4. Output Voltage Figure 5. Quiescent Current LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 18 Typical Applications Figure 6. DC Parameters Figure 7. Load Regulation Figure 8. Ripple Rejection CI CO 0.1μF 0.33μF Input Output LM78XX 1 3 2 LM78XX 3 2 1 0.33μF 270pF 100Ω 30μS RL 2N6121 or EQ Input Output VO 0V VO LM78XX Input Output 5.1Ω 0.33μF 2 1 3 RL 470μF 120Hz + LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 19 Figure 9. Fixed-Output Regulator Notes: 29. To specify an output voltage, substitute voltage value for “XX”. A common ground is required between the input and the output voltage. The input voltage must remain typically 2.0 V above the output voltage even during the low point on the input ripple voltage. 30. CI is required if regulator is located an appreciable distance from power supply filter. 31. CO improves stability and transient response. Figure 10. Figure 11. Circuit for Increasing Output Voltage CI CO 0.1μF 0.33μF Input Output LM78XX 1 3 2 CI CO 0.1μF 0.33μF Output Input LM78XX 1 3 2 VXX R1 RL IQ IO IO = R1 +IQ VXX CI CO 0.1μF 0.33μF Output Input LM78XX 1 3 2 VXX R1 R2 IQ IRI ≥ 5 IQ VO = VXX(1 + R2 / R1) + IQR2 LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 20 Figure 12. Adjustable Output Regulator (7 V to 30 V) Figure 13. High-Current Voltage Regulator Figure 14. High Output Current with Short-Circuit Protection LM741 - + 2 3 6 4 2 1 3 CI 0.33μF Input Output 0.1μF CO LM7805 10kΩ IRI ≥ 5 IQ VO = VXX(1 + R2 / R1) + IQR2 3 2 1 LM78XX Output Input R1 3Ω 0.33μF IREG 0.1μF IO IQ1 IO = IREG + BQ1 (IREG–VBEQ1/R1) Q1 BD536 R1 = VBEQ1 IREG–IQ1/ BQ1 LM78XX Output 0.33μF 0.1μF R1 3Ω 3 2 1 Input Q1 Q2 Q1 = TIP42 Q2 = TIP42 RSC = I SC VBEQ2 RSC LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 21 Figure 15. Tracking Voltage Regulator Figure 16. Split Power Supply (±15 V - 1 A) LM78XX LM741 0.33μF 0.1μF 1 2 3 7 2 6 4 3 4.7kΩ 4.7kΩ TIP42 COMMON COMMON VO -VO VI -VIN _ + 1 3 2 1 2 3 0.33μF 0.1μF 2.2μF 1μF + + 1N4001 1N4001 +15V -15V +20V -20V LM7815 MC7915 LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 22 Figure 17. Negative Output Voltage Circuit Figure 18. Switching Regulator LM78XX Output Input + 1 2 0.1μF 3 LM78XX 1mH 1 3 2 2000μF Input Output D45H11 0.33μF 470Ω 4.7Ω 10μF 0.5Ω Z1 + + LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 23 Physical Dimensions Figure 19. TO-220, MOLDED, 3-LEAD, JEDEC VARIATION AB (ACTIVE) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/TO/TO220B03.pdf. For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area: http://www.fairchildsemi.com/packing_dwg/PKG-TO220B03_TC.pdf. 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Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I65 ® Low Cost Low Power Instrumentation Amplifier AD620 Rev. H Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703© 2003–2011 Analog Devices, Inc. All rights reserved. FEATURES Easy to use Gain set with one external resistor (Gain range 1 to 10,000) Wide power supply range (±2.3 V to ±18 V) Higher performance than 3 op amp IA designs Available in 8-lead DIP and SOIC packaging Low power, 1.3 mA max supply current Excellent dc performance (B grade) 50 μV max, input offset voltage 0.6 μV/°C max, input offset drift 1.0 nA max, input bias current 100 dB min common-mode rejection ratio (G = 10) Low noise 9 nV/√Hz @ 1 kHz, input voltage noise 0.28 μV p-p noise (0.1 Hz to 10 Hz) Excellent ac specifications 120 kHz bandwidth (G = 100) 15 μs settling time to 0.01% APPLICATIONS Weigh scales ECG and medical instrumentation Transducer interface Data acquisition systems Industrial process controls Battery-powered and portable equipment CONNECTION DIAGRAM –IN RG –VS +IN RG +VS OUTPUT REF 1 2 3 4 8 7 6 AD620 5 TOP VIEW 00775-0-001 Figure 1. 8-Lead PDIP (N), CERDIP (Q), and SOIC (R) Packages PRODUCT DESCRIPTION The AD620 is a low cost, high accuracy instrumentation amplifier that requires only one external resistor to set gains of 1 to 10,000. Furthermore, the AD620 features 8-lead SOIC and DIP packaging that is smaller than discrete designs and offers lower power (only 1.3 mA max supply current), making it a good fit for battery-powered, portable (or remote) applications. The AD620, with its high accuracy of 40 ppm maximum nonlinearity, low offset voltage of 50 μV max, and offset drift of 0.6 μV/°C max, is ideal for use in precision data acquisition systems, such as weigh scales and transducer interfaces. Furthermore, the low noise, low input bias current, and low power of the AD620 make it well suited for medical applications, such as ECG and noninvasive blood pressure monitors. The low input bias current of 1.0 nA max is made possible with the use of Superϐeta processing in the input stage. The AD620 works well as a preamplifier due to its low input voltage noise of 9 nV/√Hz at 1 kHz, 0.28 μV p-p in the 0.1 Hz to 10 Hz band, and 0.1 pA/√Hz input current noise. Also, the AD620 is well suited for multiplexed applications with its settling time of 15 μs to 0.01%, and its cost is low enough to enable designs with one in-amp per channel. Table 1. Next Generation Upgrades for AD620 Part Comment AD8221 Better specs at lower price AD8222 Dual channel or differential out AD8226 Low power, wide input range AD8220 JFET input AD8228 Best gain accuracy AD8295 +2 precision op amps or differential out AD8429 Ultra low noise 0 5 10 15 20 30,000 5,000 10,000 15,000 20,000 25,000 0 TOTAL ERROR, PPM OF FULL SCALE SUPPLY CURRENT (mA) AD620A RG 3 OP AMP IN-AMP (3 OP-07s) 00775-0-002 Figure 2. Three Op Amp IA Designs vs. AD620 IMPORTANT LINKS for the AD620* Last content update 01/08/2014 09:49 am Looking for a high performance in-amp with lower noise, wider bandwidth, and fast settling time? Consider the AD8421 Looking for a high performance in-amp with lower power and a rail-to-rail output? Consider the AD8422. DOCUMENTATION AD620: Military Data Sheet AN-282: Fundamentals of Sampled Data Systems AN-244: A User's Guide to I.C. Instrumentation Amplifiers AN-245: Instrumentation Amplifiers Solve Unusual Design Problems AN-671: Reducing RFI Rectification Errors in In-Amp Circuits AN-589: Ways to Optimize the Performance of a Difference Amplifier A Designer's Guide to Instrumentation Amplifiers (3rd Edition) UG-261: Evaluation Boards for the AD62x, AD822x and AD842x Series ECG Front-End Design is Simplified with MicroConverter Low-Power, Low-Voltage IC Choices for ECG System Requirements Ask The Applications Engineer-10 Auto-Zero Amplifiers High-performance Adder Uses Instrumentation Amplifiers Protecting Instrumentation Amplifiers Input Filter Prevents Instrumentation-amp RF-Rectification Errors The AD8221 - Setting a New Industry Standard for Instrumentation Amplifiers ADI Warns Against Misuse of COTS Integrated Circuits Space Qualified Parts List Applying Instrumentation Amplifiers Effectively: The Importance of an Input Ground Return Leading Inside Advertorials: Applying Instrumentation Amplifiers Effectively–The Importance of an Input Ground Return DESIGN TOOLS, MODELS, DRIVERS & SOFTWARE In-Amp Error Calculator These tools will help estimate error contributions in your instrumentation amplifier circuit. It uses input parameters such as temperature, gain, voltage input, and source impedance to determine the errors that can contribute to your overall design. In-Amp Common Mode Calculator AD620 SPICE Macro-Model AD620A SPICE Macro-Model AD620B SPICE Macro-Model AD620S SPICE Macro-Model AD620 SABER Macro-Model Conv, 10/00 EVALUATION KITS & SYMBOLS & FOOTPRINTS View the Evaluation Boards and Kits page for documentation and purchasing Symbols and Footprints PRODUCT RECOMMENDATIONS & REFERENCE DESIGNS CN-0146: Low Cost Programmable Gain Instrumentation Amplifier Circuit Using the ADG1611 Quad SPST Switch and AD620 Instrumentation Amplifier DESIGN COLLABORATION COMMUNITY Collaborate Online with the ADI support team and other designers about select ADI products. Follow us on Twitter: www.twitter.com/ADI_News Like us on Facebook: www.facebook.com/AnalogDevicesInc DESIGN SUPPORT Submit your support request here: Linear and Data Converters Embedded Processing and DSP Telephone our Customer Interaction Centers toll free: Americas: 1-800-262-5643 Europe: 00800-266-822-82 China: 4006-100-006 India: 1800-419-0108 Russia: 8-800-555-45-90 Quality and Reliability Lead(Pb)-Free Data SAMPLE & BUY AD620 View Price & Packaging Request Evaluation Board Request Samples Check Inventory & Purchase Find Local Distributors * This page was dynamically generated by Analo g Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to the content on this page (labeled 'Important Links') does not constitute a change to the revision number of the product data sheet. This content may be frequently modified. Powered by TCPDF (www.tcpdf.org) AD620 Rev. H | Page 2 of 20 TABLE OF CONTENTS Specifications .....................................................................................3 Absolute Maximum Ratings ............................................................5 ESD Caution ..................................................................................5 Typical Performance Characteristics..............................................6 Theory of Operation.......................................................................12 Gain Selection..............................................................................15 Input and Output Offset Voltage ..............................................15 Reference Terminal .....................................................................15 Input Protection ..........................................................................15 RF Interference............................................................................15 Common-Mode Rejection.........................................................16 Grounding....................................................................................16 Ground Returns for Input Bias Currents.................................17 AD620ACHIPS Information.........................................................18 Outline Dimensions........................................................................19 Ordering Guide ...........................................................................20 REVISION HISTORY 7/11—Rev. G to Rev. H Deleted Figure 3.................................................................................1 Added Table 1 ....................................................................................1 Moved Figure 2 ..................................................................................1 Added ESD Input Diodes to Simplified Schematic ....................12 Changes to Input Protection Section............................................15 Added Figure 41; Renumbered Sequentially ...............................15 Changes to AD620ACHIPS Information Section ......................18 Updated Ordering Guide ...............................................................20 12/04—Rev. F to Rev. G Updated Format..................................................................Universal Change to Features............................................................................1 Change to Product Description.......................................................1 Changes to Specifications.................................................................3 Added Metallization Photograph....................................................4 Replaced Figure 4-Figure 6 ..............................................................6 Replaced Figure 15............................................................................7 Replaced Figure 33..........................................................................10 Replaced Figure 34 and Figure 35.................................................10 Replaced Figure 37..........................................................................10 Changes to Table 3 ..........................................................................13 Changes to Figure 41 and Figure 42 .............................................14 Changes to Figure 43 ......................................................................15 Change to Figure 44 ........................................................................17 Changes to Input Protection section ............................................15 Deleted Figure 9 ..............................................................................15 Changes to RF Interference section..............................................15 Edit to Ground Returns for Input Bias Currents section...........17 Added AD620CHIPS to Ordering Guide ....................................19 7/03—Data Sheet Changed from Rev. E to Rev. F Edit to FEATURES............................................................................1 Changes to SPECIFICATIONS.......................................................2 Removed AD620CHIPS from ORDERING GUIDE ...................4 Removed METALLIZATION PHOTOGRAPH...........................4 Replaced TPCs 1–3 ...........................................................................5 Replaced TPC 12...............................................................................6 Replaced TPC 30...............................................................................9 Replaced TPCs 31 and 32...............................................................10 Replaced Figure 4............................................................................10 Changes to Table I...........................................................................11 Changes to Figures 6 and 7 ............................................................12 Changes to Figure 8 ........................................................................13 Edited INPUT PROTECTION section........................................13 Added new Figure 9........................................................................13 Changes to RF INTERFACE section ............................................14 Edit to GROUND RETURNS FOR INPUT BIAS CURRENTS section...............................................................................................15 Updated OUTLINE DIMENSIONS.............................................16 AD620 Rev. H | Page 3 of 20 SPECIFICATIONS Typical @ 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted. Table 2. Parameter Conditions AD620A AD620B AD620S1 Min Typ Max Min Typ Max Min Typ Max Unit GAIN G = 1 + (49.4 kΩ/RG) Gain Range 1 10,000 1 10,000 1 10,000 Gain Error2 VOUT = ±10 V G = 1 0.03 0.10 0.01 0.02 0.03 0.10 % G = 10 0.15 0.30 0.10 0.15 0.15 0.30 % G = 100 0.15 0.30 0.10 0.15 0.15 0.30 % G = 1000 0.40 0.70 0.35 0.50 0.40 0.70 % Nonlinearity VOUT = −10 V to +10 V G = 1–1000 RL = 10 kΩ 10 40 10 40 10 40 ppm G = 1–100 RL = 2 kΩ 10 95 10 95 10 95 ppm Gain vs. Temperature G = 1 10 10 10 ppm/°C Gain >12 −50 −50 −50 ppm/°C VOLTAGE OFFSET (Total RTI Error = VOSI + VOSO/G) Input Offset, VOSI VS = ±5 V to ± 15 V 30 125 15 50 30 125 μV Overtemperature VS = ±5 V to ± 15 V 185 85 225 μV Average TC VS = ±5 V to ± 15 V 0.3 1.0 0.1 0.6 0.3 1.0 μV/°C Output Offset, VOSO VS = ±15 V 400 1000 200 500 400 1000 μV VS = ± 5 V 1500 750 1500 μV Overtemperature VS = ±5 V to ± 15 V 2000 1000 2000 μV Average TC VS = ±5 V to ± 15 V 5.0 15 2.5 7.0 5.0 15 μV/°C Offset Referred to the Input vs. Supply (PSR) VS = ±2.3 V to ±18 V G = 1 80 100 80 100 80 100 dB G = 10 95 120 100 120 95 120 dB G = 100 110 140 120 140 110 140 dB G = 1000 110 140 120 140 110 140 dB INPUT CURRENT Input Bias Current 0.5 2.0 0.5 1.0 0.5 2 nA Overtemperature 2.5 1.5 4 nA Average TC 3.0 3.0 8.0 pA/°C Input Offset Current 0.3 1.0 0.3 0.5 0.3 1.0 nA Overtemperature 1.5 0.75 2.0 nA Average TC 1.5 1.5 8.0 pA/°C INPUT Input Impedance Differential 10||2 10||2 10||2 GΩ_pF Common-Mode 10||2 10||2 10||2 GΩ_pF Input Voltage Range3 VS = ±2.3 V to ±5 V −VS + 1.9 +VS − 1.2 −VS + 1.9 +VS − 1.2 −VS + 1.9 +VS − 1.2 V Overtemperature −VS + 2.1 +VS − 1.3 −VS + 2.1 +VS − 1.3 −VS + 2.1 +VS − 1.3 V VS = ± 5 V to ±18 V −VS + 1.9 +VS − 1.4 −VS + 1.9 +VS − 1.4 −VS + 1.9 +VS − 1.4 V Overtemperature −VS + 2.1 +VS − 1.4 −VS + 2.1 +VS + 2.1 −VS + 2.3 +VS − 1.4 V AD620 Rev. H | Page 4 of 20 AD620A AD620B AD620S1 Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit Common-Mode Rejection Ratio DC to 60 Hz with 1 kΩ Source Imbalance VCM = 0 V to ± 10 V G = 1 73 90 80 90 73 90 dB G = 10 93 110 100 110 93 110 dB G = 100 110 130 120 130 110 130 dB G = 1000 110 130 120 130 110 130 dB OUTPUT Output Swing RL = 10 kΩ VS = ±2.3 V to ± 5 V −VS + 1.1 +VS − 1.2 −VS + 1.1 +VS − 1.2 −VS + 1.1 +VS − 1.2 V Overtemperature −VS + 1.4 +VS − 1.3 −VS + 1.4 +VS − 1.3 −VS + 1.6 +VS − 1.3 V VS = ±5 V to ± 18 V −VS + 1.2 +VS − 1.4 −VS + 1.2 +VS − 1.4 −VS + 1.2 +VS − 1.4 V Overtemperature −VS + 1.6 +VS – 1.5 −VS + 1.6 +VS – 1.5 –VS + 2.3 +VS – 1.5 V Short Circuit Current ±18 ±18 ±18 mA DYNAMIC RESPONSE Small Signal –3 dB Bandwidth G = 1 1000 1000 1000 kHz G = 10 800 800 800 kHz G = 100 120 120 120 kHz G = 1000 12 12 12 kHz Slew Rate 0.75 1.2 0.75 1.2 0.75 1.2 V/μs Settling Time to 0.01% 10 V Step G = 1–100 15 15 15 μs G = 1000 150 150 150 μs NOISE Voltage Noise, 1 kHz Total RTI Noise (e2 ) (e /G)2 = ni + no Input, Voltage Noise, eni 9 13 9 13 9 13 nV/√Hz Output, Voltage Noise, eno 72 100 72 100 72 100 nV/√Hz RTI, 0.1 Hz to 10 Hz G = 1 3.0 3.0 6.0 3.0 6.0 μV p-p G = 10 0.55 0.55 0.8 0.55 0.8 μV p-p G = 100–1000 0.28 0.28 0.4 0.28 0.4 μV p-p Current Noise f = 1 kHz 100 100 100 fA/√Hz 0.1 Hz to 10 Hz 10 10 10 pA p-p REFERENCE INPUT RIN 20 20 20 kΩ IIN VIN+, VREF = 0 50 60 50 60 50 60 μA Voltage Range −VS + 1.6 +VS − 1.6 −VS + 1.6 +VS − 1.6 −VS + 1.6 +VS − 1.6 V Gain to Output 1 ± 0.0001 1 ± 0.0001 1 ± 0.0001 POWER SUPPLY Operating Range4 ±2.3 ±18 ±2.3 ±18 ±2.3 ±18 V Quiescent Current VS = ±2.3 V to ±18 V 0.9 1.3 0.9 1.3 0.9 1.3 mA Overtemperature 1.1 1.6 1.1 1.6 1.1 1.6 mA TEMPERATURE RANGE For Specified Performance −40 to +85 −40 to +85 −55 to +125 °C 1 See Analog Devices military data sheet for 883B tested specifications. 2 Does not include effects of external resistor RG. 3 One input grounded. G = 1. 4 This is defined as the same supply range that is used to specify PSR. AD620 Rev. H | Page 5 of 20 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Supply Voltage ±18 V Internal Power Dissipation1 650 mW Input Voltage (Common-Mode) ±VS Differential Input Voltage 25 V Output Short-Circuit Duration Indefinite Storage Temperature Range (Q) −65°C to +150°C Storage Temperature Range (N, R) −65°C to +125°C Operating Temperature Range AD620 (A, B) −40°C to +85°C AD620 (S) −55°C to +125°C Lead Temperature Range (Soldering 10 seconds) 300°C 1 Specification is for device in free air: 8-Lead Plastic Package: θJA = 95°C 8-Lead CERDIP Package: θJA = 110°C 8-Lead SOIC Package: θJA = 155°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION AD620 Rev. H | Page 6 of 20 TYPICAL PERFORMANCE CHARACTERISTICS (@ 25°C, VS = ±15 V, RL = 2 kΩ, unless otherwise noted.) INPUT OFFSET VOLTAGE (μV) 20 30 40 50 –40 0 40 80 PERCENTAGE OF UNITS –80 SAMPLE SIZE = 360 10 0 00775-0-005 Figure 3. Typical Distribution of Input Offset Voltage INPUT BIAS CURRENT (pA) 0 10 20 30 40 50 –600 0 600 PERCENTAGE OF UNITS –1200 1200 SAMPLE SIZE = 850 00775-0-006 Figure 4. Typical Distribution of Input Bias Current 10 20 30 40 50 –200 0 200 400 INPUT OFFSET CURRENT (pA) PERCENTAGE OF UNITS –400 0 SAMPLE SIZE = 850 00775-0-007 Figure 5. Typical Distribution of Input Offset Current TEMPERATURE (°C) INPUT BIAS CURRENT (nA) +IB –IB 2.0 –2.0 175 –1.0 –1.5 –75 –0.5 0 0.5 1.0 1.5 –25 25 75 125 00775-0-008 Figure 6. Input Bias Current vs. Temperature CHANGE IN OFFSET VOLTAGE (μV) 1.5 0.5 WARM-UP TIME (Minutes) 2.0 0 0 1 1.0 2 3 4 5 00775-0-009 Figure 7. Change in Input Offset Voltage vs. Warm-Up Time FREQUENCY (Hz) 1000 1 1 100k 100 10 100 1k 10k VOLTAGE NOISE (nV/ Hz) GAIN = 1 GAIN = 10 10 GAIN = 100, 1,000 GAIN = 1000 BW LIMIT 00775-0-010 Figure 8. Voltage Noise Spectral Density vs. Frequency (G = 1−1000) AD620 Rev. H | Page 7 of 20 FREQUENCY (Hz) 1000 100 10 1 10 100 1000 CURRENT NOISE (fA/ Hz) 00775-0-011 Figure 9. Current Noise Spectral Density vs. Frequency RTI NOISE (2.0μV/DIV) TIME (1 SEC/DIV) 00775-0-012 Figure 10. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1) RTI NOISE (0.1μV/DIV) TIME (1 SEC/DIV) 00775-0-013 Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000) 00775-0-014 Figure 12. 0.1 Hz to 10 Hz Current Noise, 5 pA/Div 100 1000 AD620A FET INPUT IN-AMP SOURCE RESISTANCE (Ω) TOTAL DRIFT FROM 25°C TO 85°C, RTI (μV) 100,000 10 1k 10M 10,000 10k 100k 1M 00775-0-015 Figure 13. Total Drift vs. Source Resistance FREQUENCY (Hz) CMR (dB) 160 0 1M 80 40 1 60 0.1 140 100 120 10 100 1k 10k 100k G = 1000 G = 100 G = 10 G = 1 20 00775-0-016 Figure 14. Typical CMR vs. Frequency, RTI, Zero to 1 kΩ Source Imbalance AD620 Rev. H | Page 8 of 20 FREQUENCY (Hz) PSR (dB) 160 1M 80 40 1 60 0.1 140 100 120 10 100 1k 10k 100k 20 G = 1000 G = 100 G = 10 G = 1 180 00775-0-017 Figure 15. Positive PSR vs. Frequency, RTI (G = 1−1000) FREQUENCY (Hz) PSR (dB) 160 1M 80 40 1 60 0.1 140 100 120 10 100 1k 10k 100k 20 180 G = 10 G = 100 G = 1 G = 1000 00775-0-018 Figure 16. Negative PSR vs. Frequency, RTI (G = 1−1000) 1000 100 10M 100 1 1k 10 10k 100k 1M FREQUENCY (Hz) GAIN (V/V) 0.1 00775-0-019 Figure 17. Gain vs. Frequency OUTPUT VOLTAGE (V p-p) FREQUENCY (Hz) 35 0 1M 15 5 10k 10 1k 30 20 25 100k G = 10, 100, 1000 G = 1 G = 1000 G = 100 BW LIMIT 00775-0-020 Figure 18. Large Signal Frequency Response INPUT VOLTAGE LIMIT (V) (REFERRED TO SUPPLY VOLTAGES) 20 +1.0 +0.5 0 5 +1.5 –1.5 –1.0 –0.5 10 15 SUPPLY VOLTAGE ± Volts +VS –0.0 –VS +0.0 00775-0-021 Figure 19. Input Voltage Range vs. Supply Voltage, G = 1 20 +1.0 +0.5 0 5 +1.5 –1.5 –1.0 –0.5 10 15 SUPPLY VOLTAGE ± Volts RL = 10kΩ RL = 2kΩ RL = 10kΩ OUTPUT VOLTAGE SWING (V) (REFERRED TO SUPPLY VOLTAGES) RL = 2kΩ +VS –VS 00775-0-022 –0.0 +0.0 Figure 20. Output Voltage Swing vs. Supply Voltage, G = 10 AD620 Rev. H | Page 9 of 20 OUTPUT VOLTAGE SWING (V p-p) LOAD RESISTANCE (Ω) 30 0 0 10k 20 10 100 1k VS = ±15V G = 10 00775-0-023 Figure 21. Output Voltage Swing vs. Load Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00775-0-024 Figure 22. Large Signal Pulse Response and Settling Time G = 1 (0.5 mV = 0.01%) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00775-0-025 Figure 23. Small Signal Response, G = 1, RL = 2 kΩ, CL = 100 pF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00775-0-026 Figure 24. Large Signal Response and Settling Time, G = 10 (0.5 mV = 0.01%) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00775-0-027 Figure 25. Small Signal Response, G = 10, RL = 2 kΩ, CL = 100 pF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00775-0-030 Figure 26. Large Signal Response and Settling Time, G = 100 (0.5 mV = 0.01%) AD620 Rev. H | Page 10 of 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00775-0-029 Figure 27. Small Signal Pulse Response, G = 100, RL = 2 kΩ, CL = 100 pF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00775-0-030 Figure 28. Large Signal Response and Settling Time, G = 1000 (0.5 mV = 0.01% ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00775-0-031 Figure 29. Small Signal Pulse Response, G = 1000, RL = 2 kΩ, CL = 100 pF OUTPUT STEP SIZE (V) SETTLING TIME (μs) TO 0.01% TO 0.1% 20 0 0 2 15 5 5 10 10 15 0 00775-0-032 Figure 30. Settling Time vs. Step Size (G = 1) GAIN SETTLING TIME (μs) 1000 1 1 1000 100 10 10 100 00775-0-033 Figure 31. Settling Time to 0.01% vs. Gain, for a 10 V Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00775-0-034 Figure 32. Gain Nonlinearity, G = 1, RL = 10 kΩ (10 μV = 1 ppm) AD620 Rev. H | Page 11 of 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00775-0-035 Figure 33. Gain Nonlinearity, G = 100, RL = 10 kΩ (100 μV = 10 ppm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00775-0-036 Figure 34. Gain Nonlinearity, G = 1000, RL = 10 kΩ (1 mV = 100 ppm) AD620 VOUT G = 1000 G = 1 49.9Ω 10kΩ * 1kΩ 10T 10kΩ 499Ω G = 100 G = 10 5.49kΩ +VS 11kΩ 1kΩ 100Ω 100kΩ INPUT 10V p-p –VS *ALL RESISTORS 1% TOLERANCE 1 7 2 3 8 6 4 5 00775-0-037 Figure 35. Settling Time Test Circuit AD620 Rev. H | Page 12 of 20 THEORY OF OPERATION VB –VS A1 A2 A3 C2 RG R1 R2 GAIN SENSE GAIN SENSE 10kΩ 10kΩ I1 I2 10kΩ REF 10kΩ +IN – IN R4 400Ω OUTPUT C1 Q1 Q2 00775-0-038 R3 400Ω +VS +VS +VS 20μA 20μA Figure 36. Simplified Schematic of AD620 The AD620 is a monolithic instrumentation amplifier based on a modification of the classic three op amp approach. Absolute value trimming allows the user to program gain accurately (to 0.15% at G = 100) with only one resistor. Monolithic construction and laser wafer trimming allow the tight matching and tracking of circuit components, thus ensuring the high level of performance inherent in this circuit. The input transistors Q1 and Q2 provide a single differentialpair bipolar input for high precision (Figure 36), yet offer 10× lower input bias current thanks to Superϐeta processing. Feedback through the Q1-A1-R1 loop and the Q2-A2-R2 loop maintains constant collector current of the input devices Q1 and Q2, thereby impressing the input voltage across the external gain setting resistor RG. This creates a differential gain from the inputs to the A1/A2 outputs given by G = (R1 + R2)/RG + 1. The unity-gain subtractor, A3, removes any common-mode signal, yielding a single-ended output referred to the REF pin potential. The value of RG also determines the transconductance of the preamp stage. As RG is reduced for larger gains, the transconductance increases asymptotically to that of the input transistors. This has three important advantages: (a) Open-loop gain is boosted for increasing programmed gain, thus reducing gain related errors. (b) The gain-bandwidth product (determined by C1 and C2 and the preamp transconductance) increases with programmed gain, thus optimizing frequency response. (c) The input voltage noise is reduced to a value of 9 nV/√Hz, determined mainly by the collector current and base resistance of the input devices. The internal gain resistors, R1 and R2, are trimmed to an absolute value of 24.7 kΩ, allowing the gain to be programmed accurately with a single external resistor. The gain equation is then 1 49.4 + Ω = RG k G 1 49.4 − Ω = G k RG Make vs. Buy: a Typical Bridge Application Error Budget The AD620 offers improved performance over “homebrew” three op amp IA designs, along with smaller size, fewer components, and 10× lower supply current. In the typical application, shown in Figure 37, a gain of 100 is required to amplify a bridge output of 20 mV full-scale over the industrial temperature range of −40°C to +85°C. Table 4 shows how to calculate the effect various error sources have on circuit accuracy. AD620 Rev. H | Page 13 of 20 Regardless of the system in which it is being used, the AD620 provides greater accuracy at low power and price. In simple systems, absolute accuracy and drift errors are by far the most significant contributors to error. In more complex systems with an intelligent processor, an autogain/autozero cycle removes all absolute accuracy and drift errors, leaving only the resolution errors of gain, nonlinearity, and noise, thus allowing full 14-bit accuracy. Note that for the homebrew circuit, the OP07 specifications for input voltage offset and noise have been multiplied by √2. This is because a three op amp type in-amp has two op amps at its inputs, both contributing to the overall input error. R = 350Ω 10V PRECISION BRIDGE TRANSDUCER R = 350Ω R = 350Ω R = 350Ω 00775-0-039 AD620A MONOLITHIC INSTRUMENTATION AMPLIFIER, G = 100 SUPPLY CURRENT = 1.3mA MAX AD620A RG 499Ω REFERENCE 00775-0-040 Figure 37. Make vs. Buy "HOMEBREW" IN-AMP, G = 100 *0.02% RESISTOR MATCH, 3ppm/°C TRACKING **DISCRETE 1% RESISTOR, 100ppm/°C TRACKING SUPPLY CURRENT = 15mA MAX 100Ω ** 10kΩ * 10kΩ ** 10kΩ * 10kΩ * 10kΩ ** 10kΩ* OP07D OP07D OP07D 00775-0-041 Table 4. Make vs. Buy Error Budget Error, ppm of Full Scale Error Source AD620 Circuit Calculation “Homebrew” Circuit Calculation AD620 Homebrew ABSOLUTE ACCURACY at TA = 25°C Input Offset Voltage, μV 125 μV/20 mV (150 μV × √2)/20 mV 6,250 10,607 Output Offset Voltage, μV 1000 μV/100 mV/20 mV ((150 μV × 2)/100)/20 mV 500 150 Input Offset Current, nA 2 nA ×350 Ω/20 mV (6 nA ×350 Ω)/20 mV 18 53 CMR, dB 110 dB(3.16 ppm) ×5 V/20 mV (0.02% Match × 5 V)/20 mV/100 791 500 Total Absolute Error 7,559 11,310 DRIFT TO 85°C Gain Drift, ppm/°C (50 ppm + 10 ppm) ×60°C 100 ppm/°C Track × 60°C 3,600 6,000 Input Offset Voltage Drift, μV/°C 1 μV/°C × 60°C/20 mV (2.5 μV/°C × √2 × 60°C)/20 mV 3,000 10,607 Output Offset Voltage Drift, μV/°C 15 μV/°C × 60°C/100 mV/20 mV (2.5 μV/°C × 2 × 60°C)/100 mV/20 mV 450 150 Total Drift Error 7,050 16,757 RESOLUTION Gain Nonlinearity, ppm of Full Scale 40 ppm 40 ppm 40 40 Typ 0.1 Hz to 10 Hz Voltage Noise, μV p-p 0.28 μV p-p/20 mV (0.38 μV p-p × √2)/20 mV 14 27 Total Resolution Error 54 67 Grand Total Error 14,663 28,134 G = 100, VS = ±15 V. (All errors are min/max and referred to input.) AD620 Rev. H | Page 14 of 20 3kΩ 5V DIGITAL DATA OUTPUT ADC REF IN AGND 20kΩ 10kΩ 20kΩ G = 100 AD620B 1.7mA 0.10mA 0.6mA MAX 499Ω 3kΩ 3kΩ 3kΩ 2 1 8 3 7 6 5 4 1.3mA MAX AD705 00775-0-042 Figure 38. A Pressure Monitor Circuit that Operates on a 5 V Single Supply Pressure Measurement Although useful in many bridge applications, such as weigh scales, the AD620 is especially suitable for higher resistance pressure sensors powered at lower voltages where small size and low power become more significant. Figure 38 shows a 3 kΩ pressure transducer bridge powered from 5 V. In such a circuit, the bridge consumes only 1.7 mA. Adding the AD620 and a buffered voltage divider allows the signal to be conditioned for only 3.8 mA of total supply current. Small size and low cost make the AD620 especially attractive for voltage output pressure transducers. Since it delivers low noise and drift, it also serves applications such as diagnostic noninvasive blood pressure measurement. Medical ECG The low current noise of the AD620 allows its use in ECG monitors (Figure 39) where high source resistances of 1 MΩ or higher are not uncommon. The AD620’s low power, low supply voltage requirements, and space-saving 8-lead mini-DIP and SOIC package offerings make it an excellent choice for batterypowered data recorders. Furthermore, the low bias currents and low current noise, coupled with the low voltage noise of the AD620, improve the dynamic range for better performance. The value of capacitor C1 is chosen to maintain stability of the right leg drive loop. Proper safeguards, such as isolation, must be added to this circuit to protect the patient from possible harm. G = 7 AD620A 0.03Hz HIGHPASS FILTER OUTPUT 1V/mV +3V –3V RG 8.25kΩ 24.9kΩ 24.9kΩ AD705J G = 143 C1 1MΩ R4 10kΩ R1 R3 R2 OUTPUT AMPLIFIER PATIENT/CIRCUIT PROTECTION/ISOLATION 00775-0-043 Figure 39. A Medical ECG Monitor Circuit AD620 Rev. H | Page 15 of 20 Precision V-I Converter The AD620, along with another op amp and two resistors, makes a precision current source (Figure 40). The op amp buffers the reference terminal to maintain good CMR. The output voltage, VX, of the AD620 appears across R1, which converts it to a current. This current, less only the input bias current of the op amp, then flows out to the load. RG AD620 –VS VIN+ VIN– LOAD R1 IL Vx I L = R1 = IN+ [(V ) – (V IN – )] G R1 6 5 + VX – 2 4 1 8 3 7 +VS AD705 00775-0-044 Figure 40. Precision Voltage-to-Current Converter (Operates on 1.8 mA, ±3 V) GAIN SELECTION The AD620 gain is resistor-programmed by RG, or more precisely, by whatever impedance appears between Pins 1 and 8. The AD620 is designed to offer accurate gains using 0.1% to 1% resistors. Table 5 shows required values of RG for various gains. Note that for G = 1, the RG pins are unconnected (RG = ∞). For any arbitrary gain, RG can be calculated by using the formula: 1 49.4 − Ω = G k RG To minimize gain error, avoid high parasitic resistance in series with RG; to minimize gain drift, RG should have a low TC—less than 10 ppm/°C—for the best performance. Table 5. Required Values of Gain Resistors 1% Std Table Value of RG(Ω) Calculated Gain 0.1% Std Table Value of RG(Ω ) Calculated Gain 49.9 k 1.990 49.3 k 2.002 12.4 k 4.984 12.4 k 4.984 5.49 k 9.998 5.49 k 9.998 2.61 k 19.93 2.61 k 19.93 1.00 k 50.40 1.01 k 49.91 499 100.0 499 100.0 249 199.4 249 199.4 100 495.0 98.8 501.0 49.9 991.0 49.3 1,003.0 INPUT AND OUTPUT OFFSET VOLTAGE The low errors of the AD620 are attributed to two sources, input and output errors. The output error is divided by G when referred to the input. In practice, the input errors dominate at high gains, and the output errors dominate at low gains. The total VOS for a given gain is calculated as Total Error RTI = input error + (output error/G) Total Error RTO = (input error × G) + output error REFERENCE TERMINAL The reference terminal potential defines the zero output voltage and is especially useful when the load does not share a precise ground with the rest of the system. It provides a direct means of injecting a precise offset to the output, with an allowable range of 2 V within the supply voltages. Parasitic resistance should be kept to a minimum for optimum CMR. INPUT PROTECTION The AD620 safely withstands an input current of ±60 mA for several hours at room temperature. This is true for all gains and power on and off, which is useful if the signal source and amplifier are powered separately. For longer time periods, the input current should not exceed 6 mA. For input voltages beyond the supplies, a protection resistor should be placed in series with each input to limit the current to 6 mA. These can be the same resistors as those used in the RFI filter. High values of resistance can impact the noise and AC CMRR performance of the system. Low leakage diodes (such as the BAV199) can be placed at the inputs to reduce the required protection resistance. AD620 R REF R +SUPPLY –SUPPLY VOUT +IN –IN 00775-0-052 Figure 41. Diode Protection for Voltages Beyond Supply RF INTERFERENCE All instrumentation amplifiers rectify small out of band signals. The disturbance may appear as a small dc voltage offset. High frequency signals can be filtered with a low pass R-C network placed at the input of the instrumentation amplifier. Figure 42 demonstrates such a configuration. The filter limits the input AD620 Rev. H | Page 16 of 20 signal according to the following relationship: 2 (2 ) 1 D C DIFF R C C FilterFreq π + = C CM RC FilterFreq π = 2 1 where CD ≥10CC. CD affects the difference signal. CC affects the common-mode signal. Any mismatch in R × CC degrades the AD620 CMRR. To avoid inadvertently reducing CMRR-bandwidth performance, make sure that CC is at least one magnitude smaller than CD. The effect of mismatched CCs is reduced with a larger CD:CC ratio. 499Ω AD620 + – VOUT R R CC CD CC +IN –IN REF –15V 0.1μ F 10μ F +15V 0.1μ F 10μ F 00775-0-045 Figure 42. Circuit to Attenuate RF Interference COMMON-MODE REJECTION Instrumentation amplifiers, such as the AD620, offer high CMR, which is a measure of the change in output voltage when both inputs are changed by equal amounts. These specifications are usually given for a full-range input voltage change and a specified source imbalance. For optimal CMR, the reference terminal should be tied to a low impedance point, and differences in capacitance and resistance should be kept to a minimum between the two inputs. In many applications, shielded cables are used to minimize noise; for best CMR over frequency, the shield should be properly driven. Figure 43 and Figure 44 show active data guards that are configured to improve ac common-mode rejections by “bootstrapping” the capacitances of input cable shields, thus minimizing the capacitance mismatch between the inputs. REFERENCE VOUT AD620 100Ω 100Ω – INPUT + INPUT AD648 RG –VS +VS –VS 00775-0-046 Figure 43. Differential Shield Driver 100Ω – INPUT + INPUT REFERENCE VOUT AD620 –VS +VS 2 RG 2 RG AD548 00775-0-047 Figure 44. Common-Mode Shield Driver GROUNDING Since the AD620 output voltage is developed with respect to the potential on the reference terminal, it can solve many grounding problems by simply tying the REF pin to the appropriate “local ground.” To isolate low level analog signals from a noisy digital environment, many data-acquisition components have separate analog and digital ground pins (Figure 45). It would be convenient to use a single ground line; however, current through ground wires and PC runs of the circuit card can cause hundreds of millivolts of error. Therefore, separate ground returns should be provided to minimize the current flow from the sensitive points to the system ground. These ground returns must be tied together at some point, usually best at the ADC package shown in Figure 45. DIGITAL P.S. C +5V ANALOG P.S. +15V C –15V AD574A DIGITAL DATA OUTPUT + 1μF AD620 0.1μF AD585 S/H ADC 0.1μF 1μF 1μF 00775-0-048 Figure 45. Basic Grounding Practice AD620 Rev. H | Page 17 of 20 GROUND RETURNS FOR INPUT BIAS CURRENTS VOUT – INPUT + INPUT RG LOAD TO POWER SUPPLY GROUND REFERENCE +VS –VS AD620 00775-0-050 Input bias currents are those currents necessary to bias the input transistors of an amplifier. There must be a direct return path for these currents. Therefore, when amplifying “floating” input sources, such as transformers or ac-coupled sources, there must be a dc path from each input to ground, as shown in Figure 46, Figure 47, and Figure 48. Refer to A Designer’s Guide to Instrumentation Amplifiers (free from Analog Devices) for more information regarding in-amp applications. AD620 VOUT – INPUT RG TO POWER SUPPLY GROUND + INPUT REFERENCE +VS –VS LOAD 00775-0-049 Figure 47. Ground Returns for Bias Currents with Thermocouple Inputs 100kΩ AD620 VOUT – INPUT + INPUT RG LOAD TO POWER SUPPLY GROUND REFERENCE 100kΩ –VS +VS 00775-0-051 Figure 46. Ground Returns for Bias Currents with Transformer-Coupled Inputs Figure 48. Ground Returns for Bias Currents with AC-Coupled Inputs AD620 Rev. H | Page 18 of 20 AD620ACHIPS INFORMATION Die size: 1803 μm × 3175 μm Die thickness: 483 μm Bond Pad Metal: 1% Copper Doped Aluminum To minimize gain errors introduced by the bond wires, use Kelvin connections between the chip and the gain resistor, RG, by connecting Pad 1A and Pad 1B in parallel to one end of RG and Pad 8A and Pad 8B in parallel to the other end of RG. For unity gain applications where RG is not required, Pad 1A and Pad 1B must be bonded together as well as the Pad 8A and Pad 8B. 1A 1B 2 3 4 5 6 7 8A 8B LOGO 00775-0-053 Figure 49. Bond Pad Diagram Table 6. Bond Pad Information Pad Coordinates1 Pad No. Mnemonic X (μm) Y (μm) 1A RG −623 +1424 1B RG −789 +628 2 −IN −790 +453 3 +IN −790 −294 4 −VS −788 −1419 5 REF +570 −1429 6 OUTPUT +693 −1254 7 +VS +693 +139 8A RG +505 +1423 8B RG +693 +372 1 The pad coordinates indicate the center of each pad, referenced to the center of the die. The die orientation is indicated by the logo, as shown in Figure 49. AD620 Rev. H | Page 19 of 20 OUTLINE DIMENSIONS COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. 070606-A 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) SEATING PLANE 0.015 (0.38) MIN 0.210 (5.33) MAX 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 8 1 4 5 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) BSC 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 0.060 (1.52) MAX 0.430 (10.92) MAX 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE 0.005 (0.13) MIN Figure 50. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8). Dimensions shown in inches and (millimeters) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 0.310 (7.87) 0.220 (5.59) 0.005 (0.13) MIN 0.055 (1.40) MAX 0.100 (2.54) BSC 15° 0° 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) SEATING 0.008 (0.20) PLANE 0.200 (5.08) MAX 0.405 (10.29) MAX 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 1 4 8 5 Figure 51. 8-Lead Ceramic Dual In-Line Package [CERDIP] (Q-8) Dimensions shown in inches and (millimeters) CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. COMPLIANT TO JEDEC STANDARDS MS-012-AA 012407-A 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 1.75 (0.0688) 1.35 (0.0532) SEATING PLANE 0.25 (0.0098) 0.10 (0.0040) 1 4 8 5 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) BSC 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) COPLANARITY 0.10 Figure 52. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) AD620 Rev. H | Page 20 of 20 ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD620AN −40°C to +85°C 8-Lead PDIP N-8 AD620ANZ −40°C to +85°C 8-Lead PDIP N-8 AD620BN −40°C to +85°C 8-Lead PDIP N-8 AD620BNZ −40°C to +85°C 8-Lead PDIP N-8 AD620AR −40°C to +85°C 8-Lead SOIC_N R-8 AD620ARZ −40°C to +85°C 8-Lead SOIC_N R-8 AD620AR-REEL −40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8 AD620ARZ-REEL −40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8 AD620AR-REEL7 −40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8 AD620ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8 AD620BR −40°C to +85°C 8-Lead SOIC_N R-8 AD620BRZ −40°C to +85°C 8-Lead SOIC_N R-8 AD620BR-REEL −40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8 AD620BRZ-RL −40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8 AD620BR-REEL7 −40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8 AD620BRZ-R7 −40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8 AD620ACHIPS −40°C to +85°C Die Form AD620SQ/883B −55°C to +125°C 8-Lead CERDIP Q-8 1 Z = RoHS Compliant Part. © 2003–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00775–0–7/11(H) a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 1 of 18 a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 2 of 18 Table of Contents SUMMARY...................................................................................................................... 3 1 DEAD TIME EFFECTS AND THEIR COMPENSATION .......................................... 3 2 IMPLEMENTATION OF THE FEED FORWARD DEAD TIME COMPENSATION .. 5 2.1 Using the dt_comp routines ...........................................................................................................................5 2.2 Using the dt_comp routine.............................................................................................................................6 2.3 The program code...........................................................................................................................................7 3 EXAMPLE: TESTING THE VALIDITY OF THE FEED FORWARD DEAD TIME COMPENSATION........................................................................................................... 7 3.1 The construction of an inverter .....................................................................................................................7 3.2 The software program used to test the feed forward dead time compensation.........................................8 3.3 The main include file: main.h ......................................................................................................................12 3.4 The program offset.dsp and its header offset.h..........................................................................................12 3.5 Experimental results.....................................................................................................................................16 4 REFERENCES ....................................................................................................... 18 a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 3 of 18 Summary Due to the finite switching time, in order to prevent the appearance of short circuits, the power devices of an inverter must be commanded introducing a delay between their active times. This delay, called dead time because in this period no power device is active, introduces small voltage errors, which are sufficient to produce distorted motor currents, oscillations of the motor torque and therefore even the motor controllability may be lost [1]. This paper presents one method to compensate the effects of the dead time, the experimental hardware on which this method was tested and the assembly program associated with it. 1 Dead Time effects and their compensation Consider a voltage inverter with a motor connected at its output terminals (Figure 1). d V T1 T 2 T 3 T 4 T 5 T 6 D1 D2 D4 D6 D3 D5 0 1 ≥ s i 1 v Figure 1: Voltage source inverter The effects of the dead time may be examined by considering only the first phase of the inverter. On this phase it is desired to obtain the reference PWM signal * 1 v presented in Figure 2a. The signals used to command the power devices are assumed to be active LOW, which means that when they are LOW, the power devices conduct (Figures 2b and 2c). The output signal obtained at the motor terminal depends on the sense of the current flowing in this phase: In the case of the current flowing from inverter to the motor (assumed positive sense), when T2 conducts, the phase terminal is linked to the GND and the voltage 1 v is 0. During the dead time period, when both power devices are turned OFF, the current continues to flow into the motor using the reverse recovery diode D2, so 1 v will continue to be 0. When the upper power device T1 conducts, the phase terminal is connected to d V and 1 v is equal to d V . During the second half cycle, the phenomenon repeats itself a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 4 of 18 symmetrically. The final behaviour of 1 v is presented in Figure 2d. It may be observed that the average value of 1 v is less than the reference value by an amount determined by the dead time: d s V T DT v = v − ⋅ * 1 1 (1) DT DT 2 DT 2 s T * 1 v T1 T 2 0 1 1 ≥ s i v when 0 1 1 < s i v when a) b) c) d) e) d V d V * 1 T Figure 2: The influence of the dead time over the output phase voltage In the case of the current flowing from the motor to the inverter, when T2 conducts, the phase terminal is linked to the GND and the voltage 1 v is 0. During the dead time period, the current continues to flow from the motor using the reverse recovery diode D1, so 1 v will become equal to d V . When the upper power device T1 conducts, the phase terminal is connected to d V and 1 v will continue to be equal to d V . During the second half, the phenomenon repeats itself symmetrically. The final behaviour of 1 v is presented in Figure 2e. It may be observed that the average value of 1 v is greater than the reference value by an amount determined by the dead time: a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 5 of 18 d s V T DT v = v + ⋅ * 1 1 (2) Equations (1) and (2) provide the first method to compensate for the dead time: the feed-forward compensation. In relation of the current sense, the inverter phase will be commanded with a reference voltage ** 1 v such that the voltage 1 v at the inverter terminal will become equal with the reference voltage * 1 v : d s V T DT v = v + ⋅ * 1 ** 1 when i ≥ 0 (3) d s V T DT v = v − ⋅ * 1 ** 1 when i < 0 . These expressions mean that when the phase current is positive, the duty cycle * 1 T correspondent to * 1 v has to be increased by the dead time and when the phase current is negative, the duty cycle has to be decreased by the dead time. The only drawback of this method appears when the current changes its sign, because this moment cannot be foreseen. It is easily seen that when the sign is not correctly applied, an error of two times the dead time is introduced. Another method to compensate the dead time is the following: The actual inverter voltages are measured on every phase. The compensation is done adding to the reference phase voltage * 1 v a term proportional to the voltage error on that phase: ( 1) ( 1) [ ( ) ( )] 1 * 1 * 1 ** 1 v k + = v k + + K ⋅ v k − v k (4) where: - ** ( 1) 1 v k + is the voltage which will be commanded on the first inverter phase; - * ( 1) 1 v k + is the reference voltage which would have been commanded if the dead time compensation had not been considered; -K is the gain of the compensator, usually less than or equal to 1; - * ( ) 1 v k is the reference voltage which would have been commanded during the previous PWM cycle if the dead time compensation had not been considered; - ( ) 1 v k is the inverter phase voltage measured during the previous PWM cycle. The drawback of this method is that all the inverter phase voltages have to be measured. It is possible to measure only two inverter phases if the PWM modulation is space vector type or sinusoidal. 2 Implementation of the feed forward dead time compensation 2.1 Using the dt_comp routines The routines are developed as an easy-to-use library, which has to be linked to the user’s application. The library consists of two files. The file “dt_comp.dsp” contains the assembly code of the subroutines. The block has to be compiled and then linked to an application. The user has to include the header file dt_comp.h, which provides the function-like calls to the subroutines. The example file in Section 3 will demonstrate the usage of all the routines. a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 6 of 18 Operation Usage Compute On-times compensating the dead time DeadTime_Comp(StatorCurrent_struct, Dutycycles_struct) Table 1 Implemented routine The input vector StatorCurrents_struct consists of three elements, the three inverter phase currents. Because their sum is always zero, only two of them need to be measured. They have to be scaled because the DSP uses fixed point formats. The scaling factor is 2⋅ Imax , where max I represents the maximum current which may be placed at the input pin of the A/D converter. The 2 factor is used to prevent overflows when the currents are used in arithmetical operations. The vector Dutycycles_struct is an input and also an output: It represents the duty cycles for each phase, previously computed by the PWM modulator. After the compensation, they represent the duty cycles effectively commanded to the inverter. Their values have to be between 0 and PWMTM, the number which controls the PWM switching frequency. DeadTime_comp represents a macro, which must be introduced into the program code if the dead time compensation is desired. The format of inputs and outputs are explained in more detail in the next section. The routines do not require any configuration constants from the main include-file “main.h” that comes with every application note. For more information about the general structure of the application notes and including libraries into user applications refer to the Library Documentation File. Section 2.2 shows an example of usage of this library. In the following sections each routine is explained in detail with the relevant segments of code which is found in either “dt_comp.h” or “dt_comp.dsp”. For more information see the comments in those files. 2.2 Using the dt_comp routine The macro listed in the Table 1 is based on a subroutine called DeadTime_Comp_. It is described in detail in the next section. The following table gives an overview of what DSP registers are used in this macro: Macro Input1 and modified DAG registers Output2 Modified core registers DeadTime_Comp I1 = ^ StatorCurrents_struct; M1, M2 = 1; L1, L2 = 0; I2 = ^ Dutycycles_struct; M3 = 0; N/A AX0, AY0, AY1, MR, AR Table2. DSP core registers used in the macro This macro has to be placed in the main program after the PWM reference duty cycles are computed, but prior to the program that saves them into the duty cycle registers PWMCHA, PWMCHB, PWMCHC. 1 ^vector stands for ‘address of vector’. 2 N/A: The output values are stored in the output vector in the Data memory. No DSP core register is used. a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 7 of 18 2.3 The program code The following code contained in the file dt_comp.dsp describes the routine DeadTime_Comp_ mentioned in the previous section. The routine is organised as a loop managed by the loop counter cntr. At each iteration, one phase current from the buffer StatorCurrents_struct is tested and the compensation is done function of its sign. In the end, the new duty cycle number is tested to ensure it is positive and less than the maximum admissible value, PWMTM. The last instruction saves the number back into the buffer Dutycycles_struct. DeadTime_Comp_: AY0 = DM(PWMDT); { dead time normalized } AY1 = dm(PWMTM); CNTR = 3; do dead_loop until ce; ax0 = DM(I1, M1); { ax0 = Isk, k=1,2,3 } mr1 = DM(I2, M3); { load Ta, Tb, Tc } AR = MR1 + AY0; none = pass ax0; {chek sign of the currents } IF LT AR = MR1 - AY0; none = pass AR; if lt AR = PASS 0; { no negative values admitted} af = AR - AY1; if gt ar = pass ay1; { protection against overflows} dead_loop: DM(I2, M2) = ar; rts; 3 Example: Testing the validity of the feed forward dead time compensation 3.1 The construction of the inverter The proposed compensation method was implemented on the ADMC331 Processor Board mounted on an ADMC Connector Board. As inverter power part was used an evaluation platform produced by International Rectifier, IRPT2056D Driver-Plus Board. It is a three phase 230VAC 3HP board and it integrates all the processing components needed for a 3 HP motor drive. It is equipped with an IRPT2056A IGBT power module and an IR2133J driver. The Analog Devices’ ADMC PWM isolation board linked the Connector Board to the Power Board. This board produces an electric isolation between the digital part and the inverter power part and also inverts the signals used to drive the power devices (74HC240). Because the signals used by the driver IR2133J are active LOW and because of the inverting line driver HC240, the PWM outputs of the ADMC331 are set to be active HIGH. Therefore the jumper JP51 is in position 1-2. 1 See the ADMC331 Processor Board manual, Motion Control Group, Analog Devices, 1998 a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 8 of 18 The inverter is driving an induction motor with the following characteristics: .13HP, 230V, 60Hz, 1725rpm, produced by Baldor. Because the power part is supplied with 110V, the maximum frequency the motor may be run in the constant torque regime is: c f 3 110 2 60 3 230 2 ⋅ = ⋅ f Hz c 28.7 230 110 60 = ⋅ = Because the compensation needs the value of the inverter phase currents, two of them were sensed using current transducers HA 10-NP produced by LEM. They are capable to measure up to 20A and this value is used to scale down the measured values: I 20A max = . Also, an operational amplifier LM348 is used to obtain the signal into the range of A/D converter of ADMC331: 0.3V÷3.5V. On the ADMC331 Processor Board there are 5KHz filters that have an anti-aliasing role. A block structure of the inverter is presented in Figure 3. ADMCConnector Board ADMC331 Processor Board IRPT2056D Driver Plus Board ADMC PWM Isolation Board .13HP Induction Motor 2xHP10-NP s1 I s 2 I Figure 3. Inverter Block structure 3.2 The software program used to test the feed forward dead time compensation The purpose of this program is to demonstrate the improvement offered by the feed forward dead time compensation. It reads two motor currents, commands the motor to run at 14Hz, half of the cut frequency c f and compensates for the dead time. The file main.dsp contains the root program. The batch file build.bat compiles every file of the project, links them together and builds the executable file main.exe. It may be applied either within DOS prompt or clicking on it from Windows Explorer. Main.exe may be run on the Motion Control Debugger. A brief description of the program will be given in the following: Start of code - declaring start location in program memory .MODULE/RAM/SEG=USER_PM1/ABS=0x30 Main_Program; a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 9 of 18 Next, the general systems constants and PWM configuration constants (main.h – see the next section) are included. Also included are the PWM library2, the DAC interface3 and the space vector modulation4 module definitions. The header file offset.h declares some macros used to measure the offset introduced by the current transducers and autocal.h declares the macros used to calibrate the ADMC331 A/D converter. {*************************************************************************************** * Include General System Parameters and Libraries * ***************************************************************************************} #include ; #include ; #include ; #include ; #include ; #include ; #include ; #include ; #include ; { Application Specific Module } #include ; #include ; #include ; Constants used in this program {*************************************************************************************** * Constants Defined in the Module * ***************************************************************************************} .CONST CUT_FREQ = 28; {the cutting frequency of the tested motor} .CONST Delta = 32768*2*CUT_FREQ/PWM_freq; {the increment of the angle} .CONST TwoPiOverThree = 0xffff / 3; { Hex equivalent of 2pi/3 } .CONST ALLOFF = 0x3F; { Used to disable IGBTies into PWMSEG } Here is where all the vectors for the program are declared. The buffer StatorCurrents_struct represents the three stator currents. The PWM duty cycles are stored in the buffer Dutycycles_struct and they are initialised with 0.It may be seen that the variables which identify the current offsets, Is1Offset and Is2Offset are declared circular because programming becomes easier. The average of the readings is computed on 32bit precision, so every buffer consists of 2 words. {*************************************************************************************** * Local Variables Defined in this Module * ***************************************************************************************} .VAR/DM/RAM/SEG=USER_DM AD_IN; { Volts/Hertz Command (0-1) } 2 see AN331-03: Three-Phase Sine-Wave Generation using the PWM Unit of the ADMC331 3 see AN331-06: Using the Serial Digital to Analog Converter of the ADMC Connector Board 4 see AN331-17: Implementing Space Vector Modulation with the ADMC331 a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 10 of 18 .INIT AD_IN : 0x3A0A; { Corresponds to 0.906/2 } .VAR/DM/RAM/SEG=USER_DM Theta; { Current angle } .INIT Theta : 0x0000; .VAR/DM/RAM/SEG=USER_DM Vdq_ref[2]; { rotor ref.frame } .VAR/DM/RAM/CIRC/SEG=USER_DM Valphabeta_ref[2]; { alphabeta frame } .VAR/RAM/DM/SEG=USER_DM OnTime_struct[1*4]; .INIT OnTime_struct: 0x0000, 0x0000, 0x0000, 0x0000; .VAR/RAM/DM/SEG=USER_DM Dutycycles_struct[1*3]; .INIT Dutycycles_struct: 0x0000, 0x0000, 0x0000; .VAR/DM/RAM/SEG=USER_DM VrefA; { Voltage demands } .VAR/DM/RAM/SEG=USER_DM VrefB; .VAR/DM/RAM/SEG=USER_DM VrefC; .INIT VrefA : 0x0000; .INIT VrefB : 0x0000; .INIT VrefC : 0x0000; .VAR/DM/RAM/SEG=USER_DM StatorCurrents_struct[1*3]; { stator currents } .VAR/DM/RAM/SEG=USER_DM Is1Offset[1]; .VAR/DM/RAM/SEG=USER_DM Is2Offset[1]; When the program begins, the PWM output signals are disabled. Then, the power module is reset and the PWM block is set up to generate interrupts every 100μsec (see main.h in the next section). There is initialised the D/A serial converter1 and there is unmasked the IRQ2 interrupt (the interrupt which manages the peripheral interrupts on ADMC331). The main loop just waits for interrupts. {********************************************************************************************} { Start of program code } {********************************************************************************************} Startup: Write_DM(PWMSEG, ALLOFF); { the IGBTies are disabled } IR_reset_PIO3; { Reset PowIRTrain Module } PWM_Init(PWMSYNC_ISR, PWMTRIP_ISR); DAC_Init; { Initialize the DAC-Module } IFC = 0x80; { Clear any pending IRQ2 inter. } ay0 = 0x200; { unmask irq2 interrupts. } ar = IMASK; ar = ar or ay0; 1 See ADMC Connector board user’s manual for further details a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 11 of 18 IMASK = ar; { IRQ2 ints fully enabled here } ADC_Init; { ADC Counter will Operate at the DSP CLKOUT Frequency } AutoCal_Init; { Initialize the Auto Calibration Routine } Offset_Init; { offset.h } Main: { Wait for interrupt to occur } jump Main; During the PWM_SYNC interrupt there are executed some routines which determine the internal offset of the A/D converter1, the external offsets introduced by the current transducers and the measurement of the currents. The successive routines generate three PWM signals of 14Hz obtained applying a continuous space vector modulation2. The dead time compensation is placed at the end of this block. Finally, the signals that will be provided to the D/A converter are computed. {********************************************************************************************} { PWM Interrupt Service Routine } {********************************************************************************************} PWMSYNC_ISR: Auto_Calibrate; { autocal.h } OffsetDetermination(ADC1, ADC2, Is1Offset, Is2Offset); { offset.h } ReadCurrents(Is1Offset, Is2Offset, StatorCurrents_struct, ADC1, ADC2); { offset.h } DAC_Pause; { Required only when I1, M1 or L1 is used} ar = DM (AD_IN ); mr = 0; {Clear mr } mr1 = dm(Theta); {Preload Theta} my0 = Delta; mr = mr + ar*my0 (SS); {Compute new angle & store} dm(Theta) = mr1; DM(Vdq_ref )= ar; {Set constant Vdq reference (AD_IN,0)} ar = pass 0; DM(Vdq_ref+1)= ar; refframe_Set_DAG_registers_for_transformations; refframe_Forward_Park_angle(Vdq_ref,Valphabeta_ref,mr1); {generate Vreference in alpha-beta frame} SVPWM_Calc_Ontimes(Valphabeta_ref, OnTime_struct); { use SVPWM routines} SVPWM_Calc_Dutycycles(OnTime_struct, Dutycycles_struct); DeadTime_Comp(StatorCurrents_struct, Dutycycles_struct); SVPWM_Update_DutyCycles(Dutycycles_struct); Dac_Resume; my0 = DM(Theta); DAC_Put(1, my0); { output on DACs, amplified by multiplication } mx0 = 0x8; my0 = DM(Dutycycles_struct ); mr = mx0 * my0 (SS); Dac_Put(2, mr0); my0 = DM(Dutycycles_struct+1); mr = mx0 * my0 (SS); Dac_Put(3, mr0); 1 See AN331-05: ADC-system on the ADMC331. 2 See AN331-17: Implementing Space Vector Modulation with ADMC331 a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 12 of 18 AX0 = dm(Dutycycles_struct); AY0 = Half_PWMTM; AR = AX0 - AY0; MY0 = 0x6523; {2/PWMTM=2/1296*2^15/2^6*2^15} MR = AR * MY0 (SS); SR = ASHIFT MR1 BY 6 (HI); SR = SR OR LSHIFT MR0 BY 6 (LO); DAC_Put(4, SR1); sr1 = DM(StatorCurrents_struct); sr = ASHIFT sr1 BY 5 (HI); DAC_Put(5,sr1); sr1 = DM(StatorCurrents_struct+1); sr = ASHIFT sr1 BY 5 (HI); DAC_Put(6, sr1); SR1 = DM(StatorCurrents_struct+2); sr = ASHIFT sr1 BY 5 (HI); DAC_Put(7, sr1); DAC_Update; RTI; 3.3 The main include file: main.h This file contains the definitions of ADMC331 constants, general-purpose macros, the configuration parameters of the system and library routines. It should be included in every application. For more information refer to the Library Documentation File. This file is mostly self-explaining. As already mentioned, the dt_comp library does not require any configuration parameters. The following table presents the parameters used to initialise the PWM block .It may be emphasized the dead time period set at 6μsec, a large value for the power devices used on the IRPT2056D. {********************************************************************************************} { Library: PWM block } { file : PWM331.dsp } { Application Note: Usage of the ADMC331 Pulse Width Modulation Block } .CONST PWM_freq = 10000; {Desired PWM switching frequency [Hz] } .CONST PWM_deadtime = 6000; {Desired deadtime [nsec] } .CONST PWM_minpulse = 1000; {Desired minimal pulse time [nsec] } .CONST PWM_syncpulse = 1540; {Desired sync pulse time [nsec] } .CONST Half_PWMTM = 1000*Cry_clock/PWM_freq/2; {********************************************************************************************} 3.4 The program offset.dsp and its header offset.h The current transducers introduce an offset that has to be evaluated, otherwise the sign of the currents would be determined with large errors. For this reason, at the beginning of the program, for a certain number of PWM cycles (in this particular case 128, but may be more or less depending on the system) there are measured the A/D channels corresponding to the two phase currents, V1 and V2. The average of all measurements constitutes the offset of that current. Of course, this procedure may be applied at every channel, if the signal is zero at the beginning of the program. The header file offset.h contains the macros that are used during this process. Generally, they call subroutines presented in the file offset.dsp. This file begins declaring the variables OffsetCounter, TempOffset1 and TempOffset2 used in these routines. a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 13 of 18 {*************************************************************************************** * Global Variables Defined in this Module * ***************************************************************************************} .VAR/DM/RAM/SEG=USER_DM OffsetCounter[1]; .GLOBAL OffsetCounter; .VAR/DM/RAM/CIRC/SEG=USER_DM TempOffset1[2]; .GLOBAL TempOffset1; .VAR/DM/RAM/CIRC/SEG=USER_DM TempOffset2[2]; .GLOBAL TempOffset2; The subroutine Offset_Init_ initialises the variables used to evaluate the offsets of the current transducers. OffsetCounter is set to 128 because the offsets are considered the average of 128 measurements. {************************************************************************************* * Type: Routine * * Call: Call Offset_Init_; * * This subroutine initializes the variables initializes variables used to * * evaluate the offsets of the current sensors * * Inputs : None * * Ouputs :None * * Modified: AR * ***************************************************************************************} Offset_Init_: AR = Offset_Average; dm(OffsetCounter) = AR; AR = 0x0; dm(TempOffset1) = AR; dm(TempOffset1+1) = AR; dm(TempOffset2) = AR; dm(TempOffset2+1) = AR; rts; The subroutine EvaluateIs_offset_ computes the average of the measurements of a particular A/D channel. {*************************************************************************************** * Type: Routine * * Call: Call EvaluateIs_offset_; * * This subroutine computes the average of the measurements of one A/D channel * * Inputs : AR = the lecture of the A/D channel * I1 = placed at the begining of the buffer which is averaged * * M1 = 0, L1 = 0 * * Ouputs :None * * Modified: AY1, AY0, AR, SR, AX0 * ***************************************************************************************} EvaluateIs_offset_: AY1 = dm(I1, M1); a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 14 of 18 AY0 = dm(I1, M1); AR = 0x4000 - AR; SR = ASHIFT AR BY -7 (HI); AR = SR0 + AY0; AX0 = AR, AR = SR1 + AY1 + C; dm(I1, M1) = AR; dm(I1, M1) = AX0; RTS; . In the file offset.h there is a macro Offset_Init that initialises the address generators at the current offsets buffers and then calls the subroutine Offset_Init_ from offset.dsp. {*************************************************************************************** * Type: Macro * * Call: Offset_Init; * * This macro initializes variables used to evaluate the offsets of the current sensors * * Input: none * * Output: none * * Modified: AR * ***************************************************************************************} .MACRO Offset_Init; CALL Offset_Init_; .ENDMACRO; The macro EvaluateIs_offset reads one A/D channel and computes the average offset of that channel calling the subroutine EvaluateIs_offset_. {*************************************************************************************** * Type: Macro * * Call: EvaluateIs_offset; * * Routine to compute the offset of one phase * * Input: %0=the targeted AD channel * * %1=the offset structure dedicated to the phase * * %1=most significant word * * %1+1=less significant word * * Output: Current Offset structure * * Modified: * ***************************************************************************************} .MACRO EvaluateIs_offset(%0, %1); ADC_Read(%0); I1 = ^%1; M1 = 1; L1 = %%1; a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 15 of 18 CALL EvaluateIs_offset_; .ENDMACRO; The macro OffsetDetermination computes the offsets of the both A/D channels that measure the phase currents. {*************************************************************************************** * Type: Macro * * Call: OffsetDetermination * * Routine to compute the offsets introduced by the current sensors * * Input: %0=ADC1 * * %1=ADC2 * * %2=Is1Offset * * %3=Is2Offset * * Output: Current Offsets structure * * Modified: * ***************************************************************************************} .MACRO OffsetDetermination(%0, %1, %2, %3); AY0 = dm(OffsetCounter); AR = AY0 - 1; IF LT JUMP SaveOffsets; dm(OffsetCounter) = AR; EvaluateIs_offset(%0, TempOffset1); EvaluateIs_offset(%1, TempOffset2); RTI; SaveOffsets: AF = AR + 1; IF NE JUMP ExitOffsetDet; dm(OffsetCounter) = AR; AR = dm(TempOffset1); dm(%2) = AR; AR = dm(TempOffset2); dm(%3) = AR; ExitOffsetDet: .ENDMACRO; The macro ReadCurrents reads the two phase currents, corrects them with the offset and finally computes the third phase current. It may be noted that the output of the A/D converter is always a positive number. Because of the presence of an inverting operational amplifier in the hardware, in order to obtain values between –1/2 and +1/2 (in fixed point the currents are scaled by 2⋅ Imax ) the outputs of the A/D converter have to be offset by 1/2 (0x4000). {*************************************************************************************** * Type: Macro * * Call: ReadCurrents; * a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 16 of 18 * This macro reads ADC1(Is1), ADC2(Is2) and then evaluates Is1, Is2 and Is3 * * Input: %0 = offset of the first phase current * * %1 = offset of the second phase current * * %2 = the buffer of the 3 phase currents * * %3 = ADC1 * * %4 = ADC2 * * Output: none * * Modified: AY0, AR, MY0, MR, SR ,AF * ***************************************************************************************} .MACRO ReadCurrents(%0, %1, %2, %3, %4); ADC_Read(%3); { read Is1/Imax } AR = 0x4000 - AR; AY0 = dm(%0); AR = AR - AY0; dm(%2) = AR; { Is1/2Imax } ADC_Read(%4); { read Is2/Imax } AR = 0x4000 - AR; AY0 = dm(%1); AR = AR - AY0; dm(%2+1) = AR; { Is2/2Imax } AR = -AR; AY0 = dm(%2); { Is1/2Imax } AR = AR - AY0; dm(%2+2) = AR; { Is3/2Imax=-Is2/2Imax-Is1/2Imax} .ENDMACRO; 3.5 Experimental results First of all, experiments without the dead time compensation were made. Figure 4 represents the inverter phase voltage compared to the reference voltage that is desired at the inverter terminal and the phase current. It may be seen that the behavior presented in chapter 1 is verified in practice: When the phase current is positive, the real inverter phase voltage is less than the commanded one by an amount determined by the dead time and when the phase current is negative, the real inverter phase voltage is greater than the commanded. At last, Figure 5 displays the inverter phase voltage and the phase current obtained with the feed forward dead time compensation. It may be observed that the voltage still presents some distortions caused by the nature of feed forwarding: it is supposed that the current measured during the previous PWM cycle maintains its sign into the next PWM cycle; when the current changes the sign, this moment cannot be foreseen and the error is doubled. These voltage deformations cause also deformations in the current behaviour, and they may be prevented only implementing current controllers in a more accurate control strategy, like field-oriented control. a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 17 of 18 Figure 4. Reference and real inverter phase voltages and the phase current a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 18 of 18 Figure 5. Inverter phase voltage and phase current after the dead time compensation 4 References [1] Pulse dead time compensator for PWM voltage inverters, David Leggate, Russel J. Kerkman, Industrial Electronics, Control, and Instrumentation, 1995, Proceedings of the 1995 IEEE IECON 21st International Conference on Volume: 1, Page(s): 474 -481 vol.1. SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 􀀀 Wide Operating Voltage Range of 2 V to 6 V 􀀀 Typical Switch Enable Time of 18 ns 􀀀 Low Power Consumption, 20-μA Max ICC 􀀀 Low Input Current of 1 μA Max 􀀀 High Degree of Linearity 􀀀 High On-Off Output-Voltage Ratio 􀀀 Low Crosstalk Between Switches 􀀀 Low On-State Impedance . . . 50-Ω TYP at VCC = 6 V 􀀀 Individual Switch Controls description/ordering information The SN74HC4066 is a silicon-gate CMOS quadruple analog switch designed to handle both analog and digital signals. Each switch permits signals with amplitudes of up to 6 V (peak) to be transmitted in either direction. Each switch section has its own enable input control (C). A high-level voltage applied to C turns on the associated switch section. Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP – N Tube of 25 SN74HC4066N SN74HC4066N Tube of 50 SN74HC4066D SOIC – D Reel of 2500 SN74HC4066DR HC4066 Reel of 250 SN74HC4066DT –40°C to 85°C SOP – NS Reel of 2000 SN74HC4066NSR HC4066 SSOP – DB Reel of 2000 SN74HC4066DBR HC4066 Tube of 90 SN74HC4066PW TSSOP – PW Reel of 2000 SN74HC4066PWR HC4066 Reel of 250 SN74HC4066PWT † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each switch) INPUT CONTROL (C) SWITCH L OFF H ON PRODUCTION DATA information is current as of publication date. Copyright  2003, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1A 1B 2B 2A 2C 3C GND VCC 1C 4C 4A 4B 3B 3A D, DB, N, NS, OR PW PACKAGE (TOP VIEW) SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 logic diagram, each switch (positive logic) A VCC VCC B One of Four Switches C absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Control-input diode current, II (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA I/O port diode current, II (VI < 0 or VI/O > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA On-state switch current (VI/O = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground unless otherwise specified. 2. The package thermal impedance is calculated in accordance with JESD 51-7. SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 recommended operating conditions (see Note 3) MIN NOM MAX UNIT VCC Supply voltage 2† 5 6 V VI/O I/O port voltage 0 VCC V VCC = 2 V 1.5 VCC VIH High-level input voltage, control inputs VCC = 4.5 V 3.15 VCC V VCC = 6 V 4.2 VCC VCC = 2 V 0 0.3 VIL Low-level input voltage, control inputs VCC = 4.5 V 0 0.9 V VCC = 6 V 0 1.2 VCC = 2 V 1000 Δt/Δv Input transition rise/fall time VCC = 4.5 V 500 ns VCC = 6 V 400 TA Operating free-air temperature –40 85 °C † With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital signals be transmitted at these low supply voltages. NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS V TA = 25􀀀C VCC MIN MAX UNIT MIN TYP MAX I A V 0t V 2 V 150 ron On-state switch resistance IT = –1 mA, VI = 0 to VCC, 4.5 V 50 85 106 Ω VC = VIH (see Figure 1) 6 V 30 V V GND V V 2 V 320 ron(p) Peak on-state resistance VI = VCC or GND, VC = VIH, ( ) 4.5 V 70 170 215 Ω IT = –1 mA 6 V 50 II Control input current VC = 0 or VCC 6 V ±0.1 ±100 ±1000 nA Isoff Off-state switch leakage current VI = VCC or 0, VO = VCC or 0, VC = VIL (see Figure 2) 6 V ±0.1 ±5 μA Ison On-state switch leakage current VI = VCC or 0, VC = VIH (see Figure 3) 6 V ±0.1 ±5 μA ICC Supply current VI = 0 or VCC, IO = 0 6 V 2 20 μA Ci Input capacitance A or B 5 V 9 pF C 3 10 10 Cf Feed-through capacitance A to B VI = 0 0.5 pF Co Output capacitance A or B 5 V 9 pF SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended operating free-air temperature range PARAMETER FROM TO TEST VCC TA = 25􀀀C MIN MAX UNIT (INPUT) (OUTPUT) CONDITIONS MIN TYP MAX t P ti C 50 F 2 V 10 60 75 tPLH, Propagation A or B B or A CL = pF 4.5 V 4 12 15 ns tPHL delay time (see Figure 4) 6 V 3 10 13 t S it h RL = 1 kΩ, 2 V 70 180 225 tPZH, tPZL Switch turn-on time C A or B CL = 50 pF 4.5 V 21 36 45 ns L (see Figure 5) 6 V 18 31 38 t S it h RL = 1 kΩ, 2 V 50 200 250 tPLZ, Switch C A or B CL = 50 pF 4.5 V 25 40 50 ns tPHZ turn-off time L (see Figure 5) 6 V 22 34 43 Control CL = 15 pF, RL = 1 kΩ 2 V 15 fI input frequency C A or B kΩ, VC = VCC or GND, V V /2 4.5 V 30 MHz VO = VCC/(see Figure 6) 6 V 30 Control feed-through C A or B CL = 50 pF, Rin = RL = 600 Ω, VC = VCC or GND 4.5 V 15 mV noise GND, fin = 1 MHz (see Figure 7) 6 V 20 (rms) operating characteristics, VCC = 4.5 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance per gate CL = 50 pF, f = 1 MHz 45 pF Minimum through bandwidth, A to B or B to A† [20 log (VO/VI)] = –3 dB CL = 50 pF, VC = VCC RL = 600 Ω, (see Figure 8) 30 MHz Crosstalk between any switches‡ CL = 10 pF, fin = 1 MHz RL = 50 Ω, (see Figure 9) 45 dB Feed through, switch off, A to B or B to A‡ CL = 50 pF, fin = 1 MHz RL = 600 Ω, (see Figure 10) 42 dB Amplitude distortion rate, A to B or B to A CL = 50 pF, fin = 1 kHz RL = 10 kΩ, (see Figure 11) 0.05% † Adjust the input amplitude for output = 0 dBm at f = 1 MHz. Input signal must be a sine wave. ‡ Adjust the input amplitude for input = 0 dBm at f = 1 MHz. Input signal must be a sine wave. SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PARAMETER MEASUREMENT INFORMATION VCC VI = VCC VC = VIH + 1.0 mA – VO ron 􀀀 VI–O 10–3 􀀀 VI–O VCC GND (ON) V Figure 1. On-State Resistance Test Circuit VCC VC = VIL A B VS = VA – VB CONDITION 1: VA = 0, VB = VCC CONDITION 2: VA = VCC, VB = 0 VCC GND A (OFF) Figure 2. Off-State Switch Leakage-Current Test Circuit SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION VCC VC = VIH A B VCC Open VA = VCC TO GND VCC GND A (ON) Figure 3. On-State Leakage-Current Test Circuit VCC VC = VIH VI VO 50 pF TEST CIRCUIT tPLH tPHL 50% 50% VCC 0 V 50% 50% VOH VOL VI A or B VO B or A VOLTAGE WAVEFORMS 50 Ω tr 90% 10% tf 10% 90% VCC GND (ON) Figure 4. Propagation Delay Time, Signal Input to Signal Output SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PARAMETER MEASUREMENT INFORMATION CL GND 50 pF VCC VI VO TEST CIRCUIT tPLZ 50% VOLTAGE WAVEFORMS RL 1 kΩ 10% S1 VC 50 Ω S2 tPZH tPHZ 50% 50% 50% 90% tPZL tPZH tPLZ tPHZ GND VCC GND VCC TEST S1 S2 VCC GND VCC GND tPZL 50% VCC VO 50% 0 V VOL VOH VC (tPZL, tPZH) (tPLZ, tPHZ) VCC VCC VO 0 V VOL VOH VC VCC 0 V VOL VOH VCC 0 V VOL VOH Figure 5. Switching Time (tPZL, tPLZ, tPZH, tPHZ), Control to Signal Output SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION VCC GND VO RL 1 kΩ CL 15 pF VCC VC 50 Ω VI = VCC VCC VC 0 V VCC/2 Figure 6. Control-Input Frequency VCC GND VO RL 600 Ω CL 50 pF VCC VC 50 Ω VI VCC/2 Rin 600 Ω VCC/2 tr tf 90% 10% (f = 1 MHz) tr = tf = 6 ns 90% 10% VCC VC 0 V Figure 7. Control Feed-Through Noise VO VCC 50 Ω fin VCC/2 VC = VCC 0.1 μF VI VI (VI = 0 dBm at f = 1 MHz) VCC GND (ON) RL 600 Ω CL 50 pF Figure 8. Minimum Through Bandwidth SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PARAMETER MEASUREMENT INFORMATION VO1 RL 600 Ω CL 50 pF VCC 50 Ω fin VCC/2 VC = VCC 0.1 μF VI VI (VI = 0 dBm at f = 1 MHz) VO2 VCC Rin 600 Ω VCC/2 VC = GND Rin 600 Ω VCC GND (ON) VCC GND (OFF) RL 600 Ω CL 50 pF Figure 9. Crosstalk Between Any Two Switches VO VCC 50 Ω fin VC = GND 0.1 μF VI VI (VI = 0 dBm at f = 1 MHz) VCC GND (OFF) Rin 600 Ω RL 600 Ω CL 50 pF VCC/2 VCC/2 Figure 10. Feed Through, Switch Off VI (VI = 0 dBm at f = 1 kHz) VO RL 10 kΩ CL 50 pF VCC VCC/2 VC = VCC 10 μF VI fin VCC GND (ON) Figure 11. Amplitude-Distortion Rate PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN74HC4066D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066DBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI -40 to 85 SN74HC4066DBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066DBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066DT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC4066N SN74HC4066NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC4066N SN74HC4066NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI -40 to 85 SN74HC4066PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066PWT ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 2 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN74HC4066DBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74HC4066DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC4066DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC4066NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74HC4066PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HC4066PWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC4066DBR SSOP DB 14 2000 367.0 367.0 38.0 SN74HC4066DR SOIC D 14 2500 367.0 367.0 38.0 SN74HC4066DT SOIC D 14 250 367.0 367.0 38.0 SN74HC4066NSR SO NS 14 2000 367.0 367.0 38.0 SN74HC4066PWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74HC4066PWT TSSOP PW 14 250 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01 28 PINS SHOWN Gage Plane 8,20 7,40 0,55 0,95 0,25 38 12,90 12,30 28 10,50 24 8,50 Seating Plane 7,90 9,90 30 10,50 9,90 0,38 5,60 5,00 15 0,22 14 A 28 1 16 20 6,50 6,50 14 0,05 MIN 5,90 5,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 0,15 M 0°–8° 0,10 0,09 0,25 NOTES: A. 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This application note describe the use of a tracebuffer structure where values treated in the DSP can be saved in a data-array and used for internal of external modification interfaced though the Motion Control Debugger system. 1 The Tracebuffer Structure A data-array structure is defined to enable saving arrays of values in data-memory (DM). This array of memory locations can be addressed by the use of the pointer-system on the 2171 core. With this structure defined, further treating or evaluation of the internal data-calculations can be analyzed and checked for errors. Using the Motion Control Debugger the values can be either be plotted directly or dumped for analyzing the data-array in other external programs In the chosen structure any number of pointer arrays in DM can be enabled and individually initialized for locations in DM. The structure will furthermore allow the user to under-sample the writing to the buffer. Initialize the Tracebuffer Though macro Is the Sample Ratio = Sample number? Is Flag enabled ? Is there still space in the Buffer Full ? YES No YES No Update Buffer and increment pointer and counter End Macro; Macro Call YES No Figure 1 - Flowchart for the Buffer writing The flow chart illustrate the structure of the trace buffer writing. Initialization is done in the startup sequence. After this, the Flag is checked - is the flag set then the corresponding tracebuffer is enabled. Secondly the buffer is checked for available spaces. If the DM locations defined for memory write aren't full it is safe to go on. If the buffer is full return. Finally the sample-ratio is checked. If a sample-ratio is a Using a Tracebuffer with the ADMCF32X ANF32X-34 © Analog Devices Inc., March 2000 Page 4 of 11 declared different from zero then check if the sample-number is equal to the sample-ratio. If it is write the chosen variable to the data-array. If not, return to the subroutine. The structure of the buffer is circular and to optimize the flexibility the format is provided as a complete macro setting with locked data-array format. 1.1 The Tracebuffer Data-Array To enable the tracebuffer array in DM it is necessary to define a given circular buffer with associated pointer. The circular buffer is structured as: First location : Statement of flag - ON/OFF Second location : Pointer to next free address Third location : Sample ratio (specified by the user) Fourth location : Sample number (used during the re-sampling of values) Fifth location : Counter for the buffer. Sixth to XXX locations : Placement for the values Every time the macro is called, Ex. in the PWMSYNC_ISR, a new value is added to the buffer if there are available space left and the sample number is equal to the under-sample ratio. DM(Address) Flag (ON/OFF) DM(Address+1) Pointer to next free address .. Sample ratio .. Sample number .. Counter for Buffer .. First Data-placement .. Value(1) .. Value(2) .. .. .. .. .. .. .. Value (Buffer size -2) .. Value (Buffer size -1) .. Value (Buffer size) Figure 2 - Tracebuffer - locations in DM Figure 2 illustrates how the values are placed in the allocated DM locations. Here values are stored at specific addresses in order to analyze these off-line. First value Placed in the buffer N = numbers in tracebuffer Buffer full a Using a Tracebuffer with the ADMCF32X ANF32X-34 © Analog Devices Inc., March 2000 Page 5 of 11 2 Implementation of the Tracebuffer Library Routines 2.1 Usage of the tracebuffer routines The routines are developed as an easy-to-use library, which has to be linked to the user’s application. The library consists of two files. The file “T_buffer.dsp” contains the assembly code for the subroutines. This package has to be compiled and can then be linked to an application. The user has to include the header file “T_buffer.h”, which provides the function-like macros for this routine. The following table summarizes the set of macros that are defined in this library. Operation Usage Input Output Initialization Buffer_Init("name", sample ratio); Name & Sample ratio None Activate Buffer_ON("name"); Name None Deactivate Buffer_OFF("name"); Name None Record Buffer_Record("name", value); Name & Value None Table 1: Implemented routines The four-macro settings allow the user to setup any given DM-locations for trace-buffer availability. Specifying the selected buffer and record value enables the flexibility of writing any number to a known position in memory. 2.2 Usage of the DSP registers Table 2 gives an overview of the DSP core registers that are modified by the four macros mentioned above. Obviously, also the "input" values are modified. Usage Modified registers Buffer_Init("name", sample ratio); ax0 Buffer_OFF("name"); ax0 Buffer_ON("name"); ax0 Buffer_Record("name", value); ax0, ax1, ay0, ar, I5, M5 Table 2: Usage of DSP core registers for the subroutines a Using a Tracebuffer with the ADMCF32X ANF32X-34 © Analog Devices Inc., March 2000 Page 6 of 11 2.3 Access to the library: the header file Including the header file "t_buffer.h" into the application code may access the library. The header file is intended to provide function-like macros to the Trace buffer routines. It defines the calls shown in Table 1. The file is mostly self-explaining but some comments have to be added. The sample ratio is here defined as how often is a new value can be written to the buffer. First macro is the Buffer_Init macro. This macro initializes the five first location of the circular buffer in respect to "name of the buffer" and the sample-ratio. Furthermore the sample-number and the internal counter is cleared. The second and third macro Buffer_ON and Buffer_OFF just enables or disables writing to the buffers. In this case the first location in the buffer ( the flag ) are set/or cleared. {******************************************************************************** * * * Type: Macro * * * * Call: Buffer_Init("Buffer", sampleratio) * * Description : Initialize the tracebuffer * * * * Undersample ratio 0 = every time * * 1 = every 1.time * * 2 = every 2.time ..... * * * * Ouputs : none * * * * Modified: ax0 * * * ********************************************************************************} .MACRO Buffer_Init(%0,%1); ax0 = %1; { Sample ratio } dm(%0+2)= ax0; ax0 =^%0+5; { Store start value } dm(%0+1)= ax0; { first location for data } ax0 = 0x0000; dm(%0) = ax0; { Clear Flag - Non-Active } dm(%0+3)= ax0; { Clear sample number } dm(%0+4)= ax0; { Clear counter for this buffer } .ENDMACRO; {******************************************************************************** * * * Type: Macro * * * * Call: Buffer_ON("buffer") * * * * Description : Enable tracebuffer "Buffer" * * Ouputs : none * * * * Modified : ax0 * * * ********************************************************************************} .MACRO Buffer_ON(%0); ax0 = 1; dm(%0) = ax0; .ENDMACRO; a Using a Tracebuffer with the ADMCF32X ANF32X-34 © Analog Devices Inc., March 2000 Page 7 of 11 {******************************************************************************** * * * Type: Macro * * * * Call: Buffer_OFF("buffer") * * * * Description : Disable tracebuffer "Buffer" * * Ouputs : none * * * * Modified : ax0 * * * ********************************************************************************} .MACRO Buffer_OFF(%0); ax0 = 0; dm(%0) = ax0; .ENDMACRO; 2.4 The program macro The following code contained in the file “t_buffer.h” defines the macrocode used for the Tracebuffer. In many cases this piece of code is placed in the "t_buffer.dsp"-file but here the flexibility advances by placing the program-code directly in the macro. It should be mentioned that this way of using the tracebuffer enables flexibility but takes up more memory. The following code implements the tracebuffer routines. Refer to the flowchart in section 1 for the structure of the buffers. Input to the tracebuffer are any numbers computed in the DSP. Underneath is the code for the Buffer_Record.. It just need to be said that since the buffer is structured as a circular buffer the data-placement for each of the "buffer-handle" values are placed from buffer-location 1 to 5 (here %0….%0+4) {******************************************************************************** * * * Type: Macro * * * * all: Buffer_Record(buffer,data) * * * * Description : Place data in buffer memory * * Ouputs : none * * * * Modified: M5, I5, ar, ax1, ax0, ay0 * * * ********************************************************************************} .MACRO Buffer_Record(%0,%1); .Local Continue1,Continue2,Continue3,End; { Local routines in Macro } M5 = 1; { modify factor = 1 } ax1 = %1; I5 = ^%0; { load start value for pointer } ar = dm(%0); { temporary storage } ar= tstbit 0 of ar; if NE jump Continue1; Jump end; Continue1: ax0 = %%0; ay0 = dm(%0+4); ar = ax0 - ay0; if gt jump Continue2; ax0 = 0x0000; dm(%0) = ax0; Jump end; a Using a Tracebuffer with the ADMCF32X ANF32X-34 © Analog Devices Inc., March 2000 Page 8 of 11 Continue2: { is sample_num equal to ratio? } ax0 = dm(%0+3); ay0 = dm(%0+2); ar = ax0 - ay0; if eq jump Continue3; ar = ax0 + 1; dm(%0+3) = ar; Jump end; Continue3: { write into buffer } I5 = dm(%0+1); { load backup value for pointer } dm(I5,M5) = ax1; { Value updated to Buffer } ax0 = dm(%0+4); { increment count } ar = ax0 + 1; dm(%0+4) = ar; ax0 = 0x0000; { clear sample_num } dm(%0+3) = ax0; dm(%0+1) = I5; end: .ENDMACRO; 3 Software Example: Tracebuffer 3.1 Usage of the Tracebuffer routine an example This example demonstrates how two values are written to Buffer1 and Buffer2. In this case the memorylocations used as buffers are set to 2*105-locations (100 location of calculated data). The values written to these two buffer-arrays are values computed for three 120-degree phase shifted reference voltages. 3.2 The main program: main.dsp The file “main.dsp” contains the initialisation and PWM Sync and Trip interrupt service routines. To activate, build the executable file using the attached build.bat either within your DOS prompt or clicking on it from Windows Explorer. This will create the object files and the main.exe example file. This file may be run on the Motion Control Debugger. The program can be booted from Flash but in this tracebuffer case it is not effectuated since the DM can not be read without the Motion Control Debugger. Every module besides from the Main_program module is by default placed in either one of the three USERFLASH memory banks. In the following, a brief description of the code is given. Start of code – declaring start location in program memory or FLASH memory. Comments are placed depending on whether the program should run in PMRAM or Flash memory. {************************************************************************************** * Application: Starting from FLASH (out-comment the one not used) **************************************************************************************} !.MODULE/RAM/SEG=USERFLASH1/ABS=0x2200 Main_Program; {************************************************************************************** * Application: Starting from RAM (out-comment the one not used) **************************************************************************************} .MODULE/RAM/SEG=USER_PM1/ABS=0x30 Main_Program; a Using a Tracebuffer with the ADMCF32X ANF32X-34 © Analog Devices Inc., March 2000 Page 9 of 11 Next, the general systems constants and PWM configuration constants (main.h – see the next section) are included. Also included are the PWM library and the T_BUFFER library definitions {******************************************************************************** * Include General System Parameters and Libraries * ********************************************************************************} #include ; #include ; #include ; #include ; {******************************************************************************** * Local Variables Defined in this Module * ********************************************************************************} .VAR/DM/RAM/SEG=USER_DM AD_IN; { Volts/Hertz Command (0-1) } .VAR/DM/RAM/SEG=USER_DM Theta; { Current angle } .VAR/DM/RAM/SEG=USER_DM VrefA; { Voltage demands } .VAR/DM/RAM/SEG=USER_DM VrefB; .VAR/DM/RAM/SEG=USER_DM VrefC; .VAR/DM/RAM/CIRC/SEG=USER_DM Buffer1[105]; { Tracebuffer } .VAR/DM/RAM/CIRC/SEG=USER_DM Buffer2[105]; { Tracebuffer } ar = 0x7FFF; dm(AD_IN) = ar; ar = 0x0000; dm(Theta) = ar; dm(VrefA) = ar; dm(VrefB) = ar; dm(VrefC) = ar; Some Variables are defined hereafter. These are used to calculate the three reference voltages. For further information see ANF32X-3. The two circular buffers are defined - here the size is 105 locations (5 locations are used for handling the buffer) this number is arbitrary - just depending on the memory locations occupied by these buffers. The first thing that is done in the initialisation block (Startup) is checking a selected PIO line for level. If the PIO-pin is high jump to an ERASE BOOT FROM FLASH BIT routine in ROM and return. If not, just go ahead with normal operation. This small macro is done to enable re-coding of the FLASH memory. For further information (See Reference Manual). In this example the PIO-pin 6 is chosen as erase pin. The initialisation of the PWM block is executed. Note how the interrupt vectors for the PWMSync and PWMTrip service routines are passed as arguments. Then the interrupt IRQ2 is enabled by setting the corresponding bit in the IMASK register. Two Tracebuffers are initialised with 1x under-sampling Then the Tracebuffers are activated by setting the flag (Buffer_ON(Buffer1) & Buffer_ON(Buffer2)). After that, the program enters a loop, which just waits for interrupts. {******************************************************************************** * Start of program code * ********************************************************************************} Startup: FLASH_erase_PIO(6); { Select PIO6 as clearing PIO } { Remember that sport1 is muxed with the PIO-lines } { If the bit is high Clear Memory and Boot from } { Flash bit } PWM_Init(PWMSYNC_ISR, PWMTRIP_ISR); IFC = 0x80; { Clear any pending IRQ2 inter. } ay0 = 0x200; { unmask irq2 interrupts. } ar = IMASK; ar = ar or ay0; IMASK = ar; { IRQ2 ints fully enabled here } Buffer_Init(Buffer1, 1); { 1x undersampling } Buffer_Init(Buffer2, 1); { 1X undersampling } Buffer_ON(Buffer1); { Activate the Buffer } Buffer_ON(Buffer2); { Activate the Buffer } Main: { Wait for interrupt to occur } jump Main; rts; a Using a Tracebuffer with the ADMCF32X ANF32X-34 © Analog Devices Inc., March 2000 Page 10 of 11 In the PWMSYNC_ISR the DAGS are first set up for trigonometric functionality. Three reference voltages VrefA,B and C are calculated on base of the trigonometric functions in the Trigonometric-library ( See ANF32X-10 ). The PWM block is update with these control signals and finally the two Tracebuffers Buffer1 and Buffer2 are updated. Here the variables VrefA and VrefB are stored in the two data-arrays. PWMSYNC_ISR: Set_DAG_registers_for_trigonometric; my0 = DM(AD_IN); mr = 0; { Clear mr } mr1 = dm(Theta); { Preload Theta } mx0 = Delta; mr = mr + mx0*my0 (SS); { Compute new angle & store } dm(Theta) = mr1; Sin(mr1); { Result in ar register } mr = ar*my0 (SS); { Multiply by Scale for VrefA } dm(VrefA) = mr1; ax1 = dm(Theta); { Compute angle of phase B } ay1 = TwoPioverThree; ar = ax1 - ay1; Sin(ar); { Result in ar register } mr = ar*my0 (SS); { Multiply by Scale for VrefB } dm(VrefB) = mr1; ax1 = dm(Theta); { Compute angle of phase C } ay1 = TwoPioverThree; ar = ax1 + ay1; Sin(ar); { Result in ar register } mr = ar*my0 (SS); { Multiply by Scale for VrefC } dm(VrefC) = mr1; ax0 = DM(VrefA); ax1 = DM(VrefB); ay0 = DM(VrefC); ay1= DM(Theta); PWM_update_demanded_Voltage(ax0,ax1,ay0); {******************************************************************************* * Update tracebuffers * *******************************************************************************} ax0 = DM(VrefA); Buffer_Record(Buffer1,ax0); ax0 = DM(VrefB); Buffer_Record(Buffer2,ax0); RTI; It has to be mentioned that the Buffer_Record macro uses some DSP registers (see T_buffer.h) for that reason the proposed way of writing to the buffer is as defined above. 4 Experimental results The experimental results illustrated beneath are two plots of VrefA and VrefB. These values are written into Buffer1 and Buffer2 and then plotted though the Motion Control Debugger. As can be seen on Figure 3 the two waveforms are plotted as a function of the given number in Buffer1 and 2. From the figures the scaling can also be seen - here the numbers are represented in decimal. Selecting another scaling of these reference-voltages will re-scale these plots. a Using a Tracebuffer with the ADMCF32X ANF32X-34 © Analog Devices Inc., March 2000 Page 11 of 11 Figure 3 - Plot from the Motion Control Debugger using the Internal Plot Function. www.analog.com Developing VisualAudio Modules Copyright Information © 2006 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc. Trademark and Service Mark Notice The Analog Devices logo, VisualDSP++, VisualAudio, SHARC, Blackfin, and EZ-KIT Lite are registered trademarks of Analog Devices, Inc. All other brand and product names are trademarks or service marks of their respective owners. 2 of 51 Contents Contents..............................................................................................................................................................................................................3 Preface.................................................................................................................................................................................................................4 Purpose of This Manual................................................................................................................................................................................4 Custom Audio Modules....................................................................................................................................................................................5 Overview.........................................................................................................................................................................................................5 Numerics on the Blackfin and SHARC.......................................................................................................................................................9 Example 1A – Mono Parametric Scaling....................................................................................................................................................9 Example 1B – Render Function in ASM.................................................................................................................................................19 Scratch Buffers............................................................................................................................................................................................22 Auxiliary Memory for Module Instances................................................................................................................................................22 Pointer Aliasing Rules................................................................................................................................................................................25 Meta-Variables and Expressions...............................................................................................................................................................26 Modifying Module Parameters.................................................................................................................................................................27 Expression Language Details.....................................................................................................................................................................28 Modules With Data of Varying Size.........................................................................................................................................................33 Modules With a Variable Number of Pins...............................................................................................................................................34 Frequency Domain Processing.................................................................................................................................................................36 Other Features of the XML File................................................................................................................................................................36 Custom Bypass Functions..........................................................................................................................................................................38 SHARC SIMD Considerations..................................................................................................................................................................38 Adjusting Modules from Other Modules................................................................................................................................................39 Dynamically Changing a Module’s Render Function............................................................................................................................39 Compatibility between Blackfin and SHARC Modules.........................................................................................................................39 Reference Section............................................................................................................................................................................................41 AudioProcessing.h Structures...................................................................................................................................................................41 Module Memory Sections.........................................................................................................................................................................44 Summary of Naming Conventions...........................................................................................................................................................45 Inspector Control Types............................................................................................................................................................................47 XML Format................................................................................................................................................................................................50 Index.................................................................................................................................................................................................................51 3 of 51 Preface PURPOSE OF THIS MANUAL The VisualAudio Designer Users’ Guide explains how to use VisualAudio to develop audio processing software for a wide variety of products. The guide describes the graphical interface, provides step-by-step procedures for completing tasks, and contains detailed technical information on how to integrate the generated code into your final product. Intended Audience The primary audience for this manual is a programmer who is familiar with Analog Devices, Inc. processors. This manual assumes that the audience can use the VisualDSP++ development environment to develop, build, and debug Digital Signal Processing (DSP) applications for the SHARC or Blackfin processor. 4 of 51 Custom Audio Modules This document explains how to write an audio processing module for VisualAudio for SHARC processors in the 26x and 36x families, as well as for Blackfin processors in the 53x and 56x families. Audio modules allow audio processing (sometimes called “post-processing”) to be implemented by making use of a number of smaller, self-contained processing blocks. The topics are organized as follows. • “Overview” • “Numerics on SHARC and Blackfin” • “Example 1A – Mono parameter scaling” • “Example 1B – Render function in ASM” • “Scratch Buffers” • “Auxiliary Memory for Module Instances” • “Pointer Aliasing Rules” • “Meta-variables and Expressions” • “Modifying Module Parameters” • “Expression Language Details” • “Modules with Data of Varying Size” • “Modules with Variable Numbers of Pins” • “Other Features of the XML File” • Custom Bypass Functions” • “SHARC SIMD Considerations” • “Adjusting Modules from Other Modules” • “Dynamically Changing a Module’s Render Function” • “Compatibility between Blackfin and SHARC Modules” OVERVIEW This section includes a brief philosophical review of what motivated certain design decisions, a discussion about the quasi-object orientation inherent in the module concept, a description of usage scenarios and a high-level description of the parts of a module. Design Philosophy The module format was designed with the following goals in mind. • Minimal run-time processor footprint • CPU efficiency • Straightforward to write and use Several key features help accomplish these goals. • VisualAudio does as much work as possible at compile and assembly time to enable the production DSP code to be lean, while still providing a flexible environment for creating and deploying modules. • Modules process a block of samples at a time to ensure that the cost of loading and storing state and parameters is incurred only once per block instead of once per sample. • VisualAudio supports interleaved stereo connections between modules to enable a common use of Single-Instruction, Multiple-Data (SIMD) on the SHARC DSP. This signal type is also supported on the Blackfin, primarily for compatibility with system designs originating on SHARCs. 5 of 51 • VisualAudio supports signals at both the audio sampling rate and a lower “control rate.” This allows slowly-changing control signals to use less memory and MIPS. • VisualAudio supports a variety of frequency domain signal types, as well as a user-settable FFT size and hop factor for “overlap-add” and “overlap-save” style processing. • Some of the spirit of object-oriented programming is borrowed, while a lean approach is maintained. Note that C++ is not used. • To keep the CPU usage (MIPS) of a module relatively constant, a module instance should perform roughly the same operations every time it runs. Assume the module’s worst case CPU usage. The exception is when there are clear modes. In this case, the user can plan in advance the combination of module modes that will be in use at a particular time. • In keeping with the goals of near-constant CPU usage and minimal memory usage, parameter calculation (such as filter design) is normally pushed forward to design time, and implemented outside the DSP runtime (for example within VisualAudio Designer). Therefore, modules usually do not contain design or initialization code on the DSP. Instead, module instances are normally initialized and designed via static initialization of their state structures (in code generated by VisualAudio Designer or by the user).1 Module Terminology Each type of processing module is represented by its own module class. These are instantiable; multiple instances of each class may exist at the same time. We use the term module when the distinction between the class and the instance is clear from context. Examples of modules include “Scaler N Smoothed” and “Delay).” The behavior of modules is adjusted via render variables. These are variables that exist on the DSP as part of the module instance structure. In addition, VisualAudio Designer presents high-level interface variables for each module. Interface variables are those exposed via module inspectors within VisualAudio Designer. An interface variable may correspond directly to a render variable. Alternatively, an interface variable may be mapped to a render variable through some function; for example, translating a delay time in milliseconds to a sample delay. Other possibilities include more complicated dependencies, where one or more interface variables touch one or more render variables. Render variables are defined in associated .h files detailing the instance structure of each module; interface variables are defined in associated .xml files. Interface variables are sometimes referred to as high-level variables, while render variables are sometimes referred to as low-level variables. There are three kinds of render variables, differing in restrictions on when they are set: • Constants are typically set only at design time (i.e. their value doesn’t usually change at run time.) • Parameters are typically set at design or tuning time from VisualAudio Designer, or by DSP control code • States can be set by the module’s render function itself, as well as by VisualAudio Designer in tuning mode or by DSP control code. Within VisualAudio Designer, these restrictions are enforced. On the DSP itself, it is up to the user to abide by these guidelines as appropriate. The term render variable is used to distinguish it from a meta-variable, which exists only in VisualAudio Designer’s representation of the module, not on the DSP. Thus, the set of interface variables contains some render variables and some meta-variables. Modules are interconnected via pins. Pins may be designated as either input or output. Either may be of type stereo_pcm, mono_pcm or control. The stereo_pcm and mono_pcm pins are collectively referred to as “audio rate pins,” or simply “audio 1 In stand-alone usage (without VisualAudio Designer) or when modules are implemented in terms of other modules, allocation can be either dynamic or static and initialization DSP code is often included. 6 of 51 pins.” Control rate pins are referred to as “control pins” and are of type control. Frequency domain pins may be of the following types: spectrum_real, spectrum_complex, spectrum_half_real and spectrum_half_complex. These are explained in more detail later. There are two kinds of modules: those that have a fixed number of pins, and those in which the number of input and/or output pins varies from instance to instance. A module class may have outputs, but no inputs, in which case it can be thought of as a signal generator (such as a sine wave generator). Or, it can have inputs, but no outputs, and report its results in a state variable (such as a VU meter). Finally, a module can have neither outputs nor inputs, and can do its work entirely in terms of side effects to itself (modifying its own state) or to other modules (modifying the render variables of other modules). Such a module could be used, for example, in testing other modules, when strictly-repeatable sample-synchronous updates are needed. Render functions must never write to their inputs. To see why this is true, consider a module whose output fans out to several other modules. If the first module wrote to its input, it would corrupt the input to the second module. However, the VisualAudio Designer routing algorithm knows the overall connection between audio modules and may reuse the same patch buffer for the input and output of a module, when it is safe. For more details, see Pointer Aliasing Rules below. Module Usage Scenarios There are two ways that VisualAudio modules can be used: • In a drag-and-drop fashion from VisualAudio Designer - Memory allocation, parameter setting and calling of the render function are handled automatically. • As C-callable functions in a stand-alone library - Memory allocation, parameter setting and calling of the render function are all handled by the user’s C or assembly code. Even if a module is used in drag-and-drop fashion, its render variables may be modified in the DSP program’s control code (sometimes referred to as “user control code.”) Similarly, a module used in a drag-and-drop fashion may include, in its implementation, a render function that calls other render functions using the stand-alone style. This document contains information on developing modules that may be used in either style of usage. For more information on usage, see the document VisualAudio Module Library Usage Guide. For more information on the particular modules supplied by VisualAudio, see VisualAudio Module Library Reference for Blackfin and VisualAudio Module Library Reference for SHARC. Module Modes When used within a layout generated by VisualAudio Designer1, a module may be in one of four modes. These can be set at runtime with the following function: AMFSetModuleStatus(AMF_Module *module, AMF_ModuleStatus status) The possible status values and their meanings are given below. • AMFModuleStatus_ACTIVE. The module processes its inputs and writes its outputs via its render function each time it is run. This is the default mode. Note that a module may have several alternative render functions, but one must be specified as the default. • AMFModuleStatus_INACTIVE. The module is not run. This implies that its outputs are not written, leaving their contents undefined. • AMFModuleStatus_MUTED. The module's outputs are zeroed each time it is run. This behavior is provided automatically. You need not write any code to implement this mode. 1 More specifically, when used with the VisualAudio Layout Support library. 7 of 51 • AMFModuleStatus_BYPASSED. The module performs the bypass function, which means that its input(s) are copied to its output(s) each time it is run. The default algorithm copies audio inputs to audio outputs, copies signal inputs to signal outputs, and mutes unused outputs. Where there is a mono/stereo mismatch, stereo is converted to mono by adding the channels and dividing by two; mono is converted to stereo by duplicating the channel. Alternatively, the module designer may provide a custom bypass function. For more information, see How to Write a Custom Bypass Function below. The default bypass algorithm copies the Nth input pin of a given type to the Nth output pin of the same type. For example, the 3rd control pin input is copied to the 3rd control pin output. If there are more output pins than input pins, the remainder are muted. Note that for the purposes of bypass, stereo and mono pins are considered the same type. If a mono input matches a stereo output, the mono input is duplicated on both channels. If a stereo input matches a mono output, the stereo channels are added and divided by 2. Parts of a Module A module consists of these parts: • A header (.h) file that defines the run-time interface to the module, including the instance structure typedef. The name of this file must be the same as the module name with .h (for example, AMF_Scaler.h). • The module’s run-time DSP code, in source or binary form (e.g., to protect any intellectual property). The VisualAudio Module Library is delivered in binary form as a VisualDSP++ .dlb file, and the source is also included. If delivered in source form, the module must contain the following two parts: • The module’s render function, which implements the module’s primary function • The module’s class object, which describes the module to the run-time system • A .xml file that describes the module to VisualAudio Designer in detail. This file is not required if the module is never used with VisualAudio Designer. The name of this file must be the same as the module name, with .xml appended (for example, AMF_Scaler.xml where “AMF” stands for Audio Module Format). The .xml file includes information about what files constitute the module’s run-time and header files, as well as information about the module’s parameters, and may also include simple design formulas. How to Add a Module to VisualAudio Designer To make a custom SHARC module available to VisualAudio Designer, create a directory (we’ll call it xxx) and put the XML, include, source files and object files1 in sub-directories. For the SHARC, the subdirectories should be: • XML files in xxx\SHARC\XML\ • Header files in xxx\SHARC\Include\ • Source files in xxx\SHARC\Source\ • Object files in xxx\SHARC\Lib For the Blackfin, they should be: • XML files in xxx\Blackfin\XML\ • Header files in xxx\Blackfin\Include\ • Source files in xxx\Blackfin\Source\ • Object files in xxx\Blackfin\Lib Where xxx is your Modules directory. You must then add your Modules directory to the list of directories searched by VisualAudio Designer. See the VisualAudio Designer User's Guide for details. 1 Third parties can protect their IP by delivering it as a library (a .dlb). Alternatively, they can deliver it is as a pre-compiled or pre-assembled object file (a .doj). 8 of 51 You must add your custom module source files to the VisualDSP++ project (.dpj) file for your platform. In contrast, when a module is included in object form (.dlb or .doj), it is automatically added to the linker list via the VALinkerCmds.txt file. NUMERICS ON THE BLACKFIN AND SHARC The primary difference between Blackfin and SHARC modules is the use of floating point on the SHARC. On the Blackfin, floating point is not available in hardware; hence Blackfin modules typically operate in fixed point. The basic VisualAudio signal type on the Blackfin is fract32, a 32-bit 1.31 format fraction. The basic VisualAudio signal type on the SHARC is a float, a 32-bit floating point number. To ease the task of moving between SHARC and Blackfin, VisualAudio defines a type AMF_Signal, which is fract32 for Blackfin and float for SHARC. Most SHARC modules use floating point internally. However, extended precision SHARC modules may use fixed point internally. Most Blackfin modules use fixed point internally. A number of conventions have been established for fixed-point processing on the Blackfin. We recommend that custom modules obey these conventions for maximum compatibility: The default format for fixed point coefficients is 1.31. Coefficients which perform a “volume scaling” can be 16 bits (typically 1.15 format), so that faster 16x32 multiplication can be used (as opposed to 32x32), since a volume-like scale tends not to need to be represented with an extremely high precision. Smoothing of 16-bit coefficients may need to be performed at 32 bits (to allow the smoothing to move at very slow smoothing rates), but the top 16 bits can still be used for doing the volume scaling cheaply. Headroom in signals is assumed to be managed by the layout creator, not by the module or by VisualAudio. Therefore, except where noted, a Blackfin module assumes 1.31 input and output signals, and for compatibility a SHARC module assumes signals where 1.0f corresponds to maximum amplitude (though clipping to +/- 1.0 is only implemented at the output). Saturating arithmetic is used in fixed point modules. In fixed point modules, multiplications implemented to “31-bit” precision (i.e. discarding the low order product as a speed optimization) may be used as a satisfactory substitute for full 32x32 multiplications. 16 bit types (fract16 and int16 ) as module variables are not supported on the SHARC in VisualAudio. The module implementer is responsible for creating correct alignment in the module state structure, if necessary (via padding and/or ordering). This is an issue only with Blackfin modules. The structures allocated by VisualAudio Designer can be assumed to be aligned to 32-bit boundaries. EXAMPLE 1A – MONO PARAMETRIC SCALING The following example shows a parametric scaling of a mono signal, for both SHARC and Blackfin versions of VisualAudio Example 1A Header File: AMF_Scaler.h The example module’s header file is shown below, for the SHARC or Blackfin version of VisualAudio: /***** Begin AMF_Scaler.h *******/ // Include header file with base class definitions: #include "AudioProcessing.h" // Instance structure typedef 9 of 51 typedef struct { AMF_Module b; // Parameters AMF_Signal amplitude; } AMF_Scaler; // Class object declaration extern const AMF_ModuleClass AMFClassScaler; /**** End AMF_Scaler.h *****/ Notice that the instance structure begins with an embedded struct of type AMF_Module. All module instance structures must begin in this manner (this allows any module’s struct to be interpreted as an AMF_Module, hence implementing a form of inheritance). This struct is followed by a single render variable, amplitude. The structure for the Blackfin and SHARC versions of the module are identical, except for the definition of AMF_Signal as fract32 instead of float in AudioProcessing.h. Example 1A Code File: AMF_Scaler.c The example module’s C code file is AMF_Scaler.c. The first half of the C file for the SHARC version of the module is listed below and analyzed in detail, with comparisons to the Blackfin version as necessary. /****** Begin AMF_Scaler.c *********/ #include "AMF_Scaler.h" // The module's header file #pragma optimize_for_speed // VisualDSP++ directive SEG_MOD_FAST_CODE void AMF_Scaler_Render( AMF_Scaler *restrict instance, AMF_Signal * restrict * buffers, int tickSize) { int i; AMF_Signal *in = buffers[0]; AMF_Signal *out = buffers[1]; AMF_Signal amplitude = instance->amplitude; #pragma SIMD_for for (i=0; iamplitude; #pragma SIMD_for for (i=0; iamplitude; for (i=0; i tag with value 2. To make it easy to supply values for the type vector, the following macros are supplied: #define AMF_StereoPin(whichPin) \ (AMFPinType_STEREO<<(whichPin*4)) #define AMF_ControlPin(whichPin) \ (AMFPinType_CONTROL<<(whichPin*4)) #define AMF_MonoPin(whichPin) (0) #define AMF_SpectrumRealPin(whichPin) \ (AMFPinType_SPECTRUM_REAL<<(whichPin*4)) #define AMF_SpectrumComplexPin(whichPin) \ (AMFPinType_SPECTRUM_COMPLEX<<(whichPin*4)) #define AMF_SpectrumHalfRealPin(whichPin) \ (AMFPinType_SPECTRUM_HALF_REAL<<(whichPin*4)) #define AMF_SpectrumHalfComplexPin(whichPin) \ (AMFPinType_SPECTRUM_HALF_COMPLEX<<(whichPin*4)) Type descriptors can then be assembled by bitwise OR’ing of these macros. Note that the whichPin argument is zero-based. For example, if a module has one mono input followed by one stereo input, its input type designator could be written as: (AMF_MonoPin(0) | AMF_StereoPin(1)) Alternatively, it could be written directly as 0x10. If there are more than eight pins, then the high order nibble is assumed to be sticky and applies to all pins beyond eight. However, there are situations where this convention is inadequate, such as when a pin greater than the 8th has a type differing from the 8th. For these situations, an indirect form is available as follows: 13 of 51 If the AMF_ModuleClass flags field includes the bit AMFModuleClassFlag_INDIRECT_INPUT_PIN_TYPE, then the input type descriptor is actually a pointer to an array of sufficient length to support bit vectors for all input pins. Similarly, if the flags include the bit AMFModuleClassFlag_INDIRECT_OUTPUT_PIN_TYPE, then the output type descriptor is actually a pointer to an array of sufficient length to support bit vectors for all input pins. In modules with variable number of pins (described in a later section of this document), the input and output type descriptors are in the instance, rather than the class. Example 1A XML File: AMF_Scaler.xml The .xml file describes the module to VisualAudio Designer. In this discussion, we assume a minimal familiarity with XML. Please note that all module xml element type attributes (i.e. type = “string”, type = “float” etc.) are optional as of VisualAudio 1.6 and therefore, are not shown in the examples below. When creating a custom module, we recommend copying the XML file from an existing module, renaming the XML file, and modifying it. At the outermost level, the XML file looks like this: . . . It begins by telling the XML parser where to find the VisualAudio Designer schema, which is used to validate the file.1 Validating the file ensures that it has all the information needed by VisualAudio Designer, that it is structured correctly, that the fields are listed in the proper order, and that it contains legal values for the required fields. The actual module definition is inside the body of the tag, which includes the information detailed below. Module Fields A module has several different self-description tags • The