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Branding Farnell element14 (France)

 

Farnell Element 14 :

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Everything You Need To Know About Arduino

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Tutorial 01 for Arduino: Getting Acquainted with Arduino

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The Cube® 3D Printer

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What's easier- DIY Dentistry or our new our website features?

 

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Ben Heck's Getting Started with the BeagleBone Black Trailer

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Ben Heck's Home-Brew Solder Reflow Oven 2.0 Trailer

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Get Started with Pi Episode 3 - Online with Raspberry Pi

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Discover Simulink Promo -- Exclusive element14 Webinar

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Ben Heck's TV Proximity Sensor Trailer

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Ben Heck's PlayStation 4 Teardown Trailer

See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…

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Get Started with Pi Episode 4 - Your First Raspberry Pi Project

Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.

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Ben Heck Anti-Pickpocket Wallet Trailer

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Molex Earphones - The 14 Holiday Products of Newark element14 Promotion

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Tripp Lite Surge Protector - The 14 Holiday Products of Newark element14 Promotion

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Microchip ChipKIT Pi - The 14 Holiday Products of Newark element14 Promotion

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Beagle Bone Black - The 14 Holiday Products of Newark element14 Promotion

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3M E26, LED Lamps - The 14 Holiday Products of Newark element14 Promotion

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3M Colored Duct Tape - The 14 Holiday Products of Newark element14 Promotion

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Tenma Soldering Station - The 14 Holiday Products of Newark element14 Promotion

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Duratool Screwdriver Kit - The 14 Holiday Products of Newark element14 Promotion

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Cubify 3D Cube - The 14 Holiday Products of Newark element14 Promotion

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Bud Boardganizer - The 14 Holiday Products of Newark element14 Promotion

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Raspberry Pi Starter Kit - The 14 Holiday Products of Newark element14 Promotion

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Fluke 323 True-rms Clamp Meter - The 14 Holiday Products of Newark element14 Promotion

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Dymo RHINO 6000 Label Printer - The 14 Holiday Products of Newark element14 Promotion

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3M LED Advanced Lights A-19 - The 14 Holiday Products of Newark element14 Promotion

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Innovative LPS Resistor Features Very High Power Dissipation

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Charge Injection Evaluation Board for DG508B Multiplexer Demo

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Ben Heck The Great Glue Gun Trailer Part 2

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Introducing element14 TV

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Ben Heck Time to Meet Your Maker Trailer

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Détecteur de composants

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Recherche intégrée

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Ben Builds an Accessibility Guitar Trailer Part 1

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Ben Builds an Accessibility Guitar - Part 2 Trailer

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PiFace Control and Display Introduction

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Flashmob Farnell

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Express Yourself in 3D with Cube 3D Printers from Newark element14

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Farnell YouTube Channel Move

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Farnell: Design with the best

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French Farnell Quest

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Altera - 3 Ways to Quickly Adapt to Changing Ethernet Protocols

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Cy-Net3 Network Module

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MC AT - Professional and Precision Series Thin Film Chip Resistors

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Solderless LED Connector

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PSA-T Series Spectrum Analyser: PSA1301T/ PSA2701T

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3-axis Universal Motion Controller For Stepper Motor Drivers: TMC429

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Voltage Level Translation

Puce électronique / Microchip :

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Microchip - 8-bit Wireless Development Kit

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 2 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 3 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 1 of 3

Sans fil - Wireless :

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Microchip - 8-bit Wireless Development Kit

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Wireless Power Solutions - Wurth Electronics, Texas Instruments, CadSoft and element14

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Analog Devices - Remote Water Quality Monitoring via a Low Power, Wireless Network

Texas instrument :

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Texas Instruments - Automotive LED Headlights

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Texas Instruments - Digital Power Solutions

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Texas Instruments - Industrial Sensor Solutions

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Texas Instruments - Wireless Pen Input Demo (Mobile World Congress)

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Texas Instruments - Industrial Automation System Components

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Texas Instruments - TMS320C66x - Industry's first 10-GHz fixed/floating point DSP

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Texas Instruments - TMS320C66x KeyStone Multicore Architecture

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Texas Instruments - Industrial Interfaces

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Texas Instruments - Concerto™ MCUs - Connectivity without compromise

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Texas Instruments - Stellaris Robot Chronos

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Texas Instruments - DRV8412-C2-KIT, Brushed DC and Stepper Motor Control Kit

Ordinateurs :

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Ask Ben Heck - Connect Raspberry Pi to Car Computer

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Ben's Portable Raspberry Pi Computer Trailer

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Ben's Raspberry Pi Portable Computer Trailer 2

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Ben Heck's Pocket Computer Trailer

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Ask Ben Heck - Atari Computer

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Ask Ben Heck - Using Computer Monitors for External Displays

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Raspberry Pi Partnership with BBC Computer Literacy Project - Answers from co-founder Eben Upton

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Installing RaspBMC on your Raspberry Pi with the Farnell element14 Accessory kit

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Raspberry Pi Served - Joey Hudy

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Happy Birthday Raspberry Pi

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Raspberry Pi board B product overview

Logiciels :

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Ask Ben Heck - Best Opensource or Free CAD Software

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Tektronix FPGAView™ software makes debugging of FPGAs faster than ever!

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Ask Ben Heck - Best Open-Source Schematic Capture and PCB Layout Software

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Introduction to Cadsoft EAGLE PCB Design Software in Chinese

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Altera - Developing Software for Embedded Systems on FPGAs

Tutoriels :

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Ben Heck The Great Glue Gun Trailer Part 1

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the knode tutorial - element14

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Ben's Autodesk 123D Tutorial Trailer

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Ben's CadSoft EAGLE Tutorial Trailer

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Ben Heck's Soldering Tutorial Trailer

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Ben Heck's AVR Dev Board tutorial

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Ben Heck's Pinball Tutorial Trailer

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Ben Heck's Interface Tutorial Trailer

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First Stage with Python and PiFace Digital

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Cypress - Getting Started with PSoC® 3 - Part 2

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Energy Harvesting Challenge

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New Features of CadSoft EAGLE v6

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All technical caracteristics are subject to change without previous notice. Caractéristiques sujettes à modifications sans préavis. Proud to serve you celduc r e l a i s page 1 / 5F/GB S/MON/SO967460/B/01/03/2005 Relais statique monophasé de puissance Power Solid State Relay SO967460 okpac ❏ Relais statique synchrone spécialement adapté aux charges résistives. Zero Cross Solid State Relay specially designed for resistive loads. ❏ Sortie thyristors technologie TMS2 (*) permettant une longue durée de vie : 24 à 600VAC 75A. Back to back thyristors on output with TMS2 (*) technology for a long lifetime expectancy : 24 to 600VAC 75A. ❏ Large plage de contrôle: 3,5 - 32VDC avec un courant de commande régulé. LED de visualisation sur l'entrée de couleur verte. Protection aux surtensions sur l'entrée intégrée. Large control range: 3.5-32VDC with input current limiter. Green LED visualization on the input. Input over-voltage protection. ❏ Protection IP20 sur demande par l'ajout de volets. IP20 protection flaps on request (option). ❏ Construit en conformité aux normes EN60947-4-3 (IEC947-4-3) et EN60950/VDE0805 (Isolement renforcé) -UL-cUL Designed in conformity with EN60947-4-3 (IEC947-4-3) and EN60950/VDE0805 (Reinforced Insulation) -UL-cUL Output : 24-600VAC 75A Input : 3,5-32VDC Typical application: 30kW resistor (AC-51 load) on 400 VAC avec protection IP20/ with IP20 flaps Entrée control + * 1/L1 et 2/T2 peuvent être inversées/ 1/L1 T2 can be changed * le relais doit être monté sur dissipateur thermique / SSR must be mounted on a heatsink 24-600VAC - CHARGE/LOAD protection réseau line protection 4/A2- 3/A1+ 1/L1 2/T1 LED ZC sans protection IP20/ without IP20 flaps (*) : Thermo mechanical Stress Solution - 1/L1 et 2/T1 peuvent être inversées. 1/L1 and 2/T1 can be swapped. - Le relais être monté sur dissipateur thermique. SSR must be mounted on heatsink Application typique: Resistance 30 kW (Catégorie AC-51) en 400 VAC 3,5-32VDC Volets IP20 sur demande/ with IP20 flaps on request Dimensions : r e l a i s Rue Ampère B.P. 4 42290 SORBIERS - FRANCE E-Mail : celduc-relais@celduc.com Fax +33 (0) 4 77 53 85 51 Service Commercial France Tél. : +33 (0) 4 77 53 90 20 Sales Dept.For Europe Tel. : +33 (0) 4 77 53 90 21 Sales Dept. Asia : Tél. +33 (0) 4 77 53 90 19 www.celduc.com celduc Caractéristiques d'entrée / Control characteristics (at 25°C) DC Paramètre / Parameter Symbol Min Typ Max Unit Tension de commande / Control voltage Uc 3,5 5-12-24 32 V Courant de commande / Control current (@ Uc ) Ic <10 <13 <13 mA Tension de non fonctionnement / Release voltage Uc off 2 V LED d'entrée / Input LED verte / green Tension Inverse / Reverse voltage Urv 32 V Tension de transil d'entrée / Clamping voltage (Transil) Uclamp 36 V Immunité / Input immunity : EN61000-4-4 2kV Immunité / Input immunity : EN61000-4-5 2KV Caractéristiques de sortie / Output characteristics (at 25°C) Paramètre / Parameter Conditions Symbol Min Typ. Max Unit Plage de tension utilisation / Operating voltage range Ue 24 400 600 V rms Tension de crête / Peak voltage Up 1200 V Niveau de synchronisme / Zero cross level Usync 35 V Tension minimum amorçage / Latching voltage Ie nom Ua 10 V Courant nominal / nominal current (AC-51) Ie AC-51 75 90 A rms Courant surcharge / Non repetitive overload current tp=10ms (Fig. 3) Itsm 1000 1200 A Chute directe à l'état passant / On state voltage drop @ 25°C Vt 0,9 V Résistance dynamique / On state dynamic resistance rt 4,5 mΩ Puissance dissipée (max) / Output power dissipation (max value) Pd 0,9x0,9xIe + 0,0045xIe2 W Résistance thermique jonction/semelle Thermal resistance between junction to case Rthj/c 0,4 K/W Courant de fuite à l'état bloqué / Off state leakage current @Ue typ, 50Hz Ilk 1 mA Courant minimum de charge / Minimum load current Iemin 5 mA Temps de fermeture / Turn on time @Ue typ, 50Hz ton max 10 ms Temps d'ouverture / Turn off time @Ue typ, 50Hz toff max 10 ms Fréquence utilisation/ Operating frequency range F mains f 0,1 50-60 800 Hz dv/dt à l'état bloqué / Off state dv/dt dv/dt 500 V/μs di/dt max / Maximum di/dt non repetitive di/dt 50 A/μs I2t (<10ms) I2t 5000 7200 A2s Immunité / Conducted immunity level IEC/EN61000-4-4 (bursts) 2kV criterion B Immunité / Conducted immunity level IEC/EN61000-4-5 (surge) 2kV criterion A with external VDR Protection court-circuit / Short circuit protection voir/see page 5 Example Fuse Ferraz URC63A or fast Breaker Input : Ic = f( Uc) page 2 / 5F/GB S/MON/SO967460/B/01/03/2005 okpac Caractéristiques générales / General characteristics (at 25°C) Symbol Isolement entrée/sortie - Input to output insulation Ui 4000 VRMS Isolation sortie/ semelle - Output to case insulation Ui 4000 VRMS Résistance Isolement / Insulation resistance Ri 1000 (@500VDC) MΩ Tenue aux tensions de chocs / Rated impulse voltage Uimp 4000 V Degré de protection / Protection level / CEI529 IP00 Degré de pollution / Pollution degree - 2 Vibrations / Vibration withstand 10 -55 Hz according to CEI68 double amplitude 1,5 mm Tenue aux chocs / Shocks withstand according to CEI68 - 30/50 g Température de fonctionnement / Ambient temperature (no icing, no condensation) - -40 /+100 °C Température de stockage/ Storage temperature (no icing, no condensation) -40/+125 °C Humidité relative / Ambient humidity HR 40 to 85 % Poids/ Weight 80 g Conformité / Conformity EN60947-4-3 (IEC947-4-3) Conformité / Conformity VDE0805/EN60950 UL/cUL plastique du boitier / Housing Material PA 6 UL94VO Semelle / Base plate Aluminium, nickel-plated 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 0 2 4 6 8 10 12 14 Uc (VDc) Ic (mA) r e l a i s Rue Ampère B.P. 4 42290 SORBIERS - FRANCE E-Mail : celduc-relais@celduc.com Fax +33 (0) 4 77 53 85 51 Service Commercial France Tél. : +33 (0) 4 77 53 90 20 Sales Dept.For Europe Tel. : +33 (0) 4 77 53 90 21 Sales Dept. Asia : Tél. +33 (0) 4 77 53 90 19 www.celduc.com celduc page 3 / 5F/GB S/MON/SO967460/B/01/03/2005 okpac Surcharge de courant non répétitive sans tension réappliquée / No repetive surge current without voltage reapplied. Surcharge de courant répétitive avec tension réappliquée Repetive surge current with voltage reapplied. 0,01 0,1 1 10 0 500 1000 1500 t (s) Itsm (Apeak) Surcharge de courant :Itsm (Apeak)=f(t) pour modéle 75A/ Surge current : Itsm (Apeak) = f(t) for 75A Fig.3: 1 2 fig 3 : Courants de surcharges / Overload currents 6K/W correspond à un relais monté sur un adaptateur DIN celduc type 1LD12020 6K/W corresponds to a relay mounted on a DIN rail adaptator like celduc 1LD12020 Fig. 2 Courbes thermiques & Choix dissipateur thermique / Thermal curves and heatsink choice 0 10 20 30 40 50 60 70 80 90 0 10 20 30 40 50 60 70 80 90 100 110 Courant de charge / RMS load current (A) Puissance Dissipée / Power Dissipation (W) 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 110 Température ambiante / Ambient temperature (°C) 1,1K/W 6K/W 2,1K/W 1,5K/W Full on State 50% on State 0,95K/W 0,75K/W 0,55K/W 0,3K/W −> Warning ! semiconductor relays don't provide any galvanic insulation between the load and the mains. Always use in conjunction with an adapted circuit breaker with isolation feature or a similar device in order to ensure a reliable insulation in the event of wrong function and when the relay must be insulated from the mains (maintenance ; if not used for a long duration ...). 1 -Itsm non répétitif sans tension réappliquée est donné pour la détermination des protections. 1 - No repetitive Itsm is given without voltage reapplied . This curve is used to define the protection (fuses). 2 -Itsm répétitif est donné pour des surcharges de courant (Tj initiale=70°C). Attention : la répétition de ces surcharges de courant diminue la durée de vie du relais. 2 - Repetitive Itsm is given for inrush current with initial Tj = 70°C. In normal operation , this curve musn't be exceeded. Be careful, the repetition of the surge current decreases the life expectancy of the SSR. −> Attention ! les relais à semi-conducteurs ne procurent pas d'isolation galvanique entre le réseau et la charge. Ils doivent être utilisés associés à un disjoncteur avec propriété de sectionnement ou similaire, afin d'assurer un sectionnement fiable en amont de la ligne dans l'hypothèse d'une défaillance et pour tous les cas où le relais doit être isolé du réseau (maintenance ; non utilisation sur une longue durée...). r e l a i s Rue Ampère B.P. 4 42290 SORBIERS - FRANCE E-Mail : celduc-relais@celduc.com Fax +33 (0) 4 77 53 85 51 Service Commercial France Tél. : +33 (0) 4 77 53 90 20 Sales Dept.For Europe Tel. : +33 (0) 4 77 53 90 21 Sales Dept. Asia : Tél. +33 (0) 4 77 53 90 19 www.celduc.com page 4 / 5F/GB S/MON/SO967460/B/01/03/2005 okpac okpac Raccordement d'entrée / Control wiring Nombre de fils / Number of wires Modèle de tournevis / Screwdriver type Couple de serrage recommandé 1 2 Recommended Torque Fil rigide (sans embout) SOLID (No ferrule) Fil multibrins (avec embout) FINE STRANDED (With ferrule) Fil rigide (sans embout) SOLID (No ferrule) Fil multibrins (avec embout) FINE STRANDED (With ferrule) M4 N.m 0,75 ... 2,5 mm2 AWG18....AWG14 0,75 ... 2,5 mm2 AWG18....AWG14 0,75 ... 2,5 mm2 AWG18....AWG14 0,75 ... 2,5 mm2 AWG18....AWG14 POZIDRIV 2 1,2 okpac Raccordement de puissance / Power wiring Nombre de fils / Number of wires Modèle de tournevis / Screwdriver type Couple de serrage recommandé 1 2 Recommended Torque Fil rigide (sans embout) SOLID (No ferrule) Fil multibrins (avec embout) FINE STRANDED (With ferrule) Fil rigide (sans embout) SOLID (No ferrule) Fil multibrins (avec embout) FINE STRANDED (With ferrule) M5 N.m 1,5 ... 10 mm2 AWG16....AWG8 1,5 ... 6 mm2 AWG16....AWG10 1,5 ... 10 mm2 AWG16....AWG8 1,5 ... 6 mm2 AWG16....AWG10 POZIDRIV 2 2 Raccordement / Connections celduc Options : Volets IP20 1K453000 = référence d'un volet sans le montage 1LK00500 = 1 volet (côté puissance) + 1 montage celduc 1LK00600 = 2 volets (puissance & commande) + montages celduc Option : IP20 flaps 1K453000 : Flap reference without mounting 1LK00500 = 1 flap (on output) + 1 celduc mounting 1LK00600 = 2 flaps (input & output) + 2 celduc mounting FASTONS : Nous consulter / Consult us Directement avec fils avec ou sans embouts/ Direct connection with wires with or without ferrules Avec cosses/ With ring terminals Puissance avec cosses / Power with ring terminals. W max =12,6mm 16 mm2 (AWG6) 25 mm2 (AWG4) 35mm2 (AWG2 /AWG3) 50mm2 (AWG0 /AWG1) Des cosses et kits d'adaptation peuvent être fournis : voir relais forte puissance et documentation connexion forte puissance/ Suitable ring terminals and special kit for high current can be delivered: see high power SSR and data-sheet for power connexion. r e l a i s Rue Ampère B.P. 4 42290 SORBIERS - FRANCE E-Mail : celduc-relais@celduc.com Fax +33 (0) 4 77 53 85 51 Service Commercial France Tél. : +33 (0) 4 77 53 90 20 Sales Dept.For Europe Tel. : +33 (0) 4 77 53 90 21 Sales Dept. Asia : Tél. +33 (0) 4 77 53 90 19 www.celduc.com S/MON/SO967460/B/01/03/2005 okpac Montage /Mounting: −> Les relais statiques de la gamme okpac doivent être montés sur dissipateur thermique. Une gamme étendue de dissipateurs est disponible. Voir exemples ci dessous et la gamme "WF" sur www.celduc.com. okpac SSRs must be mounted on heatsinks. A large range of heatsinks is available. See below some examples and "WF" range on www.celduc.com. −> Pour le montage du relais sur dissipateur utiliser de la graisse thermique ou un "thermal pad" haute performance spécifié par celduc .Une version autocollante précollée sur le relais est aussi disponible: nous consulter / For heatsink mounting, it is necessary to use thermal grease or thermal pad with high conductibility specified by celduc. An adhesive model mounted by celduc on the SSR is also available: please contact us. Application typiques / Typical LOADS −> Le produit SO9 est défini principalement pour charge résistive AC-51 (chauffage). Pour les autres charges, consulter notre guide de choix. SO9 product is specially designed for AC-51 résistive load (heating). For other loads, consult our selection guide Protection /Protection : −> La protection d'un relais statique contre les court-circuits de la charge peut être faite par fusibles rapides avec des I2t = 1/2 I2t du relais . Un test en laboratoire a été effectué sur les fusibles de marque FERRAZ. Une protection par MCB ( disjoncteurs modulaires miniatures) est aussi possible. Voir notre note application ( protection SSR) et utiliser des relais avec I2t >5000A2s To protect the SSR against a short-circuit of the load , use a fuse with a I2t value = 1/2 I2t value specified page 2. A test has been made with FERRAZ fuses . It is possible to protect SSR by MCB ( miniature circuit breaker). In this case, see application note ( SSR protection) and use a SSR with high I2t value (5000A2s minimum). EMC : −> Immunité : Nous spécifions dans nos notices le niveau d'immunité de nos produits selon les normes essentielles pour ce type de produit, c'est à dire EN61000-4-4 &5. Immunity : We give in our data-sheets the immunity level of our SSRs according to the main standards for these products: EN61000-4-4 &5. −> Emission: Nos relais statiques sont principalement conçus et conformes pour la classe d'appareils A (Industrie). L'utilisation du produit dans des environnements domestiques peut amener l'utilisateur à employer des moyens d'atténuation supplémentaires. En effet, les relais statiques sont des dispositifs complexes qui doivent être interconnectés avec d'autres materiels (charges, cables, etc) pour former un système. Etant donné que les autres materiels ou interconnexions ne sont pas de la responsabilité de celduc, il est de la responsabilité du réalisateur du système de s'assurer que les systèmes contenant des relais statiques satisfont aux prescriptions de toutes les règles et règlements applicables au niveau des systèmes. Consulter celduc qui peut vous conseiller ou réaliser des essais dans son laboratoire sur votre application. Emission: celduc SSRs are mainly designed in compliance with standards for class A equipment (Industry). Use of this product in domestic environments may cause radio interference. In this case the user may be required to employ additionnal devices to reduce noise. SSRs are complex devices that must be interconnected with other equipment (loads, cables, etc.) to form a system. Because the other equipment or the interconnections may not be under the control of celduc, it shall be the responsability of the system integrator to ensure that systems containing SSRs comply with the requirement of any rules and regulations applicable at the system level. Consult celduc for advices. Tests can be preformed in our laboratory. Thermal pad : 5TH21000 WF151200 (2-2,5 K/W) WF108110 ( 1,1 K/W) Installation des volets IP20 / IP20 flaps mounting Poussez et fermer. Push and close M4x12mm 1,2N.m Thermal grease or pad page 5 / 5F/GB celduc 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 1B 2B 3B 4B 5B 6B 7B 8B GND 1C 2C 3C 4C 5C 6C 7C 8C COM DW OR N PACKAGE (TOP VIEW) ULN2803A www.ti.com SLRS049F –FEBRUARY 1997–REVISED JANUARY 2014 ULN2803A Darlington Transistor Arrays Check for Samples: ULN2803A 1FEATURES DESCRIPTION • 500-mA-Rated Collector Current The ULN2803A device is a high-voltage, high-current (Single Output) Darlington transistor array. The device consists of eight npn Darlington pairs that feature high-voltage • High-Voltage Outputs: 50 V outputs with common-cathode clamp diodes for • Output Clamp Diodes switching inductive loads. The collector-current rating • Inputs Compatible With Various of each Darlington pair is 500 mA. The Darlington Types of Logic pairs may be connected in parallel for higher current capability. • Relay-Driver Applications • Compatible with ULN2800A Series Applications include relay drivers, hammer drivers, lamp drivers, display drivers (LED and gas discharge), line drivers, and logic buffers. The ULN2803A device has a 2.7-kΩ series base resistor for each Darlington pair for operation directly with TTL or 5-V CMOS devices. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 1997–2014, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 2.7 k! 7.2 k! 3 k! COM Output C E Input B 8C 7C 6C 5C 4C 3C 2C 7 6 5 4 3 2 1 7B 6B 5B 4B 3B 2B 1B 11 12 13 14 15 16 17 COM 8 8B 10 1C 18 ULN2803A SLRS049F –FEBRUARY 1997–REVISED JANUARY 2014 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Logic Diagram Schematic (Each Darlington Pair) 2 Submit Documentation Feedback Copyright © 1997–2014, Texas Instruments Incorporated Product Folder Links :ULN2803A ULN2803A www.ti.com SLRS049F –FEBRUARY 1997–REVISED JANUARY 2014 Absolute Maximum Ratings(1) at 25°C free-air temperature (unless otherwise noted) VALUE UNIT Collector-emitter voltage 50 V Input voltage(2) 30 V Peak collector current 500 mA Output clamp current 500 mA Total substrate-terminal current –2.5 A D package 73.14 θJA Package thermal impedance(3) (4) °C/W DW package 62.66 TJ Operating virtual junction temperature 150 °C Tstg Storage temperature range –65 to 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, unless otherwise noted, are with respect to the emitter/substrate terminal GND. (3) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. (4) The package thermal impedance is calculated in accordance with JESD 51-7. Electrical Characteristics at TA = 25°C free-air temperature (unless otherwise noted) ULN2002A PARAMETER TEST CONDITIONS UNIT MIN TYP MAX I VCE = 50 V, CEX Collector cutoff current see Figure 1 II = 0 50 μA I VCE = 50 V, IC = 500 μA, I(off) Off-state input current T 50 65 μA A = 70°C see Figure 2 II(on) Input current VI = 3.85 V, See Figure 3 0.93 1.35 mA IC = 200 mA 2.4 V VCE = 2 V, I(on) On-state input voltage see Figure 4 IC = 250 mA 2.7 V IC = 300 mA 3 II = 250 μA, IC = 100 mA 0.9 1.1 see Figure 5 V II = 350 μA, CE(sat) Collector-emitter saturation voltage see Figure 5 IC = 200 mA 1 1.3 V II = 500 μA, IC = 350 mA 1.3 1.6 see Figure 5 IR Clamp diode reverse current VR = 50 V, see Figure 6 50 μA VF Clamp diode forward voltage IF = 350 mA see Figure 7 1.7 2 V Ci Input capacitance VI = 0, f = 1 MHz 15 25 pF Switching Characteristics TA = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low- to high-level output VS = 50 V, CL = 15 pF, RL = 163 Ω, 130 See Figure 8 ns tPHL Propagation delay time, high- to low-level output 20 VOH High-level output voltage after switching VS = 50 V, IO = 300 mA, See Figure 9 VS – 20 mV Copyright © 1997–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links :ULN2803A Open VF IF Open VCE II IC hFE = IC II VR Open IR Open VCE IC VI Open II VI Open Open VCE IC II(off) Open VCE ICEX Open ULN2803A SLRS049F –FEBRUARY 1997–REVISED JANUARY 2014 www.ti.com Parameter Measurement Information Figure 1. ICEX Test Circuit Figure 2. II(off) Test Circuit Figure 3. II(on) Test Circuit Figure 4. VI(on) Test Circuit Figure 5. hFE, VCE(sat) Test Circuit Figure 6. IR Test Circuit Figure 7. VF Test Circuit 4 Submit Documentation Feedback Copyright © 1997–2014, Texas Instruments Incorporated Product Folder Links :ULN2803A Pulse Generator (see Note A) Input Open VS = 50 V RL = 163 ! CL = 15 pF (see Note B) Output tPHL tPLH 0.5 μs <5 ns <10 ns 90% 50% 10% 10% 90% 50% 50% 50% VIH Input (see Note C) Output 0 Test Circuit Voltage Waveforms VOH ULN2803A www.ti.com SLRS049F –FEBRUARY 1997–REVISED JANUARY 2014 Parameter Measurement Information (continued) A. The pulse generator has the following characteristics: PRR = 12.5 kHz, ZO = 50 Ω. B. CL includes probe and jig capacitance. C. VIH = 3 V Figure 8. Propagation Delay-Times Copyright © 1997–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links :ULN2803A Pulse Generator (see Note A) Input VS 163 ! CL = 15 pF (see Note B) Output 40 μs <5 ns <10 ns 90% 1.5 V 10% 10% 90% 1.5 V VIH Input (see Note C) Output 0 2 mH VOH Test Circuit Voltage Waveforms ULN2803A SLRS049F –FEBRUARY 1997–REVISED JANUARY 2014 www.ti.com Parameter Measurement Information (continued) A. The pulse generator has the following characteristics: PRR = 12.5 kHz, ZO = 50 Ω. B. CL includes probe and jig capacitance. C. VIH = 3 V Figure 9. Latch-Up Test 6 Submit Documentation Feedback Copyright © 1997–2014, Texas Instruments Incorporated Product Folder Links :ULN2803A ULN2803A www.ti.com SLRS049F –FEBRUARY 1997–REVISED JANUARY 2014 REVISION HISTORY Changes from Revision E (July 2006) to Revision F Page • Updated document to new TI data sheet format - no specification changes. ...................................................................... 1 • Deleted Ordering Information table. ...................................................................................................................................... 1 • Added ESD warning. ............................................................................................................................................................ 2 Copyright © 1997–2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links :ULN2803A PACKAGE OPTION ADDENDUM www.ti.com 27-Jan-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples ULN2803ADW ACTIVE SOIC DW 18 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ULN2803A ULN2803ADWG4 ACTIVE SOIC DW 18 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ULN2803A ULN2803ADWR ACTIVE SOIC DW 18 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ULN2803A ULN2803ADWRG4 ACTIVE SOIC DW 18 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 ULN2803A ULN2803AN ACTIVE PDIP N 18 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 ULN2803AN ULN2803ANE4 ACTIVE PDIP N 18 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 ULN2803AN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. PACKAGE OPTION ADDENDUM www.ti.com 27-Jan-2014 Addendum-Page 2 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant ULN2803ADWR SOIC DW 18 2000 330.0 24.4 10.9 12.0 2.7 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 27-Jan-2014 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ULN2803ADWR SOIC DW 18 2000 370.0 355.0 55.0 PACKAGE MATERIALS INFORMATION www.ti.com 27-Jan-2014 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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The devices require only four small 0.1μF external chargepump capacitors. The MAX3222, MAX3232, and MAX3241 are guaranteed to run at data rates of 120kbps while maintaining RS-232 output levels. The MAX3237 is guaranteed to run at data rates of 250kbps in the normal operating mode and 1Mbps in the MegaBaud™ operating mode, while maintaining RS-232 output levels. The MAX3222/MAX3232 have 2 receivers and 2 drivers. The MAX3222 features a 1μA shutdown mode that reduces power consumption and extends battery life in portable systems. Its receivers remain active in shutdown mode, allowing external devices such as modems to be monitored using only 1μA supply current. The MAX3222 and MAX3232 are pin, package, and functionally compatible with the industry-standard MAX242 and MAX232, respectively. The MAX3241 is a complete serial port (3 drivers/ 5 receivers) designed for notebook and subnotebook computers. The MAX3237 (5 drivers/3 receivers) is ideal for fast modem applications. Both these devices feature a shutdown mode in which all receivers can remain active while using only 1μA supply current. Receivers R1 (MAX3237/MAX3241) and R2 (MAX3241) have extra outputs in addition to their standard outputs. These extra outputs are always active, allowing external devices such as a modem to be monitored without forward biasing the protection diodes in circuitry that may have VCC completely removed. The MAX3222, MAX3232, and MAX3241 are available in space-saving TSSOP and SSOP packages. ________________________Applications Notebook, Subnotebook, and Palmtop Computers High-Speed Modems Battery-Powered Equipment Hand-Held Equipment Peripherals Printers __Next Generation Device Features ♦ For Smaller Packaging: MAX3228E/MAX3229E: +2.5V to +5.5V RS-232 Transceivers in UCSP™ ♦ For Integrated ESD Protection: MAX3222E/MAX3232E/MAX3237E/MAX3241E*/ MAX3246E: ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers ♦ For Low-Voltage or Data Cable Applications: MAX3380E/MAX3381E: +2.35V to +5.5V, 1μA, 2Tx/2Rx RS-232 Transceivers with ±15kV ESD-Protected I/O and Logic Pins 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 SHDN VCC GND C1- T1OUT V+ C1+ EN TOP VIEW R1IN R1OUT T1IN T2OUT T2IN VC2- C2+ R2IN 9 10 R2OUT DIP/SO MAX3222 + MAX3222 _________________Pin Configurations _______________Ordering Information MegaBaud and UCSP are trademarks of Maxim Integrated Products, Inc. *Covered by U.S. Patent numbers 4,636,930; 4,679,134; 4,777,577; 4,797,899; 4,809,152; 4,897,774; 4,999,761; and other patents pending. Typical Operating Circuits appear at end of data sheet. Pin Configurations continued at end of data sheet. Ordering Information continued at end of data sheet. +Denotes lead-free package. PART TEMP RANGE PIN-PACKAGE PKG CODE MAX3222CUP+ 0°C to +70°C 20 TSSOP U20+2 MAX3222CAP+ 0°C to +70°C 20 SSOP A20+1 MAX3222CWN+ 0°C to +70°C 18 SO W18+1 MAX3222CPN+ 0°C to +70°C 18 Plastic Dip P18+5 VCC = 5.0V MAX3222/MAX3232/MAX3237/MAX3241 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors 2 _______________________________________________________________________________________ ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +5.5V, C1–C4 = 0.1μF (Note 2), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 1: V+ and V- can have a maximum magnitude of 7V, but their absolute difference cannot exceed 13V. VCC...........................................................................-0.3V to +6V V+ (Note 1) ...............................................................-0.3V to +7V V- (Note 1) ................................................................+0.3V to -7V V+ + V- (Note 1)...................................................................+13V Input Voltages T_IN, SHDN, EN ...................................................-0.3V to +6V MBAUD...................................................-0.3V to (VCC + 0.3V) R_IN .................................................................................±25V Output Voltages T_OUT...........................................................................±13.2V R_OUT....................................................-0.3V to (VCC + 0.3V) Short-Circuit Duration T_OUT ....................................................................Continuous Continuous Power Dissipation (TA = +70°C) 16-Pin TSSOP (derate 6.7mW/°C above +70°C).............533mW 16-Pin Narrow SO (derate 8.70mW/°C above +70°C) ....696mW 16-Pin Wide SO (derate 9.52mW/°C above +70°C)........762mW 16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)...842mW 18-Pin SO (derate 9.52mW/°C above +70°C)..............762mW 18-Pin Plastic DIP (derate 11.11mW/°C above +70°C) ..889mW 20-Pin SSOP (derate 7.00mW/°C above +70°C) .........559mW 20-Pin TSSOP (derate 8.0mW/°C above +70°C).............640mW 28-Pin TSSOP (derate 8.7mW/°C above +70°C).............696mW 28-Pin SSOP (derate 9.52mW/°C above +70°C) .........762mW 28-Pin SO (derate 12.50mW/°C above +70°C) .....................1W Operating Temperature Ranges MAX32_ _C_ _.....................................................0°C to +70°C MAX32_ _E_ _ .................................................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C IOUT = -1.0mA IOUT = 1.6mA Receivers disabled T_IN, EN, SHDN, MBAUD T_IN, EN, SHDN, MBAUD CONDITIONS V 0.8 1.5 Input Threshold Low 0.6 1.2 Input Voltage Range -25 25 V 0.5 2.0 VCC Power-Supply Current Output Voltage High VCC - 0.6 VCC - 0.1 V Output Voltage Low 0.4 V Output Leakage Current ±0.05 ±10 μA Input Leakage Current ±0.01 ±1.0 μA 0.8 V Input Logic Threshold Low (Note 3) PARAMETER MIN TYP MAX UNITS TA = +25°C TA = +25°C V 1.8 2.4 Input Threshold High 1.5 2.4 VCC = 3.3V VCC = 5.0V 2.0 V 2.4 Input Logic Threshold High (Note 3) No load, VCC = 3.3V or 5.0V, TA = +25°C mA 0.3 1.0 MAX3222/MAX3232/ MAX3241 MAX3237 Shutdown Supply Current SHDN = GND, TA = +25°C 1.0 10 μA VCC = 3.3V VCC = 5.0V VCC = 3.3V VCC = 5.0V DC CHARACTERISTICS LOGIC INPUTS AND RECEIVER OUTPUTS RECEIVER INPUTS MAX3222/MAX3232/MAX3237/MAX3241 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors _______________________________________________________________________________________ 3 TIMING CHARACTERISTICS—MAX3222/MAX3232/MAX3241 (VCC = +3.0V to +5.5V, C1–C4 = 0.1μF (Note 2), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +5.5V, C1–C4 = 0.1μF (Note 2), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) T1IN = T2IN = GND, T3IN = VCC, T3OUT loaded with 3kΩ to GND, T1OUT and T2OUT loaded with 2.5mA each CONDITIONS Transmitter Output Voltage ±5.0 V Input Hysteresis 0.3 V PARAMETER MIN TYP MAX UNITS Output Voltage Swing All transmitter outputs loaded with 3kΩ to ground ±5.0 ±5.4 V Output Short-Circuit Current ±35 ±60 mA Output Resistance VCC = V+ = V- = 0V, VOUT = ±2V 300 10M Ω VOUT = ±12V, VCC = 0V or 3V to 5.5V, transmitters disabled Output Leakage Current ±25 μA tPHL RL = 3kΩ, CL = 1000pF, one transmitter switching tPLH | tPHL - tPLH | | tPHL - tPLH | Normal operation Normal operation CONDITIONS 0.3 μs 0.3 Receiver Propagation Delay Maximum Data Rate 120 235 kbps Receiver Skew 300 ns Transmitter Skew 300 ns Receiver Output Disable Time 200 ns Receiver Output Enable Time 200 ns PARAMETER MIN TYP MAX UNITS VCC = 3.3V, RL = 3kΩ to 7kΩ, 6 30 +3V to -3V or -3V to +3V, TA = +25°C, one transmitter switching V/μs 4 30 Transition-Region Slew Rate R_IN to R_OUT, CL = 150pF CL = 150pF to 1000pF CL = 150pF to 2500pF Input Resistance TA = +25°C 3 5 7 kΩ MOUSE DRIVEABILITY (MAX3241) TRANSMITTER OUTPUTS MAX3222/MAX3232/MAX3237/MAX3241 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors 4 _______________________________________________________________________________________ __________________________________________Typical Operating Characteristics (VCC = +3.3V, 235kbps data rate, 0.1μF capacitors, all transmitters loaded with 3kΩ, TA = +25°C, unless otherwise noted.) RL = 3kΩ, CL = 1000pF, one transmitter switching, MBAUD = GND Normal operation CONDITIONS Receiver Output Disable Time Normal operation 200 ns | tPHL - tPLH |, MBAUD = GND 100 ns 0.15 250 μs 0.15 Receiver Propagation Delay Receiver Output Enable Time 200 ns PARAMETER MIN TYP MAX UNITS TIMING CHARACTERISTICS—MAX3237 (VCC = +3.0V to +5.5V, C1–C4 = 0.1μF (Note 2), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) VCC = 3.0V to 4.5V, RL = 3kΩ, CL = 250pF, one transmitter switching, MBAUD = VCC 1000 VCC = 4.5V to 5.5V, RL = 3kΩ, CL = 1000pF, one transmitter switching, MBAUD = VCC kbps 1000 Maximum Data Rate R_IN to R_OUT, CL = 150pF | tPHL - tPLH |, MBAUD = VCC 25 ns Transmitter Skew Receiver Skew | tPHL - tPLH | 50 ns 6 30 V/μs 4 30 tPHL tPLH CL = 150pF to 2500pF, MBAUD = GND CL = 150pF to 1000pF MBAUD = GND VCC = 3.3V, RL = 3Ω to 7kΩ, +3V to -3V or -3V to +3V, TA = +25°C Transition-Region Slew Rate MBAUD = VCC 24 150 Note 2: MAX3222/MAX3232/MAX3241: C1–C4 = 0.1μF tested at 3.3V ±10%; C1 = 0.047μF, C2–C4 = 0.33μF tested at 5.0V ±10%. MAX3237: C1–C4 = 0.1μF tested at 3.3V ±5%; C1–C4 = 0.22μF tested at 3.3V ±10%; C1 = 0.047μF, C2–C4 = 0.33μF tested at 5.0V ±10%. Note 3: Transmitter input hysteresis is typically 250mV. -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 0 MAX3222/MAX3232 TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE MAX3222-01 LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (V) 1000 2000 3000 4000 5000 VOUT+ VOUT- 0 2 4 6 8 10 12 14 16 18 20 22 150 MAX3222/MAX3232 SLEW RATE vs. LOAD CAPACITANCE MAX3222-02 LOAD CAPACITANCE (pF) SLEW RATE (V/μs) 1000 2000 3000 4000 5000 FOR DATA RATES UP TO 235kbps +SLEW -SLEW 0 5 10 15 20 25 30 35 40 0 MAX3222/MAX3232 SUPPLY CURRENT vs. LOAD CAPACITANCE WHEN TRANSMITTING DATA MAX3222-03 LOAD CAPACITANCE (pF) SUPPLY CURRENT (mA) 1000 2000 3000 4000 5000 235kbps 120kbps 20kbps MAX3222/MAX3232/MAX3237/MAX3241 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors _______________________________________________________________________________________ 5 -7.5 -5.0 -2.5 0 2.5 5.0 7.5 0 MAX3241 TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE MAX3222-04 LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (V) 1000 2000 3000 4000 5000 VOUT+ 1 TRANSMITTER AT 235kbps 2 TRANSMITTERS AT 30kbps VOUTALL OUTPUTS LOADED WITH 3kΩ +CL 0.1μF CHARGE-PUMP CAPACITORS 4 FOR ALL DATA RATES UP TO 235kbps 6 8 10 12 14 16 18 20 22 24 0 MAX3241 SLEW RATE vs. LOAD CAPACITANCE MAX3222-05 LOAD CAPACITANCE (pF) SLEW RATE (V/μs) 1000 2000 3000 4000 5000 +SLEW -SLEW 0 5 10 15 20 25 30 35 45 40 0 MAX3241 SUPPLY CURRENT vs. LOAD CAPACITANCE WHEN TRANSMITTING DATA MAX3222-06 LOAD CAPACITANCE (pF) SUPPLY CURRENT (mA) 1000 2000 3000 4000 5000 235kbps 120kbps 20kbps -7.5 -5.0 -2.5 0 2.5 5.0 7.5 0 MAX3237 TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE (MBAUD = GND) MAX3222-07 LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (V) 1000 2000 3000 4000 5000 1 TRANSMITTER AT 240kbps 4 TRANSMITTERS AT 15kbps 3kΩ + CL LOADS VCC = 3.3V 0 10 20 30 50 40 60 70 0 MAX3237 SLEW RATE vs. LOAD CAPACITANCE (MBAUD = VCC) MAX3222-10 LOAD CAPACITANCE (pF) SLEW RATE (V/μs) 500 1000 1500 2000 -SLEW, 1Mbps +SLEW, 1Mbps 1 TRANSMITTER AT FULL DATA RATE 4 TRANSMITTERS AT 1/16 DATA RATE 3kΩ + CL LOAD EACH OUTPUT VCC = 3.3V -SLEW, 2Mbps +SLEW, 2Mbps -7.5 -5.0 -2.5 0 2.5 5.0 7.5 0 MAX3237 TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE (MBAUD = VCC) MAX3222-08 LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (V) 500 1000 1500 2000 1 TRANSMITTER AT FULL DATA RATE 4 TRANSMITTERS AT 1/16 DATA RATE 3kΩ + CL LOAD, EACH OUTPUT VCC = 3.3V 2Mbps 1.5Mbps 1Mbps 2Mbps 1Mbps 1.5Mbps 0 10 20 30 40 50 60 0 MAX3237 SUPPLY CURRENT vs. LOAD CAPACITANCE (MBAUD = GND) MAX3222-11 LOAD CAPACITANCE (pF) SUPPLY CURRENT (mA) 1000 2000 3000 4000 5000 240kbps 120kbps 20kbps 1 TRANSMITTER AT FULL DATA RATE 4 TRANSMITTERS AT 1/16 DATA RATE 3kΩ + CL LOADS VCC = 3.3V 0 2 4 6 8 10 12 0 MAX3237 SLEW RATE vs. LOAD CAPACITANCE (MBAUD = GND) MAX3222-09 LOAD CAPACITANCE (pF) SLEW RATE (V/μs) 1000 2000 3000 4000 5000 +SLEW -SLEW 1 TRANSMITTER AT 240kbps 4 TRANSMITTERS AT 15kbps 3kΩ + CL LOADS VCC = 3.3V 0 10 30 20 40 50 60 70 0 MAX3237 SKEW vs. LOAD CAPACITANCE (tPLH - tPHL) MAX3222-12 LOAD CAPACITANCE (pF) 500 1000 1500 2000 2500 MAX MIN AVERAGE; 10 PARTS SKEW (ns) 1 TRANSMITTER AT 512kbps 4 TRANSMITTERS AT 32kbps 3kΩ + CL LOADS VCC = 3.3V MBAUD = VCC _____________________________Typical Operating Characteristics (continued) (VCC = +3.3V, 235kbps data rate, 0.1μF capacitors, all transmitters loaded with 3kΩ, TA = +25°C, unless otherwise noted.) MAX3222/MAX3232/MAX3237/MAX3241 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors 6 _______________________________________________________________________________________ — FUNCTION — MAX3222 Noninverting Complementary Receiver Outputs. Always active. DIP/SO SSOP — 11, 14 1 1 Receiver Enable. Active low. 2 2 Positive Terminal of Voltage-Doubler Charge-Pump Capacitor 6 6 Negative Terminal of Inverting Charge-Pump Capacitor 5 5 Positive Terminal of Inverting Charge-Pump Capacitor 4 4 Negative Terminal of Voltage-Doubler Charge-Pump Capacitor 3 3 +5.5V Generated by the Charge Pump 11, 12 12, 13 TTL/CMOS Transmitter Inputs 10, 13 10, 15 TTL/CMOS Receiver Outputs 9, 14 9, 16 RS-232 Receiver Inputs 8, 15 8, 17 RS-232 Transmitter Outputs 7 7 -5.5V Generated by the Charge Pump 18 20 Shutdown Control. Active low. 17 19 +3.0V to +5.5V Supply Voltage 16 18 Ground No Connection MAX3232 MAX3237 — 16 — 13 1 28 5 3 4 1 3 25 2 27 10, 11 17, 19, 22, 23, 24 9, 12 18, 20, 21 8, 13 8, 9, 11 7, 14 5, 6, 7, 10, 12 6 4 — 14 16 26 15 2 — — NAME EN C1+ C2- C2+ C1- V+ T_IN R_OUT R_IN T_OUT VSHDN VCC GND R_OUTB N.C. MAX3241 20, 21 23 28 2 1 24 27 12, 13, 14 15–19 4–8 9, 10, 11 3 22 26 25 — PIN — — MegaBaud Control Input. Connect to GND for normal operation; connect to VCC for 1Mbps transmission rates. — 15 — MBAUD ______________________________________________________________Pin Description MAX3222/MAX3232/MAX3237/MAX3241 _______________Detailed Description Dual Charge-Pump Voltage Converter The MAX3222/MAX3232/MAX3237/MAX3241’s internal power supply consists of a regulated dual charge pump that provides output voltages of +5.5V (doubling charge pump) and -5.5V (inverting charge pump), regardless of the input voltage (VCC) over the 3.0V to 5.5V range. The charge pumps operate in a discontinuous mode; if the output voltages are less than 5.5V, the charge pumps are enabled, and if the output voltages exceed 5.5V, the charge pumps are disabled. Each charge pump requires a flying capacitor (C1, C2) and a reservoir capacitor (C3, C4) to generate the V+ and V- supplies. RS-232 Transmitters The transmitters are inverting level translators that convert CMOS-logic levels to 5.0V EIA/TIA-232 levels. The MAX3222/MAX3232/MAX3241 transmitters guarantee a 120kbps data rate with worst-case loads of 3kΩ in parallel with 1000pF, providing compatibility with PC-to- PC communication software (such as LapLink™). Typically, these three devices can operate at data rates of 235kbps. Transmitters can be paralleled to drive multiple receivers or mice. The MAX3222/MAX3237/MAX3241’s output stage is turned off (high impedance) when the device is in shutdown mode. When the power is off, the MAX3222/ MAX3232/MAX3237/MAX3241 permit the outputs to be driven up to ±12V. The transmitter inputs do not have pullup resistors. Connect unused inputs to GND or VCC. MAX3237 MegaBaud Operation In normal operating mode (MBAUD = GND), the MAX3237 transmitters guarantee a 250kbps data rate with worst-case loads of 3kΩ in parallel with 1000pF. This provides compatibility with PC-to-PC communication software, such as LapLink. For higher speed serial communications, the MAX3237 features MegaBaud operation. In MegaBaud operating mode (MBAUD = VCC), the MAX3237 transmitters guarantee a 1Mbps data rate with worst-case loads of 3kΩ in parallel with 250pF for 3.0V < VCC < 4.5V. For 5V ±10% operation, the MAX3237 transmitters guarantee a 1Mbps data rate into worst-case loads of 3kΩ in parallel with 1000pF. MAX3222 MAX3232 MAX3237 MAX3241 5kΩ R_ OUT R_ IN EN* C2- C2+ C1- C1+ VV+ VCC C4 C1 C3 C2 0.1μF VCC SHDN* T_ IN T_ OUT GND VCC 0V 7kΩ 150pF MAX3222 MAX3232 MAX3237 MAX3241 5kΩ R_ OUT R_ IN EN* C2- C2+ C1- C1+ VV+ VCC C4 C1 C3 C2 0.1μF VCC SHDN* T_ IN T_ OUT GND VCC 0V 3kΩ 2500pF MINIMUM SLEW-RATE TEST CIRCUIT MAXIMUM SLEW-RATE TEST CIRCUIT *MAX3222/MAX3237/MAX3241 ONLY Figure 1. Slew-Rate Test Circuits LapLink is a trademark of Traveling Software, Inc. 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors _______________________________________________________________________________________ 7 MAX3222/MAX3232/MAX3237/MAX3241 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors 8 _______________________________________________________________________________________ RS-232 Receivers The receivers convert RS-232 signals to CMOS-logic output levels. The MAX3222/MAX3237/MAX3241 receivers have inverting three-state outputs. In shutdown, the receivers can be active or inactive (Table 1). The complementary outputs on the MAX3237 (R1OUTB) and the MAX3241 (R1OUTB, R2OUTB) are always active, regardless of the state of EN or SHDN. This allows for Ring Indicator applications without forward biasing other devices connected to the receiver outputs. This is ideal for systems where VCC is set to 0V in shutdown to accommodate peripherals, such as UARTs (Figure 2). MAX3222/MAX3237/MAX3241 Shutdown Mode Supply current falls to less than 1μA in shutdown mode (SHDN = low). When shut down, the device’s charge pumps are turned off, V+ is pulled down to VCC, V- is pulled to ground, and the transmitter outputs are disabled (high impedance). The time required to exit shutdown is typically 100μs, as shown in Figure 3. Connect SHDN to VCC if the shutdown mode is not used. SHDN has no effect on R_OUT or R_OUTB. MAX3222/MAX3237/MAX3241 Enable Control The inverting receiver outputs (R_OUT) are put into a high-impedance state when EN is high. The complementary outputs R1OUTB and R2OUTB are always active, regardless of the state of EN and SHDN (Table 1). EN has no effect on T_OUT. __________Applications Information Capacitor Selection The capacitor type used for C1–C4 is not critical for proper operation; polarized or nonpolarized capacitors can be used. The charge pump requires 0.1μF capacitors for 3.3V operation. For other supply voltages, refer to Table 2 for required capacitor values. Do not use values lower than those listed in Table 2. Increasing the capacitor values (e.g., by a factor of 2) reduces ripple on the transmitter outputs and slightly reduces power consumption. C2, C3, and C4 can be increased without changing C1’s value. However, do not increase C1 without also increasing the values of C2, C3, and C4, to maintain the proper ratios (C1 to the other capacitors). When using the minimum required capacitor values, make sure the capacitor value does not degrade excessively with temperature. If in doubt, use capacitors with a higher nominal value. The capacitor’s equivalent series resistance (ESR), which usually rises at low temperatures, influences the amount of ripple on V+ and V-. MAX3237 MAX3241 T1OUT R1OUTB Tx UART VCC T1IN LOGIC TRANSITION DETECTOR R1OUT R1IN EN = VCC SHDN = GND VCC TO μP Rx PREVIOUS RS-232 Tx UART PROTECTION DIODE PROTECTION DIODE SHDN = GND VCC VCC GND Rx 5kΩ a) OLDER RS-232: POWERED-DOWN UART DRAWS CURRENT FROM ACTIVE RECEIVER OUTPUT IN SHUTDOWN. b) NEW MAX3237/MAX3241: EN SHUTS DOWN RECEIVER OUTPUTS (EXCEPT FOR B OUTPUTS), SO NO CURRENT FLOWS TO UART IN SHUTDOWN. B OUTPUTS INDICATE RECEIVER ACTIVITY DURING SHUTDOWN WITH EN HIGH. GND 5kΩ Figure 2. Detection of RS-232 Activity when the UART and Interface are Shut Down; Comparison of MAX3237/MAX3241 (b) with Previous Transceivers (a). MAX3222/MAX3232/MAX3237/MAX3241 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors _______________________________________________________________________________________ 9 Power-Supply Decoupling In most circumstances, a 0.1μF bypass capacitor is adequate. In applications that are sensitive to powersupply noise, decouple VCC to ground with a capacitor of the same value as charge-pump capacitor C1. Connect bypass capacitors as close to the IC as possible. Operation Down to 2.7V Transmitter outputs will meet EIA/TIA-562 levels of ±3.7V with supply voltages as low as 2.7V. Transmitter Outputs when Exiting Shutdown Figure 3 shows two transmitter outputs when exiting shutdown mode. As they become active, the two transmitter outputs are shown going to opposite RS-232 levels (one transmitter input is high, the other is low). Each transmitter is loaded with 3kΩ in parallel with 2500pF. The transmitter outputs display no ringing or undesirable transients as they come out of shutdown. Note that the transmitters are enabled only when the magnitude of V- exceeds approximately 3V. Mouse Driveability The MAX3241 has been specifically designed to power serial mice while operating from low-voltage power supplies. It has been tested with leading mouse brands from manufacturers such as Microsoft and Logitech. The MAX3241 successfully drove all serial mice tested and met their respective current and voltage requirements. Figure 4a shows the transmitter output voltages under increasing load current at 3.0V. Figure 4b shows a typical mouse connection using the MAX3241. Table 1. MAX3222/MAX3237/MAX3241 Shutdown and Enable Control Truth Table Table 2. Required Minimum Capacitor Values 5V/div VCC = 3.3V C1–C4 = 0.1μF 2V/div T2 50μs/div T1 Figure 3. Transmitter Outputs when Exiting Shutdown or Powering Up VCC (V) C1 (μF) 4.5 to 5.5 0.047 3.0 to 5.5 0.1 C2, C3, C4 (μF) MAX3222/MAX3232/MAX3241 0.33 0.47 1 Active 0 1 1 Active SHDN 0 1 High-Z 0 0 High-Z EN T_OUT High-Z Active High-Z Active R_OUT R_OUTB (MAX3237/ MAX3241) Active Active Active Active 3.0 to 3.6 0.22 3.15 to 3.6 0.1 MAX3237 0.22 0.1 4.5 to 5.5 0.047 3.0 to 5.5 0.22 0.33 1.0 3.0 to 3.6 0.1 0.1 MAX3222/MAX3232/MAX3237/MAX3241 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors 10 ______________________________________________________________________________________ MAX3241 23 EN 15 R5OUT 16 R4OUT 17 R3OUT 18 R2OUT 19 R1OUT 20 R2OUTB 21 R1OUTB 5kΩ 5kΩ 5kΩ 5kΩ 5kΩ R5IN 8 R4IN 7 6 R2IN 5 R1IN 4 SHDN 22 GND 25 12 T3IN 13 T2IN 14 T1IN 2 C2- 1 C2+ 24 C1- 28 C1+ T3OUT 11 +V COMPUTER SERIAL PORT MOUSE +V -V GND Tx T2OUT 10 T1OUT 9 V- 3 V+ VCC 27 VCC C4 C1 C3 C2 0.1μF VCC = 3V to 5.5V 26 R3IN Figure 4b. Mouse Driver Test Circuit -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 MAX3222-04 LOAD CURRENT PER TRANSMITTER (mA) TRANSMITTER OUTPUT VOLTAGE (V) VOUT+ VCC = 3.0V VOUTVOUT+ VCC VOUTT1 T2 T3 Figure 4a. MAX3241 Transmitter Output Voltage vs. Load Current per Transmitter MAX3222/MAX3232/MAX3237/MAX3241 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors ______________________________________________________________________________________ 11 High Data Rates The MAX3222/MAX3232/MAX3241 maintain the RS-232 ±5.0V minimum transmitter output voltage even at high data rates. Figure 5 shows a transmitter loopback test circuit. Figure 6 shows a loopback test result at 120kbps, and Figure 7 shows the same test at 235kbps. For Figure 6, all transmitters were driven simultaneously at 120kbps into RS-232 loads in parallel with 1000pF. For Figure 7, a single transmitter was driven at 235kbps, and all transmitters were loaded with an RS-232 receiver in parallel with 1000pF. The MAX3237 maintains the RS-232 ±5.0V minimum transmitter output voltage at data rates up to 1Mbps. Figure 8 shows a loopback test result at 1Mbps with MBAUD = VCC. For Figure 8, all transmitters were loaded with an RS-232 receiver in parallel with 250pF. MAX3222 MAX3232 MAX3237 MAX3241 5kΩ R_ OUT R_ IN EN* C2- C2+ C1- C1+ VV+ VCC C4 C1 C3 C2 0.1μF VCC SHDN* T_ IN T_ OUT GND VCC 0V 1000pF *MAX3222/MAX3237/MAX3241 ONLY T1IN R1OUT VCC = 3.3V T1OUT 5V/div 5V/div 5V/div 5μs/div Figure 5. Loopback Test Circuit Figure 6. MAX3241 Loopback Test Result at 120kbps T1IN R1OUT VCC = 3.3V T1OUT 5V/div 5V/div 2μs/div 5V/div Figure 7. MAX3241 Loopback Test Result at 235kbps +5V 0V +5V 0V -5V +5V 0V T_IN T_OUT = R_IN 5kΩ + 250pF R_OUT 150pF 200ns/div VCC = 3.3V Figure 8. MAX3237 Loopback Test Result at 1000kbps (MBAUD = VCC) MAX3222/MAX3232/MAX3237/MAX3241 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors 12 ______________________________________________________________________________________ __________________________________________________Typical Operating Circuits MAX3222 10 R2OUT 1 13 R1OUT R2IN 9 18 GND 16 RS-232 OUTPUTS TTL/CMOS INPUTS 11 T2IN 12 T1IN C2- 6 5 C2+ 4 C1- 2 C1+ R1IN 14 T2OUT 8 T1OUT 15 V- 7 V+ VCC 3 17 C1 0.1μF C2 0.1μF 0.1μF +3.3V RS-232 INPUTS TTL/CMOS OUTPUTS EN SHDN C3* 0.1μF C4 0.1μF PIN NUMBERS REFER TO DIP/SO PACKAGES. * C3 CAN BE RETURNED TO EITHER VCC OR GROUND. MAX3232 9 R2OUT 12 R1OUT R2IN 8 GND 15 RS-232 OUTPUTS TTL/CMOS INPUTS 10 T2IN 11 T1IN C2- 5 4 C2+ 3 C1- 1 C1+ R1IN 13 T2OUT 7 T1OUT 14 V- 6 V+ VCC 2 C4 0.1μF 16 0.1μF 0.1μF 0.1μF +3.3V RS-232 INPUTS TTL/CMOS OUTPUTS C3* 0.1μF * C3 CAN BE RETURNED TO EITHER VCC OR GROUND. SEE TABLE 2 FOR CAPACITOR SELECTION 5kΩ 5kΩ 5kΩ 5kΩ Interconnection with 3V and 5V Logic The MAX3222/MAX3232/MAX3237/MAX3241 can directly interface with various 5V logic families, including ACT and HCT CMOS. See Table 3 for more information on possible combinations of interconnections. Table 3. Logic-Family Compatibility with Various Supply Voltages Compatible with ACT and HCT CMOS, and with TTL. Incompatible with AC, HC, and CD4000 CMOS. 5 3.3 SYSTEM POWERSUPPLY VOLTAGE (V) Compatible with all TTL and CMOS-logic families. 5 5 Compatible with all CMOS families. 3.3 3.3 COMPATIBILITY MAX32_ _ VCC SUPPLY VOLTAGE (V) MAX3222/MAX3232/MAX3237/MAX3241 _____________________________________Typical Operating Circuits (continued) MAX3241 23 EN 15 R5OUT 16 R4OUT 17 R3OUT 18 R2OUT 19 R1OUT 20 R2OUTB 21 R1OUTB TTL/CMOS OUTPUTS 5kΩ 5kΩ 5kΩ 5kΩ 5kΩ R5IN 8 * C3 CAN BE RETURNED TO EITHER VCC OR GROUND. R4IN 7 R3IN 6 R2IN 5 R1IN 4 RS-232 INPUTS SHDN 22 GND 25 RS-232 OUTPUTS TTL/CMOS INPUTS 12 T3IN 13 T2IN 14 T1IN C2- 2 1 C2+ 24 C1- 28 C1+ T3OUT 11 T2OUT 10 T1OUT 9 V- 3 V+ VCC 27 C4 0.1μF C3* 0.1μF 0.1μF 0.1μF 0.1μF +3.3V 26 MAX3237 13 EN 18 R3OUT 20 R2OUT 21 R1OUT 16 R1OUTB LOGIC OUTPUTS 5kΩ 5kΩ 5kΩ * C3 CAN BE RETURNED TO EITHER VCC OR GROUND. R3IN 11 R2IN 9 R1IN 8 RS-232 INPUTS GND 2 RS-232 OUTPUTS LOGIC INPUTS 22 T3IN 23 T2IN 24 T1IN C2- 3 1 C2+ 25 C1- 28 C1+ T3OUT 7 T2OUT 6 T1OUT 5 T1 T2 T3 R1 R2 R3 V- 4 V+ VCC 27 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF 26 MBAUD 15 17 T5IN 19 T4IN T5OUT 12 T4OUT 10 SHDN 14 T4 T5 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors ______________________________________________________________________________________ 13 MAX3222/MAX3232/MAX3237/MAX3241 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors 14 ______________________________________________________________________________________ _____________________________________________Pin Configurations (continued) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC GND T1OUT C2+ R1IN C1- V+ C1+ MAX3232 R1OUT T1IN T2IN R2IN R2OUT T2OUT VC2- DIP/SO/SSOP/TSSOP + TOP VIEW 20 19 18 17 16 15 14 13 1 2 3 8 12 10 11 4 5 6 7 SHDN VCC GND C1- T1OUT V+ C1+ EN R1IN R1OUT T1IN T2IN T2OUT VC2- C2+ R2IN 9 R2OUT SSOP/TSSOP + N.C. N.C. MAX3222 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C1+ V+ VCC C1- T1IN T2IN MBAUD T3IN R1OUT R2OUT T4IN R3OUT T5IN R1OUTB SHDN EN T5OUT R3IN T4OUT R2IN R1IN T3OUT T2OUT T1OUT VC2- GND C2+ SSOP MAX3237 + 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C1+ V+ VCC GND C1- EN R5OUT SHDN R1OUTB R2OUTB R1OUT R2OUT R3OUT R4OUT T1IN T2IN T3IN T3OUT T2OUT T1OUT R5IN R4IN R3IN R2IN R1IN VC2- C2+ SO/SSOP/TSSOP MAX3241 + MAX3222/MAX3232/MAX3237/MAX3241 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors ______________________________________________________________________________________ 15 ______3V-Powered EIA/TIA-232 and EIA/TIA-562 Transceivers from Maxim Ordering Information (continued) *Dice are tested at TA = +25°C, DC parameters only. +Denotes lead-free package. 0.1μF capacitors, 1 complementary receiver, MegaBaud operation MAX3237 3.0 to 5.5 5/3 3 250/1000 232 0.1μF capacitors, AutoShutdown, complementary receiver, drives mice MAX3243 3.0 to 5.5 3/5 1 120 232 MAX3232 3.0 to 5.5 2/2 N/A 120 232 0.1μF capacitors MAX3223 3.0 to 5.5 2/2 2 120 232 0.1μF capacitors, AutoShutdown MAX3222 3.0 to 5.5 2/2 2 120 232 0.1μF capacitors 232 562 232 562 232 EIA/ TIA-232 OR 562 2.7 to 3.6 AutoShutdown, complementary receiver, drives mice, transient detection MAX3212 3/5 5 235 MAX563 3.0 to 3.6 2/2 2 230 0.1μF capacitors Operates directly from batteries without a voltage regulator MAX218 1.8 to 4.25 2/2 2 120 No. OF RECEIVERS ACTIVE IN SHUTDOWN POWERSUPPLY VOLTAGE (V) MAX562 2.7 to 5.25 3/5 5 230 Wide supply range MAX212 3.0 to 3.6 3/5 5 120 Drives mice FEATURES GUARANTEED DATA RATE (kbps) No. OF TRANSMITTERS/ RECEIVERS PART 0.1μF capacitors, 2 complementary receivers, drives mice MAX3241 3.0 to 5.5 3/5 5 120 232 PART TEMP RANGE PIN-PACKAGE PKG CODE MAX3222EUP+ -40°C to +85°C 20 TSSOP U20+2 MAX3222EAP+ -40°C to +85°C 20 SSOP A20+1 MAX3222EWN+ -40°C to +85°C 18 SO W18+1 MAX3222EPN+ -40°C to +85°C 18 Plastic Dip P18+5 MAX3222C/D 0°C to +70°C Dice* — MAX3232CUE+ 0°C to +70°C 16 TSSOP U16+1 MAX3232CSE+ 0°C to +70°C 16 Narrow SO S16+1 MAX3232CWE+ 0°C to +70°C 16 Wide SO W16+1 MAX3232CPE+ 0°C to +70°C 16 Plastic DIP P16+1 MAX3232EUE+ -40°C to +85°C 16 TSSOP U16+1 MAX3232ESE+ -40°C to +85°C 16 Narrow SO S16+5 PART TEMP RANGE PIN-PACKAGE PKG CODE MAX3232EWE+ -40°C to +85°C 16 Wide SO W16+1 MAX3232EPE+ -40°C to +85°C 16 Plastic DIP P16+1 MAX3232CAE+ 0°C to +70°C 16 SSOP A28+2 MAX3237CAI+ 0°C to +70°C 28 SSOP A28+1 MAX3237ENI+ -40°C to +85°C 28 SSOP A28+1 MAX3241CAI+ 0°C to +70°C 28 SSOP A28+1 MAX3241CWI+ 0°C to +70°C 28 SO W28+6 MAX3241EUI+ -40°C to +85°C 28 TSSOP U28+2 MAX3241EAI+ -40°C to +85°C 28 SSOP A28+1 MAX3241EWI+ -40°C to +85°C 28 SO W28+6 MAX3222/MAX3232/MAX3237/MAX3241 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors 16 ______________________________________________________________________________________ ___________________Chip Topography ___________________Chip Information T2IN T1IN 0.127" (3.225mm) 0.087" (2.209mm) T2OUT R2IN R2OUT R1OUT R1IN T1OUT V+ C1+ VCC SHDN EN C1- C2+ C2- VGND MAX3222 TRANSISTOR COUNT: 339 SUBSTRATE CONNECTED TO GND MAX3222 339 MAX3232 339 MAX3237 1212 MAX3241 894 PART TRANSISTOR COUNT 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1μF External Capacitors Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 © 2007 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX3222/MAX3232/MAX3237/MAX3241 TSSOP4.40mm.EPS Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Revision History Pages changed at Rev 7: 1, 15, 16, 17 Precision Micropower, Low Dropout Voltage References Data Sheet REF19x Series Rev. L Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1996–2011 Analog Devices, Inc. All rights reserved. FEATURES Temperature coefficient: 5 ppm/°C maximum High output current: 30 mA Low supply current: 45 μA maximum Initial accuracy: ±2 mV maximum1 Sleep mode: 15 μA maximum Low dropout voltage Load regulation: 4 ppm/mA Line regulation: 4 ppm/V Short-circuit protection APPLICATIONS Portable instruments ADCs and DACs Smart sensors Solar powered applications Loop-current-powered instruments GENERAL DESCRIPTION The REF19x series precision band gap voltage references use a patented temperature drift curvature correction circuit and laser trimming of highly stable, thin-film resistors to achieve a very low temperature coefficient and high initial accuracy. The REF19x series is made up of micropower, low dropout voltage (LDV) devices, providing stable output voltage from supplies as low as 100 mV above the output voltage and consuming less than 45 μA of supply current. In sleep mode, which is enabled by applying a low TTL or CMOS level to the SLEEP pin, the output is turned off and supply current is further reduced to less than 15 μA. The REF19x series references are specified over the extended industrial temperature range (−40°C to +85°C) with typical performance specifications over −40°C to +125°C for applications, such as automotive. All electrical grades are available in an 8-lead SOIC package; the PDIP and TSSOP packages are available only in the lowest electrical grade. TEST PINS Test Pin 1 and Test Pin 5 are reserved for in-package Zener zap. To achieve the highest level of accuracy at the output, the Zener zapping technique is used to trim the output voltage. Because each unit may require a different amount of adjustment, the resistance value at the test pins varies widely from pin to pin and from part to part. The user should leave Pin 1 and Pin 5 unconnected. REF19xSERIESTOP VIEW(Not to Scale)TP1VS2SLEEP3GND4NCNCOUTPUTTP876500371-001NOTES1.NC = NO CONNECT.2.TP PINS ARE FACTORY TESTPOINTS, NO USER CONNECTION. Figure 1. 8-Lead SOIC_N and TSSOP Pin Configuration (S Suffix and RU Suffix) REF19xSERIESTOP VIEW(Not to Scale)TP1VS2SLEEP3GND4NCNCOUTPUTTP876500371-002NOTES1.NC = NO CONNECT.2.TP PINS ARE FACTORY TESTPOINTS, NO USER CONNECTION. Figure 2. 8-Lead PDIP Pin Configuration (P Suffix) Table 1. Nominal Output Voltage Part Number Nominal Output Voltage (V) REF191 2.048 REF192 2.50 REF193 3.00 REF194 4.50 REF195 5.00 REF196 3.30 REF198 4.096 1 Initial accuracy does not include shift due to solder heat effect (see the Applications Information section). FEATURES l VERY LOW NOISE: 4.5nV/ÖHz at 10kHz l FAST SETTLING TIME: OPA627—550ns to 0.01% OPA637—450ns to 0.01% l LOW VOS: 100mV max l LOW DRIFT: 0.8mV/°C max l LOW IB: 5pA max l OPA627: Unity-Gain Stable l OPA637: Stable in Gain ³ 5 OPA627 OPA637 DESCRIPTION The OPA627 and OPA637 Difet operational amplifiers provide a new level of performance in a precision FET op amp. When compared to the popular OPA111 op amp, the OPA627/637 has lower noise, lower offset voltage, and much higher speed. It is useful in a broad range of precision and high speed analog circuitry. The OPA627/637 is fabricated on a high-speed, dielectrically- isolated complementary NPN/PNP process. It operates over a wide range of power supply voltage— ±4.5V to ±18V. Laser-trimmed Difet input circuitry provides high accuracy and low-noise performance comparable with the best bipolar-input op amps. High frequency complementary transistors allow increased circuit bandwidth, attaining dynamic performance not possible with previous precision FET op amps. The OPA627 is unity-gain stable. The OPA637 is stable in gains equal to or greater than five. Difet fabrication achieves extremely low input bias currents without compromising input voltage noise performance. Low input bias current is maintained over a wide input common-mode voltage range with unique cascode circuitry. The OPA627/637 is available in plastic DIP, SOIC and metal TO-99 packages. Industrial and military temperature range models are available. Difet ®, Burr-Brown Corp. ® Precision High-Speed Difet ® OPERATIONAL AMPLIFIERS APPLICATIONS l PRECISION INSTRUMENTATION l FAST DATA ACQUISITION l DAC OUTPUT AMPLIFIER l OPTOELECTRONICS l SONAR, ULTRASOUND l HIGH-IMPEDANCE SENSOR AMPS l HIGH-PERFORMANCE AUDIO CIRCUITRY l ACTIVE FILTERS Trim 5 Trim 1 +In 3 –In 2 Output 6 7 +VS –VS 4 ©1989 Burr-Brown Corporation PDS-998H Printed in U.S.A. March, 1998 International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 OPA627 OPA627 SBOS165 2 ® OPA627, 637 SPECIFICATIONS ELECTRICAL At TA = +25°C, and VS = ±15V, unless otherwise noted. OPA627BM, BP, SM OPA627AM, AP, AU OPA637BM, BP, SM OPA637AM, AP, AU PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS OFFSET VOLTAGE (1) Input Offset Voltage 40 100 130 250 mV AP, BP, AU Grades 100 250 280 500 mV Average Drift 0.4 0.8 1.2 2 mV/°C AP, BP, AU Grades 0.8 2 2.5 mV/°C Power Supply Rejection VS = ±4.5 to ±18V 106 120 100 116 dB INPUT BIAS CURRENT (2) Input Bias Current VCM = 0V 1 5 2 10 pA Over Specified Temperature VCM = 0V 1 2 nA SM Grade VCM = 0V 50 nA Over Common-Mode Voltage VCM = ±10V 1 2 pA Input Offset Current VCM = 0V 0.5 5 1 10 pA Over Specified Temperature VCM = 0V 1 2 nA SM Grade 50 nA NOISE Input Voltage Noise Noise Density: f = 10Hz 15 40 20 nV/ÖHz f = 100Hz 8 20 10 nV/ÖHz f = 1kHz 5.2 8 5.6 nV/ÖHz f = 10kHz 4.5 6 4.8 nV/ÖHz Voltage Noise, BW = 0.1Hz to 10Hz 0.6 1.6 0.8 mVp-p Input Bias Current Noise Noise Density, f = 100Hz 1.6 2.5 2.5 fA/ÖHz Current Noise, BW = 0.1Hz to 10Hz 30 60 48 fAp-p INPUT IMPEDANCE Differential 1013 || 8 * W || pF Common-Mode 1013 || 7 * W || pF INPUT VOLTAGE RANGE Common-Mode Input Range ±11 ±11.5 * * V Over Specified Temperature ±10.5 ±11 * * V Common-Mode Rejection VCM = ±10.5V 106 116 100 110 dB OPEN-LOOP GAIN Open-Loop Voltage Gain VO = ±10V, RL = 1kW 112 120 106 116 dB Over Specified Temperature VO = ±10V, RL = 1kW 106 117 100 110 dB SM Grade VO = ±10V, RL = 1kW 100 114 dB FREQUENCY RESPONSE Slew Rate: OPA627 G = –1, 10V Step 40 55 * * V/ms OPA637 G = –4, 10V Step 100 135 * * V/ms Settling Time: OPA627 0.01% G = –1, 10V Step 550 * ns 0.1% G = –1, 10V Step 450 * ns OPA637 0.01% G = –4, 10V Step 450 * ns 0.1% G = –4, 10V Step 300 * ns Gain-Bandwidth Product: OPA627 G = 1 16 * MHz OPA637 G = 10 80 * MHz Total Harmonic Distortion + Noise G = +1, f = 1kHz 0.00003 * % POWER SUPPLY Specified Operating Voltage ±15 * V Operating Voltage Range ±4.5 ±18 * * V Current ±7 ±7.5 * * mA OUTPUT Voltage Output RL = 1kW ±11.5 ±12.3 * * Over Specified Temperature ±11 ±11.5 * * V Current Output VO = ±10V ±45 * mA Short-Circuit Current ±35 +70/–55 ±100 * * * mA Output Impedance, Open-Loop 1MHz 55 * W TEMPERATURE RANGE Specification: AP, BP, AM, BM, AU –25 +85 * * °C SM –55 +125 °C Storage: AM, BM, SM –60 +150 * * °C AP, BP, AU –40 +125 * * °C qJ-A: AM, BM, SM 200 * °C/W AP, BP 100 * °C/W AU 160 °C/W * Specifications same as “B” grade. NOTES: (1) Offset voltage measured fully warmed-up. (2) High-speed test at TJ = +25°C. See Typical Performance Curves for warmed-up performance. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. 3 ® OPA627, 637 PIN CONFIGURATIONS Top View DIP/SOIC Offset Trim –In +In –V No Internal Connection +V Output S Offset Trim S 1 2 3 4 8 7 6 5 Top View TO-99 Offset Trim –In Output +In Offset Trim –VS +VS No Internal Connection Case connected to –VS. 8 1 2 3 4 5 6 7 ABSOLUTE MAXIMUM RATINGS(1) Supply Voltage .................................................................................. ±18V Input Voltage Range .............................................. +VS + 2V to –VS – 2V Differential Input Range ....................................................... Total VS + 4V Power Dissipation ........................................................................ 1000mW Operating Temperature M Package .................................................................. –55°C to +125°C P, U Package ............................................................. –40°C to +125°C Storage Temperature M Package .................................................................. –65°C to +150°C P, U Package ............................................................. –40°C to +125°C Junction Temperature M Package .................................................................................. +175°C P, U Package ............................................................................. +150°C Lead Temperature (soldering, 10s) ............................................... +300°C SOlC (soldering, 3s) ................................................................... +260°C NOTE: (1) Stresses above these ratings may cause permanent damage. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PACKAGE DRAWING TEMPERATURE PRODUCT PACKAGE NUMBER(1) RANGE OPA627AP Plastic DIP 006 –25°C to +85°C OPA627BP Plastic DIP 006 –25°C to +85°C OPA627AU SOIC 182 –25°C to +85°C OPA627AM TO-99 Metal 001 –25°C to +85°C OPA627BM TO-99 Metal 001 –25°C to +85°C OPA627SM TO-99 Metal 001 –55°C to +125°C OPA637AP Plastic DIP 006 –25°C to +85°C OPA637BP Plastic DIP 006 –25°C to +85°C OPA637AU SOIC 182 –25°C to +85°C OPA637AM TO-99 Metal 001 –25°C to +85°C OPA637BM TO-99 Metal 001 –25°C to +85°C OPA637SM TO-99 Metal 001 –55°C to +125°C NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. 4 ® OPA627, 637 TYPICAL PERFORMANCE CURVES At TA = +25°C, and VS = ±15V, unless otherwise noted. INPUT VOLTAGE NOISE SPECTRAL DENSITY 1k 100 10 1 1 Frequency (Hz) Voltage Noise (nV/ Ö Hz) 10 100 1k 10k 100k 1M 10M VOLTAGE NOISE vs SOURCE RESISTANCE Source Resistance ( W ) 1k 100 10 1 100 OPA627 + Resistor Resistor Noise Only Spot Noise at 10kHz Voltage Noise (nV/ Ö Hz) 1k 10k 100k 1M 10M 100M Comparison with OPA27 Bipolar Op Amp + Resistor – + RS OPA627 GAIN/PHASE vs FREQUENCY Phase (Degrees) Gain (dB) 30 20 10 0 –10 –90 –120 –150 –180 –210 1 Phase Gain Frequency (MHz) 10 100 75° Phase Margin OPA637 GAIN/PHASE vs FREQUENCY Phase (Degrees) Gain (dB) 30 20 10 0 –10 –90 –120 –150 –180 –210 1 10 100 Phase Gain Frequency (MHz) TOTAL INPUT VOLTAGE NOISE vs BANDWIDTH 100 10 1 0.1 0.01 1 10 100 1k 10k 100k 1M 10M Bandwidth (Hz) Input Voltage Noise (μV) Noise Bandwidth: 0.1Hz to indicated frequency. RMS p-p OPEN-LOOP GAIN vs FREQUENCY Frequency (Hz) Voltage Gain (dB) 1 10 100 1k 10k 100k 1M 10M 100M 140 120 100 80 60 40 20 0 –20 OPA637 OPA627 5 ® OPA627, 637 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, and VS = ±15V, unless otherwise noted. OPEN-LOOP GAIN vs TEMPERATURE Voltage Gain (dB) Temperature (°C) 125 120 115 110 105 –75 –50 –25 0 25 50 75 100 125 OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY Frequency (Hz) Output Resistance (W) 100 80 60 40 20 0 2 20 200 2k 20k 200k 2M 20M COMMON-MODE REJECTION vs FREQUENCY Frequency (Hz) Common-Mode Rejection Ratio (dB) 140 120 100 80 60 40 20 0 1 10 100 1k 10k 100k 1M 10M OPA627 OPA637 COMMON-MODE REJECTION vs INPUT COMMON MODE VOLTAGE 130 120 110 100 90 80 Common-Mode Rejection (dB) Common-Mode Voltage (V) –15 –10 –5 0 5 10 15 POWER-SUPPLY REJECTION vs FREQUENCY Frequency (Hz) Power-Supply Rejection (dB) 140 120 100 80 60 40 20 0 1 –VS PSRR 627 and 637 +VS PSRR 627 637 10 100 1k 10k 100k 1M 10M POWER-SUPPLY REJECTION AND COMMON-MODE REJECTION vs TEMPERATURE Temperature (°C) CMR and PSR (dB) 125 120 115 110 105 –75 PSR CMR –50 –25 0 25 50 75 100 125 6 ® OPA627, 637 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, and VS = ±15V, unless otherwise noted. SUPPLY CURRENT vs TEMPERATURE Temperature (°C) Supply Current (mA) 8 7.5 7 6.5 6 –75 –50 –25 0 25 50 75 100 125 OUTPUT CURRENT LIMIT vs TEMPERATURE Output Current (mA) 100 80 60 40 20 0 –75 –50 –25 0 25 50 75 100 125 Temperature (°C) –IL at VO = –10V –IL at VO = 0V +IL at VO = +10V +IL at VO = 0V OPA627 GAIN-BANDWIDTH AND SLEW RATE vs TEMPERATURE Temperature (°C) Gain-Bandwidth (MHz) 24 20 16 12 8 –75 Slew Rate GBW 60 55 50 Slew Rate (V/μs) –50 –25 0 25 50 75 100 125 OPA637 GAIN-BANDWIDTH AND SLEW RATE vs TEMPERATURE Temperature (°C) Gain-Bandwidth (MHz) 120 100 80 60 40 –75 Slew Rate (V/μs) 160 140 120 100 80 Slew Rate GBW –50 –25 0 25 50 75 100 125 OPA627 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY Frequency (Hz) THD+N (%) 20 100 1k 10k 20k 0.1 0.01 0.001 0.0001 0.00001 G = +10 G = +1 Measurement BW: 80kHz – + – + 100pF 100pF G = +1 G = +10 VI VI 549 5k 600 600 VO = ±10V VO = ±10V W W W W OPA637 TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY Frequency (Hz) THD+N (%) 20 100 1k 10k 20k 1 0.1 0.01 0.001 0.0001 G = +10 G = +50 – + 100pF G = +10 VI 549 5k 600 VO = ±10V W W W – + 100pF G = +50 VI 102 5k 600 VO = ±10V W W W Measurement BW: 80kHz 7 ® OPA627, 637 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, and VS = ±15V, unless otherwise noted. INPUT BIAS AND OFFSET CURRENT vs JUNCTION TEMPERATURE Junction Temperature (°C) Input Current (pA) 10k 1k 100 10 1 0.1 –50 –25 0 25 50 75 100 125 150 IB IOS INPUT BIAS CURRENT vs POWER SUPPLY VOLTAGE Supply Voltage (±VS) Input Bias Current (pA) 20 15 10 5 0 ±4 ±6 ±8 ±10 ±12 ±14 ±16 ±18 NOTE: Measured fully warmed-up. TO-99 with 0807HS Heat Sink TO-99 Plastic DIP, SOIC INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE Common-Mode Voltage (V) Input Bias Current Multiplier 1.2 1.1 1 0.9 0.8 –15 –10 –5 0 5 10 15 Beyond Linear Common-Mode Range Beyond Linear Common-Mode Range INPUT OFFSET VOLTAGE WARM-UP vs TIME Time From Power Turn-On (Min) Offset Voltage Change (μV) 50 25 0 –25 –50 0 1 2 3 4 5 6 MAX OUTPUT VOLTAGE vs FREQUENCY Frequency (Hz) Output Voltage (Vp-p) 30 20 10 0 100k 1M 10M 100M OPA627 OPA637 SETTLING TIME vs CLOSED-LOOP GAIN 100 10 1 0.1 –1 –10 –100 –1000 Closed-Loop Gain (V/V) Settling Time (μs) Error Band: ±0.01% OPA637 OPA627 8 ® OPA627, 637 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, and VS = ±15V, unless otherwise noted. FIGURE 1. Circuits with Noise Gain Less than Five Require the OPA627 for Proper Stability. SETTLING TIME vs ERROR BAND 1500 1000 500 0 0.001 0.01 0.1 1 10 Error Band (%) Settling Time (ns) OPA637 G = –4 OPA627 G = –1 – + CF RI RF 2kW +5V –5V OPA627 OPA637 RI 2kW 500W RF 2kW 2kW CF 6pF 4pF SETTLING TIME vs LOAD CAPACITANCE 0 150 200 300 400 500 Load Capacitance (pF) 3 2 1 0 Settling Time (μs) Error Band: ±0.01% OPA637 G = –4 OPA627 G = –1 APPLICATIONS INFORMATION The OPA627 is unity-gain stable. The OPA637 may be used to achieve higher speed and bandwidth in circuits with noise gain greater than five. Noise gain refers to the closed-loop gain of a circuit as if the non-inverting op amp input were being driven. For example, the OPA637 may be used in a non-inverting amplifier with gain greater than five, or an inverting amplifier of gain greater than four. When choosing between the OPA627 or OPA637, it is important to consider the high frequency noise gain of your circuit configuration. Circuits with a feedback capacitor (Figure 1) place the op amp in unity noise-gain at high frequency. These applications must use the OPA627 for proper stability. An exception is the circuit in Figure 2, where a small feedback capacitance is used to compensate for the input capacitance at the op amp’s inverting input. In this case, the closed-loop noise gain remains constant with frequency, so if the closed-loop gain is equal to five or greater, the OPA637 may be used. – + – + – + – + – + – + Buffer Bandwidth Limiting Integrator Filter RI RF < 4R Inverting Amp G < |–4| RI RF < 4RI Non-Inverting Amp G < 5 OPA627 OPA627 OPA627 OPA627 OPA627 OPA627 9 ® OPA627, 637 – + C2 C1 R2 R1 OPA637 C1 = CIN + CSTRAY C2 = R1 C1 R2 OFFSET VOLTAGE ADJUSTMENT The OPA627/637 is laser-trimmed for low offset voltage and drift, so many circuits will not require external adjustment. Figure 3 shows the optional connection of an external potentiometer to adjust offset voltage. This adjustment should not be used to compensate for offsets created elsewhere in a system (such as in later amplification stages or in an A/D converter) because this could introduce excessive temperature drift. Generally, the offset drift will change by approximately 4mV/°C for 1mV of change in the offset voltage due to an offset adjustment (as shown on Figure 3). FIGURE 2. Circuits with Noise Gain Equal to or Greater than Five May Use the OPA637. amp contributes little additional noise. Below 1kW, op amp noise dominates over the resistor noise, but compares favorably with precision bipolar op amps. CIRCUIT LAYOUT As with any high speed, wide bandwidth circuit, careful layout will ensure best performance. Make short, direct interconnections and avoid stray wiring capacitance—especially at the input pins and feedback circuitry. The case (TO-99 metal package only) is internally connected to the negative power supply as it is with most common op amps. Pin 8 of the plastic DIP, SOIC, and TO-99 packages has no internal connection. Power supply connections should be bypassed with good high frequency capacitors positioned close to the op amp pins. In most cases 0.1mF ceramic capacitors are adequate. The OPA627/637 is capable of high output current (in excess of 45mA). Applications with low impedance loads or capacitive loads with fast transient signals demand large currents from the power supplies. Larger bypass capacitors such as 1mF solid tantalum capacitors may improve dynamic performance in these applications. NOISE PERFORMANCE Some bipolar op amps may provide lower voltage noise performance, but both voltage noise and bias current noise contribute to the total noise of a system. The OPA627/637 is unique in providing very low voltage noise and very low current noise. This provides optimum noise performance over a wide range of sources, including reactive source impedances. This can be seen in the performance curve showing the noise of a source resistor combined with the noise of an OPA627. Above a 2kW source resistance, the op FIGURE 4. Connection of Input Guard for Lowest IB. Board Layout for Input Guarding: Guard top and bottom of board. Alternate—use Teflon® standoff for sensitive input pins. Teflon® E.I. du Pont de Nemours & Co. – + 2 In 3 Non-inverting 6 OPA627 Out – + 2 3 In Inverting 6 OPA627 Out – + 2 In 3 Buffer 6 OPA627 Out 3 2 4 5 6 7 8 No Internal Connection 1 TO-99 Bottom View To Guard Drive – + 2 3 7 1 5 6 +VS –VS OPA627/637 100kW 10kW to 1MW Potentiometer (100kW preferred) ±10mV Typical Trim Range 4 FIGURE 3. Optional Offset Voltage Trim Circuit. 10 ® OPA627, 637 takes approximately 500ns. When the output is driven into the positive limit, recovery takes approximately 6ms. Output recovery of the OPA627 can be improved using the output clamp circuit shown in Figure 5. Diodes at the inverting input prevent degradation of input bias current. INPUT BIAS CURRENT Difet fabrication of the OPA627/637 provides very low input bias current. Since the gate current of a FET doubles approximately every 10°C, to achieve lowest input bias current, the die temperature should be kept as low as possible. The high speed and therefore higher quiescent current of the OPA627/637 can lead to higher chip temperature. A simple press-on heat sink such as the Burr-Brown model 807HS (TO-99 metal package) can reduce chip temperature by approximately 15°C, lowering the IB to one-third its warmed-up value. The 807HS heat sink can also reduce lowfrequency voltage noise caused by air currents and thermoelectric effects. See the data sheet on the 807HS for details. Temperature rise in the plastic DIP and SOIC packages can be minimized by soldering the device to the circuit board. Wide copper traces will also help dissipate heat. The OPA627/637 may also be operated at reduced power supply voltage to minimize power dissipation and temperature rise. Using ±5V power supplies reduces power dissipation to one-third of that at ±15V. This reduces the IB of TO- 99 metal package devices to approximately one-fourth the value at ±15V. Leakage currents between printed circuit board traces can easily exceed the input bias current of the OPA627/637. A circuit board “guard” pattern (Figure 4) reduces leakage effects. By surrounding critical high impedance input circuitry with a low impedance circuit connection at the same potential, leakage current will flow harmlessly to the lowimpedance node. The case (TO-99 metal package only) is internally connected to –VS. Input bias current may also be degraded by improper handling or cleaning. Contamination from handling parts and circuit boards may be removed with cleaning solvents and deionized water. Each rinsing operation should be followed by a 30-minute bake at 85°C. Many FET-input op amps exhibit large changes in input bias current with changes in input voltage. Input stage cascode circuitry makes the input bias current of the OPA627/637 virtually constant with wide common-mode voltage changes. This is ideal for accurate high inputimpedance buffer applications. PHASE-REVERSAL PROTECTION The OPA627/637 has internal phase-reversal protection. Many FET-input op amps exhibit a phase reversal when the input is driven beyond its linear common-mode range. This is most often encountered in non-inverting circuits when the input is driven below –12V, causing the output to reverse into the positive rail. The input circuitry of the OPA627/637 does not induce phase reversal with excessive commonmode voltage, so the output limits into the appropriate rail. OUTPUT OVERLOAD When the inputs to the OPA627/637 are overdriven, the output voltage of the OPA627/637 smoothly limits at approximately 2.5V from the positive and negative power supplies. If driven to the negative swing limit, recovery +VS 5kW (2) HP 5082-2811 1kW 5kW –VS VO Diode Bridge BB: PWS740-3 ZD1 : 10V IN961 Clamps output at VO = ±11.5V RI VI – + RF ZD1 OPA627 FIGURE 5. Clamp Circuit for Improved Overload Recovery. CAPACITIVE LOADS As with any high-speed op amp, best dynamic performance can be achieved by minimizing the capacitive load. Since a load capacitance presents a decreasing impedance at higher frequency, a load capacitance which is easily driven by a slow op amp can cause a high-speed op amp to perform poorly. See the typical curves showing settling times as a function of capacitive load. The lower bandwidth of the OPA627 makes it the better choice for driving large capacitive loads. Figure 6 shows a circuit for driving very large load capacitance. This circuit’s two-pole response can also be used to sharply limit system bandwidth. This is often useful in reducing the noise of systems which do not require the full bandwidth of the OPA627. FIGURE 6. Driving Large Capacitive Loads. R1 – + RF 1kW OPA627 CF G = +1 BW 1MHz 200pF For Approximate Butterworth Response: CF = 2 RO CL RF RF >> RO G = 1+ RF R1 ³ Optional Gain Gain > 1 f–3dB = 1 2p Ö RF RO CF CL CL 5nF RO 20W 11 ® OPA627, 637 INPUT PROTECTION The inputs of the OPA627/637 are protected for voltages between +VS + 2V and –VS – 2V. If the input voltage can exceed these limits, the amplifier should be protected. The diode clamps shown in Figure 7a will prevent the input voltage from exceeding one forward diode voltage drop beyond the power supplies—well within the safe limits. If the input source can deliver current in excess of the maximum forward current of the protection diodes, use a series resistor, RS, to limit the current. Be aware that adding resistance to the input will increase noise. The 4nV/ÖHz theoretical thermal noise of a 1kW resistor will add to the 4.5nV/ÖHz noise of the OPA627/637 (by the square-root of the sum of the squares), producing a total noise of 6nV/ÖHz. Resistors below 100W add negligible noise. Leakage current in the protection diodes can increase the total input bias current of the circuit. The specified maximum leakage current for commonly used diodes such as the 1N4148 is approximately 25nA—more than a thousand times larger than the input bias current of the OPA627/637. Leakage current of these diodes is typically much lower and may be adequate in many applications. Light falling on the junction of the protection diodes can dramatically increase leakage current, so common glass-packaged diodes should be shielded from ambient light. Very low leakage can be achieved by using a diode-connected FET as shown. The 2N4117A is specified at 1pA and its metal case shields the junction from light. Sometimes input protection is required on I/V converters of inverting amplifiers (Figure 7b). Although in normal operation, the voltage at the summing junction will be near zero (equal to the offset voltage of the amplifier), large input transients may cause this node to exceed 2V beyond the power supplies. In this case, the summing junction should be protected with diode clamps connected to ground. Even with the low voltage present at the summing junction, common signal diodes may have excessive leakage current. Since the reverse voltage on these diodes is clamped, a diode-connected signal transistor can be used as an inexpensive low leakage diode (Figure 7b). FIGURE 7. Input Protection Circuits. – + –VS +VS Optional RS VO D: IN4148 — 25nA Leakage 2N4117A — 1pA Leakage (a) = – + IIN VO D D D (b) D D: 2N3904 = NC Siliconix OPA627 OPA627 FPO When used as a unity-gain buffer, large common-mode input voltage steps produce transient variations in input-stage currents. This causes the rising edge to be slower and falling edges to be faster than nominal slew rates observed in higher-gain circuits. (A) (B) LARGE SIGNAL RESPONSE SMALL SIGNAL RESPONSE FIGURE 8. OPA627 Dynamic Performance, G = +1. – + OPA627 G = 1 12 ® OPA627, 637 When driven with a very fast input step (left), common-mode transients cause a slight variation in input stage currents which will reduce output slew rate. If the input step slew rate is reduced (right), output slew rate will increase slightly. FIGURE 9. OPA627 Dynamic Performance, G = –1. NOTE: (1) Optimum value will depend on circuit board layout and stray capacitance at the inverting input. LARGE SIGNAL RESPONSE +10 0 –10 VOUT (V) +10 0 –10 (C) (D) OPA637 LARGE SIGNAL RESPONSE OPA637 SMALL SIGNAL RESPONSE FPO FIGURE 10. OPA637 Dynamic Response, G = 5. –10 0 +10 –100 0 +100 (E) (F) VOUT (V) – + OPA627 G = –1 2kW 2kW 6pF(1) VOUT – + OPA637 G = 5 2kW 500W 4pF(1) VOUT NOTE: (1) Optimum value will depend on circuit board layout and capacitance at inverting input. VOUT (V) VOUT (mV) 13 ® OPA627, 637 OPA627 OPA637 RI, R1 2kW 500W CF 6pF 4pF Error Band ±0.5mV ±0.2mV (0.01%) NOTE: CF is selected for best settling time performance depending on test fixture layout. Once optimum value is determined, a fixed capacitor may be used. FIGURE 12. High Speed Instrumentation Amplifier, Gain = 100. –In +In + – OPA637 Differential Voltage Gain = 1 + 2RF/RG 2 3 – + – + INA105 Differential Amplifier 1 6 5 Output Gain = 100 CMRR 116dB Bandwidth 1MHz OPA637 25kW 25kW 25kW 25kW Input Common-Mode Range = ±5V » » 3pF RF 5kW RF 5kW RG 101W – + ±5V Out +15V 2kW CF 2kW Error Out RI RI 51W –15V HP- 5082- 2835 High Quality Pulse Generator / FIGURE 11. Settling Time and Slew Rate Test Circuit. FIGURE 14. Composite Amplifier for Wide Bandwidth. This composite amplifier uses the OPA603 current-feedback op amp to provide extended bandwidth and slew rate at high closed-loop gain. The feedback loop is closed around the composite amp, preserving the precision input characteristics of the OPA627/637. Use separate power supply bypass capacitors for each op amp. GAIN A1 R1 R2 R3 R4 –3dB SLEW RATE (V/V) OP AMP (W) (kW) (W) (kW) (MHz) (V/ms) 100 OPA627 50.5(1) 4.99 20 1 15 700 1000 OPA637 49.9 4.99 12 1 11 500 NOTE: (1) Closest 1/2% value. *Minimize capacitance at this node. FIGURE 13. High Speed Instrumentation Amplifier, Gain = 1000. + – OPA603 – + A1 R3 R1 R4 R2 VI VO * RL ³ 150W for ±10V Out –In +In + – OPA637 Differential Voltage Gain = (1 + 2RF/RG) • 10 2 3 – + – + INA106 Differential Amplifier 1 6 5 Output Gain = 1000 CMRR 116dB Bandwidth 400kHz OPA637 10kW 10kW 100kW 100kW Input Common-Mode Range = ±10V » » 3pF RF 5kW RF 5kW RG 101W PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples OPA627AM NRND TO-99 LMC 8 20 Green (RoHS & no Sb/Br) AU N / A for Pkg Type OPA627AM OPA627AP ACTIVE PDIP P 8 50 TBD Call TI Call TI OPA627AP OPA627APG4 ACTIVE PDIP P 8 50 TBD Call TI Call TI OPA627AP OPA627AU ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 OPA 627AU OPA627AU/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 OPA 627AU OPA627AU/2K5E4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 OPA 627AU OPA627AUE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 OPA 627AU OPA627AUG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 OPA 627AU OPA627BM NRND TO-99 LMC 8 1 Green (RoHS & no Sb/Br) AU N / A for Pkg Type OPA627BM OPA627BP ACTIVE PDIP P 8 50 TBD Call TI Call TI OPA627BP OPA627BPG4 ACTIVE PDIP P 8 50 TBD Call TI Call TI OPA627BP OPA627SM NRND TO-99 LMC 8 20 Green (RoHS & no Sb/Br) AU N / A for Pkg Type OPA627SM OPA637AM NRND TO-99 LMC 8 20 Green (RoHS & no Sb/Br) AU N / A for Pkg Type OPA637AM OPA637AM2 OBSOLETE TO-99 LMC 8 TBD Call TI Call TI OPA637AP ACTIVE PDIP P 8 50 TBD Call TI Call TI OPA637AP OPA637APG4 ACTIVE PDIP P 8 50 TBD Call TI Call TI OPA637AP OPA637AU ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 OPA 637AU OPA637AU/2K5 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 OPA 637AU OPA637AUE4 OBSOLETE SOIC D 8 TBD Call TI Call TI -25 to 85 PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples OPA637AUG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -25 to 85 OPA 637AU OPA637BM NRND TO-99 LMC 8 20 Green (RoHS & no Sb/Br) AU N / A for Pkg Type OPA637BM OPA637BM1 OBSOLETE TO-99 LMC 8 TBD Call TI Call TI OPA637BP ACTIVE PDIP P 8 50 TBD Call TI Call TI OPA637BP OPA637BPG4 ACTIVE PDIP P 8 50 TBD Call TI Call TI OPA637BP OPA637SM NRND TO-99 LMC 8 20 Green (RoHS & no Sb/Br) AU N / A for Pkg Type OPA637SM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 3 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant OPA627AU/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OPA637AU/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) OPA627AU/2K5 SOIC D 8 2500 367.0 367.0 35.0 OPA637AU/2K5 SOIC D 8 2500 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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For small orders, phone 1-800-835-8769. General Description The MAX4661/MAX4662/MAX4663 quad analog switches feature low on-resistance of 2.5½ max. On-resistance is matched between switches to 0.5W max and is flat (0.5W max) over the specified signal range. Each switch can handle Rail-to-Rail® analog signals. Offleakage current is only 5nA max at TA = +85°C. These analog switches are ideal in low-distortion applications and are the preferred solution over mechanical relays in automatic test equipment or applications where current switching is required. They have lower power requirements, use less board space, and are more reliable than mechanical relays. The MAX4661 has four normally closed (NC) switches, and the MAX4662 has four normally open (NO) switches. The MAX4663 has two NC and two NO switches, and features guaranteed break-before-make switching. These devices operate from a single +4.5V to +36V supply or from dual ±4.5V to ±20V supplies. A separate logic supply pin guarantees TTL/CMOS-logic compatibility when operating across the entire supply voltage range. Applications Reed Relay Replacement Avionics Test Equipment ADC Systems Communication Systems Sample-and-Hold Circuits PBX, PABX Systems Data Acquisition Systems Audio-Signal Routing Features © Low On-Resistance (2.5W max) © Guaranteed RON Match Between Channels (0.5W max) © Guaranteed RON Flatness over Specified Signal Range (0.5W max) © Rail-to-Rail Signal Handling © Guaranteed Break-Before-Make (MAX4663) © > 2kV ESD Protection per Method 3015.7 © +4.5V to +36V Single-Supply Operation ±4.5V to ±20V Dual-Supply Operation © TTL/CMOS-Compatible Control Inputs MAX4661/MAX4662/MAX4663 2.5W, Quad, SPST, CMOS Analog Switches ________________________________________________________________ Maxim Integrated Products 1 19-1516; Rev 0; 7/99 PART MAX4661CAE MAX4661CWE MAX4661CPE 0°C to +70°C 0°C to +70°C 0°C to +70°C TEMP. RANGE PIN-PACKAGE 16 SSOP 16 Wide SO 16 Plastic DIP Ordering Information continued at end of data sheet. Ordering Information MAX4661EAE -40°C to +85°C 16 SSOP MAX4661EWE -40°C to +85°C 16 Wide SO MAX4661EPE -40°C to +85°C 16 Plastic DIP SWITCHES SHOWN FOR LOGIC “0” INPUT SSOP/SO/DIP MAX4662 LOGIC SWITCH 0 1 OFF ON TOP VIEW SSOP/SO/DIP MAX4661 LOGIC SWITCH 0 1 ON OFF SSOP/SO/DIP MAX4663 LOGIC SWITCHES 1, 4 0 1 OFF ON SWITCHES 2, 3 ON OFF 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 IN2 COM2 NC2 V- V+ NO1 COM1 IN1 MAX4663 VL NC3 COM3 IN4 IN3 COM4 NO4 GND 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 IN2 COM2 NC2 V- V+ NC1 COM1 IN1 MAX4661 VL NC3 COM3 IN4 IN3 COM4 NC4 GND 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 IN2 COM2 NO2 V- V+ NO1 COM1 IN1 MAX4662 VL NO3 COM3 IN4 IN3 COM4 NO4 GND Pin Configurations/Functional Diagrams/Truth Tables Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. MAX4661/MAX4662/MAX4663 2.5W, Quad, SPST, CMOS Analog Switches 2 _______________________________________________________________________________________ ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. V+ to GND ..............................................................-0.3V to +44V V- to GND ..............................................................+0.3V to -44V V+ to V-...................................................................-0.3V to +44V VL to GND .......................................(GND - 0.3V) to (V+ + 0.3V) All Other Pins to GND (Note 1) .............(V- - 0.3V) to (V+ + 0.3V) Continuous Current (COM_, NO_, NC_) ........................±200mA Peak Current (COM_, NO_, NC_) (pulsed at 1ms, 10% duty cycle)................................ ±300mA Continuous Power Dissipation (TA = +70°C) SSOP (derate 7.1mW/°C above +70°C) .......................571mW Wide SO (derate 9.52mW/°C above +70°C).................762mW Plastic DIP (derate 10.53mW/°C above +70°C) ...........842mW Operating Temperature Ranges MAX466_C_E ......................................................0°C to +70°C MAX466_E_E ....................................................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10sec) .............................+300°C -5 5 -5 5 -20 20 TA = TMIN to TMAX V TA = +25°C V- V+ VCOM_, VNO_, VNC_ Input Voltage Range (Note 3) IN_ = 0.8V, all others = 2.4V IN_ = 2.4V, all others = 0.8V ICOM_ = 10mA, VNO_ or VNC_ = ±10V TA = +25°C TA = +25°C TA = +25°C CONDITIONS Logic Input Voltage Low VIN_L 0.8 ½ 0.1 0.5 ÆRON COM_ to NO_ or NC_ On-Resistance Match Between Channels (Notes 3, 4) ½ 1.7 2.5 RON COM_ to NO or NC_ On-Resistance Logic Input Voltage High VIN_H 2.4 V IIN_L -0.5 0.001 0.5 Input Current with Input Voltage Low IIN_H -0.5 0.001 0.5 μA Input Current with Input Voltage High ½ 0.1 0.5 RFLAT(ON) COM_ to NO_ or NC_ On-Resistance Flatness (Notes 3, 5) nA -0.5 0.01 0.5 INO_, INC_ Off-Leakage Current (NO_ or NC_) (Note 6) nA -0.5 0.01 0.5 ICOM_(OFF) COM Off-Leakage Current (Note 6) nA -1 0.01 1 ICOM_(ON) COM On-Leakage Current (Note 6) PARAMETER SYMBOL MIN TYP MAX UNITS ICOM_ = 10mA, VNO_ or VNC_= ±10V ICOM_ = 10mA; VNO_ or VNC_ = -5V, 0, 5V TA = +25°C VCOM_ = ±10V, VNO_ or VNC_= –+ 10V VCOM_ = ±10V, VNO_ or VNC_ = –+ 10V VCOM_ = ±10V, VNO_ or VNC_= ±10V or floating TA = +25°C TA = TMIN to TMAX 2.7 0.6 TA = TMIN to TMAX 0.6 TA = TMIN to TMAX TA = TMIN to TMAX TA = TMIN to TMAX ELECTRICAL CHARACTERISTICS—Dual Supplies (V+ = +15V, V- = -15V, VL = +5V, VIN_H = +2.4V, VIN_L = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) μA V ANALOG SWITCH LOGIC INPUT Note 1: Signals on NC_, NO_, COM_, or IN_ exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current rating. MAX4661/MAX4662/MAX4663 2.5W, Quad, SPST, CMOS Analog Switches _______________________________________________________________________________________ 3 VIN = 0 or 5V μA TA = +25°C -0.5 0.001 0.5 Positive Supply Current I+ TA = +25°C f = 1MHz, Figure 7 RL = 50½, CL = 5pF, f = 1MHz, Figure 6 TA = TMIN to TMAX -5 5 RL = 50½, CL = 5pF, f = 1MHz, Figure 5 VCOM_ = ±10V, Figure 3, TA = +25°C VIN = 0 or 5V TA = +25°C f = 1MHz, Figure 7 CONDITIONS Power-Supply Range ±4.5 ±20.0 V pF dB On-Capacitance CCOM f = 1MHz, Figure 8 250 pF COM_ Off-Capacitance CCOM 55 -0.5 0.001 0.5 Logic Supply Current IL -0.5 0.001 0.5 Negative Supply Current INC_ or NO_ Capacitance COFF pF Crosstalk (Note 8) VCT -59 Off-Isolation (Note 7) VISO -56 dB tOPEN 5 30 ns Break-Before-Make Time (MAX4663 only) -0.5 0.001 0.5 Ground Current IGND 130 275 100 175 PARAMETER SYMBOL MIN TYP MAX UNITS VIN = 0 or 5V VIN = 0 or 5V TA = +25°C TA = TMIN to TMAX -5 5 -5 5 TA = TMIN to TMAX -5 5 ELECTRICAL CHARACTERISTICS—Dual Supplies (continued) (V+ = +15V, V- = -15V, VL = +5V, VIN_H = +2.4V, VIN_L = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) μA μA μA TA = TMIN to TMAX 55 ns 400 Turn-On Time tON VCOM_ = ±10V, Figure 2 ns 300 Turn-Off Time tOFF VCOM_ = ±10V, Figure 2 CL = 1.0nF, VGEN = 0, RGEN = 0, Figure 4 Charge Injection Q 300 pC POWER SUPPLY SWITCH DYNAMIC CHARACTERISTICS TA = +25°C TA = TMIN to TMAX TA = +25°C TA = TMIN to TMAX MAX4661/MAX4662/MAX4663 2.5W, Quad, SPST, CMOS Analog Switches 4 _______________________________________________________________________________________ -5 5 -5 5 -20 20 TA = TMIN to TMAX V TA = +25°C GND V+ VCOM_, VNO_, VNC_ Input Voltage Range (Note 3) IN_ = 0.8V, all others = 2.4V +4.5 +36.0 IN_ = 2.4V, all others = 0.8V ICOM_ = 10mA, VNO_ or VNC_ = 10V TA = +25°C TA = +25°C TA = +25°C CONDITIONS Power-Supply Range VIN = 0 or 5V VIN = 0 or 5V -0.5 0.001 0.5 Logic Supply Current IL μA -0.5 0.001 0.5 Positive Supply Current I+ V μA VIN = 0 or 5V -0.5 0.001 0.5 Ground Current IGND μA TA = +25°C TA = +25°C TA = TMIN to TMAX TA = +25°C TA = TMIN to TMAX TA = TMIN to TMAX -5 5 -5 5 -5 5 Logic Input Voltage Low VIN_L 0.8 ½ 0.03 0.4 ÆRON COM_ to NO_ or NC_ On-Resistance Match Between Channels (Notes 3, 4) ½ 3 4 RON COM_ to NO or NC_ On-Resistance Logic Input Voltage High VIN_H 2.4 V IIN_L -0.5 0.001 0.5 Input Current with Input Voltage Low IIN_H -0.5 0.001 0.5 μA Input Current with Input Voltage High ½ 0.1 0.7 RFLAT(ON) COM_ to NO_ or NC_ On-Resistance Flatness (Notes 3, 5) nA I -0.5 0.01 0.5 NO_ INC_ Off-Leakage Current (NO_ or NC_) (Notes 6, 9) nA -0.5 0.01 0.5 ICOM_(OFF) COM Off-Leakage Current (Notes 6, 9) nA -1 0.01 1 ICOM_(ON) COM On-Leakage Current (Notes 6, 9) PARAMETER SYMBOL MIN TYP MAX UNITS ICOM_ = 10mA, VNO_ or = VNC_= 10V ICOM_ = 10mA; VNO_ or VNC_ = 3V, 6V, 9V TA = +25°C VCOM_ = 1V, 10V; VNO_ or VNC_ = 10V, 1V VNO_ or VNC_ = 10V, 1V; VCOM_ = 1V, 10V VCOM_ = 1V ,10V; VNO_ or VNC_ = 1V, 10V, or floating TA = +25°C TA = TMIN to TMAX 5 0.5 TA = TMIN to TMAX 0.8 TA = TMIN to TMAX TA = TMIN to TMAX TA = TMIN to TMAX ELECTRICAL CHARACTERISTICS—Single Supply (V+ = +12V, V- = 0, VL = +5V, VIN_H = +2.4V, VIN_L = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) μA V ANALOG SWITCH LOGIC INPUT POWER SUPPLY MAX4661/MAX4662/MAX4663 2.5W, Quad, SPST, CMOS Analog Switches _______________________________________________________________________________________ 5 ELECTRICAL CHARACTERISTICS—Single Supply (continued) (V+ = +12V, V- = 0, VL = +5V, VIN_H = +2.4V, VIN_L = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) Note 2: The algebraic convention, where the most negative value is a minimum and the most positive value a maximum, is used in this data sheet. Note 3: Guaranteed by design. Note 4: DRON = RON(MAX) - RON(MIN). Note 5: Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal range. Note 6: Leakage parameters are 100% tested at maximum-rated hot temperature and guaranteed by correlation at +25°C. Note 7: Off-isolation = 20log10 [VCOM / (VNC or VNO)], VCOM = output, VNC or VNO = input to off switch. Note 8: Between any two switches. Note 9: Leakage testing at single supply is guaranteed by testing with dual supplies. 200 400 On-Capacitance CCOM f = 1MHz, Figure 8 140 pF COM Off-Capacitance CCOM f = 1MHz, Figure 7 85 pF NC_ or NO_ Capacitance COFF f = 1MHz, Figure 7 85 pF RL = 50½, CL = 5pF, f = 1MHz, Figure 6 VCOM_ = 10V, Figure 3, TA = +25°C PARAMETER SYMBOL MIN TYP MAX UNITS Crosstalk (Note 8) VCT -60 dB Break-Before-Make Time (MAX4663 only) (Note 3) tOPEN 5 125 ns 100 250 CONDITIONS Turn-On Time (Note 3) tON 500 ns VCOM_ = 10V, Figure 2 VCOM_ = 10V, Figure 2 Turn-Off Time (Note 3) tOFF 350 ns TA = +25°C TA = TMIN to TMAX TA = +25°C TA = TMIN to TMAX CL = 1.0nF, VGEN = 0, RGEN = 0, Figure 4 Charge Injection Q 20 pC SWITCH DYNAMIC CHARACTERISTICS MAX4661/MAX4662/MAX4663 2.5W, Quad, SPST, CMOS Analog Switches 6 _______________________________________________________________________________________ Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) 0 1.0 0.5 2.0 1.5 3.0 2.5 3.5 4.5 4.0 5.0 -20 -15 -10 -5 0 5 10 15 20 ON-RESISTANCE vs. VCOM (DUAL SUPPLIES) MAX4661/2/3-01 VCOM (V) RON (W) V+, V- = ±5V V+, V- = ±15V V+, V- = ±20V 0 0.50 0.25 1.00 0.75 1.50 1.25 1.75 2.25 2.00 2.50 -15 -10 -5 0 5 10 15 ON-RESISTANCE vs. VCOM AND TEMPERATURE (DUAL SUPPLIES) MAX4661/2/3-02 VCOM (V) RON (W) TA = +85°C TA = +25°C V+, V- = ±15V TA = -40°C 0 3 2 1 4 5 6 7 8 9 10 0 2 4 6 8 10 12 14 16 18 20 22 24 ON-RESISTANCE vs. VCOM (SINGLE SUPPLY) MAX4661/2/3-03 VCOM (V) RON (W) V+ = 5V V+ = 12V V+ = 24V 0 1.50 1.00 0.50 2.00 2.50 3.50 3.00 4.00 0 1 2 3 4 5 6 7 8 9 10 11 12 ON-RESISTANCE vs. VCOM AND TEMPERATURE (SINGLE SUPPLY) MAX4661/2/3-04 VCOM (V) RON (W) TA = +85°C TA = +25°C TA = -40°C V+ = +12V V- = GND 0.1m 0.01 1m 10 1 0.1 1k 10k 100 100k -40 -20 0 20 40 60 80 100 ON/OFF-LEAKAGE CURRENT vs. TEMPERATURE MAX4661/2/3-05 TEMPERATURE (°C) LEAKAGE (pA) ON-LEAKAGE OFF-LEAKAGE V+ = +15V V- = -15V -200 0 -100 200 100 300 400 -20 -15 -10 -5 0 5 10 15 20 CHARGE INJECTION vs. VCOM MAX4661/2/3-06 VCOM (V) Q (pC) V- = -15V V+ = +15V V- = GND V+ = 12V 0.1 I+ I- 0.01 0.001 100 10 1 10k 100k 1k -40 -20 0 20 40 60 80 100 POWER-SUPPLY CURRENT vs. TEMPERATURE MAX4661/2/3-07 TEMPERATURE (°C) I+, I- (nA) V+ = +15V V- = -15V -10 -100 0.1 1 10 100 FREQUENCY RESPONSE -70 -90 -30 -50 0 -60 -80 -20 -40 MAX4661/2/3-08 FREQUENCY (MHz) LOSS (dB) 90 180 -720 -450 -630 -90 -270 -360 -540 -0 -180 PHASE (degrees) OFF-ISOLATION ON-PHASE ON-RESPONSE V+ = +15V V- = -15V INPUT = OdBm 50W IN AND OUT MAX4661/MAX4662/MAX4663 2.5W, Quad, SPST, CMOS Analog Switches _______________________________________________________________________________________ 7 NAME FUNCTION MAX4661 1, 16, 9, 8 IN1, IN2, IN3, IN4 Logic-Control Digital Inputs 2, 15, 10, 7 COM1, COM2, COM3, COM4 Analog Switch Common Terminals 3, 14, 11, 6 NC1, NC2, NC3, NC4 Analog Switch Normally Closed Terminals 4 VNegative Analog Supply-Voltage Input. Connect to GND for singlesupply operation. — NC2, NC3 Analog Switch Normally Closed Terminals — NO1, NO4 Analog Switch Normally Open Terminals — NO1, NO2, NO3, NO4 Analog Switch Normally Open Terminals 13 V+ Positive Analog Supply Input 12 VL Logic-Supply Input 5 GND Ground Pin Description MAX4662 1, 16, 9, 8 2, 15, 10, 7 — 4 — — 3, 14, 11, 6 13 12 5 MAX4663 1, 16, 9, 8 PIN 2, 15, 10, 7 — 4 14, 11 3, 6 — 13 12 5 Applications Information Overvoltage Protection Proper power-supply sequencing is recommended for all CMOS devices. Do not exceed the absolute maximum ratings because stresses beyond the listed ratings can cause permanent damage to the devices. Always sequence V+ on first, then V-, followed by the logic inputs, NO, or COM. If power-supply sequencing is not possible, add two small-signal diodes (D1, D2) in series with the supply pins and a Schottky diode between V+ and VL for overvoltage protection (Figure 1). Adding diodes reduces the analog signal range to one diode drop below V+ and one diode drop above V-, but does not affect the devices’ low switch resistance and low leakage characteristics. Device operation is unchanged, and the difference between V+ and Vshould not exceed 44V. Off-Isolation at High Frequencies In 50½ systems, the high-frequency on-response of these parts extends from DC to above 100MHz with a typical loss of -2dB. When the switch is turned off, however, it behaves like a capacitor and off-isolation decreases with increasing frequency. (Above 300MHz, the switch actually passes more signal turned off than turned on.) This effect is more pronounced with higher source and load impedances. Above 5MHz, circuit board layout becomes critical and it becomes difficult to characterize the response of the switch independent of the circuit. The graphs shown in the Typical Operating Characteristics were taken using a 50½ source and load connected with BNC connectors to a circuit board deemed “average”; that is, designed with isolation in mind, but not using stripline or other special RF circuit techniques. For critical applications above 5MHz, use the MAX440, MAX441, and MAX442, which are fully characterized up to 160MHz. COM_ VV+ VL NO_ * INTERNAL PROTECTION DIODES D2 D1 -15V +15V MAX4661 MAX4662 MAX4663 * * * * Figure 1. Overvoltage Protection Using External Blocking Diodes MAX4661/MAX4662/MAX4663 2.5W, Quad, SPST, CMOS Analog Switches 8 _______________________________________________________________________________________ 50% 0.9 · V0UT1 +3V 0V 0V LOGIC INPUT SWITCH OUTPUT 2 (VOUT2) 0V 0.9 · VOUT2 tD tD LOGIC INPUT V- -15V RL2 GND CL INCLUDES FIXTURE AND STRAY CAPACITANCE. COM2 IN1, 2 COM1 VOUT2 V+ +15V CL2 VCOM1 RL1 VOUT1 CL1 RL = 100W CL = 35pF NO NC SWITCH OUTPUT 1 (VOUT1) MAX4663 VCOM2 Figure 3. Break-Before-Make Interval (MAX4663 only) tr < 20ns tf < 20ns 50% 0 LOGIC INPUT V- -15V RL 100W NO_ OR NC_ GND CL INCLUDES FIXTURE AND STRAY CAPACITANCE. VO = VCOM ( RL RL + RON) SWITCH INPUT IN_ +3V tOFF 0 COM_ SWITCH OUTPUT 0.9V0 0.9V0 tON VO SWITCH OUTPUT LOGIC INPUT LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES THAT HAVE THE OPPOSITE LOGIC SENSE. VL V+ CL 35pF +5V +15V VCOM_ VO 0 REPEAT TEST FOR EACH SWITCH. FOR LOAD CONDITIONS, SEE Electrical Characteristics. MAX4661 MAX4662 MAX4663 Figure 2. Switching-Time Test Circuit MAX4661/MAX4662/MAX4663 2.5W, Quad, SPST, CMOS Analog Switches _______________________________________________________________________________________ 9 VGEN GND NC OR NO CL VO -15V VV+ VO VIN OFF ON OFF DVO Q = (DVO)(CL) COM +5V VIN DEPENDS ON SWITCH CONFIGURATION; INPUT POLARITY DETERMINED BY SENSE OF SWITCH. OFF ON OFF VIN VIN = +3V +15V RGEN IN VL MAX4661 MAX4662 MAX4663 Figure 4. Charge-Injection Test Circuit IN 0 OR 3.0V SIGNAL GENERATOR 0dBm +15V VL ANALYZER NC OR NO RL GND COM -15V V- +5V COM V+ MAX4661 MAX4662 MAX4663 Figure 5. Off-Isolation Test Circuit SIGNAL GENERATOR 0dBm +15V ANALYZER N_2 RL GND COM1 V- -15V 3.0V IN1 N_1 VL 50W COM2 +5V IN2 0 OR 3.0V N.C. V+ MAX4661 MAX4662 MAX4663 Figure 6. Crosstalk Test Circuit MAX4661/MAX4662/MAX4663 2.5W, Quad, SPST, CMOS Analog Switches 10 ______________________________________________________________________________________ CAPACITANCE METER NC OR NO COM GND V- -15V IN 0 OR 3.0V +15V VL +5V f = 1MHz V+ MAX4661 MAX4662 MAX4663 Figure 7. Switch Off-Capacitance Test Circuit CAPACITANCE METER NC OR NO COM GND V- -15V IN 0 OR 3.0V +15V VL +5V f = 1MHz V+ MAX4661 MAX4662 MAX4663 Figure 8. Switch On-Capacitance Test Circuit Chip Information TRANSISTOR COUNT: 108 Ordering Information (continued) PART TEMP. RANGE PIN-PACKAGE MAX4662CAE 0°C to +70°C 16 SSOP MAX4662CWE 0°C to +70°C 16 Wide SO MAX4662CPE 0°C to +70°C 16 Plastic DIP MAX4662EAE -40°C to +85°C 16 SSOP MAX4662EWE -40°C to +85°C 16 Wide SO MAX4662EPE -40°C to +85°C 16 Plastic DIP MAX4663CAE 0°C to +70°C 16 SSOP MAX4663CWE 0°C to +70°C 16 Wide SO MAX4663CPE 0°C to +70°C 16 Plastic DIP MAX4663EAE -40°C to +85°C 16 SSOP MAX4663EWE -40°C to +85°C 16 Wide SO MAX4663EPE -40°C to +85°C 16 Plastic DIP MAX4661/MAX4662/MAX4663 2.5W, Quad, SPST, CMOS Analog Switches ______________________________________________________________________________________ 11 Package Information SSOP.EPS MAX4661/MAX4662/MAX46663 2.5W, Quad, SPST, CMOS Analog Switches Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. Package Information (continued) SOICW.EPS Copyright © 2010 Future Technology Devices International Limited 1 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Future Technology Devices International Ltd. FT232R USB UART IC The FT232R is a USB to serial UART interface with the following advanced features: Single chip USB to asynchronous serial data transfer interface. Entire USB protocol handled on the chip. No USB specific firmware programming required. Fully integrated 1024 bit EEPROM storing device descriptors and CBUS I/O configuration. Fully integrated USB termination resistors. Fully integrated clock generation with no external crystal required plus optional clock output selection enabling a glue-less interface to external MCU or FPGA. Data transfer rates from 300 baud to 3 Mbaud (RS422, RS485, RS232 ) at TTL levels. 128 byte receive buffer and 256 byte transmit buffer utilising buffer smoothing technology to allow for high data throughput. FTDI‟s royalty-free Virtual Com Port (VCP) and Direct (D2XX) drivers eliminate the requirement for USB driver development in most cases. Unique USB FTDIChip-ID™ feature. Configurable CBUS I/O pins. Transmit and receive LED drive signals. UART interface support for 7 or 8 data bits, 1 or 2 stop bits and odd / even / mark / space / no parity FIFO receive and transmit buffers for high data throughput. Synchronous and asynchronous bit bang interface options with RD# and WR# strobes. Device supplied pre-programmed with unique USB serial number. Supports bus powered, self powered and high-power bus powered USB configurations. Integrated +3.3V level converter for USB I/O. Integrated level converter on UART and CBUS for interfacing to between +1.8V and +5V logic. True 5V/3.3V/2.8V/1.8V CMOS drive output and TTL input. Configurable I/O pin output drive strength. Integrated power-on-reset circuit. Fully integrated AVCC supply filtering - no external filtering required. UART signal inversion option. +3.3V (using external oscillator) to +5.25V (internal oscillator) Single Supply Operation. Low operating and USB suspend current. Low USB bandwidth consumption. UHCI/OHCI/EHCI host controller compatible. USB 2.0 Full Speed compatible. -40°C to 85°C extended operating temperature range. Available in compact Pb-free 28 Pin SSOP and QFN-32 packages (both RoHS compliant). Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. Future Technology Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product. Your statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminary information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by the publication of this document. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow G41 1HH United Kingdom. Scotland Registered Company Number: SC136640 Copyright © 2010 Future Technology Devices International Limited 2 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 1 Typical Applications USB to RS232/RS422/RS485 Converters Upgrading Legacy Peripherals to USB Cellular and Cordless Phone USB data transfer cables and interfaces Interfacing MCU/PLD/FPGA based designs to USB USB Audio and Low Bandwidth Video data transfer PDA to USB data transfer USB Smart Card Readers USB Instrumentation USB Industrial Control USB MP3 Player Interface USB FLASH Card Reader and Writers Set Top Box PC - USB interface USB Digital Camera Interface USB Hardware Modems USB Wireless Modems USB Bar Code Readers USB Software and Hardware Encryption Dongles 1.1 Driver Support Royalty free VIRTUAL COM PORT (VCP) DRIVERS for... Windows 98, 98SE, ME, 2000, Server 2003, XP and Server 2008 Windows 7 32,64-bit Windows XP and XP 64-bit Windows Vista and Vista 64-bit Windows XP Embedded Windows CE 4.2, 5.0 and 6.0 Mac OS 8/9, OS-X Linux 2.4 and greater Royalty free D2XX Direct Drivers (USB Drivers + DLL S/W Interface) Windows 98, 98SE, ME, 2000, Server 2003, XP and Server 2008 Windows 7 32,64-bit Windows XP and XP 64-bit Windows Vista and Vista 64-bit Windows XP Embedded Windows CE 4.2, 5.0 and 6.0 Linux 2.4 and greater The drivers listed above are all available to download for free from FTDI website (www.ftdichip.com). Various 3rd party drivers are also available for other operating systems - see FTDI website (www.ftdichip.com) for details. For driver installation, please refer to http://www.ftdichip.com/Documents/InstallGuides.htm 1.2 Part Numbers Part Number Package FT232RQ-xxxx 32 Pin QFN FT232RL-xxxx 28 Pin SSOP Note: Packing codes for xxxx is: - Reel: Taped and Reel, (SSOP is 2,000pcs per reel, QFN is 6,000pcs per reel). - Tube: Tube packing, 47pcs per tube (SSOP only) - Tray: Tray packing, 490pcs per tray (QFN only) For example: FT232RQ-Reel is 6,000pcs taped and reel packing Copyright © 2010 Future Technology Devices International Limited 3 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 1.3 USB Compliant The FT232R is fully compliant with the USB 2.0 specification and has been given the USB-IF Test-ID (TID) 40680004 (Rev B) and 40770018 (Rev C). Copyright © 2010 Future Technology Devices International Limited 4 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 2 FT232R Block Diagram Figure 2.1 FT232R Block Diagram For a description of each function please refer to Section 4. x4 ClockMultiplierUARTFIFO ControllerSerial InterfaceEngine( SIE )USBProtocol EngineBaud RateGeneratorUART ControllerwithProgrammableSignal Inversion3.3 VoltLDORegulatorUSBTransceiverwithIntegratedSeriesResistorsand 1.5KPull-upUSB DPLLInternal12MHzOscillator48MHz48MHzOCSI(optional)OSCO(optional)USBDPUSBDM3V3OUTVCCDBUS0DBUS1DBUS2DBUS3DBUS4DBUS5DBUS6DBUS7CBUS0CBUS2CBUS3SLEEP#RESET#TESTGNDResetGenerator3V3OUTCBUS1FIFO RX BufferFIFO TX BufferInternalEEPROMTo USB Transeiver CellCBUS4 Copyright © 2010 Future Technology Devices International Limited 5 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Table of Contents 1 Typical Applications ........................................................................ 2 1.1 Driver Support .................................................................................... 2 1.2 Part Numbers...................................................................................... 2 Note: Packing codes for xxxx is: .................................................................. 2 1.3 USB Compliant .................................................................................... 3 2 FT232R Block Diagram .................................................................... 4 3 Device Pin Out and Signal Description ............................................ 7 3.1 28-LD SSOP Package .......................................................................... 7 3.2 SSOP Package Pin Out Description ...................................................... 7 3.3 QFN-32 Package ............................................................................... 10 3.4 QFN-32 Package Signal Description .................................................. 10 3.5 CBUS Signal Options ......................................................................... 13 4 Function Description ..................................................................... 14 4.1 Key Features ..................................................................................... 14 4.2 Functional Block Descriptions ........................................................... 15 5 Devices Characteristics and Ratings .............................................. 17 5.1 Absolute Maximum Ratings............................................................... 17 5.2 DC Characteristics............................................................................. 18 5.3 EEPROM Reliability Characteristics ................................................... 21 5.4 Internal Clock Characteristics ........................................................... 21 6 USB Power Configurations ............................................................ 23 6.1 USB Bus Powered Configuration ...................................................... 23 6.2 Self Powered Configuration .............................................................. 24 6.3 USB Bus Powered with Power Switching Configuration .................... 25 6.4 USB Bus Powered with Selectable External Logic Supply .................. 26 7 Application Examples .................................................................... 27 7.1 USB to RS232 Converter ................................................................... 27 7.2 USB to RS485 Coverter ..................................................................... 28 7.3 USB to RS422 Converter ................................................................... 29 7.4 USB to MCU UART Interface .............................................................. 30 7.5 LED Interface .................................................................................... 31 7.6 Using the External Oscillator ............................................................ 32 8 Internal EEPROM Configuration .................................................... 33 9 Package Parameters ..................................................................... 35 9.1 SSOP-28 Package Dimensions .......................................................... 35 Copyright © 2010 Future Technology Devices International Limited 6 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 9.2 QFN-32 Package Dimensions ............................................................ 36 9.3 QFN-32 Package Typical Pad Layout ................................................. 37 9.4 QFN-32 Package Typical Solder Paste Diagram ................................. 37 9.5 Solder Reflow Profile ........................................................................ 38 10 Contact Information ................................................................... 39 Appendix A – References ........................................................................... 40 Appendix B - List of Figures and Tables ..................................................... 41 Appendix C - Revision History .................................................................... 43 Copyright © 2010 Future Technology Devices International Limited 7 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 3 Device Pin Out and Signal Description 3.1 28-LD SSOP Package Figure 3.1 SSOP Package Pin Out and Schematic Symbol 3.2 SSOP Package Pin Out Description Note: The convention used throughout this document for active low signals is the signal name followed by a # Pin No. Name Type Description 15 USBDP I/O USB Data Signal Plus, incorporating internal series resistor and 1.5kΩ pull up resistor to 3.3V. 16 USBDM I/O USB Data Signal Minus, incorporating internal series resistor. Table 3.1 USB Interface Group Pin No. Name Type Description 4 VCCIO PWR +1.8V to +5.25V supply to the UART Interface and CBUS group pins (1...3, 5, 6, 9...14, 22, 23). In USB bus powered designs connect this pin to 3V3OUT pin to drive out at +3.3V levels, or connect to VCC to drive out at 5V CMOS level. This pin can also be supplied with an external +1.8V to +2.8V supply in order to drive outputs at lower levels. It should be noted that in this case this supply should originate from the same source as the supply to VCC. This means that in bus powered designs a regulator which is supplied by the +5V on the USB bus should be used. 7, 18, 21 GND PWR Device ground supply pins USBDPUSBDM3V3OUTGNDRESET#VCCGNDNCAGNDTESTOSCIOSCOCBUS1CBUS0TXDRTS#RXDDTR#VCCIORI#GNDNCDSR#DCD#CTS#CBUS4CBUS2CBUS31141528FT232RLAGNDGNDGNDGNDTEST2571821263V3OUTVCCIO417NCRESET#NC24198TXDRXDRTS#CTS#DTR#DSR#DCD#RI#1531129106CBUS0CBUS3CBUS2CBUS123221314201615USBDPUSBDMVCCOSCI27OSCO28CBUS412FTDIFT232RLYYXX-AXXXXXXXXXXXX Copyright © 2010 Future Technology Devices International Limited 8 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Pin No. Name Type Description 17 3V3OUT Output +3.3V output from integrated LDO regulator. This pin should be decoupled to ground using a 100nF capacitor. The main use of this pin is to provide the internal +3.3V supply to the USB transceiver cell and the internal 1.5kΩ pull up resistor on USBDP. Up to 50mA can be drawn from this pin to power external logic if required. This pin can also be used to supply the VCCIO pin. 20 VCC PWR +3.3V to +5.25V supply to the device core. (see Note 1) 25 AGND PWR Device analogue ground supply for internal clock multiplier Table 3.2 Power and Ground Group Pin No. Name Type Description 8, 24 NC NC No internal connection 19 RESET# Input Active low reset pin. This can be used by an external device to reset the FT232R. If not required can be left unconnected, or pulled up to VCC. 26 TEST Input Puts the device into IC test mode. Must be tied to GND for normal operation, otherwise the device will appear to fail. 27 OSCI Input Input 12MHz Oscillator Cell. Optional – Can be left unconnected for normal operation. (see Note 2) 28 OSCO Output Output from 12MHZ Oscillator Cell. Optional – Can be left unconnected for normal operation if internal Oscillator is used. (see Note 2) Table 3.3 Miscellaneous Signal Group Pin No. Name Type Description 1 TXD Output Transmit Asynchronous Data Output. 2 DTR# Output Data Terminal Ready Control Output / Handshake Signal. 3 RTS# Output Request to Send Control Output / Handshake Signal. 5 RXD Input Receiving Asynchronous Data Input. 6 RI# Input Ring Indicator Control Input. When remote wake up is enabled in the internal EEPROM taking RI# low (20ms active low pulse) can be used to resume the PC USB host controller from suspend. 9 DSR# Input Data Set Ready Control Input / Handshake Signal. 10 DCD# Input Data Carrier Detect Control Input. 11 CTS# Input Clear To Send Control Input / Handshake Signal. 12 CBUS4 I/O Configurable CBUS output only Pin. Function of this pin is configured in the device internal EEPROM. Factory default configuration is SLEEP#. See CBUS Signal Options, Table 3.9. 13 CBUS2 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory default configuration is TXDEN. See CBUS Signal Options, Table 3.9. Copyright © 2010 Future Technology Devices International Limited 9 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Pin No. Name Type Description 14 CBUS3 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory default configuration is PWREN#. See CBUS Signal Options, Table 3.9. PWREN# should be used with a 10kΩ resistor pull up. 22 CBUS1 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory default configuration is RXLED#. See CBUS Signal Options, Table 3.9. 23 CBUS0 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory default configuration is TXLED#. See CBUS Signal Options, Table 3.9. Table 3.4 UART Interface and CUSB Group (see note 3) Notes: 1. The minimum operating voltage VCC must be +4.0V (could use VBUS=+5V) when using the internal clock generator. Operation at +3.3V is possible using an external crystal oscillator. 2. For details on how to use an external crystal, ceramic resonator, or oscillator with the FT232R, please refer Section 7.6 3. When used in Input Mode, the input pins are pulled to VCCIO via internal 200kΩ resistors. These pins can be programmed to gently pull low during USB suspend (PWREN# = “1”) by setting an option in the internal EEPROM. Copyright © 2010 Future Technology Devices International Limited 10 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 3.3 QFN-32 Package Figure 3.2 QFN-32 Package Pin Out and schematic symbol 3.4 QFN-32 Package Signal Description Pin No. Name Type Description 14 USBDP I/O USB Data Signal Plus, incorporating internal series resistor and 1.5kΩ pull up resistor to +3.3V. 15 USBDM I/O USB Data Signal Minus, incorporating internal series resistor. Table 3.5 USB Interface Group Pin No. Name Type Description 1 VCCIO PWR +1.8V to +5.25V supply for the UART Interface and CBUS group pins (2, 3, 6,7,8,9,10 11, 21, 22, 30,31,32). In USB bus powered designs connect this pin to 3V3OUT to drive out at +3.3V levels, or connect to VCC to drive out at +5V CMOS level. This pin can also be supplied with an external +1.8V to +2.8V supply in order to drive out at lower levels. It should be noted that in this case this supply should originate from the same source as the supply to VCC. This means that in bus powered designs a regulator which is supplied by the +5V on the USB bus should be used. 4, 17, 20 GND PWR Device ground supply pins. FT232RQ3225241716981YYXX-A1891234567810111213141516171920212223242526272829303132USBDPUSBDM3V3OUTRESET#VCCNCAGNDTESTOSCIOSCOCBUS1CBUS0TXDRTS#RXDDTR#VCCIORI#GNDNCDSR#DCD#CTS#CBUS4CBUS2CBUS3GNDGNDNCNCNCNCIFT232RQAGNDGNDGNDGNDTEST2441720263V3OUTVCCIO116NCRESET#NC231813TXDRXDRTS#CTS#DTR#DSR#DCD#RI#30232831673CBUS0CBUS3CBUS2CBUS122211011191514USBDPUSBDMVCCOSCI27OSCO28CBUS49NC12NC5NC29NC25FTDXXXXXXX Copyright © 2010 Future Technology Devices International Limited 11 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Pin No. Name Type Description 16 3V3OUT Output +3.3V output from integrated LDO regulator. This pin should be decoupled to ground using a 100nF capacitor. The purpose of this output is to provide the internal +3.3V supply to the USB transceiver cell and the internal 1.5kΩ pull up resistor on USBDP. Up to 50mA can be drawn from this pin to power external logic if required. This pin can also be used to supply the VCCIO pin. 19 VCC PWR +3.3V to +5.25V supply to the device core. (See Note 1). 24 AGND PWR Device analogue ground supply for internal clock multiplier. Table 3.6 Power and Ground Group Pin No. Name Type Description 5, 12, 13, 23, 25, 29 NC NC No internal connection. Do not connect. 18 RESET# Input Active low reset. Can be used by an external device to reset the FT232R. If not required can be left unconnected, or pulled up to VCC. 26 TEST Input Puts the device into IC test mode. Must be tied to GND for normal operation, otherwise the device will appear to fail. 27 OSCI Input Input 12MHz Oscillator Cell. Optional – Can be left unconnected for normal operation. (See Note 2). 28 OSCO Output Output from 12MHZ Oscillator Cell. Optional – Can be left unconnected for normal operation if internal Oscillator is used. (See Note 2). Table 3.7 Miscellaneous Signal Group Pin No. Name Type Description 30 TXD Output Transmit Asynchronous Data Output. 31 DTR# Output Data Terminal Ready Control Output / Handshake Signal. 32 RTS# Output Request to Send Control Output / Handshake Signal. 2 RXD Input Receiving Asynchronous Data Input. 3 RI# Input Ring Indicator Control Input. When remote wake up is enabled in the internal EEPROM taking RI# low (20ms active low pulse) can be used to resume the PC USB host controller from suspend. 6 DSR# Input Data Set Ready Control Input / Handshake Signal. 7 DCD# Input Data Carrier Detect Control Input. 8 CTS# Input Clear To Send Control Input / Handshake Signal. 9 CBUS4 I/O Configurable CBUS output only Pin. Function of this pin is configured in the device internal EEPROM. Factory default configuration is SLEEP#. See CBUS Signal Options, Table 3.9. 10 CBUS2 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory default configuration is TXDEN. See CBUS Signal Options, Table 3.9. Copyright © 2010 Future Technology Devices International Limited 12 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Pin No. Name Type Description 11 CBUS3 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory default configuration is PWREN#. See CBUS Signal Options, Table 3.9. PWREN# should be used with a 10kΩ resistor pull up. 21 CBUS1 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory default configuration is RXLED#. See CBUS Signal Options, Table 3.9. 22 CBUS0 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory default configuration is TXLED#. See CBUS Signal Options, Table 3.9. Table 3.8 UART Interface and CBUS Group (see note 3) Notes: 1. The minimum operating voltage VCC must be +4.0V (could use VBUS=+5V) when using the internal clock generator. Operation at +3.3V is possible using an external crystal oscillator. 2. For details on how to use an external crystal, ceramic resonator, or oscillator with the FT232R, please refer to Section 7.6. 3. When used in Input Mode, the input pins are pulled to VCCIO via internal 200kΩ resistors. These pins can be programmed to gently pull low during USB suspend (PWREN# = “1”) by setting an option in the internal EEPROM. Copyright © 2010 Future Technology Devices International Limited 13 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 3.5 CBUS Signal Options The following options can be configured on the CBUS I/O pins. CBUS signal options are common to both package versions of the FT232R. These options can be configured in the internal EEPROM using the software utility FT_PPROG or MPROG, which can be downloaded from the FTDI Utilities (www.ftdichip.com). The default configuration is described in Section 8. CBUS Signal Option Available On CBUS Pin Description TXDEN CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 Enable transmit data for RS485 PWREN# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 Output is low after the device has been configured by USB, then high during USB suspend mode. This output can be used to control power to external logic P-Channel logic level MOSFET switch. Enable the interface pull-down option when using the PWREN# in this way.* TXLED# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 Transmit data LED drive: Data from USB Host to FT232R. Pulses low when transmitting data via USB. See Section 7.5 for more details. RXLED# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 Receive data LED drive: Data from FT232R to USB Host. Pulses low when receiving data via USB. See Section 7.5 for more details. TX&RXLED# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 LED drive – pulses low when transmitting or receiving data via USB. See Section 7.5 for more details. SLEEP# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 Goes low during USB suspend mode. Typically used to power down an external TTL to RS232 level converter IC in USB to RS232 converter designs. CLK48 CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 48MHz ±0.7% Clock output. ** CLK24 CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 24 MHz Clock output.** CLK12 CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 12 MHz Clock output.** CLK6 CBUS0, CBUS1, CBUS2, CBUS3, CBUS4 6 MHz ±0.7% Clock output. ** CBitBangI/O CBUS0, CBUS1, CBUS2, CBUS3 CBUS bit bang mode option. Allows up to 4 of the CBUS pins to be used as general purpose I/O. Configured individually for CBUS0, CBUS1, CBUS2 and CBUS3 in the internal EEPROM. A separate application note, AN232R-01, available from FTDI website (www.ftdichip.com) describes in more detail how to use CBUS bit bang mode. BitBangWRn CBUS0, CBUS1, CBUS2, CBUS3 Synchronous and asynchronous bit bang mode WR# strobe output. BitBangRDn CBUS0, CBUS1, CBUS2, CBUS3 Synchronous and asynchronous bit bang mode RD# strobe output. Table 3.9 CBUS Configuration Control * PWREN# must be used with a 10kΩ resistor pull up. **When in USB suspend mode the outputs clocks are also suspended. Copyright © 2010 Future Technology Devices International Limited 14 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 4 Function Description The FT232R is a USB to serial UART interface device which simplifies USB to serial designs and reduces external component count by fully integrating an external EEPROM, USB termination resistors and an integrated clock circuit which requires no external crystal, into the device. It has been designed to operate efficiently with a USB host controller by using as little as possible of the total USB bandwidth available. 4.1 Key Features Functional Integration. Fully integrated EEPROM, USB termination resistors, clock generation, AVCC filtering, POR and LDO regulator. Configurable CBUS I/O Pin Options. The fully integrated EEPROM allows configuration of the Control Bus (CBUS) functionality, signal inversion and drive strength selection. There are 5 configurable CBUS I/O pins. These configurable options are 1. TXDEN - transmit enable for RS485 designs. 2. PWREN# - Power control for high power, bus powered designs. 3. TXLED# - for pulsing an LED upon transmission of data. 4. RXLED# - for pulsing an LED upon receiving data. 5. TX&RXLED# - which will pulse an LED upon transmission OR reception of data. 6. SLEEP# - indicates that the device going into USB suspend mode. 7. CLK48 / CLK24 / CLK12 / CLK6 - 48MHz, 24MHz, 12MHz, and 6MHz clock output signal options. The CBUS pins can also be individually configured as GPIO pins, similar to asynchronous bit bang mode. It is possible to use this mode while the UART interface is being used, thus providing up to 4 general purpose I/O pins which are available during normal operation. An application note, AN232R-01, available from FTDI website (www.ftdichip.com) describes this feature. The CBUS lines can be configured with any one of these output options by setting bits in the internal EEPROM. The device is supplied with the most commonly used pin definitions pre-programmed - see Section 8 for details. Asynchronous Bit Bang Mode with RD# and WR# Strobes. The FT232R supports FTDI‟s previous chip generation bit-bang mode. In bit-bang mode, the eight UART lines can be switched from the regular interface mode to an 8-bit general purpose I/O port. Data packets can be sent to the device and they will be sequentially sent to the interface at a rate controlled by an internal timer (equivalent to the baud rate pre-scaler). With the FT232R device this mode has been enhanced by outputting the internal RD# and WR# strobes signals which can be used to allow external logic to be clocked by accesses to the bit-bang I/O bus. This option will be described more fully in a separate application note available from FTDI website (www.ftdichip.com). Synchronous Bit Bang Mode. The FT232R supports synchronous bit bang mode. This mode differs from asynchronous bit bang mode in that the interface pins are only read when the device is written to. This makes it easier for the controlling program to measure the response to an output stimulus as the data returned is synchronous to the output data. An application note, AN232R-01, available from FTDI website (www.ftdichip.com) describes this feature. FTDIChip-ID™. The FT232R also includes the new FTDIChip-ID™ security dongle feature. This FTDIChip-ID™ feature allows a unique number to be burnt into each device during manufacture. This number cannot be reprogrammed. This number is only readable over USB and forms a basis of a security dongle which can be used to protect any customer application software being copied. This allows the possibility of using the FT232R in a dongle for software licensing. Further to this, a renewable license scheme can be implemented based on the FTDIChip-ID™ number when encrypted with other information. This encrypted number can be stored in the user area of the FT232R internal EEPROM, and can be decrypted, then compared with the protected FTDIChip-ID™ to verify that a license is valid. Web based applications can be used to maintain product licensing this way. An application note, AN232R-02, available from FTDI website (www.ftdichip.com) describes this feature. The FT232R is capable of operating at a voltage supply between +3.3V and +5V with a nominal operational mode current of 15mA and a nominal USB suspend mode current of 70μA. This allows greater margin for peripheral designs to meet the USB suspend mode current limit of 2.5mA. An integrated level converter within the UART interface allows the FT232R to interface to UART logic running at +1.8V, 2.5V, +3.3V or +5V. Copyright © 2010 Future Technology Devices International Limited 15 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 4.2 Functional Block Descriptions The following paragraphs detail each function within the FT232R. Please refer to the block diagram shown in Figure 2.1 Internal EEPROM. The internal EEPROM in the FT232R is used to store USB Vendor ID (VID), Product ID (PID), device serial number, product description string and various other USB configuration descriptors. The internal EEPROM is also used to configure the CBUS pin functions. The FT232R is supplied with the internal EEPROM pre-programmed as described in Section 8. A user area of the internal EEPROM is available to system designers to allow storing additional data. The internal EEPROM descriptors can be programmed in circuit, over USB without any additional voltage requirement. It can be programmed using the FTDI utility software called MPROG, which can be downloaded from FTDI Utilities on the FTDI website (www.ftdichip.com). +3.3V LDO Regulator. The +3.3V LDO regulator generates the +3.3V reference voltage for driving the USB transceiver cell output buffers. It requires an external decoupling capacitor to be attached to the 3V3OUT regulator output pin. It also provides +3.3V power to the 1.5kΩ internal pull up resistor on USBDP. The main function of the LDO is to power the USB Transceiver and the Reset Generator Cells rather than to power external logic. However, it can be used to supply external circuitry requiring a +3.3V nominal supply with a maximum current of 50mA. USB Transceiver. The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface to the USB cable. The output drivers provide +3.3V level slew rate control signalling, whilst a differential input receiver and two single ended input receivers provide USB data in, Single-Ended-0 (SE0) and USB reset detection conditions respectfully. This function also incorporates the internal USB series termination resistors on the USB data lines and a 1.5kΩ pull up resistor on USBDP. USB DPLL. The USB DPLL cell locks on to the incoming NRZI USB data and generates recovered clock and data signals for the Serial Interface Engine (SIE) block. Internal 12MHz Oscillator - The Internal 12MHz Oscillator cell generates a 12MHz reference clock. This provides an input to the x4 Clock Multiplier function. The 12MHz Oscillator is also used as the reference clock for the SIE, USB Protocol Engine and UART FIFO controller blocks. Clock Multiplier / Divider. The Clock Multiplier / Divider takes the 12MHz input from the Internal Oscillator function and generates the 48MHz, 24MHz, 12MHz and 6MHz reference clock signals. The 48Mz clock reference is used by the USB DPLL and the Baud Rate Generator blocks. Serial Interface Engine (SIE). The Serial Interface Engine (SIE) block performs the parallel to serial and serial to parallel conversion of the USB data. In accordance with the USB 2.0 specification, it performs bit stuffing/un-stuffing and CRC5/CRC16 generation. It also checks the CRC on the USB data stream. USB Protocol Engine. The USB Protocol Engine manages the data stream from the device USB control endpoint. It handles the low level USB protocol requests generated by the USB host controller and the commands for controlling the functional parameters of the UART in accordance with the USB 2.0 specification chapter 9. FIFO RX Buffer (128 bytes). Data sent from the USB host controller to the UART via the USB data OUT endpoint is stored in the FIFO RX (receive) buffer. Data is removed from the buffer to the UART transmit register under control of the UART FIFO controller. (Rx relative to the USB interface). FIFO TX Buffer (256 bytes). Data from the UART receive register is stored in the TX buffer. The USB host controller removes data from the FIFO TX Buffer by sending a USB request for data from the device data IN endpoint. (Tx relative to the USB interface). UART FIFO Controller. The UART FIFO controller handles the transfer of data between the FIFO RX and TX buffers and the UART transmit and receive registers. UART Controller with Programmable Signal Inversion and High Drive. Together with the UART FIFO Controller the UART Controller handles the transfer of data between the FIFO RX and FIFO TX buffers and the UART transmit and receive registers. It performs asynchronous 7 or 8 bit parallel to serial and serial to parallel conversion of the data on the RS232 (or RS422 or RS485) interface. Control signals supported by UART mode include RTS, CTS, DSR, DTR, DCD and RI. The UART Controller also provides a transmitter enable control signal pin option (TXDEN) to assist with interfacing to RS485 transceivers. RTS/CTS, DSR/DTR and XON / XOFF handshaking options are also supported. Handshaking is handled in hardware to ensure fast response times. The UART interface also supports the RS232 BREAK setting and detection conditions. Copyright © 2010 Future Technology Devices International Limited 16 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Additionally, the UART signals can each be individually inverted and have a configurable high drive strength capability. Both these features are configurable in the EEPROM. Baud Rate Generator - The Baud Rate Generator provides a 16x clock input to the UART Controller from the 48MHz reference clock. It consists of a 14 bit pre-scaler and 3 register bits which provide fine tuning of the baud rate (used to divide by a number plus a fraction or “sub-integer”). This determines the baud rate of the UART, which is programmable from 183 baud to 3 Mbaud. The FT232R supports all standard baud rates and non-standard baud rates from 183 Baud up to 3 Mbaud. Achievable non-standard baud rates are calculated as follows - Baud Rate = 3000000 / (n + x) where „n‟ can be any integer between 2 and 16,384 ( = 214 ) and „x’ can be a sub-integer of the value 0, 0.125, 0.25, 0.375, 0.5, 0.625, 0.75, or 0.875. When n = 1, x = 0, i.e. baud rate divisors with values between 1 and 2 are not possible. This gives achievable baud rates in the range 183.1 baud to 3,000,000 baud. When a non-standard baud rate is required simply pass the required baud rate value to the driver as normal, and the FTDI driver will calculate the required divisor, and set the baud rate. See FTDI application note AN232B-05 on the FTDI website (www.ftdichip.com) for more details. RESET Generator - The integrated Reset Generator Cell provides a reliable power-on reset to the device internal circuitry at power up. The RESET# input pin allows an external device to reset the FT232R. RESET# can be tied to VCC or left unconnected if not being used. Copyright © 2010 Future Technology Devices International Limited 17 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 5 Devices Characteristics and Ratings 5.1 Absolute Maximum Ratings The absolute maximum ratings for the FT232R devices are as follows. These are in accordance with the Absolute Maximum Rating System (IEC 60134). Exceeding these may cause permanent damage to the device. Parameter Value Unit Storage Temperature -65°C to 150°C Degrees C Floor Life (Out of Bag) At Factory Ambient (30°C / 60% Relative Humidity) 168 Hours (IPC/JEDEC J-STD-033A MSL Level 3 Compliant)* Hours Ambient Temperature (Power Applied) -40°C to 85°C Degrees C MTTF FT232RL 11162037 hours MTTF FT232RQ 4464815 hours VCC Supply Voltage -0.5 to +6.00 V DC Input Voltage – USBDP and USBDM -0.5 to +3.8 V DC Input Voltage – High Impedance Bidirectionals -0.5 to + (VCC +0.5) V DC Input Voltage – All Other Inputs -0.5 to + (VCC +0.5) V DC Output Current – Outputs 24 mA DC Output Current – Low Impedance Bidirectionals 24 mA Power Dissipation (VCC = 5.25V) 500 mW Table 5.1 Absolute Maximum Ratings * If devices are stored out of the packaging beyond this time limit the devices should be baked before use. The devices should be ramped up to a temperature of +125°C and baked for up to 17 hours. Copyright © 2010 Future Technology Devices International Limited 18 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 5.2 DC Characteristics DC Characteristics (Ambient Temperature = -40°C to +85°C) Parameter Description Minimum Typical Maximum Units Conditions VCC1 VCC Operating Supply Voltage 4.0 --- 5.25 V Using Internal Oscillator VCC1 VCC Operating Supply Voltage 3.3 --- 5.25 V Using External Crystal VCC2 VCCIO Operating Supply Voltage 1.8 --- 5.25 V Icc1 Operating Supply Current --- 15 --- mA Normal Operation Icc2 Operating Supply Current 50 70 100 μA USB Suspend 3V3 3.3v regulator output 3.0 3.3 3.6 V Table 5.2 Operating Voltage and Current Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 3.2 4.1 4.9 V I source = 2mA Vol Output Voltage Low 0.3 0.4 0.6 V I sink = 2mA Vin Input Switching Threshold 1.0 1.2 1.5 V ** VHys Input Switching Hysteresis 20 25 30 mV ** Table 5.3 UART and CBUS I/O Pin Characteristics (VCCIO = +5.0V, Standard Drive Level) Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 2.2 2.7 3.2 V I source = 1mA Vol Output Voltage Low 0.3 0.4 0.5 V I sink = 2mA Vin Input Switching Threshold 1.0 1.2 1.5 V ** VHys Input Switching Hysteresis 20 25 30 mV ** Table 5.4 UART and CBUS I/O Pin Characteristics (VCCIO = +3.3V, Standard Drive Level) Copyright © 2010 Future Technology Devices International Limited 19 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 2.1 2.6 2.8 V I source = 1mA Vol Output Voltage Low 0.3 0.4 0.5 V I sink = 2mA Vin Input Switching Threshold 1.0 1.2 1.5 V ** VHys Input Switching Hysteresis 20 25 30 mV ** Table 5.5 UART and CBUS I/O Pin Characteristics (VCCIO = +2.8V, Standard Drive Level) Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 1.32 1.62 1.8 V I source = 0.2mA Vol Output Voltage Low 0.06 0.1 0.18 V I sink = 0.5mA Vin Input Switching Threshold 1.0 1.2 1.5 V ** VHys Input Switching Hysteresis 20 25 30 mV ** Table 5.6 UART and CBUS I/O Pin Characteristics (VCCIO = +1.8V, Standard Drive Level) Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 3.2 4.1 4.9 V I source = 6mA Vol Output Voltage Low 0.3 0.4 0.6 V I sink = 6mA Vin Input Switching Threshold 1.0 1.2 1.5 V ** VHys Input Switching Hysteresis 20 25 30 mV ** Table 5.7 UART and CBUS I/O Pin Characteristics (VCCIO = +5.0V, High Drive Level) Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 2.2 2.8 3.2 V I source = 3mA Vol Output Voltage Low 0.3 0.4 0.6 V I sink = 8mA Vin Input Switching Threshold 1.0 1.2 1.5 V ** VHys Input Switching Hysteresis 20 25 30 mV ** Table 5.8 UART and CBUS I/O Pin Characteristics (VCCIO = +3.3V, High Drive Level) Copyright © 2010 Future Technology Devices International Limited 20 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 2.1 2.6 2.8 V I source = 3mA Vol Output Voltage Low 0.3 0.4 0.6 V I sink = 8mA Vin Input Switching Threshold 1.0 1.2 1.5 V ** VHys Input Switching Hysteresis 20 25 30 mV ** Table 5.9 UART and CBUS I/O Pin Characteristics (VCCIO = +2.8V, High Drive Level) Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 1.35 1.67 1.8 V I source = 0.4mA Vol Output Voltage Low 0.12 0.18 0.35 V I sink = 3mA Vin Input Switching Threshold 1.0 1.2 1.5 V ** VHys Input Switching Hysteresis 20 25 30 mV ** Table 5.10 UART and CBUS I/O Pin Characteristics (VCCIO = +1.8V, High Drive Level) ** Only input pins have an internal 200KΩ pull-up resistor to VCCIO Parameter Description Minimum Typical Maximum Units Conditions Vin Input Switching Threshold 1.3 1.6 1.9 V VHys Input Switching Hysteresis 50 55 60 mV Table 5.11 RESET# and TEST Pin Characteristics Copyright © 2010 Future Technology Devices International Limited 21 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Parameter Description Minimum Typical Maximum Units Conditions UVoh I/O Pins Static Output (High) 2.8 3.6 V RI = 1.5kΩ to 3V3OUT (D+) RI = 15KΩ to GND (D-) UVol I/O Pins Static Output (Low) 0 0.3 V RI = 1.5kΩ to 3V3OUT (D+) RI = 15kΩ to GND (D-) UVse Single Ended Rx Threshold 0.8 2.0 V UCom Differential Common Mode 0.8 2.5 V UVDif Differential Input Sensitivity 0.2 V UDrvZ Driver Output Impedance 26 29 44 Ohms See Note 1 Table 5.12 USB I/O Pin (USBDP, USBDM) Characteristics 5.3 EEPROM Reliability Characteristics The internal 1024 Bit EEPROM has the following reliability characteristics: Parameter Value Unit Data Retention 10 Years Read / Write Cycle 10,000 Cycles Table 5.13 EEPROM Characteristics 5.4 Internal Clock Characteristics The internal Clock Oscillator has the following characteristics: Parameter Value Unit Minimum Typical Maximum Frequency of Operation (see Note 1) 11.98 12.00 12.02 MHz Clock Period 83.19 83.33 83.47 ns Duty Cycle 45 50 55 % Table 5.14 Internal Clock Characteristics Note 1: Equivalent to +/-1667ppm Copyright © 2010 Future Technology Devices International Limited 22 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 2.1 2.8 3.2 V I source = 3mA Vol Output Voltage Low 0.3 0.4 0.6 V I sink = 8mA Vin Input Switching Threshold 1.0 1.2 1.5 V Table 5.15 OSCI, OSCO Pin Characteristics – see Note 1 Note1: When supplied, the FT232R is configured to use its internal clock oscillator. These characteristics only apply when an external oscillator or crystal is used. Copyright © 2010 Future Technology Devices International Limited 23 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 6 USB Power Configurations The following sections illustrate possible USB power configurations for the FT232R. The illustrations have omitted pin numbers for ease of understanding since the pins differ between the FT232RL and FT232RQ package options. All USB power configurations illustrated apply to both package options for the FT232R device. Please refer to Section 3 for the package option pin-out and signal descriptions. 6.1 USB Bus Powered Configuration Figure 6.1 Bus Powered Configuration Figure 6.1 Illustrates the FT232R in a typical USB bus powered design configuration. A USB bus powered device gets its power from the USB bus. Basic rules for USB bus power devices are as follows – i) On plug-in to USB, the device should draw no more current than 100mA. ii) In USB Suspend mode the device should draw no more than 2.5mA. iii) A bus powered high power USB device (one that draws more than 100mA) should use one of the CBUS pins configured as PWREN# and use it to keep the current below 100mA on plug-in and 2.5mA on USB suspend. iv) A device that consumes more than 100mA cannot be plugged into a USB bus powered hub. v) No device can draw more than 500mA from the USB bus. The power descriptors in the internal EEPROM of the FT232R should be programmed to match the current drawn by the device. A ferrite bead is connected in series with the USB power supply to reduce EMI noise from the FT232R and associated circuitry being radiated down the USB cable to the USB host. The value of the Ferrite Bead depends on the total current drawn by the application. A suitable range of Ferrite Beads is available from Steward (www.steward.com), for example Steward Part # MI0805K400R-10. Note: If using PWREN# (available using the CBUS) the pin should be pulled to VCCIO using a 10kΩ resistor. FT232RAGNDGNDGNDGNDTEST100nF3V3OUTVCCIONCRESET#NC+100nF10nFVccTXDRXDRTS#CTS#DTR#DSR#DCD#RI#CBUS0CBUS3CBUS2CBUS1USBDPUSBDMVCC12345OSCIOSCOCBUS4FerriteBead+4.7uFSHIELDGNDGNDGNDGNDVcc Copyright © 2010 Future Technology Devices International Limited 24 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 6.2 Self Powered Configuration Figure 6.2 Self Powered Configuration Figure 6.2 illustrates the FT232R in a typical USB self powered configuration. A USB self powered device gets its power from its own power supply, VCC, and does not draw current from the USB bus. The basic rules for USB self powered devices are as follows – i) A self powered device should not force current down the USB bus when the USB host or hub controller is powered down. ii) A self powered device can use as much current as it needs during normal operation and USB suspend as it has its own power supply. iii) A self powered device can be used with any USB host, a bus powered USB hub or a self powered USB hub. The power descriptor in the internal EEPROM of the FT232R should be programmed to a value of zero (self powered). In order to comply with the first requirement above, the USB bus power (pin 1) is used to control the RESET# pin of the FT232R device. When the USB host or hub is powered up an internal 1.5kΩ resistor on USBDP is pulled up to +3.3V (generated using the 4K7 and 10k resistor network), thus identifying the device as a full speed device to the USB host or hub. When the USB host or hub is powered off, RESET# will be low and the FT232R is held in reset. Since RESET# is low, the internal 1.5kΩ resistor is not pulled up to any power supply (hub or host is powered down), so no current flows down USBDP via the 1.5kΩ pull-up resistor. Failure to do this may cause some USB host or hub controllers to power up erratically. Figure 6.2 illustrates a self powered design which has a +4V to +5.25V supply. Note: 1. When the FT232R is in reset, the UART interface I/O pins are tri-stated. Input pins have internal 200kΩ pull-up resistors to VCCIO, so they will gently pull high unless driven by some external logic. 2. When using internal FT232R oscillator the VCC supply voltage range must be +4.0V to 5.25V. 3. When using external oscillator the VCC supply voltage range must be +3.3V to 5.25V Any design which interfaces to +3.3 V or +1.8V would be having a +3.3V or +1.8V supply to VCCIO. Copyright © 2010 Future Technology Devices International Limited 25 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 6.3 USB Bus Powered with Power Switching Configuration FT232R GND GND 100nF VCC USBDM USBDP VCCIO NC RESET# NC OSCI OSCO 3V3OUT A G N D G N D G N D G N D T E S T TXD RXD RTS# CTS# DTR# DSR# DCD# RI# CBUS0 CBUS1 CBUS2 CBUS3 CBUS4 1 2 3 4 GND SHIELD GND 100nF 4.7uF + 5 10nF + Ferrite Bead s d g P-Channel Power MOSFET PWREN# 1K Switched 5V Power To External Logic Soft Start Circuit 0.1uF 0.1uF 5V VCC 5V VCC 5V VCC 10K Figure 6.3 Bus Powered with Power Switching Configuration A requirement of USB bus powered applications, is when in USB suspend mode, the application draws a total current of less than 2.5mA. This requirement includes external logic. Some external logic has the ability to power itself down into a low current state by monitoring the PWREN# signal. For external logic that cannot power itself down in this way, the FT232R provides a simple but effective method of turning off power during the USB suspend mode. Figure 6.3 shows an example of using a discrete P-Channel MOSFET to control the power to external logic. A suitable device to do this is an International Rectifier (www.irf.com) IRLML6402, or equivalent. It is recommended that a “soft start” circuit consisting of a 1kΩ series resistor and a 0.1μF capacitor is used to limit the current surge when the MOSFET turns on. Without the soft start circuit it is possible that the transient power surge, caused when the MOSFET switches on, will reset the FT232R or the USB host/hub controller. The soft start circuit example shown in Figure 6.3 powers up with a slew rate of approximaely12.5V/ms. Thus supply voltage to external logic transitions from GND to +5V in approximately 400 microseconds. As an alternative to the MOSFET, a dedicated power switch IC with inbuilt “soft-start” can be used. A suitable power switch IC for such an application is the Micrel (www.micrel.com) MIC2025-2BM or equivalent. With power switching controlled designs the following should be noted: i) The external logic to which the power is being switched should have its own reset circuitry to automatically reset the logic when power is re-applied when moving out of suspend mode. ii) Set the Pull-down on Suspend option in the internal FT232R EEPROM. iii) One of the CBUS Pins should be configured as PWREN# in the internal FT232R EEPROM, and used to switch the power supply to the external circuitry. This should be pulled high through a 10 kΩ resistor. iv) For USB high-power bus powered applications (one that consumes greater than 100mA, and up to 500mA of current from the USB bus), the power consumption of the application must be set in the Max Power field in the internal FT232R EEPROM. A high-power bus powered application uses the descriptor in the internal FT232R EEPROM to inform the system of its power requirements. v) PWREN# gets its VCC from VCCIO. For designs using 3V3 logic, ensure VCCIO is not powered down using the external logic. In this case use the +3V3OUT. Copyright © 2010 Future Technology Devices International Limited 26 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 6.4 USB Bus Powered with Selectable External Logic Supply FT232R A G N D G N D G N D G N D T E S T 100nF 3V3OUT VCCIO NC RESET# NC 10nF TXD RXD RTS# CTS# DTR# DSR# DCD# RI# CBUS0 CBUS3 CBUS2 CBUS1 USBDP USBDM 1 VCC 2 3 4 5 OSCI OSCO CBUS4 Ferrite Bead + SHIELD GND GND GND 3.3V or 5V Supply to External Logic 100nF + 100nF Vcc 4.7uF GND 1 Jumper SLEEP# PWREN# 2 3 Vcc VCCIO 10K VCCIO Figure 6.4 USB Bus Powered with +3.3V or +5V External Logic Power Supply Figure 6.4 illustrates a USB bus power application with selectable external logic supply. The external logic can be selected between +3.3V and +5V using the jumper switch. This jumper is used to allow the FT232R to be interfaced with a +3.3V or +5V logic devices. The VCCIO pin is either supplied with +5V from the USB bus (jumper pins1 and 2 connected), or from the +3.3V output from the FT232R 3V3OUT pin (jumper pins 2 and 3 connected). The supply to VCCIO is also used to supply external logic. With bus powered applications, the following should be noted: i) To comply with the 2.5mA current supply limit during USB suspend mode, PWREN# or SLEEP# signals should be used to power down external logic in this mode. If this is not possible, use the configuration shown in Section 6.3. ii) The maximum current sourced from the USB bus during normal operation should not exceed 100mA, otherwise a bus powered design with power switching (Section 6.3) should be used. Another possible configuration could use a discrete low dropout (LDO) regulator which is supplied by the 5V on the USB bus to supply between +1.8V and +2.8V to the VCCIO pin and to the external logic. In this case VCC would be supplied with the +5V from the USB bus and the VCCIO would be supplied from the output of the LDO regulator. This results in the FT232R I/O pins driving out at between +1.8V and +2.8V logic levels. For a USB bus powered application, it is important to consider the following when selecting the regulator: i) The regulator must be capable of sustaining its output voltage with an input voltage of +4.35V. An Low Drop Out (LDO) regulator should be selected. ii) The quiescent current of the regulator must be low enough to meet the total current requirement of <= 2.5mA during USB suspend mode. A suitable series of LDO regulators that meets these requirements is the MicroChip/Telcom (www.microchip.com) TC55 series of devices. These devices can supply up to 250mA current and have a quiescent current of under 1μA. Copyright © 2010 Future Technology Devices International Limited 27 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 7 Application Examples The following sections illustrate possible applications of the FT232R. The illustrations have omitted pin numbers for ease of understanding since the pins differ between the FT232RL and FT232RQ package options. 7.1 USB to RS232 Converter FT232R GND GND 100nF VCC USBDM USBDP VCCIO NC RESET# NC OSCI OSCO 3V3OUT A G N D G N D G N D G N D T E S T TXD RXD RTS# CTS# DTR# DSR# DCD# RI# CBUS0 CBUS1 CBUS2 CBUS3 CBUS4 1 2 3 4 GND SHIELD GND 100nF 4.7uF + 5 10nF + Ferrite Bead VCC VCC SLEEP# GPIO2 GPIO3 TXD RXD RTS# CTS# DTR# DSR# DCD# RI# RS232 LEVEL CONVERTER TXDATA RXDATA RTS CTS DTR DSR DCD RI TXLED# RXLED# VCC VCC 270R 270R GND RI DTR CTS TXDATA RTS RXDATA DSR DCD DB9M SHIELD 10 5 9 48 3 7 2 6 1 SHDN# Figure 7.1 Application Example showing USB to RS232 Converter An example of using the FT232R as a USB to RS232 converter is illustrated in Figure 7.1. In this application, a TTL to RS232 Level Converter IC is used on the serial UART interface of the FT232R to convert the TTL levels of the FT232R to RS232 levels. This level shift can be done using the popular “213” series of TTL to RS232 level converters. These “213” devices typically have 4 transmitters and 5 receivers in a 28-LD SSOP package and feature an in-built voltage converter to convert the +5V (nominal) VCC to the +/- 9 volts required by RS232. A useful feature of these devices is the SHDN# pin which can be used to power down the device to a low quiescent current during USB suspend mode. A suitable level shifting device is the Sipex SP213EHCA which is capable of RS232 communication at up to 500k baud. If a lower baud rate is acceptable, then several pin compatible alternatives are available such as the Sipex SP213ECA, the Maxim MAX213CAI and the Analogue Devices ADM213E, which are all suitable for communication at up to 115.2k baud. If a higher baud rate is required, the Maxim MAX3245CAI device is capable of RS232 communication rates up to 1Mbaud. Note that the MAX3245 is not pin compatible with the 213 series devices and that the SHDN pin on the MAX device is active high and should be connect to PWREN# pin instead of SLEEP# pin. In example shown, the CBUS0 and CBUS1 have been configured as TXLED# and RXLED# and are being used to drive two LEDs. Copyright © 2010 Future Technology Devices International Limited 28 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 7.2 USB to RS485 Coverter FT232R GND GND 100nF VCC USBDM USBDP VCCIO NC RESET# NC OSCI OSCO 3V3OUT A G N D G N D G N D G N D T E S T TXD RXD RTS# CTS# DTR# DSR# DCD# RI# CBUS0 CBUS1 CBUS2 CBUS3 CBUS4 1 2 3 4 GND SHIELD GND 100nF 4.7uF + 5 10nF + Ferrite Bead Vcc Vcc TXD RXD GND DB9M SHIELD 10 TXDEN GPO PWREN# GPIO0 GPIO1 VCCIO 10K RS485 LEVEL CONVERTER Vcc SP481 5 1 2 3 4 Link 120R 7 6 Figure 7.2 Application Example Showing USB to RS485 Converter An example of using the FT232R as a USB to RS485 converter is shown in Figure 7.2. In this application, a TTL to RS485 level converter IC is used on the serial UART interface of the FT232R to convert the TTL levels of the FT232R to RS485 levels. This example uses the Sipex SP481 device. Equivalent devices are available from Maxim and Analogue Devices. The SP481 is a RS485 device in a compact 8 pin SOP package. It has separate enables on both the transmitter and receiver. With RS485, the transmitter is only enabled when a character is being transmitted from the UART. The TXDEN signal CBUS pin option on the FT232R is provided for exactly this purpose and so the transmitter enable is wired to CBUS2 which has been configured as TXDEN. Similarly, CBUS3 has been configured as PWREN#. This signal is used to control the SP481‟s receiver enable. The receiver enable is active low, so it is wired to the PWREN# pin to disable the receiver when in USB suspend mode. CBUS2 = TXDEN and CBUS3 = PWREN# are the default device configurations of the FT232R pins. RS485 is a multi-drop network; so many devices can communicate with each other over a two wire cable interface. The RS485 cable requires to be terminated at each end of the cable. A link (which provides the 120Ω termination) allows the cable to be terminated if the SP481 is physically positioned at either end of the cable. In this example the data transmitted by the FT232R is also present on the receive path of the SP481.This is a common feature of RS485 and requires the application software to remove the transmitted data from the received data stream. With the FT232R it is possible to do this entirely in hardware by modifying the example shown in Figure 7.2 by logically OR‟ing the FT232R TXDEN and the SP481 receiver output and connecting the output of the OR gate to the RXD of the FT232R. Note that the TXDEN is activated 1 bit period before the start bit. TXDEN is deactivated at the same time as the stop bit. This is not configurable. Copyright © 2010 Future Technology Devices International Limited 29 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 7.3 USB to RS422 Converter FT232R GND GND 100nF VCC USBDM USBDP VCCIO NC RESET# NC OSCI OSCO 3V3OUT A G N D G N D G N D G N D T E S T TXD RXD RTS# CTS# DTR# DSR# DCD# RI# CBUS0 CBUS1 CBUS2 CBUS3 CBUS4- 1 2 3 4 GND SHIELD GND 100nF 4.7uF + 5 10nF + Ferrite Bead Vcc Vcc PWREN# RS422 LEVEL CONVERTER Vcc SP491 5 3 4 6 7 TXDM TXDP RXDP RXDM 120R 10 9 11 12 SLEEP# RS422 LEVEL CONVERTER SP491 3 4 6 7 Vcc Vcc 10K 2 5 120R 11 12 9 10 RTSM RTSP CTSP CTSM GND DB9M SHIELD TXDM TXDP RXDP RXDM RTSM RTSP CTSP CTSM 2 Figure 7.3 USB to RS422 Converter Configuration An example of using the FT232R as a USB to RS422 converter is shown in Figure 7.3. In this application, two TTL to RS422 Level Converter ICs are used on the serial UART interface of the FT232R to convert the TTL levels of the FT232R to RS422 levels. There are many suitable level converter devices available. This example uses Sipex SP491 devices which have enables on both the transmitter and receiver. Since the SP491 transmitter enable is active high, it is connected to a CBUS pin in SLEEP# configuration. The SP491 receiver enable is active low and is therefore connected to a CBUS pin PWREN# configuration. This ensures that when both the SP491 transmitters and receivers are enabled then the device is active, and when the device is in USB suspend mode, the SP491 transmitters and receivers are disabled. If a similar application is used, but the design is USB BUS powered, it may be necessary to use a P-Channel logic level MOSFET (controlled by PWREN#) in the VCC line of the SP491 devices to ensure that the USB standby current of 2.5mA is met. The SP491 is specified to transmit and receive data at a rate of up to 5 Mbaud. In this example the maximum data rate is limited to 3 Mbaud by the FT232R. Copyright © 2010 Future Technology Devices International Limited 30 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 7.4 USB to MCU UART Interface FT232R GND GND 100nF VCC USBDM USBDP VCCIO NC RESET# NC OSCI OSCO 3V3OUT A G N D G N D G N D G N D T E S T TXD RXD RTS# CTS# DTR# DSR# DCD# RI# CBUS0 CBUS1 CBUS2 CBUS3 CBUS4 1 2 3 4 GND SHIELD GND 100nF 4.7uF + 5 10nF + Ferrite Bead Vcc Vcc PWREN# Vcc 12MHz OUT 10K Microcontroller CLK_IN I/O RTS# RXD TXD CTS# Vcc Figure 7.4 USB to MCU UART Interface An example of using the FT232R as a USB to Microcontroller (MCU) UART interface is shown in Figure 7.4. In this application the FT232R uses TXD and RXD for transmission and reception of data, and RTS# / CTS# signals for hardware handshaking. Also in this example CBUS0 has been configured as a 12MHz output to clock the MCU. Optionally, RI# could be connected to another I/O pin on the MCU and used to wake up the USB host controller from suspend mode. If the MCU is handling power management functions, then a CBUS pin can be configured as PWREN# and would also be connected to an I/O pin of the MCU. Copyright © 2010 Future Technology Devices International Limited 31 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 7.5 LED Interface Any of the CBUS I/O pins can be configured to drive an LED. The FT232R has 3 configuration options for driving LEDs from the CBUS. These are TXLED#, RXLED#, and TX&RXLED#. Refer to Section 3.5 for configuration options. FT232R CBUS[0...4] CBUS[0...4] VCCIO TX TXLED# RXLED# RX 270R 270R Figure 7.5 Dual LED Configuration An example of using the FT232R to drive LEDs is shown in Figure 7.5. In this application one of the CBUS pins is used to indicate transmission of data (TXLED#) and another is used to indicate receiving data (RXLED#). When data is being transmitted or received the respective pins will drive from tri-state to low in order to provide indication on the LEDs of data transfer. A digital one-shot is used so that even a small percentage of data transfer is visible to the end user. FT232R CBUS[0...4] TX&RXLED# 270R VCCIO LED Figure 7.6 Single LED Configuration Another example of using the FT232R to drive LEDs is shown in Figure 7.6. In this example one of the CBUS pins is used to indicate when data is being transmitted or received by the device (TX&RXLED). In this configuration the FT232R will drive only a single LED. Copyright © 2010 Future Technology Devices International Limited 32 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 7.6 Using the External Oscillator The FT232R defaults to operating using its own internal oscillator. This requires that the device is powered with VCC(min)=+4.0V. This supply voltage can be taken from the USB VBUS. Applications which require using an external oscillator, VCC= +3.3V, must do so in the following order: 1. When device powered for the very first time, it must have VCC > +4.0V. This supply is available from the USB VBUS supply = +5.0V. 2. The EEPROM must then be programmed to enable external oscillator. This EEPROM modification cannot be done using the FTDI programming utility, MPROG. The EEPROM can only be re-configured from a custom application. Please refer to the following applications note on how to do this: http://www.ftdichip.com/Documents/AppNotes/AN_100_Using_The_FT232_245R_With_External_Osc(FT_000067).pdf 3. The FT232R can then be powered from VCC=+3.3V and an external oscillator. This can be done using a link to switch the VCC supply. The FT232R will fail to operate when the internal oscillator has been disabled, but no external oscillator has been connected. Copyright © 2010 Future Technology Devices International Limited 33 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 8 Internal EEPROM Configuration Following a power-on reset or a USB reset the FT232R will scan its internal EEPROM and read the USB configuration descriptors stored there. The default factory programmed values of the internal EEPROM are shown in Table 8.1. Parameter Value Notes USB Vendor ID (VID) 0403h FTDI default VID (hex) USB Product UD (PID) 6001h FTDI default PID (hex) Serial Number Enabled? Yes Serial Number See Note A unique serial number is generated and programmed into the EEPROM during device final test. Pull down I/O Pins in USB Suspend Disabled Enabling this option will make the device pull down on the UART interface lines when in USB suspend mode (PWREN# is high). Manufacturer Name FTDI Product Description FT232R USB UART Max Bus Power Current 90mA Power Source Bus Powered Device Type FT232R USB Version 0200 Returns USB 2.0 device description to the host. Note: The device is a USB 2.0 Full Speed device (12Mb/s) as opposed to a USB 2.0 High Speed device (480Mb/s). Remote Wake Up Enabled Taking RI# low will wake up the USB host controller from suspend in approximately 20 ms. High Current I/Os Disabled Enables the high drive level on the UART and CBUS I/O pins. Load VCP Driver Enabled Makes the device load the VCP driver interface for the device. CBUS0 TXLED# Default configuration of CBUS0 – Transmit LED drive. CBUS1 RXLED# Default configuration of CBUS1 – Receive LED drive. CBUS2 TXDEN Default configuration of CBUS2 – Transmit data enable for RS485 CBUS3 PWREN# Default configuration of CBUS3 – Power enable. Low after USB enumeration, high during USB suspend mode. Copyright © 2010 Future Technology Devices International Limited 34 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Parameter Value Notes CBUS4 SLEEP# Default configuration of CBUS4 – Low during USB suspend mode. Invert TXD Disabled Signal on this pin becomes TXD# if enable. Invert RXD Disabled Signal on this pin becomes RXD# if enable. Invert RTS# Disabled Signal on this pin becomes RTS if enable. Invert CTS# Disabled Signal on this pin becomes CTS if enable. Invert DTR# Disabled Signal on this pin becomes DTR if enable. Invert DSR# Disabled Signal on this pin becomes DSR if enable. Invert DCD# Disabled Signal on this pin becomes DCD if enable. Invert RI# Disabled Signal on this pin becomes RI if enable. Table 8.1 Default Internal EEPROM Configuration The internal EEPROM in the FT232R can be programmed over USB using the FTDI utility program MPROG. MPROG can be downloaded from FTDI Utilities on the FTDI website (www.ftdichip.com). Version 2.8a or later is required for the FT232R chip. Users who do not have their own USB Vendor ID but who would like to use a unique Product ID in their design can apply to FTDI for a free block of unique PIDs. Contact FTDI support for this service. Copyright © 2010 Future Technology Devices International Limited 35 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 9 Package Parameters The FT232R is available in two different packages. The FT232RL is the SSOP-28 option and the FT232RQ is the QFN-32 package option. The solder reflow profile for both packages is described in Section 9.5. 9.1 SSOP-28 Package Dimensions Figure 9.1 SSOP-28 Package Dimensions The FT232RL is supplied in a RoHS compliant 28 pin SSOP package. The package is lead (Pb) free and uses a „green‟ compound. The package is fully compliant with European Union directive 2002/95/EC. This package is nominally 5.30mm x 10.20mm body (7.80mm x 10.20mm including pins). The pins are on a 0.65 mm pitch. The above mechanical drawing shows the SSOP-28 package. All dimensions are in millimetres. The date code format is YYXX where XX = 2 digit week number, YY = 2 digit year number. This is followed by the revision number. The code XXXXXXXXXXXX is the manufacturing LOT code. This only applies to devices manufactured after April 2009. 12° Typ0° - 8°0.25 0.75 +/-0.200.092.00 Max1.75+/- 0.100.05 Min1.25 +/-0.12FT232RLYYXX-A1141528FTDI5.30 +/-0.307.80 +/-0.40 10.20 +/-0.301.02 Typ.0.30 +/-0.0120.65 +/-0.026XXXXXXXXXXXX Copyright © 2010 Future Technology Devices International Limited 36 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 9.2 QFN-32 Package Dimensions Figure 9.2 QFN-32 Package Dimensions The FT232RQ is supplied in a RoHS compliant leadless QFN-32 package. The package is lead ( Pb ) free, and uses a „green‟ compound. The package is fully compliant with European Union directive 2002/95/EC. This package is nominally 5.00mm x 5.00mm. The solder pads are on a 0.50mm pitch. The above mechanical drawing shows the QFN-32 package. All dimensions are in millimetres. The centre pad on the base of the FT232RQ is not internally connected, and can be left unconnected, or connected to ground (recommended). The date code format is YYXX where XX = 2 digit week number, YY = 2 digit year number. The code XXXXXXX is the manufacturing LOT code. This only applies to devices manufactured after April 2009. Indicates Pin #1 (Laser Marked)FT232RQ3225241716981YYXX-A5.000 +/-0.0755.000 +/-0.0753.200 +/-0.1003.200 +/-0.1000.5000.250 +/-0.0500.500 +/-0.0500.150 MaxPin #1 ID0.900 +/-0.1000.200 0.0502134567823242221201918172526272829303132161514131211109Note: The pin #1 ID is connected internally to the device’s central heat sink area . It is recommended to ground the central heat sink area of the device. 0.200 MinDimensions in mm.Central Heat Sink AreaFTDIXXXXXXX Copyright © 2010 Future Technology Devices International Limited 37 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 9.3 QFN-32 Package Typical Pad Layout Figure 9.3 Typical Pad Layout for QFN-32 Package 9.4 QFN-32 Package Typical Solder Paste Diagram 2.5 +/- 0.0375 2.5 +/- 0.0375 Figure 9.4 Typical Solder Paste Diagram for QFN-32 Package 1 17 25 0.500 0.30 0.200 Min 0.500 +/-0.050 0.150 Max 0.20 0.100 3.200 +/-0.100 3.200 +/-0.100 2.50 2.50 Optional GND Connection Optional GND Connection 9 Copyright © 2010 Future Technology Devices International Limited 38 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 9.5 Solder Reflow Profile The FT232R is supplied in Pb free 28 LD SSOP and QFN-32 packages. The recommended solder reflow profile for both package options is shown in Figure 9.5. Figure 9.5 FT232R Solder Reflow Profile The recommended values for the solder reflow profile are detailed in Table 9.1. Values are shown for both a completely Pb free solder process (i.e. the FT232R is used with Pb free solder), and for a non-Pb free solder process (i.e. the FT232R is used with non-Pb free solder). Profile Feature Pb Free Solder Process Non-Pb Free Solder Process Average Ramp Up Rate (Ts to Tp) 3°C / second Max. 3°C / Second Max. Preheat - Temperature Min (Ts Min.) - Temperature Max (Ts Max.) - Time (ts Min to ts Max) 150°C 200°C 60 to 120 seconds 100°C 150°C 60 to 120 seconds Time Maintained Above Critical Temperature TL: - Temperature (TL) - Time (tL) 217°C 60 to 150 seconds 183°C 60 to 150 seconds Peak Temperature (Tp) 260°C 240°C Time within 5°C of actual Peak Temperature (tp) 20 to 40 seconds 20 to 40 seconds Ramp Down Rate 6°C / second Max. 6°C / second Max. Time for T= 25°C to Peak Temperature, Tp 8 minutes Max. 6 minutes Max. Table 9.1 Reflow Profile Parameter Values Critical Zone: whenT is in the rangeT to TTemperature, T ( Degrees C)Time, t (seconds)25PT = 25º C to TtpTpTLtPreheatStLRamp UpLpRampDownT MaxST MinS Copyright © 2010 Future Technology Devices International Limited 39 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 10 Contact Information Head Office – Glasgow, UK Future Technology Devices International Limited Unit 1, 2 Seaward Place Centurion Business Park Glasgow, G41 1HH United Kingdom Tel: +44 (0) 141 429 2777 Fax: +44 (0) 141 429 2758 E-mail (Sales) sales1@ftdichip.com E-mail (Support) support1@ftdichip.com E-mail (General Enquiries) admin1@ftdichip.com Web Site URL http://www.ftdichip.com Web Shop URL http://www.ftdichip.com Branch Office – Taipei, Taiwan Future Technology Devices International Limited (Taiwan) 2F, No 516, Sec. 1 NeiHu Road Taipei 114 Taiwan, R.O.C. Tel: +886 (0) 2 8791 3570 Fax: +886 (0) 2 8791 3576 E-mail (Sales) tw.sales1@ftdichip.com E-mail (Support) tw.support1@ftdichip.com E-mail (General Enquiries) tw.admin1@ftdichip.com Web Site URL http://www.ftdichip.com Branch Office – Hillsboro, Oregon, USA Future Technology Devices International Limited (USA) 7235 NW Evergreen Parkway, Suite 600 Hillsboro, OR 97123-5803 USA Tel: +1 (503) 547 0988 Fax: +1 (503) 547 0987 E-Mail (Sales) us.sales@ftdichip.com E-Mail (Support) us.admin@ftdichip.com Web Site URL http://www.ftdichip.com Branch Office – Shanghai, China Future Technology Devices International Limited (China) Room 408, 317 Xianxia Road, ChangNing District, ShangHai, China Tel: +86 (21) 62351596 Fax: +86(21) 62351595 E-Mail (Sales): cn.sales@ftdichip.com E-Mail (Support): cn.support@ftdichip.com E-Mail (General Enquiries): cn.admin1@ftdichip.com Web Site URL: http://www.ftdichip.com Distributor and Sales Representatives Please visit the Sales Network page of the FTDI Web site for the contact details of our distributor(s) and sales representative(s) in your country. Copyright © 2010 Future Technology Devices International Limited 40 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Appendix A – References Useful Application Notes http://www.ftdichip.com/Documents/AppNotes/AN232R-01_FT232RBitBangModes.pdf http://www.ftdichip.com/Documents/AppNotes/AN_107_AdvancedDriverOptions_AN_000073.pdf http://www.ftdichip.com/Documents/AppNotes/AN232R-02_FT232RChipID.pdf http://www.ftdichip.com/Documents/AppNotes/AN_121_FTDI_Device_EEPROM_User_Area_Usage.pdf http://www.ftdichip.com/Documents/AppNotes/AN_120_Aliasing_VCP_Baud_Rates.pdf http://www.ftdichip.com/Documents/AppNotes/AN_100_Using_The_FT232_245R_With_External_Osc(FT_000067).pdf http://www.ftdichip.com/Resources/Utilities/AN_126_User_Guide_For_FT232_Factory%20test%20utility.pdf http://www.ftdichip.com/Documents/AppNotes/AN232B-05_BaudRates.pdf http://www.ftdichip.com/Documents/InstallGuides.htm Copyright © 2010 Future Technology Devices International Limited 41 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Appendix B - List of Figures and Tables List of Figures Figure 2.1 FT232R Block Diagram ................................................................................................... 4 Figure 3.1 SSOP Package Pin Out and Schematic Symbol .......................................................... 7 Figure 3.2 QFN-32 Package Pin Out and schematic symbol .............................................................. 10 Figure 6.1 Bus Powered Configuration ........................................................................................... 23 Figure 6.2 Self Powered Configuration ........................................................................................... 24 Figure 6.4 USB Bus Powered with +3.3V or +5V External Logic Power Supply .................................... 26 Figure 7.1 Application Example showing USB to RS232 Converter ..................................................... 27 Figure 7.2 Application Example Showing USB to RS485 Converter .................................................... 28 Figure 7.3 USB to RS422 Converter Configuration ........................................................................... 29 Figure 7.4 USB to MCU UART Interface .......................................................................................... 30 Figure 7.5 Dual LED Configuration ................................................................................................ 31 Figure 7.6 Single LED Configuration .............................................................................................. 31 Figure 9.1 SSOP-28 Package Dimensions ....................................................................................... 35 Figure 9.2 QFN-32 Package Dimensions ......................................................................................... 36 Figure 9.3 Typical Pad Layout for QFN-32 Package .......................................................................... 37 Figure 9.4 Typical Solder Paste Diagram for QFN-32 Package ........................................................... 37 Figure 9.5 FT232R Solder Reflow Profile ........................................................................................ 38 List of Tables Table 3.1 USB Interface Group ....................................................................................................... 7 Table 3.2 Power and Ground Group ................................................................................................. 8 Table 3.3 Miscellaneous Signal Group .............................................................................................. 8 Table 3.4 UART Interface and CUSB Group (see note 3) .................................................................... 9 Table 3.5 USB Interface Group ..................................................................................................... 10 Table 3.6 Power and Ground Group ............................................................................................... 11 Table 3.7 Miscellaneous Signal Group ............................................................................................ 11 Table 3.8 UART Interface and CBUS Group (see note 3) .................................................................. 12 Table 3.9 CBUS Configuration Control ........................................................................................... 13 Table 5.1 Absolute Maximum Ratings ............................................................................................ 17 Table 5.2 Operating Voltage and Current ....................................................................................... 18 Table 5.3 UART and CBUS I/O Pin Characteristics (VCCIO = +5.0V, Standard Drive Level) .................. 18 Table 5.4 UART and CBUS I/O Pin Characteristics (VCCIO = +3.3V, Standard Drive Level) .................. 18 Table 5.5 UART and CBUS I/O Pin Characteristics (VCCIO = +2.8V, Standard Drive Level) .................. 19 Table 5.6 UART and CBUS I/O Pin Characteristics (VCCIO = +1.8V, Standard Drive Level) .................. 19 Table 5.7 UART and CBUS I/O Pin Characteristics (VCCIO = +5.0V, High Drive Level) ......................... 19 Table 5.8 UART and CBUS I/O Pin Characteristics (VCCIO = +3.3V, High Drive Level) ......................... 19 Table 5.9 UART and CBUS I/O Pin Characteristics (VCCIO = +2.8V, High Drive Level) ......................... 20 Table 5.10 UART and CBUS I/O Pin Characteristics (VCCIO = +1.8V, High Drive Level) ....................... 20 Copyright © 2010 Future Technology Devices International Limited 42 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Table 5.11 RESET# and TEST Pin Characteristics ............................................................................ 20 Table 5.12 USB I/O Pin (USBDP, USBDM) Characteristics ................................................................. 21 Table 5.13 EEPROM Characteristics ............................................................................................... 21 Table 5.14 Internal Clock Characteristics ....................................................................................... 21 Table 5.15 OSCI, OSCO Pin Characteristics – see Note 1 ................................................................. 22 Table 8.1 Default Internal EEPROM Configuration ............................................................................ 34 Table 9.1 Reflow Profile Parameter Values ..................................................................................... 38 Copyright © 2010 Future Technology Devices International Limited 43 Document No.: FT_000053 FT232R USB UART IC Datasheet Version 2.10 Clearance No.: FTDI# 38 Appendix C - Revision History Document Title: USB UART IC FT232R Document Reference No.: FT_000053 Clearance No.: FTDI# 38 Product Page: http://www.ftdichip.com/FTProducts.htm Document Feedback: Send Feedback Version 0.90 Initial Datasheet Created August 2005 Version 0.96 Revised Pre-release datasheet October 2005 Version 1.00 Full datasheet released December 2005 Version 1.02 Minor revisions to datasheet December 2005 Version 1.03 Manufacturer ID added to default EEPROM configuration; Buffer sizes added January 2006 Version 1.04 QFN-32 Pad layout and solder paste diagrams added January 2006 Version 2.00 Reformatted, updated package info, added notes for 3.3V operation; June 2008 Part numbers, TID; added UART and CBUS characteristics for +1.8V; Corrected RESET#; Added MTTF data; Corrected the input switching threshold and input hysteresis values for VCCIO=5V Version 2.01 Corrected pin-out number in table3.2 for GND pin18. Improved graphics on some Figures. Add packing details. Changed USB suspend current spec from 500uA to 2.5mA Corrected Figure 9.2 QFN dimensions. August 2008 Version 2.02 Corrected Tape and Reel quantities. Added comment “PWREN# should be used with a 10kΩ resistor pull up”. Replaced TXDEN# with TXDEN since it is active high in various places. Added lot number to the device markings. Added 3V3 regulator output tolerance. Clarified VCC operation and added section headed “Using an external Oscillator” Updated company contact information. April 2009 Version 2.03 Corrected the RX/TX buffer definitions to be relative to the USB interface June 2009 Version 2.04 Additional dimensions added to QFN solder profile June 2009 Version 2.05 Modified package dimensions to 5.0 x 5.0 +/-0.075mm. December 2009 and Solder paste diagram to 2.50 x 2.50 +/-0.0375mm Added Windows 7 32, 64 bit driver support Added FT_PROG utility references Added Appendix A-references.Figure 2.1 updated. Updated USB-IF TID for Rev B Version 2.06 Updated section 6.2, Figure 6.2 and the note, May 2010 Updated section 5.3, Table 5.13, EEPROM data retention time Version 2.07 Added USB Certification Logos July 2010 Version 2.08 Updated USB-IF TID for Rev C April 2011 Version 2.09 Corrected Rev C TID number April 2011 Version 2.10 Table 3.9, added clock output frequency within ±0.7% March 2012 Edited Table 3.9, TXLED# and TXLED# Description Added feedback links LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 1 August 2013 LM78XX / LM78XXA 3-Terminal 1 A Positive Voltage Regulator Features • Output Current up to 1 A • Output Voltages: 5, 6, 8, 9, 10, 12, 15, 18, 24 V • Thermal Overload Protection • Short-Circuit Protection • Output Transistor Safe Operating Area Protection Ordering Information(1) Note: 1. Above output voltage tolerance is available at 25°C. Product Number Output Voltage Tolerance Package Operating Temperature Packing Method LM7805CT ±4% TO-220 (Single Gauge) -40°C to +125°C Rail LM7806CT LM7808CT LM7809CT LM7810CT LM7812CT LM7815CT LM7818CT LM7824CT LM7805ACT ±2% 0°C to +125°C LM7809ACT LM7810ACT LM7812ACT LM7815ACT Description The LM78XX series of three-terminal positive regulators is available in the TO-220 package and with several fixed output voltages, making them useful in a wide range of applications. Each type employs internal current limiting, thermal shut-down, and safe operating area protection. If adequate heat sinking is provided, they can deliver over 1 A output current. Although designed primarily as fixedvoltage regulators, these devices can be used with external components for adjustable voltages and currents. 1 1. Input 2. GND 3. Output GND TO-220 (Single Gauge) LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 2 Block Diagram Figure 1. Block Diagram Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Values are at TA = 25°C unless otherwise noted. Symbol Parameter Value Unit VI Input Voltage VO = 5 V to 18 V 35 V VO = 24 V 40 RθJC Thermal Resistance, Junction-Case (TO-220) 5 °C/W RθJA Thermal Resistance, Junction-Air (TO-220) 65 °C/W TOPR Operating Temperature Range LM78xx -40 to +125 °C LM78xxA 0 to +125 TSTG Storage Temperature Range - 65 to +150 °C Starting Circuit Input 1 Reference Voltage Current Generator SOA Protection Thermal Protection Series Pass Element Error Amplifier Output 3 GND 2 LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 3 Electrical Characteristics (LM7805) Refer to the test circuit, -40°C < TJ < 125°C, IO = 500 mA, VI = 10 V, CI = 0.1 μF, unless otherwise specified. Notes: 2. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 3. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 4.80 5.00 5.20 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 7 V to 20 V 4.75 5.00 5.25 Regline Line Regulation(2) TJ = +25°C VI = 7 V to 25 V 4.0 100.0 mV VI = 8 V to 12 V 1.6 50.0 Regload Load Regulation(2) TJ = +25°C IO = 5 mA to 1.5 A 9.0 100.0 mV IO = 250 mA to 750 mA 4.0 50.0 IQ Quiescent Current TJ =+25°C 5.0 8.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.03 0.50 mA VI = 7 V to 25 V 0.30 1.30 ΔVO/ΔT Output Voltage Drift(3) IO = 5 mA -0.8 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 42.0 μV/VO RR Ripple Rejection(3) f = 120 Hz, VI = 8 V to 18 V 62.0 73.0 dB VDROP Dropout Voltage TJ = +25°C, IO = 1 A 2.0 V RO Output Resistance(3) f = 1 kHz 15.0 mΩ ISC Short-Circuit Current TJ = +25°C, VI = 35 V 230 mA IPK Peak Current(3) TJ = +25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 4 Electrical Characteristics (LM7806) Refer to the test circuit, -40°C < TJ < 125°C, IO = 500 mA, VI = 11 V, CI = 0.33 μF,CO = 0.1 μF, unless otherwise specified. Notes: 4. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 5. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 5.75 6.00 6.25 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 8.0 V to 21 V 5.70 6.00 6.30 Regline Line Regulation(4) TJ = +25°C VI = 8 V to 25 V 5.0 120 mV VI = 9 V to 13 V 1.5 60.0 Regload Load Regulation(4) TJ = +25°C IO = 5 mA to 1.5 A 9.0 120.0 mV IO = 250 mA to 750 mA 3.0 60.0 IQ Quiescent Current TJ =+25°C 5.0 8.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.5 mA VI = 8 V to 25 V 1.3 ΔVO/ΔT Output Voltage Drift(5) IO = 5 mA -0.8 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 45.0 μV/VO RR Ripple Rejection(5) f = 120 Hz, VI = 8 V to 18 V 62.0 73.0 dB VDROP Dropout Voltage TJ = +25°C, IO = 1 A 2.0 V RO Output Resistance(5) f = 1 kHz 19.0 mΩ ISC Short-Circuit Current TJ = +25°C, VI = 35 V 250 mA IPK Peak Current(5) TJ = +25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 5 Electrical Characteristics (LM7808) Refer to the test circuit, -40°C < TJ < 125°C, IO = 500 mA, VI = 14 V, CI = 0.33 μF, CO = 0.1 μF, unless otherwise specified. Notes: 6. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 7. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 7.7 8.0 8.3 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 10.5 V to 23 V 7.6 8.0 8.4 Regline Line Regulation(6) TJ = +25°C VI = 10.5 V to 25 V 5.0 160.0 mV VI = 11.5 V to 17 V 2.0 80.0 Regload Load Regulation(6) TJ = +25°C IO = 5 mA to 1.5 A 10.0 160.0 mV IO = 250 mA to 750 mA 5.0 80.0 IQ Quiescent Current TJ =+25°C 5.0 8.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.05 0.50 mA VI = 10.5 V to 25 V 0.5 1.0 ΔVO/ΔT Output Voltage Drift(7) IO = 5 mA -0.8 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 52.0 μV/VO RR Ripple Rejection(7) f = 120 Hz, VI = 11.5 V to 21.5 V 56.0 73.0 dB VDROP Dropout Voltage IO = 1 A, TJ = +25°C 2.0 V RO Output Resistance(7) f = 1 kHz 17.0 mΩ ISC Short-Circuit Current VI = 35 V, TJ = +25°C 230 mA IPK Peak Current(7) TJ = +25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 6 Electrical Characteristics (LM7809) Refer to the test circuit, -40°C < TJ < 125°C, IO = 500 mA, VI = 15 V, CI = 0.33 μF,CO = 0.1 μF, unless otherwise specified. Notes: 8. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 9. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 8.65 9.00 9.35 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 11.5 V to 24 V 8.60 9.00 9.40 Regline Line Regulation(8) TJ = +25°C VI = 11.5 V to 25 V 6.0 180.0 mV VI = 12 V to 17 V 2.0 90.0 Regload Load Regulation(8) TJ = +25°C IO = 5 mA to 1.5 A 12.0 180.0 mV IO = 250 mA to 750 mA 4.0 90.0 IQ Quiescent Current TJ =+25°C 5.0 8.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.5 mA VI = 11.5 V to 26 V 1.3 ΔVO/ΔT Output Voltage Drift(9) IO = 5 mA -1.0 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 58.0 μV/VO RR Ripple Rejection(9) f = 120 Hz, VI = 13 V to 23 V 56.0 71.0 dB VDROP Dropout Voltage IO = 1 A, TJ = +25°C 2.0 V RO Output Resistance(9) f = 1 kHz 17.0 mΩ ISC Short-Circuit Current VI = 35 V, TJ = +25°C 250 mA IPK Peak Current(9) TJ = +25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 7 Electrical Characteristics (LM7810) Refer to the test circuit, -40°C < TJ < 125°C, IO = 500 mA, VI = 16 V, CI = 0.33 μF,CO = 0.1 μF, unless otherwise specified. Notes: 10. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 11. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 9.6 10.0 10.4 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 12.5 V to 25 V 9.5 10.0 10.5 Regline Line Regulation(10) TJ = +25°C VI = 12.5 V to 25 V 10 200 mV VI = 13 V to 25 V 3 100 Regload Load Regulation(10) TJ = +25°C IO = 5 mA to 1.5 A 12 200 mV IO = 250 mA to 750 mA 4 400 IQ Quiescent Current TJ =+25°C 5.1 8.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.5 mA VI = 12.5 V to 29 V 1.0 ΔVO/ΔT Output Voltage Drift(11) IO = 5 mA -1.0 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 58.0 μV/VO RR Ripple Rejection(11) f = 120 Hz, VI = 13 V to 23 V 56.0 71.0 dB VDROP Dropout Voltage IO = 1 A, TJ = +25°C 2.0 V RO Output Resistance(11) f = 1 kHz 17.0 mΩ ISC Short-Circuit Current VI = 35 V, TJ = +25°C 250 mA IPK Peak Current(11) TJ = +25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 8 Electrical Characteristics (LM7812) Refer to the test circuit, -40°C < TJ < 125°C, IO = 500 mA, VI = 19 V, CI = 0.33 μF,CO = 0.1 μF, unless otherwise specified. Notes: 12. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 13. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 11.5 12.0 12.5 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 14.5 V to 27 V 11.4 12.0 12.6 Regline Line Regulation(12) TJ = +25°C VI = 14.5 V to 30 V 10 240 mV VI = 16 V to 22 V 3 120 Regload Load Regulation(12) TJ = +25°C IO = 5 mA to 1.5 A 11 240 mV IO = 250 mA to 750 mA 5 120 IQ Quiescent Current TJ =+25°C 5.1 8.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.1 0.5 mA VI = 14.5 V to 30 V 0.5 1.0 ΔVO/ΔT Output Voltage Drift(13) IO = 5 mA -1.0 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 76.0 μV/VO RR Ripple Rejection(13) f = 120 Hz, VI = 15 V to 25 V 55.0 71.0 dB VDROP Dropout Voltage IO = 1 A, TJ = +25°C 2.0 V RO Output Resistance(13) f = 1 kHz 18.0 mΩ ISC Short-Circuit Current VI = 35 V, TJ = +25°C 230 mA IPK Peak Current(13) TJ = +25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 9 Electrical Characteristics (LM7815) Refer to the test circuit, -40°C < TJ < 125°C, IO = 500 mA, VI = 23 V, CI = 0.33 μF,CO = 0.1 μF, unless otherwise specified. Notes: 14. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 15. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 14.40 15.00 15.60 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 17.5 V to 30 V 14.25 15.00 15.75 Regline Line Regulation(14) TJ = +25°C VI = 17.5 V to 30 V 11 300 mV VI = 20 V to 26 V 3 150 Regload Load Regulation(14) TJ = +25°C IO = 5 mA to 1.5 A 12 300 mV IO = 250 mA to 750 mA 4 150 IQ Quiescent Current TJ =+25°C 5.2 8.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.5 mA VI = 17.5 V to 30 V 1.0 ΔVO/ΔT Output Voltage Drift(15) IO = 5 mA -1.0 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 90.0 μV/VO RR Ripple Rejection(15) f = 120 Hz, VI = 18.5 V to 28.5 V 54.0 70.0 dB VDROP Dropout Voltage IO = 1 A, TJ =+25°C 2.0 V RO Output Resistance(15) f = 1 kHz 19.0 mΩ ISC Short-Circuit Current VI = 35 V, TJ = +25°C 250 mA IPK Peak Current(15) TJ = +25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 10 Electrical Characteristics (LM7818) Refer to the test circuit, -40°C < TJ < 125°C, IO = 500 mA, VI = 27 V, CI = 0.33 μF, CO = 0.1 μF, unless otherwise specified. Notes: 16. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 17. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 17.3 18.0 18.7 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 21 V to 33 V 17.1 18.0 18.9 Regline Line Regulation(16) TJ = +25°C VI = 21 V to 33 V 15 360 mV VI = 24 V to 30 V 5 180 Regload Load Regulation(16) TJ = +25°C IO = 5 mA to 1.5 A 15 360 mV IO = 250 mA to 750 mA 5 180 IQ Quiescent Current TJ =+25°C 5.2 8.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.5 mA VI = 21 V to 33 V 1.0 ΔVO/ΔT Output Voltage Drift(17) IO = 5 mA -1.0 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 110 μV/VO RR Ripple Rejection(17) f = 120 Hz, VI = 22 V to 32 V 53.0 69.0 dB VDROP Dropout Voltage IO = 1 A, TJ =+25°C 2.0 V RO Output Resistance(17) f = 1 kHz 22.0 mΩ ISC Short-Circuit Current VI = 35 V, TJ =+25°C 250 mA IPK Peak Current(17) TJ =+25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 11 Electrical Characteristics (LM7824) Refer to the test circuit, -40°C < TJ < 125°C, IO = 500 mA, VI = 33 V, CI = 0.33 μF, CO = 0.1 μF, unless otherwise specified. Notes: 18. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 19. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 23.00 24.00 25.00 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 27 V to 38 V 22.80 24.00 25.25 Regline Line Regulation(18) TJ = +25°C VI = 27 V to 38 V 17 480 mV VI = 30 V to 36 V 6 240 Regload Load Regulation(18) TJ = +25°C IO = 5 mA to 1.5 A 15 480 mV IO = 250 mA to 750 mA 5 240 IQ Quiescent Current TJ =+25°C 5.2 8.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.1 0.5 mA VI = 27 V to 38 V 0.5 1.0 ΔVO/ΔT Output Voltage Drift(19) IO = 5 mA -1.5 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 6.0 μV/VO RR Ripple Rejection(19) f = 120 Hz, VI = 28 V to 38 V 50.0 67.0 dB VDROP Dropout Voltage IO = 1 A, TJ = +25°C 2.0 V RO Output Resistance(19) f = 1 kHz 28.0 mΩ ISC Short-Circuit Current VI = 35 V, TJ = +25°C 230 mA IPK Peak Current(19) TJ = +25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 12 Electrical Characteristics (LM7805A) Refer to the test circuit, 0°C < TJ < 125°C, IO = 1 A, VI = 10 V, CI = 0.33 μF, CO = 0.1 μF, unless otherwise specified. Notes: 20. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 21. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 4.9 5.0 5.1 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 7.5 V to 20 V 4.8 5.0 5.2 Regline Line Regulation(20) VI = 7.5 V to 25 V, IO = 500 mA 5.0 50.0 mV VI = 8 V to 12 V 3.0 50.0 TJ = +25°C VI = 7.3 V to 20 V 5.0 50.0 VI = 8 V to 12 V 1.5 25.0 Regload Load Regulation(20) TJ = +25°C, IO = 5 mA to 1.5 A 9.0 100.0 IO = 5 mA to 1 A 9.0 100.0 mV IO = 250 mA to 750 mA 4.0 50.0 IQ Quiescent Current TJ =+25°C 5.0 6.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.5 VI = 8 V to 25 V, IO = 500 mA 0.8 mA VI = 7.5 V to 20 V, TJ = +25°C 0.8 ΔVO/ΔT Output Voltage Drift(21) IO = 5 mA -0.8 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 10.0 μV/VO RR Ripple Rejection(21) f = 120 Hz, VO = 500 mA, VI =8 V to 18 V 68.0 dB VDROP Dropout Voltage IO = 1 A, TJ =+25°C 2.0 V RO Output Resistance(21) f = 1 kHz 17.0 mΩ ISC Short-Circuit Current VI = 35 V, TJ =+25°C 250 mA IPK Peak Current(21) TJ =+25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 13 Electrical Characteristics (LM7809A) Refer to the test circuit, 0°C < TJ < 125°C, IO = 1 A, VI = 15 V, CI = 0.33 μF,CO = 0.1 μF, unless otherwise specified. Notes: 22. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 23. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 8.82 9.00 9.16 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 11.2 V to 24 V 8.65 9.00 9.35 Regline Line Regulation(22) VI = 11.7 V to 25 V, IO = 500 mA 6.0 90.0 mV VI = 12.5 V to 19 V 4.0 45.0 TJ = +25°C VI = 11.5 V to 24 V 6.0 90.0 VI = 12.5 V to 19 V 2.0 45.0 Regload Load Regulation(22) TJ = +25°C, IO = 5 mA to 1.5 A 12.0 100.0 IO = 5 mA to 1 A 12.0 100.0 mV IO = 250 mA to 750 mA 5.0 50.0 IQ Quiescent Current TJ = +25°C 5.0 6.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.5 VI = 12 V to 25 V, IO = 500 mA 0.8 mA VI = 11.7 V to 25 V, TJ = +25°C 0.8 ΔVO/ΔT Output Voltage Drift(23) IO = 5 mA -1.0 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 10.0 μV/VO RR Ripple Rejection(23) f = 120 Hz, VO = 500 mA, VI =12 V to 22 V 62.0 dB VDROP Dropout Voltage IO = 1 A, TJ = +25°C 2.0 V RO Output Resistance(23) f = 1 kHz 17.0 mΩ ISC Short-Circuit Current VI = 35 V, TJ = +25°C 250 mA IPK Peak Current(23) TJ = +25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 14 Electrical Characteristics (LM7810A) Refer to the test circuit, 0°C < TJ < 125°C, IO = 1 A, VI = 16 V, CI = 0.33 μF, CO = 0.1 μF, unless otherwise specified. Notes: 24. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 25. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 9.8 10.0 10.2 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 12.8 V to 25 V 9.6 10.0 10.4 Regline Line Regulation(24) VI = 12.8 V to 26 V, IO = 500 mA 8.0 100.0 mV VI = 13 V to 20 V 4.0 50.0 TJ = +25°C VI = 12.5 V to 25 V 8.0 100.0 VI = 13 V to 20 V 3.0 50.0 Regload Load Regulation(24) TJ = +25°C, IO = 5 mA to 1.5 A 12.0 100.0 IO = 5 mA to 1 A 12.0 100.0 mV IO = 250 mA to 750 mA 5.0 50.0 IQ Quiescent Current TJ =+25°C 5.0 6.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.5 VI = 12.8 V to 25 V, IO = 500 mA 0.8 mA VI = 13 V to 26 V, TJ = +25°C 0.5 ΔVO/ΔT Output Voltage Drift(25) IO = 5 mA -1.0 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 10.0 μV/VO RR Ripple Rejection(25) f = 120 Hz, VO = 500 mA, VI =14 V to 24 V 62.0 dB VDROP Dropout Voltage IO = 1 A, TJ =+25°C 2.0 V RO Output Resistance(25) f = 1 kHz 17.0 mΩ ISC Short-Circuit Current VI = 35 V, TJ =+25°C 250 mA IPK Peak Current(25) TJ =+25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 15 Electrical Characteristics (LM7812A) Refer to the test circuit, 0°C < TJ < 125°C, IO = 1 A, VI = 19 V, CI = 0.33 μF, CO = 0.1 μF, unless otherwise specified. Notes: 26. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 27. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 11.75 12.00 12.25 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 14.8 V to 27 V 11.50 12.00 12.50 Regline Line Regulation(26) VI = 14.8 V to 30 V, IO = 500 mA 10.0 120.0 mV VI = 16 V to 22 V 4.0 120.0 TJ = +25°C VI = 14.5 V to 27 V 10.0 120.0 VI = 16 V to 22 V 3.0 60.0 Regload Load Regulation(26) TJ = +25°C, IO = 5 mA to 1.5 A 12.0 100.0 IO = 5 mA to 1 A 12.0 100.0 mV IO = 250 mA to 750 mA 5.0 50.0 IQ Quiescent Current TJ = +25°C 5.0 6.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.5 VI = 14 V to 27 V, IO = 500 mA 0.8 mA VI = 15 V to 30 V, TJ = +25°C 0.8 ΔVO/ΔT Output Voltage Drift(27) IO = 5 mA -1.0 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 10.0 μV/VO RR Ripple Rejection(27) f = 120 Hz, VO = 500 mA, VI =14 V to 24 V 60.0 dB VDROP Dropout Voltage IO = 1 A, TJ = +25°C 2.0 V RO Output Resistance(27) f = 1 kHz 18.0 mΩ ISC Short-Circuit Current VI = 35 V, TJ = +25°C 250 mA IPK Peak Current(27) TJ = +25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 16 Electrical Characteristics (LM7815A) Refer to the test circuit, 0°C < TJ < 125°C, IO = 1 A, VI = 23 V, CI = 0.33 μF, CO = 0.1 μF, unless otherwise specified. Notes: 28. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken into account separately. Pulse testing with low duty is used. 29. These parameters, although guaranteed, are not 100% tested in production. Symbol Parameter Conditions Min. Typ. Max. Unit VO Output Voltage TJ = +25°C 14.75 15.00 15.30 IO = 5 mA to 1 A, PO ≤ 15 W, V VI = 17.7 V to 30 V 14.40 15.00 15.60 Regline Line Regulation(28) VI = 17.4 V to 30 V, IO = 500 mA 10.0 150.0 mV VI = 20 V to 26 V 5.0 150.0 TJ = +25°C VI = 17.5 V to 30 V 11.0 150.0 VI = 20 V to 26 V 3.0 75.0 Regload Load Regulation(28) TJ = +25°C, IO = 5 mA to 1.5 A 12.0 100.0 IO = 5 mA to 1 A 12.0 100.0 mV IO = 250 mA to 750 mA 5.0 50.0 IQ Quiescent Current TJ =+25°C 5.2 6.0 mA ΔIQ Quiescent Current Change IO = 5 mA to 1 A 0.5 VI = 17.5 V to 30 V, IO = 500 mA 0.8 mA VI = 17.5 V to 30 V, TJ = +25°C 0.8 ΔVO/ΔT Output Voltage Drift(29) IO = 5 mA -1.0 mV/°C VN Output Noise Voltage f = 10 Hz to 100 kHz, TA = +25°C 10.0 μV/VO RR Ripple Rejection(29) f = 120 Hz, VO = 500 mA, VI =18.5 V to 28.5 V 58.0 dB VDROP Dropout Voltage IO = 1 A, TJ =+25°C 2.0 V RO Output Resistance(29) f = 1 kHz 19.0 mΩ ISC Short-Circuit Current VI = 35 V, TJ =+25°C 250 mA IPK Peak Current(29) TJ =+25°C 2.2 A LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 17 Typical Performance Characteristics Figure 2. Quiescent Current Figure 3. Peak Output Current Figure 4. Output Voltage Figure 5. Quiescent Current LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 18 Typical Applications Figure 6. DC Parameters Figure 7. Load Regulation Figure 8. Ripple Rejection CI CO 0.1μF 0.33μF Input Output LM78XX 1 3 2 LM78XX 3 2 1 0.33μF 270pF 100Ω 30μS RL 2N6121 or EQ Input Output VO 0V VO LM78XX Input Output 5.1Ω 0.33μF 2 1 3 RL 470μF 120Hz + LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 19 Figure 9. Fixed-Output Regulator Notes: 29. To specify an output voltage, substitute voltage value for “XX”. A common ground is required between the input and the output voltage. The input voltage must remain typically 2.0 V above the output voltage even during the low point on the input ripple voltage. 30. CI is required if regulator is located an appreciable distance from power supply filter. 31. CO improves stability and transient response. Figure 10. Figure 11. Circuit for Increasing Output Voltage CI CO 0.1μF 0.33μF Input Output LM78XX 1 3 2 CI CO 0.1μF 0.33μF Output Input LM78XX 1 3 2 VXX R1 RL IQ IO IO = R1 +IQ VXX CI CO 0.1μF 0.33μF Output Input LM78XX 1 3 2 VXX R1 R2 IQ IRI ≥ 5 IQ VO = VXX(1 + R2 / R1) + IQR2 LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 20 Figure 12. Adjustable Output Regulator (7 V to 30 V) Figure 13. High-Current Voltage Regulator Figure 14. High Output Current with Short-Circuit Protection LM741 - + 2 3 6 4 2 1 3 CI 0.33μF Input Output 0.1μF CO LM7805 10kΩ IRI ≥ 5 IQ VO = VXX(1 + R2 / R1) + IQR2 3 2 1 LM78XX Output Input R1 3Ω 0.33μF IREG 0.1μF IO IQ1 IO = IREG + BQ1 (IREG–VBEQ1/R1) Q1 BD536 R1 = VBEQ1 IREG–IQ1/ BQ1 LM78XX Output 0.33μF 0.1μF R1 3Ω 3 2 1 Input Q1 Q2 Q1 = TIP42 Q2 = TIP42 RSC = I SC VBEQ2 RSC LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 21 Figure 15. Tracking Voltage Regulator Figure 16. Split Power Supply (±15 V - 1 A) LM78XX LM741 0.33μF 0.1μF 1 2 3 7 2 6 4 3 4.7kΩ 4.7kΩ TIP42 COMMON COMMON VO -VO VI -VIN _ + 1 3 2 1 2 3 0.33μF 0.1μF 2.2μF 1μF + + 1N4001 1N4001 +15V -15V +20V -20V LM7815 MC7915 LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 22 Figure 17. Negative Output Voltage Circuit Figure 18. Switching Regulator LM78XX Output Input + 1 2 0.1μF 3 LM78XX 1mH 1 3 2 2000μF Input Output D45H11 0.33μF 470Ω 4.7Ω 10μF 0.5Ω Z1 + + LM78XX / LM78XXA — 3-Terminal 1 A Positive Voltage Regulator © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com LM78XX / LM78XXA Rev. 1.3.0 23 Physical Dimensions Figure 19. TO-220, MOLDED, 3-LEAD, JEDEC VARIATION AB (ACTIVE) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/TO/TO220B03.pdf. For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area: http://www.fairchildsemi.com/packing_dwg/PKG-TO220B03_TC.pdf. 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Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I65 ® Low Cost Low Power Instrumentation Amplifier AD620 Rev. H Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703© 2003–2011 Analog Devices, Inc. All rights reserved. FEATURES Easy to use Gain set with one external resistor (Gain range 1 to 10,000) Wide power supply range (±2.3 V to ±18 V) Higher performance than 3 op amp IA designs Available in 8-lead DIP and SOIC packaging Low power, 1.3 mA max supply current Excellent dc performance (B grade) 50 μV max, input offset voltage 0.6 μV/°C max, input offset drift 1.0 nA max, input bias current 100 dB min common-mode rejection ratio (G = 10) Low noise 9 nV/√Hz @ 1 kHz, input voltage noise 0.28 μV p-p noise (0.1 Hz to 10 Hz) Excellent ac specifications 120 kHz bandwidth (G = 100) 15 μs settling time to 0.01% APPLICATIONS Weigh scales ECG and medical instrumentation Transducer interface Data acquisition systems Industrial process controls Battery-powered and portable equipment CONNECTION DIAGRAM –IN RG –VS +IN RG +VS OUTPUT REF 1 2 3 4 8 7 6 AD620 5 TOP VIEW 00775-0-001 Figure 1. 8-Lead PDIP (N), CERDIP (Q), and SOIC (R) Packages PRODUCT DESCRIPTION The AD620 is a low cost, high accuracy instrumentation amplifier that requires only one external resistor to set gains of 1 to 10,000. Furthermore, the AD620 features 8-lead SOIC and DIP packaging that is smaller than discrete designs and offers lower power (only 1.3 mA max supply current), making it a good fit for battery-powered, portable (or remote) applications. The AD620, with its high accuracy of 40 ppm maximum nonlinearity, low offset voltage of 50 μV max, and offset drift of 0.6 μV/°C max, is ideal for use in precision data acquisition systems, such as weigh scales and transducer interfaces. Furthermore, the low noise, low input bias current, and low power of the AD620 make it well suited for medical applications, such as ECG and noninvasive blood pressure monitors. The low input bias current of 1.0 nA max is made possible with the use of Superϐeta processing in the input stage. The AD620 works well as a preamplifier due to its low input voltage noise of 9 nV/√Hz at 1 kHz, 0.28 μV p-p in the 0.1 Hz to 10 Hz band, and 0.1 pA/√Hz input current noise. Also, the AD620 is well suited for multiplexed applications with its settling time of 15 μs to 0.01%, and its cost is low enough to enable designs with one in-amp per channel. Table 1. Next Generation Upgrades for AD620 Part Comment AD8221 Better specs at lower price AD8222 Dual channel or differential out AD8226 Low power, wide input range AD8220 JFET input AD8228 Best gain accuracy AD8295 +2 precision op amps or differential out AD8429 Ultra low noise 0 5 10 15 20 30,000 5,000 10,000 15,000 20,000 25,000 0 TOTAL ERROR, PPM OF FULL SCALE SUPPLY CURRENT (mA) AD620A RG 3 OP AMP IN-AMP (3 OP-07s) 00775-0-002 Figure 2. Three Op Amp IA Designs vs. AD620 IMPORTANT LINKS for the AD620* Last content update 01/08/2014 09:49 am Looking for a high performance in-amp with lower noise, wider bandwidth, and fast settling time? Consider the AD8421 Looking for a high performance in-amp with lower power and a rail-to-rail output? Consider the AD8422. DOCUMENTATION AD620: Military Data Sheet AN-282: Fundamentals of Sampled Data Systems AN-244: A User's Guide to I.C. Instrumentation Amplifiers AN-245: Instrumentation Amplifiers Solve Unusual Design Problems AN-671: Reducing RFI Rectification Errors in In-Amp Circuits AN-589: Ways to Optimize the Performance of a Difference Amplifier A Designer's Guide to Instrumentation Amplifiers (3rd Edition) UG-261: Evaluation Boards for the AD62x, AD822x and AD842x Series ECG Front-End Design is Simplified with MicroConverter Low-Power, Low-Voltage IC Choices for ECG System Requirements Ask The Applications Engineer-10 Auto-Zero Amplifiers High-performance Adder Uses Instrumentation Amplifiers Protecting Instrumentation Amplifiers Input Filter Prevents Instrumentation-amp RF-Rectification Errors The AD8221 - Setting a New Industry Standard for Instrumentation Amplifiers ADI Warns Against Misuse of COTS Integrated Circuits Space Qualified Parts List Applying Instrumentation Amplifiers Effectively: The Importance of an Input Ground Return Leading Inside Advertorials: Applying Instrumentation Amplifiers Effectively–The Importance of an Input Ground Return DESIGN TOOLS, MODELS, DRIVERS & SOFTWARE In-Amp Error Calculator These tools will help estimate error contributions in your instrumentation amplifier circuit. It uses input parameters such as temperature, gain, voltage input, and source impedance to determine the errors that can contribute to your overall design. In-Amp Common Mode Calculator AD620 SPICE Macro-Model AD620A SPICE Macro-Model AD620B SPICE Macro-Model AD620S SPICE Macro-Model AD620 SABER Macro-Model Conv, 10/00 EVALUATION KITS & SYMBOLS & FOOTPRINTS View the Evaluation Boards and Kits page for documentation and purchasing Symbols and Footprints PRODUCT RECOMMENDATIONS & REFERENCE DESIGNS CN-0146: Low Cost Programmable Gain Instrumentation Amplifier Circuit Using the ADG1611 Quad SPST Switch and AD620 Instrumentation Amplifier DESIGN COLLABORATION COMMUNITY Collaborate Online with the ADI support team and other designers about select ADI products. Follow us on Twitter: www.twitter.com/ADI_News Like us on Facebook: www.facebook.com/AnalogDevicesInc DESIGN SUPPORT Submit your support request here: Linear and Data Converters Embedded Processing and DSP Telephone our Customer Interaction Centers toll free: Americas: 1-800-262-5643 Europe: 00800-266-822-82 China: 4006-100-006 India: 1800-419-0108 Russia: 8-800-555-45-90 Quality and Reliability Lead(Pb)-Free Data SAMPLE & BUY AD620 View Price & Packaging Request Evaluation Board Request Samples Check Inventory & Purchase Find Local Distributors * This page was dynamically generated by Analo g Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to the content on this page (labeled 'Important Links') does not constitute a change to the revision number of the product data sheet. This content may be frequently modified. Powered by TCPDF (www.tcpdf.org) AD620 Rev. H | Page 2 of 20 TABLE OF CONTENTS Specifications .....................................................................................3 Absolute Maximum Ratings ............................................................5 ESD Caution ..................................................................................5 Typical Performance Characteristics..............................................6 Theory of Operation.......................................................................12 Gain Selection..............................................................................15 Input and Output Offset Voltage ..............................................15 Reference Terminal .....................................................................15 Input Protection ..........................................................................15 RF Interference............................................................................15 Common-Mode Rejection.........................................................16 Grounding....................................................................................16 Ground Returns for Input Bias Currents.................................17 AD620ACHIPS Information.........................................................18 Outline Dimensions........................................................................19 Ordering Guide ...........................................................................20 REVISION HISTORY 7/11—Rev. G to Rev. H Deleted Figure 3.................................................................................1 Added Table 1 ....................................................................................1 Moved Figure 2 ..................................................................................1 Added ESD Input Diodes to Simplified Schematic ....................12 Changes to Input Protection Section............................................15 Added Figure 41; Renumbered Sequentially ...............................15 Changes to AD620ACHIPS Information Section ......................18 Updated Ordering Guide ...............................................................20 12/04—Rev. F to Rev. G Updated Format..................................................................Universal Change to Features............................................................................1 Change to Product Description.......................................................1 Changes to Specifications.................................................................3 Added Metallization Photograph....................................................4 Replaced Figure 4-Figure 6 ..............................................................6 Replaced Figure 15............................................................................7 Replaced Figure 33..........................................................................10 Replaced Figure 34 and Figure 35.................................................10 Replaced Figure 37..........................................................................10 Changes to Table 3 ..........................................................................13 Changes to Figure 41 and Figure 42 .............................................14 Changes to Figure 43 ......................................................................15 Change to Figure 44 ........................................................................17 Changes to Input Protection section ............................................15 Deleted Figure 9 ..............................................................................15 Changes to RF Interference section..............................................15 Edit to Ground Returns for Input Bias Currents section...........17 Added AD620CHIPS to Ordering Guide ....................................19 7/03—Data Sheet Changed from Rev. E to Rev. F Edit to FEATURES............................................................................1 Changes to SPECIFICATIONS.......................................................2 Removed AD620CHIPS from ORDERING GUIDE ...................4 Removed METALLIZATION PHOTOGRAPH...........................4 Replaced TPCs 1–3 ...........................................................................5 Replaced TPC 12...............................................................................6 Replaced TPC 30...............................................................................9 Replaced TPCs 31 and 32...............................................................10 Replaced Figure 4............................................................................10 Changes to Table I...........................................................................11 Changes to Figures 6 and 7 ............................................................12 Changes to Figure 8 ........................................................................13 Edited INPUT PROTECTION section........................................13 Added new Figure 9........................................................................13 Changes to RF INTERFACE section ............................................14 Edit to GROUND RETURNS FOR INPUT BIAS CURRENTS section...............................................................................................15 Updated OUTLINE DIMENSIONS.............................................16 AD620 Rev. H | Page 3 of 20 SPECIFICATIONS Typical @ 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted. Table 2. Parameter Conditions AD620A AD620B AD620S1 Min Typ Max Min Typ Max Min Typ Max Unit GAIN G = 1 + (49.4 kΩ/RG) Gain Range 1 10,000 1 10,000 1 10,000 Gain Error2 VOUT = ±10 V G = 1 0.03 0.10 0.01 0.02 0.03 0.10 % G = 10 0.15 0.30 0.10 0.15 0.15 0.30 % G = 100 0.15 0.30 0.10 0.15 0.15 0.30 % G = 1000 0.40 0.70 0.35 0.50 0.40 0.70 % Nonlinearity VOUT = −10 V to +10 V G = 1–1000 RL = 10 kΩ 10 40 10 40 10 40 ppm G = 1–100 RL = 2 kΩ 10 95 10 95 10 95 ppm Gain vs. Temperature G = 1 10 10 10 ppm/°C Gain >12 −50 −50 −50 ppm/°C VOLTAGE OFFSET (Total RTI Error = VOSI + VOSO/G) Input Offset, VOSI VS = ±5 V to ± 15 V 30 125 15 50 30 125 μV Overtemperature VS = ±5 V to ± 15 V 185 85 225 μV Average TC VS = ±5 V to ± 15 V 0.3 1.0 0.1 0.6 0.3 1.0 μV/°C Output Offset, VOSO VS = ±15 V 400 1000 200 500 400 1000 μV VS = ± 5 V 1500 750 1500 μV Overtemperature VS = ±5 V to ± 15 V 2000 1000 2000 μV Average TC VS = ±5 V to ± 15 V 5.0 15 2.5 7.0 5.0 15 μV/°C Offset Referred to the Input vs. Supply (PSR) VS = ±2.3 V to ±18 V G = 1 80 100 80 100 80 100 dB G = 10 95 120 100 120 95 120 dB G = 100 110 140 120 140 110 140 dB G = 1000 110 140 120 140 110 140 dB INPUT CURRENT Input Bias Current 0.5 2.0 0.5 1.0 0.5 2 nA Overtemperature 2.5 1.5 4 nA Average TC 3.0 3.0 8.0 pA/°C Input Offset Current 0.3 1.0 0.3 0.5 0.3 1.0 nA Overtemperature 1.5 0.75 2.0 nA Average TC 1.5 1.5 8.0 pA/°C INPUT Input Impedance Differential 10||2 10||2 10||2 GΩ_pF Common-Mode 10||2 10||2 10||2 GΩ_pF Input Voltage Range3 VS = ±2.3 V to ±5 V −VS + 1.9 +VS − 1.2 −VS + 1.9 +VS − 1.2 −VS + 1.9 +VS − 1.2 V Overtemperature −VS + 2.1 +VS − 1.3 −VS + 2.1 +VS − 1.3 −VS + 2.1 +VS − 1.3 V VS = ± 5 V to ±18 V −VS + 1.9 +VS − 1.4 −VS + 1.9 +VS − 1.4 −VS + 1.9 +VS − 1.4 V Overtemperature −VS + 2.1 +VS − 1.4 −VS + 2.1 +VS + 2.1 −VS + 2.3 +VS − 1.4 V AD620 Rev. H | Page 4 of 20 AD620A AD620B AD620S1 Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit Common-Mode Rejection Ratio DC to 60 Hz with 1 kΩ Source Imbalance VCM = 0 V to ± 10 V G = 1 73 90 80 90 73 90 dB G = 10 93 110 100 110 93 110 dB G = 100 110 130 120 130 110 130 dB G = 1000 110 130 120 130 110 130 dB OUTPUT Output Swing RL = 10 kΩ VS = ±2.3 V to ± 5 V −VS + 1.1 +VS − 1.2 −VS + 1.1 +VS − 1.2 −VS + 1.1 +VS − 1.2 V Overtemperature −VS + 1.4 +VS − 1.3 −VS + 1.4 +VS − 1.3 −VS + 1.6 +VS − 1.3 V VS = ±5 V to ± 18 V −VS + 1.2 +VS − 1.4 −VS + 1.2 +VS − 1.4 −VS + 1.2 +VS − 1.4 V Overtemperature −VS + 1.6 +VS – 1.5 −VS + 1.6 +VS – 1.5 –VS + 2.3 +VS – 1.5 V Short Circuit Current ±18 ±18 ±18 mA DYNAMIC RESPONSE Small Signal –3 dB Bandwidth G = 1 1000 1000 1000 kHz G = 10 800 800 800 kHz G = 100 120 120 120 kHz G = 1000 12 12 12 kHz Slew Rate 0.75 1.2 0.75 1.2 0.75 1.2 V/μs Settling Time to 0.01% 10 V Step G = 1–100 15 15 15 μs G = 1000 150 150 150 μs NOISE Voltage Noise, 1 kHz Total RTI Noise (e2 ) (e /G)2 = ni + no Input, Voltage Noise, eni 9 13 9 13 9 13 nV/√Hz Output, Voltage Noise, eno 72 100 72 100 72 100 nV/√Hz RTI, 0.1 Hz to 10 Hz G = 1 3.0 3.0 6.0 3.0 6.0 μV p-p G = 10 0.55 0.55 0.8 0.55 0.8 μV p-p G = 100–1000 0.28 0.28 0.4 0.28 0.4 μV p-p Current Noise f = 1 kHz 100 100 100 fA/√Hz 0.1 Hz to 10 Hz 10 10 10 pA p-p REFERENCE INPUT RIN 20 20 20 kΩ IIN VIN+, VREF = 0 50 60 50 60 50 60 μA Voltage Range −VS + 1.6 +VS − 1.6 −VS + 1.6 +VS − 1.6 −VS + 1.6 +VS − 1.6 V Gain to Output 1 ± 0.0001 1 ± 0.0001 1 ± 0.0001 POWER SUPPLY Operating Range4 ±2.3 ±18 ±2.3 ±18 ±2.3 ±18 V Quiescent Current VS = ±2.3 V to ±18 V 0.9 1.3 0.9 1.3 0.9 1.3 mA Overtemperature 1.1 1.6 1.1 1.6 1.1 1.6 mA TEMPERATURE RANGE For Specified Performance −40 to +85 −40 to +85 −55 to +125 °C 1 See Analog Devices military data sheet for 883B tested specifications. 2 Does not include effects of external resistor RG. 3 One input grounded. G = 1. 4 This is defined as the same supply range that is used to specify PSR. AD620 Rev. H | Page 5 of 20 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Supply Voltage ±18 V Internal Power Dissipation1 650 mW Input Voltage (Common-Mode) ±VS Differential Input Voltage 25 V Output Short-Circuit Duration Indefinite Storage Temperature Range (Q) −65°C to +150°C Storage Temperature Range (N, R) −65°C to +125°C Operating Temperature Range AD620 (A, B) −40°C to +85°C AD620 (S) −55°C to +125°C Lead Temperature Range (Soldering 10 seconds) 300°C 1 Specification is for device in free air: 8-Lead Plastic Package: θJA = 95°C 8-Lead CERDIP Package: θJA = 110°C 8-Lead SOIC Package: θJA = 155°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION AD620 Rev. H | Page 6 of 20 TYPICAL PERFORMANCE CHARACTERISTICS (@ 25°C, VS = ±15 V, RL = 2 kΩ, unless otherwise noted.) INPUT OFFSET VOLTAGE (μV) 20 30 40 50 –40 0 40 80 PERCENTAGE OF UNITS –80 SAMPLE SIZE = 360 10 0 00775-0-005 Figure 3. Typical Distribution of Input Offset Voltage INPUT BIAS CURRENT (pA) 0 10 20 30 40 50 –600 0 600 PERCENTAGE OF UNITS –1200 1200 SAMPLE SIZE = 850 00775-0-006 Figure 4. Typical Distribution of Input Bias Current 10 20 30 40 50 –200 0 200 400 INPUT OFFSET CURRENT (pA) PERCENTAGE OF UNITS –400 0 SAMPLE SIZE = 850 00775-0-007 Figure 5. Typical Distribution of Input Offset Current TEMPERATURE (°C) INPUT BIAS CURRENT (nA) +IB –IB 2.0 –2.0 175 –1.0 –1.5 –75 –0.5 0 0.5 1.0 1.5 –25 25 75 125 00775-0-008 Figure 6. Input Bias Current vs. Temperature CHANGE IN OFFSET VOLTAGE (μV) 1.5 0.5 WARM-UP TIME (Minutes) 2.0 0 0 1 1.0 2 3 4 5 00775-0-009 Figure 7. Change in Input Offset Voltage vs. Warm-Up Time FREQUENCY (Hz) 1000 1 1 100k 100 10 100 1k 10k VOLTAGE NOISE (nV/ Hz) GAIN = 1 GAIN = 10 10 GAIN = 100, 1,000 GAIN = 1000 BW LIMIT 00775-0-010 Figure 8. Voltage Noise Spectral Density vs. Frequency (G = 1−1000) AD620 Rev. H | Page 7 of 20 FREQUENCY (Hz) 1000 100 10 1 10 100 1000 CURRENT NOISE (fA/ Hz) 00775-0-011 Figure 9. Current Noise Spectral Density vs. Frequency RTI NOISE (2.0μV/DIV) TIME (1 SEC/DIV) 00775-0-012 Figure 10. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1) RTI NOISE (0.1μV/DIV) TIME (1 SEC/DIV) 00775-0-013 Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000) 00775-0-014 Figure 12. 0.1 Hz to 10 Hz Current Noise, 5 pA/Div 100 1000 AD620A FET INPUT IN-AMP SOURCE RESISTANCE (Ω) TOTAL DRIFT FROM 25°C TO 85°C, RTI (μV) 100,000 10 1k 10M 10,000 10k 100k 1M 00775-0-015 Figure 13. Total Drift vs. Source Resistance FREQUENCY (Hz) CMR (dB) 160 0 1M 80 40 1 60 0.1 140 100 120 10 100 1k 10k 100k G = 1000 G = 100 G = 10 G = 1 20 00775-0-016 Figure 14. Typical CMR vs. Frequency, RTI, Zero to 1 kΩ Source Imbalance AD620 Rev. H | Page 8 of 20 FREQUENCY (Hz) PSR (dB) 160 1M 80 40 1 60 0.1 140 100 120 10 100 1k 10k 100k 20 G = 1000 G = 100 G = 10 G = 1 180 00775-0-017 Figure 15. Positive PSR vs. Frequency, RTI (G = 1−1000) FREQUENCY (Hz) PSR (dB) 160 1M 80 40 1 60 0.1 140 100 120 10 100 1k 10k 100k 20 180 G = 10 G = 100 G = 1 G = 1000 00775-0-018 Figure 16. Negative PSR vs. Frequency, RTI (G = 1−1000) 1000 100 10M 100 1 1k 10 10k 100k 1M FREQUENCY (Hz) GAIN (V/V) 0.1 00775-0-019 Figure 17. Gain vs. Frequency OUTPUT VOLTAGE (V p-p) FREQUENCY (Hz) 35 0 1M 15 5 10k 10 1k 30 20 25 100k G = 10, 100, 1000 G = 1 G = 1000 G = 100 BW LIMIT 00775-0-020 Figure 18. Large Signal Frequency Response INPUT VOLTAGE LIMIT (V) (REFERRED TO SUPPLY VOLTAGES) 20 +1.0 +0.5 0 5 +1.5 –1.5 –1.0 –0.5 10 15 SUPPLY VOLTAGE ± Volts +VS –0.0 –VS +0.0 00775-0-021 Figure 19. Input Voltage Range vs. Supply Voltage, G = 1 20 +1.0 +0.5 0 5 +1.5 –1.5 –1.0 –0.5 10 15 SUPPLY VOLTAGE ± Volts RL = 10kΩ RL = 2kΩ RL = 10kΩ OUTPUT VOLTAGE SWING (V) (REFERRED TO SUPPLY VOLTAGES) RL = 2kΩ +VS –VS 00775-0-022 –0.0 +0.0 Figure 20. Output Voltage Swing vs. Supply Voltage, G = 10 AD620 Rev. H | Page 9 of 20 OUTPUT VOLTAGE SWING (V p-p) LOAD RESISTANCE (Ω) 30 0 0 10k 20 10 100 1k VS = ±15V G = 10 00775-0-023 Figure 21. Output Voltage Swing vs. Load Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00775-0-024 Figure 22. Large Signal Pulse Response and Settling Time G = 1 (0.5 mV = 0.01%) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00775-0-025 Figure 23. Small Signal Response, G = 1, RL = 2 kΩ, CL = 100 pF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00775-0-026 Figure 24. Large Signal Response and Settling Time, G = 10 (0.5 mV = 0.01%) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00775-0-027 Figure 25. Small Signal Response, G = 10, RL = 2 kΩ, CL = 100 pF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00775-0-030 Figure 26. Large Signal Response and Settling Time, G = 100 (0.5 mV = 0.01%) AD620 Rev. H | Page 10 of 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00775-0-029 Figure 27. Small Signal Pulse Response, G = 100, RL = 2 kΩ, CL = 100 pF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00775-0-030 Figure 28. Large Signal Response and Settling Time, G = 1000 (0.5 mV = 0.01% ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00775-0-031 Figure 29. Small Signal Pulse Response, G = 1000, RL = 2 kΩ, CL = 100 pF OUTPUT STEP SIZE (V) SETTLING TIME (μs) TO 0.01% TO 0.1% 20 0 0 2 15 5 5 10 10 15 0 00775-0-032 Figure 30. Settling Time vs. Step Size (G = 1) GAIN SETTLING TIME (μs) 1000 1 1 1000 100 10 10 100 00775-0-033 Figure 31. Settling Time to 0.01% vs. Gain, for a 10 V Step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00775-0-034 Figure 32. Gain Nonlinearity, G = 1, RL = 10 kΩ (10 μV = 1 ppm) AD620 Rev. H | Page 11 of 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00775-0-035 Figure 33. Gain Nonlinearity, G = 100, RL = 10 kΩ (100 μV = 10 ppm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00775-0-036 Figure 34. Gain Nonlinearity, G = 1000, RL = 10 kΩ (1 mV = 100 ppm) AD620 VOUT G = 1000 G = 1 49.9Ω 10kΩ * 1kΩ 10T 10kΩ 499Ω G = 100 G = 10 5.49kΩ +VS 11kΩ 1kΩ 100Ω 100kΩ INPUT 10V p-p –VS *ALL RESISTORS 1% TOLERANCE 1 7 2 3 8 6 4 5 00775-0-037 Figure 35. Settling Time Test Circuit AD620 Rev. H | Page 12 of 20 THEORY OF OPERATION VB –VS A1 A2 A3 C2 RG R1 R2 GAIN SENSE GAIN SENSE 10kΩ 10kΩ I1 I2 10kΩ REF 10kΩ +IN – IN R4 400Ω OUTPUT C1 Q1 Q2 00775-0-038 R3 400Ω +VS +VS +VS 20μA 20μA Figure 36. Simplified Schematic of AD620 The AD620 is a monolithic instrumentation amplifier based on a modification of the classic three op amp approach. Absolute value trimming allows the user to program gain accurately (to 0.15% at G = 100) with only one resistor. Monolithic construction and laser wafer trimming allow the tight matching and tracking of circuit components, thus ensuring the high level of performance inherent in this circuit. The input transistors Q1 and Q2 provide a single differentialpair bipolar input for high precision (Figure 36), yet offer 10× lower input bias current thanks to Superϐeta processing. Feedback through the Q1-A1-R1 loop and the Q2-A2-R2 loop maintains constant collector current of the input devices Q1 and Q2, thereby impressing the input voltage across the external gain setting resistor RG. This creates a differential gain from the inputs to the A1/A2 outputs given by G = (R1 + R2)/RG + 1. The unity-gain subtractor, A3, removes any common-mode signal, yielding a single-ended output referred to the REF pin potential. The value of RG also determines the transconductance of the preamp stage. As RG is reduced for larger gains, the transconductance increases asymptotically to that of the input transistors. This has three important advantages: (a) Open-loop gain is boosted for increasing programmed gain, thus reducing gain related errors. (b) The gain-bandwidth product (determined by C1 and C2 and the preamp transconductance) increases with programmed gain, thus optimizing frequency response. (c) The input voltage noise is reduced to a value of 9 nV/√Hz, determined mainly by the collector current and base resistance of the input devices. The internal gain resistors, R1 and R2, are trimmed to an absolute value of 24.7 kΩ, allowing the gain to be programmed accurately with a single external resistor. The gain equation is then 1 49.4 + Ω = RG k G 1 49.4 − Ω = G k RG Make vs. Buy: a Typical Bridge Application Error Budget The AD620 offers improved performance over “homebrew” three op amp IA designs, along with smaller size, fewer components, and 10× lower supply current. In the typical application, shown in Figure 37, a gain of 100 is required to amplify a bridge output of 20 mV full-scale over the industrial temperature range of −40°C to +85°C. Table 4 shows how to calculate the effect various error sources have on circuit accuracy. AD620 Rev. H | Page 13 of 20 Regardless of the system in which it is being used, the AD620 provides greater accuracy at low power and price. In simple systems, absolute accuracy and drift errors are by far the most significant contributors to error. In more complex systems with an intelligent processor, an autogain/autozero cycle removes all absolute accuracy and drift errors, leaving only the resolution errors of gain, nonlinearity, and noise, thus allowing full 14-bit accuracy. Note that for the homebrew circuit, the OP07 specifications for input voltage offset and noise have been multiplied by √2. This is because a three op amp type in-amp has two op amps at its inputs, both contributing to the overall input error. R = 350Ω 10V PRECISION BRIDGE TRANSDUCER R = 350Ω R = 350Ω R = 350Ω 00775-0-039 AD620A MONOLITHIC INSTRUMENTATION AMPLIFIER, G = 100 SUPPLY CURRENT = 1.3mA MAX AD620A RG 499Ω REFERENCE 00775-0-040 Figure 37. Make vs. Buy "HOMEBREW" IN-AMP, G = 100 *0.02% RESISTOR MATCH, 3ppm/°C TRACKING **DISCRETE 1% RESISTOR, 100ppm/°C TRACKING SUPPLY CURRENT = 15mA MAX 100Ω ** 10kΩ * 10kΩ ** 10kΩ * 10kΩ * 10kΩ ** 10kΩ* OP07D OP07D OP07D 00775-0-041 Table 4. Make vs. Buy Error Budget Error, ppm of Full Scale Error Source AD620 Circuit Calculation “Homebrew” Circuit Calculation AD620 Homebrew ABSOLUTE ACCURACY at TA = 25°C Input Offset Voltage, μV 125 μV/20 mV (150 μV × √2)/20 mV 6,250 10,607 Output Offset Voltage, μV 1000 μV/100 mV/20 mV ((150 μV × 2)/100)/20 mV 500 150 Input Offset Current, nA 2 nA ×350 Ω/20 mV (6 nA ×350 Ω)/20 mV 18 53 CMR, dB 110 dB(3.16 ppm) ×5 V/20 mV (0.02% Match × 5 V)/20 mV/100 791 500 Total Absolute Error 7,559 11,310 DRIFT TO 85°C Gain Drift, ppm/°C (50 ppm + 10 ppm) ×60°C 100 ppm/°C Track × 60°C 3,600 6,000 Input Offset Voltage Drift, μV/°C 1 μV/°C × 60°C/20 mV (2.5 μV/°C × √2 × 60°C)/20 mV 3,000 10,607 Output Offset Voltage Drift, μV/°C 15 μV/°C × 60°C/100 mV/20 mV (2.5 μV/°C × 2 × 60°C)/100 mV/20 mV 450 150 Total Drift Error 7,050 16,757 RESOLUTION Gain Nonlinearity, ppm of Full Scale 40 ppm 40 ppm 40 40 Typ 0.1 Hz to 10 Hz Voltage Noise, μV p-p 0.28 μV p-p/20 mV (0.38 μV p-p × √2)/20 mV 14 27 Total Resolution Error 54 67 Grand Total Error 14,663 28,134 G = 100, VS = ±15 V. (All errors are min/max and referred to input.) AD620 Rev. H | Page 14 of 20 3kΩ 5V DIGITAL DATA OUTPUT ADC REF IN AGND 20kΩ 10kΩ 20kΩ G = 100 AD620B 1.7mA 0.10mA 0.6mA MAX 499Ω 3kΩ 3kΩ 3kΩ 2 1 8 3 7 6 5 4 1.3mA MAX AD705 00775-0-042 Figure 38. A Pressure Monitor Circuit that Operates on a 5 V Single Supply Pressure Measurement Although useful in many bridge applications, such as weigh scales, the AD620 is especially suitable for higher resistance pressure sensors powered at lower voltages where small size and low power become more significant. Figure 38 shows a 3 kΩ pressure transducer bridge powered from 5 V. In such a circuit, the bridge consumes only 1.7 mA. Adding the AD620 and a buffered voltage divider allows the signal to be conditioned for only 3.8 mA of total supply current. Small size and low cost make the AD620 especially attractive for voltage output pressure transducers. Since it delivers low noise and drift, it also serves applications such as diagnostic noninvasive blood pressure measurement. Medical ECG The low current noise of the AD620 allows its use in ECG monitors (Figure 39) where high source resistances of 1 MΩ or higher are not uncommon. The AD620’s low power, low supply voltage requirements, and space-saving 8-lead mini-DIP and SOIC package offerings make it an excellent choice for batterypowered data recorders. Furthermore, the low bias currents and low current noise, coupled with the low voltage noise of the AD620, improve the dynamic range for better performance. The value of capacitor C1 is chosen to maintain stability of the right leg drive loop. Proper safeguards, such as isolation, must be added to this circuit to protect the patient from possible harm. G = 7 AD620A 0.03Hz HIGHPASS FILTER OUTPUT 1V/mV +3V –3V RG 8.25kΩ 24.9kΩ 24.9kΩ AD705J G = 143 C1 1MΩ R4 10kΩ R1 R3 R2 OUTPUT AMPLIFIER PATIENT/CIRCUIT PROTECTION/ISOLATION 00775-0-043 Figure 39. A Medical ECG Monitor Circuit AD620 Rev. H | Page 15 of 20 Precision V-I Converter The AD620, along with another op amp and two resistors, makes a precision current source (Figure 40). The op amp buffers the reference terminal to maintain good CMR. The output voltage, VX, of the AD620 appears across R1, which converts it to a current. This current, less only the input bias current of the op amp, then flows out to the load. RG AD620 –VS VIN+ VIN– LOAD R1 IL Vx I L = R1 = IN+ [(V ) – (V IN – )] G R1 6 5 + VX – 2 4 1 8 3 7 +VS AD705 00775-0-044 Figure 40. Precision Voltage-to-Current Converter (Operates on 1.8 mA, ±3 V) GAIN SELECTION The AD620 gain is resistor-programmed by RG, or more precisely, by whatever impedance appears between Pins 1 and 8. The AD620 is designed to offer accurate gains using 0.1% to 1% resistors. Table 5 shows required values of RG for various gains. Note that for G = 1, the RG pins are unconnected (RG = ∞). For any arbitrary gain, RG can be calculated by using the formula: 1 49.4 − Ω = G k RG To minimize gain error, avoid high parasitic resistance in series with RG; to minimize gain drift, RG should have a low TC—less than 10 ppm/°C—for the best performance. Table 5. Required Values of Gain Resistors 1% Std Table Value of RG(Ω) Calculated Gain 0.1% Std Table Value of RG(Ω ) Calculated Gain 49.9 k 1.990 49.3 k 2.002 12.4 k 4.984 12.4 k 4.984 5.49 k 9.998 5.49 k 9.998 2.61 k 19.93 2.61 k 19.93 1.00 k 50.40 1.01 k 49.91 499 100.0 499 100.0 249 199.4 249 199.4 100 495.0 98.8 501.0 49.9 991.0 49.3 1,003.0 INPUT AND OUTPUT OFFSET VOLTAGE The low errors of the AD620 are attributed to two sources, input and output errors. The output error is divided by G when referred to the input. In practice, the input errors dominate at high gains, and the output errors dominate at low gains. The total VOS for a given gain is calculated as Total Error RTI = input error + (output error/G) Total Error RTO = (input error × G) + output error REFERENCE TERMINAL The reference terminal potential defines the zero output voltage and is especially useful when the load does not share a precise ground with the rest of the system. It provides a direct means of injecting a precise offset to the output, with an allowable range of 2 V within the supply voltages. Parasitic resistance should be kept to a minimum for optimum CMR. INPUT PROTECTION The AD620 safely withstands an input current of ±60 mA for several hours at room temperature. This is true for all gains and power on and off, which is useful if the signal source and amplifier are powered separately. For longer time periods, the input current should not exceed 6 mA. For input voltages beyond the supplies, a protection resistor should be placed in series with each input to limit the current to 6 mA. These can be the same resistors as those used in the RFI filter. High values of resistance can impact the noise and AC CMRR performance of the system. Low leakage diodes (such as the BAV199) can be placed at the inputs to reduce the required protection resistance. AD620 R REF R +SUPPLY –SUPPLY VOUT +IN –IN 00775-0-052 Figure 41. Diode Protection for Voltages Beyond Supply RF INTERFERENCE All instrumentation amplifiers rectify small out of band signals. The disturbance may appear as a small dc voltage offset. High frequency signals can be filtered with a low pass R-C network placed at the input of the instrumentation amplifier. Figure 42 demonstrates such a configuration. The filter limits the input AD620 Rev. H | Page 16 of 20 signal according to the following relationship: 2 (2 ) 1 D C DIFF R C C FilterFreq π + = C CM RC FilterFreq π = 2 1 where CD ≥10CC. CD affects the difference signal. CC affects the common-mode signal. Any mismatch in R × CC degrades the AD620 CMRR. To avoid inadvertently reducing CMRR-bandwidth performance, make sure that CC is at least one magnitude smaller than CD. The effect of mismatched CCs is reduced with a larger CD:CC ratio. 499Ω AD620 + – VOUT R R CC CD CC +IN –IN REF –15V 0.1μ F 10μ F +15V 0.1μ F 10μ F 00775-0-045 Figure 42. Circuit to Attenuate RF Interference COMMON-MODE REJECTION Instrumentation amplifiers, such as the AD620, offer high CMR, which is a measure of the change in output voltage when both inputs are changed by equal amounts. These specifications are usually given for a full-range input voltage change and a specified source imbalance. For optimal CMR, the reference terminal should be tied to a low impedance point, and differences in capacitance and resistance should be kept to a minimum between the two inputs. In many applications, shielded cables are used to minimize noise; for best CMR over frequency, the shield should be properly driven. Figure 43 and Figure 44 show active data guards that are configured to improve ac common-mode rejections by “bootstrapping” the capacitances of input cable shields, thus minimizing the capacitance mismatch between the inputs. REFERENCE VOUT AD620 100Ω 100Ω – INPUT + INPUT AD648 RG –VS +VS –VS 00775-0-046 Figure 43. Differential Shield Driver 100Ω – INPUT + INPUT REFERENCE VOUT AD620 –VS +VS 2 RG 2 RG AD548 00775-0-047 Figure 44. Common-Mode Shield Driver GROUNDING Since the AD620 output voltage is developed with respect to the potential on the reference terminal, it can solve many grounding problems by simply tying the REF pin to the appropriate “local ground.” To isolate low level analog signals from a noisy digital environment, many data-acquisition components have separate analog and digital ground pins (Figure 45). It would be convenient to use a single ground line; however, current through ground wires and PC runs of the circuit card can cause hundreds of millivolts of error. Therefore, separate ground returns should be provided to minimize the current flow from the sensitive points to the system ground. These ground returns must be tied together at some point, usually best at the ADC package shown in Figure 45. DIGITAL P.S. C +5V ANALOG P.S. +15V C –15V AD574A DIGITAL DATA OUTPUT + 1μF AD620 0.1μF AD585 S/H ADC 0.1μF 1μF 1μF 00775-0-048 Figure 45. Basic Grounding Practice AD620 Rev. H | Page 17 of 20 GROUND RETURNS FOR INPUT BIAS CURRENTS VOUT – INPUT + INPUT RG LOAD TO POWER SUPPLY GROUND REFERENCE +VS –VS AD620 00775-0-050 Input bias currents are those currents necessary to bias the input transistors of an amplifier. There must be a direct return path for these currents. Therefore, when amplifying “floating” input sources, such as transformers or ac-coupled sources, there must be a dc path from each input to ground, as shown in Figure 46, Figure 47, and Figure 48. Refer to A Designer’s Guide to Instrumentation Amplifiers (free from Analog Devices) for more information regarding in-amp applications. AD620 VOUT – INPUT RG TO POWER SUPPLY GROUND + INPUT REFERENCE +VS –VS LOAD 00775-0-049 Figure 47. Ground Returns for Bias Currents with Thermocouple Inputs 100kΩ AD620 VOUT – INPUT + INPUT RG LOAD TO POWER SUPPLY GROUND REFERENCE 100kΩ –VS +VS 00775-0-051 Figure 46. Ground Returns for Bias Currents with Transformer-Coupled Inputs Figure 48. Ground Returns for Bias Currents with AC-Coupled Inputs AD620 Rev. H | Page 18 of 20 AD620ACHIPS INFORMATION Die size: 1803 μm × 3175 μm Die thickness: 483 μm Bond Pad Metal: 1% Copper Doped Aluminum To minimize gain errors introduced by the bond wires, use Kelvin connections between the chip and the gain resistor, RG, by connecting Pad 1A and Pad 1B in parallel to one end of RG and Pad 8A and Pad 8B in parallel to the other end of RG. For unity gain applications where RG is not required, Pad 1A and Pad 1B must be bonded together as well as the Pad 8A and Pad 8B. 1A 1B 2 3 4 5 6 7 8A 8B LOGO 00775-0-053 Figure 49. Bond Pad Diagram Table 6. Bond Pad Information Pad Coordinates1 Pad No. Mnemonic X (μm) Y (μm) 1A RG −623 +1424 1B RG −789 +628 2 −IN −790 +453 3 +IN −790 −294 4 −VS −788 −1419 5 REF +570 −1429 6 OUTPUT +693 −1254 7 +VS +693 +139 8A RG +505 +1423 8B RG +693 +372 1 The pad coordinates indicate the center of each pad, referenced to the center of the die. The die orientation is indicated by the logo, as shown in Figure 49. AD620 Rev. H | Page 19 of 20 OUTLINE DIMENSIONS COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. 070606-A 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) SEATING PLANE 0.015 (0.38) MIN 0.210 (5.33) MAX 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 8 1 4 5 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.100 (2.54) BSC 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 0.060 (1.52) MAX 0.430 (10.92) MAX 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE 0.005 (0.13) MIN Figure 50. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8). Dimensions shown in inches and (millimeters) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 0.310 (7.87) 0.220 (5.59) 0.005 (0.13) MIN 0.055 (1.40) MAX 0.100 (2.54) BSC 15° 0° 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) SEATING 0.008 (0.20) PLANE 0.200 (5.08) MAX 0.405 (10.29) MAX 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 1 4 8 5 Figure 51. 8-Lead Ceramic Dual In-Line Package [CERDIP] (Q-8) Dimensions shown in inches and (millimeters) CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. COMPLIANT TO JEDEC STANDARDS MS-012-AA 012407-A 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 1.75 (0.0688) 1.35 (0.0532) SEATING PLANE 0.25 (0.0098) 0.10 (0.0040) 1 4 8 5 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) BSC 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) COPLANARITY 0.10 Figure 52. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) AD620 Rev. H | Page 20 of 20 ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD620AN −40°C to +85°C 8-Lead PDIP N-8 AD620ANZ −40°C to +85°C 8-Lead PDIP N-8 AD620BN −40°C to +85°C 8-Lead PDIP N-8 AD620BNZ −40°C to +85°C 8-Lead PDIP N-8 AD620AR −40°C to +85°C 8-Lead SOIC_N R-8 AD620ARZ −40°C to +85°C 8-Lead SOIC_N R-8 AD620AR-REEL −40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8 AD620ARZ-REEL −40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8 AD620AR-REEL7 −40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8 AD620ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8 AD620BR −40°C to +85°C 8-Lead SOIC_N R-8 AD620BRZ −40°C to +85°C 8-Lead SOIC_N R-8 AD620BR-REEL −40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8 AD620BRZ-RL −40°C to +85°C 8-Lead SOIC_N, 13" Tape and Reel R-8 AD620BR-REEL7 −40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8 AD620BRZ-R7 −40°C to +85°C 8-Lead SOIC_N, 7" Tape and Reel R-8 AD620ACHIPS −40°C to +85°C Die Form AD620SQ/883B −55°C to +125°C 8-Lead CERDIP Q-8 1 Z = RoHS Compliant Part. © 2003–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00775–0–7/11(H) a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 1 of 18 a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 2 of 18 Table of Contents SUMMARY...................................................................................................................... 3 1 DEAD TIME EFFECTS AND THEIR COMPENSATION .......................................... 3 2 IMPLEMENTATION OF THE FEED FORWARD DEAD TIME COMPENSATION .. 5 2.1 Using the dt_comp routines ...........................................................................................................................5 2.2 Using the dt_comp routine.............................................................................................................................6 2.3 The program code...........................................................................................................................................7 3 EXAMPLE: TESTING THE VALIDITY OF THE FEED FORWARD DEAD TIME COMPENSATION........................................................................................................... 7 3.1 The construction of an inverter .....................................................................................................................7 3.2 The software program used to test the feed forward dead time compensation.........................................8 3.3 The main include file: main.h ......................................................................................................................12 3.4 The program offset.dsp and its header offset.h..........................................................................................12 3.5 Experimental results.....................................................................................................................................16 4 REFERENCES ....................................................................................................... 18 a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 3 of 18 Summary Due to the finite switching time, in order to prevent the appearance of short circuits, the power devices of an inverter must be commanded introducing a delay between their active times. This delay, called dead time because in this period no power device is active, introduces small voltage errors, which are sufficient to produce distorted motor currents, oscillations of the motor torque and therefore even the motor controllability may be lost [1]. This paper presents one method to compensate the effects of the dead time, the experimental hardware on which this method was tested and the assembly program associated with it. 1 Dead Time effects and their compensation Consider a voltage inverter with a motor connected at its output terminals (Figure 1). d V T1 T 2 T 3 T 4 T 5 T 6 D1 D2 D4 D6 D3 D5 0 1 ≥ s i 1 v Figure 1: Voltage source inverter The effects of the dead time may be examined by considering only the first phase of the inverter. On this phase it is desired to obtain the reference PWM signal * 1 v presented in Figure 2a. The signals used to command the power devices are assumed to be active LOW, which means that when they are LOW, the power devices conduct (Figures 2b and 2c). The output signal obtained at the motor terminal depends on the sense of the current flowing in this phase: In the case of the current flowing from inverter to the motor (assumed positive sense), when T2 conducts, the phase terminal is linked to the GND and the voltage 1 v is 0. During the dead time period, when both power devices are turned OFF, the current continues to flow into the motor using the reverse recovery diode D2, so 1 v will continue to be 0. When the upper power device T1 conducts, the phase terminal is connected to d V and 1 v is equal to d V . During the second half cycle, the phenomenon repeats itself a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 4 of 18 symmetrically. The final behaviour of 1 v is presented in Figure 2d. It may be observed that the average value of 1 v is less than the reference value by an amount determined by the dead time: d s V T DT v = v − ⋅ * 1 1 (1) DT DT 2 DT 2 s T * 1 v T1 T 2 0 1 1 ≥ s i v when 0 1 1 < s i v when a) b) c) d) e) d V d V * 1 T Figure 2: The influence of the dead time over the output phase voltage In the case of the current flowing from the motor to the inverter, when T2 conducts, the phase terminal is linked to the GND and the voltage 1 v is 0. During the dead time period, the current continues to flow from the motor using the reverse recovery diode D1, so 1 v will become equal to d V . When the upper power device T1 conducts, the phase terminal is connected to d V and 1 v will continue to be equal to d V . During the second half, the phenomenon repeats itself symmetrically. The final behaviour of 1 v is presented in Figure 2e. It may be observed that the average value of 1 v is greater than the reference value by an amount determined by the dead time: a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 5 of 18 d s V T DT v = v + ⋅ * 1 1 (2) Equations (1) and (2) provide the first method to compensate for the dead time: the feed-forward compensation. In relation of the current sense, the inverter phase will be commanded with a reference voltage ** 1 v such that the voltage 1 v at the inverter terminal will become equal with the reference voltage * 1 v : d s V T DT v = v + ⋅ * 1 ** 1 when i ≥ 0 (3) d s V T DT v = v − ⋅ * 1 ** 1 when i < 0 . These expressions mean that when the phase current is positive, the duty cycle * 1 T correspondent to * 1 v has to be increased by the dead time and when the phase current is negative, the duty cycle has to be decreased by the dead time. The only drawback of this method appears when the current changes its sign, because this moment cannot be foreseen. It is easily seen that when the sign is not correctly applied, an error of two times the dead time is introduced. Another method to compensate the dead time is the following: The actual inverter voltages are measured on every phase. The compensation is done adding to the reference phase voltage * 1 v a term proportional to the voltage error on that phase: ( 1) ( 1) [ ( ) ( )] 1 * 1 * 1 ** 1 v k + = v k + + K ⋅ v k − v k (4) where: - ** ( 1) 1 v k + is the voltage which will be commanded on the first inverter phase; - * ( 1) 1 v k + is the reference voltage which would have been commanded if the dead time compensation had not been considered; -K is the gain of the compensator, usually less than or equal to 1; - * ( ) 1 v k is the reference voltage which would have been commanded during the previous PWM cycle if the dead time compensation had not been considered; - ( ) 1 v k is the inverter phase voltage measured during the previous PWM cycle. The drawback of this method is that all the inverter phase voltages have to be measured. It is possible to measure only two inverter phases if the PWM modulation is space vector type or sinusoidal. 2 Implementation of the feed forward dead time compensation 2.1 Using the dt_comp routines The routines are developed as an easy-to-use library, which has to be linked to the user’s application. The library consists of two files. The file “dt_comp.dsp” contains the assembly code of the subroutines. The block has to be compiled and then linked to an application. The user has to include the header file dt_comp.h, which provides the function-like calls to the subroutines. The example file in Section 3 will demonstrate the usage of all the routines. a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 6 of 18 Operation Usage Compute On-times compensating the dead time DeadTime_Comp(StatorCurrent_struct, Dutycycles_struct) Table 1 Implemented routine The input vector StatorCurrents_struct consists of three elements, the three inverter phase currents. Because their sum is always zero, only two of them need to be measured. They have to be scaled because the DSP uses fixed point formats. The scaling factor is 2⋅ Imax , where max I represents the maximum current which may be placed at the input pin of the A/D converter. The 2 factor is used to prevent overflows when the currents are used in arithmetical operations. The vector Dutycycles_struct is an input and also an output: It represents the duty cycles for each phase, previously computed by the PWM modulator. After the compensation, they represent the duty cycles effectively commanded to the inverter. Their values have to be between 0 and PWMTM, the number which controls the PWM switching frequency. DeadTime_comp represents a macro, which must be introduced into the program code if the dead time compensation is desired. The format of inputs and outputs are explained in more detail in the next section. The routines do not require any configuration constants from the main include-file “main.h” that comes with every application note. For more information about the general structure of the application notes and including libraries into user applications refer to the Library Documentation File. Section 2.2 shows an example of usage of this library. In the following sections each routine is explained in detail with the relevant segments of code which is found in either “dt_comp.h” or “dt_comp.dsp”. For more information see the comments in those files. 2.2 Using the dt_comp routine The macro listed in the Table 1 is based on a subroutine called DeadTime_Comp_. It is described in detail in the next section. The following table gives an overview of what DSP registers are used in this macro: Macro Input1 and modified DAG registers Output2 Modified core registers DeadTime_Comp I1 = ^ StatorCurrents_struct; M1, M2 = 1; L1, L2 = 0; I2 = ^ Dutycycles_struct; M3 = 0; N/A AX0, AY0, AY1, MR, AR Table2. DSP core registers used in the macro This macro has to be placed in the main program after the PWM reference duty cycles are computed, but prior to the program that saves them into the duty cycle registers PWMCHA, PWMCHB, PWMCHC. 1 ^vector stands for ‘address of vector’. 2 N/A: The output values are stored in the output vector in the Data memory. No DSP core register is used. a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 7 of 18 2.3 The program code The following code contained in the file dt_comp.dsp describes the routine DeadTime_Comp_ mentioned in the previous section. The routine is organised as a loop managed by the loop counter cntr. At each iteration, one phase current from the buffer StatorCurrents_struct is tested and the compensation is done function of its sign. In the end, the new duty cycle number is tested to ensure it is positive and less than the maximum admissible value, PWMTM. The last instruction saves the number back into the buffer Dutycycles_struct. DeadTime_Comp_: AY0 = DM(PWMDT); { dead time normalized } AY1 = dm(PWMTM); CNTR = 3; do dead_loop until ce; ax0 = DM(I1, M1); { ax0 = Isk, k=1,2,3 } mr1 = DM(I2, M3); { load Ta, Tb, Tc } AR = MR1 + AY0; none = pass ax0; {chek sign of the currents } IF LT AR = MR1 - AY0; none = pass AR; if lt AR = PASS 0; { no negative values admitted} af = AR - AY1; if gt ar = pass ay1; { protection against overflows} dead_loop: DM(I2, M2) = ar; rts; 3 Example: Testing the validity of the feed forward dead time compensation 3.1 The construction of the inverter The proposed compensation method was implemented on the ADMC331 Processor Board mounted on an ADMC Connector Board. As inverter power part was used an evaluation platform produced by International Rectifier, IRPT2056D Driver-Plus Board. It is a three phase 230VAC 3HP board and it integrates all the processing components needed for a 3 HP motor drive. It is equipped with an IRPT2056A IGBT power module and an IR2133J driver. The Analog Devices’ ADMC PWM isolation board linked the Connector Board to the Power Board. This board produces an electric isolation between the digital part and the inverter power part and also inverts the signals used to drive the power devices (74HC240). Because the signals used by the driver IR2133J are active LOW and because of the inverting line driver HC240, the PWM outputs of the ADMC331 are set to be active HIGH. Therefore the jumper JP51 is in position 1-2. 1 See the ADMC331 Processor Board manual, Motion Control Group, Analog Devices, 1998 a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 8 of 18 The inverter is driving an induction motor with the following characteristics: .13HP, 230V, 60Hz, 1725rpm, produced by Baldor. Because the power part is supplied with 110V, the maximum frequency the motor may be run in the constant torque regime is: c f 3 110 2 60 3 230 2 ⋅ = ⋅ f Hz c 28.7 230 110 60 = ⋅ = Because the compensation needs the value of the inverter phase currents, two of them were sensed using current transducers HA 10-NP produced by LEM. They are capable to measure up to 20A and this value is used to scale down the measured values: I 20A max = . Also, an operational amplifier LM348 is used to obtain the signal into the range of A/D converter of ADMC331: 0.3V÷3.5V. On the ADMC331 Processor Board there are 5KHz filters that have an anti-aliasing role. A block structure of the inverter is presented in Figure 3. ADMCConnector Board ADMC331 Processor Board IRPT2056D Driver Plus Board ADMC PWM Isolation Board .13HP Induction Motor 2xHP10-NP s1 I s 2 I Figure 3. Inverter Block structure 3.2 The software program used to test the feed forward dead time compensation The purpose of this program is to demonstrate the improvement offered by the feed forward dead time compensation. It reads two motor currents, commands the motor to run at 14Hz, half of the cut frequency c f and compensates for the dead time. The file main.dsp contains the root program. The batch file build.bat compiles every file of the project, links them together and builds the executable file main.exe. It may be applied either within DOS prompt or clicking on it from Windows Explorer. Main.exe may be run on the Motion Control Debugger. A brief description of the program will be given in the following: Start of code - declaring start location in program memory .MODULE/RAM/SEG=USER_PM1/ABS=0x30 Main_Program; a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 9 of 18 Next, the general systems constants and PWM configuration constants (main.h – see the next section) are included. Also included are the PWM library2, the DAC interface3 and the space vector modulation4 module definitions. The header file offset.h declares some macros used to measure the offset introduced by the current transducers and autocal.h declares the macros used to calibrate the ADMC331 A/D converter. {*************************************************************************************** * Include General System Parameters and Libraries * ***************************************************************************************} #include ; #include ; #include ; #include ; #include ; #include ; #include ; #include ; #include ; { Application Specific Module } #include ; #include ; #include ; Constants used in this program {*************************************************************************************** * Constants Defined in the Module * ***************************************************************************************} .CONST CUT_FREQ = 28; {the cutting frequency of the tested motor} .CONST Delta = 32768*2*CUT_FREQ/PWM_freq; {the increment of the angle} .CONST TwoPiOverThree = 0xffff / 3; { Hex equivalent of 2pi/3 } .CONST ALLOFF = 0x3F; { Used to disable IGBTies into PWMSEG } Here is where all the vectors for the program are declared. The buffer StatorCurrents_struct represents the three stator currents. The PWM duty cycles are stored in the buffer Dutycycles_struct and they are initialised with 0.It may be seen that the variables which identify the current offsets, Is1Offset and Is2Offset are declared circular because programming becomes easier. The average of the readings is computed on 32bit precision, so every buffer consists of 2 words. {*************************************************************************************** * Local Variables Defined in this Module * ***************************************************************************************} .VAR/DM/RAM/SEG=USER_DM AD_IN; { Volts/Hertz Command (0-1) } 2 see AN331-03: Three-Phase Sine-Wave Generation using the PWM Unit of the ADMC331 3 see AN331-06: Using the Serial Digital to Analog Converter of the ADMC Connector Board 4 see AN331-17: Implementing Space Vector Modulation with the ADMC331 a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 10 of 18 .INIT AD_IN : 0x3A0A; { Corresponds to 0.906/2 } .VAR/DM/RAM/SEG=USER_DM Theta; { Current angle } .INIT Theta : 0x0000; .VAR/DM/RAM/SEG=USER_DM Vdq_ref[2]; { rotor ref.frame } .VAR/DM/RAM/CIRC/SEG=USER_DM Valphabeta_ref[2]; { alphabeta frame } .VAR/RAM/DM/SEG=USER_DM OnTime_struct[1*4]; .INIT OnTime_struct: 0x0000, 0x0000, 0x0000, 0x0000; .VAR/RAM/DM/SEG=USER_DM Dutycycles_struct[1*3]; .INIT Dutycycles_struct: 0x0000, 0x0000, 0x0000; .VAR/DM/RAM/SEG=USER_DM VrefA; { Voltage demands } .VAR/DM/RAM/SEG=USER_DM VrefB; .VAR/DM/RAM/SEG=USER_DM VrefC; .INIT VrefA : 0x0000; .INIT VrefB : 0x0000; .INIT VrefC : 0x0000; .VAR/DM/RAM/SEG=USER_DM StatorCurrents_struct[1*3]; { stator currents } .VAR/DM/RAM/SEG=USER_DM Is1Offset[1]; .VAR/DM/RAM/SEG=USER_DM Is2Offset[1]; When the program begins, the PWM output signals are disabled. Then, the power module is reset and the PWM block is set up to generate interrupts every 100μsec (see main.h in the next section). There is initialised the D/A serial converter1 and there is unmasked the IRQ2 interrupt (the interrupt which manages the peripheral interrupts on ADMC331). The main loop just waits for interrupts. {********************************************************************************************} { Start of program code } {********************************************************************************************} Startup: Write_DM(PWMSEG, ALLOFF); { the IGBTies are disabled } IR_reset_PIO3; { Reset PowIRTrain Module } PWM_Init(PWMSYNC_ISR, PWMTRIP_ISR); DAC_Init; { Initialize the DAC-Module } IFC = 0x80; { Clear any pending IRQ2 inter. } ay0 = 0x200; { unmask irq2 interrupts. } ar = IMASK; ar = ar or ay0; 1 See ADMC Connector board user’s manual for further details a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 11 of 18 IMASK = ar; { IRQ2 ints fully enabled here } ADC_Init; { ADC Counter will Operate at the DSP CLKOUT Frequency } AutoCal_Init; { Initialize the Auto Calibration Routine } Offset_Init; { offset.h } Main: { Wait for interrupt to occur } jump Main; During the PWM_SYNC interrupt there are executed some routines which determine the internal offset of the A/D converter1, the external offsets introduced by the current transducers and the measurement of the currents. The successive routines generate three PWM signals of 14Hz obtained applying a continuous space vector modulation2. The dead time compensation is placed at the end of this block. Finally, the signals that will be provided to the D/A converter are computed. {********************************************************************************************} { PWM Interrupt Service Routine } {********************************************************************************************} PWMSYNC_ISR: Auto_Calibrate; { autocal.h } OffsetDetermination(ADC1, ADC2, Is1Offset, Is2Offset); { offset.h } ReadCurrents(Is1Offset, Is2Offset, StatorCurrents_struct, ADC1, ADC2); { offset.h } DAC_Pause; { Required only when I1, M1 or L1 is used} ar = DM (AD_IN ); mr = 0; {Clear mr } mr1 = dm(Theta); {Preload Theta} my0 = Delta; mr = mr + ar*my0 (SS); {Compute new angle & store} dm(Theta) = mr1; DM(Vdq_ref )= ar; {Set constant Vdq reference (AD_IN,0)} ar = pass 0; DM(Vdq_ref+1)= ar; refframe_Set_DAG_registers_for_transformations; refframe_Forward_Park_angle(Vdq_ref,Valphabeta_ref,mr1); {generate Vreference in alpha-beta frame} SVPWM_Calc_Ontimes(Valphabeta_ref, OnTime_struct); { use SVPWM routines} SVPWM_Calc_Dutycycles(OnTime_struct, Dutycycles_struct); DeadTime_Comp(StatorCurrents_struct, Dutycycles_struct); SVPWM_Update_DutyCycles(Dutycycles_struct); Dac_Resume; my0 = DM(Theta); DAC_Put(1, my0); { output on DACs, amplified by multiplication } mx0 = 0x8; my0 = DM(Dutycycles_struct ); mr = mx0 * my0 (SS); Dac_Put(2, mr0); my0 = DM(Dutycycles_struct+1); mr = mx0 * my0 (SS); Dac_Put(3, mr0); 1 See AN331-05: ADC-system on the ADMC331. 2 See AN331-17: Implementing Space Vector Modulation with ADMC331 a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 12 of 18 AX0 = dm(Dutycycles_struct); AY0 = Half_PWMTM; AR = AX0 - AY0; MY0 = 0x6523; {2/PWMTM=2/1296*2^15/2^6*2^15} MR = AR * MY0 (SS); SR = ASHIFT MR1 BY 6 (HI); SR = SR OR LSHIFT MR0 BY 6 (LO); DAC_Put(4, SR1); sr1 = DM(StatorCurrents_struct); sr = ASHIFT sr1 BY 5 (HI); DAC_Put(5,sr1); sr1 = DM(StatorCurrents_struct+1); sr = ASHIFT sr1 BY 5 (HI); DAC_Put(6, sr1); SR1 = DM(StatorCurrents_struct+2); sr = ASHIFT sr1 BY 5 (HI); DAC_Put(7, sr1); DAC_Update; RTI; 3.3 The main include file: main.h This file contains the definitions of ADMC331 constants, general-purpose macros, the configuration parameters of the system and library routines. It should be included in every application. For more information refer to the Library Documentation File. This file is mostly self-explaining. As already mentioned, the dt_comp library does not require any configuration parameters. The following table presents the parameters used to initialise the PWM block .It may be emphasized the dead time period set at 6μsec, a large value for the power devices used on the IRPT2056D. {********************************************************************************************} { Library: PWM block } { file : PWM331.dsp } { Application Note: Usage of the ADMC331 Pulse Width Modulation Block } .CONST PWM_freq = 10000; {Desired PWM switching frequency [Hz] } .CONST PWM_deadtime = 6000; {Desired deadtime [nsec] } .CONST PWM_minpulse = 1000; {Desired minimal pulse time [nsec] } .CONST PWM_syncpulse = 1540; {Desired sync pulse time [nsec] } .CONST Half_PWMTM = 1000*Cry_clock/PWM_freq/2; {********************************************************************************************} 3.4 The program offset.dsp and its header offset.h The current transducers introduce an offset that has to be evaluated, otherwise the sign of the currents would be determined with large errors. For this reason, at the beginning of the program, for a certain number of PWM cycles (in this particular case 128, but may be more or less depending on the system) there are measured the A/D channels corresponding to the two phase currents, V1 and V2. The average of all measurements constitutes the offset of that current. Of course, this procedure may be applied at every channel, if the signal is zero at the beginning of the program. The header file offset.h contains the macros that are used during this process. Generally, they call subroutines presented in the file offset.dsp. This file begins declaring the variables OffsetCounter, TempOffset1 and TempOffset2 used in these routines. a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 13 of 18 {*************************************************************************************** * Global Variables Defined in this Module * ***************************************************************************************} .VAR/DM/RAM/SEG=USER_DM OffsetCounter[1]; .GLOBAL OffsetCounter; .VAR/DM/RAM/CIRC/SEG=USER_DM TempOffset1[2]; .GLOBAL TempOffset1; .VAR/DM/RAM/CIRC/SEG=USER_DM TempOffset2[2]; .GLOBAL TempOffset2; The subroutine Offset_Init_ initialises the variables used to evaluate the offsets of the current transducers. OffsetCounter is set to 128 because the offsets are considered the average of 128 measurements. {************************************************************************************* * Type: Routine * * Call: Call Offset_Init_; * * This subroutine initializes the variables initializes variables used to * * evaluate the offsets of the current sensors * * Inputs : None * * Ouputs :None * * Modified: AR * ***************************************************************************************} Offset_Init_: AR = Offset_Average; dm(OffsetCounter) = AR; AR = 0x0; dm(TempOffset1) = AR; dm(TempOffset1+1) = AR; dm(TempOffset2) = AR; dm(TempOffset2+1) = AR; rts; The subroutine EvaluateIs_offset_ computes the average of the measurements of a particular A/D channel. {*************************************************************************************** * Type: Routine * * Call: Call EvaluateIs_offset_; * * This subroutine computes the average of the measurements of one A/D channel * * Inputs : AR = the lecture of the A/D channel * I1 = placed at the begining of the buffer which is averaged * * M1 = 0, L1 = 0 * * Ouputs :None * * Modified: AY1, AY0, AR, SR, AX0 * ***************************************************************************************} EvaluateIs_offset_: AY1 = dm(I1, M1); a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 14 of 18 AY0 = dm(I1, M1); AR = 0x4000 - AR; SR = ASHIFT AR BY -7 (HI); AR = SR0 + AY0; AX0 = AR, AR = SR1 + AY1 + C; dm(I1, M1) = AR; dm(I1, M1) = AX0; RTS; . In the file offset.h there is a macro Offset_Init that initialises the address generators at the current offsets buffers and then calls the subroutine Offset_Init_ from offset.dsp. {*************************************************************************************** * Type: Macro * * Call: Offset_Init; * * This macro initializes variables used to evaluate the offsets of the current sensors * * Input: none * * Output: none * * Modified: AR * ***************************************************************************************} .MACRO Offset_Init; CALL Offset_Init_; .ENDMACRO; The macro EvaluateIs_offset reads one A/D channel and computes the average offset of that channel calling the subroutine EvaluateIs_offset_. {*************************************************************************************** * Type: Macro * * Call: EvaluateIs_offset; * * Routine to compute the offset of one phase * * Input: %0=the targeted AD channel * * %1=the offset structure dedicated to the phase * * %1=most significant word * * %1+1=less significant word * * Output: Current Offset structure * * Modified: * ***************************************************************************************} .MACRO EvaluateIs_offset(%0, %1); ADC_Read(%0); I1 = ^%1; M1 = 1; L1 = %%1; a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 15 of 18 CALL EvaluateIs_offset_; .ENDMACRO; The macro OffsetDetermination computes the offsets of the both A/D channels that measure the phase currents. {*************************************************************************************** * Type: Macro * * Call: OffsetDetermination * * Routine to compute the offsets introduced by the current sensors * * Input: %0=ADC1 * * %1=ADC2 * * %2=Is1Offset * * %3=Is2Offset * * Output: Current Offsets structure * * Modified: * ***************************************************************************************} .MACRO OffsetDetermination(%0, %1, %2, %3); AY0 = dm(OffsetCounter); AR = AY0 - 1; IF LT JUMP SaveOffsets; dm(OffsetCounter) = AR; EvaluateIs_offset(%0, TempOffset1); EvaluateIs_offset(%1, TempOffset2); RTI; SaveOffsets: AF = AR + 1; IF NE JUMP ExitOffsetDet; dm(OffsetCounter) = AR; AR = dm(TempOffset1); dm(%2) = AR; AR = dm(TempOffset2); dm(%3) = AR; ExitOffsetDet: .ENDMACRO; The macro ReadCurrents reads the two phase currents, corrects them with the offset and finally computes the third phase current. It may be noted that the output of the A/D converter is always a positive number. Because of the presence of an inverting operational amplifier in the hardware, in order to obtain values between –1/2 and +1/2 (in fixed point the currents are scaled by 2⋅ Imax ) the outputs of the A/D converter have to be offset by 1/2 (0x4000). {*************************************************************************************** * Type: Macro * * Call: ReadCurrents; * a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 16 of 18 * This macro reads ADC1(Is1), ADC2(Is2) and then evaluates Is1, Is2 and Is3 * * Input: %0 = offset of the first phase current * * %1 = offset of the second phase current * * %2 = the buffer of the 3 phase currents * * %3 = ADC1 * * %4 = ADC2 * * Output: none * * Modified: AY0, AR, MY0, MR, SR ,AF * ***************************************************************************************} .MACRO ReadCurrents(%0, %1, %2, %3, %4); ADC_Read(%3); { read Is1/Imax } AR = 0x4000 - AR; AY0 = dm(%0); AR = AR - AY0; dm(%2) = AR; { Is1/2Imax } ADC_Read(%4); { read Is2/Imax } AR = 0x4000 - AR; AY0 = dm(%1); AR = AR - AY0; dm(%2+1) = AR; { Is2/2Imax } AR = -AR; AY0 = dm(%2); { Is1/2Imax } AR = AR - AY0; dm(%2+2) = AR; { Is3/2Imax=-Is2/2Imax-Is1/2Imax} .ENDMACRO; 3.5 Experimental results First of all, experiments without the dead time compensation were made. Figure 4 represents the inverter phase voltage compared to the reference voltage that is desired at the inverter terminal and the phase current. It may be seen that the behavior presented in chapter 1 is verified in practice: When the phase current is positive, the real inverter phase voltage is less than the commanded one by an amount determined by the dead time and when the phase current is negative, the real inverter phase voltage is greater than the commanded. At last, Figure 5 displays the inverter phase voltage and the phase current obtained with the feed forward dead time compensation. It may be observed that the voltage still presents some distortions caused by the nature of feed forwarding: it is supposed that the current measured during the previous PWM cycle maintains its sign into the next PWM cycle; when the current changes the sign, this moment cannot be foreseen and the error is doubled. These voltage deformations cause also deformations in the current behaviour, and they may be prevented only implementing current controllers in a more accurate control strategy, like field-oriented control. a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 17 of 18 Figure 4. Reference and real inverter phase voltages and the phase current a Compensating the dead time of voltage inverters with the ADMC331 AN331-50 © Analog Devices Inc., August 2000 Page 18 of 18 Figure 5. Inverter phase voltage and phase current after the dead time compensation 4 References [1] Pulse dead time compensator for PWM voltage inverters, David Leggate, Russel J. Kerkman, Industrial Electronics, Control, and Instrumentation, 1995, Proceedings of the 1995 IEEE IECON 21st International Conference on Volume: 1, Page(s): 474 -481 vol.1. SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 􀀀 Wide Operating Voltage Range of 2 V to 6 V 􀀀 Typical Switch Enable Time of 18 ns 􀀀 Low Power Consumption, 20-μA Max ICC 􀀀 Low Input Current of 1 μA Max 􀀀 High Degree of Linearity 􀀀 High On-Off Output-Voltage Ratio 􀀀 Low Crosstalk Between Switches 􀀀 Low On-State Impedance . . . 50-Ω TYP at VCC = 6 V 􀀀 Individual Switch Controls description/ordering information The SN74HC4066 is a silicon-gate CMOS quadruple analog switch designed to handle both analog and digital signals. Each switch permits signals with amplitudes of up to 6 V (peak) to be transmitted in either direction. Each switch section has its own enable input control (C). A high-level voltage applied to C turns on the associated switch section. Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP – N Tube of 25 SN74HC4066N SN74HC4066N Tube of 50 SN74HC4066D SOIC – D Reel of 2500 SN74HC4066DR HC4066 Reel of 250 SN74HC4066DT –40°C to 85°C SOP – NS Reel of 2000 SN74HC4066NSR HC4066 SSOP – DB Reel of 2000 SN74HC4066DBR HC4066 Tube of 90 SN74HC4066PW TSSOP – PW Reel of 2000 SN74HC4066PWR HC4066 Reel of 250 SN74HC4066PWT † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each switch) INPUT CONTROL (C) SWITCH L OFF H ON PRODUCTION DATA information is current as of publication date. Copyright  2003, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1A 1B 2B 2A 2C 3C GND VCC 1C 4C 4A 4B 3B 3A D, DB, N, NS, OR PW PACKAGE (TOP VIEW) SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 logic diagram, each switch (positive logic) A VCC VCC B One of Four Switches C absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Control-input diode current, II (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA I/O port diode current, II (VI < 0 or VI/O > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA On-state switch current (VI/O = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground unless otherwise specified. 2. The package thermal impedance is calculated in accordance with JESD 51-7. SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 recommended operating conditions (see Note 3) MIN NOM MAX UNIT VCC Supply voltage 2† 5 6 V VI/O I/O port voltage 0 VCC V VCC = 2 V 1.5 VCC VIH High-level input voltage, control inputs VCC = 4.5 V 3.15 VCC V VCC = 6 V 4.2 VCC VCC = 2 V 0 0.3 VIL Low-level input voltage, control inputs VCC = 4.5 V 0 0.9 V VCC = 6 V 0 1.2 VCC = 2 V 1000 Δt/Δv Input transition rise/fall time VCC = 4.5 V 500 ns VCC = 6 V 400 TA Operating free-air temperature –40 85 °C † With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital signals be transmitted at these low supply voltages. NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS V TA = 25􀀀C VCC MIN MAX UNIT MIN TYP MAX I A V 0t V 2 V 150 ron On-state switch resistance IT = –1 mA, VI = 0 to VCC, 4.5 V 50 85 106 Ω VC = VIH (see Figure 1) 6 V 30 V V GND V V 2 V 320 ron(p) Peak on-state resistance VI = VCC or GND, VC = VIH, ( ) 4.5 V 70 170 215 Ω IT = –1 mA 6 V 50 II Control input current VC = 0 or VCC 6 V ±0.1 ±100 ±1000 nA Isoff Off-state switch leakage current VI = VCC or 0, VO = VCC or 0, VC = VIL (see Figure 2) 6 V ±0.1 ±5 μA Ison On-state switch leakage current VI = VCC or 0, VC = VIH (see Figure 3) 6 V ±0.1 ±5 μA ICC Supply current VI = 0 or VCC, IO = 0 6 V 2 20 μA Ci Input capacitance A or B 5 V 9 pF C 3 10 10 Cf Feed-through capacitance A to B VI = 0 0.5 pF Co Output capacitance A or B 5 V 9 pF SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended operating free-air temperature range PARAMETER FROM TO TEST VCC TA = 25􀀀C MIN MAX UNIT (INPUT) (OUTPUT) CONDITIONS MIN TYP MAX t P ti C 50 F 2 V 10 60 75 tPLH, Propagation A or B B or A CL = pF 4.5 V 4 12 15 ns tPHL delay time (see Figure 4) 6 V 3 10 13 t S it h RL = 1 kΩ, 2 V 70 180 225 tPZH, tPZL Switch turn-on time C A or B CL = 50 pF 4.5 V 21 36 45 ns L (see Figure 5) 6 V 18 31 38 t S it h RL = 1 kΩ, 2 V 50 200 250 tPLZ, Switch C A or B CL = 50 pF 4.5 V 25 40 50 ns tPHZ turn-off time L (see Figure 5) 6 V 22 34 43 Control CL = 15 pF, RL = 1 kΩ 2 V 15 fI input frequency C A or B kΩ, VC = VCC or GND, V V /2 4.5 V 30 MHz VO = VCC/(see Figure 6) 6 V 30 Control feed-through C A or B CL = 50 pF, Rin = RL = 600 Ω, VC = VCC or GND 4.5 V 15 mV noise GND, fin = 1 MHz (see Figure 7) 6 V 20 (rms) operating characteristics, VCC = 4.5 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance per gate CL = 50 pF, f = 1 MHz 45 pF Minimum through bandwidth, A to B or B to A† [20 log (VO/VI)] = –3 dB CL = 50 pF, VC = VCC RL = 600 Ω, (see Figure 8) 30 MHz Crosstalk between any switches‡ CL = 10 pF, fin = 1 MHz RL = 50 Ω, (see Figure 9) 45 dB Feed through, switch off, A to B or B to A‡ CL = 50 pF, fin = 1 MHz RL = 600 Ω, (see Figure 10) 42 dB Amplitude distortion rate, A to B or B to A CL = 50 pF, fin = 1 kHz RL = 10 kΩ, (see Figure 11) 0.05% † Adjust the input amplitude for output = 0 dBm at f = 1 MHz. Input signal must be a sine wave. ‡ Adjust the input amplitude for input = 0 dBm at f = 1 MHz. Input signal must be a sine wave. SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PARAMETER MEASUREMENT INFORMATION VCC VI = VCC VC = VIH + 1.0 mA – VO ron 􀀀 VI–O 10–3 􀀀 VI–O VCC GND (ON) V Figure 1. On-State Resistance Test Circuit VCC VC = VIL A B VS = VA – VB CONDITION 1: VA = 0, VB = VCC CONDITION 2: VA = VCC, VB = 0 VCC GND A (OFF) Figure 2. Off-State Switch Leakage-Current Test Circuit SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION VCC VC = VIH A B VCC Open VA = VCC TO GND VCC GND A (ON) Figure 3. On-State Leakage-Current Test Circuit VCC VC = VIH VI VO 50 pF TEST CIRCUIT tPLH tPHL 50% 50% VCC 0 V 50% 50% VOH VOL VI A or B VO B or A VOLTAGE WAVEFORMS 50 Ω tr 90% 10% tf 10% 90% VCC GND (ON) Figure 4. Propagation Delay Time, Signal Input to Signal Output SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PARAMETER MEASUREMENT INFORMATION CL GND 50 pF VCC VI VO TEST CIRCUIT tPLZ 50% VOLTAGE WAVEFORMS RL 1 kΩ 10% S1 VC 50 Ω S2 tPZH tPHZ 50% 50% 50% 90% tPZL tPZH tPLZ tPHZ GND VCC GND VCC TEST S1 S2 VCC GND VCC GND tPZL 50% VCC VO 50% 0 V VOL VOH VC (tPZL, tPZH) (tPLZ, tPHZ) VCC VCC VO 0 V VOL VOH VC VCC 0 V VOL VOH VCC 0 V VOL VOH Figure 5. Switching Time (tPZL, tPLZ, tPZH, tPHZ), Control to Signal Output SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION VCC GND VO RL 1 kΩ CL 15 pF VCC VC 50 Ω VI = VCC VCC VC 0 V VCC/2 Figure 6. Control-Input Frequency VCC GND VO RL 600 Ω CL 50 pF VCC VC 50 Ω VI VCC/2 Rin 600 Ω VCC/2 tr tf 90% 10% (f = 1 MHz) tr = tf = 6 ns 90% 10% VCC VC 0 V Figure 7. Control Feed-Through Noise VO VCC 50 Ω fin VCC/2 VC = VCC 0.1 μF VI VI (VI = 0 dBm at f = 1 MHz) VCC GND (ON) RL 600 Ω CL 50 pF Figure 8. Minimum Through Bandwidth SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325G – MARCH 1996 – REVISED JULY 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 PARAMETER MEASUREMENT INFORMATION VO1 RL 600 Ω CL 50 pF VCC 50 Ω fin VCC/2 VC = VCC 0.1 μF VI VI (VI = 0 dBm at f = 1 MHz) VO2 VCC Rin 600 Ω VCC/2 VC = GND Rin 600 Ω VCC GND (ON) VCC GND (OFF) RL 600 Ω CL 50 pF Figure 9. Crosstalk Between Any Two Switches VO VCC 50 Ω fin VC = GND 0.1 μF VI VI (VI = 0 dBm at f = 1 MHz) VCC GND (OFF) Rin 600 Ω RL 600 Ω CL 50 pF VCC/2 VCC/2 Figure 10. Feed Through, Switch Off VI (VI = 0 dBm at f = 1 kHz) VO RL 10 kΩ CL 50 pF VCC VCC/2 VC = VCC 10 μF VI fin VCC GND (ON) Figure 11. Amplitude-Distortion Rate PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN74HC4066D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066DBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI -40 to 85 SN74HC4066DBR ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066DBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066DT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC4066N SN74HC4066NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC4066N SN74HC4066NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI -40 to 85 SN74HC4066PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 SN74HC4066PWT ACTIVE TSSOP PW 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC4066 PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Addendum-Page 2 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN74HC4066DBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74HC4066DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC4066DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74HC4066NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74HC4066PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HC4066PWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC4066DBR SSOP DB 14 2000 367.0 367.0 38.0 SN74HC4066DR SOIC D 14 2500 367.0 367.0 38.0 SN74HC4066DT SOIC D 14 250 367.0 367.0 38.0 SN74HC4066NSR SO NS 14 2000 367.0 367.0 38.0 SN74HC4066PWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74HC4066PWT TSSOP PW 14 250 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01 28 PINS SHOWN Gage Plane 8,20 7,40 0,55 0,95 0,25 38 12,90 12,30 28 10,50 24 8,50 Seating Plane 7,90 9,90 30 10,50 9,90 0,38 5,60 5,00 15 0,22 14 A 28 1 16 20 6,50 6,50 14 0,05 MIN 5,90 5,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 0,15 M 0°–8° 0,10 0,09 0,25 NOTES: A. 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This application note describe the use of a tracebuffer structure where values treated in the DSP can be saved in a data-array and used for internal of external modification interfaced though the Motion Control Debugger system. 1 The Tracebuffer Structure A data-array structure is defined to enable saving arrays of values in data-memory (DM). This array of memory locations can be addressed by the use of the pointer-system on the 2171 core. With this structure defined, further treating or evaluation of the internal data-calculations can be analyzed and checked for errors. Using the Motion Control Debugger the values can be either be plotted directly or dumped for analyzing the data-array in other external programs In the chosen structure any number of pointer arrays in DM can be enabled and individually initialized for locations in DM. The structure will furthermore allow the user to under-sample the writing to the buffer. Initialize the Tracebuffer Though macro Is the Sample Ratio = Sample number? Is Flag enabled ? Is there still space in the Buffer Full ? YES No YES No Update Buffer and increment pointer and counter End Macro; Macro Call YES No Figure 1 - Flowchart for the Buffer writing The flow chart illustrate the structure of the trace buffer writing. Initialization is done in the startup sequence. After this, the Flag is checked - is the flag set then the corresponding tracebuffer is enabled. Secondly the buffer is checked for available spaces. If the DM locations defined for memory write aren't full it is safe to go on. If the buffer is full return. Finally the sample-ratio is checked. If a sample-ratio is a Using a Tracebuffer with the ADMCF32X ANF32X-34 © Analog Devices Inc., March 2000 Page 4 of 11 declared different from zero then check if the sample-number is equal to the sample-ratio. If it is write the chosen variable to the data-array. If not, return to the subroutine. The structure of the buffer is circular and to optimize the flexibility the format is provided as a complete macro setting with locked data-array format. 1.1 The Tracebuffer Data-Array To enable the tracebuffer array in DM it is necessary to define a given circular buffer with associated pointer. The circular buffer is structured as: First location : Statement of flag - ON/OFF Second location : Pointer to next free address Third location : Sample ratio (specified by the user) Fourth location : Sample number (used during the re-sampling of values) Fifth location : Counter for the buffer. Sixth to XXX locations : Placement for the values Every time the macro is called, Ex. in the PWMSYNC_ISR, a new value is added to the buffer if there are available space left and the sample number is equal to the under-sample ratio. DM(Address) Flag (ON/OFF) DM(Address+1) Pointer to next free address .. Sample ratio .. Sample number .. Counter for Buffer .. First Data-placement .. Value(1) .. Value(2) .. .. .. .. .. .. .. Value (Buffer size -2) .. Value (Buffer size -1) .. Value (Buffer size) Figure 2 - Tracebuffer - locations in DM Figure 2 illustrates how the values are placed in the allocated DM locations. Here values are stored at specific addresses in order to analyze these off-line. First value Placed in the buffer N = numbers in tracebuffer Buffer full a Using a Tracebuffer with the ADMCF32X ANF32X-34 © Analog Devices Inc., March 2000 Page 5 of 11 2 Implementation of the Tracebuffer Library Routines 2.1 Usage of the tracebuffer routines The routines are developed as an easy-to-use library, which has to be linked to the user’s application. The library consists of two files. The file “T_buffer.dsp” contains the assembly code for the subroutines. This package has to be compiled and can then be linked to an application. The user has to include the header file “T_buffer.h”, which provides the function-like macros for this routine. The following table summarizes the set of macros that are defined in this library. Operation Usage Input Output Initialization Buffer_Init("name", sample ratio); Name & Sample ratio None Activate Buffer_ON("name"); Name None Deactivate Buffer_OFF("name"); Name None Record Buffer_Record("name", value); Name & Value None Table 1: Implemented routines The four-macro settings allow the user to setup any given DM-locations for trace-buffer availability. Specifying the selected buffer and record value enables the flexibility of writing any number to a known position in memory. 2.2 Usage of the DSP registers Table 2 gives an overview of the DSP core registers that are modified by the four macros mentioned above. Obviously, also the "input" values are modified. Usage Modified registers Buffer_Init("name", sample ratio); ax0 Buffer_OFF("name"); ax0 Buffer_ON("name"); ax0 Buffer_Record("name", value); ax0, ax1, ay0, ar, I5, M5 Table 2: Usage of DSP core registers for the subroutines a Using a Tracebuffer with the ADMCF32X ANF32X-34 © Analog Devices Inc., March 2000 Page 6 of 11 2.3 Access to the library: the header file Including the header file "t_buffer.h" into the application code may access the library. The header file is intended to provide function-like macros to the Trace buffer routines. It defines the calls shown in Table 1. The file is mostly self-explaining but some comments have to be added. The sample ratio is here defined as how often is a new value can be written to the buffer. First macro is the Buffer_Init macro. This macro initializes the five first location of the circular buffer in respect to "name of the buffer" and the sample-ratio. Furthermore the sample-number and the internal counter is cleared. The second and third macro Buffer_ON and Buffer_OFF just enables or disables writing to the buffers. In this case the first location in the buffer ( the flag ) are set/or cleared. {******************************************************************************** * * * Type: Macro * * * * Call: Buffer_Init("Buffer", sampleratio) * * Description : Initialize the tracebuffer * * * * Undersample ratio 0 = every time * * 1 = every 1.time * * 2 = every 2.time ..... * * * * Ouputs : none * * * * Modified: ax0 * * * ********************************************************************************} .MACRO Buffer_Init(%0,%1); ax0 = %1; { Sample ratio } dm(%0+2)= ax0; ax0 =^%0+5; { Store start value } dm(%0+1)= ax0; { first location for data } ax0 = 0x0000; dm(%0) = ax0; { Clear Flag - Non-Active } dm(%0+3)= ax0; { Clear sample number } dm(%0+4)= ax0; { Clear counter for this buffer } .ENDMACRO; {******************************************************************************** * * * Type: Macro * * * * Call: Buffer_ON("buffer") * * * * Description : Enable tracebuffer "Buffer" * * Ouputs : none * * * * Modified : ax0 * * * ********************************************************************************} .MACRO Buffer_ON(%0); ax0 = 1; dm(%0) = ax0; .ENDMACRO; a Using a Tracebuffer with the ADMCF32X ANF32X-34 © Analog Devices Inc., March 2000 Page 7 of 11 {******************************************************************************** * * * Type: Macro * * * * Call: Buffer_OFF("buffer") * * * * Description : Disable tracebuffer "Buffer" * * Ouputs : none * * * * Modified : ax0 * * * ********************************************************************************} .MACRO Buffer_OFF(%0); ax0 = 0; dm(%0) = ax0; .ENDMACRO; 2.4 The program macro The following code contained in the file “t_buffer.h” defines the macrocode used for the Tracebuffer. In many cases this piece of code is placed in the "t_buffer.dsp"-file but here the flexibility advances by placing the program-code directly in the macro. It should be mentioned that this way of using the tracebuffer enables flexibility but takes up more memory. The following code implements the tracebuffer routines. Refer to the flowchart in section 1 for the structure of the buffers. Input to the tracebuffer are any numbers computed in the DSP. Underneath is the code for the Buffer_Record.. It just need to be said that since the buffer is structured as a circular buffer the data-placement for each of the "buffer-handle" values are placed from buffer-location 1 to 5 (here %0….%0+4) {******************************************************************************** * * * Type: Macro * * * * all: Buffer_Record(buffer,data) * * * * Description : Place data in buffer memory * * Ouputs : none * * * * Modified: M5, I5, ar, ax1, ax0, ay0 * * * ********************************************************************************} .MACRO Buffer_Record(%0,%1); .Local Continue1,Continue2,Continue3,End; { Local routines in Macro } M5 = 1; { modify factor = 1 } ax1 = %1; I5 = ^%0; { load start value for pointer } ar = dm(%0); { temporary storage } ar= tstbit 0 of ar; if NE jump Continue1; Jump end; Continue1: ax0 = %%0; ay0 = dm(%0+4); ar = ax0 - ay0; if gt jump Continue2; ax0 = 0x0000; dm(%0) = ax0; Jump end; a Using a Tracebuffer with the ADMCF32X ANF32X-34 © Analog Devices Inc., March 2000 Page 8 of 11 Continue2: { is sample_num equal to ratio? } ax0 = dm(%0+3); ay0 = dm(%0+2); ar = ax0 - ay0; if eq jump Continue3; ar = ax0 + 1; dm(%0+3) = ar; Jump end; Continue3: { write into buffer } I5 = dm(%0+1); { load backup value for pointer } dm(I5,M5) = ax1; { Value updated to Buffer } ax0 = dm(%0+4); { increment count } ar = ax0 + 1; dm(%0+4) = ar; ax0 = 0x0000; { clear sample_num } dm(%0+3) = ax0; dm(%0+1) = I5; end: .ENDMACRO; 3 Software Example: Tracebuffer 3.1 Usage of the Tracebuffer routine an example This example demonstrates how two values are written to Buffer1 and Buffer2. In this case the memorylocations used as buffers are set to 2*105-locations (100 location of calculated data). The values written to these two buffer-arrays are values computed for three 120-degree phase shifted reference voltages. 3.2 The main program: main.dsp The file “main.dsp” contains the initialisation and PWM Sync and Trip interrupt service routines. To activate, build the executable file using the attached build.bat either within your DOS prompt or clicking on it from Windows Explorer. This will create the object files and the main.exe example file. This file may be run on the Motion Control Debugger. The program can be booted from Flash but in this tracebuffer case it is not effectuated since the DM can not be read without the Motion Control Debugger. Every module besides from the Main_program module is by default placed in either one of the three USERFLASH memory banks. In the following, a brief description of the code is given. Start of code – declaring start location in program memory or FLASH memory. Comments are placed depending on whether the program should run in PMRAM or Flash memory. {************************************************************************************** * Application: Starting from FLASH (out-comment the one not used) **************************************************************************************} !.MODULE/RAM/SEG=USERFLASH1/ABS=0x2200 Main_Program; {************************************************************************************** * Application: Starting from RAM (out-comment the one not used) **************************************************************************************} .MODULE/RAM/SEG=USER_PM1/ABS=0x30 Main_Program; a Using a Tracebuffer with the ADMCF32X ANF32X-34 © Analog Devices Inc., March 2000 Page 9 of 11 Next, the general systems constants and PWM configuration constants (main.h – see the next section) are included. Also included are the PWM library and the T_BUFFER library definitions {******************************************************************************** * Include General System Parameters and Libraries * ********************************************************************************} #include ; #include ; #include ; #include ; {******************************************************************************** * Local Variables Defined in this Module * ********************************************************************************} .VAR/DM/RAM/SEG=USER_DM AD_IN; { Volts/Hertz Command (0-1) } .VAR/DM/RAM/SEG=USER_DM Theta; { Current angle } .VAR/DM/RAM/SEG=USER_DM VrefA; { Voltage demands } .VAR/DM/RAM/SEG=USER_DM VrefB; .VAR/DM/RAM/SEG=USER_DM VrefC; .VAR/DM/RAM/CIRC/SEG=USER_DM Buffer1[105]; { Tracebuffer } .VAR/DM/RAM/CIRC/SEG=USER_DM Buffer2[105]; { Tracebuffer } ar = 0x7FFF; dm(AD_IN) = ar; ar = 0x0000; dm(Theta) = ar; dm(VrefA) = ar; dm(VrefB) = ar; dm(VrefC) = ar; Some Variables are defined hereafter. These are used to calculate the three reference voltages. For further information see ANF32X-3. The two circular buffers are defined - here the size is 105 locations (5 locations are used for handling the buffer) this number is arbitrary - just depending on the memory locations occupied by these buffers. The first thing that is done in the initialisation block (Startup) is checking a selected PIO line for level. If the PIO-pin is high jump to an ERASE BOOT FROM FLASH BIT routine in ROM and return. If not, just go ahead with normal operation. This small macro is done to enable re-coding of the FLASH memory. For further information (See Reference Manual). In this example the PIO-pin 6 is chosen as erase pin. The initialisation of the PWM block is executed. Note how the interrupt vectors for the PWMSync and PWMTrip service routines are passed as arguments. Then the interrupt IRQ2 is enabled by setting the corresponding bit in the IMASK register. Two Tracebuffers are initialised with 1x under-sampling Then the Tracebuffers are activated by setting the flag (Buffer_ON(Buffer1) & Buffer_ON(Buffer2)). After that, the program enters a loop, which just waits for interrupts. {******************************************************************************** * Start of program code * ********************************************************************************} Startup: FLASH_erase_PIO(6); { Select PIO6 as clearing PIO } { Remember that sport1 is muxed with the PIO-lines } { If the bit is high Clear Memory and Boot from } { Flash bit } PWM_Init(PWMSYNC_ISR, PWMTRIP_ISR); IFC = 0x80; { Clear any pending IRQ2 inter. } ay0 = 0x200; { unmask irq2 interrupts. } ar = IMASK; ar = ar or ay0; IMASK = ar; { IRQ2 ints fully enabled here } Buffer_Init(Buffer1, 1); { 1x undersampling } Buffer_Init(Buffer2, 1); { 1X undersampling } Buffer_ON(Buffer1); { Activate the Buffer } Buffer_ON(Buffer2); { Activate the Buffer } Main: { Wait for interrupt to occur } jump Main; rts; a Using a Tracebuffer with the ADMCF32X ANF32X-34 © Analog Devices Inc., March 2000 Page 10 of 11 In the PWMSYNC_ISR the DAGS are first set up for trigonometric functionality. Three reference voltages VrefA,B and C are calculated on base of the trigonometric functions in the Trigonometric-library ( See ANF32X-10 ). The PWM block is update with these control signals and finally the two Tracebuffers Buffer1 and Buffer2 are updated. Here the variables VrefA and VrefB are stored in the two data-arrays. PWMSYNC_ISR: Set_DAG_registers_for_trigonometric; my0 = DM(AD_IN); mr = 0; { Clear mr } mr1 = dm(Theta); { Preload Theta } mx0 = Delta; mr = mr + mx0*my0 (SS); { Compute new angle & store } dm(Theta) = mr1; Sin(mr1); { Result in ar register } mr = ar*my0 (SS); { Multiply by Scale for VrefA } dm(VrefA) = mr1; ax1 = dm(Theta); { Compute angle of phase B } ay1 = TwoPioverThree; ar = ax1 - ay1; Sin(ar); { Result in ar register } mr = ar*my0 (SS); { Multiply by Scale for VrefB } dm(VrefB) = mr1; ax1 = dm(Theta); { Compute angle of phase C } ay1 = TwoPioverThree; ar = ax1 + ay1; Sin(ar); { Result in ar register } mr = ar*my0 (SS); { Multiply by Scale for VrefC } dm(VrefC) = mr1; ax0 = DM(VrefA); ax1 = DM(VrefB); ay0 = DM(VrefC); ay1= DM(Theta); PWM_update_demanded_Voltage(ax0,ax1,ay0); {******************************************************************************* * Update tracebuffers * *******************************************************************************} ax0 = DM(VrefA); Buffer_Record(Buffer1,ax0); ax0 = DM(VrefB); Buffer_Record(Buffer2,ax0); RTI; It has to be mentioned that the Buffer_Record macro uses some DSP registers (see T_buffer.h) for that reason the proposed way of writing to the buffer is as defined above. 4 Experimental results The experimental results illustrated beneath are two plots of VrefA and VrefB. These values are written into Buffer1 and Buffer2 and then plotted though the Motion Control Debugger. As can be seen on Figure 3 the two waveforms are plotted as a function of the given number in Buffer1 and 2. From the figures the scaling can also be seen - here the numbers are represented in decimal. Selecting another scaling of these reference-voltages will re-scale these plots. a Using a Tracebuffer with the ADMCF32X ANF32X-34 © Analog Devices Inc., March 2000 Page 11 of 11 Figure 3 - Plot from the Motion Control Debugger using the Internal Plot Function. www.analog.com Developing VisualAudio Modules Copyright Information © 2006 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc. Trademark and Service Mark Notice The Analog Devices logo, VisualDSP++, VisualAudio, SHARC, Blackfin, and EZ-KIT Lite are registered trademarks of Analog Devices, Inc. All other brand and product names are trademarks or service marks of their respective owners. 2 of 51 Contents Contents..............................................................................................................................................................................................................3 Preface.................................................................................................................................................................................................................4 Purpose of This Manual................................................................................................................................................................................4 Custom Audio Modules....................................................................................................................................................................................5 Overview.........................................................................................................................................................................................................5 Numerics on the Blackfin and SHARC.......................................................................................................................................................9 Example 1A – Mono Parametric Scaling....................................................................................................................................................9 Example 1B – Render Function in ASM.................................................................................................................................................19 Scratch Buffers............................................................................................................................................................................................22 Auxiliary Memory for Module Instances................................................................................................................................................22 Pointer Aliasing Rules................................................................................................................................................................................25 Meta-Variables and Expressions...............................................................................................................................................................26 Modifying Module Parameters.................................................................................................................................................................27 Expression Language Details.....................................................................................................................................................................28 Modules With Data of Varying Size.........................................................................................................................................................33 Modules With a Variable Number of Pins...............................................................................................................................................34 Frequency Domain Processing.................................................................................................................................................................36 Other Features of the XML File................................................................................................................................................................36 Custom Bypass Functions..........................................................................................................................................................................38 SHARC SIMD Considerations..................................................................................................................................................................38 Adjusting Modules from Other Modules................................................................................................................................................39 Dynamically Changing a Module’s Render Function............................................................................................................................39 Compatibility between Blackfin and SHARC Modules.........................................................................................................................39 Reference Section............................................................................................................................................................................................41 AudioProcessing.h Structures...................................................................................................................................................................41 Module Memory Sections.........................................................................................................................................................................44 Summary of Naming Conventions...........................................................................................................................................................45 Inspector Control Types............................................................................................................................................................................47 XML Format................................................................................................................................................................................................50 Index.................................................................................................................................................................................................................51 3 of 51 Preface PURPOSE OF THIS MANUAL The VisualAudio Designer Users’ Guide explains how to use VisualAudio to develop audio processing software for a wide variety of products. The guide describes the graphical interface, provides step-by-step procedures for completing tasks, and contains detailed technical information on how to integrate the generated code into your final product. Intended Audience The primary audience for this manual is a programmer who is familiar with Analog Devices, Inc. processors. This manual assumes that the audience can use the VisualDSP++ development environment to develop, build, and debug Digital Signal Processing (DSP) applications for the SHARC or Blackfin processor. 4 of 51 Custom Audio Modules This document explains how to write an audio processing module for VisualAudio for SHARC processors in the 26x and 36x families, as well as for Blackfin processors in the 53x and 56x families. Audio modules allow audio processing (sometimes called “post-processing”) to be implemented by making use of a number of smaller, self-contained processing blocks. The topics are organized as follows. • “Overview” • “Numerics on SHARC and Blackfin” • “Example 1A – Mono parameter scaling” • “Example 1B – Render function in ASM” • “Scratch Buffers” • “Auxiliary Memory for Module Instances” • “Pointer Aliasing Rules” • “Meta-variables and Expressions” • “Modifying Module Parameters” • “Expression Language Details” • “Modules with Data of Varying Size” • “Modules with Variable Numbers of Pins” • “Other Features of the XML File” • Custom Bypass Functions” • “SHARC SIMD Considerations” • “Adjusting Modules from Other Modules” • “Dynamically Changing a Module’s Render Function” • “Compatibility between Blackfin and SHARC Modules” OVERVIEW This section includes a brief philosophical review of what motivated certain design decisions, a discussion about the quasi-object orientation inherent in the module concept, a description of usage scenarios and a high-level description of the parts of a module. Design Philosophy The module format was designed with the following goals in mind. • Minimal run-time processor footprint • CPU efficiency • Straightforward to write and use Several key features help accomplish these goals. • VisualAudio does as much work as possible at compile and assembly time to enable the production DSP code to be lean, while still providing a flexible environment for creating and deploying modules. • Modules process a block of samples at a time to ensure that the cost of loading and storing state and parameters is incurred only once per block instead of once per sample. • VisualAudio supports interleaved stereo connections between modules to enable a common use of Single-Instruction, Multiple-Data (SIMD) on the SHARC DSP. This signal type is also supported on the Blackfin, primarily for compatibility with system designs originating on SHARCs. 5 of 51 • VisualAudio supports signals at both the audio sampling rate and a lower “control rate.” This allows slowly-changing control signals to use less memory and MIPS. • VisualAudio supports a variety of frequency domain signal types, as well as a user-settable FFT size and hop factor for “overlap-add” and “overlap-save” style processing. • Some of the spirit of object-oriented programming is borrowed, while a lean approach is maintained. Note that C++ is not used. • To keep the CPU usage (MIPS) of a module relatively constant, a module instance should perform roughly the same operations every time it runs. Assume the module’s worst case CPU usage. The exception is when there are clear modes. In this case, the user can plan in advance the combination of module modes that will be in use at a particular time. • In keeping with the goals of near-constant CPU usage and minimal memory usage, parameter calculation (such as filter design) is normally pushed forward to design time, and implemented outside the DSP runtime (for example within VisualAudio Designer). Therefore, modules usually do not contain design or initialization code on the DSP. Instead, module instances are normally initialized and designed via static initialization of their state structures (in code generated by VisualAudio Designer or by the user).1 Module Terminology Each type of processing module is represented by its own module class. These are instantiable; multiple instances of each class may exist at the same time. We use the term module when the distinction between the class and the instance is clear from context. Examples of modules include “Scaler N Smoothed” and “Delay).” The behavior of modules is adjusted via render variables. These are variables that exist on the DSP as part of the module instance structure. In addition, VisualAudio Designer presents high-level interface variables for each module. Interface variables are those exposed via module inspectors within VisualAudio Designer. An interface variable may correspond directly to a render variable. Alternatively, an interface variable may be mapped to a render variable through some function; for example, translating a delay time in milliseconds to a sample delay. Other possibilities include more complicated dependencies, where one or more interface variables touch one or more render variables. Render variables are defined in associated .h files detailing the instance structure of each module; interface variables are defined in associated .xml files. Interface variables are sometimes referred to as high-level variables, while render variables are sometimes referred to as low-level variables. There are three kinds of render variables, differing in restrictions on when they are set: • Constants are typically set only at design time (i.e. their value doesn’t usually change at run time.) • Parameters are typically set at design or tuning time from VisualAudio Designer, or by DSP control code • States can be set by the module’s render function itself, as well as by VisualAudio Designer in tuning mode or by DSP control code. Within VisualAudio Designer, these restrictions are enforced. On the DSP itself, it is up to the user to abide by these guidelines as appropriate. The term render variable is used to distinguish it from a meta-variable, which exists only in VisualAudio Designer’s representation of the module, not on the DSP. Thus, the set of interface variables contains some render variables and some meta-variables. Modules are interconnected via pins. Pins may be designated as either input or output. Either may be of type stereo_pcm, mono_pcm or control. The stereo_pcm and mono_pcm pins are collectively referred to as “audio rate pins,” or simply “audio 1 In stand-alone usage (without VisualAudio Designer) or when modules are implemented in terms of other modules, allocation can be either dynamic or static and initialization DSP code is often included. 6 of 51 pins.” Control rate pins are referred to as “control pins” and are of type control. Frequency domain pins may be of the following types: spectrum_real, spectrum_complex, spectrum_half_real and spectrum_half_complex. These are explained in more detail later. There are two kinds of modules: those that have a fixed number of pins, and those in which the number of input and/or output pins varies from instance to instance. A module class may have outputs, but no inputs, in which case it can be thought of as a signal generator (such as a sine wave generator). Or, it can have inputs, but no outputs, and report its results in a state variable (such as a VU meter). Finally, a module can have neither outputs nor inputs, and can do its work entirely in terms of side effects to itself (modifying its own state) or to other modules (modifying the render variables of other modules). Such a module could be used, for example, in testing other modules, when strictly-repeatable sample-synchronous updates are needed. Render functions must never write to their inputs. To see why this is true, consider a module whose output fans out to several other modules. If the first module wrote to its input, it would corrupt the input to the second module. However, the VisualAudio Designer routing algorithm knows the overall connection between audio modules and may reuse the same patch buffer for the input and output of a module, when it is safe. For more details, see Pointer Aliasing Rules below. Module Usage Scenarios There are two ways that VisualAudio modules can be used: • In a drag-and-drop fashion from VisualAudio Designer - Memory allocation, parameter setting and calling of the render function are handled automatically. • As C-callable functions in a stand-alone library - Memory allocation, parameter setting and calling of the render function are all handled by the user’s C or assembly code. Even if a module is used in drag-and-drop fashion, its render variables may be modified in the DSP program’s control code (sometimes referred to as “user control code.”) Similarly, a module used in a drag-and-drop fashion may include, in its implementation, a render function that calls other render functions using the stand-alone style. This document contains information on developing modules that may be used in either style of usage. For more information on usage, see the document VisualAudio Module Library Usage Guide. For more information on the particular modules supplied by VisualAudio, see VisualAudio Module Library Reference for Blackfin and VisualAudio Module Library Reference for SHARC. Module Modes When used within a layout generated by VisualAudio Designer1, a module may be in one of four modes. These can be set at runtime with the following function: AMFSetModuleStatus(AMF_Module *module, AMF_ModuleStatus status) The possible status values and their meanings are given below. • AMFModuleStatus_ACTIVE. The module processes its inputs and writes its outputs via its render function each time it is run. This is the default mode. Note that a module may have several alternative render functions, but one must be specified as the default. • AMFModuleStatus_INACTIVE. The module is not run. This implies that its outputs are not written, leaving their contents undefined. • AMFModuleStatus_MUTED. The module's outputs are zeroed each time it is run. This behavior is provided automatically. You need not write any code to implement this mode. 1 More specifically, when used with the VisualAudio Layout Support library. 7 of 51 • AMFModuleStatus_BYPASSED. The module performs the bypass function, which means that its input(s) are copied to its output(s) each time it is run. The default algorithm copies audio inputs to audio outputs, copies signal inputs to signal outputs, and mutes unused outputs. Where there is a mono/stereo mismatch, stereo is converted to mono by adding the channels and dividing by two; mono is converted to stereo by duplicating the channel. Alternatively, the module designer may provide a custom bypass function. For more information, see How to Write a Custom Bypass Function below. The default bypass algorithm copies the Nth input pin of a given type to the Nth output pin of the same type. For example, the 3rd control pin input is copied to the 3rd control pin output. If there are more output pins than input pins, the remainder are muted. Note that for the purposes of bypass, stereo and mono pins are considered the same type. If a mono input matches a stereo output, the mono input is duplicated on both channels. If a stereo input matches a mono output, the stereo channels are added and divided by 2. Parts of a Module A module consists of these parts: • A header (.h) file that defines the run-time interface to the module, including the instance structure typedef. The name of this file must be the same as the module name with .h (for example, AMF_Scaler.h). • The module’s run-time DSP code, in source or binary form (e.g., to protect any intellectual property). The VisualAudio Module Library is delivered in binary form as a VisualDSP++ .dlb file, and the source is also included. If delivered in source form, the module must contain the following two parts: • The module’s render function, which implements the module’s primary function • The module’s class object, which describes the module to the run-time system • A .xml file that describes the module to VisualAudio Designer in detail. This file is not required if the module is never used with VisualAudio Designer. The name of this file must be the same as the module name, with .xml appended (for example, AMF_Scaler.xml where “AMF” stands for Audio Module Format). The .xml file includes information about what files constitute the module’s run-time and header files, as well as information about the module’s parameters, and may also include simple design formulas. How to Add a Module to VisualAudio Designer To make a custom SHARC module available to VisualAudio Designer, create a directory (we’ll call it xxx) and put the XML, include, source files and object files1 in sub-directories. For the SHARC, the subdirectories should be: • XML files in xxx\SHARC\XML\ • Header files in xxx\SHARC\Include\ • Source files in xxx\SHARC\Source\ • Object files in xxx\SHARC\Lib For the Blackfin, they should be: • XML files in xxx\Blackfin\XML\ • Header files in xxx\Blackfin\Include\ • Source files in xxx\Blackfin\Source\ • Object files in xxx\Blackfin\Lib Where xxx is your Modules directory. You must then add your Modules directory to the list of directories searched by VisualAudio Designer. See the VisualAudio Designer User's Guide for details. 1 Third parties can protect their IP by delivering it as a library (a .dlb). Alternatively, they can deliver it is as a pre-compiled or pre-assembled object file (a .doj). 8 of 51 You must add your custom module source files to the VisualDSP++ project (.dpj) file for your platform. In contrast, when a module is included in object form (.dlb or .doj), it is automatically added to the linker list via the VALinkerCmds.txt file. NUMERICS ON THE BLACKFIN AND SHARC The primary difference between Blackfin and SHARC modules is the use of floating point on the SHARC. On the Blackfin, floating point is not available in hardware; hence Blackfin modules typically operate in fixed point. The basic VisualAudio signal type on the Blackfin is fract32, a 32-bit 1.31 format fraction. The basic VisualAudio signal type on the SHARC is a float, a 32-bit floating point number. To ease the task of moving between SHARC and Blackfin, VisualAudio defines a type AMF_Signal, which is fract32 for Blackfin and float for SHARC. Most SHARC modules use floating point internally. However, extended precision SHARC modules may use fixed point internally. Most Blackfin modules use fixed point internally. A number of conventions have been established for fixed-point processing on the Blackfin. We recommend that custom modules obey these conventions for maximum compatibility: The default format for fixed point coefficients is 1.31. Coefficients which perform a “volume scaling” can be 16 bits (typically 1.15 format), so that faster 16x32 multiplication can be used (as opposed to 32x32), since a volume-like scale tends not to need to be represented with an extremely high precision. Smoothing of 16-bit coefficients may need to be performed at 32 bits (to allow the smoothing to move at very slow smoothing rates), but the top 16 bits can still be used for doing the volume scaling cheaply. Headroom in signals is assumed to be managed by the layout creator, not by the module or by VisualAudio. Therefore, except where noted, a Blackfin module assumes 1.31 input and output signals, and for compatibility a SHARC module assumes signals where 1.0f corresponds to maximum amplitude (though clipping to +/- 1.0 is only implemented at the output). Saturating arithmetic is used in fixed point modules. In fixed point modules, multiplications implemented to “31-bit” precision (i.e. discarding the low order product as a speed optimization) may be used as a satisfactory substitute for full 32x32 multiplications. 16 bit types (fract16 and int16 ) as module variables are not supported on the SHARC in VisualAudio. The module implementer is responsible for creating correct alignment in the module state structure, if necessary (via padding and/or ordering). This is an issue only with Blackfin modules. The structures allocated by VisualAudio Designer can be assumed to be aligned to 32-bit boundaries. EXAMPLE 1A – MONO PARAMETRIC SCALING The following example shows a parametric scaling of a mono signal, for both SHARC and Blackfin versions of VisualAudio Example 1A Header File: AMF_Scaler.h The example module’s header file is shown below, for the SHARC or Blackfin version of VisualAudio: /***** Begin AMF_Scaler.h *******/ // Include header file with base class definitions: #include "AudioProcessing.h" // Instance structure typedef 9 of 51 typedef struct { AMF_Module b; // Parameters AMF_Signal amplitude; } AMF_Scaler; // Class object declaration extern const AMF_ModuleClass AMFClassScaler; /**** End AMF_Scaler.h *****/ Notice that the instance structure begins with an embedded struct of type AMF_Module. All module instance structures must begin in this manner (this allows any module’s struct to be interpreted as an AMF_Module, hence implementing a form of inheritance). This struct is followed by a single render variable, amplitude. The structure for the Blackfin and SHARC versions of the module are identical, except for the definition of AMF_Signal as fract32 instead of float in AudioProcessing.h. Example 1A Code File: AMF_Scaler.c The example module’s C code file is AMF_Scaler.c. The first half of the C file for the SHARC version of the module is listed below and analyzed in detail, with comparisons to the Blackfin version as necessary. /****** Begin AMF_Scaler.c *********/ #include "AMF_Scaler.h" // The module's header file #pragma optimize_for_speed // VisualDSP++ directive SEG_MOD_FAST_CODE void AMF_Scaler_Render( AMF_Scaler *restrict instance, AMF_Signal * restrict * buffers, int tickSize) { int i; AMF_Signal *in = buffers[0]; AMF_Signal *out = buffers[1]; AMF_Signal amplitude = instance->amplitude; #pragma SIMD_for for (i=0; iamplitude; #pragma SIMD_for for (i=0; iamplitude; for (i=0; i tag with value 2. To make it easy to supply values for the type vector, the following macros are supplied: #define AMF_StereoPin(whichPin) \ (AMFPinType_STEREO<<(whichPin*4)) #define AMF_ControlPin(whichPin) \ (AMFPinType_CONTROL<<(whichPin*4)) #define AMF_MonoPin(whichPin) (0) #define AMF_SpectrumRealPin(whichPin) \ (AMFPinType_SPECTRUM_REAL<<(whichPin*4)) #define AMF_SpectrumComplexPin(whichPin) \ (AMFPinType_SPECTRUM_COMPLEX<<(whichPin*4)) #define AMF_SpectrumHalfRealPin(whichPin) \ (AMFPinType_SPECTRUM_HALF_REAL<<(whichPin*4)) #define AMF_SpectrumHalfComplexPin(whichPin) \ (AMFPinType_SPECTRUM_HALF_COMPLEX<<(whichPin*4)) Type descriptors can then be assembled by bitwise OR’ing of these macros. Note that the whichPin argument is zero-based. For example, if a module has one mono input followed by one stereo input, its input type designator could be written as: (AMF_MonoPin(0) | AMF_StereoPin(1)) Alternatively, it could be written directly as 0x10. If there are more than eight pins, then the high order nibble is assumed to be sticky and applies to all pins beyond eight. However, there are situations where this convention is inadequate, such as when a pin greater than the 8th has a type differing from the 8th. For these situations, an indirect form is available as follows: 13 of 51 If the AMF_ModuleClass flags field includes the bit AMFModuleClassFlag_INDIRECT_INPUT_PIN_TYPE, then the input type descriptor is actually a pointer to an array of sufficient length to support bit vectors for all input pins. Similarly, if the flags include the bit AMFModuleClassFlag_INDIRECT_OUTPUT_PIN_TYPE, then the output type descriptor is actually a pointer to an array of sufficient length to support bit vectors for all input pins. In modules with variable number of pins (described in a later section of this document), the input and output type descriptors are in the instance, rather than the class. Example 1A XML File: AMF_Scaler.xml The .xml file describes the module to VisualAudio Designer. In this discussion, we assume a minimal familiarity with XML. Please note that all module xml element type attributes (i.e. type = “string”, type = “float” etc.) are optional as of VisualAudio 1.6 and therefore, are not shown in the examples below. When creating a custom module, we recommend copying the XML file from an existing module, renaming the XML file, and modifying it. At the outermost level, the XML file looks like this: . . . It begins by telling the XML parser where to find the VisualAudio Designer schema, which is used to validate the file.1 Validating the file ensures that it has all the information needed by VisualAudio Designer, that it is structured correctly, that the fields are listed in the proper order, and that it contains legal values for the required fields. The actual module definition is inside the body of the tag, which includes the information detailed below. Module Fields A module has several different self-description tags • The