ATtiny2313 - Atmel - Farnell Element 14 - Revenir à l'accueil

 

 

Branding Farnell element14 (France)

 

Farnell Element 14 :

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Everything You Need To Know About Arduino

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Tutorial 01 for Arduino: Getting Acquainted with Arduino

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The Cube® 3D Printer

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What's easier- DIY Dentistry or our new our website features?

 

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Ben Heck's Getting Started with the BeagleBone Black Trailer

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Ben Heck's Home-Brew Solder Reflow Oven 2.0 Trailer

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Get Started with Pi Episode 3 - Online with Raspberry Pi

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Discover Simulink Promo -- Exclusive element14 Webinar

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Ben Heck's TV Proximity Sensor Trailer

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Ben Heck's PlayStation 4 Teardown Trailer

See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…

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Get Started with Pi Episode 4 - Your First Raspberry Pi Project

Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.

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Ben Heck Anti-Pickpocket Wallet Trailer

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Molex Earphones - The 14 Holiday Products of Newark element14 Promotion

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Tripp Lite Surge Protector - The 14 Holiday Products of Newark element14 Promotion

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Microchip ChipKIT Pi - The 14 Holiday Products of Newark element14 Promotion

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Beagle Bone Black - The 14 Holiday Products of Newark element14 Promotion

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3M E26, LED Lamps - The 14 Holiday Products of Newark element14 Promotion

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3M Colored Duct Tape - The 14 Holiday Products of Newark element14 Promotion

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Tenma Soldering Station - The 14 Holiday Products of Newark element14 Promotion

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Duratool Screwdriver Kit - The 14 Holiday Products of Newark element14 Promotion

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Cubify 3D Cube - The 14 Holiday Products of Newark element14 Promotion

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Bud Boardganizer - The 14 Holiday Products of Newark element14 Promotion

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Raspberry Pi Starter Kit - The 14 Holiday Products of Newark element14 Promotion

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Fluke 323 True-rms Clamp Meter - The 14 Holiday Products of Newark element14 Promotion

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Dymo RHINO 6000 Label Printer - The 14 Holiday Products of Newark element14 Promotion

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3M LED Advanced Lights A-19 - The 14 Holiday Products of Newark element14 Promotion

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Innovative LPS Resistor Features Very High Power Dissipation

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Charge Injection Evaluation Board for DG508B Multiplexer Demo

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Ben Heck The Great Glue Gun Trailer Part 2

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Introducing element14 TV

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Ben Heck Time to Meet Your Maker Trailer

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Détecteur de composants

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Recherche intégrée

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Ben Builds an Accessibility Guitar Trailer Part 1

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Ben Builds an Accessibility Guitar - Part 2 Trailer

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PiFace Control and Display Introduction

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Flashmob Farnell

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Express Yourself in 3D with Cube 3D Printers from Newark element14

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Farnell YouTube Channel Move

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Farnell: Design with the best

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French Farnell Quest

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Altera - 3 Ways to Quickly Adapt to Changing Ethernet Protocols

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Cy-Net3 Network Module

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MC AT - Professional and Precision Series Thin Film Chip Resistors

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Solderless LED Connector

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PSA-T Series Spectrum Analyser: PSA1301T/ PSA2701T

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3-axis Universal Motion Controller For Stepper Motor Drivers: TMC429

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Voltage Level Translation

Puce électronique / Microchip :

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Microchip - 8-bit Wireless Development Kit

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 2 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 3 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 1 of 3

Sans fil - Wireless :

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Microchip - 8-bit Wireless Development Kit

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Wireless Power Solutions - Wurth Electronics, Texas Instruments, CadSoft and element14

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Analog Devices - Remote Water Quality Monitoring via a Low Power, Wireless Network

Texas instrument :

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Texas Instruments - Automotive LED Headlights

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Texas Instruments - Digital Power Solutions

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Texas Instruments - Industrial Sensor Solutions

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Texas Instruments - Wireless Pen Input Demo (Mobile World Congress)

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Texas Instruments - Industrial Automation System Components

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Texas Instruments - TMS320C66x - Industry's first 10-GHz fixed/floating point DSP

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Texas Instruments - TMS320C66x KeyStone Multicore Architecture

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Texas Instruments - Industrial Interfaces

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Texas Instruments - Concerto™ MCUs - Connectivity without compromise

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Texas Instruments - Stellaris Robot Chronos

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Texas Instruments - DRV8412-C2-KIT, Brushed DC and Stepper Motor Control Kit

Ordinateurs :

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Ask Ben Heck - Connect Raspberry Pi to Car Computer

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Ben's Portable Raspberry Pi Computer Trailer

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Ben's Raspberry Pi Portable Computer Trailer 2

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Ben Heck's Pocket Computer Trailer

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Ask Ben Heck - Atari Computer

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Ask Ben Heck - Using Computer Monitors for External Displays

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Raspberry Pi Partnership with BBC Computer Literacy Project - Answers from co-founder Eben Upton

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Installing RaspBMC on your Raspberry Pi with the Farnell element14 Accessory kit

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Raspberry Pi Served - Joey Hudy

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Happy Birthday Raspberry Pi

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Raspberry Pi board B product overview

Logiciels :

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Ask Ben Heck - Best Opensource or Free CAD Software

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Tektronix FPGAView™ software makes debugging of FPGAs faster than ever!

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Ask Ben Heck - Best Open-Source Schematic Capture and PCB Layout Software

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Introduction to Cadsoft EAGLE PCB Design Software in Chinese

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Altera - Developing Software for Embedded Systems on FPGAs

Tutoriels :

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Ben Heck The Great Glue Gun Trailer Part 1

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the knode tutorial - element14

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Ben's Autodesk 123D Tutorial Trailer

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Ben's CadSoft EAGLE Tutorial Trailer

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Ben Heck's Soldering Tutorial Trailer

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Ben Heck's AVR Dev Board tutorial

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Ben Heck's Pinball Tutorial Trailer

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Ben Heck's Interface Tutorial Trailer

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First Stage with Python and PiFace Digital

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Cypress - Getting Started with PSoC® 3 - Part 2

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Energy Harvesting Challenge

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New Features of CadSoft EAGLE v6

Autres documentations :

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Features • Utilizes the AVR® RISC Architecture • AVR – High-performance and Low-power RISC Architecture – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Throughput at 20 MHz • Data and Non-volatile Program and Data Memories – 2K Bytes of In-System Self Programmable Flash Endurance 10,000 Write/Erase Cycles – 128 Bytes In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles – 128 Bytes Internal SRAM – Programming Lock for Flash Program and EEPROM Data Security • Peripheral Features – One 8-bit Timer/Counter with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes – Four PWM Channels – On-chip Analog Comparator – Programmable Watchdog Timer with On-chip Oscillator – USI – Universal Serial Interface – Full Duplex USART • Special Microcontroller Features – debugWIRE On-chip Debugging – In-System Programmable via SPI Port – External and Internal Interrupt Sources – Low-power Idle, Power-down, and Standby Modes – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit – Internal Calibrated Oscillator • I/O and Packages – 18 Programmable I/O Lines – 20-pin PDIP, 20-pin SOIC, 20-pad QFN/MLF • Operating Voltages – 1.8 – 5.5V (ATtiny2313V) – 2.7 – 5.5V (ATtiny2313) • Speed Grades – ATtiny2313V: 0 – 4 MHz @ 1.8 - 5.5V, 0 – 10 MHz @ 2.7 – 5.5V – ATtiny2313: 0 – 10 MHz @ 2.7 - 5.5V, 0 – 20 MHz @ 4.5 – 5.5V • Typical Power Consumption – Active Mode 1 MHz, 1.8V: 230 µA 32 kHz, 1.8V: 20 µA (including oscillator) – Power-down Mode < 0.1 µA at 1.8V 8-bit Microcontroller with 2K Bytes In-System Programmable Flash ATtiny2313/V Preliminary Rev. 2543L–AVR–08/102 2543L–AVR–08/10 ATtiny2313 Pin Configurations Figure 1. Pinout ATtiny2313 Overview The ATtiny2313 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny2313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. (RESET/dW) PA2 (RXD) PD0 (TXD) PD1 (XTAL2) PA1 (XTAL1) PA0 (CKOUT/XCK/INT0) PD2 (INT1) PD3 (T0) PD4 (OC0B/T1) PD5 GND 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 VCC PB7 (UCSK/SCL/PCINT7) PB6 (MISO/DO/PCINT6) PB5 (MOSI/DI/SDA/PCINT5) PB4 (OC1B/PCINT4) PB3 (OC1A/PCINT3) PB2 (OC0A/PCINT2) PB1 (AIN1/PCINT1) PB0 (AIN0/PCINT0) PD6 (ICP) PDIP/SOIC 1 2 3 4 5 MLF 15 14 13 12 11 20 19 18 17 16 6 7 8 9 10 (TXD) PD1 XTAL2) PA1 (XTAL1) PA0 (CKOUT/XCK/INT0) PD2 (INT1) PD3 (T0) PD4 (OC0B/T1) PD5 GND (ICP) PD6 (AIN0/PCINT0) PB0 PB5 (MOSI/DI/SDA/PCINT5) PB4 (OC1B/PCINT4) PB3 (OC1A/PCINT3) PB2 (OC0A/PCINT2) PB1 (AIN1/PCINT1) PD0 (RXD) PA2 (RESET/dW) VCC PB7 (UCSK/SCK/PCINT7) PB6 (MISO/DO/PCINT6) NOTE: Bottom pad should be soldered to ground.3 2543L–AVR–08/10 ATtiny2313 Block Diagram Figure 2. Block Diagram PROGRAM COUNTER PROGRAM FLASH INSTRUCTION REGISTER GND VCC INSTRUCTION DECODER CONTROL LINES STACK POINTER SRAM GENERAL PURPOSE REGISTER ALU STATUS REGISTER PROGRAMMING LOGIC SPI 8-BIT DATA BUS XTAL1 XTAL2 RESET INTERNAL OSCILLATOR OSCILLATOR WATCHDOG TIMER TIMING AND CONTROL MCU CONTROL REGISTER MCU STATUS REGISTER TIMER/ COUNTERS INTERRUPT UNIT EEPROM USI USART ANALOG COMPARATOR DATA REGISTER PORTB DATA DIR. REG. PORTB DATA REGISTER PORTA DATA DIR. REG. PORTA PORTB DRIVERS PB0 - PB7 PORTA DRIVERS PA0 - PA2 DATA REGISTER PORTD DATA DIR. REG. PORTD PORTD DRIVERS PD0 - PD6 ON-CHIP DEBUGGER INTERNAL CALIBRATED OSCILLATOR4 2543L–AVR–08/10 ATtiny2313 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny2313 provides the following features: 2K bytes of In-System Programmable Flash, 128 bytes EEPROM, 128 bytes SRAM, 18 general purpose I/O lines, 32 general purpose working registers, a single-wire Interface for On-chip Debugging, two flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, or by a conventional non-volatile memory programmer. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATtiny2313 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATtiny2313 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.5 2543L–AVR–08/10 ATtiny2313 Pin Descriptions VCC Digital supply voltage. GND Ground. Port A (PA2..PA0) Port A is a 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATtiny2313 as listed on page 53. Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny2313 as listed on page 53. Port D (PD6..PD0) Port D is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATtiny2313 as listed on page 56. RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page 34. Shorter pulses are not guaranteed to generate a reset. The Reset Input is an alternate function for PA2 and dW. XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. XTAL1 is an alternate function for PA0. XTAL2 Output from the inverting Oscillator amplifier. XTAL2 is an alternate function for PA1.6 2543L–AVR–08/10 ATtiny2313 General Information Resources A comprehensive set of development tools, application notes and datasheets are available for downloadon http://www.atmel.com/avr. Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. Disclaimer Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.7 2543L–AVR–08/10 ATtiny2313 AVR CPU Core Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 3. Block Diagram of the AVR Architecture In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Flash Program Memory Instruction Register Instruction Decoder Program Counter Control Lines 32 x 8 General Purpose Registrers ALU Status and Control I/O Lines EEPROM Data Bus 8-bit Data SRAM Direct Addressing Indirect Addressing Interrupt Unit SPI Unit Watchdog Timer Analog Comparator I/O Module 2 I/O Module1 I/O Module n8 2543L–AVR–08/10 ATtiny2313 Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description. Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.9 2543L–AVR–08/10 ATtiny2313 The AVR Status Register – SREG – is defined as: • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. • Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information. • Bit 4 – S: Sign Bit, S = N ⊕ V The S-bit is always an exclusive or between the negative flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information. • Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 4 shows the structure of the 32 general purpose working registers in the CPU. Bit 7 6 5 4 3 2 1 0 I T H S V N Z C SREG Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 010 2543L–AVR–08/10 ATtiny2313 Figure 4. AVR CPU General Purpose Working Registers Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 4, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. The X-register, Yregister, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 5. Figure 5. The X-, Y-, and Z-registers In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 … R13 0x0D General R14 0x0E Purpose R15 0x0F Working R16 0x10 Registers R17 0x11 … R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte 15 XH XL 0 X-register 7 0 7 0 R27 (0x1B) R26 (0x1A) 15 YH YL 0 Y-register 7 0 7 0 R29 (0x1D) R28 (0x1C) 15 ZH ZL 0 Z-register 7 0 7 0 R31 (0x1F) R30 (0x1E)11 2543L–AVR–08/10 ATtiny2313 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 6. The Parallel Instruction Fetches and Instruction Executions Figure 7 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Bit 15 14 13 12 11 10 9 8 – – – – – – – – SPH SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 76543210 Read/Write R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND clk 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch T1 T2 T3 T4 CPU12 2543L–AVR–08/10 ATtiny2313 Figure 7. Single Cycle ALU Operation Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 44. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. Refer to “Interrupts” on page 44 for more information. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back T1 T2 T3 T4 clkCPU13 2543L–AVR–08/10 ATtiny2313 CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.. When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. Assembly Code Example in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1< xxx ... ... ... ... 46 2543L–AVR–08/10 ATtiny2313 I/O-Ports Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both VCC and Ground as indicated in Figure 21. Refer to “Electrical Characteristics” on page 177 for a complete list of parameters. Figure 21. I/O Pin Equivalent Schematic All registers and bit references in this section are written in general form. A lower case “x” represents the numbering letter for the port, and a lower case “n” represents the bit number. However, when using the register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Registers and bit locations are listed in “Register Description for I/O-Ports” on page 58. Three I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the pull-up function for all pins in all ports when set. Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page 47. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in “Alternate Port Functions” on page 51. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. Cpin Logic Rpu See Figure "General Digital I/O" for Details Pxn47 2543L–AVR–08/10 ATtiny2313 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 22 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 22. General Digital I/O(1) Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports. Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register Description for I/O-Ports” on page 58, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. clk RPx RRx RDx WDx PUD SYNCHRONIZER WDx: WRITE DDRx WRx: WRITE PORTx RRx: READ PORTx REGISTER RPx: READ PORTx PIN PUD: PULLUP DISABLE clkI/O: I/O CLOCK RDx: READ DDRx D L Q Q RESET RESET Q D Q Q Q D CLR PORTxn Q Q D CLR DDxn PINxn DATA BUS SLEEP SLEEP: SLEEP CONTROL Pxn I/O WPx 0 1 WRx WPx: WRITE PINx REGISTER48 2543L–AVR–08/10 ATtiny2313 Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step. Table 22 summarizes the control signals for the pin value. Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As shown in Figure 22, the PINxn Register bit and the preceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. Figure 23 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted tpd,max and tpd,min respectively. Figure 23. Synchronization when Reading an Externally Applied Pin value Table 22. Port Pin Configurations DDxn PORTxn PUD (in MCUCR) I/O Pull-up Comment 0 0 X Input No Tri-state (Hi-Z) 0 1 0 Input Yes Pxn will source current if ext. pulled low. 0 1 1 Input No Tri-state (Hi-Z) 1 0 X Output No Output Low (Sink) 1 1 X Output No Output High (Source) XXX in r17, PINx 0x00 0xFF INSTRUCTIONS SYNC LATCH PINxn r17 XXX SYSTEM CLK tpd, max tpd, min49 2543L–AVR–08/10 ATtiny2313 Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 24. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock period. Figure 24. Synchronization when Reading a Software Assigned Pin Value out PORTx, r16 nop in r17, PINx 0xFF 0x00 0xFF SYSTEM CLK r16 INSTRUCTIONS SYNC LATCH PINxn r17 t pd50 2543L–AVR–08/10 ATtiny2313 The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Note: 1. For the assembly program, two temporary registers are used to minimize the time from pullups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. Digital Input Enable and Sleep Modes As shown in Figure 22, the digital input signal can be clamped to ground at the input of the Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, and Standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to VCC/2. SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in “Alternate Port Functions” on page 51. If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change. Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1< CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is connected to. External Clock Source An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock (clkT1/clkT0). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 38 shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the internal system clock. The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects. Figure 38. T1/T0 Pin Sampling The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated. Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling freTn_sync (To Clock Select Logic) Synchronization Edge Detector D Q D Q LE Tn D Q clkI/O81 2543L–AVR–08/10 ATtiny2313 quency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 39. Prescaler for Timer/Counter0 and Timer/Counter1(1) Note: 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 38. General Timer/Counter Control Register – GTCCR • Bits 7..1 – Res: Reserved Bits These bits are reserved bits in the ATtiny2313 and will always read as zero. • Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0 When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. PSR10 Clear clkT1 clkT0 T1 T0 clkI/O Synchronization Synchronization Bit 7 6 5 4 3 2 1 0 — – – – – – — PSR10 GTCCR Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 082 2543L–AVR–08/10 ATtiny2313 16-bit Timer/Counter1 The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e., Allows 16-bit PWM) • Two independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceler • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Variable PWM Period • Frequency Generator • External Event Counter • Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1) Overview Most register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit channel. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on. A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 40. For the actual placement of I/O pins, refer to “Pinout ATtiny2313” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “16-bit Timer/Counter Register Description” on page 104. Figure 40. 16-bit Timer/Counter Block Diagram(1) Note: 1. Refer to Figure 1 on page 2 for Timer/Counter1 pin placement and description. Clock Select Timer/Counter DATA BUS OCRnA OCRnB ICRn = = TCNTn Waveform Generation Waveform Generation OCnA OCnB Noise Canceler ICPn = Fixed TOP Values Edge Detector Control Logic = 0 TOP BOTTOM Count Clear Direction TOVn (Int.Req.) OCnA (Int.Req.) OCnB (Int.Req.) ICFn (Int.Req.) TCCRnA TCCRnB ( From Analog Comparator Ouput ) Tn Edge Detector ( From Prescaler ) clkTn83 2543L–AVR–08/10 ATtiny2313 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are described in the section “Accessing 16-bit Registers” on page 84. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T1 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT1). The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter value at all time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC1A/B). See “Output Compare Units” on page 90.. The compare match event will also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICP1) or on the Analog Comparator pins (See “Analog Comparator” on page 149.) The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCR1A Register, the ICR1 Register, or by a set of fixed values. When using OCR1A as TOP value in a PWM mode, the OCR1A Register can not be used for generating a PWM output. However, the TOP value will in this case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP value is required, the ICR1 Register can be used as an alternative, freeing the OCR1A to be used as PWM output. Definitions The following definitions are used extensively throughout the section: Compatibility The 16-bit Timer/Counter has been updated and improved from previous versions of the 16-bit AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier version regarding: • All 16-bit Timer/Counter related I/O Register address locations, including Timer Interrupt Registers. • Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers. • Interrupt Vectors. The following control bits have changed name, but have same functionality and register location: • PWM10 is changed to WGM10. • PWM11 is changed to WGM11. • CTC1 is changed to WGM12. Table 42. Definitions BOTTOM The counter reaches the BOTTOM when it becomes 0x0000. MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCR1A or ICR1 Register. The assignment is dependent of the mode of operation.84 2543L–AVR–08/10 ATtiny2313 The following bits are added to the 16-bit Timer/Counter Control Registers: • FOC1A and FOC1B are added to TCCR1A. • WGM13 is added to TCCR1B. The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a 16-bit register is written by the CPU, the high byte stored in the temporary register, and the low byte written are both copied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read. Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR1A/B 16- bit registers does not involve using the temporary register. To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte. The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCR1A/B and ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit access.85 2543L–AVR–08/10 ATtiny2313 Note: 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. The assembly code example returns the TCNT1 value in the r17:r16 register pair. It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit timer registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. Assembly Code Examples(1) ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ... C Code Examples(1) unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into i */ i = TCNT1; ...86 2543L–AVR–08/10 ATtiny2313 The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Note: 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. The assembly code example returns the TCNT1 value in the r17:r16 register pair. Assembly Code Example(1) TIM16_ReadTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ; Restore global interrupt flag out SREG,r18 ret C Code Example(1) unsigned int TIM16_ReadTCNT1( void ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Read TCNT1 into i */ i = TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; }87 2543L–AVR–08/10 ATtiny2313 The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Note: 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNT1. Reusing the Temporary High Byte Register If writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. Assembly Code Example(1) TIM16_WriteTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Set TCNT1 to r17:r16 out TCNT1H,r17 out TCNT1L,r16 ; Restore global interrupt flag out SREG,r18 ret C Code Example(1) void TIM16_WriteTCNT1( unsigned int i ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Set TCNT1 to i */ TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg; }88 2543L–AVR–08/10 ATtiny2313 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits located in the Timer/Counter control Register B (TCCR1B). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 80. Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 41 shows a block diagram of the counter and its surroundings. Figure 41. Counter Unit Block Diagram Signal description (internal signals): Count Increment or decrement TCNT1 by 1. Direction Select between increment and decrement. Clear Clear TCNT1 (set all bits to zero). clkT1 Timer/Counter clock. TOP Signalize that TCNT1 has reached maximum value. BOTTOM Signalize that TCNT1 has reached minimum value (zero). The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) containing the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU does an access to the TCNT1H I/O location, the CPU accesses the high byte temporary register (TEMP). The temporary register is updated with the TCNT1H value when the TCNT1L is read, and TCNT1H is updated with the temporary register value when TCNT1L is written. This allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is important to notice that there are special cases of writing to the TCNT1 Register when the counter is counting that will give unpredictable results. The special cases are described in the sections where they are of importance. Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT1). The clkT1 can be generated from an external or internal clock source, selected by the Clock Select bits (CS12:0). When no clock source is selected (CS12:0 = 0) the timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of whether clkT1 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the Waveform Generation mode bits (WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC1x. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 94. TEMP (8-bit) DATA BUS (8-bit) TCNTn (16-bit Counter) TCNTnH (8-bit) TCNTnL (8-bit) Control Logic Count Clear Direction TOVn (Int.Req.) Clock Select TOP BOTTOM Tn Edge Detector ( From Prescaler ) clkTn89 2543L–AVR–08/10 ATtiny2313 The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP1 pin or alternatively, via the analog-comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events. The Input Capture unit is illustrated by the block diagram shown in Figure 42. The elements of the block diagram that are not directly a part of the Input Capture unit are gray shaded. The small “n” in register and bit names indicates the Timer/Counter number. Figure 42. Input Capture Unit Block Diagram When a change of the logic level (an event) occurs on the Input Capture pin (ICP1), alternatively on the Analog Comparator output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter (TCNT1) is written to the Input Capture Register (ICR1). The Input Capture Flag (ICF1) is set at the same system clock as the TCNT1 value is copied into ICR1 Register. If enabled (ICIE1 = 1), the Input Capture Flag generates an Input Capture interrupt. The ICF1 flag is automatically cleared when the interrupt is executed. Alternatively the ICF1 flag can be cleared by software by writing a logical one to its I/O bit location. Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the low byte (ICR1L) and then the high byte (ICR1H). When the low byte is read the high byte is copied into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP Register. The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Generation mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is written to ICR1L. ICFn (Int.Req.) Analog Comparator WRITE ICRn (16-bit Register) ICRnH (8-bit) Noise Canceler ICPn Edge Detector TEMP (8-bit) DATA BUS (8-bit) ICRnL (8-bit) TCNTn (16-bit Counter) TCNTnH (8-bit) TCNTnL (8-bit) ACO* ACIC* ICNC ICES90 2543L–AVR–08/10 ATtiny2313 For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 84. Input Capture Trigger Source The main trigger source for the Input Capture unit is the Input Capture pin (ICP1). Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change. Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled using the same technique as for the T1 pin (Figure 38 on page 80). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. Note that the input of the noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform Generation mode that uses ICR1 to define TOP. An Input Capture can be triggered by software by controlling the port of the ICP1 pin. Noise Canceler The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in Timer/Counter Control Register B (TCCR1B). When enabled the noise canceler introduces additional four system clock cycles of delay from a change applied to the input, to the update of the ICR1 Register. The noise canceler uses the system clock and is therefore not affected by the prescaler. Using the Input Capture Unit The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the incoming events. The time between two events is critical. If the processor has not read the captured value in the ICR1 Register before the next event occurs, the ICR1 will be overwritten with a new value. In this case the result of the capture will be incorrect. When using the Input Capture interrupt, the ICR1 Register should be read as early in the interrupt handler routine as possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICR1 Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 flag is not required (if an interrupt handler is used). Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF1x flag is automatically cleared when the interrupt is executed. Alternatively the OCF1x flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the Waveform Generation mode (WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP and BOTTOM signals91 2543L–AVR–08/10 ATtiny2313 are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (See “Modes of Operation” on page 94.) A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the Waveform Generator. Figure 43 shows a block diagram of the Output Compare unit. The small “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded. Figure 43. Output Compare Unit, Block Diagram The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR1x Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x directly. The content of the OCR1x (Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the high byte temporary register (TEMP). However, it is a good practice to read the low byte first as when accessing other 16-bit registers. Writing the OCR1x Registers must be done via the TEMP Register since the compare of all 16 bits is done continuously. The high byte (OCR1xH) has to be written first. When the high byte I/O location is written by the CPU, the TEMP Register will be updated by the value written. Then when the low byte (OCR1xL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare Register in the same system clock cycle. OCFnx (Int.Req.) = (16-bit Comparator ) OCRnx Buffer (16-bit Register) OCRnxH Buf. (8-bit) OCnx TEMP (8-bit) DATA BUS (8-bit) OCRnxL Buf. (8-bit) TCNTn (16-bit Counter) TCNTnH (8-bit) TCNTnL (8-bit) WGMn3:0 COMnx1:0 OCRnx (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) Waveform Generator TOP BOTTOM92 2543L–AVR–08/10 ATtiny2313 For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 84. Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC1x) bit. Forcing compare match will not set the OCF1x flag or reload/clear the timer, but the OC1x pin will be updated as if a real compare match had occurred (the COM11:0 bits settings define whether the OC1x pin is set, cleared or toggled). Compare Match Blocking by TCNT1 Write All CPU writes to the TCNT1 Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled. Using the Output Compare Unit Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT1 when using any of the Output Compare channels, independent of whether the Timer/Counter is running or not. If the value written to TCNT1 equals the OCR1x value, the compare match will be missed, resulting in incorrect waveform generation. Do not write the TCNT1 equal to TOP in PWM modes with variable TOP values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF. Similarly, do not write the TCNT1 value equal to BOTTOM when the counter is downcounting. The setup of the OC1x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC1x value is to use the Force Output Compare (FOC1x) strobe bits in Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately.93 2543L–AVR–08/10 ATtiny2313 Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 44 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to the OC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a system reset occur, the OC1x Register is reset to “0”. Figure 44. Compare Match Output Unit, Schematic The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform Generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x value is visible on the pin. The port override function is generally independent of the Waveform Generation mode, but there are some exceptions. Refer to Table 43, Table 44 and Table 45 for details. The design of the Output Compare pin logic allows initialization of the OC1x state before the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation. See “16-bit Timer/Counter Register Description” on page 104. The COM1x1:0 bits have no effect on the Input Capture unit. PORT DDR D Q D Q OCnx OCnx Pin D Q Waveform Generator COMnx1 COMnx0 0 1 DATA BUS FOCnx clkI/O94 2543L–AVR–08/10 ATtiny2313 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no action on the OC1x Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 43 on page 104. For fast PWM mode refer to Table 44 on page 104, and for phase correct and phase and frequency correct PWM refer to Table 45 on page 105. A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits. Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Output mode (COM1x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM1x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM1x1:0 bits control whether the output should be set, cleared or toggle at a compare match (See “Compare Match Output Unit” on page 93.) For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 102. Normal Mode The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOV1) will be set in the same timer clock cycle as the TCNT1 becomes zero. The TOV1 flag in this case behaves like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV1 flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the external events must not exceed the resolution of the counter. If the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Register are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 45 on page 95. The counter value (TCNT1) increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared.95 2543L–AVR–08/10 ATtiny2313 Figure 45. CTC Mode, Timing Diagram An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR1A or ICR1 is lower than the current value of TCNT1, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode using OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double buffered. For generating a waveform output in CTC mode, the OCFA output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM1A1:0 = 1). The OCF1A value will not be visible on the port pin unless the data direction for the pin is set to output (DDR_OCF1A = 1). The waveform generated will have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). The waveform frequency is defined by the following equation: The N variable represents the prescaler factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV1 flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000. TCNTn OCnA (Toggle) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) Period 1 2 3 4 (COMnA1:0 = 1) f OCnA f clk_I/O 2 ⋅ ⋅ N ( ) 1 + OCRnA = --------------------------------------------------96 2543L–AVR–08/10 ATtiny2313 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is set on the compare match between TCNT1 and OCR1x, and cleared at TOP. In inverting Compare Output mode output is cleared on compare match and set at TOP. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 = 14), or the value in OCR1A (WGM13:0 = 15). The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 46. The figure shows fast PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x interrupt flag will be set when a compare match occurs. Figure 46. Fast PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition the OCF1A or ICF1 flag is set at the same timer clock cycle as TOV1 is set when either OCR1A or ICR1 is used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and compare values. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. RFPWM log( ) TOP + 1 log( ) 2 = ----------------------------------- TCNTn OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) Period 1 2 3 4 5 6 7 8 OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3)97 2543L–AVR–08/10 ATtiny2313 Note that when using fixed TOP values the unused bits are masked to zero when any of the OCR1x Registers are written. The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value. The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new ICR1 value written is lower than the current value of TCNT1. The result will then be that the counter will miss the compare match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location to be written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 flag is set. Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed (by changing the TOP value), using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to three (see Table 43 on page 104). The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the compare match between OCR1x and TCNT1, and clearing (or setting) the OC1x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR1x is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR1x equal to TOP will result in a constant high or low output (depending on the polarity of the output set by the COM1x1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OCF1A to toggle its logical level on each compare match (COM1A1:0 = 1). The waveform generated will have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). This feature is similar to the OCF1A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. f OCnxPWM f clk_I/O N ⋅ ( ) 1 + TOP = -----------------------------------98 2543L–AVR–08/10 ATtiny2313 Phase Correct PWM Mode The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dualslope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x while upcounting, and set on the compare match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 47. The figure shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x interrupt flag will be set when a compare match occurs. Figure 47. Phase Correct PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When either OCR1A or ICR1 is used for defining the TOP value, the OCF1A or ICF1 flag is set accordingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer RPCPWM log( ) TOP + 1 log( ) 2 = ----------------------------------- OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) 1 2 3 4 TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn Period OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3)99 2543L–AVR–08/10 ATtiny2313 value (at TOP). The interrupt flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values, the unused bits are masked to zero when any of the OCR1x Registers are written. As the third period shown in Figure 47 illustrates, changing the TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Register. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output. It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically no differences between the two modes of operation. In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to three (See Table 44 on page 104). The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the compare match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at compare match between OCR1x and TCNT1 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. f OCnxPCPWM f clk_I/O 2 ⋅ ⋅ N TOP = ----------------------------100 2543L–AVR–08/10 ATtiny2313 Phase and Frequency Correct PWM Mode The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation option. The phase and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x while upcounting, and set on the compare match while downcounting. In inverting Compare Output mode, the operation is inverted. The dual-slope operation gives a lower maximum operation frequency compared to the single-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the OCR1x Register is updated by the OCR1x Buffer Register, (see Figure 47 and Figure 48). The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown on Figure 48. The figure shows phase and frequency correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes noninverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x interrupt flag will be set when a compare match occurs. Figure 48. Phase and Frequency Correct PWM Mode, Timing Diagram RPFCPWM log( ) TOP + 1 log( ) 2 = ----------------------------------- OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) 1 2 3 4 TCNTn Period OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3)101 2543L–AVR–08/10 ATtiny2313 The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the OCF1A or ICF1 flag set when TCNT1 has reached TOP. The interrupt flags can then be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. As Figure 48 shows the output generated is, in contrast to the phase correct mode, symmetrical in all periods. Since the OCR1x Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct. Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to three (See Table 45 on page 105). The actual OC1Fx value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OCF1x). The PWM waveform is generated by setting (or clearing) the OCF1x Register at the compare match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OCF1x Register at compare match between OCR1x and TCNT1 when the counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for noninverted PWM mode. For inverted PWM the output will have the opposite logic values. f OCnxPFCPWM f clk_I/O 2 ⋅ ⋅ N TOP = ----------------------------102 2543L–AVR–08/10 ATtiny2313 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal in the following figures. The figures include information on when interrupt flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double buffering). Figure 49 shows a timing diagram for the setting of OCF1x. Figure 49. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling Figure 50 shows the same timing data, but with the prescaler enabled. Figure 50. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8) Figure 51 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 flag at BOTTOM. clkTn (clkI/O/1) OCFnx clkI/O OCRnx TCNTn OCRnx Value OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCFnx OCRnx TCNTn OCRnx Value OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 clkI/O clkTn (clkI/O/8)103 2543L–AVR–08/10 ATtiny2313 Figure 51. Timer/Counter Timing Diagram, no Prescaling Figure 52 shows the same timing data, but with the prescaler enabled. Figure 52. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 Old OCRnx Value New OCRnx Value TOP - 1 TOP BOTTOM BOTTOM + 1 clkTn (clkI/O/1) clkI/O TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 Old OCRnx Value New OCRnx Value TOP - 1 TOP BOTTOM BOTTOM + 1 clkI/O clkTn (clkI/O/8)104 2543L–AVR–08/10 ATtiny2313 16-bit Timer/Counter Register Description Timer/Counter1 Control Register A – TCCR1A • Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A • Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respectively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC1A or OC1B pin must be set in order to enable the output driver. When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is dependent of the WGM13:0 bits setting. Table 43 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to a Normal or a CTC mode (non-PWM). Table 44 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Bit 7 6 5 4 3 2 1 0 COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 TCCR1A Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 43. Compare Output Mode, non-PWM COM1A1/COM1B1 COM1A0/COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 Toggle OC1A/OC1B on Compare Match. 1 0 Clear OC1A/OC1B on Compare Match (Set output to low level). 1 1 Set OC1A/OC1B on Compare Match (Set output to high level). Table 44. Compare Output Mode, Fast PWM(1) COM1A1/COM1B1 COM1A0/COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13=0: Normal port operation, OC1A/OC1B disconnected. WGM13=1: Toggle OC1A on Compare Match, OC1B reserved. 1 0 Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at TOP 1 1 Set OC1A/OC1B on Compare Match, clear OC1A/OC1B at TOP105 2543L–AVR–08/10 ATtiny2313 Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the compare match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 96. for more details. Table 45 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See “Phase Correct PWM Mode” on page 98. for more details. • Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 46. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 94.). Table 45. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1) COM1A1/COM1B1 COM1A0/COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13=0: Normal port operation, OC1A/OC1B disconnected. WGM13=1: Toggle OC1A on Compare Match, OC1B reserved. 1 0 Clear OC1A/OC1B on Compare Match when upcounting. Set OC1A/OC1B on Compare Match when downcounting. 1 1 Set OC1A/OC1B on Compare Match when upcounting. Clear OC1A/OC1B on Compare Match when downcounting.106 2543L–AVR–08/10 ATtiny2313 Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. Table 46. Waveform Generation Mode Bit Description(1) Mode WGM13 WGM12 (CTC1) WGM11 (PWM11) WGM10 (PWM10) Timer/Counter Mode of Operation TOP Update of OCR1x at TOV1 Flag Set on 0 0 0 0 0 Normal 0xFFFF Immediate MAX 1 0 0 0 1 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM 2 0 0 1 0 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM 3 0 0 1 1 PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM 4 0 1 0 0 CTC OCR1A Immediate MAX 5 0 1 0 1 Fast PWM, 8-bit 0x00FF TOP TOP 6 0 1 1 0 Fast PWM, 9-bit 0x01FF TOP TOP 7 0 1 1 1 Fast PWM, 10-bit 0x03FF TOP TOP 8 1 0 0 0 PWM, Phase and Frequency Correct ICR1 BOTTOM BOTTOM 9 1 0 0 1 PWM, Phase and Frequency Correct OCR1A BOTTOM BOTTOM 10 1 0 1 0 PWM, Phase Correct ICR1 TOP BOTTOM 11 1 0 1 1 PWM, Phase Correct OCR1A TOP BOTTOM 12 1 1 0 0 CTC ICR1 Immediate MAX 13 1 1 0 1 (Reserved) – – – 14 1 1 1 0 Fast PWM ICR1 TOP TOP 15 1 1 1 1 Fast PWM OCR1A TOP TOP107 2543L–AVR–08/10 ATtiny2313 Timer/Counter1 Control Register B – TCCR1B • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture pin (ICP1) is filtered. The filter function requires four successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled. • Bit 6 – ICES1: Input Capture Edge Select This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled. • Bit 5 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCR1B is written. • Bit 4:3 – WGM13:2: Waveform Generation Mode See TCCR1A Register description. • Bit 2:0 – CS12:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure 49 and Figure 50. If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. Bit 7 6 5 4 3 2 1 0 ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 47. Clock Select Bit Description CS12 CS11 CS10 Description 0 0 0 No clock source (Timer/Counter stopped). 0 0 1 clkI/O/1 (No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T1 pin. Clock on falling edge. 1 1 1 External clock source on T1 pin. Clock on rising edge.108 2543L–AVR–08/10 ATtiny2313 Timer/Counter1 Control Register C – TCCR1C • Bit 7 – FOC1A: Force Output Compare for Channel A • Bit 6 – FOC1B: Force Output Compare for Channel B The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. Timer/Counter1 – TCNT1H and TCNT1L The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 84. Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a compare match between TCNT1 and one of the OCR1x Registers. Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock for all compare units. Output Compare Register 1 A – OCR1AH and OCR1AL Bit 7 6 5 4 3 2 1 0 FOC1A FOC1B – – – – – – TCCR1C Read/Write W W R R R R R R Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 TCNT1[15:8] TCNT1H TCNT1[7:0] TCNT1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OCR1A[15:8] OCR1AH OCR1A[7:0] OCR1AL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0109 2543L–AVR–08/10 ATtiny2313 Output Compare Register 1 B - OCR1BH and OCR1BL The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC1x pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16- bit registers. See “Accessing 16-bit Registers” on page 84. Input Capture Register 1 – ICR1H and ICR1L The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 84. Timer/Counter Interrupt Mask Register – TIMSK • Bit 7 – TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 44.) is executed when the TOV1 flag, located in TIFR, is set. • Bit 6 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 44.) is executed when the OCF1A flag, located in TIFR, is set. • Bit 5 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 44.) is executed when the OCF1B flag, located in TIFR, is set. • Bit 3 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable Bit 7 6 5 4 3 2 1 0 OCR1B[15:8] OCR1BH OCR1B[7:0] OCR1BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 ICR1[15:8] ICR1H ICR1[7:0] ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 TOIE1 OCIE1A OCIE1B – ICIE1 OCIE0B TOIE0 OCIE0A TIMSK Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0110 2543L–AVR–08/10 ATtiny2313 When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 44.) is executed when the ICF1 flag, located in TIFR, is set. Timer/Counter Interrupt Flag Register – TIFR • Bit 7 – TOV1: Timer/Counter1, Overflow Flag The setting of this flag is dependent of the WGM13:0 bits setting. In Normal and CTC modes, the TOV1 flag is set when the timer overflows. Refer to Table 46 on page 106 for the TOV1 flag behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. • Bit 6 – OCF1A: Timer/Counter1, Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A (OCR1A). Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A flag. OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location. • Bit 5 – OCF1B: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B (OCR1B). Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B flag. OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location. • Bit 3 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 flag is set when the counter reaches the TOP value. ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location. Bit 7 6 5 4 3 2 1 0 TOV1 OCF1A OCF1B – ICF1 OCF0B TOV0 OCF0A TIFR Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0111 2543L–AVR–08/10 ATtiny2313 USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous Communication Mode Overview A simplified block diagram of the USART Transmitter is shown in Figure 53. CPU accessible I/O Registers and I/O pins are shown in bold. Figure 53. USART Block Diagram(1) Note: 1. Refer to Figure 1 on page 2, Table 29 on page 57, and Table 26 on page 55 for USART pin placement. PARITY GENERATOR UBRR[H:L] UDR (Transmit) UCSRA UCSRB UCSRC BAUD RATE GENERATOR TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER RxD TxD PIN CONTROL UDR (Receive) PIN CONTROL XCK DATA RECOVERY CLOCK RECOVERY PIN CONTROL TX CONTROL RX CONTROL PARITY CHECKER DATA BUS OSC SYNC LOGIC Clock Generator Transmitter Receiver112 2543L–AVR–08/10 ATtiny2313 The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control registers are shared by all units. The Clock Generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only used by synchronous transfer mode. The Transmitter consists of a single write buffer, a serial Shift Register, Parity Generator and Control logic for handling different serial frame formats. The write buffer allows a continuous transfer of data without any delay between frames. The Receiver is the most complex part of the USART module due to its clock and data recovery units. The recovery units are used for asynchronous data reception. In addition to the recovery units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level receive buffer (UDR). The Receiver supports the same frame formats as the Transmitter, and can detect Frame Error, Data OverRun and Parity Errors. AVR USART vs. AVR UART – Compatibility The USART is fully compatible with the AVR UART regarding: • Bit locations inside all USART Registers. • Baud Rate Generation. • Transmitter Operation. • Transmit Buffer Functionality. • Receiver Operation. However, the receive buffering has two improvements that will affect the compatibility in some special cases: • A second Buffer Register has been added. The two Buffer Registers operate as a circular FIFO buffer. Therefore the UDR must only be read once for each incoming data! More important is the fact that the error flags (FE and DOR) and the ninth data bit (RXB8) are buffered with the data in the receive buffer. Therefore the status bits must always be read before the UDR Register is read. Otherwise the error status will be lost since the buffer state is lost. • The Receiver Shift Register can now act as a third buffer level. This is done by allowing the received data to remain in the serial Shift Register (see Figure 53) if the Buffer Registers are full, until a new start bit is detected. The USART is therefore more resistant to Data OverRun (DOR) error conditions. The following control bits have changed name, but have same functionality and register location: • CHR9 is changed to UCSZ2. • OR is changed to DOR. Clock Generation The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation: Normal asynchronous, Double Speed asynchronous, Master synchronous and Slave synchronous mode. The UMSEL bit in USART Control and Status Register C (UCSRC) selects between asynchronous and synchronous operation. Double Speed (asynchronous mode only) is controlled by the U2X found in the UCSRA Register. When using synchronous mode (UMSEL = 1), the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using synchronous mode. Figure 54 shows a block diagram of the clock generation logic.113 2543L–AVR–08/10 ATtiny2313 Figure 54. Clock Generation Logic, Block Diagram Signal description: txclk Transmitter clock (Internal Signal). rxclk Receiver base clock (Internal Signal). xcki Input from XCK pin (internal Signal). Used for synchronous slave operation. xcko Clock output to XCK pin (Internal Signal). Used for synchronous master operation. fosc XTAL pin frequency (System Clock). Internal Clock Generation – The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The description in this section refers to Figure 54. The USART Baud Rate Register (UBRR) and the down-counter connected to it function as a programmable prescaler or baud rate generator. The down-counter, running at system clock (fosc), is loaded with the UBRR value each time the counter has counted down to zero or when the UBRRL Register is written. A clock is generated each time the counter reaches zero. This clock is the baud rate generator clock output (= fosc/(UBRR+1)). The Transmitter divides the baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator output is used directly by the Receiver’s clock and data recovery units. However, the recovery units use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the UMSEL, U2X and DDR_XCK bits. Table 48 contains equations for calculating the baud rate (in bits per second) and for calculating the UBRR value for each mode of operation using an internally generated clock source. Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps) Prescaling Down-Counter /2 UBRR /4 /2 fosc UBRR+1 Sync Register OSC XCK Pin txclk U2X UMSEL DDR_XCK 0 1 0 1 xcki xcko DDR_XCK rxclk 0 1 1 0 Edge Detector UCPOL Table 48. Equations for Calculating Baud Rate Register Setting Operating Mode Equation for Calculating Baud Rate(1) Equation for Calculating UBRR Value Asynchronous Normal mode (U2X = 0) Asynchronous Double Speed mode (U2X = 1) Synchronous Master mode BAUD f OSC 16( ) UBRR + 1 = -------------------------------------- UBRR f OSC 16BAUD = ------------------------ – 1 BAUD f OSC 8( ) UBRR + 1 = ----------------------------------- UBRR f OSC 8BAUD = -------------------- – 1 BAUD f OSC 2( ) UBRR + 1 = ----------------------------------- UBRR f OSC 2BAUD = -------------------- – 1114 2543L–AVR–08/10 ATtiny2313 BAUD Baud rate (in bits per second, bps) fOSC System Oscillator clock frequency UBRR Contents of the UBRRH and UBRRL Registers, (0-4095) Some examples of UBRR values for some system clock frequencies are found in Table 56 (see page 134). Double Speed Operation (U2X) The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only has effect for the asynchronous operation. Set this bit to zero when using synchronous operation. Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for asynchronous communication. Note however that the Receiver will in this case only use half the number of samples (reduced from 16 to 8) for data sampling and clock recovery, and therefore a more accurate baud rate setting and system clock are required when this mode is used. For the Transmitter, there are no downsides. External Clock External clocking is used by the synchronous slave modes of operation. The description in this section refers to Figure 54 for details. External clock input from the XCK pin is sampled by a synchronization register to minimize the chance of meta-stability. The output from the synchronization register must then pass through an edge detector before it can be used by the Transmitter and Receiver. This process introduces a two CPU clock period delay and therefore the maximum external XCK clock frequency is limited by the following equation: Note that fosc depends on the stability of the system clock source. It is therefore recommended to add some margin to avoid possible loss of data due to frequency variations. Synchronous Clock Operation When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed. Figure 55. Synchronous Mode XCK Timing. The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is used for data change. As Figure 55 shows, when UCPOL is zero the data will be changed at risf XCK f OSC 4 < ----------- RxD / TxD XCK RxD / TxD UCPOL = 0 XCK UCPOL = 1 Sample Sample115 2543L–AVR–08/10 ATtiny2313 ing XCK edge and sampled at falling XCK edge. If UCPOL is set, the data will be changed at falling XCK edge and sampled at rising XCK edge. Frame Formats A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame formats: • 1 start bit • 5, 6, 7, 8, or 9 data bits • no, even or odd parity bit • 1 or 2 stop bits A frame starts with the start bit followed by the least significant data bit. Then the next data bits, up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle (high) state. Figure 56 illustrates the possible combinations of the frame formats. Bits inside brackets are optional. Figure 56. Frame Formats St Start bit, always low. (n) Data bits (0 to 8). P Parity bit. Can be odd or even. Sp Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in UCSRB and UCSRC. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter. The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame. The USART Parity mode (UPM1:0) bits enable and set the type of parity bit. The selection between one or two stop bits is done by the USART Stop Bit Select (USBS) bit. The Receiver ignores the second stop bit. An FE (Frame Error) will therefore only be detected in the cases where the first stop bit is zero. Parity Bit Calculation The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of the exclusive or is inverted. The relation between the parity bit and data bits is as follows: Peven Parity bit using even parity Podd Parity bit using odd parity (IDLE) St Sp1 [Sp2] 0 2 3 4 [5] [6] [7] [8] [P] 1 (St / IDLE) FRAME Peven dn – 1 … d3 d2 d1 d0 0 Podd ⊕⊕⊕⊕⊕⊕ dn – 1 … d3 d2 d1 d0 ⊕⊕⊕⊕⊕⊕ 1 = =116 2543L–AVR–08/10 ATtiny2313 dn Data bit n of the character If used, the parity bit is located between the last data bit and first stop bit of a serial frame. USART Initialization The USART has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the initialization. Before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the registers are changed. The TXC flag can be used to check that the Transmitter has completed all transfers, and the RXC flag can be used to check that there are no unread data in the receive buffer. Note that the TXC flag must be cleared before each transmission (before UDR is written) if it is used for this purpose. The following simple USART initialization code examples show one assembly and one C function that are equal in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers. Note: 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Assembly Code Example(1) USART_Init: ; Set baud rate out UBRRH, r17 out UBRRL, r16 ; Enable receiver and transmitter ldi r16, (1<>8); UBRRL = (unsigned char)baud; /* Enable receiver and transmitter */ UCSRB = (1<> 1) & 0x01; return ((resh << 8) | resl); }123 2543L–AVR–08/10 ATtiny2313 Note: 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXC) flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit will become zero. When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART Receive Complete interrupt will be executed as long as the RXC flag is set (provided that global interrupts are enabled). When interrupt-driven data reception is used, the receive complete routine must read the received data from UDR in order to clear the RXC flag, otherwise a new interrupt will occur once the interrupt routine terminates. Receiver Error Flags The USART Receiver has three error flags: Frame Error (FE), Data OverRun (DOR) and Parity Error (UPE). All can be accessed by reading UCSRA. Common for the error flags is that they are located in the receive buffer together with the frame for which they indicate the error status. Due to the buffering of the error flags, the UCSRA must be read before the receive buffer (UDR), since reading the UDR I/O location changes the buffer read location. Another equality for the error flags is that they can not be altered by software doing a write to the flag location. However, all flags must be set to zero when the UCSRA is written for upward compatibility of future USART implementations. None of the error flags can generate interrupts. The Frame Error (FE) flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. The FE flag is zero when the stop bit was correctly read (as one), and the FE flag will be one when the stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. The FE flag is not affected by the setting of the USBS bit in UCSRC since the Receiver ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when writing to UCSRA. The Data OverRun (DOR) flag indicates data loss due to a receiver buffer full condition. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. If the DOR flag is set there was one or more serial frame lost between the frame last read from UDR, and the next frame read from UDR. For compatibility with future devices, always write this bit to zero when writing to UCSRA. The DOR flag is cleared when the frame received was successfully moved from the Shift Register to the receive buffer. The Parity Error (UPE) Flag indicates that the next frame in the receive buffer had a Parity Error when received. If Parity Check is not enabled the UPE bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRA. For more details see “Parity Bit Calculation” on page 115 and “Parity Checker” on page 124.124 2543L–AVR–08/10 ATtiny2313 Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of Parity Check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPE) flag can then be read by software to check if the frame had a Parity Error. The UPE bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is read. Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e., the RXEN is set to zero) the Receiver will no longer override the normal function of the RxD port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost Flushing the Receive Buffer The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDR I/O location until the RXC flag is cleared. The following code example shows how to flush the receive buffer. Note: 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Asynchronous Data Reception The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the RxD pin. The data recovery logic samples and low pass filters each incoming bit, thereby improving the noise immunity of the Receiver. The asynchronous reception operational range depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. Assembly Code Example(1) USART_Flush: sbis UCSRA, RXC ret in r16, UDR rjmp USART_Flush C Code Example(1) void USART_Flush( void ) { unsigned char dummy; while ( UCSRA & (1< 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz t BVDV BS1 Valid to DATA valid 0 250 ns tOLDV OE Low to DATA Valid 250 ns tOHDZ OE High to DATA Tri-stated 250 ns Table 76. Parallel Programming Characteristics, VCC = 5V ± 10% (Continued) Symbol Parameter Min Typ Max Units VCC GND XTAL1 SCK MISO MOSI RESET +1.8 - 5.5V173 2543L–AVR–08/10 ATtiny2313 Serial Programming Algorithm When writing serial data to the ATtiny2313, data is clocked on the rising edge of SCK. When reading data from the ATtiny2313, data is clocked on the falling edge of SCK. See Figure 79, Figure 80 and Table 79 for timing details. To program and verify the ATtiny2313 in the serial programming mode, the following sequence is recommended (See four byte instruction formats in Table 78 on page 174): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”. 2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI. 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 4 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 6 MSB of the address. If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 77 on page 174.) Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming. 5. A: The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling (RDY/BSY) is not used, the user must wait at least tWD_EEPROM before issuing the next byte. (See Table 77 on page 174.) In a chip erased device, no 0xFFs in the data file(s) need to be programmed. B: The EEPROM array is programmed one page at a time. The Memory page is loaded one byte at a time by supplying the 2 LSB of the address and data together with the Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading the Write EEPROM Memory Page Instruction with the 5 MSB of the address. When using EEPROM page access only byte locations loaded with the Load EEPROM Memory Page instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is not used, the used must wait at least tWD_EEPROM before issuing the next page (See Table 77 on page 174). In a chip erased device, no 0xFF in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to “1”. Turn VCC power off.174 2543L–AVR–08/10 ATtiny2313 Figure 79. Serial Programming Waveforms Table 77. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay tWD_FLASH 4.5 ms tWD_EEPROM 4.0 ms tWD_ERASE 9.0 ms tWD_FUSE 4.5 ms MSB MSB LSB LSB SERIAL CLOCK INPUT (SCK) SERIAL DATA INPUT (MOSI) (MISO) SAMPLE SERIAL DATA OUTPUT Table 78. Serial Programming Instruction Set Instruction Instruction Format Byte 1 Byte 2 Byte 3 Byte4 Operation Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after RESET goes low. Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash. Read Program Memory 0010 H000 0000 00aa bbbb bbbb oooo oooo Read H (high or low) data o from Program memory at word address a:b. Load Program Memory Page 0100 H000 000x xxxx xxxx bbbb iiii iiii Write H (high or low) data i to Program Memory page at word address b. Data low byte must be loaded before Data high byte is applied within the same address. Write Program Memory Page 0100 1100 0000 00aa bbbb xxxx xxxx xxxx Write Program Memory Page at address a:b. Read EEPROM Memory 1010 0000 000x xxxx xbbb bbbb oooo oooo Read data o from EEPROM memory at address b. Write EEPROM Memory 1100 0000 000x xxxx xbbb bbbb iiii iiii Write data i to EEPROM memory at address b. Load EEPROM Memory Page (page access) 1100 0001 0000 0000 0000 00bb iiii iiii Load data i to EEPROM memory page buffer. After data is loaded, program EEPROM page. Write EEPROM Memory Page (page access) 1100 0010 00xx xxxx xbbb bb00 xxxx xxxx Write EEPROM page at address b.175 2543L–AVR–08/10 ATtiny2313 Note: a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Read Lock bits 0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock bits. “0” = programmed, “1” = unprogrammed. See Table 64 on page 158 for details. Write Lock bits 1010 1100 111x xxxx xxxx xxxx 11ii iiii Write Lock bits. Set bits = “0” to program Lock bits. See Table 64 on page 158 for details. Read Signature Byte 0011 0000 000x xxxx xxxx xxbb oooo oooo Read Signature Byte o at address b. Write Fuse bits 1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to unprogram. Write Fuse High bits 1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to unprogram. Write Extended Fuse Bits 1010 1100 1010 0100 xxxx xxxx xxxx xxxi Set bits = “0” to program, “1” to unprogram. Read Fuse bits 0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fuse bits. “0” = programmed, “1” = unprogrammed. Read Fuse High bits 0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fuse High bits. “0” = programmed, “1” = unprogrammed. Read Extended Fuse Bits 0101 0000 0000 1000 xxxx xxxx oooo oooo Read Extended Fuse bits. “0” = programmed, “1” = unprogrammed. Read Calibration Byte 0011 1000 000x xxxx 0000 000b oooo oooo Read Calibration Byte at address b. Poll RDY/BSY 1111 0000 0000 0000 xxxx xxxx xxxx xxxo If o = “1”, a programming operation is still busy. Wait until this bit returns to “0” before applying another command. Table 78. Serial Programming Instruction Set Instruction Instruction Format Byte 1 Byte 2 Byte 3 Byte4 Operation176 2543L–AVR–08/10 ATtiny2313 Serial Programming Characteristics Figure 80. Serial Programming Timing Note: 1. 2 tCLCL for fck < 12 MHz, 3 tCLCL for fck >= 12 MHz Table 79. Serial Programming Characteristics, TA = -40°C to +85°C, VCC = 2.7V - 5.5V (Unless Otherwise Noted) Symbol Parameter Min Typ Max Units 1/tCLCL Oscillator Frequency (ATtiny2313L) 0 10 MHz tCLCL Oscillator Period (ATtiny2313L) 125 ns 1/tCLCL Oscillator Frequency (ATtiny2313, VCC = 4.5V - 5.5V) 0 20 MHz tCLCL Oscillator Period (ATtiny2313, VCC = 4.5V - 5.5V) 67 ns tSHSL SCK Pulse Width High 2 tCLCL* ns tSLSH SCK Pulse Width Low 2 tCLCL* ns tOVSH MOSI Setup to SCK High tCLCL ns tSHOX MOSI Hold after SCK High 2 tCLCL ns tSLIV SCK Low to MISO Valid 100 ns MOSI MISO SCK t OVSH t SHSL t t SHOX SLSH t SLIV177 2543L–AVR–08/10 ATtiny2313 Electrical Characteristics Absolute Maximum Ratings* DC Characteristics Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Maximum Operating Voltage ............................................ 6.0V DC Current per I/O Pin ............................................... 40.0 mA DC Current VCC and GND Pins ................................ 200.0 mA TA = -40°C to +85°C, VCC = 1.8V to 5.5V (unless otherwise noted)(1) Symbol Parameter Condition Min. Typ.(2) Max. Units VIL Input Low Voltage except XTAL1 and RESET pin VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V -0.5 0.2VCC(3) 0.3VCC(3) V VIH Input High-voltage except XTAL1 and RESET pins VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V 0.7VCC(4) 0.6VCC(4) VCC +0.5 V VIL1 Input Low Voltage XTAL1 pin VCC = 1.8V - 5.5V -0.5 0.1VCC(3) V VIH1 Input High-voltage XTAL1 pin VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V 0.8VCC(4) 0.7VCC(4) VCC +0.5 V VIL2 Input Low Voltage RESET pin VCC = 1.8V - 5.5V -0.5 0.2VCC(3) V VIH2 Input High-voltage RESET pin VCC = 1.8V - 5.5V 0.9VCC(4) VCC +0.5 V VIL3 Input Low Voltage RESET pin as I/O VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V -0.5 0.2VCC(3) 0.3VCC(3) V VIH3 Input High-voltage RESET pin as I/O VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V 0.7VCC(4) 0.6VCC(4) VCC +0.5 V VOL Output Low Voltage(5) (Port A, Port B, Port D) I OL = 20 mA, VCC = 5V IOL = 10 mA, VCC = 3V 0.7 0.5 V V VOH Output High-voltage(6) (Port A, Port B, Port D) I OH = -20 mA, VCC = 5V IOH = -10 mA, VCC = 3V 4.2 2.5 V V IIL Input Leakage Current I/O Pin VCC = 5.5V, pin low (absolute value) 1 µA IIH Input Leakage Current I/O Pin VCC = 5.5V, pin high (absolute value) 1 µA RRST Reset Pull-up Resistor 30 60 kΩ Rpu I/O Pin Pull-up Resistor 20 50 kΩ178 2543L–AVR–08/10 ATtiny2313 Notes: 1. All DC Characteristics contained in this data sheet are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are preliminary values representing design targets, and will be updated after characterization of actual silicon. 2. Typical values at +25°C. 3. “Max” means the highest value where the pin is guaranteed to be read as low. 4. “Min” means the lowest value where the pin is guaranteed to be read as high. 5. Although each I/O port can sink more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: 1] The sum of all IOL, for all ports, should not exceed 60 mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 6. Although each I/O port can source more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: 1] The sum of all IOH, for all ports, should not exceed 60 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. ICC Power Supply Current Active 1MHz, VCC = 2V 0.35 mA Active 4MHz, VCC = 3V 2 mA Active 8MHz, VCC = 5V 6 mA Idle 1MHz, VCC = 2V 0.08 0.2 mA Idle 4MHz, VCC = 3V 0.41 1 mA Idle 8MHz, VCC = 5V 1.6 3 mA Power-down mode WDT enabled, VCC = 3V < 3 6 µA WDT disabled, VCC = 3V < 0.5 2 µA VACIO Analog Comparator Input Offset Voltage VCC = 5V Vin = VCC/2 < 10 40 mV IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/2 -50 50 nA t ACPD Analog Comparator Propagation Delay VCC = 2.7V VCC = 5.0V 750 500 ns TA = -40°C to +85°C, VCC = 1.8V to 5.5V (unless otherwise noted)(1) (Continued) Symbol Parameter Condition Min. Typ.(2) Max. Units179 2543L–AVR–08/10 ATtiny2313 External Clock Drive Waveforms Figure 81. External Clock Drive Waveforms External Clock Drive VIL1 VIH1 Table 80. External Clock Drive (Estimated Values) Symbol Parameter VCC = 1.8 - 5.5V VCC = 2.7 - 5.5V VCC = 4.5 - 5.5V Min. Max. Min. Max. Min. Max. Units 1/tCLCL Oscillator Frequency 0 4 0 10 0 20 MHz tCLCL Clock Period 250 100 50 ns tCHCX High Time 100 40 20 ns tCLCX Low Time 100 40 20 ns tCLCH Rise Time 2.0 1.6 0.5 μs tCHCL Fall Time 2.0 1.6 0.5 μs ΔtCLCL Change in period from one clock cycle to the next 2 2 2%180 2543L–AVR–08/10 ATtiny2313 Maximum Speed vs. VCC Maximum frequency is dependent on VCC. As shown in Figure 82 and Figure 83, the Maximum Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V and between 2.7V < VCC < 4.5V. Figure 82. Maximum Frequency vs. VCC, ATtiny2313V Figure 83. Maximum Frequency vs. VCC, ATtiny2313 10 MHz 4 MHz 1.8V 2.7V 5.5V Safe Operating Area 20 MHz 10 MHz 2.7V 4.5V 5.5V Safe Operating Area181 2543L–AVR–08/10 ATtiny2313 ATtiny2313 Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. Active Supply Current Figure 84. Active Supply Current vs. Frequency (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY 0.1 - 1.0 MHz 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0 0.2 0.4 0.6 0.8 1 1.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) ICC (mA)182 2543L–AVR–08/10 ATtiny2313 Figure 85. Active Supply Current vs. Frequency (1 - 20 MHz) Figure 86. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) ICC (mA) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 85 ˚C 25 ˚C -40 ˚C 0 1 2 3 4 5 6 7 8 9 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA)183 2543L–AVR–08/10 ATtiny2313 Figure 87. Active Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) Figure 88. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) ACTIVE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 4 MHz 85 °C 25 °C -40 °C 0 1 2 3 4 5 6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (mA) ACTIVE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 1 MHz 85 °C 25 °C -40 °C 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (mA)184 2543L–AVR–08/10 ATtiny2313 Figure 89. Active Supply Current vs. VCC (Internal RC Oscillator, 0.5 MHz) Figure 90. Active Supply Current vs. VCC (Internal RC Oscillator, 128 KHz) ACTIVE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 0.5 MHz 85 °C 25 °C -40 °C 0 0.2 0.4 0.6 0.8 1 1.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (mA) ACTIVE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 128 KHz 85 °C 25 °C -40 °C 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Vcc (V) Icc (mA)185 2543L–AVR–08/10 ATtiny2313 Idle Supply Current Figure 91. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) Figure 92. Idle Supply Current vs. Frequency (1 - 20 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY 0.1 - 1.0 MHz 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0 0.05 0.1 0.15 0.2 0.25 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Icc (m A) IDLE SUPPLY CURRENT vs. FREQUENCY 1 - 20 MHz 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Icc (mA)186 2543L–AVR–08/10 ATtiny2313 Figure 93. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) Figure 94. Idle Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) IDLE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 8 MHz 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (mA) IDLE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 4 MHz 85 °C 25 °C -40 °C 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (mA)187 2543L–AVR–08/10 ATtiny2313 Figure 95. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) Figure 96. Idle Supply Current vs. VCC (Internal RC Oscillator, 0.5 MHz) IDLE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 1 MHz 85 °C 25 °C -40 °C 0 0.1 0.2 0.3 0.4 0.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (mA) IDLE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 0.5 MHz 85 °C 25 °C -40 °C 0 0.05 0.1 0.15 0.2 0.25 0.3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (mA)188 2543L–AVR–08/10 ATtiny2313 Figure 97. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 KHz) Power-down Supply Current Figure 98. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) IDLE SUPPLY CURRENT vs. Vcc INTERNAL RC OSCILLATOR, 128 KHz 85 °C 25 °C -40 °C 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (m A) POWER-DOWN SUPPLY CURRENT vs. Vcc WATCHDOG TIMER DISABLED 85 °C 25 °C -40 °C 0 0.25 0.5 0.75 1 1.25 1.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (uA)189 2543L–AVR–08/10 ATtiny2313 Figure 99. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) Standby Supply Current Figure 100. Standby Supply Current vs. VCC POWER-DOWN SUPPLY CURRENT vs. Vcc WATCHDOG TIMER ENABLED 85 °C 25 °C -40 °C 0 2 4 6 8 10 12 14 16 18 20 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (uA) STANDBY SUPPLY CURRENT vs. Vcc 455KHz Res 2MHz Xtal 2MHz Res 1MHz Res 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (m A)190 2543L–AVR–08/10 ATtiny2313 Pin Pull-up Figure 101. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) Figure 102. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5V 85 °C 25 °C -40 °C 0 20 40 60 80 100 120 140 160 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOP (V) IOP (uA ) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7V 85 °C 25 °C -40 °C 0 10 20 30 40 50 60 70 80 0 0.5 1 1.5 2 2.5 3 VOP (V) IOP (uA)191 2543L–AVR–08/10 ATtiny2313 Figure 103. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) Figure 104. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 5V 85 °C 25 °C -40 °C 0 20 40 60 80 100 120 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VRESET (V) IRESET (uA) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 2.7V 85 °C -40 °C 25 °C 0 10 20 30 40 50 60 0 0.5 1 1.5 2 2.5 3 VRESET (V) IRESET (uA)192 2543L–AVR–08/10 ATtiny2313 Pin Driver Strength Figure 105. I/O Pin Source Current vs. Output Voltage (VCC = 5V) Figure 106. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 85 °C 25 °C -40 °C 0 10 20 30 40 50 60 70 80 90 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 VOH (V) IOH (mA) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 85 °C 25 °C -40 °C 0 5 10 15 20 25 30 35 0.5 1 1.5 2 2.5 3 VOH (V) IOH (mA)193 2543L–AVR–08/10 ATtiny2313 Figure 107. I/O Pin Source Current vs. Output Voltage (VCC = 1.8V) Figure 108. I/O Pin Sink Current vs. Output Voltage (VCC = 5V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 1.8V 85 °C 25 °C -40 °C 0 1 2 3 4 5 6 7 8 9 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOH (V) IOH (mA) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 85 °C 25 °C -40 °C 0 10 20 30 40 50 60 70 80 90 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) IOL (mA)194 2543L–AVR–08/10 ATtiny2313 Figure 109. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V) Figure 110. I/O Pin Sink Current vs. Output Voltage (VCC = 1.8V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 85 °C 25 °C -40 °C 0 5 10 15 20 25 30 35 40 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) IOL (mA) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 1.8V 85 °C 25 °C -40 °C 0 2 4 6 8 10 12 14 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOL (V) IOL (mA)195 2543L–AVR–08/10 ATtiny2313 Figure 111. Reset I/O Pin Source Current vs. Output Voltage (VCC = 5V) Figure 112. Reset I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) RESET I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 85 °C 25 °C -40 °C 0 2 4 6 8 10 12 14 16 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOH (V) Current (mA) RESET I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 0.5 1 1.5 2 2.5 3 VOH (V) Current (m A)196 2543L–AVR–08/10 ATtiny2313 Figure 113. Reset I/O Pin Source Current vs. Output Voltage (VCC = 1.8V) Figure 114. Reset I/O Pin Sink Current vs. Output Voltage (VCC = 5V) RESET I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 1.8V 85 °C 25 °C -40 °C 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOH (V) Current (mA) RESET I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 85 °C 25 °C -40 °C 0 2 4 6 8 10 12 14 16 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOL (V) Current (mA)197 2543L–AVR–08/10 ATtiny2313 Figure 115. Reset I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V) Figure 116. Reset I/O Pin Sink Current vs. Output Voltage (VCC = 1.8V) RESET I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOL (V) Current (mA) RESET I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 1.8V 85 °C 25 °C -40 °C 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VOL (V) Current (mA)198 2543L–AVR–08/10 ATtiny2313 Pin Thresholds and Hysteresis Figure 117. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) Figure 118. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc VIH, IO PIN READ AS '1' 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V) I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc VIL, IO PIN READ AS '0' 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V)199 2543L–AVR–08/10 ATtiny2313 Figure 119. Reset I/O Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) Figure 120. Reset I/O Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) RESET I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc VIH, IO PIN READ AS '1' 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Threshold (V) RESET I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc VIL, IO PIN READ AS '0' 85°C 25°C -40°C 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Threshold (V)200 2543L–AVR–08/10 ATtiny2313 Figure 121. Reset I/O Input Pin Hysteresis vs. VCC Figure 122. Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) RESET I/O INPUT PIN HYSTERESIS vs. Vcc 85 °C 25 °C -40 °C 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Input Hysteresis (V) RESET INPUT THRESHOLD VOLTAGE vs. Vcc VIH, IO PIN READ AS '1' 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V)201 2543L–AVR–08/10 ATtiny2313 Figure 123. Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) Figure 124. Reset Input Pin Hysteresis vs. VCC RESET INPUT THRESHOLD VOLTAGE vs. Vcc VIL, IO PIN READ AS '0' 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Threshold (V) RESET INPUT PIN HYSTERESIS vs. Vcc 85 °C 25 °C -40 °C 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Input Hysteresis (V)202 2543L–AVR–08/10 ATtiny2313 BOD Thresholds and Analog Comparator Offset Figure 125. BOD Thresholds vs. Temperature (BOD Level is 4.3V) Figure 126. BOD Thresholds vs. Temperature (BOD Level is 2.7V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 4.3V 4.25 4.3 4.35 4.4 4.45 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (C) Thres hol d (V ) Rising Vcc Falling Vcc BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 2.7V 2.65 2.7 2.75 2.8 2.85 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (C) Threshold (V) Rising Vcc Falling Vcc203 2543L–AVR–08/10 ATtiny2313 Figure 127. BOD Thresholds vs. Temperature (BOD Level is 1.8V) Internal Oscillator Speed Figure 128. Watchdog Oscillator Frequency vs. VCC BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 1.8V Rising Vcc Falling Vcc 1.78 1.8 1.82 1.84 1.86 1.88 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (C) Threshold (V) WATCHDOG OSCILLATOR FREQUENCY vs. VCC 85 °C 25 °C -40 °C 0.095 0.096 0.097 0.098 0.099 0.1 0.101 0.102 0.103 0.104 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) FRC (M Hz)204 2543L–AVR–08/10 ATtiny2313 Figure 129. Watchdog Oscillator Frequency vs. Temperature Figure 130. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0.096 0.097 0.098 0.099 0.1 0.101 0.102 0.103 0.104 0.105 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) FRC (MHz) CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 7.7 7.8 7.9 8 8.1 8.2 8.3 8.4 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) FRC (MHz )205 2543L–AVR–08/10 ATtiny2313 Figure 131. Calibrated 8 MHz RC Oscillator Frequency vs. VCC Figure 132. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. Vcc 85 °C 25 °C -40 °C 7.7 7.8 7.9 8 8.1 8.2 8.3 8.4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) FRC (MHz) CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 25 °C 0 2 4 6 8 10 12 14 0 16 32 48 64 80 96 112 128 OSCCAL VALUE FRC (MHz)206 2543L–AVR–08/10 ATtiny2313 Figure 133. Calibrated 4 MHz RC Oscillator Frequency vs. Temperature Figure 134. Calibrated 4 MHz RC Oscillator Frequency vs. VCC CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 5.5 V 5.0 V 3.3 V 1.8 V 3.9 3.95 4 4.05 4.1 4.15 4.2 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (°C) FRC (MHz) CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. Vcc 85 °C 25 °C -40 °C 3.9 3.95 4 4.05 4.1 4.15 4.2 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) FRC (MHz)207 2543L–AVR–08/10 ATtiny2313 Figure 135. Calibrated 4 MHz RC Oscillator Frequency vs. Osccal Value Current Consumption of Peripheral Units Figure 136. Brownout Detector Current vs. VCC CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 25 °C 0 1 2 3 4 5 6 7 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 OSCCAL VALUE FRC (MHz ) BROWNOUT DETECTOR CURRENT vs. Vcc 85 °C 25 °C -40 °C 0 5 10 15 20 25 30 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (uA)208 2543L–AVR–08/10 ATtiny2313 Figure 137. Analog Comparator Current vs. VCC Figure 138. Programming Current vs. VCC ANALOG COMPARATOR CURRENT vs. Vcc 85 °C 25 °C -40 °C 0 10 20 30 40 50 60 70 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (uA) PROGRAMMING CURRENT vs. Vcc 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Icc (mA)209 2543L–AVR–08/10 ATtiny2313 Current Consumption in Reset and Reset Pulsewidth Figure 139. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up) Figure 140. Reset Supply Current vs. VCC (1 - 20 MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs. Vcc 0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Icc (mA) RESET SUPPLY CURRENT vs. Vcc 1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 0 0.5 1 1.5 2 2.5 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Icc (mA)210 2543L–AVR–08/10 ATtiny2313 Figure 141. Minimum Reset Pulse Width vs. VCC MINIMUM RESET PULSE WIDTH vs. Vcc 85 °C 25 °C -40 °C 0 500 1000 1500 2000 2500 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Pulsewidth (ns)211 2543L–AVR–08/10 ATtiny2313 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x3F (0x5F) SREG I T H S V N Z C 8 0x3E (0x5E) Reserved – – – – – – – – 0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 11 0x3C (0x5C) OCR0B Timer/Counter0 – Compare Register B 77 0x3B (0x5B) GIMSK INT1 INT0 PCIE – – – – – 60 0x3A (0x5A) EIFR INTF1 INTF0 PCIF – – – – – 61 0x39 (0x59) TIMSK TOIE1 OCIE1A OCIE1B – ICIE1 OCIE0B TOIE0 OCIE0A 78, 109 0x38 (0x58) TIFR TOV1 OCF1A OCF1B – ICF1 OCF0B TOV0 OCF0A 78 0x37 (0x57) SPMCSR – – – CTPB RFLB PGWRT PGERS SELFPRGEN 155 0x36 (0x56) OCR0A Timer/Counter0 – Compare Register A 77 0x35 (0x55) MCUCR PUD SM1 SE SM0 ISC11 ISC10 ISC01 ISC00 53 0x34 (0x54) MCUSR – – – – WDRF BORF EXTRF PORF 37 0x33 (0x53) TCCR0B FOC0A FOC0B – – WGM02 CS02 CS01 CS00 76 0x32 (0x52) TCNT0 Timer/Counter0 (8-bit) 77 0x31 (0x51) OSCCAL – CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 26 0x30 (0x50) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 73 0x2F (0x4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1BO – – WGM11 WGM10 104 0x2E (0x4E) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 107 0x2D (0x4D) TCNT1H Timer/Counter1 – Counter Register High Byte 108 0x2C (0x4C) TCNT1L Timer/Counter1 – Counter Register Low Byte 108 0x2B (0x4B) OCR1AH Timer/Counter1 – Compare Register A High Byte 108 0x2A (0x4A) OCR1AL Timer/Counter1 – Compare Register A Low Byte 108 0x29 (0x49) OCR1BH Timer/Counter1 – Compare Register B High Byte 109 0x28 (0x48) OCR1BL Timer/Counter1 – Compare Register B Low Byte 109 0x27 (0x47) Reserved – – – – – – – – 0x26 (0x46) CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 28 0x25 (0x45) ICR1H Timer/Counter1 - Input Capture Register High Byte 109 0x24 (0x44) ICR1L Timer/Counter1 - Input Capture Register Low Byte 109 0x23 (0x43) GTCCR – – – – – – – PSR10 81 0x22 (ox42) TCCR1C FOC1A FOC1B – – – – – – 108 0x21 (0x41) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 42 0x20 (0x40) PCMSK PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 61 0x1F (0x3F) Reserved – – – – – – – – 0x1E (0x3E) EEAR – EEPROM Address Register 16 0x1D (0x3D) EEDR EEPROM Data Register 17 0x1C (0x3C) EECR – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE 17 0x1B (0x3B) PORTA – – – – – PORTA2 PORTA1 PORTA0 58 0x1A (0x3A) DDRA – – – – – DDA2 DDA1 DDA0 58 0x19 (0x39) PINA – – – – – PINA2 PINA1 PINA0 58 0x18 (0x38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 58 0x17 (0x37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 58 0x16 (0x36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 58 0x15 (0x35) GPIOR2 General Purpose I/O Register 2 21 0x14 (0x34) GPIOR1 General Purpose I/O Register 1 21 0x13 (0x33) GPIOR0 General Purpose I/O Register 0 21 0x12 (0x32) PORTD – PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 58 0x11 (0x31) DDRD – DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 58 0x10 (0x30) PIND – PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 58 0x0F (0x2F) USIDR USI Data Register 144 0x0E (0x2E) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 145 0x0D (0x2D) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC 145 0x0C (0x2C) UDR UART Data Register (8-bit) 129 0x0B (0x2B) UCSRA RXC TXC UDRE FE DOR UPE U2X MPCM 129 0x0A (0x2A) UCSRB RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 131 0x09 (0x29) UBRRL UBRRH[7:0] 133 0x08 (0x28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 149 0x07 (0x27) Reserved – – – – – – – – 0x06 (0x26) Reserved – – – – – – – – 0x05 (0x25) Reserved – – – – – – – – 0x04 (0x24) Reserved – – – – – – – – 0x03 (0x23) UCSRC – UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL 132 0x02 (0x22) UBRRH – – – – UBRRH[11:8] 133 0x01 (0x21) DIDR – – – – – – AIN1D AIN0D 150 0x00 (0x20) Reserved – – – – – – – –212 2543L–AVR–08/10 ATtiny2313 Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. 213 2543L–AVR–08/10 ATtiny2313 Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1 COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1 NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1 INC Rd Increment Rd ← Rd + 1 Z,N,V 1 DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1 SER Rd Set Register Rd ← 0xFF None 1 BRANCH INSTRUCTIONS RJMP k Relative Jump PC ← PC + k + 1 None 2 IJMP Indirect Jump to (Z) PC ← Z None 2 RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3 ICALL Indirect Call to (Z) PC ← Z None 3 RET Subroutine Return PC ← STACK None 4 RETI Interrupt Return PC ← STACK I 4 CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3 CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1214 2543L–AVR–08/10 ATtiny2313 ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1 BSET s Flag Set SREG(s) ← 1 SREG(s) 1 BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) ← T None 1 SEC Set Carry C ← 1 C1 CLC Clear Carry C ← 0 C 1 SEN Set Negative Flag N ← 1 N1 CLN Clear Negative Flag N ← 0 N 1 SEZ Set Zero Flag Z ← 1 Z1 CLZ Clear Zero Flag Z ← 0 Z 1 SEI Global Interrupt Enable I ← 1 I1 CLI Global Interrupt Disable I ← 0 I 1 SES Set Signed Test Flag S ← 1 S1 CLS Clear Signed Test Flag S ← 0 S 1 SEV Set Twos Complement Overflow. V ← 1 V1 CLV Clear Twos Complement Overflow V ← 0 V 1 SET Set T in SREG T ← 1 T1 CLT Clear T in SREG T ← 0 T 1 SEH Set Half Carry Flag in SREG H ← 1 H1 CLH Clear Half Carry Flag in SREG H ← 0 H 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers Rd ← Rr None 1 MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1 LDI Rd, K Load Immediate Rd ← K None 1 LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2 LD Rd, Y Load Indirect Rd ← (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd ← (k) None 2 ST X, Rr Store Indirect (X) ← Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2 ST Y, Rr Store Indirect (Y) ← Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2 ST Z, Rr Store Indirect (Z) ← Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2 STS k, Rr Store Direct to SRAM (k) ← Rr None 2 LPM Load Program Memory R0 ← (Z) None 3 LPM Rd, Z Load Program Memory Rd ← (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3 SPM Store Program Memory (Z) ← R1:R0 None - IN Rd, P In Port Rd ← P None 1 OUT P, Rr Out Port P ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/timer) None 1 BREAK Break For On-chip Debug Only None N/A Mnemonics Operands Description Operation Flags #Clocks215 2543L–AVR–08/10 ATtiny2313 Ordering Information Notes: 1. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC, see Figure 82 on page 180 and Figure 83 on page 180. 4. Code Indicators: – U: matte tin – R: tape & reel Speed (MHz)(3) Power Supply (V) Ordering Code(4) Package(2) Operation Range 10 1.8 - 5.5 ATtiny2313V-10PU ATtiny2313V-10SU ATtiny2313V-10SUR ATtiny2313V-10MU ATtiny2313V-10MUR 20P3 20S 20S 20M1 20M1 Industrial (-40°C to +85°C)(1) 20 2.7 - 5.5 ATtiny2313-20PU ATtiny2313-20SU ATtiny2313-20SUR ATtiny2313-20MU ATtiny2313-20MUR 20P3 20S 20S 20M1 20M1 Industrial (-40°C to +85°C)(1) Package Type 20P3 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20S 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC) 20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (MLF)216 2543L–AVR–08/10 ATtiny2313 Packaging Information 20P3 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) 20P3 C 1/12/04 PIN 1 E1 A1 B E B1 C L SEATING PLANE A D e eB eC COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 5.334 A1 0.381 – – D 25.493 – 25.984 Note 2 E 7.620 – 8.255 E1 6.096 – 7.112 Note 2 B 0.356 – 0.559 B1 1.270 – 1.551 L 2.921 – 3.810 C 0.203 – 0.356 eB – – 10.922 eC 0.000 – 1.524 e 2.540 TYP Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 217 2543L–AVR–08/10 ATtiny2313 20S218 2543L–AVR–08/10 ATtiny2313 20M1 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, 20M1 A 10/27/04 2.6 mm Exposed Pad, Micro Lead Frame Package (MLF) A 0.70 0.75 0.80 A1 – 0.01 0.05 A2 0.20 REF b 0.18 0.23 0.30 D 4.00 BSC D2 2.45 2.60 2.75 E 4.00 BSC E2 2.45 2.60 2.75 e 0.50 BSC L 0.35 0.40 0.55 SIDE VIEW Pin 1 ID Pin #1 Notch (0.20 R) BOTTOM VIEW TOP VIEW Note: Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D E e A2 A1 A D2 E2 0.08 C L 1 2 3 b 1 2 3219 2543L–AVR–08/10 ATtiny2313 Errata The revision in this section refers to the revision of the ATtiny2313 device. ATtiny2313 Rev C No known errata ATtiny2313 Rev B • Wrong values read after Erase Only operation • Parallel Programming does not work • Watchdog Timer Interrupt disabled • EEPROM can not be written below 1.9 volts 1. Wrong values read after Erase Only operation At supply voltages below 2.7 V, an EEPROM location that is erased by the Erase Only operation may read as programmed (0x00). Problem Fix/Workaround If it is necessary to read an EEPROM location after Erase Only, use an Atomic Write operation with 0xFF as data in order to erase a location. In any case, the Write Only operation can be used as intended. Thus no special considerations are needed as long as the erased location is not read before it is programmed. 2. Parallel Programming does not work Parallel Programming is not functioning correctly. Because of this, reprogramming of the device is impossible if one of the following modes are selected: – In-System Programming disabled (SPIEN unprogrammed) – Reset Disabled (RSTDISBL programmed) Problem Fix/Workaround Serial Programming is still working correctly. By avoiding the two modes above, the device can be reprogrammed serially. 3. Watchdog Timer Interrupt disabled If the watchdog timer interrupt flag is not cleared before a new timeout occurs, the watchdog will be disabled, and the interrupt flag will automatically be cleared. This is only applicable in interrupt only mode. If the Watchdog is configured to reset the device in the watchdog timeout following an interrupt, the device works correctly. Problem fix / Workaround Make sure there is enough time to always service the first timeout event before a new watchdog timeout occurs. This is done by selecting a long enough time-out period. 4. EEPROM can not be written below 1.9 volts Writing the EEPROM at VCC below 1.9 volts might fail. Problem fix / Workaround Do not write the EEPROM when VCC is below 1.9 volts. ATtiny2313 Rev A Revision A has not been sampled.220 2543L–AVR–08/10 ATtiny2313 Datasheet Revision History Please note that the referring page numbers in this section refer to the complete document. Rev. 2543L - 8/10 Added tape and reel part numbers in “Ordering Information” on page 215. Removed text “Not recommended for new design” from cover page. Fixed literature number mismatch in Datasheet Revision History. Rev. 2543K - 03/10 Rev. 2543J - 11/09 Changes from Rev. 2543H-02/05 to Rev. 2543I-04/06 Changes from Rev. 2543G-10/04 to Rev. 2543H-02/05 1. Added device Rev C “No known errata” in “Errata” on page 219. 1. Updated template 2. Changed device status to “Not recommended for new designs.” 3. Updated “Stack Pointer” on page 11. 4. Updated Table “Sleep Mode Select” on page 30. 5. Updated “Calibration Byte” on page 160 (to one byte of calibration data) 1. Updated typos. 2. Updated Figure 1 on page 2. 3 Added “Resources” on page 6. 4. Updated “Default Clock Source” on page 23. 5. Updated “128 kHz Internal Oscillator” on page 28. 6. Updated “Power Management and Sleep Modes” on page 30 7. Updated Table 3 on page 23,Table 13 on page 30, Table 14 on page 31, Table 19 on page 42, Table 31 on page 60, Table 79 on page 176. 8. Updated “External Interrupts” on page 59. 9. Updated “Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0” on page 61. 10. Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page 149. 11. Updated “Calibration Byte” on page 160. 12. Updated “DC Characteristics” on page 177. 13. Updated “Register Summary” on page 211. 14. Updated “Ordering Information” on page 215. 15. Changed occurences of OCnA to OCFnA, OCnB to OCFnB and OC1x to OCF1x. 1. Updated Table 6 on page 25, Table 15 on page 34, Table 68 on page 160 and Table 80 on page 179. 2. Changed CKSEL default value in “Default Clock Source” on page 23 to 8 MHz.221 2543L–AVR–08/10 ATtiny2313 Changes from Rev. 2543F-08/04 to Rev. 2543G-10/04 Changes from Rev. 2543E-04/04 to Rev. 2543F-08/04 Changes from Rev. 2543D-03/04 to Rev. 2543E-04/04 Changes from Rev. 2543C-12/03 to Rev. 2543D-03/04 3. Updated “Programming the Flash” on page 165, “Programming the EEPROM” on page 167 and “Enter Programming Mode” on page 163. 4. Updated “DC Characteristics” on page 177. 5. MLF option updated to “Quad Flat No-Lead/Micro Lead Frame (QFN/MLF)” 1. Updated “Features” on page 1. 2. Updated “Pinout ATtiny2313” on page 2. 3. Updated “Ordering Information” on page 215. 4. Updated “Packaging Information” on page 216. 5. Updated “Errata” on page 219. 1. Updated “Features” on page 1. 2. Updated “Alternate Functions of Port B” on page 53. 3. Updated “Calibration Byte” on page 160. 4. Moved Table 69 on page 160 and Table 70 on page 160 to “Page Size” on page 160. 5. Updated “Enter Programming Mode” on page 163. 6. Updated “Serial Programming Algorithm” on page 173. 7. Updated Table 78 on page 174. 8. Updated “DC Characteristics” on page 177. 9. Updated “ATtiny2313 Typical Characteristics” on page 181. 10. Changed occurences of PCINT15 to PCINT7, EEMWE to EEMPE and EEWE to EEPE in the document. 1. Speed Grades changed - 12MHz to 10MHz - 24MHz to 20MHz 2. Updated Figure 1 on page 2. 3. Updated “Ordering Information” on page 215. 4. Updated “Maximum Speed vs. VCC” on page 180. 5. Updated “ATtiny2313 Typical Characteristics” on page 181. 1. Updated Table 2 on page 23. 2. Replaced “Watchdog Timer” on page 39. 3. Added “Maximum Speed vs. VCC” on page 180. 4. “Serial Programming Algorithm” on page 173 updated. 5. Changed mA to µA in preliminary Figure 136 on page 207. 6. “Ordering Information” on page 215 updated. MLF package option removed222 2543L–AVR–08/10 ATtiny2313 Changes from Rev. 2543B-09/03 to Rev. 2543C-12/03 Changes from Rev. 2543A-09/03 to Rev. 2543B-09/03 7. Package drawing “20P3” on page 216 updated. 8. Updated C-code examples. 9. Renamed instances of SPMEN to SELFPRGEN, Self Programming Enable. 1. Updated “Calibrated Internal RC Oscillator” on page 25. 1. Fixed typo from UART to USART and updated Speed Grades and Power Consumption Estimates in “Features” on page 1. 2. Updated “Pin Configurations” on page 2. 3. Updated Table 15 on page 34 and Table 80 on page 179. 4. Updated item 5 in “Serial Programming Algorithm” on page 173. 5. Updated “Electrical Characteristics” on page 177. 6. Updated Figure 82 on page 180 and added Figure 83 on page 180. 7. Changed SFIOR to GTCCR in “Register Summary” on page 211. 8. Updated “Ordering Information” on page 215. 9. Added new errata in “Errata” on page 219.i 2543L–AVR–08/10 ATtiny2313 Table of Contents Features 1 Pin Configurations 2 General Information 6 Resources 6 Code Examples 6 Disclaimer 6 AVR CPU Core 7 Introduction 7 Architectural Overview 7 ALU – Arithmetic Logic Unit 8 Status Register 8 General Purpose Register File 9 Instruction Execution Timing 11 Reset and Interrupt Handling 12 AVR ATtiny2313 Memories 14 In-System Reprogrammable Flash Program Memory 14 EEPROM Data Memory 16 I/O Memory 20 System Clock and Clock Options 22 Clock Systems and their Distribution 22 Clock Sources 23 Default Clock Source 23 Crystal Oscillator 23 Calibrated Internal RC Oscillator 25 System Clock Prescalar 28 Power Management and Sleep Modes 30 Idle Mode 30 Power-down Mode 31 Standby Mode 31 Minimizing Power Consumption 31 System Control and Reset 33 Interrupts 44 Interrupt Vectors in ATtiny2313 44 I/O-Ports 46 Introduction 46ii 2543L–AVR–08/10 ATtiny2313 Ports as General Digital I/O 47 Alternate Port Functions 51 External Interrupts 59 Pin Change Interrupt Timing 59 8-bit Timer/Counter0 with PWM 62 Overview 62 Timer/Counter Clock Sources 63 Counter Unit 63 Output Compare Unit 64 Compare Match Output Unit 65 Modes of Operation 66 Timer/Counter Timing Diagrams 71 Timer/Counter0 and Timer/Counter1 Prescalers 80 16-bit Timer/Counter1 82 Overview 82 Accessing 16-bit Registers 84 Counter Unit 88 Input Capture Unit 89 Output Compare Units 90 Modes of Operation 94 USART 111 Overview 111 Clock Generation 112 Frame Formats 115 USART Initialization 116 Asynchronous Data Reception 124 Universal Serial Interface – USI 138 Overview 138 Functional Descriptions 139 Alternative USI Usage 144 USI Register Descriptions 144 Analog Comparator 149 debugWIRE On-chip Debug System 151 Features 151 Overview 151 Physical Interface 151 Software Break Points 152 Limitations of debugWIRE 152iii 2543L–AVR–08/10 ATtiny2313 debugWIRE Related Register in I/O Memory 152 Self-Programming the Flash 153 Memory Programming 158 Program And Data Memory Lock Bits 158 Signature Bytes 160 Calibration Byte 160 Page Size 160 Parallel Programming Parameters, Pin Mapping, and Commands 161 Serial Programming Pin Mapping 163 Parallel Programming 163 Serial Downloading 172 External Clock Drive 179 ATtiny2313 Typical Characteristics 181 Errata 219 ATtiny2313 Rev C 219 ATtiny2313 Rev B 219 ATtiny2313 Rev A 219 Datasheet Revision History 220 Rev. 2543L - 8/10 220 Rev. 2543K - 03/10 220 Rev. 2543J - 11/09 220 Changes from Rev. 2543H-02/05 to Rev. 2543I-04/06 220 Changes from Rev. 2543G-10/04 to Rev. 2543H-02/05 220 Changes from Rev. 2543F-08/04 to Rev. 2543G-10/04 221 Changes from Rev. 2543E-04/04 to Rev. 2543F-08/04 221 Changes from Rev. 2543D-03/04 to Rev. 2543E-04/04 221 Changes from Rev. 2543C-12/03 to Rev. 2543D-03/04 221 Changes from Rev. 2543B-09/03 to Rev. 2543C-12/03 222 Changes from Rev. 2543A-09/03 to Rev. 2543B-09/03 2222543L–AVR–08/10 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support avr@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2010 Atmel Corporation. All rights reserved. Atmel®, Atmel logo and combinations thereof, AVR® and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. AVR172: Sensorless Commutation of Brushless DC Motor (BLDC) using ATmega32M1 and ATAVRMC320 Features • Robust sensorless commutation control • Ramp-up sequence References [1] ATmega32M1 Data sheet [2] AVR194: Brushless DC Motor Control using ATmega32M1 [3] AVR430: MC300 Hardware User Guide [4] AVR470: MC310 User Guide [5] AVR471: MC320 Getting Started Guide [6] AVR928: Sensorless methods to drive BLDC motors 1 Introduction This application note describes how to implement a sensorless commutation of BLDC motors with the ATAVRMC320 development kit. The ATmega32M1 is equipped with integrated peripherals that reduce the number of external components required in a BLDC application. The ATmega32M1 is suitable for sensorless commutation and for commutation with Hall sensors as well, but this application note focuses on the sensorless commutation. The AVR928 Application Note describes the theory of the sensorless control method and must be carefully read first. 8-bit Microcontrollers Application Note Rev. 8306B-AVR-05/10 2 AVR172 8306B-AVR-05/10 2 Hardware The hardware includes the ATAVRMC310 and ATAVRMC300 boards which are the two parts of the ATAVRMC320 Starter kit. Please refer to the ATAVRMC300 and ATAVRMC310 user guides : - AVR430: MC300 Hardware User Guide - AVR470: MC310 Hardware User Guide 2.1 MC310 jumpers setting The AVR172 firmware has been developed with the following jumper settings: Table 2-1.ATAVRMC310 jumpers setting for sensorless control Designator Setting Function J5 Vm connect PB4 to Vm’ (motor voltage measurement if necessary) J6 PFC OC Connect to overcurrent signal J7 none used by CAN applications J8 ShCo connect PC5 to ShCo for current measurement J9 GNDm connect PC4 to GNDm for current measurement J12 TxD connect PD3 to the RS232 driver MOSI A Connect PD3 to ISP connector (for ISP use) RxDUSB Connect PD3 to RxD1 (for USB interface use) J13 RxD connect PD4 to the RS232 driver SCK Connect PD3 to ISP connector (for ISP use) TxDUSB Connect PD3 to RxD1 (for USB interface use) J15 none used by CAN application to add a termination resistor J21 Cmp- connect ACMP0- to V+W bemf conditioning J22 Cmp+ connect ACMP0+ to U bemf conditioning J23 Cmp- connect ACMP1- to U+W bemf conditioning J24 Cmp+ connect ACMP1+ to V bemf conditioning J25 Cmp- connect ACMP2- to U+V bemf conditioning J26 Cmp+ connect ACMP2+ to W bemf conditioning J28 VCC supply the on board USB dongle from the board power supply See also following picture of MC310 Jumpers configurations : AVR172 3 8306B-AVR-05/10 Figure 1. MC310 Jumpers configuration 2.2 MC300 jumper settings Table 2-1. ATAVRMC300 jumpers setting for sensorless control Designator Setting Function J2 none provide +5V to supply the ATAVRMC310 board On ATAVRMC300, Vm and Vin connectors can be supplied from the same +12V/7A power supply. Nevertheless a separate +12V/1A can also be used to supply the Vin (processor supply voltage). 2.3 Power-supply This firmware example has been configured according to a power-supply Vm=12V. This power-supply must be able to provide up to 4A output current. 2.4 Motor The BLDC motor provided inside MC320 and MC300 Motor Control Kit has the following characteristics: Manufacturer : TECMOTION Number of phases : 3 Number of poles : 8 (4 pairs) Rated voltage : 24V Rated speed : 4000 rpm Rated torque : 62.5 Nm Torque constant : 35 Nm/A = k_tau4 AVR172 8306B-AVR-05/10 Line to Line Resistance : 1.8 ohm = R Back EMF : 3.66 V/Krpm = k_e Peak current : 5.4A As Vm=12V, the rated speed will be 2000 rpm. 2.5 ATmega32M1 Configuration ATmega32M1 must be programmed to run at 16MHz using PLL (set corresponding Fuse bits). The CKDIV8 fuse must be disabled. Extended/High/Low Fuses configurations are : FF/DF/F3 2.6 Technical Advices 2.6.1 Disconnecting the BLDC Motor The BLDC motor must not be disconnected while it is running or while its coils carry current. It is allowed to disconnect a BLDC motor if the PWM duty cycle is 0% and the rotor is at rest so that no current is driven through the coils. Be careful, when stopping the power supply or PWM, a BLDC motor with a high moment of inertia is able to run for a relatively long time. 2.6.2 Ground and Power Wirings One design its own board has to take care of the ground wiring and power wiring. The power supply of the processor and additional signal conditioning components (e.g. additional fast comparators, operational amplifiers, …) has to be decoupled from the motor power supply. The ground connection has to be of low resistance and low inductance to prevent against voltage drop and noise due to high currents. A ground plane within a multi layer PCB is recommended for proper operation. 3 Firmware The example firmware is based on the Sensorless method described in AVR928 Application Note. It is operating in sensorless mode using the ATmega32M1 internal comparators. Hall sensor wires of the BLDC motor of the kit can remain unconnected. The source file directory embeds an html documentation which can be opened through the readme.html file. The theory of the different tasks has been detailed in AVR928. The application to ATmega32M1 is detailed in following sections. 3.1 Main Flow chart The firmware main flowchart is described below : AVR172 5 8306B-AVR-05/10 Figure 2. Main flow chart The tasks are scheduled thanks to the g_tick produced each 1.024ms with Timer0. 6 AVR172 8306B-AVR-05/10 3.2 MS_ALIGN phase The ALIGN phase forces the motor at a specific position. The time of this phase is controlled with ALIGN_TIME constant which is the ru_period_counter initial value (200 for MC310 motor). 3.3 RAMP_UP phase The ramp-up charateristics (duty-cycles and times) are stored in two tables: • ramp_up_duty_table[] : which provides the duty_cycle of the step • ramp_up_time_table[] : which provides the length of the step (ru_step_length) These two tables are specific to the motor and the application. The scanning of the step sequences and the monitoring of the step length are achieved thanks to three independant counters : - ru_step_length_cntr : which counts the commutation time (up to ru_step_length variable) - ru_period_counter : which counts the step length (up to RAMP_UP_PERIOD constant) - ramp_up_index : which counts the step numbers (up to RAMP_UP_INDEX_MAX constant) The figure below provides a waveform of steps timing : Figure 3. Steps timing AVR172 7 8306B-AVR-05/10 3.3.1 Time of steps The step time is RAMP_UP_PERIOD = 50ms. 3.3.2 Number of steps The parameter : RAMP_UP_INDEX_MAX = 9, defines 10 steps ramp up. 3.3.3 Parameters tables In firmware example, the tables have been defined according to the characteristics of the motor provided in the kit (see parameters in 2.4 Motor section) : ramp_up_time_table[] = {26,23,20,17,14,11,8,5,3,2,2}; ramp_up_duty_table[] = {122,124,126,129,131,133,135,137,140,143,145}; 3.3.4 Sp1/pwm1 The usual parameters described in AVR928 Application Note are: • Pwm1 = 50% • Sp1 = Sp_max/60 The parameters defined with MC310 Tecmotion motor are: • Pwm1 = 48% (= 122/256) • Sp1 : Sp1 is defined thanks to the initialization value of ru_step_length : ru_step_length = RAMP_UP_STEP_MAX = 40 This variable determines one commutation each 40ms. So an electrical rotation time is 120ms. As the motor has 4 pairs of poles, the mechanical rotation time is 480ms. So the rotation speed is 60/0.48 = 125 rpm. So Sp1 = Sp_max/32. The second value of ru_step_length is 26 in the time table. It defines the following commutation time. 3.3.5 Sp2/pwm2 The theorical parameters described in AVR928 Application Note are: • Pwm2 = 60% • Sp2 = Sp_max/6 = Sp1 / 10 The parameters defined with Tecmotion motor are: • Pwm2 = 57% (= 145/256) • Sp2 : Sp2 is defined thanks to the last value of ru_step_length : 2 This variable determines one commutation each 4ms. So an electrical rotation time is 12ms. As the motor has 4 pairs of poles, the mechanical rotation time is 48ms. So the rotation speed is 60/0.048 = 1250 rpm. So Sp2 = Sp_max/3.2. 8 AVR172 8306B-AVR-05/10 This confirms also the usual ratio = 10 between Sp1 and Sp2 which is defined in AVR498 Application Note. 3.4 LAST_RAMP_UP phase To avoid a shorten last step, this phase monitors the last ramp-up step to guarantee it is ended properly before running in closed loop. 3.5 RUNNING Phase 3.5.1 Closed-loop block diagram The Running phase is a sensorless closed loop which block diagram is following : Figure 4. Closed-loop block diagram AVR172 9 8306B-AVR-05/10 3.5.2 Running flowchart The flowchart is following : Figure 5. Closed-loop flowchart • Motor_state is kept equal to MS_RUNNING mci_set_ref_speed() function updates the speed setpoint according to the potentiometer adjustment or the speed command received on serial transmission. In mc_regulation_loop() function, duty_cycle_reference is the duty_cycle variable which controls the PWM generator. This variable is the result of following functions : • In OPEN_LOOP: mci_set_ref_speed() function • In SPEED_LOOP: 10 AVR172 8306B-AVR-05/10 mc_control_speed(2*mci_get_ref_speed()) duty-cycle_reference is calculated from ref_speed and from monitored mci_get_measured_speed() measured_speed = (KSPEED * 4) / mci_measured_period with mci_measured_period calculated in the Interrupt vector of Analog Comparator 1. This interrupt uses Timer 0 to compute the period. • In CURRENT_LOOP : mc_control_current(mc_get_potentiometer_value() 3.5.3 Sensorless Detection and Commutation Management The analog comparators 0, 1 and 2 are used to detect the zero crossing of the U, V and W phases. The timer 1 is used to monitor the time between two consecutive zero crossings. This time corresponds to one sector of the electrical rotation of the motor. It equals 60° of the entire electrical period of the motor. When a zero crossing event occurs, the timer 1 value is stored. Then this value is divided by 2 (providing the 30° time) and loaded into the Compare A register of timer 1. Then this value is added to the half of itself to provide the 45° time and loaded into the Compare B register of timer 1. The timer 1 compare A event occurs 30° after the zero crossing. It activates the next commutation state and masks the zero crossing to avoid the discharge of the inductance (demagnetization) pulse generated at the end of a step when the active switches are released. Due to the inductance of the motor coils, a voltage equals to -Ldi/dt is generated, the demagnetization is done through the diodes of the power bridge. The timer 1 compare B event releases the zero crossing mask : enables the comparator n interrupt according to the motor_step variable. This Timer1 interrupt provides the demagnetization mask delay. AVR172 11 8306B-AVR-05/10 4 RS232 Communication with firmware 4.1 Connecting ATAVRMC310 to use the RS232 interface Connect PC com port to the ATAVRMC310 RS232 connector through a direct cable. The serial configuration is: • 38400 bauds, • 8 bit data bit, • 1 stop bit, • no handshake, 4.2 PC applications User can communicate with firmware through RS232 with usual PC serial communication applications (i.e. Hyperterminal) or the Atmel “Motor Control Center” application which can be downloaded from Atmel web at url : http://www.atmel.com 4.2.1 PC Terminal : RS232 Messages and Commands At power up the following welcome message is received on terminal : “ATMEL Motor Control Interface”. The following commands can be sent to the firmware: Table 2-1. List of commands Command Action ru Run motor st Stop Motor help Gives help fw Set direction to Forward bw Set direction to Backward ss Set Speed (followed with speed value) gi Get ID g0 Get Status 0 g1 Get Status 1 4.2.2 Motor Control Center The User Guide is available in Install directory at URL : C:\Program Files\Atmel\Motor Control Center\help\Overview.htm The AVR172 Target must be selected first to get the right configuration : To select a target, execute the File > Select Target command or click the button in the toolbar. The following dialog pops up: 12 AVR172 8306B-AVR-05/10 Figure 6. Motor Control Center Interface 5 USB communication Communication can be achieved from PC to USB connector of MC310 board. The AVR470, MC310 Hardware User Guide details the configuration to be achieved. Communication port becomes a Virtual Com port. Same tools as described in section 4 (RS232 Communication with firmware), can be used through this Virtual Com port. 8306B-AVR-05/10 Disclaimer Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Product Contact Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Web Site http://www.atmel.com/ Technical Support avr@atmel.com Sales Contact www.atmel.com/contacts Literature Request www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2010 Atmel Corporation. All rights reserved. Atmel® , Atmel logo and combinations thereof, AVR® , AVR® logo and others, are the registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 1. Product profile 1.1 General description NPN/NPN general-purpose transistor pair in a small SOT457 (SC-74) Surface-Mounted Device (SMD) plastic package. 1.2 Features ■ Low collector capacitance ■ Low collector-emitter saturation voltage ■ Closely matched current gain ■ Reduces number of components and board space ■ No mutual interference between the transistors ■ AEC-Q101 qualified 1.3 Applications ■ General-purpose switching and amplification 1.4 Quick reference data BC846DS 65 V, 100 mA NPN/NPN general-purpose transistor Rev. 01 — 17 July 2009 Product data sheet Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit Per transistor VCEO collector-emitter voltage open base - - 65 V IC collector current - - 100 mA hFE DC current gain VCE = 5 V; IC = 2 mA 200 300 450BC846DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 17 July 2009 2 of 12 NXP Semiconductors BC846DS 65 V, 100 mA NPN/NPN general-purpose transistor 2. Pinning information 3. Ordering information 4. Marking 5. Limiting values Table 2. Pinning Pin Description Simplified outline Graphic symbol 1 emitter TR1 2 base TR1 3 collector TR2 4 emitter TR2 5 base TR2 6 collector TR1 1 3 2 6 5 4 sym020 1 2 3 6 5 TR1 TR2 4 Table 3. Ordering information Type number Package Name Description Version BC846DS SC-74 plastic surface-mounted package (TSOP6); 6 leads SOT457 Table 4. Marking codes Type number Marking code BC846DS ZK Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Per transistor VCBO collector-base voltage open emitter - 80 V VCEO collector-emitter voltage open base - 65 V VEBO emitter-base voltage open collector - 6 V IC collector current - 100 mA ICM peak collector current single pulse; tp ≤ 1 ms - 200 mA IBM peak base current single pulse; tp ≤ 1 ms - 200 mA Ptot total power dissipation Tamb ≤ 25 °C [1] - 250 mW Per device Ptot total power dissipation Tamb ≤ 25 °C [1] - 380 mWBC846DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 17 July 2009 3 of 12 NXP Semiconductors BC846DS 65 V, 100 mA NPN/NPN general-purpose transistor [1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint. 6. Thermal characteristics [1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. Tj junction temperature - 150 °C Tamb ambient temperature −55 +150 °C Tstg storage temperature −65 +150 °C FR4 PCB, standard footprint Fig 1. Per device: Power derating curve SOT457 (SC-74) Table 5. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Tamb (°C) −75 175 −25 25 75 125 006aab621 200 300 100 400 500 Ptot (mW) 0 Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Per transistor Rth(j-a) thermal resistance from junction to ambient in free air [1] - - 500 K/W Rth(j-sp) thermal resistance from junction to solder point - - 250 K/W Per device Rth(j-a) thermal resistance from junction to ambient in free air [1] - - 328 K/WBC846DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 17 July 2009 4 of 12 NXP Semiconductors BC846DS 65 V, 100 mA NPN/NPN general-purpose transistor 7. Characteristics FR4 PCB, standard footprint Fig 2. Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration; typical values 006aab622 10−5 10 10 −2 10−4 102 10−1 tp (s) 10−3 103 1 102 10 103 Zth(j-a) (K/W) 1 δ = 1 0.75 0.50 0.33 0.10 0.05 0.02 0.01 0 0.20 Table 7. Characteristics Tamb = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Per transistor ICBO collector-base cut-off current VCB = 50 V; IE = 0 A - - 15 nA VCB = 30 V; IE = 0 A; Tj = 150 °C --5 µA IEBO emitter-base cut-off current VEB = 6 V; IC = 0 A - - 100 nA hFE DC current gain VCE =5V IC = 10 µA - 280 - IC = 2 mA 200 300 450 VCEsat collector-emitter saturation voltage IC = 10 mA; IB = 0.5 mA - 55 100 mV IC = 100 mA; IB = 5 mA - 200 300 mV VBEsat base-emitter saturation voltage IC = 10 mA; IB = 0.5 mA - 755 850 mV IC = 100 mA; IB = 5 mA - 1000 - mV VBE base-emitter voltage VCE =5V IC = 2 mA 580 650 700 mV IC = 10 mA - - 770 mVBC846DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 17 July 2009 5 of 12 NXP Semiconductors BC846DS 65 V, 100 mA NPN/NPN general-purpose transistor Cc collector capacitance VCB = 10 V; IE = ie = 0 A; f = 1 MHz - 1.9 - pF Ce emitter capacitance VEB = 0.5 V; IC = ic = 0 A; f = 1 MHz - 11 - pF fT transition frequency VCE = 5 V; IC = 10 mA; f = 100 MHz 100 - - MHz NF noise figure VCE = 5 V; IC = 0.2 mA; RS =2kΩ; f = 10 Hz to 15.7 kHz - 1.9 - dB VCE = 5 V; IC = 0.2 mA; RS =2kΩ; f = 1 kHz; B = 200 Hz - 3.1 - dB Table 7. Characteristics …continued Tamb = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VCE =5V (1) Tamb = 100 °C (2) Tamb = 25 °C (3) Tamb = −55 °C Tamb = 25 °C Fig 3. Per transistor: DC current gain as a function of collector current; typical values Fig 4. Per transistor: Collector current as a function of collector-emitter voltage; typical values 006aaa533 200 400 600 hFE 0 IC (mA) 10−2 103 102 10−1 1 10 (3) (1) (2) 006aaa532 VCE (V) 0 10 2 4 6 8 0.08 0.12 0.04 0.16 0.20 IC (A) 0 IB (mA) = 4.50 2.70 3.15 4.05 3.60 0.45 0.90 1.35 1.80 2.25BC846DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 17 July 2009 6 of 12 NXP Semiconductors BC846DS 65 V, 100 mA NPN/NPN general-purpose transistor VCE = 5 V; Tamb = 25 °C IC/IB = 20 (1) Tamb = −55 °C (2) Tamb = 25 °C (3) Tamb = 100 °C Fig 5. Per transistor: Base-emitter voltage as a function of collector current; typical values Fig 6. Per transistor: Base-emitter saturation voltage as a function of collector current; typical values IC/IB = 20 (1) Tamb = 100 °C (2) Tamb = 25 °C (3) Tamb = −55 °C VCE = 5 V; Tamb = 25 °C Fig 7. Per transistor: Collector-emitter saturation voltage as a function of collector current; typical values Fig 8. Per transistor: Transition frequency as a function of collector current; typical values 006aaa536 0.6 0.8 1 VBE (V) 0.4 IC (mA) 10−1 103 102 1 10 006aaa534 IC (mA) 10−1 103 102 1 10 0.5 0.9 1.3 0.3 0.7 1.1 VBEsat (V) 0.1 (1) (2) (3) 006aaa535 1 10−1 10 VCEsat (V) 10−2 IC (mA) 10−1 103 102 1 10 (1) (2) (3) 006aaa537 IC (mA) 1 102 10 102 103 fT (MHz) 10BC846DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 17 July 2009 7 of 12 NXP Semiconductors BC846DS 65 V, 100 mA NPN/NPN general-purpose transistor f = 1 MHz; Tamb = 25 °C f = 1 MHz; Tamb = 25 °C Fig 9. Per transistor: Collector capacitance as a function of collector-base voltage; typical values Fig 10. Per transistor: Emitter capacitance as a function of emitter-base voltage; typical values VCB (V) 0 10 2 4 6 8 006aab620 2 4 6 Cc (pF) 0 006aaa539 VEB (V) 0 6 2 4 9 11 7 13 15 Ce (pF) 5BC846DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 17 July 2009 8 of 12 NXP Semiconductors BC846DS 65 V, 100 mA NPN/NPN general-purpose transistor 8. Test information 8.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is suitable for use in automotive applications. 9. Package outline 10. Packing information [1] For further information and the availability of packing methods, see Section 14. [2] T1: normal taping [3] T2: reverse taping Fig 11. Package outline SOT457 (SC-74) Dimensions in mm 04-11-08 3.0 2.5 1.7 1.3 3.1 2.7 pin 1 index 1.9 0.26 0.10 0.40 0.25 0.95 1.1 0.9 0.6 0.2 1 3 2 6 5 4 Table 8. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number Package Description Packing quantity 3000 10000 BC846DS SOT457 4 mm pitch, 8 mm tape and reel; T1 [2] -115 -135 4 mm pitch, 8 mm tape and reel; T2 [3] -125 -165BC846DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 17 July 2009 9 of 12 NXP Semiconductors BC846DS 65 V, 100 mA NPN/NPN general-purpose transistor 11. Soldering Fig 12. Reflow soldering footprint SOT457 (SC-74) Fig 13. Wave soldering footprint SOT457 (SC-74) solder lands solder resist occupied area solder paste sot457_fr 3.45 1.95 3.3 2.825 0.45 (6×) 0.55 (6×) 0.7 (6×) 0.8 (6×) 2.4 0.95 0.95 Dimensions in mm sot457_fw 5.3 5.05 1.45 (6×) 0.45 (2×) 1.5 (4×) 2.85 1.475 1.475 solder lands solder resist occupied area preferred transport direction during soldering Dimensions in mmBC846DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 17 July 2009 10 of 12 NXP Semiconductors BC846DS 65 V, 100 mA NPN/NPN general-purpose transistor 12. Revision history Table 9. Revision history Document ID Release date Data sheet status Change notice Supersedes BC846DS_1 20090717 Product data sheet - -BC846DS_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 17 July 2009 11 of 12 NXP Semiconductors BC846DS 65 V, 100 mA NPN/NPN general-purpose transistor 13. Legal information 13.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 13.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 13.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.NXP Semiconductors BC846DS 65 V, 100 mA NPN/NPN general-purpose transistor © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 17 July 2009 Document identifier: BC846DS_1 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 15. Contents 1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 General description. . . . . . . . . . . . . . . . . . . . . . 1 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Thermal characteristics. . . . . . . . . . . . . . . . . . . 3 7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Test information . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.1 Quality information . . . . . . . . . . . . . . . . . . . . . . 8 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 10 Packing information. . . . . . . . . . . . . . . . . . . . . . 8 11 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11 13.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11 13.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 13.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 13.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11 14 Contact information. . . . . . . . . . . . . . . . . . . . . 11 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1. Product profile 1.1 General description Planar Maximum Efficiency General Application (MEGA) Schottky barrier rectifier with an integrated guard ring for stress protection, encapsulated in a SOD128 small and flat lead Surface-Mounted Device (SMD) plastic package. 1.2 Features ■ Average forward current: IF(AV) ≤ 1 A ■ Reverse voltage: VR ≤ 30 V ■ Low forward voltage ■ High power capability due to clip-bond technology ■ AEC-Q101 qualified ■ Small and flat lead SMD plastic package 1.3 Applications ■ Low voltage rectification ■ High efficiency DC-to-DC conversion ■ Switch Mode Power Supply (SMPS) ■ Reverse polarity protection ■ Low power consumption applications 1.4 Quick reference data [1] Device mounted on a ceramic Printed-Circuit Board (PCB), Al2O3, standard footprint. PMEG3010EP 1 A low VF MEGA Schottky barrier rectifier Rev. 01 — 30 December 2008 Product data sheet Table 1. Quick reference data Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit IF(AV) average forward current square wave; δ = 0.5; f = 20 kHz Tamb ≤ 130 °C [1] - - 1A Tsp ≤ 145 °C - - 1A VR reverse voltage - - 30 V VF forward voltage IF = 1 A - 320 360 mV IR reverse current VR = 30 V - 0.6 1.5 mAPMEG3010EP_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 30 December 2008 2 of 13 NXP Semiconductors PMEG3010EP 1 A low VF MEGA Schottky barrier rectifier 2. Pinning information [1] The marking bar indicates the cathode. 3. Ordering information 4. Marking 5. Limiting values Table 2. Pinning Pin Description Simplified outline Graphic symbol 1 cathode [1] 2 anode 1 2 sym001 1 2 Table 3. Ordering information Type number Package Name Description Version PMEG3010EP - plastic surface-mounted package; 2 leads SOD128 Table 4. Marking codes Type number Marking code PMEG3010EP A1 Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VR reverse voltage Tj = 25 °C - 30 V IF(AV) average forward current square wave; δ = 0.5; f = 20 kHz Tamb ≤ 130 °C [1] - 1A Tsp ≤ 145 °C - 1A IFSM non-repetitive peak forward current square wave; tp = 8 ms [2] - 50 A Ptot total power dissipation Tamb ≤ 25 °C [3][4] - 625 mW [3][5] - 1050 mW [3][1] - 2100 mWPMEG3010EP_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 30 December 2008 3 of 13 NXP Semiconductors PMEG3010EP 1 A low VF MEGA Schottky barrier rectifier [1] Device mounted on a ceramic PCB, Al2O3, standard footprint. [2] Tj = 25 °C prior to surge. [3] Reflow soldering is the only recommended soldering method. [4] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. [5] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for cathode 1 cm2. 6. Thermal characteristics [1] For Schottky barrier diodes thermal runaway has to be considered, as in some applications the reverse power losses PR are a significant part of the total power losses. [2] Reflow soldering is the only recommended soldering method. [3] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. [4] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for cathode 1 cm2. [5] Device mounted on a ceramic PCB, Al2O3, standard footprint. [6] Soldering point of cathode tab. Tj junction temperature - 150 °C Tamb ambient temperature −55 +150 °C Tstg storage temperature −65 +150 °C Table 5. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-a) thermal resistance from junction to ambient in free air [1][2] [3] - - 200 K/W [4] - - 120 K/W [5] - - 60 K/W Rth(j-sp) thermal resistance from junction to solder point [6] - - 12 K/WPMEG3010EP_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 30 December 2008 4 of 13 NXP Semiconductors PMEG3010EP 1 A low VF MEGA Schottky barrier rectifier FR4 PCB, standard footprint Fig 1. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values FR4 PCB, mounting pad for cathode 1 cm2 Fig 2. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values 006aab296 10 1 102 103 Zth(j-a) (K/W) 10−1 tp (s) 10−3 102 103 10 1 10 −2 10−1 duty cycle = 1 0.75 0.5 0.33 0.25 0.2 0.1 0.05 0.02 0.01 0 006aab297 10 1 102 103 Zth(j-a) (K/W) 10−1 tp (s) 10−3 102 103 10 1 10 −2 10−1 duty cycle = 1 0.75 0.5 0.33 0.25 0.2 0.1 0.05 0.02 0.01 0PMEG3010EP_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 30 December 2008 5 of 13 NXP Semiconductors PMEG3010EP 1 A low VF MEGA Schottky barrier rectifier 7. Characteristics Ceramic PCB, Al2O3, standard footprint Fig 3. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values 006aab298 10 1 102 103 Zth(j-a) (K/W) 10−1 tp (s) 10−3 102 103 10 1 10 −2 10−1 duty cycle = 1 0.75 0.5 0.33 0.25 0.2 0.1 0.05 0.02 0.01 0 Table 7. Characteristics Tj = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VF forward voltage IF = 0.1 A - 230 260 mV IF = 0.5 A - 280 310 mV IF = 1 A - 320 360 mV IR reverse current VR = 5 V - 55 - µA VR = 30 V - 0.6 1.5 mA Cd diode capacitance f = 1 MHz VR = 1 V - 170 - pF VR = 10 V - 60 - pFPMEG3010EP_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 30 December 2008 6 of 13 NXP Semiconductors PMEG3010EP 1 A low VF MEGA Schottky barrier rectifier (1) Tj = 150 °C (2) Tj = 125 °C (3) Tj = 85 °C (4) Tj = 25 °C (5) Tj = −40 °C (1) Tj = 125 °C (2) Tj = 85 °C (3) Tj = 25 °C (4) Tj = −40 °C Fig 4. Forward current as a function of forward voltage; typical values Fig 5. Reverse current as a function of reverse voltage; typical values f = 1 MHz; Tamb = 25 °C Fig 6. Diode capacitance as a function of reverse voltage; typical values 006aab299 10−2 10−3 1 10−1 10 IF (A) 10−4 VF (V) 0 0.8 0.2 0.4 0.6 (1) (2) (3) (4) (5) 006aab300 VR (V) 0 30 10 20 1 10−1 10−2 10−3 10−4 10−5 10−6 IR (A) 10−7 (1) (2) (3) (4) VR (V) 0 30 10 20 006aab301 100 200 300 Cd (pF) 0PMEG3010EP_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 30 December 2008 7 of 13 NXP Semiconductors PMEG3010EP 1 A low VF MEGA Schottky barrier rectifier Tj = 150 °C (1) δ = 0.1 (2) δ = 0.2 (3) δ = 0.5 (4) δ = 1 Tj = 125 °C (1) δ = 1 (2) δ = 0.9 (3) δ = 0.8 (4) δ = 0.5 Fig 7. Average forward power dissipation as a function of average forward current; typical values Fig 8. Average reverse power dissipation as a function of reverse voltage; typical values FR4 PCB, standard footprint Tj = 150 °C (1) δ = 1; DC (2) δ = 0.5; f = 20 kHz (3) δ = 0.2; f = 20 kHz (4) δ = 0.1; f = 20 kHz FR4 PCB, mounting pad for cathode 1 cm2 Tj = 150 °C (1) δ = 1; DC (2) δ = 0.5; f = 20 kHz (3) δ = 0.2; f = 20 kHz (4) δ = 0.1; f = 20 kHz Fig 9. Average forward current as a function of ambient temperature; typical values Fig 10. Average forward current as a function of ambient temperature; typical values 006aab302 IF(AV) (A) 0 1.5 0.5 1 0.2 0.1 0.3 0.4 PF(AV) (W) 0 (1) (2) (3) (4) VR (V) 0 30 10 20 006aab303 3.5 PR(AV) (W) 0 0.5 1 1.5 2 2.5 3 (1) (2) (3) (4) Tamb (°C) 0 75 25 150 50 100 125 175 006aab304 0.8 0.4 1.2 1.6 IF(AV) (A) 0 (1) (2) (3) (4) Tamb (°C) 0 75 25 150 50 100 125 175 006aab305 0.8 0.4 1.2 1.6 IF(AV) (A) 0 (1) (2) (3) (4)PMEG3010EP_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 30 December 2008 8 of 13 NXP Semiconductors PMEG3010EP 1 A low VF MEGA Schottky barrier rectifier Ceramic PCB, Al2O3, standard footprint Tj = 150 °C (1) δ = 1; DC (2) δ = 0.5; f = 20 kHz (3) δ = 0.2; f = 20 kHz (4) δ = 0.1; f = 20 kHz Tj = 150 °C (1) δ = 1; DC (2) δ = 0.5; f = 20 kHz (3) δ = 0.2; f = 20 kHz (4) δ = 0.1; f = 20 kHz Fig 11. Average forward current as a function of ambient temperature; typical values Fig 12. Average forward current as a function of solder point temperature; typical values Tamb (°C) 0 75 25 150 50 100 125 175 006aab306 0.8 0.4 1.2 1.6 IF(AV) (A) 0 (1) (2) (3) (4) Tsp (°C) 0 75 25 150 50 100 125 175 006aab307 0.8 0.4 1.2 1.6 IF(AV) (A) 0 (1) (2) (3) (4)PMEG3010EP_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 30 December 2008 9 of 13 NXP Semiconductors PMEG3010EP 1 A low VF MEGA Schottky barrier rectifier 8. Test information The current ratings for the typical waveforms as shown in Figure 9, 10, 11 and 12 are calculated according to the equations: with IM defined as peak current, at DC, and with IRMS defined as RMS current. 8.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is suitable for use in automotive applications. 9. Package outline Fig 13. Duty cycle definition t1 t2 P t 006aaa812 duty cycle δ = t1 t2 IF AV ( ) = IM × δ IRMS IF AV ( ) = IRMS = IM × δ Fig 14. Package outline SOD128 Dimensions in mm 07-09-12 1.1 0.9 0.22 0.10 0.6 0.3 5.0 4.4 4.0 3.6 1.9 1.6 2.7 2.3 1 2PMEG3010EP_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 30 December 2008 10 of 13 NXP Semiconductors PMEG3010EP 1 A low VF MEGA Schottky barrier rectifier 10. Packing information [1] For further information and the availability of packing methods, see Section 14. 11. Soldering Table 8. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number Package Description Packing quantity 3000 PMEG3010EP SOD128 4 mm pitch, 12 mm tape and reel -115 Reflow soldering is the only recommended soldering method. Fig 15. Reflow soldering footprint SOD128 solder lands solder resist occupied area solder paste 3.4 2.5 2.1 (2×) 1.9 (2×) 4.4 4.2 6.2 1.2 (2×) 1.4 (2×) sod128_fr Dimensions in mmPMEG3010EP_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 30 December 2008 11 of 13 NXP Semiconductors PMEG3010EP 1 A low VF MEGA Schottky barrier rectifier 12. Revision history Table 9. Revision history Document ID Release date Data sheet status Change notice Supersedes PMEG3010EP_1 20081230 Product data sheet - -PMEG3010EP_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 30 December 2008 12 of 13 NXP Semiconductors PMEG3010EP 1 A low VF MEGA Schottky barrier rectifier 13. Legal information 13.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 13.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 13.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.NXP Semiconductors PMEG3010EP 1 A low VF MEGA Schottky barrier rectifier © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 30 December 2008 Document identifier: PMEG3010EP_1 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 15. Contents 1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 General description. . . . . . . . . . . . . . . . . . . . . . 1 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Thermal characteristics. . . . . . . . . . . . . . . . . . . 3 7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Test information . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.1 Quality information . . . . . . . . . . . . . . . . . . . . . . 9 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 10 Packing information. . . . . . . . . . . . . . . . . . . . . 10 11 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 13.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 13.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12 14 Contact information. . . . . . . . . . . . . . . . . . . . . 12 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1. Product profile 1.1 General description Planar Schottky barrier single diode with an integrated guard ring for stress protection, encapsulated in a SOD323F (SC-90) very small and flat lead Surface-Mounted Device (SMD) plastic package. 1.2 Features ■ Low forward voltage ■ Very small and flat lead SMD plastic package ■ Low capacitance ■ Flat leads: excellent coplanarity and improved thermal behavior 1.3 Applications ■ Voltage clamping ■ Line termination ■ Reverse polarity protection 1.4 Quick reference data [1] Pulse test: tp ≤ 300 µs; δ ≤ 0.02. BAT54J Schottky barrier single diode Rev. 01 — 8 March 2007 Product data sheet Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit IF forward current - - 200 mA VR reverse voltage - - 30 V VF forward voltage IF = 1 mA [1] - - 320 mVBAT54J_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 8 March 2007 2 of 8 NXP Semiconductors BAT54J Schottky barrier single diode 2. Pinning information [1] The marking bar indicates the cathode. 3. Ordering information 4. Marking 5. Limiting values [1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated, mounting pad for cathode 1 cm2. Table 2. Pinning Pin Description Simplified outline Symbol 1 cathode [1] 2 anode 1 2 sym001 1 2 Table 3. Ordering information Type number Package Name Description Version BAT54J SC-90 plastic surface-mounted package; 2 leads SOD323F Table 4. Marking codes Type number Marking code BAT54J AP Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VR reverse voltage - 30 V IF forward current - 200 mA IFRM repetitive peak forward current tp ≤ 1 s; δ ≤ 0.5 - 300 mA IFSM non-repetitive peak forward current square wave; tp < 10 ms - 600 mA Ptot total power dissipation Tamb ≤ 25 °C [1] - 550 mW Tj junction temperature - 150 °C Tamb ambient temperature −65 +150 °C Tstg storage temperature −65 +150 °CBAT54J_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 8 March 2007 3 of 8 NXP Semiconductors BAT54J Schottky barrier single diode 6. Thermal characteristics [1] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for cathode 1 cm2. [2] Reflow soldering is the only recommended soldering method. [3] Soldering point of cathode tab. 7. Characteristics [1] Pulse test: tp ≤ 300 µs; δ ≤ 0.02. Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-a) thermal resistance from junction to ambient in free air [1][2] - - 230 K/W Rth(j-sp) thermal resistance from junction to solder point [3] - - 55 K/W Table 7. Characteristics Tamb = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VF forward voltage [1] IF = 0.1 mA - - 240 mV IF = 1 mA - - 320 mV IF = 10 mA - - 400 mV IF = 30 mA - - 500 mV IF = 100 mA - - 800 mV IR reverse current VR = 25 V - - 2 µA Cd diode capacitance VR = 1 V; f = 1 MHz - - 10 pFBAT54J_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 8 March 2007 4 of 8 NXP Semiconductors BAT54J Schottky barrier single diode (1) Tamb = 125 °C (2) Tamb = 85 °C (3) Tamb = 25 °C (1) Tamb = 125 °C (2) Tamb = 85 °C (3) Tamb = 25 °C Fig 1. Forward current as a function of forward voltage; typical values Fig 2. Reverse current as a function of reverse voltage; typical values Tamb = 25 °C; f = 1 MHz Fig 3. Diode capacitance as a function of reverse voltage; typical values 103 102 10−1 IF (mA) VF (V) 10 1 0 0.4 0.8 1.2 msa892 (1) (2) (3) (1) (2) (3) 0 10 20 30 VR (V) 103 102 10−1 IR (µA) 10 1 (1) (2) (3) msa893 0 10 20 30 0 5 10 15 VR (V) Cd (pF) msa891BAT54J_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 8 March 2007 5 of 8 NXP Semiconductors BAT54J Schottky barrier single diode 8. Package outline 9. Packing information [1] For further information and the availability of packing methods, see Section 13. 10. Soldering Fig 4. Package outline SOD323F (SC-90) Dimensions in mm 04-09-13 0.80 0.65 0.25 0.10 0.5 0.3 2.7 2.3 1.8 1.6 0.40 0.25 1.35 1.15 1 2 Table 8. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number Package Description Packing quantity 3000 10000 BAT54J SOD323F 4 mm pitch, 8 mm tape and reel -115 -135 Reflow soldering is the only recommended soldering method. Dimensions in mm Fig 5. Reflow soldering footprint SOD323F (SC-90) 001aab169 1.65 0.50 (2×) 2.10 1.60 2.80 0.60 3.05 0.95 0.50 solder lands solder resist occupied area solder pasteBAT54J_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 8 March 2007 6 of 8 NXP Semiconductors BAT54J Schottky barrier single diode 11. Revision history Table 9. Revision history Document ID Release date Data sheet status Change notice Supersedes BAT54J_1 20070308 Product data sheet - -BAT54J_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 8 March 2007 7 of 8 NXP Semiconductors BAT54J Schottky barrier single diode 12. Legal information 12.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 12.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 12.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 12.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 13. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.NXP Semiconductors BAT54J Schottky barrier single diode © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 8 March 2007 Document identifier: BAT54J_1 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 14. Contents 1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 General description. . . . . . . . . . . . . . . . . . . . . . 1 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Thermal characteristics. . . . . . . . . . . . . . . . . . . 3 7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 Packing information. . . . . . . . . . . . . . . . . . . . . . 5 10 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 11 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 6 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 7 12.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 7 12.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 13 Contact information. . . . . . . . . . . . . . . . . . . . . . 7 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 FUJITSU SEMICONDUCTOR DATA SHEET Copyright©2012-2013 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2013.2 Memory FRAM 128K (16 K × 8) Bit SPI MB85RS128B ■ DESCRIPTION MB85RS128B is a FRAM (Ferroelectric Random Access Memory) chip in a configuration of 16,384 words × 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming the nonvolatile memory cells. MB85RS128B adopts the Serial Peripheral Interface (SPI). The MB85RS128B is able to retain data without using a back-up battery, as is needed for SRAM. The memory cells used in the MB85RS128B can be used for 1012 read/write operations, which is a significant improvement over the number of read and write operations supported by Flash memory and E2PROM. MB85RS128B does not take long time to write data like Flash memories or E2PROM, and MB85RS128B takes no wait time. ■ FEATURES • Bit configuration : 16,384 words × 8 bits • Serial Peripheral Interface : SPI (Serial Peripheral Interface) Correspondent to SPI mode 0 (0, 0) and mode 3 (1, 1) • Operating frequency : All commands except READ 33 MHz (Max) READ command 25 MHz (Max) • High endurance : 1012 times / byte • Data retention : 10 years ( + 85 °C), 95 years ( + 55 °C), over 200 years ( + 35 °C) • Operating power supply voltage : 2.7 V to 3.6 V • Low power consumption : Operating power supply current 6 mA (Typ @33 MHz) Standby current 9 μA (Typ) • Operation ambient temperature range : − 40 °C to + 85 °C • Package : 8-pin plastic SOP (FPT-8P-M02) RoHS compliant DS501-00020-2v0-EMB85RS128B 2 DS501-00020-2v0-E ■ PIN ASSIGNMENT ■ PIN FUNCTIONAL DESCRIPTIONS Pin No. Pin Name Functional description 1 CS Chip Select pin This is an input pin to make chips select. When CS is the “H” level, device is in deselect (standby) status and SO becomes High-Z. Inputs from other pins are ignored at this time. When CS is the “L” level, device is in select (active) status. CS has to be the “L” level before inputting op-code. 3 WP Write Protect pin This is a pin to control writing to a status register. The writing of status register (see “■STATUS REGISTER”) is protected in related with WP and WPEN. See “■WRITING PROTECT” for detail. 7 HOLD Hold pin This pin is used to interrupt serial input/output without making chips deselect. When HOLD is the “L” level, hold operation is activated, SO becomes High-Z, SCK and SI become don’t care. While the hold operation, CS has to be retained the “L” level. 6 SCK Serial Clock pin This is a clock input pin to input/output serial data. SI is loaded synchronously to a rising edge, SO is output synchronously to a falling edge. 5 SI Serial Data Input pin This is an input pin of serial data. This inputs op-code, address, and writing data. 2 SO Serial Data Output pin This is an output pin of serial data. Reading data of FRAM memory cell array and status register data are output. This is High-Z during standby. 8 VDD Supply Voltage pin 4 GND Ground pin GND SI SO VDD WP SCK CS HOLD 8 7 6 4 5 3 2 1 (TOP VIEW) (FPT-8P-M02)MB85RS128B DS501-00020-2v0-E 3 ■ BLOCK DIAGRAM SCK SO SI Serial-Parallel Converter FRAM Cell Array 16,384 ✕ 8 Column Decoder/Sense Amp/ Write Amp FRAM Status Register Data Register Parallel-Serial Converter Control Circuit Address Counter Ro w Decoder CS WP HOLDMB85RS128B 4 DS501-00020-2v0-E ■ SPI MODE MB85RS128B corresponds to the SPI mode 0 (CPOL = 0, CPHA = 0) , and SPI mode 3 (CPOL = 1, CPHA = 1) . SCK SI CS SCK SI CS 76543210 76543210 MSB LSB MSB LSB SPI Mode 0 SPI Mode 3MB85RS128B DS501-00020-2v0-E 5 ■ SERIAL PERIPHERAL INTERFACE (SPI) MB85RS128B works as a slave of SPI. More than 2 devices can be connected by using microcontroller equipped with SPI port. By using a microcontroller not equipped with SPI port, SI and SO can be bus connected to use. SCK SS1 HOLD1 MOSI MISO SS2 HOLD2 SCK CS HOLD SISO SCK CS HOLD SISO MB85RS128B MB85RS128B SCK CS HOLD SISO MB85RS128B SPI Microcontroller MOSI : Master Out Slave In MISO : Master In Slave Out SS : Slave Select System Configuration with SPI Port System Configuration without SPI Port MicrocontrollerMB85RS128B 6 DS501-00020-2v0-E ■ STATUS REGISTER ■ OP-CODE MB85RS128B accepts 8 kinds of command specified in op-code. Op-code is a code composed of 8 bits shown in the table below. Do not input invalid codes other than those codes. If CS is risen while inputting op-code, the command are not performed. Bit No. Bit Name Function 7 WPEN Status Register Write Protect This is a bit composed of nonvolatile memories (FRAM). WPEN protects writing to a status register (refer to “■ WRITING PROTECT”) relating with WP input. Writing with the WRSR command and reading with the RDSR command are possible. 6 to 4 ⎯ Not Used Bits These are bits composed of nonvolatile memories, writing with the WRSR command is possible, and “000” is written before shipment. These bits are not used but they are read with the RDSR command. 3 BP1 Block Protect This is a bit composed of nonvolatile memory. This defines size of write protect block for the WRITE command (refer to “■ BLOCK PROTECT”). Writing with the WRSR command and reading with the RDSR command are possible. 2 BP0 1 WEL Write Enable Latch This indicates an FRAM Array and status register are writable. The WREN command is for setting, and the WRDI command is for resetting. With the RDSR command, reading is possible but writing is not possible with the WRSR command. WEL is reset after the following operations. After power ON. After WRDI command recognition. The rising edge of CS after WRSR command recognition. The rising edge of CS after WRITE command recognition. 0 0 This is a bit fixed to “0”. Name Description Op-code WREN Set Write Enable Latch 0000 0110B WRDI Reset Write Enable Latch 0000 0100B RDSR Read Status Register 0000 0101B WRSR Write Status Register 0000 0001B READ Read Memory Code 0000 0011B WRITE Write Memory Code 0000 0010B RDID Read Device ID 1001 1111B FSTRD Fast Read Memory Code 0000 1011BMB85RS128B DS501-00020-2v0-E 7 ■ COMMAND • WREN The WREN command sets WEL (Write Enable Latch) . WEL has to be set with the WREN command before writing operation (WRSR command and WRITE command) . WREN command is applicable to “Up to 33 MHz operation”. • WRDI The WRDI command resets WEL (Write Enable Latch) . Writing operation (WRITE command and WRSR command) are not performed when WEL is reset. WRDI command is applicable to “Up to 33 MHz operation”. SO SCK SI CS 00000110 High-Z 210 3 7654 Invalid Invalid SO SCK SI CS 00000100 High-Z 210 3 7654 Invalid InvalidMB85RS128B 8 DS501-00020-2v0-E • RDSR The RDSR command reads status register data. After op-code of RDSR is input to SI, 8-cycle clock is input to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. In the RDSR command, repeated reading of status register is enabled by sending SCK continuously before rising of CS. RDSR command is applicable to “Up to 33 MHz operation”. • WRSR The WRSR command writes data to the nonvolatile memory bit of status register. After performing WRSR op-code to a SI pin, 8 bits writing data is input. WEL (Write Enable Latch) is not able to be written with WRSR command. A SI value correspondent to bit 1 is ignored. Bit 0 of the status register is fixed to “0” and cannot be written. The SI value corresponding to bit 0 is ignored. The WP signal level shall be fixed before performing the WRSR command, and do not change the WP signal level until the end of command sequence. WRSR command is applicable to “Up to 33 MHz operation”. SO SCK SI CS 00000101 High-Z 210 3 7654 Invalid MSB 210 3 7654 Data Out LSB Invalid SO SCK SI CS 00000001 210 3 7654 Data In MSB 210 3 7654 High-Z LSB 7654 3 210 InstructionMB85RS128B DS501-00020-2v0-E 9 • READ The READ command reads FRAM memory cell array data. Arbitrary 16 bits address and op-code of READ are input to SI. The 2-bit upper address bit is invalid. Then, 8-cycle clock is input to SCK. SO is output synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the READ command is completed, but keeps on reading with automatic address increment which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches the most significant address, it rolls over to the starting address, and reading cycle keeps on infinitely. READ command is applicable to “Up to 25 MHz operation”. • WRITE The WRITE command writes data to FRAM memory cell array. WRITE op-code, arbitrary 16 bits of address and 8 bits of writing data are input to SI. The 2-bit upper address bit is invalid. When 8 bits of writing data is input, data is written to FRAM memory cell array. Risen CS will terminate the WRITE command, but if you continue sending the writing data for 8 bits each before CS rising, it is possible to continue writing with automatic address increment. When it reaches the most significant address, it rolls over to the starting address, and writing cycle can be continued infinitely. WRITE command is applicable to “Up to 33 MHz operation”. SO SCK SI CS 00 0 0 X 1 12 10 MSB 76543210 MSB Data Out High-Z LSB 420 1 Invalid 8 131211109 8 252423222120191 2726 8 3130292 OP-CODE 0 0 1 11 X 3 13 5 16-bit Address Invalid LSB 6 4 57 2 0 13 SO SCK SI CS 00 0 0 X 1 12 10 MSB 76543210 Data In MSB High-Z LSB 420 1 8 131211109 8 252423222120191 2726 8 3130292 OP-CODE 0 0 0 11 X 3 13 5 16-bit Address LSB 6 4 57 2 0 13MB85RS128B 10 DS501-00020-2v0-E • FSTRD The FSTRD command reads FRAM memory cell array data. Arbitrary 16 bits address and op-code of FSTRD are input to SI followed by 8 bits dummy. The 2-bit upper address bit is invalid. Then, 8-cycle clock is input to SCK. SO is output synchronously to the falling edge of SCK. While reading, the SI value is invalid. When CS is risen, the FSTRD command is completed, but keeps on reading with automatic address increment which is enabled by continuously sending clocks to SCK in unit of 8 cycles before CS rising. When it reaches the most significant address, it rolls over to the starting address, and reading cycle keeps on infinitely. FSTRD command is applicable to “Up to 33 MHz operation”. • RDID The RDID command reads fixed Device ID. After performing RDID op-code to SI, 32-cycle clock is input to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. The output is in order of Manufacturer ID (8bit)/Continuation code (8bit)/Product ID (1st Byte)/Product ID (2nd Byte). In the RDID command, SO holds the output state of the last bit after 32-bit Device ID output by continuously sending SCK clock before CS is risen. RDID command is applicable to “Up to 33 MHz operation”. SO SCK SI CS 00 0 1 X 1 13 76543210 MSB High-Z XX 8 11109 33323130 37363534 8 393 0 0 1 12 X Invalid LSB 6 4 57 2 0 13 1 XX 02 24 25232221 Invalid MSB Data Out LSB OP-CODE 16-bit Address 8-bit Dummy SO SCK SI CS MSB 76543210 Data Out Data Out High-Z LSB 8 11109 333231 37363534 8 393 Invalid 30 2 2931 8 10011111 8 6 4 57 2 0 13 bit 7 6 5 4 3 2 1 0 Hex Manufacturer ID 0 0 0 0 0 1 0 0 04H Fujitsu Continuation code 0 1 1 1 1 1 1 1 7FH Proprietary use Density Hex Product ID (1st Byte) 0 0 0 0 0 1 0 0 04H Density: 00100B = 128kbit Proprietary use Hex Product ID (2nd Byte) 0 0 0 0 1 0 0 1 09HMB85RS128B DS501-00020-2v0-E 11 ■ BLOCK PROTECT Writing protect block for WRITE command is configured by the value of BP0 and BP1 in the status register. ■ WRITING PROTECT Writing operation of the WRITE command and the WRSR command are protected with the value of WEL, WPEN, WP as shown in the table. ■ HOLD OPERATION Hold status is retained without aborting a command if HOLD is the “L” level while CS is the “L” level. The timing for starting and ending hold status depends on the SCK to be the “H” level or the “L” level when a HOLD pin input is transited to the hold condition as shown in the diagram below. In case the HOLD pin transited to “L” level when SCK is “L” level, return the HOLD pin to “H” level at SCK being “L” level. In the same manner, in case the HOLD pin transited to “L” level when SCK is “H” level, return the HOLD pin to “H” level at SCK being “H” level. Arbitrary command operation is interrupted in hold status, SCK and SI inputs become don’t care. And, SO becomes High-Z while reading command (RDSR, READ) . If CS is rising during hold status, a command is aborted. In case the command is aborted before its recognition, WEL holds the value before transition to HOLD status. BP1 BP0 Protected Block 0 0 None 0 1 3000H to 3FFFH (upper 1/4) 1 0 2000H to 3FFFH (upper 1/2) 1 1 0000H to 3FFFH (all) WEL WPEN WP Protected Blocks Unprotected Blocks Status Register 0 X X Protected Protected Protected 1 0 X Protected Unprotected Unprotected 1 1 0 Protected Unprotected Protected 1 1 1 Protected Unprotected Unprotected SCK CS Hold Condition HOLD Hold ConditionMB85RS128B 12 DS501-00020-2v0-E ■ ABSOLUTE MAXIMUM RATINGS *:These parameters are based on the condition that VSS is 0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS *:These parameters are based on the condition that VSS is 0 V. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Parameter Symbol Rating Unit Min Max Power supply voltage* VDD − 0.5 + 4.0 V Input voltage* VIN − 0.5 VDD + 0.5 V Output voltage* VOUT − 0.5 VDD + 0.5 V Operation ambient temperature TA − 40 + 85 °C Storage temperature Tstg − 55 + 125 °C Parameter Symbol Value Unit Min Typ Max Power supply voltage* VDD 2.7 3.3 3.6 V Input high voltage* VIH VDD × 0.8 ⎯ VDD + 0.5 V Input low voltage* VIL − 0.5 ⎯ + 0.6 V Operation ambient temperature TA − 40 ⎯ + 85 °CMB85RS128B DS501-00020-2v0-E 13 ■ ELECTRICAL CHARACTERISTICS 1. DC Characteristics (within recommended operating conditions) *1 : Applicable pin : CS, WP, HOLD, SCK, SI *2 : Applicable pin : SO Parameter Symbol Condition Value Unit Min Typ Max Input leakage current*1 |ILI| VIN = 0 V to VDD ⎯ ⎯ 10 μA Output leakage current*2 |ILO| VOUT = 0 V to VDD ⎯ ⎯ 10 μA Operating power supply current IDD SCK = 25 MHz ⎯ 4 5 mA SCK = 33 MHz ⎯ 5 6 mA Standby current ISB All inputs VSS or SCK = SI = CS = VDD ⎯ 9 50 μA Output high voltage VOH IOH = −2 mA VDD × 0.8 ⎯ ⎯ V Output low voltage VOL IOL = 2 mA ⎯ ⎯ 0.4 VMB85RS128B 14 DS501-00020-2v0-E 2. AC Characteristics * : All commands except READ are applicable to “Up to 33 MHz operation”. READ command is applicable to “Up to 25MHz operation”. AC Test Condition Power supply voltage : 2.7 V to 3.6 V Operation ambient temperature : − 40 °C to + 85 °C Input voltage magnitude : 0.3 V to 2.7 V Input rising time : 5 ns Input falling time : 5 ns Input judge level : VDD/2 Output judge level : VDD/2 Parameter Symbol Value Up to 25MHz Operation Up to 33MHz Operation* Unit Min Max Min Max SCK clock frequency fCK 0 25033 MHz Clock high time tCH 20 ⎯ 15 ⎯ ns Clock low time tCL 20 ⎯ 15 ⎯ ns Chip select set up time tCSU 10 ⎯ 10 ⎯ ns Chip select hold time tCSH 10 ⎯ 10 ⎯ ns Output disable time tOD ⎯ 20 ⎯ 20 ns Output data valid time tODV ⎯ 18 ⎯ 13 ns Output hold time tOH 0 ⎯ 0 ⎯ ns Deselect time tD 60 ⎯ 40 ⎯ ns Data in rising time tR ⎯ 50 - 50 ns Data falling time tF ⎯ 50 - 50 ns Data set up time tSU 5 ⎯ 5 ⎯ ns Data hold time tH 5 ⎯ 5 ⎯ ns HOLD set up time tHS 10 ⎯ 10 ⎯ ns HOLD hold time tHH 10 ⎯ 10 ⎯ ns HOLD output floating time tHZ ⎯ 20 ⎯ 20 ns HOLD output active time tLZ ⎯ 20 ⎯ 20 nsMB85RS128B DS501-00020-2v0-E 15 AC Load Equivalent Circuit 3. Pin Capacitance Parameter Symbol Conditions Value Unit Min Max Output capacitance CO VDD = VIN = VOUT = 0 V, f = 1 MHz, TA = + 25 °C ⎯ 10 pF Input capacitance CI ⎯ 10 pF 30 pF Output 3.3 V 1.2 k 0.95 kMB85RS128B 16 DS501-00020-2v0-E ■ TIMING DIAGRAM • Serial Data Timing • Hold Timing SCK CS SI Valid in SO High-Z : H or L tCSU tCH tCL tCH tSU tH tODV tOH tOD tCSH tD High-Z SCK CS SO tHS tHS tHH tHH tHH tHH tHZ tLZ tHZ tLZ tHS tHS HOLD High-Z High-ZMB85RS128B DS501-00020-2v0-E 17 ■ POWER ON/OFF SEQUENCE If VDD falls down below 2.0 V, VDD is required to be started from 1.0 V or less to prevent malfunctions when the power is turned on again (see the figure below). If the device does not operate within the specified conditions of read cycle, write cycle or power on/off sequence, memory data can not be guaranteed. ■ FRAM CHARACTERISTICS *1 : Total number of reading and writing defines the minimum value of endurance, as an FRAM memory operates with destructive readout mechanism. *2 : Minimun values define retention time of the first reading/writing data right after shipment, and these values are calculated by qualification results. ■ NOTE ON USE Data written before performing IR reflow is not guaranteed after IR reflow. Parameter Symbol Value Unit Min Max CS level hold time at power OFF tpd 200 ⎯ ns CS level hold time at power ON tpu 85 ⎯ ns Power supply rising time tr 0.05 200 ms Item Min Max Unit Parameter Read/Write Endurance*1 1012 ⎯ Times/byte Operation Ambient Temperature TA = + 85 °C Data Retention*2 10 ⎯ Years Operation Ambient Temperature TA = + 85 °C 95 ⎯ Operation Ambient Temperature TA = + 55 °C ≥ 200 ⎯ Operation Ambient Temperature TA = + 35 °C GND CS >VDD × 0.8* tpd tr tpu VIL (Max) 1.0 V VIH (Min) 3.0 V VDD CS : don't care CS >VDD × 0.8* CS CS GND VIL (Max) 1.0 V VIH (Min) 3.0 V VDD * : CS (Max) < VDD + 0.5 VMB85RS128B 18 DS501-00020-2v0-E ■ ESD AND LATCH-UP • Current method of Latch-Up Resistance Test Note : The voltage VIN is increased gradually and the current IIN of 300 mA at maximum shall flow. Confirm the latch up does not occur under IIN = ± 300 mA. In case the specific requirement is specified for I/O and IIN cannot be 300 mA, the voltage shall be increased to the level that meets the specific requirement. Test DUT Value ESD HBM (Human Body Model) JESD22-A114 compliant MB85RS128BPNF-G-JNE1 ≥ |2000 V| ESD MM (Machine Model) JESD22-A115 compliant ≥ |200 V| ESD CDM (Charged Device Model) JESD22-C101 compliant ⎯ Latch-Up (I-test) JESD78 compliant ⎯ Latch-Up (Vsupply overvoltage test) JESD78 compliant ⎯ Latch-Up (Current Method) Proprietary method ⎯ Latch-Up (C-V Method) Proprietary method ⎯ A VDD VSS DUT V IIN VIN + - Test terminal Protection Resistance VDD (Max.Rating) Reference terminalMB85RS128B DS501-00020-2v0-E 19 • C-V method of Latch-Up Resistance Test Note : Charge voltage alternately switching 1 and 2 approximately 2 sec interval. This switching process is considered as one cycle. Repeat this process 5 times. However, if the latch-up condition occurs before completing 5times, this test must be stopped immediately. VDD VSS DUT VIN + - SW 1 2 C 200pF V A Test terminal Protection Resistance VDD (Max.Rating) Reference terminalMB85RS128B 20 DS501-00020-2v0-E ■ REFLOW CONDITIONS AND FLOOR LIFE Reflow Profile Item Condition Method IR (infrared reflow) , Convection Times 2 Floor life Before unpacking Please use within 2 years after production. From unpacking to 2nd reflow Within 8 days In case over period of floor life Baking with 125 °C+/-3 °C for 24hrs+2hrs/-0hrs is required. Then please use within 8 days. (Please remember baking is up to 2 times) Floor life condition Between 5 °C and 30 °C and also below 70%RH required. (It is preferred lower humidity in the required temp range.) 260°C (e) (d') (d) 255°C 170 °C 190 °C RT (b) (a) (c) to Note : Temperature on the top of the package body is measured. (a) Average ramp-up rate : 1 °C/s to 4 °C/s (b) Preheat & Soak : 170 °C to 190 °C, 60 s to 180 s (c) Average ramp-up rate : 1 °C/s to 4 °C/s (d) Peak temperature : Temperature 260 °C Max; 255 °C within 10 s (d’) Liquidous temperature : Up to 230 °C within 40 s or Up to 225 °C within 60 s or Up to 220 °C within 80 s (e) Cooling : Natural cooling or forced cooling Liquidous TemperatureMB85RS128B DS501-00020-2v0-E 21 ■ RESTRICTED SUBSTANCES This product complies with the regulations below (Based on current knowledge as of November 2011). • EU RoHS Directive (2002/95/EC) • China RoHS (Administration on the Control of Pollution Caused by Electronic Information Products ( )) • Vietnam RoHS (30/2011/TT-BCT) Restricted substances in each regulation are as follows. * : The mark of “❍” shows below a threshold value. Substances Threshold Contain status* Lead and its compounds 1,000 ppm ❍ Mercury and its compounds 1,000 ppm ❍ Cadmium and its compounds 100 ppm ❍ Hexavalent chromium compound 1,000 ppm ❍ Polybrominated biphenyls (PBB) 1,000 ppm ❍ Polybrominated diphenyl ethers (PBDE) 1,000 ppm ❍MB85RS128B 22 DS501-00020-2v0-E ■ ORDERING INFORMATION Part number Package Shipping form Minimum shipping quantity MB85RS128BPNF-G-JNE1 8-pin plastic SOP (FPT-8P-M02) Tube 1 MB85RS128BPNF-G-JNERE1 8-pin plastic SOP (FPT-8P-M02) Embossed Carrier tape 1500MB85RS128B DS501-00020-2v0-E 23 ■ PACKAGE DIMENSION Please check the latest package dimension at the following URL. http://edevice.fujitsu.com/package/en-search/ 8-pin plastic SOP Lead pitch 1.27 mm Package width × package length 3.9 mm × 5.05 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.75 mm MAX Weight 0.06 g 8-pin plastic SOP (FPT-8P-M02) (FPT-8P-M02) C 1.27(.050) 3.90±0.30 6.00±0.20 .199 –.008 +.010 –0.20 +0.25 5.05 0.13(.005) M (.154±.012) (.236±.008) 0.10(.004) 1 4 8 5 0.44±0.08 (.017±.003) –0.07 +0.03 0.22 .009 +.001 –.003 45° 0.40(.016) "A" 0~8° 0.25(.010) (Mounting height) Details of "A" part 1.55±0.20 (.061±.008) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) 0.15±0.10 (.006±.004) (Stand off) 0.10(.004) *1 *2 2002-2012 FUJITSU SEMICONDUCTOR LIMITED F08004S-c-5-10 Dimensions in mm (inches). Note: The values in parentheses are reference values. Note 1) 1 : These dimensions include resin protrusion. Note 2) 2 : These dimensions do not include resin protrusion. Note 3) Pins width and pins thickness include plating thickness. Note 4) Pins width do not include tie bar cutting remainder. * *MB85RS128B 24 DS501-00020-2v0-E ■ MARKING RS128B E11150 300 [MB85RS128BPNF-G-JNE1] [MB85RS128BPNF-G-JNERE1] [FPT-8P-M02]MB85RS128B DS501-00020-2v0-E 25 ■ PACKING INFORMATION 1. Tube 1.1 Tube Dimensions • Tube/stopper shape Tube cross-sections and Maximum quantity Package form Package code Maximum quantity pcs/ tube pcs/inner box pcs/outer box SOP, 8, plastic (2) t = 0.5 Transparent polyethylene terephthalate FPT-8P-M02 95 7600 30400 (Dimensions in mm) (treated to antistatic) Tube length: 520 mm (treated to antistatic) Stopper Tube Transparent polyethylene terephthalate 4.4 6.4 7.4 1.8 C 2006 FUJITSU LIMITED F08008-SET1-PET:FJ99L-0022-E0008-1-K-1 2.6 ©2006-2010 FUJITSU SEMICONDUCTOR LIMITED F08008-SET1-PET:FJ99L-0022-E0008-1-K-3MB85RS128B 26 DS501-00020-2v0-E 1.2 Tube Dry pack packing specifications *1: For a product of witch part number is suffixed with “E1”, a “ ” marks is display to the moisture barrier bag and the inner boxes. *2: The space in the outer box will be filled with empty inner boxes, or cushions, etc. *3: Please refer to an attached sheet about the indication label. Note: The packing specifications may not be applied when the product is delivered via a distributer. Tube Dry pack Inner box Outer box For SOP Stopper Aluminum Iaminated bag Index mark Desiccant Label I *1*3 Heat seal Aluminum Iaminated bag (tubes inside) Cushioning material Inner box Label I *1*3 Cushioning material Humidity indicater Outer box*2 Label II-A *3 Label II-B *3 IC Use adhesive tapes. G PbMB85RS128B DS501-00020-2v0-E 27 1.3 Product label indicators Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping) [C-3 Label (50mm × 100mm) Supplemental Label (20mm × 100mm)] Label II-A: Label on Outer box [D Label] (100mm × 100mm) Label II-B: Outer boxes product indicate Note: Depending on shipment state, “Label II-A” and “Label II-B” on the external boxes might not be printed. (Customer part number or FJ part number) (Customer part number or FJ part number) (FJ control number bar code) XX/XX XXXX-XXX XXX XXXX-XXX XXX (Lot Number and quantity) (Package count) (Customer part number or FJ part number bar code) (Part number and quantity) (FJ control number) QC PASS XXXXXXXXXXXXXX XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx (3N)1 XXXXXXXXXXXXXX XXX (Quantity) (3N)2 XXXXXXXXXX XXX pcs XXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX (Customer part number or FJ part number) XXXXXXXXXXXXXX (Comment) XXXXXXXXXX (FJ control number ) (LEAD FREE mark) C-3 Label Supplemental Label Perforated line XXXXXXXXXXXXX (Customer Name) (CUST.) XXX (FJ control number) XXX (FJ control number) XXX (FJ control number) XXXXXXXXXXXXXX (Part number) (FJ control number + Product quantity) (FJ control number + Product quantity bar code) (Part number + Product quantity bar code) XXXXXXXXX (Delivery Address) (DELIVERY POINT) XXXXXXXXXXXXXX (TRANS.NO.) (FJ control number) XXXXXXXXXXXXXX (PART NO.) (Customer part number or FJ part number) XXX/XXX (Q’TY/TOTAL Q’TY) XX (UNIT) (CUSTOMER'S REMARKS) XXXXXXXXXXXXXXXXXXXX (PACKAGE COUNT) XXX/XXX (PART NAME) XXXXXXXXXXXXXX (Part number) (3N)3 XXXXXXXXXXXXXX XXX (3N)4 XXXXXXXXXXXXXX XXX (Part number + Product quantity) (FJ control number) (FJ control number bar code) (3N)5 XXXXXXXXXX D Label XXXXXXXXXXXXXX (Part number) (Lot Number) XXXX-XXX XXXX-XXX (Count) (Quantity) X XXX X XXX XXXMB85RS128B 28 DS501-00020-2v0-E 1.4 Dimensions for Containers (1) Dimensions for inner box (2) Dimensions for outer box LWH 540 125 75 (Dimensions in mm) LWH 565 270 180 (Dimensions in mm) L W H L W HMB85RS128B DS501-00020-2v0-E 29 2. Emboss Tape 2.1 Tape Dimensions PKG code Reel No Maximum storage capacity pcs/reel pcs/inner box pcs/outer box FPT-8P-M02 3 1500 1500 10500 (Dimensions in mm) Material : Conductive polystyrene Heat proof temperature : No heat resistance. Package should not be baked by using tape and reel. C 2012 FUJITSU SEMICONDUCTOR LIMITED SOL8-EMBOSSTAPE9 : NFME-EMB-X0084-1-P-1 8±0.1 6.4±0.1 3.9±0.2 4±0.1 5.5±0.05 5.5±0.1 2.1±0.1 0.4 1.75±0.1 0.3±0.05 2±0.05 +0.1 ø1.5 –0 +0.1 ø1.5 –0 +0.3 –0.1 12 B A B A SEC.A-A SEC.B-BMB85RS128B 30 DS501-00020-2v0-E 2.2 IC orientation 2.3 Reel dimensions Dimensions in mm Reel No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Tape width Symbol 8 12 16 24 32 44 56 12 16 24 A 254 ± 2 254 ± 2 330 ± 2 254 ± 2 330 ± 2 254 ± 2 330 ± 2 330 ± 2 B 100 100 150 100 150 100 100 ± 2 C 13 ± 0.2 13 D 21 ± 0.8 20.5 E 2 ± 0.5 W1 8.4 12.4 16.4 24.4 32.4 44.4 56.4 12.4 16.4 24.4 W2 less than 14.4 less than 18.4 less than 22.4 less than 30.4 less than 38.4 less than 50.4 less than 62.4 less than 18.4 less than 22.4 less than 30.4 W3 7.9 ~ 10.9 11.9 ~ 15.4 15.9 ~ 19.4 23.9 ~ 27.4 31.9 ~ 35.4 43.9 ~ 47.4 55.9 ~ 59.4 12.4 ~ 14.4 16.4 ~ 18.4 24.4 ~ 26.4 r 1.0 (User Direction of Feed) (User Direction of Feed) • ER type Index mark (Reel side) ∗ ∗: Hub unit width dimensions Reel cutout dimensions W1 W2 r E W3 B A C D +2 -0 +2 -0 +2 -0 +2 -0 +2 -0 +2 -0 +0.5 -0.2 +1 -0.2 +2 -0 +2 -0 +2 -0 +2 -0 +2 -0 +2 -0 +2 -0 +1 -0 +1 -0 +0.1 -0MB85RS128B DS501-00020-2v0-E 31 2.4 Taping (φ330mm Reel) Dry Pack Packing Specifications *1: For a product of witch part number is suffixed with “E1”, a “ ” marks is display to the moisture barrier bag and the inner boxes. *2: The size of the outer box may be changed depending on the quantity of inner boxes. *3: The space in the outer box will be filled with empty inner boxes, or cushions, etc. *4: Please refer to an attached sheet about the indication label. Note: The packing specifications may not be applied when the product is delivered via a distributer. Embossed tapes Dry pack Inner box Outer box Outside diameter: 330mm reel Heat seal Label I *1, *4 Label II-B Label II-A *4 *4 Label I *1, *4 Label I *1, *4 Taping Use adhesive tapes. Outer box *2, *3 φ Inner box Label I *1, *4 Desiccant Humidity indicator Aluminum laminated bag G PbMB85RS128B 32 DS501-00020-2v0-E 2.5 Product label indicators Label I: Label on Inner box/Moisture Barrier Bag/ (It sticks it on the reel for the emboss taping) [C-3 Label (50mm × 100mm) Supplemental Label (20mm × 100mm)] Label II-A: Label on Outer box [D Label] (100mm × 100mm) Label II-B: Outer boxes product indicate Note: Depending on shipment state, “Label II-A” and “Label II-B” on the external boxes might not be printed. (Customer part number or FJ part number) (Customer part number or FJ part number) (FJ control number bar code) XX/XX XXXX-XXX XXX XXXX-XXX XXX (Lot Number and quantity) (Package count) (Customer part number or FJ part number bar code) (Part number and quantity) (FJ control number) QC PASS XXXXXXXXXXXXXX XXXX/XX/XX (Packed years/month/day) ASSEMBLED IN xxxx (3N)1 XXXXXXXXXXXXXX XXX (Quantity) (3N)2 XXXXXXXXXX XXX pcs XXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX (Customer part number or FJ part number) XXXXXXXXXXXXXX (Comment) XXXXXXXXXX (FJ control number ) (LEAD FREE mark) C-3 Label Supplemental Label Perforated line XXXXXXXXXXXXX (Customer Name) (CUST.) XXX (FJ control number) XXX (FJ control number) XXX (FJ control number) XXXXXXXXXXXXXX (Part number) (FJ control number + Product quantity) (FJ control number + Product quantity bar code) (Part number + Product quantity bar code) XXXXXXXXX (Delivery Address) (DELIVERY POINT) XXXXXXXXXXXXXX (TRANS.NO.) (FJ control number) XXXXXXXXXXXXXX (PART NO.) (Customer part number or FJ part number) XXX/XXX (Q’TY/TOTAL Q’TY) XX (UNIT) (CUSTOMER'S REMARKS) XXXXXXXXXXXXXXXXXXXX (PACKAGE COUNT) XXX/XXX (PART NAME) XXXXXXXXXXXXXX (Part number) (3N)3 XXXXXXXXXXXXXX XXX (3N)4 XXXXXXXXXXXXXX XXX (Part number + Product quantity) (FJ control number) (FJ control number bar code) (3N)5 XXXXXXXXXX D Label XXXXXXXXXXXXXX (Part number) (Lot Number) XXXX-XXX XXXX-XXX (Count) (Quantity) X XXX X XXX XXXMB85RS128B DS501-00020-2v0-E 33 2.6 Dimensions for Containers (1) Dimensions for inner box (2) Dimensions for outer box Tape width L W H 12, 16 365 345 40 24, 32 50 44 65 56 75 (Dimensions in mm) LWH 415 400 315 (Dimensions in mm) L W H L W HMB85RS128B 34 DS501-00020-2v0-E ■ MAJOR CHANGES IN THIS EDITION A change on a page is indicated by a vertical line drawn on the left side of that page. Page Section Change Results 1 ■ FEATURES Revised the Data retention 10 years ( + 85 °C) →10 years ( + 85 °C), 95 years ( + 55 °C), over 200 years ( + 35 °C) 17 ■ POWER ON/OFF SEQUENCE Revised the following description: “VDD pin is required to be rising from 0 V because turning the power on from an intermediate level may cause malfunctions, when the power is turned on.” → “If VDD falls down below 2.0 V, VDD is required to be started from 1.0 V or less to prevent malfunctions when the power is turned on again (see the figure below).” Moved the following description under the table: “If the device does not operate within the specified conditions of read cycle, write cycle or power on/off sequence, memory data can not be guaranteed.” ■ FRAM CHARACTERISTICS Revised the table and NoteMB85RS128B DS501-00020-2v0-E 35 MEMOMB85RS128B FUJITSU SEMICONDUCTOR LIMITED Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome, Kohoku-ku Yokohama Kanagawa 222-0033, Japan Tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ For further information please contact: North and South America FUJITSU SEMICONDUCTOR AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://us.fujitsu.com/micro/ Europe FUJITSU SEMICONDUCTOR EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ Korea FUJITSU SEMICONDUCTOR KOREA LTD. 902 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fsk/ Asia Pacific FUJITSU SEMICONDUCTOR ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://sg.fujitsu.com/semiconductor/ FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD. 30F, Kerry Parkside, 1155 Fang Dian Road, Pudong District, Shanghai 201204, China Tel : +86-21-6146-3688 Fax : +86-21-6146-3660 http://cn.fujitsu.com/fss/ FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD. 2/F, Green 18 Building, Hong Kong Science Park, Shatin, N.T., Hong Kong Tel : +852-2736-3232 Fax : +852-2314-4207 http://cn.fujitsu.com/fsp/ Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department 1. Product profile 1.1 General description Standard level N-channel MOSFET in LFPAK package qualified to 175 °C. This product is designed and qualified for use in a wide range of industrial, communications and domestic equipment. 1.2 Features and benefits „ Advanced TrenchMOS provides low RDSon and low gate charge „ High efficiency gains in switching power converters „ Improved mechanical and thermal characteristics „ LFPAK provides maximum power density in a Power SO8 package 1.3 Applications „ DC-to-DC converters „ Lithium-ion battery protection „ Load switching „ Motor control „ Server power supplies 1.4 Quick reference data PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET Rev. 02 — 28 October 2010 Product data sheet Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 80 V ID drain current Tmb = 25 °C; VGS = 10 V; see Figure 1 - - 67 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - - 117 W Tj junction temperature -55 - 175 °C Static characteristics RDSon drain-source on-state resistance VGS = 10 V; ID = 25 A; Tj = 100 °C; see Figure 12 - - 18 mΩ VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 12; see Figure 13 - 8.6 11 mΩPSMN011-80YS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 28 October 2010 2 of 15 NXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET 2. Pinning information 3. Ordering information Dynamic characteristics QGD gate-drain charge VGS = 10 V; ID = 25 A; VDS = 40 V; see Figure 14; see Figure 15 - 11 - nC QG(tot) total gate charge - 45 - nC Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy VGS = 10 V; Tj(init) = 25 °C; ID = 67 A; Vsup ≤ 80 V; RGS = 50 Ω; unclamped - - 121 mJ Table 1. Quick reference data …continued Symbol Parameter Conditions Min Typ Max Unit Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 S source SOT669 (LFPAK) 2 S source 3 S source 4 G gate mb D mounting base; connected to drain mb 1234 S D G mbb076 Table 3. Ordering information Type number Package Name Description Version PSMN011-80YS LFPAK plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669PSMN011-80YS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 28 October 2010 3 of 15 NXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 80 V VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ - 80 V VGS gate-source voltage -20 20 V ID drain current VGS = 10 V; Tmb = 100 °C; see Figure 1 - 47 A VGS = 10 V; Tmb = 25 °C; see Figure 1 - 67 A IDM peak drain current pulsed; tp ≤ 10 µs; Tmb = 25 °C; see Figure 3 - 266 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - 117 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Tsld(M) peak soldering temperature - 260 °C Source-drain diode IS source current Tmb = 25 °C - 67 A ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 266 A Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy VGS = 10 V; Tj(init) = 25 °C; ID = 67 A; Vsup ≤ 80 V; RGS = 50 Ω; unclamped - 121 mJ Fig 1. Continuous drain current as a function of mounting base temperature Fig 2. Normalized total power dissipation as a function of mounting base temperature 003aad341 0 20 40 60 80 0 50 100 150 200 Tmb (°C) ID (A) Tmb (°C) 0 200 50 100 150 03aa16 40 80 120 Pder (%) 0PSMN011-80YS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 28 October 2010 4 of 15 NXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage 003aad343 10-1 1 10 102 103 1 10 102 103 VDS (V) ID (A) DC 100 ms 10 ms 1 ms 100 μs 10 μs Limit RDSon = VDS / IDPSMN011-80YS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 28 October 2010 5 of 15 NXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base see Figure 4 - 0.5 1.3 K/W Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration; typical values 003aad342 single shot 0.2 0.1 0.05 0.02 10−3 10−2 10−1 1 1−6 10−5 10−4 10−3 10−2 10−1 1 tp (s) Zth (j-mb) (K/W) δ = 0.5PSMN011-80YS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 28 October 2010 6 of 15 NXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET 6. Characteristics Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = -55 °C 73 - - V ID = 250 µA; VGS = 0 V; Tj = 25 °C 80 - - V VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 175 °C; see Figure 10 1- - V ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 10 - - 4.6 V ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 11; see Figure 10 234V IDSS drain leakage current VDS = 80 V; VGS = 0 V; Tj = 25 °C - 0.02 1 µA VDS = 80 V; VGS = 0 V; Tj = 125 °C - - 100 µA IGSS gate leakage current VGS = -20 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = 20 V; VDS = 0 V; Tj = 25 °C - - 100 nA RDSon drain-source on-state resistance VGS = 10 V; ID = 25 A; Tj = 175 °C; see Figure 12 - 19 26 mΩ VGS = 10 V; ID = 25 A; Tj = 100 °C; see Figure 12 - - 18 mΩ VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 12; see Figure 13 - 8.6 11 mΩ RG internal gate resistance (AC) f = 1 MHz - 0.7 - Ω Dynamic characteristics QG(tot) total gate charge ID = 0 A; VDS = 0 V; VGS = 10 V - 38 - nC ID = 25 A; VDS = 40 V; VGS = 10 V; see Figure 14; see Figure 15 - 45 - nC QGS gate-source charge - 13 - nC QGS(th) pre-threshold gate-source charge ID = 25 A; VDS = 40 V; VGS = 10 V; see Figure 14 - 8 - nC QGS(th-pl) post-threshold gate-source charge - 5 - nC QGD gate-drain charge ID = 25 A; VDS = 40 V; VGS = 10 V; see Figure 14; see Figure 15 - 11 - nC VGS(pl) gate-source plateau voltage ID = 25 A; VDS = 40 V; see Figure 14; see Figure 15 - 4.9 - V Ciss input capacitance VDS = 40 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 16 - 2800 - pF Coss output capacitance - 270 - pF Crss reverse transfer capacitance - 146 - pF td(on) turn-on delay time VDS = 40 V; RL = 1.6 Ω; VGS = 10 V; RG(ext) = 4.7 Ω - 23 - ns tr rise time - 20 - ns td(off) turn-off delay time - 40 - ns tf fall time - 12 - nsPSMN011-80YS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 28 October 2010 7 of 15 NXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; see Figure 17 - 0.8 1.2 V trr reverse recovery time IS = 40 A; dIS/dt = 100 A/µs; VGS = 0 V; VDS = 40 V - 54 - ns Qr recovered charge - 98 - nC Table 6. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values Fig 7. Forward transconductance as a function of drain current; typical values Fig 8. Input and reverse transfer capacitances as a function of gate-source voltage; typical values 003aad311 0 20 40 60 80 100 0123 VDS (V) ID (A) 8 10 20 5.5 5 6 VGS (V) = 4.5 003aad333 0 20 40 60 80 100 0246 VGS (V) ID (A) Tj = 175 °C Tj = 25 °C 003aad338 0 20 40 60 80 100 0 20 40 60 80 100 ID (A) gfs (S) 003aad337 1000 1500 2000 2500 3000 3500 4000 0 5 10 15 20 25 VGS (V) C (pF) Ciss CrssPSMN011-80YS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 28 October 2010 8 of 15 NXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET Fig 9. Drain-source on-state resistance as a function of gate-source voltage; typical values Fig 10. Gate-source threshold voltage as a function of junction temperature Fig 11. Sub-threshold drain current as a function of gate-source voltage Fig 12. Normalized drain-source on-state resistance factor as a function of junction temperature 003aad339 5 10 15 20 25 30 4 8 12 16 20 VGS (V) RDSon (mΩ) Tj (°C) −60 180 0 60 120 003aad280 2 3 1 4 5 VGS(th) (V) 0 max typ min 03aa35 VGS (V) 0 6 2 4 10−4 10−5 10−2 10−3 10−1 ID (A) 10−6 min typ max 003aae090 0 0.6 1.2 1.8 2.4 3 -60 0 60 120 180 Tj (°C) aPSMN011-80YS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 28 October 2010 9 of 15 NXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET Fig 13. Drain-source on-state resistance as a function of drain current; typical values Fig 14. Gate charge waveform definitions Fig 15. Gate-source voltage as a function of gate charge; typical values Fig 16. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 003aad312 5 8 11 14 17 20 0 20 40 60 80 100 ID (A) RDSon (mΩ) 8 5.5 20 6 10 VGS (V) = 5 003aaa508 VGS VGS(th) QGS1 QGS2 QGD VDS QG(tot) ID QGS VGS(pl) 003aad335 0 2 4 6 8 10 0 10 20 30 40 50 QG (nC) VGS (V) VDS = 40V 64V 16V 003aad336 102 103 104 10-1 1 10 102 VDS (V) C (pF) Ciss Crss CossPSMN011-80YS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 28 October 2010 10 of 15 NXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET Fig 17. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values 003aad334 0 20 40 60 80 100 0 0.3 0.6 0.9 1.2 VSD (V) IS (A) Tj = 25 °C Tj = 175 °CPSMN011-80YS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 28 October 2010 11 of 15 NXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET 7. Package outline Fig 18. Package outline SOT669 (LFPAK) REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA SOT669 MO-235 04-10-13 06-03-16 0 2.5 5 mm scale e E1 b c2 A2 UNIT A A2 b c e DIMENSIONS (mm are the original dimensions) mm 1.10 0.95 A1 A3 0.15 0.00 1.20 1.01 0.50 0.35 b2 4.41 3.62 b3 2.2 2.0 b4 0.9 0.7 0.25 0.19 c2 0.30 0.24 4.10 3.80 6.2 5.8 H 1.3 0.8 L2 0.85 0.40 L 1.3 0.8 L1 8° 0° D w y (1) 5.0 4.8 E(1) 3.3 3.1 E1 D1 (1) (1) max 0.25 4.20 1.27 0.25 0.1 1 2 34 mounting base D1 c Plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669 E b2 b3 b4 H D L2 L1 A w M A C C X 1/2 e y C θ θ (A ) 3 L A A1 detail X Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. PSMN011-80YS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 28 October 2010 12 of 15 NXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes PSMN011-80YS v.2 20101028 Product data sheet - PSMN011-80YS v.1 Modifications: • Status changed from objective to product. • Various changes to content. PSMN011-80YS v.1 20100226 Objective data sheet - -PSMN011-80YS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 28 October 2010 13 of 15 NXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET 9. Legal information 9.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 9.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. 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Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.PSMN011-80YS All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 28 October 2010 14 of 15 NXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. 10. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.comNXP Semiconductors PSMN011-80YS N-channel LFPAK 80 V 11 mΩ standard level MOSFET © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 28 October 2010 Document identifier: PSMN011-80YS Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 11. Contents 1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.1 General description . . . . . . . . . . . . . . . . . . . . . .1 1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . .1 1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 2 Pinning information. . . . . . . . . . . . . . . . . . . . . . .2 3 Ordering information. . . . . . . . . . . . . . . . . . . . . .2 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3 5 Thermal characteristics . . . . . . . . . . . . . . . . . . .5 6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .6 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .11 8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . .12 9 Legal information. . . . . . . . . . . . . . . . . . . . . . . .13 9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .13 9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 9.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .14 10 Contact information. . . . . . . . . . . . . . . . . . . . . .14 1. Product profile 1.1 General description Femtofarad bidirectional ElectroStatic Discharge (ESD) protection diode in a leadless ultra small SOD882 Surface-Mounted Device (SMD) plastic package designed to protect one signal line from the damage caused by ESD and other transients. The combination of extremely low capacitance, high ESD maximum rating and ultra small package makes the device ideal for high-speed data line protection and antenna protection applications. 1.2 Features and benefits 1.3 Applications 1.4 Quick reference data PESD5V0F1BL Femtofarad bidirectional ESD protection diode Rev. 3 — 24 October 2011 Product data sheet  Bidirectional ESD protection of one line  ESD protection up to 10 kV  Femtofarad capacitance: Cd = 400 fF  IEC 61000-4-2; level 4 (ESD)  Low ESD clamping voltage: 30 V at 30 ns and  8 kV  AEC-Q101 qualified  Very low leakage current: IRM < 1 nA  10/100/1000 Mbit/s Ethernet  Portable electronics  FireWire  Communication systems  High-speed data lines  Computers and peripherals  Subscriber Identity Module (SIM) card protection  Audio and video equipment  Cellular handsets and accessories  Antenna protection Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit Per device VRWM reverse standoff voltage - - 5.5 V Cd diode capacitance f = 1 MHz; VR = 0 V - 0.4 0.55 pFPESD5V0F1BL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 24 October 2011 2 of 12 NXP Semiconductors PESD5V0F1BL Femtofarad bidirectional ESD protection diode 2. Pinning information 3. Ordering information 4. Marking 5. Limiting values [1] Non-repetitive current pulse 8/20 s exponential decay waveform according to IEC 61000-4-5. Table 2. Pinning Pin Description Simplified outline Graphic symbol 1 cathode (diode 1) 2 cathode (diode 2) 21 Transparent top view sym045 1 2 Table 3. Ordering information Type number Package Name Description Version PESD5V0F1BL - leadless ultra small plastic package; 2 terminals; body 1.0  0.6  0.5 mm SOD882 Table 4. Marking codes Type number Marking code PESD5V0F1BL ZZ Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Per device IPP peak pulse current tp = 8/20 s [1] - 2.5 A Tj junction temperature - 125 C Tamb ambient temperature 40 +125 C Tstg storage temperature 55 +125 CPESD5V0F1BL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 24 October 2011 3 of 12 NXP Semiconductors PESD5V0F1BL Femtofarad bidirectional ESD protection diode [1] Device stressed with ten non-repetitive ESD pulses. Table 6. ESD maximum ratings Tamb = 25 C unless otherwise specified. Symbol Parameter Conditions Min Max Unit Per device VESD electrostatic discharge voltage IEC 61000-4-2 (contact discharge) [1] - 10 kV MIL-STD-883 (human body model) - 10 kV Table 7. ESD standards compliance Standard Conditions Per device IEC 61000-4-2; level 4 (ESD) > 8 kV (contact) MIL-STD-883; class 3 (human body model) > 4 kV Fig 1. 8/20 s pulse waveform according to IEC 61000-4-5 Fig 2. ESD pulse waveform according to IEC 61000-4-2 t (μs) 0 40 10 20 30 001aaa630 40 80 120 IPP (%) 0 e−t 100 % IPP; 8 μs 50 % IPP; 20 μs 001aaa631 IPP 100 % 90 % t 30 ns 60 ns 10 % tr = 0.7 ns to 1 nsPESD5V0F1BL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 24 October 2011 4 of 12 NXP Semiconductors PESD5V0F1BL Femtofarad bidirectional ESD protection diode 6. Characteristics [1] Non-repetitive current pulse 8/20 s exponential decay waveform according to IEC 61000-4-5. Table 8. Characteristics Tamb = 25 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Per device VRWM reverse standoff voltage - - 5.5 V IRM reverse leakage current VRWM = 5 V - 1 100 nA VBR breakdown voltage IR = 1 mA 6 8 10 V Cd diode capacitance f = 1 MHz; VR = 0 V - 0.4 0.55 pF VCL clamping voltage [1] IPP =1A - - 11 V IPP = 2.5 A - - 15 V rdif differential resistance IR = 20 mA - - 30  f = 1 MHz; Tamb = 25 C Fig 3. Diode capacitance as a function of reverse voltage; typical values Fig 4. V-I characteristics for a bidirectional ESD protection diode VR (V) −6.0 −2.0 2.0 6.0 006aab598 0.3 0.4 0.5 Cd (pF) 0.2 006aaa676 −VCL −VBR −VRWM −IRM VRWM VBR VCL IRM −IR IR −IPP IPP − +PESD5V0F1BL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 24 October 2011 5 of 12 NXP Semiconductors PESD5V0F1BL Femtofarad bidirectional ESD protection diode Fig 5. ESD clamping test setup and waveforms 006aab599 50 Ω RZ CZ DUT (DEVICE UNDER TEST) GND GND 450 Ω RG 223/U 50 Ω coax ESD TESTER IEC 61000-4-2 network CZ = 150 pF; RZ = 330 Ω 4 GHz DIGITAL OSCILLOSCOPE 10× ATTENUATOR GND GND unclamped +8 kV ESD pulse waveform (IEC 61000-4-2 network) clamped +8 kV ESD pulse waveform (IEC 61000-4-2 network) pin 1 to 2 unclamped −8 kV ESD pulse waveform (IEC 61000-4-2 network) clamped −8 kV ESD pulse waveform (IEC 61000-4-2 network) pin 1 to 2 vertical scale = 2 kV/div horizontal scale = 15 ns/div vertical scale = 2 kV/div horizontal scale = 15 ns/div vertical scale = 50 V/div horizontal scale = 15 ns/div vertical scale = 50 V/div horizontal scale = 15 ns/divPESD5V0F1BL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 24 October 2011 6 of 12 NXP Semiconductors PESD5V0F1BL Femtofarad bidirectional ESD protection diode 7. Application information PESD5V0F1BL is designed for the protection of one bidirectional data or signal line from the damage caused by ESD and surge pulses. The device may be used on lines where the signal polarities are both, positive and negative with respect to ground. Circuit board layout and protection device placement Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT) and surge transients. The following guidelines are recommended: 1. Place the device as close to the input terminal or connector as possible. 2. The path length between the device and the protected line should be minimized. 3. Keep parallel signal paths to a minimum. 4. Avoid running protected conductors in parallel with unprotected conductors. 5. Minimize all Printed-Circuit Board (PCB) conductive loops including power and ground loops. 6. Minimize the length of the transient return path to ground. 7. Avoid using shared transient return paths to a common ground point. 8. Ground planes should be used whenever possible. For multilayer PCBs, use ground vias. 8. Test information 8.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is suitable for use in automotive applications. Fig 6. Application diagram 006aab600 PESD5V0F1BL GND GPS ANTENNAPESD5V0F1BL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 24 October 2011 7 of 12 NXP Semiconductors PESD5V0F1BL Femtofarad bidirectional ESD protection diode 9. Package outline 10. Packing information [1] For further information and the availability of packing methods, see Section 14. This is a generic drawing for SOD882 package. This product has no cathode marking. Fig 7. Package outline PESD5V0F1BL (SOD882) Dimensions in mm 03-04-17 0.55 0.47 0.65 0.62 0.55 0.50 0.46 cathode marking on top side 1.02 0.95 0.30 0.22 0.30 0.22 2 1 Table 9. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number Package Description Packing quantity 10000 PESD5V0F1BL SOD882 2 mm pitch, 8 mm tape and reel -315PESD5V0F1BL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 24 October 2011 8 of 12 NXP Semiconductors PESD5V0F1BL Femtofarad bidirectional ESD protection diode 11. Soldering Reflow soldering is the only recommended soldering method. Fig 8. Reflow soldering footprint PESD5V0F1BL (SOD882) solder lands solder resist occupied area solder paste sod882_fr 0.9 0.3 (2×) R0.05 (8×) 0.6 (2×) 0.7 (2×) 0.4 (2×) 1.3 0.5 (2×) 0.8 (2×) 0.7 Dimensions in mmPESD5V0F1BL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 24 October 2011 9 of 12 NXP Semiconductors PESD5V0F1BL Femtofarad bidirectional ESD protection diode 12. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes PESD5V0F1BL v.3 20111024 Product data sheet - PESD5V0F1BL v.2 Modifications: • Figure 7 “Package outline PESD5V0F1BL (SOD882)”: updated. • Section 13 “Legal information”: updated. PESD5V0F1BL v.2 20110323 Product data sheet - PESD5V0F1BL v.1 PESD5V0F1BL v.1 20091001 Product data sheet - -PESD5V0F1BL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 24 October 2011 10 of 12 NXP Semiconductors PESD5V0F1BL Femtofarad bidirectional ESD protection diode 13. Legal information 13.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 13.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 13.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. PESD5V0F1BL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 24 October 2011 11 of 12 NXP Semiconductors PESD5V0F1BL Femtofarad bidirectional ESD protection diode Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.comNXP Semiconductors PESD5V0F1BL Femtofarad bidirectional ESD protection diode © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 24 October 2011 Document identifier: PESD5V0F1BL Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 15. Contents 1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 General description . . . . . . . . . . . . . . . . . . . . . 1 1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1 1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . 1 2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Application information. . . . . . . . . . . . . . . . . . . 6 8 Test information. . . . . . . . . . . . . . . . . . . . . . . . . 6 8.1 Quality information . . . . . . . . . . . . . . . . . . . . . . 6 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 10 Packing information . . . . . . . . . . . . . . . . . . . . . 7 11 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 12 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10 13.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10 13.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 13.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 13.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11 14 Contact information. . . . . . . . . . . . . . . . . . . . . 11 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1. Product profile 1.1 General description 500 mA PNP Resistor-Equipped Transistor (RET) in a small SOT23 (TO-236AB) Surface-Mounted Device (SMD) plastic package. NPN complement: PDTD123TT. 1.2 Features and benefits 1.3 Applications 1.4 Quick reference data PDTB123TT PNP 500 mA, 50 V resistor-equipped transistor; R1 = 2.2 kΩ, R2 = open Rev. 4 — 8 November 2010 Product data sheet „ 500 mA output current capability „ Reduces component count „ Built-in bias resistor „ Reduces pick and place costs „ Simplifies circuit design „ AEC-Q101 qualified „ Digital application in automotive and industrial segments „ Cost-saving alternative for BC807 series in digital applications „ Control of IC inputs „ Switching loads Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VCEO collector-emitter voltage open base - - −50 V IO output current - - −500 mA R1 bias resistor 1 (input) 1.54 2.2 2.86 kΩPDTB123TT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 8 November 2010 2 of 10 NXP Semiconductors PDTB123TT PNP 500 mA resistor-equipped transistor; R1 = 2.2 kΩ, R2 = open 2. Pinning information 3. Ordering information 4. Marking [1] * = -: made in Hong Kong * = p: made in Hong Kong * = t: made in Malaysia * = W: made in China Table 2. Pinning Pin Description Simplified outline Graphic symbol 1 input (base) 2 GND (emitter) 3 output (collector) 006aaa144 1 2 3 sym009 3 2 1 R1 Table 3. Ordering information Type number Package Name Description Version PDTB123TT - plastic surface-mounted package; 3 leads SOT23 Table 4. Marking codes Type number Marking code[1] PDTB123TT *1UPDTB123TT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 8 November 2010 3 of 10 NXP Semiconductors PDTB123TT PNP 500 mA resistor-equipped transistor; R1 = 2.2 kΩ, R2 = open 5. Limiting values [1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint. 6. Thermal characteristics [1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VCBO collector-base voltage open emitter - −50 V VCEO collector-emitter voltage open base - −50 V VEBO emitter-base voltage open collector - −5 V VI input voltage positive - +5 V negative - −12 V IO output current - −500 mA Ptot total power dissipation Tamb ≤ 25 °C [1] - 250 mW Tj junction temperature - 150 °C Tamb ambient temperature −65 +150 °C Tstg storage temperature −65 +150 °C Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-a) thermal resistance from junction to ambient in free air [1] - - 500 K/WPDTB123TT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 8 November 2010 4 of 10 NXP Semiconductors PDTB123TT PNP 500 mA resistor-equipped transistor; R1 = 2.2 kΩ, R2 = open 7. Characteristics Table 7. Characteristics Tamb = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit ICBO collector-base cut-off current VCB = −40 V; IE =0A - - −100 nA VCB = −50 V; IE =0A - - −100 nA ICEO collector-emitter cut-off current VCE = −50 V; IB =0A - - −0.5 μA IEBO emitter-base cut-off current VEB = −5 V; IC =0A - - −100 nA hFE DC current gain VCE = −5 V; IC = −50 mA 100 250 - VCEsat collector-emitter saturation voltage IC = −50 mA; IB = −2.5 mA - - −0.3 V R1 bias resistor 1 (input) 1.54 2.2 2.86 kΩ Cc collector capacitance VCB = −10 V; IE = ie = 0 A; f = 100 MHz - 11 - pF VCE = −5 V (1) Tamb = 100 °C (2) Tamb = 25 °C (3) Tamb = −40 °C IC/IB = 20 (1) Tamb = 100 °C (2) Tamb = 25 °C (3) Tamb = −40 °C Fig 1. DC current gain as a function of collector current; typical values Fig 2. Collector-emitter saturation voltage as a function of collector current; typical values 006aaa455 IC (mA) −10−1 −103 −102 −1 −10 103 hFE 102 (2) (3) (1) 006aaa456 IC (mA) −10−1 −102 −1 −10 −10−1 VCEsat (V) −10−2 (2) (3) (1)PDTB123TT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 8 November 2010 5 of 10 NXP Semiconductors PDTB123TT PNP 500 mA resistor-equipped transistor; R1 = 2.2 kΩ, R2 = open 8. Test information 8.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is suitable for use in automotive applications. 9. Package outline 10. Packing information [1] For further information and the availability of packing methods, see Section 14. Fig 3. Package outline SOT23 (TO-236AB) Dimensions in mm 04-11-04 0.45 0.15 1.9 1.1 0.9 3.0 2.8 2.5 2.1 1.4 1.2 0.48 0.38 0.15 0.09 1 2 3 Table 8. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number Package Description Packing quantity 3000 10000 PDTB123TT SOT23 4 mm pitch, 8 mm tape and reel -215 -235PDTB123TT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 8 November 2010 6 of 10 NXP Semiconductors PDTB123TT PNP 500 mA resistor-equipped transistor; R1 = 2.2 kΩ, R2 = open 11. Soldering Fig 4. Reflow soldering footprint SOT23 (TO-236AB) Fig 5. Wave soldering footprint SOT23 (TO-236AB) solder lands solder resist occupied area solder paste sot023_fr 0.5 (3×) 0.6 (3×) 0.6 (3×) 0.7 (3×) 3 1 3.3 2.9 1.7 1.9 2 Dimensions in mm solder lands solder resist occupied area preferred transport direction during soldering sot023_fw 2.8 4.5 1.4 4.6 1.4 (2×) 1.2 (2×) 2.2 2.6 Dimensions in mmPDTB123TT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 8 November 2010 7 of 10 NXP Semiconductors PDTB123TT PNP 500 mA resistor-equipped transistor; R1 = 2.2 kΩ, R2 = open 12. Revision history Table 9. Revision history Document ID Release date Data sheet status Change notice Supersedes PDTB123TT v.4 20101108 Product data sheet - PDTB123T_SER_3 Modifications: • Type numbers PDTB123TK and PDTB123TS deleted. • Table 7 “Characteristics”: unit for VCEsat changed from mV to V. • Section 8 “Test information”: added. • Section 11 “Soldering”: added. • Section 13 “Legal information”: updated. PDTB123T_SER_3 20091116 Product data sheet - PDTB123T_SER_2 PDTB123T_SER_2 20050804 Product data sheet - PDTB123TK_1 PDTB123TK_1 20050519 Product data sheet - -PDTB123TT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 8 November 2010 8 of 10 NXP Semiconductors PDTB123TT PNP 500 mA resistor-equipped transistor; R1 = 2.2 kΩ, R2 = open 13. Legal information 13.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 13.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 13.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. PDTB123TT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 4 — 8 November 2010 9 of 10 NXP Semiconductors PDTB123TT PNP 500 mA resistor-equipped transistor; R1 = 2.2 kΩ, R2 = open Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.comNXP Semiconductors PDTB123TT PNP 500 mA resistor-equipped transistor; R1 = 2.2 kΩ, R2 = open © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 8 November 2010 Document identifier: PDTB123TT Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 15. Contents 1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 General description . . . . . . . . . . . . . . . . . . . . . 1 1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1 1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . 1 2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Thermal characteristics . . . . . . . . . . . . . . . . . . 3 7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Test information. . . . . . . . . . . . . . . . . . . . . . . . . 5 8.1 Quality information . . . . . . . . . . . . . . . . . . . . . . 5 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 5 10 Packing information . . . . . . . . . . . . . . . . . . . . . 5 11 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 12 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 7 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 8 13.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 8 13.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 13.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 13.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 14 Contact information. . . . . . . . . . . . . . . . . . . . . . 9 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 http://www.farnell.com/datasheets/1754399.pdf http://www.farnell.com/datasheets/1754399.pdf 1. Product profile 1.1 General description PNP switching transistor in a SOT23 (TO-236AB) small Surface-Mounted Device (SMD) plastic package. NPN complement: PMBT3904. 1.2 Features and benefits „ Collector-emitter voltage VCEO = −40 V „ Collector current capability IC = −200 mA 1.3 Applications „ General amplification and switching 1.4 Quick reference data 2. Pinning information PMBT3906 PNP switching transistor Rev. 06 — 2 March 2010 Product data sheet Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VCEO collector-emitter voltage open base - - −40 V IC collector current - - −200 mA Table 2. Pinning Pin Description Simplified outline Graphic symbol 1 base 2 emitter 3 collector 1 2 3 006aab259 2 1 3PMBT3906_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 March 2010 2 of 11 NXP Semiconductors PMBT3906 PNP switching transistor 3. Ordering information 4. Marking [1] * = -: made in Hong Kong * = p: made in Hong Kong * = t: made in Malaysia * = W: made in China 5. Limiting values [1] Device mounted on an FR4 Printed-Circuit Board (PCB). Table 3. Ordering information Type number Package Name Description Version PMBT3906 - plastic surface-mounted package; 3 leads SOT23 Table 4. Marking codes Type number Marking code[1] PMBT3906 *2A Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VCBO collector-base voltage open emitter - −40 V VCEO collector-emitter voltage open base - −40 V VEBO emitter-base voltage open collector - −6 V IC collector current - −200 mA ICM peak collector current - −200 mA IBM peak base current - −100 mA Ptot total power dissipation Tamb ≤ 25 °C [1] - 250 mW Tj junction temperature - 150 °C Tamb ambient temperature −65 +150 °C Tstg storage temperature −65 +150 °CPMBT3906_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 March 2010 3 of 11 NXP Semiconductors PMBT3906 PNP switching transistor 6. Thermal characteristics [1] Device mounted on an FR4 PCB. 7. Characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-a) thermal resistance from junction to ambient in free air [1] - - 500 K/W Table 7. Characteristics Tamb = 25 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit ICBO collector-base cut-off current VCB = −30 V; IE =0A - - −50 nA IEBO emitter-base cut-off current VEB = −6 V; IC =0A - - −50 nA hFE DC current gain VCE = −1 V IC = −0.1 mA 60 - - IC = −1 mA 80 - - IC = −10 mA 100 - 300 IC = −50 mA 60 - - IC = −100 mA 30 - - VCEsat collector-emitter saturation voltage IC = −10 mA; IB = −1 mA - - −250 mV IC = −50 mA; IB = −5 mA - - −400 mV VBEsat base-emitter saturation voltage IC = −10 mA; IB = −1 mA - - −850 mV IC = −50 mA; IB = −5 mA - - −950 mV td delay time ICon = −10 mA; IBon = −1 mA; IBoff = 1 mA - - 35 ns tr rise time - - 35 ns ton turn-on time - - 70 ns ts storage time - - 225 ns tf fall time - - 75 ns toff turn-off time - - 300 ns fT transition frequency VCE = −20 V; IC = −10 mA; f = 100 MHz 250 - - MHz Cc collector capacitance VCB = −5 V; IE = ie = 0 A; f = 1 MHz - - 4.5 pF Ce emitter capacitance VEB = −500 mV; IC = ic = 0 A; f = 1 MHz - - 10 pF NF noise figure IC = −100 μA; VCE = −5 V; RS =1kΩ; f = 10 Hz to 15.7 kHz - - 4 dBPMBT3906_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 March 2010 4 of 11 NXP Semiconductors PMBT3906 PNP switching transistor VCE = −1 V (1) Tamb = 150 °C (2) Tamb = 25 °C (3) Tamb = −55 °C Tamb = 25 °C Fig 1. DC current gain as a function of collector current; typical values Fig 2. Collector current as a function of collector-emitter voltage; typical values VCE = −1 V (1) Tamb = −55 °C (2) Tamb = 25 °C (3) Tamb = 150 °C IC/IB = 10 (1) Tamb = −55 °C (2) Tamb = 25 °C (3) Tamb = 150 °C Fig 3. Base-emitter voltage as a function of collector current; typical values Fig 4. Base-emitter saturation voltage as a function of collector current; typical values 0 400 600 200 mhc459 −10−1 −1 −10 IC (mA) hFE −102 −103 (1) (3) (2) 0 −10 −250 0 −50 −100 −150 −200 −2 VCE (V) IC (mA) −4 −6 −8 006aab845 IB (mA) = −1.5 −1.05 −0.75 −0.45 −0.15 −0.3 −0.6 −0.9 −1.2 −1.35 mhc461 −600 −800 −400 −1000 −1200 VBE (mV) −200 IC (mA) −10−1 −103 −102 −1 −10 (1) (2) (3) mhc462 −600 −800 −400 −1000 −1200 VBEsat (mV) −200 IC (mA) −10−1 −103 −102 −1 −10 (1) (2) (3)PMBT3906_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 March 2010 5 of 11 NXP Semiconductors PMBT3906 PNP switching transistor IC/IB = 10 (1) Tamb = 150 °C (2) Tamb = 25 °C (3) Tamb = −55 °C Fig 5. Collector-emitter saturation voltage as a function of collector current; typical values −103 −102 −10 mhc463 −10−1 −1 −10 IC (mA) VCEsat (mV) −102 −103 (1) (2) (3)PMBT3906_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 March 2010 6 of 11 NXP Semiconductors PMBT3906 PNP switching transistor 8. Test information Fig 6. BISS transistor switching time definition VI = 5 V; T = 500 μs; tp = 10 μs; tr = tf ≤ 3 ns R1 = 56 Ω; R2 = 2.5 kΩ; RB = 3.9 kΩ; RC = 270 Ω VBB = 1.9 V; VCC = −3 V Oscilloscope: input impedance Zi = 50 Ω Fig 7. Test circuit for switching times 006aaa266 −IBon (100 %) −IB input pulse (idealized waveform) −IBoff 90 % 10 % −IC (100 %) −IC td ton 90 % 10 % tr output pulse (idealized waveform) tf t ts toff RC R2 R1 DUT mgd624 Vo RB (probe) 450 Ω (probe) 450 Ω oscilloscope oscilloscope VBB VI VCCPMBT3906_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 March 2010 7 of 11 NXP Semiconductors PMBT3906 PNP switching transistor 9. Package outline 10. Packing information [1] For further information and the availability of packing methods, see Section 13. Fig 8. Package outline SOT23 (TO-236AB) Dimensions in mm 04-11-04 0.45 0.15 1.9 1.1 0.9 3.0 2.8 2.5 2.1 1.4 1.2 0.48 0.38 0.15 0.09 1 2 3 Table 8. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number Package Description Packing quantity 3000 10000 PMBT3906 SOT23 4 mm pitch, 8 mm tape and reel -215 -235PMBT3906_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 March 2010 8 of 11 NXP Semiconductors PMBT3906 PNP switching transistor 11. Revision history Table 9. Revision history Document ID Release date Data sheet status Change notice Supersedes PMBT3906_6 20100302 Product data sheet - PMBT3906_N_5 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section 4 “Marking”: amended • Table 7 “Characteristics”: F redefined to NF noise figure • Section 8 “Test information”: added • Figure 6: added • Figure 8: superseded by minimized package outline drawing • Section 10 “Packing information”: added • Section 12 “Legal information”: updated PMBT3906_N_5 20071004 Product data sheet - PMBT3906_4 PMBT3906_4 20040121 Product specification - PMBT3906_3 PMBT3906_3 19990427 Product specification - PMBT3906_CNV_2 PMBT3906_CNV_2 19970505 Product specification - -PMBT3906_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 March 2010 9 of 11 NXP Semiconductors PMBT3906 PNP switching transistor 12. Legal information 12.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 12.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 12.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 12.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. PMBT3906_6 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 2 March 2010 10 of 11 NXP Semiconductors PMBT3906 PNP switching transistor 13. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.comNXP Semiconductors PMBT3906 PNP switching transistor © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 2 March 2010 Document identifier: PMBT3906_6 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 14. Contents 1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 General description . . . . . . . . . . . . . . . . . . . . . 1 1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1 1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . 1 2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Thermal characteristics . . . . . . . . . . . . . . . . . . 3 7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 Test information. . . . . . . . . . . . . . . . . . . . . . . . . 6 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 10 Packing information . . . . . . . . . . . . . . . . . . . . . 7 11 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 8 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 9 12.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 9 12.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Contact information. . . . . . . . . . . . . . . . . . . . . 10 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SG2525A SG3525A REGULATING PULSE WIDTH MODULATORS ..8 TO 35 V OPERATION .5.1 V REFERENCE TRIMMED TO ± 1 % .100 Hz TO 500 KHz OSCILLATOR RANGE .SEPARATE OSCILLATOR SYNC TERMINAL .ADJUSTABLE DEADTIME CONTROL .INTERNAL SOFT-START .PULSE-BY-PULSE SHUTDOWN INPUT UNDERVOLTAGE LOCKOUT WITH .HYSTERESIS LATCHING PWM TO PREVENT MULTIPLE .PULSES DUAL SOURCE/SINK OUTPUT DRIVERS DESCRIPTION The SG3525A series of pulse width modulator integrated circuits are designed to offer improved performance and lowered external parts count when used in designing all types of switching power supplies. The on-chip + 5.1 V reference is trimmed to ± 1 % and the input common-mode range of the error amplifier includes the reference voltage eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchronized to an external system clock. A single resistor between the CT and the discharge terminals provide a wide range of dead time ad- justment. These devices also feature built-in soft-start circuitry with only an external timing capacitor required. A shutdown terminal controls both the soft-start circuity and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft-start recycle with longer shutdown commands. These functions are also controlled by an undervoltage lockout which keeps the outputs off and the soft-start capacitor discharged for sub-normal input voltages. This lockout circuitry includes approximately 500 mV of hysteresis for jitterfree operation. Another feature of these PWM circuits is a latch following the comparator. Once a PWM pulses has been terminated for any reason, the outputs will remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200 mA. The SG3525A output stage features NOR logic, giving a LOW output for an OFF state. DIP16 16(Narrow) Type Plastic DIP SO16 SG2525A SG2525AN SG2525AP SG3525A SG3525AN SG3525AP PIN CONNECTIONS AND ORDERING NUMBERS (top view) ® June 2000 1/12 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Vi Supply Voltage 40 V VC Collector Supply Voltage 40 V IOSC Oscillator Charging Current 5 mA Io Output Current, Source or Sink 500 mA IR Reference Output Current 50 mA IT Current through CT Terminal Logic Inputs Analog Inputs 5 – 0.3 to + 5.5 – 0.3 to Vi mA V V Ptot Total Power Dissipation at Tamb = 70 °C 1000 mW Tj Junction Temperature Range – 55 to 150 °C Tstg Storage Temperature Range – 65 to 150 °C Top Operating Ambient Temperature : SG2525A SG3525A – 25 to 85 0 to 70 °C °C THERMAL DATA Symbol Parameter SO16 DIP16 Unit Rth j-pins Rth j-amb Rth j-alumina Thermal Resistance Junction-pins Max Thermal Resistance Junction-ambient Max Thermal Resistance Junction-alumina (*) Max 50 50 80 °C/W °C/W °C/W * Thermal resistance junction-alumina with the device soldered on the middle of an alumina supporting substrate measuring 15 ´ 20 mm ; 0.65 mm thickness with infinite heatsink. BLOCK DIAGRAM SG2525A-SG3525A 2/12 ELECTRICAL CHARACTERISTICS (V# i = 20 V, and over operating temperature, unless otherwise specified) Symbol Parameter Test Conditions SG2525A SG3525A Unit Min. Typ. Max. Min. Typ. Max. REFERENCE SECTION VREF Output Voltage Tj = 25 °C 5.05 5.1 5.15 5 5.1 5.2 V DVREF Line Regulation Vi = 8 to 35 V 10 20 10 20 mV DVREF Load Regulation IL = 0 to 20 mA 20 50 20 50 mV DVREF/DT* Temp. Stability Over Operating Range 20 50 20 50 mV * Total Output Variation Line, Load and Temperature 5 5.2 4.95 5.25 V Short Circuit Current VREF = 0 Tj = 25 °C 80 100 80 100 mA * Output Noise Voltage 10 Hz £f £ 10 kHz, Tj = 25 °C 40 200 40 200 mVrms DVREF* Long Term Stability Tj = 125 °C, 1000 hrs 20 50 20 50 mV OSCILLATOR SECTION * * *, · Initial Accuracy Tj = 25 °C ± 2 ± 6 ± 2 ± 6 % *, · Voltage Stability Vi = 8 to 35 V ± 0.3 ± 1 ± 1 ± 2 % Df/DT* Temperature Stability Over Operating Range ± 3 ± 6 ± 3 ± 6 % fMIN Minimum Frequency RT = 200 KW CT = 0.1 mF 120 120 Hz fMAX Maximum Frequency RT = 2 KW CT = 470 pF 400 400 KHz Current Mirror IRT = 2 mA 1.7 2 2.2 1.7 2 2.2 mA *, · Clock Amplitude 3 3.5 3 3.5 V *, · Clock Width Tj = 25 °C 0.3 0.5 1 0.3 0.5 1 ms Sync Threshold 1.2 2 2.8 1.2 2 2.8 V Sync Input Current Sync Voltage = 3.5 V 1 2.5 1 2.5 mA ERROR AMPLIFIER SECTION (VCM = 5.1 V) VOS Input Offset Voltage 0.5 5 2 10 mV Ib Input Bias Current 1 10 1 10 mA Ios Input Offset Current 1 1 mA DC Open Loop Gain RL ³ 10 MW 60 75 60 75 dB * Gain Bandwidth Product Gv = 0 dB Tj = 25 °C 1 2 1 2 MHz *, z DC Transconduct. 30 KW £ RL £ 1 MW Tj = 25 °C 1.1 1.5 1.1 1.5 ms Output Low Level 0.2 0.5 0.2 0.5 V Output High Level 3.8 5.6 3.8 5.6 V CMR Comm. Mode Reject. VCM = 1.5 to 5.2 V 60 75 60 75 dB PSR Supply Voltage Rejection Vi = 8 to 35 V 50 60 50 60 dB SG2525A-SG3525A 3/12 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Conditions SG2525A SG3525A Unit Min. Typ. Max. Min. Typ. Max. PWM COMPARATOR Minimum Duty-cycle 0 0 % · Maximum Duty-cycle 45 49 45 49 % · Input Threshold Zero Duty-cycle 0.7 0.9 0.7 0.9 V Maximum Duty-cycle 3.3 3.6 3.3 3.6 V * Input Bias Current 0.05 1 0.05 1 mA SHUTDOWN SECTION Soft Start Current VSD = 0 V, VSS = 0 V 25 50 80 25 50 80 mA Soft Start Low Level VSD = 2.5 V 0.4 0.7 0.4 0.7 V Shutdown Threshold To outputs, VSS = 5.1 V Tj = 25 °C 0.6 0.8 1 0.6 0.8 1 V Shutdown Input Current VSD = 2.5 V 0.4 1 0.4 1 mA * Shutdown Delay VSD = 2.5 V Tj = 25 °C 0.2 0.5 0.2 0.5 ms OUTPUT DRIVERS (each output) (VC = 20 V) Output Low Level Isink = 20 mA 0.2 0.4 0.2 0.4 V Isink = 100 mA 1 2 1 2 V Output High Level Isource = 20 mA 18 19 18 19 V Isource = 100 mA 17 18 17 18 V Under-Voltage Lockout Vcomp and Vss = High 6 7 8 6 7 8 V IC Collector Leakage VC = 35 V 200 200 mA tr* Rise Time CL = 1 nF, Tj = 25 °C 100 600 100 600 ns tf* Fall Time CL = 1 nF, Tj = 25 °C 50 300 50 300 ns TOTAL STANDBY CURRENT Is Supply Current Vi = 35 V 14 20 14 20 mA * These parameters, although guaranteed over the recommended operating conditions, are not 100 % tested in production. · Tested at fosc = 40 KHz (RT = 3.6 KW, CT = 10nF, RD = 0 W). Approximate oscillator frequency is defined by : f = 1 CT (0.7 RT + 3 RD) .DC transconductance (gM) relates to DC open-loop voltage gain (Gv) according to the following equation : Gv = gM RL where RL is the resistance from pin 9 to ground. The minimum gM specification is used to calculate minimum Gv when the error amplifier output is loaded. SG2525A-SG3525A 4/12 TEST CIRCUIT SG2525A-SG3525A 5/12 Figure 1 : Oscillator Charge Time vs. RT and CT. Figure 2 : Oscillator Discharge Time vs. RD and CT. RECOMMENDED OPERATING CONDITIONS (·) Parameter Value Input Voltage (Vi) 8 to 35 V Collector Supply Voltage (VC) 4.5 to 35 V Sink/Source Load Current (steady state) 0 to 100 mA Sink/Source Load Current (peak) 0 to 400 mA Reference Load Current 0 to 20 mA Oscillator Frequency Range 100 Hz to 400 KHz Oscillator Timing Resistor 2 KW to 150 KW Oscillator Timing Capacitor 0.001 mF to 0.1 mF Dead Time Resistor Range 0 to 500 W · (×) Range over which the device is functional and parameter limits are guaranteed. Figure 3 : Output Saturation Characteristics. Figure 4 : Error Amplifier Voltage Gain and Phase vs. Frequency. SG2525A-SG3525A 6/12 SHUTDOWN OPTIONS (see Block Diagram) Since both the compensation and soft-start terminals (Pins 9 and 8) have current source pull-ups, either can readily accept a pull-down signal which only has to sink a maximum of 100 mA to turn off the outputs. This is subject to the added requirement of discharging whatever external capacitance may be attached to these pins. An alternate approach is the use of the shutdown circuitry of Pin 10 which has been improved to enhance the available shutdown options. Activating this circuit by applying a positive signal on Pin 10 performs two functions : the PWM latch is immediately set providing the fastest turn-off signal to the outputs ; and a 150 mA current sink begins to discharge the external soft-start capacitor. If the shutdown command is short, the PWM signal is terminated without significant discharge of the soft-start capacitor, thus, allowing, for example, a convenient implementation of pulse-by-pulse current limiting. Holding Pin 10 high for a longer duration, however, will ultimately discharge this external capacitor, recycling slow turn-on upon release. Pin 10 should not be left floating as noise pickup could conceivably interrupt normal operation. Figure 5 : Error Amplifier. PRINCIPLES OF OPERATION SG2525A-SG3525A 7/12 Figure 7 : Output Circuit (1/2 circuit shown). Figure 6 : Oscillator Schematic. SG2525A-SG3525A 8/12 Figure 10. Figure 11. For single-ended supplies, the driver outputs are grounded. The VC terminal is switched to ground by the totem-pole source transistors on alternate oscillator cycles. In conventional push-pull bipolar designs, forward base drive is controlled by R1 - R3. Rapid turn-off times for the power devices are achieved with speed-up capacitors C1 and C2. The low source impedance of the output drivers provides rapid charging of Power Mos input capacitance while minimizing external components. Low power transformers can be driven directly. Automatic reset occurs during dead time, when both ends of the primary winding are switched to ground. Figure 8. Figure 9. SG2525A-SG3525A 9/12 DIP16 DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. a1 0.51 0.020 B 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L 3.3 0.130 Z 1.27 0.050 OUTLINE AND MECHANICAL DATA SG2525A-SG3525A 10/12 SO16 Narrow DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A 1.75 0.069 a1 0.1 0.25 0.004 0.009 a2 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.020 c1 45° (typ.) D (1) 9.8 10 0.386 0.394 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F (1) 3.8 4 0.150 0.157 G 4.6 5.3 0.181 0.209 L 0.4 1.27 0.016 0.050 M 0.62 0.024 S (1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch). OUTLINE AND MECHANICAL DATA 8°(max.) SG2525A-SG3525A 11/12 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2000 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com SG2525A-SG3525A 12/12 AN2794 Application note 1 kW dual stage DC-AC converter based on the STP160N75F3 Introduction This application note provides design guidelines and performance characterization of the STEVAL-ISV001V1 demonstration board. This board implements a 1 kW dual stage DC-AC converter, suitable for use in batterypowered uninterruptible power supplies (UPS) or photovoltaic (PV) standalone systems. The converter is fed by a low DC input voltage varying from 20 V to 28 V, and is capable of supplying up to 1 kW of output power on a single-phase AC load. These features are possible thanks to a dual stage conversion topology that includes an efficient step-up pushpull DC-DC converter, which produces a regulated high-voltage DC bus and a sinusoidal HBridge PWM inverter to generate a 50 Hz, 230 Vrms output sine wave. Other key features of the system proposed are high power density, high switching frequency and efficiency greater than 90% over a wide output load range Figure 1. 1 kW DC-AC converter prototype www.st.com Contents AN2794 2/39 Doc ID 14827 Rev 2 Contents 1 System description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3 Schematic description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Appendix A Component list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Appendix B Product technical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 AN2794 List of tables Doc ID 14827 Rev 2 3/39 List of tables Table 1. System specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Push-pull converter specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3. HF transformer design parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4. Output inductor design parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5. Power MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 6. Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 7. Bill of material (BOM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 List of figures AN2794 4/39 Doc ID 14827 Rev 2 List of figures Figure 1. 1 kW DC-AC converter prototype . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2. Block diagram of an offline UPS system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. Possible use of a DC-AC converter in standalone PV conversion . . . . . . . . . . . . . . . . . . . . 5 Figure 4. Block diagram of the proposed conversion scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 5. Push-pull converter typical waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6. Distribution of converter losses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 7. Distribution of losses with 3 STP160N75F3s paralleled . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 8. Component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 9. Top layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 10. Bottom layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 11. Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 12. Characteristic waveforms (measured at 24 V input voltage and 280 W resistive load) . . . 26 Figure 13. Characteristic waveforms (measured at 28 V input voltage and 1000 W resistive load) . . 26 Figure 14. MOSFET voltage (ch4) and current (ch3) without RC snubber . . . . . . . . . . . . . . . . . . . . . 27 Figure 15. MOSFET voltage (ch4) and current (ch3) with RC snubber . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 16. Rectifier diode current (ch3) and voltage (ch4) without RDC snubber . . . . . . . . . . . . . . . . 27 Figure 17. Rectifier diode current (ch3) and voltage (ch4) with RDC snubber. . . . . . . . . . . . . . . . . . . 27 Figure 18. Ch1, ch3 MOSFETs drain current, ch2, ch4 MOSFET drain-source voltage . . . . . . . . . . . 28 Figure 19. Startup, ch2, ch3 inverter voltage and current, ch4 DC bus voltage . . . . . . . . . . . . . . . . . 28 Figure 20. DC-DC converter efficiency with 20 V input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 21. DC-DC converter efficiency with 22 V input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 22. DC-DC converter efficiency with 24 V input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 23. DC-DC converter efficiency with 26 V input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 24. DC-DC converter efficiency with 28 V input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 25. Converter efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 26. Technical specification for 1.5 mH 2.5 A inductor L4 (produced by MAGNETICA) . . . . . . 35 Figure 27. Technical specification for 1 kW, 100 kHz switch mode power transformer TX1 (produced by MAGNETICA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 28. Dimensional drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 AN2794 System description Doc ID 14827 Rev 2 5/39 1 System description In a UPS system, as shown in Figure 2, a DC-AC converter is always used to convert the DC power from the batteries to AC power used to supply the load. The basic scheme also includes a battery pack, a battery charger which converts AC power from the grid into DC power, and a transfer switch to supply the load from the mains or from the energy storage elements if a line voltage drop or failure occurs. Figure 2. Block diagram of an offline UPS system Another application where a DC-AC converter is always required is shown in the block diagram of Figure 3. In this case, the converter is part of a conversion scheme commonly used in standalone photovoltaic systems. An additional DC-DC converter operates as a battery charger while performing a maximum power point tracking algorithm (MPPT), which is necessary to maximize the energy yield from the PV array. The battery pack is always present to store energy when solar radiation is available and release it at night or during hours of low insolation. Figure 3. Possible use of a DC-AC converter in standalone PV conversion A possible implementation of an isolated DC-AC converter, which can be successfully used in both the above mentioned applications, is given in the block diagram of Figure 4. It consists of three main sections: 1. The DC-DC converter 2. The DC-AC converter 3. The power supply section Battery AC/DC DC/AC SWITCH Battery Charger + MPPT Batteries LC Filter DC/DC DC/AC Load System description AN2794 6/39 Doc ID 14827 Rev 2 Figure 4. Block diagram of the proposed conversion scheme The DC-DC section is a critical part of the converter design. In fact, the need for high overall efficiency (close to 90% or higher) together with the specifications for continuous power rating, low input voltage range leading to high input current, and the need for high switching frequency to minimize weight and size of passive components, makes it a quite challenging design. Due to the constraints given by the specifications given in Table 1, few topology solutions are suitable to meet the efficiency target. Actually, since the input voltage of the DC-AC converter must be at least equal to 350 V, it is not feasible to use non-isolated DC-DC converters. Moreover, the output power rating prevents the use of single switch topologies such as the flyback and the forward. Among the remaining isolated topologies, the half bridge and full bridge are more suitable for high DC input voltage applications and also characterized by the added complexity of gate drive circuitry of the high side switches. Due to such considerations, the push-pull represents the most suitable choice. This topology features two transistors on the primary side and a center tapped high frequency transformer, as shown in the step-up section in Figure 4. It is quite efficient at low input voltage making it widely used in battery powered UPS applications. Both power devices are ground referenced with consequent simple gate drive circuits. They are alternatively turned Table 1. System specifications Specification Value Nominal input voltage 24 V Output voltage 230 Vrms, 50 Hz Output power 1kW Efficiency 90% Switching frequency 100 kHz (DC-DC); 16 kHz (DC-AC) 􀀳􀁔􀁅􀁐􀀍􀁕􀁐􀀀􀁓􀁔􀁁􀁇􀁅􀀀􀀈􀀰􀁕􀁓􀁈􀀍􀀰􀁕􀁌􀁌􀀉􀀀 􀀳􀀧􀀓􀀕􀀒􀀕 􀀋 􀀳􀀴􀀰􀀑􀀖􀀐􀀮􀀗􀀕􀀦􀀓􀀀 􀀳􀀴􀀴􀀨􀀘􀀲􀀐􀀖 􀀬􀀖􀀓􀀘􀀖􀀀 􀀳􀀴􀀗􀀦􀁌􀁉􀁔􀁅􀀓􀀙 􀀳􀀴􀀧􀀷􀀑􀀙􀀮􀀣􀀖􀀐􀀷􀀤􀀀 􀀋 􀀿 􀀩􀁎􀁖􀁅􀁒􀁔􀁅􀁒􀀀􀀳􀁔􀁁􀁇􀁅􀀀􀀈􀀨􀀍􀀢􀁒􀁉􀁄􀁇􀁅􀀉􀀀 􀀋 􀀋􀀑􀀕􀀶 􀀬􀀗􀀘􀀐􀀕 􀀀􀀀􀀋􀀕􀀶􀀀 􀀀􀀀􀀬􀀕􀀙􀀗􀀓􀀤􀀀 􀀑􀀮􀀕􀀘􀀒􀀑 􀀳􀀴􀀮􀀔􀀮􀀦􀀐􀀓􀀬 􀀰􀁏􀁗􀁅􀁒 􀀳􀁕􀁐􀁐􀁌􀁙􀀀 􀀳􀁅􀁃􀁔􀁉􀁏􀁎􀀀 􀀋 􀀬􀀖􀀓􀀘􀀖 􀀋 􀀿 􀀭􀀑 􀀭􀀒 􀀴􀀸􀀀 􀀬 􀀣 􀀤􀀑 􀀤􀀒 􀀤􀀓􀀀 􀀤􀀔 􀀺􀀑􀀀 􀀺􀀒􀀀 􀀺􀀔􀀀 􀀺􀀓􀀀 􀀶􀁉􀁎 􀀶􀁏􀁕􀁔 􀀡􀀭􀀐􀀐􀀖􀀕􀀘􀁖􀀑 AN2794 System description Doc ID 14827 Rev 2 7/39 on and off in order to transfer power to each primary of the center tapped transformer. Contemporary conduction of both devices must be avoided by limiting the duty cycle value of the constant frequency PWM modulator to less than 0.5. The PWM modulator should also prevent unequal ON times for the driving signals since this would result in transformer saturation caused by the "Flux Walking" phenomenon. The basic operation is similar to a forward converter. In fact, when a primary switch is active, the current flows through the rectifier diodes, charging the output inductor, while when both the switches are off, the output inductor discharges. It is important to point out that the operating frequency of the output inductor is twice the switching frequency. A transformer reset circuit is not needed thanks to the bipolar flux operation, which also means better transformer core utilization with respect to single-ended topologies. The main disadvantage of the push-pull converter is the breakdown voltage of primary power devices which has to be higher than twice the input voltage. In fact, when voltage is applied to one of the two transformer primary windings by the conduction of a transistor, the reflected voltage across the other primary winding puts the drain of the off state transistor at twice the input voltage with respect to ground. This is the reason why push-pull converters are not suitable for high input voltage applications. For the above mentioned reasons, the voltage fed push-pull converter, shown in Figure 4, is chosen to boost the input voltage from 24 V to a regulated 350 V, suitable for optimal inverter operation. The high voltage conversion ratio can be achieved by proper transformer turns ratio design, taking into account that the input to output voltage transfer function is given by: Equation 1 The duty cycle is set by a voltage mode PWM regulator (SG3525) to keep a constant output DC bus voltage. This voltage is then converted into AC using a standard H-bridge converter implemented with four ultrafast switching IGBTs in PowerMESH™ technology, switching at 16 kHz. The switching strategy, based on PWM sinusoidal modulation, is implemented on an 8-bit ST7lite39 microcontroller unit. This allows the use of a simple LC circuit to obtain a high quality sine wave in terms of harmonic content. The power supply section consists of a buck-boost converter to produce a regulated 15 V from a minimum input voltage of 4 V. The circuit can be simply implemented by means of a L5973 device, characterized by an internal P-channel DMOS transistor and few external components. In this way, it is possible to supply all the driving circuits and the PWM modulator. A standard linear regulator, L7805, provides 5 V supply to the microcontroller unit. in 1 2 out DV N N V = 2 Design considerations AN2794 8/39 Doc ID 14827 Rev 2 2 Design considerations The basic operation of a voltage fed push-pull converter is shown in Figure 5, where theoretical converter waveforms are highlighted. In practice, significant overvoltages across devices M1, M2 and across the four rectifier diodes are observed in most cases due to the leakage inductance of the high frequency transformer. As a consequence, the breakdown voltage of primary devices must be greater than twice the input voltage, and the use of snubbing and/or clamping circuits is often helpful. Special attention has to be paid to transformer design, due to the difficulties in minimizing the leakage inductance and implementing low-voltage high-current terminations. Moreover, imbalance in the two primary inductance values must be avoided both by symmetrical windings and proper printed circuit board (PCB) layout. While transformer construction techniques guarantee good symmetry and low leakage inductance values, asymmetrical layout due to inappropriate component placement can be the source of different PCB trace inductances. Whatever the cause of a difference in peak current through the switching elements, transformer saturation in voltage mode push-pull converters can occur in a few switching cycles with catastrophic consequences. Figure 5. Push-pull converter typical waveforms AN2794 Design considerations Doc ID 14827 Rev 2 9/39 Starting from the specifications in Table 2, a step-by-step design procedure and some design hints to obtain a symmetrical layout are given below. A switching frequency of f = 100 kHz was chosen to minimize passive components size and weight, then the following step-by-step calculation was done: ● Switching period: Equation 2 ● Maximum duty cycle The theoretical maximum on time for each phase of the push-pull converter is: Equation 3 Since deadtime has to be provided in order to avoid simultaneous device conduction, it is better to choose the maximum duty cycle of each phase as: Equation 4 This means a total deadtime of 1μs at maximum duty cycle, occurring for minimum input voltage operation. ● Input power Assuming 90% efficiency the input power is: Equation 5 Table 2. Push-pull converter specifications Specification Symbol Value Nominal input voltage Vin 24 V Maximum input voltage Vinmax 28 V Minimum input voltage Vinmin 20 V Nominal output power Pout 1000 W Nominal output voltage Vout 350 V Target efficiency η > 90% Switching frequency f 100 kHz 10 s 10 1 f 1 T 5 = = = μ t on 0.5T 5 s * = = μ 0.45 T t D 0.9 on * max = = 1111W 0.9 P P out in = = Design considerations AN2794 10/39 Doc ID 14827 Rev 2 ● Maximum average input current: Equation 6 ● Maximum equivalent flat topped input current: Equation 7 ● Maximum input RMS current: Equation 8 ● Maximum MOSFET RMS current: Equation 9 ● Minimum MOSFET breakdown voltage: Equation 10 ● Transformer turns ratio: Equation 11 ● Minimum duty cycle value: Equation 12 ● Duty cycle at nominal input voltage: Equation 13 ● Maximum average output current: Equation 14 55.55 A 20 1111 V P I inmin in in = = = 61.72 A 0.9 55.55 2D I I max in pft = = = Iin Ipft 2Dmax 58.55A RMS = = IMosRMS = Ipft Dmax = 41.4A VBrk 1.3 2 VinMax 72.8 V Mos = • • = 19 2V D V N N N in max out 1 2 min = = = 0.32 2NV V D inmax out min = = 0.38 2NV V D in out min = = 2.86A V P I out out out = = AN2794 Design considerations Doc ID 14827 Rev 2 11/39 ● Secondary maximum RMS current Assuming that the secondary top flat current value is equal to the average output value the rms secondary current is: Equation 15 ● Rectifier diode voltage: Equation 16 ● Output filter inductor value: Equation 17 Assuming a ripple current value ΔI= 15% Iout = 0.43A, the minimum value for the output filter inductance is: Equation 18 With this value of inductance continuous current mode (CCM) operation is guaranteed for a minimum output current of: Equation 19 which means a minimum load of 75 W is required for CCM operation. The chosen value for this design is L=1.5 mH. ● Output filter capacitor value: Equation 20 Considering a maximum output ripple value equal to: Equation 21 Isec Iout Dmax 1.91A RMS = = Vdiode = NVinMax = 532 V in 1 2 min V N N L ≥ ( - I t V ) onMax out Δ Lmin = 1.109 mH 0.215A 2 I I outMin = Δ = s 0 L T V I 8 1 C Δ Δ = ΔV0 = 0.1%Vout = 0.35 V Design considerations AN2794 12/39 Doc ID 14827 Rev 2 the minimum value of capacitance is: Equation 22 and the equivalent series resistance (ESR) has to be lower than: Equation 23 ● Input capacitor: Equation 24 where Icrms is the RMS capacitor current value given by: Equation 25 and Equation 26 then Equation 27 Cmin = 1.53 μF = Ω Δ Δ = 0.81 I V ESR L 0 max in onMax in Crms V T C I Δ Δ = I I I2 19A in 2 Crms InRms = - = V 0.1%V 0.028V in inMax Δ = = 3053 F V T C I in onMax in Crms = μ Δ Δ = AN2794 Design considerations Doc ID 14827 Rev 2 13/39 ● HF transformer design The design method is based on the Kg core geometry approach. The design can be done according to the specifications in Table 3. The first step is to compute the transformer apparent power given by: Equation 28 The second step is the electrical condition parameter calculation Ke: Equation 29 where Kf=4 is the waveform coefficient (for square waves). Equation 30 The next step is to calculate the core geometry parameter: Equation 31 Table 3. HF transformer design parameters Specification Symbol Value Nominal input voltage Vin 24 V Maximum input voltage Vinmax 28 V Minimum input voltage Vinmin 20 V RMS input current Iin 41.4 A Nominal output voltage Vout 350 V Output current Iout 2.86 A Switching frequency f 100 kHz Efficiency η 98% Regulation α 0.05% Max operating flux density Bm 0.05T Window utilization Ku 0.3 Duty cycle Dmax 0.45 Temperature rise Tr 30 °C 1)V I 2021 W 1 P ( P P 0 0 0 0 t + = η + = η = ( ) 4 2m 2 2f Ke 0.145 K f B 10= • • • - K 0.145(4)2 (100.000)2 (0.05)2 (10 4 ) 5800 e = = - 5 e t g 0.348 cm 2K P K = α = Design considerations AN2794 14/39 Doc ID 14827 Rev 2 The Kg constant is related to the core geometrical parameters by the following equation: Equation 32 where Wa is the core window area, Ac is the core cross sectional area and MLT is the mean length per turn. For example, choosing an E55/28/21 core with N27 ferrite, having ● Wa= 2.8 cm2 ● Ac= 3.5 cm2 ● MLT= 11.3 cm the resulting Kg factor is: ● Kg= 0.91 cm2 which is then suitable for this application. Once the core has been chosen, it is possible to calculate the number of primary turns as follows: Equation 33 The primary inductance value is: Equation 34 and the number of secondary turns is: Equation 35 At this point wires must be selected in order to implement primary and secondary windings. At 100 kHz the current penetration depth is: Equation 36 Then, the wire diameter can be selected as follows: Equation 37 MLT W A K K u 2c a g = 2 turns BA V D T N c in max 1 min = Δ = L N AL 4 5800 nH 23.2 H 2 p = = • = μ N2 = N • N1 = 38 turns 0.0209 cm f 6.62 δ = = d = 2δ = 0.0418cm AN2794 Design considerations Doc ID 14827 Rev 2 15/39 and the conductor section is: Equation 38 Checking the wire table we notice that AWG26, having a wire area of AWAWG26 = 0.00128 cm2, can be used in this design. Considering a current density J = 500 A/cm2 the number of primary wires is given by: Equation 39 where: Equation 40 Since the AWG26 has a resistance of 1345 μΩ/cm, the primary resistance is: Equation 41 and so the value of resistance for the primary winding is: Equation 42 Using the same procedure, the secondary winding is: Equation 43 Equation 44 Equation 45 Equation 46 2 2 W 0.00137cm 4 d A = π = 62 A A S wAWG26 wp np = = in 2 wp 0.08 cm J I A = = 21.69 / cm 62 1345 / cm rp = μΩ μΩ = Rp = N1 •MLT • rp = 490.1 μΩ out 2 ws 0.00572 cm J I A = = 5 A A S wAWG26 ws ns = = 269 / cm 5 1345 / cm rs = μΩ μΩ = Rs = N2 • MLT • rs = 115 .5mΩ Design considerations AN2794 16/39 Doc ID 14827 Rev 2 The total copper losses are: Equation 47 And transformer regulation is: Equation 48 From the core loss curve of N27 material, at 55 °C, 50mT and 100 kHz, the selected core has the following losses: Equation 49 Where Ve= 43900 mm3 is the core volume. The transformer temperature rise is: Equation 50 with Equation 51 ● Output inductor The output filter inductor can be made using powder cores to minimize eddy current losses and introduce a distributed air gap into the core. The design parameters are shown in Table 4: Table 4. Output inductor design parameters Specification Symbol Value Minimum inductance value Lmin 1.5 mH DC current I0 2.86 A AC current ΔI 0.41 A Output power P0 1000 W Ripple frequency fr 200 kHz Operating flux density Bm 0.3 T Core material Kool μ Window utilization K u 0.4 Temperature rise Tr 25 °C W 78 . 1 I R I R P P P 2s in s 2 Cu = p + s = p + = 100 0.178% P P out α = cu = V 1.23W m kW PV = 28.1 3 • e = T R (P P ) 33 oC r = th • Cu + V = W C R 11 o th = AN2794 Design considerations Doc ID 14827 Rev 2 17/39 The peak current value across the inductor is: Equation 52 To select a proper core we must compute the LI2 pk value: Equation 53 Knowing this parameter, from Magnetics’ core chart, a 46.7 mm x 28.7 mm x 12.2 mm Kool μ toroid, with μ=60 permeability and AL = 0.086 nH/turn can be selected. The required number of turns is then: Equation 54 The resulting magnetizing force (DC bias) is: Equation 55 The initial value of turns has to be increased by dividing it by 0.8 (as shown in the data catalog) to take into account the reduction of initial permeability (μe = 39 at full load) at nominal current value. Then, the adjusted number of turns is: Equation 56 The wire table shows that at 3 A the AWG20 can be used. With this choice, the maximum number of turns per layer, for the selected core, is Nlayer= 96 and the resistance per single layer is rlayer= 0.166Ω. The total winding resistance is then: Equation 57 and the copper losses are: Equation 58 The core losses can be evaluated as follows: 3.06A 2 I Ipk I0 = Δ = + LI2 10.3mH A pk = • 132 turns A L N L = = 84.2 oersteds L NI H 0.4 e = π = N = 165 turns = r = 0.38Ω N N R layer layer W 1 . 3 RI P 2o cu = = Design considerations AN2794 18/39 Doc ID 14827 Rev 2 Equation 59 Equation 60 where MPL=11.8 cm is the magnetic path length. Since the core weight is 95.8 g, the core losses are: Equation 61 ● Analysis of the converter losses Once the transformer has been designed, the next step in performing the loss analysis is to choose the power devices both for the input and output stage of the push-pull converter. According to the calculations given above the following components have been selected: MOSFET and diode losses can be separated into conduction and switching losses which can be estimated, in the worst case operating condition (junction temperature of 100 °C), with the following equations: Equation 62 Equation 63 Equation 64 Table 5. Power MOSFET Device Type RDS(on) tr+tf Vbr Id at 100 °C STP160N75F3 Power MOSFET 4.5 mΩ 70 ns+15 ns 75 V 96 A Table 6. Diode Device Type VF at 175 °C trrMax VRRM IF at 100 °C STTH8R06 Ultrafast diode 1.4 V 25 ns 600 V 8 A P kB2.12f1.23 2.047mW/ g L = ac = ( ) 0.0137T MPL 10 2 I 0.4 N B 4 e ac = μ Δ π = - PL = 0.2W P 1.6R I 12.5W ON RMS Mos 2 cond = ds = Pgate = QgVgsf = 0.165W 8.5W T V I (t t ) 2 1 P Off mos r f sw(ON OFF) = + = + AN2794 Design considerations Doc ID 14827 Rev 2 19/39 Equation 65 Equation 66 Note: Assuming: tB= trr/2, VRM= 350 V Converter losses are distributed according to the graphic in Figure 6, where PCB trace losses and control losses are not considered. What is important to note is that primary switch conduction accounts for 36% of total DC-DC converter losses. This contribution can be reduced by paralleling either two or three power devices. For example, by paralleling three STP160N75F3s, a reduction in MOSFET conduction losses of 33% is achieved. Thus MOSFET conduction losses account for 16% of total DC-DC converter losses, resulting in a 1.8% efficiency improvement. Figure 6. Distribution of converter losses P V I 2.67W condDiode F secRMS = = Pdiode VRMIRRtbf 2.4W SW = = 36% 25% 16% 14% 4% 5% MOSFET cond. Losses MOSFET sw. Losses Diode cond. Losses Diode sw. Losses Transformer Losses Inductor Losses AM00627v1 Design considerations AN2794 20/39 Doc ID 14827 Rev 2 Figure 7. Distribution of losses with 3 STP160N75F3s paralleled 2.1 Layout considerations Because of the high power level involved with this design, the parasitic elements must be reduced as much as possible. Proper operation of the push-pull converter can be assured through geometrical symmetry of the PCB board. In fact, geometrical symmetry leads to electrical symmetry, preventing a difference in the current values across the two primary windings of the transformer which can be the cause of core saturation. The output stage of the converter has also to be routed with a certain degree of symmetry even if in this case the impact of unwanted parasitic elements is lower because of lower current values with respect to the input stage. In Figure 8, Figure 9 and Figure 10, a symmetrical layout designed for the application is shown. 16% 33% 21% 18% 6% 6% MOSFET cond. Losses MOSFET sw. Losses Diode cond. Losses Diode sw. Losses Transformer Losses Inductor Losses AM00628v1 AN2794 Design considerations Doc ID 14827 Rev 2 21/39 Figure 8. Component placement Figure 9. Top layer AM00629v1 AM00630v1 Design considerations AN2794 22/39 Doc ID 14827 Rev 2 Figure 10. Bottom layer To obtain geometrical symmetry the HF transformer has been placed at the center of the board, which has been developed using double-sided, 140 μm FR-4 substrate with 135 x 185 mm size. In addition, this placement of the transformer is the most suitable since it is the bulkiest part of the board. Both the primary and secondary AC current loops are placed very close to the transformer in order to reduce their area and consequently their parasitic inductances. For this reason the MOSFET and rectifier diodes lie at the edges of the PCB. Input loop PCB traces show identical shapes to guarantee the same values of resistance and parasitic inductance. Also the IGBTs of the inverter stage lie at one edge of the board. This gives the advantage of using a single heat sink for each group of power components. The output filter is placed on the right side of the transformer, between the bridge rectifier and the inverter stage. The power supply section lies on the left side of the transformer, simplifying the routing of the 15 V bus dedicated to supply all the control circuitry. AM00631v1 AN2794 Schematic description Doc ID 14827 Rev 2 23/39 3 Schematic description The schematic of the converter is shown in Figure 11. Three MOSFETs are paralleled in order to transfer power to each primary winding of the transformer. Both RC and RCD networks can be connected between the drain and source of the MOSFETs to reduce the overvoltages and voltage ringing caused by unclamped leakage inductance. The output of the transformer is rectified by a full bridge of ultrafast soft-recovery diodes. An RCD network is connected across the rectifier output to clamp the diode voltage to its steady state value and recover the reverse recovery energy stored in the leakage inductance. This energy is first transferred to the clamp capacitor and then partially diverted to the output through a resistor. The IGBT full bridge is connected to the output of the push-pull stage. Their control signals are generated by an SG3525 voltage mode PWM modulator. Its internal clock, necessary to generate the 100 kHz modulation, is set by an external RC network. The PWM output stage is capable of sourcing or sinking up to 100 mA which can be enough to directly drive the gate of the MOSFETs devices. The PWM controller power dissipation, given by the sum of its own power consumption and the power needed to drive six STP160N75F3s at 100 kHz, can be evaluated with the following equation: Equation 67 where Vs and Is are the supply voltage and current. Since this power dissipation would result in a high operating temperature of the IC, a totem pole driving circuit has been used to handle the power losses and peak currents, achieving a more favorable operating condition. This circuit was implemented by means of an NPNPNP complementary pair of BJT transistors. The control and driver stage schematic is shown in Figure 11. PContoller tot = 6QgfVdrive + VsIs = 1.3W Schematic description AN2794 24/39 Doc ID 14827 Rev 2 Figure 11. Schematic 􀀶􀁉􀁎􀀝􀀑􀀒􀀶􀀏􀀒􀀔􀀶 􀀹􀁒􀀠􀀔􀀘􀀹 􀀯􀀱􀁐􀀔􀀠􀀒􀀔􀀱􀀚􀀕􀁘􀀠􀀫􀀔􀀛 􀀖􀀤 􀀹􀀲􀀸􀀷 􀀪􀀤􀀷􀀨􀀃􀀤 􀀪􀀤􀀷􀀨􀀃􀀥 􀀹􀀲􀀸􀀷 􀀳􀀺􀀰􀀃􀀥 􀀳􀀺􀀰􀀃􀀤 􀀳􀀺􀀰􀀃􀀤 􀀪􀀤􀀷􀀨􀀃􀀤 􀀳􀀺􀀰􀀃􀀥 􀀪􀀤􀀷􀀨􀀃􀀥 􀀪􀀤􀀷􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀔 􀀧􀀵􀀤􀀬􀀱􀀃􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀔 􀀪􀀤􀀷􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀕 􀀧􀀵􀀤􀀬􀀱􀀃􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀕 􀀶􀀲􀀸􀀵􀀦􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀔 􀀶􀀲􀀸􀀵􀀦􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀕 􀀪􀀤􀀷􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀯􀀲􀀺􀀃􀀔 􀀪􀀤􀀷􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀯􀀲􀀺􀀃􀀕 􀀶􀀲􀀸􀀵􀀦􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀔 􀀶􀀲􀀸􀀵􀀦􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀕 􀀶􀀲􀀸􀀵􀀦􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀯􀀲􀀺􀀃􀀕 􀀪􀀤􀀷􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀯􀀲􀀺􀀃􀀔 􀀪􀀤􀀷􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀔 􀀪􀀤􀀷􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀯􀀲􀀺􀀃􀀕 􀀪􀀤􀀷􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀕 􀀳􀀺􀀰􀀃􀀯􀀲􀀺􀀔􀀒􀀫􀀬􀀪􀀫􀀕 􀀳􀀺􀀰􀀃􀀯􀀲􀀺􀀕􀀒􀀫􀀬􀀪􀀫􀀔 􀀶􀀲􀀸􀀵􀀦􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀯􀀲􀀺􀀃􀀔 􀀶􀀲􀀸􀀵􀀦􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀯􀀲􀀺􀀃􀀕 􀀶􀀲􀀸􀀵􀀦􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀯􀀲􀀺􀀃􀀔 􀀹􀁌􀁑 􀀎􀀔􀀘􀀹 􀀳􀀺􀀰􀀃􀀯􀀲􀀺􀀔􀀒􀀫􀀬􀀪􀀫􀀕 􀀳􀀺􀀰􀀃􀀯􀀲􀀺􀀕􀀒􀀫􀀬􀀪􀀫􀀔 􀀵􀀨􀀶􀀨􀀷 􀀳􀀤􀀘 􀀳􀀤􀀙 􀀳􀀤􀀘 􀀳􀀤􀀙 􀀵􀀨􀀶􀀨􀀷 􀀎􀀔􀀘􀀹 􀀓 􀀓 􀀎􀀔􀀘􀀹 􀀓 􀀓 􀀓 􀀓 􀀹􀁕􀁈􀁉 􀀓 􀀓 􀀎􀀔􀀘􀀹 􀀎􀀔􀀘􀀹 􀀓 􀀓 􀀹􀁌􀁑 􀀎􀀔􀀘􀀹 􀀎􀀔􀀘􀀹 􀀓 􀀓 􀀓 􀀘􀀹 􀀓 􀀘􀀹 􀀓 􀀓 􀀘􀀹 􀀓 􀀓 􀀓 􀀦􀀔􀀜 􀀕􀀕􀁘􀀃􀀕􀀘􀀹 􀀰􀀖 􀀶􀀷􀀳􀀔􀀙􀀓􀀱􀀚􀀘􀀩􀀖 􀀔 􀀕 􀀖 􀀵􀀜􀀖 􀀔􀀑􀀘􀁎 􀀬􀀦􀀕 􀀯􀀙􀀖􀀛􀀙􀀧 􀀶􀀧 􀀕 􀀹􀀦􀀦 􀀗 􀀯􀀬􀀱 􀀔 􀀫􀀹􀀪 􀀔􀀖 􀀪􀀱􀀧 􀀛 􀀫􀀬􀀱 􀀖 􀀦􀀬􀀱 􀀙 􀀧􀀬􀀤􀀪 􀀘 􀀱􀀦 􀀔􀀓 􀀶􀀪􀀱􀀧 􀀚 􀀯􀀹􀀪 􀀜 􀀲􀀸􀀷 􀀔􀀕 􀀱􀀦􀀔 􀀔􀀔 􀀹􀀥􀀲􀀲􀀷 􀀔􀀗 􀀹􀀬􀀱 􀀦􀀲􀀱􀀔 􀀔 􀀹􀀲􀀸􀀷􀀃􀀤􀀦􀀃􀀔 􀀦􀀲􀀱􀀔 􀀔 􀀦􀀘􀀜 􀀔􀀓􀀓􀁑 􀀵􀀜􀀗 􀀘􀀓􀀓􀀏􀀃􀀕􀀓􀀺 􀀵􀀔􀀓􀀖 􀀔􀀓 􀀦􀀘􀀖 􀀕􀀑􀀕􀁘􀀏􀀃􀀗􀀘􀀓􀀹 􀀵􀀪􀀤􀀷􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀯􀀲􀀺􀀃􀀔 􀀔􀀓􀀓 􀀯􀀗 􀀔􀀑􀀘􀁐􀀫 􀀔 􀀕 􀀦􀀖􀀜 􀀔􀀘􀀓􀁘􀀩􀀃􀀖􀀘􀀹􀀃􀀏􀀃􀁈􀁏􀁈􀁆􀀑 􀀵􀀕􀀗 􀀔􀀓 􀀦􀀕􀀙 􀀕􀀑􀀕􀁘􀀃􀀕􀀘􀀹 􀀵􀀜􀀓 􀀔􀀓􀁎 􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀕 􀀶􀀷􀀪􀀺􀀔􀀜􀀱􀀦􀀙􀀓􀀺􀀧 􀀴􀀛 􀀶􀀷􀀱􀀗􀀱􀀩􀀓􀀖􀀯 􀀦􀁖􀀕 􀀔􀀓􀀓􀁑􀀃􀀙􀀖􀀓􀀹 􀀪􀀱􀀧 􀀦􀀲􀀱􀀔 􀀔 􀀴􀀔􀀔 􀀕􀀶􀀥􀀚􀀚􀀕 􀀦􀀔􀀓 􀀗􀀚􀁘􀀃􀀏􀀃􀀖􀀘􀀹􀀃􀀨􀀯􀀨􀀦 􀀬􀀪􀀥􀀷􀀃􀀯􀀲􀀺􀀃􀀕 􀀶􀀷􀀪􀀺􀀔􀀜􀀱􀀦􀀙􀀓􀀺􀀧 􀀸􀀕􀀓 􀀯􀀚􀀛􀀓􀀘􀀒􀀧􀁁􀀕􀀳􀁄􀁎 􀀹􀀬􀀱 􀀔 􀀪􀀱􀀧 􀀕 􀀹􀀲􀀸􀀷 􀀖 􀀧􀀛 􀀥􀀤􀀷􀀃􀀗􀀙 􀀕 􀀔 􀀧􀀔􀀖 􀀶􀀷􀀷􀀫􀀛􀀵􀀓􀀙 􀀔 􀀕 􀀧􀀔􀀓 􀀶􀀷􀀷􀀫􀀔􀀯􀀓􀀙 􀀔 􀀕 􀀬􀀦􀀔 􀀯􀀙􀀖􀀛􀀙􀀧 􀀶􀀧 􀀕 􀀹􀀦􀀦 􀀗 􀀯􀀬􀀱 􀀔 􀀫􀀹􀀪 􀀔􀀖 􀀪􀀱􀀧 􀀛 􀀫􀀬􀀱 􀀖 􀀦􀀬􀀱 􀀙 􀀧􀀬􀀤􀀪 􀀘 􀀱􀀦 􀀔􀀓 􀀶􀀪􀀱􀀧 􀀚 􀀯􀀹􀀪 􀀜 􀀲􀀸􀀷 􀀔􀀕 􀀱􀀦􀀔 􀀔􀀔 􀀹􀀥􀀲􀀲􀀷 􀀔􀀗 􀀵􀀕􀀔 􀀔􀀕􀀒􀀓􀀑􀀕􀀘􀀺 􀀰􀀘 􀀶􀀷􀀳􀀔􀀙􀀓􀀱􀀚􀀘􀀩􀀖 􀀔 􀀕 􀀖 􀀦􀀖􀀖 􀀗􀀚􀀓􀁑􀀃􀀕􀀘􀀹 􀀦􀀗􀀓 􀀕􀀕􀁑􀀩 􀀦􀀔􀀙 􀀔􀀓􀀓􀁓 􀀵􀀜􀀔 􀀔􀀓􀁎 􀀦􀀔 􀀔􀀓􀀓􀁑 􀀵􀀜􀀘 􀀘􀀓􀀓􀀏􀀃􀀕􀀓􀀺 􀀹􀀲􀀸􀀷􀀃􀀤􀀦􀀃􀀕 􀀦􀀲􀀱􀀔 􀀔 􀀴􀀔􀀕 􀀕􀀶􀀥􀀚􀀚􀀕 􀀸􀀔 􀀶􀀪􀀖􀀘􀀕􀀘 􀀬􀀱􀀐 􀀔 􀀲􀀶􀀦 􀀗 􀀦􀀷 􀀘 􀀧􀀬􀀶􀀦􀀫􀀤􀀵 􀀚 􀀶􀀶 􀀛 􀀶􀀑􀀧􀀲􀀺􀀱 􀀔􀀓 􀀲􀀸􀀷􀀤 􀀔􀀔 􀀪􀀱􀀧 􀀔􀀕 􀀹􀀦 􀀔􀀖 􀀲􀀸􀀷􀀥 􀀔􀀗 􀀵􀀷 􀀙 􀀦􀀲􀀰􀀳 􀀜 􀀶􀀼􀀱􀀦 􀀖 􀀎􀀹􀀬 􀀔􀀘 􀀬􀀱􀀎 􀀕 􀀹􀀵􀀨􀀩 􀀔􀀙 􀀧􀀚 􀀕 􀀔 􀀥􀀤􀀷􀀗􀀙 􀀎 􀀦􀀗􀀕 􀀔􀀓􀀓􀁘􀀩􀀃􀀕􀀘􀀹 􀀧􀀜 􀀶􀀷􀀷􀀫􀀔􀀯􀀓􀀙 􀀔 􀀕 􀀦􀁖􀀔 􀀔􀀓􀀓􀁑􀀃􀀙􀀖􀀓􀀹 􀀵􀀛􀀜 􀀔􀀓􀁎 􀀦􀀘􀀛 􀀓􀀑􀀖􀀖􀁘 􀀭􀀔 􀀦􀀲􀀱􀀔􀀓 􀀔 􀀕􀀖􀀗􀀘􀀙􀀚 􀀛 􀀜 􀀔􀀓 􀀦􀀘􀀘 􀀗􀀑􀀚􀁑􀀏􀀃􀀔􀀓􀀓􀀹 􀀵􀀪􀀤􀀷􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀕 􀀔􀀓􀀓 􀀹􀀲􀀸􀀷􀀃􀀐 􀀦􀀲􀀱􀀔 􀀔 􀀵􀀚 􀀖􀀜􀀓􀀮􀀏􀀃􀀓􀀑􀀕􀀘􀀺􀀃􀀔􀀈 􀀎 􀀦􀀘􀀔 􀀔􀀓􀀓􀁘􀀩􀀃􀀕􀀘􀀹 􀀦􀀘􀀗 􀀗􀀑􀀚􀁑􀀏􀀃􀀔􀀓􀀓􀀹 􀀧􀀔􀀕 􀀔􀀱􀀘􀀛􀀕􀀔 􀀔 􀀕 􀀦􀀖􀀛 􀀖􀀜􀀓􀀓􀁘􀀏􀀃􀀖􀀘􀀹 􀀔 􀀕 􀀵􀀕􀀘 􀀔􀀓 􀀵􀀔􀀓􀀔 􀀔􀀓 􀀦􀀕 􀀔􀀓􀀓􀁑 􀀦􀀔􀀚 􀀙􀀛􀀓􀁑 􀀧􀀔 􀀶􀀷􀀷􀀫􀀛􀀵􀀓􀀙 􀀔 􀀕 􀀯􀀖 􀀔􀀘􀀓􀁘􀀫􀀃􀀖􀀤 􀀵􀀕􀀕 􀀔􀀓 􀀵􀀛􀀔 􀀕􀀕􀁎 􀀵􀀜􀀕 􀀔􀀓􀁎 􀀦􀀖􀀚 􀀖􀀜􀀓􀀓􀁘􀀏􀀃􀀖􀀘􀀹 􀀔 􀀕 􀀦􀀖􀀔 􀀕􀀑􀀕􀁘􀀃􀀕􀀘􀀹 􀀧􀀔􀀔 􀀔􀀱􀀘􀀛􀀕􀀔 􀀔 􀀕 􀀵􀀜􀀙 􀀔􀀓􀀃􀀏􀀃􀀕􀀺 􀀰􀀔 􀀶􀀷􀀳􀀔􀀙􀀓􀀱􀀚􀀘􀀩􀀖 􀀔 􀀕 􀀖 􀀵􀀜􀀛 􀀗􀀚􀁎 􀀦􀀔􀀔 􀀗􀀑􀀚􀁑 􀀦􀀘􀀙 􀀗􀀚􀀓􀁑 􀀦􀀖􀀗 􀀖􀀖􀁘􀀩􀀃􀀗􀀘􀀓􀀹 􀀔 􀀕 􀀵􀀜􀀚 􀀔􀀓􀀃􀀏􀀃􀀕􀀺 􀀵􀀛􀀛 􀀔􀀓􀁎 􀀵􀀪􀀤􀀷􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀯􀀲􀀺􀀃􀀕 􀀔􀀓􀀓 􀀧􀀗 􀀶􀀷􀀷􀀫􀀛􀀵􀀓􀀙 􀀔 􀀕 􀀦􀀕􀀛 􀀗􀀚􀀓􀁑􀀃􀀕􀀘􀀹 􀀦􀀔􀀛 􀀕􀀕􀁘􀀃􀀕􀀘􀀹􀀃 􀀴􀀜 􀀕􀀶􀀧􀀛􀀛􀀕 􀀦􀀔􀀕 􀀔􀀓􀀓􀁘 􀀵􀀕􀀖 􀀔􀀓 􀀕 􀀧􀀘 􀀔 􀀥􀀤􀀷􀀃􀀗􀀙 􀀦􀀙􀀓 􀀔􀀘􀀓􀁑 􀀵􀀛􀀕 􀀖􀀑􀀖􀁎 􀀵􀀜 􀀘􀀑􀀙􀀮􀀏􀀃􀀔􀀈 􀀰􀀗 􀀶􀀷􀀳􀀔􀀙􀀓􀀱􀀚􀀘􀀩􀀖 􀀔 􀀕 􀀖 􀀧􀀕 􀀶􀀷􀀷􀀫􀀛􀀵􀀓􀀙 􀀔 􀀕 􀀯􀁓􀀕 􀀯􀁓􀀔 􀀯􀁖 􀀷􀀻􀀔 􀀷􀀵􀀤􀀩􀀲􀀃􀀰􀀤􀀪􀀱􀀨􀀷􀀬􀀦􀀤 􀀹􀀲􀀸􀀷􀀃􀀎 􀀦􀀲􀀱􀀔 􀀔 􀀸􀀔􀀚 􀀶􀀷􀀚􀀩􀀯􀀬􀀷􀀨􀀖􀀜􀁂􀀶􀀲􀀬􀀦􀁂􀀕􀀓􀀳 􀀹􀀶􀀶 􀀔 􀀹􀀧􀀧 􀀕 􀀵􀀨􀀶􀀨􀀷 􀀖 􀀲􀀶􀀦􀀔􀀒􀀦􀀯􀀮􀀬􀀱 􀀕􀀓 􀀲􀀶􀀦􀀕 􀀔􀀜 􀀳􀀤􀀓􀀒􀀯􀀷􀀬􀀦 􀀔􀀛 􀀳􀀤􀀔􀀒􀀤􀀷􀀬􀀦 􀀔􀀚 􀀳􀀤􀀕􀀒􀀤􀀷􀀳􀀺􀀰􀀓 􀀔􀀙 􀀳􀀤􀀖􀀒􀀤􀀷􀀳􀀺􀀰􀀔 􀀔􀀘 􀀳􀀤􀀗􀀒􀀤􀀷􀀳􀀺􀀰􀀕 􀀔􀀗 􀀳􀀤􀀘􀀒􀀤􀀷􀀳􀀺􀀰􀀖􀀒􀀬􀀦􀀦􀀧􀀤􀀷􀀤 􀀔􀀖 􀀳􀀤􀀙􀀒􀀰􀀦􀀲􀀒􀀬􀀦􀀦􀀦􀀯􀀮􀀒􀀥􀀵􀀨􀀤􀀮 􀀔􀀕 􀀳􀀤􀀚 􀀔􀀔 􀀳􀀥􀀓􀀒􀀶􀀶􀀒􀀤􀀬􀀱􀀓 􀀗 􀀳􀀥􀀔􀀒􀀶􀀦􀀮􀀒􀀤􀀬􀀱􀀔 􀀘 􀀳􀀥􀀕􀀒􀀰􀀬􀀶􀀲􀀒􀀤􀀬􀀱􀀕 􀀙 􀀳􀀥􀀖􀀒􀀰􀀲􀀶􀀬􀀒􀀤􀀬􀀱􀀖 􀀚 􀀳􀀥􀀗􀀒􀀦􀀯􀀮􀀬􀀱􀀒􀀤􀀬􀀱􀀗 􀀛 􀀳􀀥􀀘􀀒􀀤􀀬􀀱􀀘 􀀜 􀀳􀀥􀀙􀀒􀀤􀀬􀀱􀀙 􀀔􀀓 􀀵􀀕􀀓 􀀔􀀕􀀃􀀒􀀓􀀑􀀕􀀘􀀺 􀀵􀀔􀀓􀀓 􀀔􀀓 􀀸􀀔􀀙 􀀯􀀘􀀜􀀚􀀖􀀧 􀀲􀀸􀀷 􀀔 􀀶􀀼􀀱􀀦 􀀕 􀀬􀀱􀀫 􀀖 􀀦􀀲􀀰􀀳 􀀗 􀀩􀀥 􀀘 􀀹􀀵􀀨􀀩 􀀙 􀀪􀀱􀀧 􀀚 􀀹􀀦􀀦 􀀛 􀀦􀀔􀀗 􀀗􀀚􀁘􀀩􀀃􀀏􀀖􀀘􀀃􀀹􀀃􀀨􀀯􀀨􀀦 􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀔 􀀶􀀷􀀪􀀺􀀔􀀜􀀱􀀦􀀙􀀓􀀺􀀧 􀀵􀀜􀀜 􀀔􀀓 􀀎 􀀦􀀘􀀕 􀀔􀀓􀀓􀁘􀀩􀀃􀀕􀀘􀀹 􀀦􀀖􀀘 􀀖􀀖􀁘􀀩 􀀔 􀀕 􀀴􀀔􀀓 􀀕􀀶􀀧􀀛􀀛􀀕 􀀵􀀛􀀚 􀀔􀀓􀁎 􀀰􀀙 􀀶􀀷􀀳􀀔􀀙􀀓􀀱􀀚􀀘􀀩􀀖 􀀔 􀀕 􀀖 􀀦􀀗􀀔 􀀔􀀓􀀓􀁓 􀀦􀀘􀀚 􀀔􀀓􀀓􀁑 􀀵􀀔􀀓􀀗 􀀔􀀓 􀀵􀀪􀀤􀀷􀀨􀀃􀀬􀀪􀀥􀀷􀀃􀀫􀀬􀀪􀀫􀀃􀀔 􀀔􀀓􀀓 􀀕 􀀧􀀙 􀀔 􀀥􀀤􀀷􀀃􀀗􀀙 􀀵􀀔􀀓􀀕 􀀔􀀓 􀀰􀀕 􀀶􀀷􀀳􀀔􀀙􀀓􀀱􀀚􀀘􀀩􀀖 􀀔 􀀕 􀀖 􀀬􀀪􀀥􀀷􀀃􀀯􀀲􀀺􀀃􀀔 􀀶􀀷􀀪􀀺􀀔􀀜􀀱􀀦􀀙􀀓􀀺􀀧 􀀵􀀛􀀖 􀀖􀀜􀁎 􀀧􀀖 􀀶􀀷􀀷􀀫􀀛􀀵􀀓􀀙 􀀔 􀀕 􀀡􀀭􀀑􀀑􀀑􀀑􀀖􀁖􀀑 AN2794 Schematic description Doc ID 14827 Rev 2 25/39 The PWM modulation of the H-bridge inverter is implemented on an ST7lite39 microcontroller connected to the gate drive circuit composed of two L6386, as shown in the schematic in Figure 11. The auxiliary power supply section consists of an L5973D and an L7805, used to implement a buck-boost converter to decrease the battery voltage from 24 V to 15 V and from 15 V to 5 V respectively. Experimental results AN2794 26/39 Doc ID 14827 Rev 2 4 Experimental results Typical voltage and current waveforms of the DC-AC converter and the efficiency curves of the push-pull DC-DC stage, measured at different input voltages, are shown below. In particular, Figure 12 and Figure 13 show both input and output characteristic waveforms of the DC-DC converter both in light load and full load condition. The HF transformer leakage inductance, which is about 1% of the magnetizing inductance, is the cause of severe ringing across the input and the output power devices. MOSFETs voltage and current waveforms with and without the connection of a snubber network are shown in Figure 14 and 15, while Figure 16 and 17 show the effect of the RCD clamp circuit connected across the rectifier bridge output. In Figure 18 the current and the voltage across one of the three parallel-connected MOSFETs, powering each of the two windings of the transformer are shown, while in Figure 19 it is possible to observe the variation of the inverter output voltage and current together with the DC-DC converter bus voltage. In Figure 20, 21, 22, 23 and 24, the efficiency curves of the push-pull converter measured with an RL load are given. A maximum efficiency above 93% has been measured at nominal input voltage and 640 W output power. The minimum value of efficiency has been tested under low load and maximum input voltage. In Figure 25, the efficiency of the whole board is shown. The efficiency tests have been carried out connecting an RL load at the inverter output connectors, with 3 mH output inductor. Figure 12. Characteristic waveforms (measured at 24 V input voltage and 280 W resistive load) Figure 13. Characteristic waveforms (measured at 28 V input voltage and 1000 W resistive load) Ch1 and Ch2: MOSFETs drain source voltage; Ch4: HF transformer output voltage; Ch3: filter inductor current Ch1 and Ch2: MOSFETs drain source voltage; Ch3: filter inductor current AN2794 Experimental results Doc ID 14827 Rev 2 27/39 Figure 14. MOSFET voltage (ch4) and current (ch3) without RC snubber Figure 15. MOSFET voltage (ch4) and current (ch3) with RC snubber Figure 16. Rectifier diode current (ch3) and voltage (ch4) without RDC snubber Figure 17. Rectifier diode current (ch3) and voltage (ch4) with RDC snubber Experimental results AN2794 28/39 Doc ID 14827 Rev 2 Figure 18. Ch1, ch3 MOSFETs drain current, ch2, ch4 MOSFET drain-source voltage Figure 19. Startup, ch2, ch3 inverter voltage and current, ch4 DC bus voltage Figure 20. DC-DC converter efficiency with 20 V input Figure 21. DC-DC converter efficiency with 22 V input Figure 22. DC-DC converter efficiency with 24 V input Figure 23. DC-DC converter efficiency with 26 V input 0.8 0.85 0.9 0.95 1 0 200 400 600 800 1000 1200 Output Power [W] Efficiency AM00636v1 0.8 0.85 0.9 0.95 1 0 200 400 600 800 1000 1200 Output Power [W] Efficiency AM00637v1 0.8 0.85 0.9 0.95 1 0 200 400 600 800 1000 1200 Output Power [W] Efficiency AM00638v1 0.8 0.85 0.9 0.95 1 0 200 400 600 800 1000 1200 Output Power [W] Efficiency AM00639v1 AN2794 Experimental results Doc ID 14827 Rev 2 29/39 Figure 24. DC-DC converter efficiency with 28 V input Figure 25. Converter efficiency 0.75 0.8 0.85 0.9 0.95 0 200 400 600 800 1000 1200 Output Power [W] Efficiency AM00640v1 87 88 89 90 91 92 93 0 200 400 600 800 1000 Output Power [W] Effciency % AM00641v1 Conclusion AN2794 30/39 Doc ID 14827 Rev 2 5 Conclusion The theoretical analysis, design and implementation of a DC-AC converter, consisting of a push-pull DC-DC stage and a full-bridge inverter circuit, have been evaluated. Due to the use of the parallel connection of three STP160N75F3 MOSFETs the converter shows good performance in terms of efficiency. Moreover the use of an ST7lite39 8-bit microcontroller allows achieving simple control of the IGBTs used to implement the DC-AC stage. Any additional feature, such as regulation of the AC output voltage or protection requirements, can simply be achieved with firmware development. 6 Bibliography 1. Power Electronics: Converters, Applications and Design 2. Transformer and Inductor Design Handbook, Second Edition 3. Magnetic Core Selection for Transformers and Inductors, Second Edition 4. Switching Power Supply Design. New York. AN2794 Component list Doc ID 14827 Rev 2 31/39 Appendix A Component list Table 7. Bill of material (BOM) Component Part value Description Supplier Cs1 100 nF, 630 V Polip. cap., MKP series EPCOS Cs2 100 nF, 630 V Polip. cap., MKP series EPCOS C1 100 nF, 50 V X7R ceramic cap.., B37987 series EPCOS C2 100 nF, 50 V X7R ceramic cap., B37987 series EPCOS C57 100 nF, 50 V X7R ceramic cap., B37987 series EPCOS C59 100 nF, 50 V X7R ceramic cap., B37987 series EPCOS C10 47 μF, 35 V SMD tantalum capacitor TAJ series AVX C11 4.7 nF, 25 V SMD multilayer ceramic capacitor muRata C12 100 μF, 25 V SMD X7R ceramic cap. C3225 series; size 1210 TDK C14 47 μF, 35 V SMD tantalum capacitor TAJ series AVX C16 100 pF, 25 V SMD multilayer ceramic capacitor muRata C41 100 pF, 50 V General purpose ceramic cap., radial AVX C17 680 nF, 25 V SMD multilayer ceramic capacitor muRata C18 22 μF, 25 V Electrolytic cap FC series Panasonic C19 22 μF, 25 V Electrolytic cap. FC series Panasonic C26 2.2 μF, 25 V X7R ceramic cap., B37984 series EPCOS C31 2.2 μF, 25 V X7R ceramic cap., B37984 series EPCOS C28 470 nF, 25 V X7R ceramic cap., B37984 series EPCOS C33 470 nF, 25 V X7R ceramic cap., B37984 series EPCOS C34 33 μF, 450 V Electrolytic cap. B43821 series EPCOS C35 33 μF, 450 V Electrolytic cap. B43821 series EPCOS C37 3900 μF, 35 V Elec. capacitor 0.012 Ω, YXH series Rubycon C38 3900 μF, 35 V Elec. capacitor 0.012 Ω, YXH series Rubycon C39 150 μF, 35 V Electrolytic cap. fc series Panasonic C40 22 nF, 50 V General purpose ceramic cap., radial AVX C42 100 μF, 25 V Electrolytic cap. fc series Panasonic C51 100 μF, 25 V Electrolytic cap.fc series Panasonic C52 100 μF, 25 V Electrolytic cap.fc series Panasonic C53 2.2 μF, 450 V Elcrolytic capactor B43851 series EPCOS C54 4.7 nF, 100 V Polip. cap., MKT series EPCOS C55 4.7 nF, 100 V Polip. cap., MKT series EPCOS C56 470 nF, 50 V X7R ceramic cap., B37984 series EPCOS Component list AN2794 32/39 Doc ID 14827 Rev 2 C58 0.33 μF, 50 V X7R ceramic cap., B37984 series EPCOS C60 150 nF, 50 V SMD multilayer ceramic capacitor muRata D1 STTH8R06D Ultrafast high voltage rectifier; TO-220AC STMicroelectronics D2 STTH8R06 D Ultrafast high voltage rectifier; TO-220AC STMicroelectronics D3 STTH8R06 D Ultrafast high voltage rectifier; TO-220AC STMicroelectronics D4 STTH8R06 D Ultrafast high voltage rectifier; TO-220AC STMicroelectronics D13 STTH8R06 D Ultrafast high voltage rectifier; TO-220AC STMicroelectronics D5 BAT46 Small signal Schottky diode; SOD-123 STMicroelectronics D6 BAT46 Small signal Schottky diode; SOD-123 STMicroelectronics D8 BAT46 Small signal Schottky diode; SOD-123 STMicroelectronics D7 BAT46 Small signal Schottky diode; SOD-123 STMicroelectronics D9 STTH1L06 Ultrafast high voltage rectifier; DO-41 STMicroelectronics D10 STTH1L06 Ultrafast high voltage rectifier; DO-41 STMicroelectronics D11 1N5821 Schottky rectifier; DO-221AD STMicroelectronics D12 1N5821 Schottky rectifier; DO-221AD STMicroelectronics VOUT AC 1 CON1 FASTON RS components VOUT AC 2 CON1 FASTON RS components VOUT - CON1 FASTON RS components VOUT + CON1 FASTON RS components VIN CON1 FASTON RS components GND CON1 FASTON RS components IC1 L6386D High-voltage high and low side driver; dip-14 STMicroelectronics IC2 L6386D High-voltage high and low side driver; dip-14 STMicroelectronics IGBT LOW 1 STGW19NC60WD N-channel 19 A - 600 V TO-247 PowerMESH™ IGBT STMicroelectronics IGBT HIGH 1 STGW19NC60WD N-channel 19 A - 600 V TO-247 PowerMESH™ IGBT STMicroelectronics IGBT LOW 2 STGW19NC60WD N-channel 19 A - 600 V TO-247 PowerMESH™ IGBT STMicroelectronics IGBT HIGH 2 STGW19NC60WD N-channel 19 A - 600 V TO-247 PowerMESH™ IGBT STMicroelectronics J1 CON10 10-way idc connector commercial box header series Tyco Electronics L3 150 μH, 3 A Power use SMD inductor; SLF12575T series TDK L4(1) 1174.0018 ST04 1.5 mH, filter inductor MAGNETICA M1 STP160N75F3 N-channel 75 V - 3.5 mΩ 120 A TO-220 STripFET™ Power MOSFET STMicroelectronics M2 STP160N75F3 N-channel 75 V - 3.5 mΩ 120 A TO-220 STripFET™ Power MOSFET STMicroelectronics M3 STP160N75F3 N-channel 75 V - 3.5 mΩ 120 A TO-220 STripFET™ Power MOSFET STMicroelectronics Table 7. Bill of material (BOM) (continued) Component Part value Description Supplier AN2794 Component list Doc ID 14827 Rev 2 33/39 M4 STP160N75F3 N-channel 75 V - 3.5 mΩ 120 A TO-220 STripFET™ Power MOSFET STMicroelectronics M5 STP160N75F3 N-channel 75 V - 3.5 mΩ 120 A TO-220 STripFET™ Power MOSFET STMicroelectronics M6 STP160N75F3 N-channel 75 V - 3.5 mΩ 120 A TO-220 STripFET™ Power MOSFET STMicroelectronics Q8 STN4NF03L N-channel 30 V , 6.5 A SOT-223 STripFET™ II Power MOSFET STMicroelectronics Q9 2SD882 NPN Power BJT 30 V, 3 A transistor- SOT-32 STMicroelectronics Q10 2SD882 NPN Power BJT 30 V, 3 A transistor- SOT-32 STMicroelectronics Q11 2SB772 NPN Power BJT 30 V, 3 A transistor - SOT-32 STMicroelectronics Q12 2SB772 NPN Power BJT 30 V, 3 A transistor - SOT-32 STMicroelectronics RGATE IGBT LOW 1 100 SMD standard film res - 1/8 W - 1% - 100 ppm/°C BC components RGATE IGBT HIGH 1 100 SMD standard film res - 1/8 W - 1% - 100 ppm/°C BC components RGATE IGBT LOW 2 100 SMD standard film res - 1/8 W - 1% - 100 ppm/°C BC components RGATE IGBT HIGH 2 100 SMD standard film res - 1/8 W - 1% - 100 ppm/°C BC components R7 390 kΩ SMD standard film res - 1/8 W - 1% - 100 ppm/°C BC components R9 5.6 kΩ SMD standard film res - 1/8 W - 1% - 100 ppm/°C BC components R20 12 Ω SMD standard film res - 1/8 W - 1% - 100 ppm/°C BC components R21 R22 10 Ω SMD standard film res - 1/8 W - 1% - 100 ppm/°C BC components R23 R24 R25 R99 R100 R101 R102 R103 R104 R81 22 kΩ Standard film res - 1/4 W 5%, axial 05 T-Ohm R82 3.3 kΩ Standard film res - 1/4 W 5%, axial 05 T-Ohm R83 39 kΩ Standard film res - 1/4 W 5%, axial 05 T-Ohm R87 10 kΩ SMD standard film res - 1/8 W - 1% - 100ppm/°C BC components Table 7. Bill of material (BOM) (continued) Component Part value Description Supplier Component list AN2794 34/39 Doc ID 14827 Rev 2 R88 10 kΩ SMD standard film res - 1/8 W - 1% - 100ppm/°C BC components R89 R90 R91 R92 R93 1.5 kΩ SMD standard film res - 1/8 W – 1% - 100ppm/°C BC components R94 470 Ω High voltage 17 W ceramic resistor sbcv type Meggit CGS R95 470 Ω High voltage 17 W ceramic resistor sbcv type Meggit CGS R96 10 Ω Standard film res – 2 W 5%, axial 05 T-Ohm R97 R98 47 kΩ Standard film res - 1/4 W 5%, axial 05 T-Ohm TX1(2) 1356.0004 rev.01 Power transformer MAGNETICA U1 SG3525 Pulse width modulator SO-16 (narrow) STMicroelectronics U16 L5973D 2.5 A switch step down regulator; HSOP8 STMicroelectronics U17 ST7FLITE39F2 8-bit microcontroller; SO-20 STMicroelectronics U20 L7805 Positive voltage regulator; D2PAK STMicroelectronics 124 HEAT SINK Part n. 78185, S562 cooled package TO-220; thermal res. 7.52 °C/W at length 70 mm width 40 mm height 57 mm Aavid Thermalloy 125 HEAT SINK Part n. 78350, SA36 cooled package TO-220; thermal res. 1.2°C/W at length 135 mm width 49.5 mm height 85.5 mm Aavid Thermalloy 126 1. The technical specification for this component is provided in Figure 26. 2. The technical specification for this component is provided in Figure 27. Table 7. Bill of material (BOM) (continued) Component Part value Description Supplier AN2794 Product technical specification Doc ID 14827 Rev 2 35/39 Appendix B Product technical specification Figure 26. Technical specification for 1.5 mH 2.5 A inductor L4 (produced by MAGNETICA) TYPICAL APPLICATION INDUCTOR FOR DC/DC CONVERTERS AS BUCK, BOOST E BUCK-BOOST CONVERTERS. ALSO SUITABLE IN HALFBRIDGE, PUSH-PULL AND FULL-BRIDGE APPLICATIONS TECHNICAL DATA INDUCTANCE 1.5mH ±15% (MEASURE 1KHZ, TA 20°C) RESISTANCE 0.52 max (MEASURE DC, TA 20°C) OPERATING VOLTAGE 800 VP MAX (F 100K HZ, IR 2.5A, TA 20°C) OPERATING VOLTAGE 2.5 A MAX (MEASURE DC 800 VP, TA 20°C) SATURATION CURRENT 4.5 A NOM (MEASURE DC, L 50%NOM, TA 20°C) SELF-RESONANT FREQUENY 1MHZ NOM (TA 20°C) OPERATING TEMPERATURE RANGE -10°C÷+45°C (IR 2.5 A MAX) DIMENSIONS 45X20 H46mm WEIGHT 78g CIRCA SCHEMATIC INDUCTANCE VS CURRENT INDUCTANCE VS FREQUENCY DIMENSIONAL DRAWING DIMENSIONS IN MM, DRAWING NOT IN SCALE 1 3 10% 100% 0 1 2 3 4 5 6 L I [A] 0% 50% 100% 150% 200% 250% 0 200 400 600 800 1000 L/L(1kHz) f [kHz] 1 2 2 3 3 min 1 45 max 46 max 20 max 0.8 (X4), RECOMMENDED PCB HOLE 1.2 (X4) 2 3 4 BOTTOM VIEW (PIN SIDE) 12.7 10.16 30.48 Product technical specification AN2794 36/39 Doc ID 14827 Rev 2 Figure 27. Technical specification for 1 kW, 100 kHz switch mode power transformer TX1 (produced by MAGNETICA) TYPICAL APPLICATION TRANSFORMER TO POWER APPLICATIONS WITH HALF - BRIDGE , PUSH -PULL E FULL -BRIDGE TYPOLOGY . TECHNICAL DATA INDUCTANCE (MEASURE 1KHZ, TA 20°C) PIN 1,2 – 3,4,5 17.2 uH MIN PIN 3,4,5 – 6,7 17.2 uH MIN PIN 9 – 13 (10-12 IN CC ) 5.7 mH MIN R ESISTANCE (MEASURE D .C, TA 20°C) PIN 1,2 – 3,4,5 6 mΩ MAX PIN 3,4,5 – 6,7 6 mΩ MAX PIN 9 – 13 (10-12 IN CC ) 90 mΩ MAX TRANSFORMER RATIO (MEASURE 10KHZ, 10-12 IN CC , TA 20°C) PIN 13 – 9 ⇔ 1,2 – 3,4,5 18 ± 5% PIN 13 – 9 ⇔ 3,4,5 – 6,7 18 ± 5% L EAKAGE INDUCTANCE 0.11 % NOM (MEASURE 9-13, 1-2-3-4-5-6-7 AND 10-12 IN C .C, F 10KHZ, TA 20°C) OPERATING VOLTAGE 800 VP MAX (MEASURE 13-9, 10-12 IN CC , F 100KHZ , DUTY CYCLE 0.8,T A 20°C) OPERATING CURRENT 2.5 A MAX (MEASURE 13-9 WITH 1-2-3-4-5-6-7 IN CC , PMAX 1KW ,F 100 KHZ, TA 20°C) OPERATING FREQUENCY 100KHZ NOM (P MAX 1KW , TA 20°C) OPERATING TEMPERATURE RANGE -10°C ÷+45°C (P MAX 1KW, F 100KHZ ) INSULATION CLASS I ( PMAX 1KW, TA 20°C ) P RIMARY TO SECONDARY INSULATION 2500V (F 50H Z,DURATION TEST 2”, TA 20°C) MAXIMUM DIMENSIONS 57X57H45 mm WEIGHT 292g CIRCA SCHEMATIC PRODUCT PICTURE PIN DESCRIPTION PIN (*) FUNCTION PIN (*) FUNCTION 1A P RIMARY DRAIN A 8 NOT USED 2A P RIMARY DRAIN A 9 SECONDARY GROUND 3B PRIMARY +VB 24V 10D INTERMEDIARY S ECONDARY ACCESS 4B 11 MISSING , REFERENCE TO PCB ASSEMBLING 5B 12D INTERMEDIARY S ECONDARY ACCESS 6C P RIMARY DRAIN B 13 S ECONDARY 400V 2.5A 7C P RIMARY DRAIN B 14 NOT USED (*)P IN WITH THE SAME SUBSCRIPT MU ST BE CONNECTED TOGETHER ON PCB 13 12 1 2 3 4 5 6 7 10 9 AN2794 Product technical specification Doc ID 14827 Rev 2 37/39 Figure 28. Dimensional drawing 7 8 55.5 max 3 min ı 1.0, Recommended PCB hole ı 1.4 56.5 max 14 13 12 4 10 9 8 1356.0004 SMT 1kW 100kHz MAGNETICA 08149 BOTTOM VIEW (PIN SIDE ) 40 5 1 7 8 14 MISSING PIN REFERENCE AS PCB ASSEMBLING Revision history AN2794 38/39 Doc ID 14827 Rev 2 7 Revision history Table 8. Document revision history Date Revision Changes 16-Feb-2009 1 Initial release 13-Jan-2012 2 – Introduction modified – Section 3 modified AN2794 Doc ID 14827 Rev 2 39/39 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2012 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com STEVAL-TDR027V1 Portable UHF 2-way radio demonstration board based on the PD84008L-E Features ■ Excellent thermal stability ■ Frequency: 380 - 512 MHz ■ Supply voltage: 7.2 V ■ Output power: > 6 W ■ Power gain: 11.7 ± 0.5 dB ■ Efficiency: 46% - 71% ■ Load mismatch: 20:1 all phases ■ BeO-free amplifier Description The STEVAL-TDR027V1 demonstration board is a portable UHF 2-way radio designed as a platform for evaluating the performance of the PD84008L-E LDMOS RF power transistor. Table 1. Device summary Part number STEVAL-TDR027V1 Mechanical specification: L = 60 mm, W = 30 mm www.st.com Contents STEVAL-TDR027V1 2/11 Doc ID 18109 Rev 1 Contents 1 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Typical performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Circuit photo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 STEVAL-TDR027V1 Electrical characteristics Doc ID 18109 Rev 1 3/11 1 Electrical characteristics TA = +25 oC, VDD = 7.2 V, Idq = 200 mA Table 2. Electrical specification Symbol Test conditions Min Typ Max Unit Freq Frequency range 380 512 MHz POUT @ PIN = 27 dBm 6 W Gain @ PIN = 27 dBm 11.7 ± 0.5 dB ND @ PIN = 27 dB 46 - 71 % H2 2nd harmonic @ PIN = 27 dB -38 / -70 dBc H3 3rd harmonic @ PIN = 27 dB -60 / -70 dBc VSWR Load mismatch all phases @ POUT = 6 W 20:1 Impedance STEVAL-TDR027V1 4/11 Doc ID 18109 Rev 1 2 Impedance Figure 1. Impedance diagram Table 3. Impedance data F (MHz) ZGS ZDL 380 3,3 + j6,2 2,2 - j0,7 390 3,6 + j6,7 2,2 - j0,4 400 4,1 + j7,1 2,2 - j0,1 410 4,6 + j7,4 2,2 + j0,2 420 5,3 + j7,5 2,2 + j0,5 430 6,2 + j7,3 2,3 + j0,8 440 6,8 + j6,6 2,4 + j1,0 450 7,0 + j5,4 2,4 + j1,3 460 6,4 + j4,2 2,6 + j1,5 470 5,2 + j3,6 2,7 + j1,6 480 3,9 + j3,7 2,8 + j1,7 490 2,8 + j4,2 2,9 + j1,8 500 2,1 + j4,9 3,0 + j1,9 510 1,6 + j5,6 3,1 + j1,8 520 1,3 + j6,3 3,2 + j1,7 STEVAL-TDR027V1 Typical performance Doc ID 18109 Rev 1 5/11 3 Typical performance Figure 2. Output power and efficiency vs. frequency (pin=27 dBm) Figure 3. Output power and efficiency vs. frequency (pin=28 dBm) Figure 4. Gain vs. frequency Figure 5. Gain vs. Pout Fig Typical performance STEVAL-TDR027V1 6/11 Doc ID 18109 Rev 1 Figure 8. Harmonics vs. frequency 􀀫􀀕 􀀫􀀖 􀀡􀀭􀀐􀀖􀀐􀀑􀀖􀁖􀀑 STEVAL-TDR027V1 Test circuit Doc ID 18109 Rev 1 7/11 4 Test circuit Figure 9. Test circuit schematic diagram + TL5 TL6 C12 C13 RFout C11 L4 C10 L3 C9 C6 RFin TL1 TL2 C8 PD84008L-E LDMOS R2 R1 R3 C7 L2 L1 C2 C1 Vcc 2 - 1 + B2 C3 C4 C5 TL4 TL3 D1 FR4 H=60 mil MSub B1 Table 4. Component list Component ID Description Value Case size Manufacturer Part code B1 Ferrite bead Panasonic EXCELDRC35C B2 Panasonic EXCELDRC35C C1, C2 Capacitor 120 pF 1206 MURATA GRM42-6 COG 121J 50_ C3 1 nF 1206 MURATA GRM42-6 COG 102J 50 C4 100 nF 1206 MURATA GRM42-6_X7R 104K 50_ C5 10 uF SMT Panasonic EEVHB1V100P C6, C13 33 pF 100B ATC ATC 100B 330JW C7 22 pF 100B ATC ATC 100B 220JW C8 47 pF 100B ATC ATC 100B 470JW C9 39 pF 100B ATC ATC 100B 390JW C10 15 pF 100B ATC ATC 100B 150JW C11 6.8 pF 100B ATC ATC 100B 6R8BW C12 2.2 pF 100B ATC ATC 100B 2R2BW D1 Zener diode 5.1 V SOD110 Philips BZX284C5V1 L1 Inductor 18.5 nH Coilcraft A05T L2 5 nH Coilcraft A02T L3, L4 2.5 nH Coilcraft A01T R1 Resistor 1 kΩ 1206 Tyco Electronics 01623440-1 Test circuit STEVAL-TDR027V1 8/11 Doc ID 18109 Rev 1 R2 Potentiometer 10 kΩ Bourns Electronics 3214W-1-103E R3 Resistor 560 Ω 1206 Bourns Electronics TL1 Transmission line W=2.87 mm L=7.4 mm TL2 W=2.87 mm L=5.0 mm TL3 W=4.98 mm L=4.8 mm TL4 W=4.98 mm L=4.0 mm TL5 W=2.87 mm L=1.5 mm TL6 W=2.87 mm L=6.1 mm PD84008L LDMOS STMicroelectronics PD84008L-E Board FR-4 THk=0.060" 2OZ Cu both sides Table 4. Component list (continued) Component ID Description Value Case size Manufacturer Part code STEVAL-TDR027V1 Board photo Doc ID 18109 Rev 1 9/11 5 Board photo Figure 10. STEVAL-TDR027V1 demonstration board Revision history STEVAL-TDR027V1 10/11 Doc ID 18109 Rev 1 6 Revision history Updated Table 5. Document revision history Date Revision Changes 18-Oct-2010 1 Initial release. STEVAL-TDR027V1 Doc ID 18109 Rev 1 11/11 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com L6384E High voltage half-bridge driver Datasheet - production data Features  High voltage rail up to 600 V  dV/dt immunity ± 50 V/nsec in full temperature range  Driver current capability – 400 mA source – 650 mA sink  Switching times 50/30 nsec rise/fall with 1 nF load  CMOS/TTL Schmitt trigger inputs with hysteresis and pull-down  Shutdown input  Deadtime setting  Undervoltage lockout  Integrated bootstrap diode  Clamping on VCC  Available in DIP-8/SO-8 packages Applications  Home appliances  Induction heating  HVAC  Industrial applications and drives  Motor drivers – DC, AC, PMDC and PMAC motors  Lighting applications  Factory automation  Power supply systems Description The L6384E is a high voltage gate driver, manufactured with the BCD™ “offline” technology, and able to drive a half-bridge of power MOS or IGBT devices. The high-side (floating) section is enabled to work with voltage rail up to 600 V. Both device outputs can sink and source 650 mA and 400 mA respectively and cannot be simultaneously driven high thanks to an integrated interlocking function. Further prevention from outputs cross conduction is guaranteed by the deadtime function, tunable by the user through an external resistor connected to the DT/SD pin. The L6384E device has one input pin, one enable pin (DT/SD) and two output pins, and guarantees matched delays between low-side and high-side sections, thus simplifying device's high frequency operation. The logic inputs are CMOS/TTL compatible to ease the interfacing with controlling devices. The bootstrap diode is integrated inside the device, allowing a more compact and reliable solution. The L6384E features the UVLO protection and a voltage clamp on the VCC supply voltage. The voltage clamp is typically around 15.6 V and is useful in order to ensure a correct device functioning in cases where VCC supply voltage is ramped up too slowly or is subject to voltage drops. The device is available in a DIP-8 tube and SO-8 tube and tape and reel packaging options. DIP-8 SO-8 Table 1. Device summary Part number Package Packaging L6384E DIP-8 Tube L6384ED SO-8 Tube L6384ED013TR SO-8 Tape and reel www.st.com Contents L6384E 2/15 DocID13862 Rev 2 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 Typical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DocID13862 Rev 2 3/15 L6384E Block diagram 15 1 Block diagram Figure 1. Block diagram LOGIC UV DETECTION LEVEL SHIFTER R S VCC LVG DRIVER VCC IN DT/SD VBOOT HVG DRIVER HVG H.V. LOAD OUT LVG GND D97IN518A DEAD TIME VCC Idt Vthi BOOTSTRAP DRIVER CBOOT 4 3 5 6 7 8 1 2 Electrical data L6384E 4/15 DocID13862 Rev 2 2 Electrical data 2.1 Absolute maximum ratings 2.2 Thermal data 2.3 Recommended operating conditions Table 2. Absolute maximum ratings Symbol Parameter Value Unit Vout Output voltage -3 to Vboot -18 V Vcc Supply voltage(1) 1. The device has an internal clamping Zener between GND and the Vcc pin, It must not be supplied by a low impedance voltage source. - 0.3 to 14.6 V Is Supply current(1) 25 mA Vboot Floating supply voltage -1 to 618 V Vhvg High-side gate output voltage -1 to Vboot V Vlvg Low-side gate output voltage -0.3 to Vcc +0.3 V Vi Logic input voltage -0.3 to Vcc +0.3 V Vsd Shutdown/deadtime voltage -0.3 to Vcc +0.3 V dVout/dt Allowed output slew rate 50 V/ns Ptot Total power dissipation (Tj = 85 °C) 750 mW TJ Junction temperature 150 °C Ts Storage temperature -50 to 150 °C Table 3. Thermal data Symbol Parameter SO-8 DIP-8 Unit Rth(JA) Thermal resistance junction to ambient 150 100 °C/W Table 4. Recommended operating conditions Symbol Pin Parameter Test condition Min. Typ. Max. Unit Vout 6 Output voltage (1) 1. If the condition Vboot - Vout < 18 V is guaranteed, Vout can range from -3 to 580 V. 580 V VBS (2) 2. VBS = Vboot - Vout. 8 Floating supply voltage (1) 17 V fsw Switching frequency HVG, LVG load CL = 1 nF 400 kHz Vcc 2 Supply voltage Vclamp V Tj Junction temperature -45 125 °C DocID13862 Rev 2 5/15 L6384E Pin connection 15 3 Pin connection Figure 2. Pin connection (top view) IN VCC DT/SD GND 1 3 2 4 LVG VOUT HVG 8 VBOOT 7 6 5 D97IN519 Table 5. Pin description No. Pin Type Function 1 IN I Logic input: it is in phase with HVG and in opposition of phase with LVG. It is compatible to VCC voltage. (Vil Max = 1.5 V, Vih Min = 3.6 V). 2 VCC P Supply input voltage: there is an internal clamp [typ. 15.6 V]. 3 DT/SD I High impedance pin with two functionalities. When pulled lower than Vdt (typ. 0.5 V), the device is shut down. A voltage higher than Vdt sets the deadtime between the high-side gate driver and low-side gate driver. The deadtime value can be set forcing a certain voltage level on the pin or connecting a resistor between the pin 3 and ground. Care must be taken to avoid below threshold spikes on the pin 3 that can cause undesired shutdown of the IC. For this reason the connection of the components between the pin 3 and ground has to be as short as possible. This pin can not be left floating for the same reason. The pin has not be pulled through a low impedance to VCC, because of the drop on the current source that feeds Rdt. The operative range is: Vdt … 270 K Idt, that allows a dt range of 0.4 - 3.1 s. 4 GND P Ground 5 LVG O Low-side driver output: the output stage can deliver 400 mA source and 650 mA sink (typ. values). The circuit guarantees 0.3 V max. on the pin (at Isink = 10 mA) with VCC > 3 V and lower than the turn-on threshold. This allows to omit the bleeder resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low; the gate driver ensures low impedance also in SD conditions. 6 Vout P High-side driver floating reference: layout care has to be taken to avoid below ground spikes on this pin. 7 HVG O High-side driver output: the output stage can deliver 400 mA source and 650 mA sink (typ. values). The circuit guarantees 0.3 V max. between this pin and Vout (at Isink = 10 mA) with VCC > 3 V and lower than the turn-on threshold. This allows to omit the bleeder resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low; the gate driver ensures low impedance also in SD conditions. 8 Vboot P Bootstrap supply voltage: it is the high-side driver floating supply. The bootstrap capacitor connected between this pin and the pin 6 can be fed by an internal structure named “bootstrap driver” (a patented structure). This structure can replace the external bootstrap diode. Electrical characteristics L6384E 6/15 DocID13862 Rev 2 4 Electrical characteristics 4.1 AC operation 4.2 DC operation Table 6. AC operation electrical characteristics (VCC = 14.4V; TJ = 25°C) Symbol Pin Parameter Test condition Min. Typ. Max. Unit ton 1 vs. 5, 7 High/low-side driver turn-on propagation delay Vout = 0 V Rdt= 47 k 200+ dt ns tonsd 3 vs. 5, 7 Shutdown input propagation delay 220 280 ns toff 1 vs. 5, 7 High/low-side driver turn-off propagation delay Vout = 0 V Rdt = 47 k 250 300 ns Vout = 0 V Rdt = 146 k 200 250 ns Vout = 0 V Rdt = 270 k 170 200 ns tr 5, 7 Rise time CL = 1000 pF 50 ns tf 5, 7 Fall time CL = 1000 pF 30 ns Table 7. DC operation electrical characteristics (VCC = 14.4 V; TJ = 25 °C) Symbol Pin Parameter Test condition Min. Typ. Max. Unit Supply voltage section Vclamp 2 Supply voltage clamping Is = 5 mA 14.6 15.6 16.6 V Vccth1 2 VCC UV turn-on threshold 11.5 12 12.5 V Vccth2 2 VCC UV turn-off threshold 9.5 10 10.5 V Vcchys VCC UV hysteresis 2 V Iqccu Undervoltage quiescent supply current Vcc 11 V 150 A Iqcc Quiescent current Vin = 0 380 500 A Bootstrapped supply voltage section Vboot 8 Bootstrap supply voltage 17 V IQBS Quiescent current IN = HIGH 100 A ILK High voltage leakage current Vhvg = Vout = Vboot = 600 V 10 A Rdson Bootstrap driver on-resistance(1) Vcc 12.5 V; IN = LOW 125  High/low-side driver Iso 5, 7 Source short-circuit current VIN = Vih (tp < 10 s) 300 400 mA Isi Sink short-circuit current VIN = Vil (tp < 10 s) 500 650 mA DocID13862 Rev 2 7/15 L6384E Electrical characteristics 15 4.3 Timing diagram Figure 3. Input/output timing diagram Symbol Pin Parameter Test condition Min. Typ. Max. Unit Logic inputs Vil 1, 3 Low level logic threshold voltage 1.5 V Vih High level logic threshold voltage 3.6 V Iih High level logic input current VIN = 15 V 50 70 A Iil Low level logic input current VIN = 0 V 1 A Iref 3 Deadtime setting current 28 A dt 3 vs. 5, 7 Deadtime setting range(2) Rdt = 47 k Rdt = 146 k Rdt = 270 k 0.4 0.5 1.5 2.7 3.1 s s s Vdt 3 Shutdown threshold 0.5 V 1. RDS(on) is tested in the following way: Where I1 is the pin 8 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2. 2. The pin 3 is a high impedance pin. Therefore dt can be set also forcing a certain voltage V3 on this pin. The deadtime is the same obtained with an Rdt if it is: Rdt × Iref = V3. Table 7. DC operation electrical characteristics (continued)(VCC = 14.4 V; TJ = 25 °C) RDSON VCC – VCBOOT1 – VCC – VCBOOT2 = I--1------V----C----C---,--V-----C---B----O----O----T---1-------–----I--2-----V-----C---C----,--V----C----B----O----O----T---2---- IN SD HVG LVG D99IN1017 Bootstrap driver L6384E 8/15 DocID13862 Rev 2 5 Bootstrap driver A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (Figure 4 a). In the L6384E device a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low-side driver (LVG), with a diode in series, as shown in Figure 4 b. An internal charge pump (Figure 4 b) provides the DMOS driving voltage. The diode connected in series to the DMOS has been added to avoid undesirable turn-on. CBOOT selection and charging To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge: Equation 1 The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss. It has to be: CBOOT>>>CEXT E.g.: if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop would be 300 mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage losses. E.g.: HVG steady state consumption is lower than 100 A, so if HVG TON is 5 ms, CBOOT has to supply 0.5 C to CEXT. This charge on a 1 F capacitor means a voltage drop of 0.5 V. The internal bootstrap driver gives great advantages: the external fast recovery diode can be avoided (it usually has a great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge ) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value: 125 ). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account. The following equation is useful to compute the drop on the bootstrap DMOS: Equation 2 where Qgate is the gate charge of the external power MOS, Rdson is the on-resistance of the bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor. CEXT Qgate Vgate = -------------- Vdrop Ich argeRdson  Vdrop Qgate Tch arge = = -------------------Rdson DocID13862 Rev 2 9/15 L6384E Bootstrap driver 15 For example: using a power MOS with a total gate charge of 30 nC, the drop on the bootstrap DMOS is about 1 V, if the Tcharge is 5 s. In fact: Equation 3 Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode can be used. Figure 4. Bootstrap driver Vdrop 30nC 5s = --------------  125  0.8V TO LOAD D99IN1067 H.V. HVG a b LVG HVG LVG CBOOT TO LOAD H.V. CBOOT DBOOT VS VBOOT VS VOUT VBOOT VOUT Typical characteristic L6384E 10/15 DocID13862 Rev 2 6 Typical characteristic Figure 5. Typical rise and fall times vs. load capacitance Figure 6. Quiescent current vs. supply voltage Figure 7. Deadtime vs. resistance Figure 8. Driver propagation delay vs. temperature Figure 9. Deadtime vs. temperature Figure 10. Shutdown threshold vs. temperature For both high and low side buffers @25°C Tamb 0 1 2 3 4 5 C (nF) 0 50 100 150 200 250 time (nsec) Tr D99IN1015 Tf 0 2 4 6 8 10 12 14 VS(V) 10 102 103 104 Iq (μA) D99IN1016 50 100 150 200 250 300 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 dt (s) Rdt (k) Typ. @ Vcc = 14.4V -45 -25 0 25 50 75 100 125 0 100 200 300 400 Ton,Toff (ns) @ Rdt = 47kOhm @ Rdt = 146kOhm @ Rdt = 270kOhm Tj (°C) Typ. Typ. Typ. @ Vcc = 14.4V -45 -25 0 25 50 75 100 125 Tj (°C) 0 0.5 1 1.5 2 2.5 3 dt (s) R=47K R=146K Typ. R=270K Typ. Typ. @ Vcc = 14.4V -45 -25 0 25 50 75 100 125 0 0.2 0.4 0.6 0.8 1 Vdt (V) Tj (°C) Typ. @ Vcc = 14.4V DocID13862 Rev 2 11/15 L6384E Typical characteristic 15 Figure 11. VCC UV turn-on vs. temperature Figure 12. Output source current vs. temperature Figure 13. VCC UV turn-off vs. temperature Figure 14. Output sink current vs. temperature -45 -25 0 25 50 75 100 125 10 11 12 13 14 15 Vccth1 (V) Tj (°C) Typ. -45 -25 0 25 50 75 100 125 0 200 400 600 800 1000 Current (mA) Tj (°C) Typ. @ Vcc = 14.4V -45 -25 0 25 50 75 100 125 8 9 10 11 12 13 Vccth2 (V) Tj (°C) Typ. -45 -25 0 25 50 75 100 125 0 200 400 600 800 1000 Current (mA) Tj (°C) Typ. @ Vcc = 14.4V Package information L6384E 12/15 DocID13862 Rev 2 7 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Figure 15. DIP-8 package outline Table 8. DIP-8 package mechanical data Symbol Dimensions (mm) Dimensions (inch) Min. Typ. Max. Min. Typ. Max. A 3.32 0.131 a1 0.51 0.020 B 1.15 1.65 0.045 0.065 b 0.356 0.55 0.014 0.022 b1 0.204 0.304 0.008 0.012 D 10.92 0.430 E 7.95 9.75 0.313 0.384 e 2.54 0.100 e3 7.62 0.300 e4 7.62 0.300 F 6.6 0.260 I 5.08 0.200 L 3.18 3.81 0.125 0.150 Z 1.52 0.060 DocID13862 Rev 2 13/15 L6384E Package information 15 Figure 16. SO-8 package outline Table 9. SO-8 package mechanical data Symbol Dimensions (mm) Dimensions (inch) Min. Typ. Max. Min. Typ. Max. A 1.750 0.0689 A1 0.100 0.250 0.0039 0.0098 A2 1.250 0.0492 b 0.280 0.480 0.0110 0.0189 c 0.170 0.230 0.0067 0.0091 D(1) 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm in total (both sides). 4.800 4.900 5.000 0.1890 0.1929 0.1969 E 5.800 6.000 6.200 0.2283 0.2362 0.2441 E1(2) 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side. 3.800 3.900 4.000 0.1496 0.1535 0.1575 e 1.270 0.0500 h 0.250 0.500 0.0098 0.0197 L 0.400 1.270 0.0157 0.0500 L1 1.040 0.0409 k 0° 8° 0° 8° ccc 0.100 0.0039 􀀤􀀰􀀔􀀔􀀚􀀘􀀚􀁙􀀔 Revision history L6384E 14/15 DocID13862 Rev 2 8 Revision history Table 10. Document revision history Date Revision Changes 12-Oct-2007 1 First release 20-Jun-2014 2 Added Section : Applications on page 1. Updated Section : Description on page 1 (replaced by new description). Updated Table 1: Device summary on page 1 (moved from page 15 to page 1, updated title). Updated Figure 1: Block diagram on page 3 (moved from page 1 to page 3, numbered and added title to Section 1: Block diagram on page 3). Updated Section 2.1: Absolute maximum ratings on page 4 (removed note below Table 2: Absolute maximum ratings). Updated Table 5: Pin description on page 5 (updated “Type” of several pins). Updated Table 7 on page 6 (updated “Max.” value of IQBS symbol). Updated Section : CBOOT selection and charging on page 8 (updated values of “E.g.: HVG”). Numbered Equation 1 on page 8, Equation 2 on page 8 and Equation 3 on page 9. Updated Section 7: Package information on page 12 [updated/added titles, updated ECOPACK text, reversed order of Figure 15 and Table 8, Figure 16 and Table 9 (numbered tables), removed 3D package figures, minor modifications]. Minor modifications throughout document. DocID13862 Rev 2 15/15 L6384E 15 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B) AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2014 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com ULQ2001 ULQ2003 - ULQ2004 Seven Darlington array Features ■ Seven Darlington per package ■ Extended temperature range: -40 to 105 °C ■ Output current 500 mA per driver (600 mA peak) ■ Output voltage 50 V ■ Automotive Grade product in SO16 package ■ Integrated suppression diodes for inductive loads ■ Outputs can be paralleled for higher current ■ TTL/CMOS/PMOS/DTL compatible inputs ■ Inputs pinned opposite outputs to simplify layout Description The ULQ2001, ULQ2003 and ULQ2004 are high voltage, high current Darlington arrays each containing seven open collector Darlington pairs with common emitters. Each channel rated at 500 mA and can withstand peak currents of 600 mA. Suppression diodes are included for inductive load driving and the inputs are pinned opposite the outputs to simplify board layout. The versions interface to all common logic families. These versatile devices are useful for driving a wide range of loads including solenoids, relays DC motors, LED displays filament lamps, thermal print-heads and high power buffers. The ULQ2001A/2003A and 2004A are supplied in 16 pin plastic DIP packages with a copper leadframe to reduce thermal resistance. They are available also in small outline package (SO16) as ULQ2003D1/2004D1. The ULQ2003 is available as Automotive Grade in SO16 package. The commercial part numbers is shown in the order codes. This device is qualified according to the specification AEC-Q100 of the Automotive market, in the temperature range -40 °C to 125 °C and the statistical tests PAT, SYL, SBL are performed. DIP-16 SO16 (Narrow) Table 1. Device summary Part numbers Order codes Description Packages ULQ2001 ULQ2001A General purpose, DTL, TTL, PMOS, CMOS DIP-16 ULQ2003 ULQ2003A 5 V TTL, CMOS DIP-16 ULQ2004 ULQ2004A 6–15 V CMOS, PMOS DIP-16 ULQ2003 ULQ2003D1013TR SO16 in tape and reel ULQ2003 ULQ2003D1013TRY (1) SO16 in tape and reel ULQ2004 ULQ2004D1013TR SO16 in tape and reel 1. Automotive Grade products. www.st.com Contents ULQ2001, ULQ2003, ULQ2004 2/14 Doc ID 1537 Rev 6 Contents 1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ULQ2001, ULQ2003, ULQ2004 Diagram Doc ID 1537 Rev 6 3/14 1 Diagram Figure 1. Schematic diagram ULQ2001 (each driver) ULQ2003 (each driver) ULQ2004 (each driver) Pin configuration ULQ2001, ULQ2003, ULQ2004 4/14 Doc ID 1537 Rev 6 2 Pin configuration Figure 2. Pin connections (top view) ULQ2001, ULQ2003, ULQ2004 Maximum ratings Doc ID 1537 Rev 6 5/14 3 Maximum ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VO Output voltage 50 V VIN Input voltage (for ULQ2003A/D1 - 2004A/D1) 30 V IC Continuous collector current 500 mA IB Continuous base current 25 mA TA Operating ambient temperature range -40 to 105 °C TSTG Storage temperature range -55 to 150 °C TJ Junction temperature 150 °C Table 3. Thermal data Symbol Parameter DIP-16 SO16 Unit RthJA Thermal resistance junction-ambient, max. 70 120 °C/W Electrical characteristics ULQ2001, ULQ2003, ULQ2004 6/14 Doc ID 1537 Rev 6 4 Electrical characteristics TJ = -40 to 105 °C for DIP16 unless otherwise specified, TJ = -25 to 105 °C for SO16 unless otherwise specified. Table 4. Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit ICEX Output leakage current VCE = 50V, (Figure 3) 50 μA TJ = 105°C, VCE= 50V (Figure 3) 100 TJ = 105°C for ULQ2004, VCE= 50V, VI = 1V (Figure 4) 500 VCE(SAT) Collector-emitter saturation voltage (Figure 5) IC = 100mA, IB = 250μA 0.9 1.1 IC = 200mA, IB= 350μA 1.1 1.3 V IC = 350mA, IB= 500μA 1.3 1.6 II(ON) Input current (Figure 6) for ULQ2003, VI = 3.85V 0.93 1.35 for ULQ2004, VI = 5V 0.35 0.5 mA for ULQ2004, VI = 12V 1 1.45 II(OFF) Input current (Figure 7) TJ = 105°C, IC = 500μA 50 65 μA VI(ON) Input voltage (Figure 8) for ULQ2003 VCE= 2V, IC = 200mA VCE= 2V, IC = 250mA VCE= 2V, IC = 300mA for ULQ2004 VCE= 2V, IC = 125mA VCE= 2V, IC = 200mA VCE= 2V, IC = 275mA VCE= 2V, IC = 350mA 2.4 2.7 3 5 6 7 8 V hFE DC forward current gain (Figure 5) for ULQ2001, VCE = 2V, IC = 350mA 1000 CI Input capacitance 15 25 (1) pF tPLH Turn-on delay time 0.5 VI to 0.5VO 0.25 1 (1) μs tPHL Turn-off delay time 0.5 VI to 0.5VO 0.25 1 (1) μs IR Clamp diode leakage current (Figure 9) VR = 50V 50 μA TJ = 105°C, VR = 50V 100 VF Clamp diode forward voltage (Figure 10) IF = 350mA 1.7 2 V 1. Guaranteed by design. ULQ2001, ULQ2003, ULQ2004 Electrical characteristics Doc ID 1537 Rev 6 7/14 TJ = -40 to 125 °C for SO16 unless otherwise specified. Table 5. Electrical characteristics for ULQ2003D1013TRY (Automotive Grade) Symbol Parameter Test conditions Min. Typ. Max. Unit ICEX Output leakage current (Figure 3) VCE = 50V 50 μA VCE(SAT) Collector-emitter saturation voltage (Figure 5) IC = 100mA, IB = 250μA 0.9 1.1 IC = 200mA, IB= 350μA 1.1 1.3 V IC = 350mA, IB= 500μA 1.3 1.6 II(ON) Input current (Figure 6) VI = 3.85V 0.93 1.35 mA II(OFF) Input current (Figure 7) IC = 500μA 50 65 μA VI(ON) Input voltage (Figure 8) VCE = 2V, IC = 200mA VCE = 2V, IC = 250mA VCE = 2V,IC = 300mA 2.4 2.7 3 V CI Input capacitance 15 25 pF tPLH Turn-on delay time 0.5 VI to 0.5VO 0.25 1 μs tPHL Turn-off delay time 0.5 VI to 0.5VO 0.25 1 μs IR Clamp diode leakage current (Figure 9) VR = 50V 50 μA VF Clamp diode forward voltage (Figure 10) IF = 350mA 1.7 2 V Test circuits ULQ2001, ULQ2003, ULQ2004 8/14 Doc ID 1537 Rev 6 5 Test circuits Figure 3. Output leakage current Figure 4. Output leakage current (for ULN2002 only) Figure 5. Collector-emitter saturation voltage Figure 6. Input current (ON) Figure 7. Input current (OFF) Figure 8. Input voltage ULQ2001, ULQ2003, ULQ2004 Test circuits Doc ID 1537 Rev 6 9/14 Figure 9. Clamp diode leakage current Figure 10. Clamp diode forward voltage Package mechanical data ULQ2001, ULQ2003, ULQ2004 10/14 Doc ID 1537 Rev 6 6 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. ULQ2001, ULQ2003, ULQ2004 Package mechanical data Doc ID 1537 Rev 6 11/14 Dim. mm. inch. Min. Typ. Max. Min. Typ. Max. a1 0.51 0.020 B 0.77 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L 3.3 0.130 Z 1.27 0.050 Plastic DIP-16 (0.25) mechanical data P001C Package mechanical data ULQ2001, ULQ2003, ULQ2004 12/14 Doc ID 1537 Rev 6 OUTLINE AND MECHANICAL DATA DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A 1.75 0.069 a1 0.1 0.25 0.004 0.009 a2 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.020 c1 45° (typ.) D(1) 9.8 10 0.386 0.394 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F(1) 3.8 4.0 0.150 0.157 G 4.60 5.30 0.181 0.208 L 0.4 1.27 0.150 0.050 M 0.62 0.024 S 8° (max.) (1) "D" and "F" do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (.006inc.) SO16 (Narrow) 0016020 D ULQ2001, ULQ2003, ULQ2004 Revision history Doc ID 1537 Rev 6 13/14 7 Revision history Table 6. Document revision history Date Revision Changes 05-Dec-2006 2 Order codes updated. 23-May-2007 3 Order codes updated. 17-Apr-2008 4 Added new order codes for Automotive grade products see Table 1 on page 1. 25-Aug-2008 5 Modified: Table 4 on page 6 and Table 5 on page 7. 11-Feb-2011 6 Modified: TJ = -25 to 105 °C Table 4 on page 6. ULQ2001, ULQ2003, ULQ2004 14/14 Doc ID 1537 Rev 6 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2011 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com ULN2001, ULN2002 ULN2003, ULN2004 Seven Darlington array Datasheet − production data Features ■ Seven Darlingtons per package ■ Output current 500 mA per driver (600 mA peak) ■ Output voltage 50 V ■ Integrated suppression diodes for inductive loads ■ Outputs can be paralleled for higher current ■ TTL/CMOS/PMOS/DTL compatible inputs ■ Inputs pinned opposite outputs to simplify layout Description The ULN2001, ULN2002, ULN2003 and ULN 2004 are high voltage, high current Darlington arrays each containing seven open collector Darlington pairs with common emitters. Each channel rated at 500 mA and can withstand peak currents of 600 mA. Suppression diodes are included for inductive load driving and the inputs are pinned opposite the outputs to simplify board layout. The versions interface to all common logic families: – ULN2001 (general purpose, DTL, TTL, PMOS, CMOS) – ULN2002 (14 - 25 V PMOS) – ULN2003 (5 V TTL, CMOS) – ULN2004 (6 - 15 V CMOS, PMOS) These versatile devices are useful for driving a wide range of loads including solenoids, relays DC motors, LED displays filament lamps, thermal printheads and high power buffers. The ULN2001A/2002A/2003A and 2004A are supplied in 16 pin plastic DIP packages with a copper leadframe to reduce thermal resistance. They are available also in small outline package (SO-16) as ULN2001D1/2002D1/2003D1/ 2004D1 DIP-16 SO-16 (Narrow) Table 1. Device summary Order codes ULN2001A ULN2001D1013TR ULN2002A ULN2002D1013TR ULN2003A ULN2003D1013TR ULN2004A ULN2004D1013TR www.st.com Contents ULN2001, ULN2002, ULN2003, ULN2004 2/16 Doc ID 5279 Rev 8 Contents 1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 ULN2001, ULN2002, ULN2003, ULN2004 Diagram Doc ID 5279 Rev 8 3/16 1 Diagram Figure 1. Schematic diagram ULN2001 (each driver) ULN2002 (each driver) ULN2003 (each driver) ULN2004 (each driver) Pin configuration ULN2001, ULN2002, ULN2003, ULN2004 4/16 Doc ID 5279 Rev 8 2 Pin configuration Figure 2. Pin connections (top view) ULN2001, ULN2002, ULN2003, ULN2004 Maximum ratings Doc ID 5279 Rev 8 5/16 3 Maximum ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VO Output voltage 50 V VI Input voltage (for ULN2002A/D - 2003A/D - 2004A/D) 30 V IC Continuous collector current 500 mA IB Continuous base current 25 mA TA Operating ambient temperature range - 40 to 85 °C TSTG Storage temperature range - 55 to 150 °C TJ Junction temperature 150 °C Table 3. Thermal data Symbol Parameter DIP-16 SO-16 Unit RthJA Thermal resistance junction-ambient, Max. 70 120 °C/W Electrical characteristics ULN2001, ULN2002, ULN2003, ULN2004 6/16 Doc ID 5279 Rev 8 4 Electrical characteristics TA = 25 °C unless otherwise specified. Table 4. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit ICEX Output leakage current VCE = 50 V, (Figure 3.) 50 μA TA = 85°C, VCE = 50 V (Figure 3.) 100 TA = 85°C for ULN2002, VCE = 50 V, VI = 6 V (Figure 4.) 500 TA = 85°C for ULN2002, VCE = 50 V, VI = 1V (Figure 4.) 500 VCE(SAT) Collector-emitter saturation voltage (Figure 5.) IC = 100 mA, IB = 250 μA 0.9 1.1 IC = 200 mA, IB= 350 μA 1.1 1.3 V IC = 350 mA, IB= 500 μA 1.3 1.6 II(ON) Input current (Figure 6.) for ULN2002, VI = 17 V 0.82 1.25 mA for ULN2003, VI = 3.85 V 0.93 1.35 for ULN2004, VI = 5 V 0.35 0.5 VI = 12 V 1 1.45 II(OFF) Input current (Figure 7.) TA = 85°C, IC = 500 μA 50 65 μA VI(ON) Input voltage (Figure 8.) VCE= 2 V, for ULN2002 IC = 300 mA for ULN2003 IC = 200 mA IC = 250 mA IC = 300 mA for ULN2004 IC = 125 mA IC = 200 mA IC = 275 mA IC = 350 mA 13 2.4 2.7 3 5 6 7 8 V hFE DC Forward current gain (Figure 5.) for ULN2001, VCE = 2 V, IC = 350 mA 1000 CI Input capacitance 15 25 pF tPLH Turn-on delay time 0.5 VI to 0.5 VO 0.25 1 μs tPHL Turn-off delay time 0.5 VI to 0.5 VO 0.25 1 μs IR Clamp diode leakage current (Figure 9.) VR = 50 V 50 μA TA = 85°C, VR = 50 V 100 VF Clamp diode forward voltage (Figure 10.) IF = 350 mA 1.7 2 V ULN2001, ULN2002, ULN2003, ULN2004 Test circuits Doc ID 5279 Rev 8 7/16 5 Test circuits Figure 3. Output leakage current Figure 4. Output leakage current (for ULN2002 only) Figure 5. Collector-emitter saturation voltage Figure 6. Input current (ON) Figure 7. Input current (OFF) Figure 8. Input voltage Test circuits ULN2001, ULN2002, ULN2003, ULN2004 8/16 Doc ID 5279 Rev 8 Figure 9. Clamp diode leakage current Figure 10. Clamp diode forward voltage ULN2001, ULN2002, ULN2003, ULN2004 Typical performance characteristics Doc ID 5279 Rev 8 9/16 6 Typical performance characteristics Figure 11. Collector current vs. saturation voltage (TJ = 25°C) Figure 12. Collector current vs. saturation voltage Figure 13. Input current vs. input voltage Figure 14. Input current vs. input voltage (Ta = 25°C) Figure 15. Collector current vs. input current Figure 16. hFE vs. output current IOUT [mA] 85°C 25°C -30°C VCESAT [V] IIN = 500 μA ULN2003A Typ Max Min ULN2003A Ta = 25°C Iout=100mA Iout=200mA Iout=300mA IIN [μA] I OUT [mA] -30°C 85°C 25°C VCE = 2 V 1 10 100 1000 10000 1 10 100 1000 DC Current Transfer Ratio (hFE) Output current IOUT [mA] 85 °C -40 °C 25 °C VCE = 2 V Typical performance characteristics ULN2001, ULN2002, ULN2003, ULN2004 10/16 Doc ID 5279 Rev 8 Figure 17. Peak collector current vs. duty cycle (DIP-16) Figure 18. Peak collector current vs. duty cycle (SO-16) 0 20 40 60 80 DC 0 100 200 300 400 500 Ic peak (mA) Tamb=70°C (DIP16) 7 6 5 4 3 2 NUMBER OF ACTIVE OUTPUT D96IN451 0 20 40 60 80 100 DC 0 100 200 300 400 500 Ic peak (mA) D96IN452A 7 5 3 2 NUMBER OF ACTIVE OUTPUT Tamb=70°C (SO16) ULN2001, ULN2002, ULN2003, ULN2004 Package mechanical data Doc ID 5279 Rev 8 11/16 7 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 5. DIP-16L mechanical data Dim. mm. Min. Typ. Max. A 5.33 A1 0.38 A2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 D 18067 19.18 19.69 E 7.62 7.87 8.26 E1 6.10 6.35 7.11 e 2.54 e1 17.78 eA 7.62 eB 10.92 L 2.92 3.30 3.81 Package mechanical data ULN2001, ULN2002, ULN2003, ULN2004 12/16 Doc ID 5279 Rev 8 Figure 19. DIP-16L package dimensions 0015895_E ULN2001, ULN2002, ULN2003, ULN2004 Package mechanical data Doc ID 5279 Rev 8 13/16 Table 6. SO-16 narrow mechanical data Dim. mm. inch. Min. Typ. Max. Min. Typ. Max. A 1.75 0.069 a1 0.1 0.25 0.004 0.009 a2 1.6 0.063 b 0.35 0.46 0.014 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.020 c1 45° (typ.) D(1) 9.8 10 0.386 0.394 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F(1) 3.8 4.0 0.150 0.157 G 4.60 5.30 0.181 0.208 L 0.4 1.27 0.150 0.050 M 0.62 0.024 S 8° (max.) Figure 20. SO-16 package dimensions Order codes ULN2001, ULN2002, ULN2003, ULN2004 14/16 Doc ID 5279 Rev 8 8 Order codes Table 7. Order codes Part numbers Packages ULN2001A DIP-16 ULN2002A DIP-16 ULN2003A DIP-16 ULN2004A DIP-16 ULN2001D1013TR SO-16 in tape and reel ULN2002D1013TR SO-16 in tape and reel ULN2003D1013TR SO-16 in tape and reel ULN2004D1013TR SO-16 in tape and reel ULN2001, ULN2002, ULN2003, ULN2004 Revision history Doc ID 5279 Rev 8 15/16 9 Revision history Table 8. Revision history Date Revision Changes 05-Dec-2006 5 Order code updated and document reformatted. 28-Aug-2007 6 Added Table 1 in cover page. 07-May-2012 7 Modified: Figure 12 on page 9. Added: Figure 13, 14, 15 and Figure 16 on page 9. 01-Jun-2012 8 Updated: DIP-16L package mechanical data Table 5 on page 11 and Figure 19 on page 12. ULN2001, ULN2002, ULN2003, ULN2004 16/16 Doc ID 5279 Rev 8 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2012 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Smart street lighting solutions GPRS/3G network Data flow Contents Goals and design of street lighting Smart street lighting From incandescent lamps to HID and LED: today’s highest luminous performances The advantages of electronic ballasts for HID lamps: ST’s solutions Using LEDs in street lighting: ST’s solutions Smart communication system: wireless and wired Real-time lamppost fall detection using MEMS A complete solution for smart street lighting Goals and design of street lighting Goals Design principles Ensure maximum visual safety for drivers and pedestrians Improve visibility of people and objects Provide the best light quality and the highest color rendering Make residential areas surer Enhance street furniture appearance Energy efficient Reliable and safe Technically advanced Cost effective Convenient for maintenance What is smart street lighting?  Enables smart cities with highly-efficient street light driving, advanced monitoring and remote control GPRS/3G network Data flow Lamp controller with connectivity PDA with RF connectivity District data concentrator Services center Reduced maintenance costs Reduced energy consumption Performance and energy-consumption data at your fingertips Reduced greenhouse gas emissions Greater citizen satisfaction Why smart street lighting? From incandescent lamps to HID, LED Inefficient light sources such as incandescent lamps will be phased out LED technology will push the lighting market HID and HB LED offer outstanding luminous efficiency Source: U.S Department of energy 2004, Philips Lighting 2005 HID, LED: highest performances Ignition at very high voltage Warm-up phase is required Steady-state phase with lamp power control is needed Different performances according to the metals and filler materials High pressure sodium (up to 150 lm/W) Metal halide (up to 110 lm/W) Mercury vapor (up to 60 lm/W) A LED is activated when a DC voltage is applied The luminous flux and dominant wavelength are controlled by average current The ripple current has to be kept at acceptable levels Dimming can be implemented through digital or analog control  Best LED efficiency: 150 lm/W High intensity discharge (HID) Light emitting diode (LED) Source: OSRAM Electronic ballasts for HID lamps Increased lamp life Enhanced lumen constancy with life 10-15% lower energy consumption than magnetic ballasts More reliable lamp operation (end of life protection) Electronic ballasts are smaller than electromagnetic ballasts Electronics allow smart communication Lamp controller with connectivity Source: Philips Lighting Input: 185 to 265 VAC, 50 Hz Load: 150 W MH or HPS lamp PF = 0.99, THD = 2.8% Dimmable Average efficiency: 90% EN55015 compliant Remote control interfacing by PLM 150 W electronic ballast for HID lamps ESICOM order code: STEVAL-ILH005V2* Description and purpose Key features 2-stage electronic ballast for 150 W HID (high-intensity discharge) lamp, including a boost converter (PFC) working in transition mode (TM), and a full bridge inverter to drive a lamp with a low-frequency square wave Key products STF10NM60ND; STGF10NC60SD; STTH1L06; STTH1R06; VIPer16L; L6562A; L6388E; TS272; ST7FLITE39F2 * Available in Q1/2012 Wide input voltage range High power factor (up to 0.998) and very low THD (5%) PFC boost working in TM Half bridge based on power MOSFETs Controls the igniter circuit Implements buck converter in TM Provides alternate low frequency square wave current Overvoltage and short-circuit protection Suitable for HPS and MH lamps 70 W electronic ballast for HID lamps ESICOM order code: STEVAL-ILH004V1* Description and purpose Key features Fully digital ballast to drive 70 W HID lamps, based on two ICs, the digital combo driver L6382D5 and a low-cost 8-bit microcontroller, able to manage the PFC and the half bridge stage Key products L6382D5; STF8NM60ND; STTH1L06; VIPer16L; ST7LITE49K2; LIC01. * Available in Q1/2012 Source of graphic: RUUD lighting LED HID Using LEDs in street lighting The green way to lowering energy costs Low power consumption Long lumen constancy Long and predictable lifetime Light emission can be easily redirected Reliability (robust against shock and vibration) Environment friendly (CO2 saving and mercury free) Quick turn on/off and dimming 100 W and above 130 W LED driver based on L6562AT and L6599AT Input mains range: 85 to 305 VAC SMPS output voltage: 48 V at 2.7 A Long life time, electrolytic capacitors are not used Mains harmonics: meet EN61000-3-2 Class-C Efficiency at full load: > 93% EMI: meets EN55022-Class-B, EN55015 Digital dimming ESICOM order code: EVL130W-STRLIG, EVL130W-SL-EU, EVL6562A-LED Description and purpose Key features The system is composed of three stages: a front-end PFC an LLC resonant converter an inverse buck converter The key benefits are very high efficiency, long term reliability and small form factor Key products L6562AT, L6599AT, STF21NM60N, STD10NM60N, SEA05, STTH3L06U, STPS1L60A, STPS2H100A, STN3NF06 Wide input voltage range: 88 to 265 VAC LED current set to 350 mA, 700 mA and 1 A High efficiency (~90%) and high power factor Universal PWM input for dimming (ext. board required) Non-isolated SMPS Brightness regulation between 0% and 100% EMI filter implemented EN55015 and EN61000-3-2 compliant 80 W and above 80 W offline LED driver with dimming based on L6562A ESICOM order code: STEVAL-ILL013V1 Description and purpose Key features An innovative non-isolated solution for driving LEDs where high power factor, high efficiency and individual LED brightness regulation is required PFC boost, inverse buck converter Key products L6562A, STTH1L06A, STF10NM50N, STP8NM50N , STPSC806D, BUX87 Input voltage range: 185 to 265 VAC Able to drive single LED String Provides 350 mA to 0.5 A constant current for LED Max output voltage: 130 VDC No input electrolytic capacitor Efficiency: from 91% to 92.5% PF > 0.95 Maximum 2fLINE output ripple: 1.0% Up to 75 W ESICOM order code: STEVAL-ILL042V1* Description and purpose Key features Key products L6562AT; STP7N95K3; TSM101; 1.5KE350A; STTH1L06; STTH2L06 Single-stage isolated solution based on L6562AT and TSM101, offering high performance with a simple and reliable design for LED street lighting High power factor flyback 60 W offline LED driver for single LED string based on L6562AT * Available in Q1/2012 Digital constant-current controller for multi-string LED driving based on STM8S Input DC bus voltage: 48 V Independent LED string average current control Inverse buck topology System power: 120 W Switching frequency: 100 kHz Ripple current <10% Global dimming from 0% to 100% at 225 Hz (PWM dimming) Independent analog dimming on 4 channels Short-circuit protection Innovative multi-string LED driving ESICOM order code: STEVAL-ILL031V1 Description and purpose Key features Key products STM8S208RB; STPS1L60; STN3NF06 Complete platform (HW/SW) for LED multi-string constant-current control based on an innovative methodology Each LED string can be dimmed and brightened independently System can be interfaced with ZigBee or PLM modules for remote control Smart communication GPRS/3G network Data flow Dimming level, adjust on/off timing, lamp failure, consumed energy, lamp-burning hours, lamppost tilt, etc. Highway: simple linear topology City centre: complex topology Wireless network solution STM32W108xx: 32-bit MCU ARM Cortex-M3 ZigBee system on chip SPZB32W1x2.1: ZigBee PRO modules based on the STM32W chipset M24LR64-R: 64-Kbit Dual Interface EEPROM (I²C and ISO 15693 RF protocol at 13.56 MHz) IEEE 802.15.4 - ZigBee® network A mesh topology is used to reach the data concentrator A network for each district is identified by its PANID Lamppost’s node configuration using RFID EEPROM which can be written/read during both manufacturing process and installation procedure by the PDA C R1 R2 N2 R3 N4 N3 N1 Data concentrator/ network coordinator Router lamppost End node lamppost STM32W or SPZB32W1x2.1 M24LR64-R Lamppost communication mode PLC wired network solution STM32F103xx: 32-bit MCU ARM Cortex-M3 microcontroller M24LR64-R: 64-Kbit Dual Interface EEPROM (I²C and ISO 15693 RF protocol at 13.56 MHz) ST7570: IEC 61334-5-1 compliant PLM ST7540: FSK stripped down power line transceiver IEC 61334-5-1 power line communication network (ST7570) or proprietary protocol (ST7540) Configured to work in CENELEC band B or C to avoid interference with AMR network Data repeaters are used to reach the data concentrator  A network for each district identified by unique identification  Node configuration using RFID EEPROM which can be written/read during both manufacturing process and installation procedure by the PDA C R1 R2 N2 R3 N4 N3 N1 Data concentrator/ network initiator Repeater lamppost End node lamppost STM32F ST7570 or ST7540 Lamppost communication mode M24LR64-R Data concentrator STM32F107xx: 32-bit MCU ARM Cortex-M3 microcontroller with Ethernet M24LR64-R: 64-Kbit Dual Interface EEPROM (I²C and ISO 15693 RF protocol at 13.56 MHz) ST7570: IEC 61334-5-1 compliant PLM ST7540: FSK stripped down power line transceiver STM32W108xx: 32-bit MCU ARM Cortex-M3 ZigBee system on chip SPZB32W1x2.1: ZigBee PRO modules based on the STM32W chipset M24128-Bxx: 128-Kbit EEPROM One concentrator for each district STM32F ST7570 or ST7540 M24LR64-R STM32W or SPZB32W1x2.1 GPRS module M24128-Bxx PLM option ZigBee® option Real-time lamppost fall detection STM32F LIS331DLH STM32W or SPZB32W1x2.1 One low-g 3-axis accelerometer for each lamppost Tilt angle measurement Lamppost fall detection Key application benefits Road safety Reduced maintenance cost 150 W HID lamp ballast + ST7540-based communication for networked street lighting Solutions for smart street lighting Lamp driver and controller 150 W high-efficiency HID lamp ballast High reliability (up to 85°C ambient temperature) Dimmable and EN55015 compliant Suitable for HPS and MH lamps Communication section Remote control on power line Routing policies to cover long distances without dedicated hardware resources Allows remote turn-on/off, dimming, lamp and ballast status monitoring Description and purpose Key features Innovative networked street lighting system with remote control and monitoring based on PLM, including a dedicated PC GUI * Available in Q1/2012 ESICOM order code: STEVAL-ILH005V2* STEVAL-IHP003V1 Thank you For more information, visit our website: www.st.com Or follow the links below: LED and general lighting HID lighting LED lighting Evaluation boards LM350 Three-terminal 3 A adjustable voltage regulators Features ■ Guaranteed 3 A output current ■ Adjustable output down to 1.2 V ■ Line regulation typically 0.005 %/V ■ Load regulation typically 0.1 % ■ Guaranteed thermal regulation ■ Current limit constant with temperature ■ Standard 3-lead transistor package TO-3 Table 1. Device summary Order codes TO-3 Temperature range LM350K 0 to 125 °C www.st.com Contents LM350 2/14 Contents 1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Typical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.1 External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.2 Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.3 Protection diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 LM350 Diagram 3/14 1 Diagram Figure 1. Schematic diagram Pin configuration LM350 4/14 2 Pin configuration Figure 2. Pin connections (bottom view) LM350 Maximum ratings 5/14 3 Maximum ratings Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied Table 2. Absolute maximum ratings Symbol Parameter Value Unit PD Power dissipation Internally limited VI - VO Input-output voltage differential 35 V TSTG Storage temperature range -65 to 150 °C TLEAD lead temperature (Soldering, 10 seconds) 300 °C TOP Operating junction temperature range 0 to 125 °C Table 3. Thermal data Symbol Parameter Value Unit RthJC Thermal resistance junction-case 1.5 °C/W RthJA Thermal resistance junction-ambient 35 °C/W Electrical characteristics LM350 6/14 4 Electrical characteristics Table 4. Electrical characteristics (VI -VO = 5V, IO = 1.5 A. Although power dissipation is internally limited, these specifications apply to power dissipation up to 30 W, unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit KVI Line regulation (1) 1. Regulation is measured at constant junction temperature. Changes in output voltage due to heating effects are taken into account separately by thermal rejection. Ta = 25°C, VI - VO = 3 to 35 V 0.005 0.03 %/V KVO Load regulation (1) Ta = 25°C IO = 10 mA to 3 A VO ≤ 5 V 5 25 mV VO ≥ 5 V 0.1 0.5 % Thermal regulation Pulse = 20 ms 0.002 0.02 %/W IADJ Adjustment pin current 50 100 μA ΔIADJ Adjustment pin current change IL = 10 mA to 3 A, VI - VO = 3 to 35 V 0.2 5 μA VREF Reference voltage VI - VO = 3 to 35 V, IO = 10 mA to 3 A P ≤ 30 W 1.19 1.24 1.29 V KVI Line regulation (1) VI - VO = 3 to 35 V 0.02 0.05 %/V KVO Load regulation (1) IO = 10 mA to 3 A VO ≤ 5 V 20 70 mV VO ≥ 5 V 0.3 1.5 % KVT Temperature stability TJ = TMIN to TMAX 1 % IO(MIN) Minimum load current VI - VO ≤ 35 V 3.5 10 mA IO(MAX) Current limit VI - VO ≤ 10 V DC 3 4.5 A VI - VO = 30 V 1 VNO RMS output noise (% of VO) Ta = 25°C, f = 10 Hz to 10 kHz 0.001 % RVF Ripple rejection ratio VO = 10 V, f = 120 Hz 65 dB CADJ = 10 μF 66 86 KVH Long term stability Ta = 125°C 0.3 1 % LM350 Typical performance 7/14 5 Typical performance Δ Needed if device is far from filter capacitors. * Optional-improves transient response. Output capacitors in the range of 1 μF to 100 μF of aluminium or tantalum electrolytic are commonly used to provide improved output impedance and rejection of transients ** VO = 1.25 V (1 + R2/R1) Figure 3. 1.2 V to 25 V adjustable regulator Application hints LM350 8/14 6 Application hints In operation, the LM350 develops a nominal 1.25 V reference voltage, V(REF), between the output and adjustment terminal. The reference voltage is impressed across program resistor R1 and, since the voltage is constant, a constant current I1 then flows through the output set resistor R2, giving an output voltage of: VO = V(REF) (1+ R2 / R1) + IADJ x R2. Since the 50 μA current from the adjustment terminal represents an error term, the LM350 was designed to minimize IADJ and make it very constant with line and load changes. To do this, all quiescent operating current is returned to the output establishing a minimum load current requirement. If there is insufficient load on the output, the output will rise. 6.1 External capacitors An input bypass capacitor is recommended. A 0.1 μF disc or 1 μF solid tantalum on the input is suitable input by passing for almost all applications. The device is more sensitive to the absence of input bypassing when adjustment or output capacitors are used by the above values will eliminate the possibility of problems. The adjustment terminal can be bypassed to ground on the LM350 to improve ripple rejection. This bypass capacitor prevents ripple form being amplified as the output voltage is increased. With a 10 μF bypass capacitor 75 dB ripple rejection is obtainable at any output level. Increases over 20 μF do not appreciably improve the ripple rejection at frequencies above 120 Hz. If the bypass capacitor is used, it is sometimes necessary to include protection diodes to prevent the capacitor from discharging through internal low current paths and damaging the device. In general, the best type of capacitors to use are solid tantalum. Solid tantalum capacitors have low impedance even at high frequencies. Depending upon capacitor construction, it takes about 25 μF in aluminium electrolytic to equal 1 μF solid tantalum at high frequencies. Ceramic capacitors are also good at high frequencies, but some types have a large Figure 4. Circuit LM350 Application hints 9/14 decrease in capacitance at frequencies around 0.5 MHz. For this reason, 0.01 μF disc may seem to work better than a 0.1 μF disc as a bypass. Although the LM350 is stable with no output capacitors, like any feedback circuit, certain values of external capacitance can cause excessive ringing. This occurs with values between 500 pF and 5000 pF. A 1 μF solid tantalum (or 25 μF aluminium electrolytic) on the output swamps this effect and insures stability. 6.2 Load regulation The LM350 is capable of providing extremely good load regulation but a few precautions are needed to obtain maximum performance. The current set resistor connected between the adjustment terminal and the output terminal (usually 240 Ω) should be tied directly to the output of the regulator rather than near the load. This eliminates line drops from appearing effectively in series with the reference and degrading regulation. For example, a 15 V regulator with 0.05 Ω resistance between the regulator and load will have a load regulation due to line resistance of 0.05 Ω x IL. If the set resistor is connected near the load the effective line resistance will be 0.05 Ω (1 + R2/R1) or in this case, 11.5 times worse. Figure 5 shows the effect of resistance between the regulator and 140 Ω set resistor. With the TO-3 package, it is easy to minimize the resistance from the case to the set resistor, by using 2 separate leads to the case. The ground of R2 can be returned near the ground of the load to provide remote ground sensing and improve load regulation. 6.3 Protection diodes When external capacitors are used with any IC regulator it is sometimes necessary to add protection diodes to prevent the capacitors from discharging through low current points into the regulator. Most 20 μF capacitors have low enough internal series resistance to deliver 20 A spikes when shorted. Although the surge is short, there is enough energy to damage parts of the IC. When an output capacitor is connected to a regulator and the input is shorted, the output capacitor will discharge into the output of the regulator. The discharge current depends on the value of the capacitor, the output voltage of the regulator, and the rate of decrease of VI. In the LM350 this discharge path is through a large junction that is able to sustain 25 A surge with no problem. This is not true of other types of positive regulators. For output capacitors of 100 μF or less at output of 15 V or less, there is no need to use diodes. The bypass capacitor on the adjustment terminal can discharge through a low current junction. Discharge occurs when either the input or output is shorted. Internal to the LM350 is a 50 Ω resistor which limits the peak discharge current. No protection is needed for output voltages of 25 V or less and 10 μF capacitance. Figure 6 shows an LM350 with protection diodes included for use with outputs greater than 25 V and high values of output capacitance. Application circuits LM350 10/14 7 Application circuits Figure 5. Regulator with line resistance in output lead Figure 6. Regulator with protection diodes LM350 Package mechanical data 11/14 8 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Package mechanical data LM350 12/14 Dim. mm. inch. Min. Typ. Max. Min. Typ. Max. A 11.85 0.466 B 0.96 1.05 1.10 0.037 0.041 0.043 C 1.70 0.066 D 8.7 0.342 E 20.0 0.787 G 10.9 0.429 N 16.9 0.665 P 26.2 1.031 R 3.88 4.09 0.152 0.161 U 39.5 1.555 V 30.10 1.185 TO-3 mechanical data P003C/C E B R C P A D G N V U O LM350 Revision history 13/14 9 Revision history Table 5. Document revision history Date Revision Changes 29-Sep-2006 1 11-Feb-2008 2 Added: Table 1 on page 1. LM350 14/14 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com VND920P-E Double channel high-side driver Features ■ ECOPACK®: lead free and RoHS compliant ■ Automotive Grade: compliance with AEC guidelines ■ Very low standby current ■ CMOS compatible input ■ Proportional load current sense ■ Current sense disable ■ Thermal shutdown protection and diagnosis ■ Undervoltage shutdown ■ Overvoltage clamp ■ Load current limitation Description The VND920P-E is a double chip device designed in STMicroelectronics™ VIPower ™ M0-3 technology. The VND920P-E is intended for driving any type of load with one side connected to ground. The active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). Active current limitation combined with thermal shutdown and automatic restart protects the device against overload. The device integrates an analog current sense output which delivers a current proportional to the load current. The device automatically turns off in the case where the ground pin becomes disconnected. Type RDS(on) IOUT VCC VND920P-E 16 mΩ 35 A(1) 1. Per channel with all the output pins connected to the PCB. 36 V SO-28 (double island) Table 1. Device summary Package Order codes Tube Tape and reel SO-28 VND920P-E VND920PTR-E www.st.com Contents VND920P-E 2/26 Doc ID 10898 Rev 5 Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 17 3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 17 3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 18 3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 Maximum demagnetization energy (VCC = 13.5 V) . . . . . . . . . . . . . . . . . 19 4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 SO-28 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 SO-28 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 VND920P-E List of tables Doc ID 10898 Rev 5 3/26 List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 5. Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 6. Switching (VCC=13 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 7. VCC output diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 8. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 9. Current sense (9 V <= VCC <=16 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 10. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 12. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 13. Thermal calculation according to the PCB heatsink area . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 14. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 15. SO-28 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 16. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 List of figures VND920P-E 4/26 Doc ID 10898 Rev 5 List of figures Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. IOUT/ISENSE versus IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7. Off-state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 9. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 10. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 11. Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 12. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 13. ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 14. On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 15. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 17. On-state resistance vs Tcase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 18. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 19. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 20. Maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 21. SO-28 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 22. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 23. SO-28 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 24. Thermal fitting model of a double channel HSD in SO-28 . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 25. SO-28 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 26. SO-28 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 27. SO-28 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 VND920P-E Block diagram and pin description Doc ID 10898 Rev 5 5/26 1 Block diagram and pin description Figure 1. Block diagram UNDERVOLTAGE OVERTEMPERATURE VCC 1 GND 1 INPUT 1 OUTPUT 1 OVERVOLTAGE CURRENT LIMITER LOGIC DRIVER Power CLAMP VCC CLAMP VDS LIMITER DETECTION DETECTION DETECTION K IOUT CURRENT SENSE 1 UNDERVOLTAGE OVERTEMPERATURE VCC 2 GND 2 INPUT 2 OUTPUT 2 OVERVOLTAGE CURRENT LIMITER LOGIC DRIVER Power CLAMP VCC CLAMP VDS LIMITER DETECTION DETECTION DETECTION K IOUT CURRENT SENSE 2 Block diagram and pin description VND920P-E 6/26 Doc ID 10898 Rev 5 Figure 2. Configuration diagram (top view) Table 2. Suggested connections for unused and not connected pins Connection / pin Current Sense N.C. Output Input Floating X X X To ground Through 1KΩ resistor X Through 10 KΩ resistor VCC 1 GND 1 INPUT 1 CURRENT SENSE 1 NC VCC 1 VCC 2 GND 2 INPUT 2 CURRENT SENSE 2 VCC 2 VCC 2 OUTPUT 2 OUTPUT 2 OUTPUT 2 OUTPUT 2 OUTPUT 1 OUTPUT 1 OUTPUT 1 OUTPUT 1 VCC1 OUTPUT 2 OUTPUT 2 OUTPUT 1 OUTPUT 1 NC NC NC 1 14 15 28 VND920P-E Electrical specifications Doc ID 10898 Rev 5 7/26 2 Electrical specifications Figure 3. Current and voltage conventions Note: VFn = VCCn - VOUTn during reverse battery condition. 2.1 Absolute maximum ratings Stressing the device above the rating listed in Table 3 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to Absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics sure program and other relevant quality document. IS2 IGND2 OUTPUT2 VCC2 IOUT2 VCC2 VSENSE2 CURRENT SENSE 1 ISENSE1 VOUT2 OUTPUT1 IOUT1 CURRENT SENSE 2 ISENSE2 VSENSE1 VOUT1 INPUT2 IIN2 INPUT1 IIN1 VIN2 VIN1 GROUND2 IS1 VCC1 VCC1 IGND1 GROUND1 VF1 (*) Table 3. Absolute maximum ratings Symbol Parameter Value Unit VCC DC supply voltage 41 V - VCC Reverse DC supply voltage - 0.3 V - Ignd DC reverse ground pin current - 200 mA IOUT DC output current Internally limited A - IOUT Reverse DC output current - 21 A IIN DC input current +/- 10 mA VCSENSE Current Sense maximum voltage - 3 + 15 V V VESD Electrostatic discharge (human body model: R = 1.5 KΩ; C = 100pF) INPUT CURRENT SENSE OUTPUT VCC 4000 2000 5000 5000 V V V V Electrical specifications VND920P-E 8/26 Doc ID 10898 Rev 5 2.2 Thermal data Symbol Parameter Value Unit EMAX Maximum switching energy (L = 0.25 mH; RL= 0 Ω; Vbat = 13.5 V; Tjstart = 150 °C; IL = 45 A) 355 mJ Ptot Power dissipation TC ≤ 25°C 6.25 W Tj Junction operating temperature Internally limited °C Tc Case operating temperature - 40 to 150 °C Tstg Storage temperature - 55 to 150 °C Table 3. Absolute maximum ratings (continued) Table 4. Thermal data (per island) Symbol Parameter Value Unit Rthj-lead Thermal resistance junction-lead 15 °C/W Rthj-amb Thermal resistance junction-ambient (one chip ON) 55(1) 1. When mounted on a standard single-sided FR-4 board with 1cm2 of Cu (at least 35 μm thick) connected to all VCC pins. Horizontal mounting and no artificial air flow. 45(2) 2. When mounted on a standard single-sided FR-4 board with 6cm2 of Cu (at least 35 μm thick) connected to all VCC pins. Horizontal mounting and no artificial air flow. °C/W Rthj-amb Thermal resistance junction-ambient (two chips ON) 46(1) 32(2) °C/W VND920P-E Electrical specifications Doc ID 10898 Rev 5 9/26 2.3 Electrical characteristics Values specified in this section are for 8 V < VCC < 36 V; -40 °C < Tj < 150 °C, unless otherwise stated. Note: VCLAMP and VOV are correlated. Typical difference is 5 V. Table 5. Power Symbol Parameter Test conditions Min. Typ. Max. Unit VCC Operating supply voltage 5.5 13 36 V VUSD Undervoltage shutdown 3 4 5.5 V VOV Overvoltage shutdown 36 V RON On-state resistance IOUT = 10 A; Tj = 25 °C; IOUT = 10 A; IOUT = 3 A; VCC = 6 V 16 32 55 mΩ mΩ mΩ VCLAMP Clamp voltage ICC = 20 mA 41 48 55 V IS Supply current Off-state; VCC = 13 V; VIN = VOUT = 0V Off-state; VCC = 13 V; VIN = VOUT = 0 V; Tj = 25 °C On-state; VCC = 13 V; VIN = 5 V; IOUT = 0 A; RSENSE = 3.9 kΩ 10 10 25 20 5 μA μA mA IL(off1) Off-state output current VIN = VOUT = 0 V 0 50 μA IL(off2) Off-state output current VIN = 0 V; VOUT = 3.5 V -75 0 μA IL(off3) Off-state output current VIN = VOUT = 0 V; VCC = 13 V; Tj = 125 °C 5 μA IL(off4) Off-state output current VIN = VOUT = 0 V; VCC = 13 V; Tj = 25 °C 3 μA Table 6. Switching (VCC=13 V) Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time RL = 1.3 Ω (see Figure 4.) 50 μs td(off) Turn-off delay time RL = 1.3 Ω (see Figure 4.) 50 μs dVOUT/dt(on) Turn-on voltage slope RL = 1.3 Ω (see Figure 4.) See Figure 10. V/μs dVOUT/dt(off) Turn-off voltage slope RL = 1.3 Ω (see Figure 4.) See Figure 12. V/μs Table 7. VCC output diode Symbol Parameter Test conditions Min. Typ. Max. Unit VF Forward on voltage - IOUT = 5 A; Tj = 150 °C - - 0.6 V Electrical specifications VND920P-E 10/26 Doc ID 10898 Rev 5 Table 8. Logic inputs Symbol Parameter Test conditions Min. Typ. Max. Unit VIL Input low level voltage 1.25 V IIL Low level input current VIN = 1.25 V 1 μA VIH Input high level voltage 3.25 V IIH High level input current VIN = 3.25 V 10 μA VI(hyst) Input hysteresis voltage 0.5 V VICL Input clamp voltage IIN = 1 mA IIN = - 1 mA 6 6.8 - 0.7 8 V V Table 9. Current sense (9 V <= VCC <=16 V) Symbol Parameter Test conditions Min. Typ. Max. Unit K1 IOUT/ISENSE IOUT = 1 A; VSENSE = 0.5 V; Tj = -40 °C...150 °C 3300 4400 6000 dK1/K1 Current sense ratio drift IOUT = 1 A; VSENSE = 0.5 V; Tj= - 40 °C...150 °C -10 +10 % K2 IOUT/ISENSE IOUT = 10 A; VSENSE = 4 V; Tj = - 40 °C Tj= 25 °C...150 °C 4200 4400 4900 4900 6000 5750 dK2/K2 Current sense ratio drift IOUT = 10 A; VSENSE = 4 V; Tj = -40 °C...150 °C -8 +8 % K3 IOUT/ISENSE IOUT = 30 A; VSENSE = 4 V; Tj = -40 °C Tj = 25 °C...150 °C 4200 4400 4900 4900 5500 5250 dK3/K3 Current sense ratio drift IOUT = 30 A; VSENSE = 4 V; Tj = -40 °C...150 °C -6 +6 % ISENSE0 Analog sense current VCC = 6...16V; IOUT = 0A; VSENSE = 0V; Tj = -40°C...150°C 0 10 μA VSENSE Max analog sense output voltage VCC = 5.5 V; IOUT = 5 A; RSENSE = 10 kΩ VCC > 8 V, IOUT = 10 A; RSENSE = 10 kΩ 2 4 V V VSENSEH Sense voltage in overtemperature condition VCC = 13 V; RSENSE = 3.9 kΩ 5.5 V RVSENSEH Analog sense output impedance in overtemperature condition VCC = 13 V; Tj > TTSD; output open 400 Ω tDSENSE Current sense delay response To 90 % ISENSE (1) 1. Current sense signal delay after positive input slope. 500 μs VND920P-E Electrical specifications Doc ID 10898 Rev 5 11/26 Table 10. Protections(1) 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device operates under abnormal conditions this software must limit the duration and number of activation cycles. Symbol Parameter Test conditions Min. Typ. Max. Unit TTSD Shutdown temperature 150 175 200 °C TR Reset temperature 135 °C Thyst Thermal hysteresis 7 15 °C Ilim Current limitation VCC = 13 V 5 V < VCC < 36 V 30 45 75 75 A A Vdemag Turn-off output clamp voltage IOUT = 2 A; VIN = 0 V; L = 6 mH VCC - 41 VCC - 48 VCC - 55 V VON Output voltage drop limitation IOUT = 1 A; Tj = -40 °C...150 °C 50 mV Table 11. Truth table Conditions Input Output Sense Normal operation L H L H 0 Nominal Overtemperature L H L L 0 VSENSEH Undervoltage L H L L 0 0 Overvoltage L H L L 0 0 Short circuit to GND L H H L L L 0 (TjTTSD) VSENSEH Short circuit to VCC L H H H 0 < Nominal Negative output voltage clamp L L 0 Electrical specifications VND920P-E 12/26 Doc ID 10898 Rev 5 Figure 4. Switching characteristics Table 12. Electrical transient requirements ISO T/R 7637/1 Test pulse Test level I II III IV Delays and impedance 1 - 25 V(1) 1. All functions of the device are performed as designed after exposure to disturbance. - 50 V(1) - 75 V(1) - 100 V(1) 2 ms, 10 Ω 2 + 25 V(1) + 50 V(1) + 75 V(1) + 100 V(1) 0.2 ms, 10 Ω 3a - 25 V(1) - 50 V(1) - 100 V(1) - 150 V(1) 0.1 μs, 50 Ω 3b + 25 V(1) + 50 V(1) + 75 V(1) + 100 V(1) 0.1 μs, 50 Ω 4 - 4 V(1) - 5 V(1) - 6 V(1) - 7 V(1) 100 ms, 0.01 Ω 5 + 26.5 V(1) + 46.5 V(2) 2. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device. + 66.5 V(2) + 86.5 V(2) 400 ms, 2 Ω VOUT dVOUT/dt(on) tr 80% 10% tf dVOUT/dt(off) ISENSE t t 90% td(off) INPUT t 90% td(on) tDSENSE VND920P-E Electrical specifications Doc ID 10898 Rev 5 13/26 Figure 5. IOUT/ISENSE versus IOUT 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 3000 3500 4000 4500 5000 5500 6000 6500 min.Tj=-40°C max.Tj=-40°C min.Tj=25...150°C max.Tj=25...150°C typical value IOUT (A) IOUT/ISENSE 6500 6000 5500 5000 4500 4000 3500 3000 Electrical specifications VND920P-E 14/26 Doc ID 10898 Rev 5 Figure 6. Waveforms SENSE INPUT NORMAL OPERATION UNDERVOLTAGE VCC VUSD VUSDhyst INPUT OVERVOLTAGE VCC SENSE INPUT SENSE LOAD CURRENT LOAD CURRENT LOAD CURRENT VOV VCC > VUSD VOVhyst SHORT TO GROUND INPUT LOAD CURRENT SENSE LOAD VOLTAGE INPUT LOAD VOLTAGE SENSE LOAD CURRENT