CLRC632 - NXP Semiconductors - Farnell Element 14 - Revenir à l'accueil
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1. Introduction This data sheet describes the functionality of the CLRC632 Integrated Circuit (IC). It includes the functional and electrical specifications and from a system and hardware viewpoint gives detailed information on how to design-in the device. Remark: The CLRC632 supports all variants of the MIFARE Mini, MIFARE 1K, MIFARE 4K and MIFARE Ultralight RF identification protocols. To aid readability throughout this data sheet, the MIFARE Mini, MIFARE 1K, MIFARE 4K and MIFARE Ultralight products and protocols have the generic name MIFARE. 2. General description The CLRC632 is a highly integrated reader IC for contactless communication at 13.56 MHz. The CLRC632 reader IC provides: • outstanding modulation and demodulation for passive contactless communication • a wide range of methods and protocols • a small, fully integrated package • pin compatibility with the MFRC500, MFRC530, MFRC531 and SLRC400 All protocol layers of the ISO/IEC 14443 A and ISO/IEC 14443 B communication standards are supported provided: • additional components, such as the oscillator, power supply, coil etc. are correctly applied. • standardized protocols, such as ISO/IEC 14443-4 and/or ISO/IEC 14443 B anticollision are correctly implemented The CLRC632 supports contactless communication using MIFARE higher baud rates (see Section 9.12 on page 40). The receiver module provides a robust and efficient demodulation/decoding circuitry implementation for compatible transponder signals (see Section 9.10 on page 34). The digital module, manages the complete ISO/IEC 14443 standard framing and error detection (parity and CRC). In addition, it supports the fast MIFARE security algorithm for authenticating the MIFARE products (see Section 9.14 on page 42). All layers of the I-CODE1 and ISO/IEC 15693 protocols are supported by the CLRC632. The receiver module provides a robust and efficient demodulation/decoding circuitry implementation for I-CODE1 and ISO/IEC 15693 compatible transponder signals. The digital module handles I-CODE1 and ISO/IEC 15693 framing and error detection (CRC). CLRC632 Standard multi-protocol reader solution Rev. 3.7 — 27 February 2014 073937 Product data sheet COMPANY PUBLICCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 2 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution The internal transmitter module (Section 9.9 on page 31) can directly drive an antenna designed for a proximity operating distance up to 100 mm without any additional active circuitry. A parallel interface can be directly connected to any 8-bit microprocessor to ensure reader/terminal design flexibility. In addition, Serial Peripheral Interface (SPI) compatibility is supported (see Section 9.1.4 on page 9). 3. Features and benefits 3.1 General Highly integrated analog circuitry for demodulating and decoding card/label response Buffered output drivers enable antenna connection using the minimum of external components Proximity operating distance up to 100 mm Supports both ISO/IEC 14443 A and ISO/IEC 14443 B standards Supports MIFARE dual-interface card ICs and the MIFARE Mini, MIFARE 1K, MIFARE 4K protocols Contactless communication at MIFARE higher baud rates (up to 424 kBd) Supports both I-CODE1 and ISO/IEC 15693 protocols Crypto1 and secure non-volatile internal key memory Pin-compatible with the MFRC500, MFRC530, MFRC531 and the SLRC400 Parallel microprocessor interface with internal address latch and IRQ line SPI compatibility Flexible interrupt handling Automatic detection of parallel microprocessor interface type 64-byte send and receive FIFO buffer Hard reset with low power function Software controlled Power-down mode Programmable timer Unique serial number User programmable start-up configuration Bit-oriented and byte oriented framing Independent power supply pins for analog, digital and transmitter modules Internal oscillator buffer optimized for low phase jitter enables 13.56 MHz quartz connection Clock frequency filtering 3.3 V to 5 V operation for transmitter in short range and proximity applications 3.3 V or 5 V operation for the digital module 4. Applications Electronic payment systems Identification systems Access control systemsCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 3 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Subscriber services Banking systems Digital content systems 5. Quick reference data 6. Ordering information Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit Tamb ambient temperature 40 - +150 C Tstg storage temperature 40 - +150 C VDDD digital supply voltage 0.5 5 6 V VDDA analog supply voltage 0.5 5 6 V VDD(TVDD) TVDD supply voltage 0.5 5 6 V Vi input voltage (absolute value) on any digital pin to DVSS 0.5 - VDDD + 0.5 V on pin RX to AVSS 0.5 - VDDA + 0.5 V ILI input leakage current 1.0 - 1.0 mA IDD(TVDD) TVDD supply current continuous wave - - 150 mA Table 2. Ordering information Type number Package Name Description Version CLRC63201T/0FE SO32 plastic small outline package; 32 leads; body width 7.5 mm SOT287-1CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 4 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 7. Block diagram Fig 1. CLRC632 block diagram 001aaj629 FIFO CONTROL 64-BYTE FIFO MASTER KEY BUFFER CRYPTO1 UNIT CONTROL REGISTER BANK NWR NRD NCS ALE A0 A1 A2 10 11 9 21 22 23 24 13 14 15 16 17 18 19 20 AD0 to AD7/D0 to D7 STATE MACHINE COMMAND REGISTER PROGRAMMABLE TIMER INTERRUPT CONTROL CRC16/CRC8 GENERATION AND CHECK PARALLEL/SERIAL CONVERTER BIT COUNTER PARITY GENERATION AND CHECK FRAME GENERATION AND CHECK SERIAL DATA SWITCH BIT DECODING BIT ENCODING 32 × 16-BYTE EEPROM EEPROM ACCESS CONTROL 32-BIT PSEUDO RANDOM GENERATOR AMPLITUDE RATING CLOCK GENERATION, FILTERING AND DISTRIBUTION OSCILLATOR LEVEL SHIFTERS CORRELATION AND REFERENCE BIT DECODING VOLTAGE Q-CHANNEL AMPLIFIER Q-CHANNEL DEMODULATOR I-CHANNEL ANALOG AMPLIFIER TEST MULTIPLEXER I-CHANNEL DEMODULATOR PARALLEL INTERFACE CONTROL (INCLUDING AUTOMATIC INTERFACE DETECTION AND SYNCHRONISATION) VOLTAGE MONITOR AND POWER ON DETECT DVDD RSTPD Q-CLOCK GENERATION TRANSMITTER CONTROL GND GND VMID AUX RX TVSS TX1 TX2 TVDD 30 27 29 8 5 7 6 V V POWER ON DETECT OSCIN AVDD AVSS OSCOUT IRQ MFIN MFOUT DVSS 25 31 1 26 28 32 2 3 4 12 RESET CONTROL POWER DOWN CONTROLCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 5 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 8. Pinning information 8.1 Pin description Fig 2. CLRC632 pin configuration CLRC632 OSCIN OSCOUT IRQ RSTPD MFIN VMID MFOUT RX TX1 AVSS TVDD AUX TX2 AVDD TVSS DVDD NCS A2/SCK NWR/R/NW/nWrite A1 NRD/NDS/nDStrb A0/nWait/MOSI DVSS ALE/AS/nAStrb/NSS AD0/D0 D7/AD7 AD1/D1 D6/AD6 AD2/D2 D5/AD5 AD3/D3 D4/AD4 001aaj630 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 17 20 19 22 21 24 23 26 25 32 31 30 29 28 27 Table 3. Pin description Pin Symbol Type[1] Description 1 OSCIN I oscillator/clock inputs: crystal oscillator input to the oscillator’s inverting amplifier externally generated clock input; fosc = 13.56 MHz 2 IRQ O interrupt request generates an output signaling an interrupt event 3 MFIN I ISO/IEC 14443 A MIFARE serial data interface input 4[2] MFOUT O interface outputs used as follows: MIFARE: generates serial data ISO/IEC 14443 A I-CODE: generates serial data based on I-CODE1 and ISO/IEC 15693 5 TX1 O transmitter 1 modulated carrier output; 13.56 MHz 6 TVDD P transmitter power supply for the TX1 and TX2 output stages 7 TX2 O transmitter 2 modulated carrier output; 13.56 MHz 8 TVSS G transmitter ground for the TX1 and TX2 output stages 9 NCS I not chip select input is used to select and activate the CLRC632’s microprocessor interface 10[3] NWR I not write input generates the strobe signal for writing data to the CLRC632 registers when applied to pins D0 to D7 R/NW I read not write input is used to switch between read or write cycles nWrite I not write input selects the read or write cycle to be performedCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 6 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution [1] Pin types: I = Input, O = Output, I/O = Input/Output, P = Power and G = Ground. [2] The SLRC400 uses pin name SIGOUT for pin MFOUT. The CLRC632 functionality includes test functions for the SLRC400 using pin MFOUT. [3] These pins provide different functionality depending on the selected microprocessor interface type (see Section 9.1 on page 7 for detailed information). 11[3] NRD I not read input generates the strobe signal for reading data from the CLRC632 registers when applied to pins D0 to D7 NDS I not data strobe input generates the strobe signal for the read and write cycles nDStrb I not data strobe input generates the strobe signal for the read and write cycles 12 DVSS G digital ground 13 D0 O SPI master in, slave out output 13 to 20[3] D0 to D7 I/O 8-bit bidirectional data bus input/output on pins D0 to D7 AD0 to AD7 I/O 8-bit bidirectional address and data bus input/output on pins AD0 to AD7 21[3] ALE I address latch enable input for pins AD0 to AD5; HIGH latches the internal address AS I address strobe input for pins AD0 to AD5; HIGH latches the internal address nAStrb I not address strobe input for pins AD0 to AD5; LOW latches the internal address NSS I not slave select strobe input for SPI communication 22[3] A0 I address line 0 is the address register bit 0 input nWait O not wait output: LOW starts an access cycle HIGH ends an access cycle MOSI I SPI master out, slave in 23 A1 I address line 1 is the address register bit 1 input 24[3] A2 I address line 2 is the address register bit 2 input SCK I SPI serial clock input 25 DVDD P digital power supply 26 AVDD P analog power supply for pins OSCIN, OSCOUT, RX, VMID and AUX 27 AUX O auxiliary output is used to generate analog test signals. The output signal is selected using the TestAnaSelect register’s TestAnaOutSel[4:0] bits 28 AVSS G analog ground 29 RX I receiver input is used as the card response input. The carrier is load modulated at 13.56 MHz, drawn from the antenna circuit 30 VMID P internal reference voltage pin provides the internal reference voltage as a supply Remark: It must be connected to a 100 nF block capacitor connected between pin VMID and ground 31 RSTPD I reset and power-down input: HIGH: the internal current sinks are switched off, the oscillator is inhibited and the input pads are disconnected LOW (negative edge): start internal reset phase 32 OSCOUT O crystal oscillator output for the oscillator’s inverting amplifier Table 3. Pin description …continued Pin Symbol Type[1] DescriptionCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 7 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9. Functional description 9.1 Digital interface 9.1.1 Overview of supported microprocessor interfaces The CLRC632 supports direct interfacing to various 8-bit microprocessors. Alternatively, the CLRC632 can be connected to a PC’s Enhanced Parallel Port (EPP). Table 4 shows the parallel interface signals supported by the CLRC632. 9.1.2 Automatic microprocessor interface detection After a Power-On or Hard reset, the CLRC632 resets parallel microprocessor interface mode and detects the microprocessor interface type. The CLRC632 identifies the microprocessor interface using the logic levels on the control pins. This is performed using a combination of fixed pin connections and the dedicated Initialization routine (see Section 9.7.4 on page 30). Table 4. Supported microprocessor and EPP interface signals Bus control signals Bus Separated address and data bus Multiplexed address and data bus Separated read and write strobes control NRD, NWR, NCS NRD, NWR, NCS, ALE address A0, A1, A2 AD0, AD1, AD2, AD3, AD4, AD5 data D0 to D7 AD0 to AD7 Common read and write strobe control R/NW, NDS, NCS R/NW, NDS, NCS, AS address A0, A1, A2 AD0, AD1, AD2, AD3, AD4, AD5 data D0 to D7 AD0 to AD7 Common read and write strobe with handshake (EPP) control - nWrite, nDStrb, nAStrb, nWait address - AD0, AD1, AD2, AD3, AD4, AD5 data - AD0 to AD7CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 8 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.1.3 Connection to different microprocessor types The connection to various microprocessor types is shown in Table 5. 9.1.3.1 Separate read and write strobe Refer to Section 13.4.1 on page 102 for timing specification. Table 5. Connection scheme for detecting the parallel interface type CLRC632 pins Parallel interface type and signals Separated read/write strobe Common read/write strobe Dedicated address bus Multiplexed address bus Dedicated address bus Multiplexed address bus Multiplexed address bus with handshake ALE HIGH ALE HIGH AS nAStrb A2 A2 LOW A2 LOW HIGH A1 A1 HIGH A1 HIGH HIGH A0 A0 HIGH A0 LOW nWait NRD NRD NRD NDS NDS nDStrb NWR NWR NWR R/NW R/NW nWrite NCS NCS NCS NCS NCS LOW D7 to D0 D7 to D0 AD7 to AD0 D7 to D0 AD7 to AD0 AD7 to AD0 Fig 3. Connection to microprocessor: separate read and write strobes 001aak607 address bus (A3 to An) NCS A0 to A2 address bus (A0 to A2) D0 to D7 ALE data bus (D0 to D7) HIGH NRD Read strobe (NRD) NWR Write strobe (NWR) DEVICE ADDRESS DECODER non-multiplexed address NCS AD0 to AD7 ALE multiplexed address/data (AD0 to AD7) address latch enable (ALE) NRD Read strobe (NRD) NWR Write strobe (NWR) A2 LOW A1 HIGH A0 HIGH DEVICE ADDRESS DECODERCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 9 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.1.3.2 Common read and write strobe Refer to Section 13.4.2 on page 103 for timing specification. 9.1.3.3 Common read and write strobe: EPP with handshake Refer to Section 13.4.3 on page 104 for timing specification. Remark: In the EPP standard a chip select signal is not defined. To cover this situation, the status of the NCS pin can be used to inhibit the nDStrb signal. If this inhibitor is not used, it is mandatory that pin NCS is connected to pin DVSS. Remark: After each Power-On or Hard reset, the nWait signal on pin A0 is high-impedance. nWait is defined as the first negative edge applied to the nAStrb pin after the reset phase. The CLRC632 does not support Read Address Cycle. 9.1.4 Serial Peripheral Interface The CLRC632 provides compatibility with the 5-wire Serial Peripheral Interface (SPI) standard and acts as a slave during the SPI communication. The SPI clock signal SCK must be generated by the master. Data communication from the master to the slave uses the MOSI line. The MISO line sends data from the CLRC632 to the master. Fig 4. Connection to microprocessor: common read and write strobes 001aak608 address bus (A3 to An) NCS A0 to A2 address bus (A0 to A2) D0 to D7 ALE data bus (D0 to D7) HIGH NRD Data strobe (NDS) NWR Read/Write (R/NW) DEVICE ADDRESS DECODER non-multiplexed address NCS AD0 to AD7 ALE multiplexed address/data (AD0 to AD7) Address strobe (AS) NRD Data strobe (NDS) NWR Read/Write (R/NW) A2 LOW A1 HIGH A0 LOW DEVICE ADDRESS DECODER Fig 5. Connection to microprocessor: EPP common read/write strobes and handshake 001aak609 LOW NCS AD0 to AD7 ALE multiplexed address/data (AD0 to AD7) Address strobe (nAStrb) NRD Data strobe (nDStrb) NWR Read/Write (nWrite) A2 HIGH A1 HIGH A0 nWait DEVICECLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 10 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Figure 6 shows the microprocessor connection to the CLRC632 using SPI. Remark: The SPI implementation for CLRC632 conforms to the SPI standard and ensures that the CLRC632 can only be addressed as a slave. 9.1.4.1 SPI read data The structure shown in Table 7 must be used to read data using SPI. It is possible to read up to n-data bytes. The first byte sent defines both, the mode and the address. The address byte must meet the following criteria: • the Most Significant Bit (MSB) of the first byte sets the mode. To read data from the CLRC632 the MSB is set to logic 1 • bits [6:1] define the address • the Least Significant Bit (LSB) should be set to logic 0. As shown in Table 8, all the bits of the last byte sent are set to logic 0. Table 6. SPI compatibility CLRC632 pins SPI pins ALE NSS A2 SCK A1 LOW A0 MOSI NRD HIGH NWR HIGH NCS LOW D7 to D1 do not connect D0 MISO Fig 6. Connection to microprocessor: SPI 001aak610 LOW NCS D0 ALE A2 SCK A1 LOW MOSI NSS A0 MISO DEVICE Table 7. SPI read data Pin Byte 0 Byte 1 Byte 2 ... Byte n Byte n + 1 MOSI address 0 address 1 address 2 ... address n 00 MISO XX data 0 data 1 ... data n 1 data nCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 11 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution [1] All reserved bits must be set to logic 0. 9.1.4.2 SPI write data The structure shown in Table 9 must be used to write data using SPI. It is possible to write up to n-data bytes. The first byte sent defines both the mode and the address. The address byte must meet the following criteria: • the MSB of the first byte sets the mode. To write data to the CLRC632, the MSB is set to logic 0 • bits [6:1] define the address • the LSB should be set to logic 0. SPI write mode writes all data to the address defined in byte 0 enabling effective write cycles to the FIFO buffer. [1] All reserved bits must be set to logic 0. Remark: The data bus pins D7 to D0 must be disconnected. Refer to Section 13.4.4 on page 106 for the timing specification. Table 8. SPI read address Address (MOSI) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) byte 0 1 address address address address address address reserved byte 1 to byte n reserved address address address address address address reserved byte n + 1 0 0 0 0 0 0 0 0 Table 9. SPI write data Byte 0 Byte 1 Byte 2 ... Byte n Byte n + 1 MOSI address data 0 data 1 ... data n 1 data n MISO XX XX XX ... XX XX Table 10. SPI write address Address line (MOSI) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) byte 0 0 address address address address address address reserved byte 1 to byte n+1 data data data data data data data dataCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 12 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.2 Memory organization of the EEPROM Table 11. EEPROM memory organization diagram Block Byte address Access Memory content Refer to Position Address 0 0 00h to 0Fh R product information field Section 9.2.1 on page 13 1 1 10h to 1Fh R/W StartUp register initialization file Section 9.2.2.1 on page 14 2 2 20h to 2Fh R/W 3 3 30h to 3Fh R/W register initialization file user data or second initialization Section 9.2.2.3 “Register initialization file (read/write)” on page 16 4 4 40h to 4Fh R/W 5 5 50h to 5Fh R/W 6 6 60h to 6Fh R/W 7 7 70h to 7Fh R/W 8 8 80h to 8Fh W keys for Crypto1 Section 9.2.3 on page 18 9 9 90h to 9Fh W 10 A A0h to AFh W 11 B B0h to BFh W 12 C C0h to CFh W 13 D D0h to DFh W 14 E E0h to EFh W 15 F F0h to FFh W 16 10 100h to 10Fh W 17 11 110h to 11Fh W 18 12 120h to 12Fh W 19 13 130h to 13Fh W 20 14 140h to 14Fh W 21 15 150h to 15Fh W 22 16 160h to 16Fh W 23 17 170h to 17Fh W 24 18 180h to 18Fh W 25 19 190h to 19Fh W 26 1A 1A0h to 1AFh W 27 1B 1B0h to 1BFh W 28 1C 1C0h to 1CFh W 29 1D 1D0h to 1DFh W 30 1E 1E0h to 1EFh W 31 1F 1F0h to 1FFh WCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 13 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.2.1 Product information field (read only) [1] Byte 4 contains the current version number. 9.2.2 Register initialization files (read/write) Register initialization from address 10h to address 2Fh is performed automatically during the initializing phase (see Section 9.7.3 on page 30) using the StartUp register initialization file. In addition, the CLRC632 registers can be initialized using values from the register initialization file when the LoadConfig command is executed (see Section 11.5.1 on page 95). Table 12. Product information field Byte Symbol Access Value Description 15 CRC R - the content of the product information field is secured using a CRC byte which is checked during start-up 14 RsMaxP R - maximum source resistance for the p-channel driver transistor on pins TX1 and TX2 The source resistance of the p-channel driver transistors of pin TX1 and TX2 can be adjusted using the value GsCfgCW[5:0] in the CwConductance register (see Section 9.9.3 on page 32). The mean value of the maximum adjustable source resistance for pins TX1 and TX2 is stored as an integer value in in this byte. Typical values for RsMaxP are between 60 to 140 . This value is denoted as maximum adjustable source resistance RS(ref)maxP and is measured by setting the CwConductance register’s GsCfgCW[5:0] bits to 01h. 13 to 12 Internal R - two bytes for internal trimming parameters 11 to 8 Product Serial Number R - a unique four byte serial number for the device 7 to 5 reserved R - 4 to 0 Product Type Identification R - the CLRC632 is a member of a new family of highly integrated reader ICs. Each member of the product family has a unique product type identification. The value of the product type identification is shown in Table 13. Table 13. Product type identification definition Definition Product type identification bytes Byte 0 1 2 3 4[1] Value 30h FFh FFh 0Fh XXhCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 14 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Remark: The following points apply to initialization: • the Page register (addressed using 10h, 18h, 20h, 28h) is skipped and not initialized. • make sure that all PreSetxx registers are not changed. • make sure that all register bits that are reserved are set to logic 0. 9.2.2.1 StartUp register initialization file (read/write) The EEPROM memory block address 1 and 2 contents are used to automatically set the register subaddresses 10h to 2Fh during the initialization phase. The default values stored in the EEPROM during production are shown in Section 9.2.2.2 “Factory default StartUp register initialization file”. The byte assignment is shown in Table 14. 9.2.2.2 Factory default StartUp register initialization file During the production tests, the StartUp register initialization file is initialized using the default values shown in Table 15. During each power-up and initialization phase, these values are written to the CLRC632’s registers. Table 14. Byte assignment for register initialization at start-up EEPROM byte address Register address Remark 10h (block 1, byte 0) 10h skipped 11h 11h copied … …… 2Fh (block 2, byte 15) 2Fh copiedCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 15 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Remark: The CLRC632 default configuration supports the MIFARE and ISO/IEC 14443 A communication scheme. Memory addresses 3 to 7 may be used for user-specific initialization files such as I-CODE1, ISO/IEC 15693 or ISO/IEC 14443 B. Table 15. Shipment content of StartUp configuration file EEPROM byte address Register address Value Symbol Description 10h 10h 00h Page free for user 11h 11h 58h TxControl transmitter pins TX1 and TX2 are switched off, bridge driver configuration, modulator driven from internal digital circuitry 12h 12h 3Fh CwConductance source resistance of TX1 and TX2 is set to minimum 13h 13h 3Fh ModConductance defines the output conductance 14h 14h 19h CoderControl ISO/IEC 14443 A coding is set 15h 15h 13h ModWidth pulse width for Miller pulse coding is set to standard configuration 16h 16h 3Fh ModWidthSOF pulse width of Start Of Frame (SOF) 17h 17h 3Bh TypeFraming ISO/IEC 14443 A framing is set 18h 18h 00h Page free for user 19h 19h 73h RxControl1 ISO/IEC 14443 A is set and internal amplifier gain is maximum 1Ah 1Ah 08h DecoderControl bit-collisions always evaluate to HIGH in the data bit stream 1Bh 1Bh ADh BitPhase BitPhase[7:0] is set to standard configuration 1Ch 1Ch FFh RxThreshold MinLevel[3:0] and CollLevel[3:0] are set to maximum 1Dh 1Dh 1Eh BPSKDemControl ISO/IEC 14443 A is set 1Eh 1Eh 41h RxControl2 use Q-clock for the receiver, automatic receiver off is switched on, decoder is driven from internal analog circuitry 1Fh 1Fh 00h ClockQControl automatic Q-clock calibration is switched on 20h 20h 00h Page free for user 21h 21h 06h RxWait frame guard time is set to six bit-clocks 22h 22h 03h ChannelRedundancy channel redundancy is set using ISO/IEC 14443 A 23h 23h 63h CRCPresetLSB CRC preset value is set using ISO/IEC 14443 A 24h 24h 63h CRCPresetMSB CRC preset value is set using ISO/IEC 14443 A 25h 25h 00h TimeSlotPeriod defines the time for the I-CODE1 time slots 26h 26h 00h MFOUTSelect pin MFOUT is set LOW 27h 27h 00h PreSet27 - 28h 28h 00h Page free for user 29h 29h 08h FIFOLevel WaterLevel[5:0] FIFO buffer warning level is set to standard configuration 2Ah 2Ah 07h TimerClock TPreScaler[4:0] is set to standard configuration, timer unit restart function is switched off 2Bh 2Bh 06h TimerControl Timer is started at the end of transmission, stopped at the beginning of reception 2Ch 2Ch 0Ah TimerReload TReloadValue[7:0]: the timer unit preset value is set to standard configuration 2Dh 2Dh 02h IRQPinConfig pin IRQ is set to high-impedance 2Eh 2Eh 00h PreSet2E - 2Fh 2Fh 00h PreSet2F -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 16 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.2.2.3 Register initialization file (read/write) The EEPROM memory content from block address 3 to 7 can initialize register sub addresses 10h to 2Fh when the LoadConfig command is executed (see Section 11.5.1 on page 95). This command requires the EEPROM starting byte address as a two byte argument for the initialization procedure. The byte assignment is shown in Table 16. The register initialization file is large enough to hold values for two initialization sets and up to one block (16-byte) of user data. The startup configuration could be adapted to the I-CODE1 StartUp configuration and stored in register block address 3 and 4, providing additional flexibility. Remark: The register initialization file can be read/written by users and these bytes can be used to store other user data. After each power-up, the default configuration enables the MIFARE and ISO/IEC 14443 A protocol. 9.2.2.4 Content of I-CODE1 and ISO/IEC 15693 StartUp register values Table 17 gives an overview of the StartUp values for I-CODE1 and ISO/IEC 15693 communication. Table 16. Byte assignment for register initialization at startup EEPROM byte address Register address Remark EEPROM starting byte address 10h skipped EEPROM + 1 starting byte address 11h copied … … EEPROM + 31 starting byte address 2Fh copiedCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 17 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Table 17. Content of I-CODE1 startup configuration EEPROM byte address Register address Value Symbol Description 30h 10h 00h Page free for user 31h 11h 58h TxControl transmitter pins TX1 and TX2 switched off, bridge driver configuration, modulator driven from internal digital circuitry 32h 12h 3Fh CwConductance source resistance (RS) of TX1 and TX2 to minimum 33h 13h 05h ModGsCfgh source resistance (RS) of TX1 and TX2 at the time of modulation, to determine the modulation index 34h 14h 2Ch CoderControl selects the bit coding mode and the framing during transmission 35h 15h 3Fh ModWidth pulse width for code used (1 out of 256, NRZ or 1 out of 4) pulse coding is set to standard configuration 36h 16h 3Fh ModWidthSOF pulse width of SOF 37h 17h 00h TypeBFraming - 38h 18h 00h Page free for user 39h 19h 8Bh RxControl1 amplifier gain is maximum 3Ah 1Ah 00h DecoderControl bit-collisions always evaluate to HIGH in the data bit stream 3Bh 1Bh 54h BitPhase BitPhase[7:0] is set to standard configuration 3Ch 1Ch 68h RxThreshold: MinLevel[3:0] and CollLevel[3:0] are set to maximum 3Dh 1Dh 00h BPSKDemControl - 3Eh 1Eh 41h RxControl2 use Q-clock for the receiver, automatic receiver off is switched on, decoder is driven from internal analog circuitry 3Fh 1Fh 00h ClockQControl automatic Q-clock calibration is switched on 40h 20h 00h Page free for user 41h 21h 08h RxWait frame guard time is set to eight bit-clocks 42h 22h 0Ch ChannelRedundancy channel redundancy is set using I-CODE1 43h 23h FEh CRCPresetLSB CRC preset value is set using I-CODE1 44h 24h FFh CRCPresetMSB CRC preset value is set using I-CODE1 45h 25h 00h TimeSlot Period defines the time for the I-CODE1 time slots 46h 26h 00h MFOUTSelect pin MFOUT is set LOW 47h 27h 00h PreSet27 - 48h 28h 00h Page free for user 49h 29h 3Eh FIFOLevel WaterLevel[5:0] FIFO buffer warning level is set to standard configuration 4Ah 2Ah 0Bh TimerClock TPreScaler[4:0] is set to standard configuration, timer unit restart function is switched off 4Bh 2Bh 02h TimerControl Timer is started at the end of transmission, stopped at the beginning of reception 4Ch 2Ch 00h TimerReload the timer unit preset value is set to standard configuration 4Dh 2Dh 02h IRQPinConfig pin IRQ is set to high-impedance 4Eh 2Eh 00h PreSet2E - 4Fh 2Fh 00h PreSet2F -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 18 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.2.3 Crypto1 keys (write only) MIFARE security requires specific cryptographic keys to encrypt data stream communication on the contactless interface. These keys are called Crypto1 keys. 9.2.3.1 Key format Keys stored in the EEPROM are written in a specific format. Each key byte must be split into lower four bits k0 to k3 (lower nibble) and the higher four bits k4 to k7 (higher nibble). Each nibble is stored twice in one byte and one of the two nibbles is bit-wise inverted. This format is a precondition for successful execution of the LoadKeyE2 (see Section 11.7.1 on page 97) and LoadKey commands (see Section 11.7.2 on page 97). Using this format, 12 bytes of EEPROM memory are needed to store a 6-byte key. This is shown in Figure 7. Example: The value for the key must be written to the EEPROM. • If the key was: A0h A1h A2h A3h A4h A5h then • 5Ah F0h 5Ah E1h 5Ah D2h 5Ah C3h 5Ah B4h 5Ah A5h would be written. Remark: It is possible to load data for other key formats into the EEPROM key storage location. However, it is not possible to validate card authentication with data which will cause the LoadKeyE2 command (see Section 11.7.1 on page 97) to fail. 9.2.3.2 Storage of keys in the EEPROM The CLRC632 reserves 384 bytes of memory in the EEPROM for the Crypto1 keys. No memory segmentation is used to mirror the 12-byte structure of key storage. Thus, every byte of the dedicated memory area can be the start of a key. Example: If the key loading cycle starts at the last byte address of an EEPROM block, (for example, key byte 0 is stored at 12Fh), the next bytes are stored in the next EEPROM block, for example, key byte 1 is stored at 130h, byte 2 at 131h up to byte 11 at 13Ah. Based on the 384 bytes of memory and a single key needing 12 bytes, then up to 32 different keys can be stored in the EEPROM. Remark: It is not possible to load a key exceeding the EEPROM byte location 1FFh. Fig 7. Key storage format 001aak640 Master key byte 0 (LSB) Master key bits EEPROM byte address Example k7 k6 k5 k4 k7 k6 k5 k4 n 5Ah k3 k2 k1 k0 k3 k2 k1 k0 n + 1 F0h 1 k7 k6 k5 k4 k7 k6 k5 k4 n + 2 5Ah k3 k2 k1 k0 k3 k2 k1 k0 n + 3 E1h 5 (MSB) k7 k6 k5 k4 k7 k6 k5 k4 n + 10 5Ah k3 k2 k1 k0 k3 k2 k1 k0 n + 11 A5hCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 19 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.3 FIFO buffer An 8 64 bit FIFO buffer is used in the CLRC632 to act as a parallel-to-parallel converter. It buffers both the input and output data streams between the microprocessor and the internal circuitry of the CLRC632. This makes it possible to manage data streams up to 64 bytes long without needing to take timing constraints into account. 9.3.1 Accessing the FIFO buffer 9.3.1.1 Access rules The FIFO buffer input and output data bus is connected to the FIFOData register. Writing to this register stores one byte in the FIFO buffer and increments the FIFO buffer write pointer. Reading from this register shows the FIFO buffer contents stored at the FIFO buffer read pointer and increments the FIFO buffer read pointer. The distance between the write and read pointer can be obtained by reading the FIFOLength register. When the microprocessor starts a command, the CLRC632 can still access the FIFO buffer while the command is running. Only one FIFO buffer has been implemented which is used for input and output. Therefore, the microprocessor must ensure that there are no inadvertent FIFO buffer accesses. Table 18 gives an overview of FIFO buffer access during command processing. 9.3.2 Controlling the FIFO buffer In addition to writing to and reading from the FIFO buffer, the FIFO buffer pointers can be reset using the FlushFIFO bit. This changes the FIFOLength[6:0] value to zero, bit FIFOOvfl is cleared and the stored bytes are no longer accessible. This enables the FIFO buffer to be written with another 64 bytes of data. Table 18. FIFO buffer access Active command FIFO buffer Remark p Write p Read StartUp - - Idle - - Transmit yes - Receive - yes Transceive yes yes the microprocessor has to know the state of the command (transmitting or receiving) WriteE2 yes - ReadE2 yes yes the microprocessor has to prepare the arguments, afterwards only reading is allowed LoadKeyE2 yes - LoadKey yes - Authent1 yes - Authent2 - - LoadConfig yes - CalcCRC yes -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 20 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.3.3 FIFO buffer status information The microprocessor can get the following FIFO buffer status data: • the number of bytes stored in the FIFO buffer: bits FIFOLength[6:0] • the FIFO buffer full warning: bit HiAlert • the FIFO buffer empty warning: bit LoAlert • the FIFO buffer overflow warning: bit FIFOOvfl. Remark: Setting the FlushFIFO bit clears the FIFOOvfl bit. The CLRC632 can generate an interrupt signal when: • bit LoAlertIRq is set to logic 1 and bit LoAlert = logic 1, pin IRQ is activated. • bit HiAlertIRq is set to logic 1 and bit HiAlert = logic 1, pin IRQ activated. The HiAlert flag bit is set to logic 1 only when the WaterLevel[5:0] bits or less can be stored in the FIFO buffer. The trigger is generated by Equation 1: (1) The LoAlert flag bit is set to logic 1 when the FIFOLevel register’s WaterLevel[5:0] bits or less are stored in the FIFO buffer. The trigger is generated by Equation 2: (2) 9.3.4 FIFO buffer registers and flags Table 18 shows the related FIFO buffer flags in alphabetic order. 9.4 Interrupt request system The CLRC632 indicates interrupt events by setting the PrimaryStatus register bit IRq (see Section 10.5.1.4 “PrimaryStatus register” on page 51) and activating pin IRQ. The signal on pin IRQ can be used to interrupt the microprocessor using its interrupt handling capabilities ensuring efficient microprocessor software. HiAlert 64 FIFOLength = – WaterLevel LoAlert FIFOLength WaterLevel = Table 19. Associated FIFO buffer registers and flags Flags Register name Bit Register address FIFOLength[6:0] FIFOLength 6 to 0 04h FIFOOvfl ErrorFlag 4 0Ah FlushFIFO Control 0 09h HiAlert PrimaryStatus 1 03h HiAlertIEn InterruptEn 1 06h HiAlertIRq InterruptRq 1 07h LoAlert PrimaryStatus 0 03h LoAlertIEn InterruptEn 0 06h LoAlertIRq InterruptRq 0 07h WaterLevel[5:0] FIFOLevel 5 to 0 29hCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 21 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.4.1 Interrupt sources overview Table 20 shows the integrated interrupt flags, related source and setting condition. The interrupt TimerIRq flag bit indicates an interrupt set by the timer unit. Bit TimerIRq is set when the timer decrements from one down to zero (bit TAutoRestart disabled) or from one to the TReLoadValue[7:0] with bit TAutoRestart enabled. Bit TxIRq indicates interrupts from different sources and is set as follows: • the transmitter automatically sets the bit TxIRq interrupt when it is active and its state changes from sending data to transmitting the end of frame pattern • the CRC coprocessor sets the bit TxIRq after all data from the FIFO buffer has been processed indicated by bit CRCReady = logic 1 • when EEPROM programming is finished, the bit TxIRq is set and is indicated by bit E2Ready = logic 1 The RxIRq flag bit indicates an interrupt when the end of the received data is detected. The IdleIRq flag bit is set when a command finishes and the content of the Command register changes to Idle. When the FIFO buffer reaches the HIGH-level indicated by the WaterLevel[5:0] value (see Section 9.3.3 on page 20) and bit HiAlert = logic 1, then the HiAlertIRq flag bit is set to logic 1. When the FIFO buffer reaches the LOW-level indicated by the WaterLevel[5:0] value (see Section 9.3.3 on page 20) and bit LoAlert = logic 1, then LoAlertIRq flag bit is set to logic 1. 9.4.2 Interrupt request handling 9.4.2.1 Controlling interrupts and getting their status The CLRC632 informs the microprocessor about the interrupt request source by setting the relevant bit in the InterruptRq register. The relevance of each interrupt request bit as source for an interrupt can be masked by the InterruptEn register interrupt enable bits. Table 20. Interrupt sources Interrupt flag Interrupt source Trigger action TimerIRq timer unit timer counts from 1 to 0 TxIRq transmitter a data stream, transmitted to the card, ends CRC coprocessor all data from the FIFO buffer has been processed EEPROM all data from the FIFO buffer has been programmed RxIRq receiver a data stream, received from the card, ends IdleIRq Command register command execution finishes HiAlertIRq FIFO buffer FIFO buffer is full LoAlertIRq FIFO buffer FIFO buffer is empty Table 21. Interrupt control registers Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 InterruptEn SetIEn reserved TimerIEn TxIEn RxIEn IdleIEn HiAlertIEn LoAlertIEn InterruptRq SetIRq reserved TimerIRq TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRqCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 22 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution If any interrupt request flag is set to logic 1 (showing that an interrupt request is pending) and the corresponding interrupt enable flag is set, the PrimaryStatus register IRq flag bit is set to logic 1. Different interrupt sources can activate simultaneously because all interrupt request bits are OR’ed, coupled to the IRq flag and then forwarded to pin IRQ. 9.4.2.2 Accessing the interrupt registers The interrupt request bits are automatically set by the CLRC632’s internal state machines. In addition, the microprocessor can also set or clear the interrupt request bits as required. A special implementation of the InterruptRq and InterruptEn registers enables changing an individual bit status without influencing any other bits. If an interrupt register is set to logic 1, bit SetIxx and the specific bit must both be set to logic 1 at the same time. Vice versa, if a specific interrupt flag is cleared, zero must be written to the SetIxx and the interrupt register address must be set to logic 1 at the same time. If a content bit is not changed during the setting or clearing phase, zero must be written to the specific bit location. Example: Writing 3Fh to the InterruptRq register clears all bits. SetIRq is set to logic 0 while all other bits are set to logic 1. Writing 81h to the InterruptRq register sets LoAlertIRq to logic 1 and leaves all other bits unchanged. 9.4.3 Configuration of pin IRQ The logic level of the IRq flag bit is visible on pin IRQ. The signal on pin IRQ can also be controlled using the following IRQPinConfig register bits. • bit IRQInv: the signal on pin IRQ is equal to the logic level of bit IRq when this bit is set to logic 0. When set to logic 1, the signal on pin IRQ is inverted with respect to bit IRq. • bit IRQPushPull: when set to logic 1, pin IRQ has CMOS output characteristics. When it is set to logic 0, it is an open-drain output which requires an external resistor to achieve a HIGH-level at pin IRQ. Remark: During the reset phase (see Section 9.7.2 on page 29) bit IRQInv is set to logic 1 and bit IRQPushPull is set to logic 0. This results in a high-impedance on pin IRQ.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 23 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.4.4 Register overview interrupt request system Table 22 shows the related interrupt request system flags in alphabetic order. 9.5 Timer unit The timer derives its clock from the 13.56 MHz on-board chip clock. The microprocessor can use this timer to manage timing-relevant tasks. The timer unit may be used in one of the following configurations: • Timeout counter • WatchDog counter • Stopwatch • Programmable one shot • Periodical trigger The timer unit can be used to measure the time interval between two events or to indicate that a specific timed event occurred. The timer is triggered by events but does not influence any event (e.g. a time-out during data receiving does not automatically influence the receiving process). Several timer related flags can be set and these flags can be used to generate an interrupt. Table 22. Associated Interrupt request system registers and flags Flags Register name Bit Register address HiAlertIEn InterruptEn 1 06h HiAlertIRq InterruptRq 1 07h IdleIEn InterruptEn 2 06h IdleIRq InterruptRq 2 07h IRq PrimaryStatus 3 03h IRQInv IRQPinConfig 1 07h IRQPushPull IRQPinConfig 0 07h LoAlertIEn InterruptEn 0 06h LoAlertIRq InterruptRq 0 07h RxIEn InterruptEn 3 06h RxIRq InterruptRq 3 07h SetIEn InterruptEn 7 06h SetIRq InterruptRq 7 07h TimerIEn InterruptEn 5 06h TimerIRq InterruptRq 5 07h TxIEn InterruptEn 4 06h TxIRq InterruptRq 4 07hCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 24 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.5.1 Timer unit implementation 9.5.1.1 Timer unit block diagram Figure 8 shows the block diagram of the timer module. The timer unit is designed, so that events when combined with enabling flags start or stop the counter. For example, setting bit TStartTxBegin = logic 1 enables control of received data with the timer unit. In addition, the first received bit is indicated by the TxBegin event. This combination starts the counter at the defined TReloadValue[7:0]. The timer stops automatically when the counter value is equal to zero or if a defined stop event happens. 9.5.1.2 Controlling the timer unit The main part of the timer unit is a down-counter. As long as the down-counter value is not zero, it decrements its value with each timer clock cycle. If the TAutoRestart flag is enabled, the timer does not decrement down to zero. On reaching value 1, the timer reloads the next clock function with the TReloadValue[7:0]. Fig 8. Timer module block diagram 001aak611 TxEnd Event TAutoRestart TRunning TStartTxEnd TStartNow S RQ START COUNTER/ PARALLEL LOAD STOP COUNTER TPreScaler[4:0] TimerValue[7:0] Counter = 0 ? to interrupt logic: TimerIRq PARALLEL OUT PARALLEL IN TReloadValue[7:0] CLOCK DIVIDER COUNTER MODULE (x ≤ x − 1) TStopNow TxBegin Event TStartTxBegin TStopRxEnd RxEnd Event TStopRxBegin 13.56 MHz to parallel interface RxBegin Event QCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 25 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution The timer is started immediately by loading a value from the TimerReload register into the counter module. This is activated by one of the following events: • transmission of the first bit to the card (TxBegin event) with bit TStartTxBegin = logic 1 • transmission of the last bit to the card (TxEnd event) with bit TStartTxEnd = logic 1 • bit TStartNow is set to logic 1 by the microprocessor Remark: Every start event reloads the timer from the TimerReload register. Thus, the timer unit is re-triggered. The timer can be configured to stop on one of the following events: • receipt of the first valid bit from the card (RxBegin event) with bit TStopRxBegin = logic 1 • receipt of the last bit from the card (RxEnd event) with bit TStopRxEnd = logic 1 • the counter module has decremented down to zero and bit TAutoRestart = logic 0 • bit TStopNow is set to logic 1 by the microprocessor. Loading a new value, e.g. zero, into the TimerReload register or changing the timer unit while it is counting will not immediately influence the counter. In both cases, this is because this register only affects the counter content after a start event. If the counter is stopped when bit TStopNow is set, no TimerIRq is flagged. 9.5.1.3 Timer unit clock and period The timer unit clock is derived from the 13.56 MHz on-board chip clock using the programmable divider. Clock selection is made using the TimerClock register TPreScaler[4:0] bits based on Equation 3: (3) The values for the TPreScaler[4:0] bits are between 0 and 21 which results in a minimum periodic time (TTimerClock) of between 74 ns and 150 ms. The time period elapsed since the last start event is calculated using Equation 4: (4) This results in a minimum time period (tTimer) of between 74 ns and 40 s. 9.5.1.4 Timer unit status The SecondaryStatus register’s TRunning bit shows the timer’s status. Configured start events start the timer at the TReloadValue[7:0] and changes the status flag TRunning to logic 1. Conversely, configured stop events stop the timer and sets the TRunning status flag to logic 0. As long as status flag TRunning is set to logic 1, the TimerValue register changes on the next timer unit clock cycle. The TimerValue[7:0] bits can be read directly from the TimerValue register. fTimerClock 1 TTimerClock --------------------------- 2 TPreScaler 13.56 = = -------------------------- MHz tTimer TReLoadValue TimerValue – fTimerClock = ----------------------------------------------------------------------------- sCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 26 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.5.1.5 TimeSlotPeriod When sending I-CODE1 Quit frames, it is necessary to generate the exact chronological relationship to the start of the command frame. If at the end of command execution TimeSlotPeriod > 0, the TimeSlotPeriod starts. If the FIFO buffer contains data when the end of TimeSlotPeriod is reached, the data is sent. If the FIFO buffer is empty nothing happens. As long as the TimeSlotPeriod is > 0, the TimeSlotPeriod counter automatically starts on reaching the end. This forms the exact time relationship between the start and finish of the command frame used to generate and send I-CODE1 Quit frames. When the TimeSlotPeriod > 0, the next Frame starts with exactly the same interval TimeSlotPeriod/CoderRate delayed after each previous send frame. CoderRate defines the clock frequency of the encoder. If TimeSlotPeriod[7:0] = 0, the send function is not automatically triggered. The content of the TimeSlotPeriod register can be changed while it is running but the change is only effective after the next TimeSlotPeriod restart. Example: • CoderRate = 0 0.5 (~52.97 kHz) • The interval should be 8.458 ms for I-CODE1 standard mode Remark: The TimeSlotPeriodMSB bit is contained in the MFOUTSelect register. Remark: Set bit TxCRCEn to logic 0 before the Quit frame is sent. If TxCRCEn is not set to logic 0, the Quit frame is sent with a calculated CRC value. Use the CRC8 algorithm to calculate the Quit value. Fig 9. TimeSlotPeriod Table 23. TimeSlotPeriod I-CODE1 mode TimeSlotPeriod for TSP1 TimeSlotPeriod for TSP2 standard mode BFh 1BFh fast mode 5Fh 67h TimeSlotPeriod CoderRate Interval = = 52.97 kHz 8.458 ms – 1 447 1BFh = = 001aak612 COMMAND RESPONSE1 RESPONSE2 TSP1 TSP2 QUIT1 QUIT2CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 27 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.5.2 Using the timer unit functions 9.5.2.1 Time-out and WatchDog counters After starting the timer using TReloadValue[7:0], the timer unit decrements the TimerValue register beginning with a given start event. If a given stop event occurs, such as a bit being received from the card, the timer unit stops without generating an interrupt. If a stop event does not occur, such as the card not answering within the expected time, the timer unit decrements down to zero and generates a timer interrupt request. This signals to the microprocessor the expected event has not occurred within the given time (tTimer). 9.5.2.2 Stopwatch The time (tTimer) between a start and stop event is measured by the microprocessor using the timer unit. Setting the TReloadValue register triggers the timer which in turn, starts to decrement. If the defined stop event occurs, the timer stops. The time between start and stop is calculated by the microprocessor using Equation 5, when the timer does not decrement down to zero. (5) 9.5.2.3 Programmable one shot timer and periodic trigger Programmable one shot timer: The microprocessor starts the timer unit and waits for the timer interrupt. The interrupt occurs after the time specified by tTimer. Periodic trigger: If the microprocessor sets the TAutoRestart bit, it generates an interrupt request after every tTimer cycle. 9.5.3 Timer unit registers Table 24 shows the related flags of the timer unit in alphabetical order. t TReLoadvalue – TimerValue tTimer = Table 24. Associated timer unit registers and flags Flags Register name Bit Register address TAutoRestart TimerClock 5 2Ah TimerValue[7:0] TimerValue 7 to 0 0Ch TReloadValue[7:0] TimerReload 7 to 0 2Ch TPreScaler[4:0] TimerClock 4 to 0 2Ah TRunning SecondaryStatus 7 05h TStartNow Control 1 09h TStartTxBegin TimerControl 0 2Bh TStartTxEnd TimerControl 1 2Bh TStopNow Control 2 09h TStopRxBegin TimerControl 2 2Bh TStopRxEnd TimerControl 3 2BhCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 28 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.6 Power reduction modes 9.6.1 Hard power-down Hard power-down is enabled when pin RSTPD is HIGH. This turns off all internal current sinks including the oscillator. All digital input buffers are separated from the input pads and defined internally (except pin RSTPD itself). The output pins are frozen at a given value. The status of all pins during a hard power-down is shown in Table 25. 9.6.2 Soft power-down mode Soft power-down mode is entered immediately using the Control register bit PowerDown. All internal current sinks, including the oscillator buffer, are switched off. The digital input buffers are not separated from the input pads and keep their functionality. In addition, the digital output pins do not change their state. After resetting the Control register bit PowerDown, the bit indicating Soft power-down mode is only cleared after 512 clock cycles. Resetting it does not immediately clear it. The PowerDown bit is automatically cleared when the Soft power-down mode is exited. Remark: When the internal oscillator is used, time (tosc) is required for the oscillator to become stable. This is because the internal oscillator is supplied by VDDA and any clock cycles will not be detected by the internal logic until VDDA is stable. Table 25. Signal on pins during Hard power-down Symbol Pin Type Description OSCIN 1 I not separated from input, pulled to AVSS IRQ 2 O high-impedance MFIN 3 I separated from input MFOUT 4 O LOW TX1 5 O HIGH, if bit TX1RFEn = logic 1 LOW, if bit TX1RFEn = logic 0 TX2 7 O HIGH, only if bit TX2RFEn = logic 1 and bit TX2Inv = logic 0 otherwise LOW NCS 9 I separated from input NWR 10 I separated from input NRD 11 I separated from input D0 to D7 13 to 20 I/O separated from input ALE 21 I separated from input A0 22 I/O separated from input A1 23 I separated from input A2 24 I separated from input AUX 27 O high-impedance RX 29 I not changed VMID 30 A pulled to VDDA RSTPD 31 I not changed OSCOUT 32 O HIGHCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 29 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.6.3 Standby mode The Standby mode is immediately entered when the Control register StandBy bit is set. All internal current sinks, including the internal digital clock buffer are switched off. However, the oscillator buffer is not switched off. The digital input buffers are not separated by the input pads, keeping their functionality and the digital output pins do not change their state. In addition, the oscillator does not need time to wake-up. After resetting the Control register StandBy bit, it takes four clock cycles on pin OSCIN for Standby mode to exit. Resetting bit StandBy does not immediately clear it. It is automatically cleared when the Standby mode is exited. 9.6.4 Automatic receiver power-down It is a power saving feature to switch off the receiver circuit when it is not needed. Setting bit RxAutoPD = logic 1, automatically powers down the receiver when it is not in use. Setting bit RxAutoPD = logic 0, keeps the receiver continuously powered up. 9.7 StartUp phase The events executed during the StartUp phase are shown in Figure 10. 9.7.1 Hard power-down phase The hard power-down phase is active during the following cases: • a Power-On Reset (POR) caused by power-up on pins DVDD or AVDD activated when VDDD or VDDA is below the digital reset threshold. • a HIGH-level on pin RSTPD which is active while pin RSTPD is HIGH. The HIGH level period on pin RSTPD must be at least 100 s (tPD 100 s). Shorter phases will not necessarily result in the reset phase (treset). The rising or falling edge slew rate on pin RSTPD is not critical because pin RSTPD is a Schmitt trigger input. 9.7.2 Reset phase The reset phase automatically follows the Hard power-down. Once the oscillator is running stably, the reset phase takes 512 clock cycles. During the reset phase, some register bits are preset by hardware. The respective reset values are given in the description of each register (see Section 10.5 on page 50). Remark: When the internal oscillator is used, time (tosc) is required for the oscillator to become stable. This is because the internal oscillator is supplied by VDDA and any clock cycles will not be detected by the internal logic until VDDA is stable. Fig 10. The StartUp procedure 001aak613 StartUp phase states tRSTPD treset tinit Hard powerdown phase Reset phase Initialising phase readyCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 30 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.7.3 Initialization phase The initialization phase automatically follows the reset phase and takes 128 clock cycles. During the initializing phase the content of the EEPROM blocks 1 and 2 is copied into the register subaddresses 10h to 2Fh (see Section 9.2.2 on page 13). Remark: During the production test, the CLRC632 is initialized with default configuration values. This reduces the microprocessor’s configuration time to a minimum. 9.7.4 Initializing the parallel interface type A different initialization sequence is used for each microprocessor. This enables detection of the correct microprocessor interface type and synchronization of the microprocessor’s and the CLRC632’s start-up. See Section 9.1.3 on page 8 for detailed information on the different connections for each microprocessor interface type. During StartUp phase, the command value is set to 3Fh once the oscillator attains clock frequency stability at an amplitude of > 90 % of the nominal 13.56 MHz clock frequency. At the end of the initialization phase, the CLRC632 automatically switches to idle and the command value changes to 00h. To ensure correct detection of the microprocessor interface, the following sequence is executed: • the Command register is read until the 6-bit register value is 00h. On reading the 00h value, the internal initialization phase is complete and the CLRC632 is ready to be controlled • write 80h to the Page register to initialize the microprocessor interface • read the Command register. If it returns a value of 00h, the microprocessor interface was successfully initialized • write 00h to the Page registers to activate linear addressing mode. 9.8 Oscillator circuit The clock applied to the CLRC632 acts as a time basis for the synchronous system encoder and decoder. The stability of the clock frequency is an important factor for correct operation. To obtain highest performance, clock jitter must be as small as possible. This is best achieved by using the internal oscillator buffer with the recommended circuitry. Fig 11. Quartz clock connection 001aak614 13.56 MHz 15 pF 15 pF OSCOUT OSCIN DEVICECLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 31 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution If an external clock source is used, the clock signal must be applied to pin OSCIN. In this case, be very careful in optimizing clock duty cycle and clock jitter. Ensure the clock quality has been verified. It must meet the specifications described in Section 13.4.5 on page 106. Remark: We do not recommend using an external clock source. 9.9 Transmitter pins TX1 and TX2 The signal on pins TX1 and TX2 is the 13.56 MHz energy carrier modulated by an envelope signal. It can be used to drive an antenna directly, using minimal passive components for matching and filtering (see Section 15.1 on page 107). To enable this, the output circuitry is designed with a very low-impedance source resistance. The TxControl register is used to control the TX1 and TX2 signals. 9.9.1 Configuring pins TX1 and TX2 TX1 pin configurations are described in Table 26. TX2 pin configurations are described in Table 27. Table 26. Pin TX1 configurations TxControl register configuration Envelope TX1 signal TX1RFEn FORCE100ASK 0 X X LOW (GND) 1 0 0 13.56 MHz carrier frequency modulated 1 0 1 13.56 MHz carrier frequency 1 1 0 LOW 1 1 1 13.56 MHz energy carrierCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 32 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.9.2 Antenna operating distance versus power consumption Using different antenna matching circuits (by varying the supply voltage on the antenna driver supply pin TVDD), it is possible to find the trade-off between maximum effective operating distance and power consumption. Different antenna matching circuits are described in the Application note “MIFARE Design of MFRC500 Matching Circuit and Antennas”. 9.9.3 Antenna driver output source resistance The output source conductance of pins TX1 and TX2 can be adjusted between 1 and 100 using the CwConductance register GsCfgCW[5:0] bits. The output source conductance of pins TX1 and TX2 during the modulation phase can be adjusted between 1 and 100 using the ModConductance register GsCfgMod[5:0] bits. The values are relative to the reference resistance (RS(ref)) which is measured during the production test and stored in the CLRC632 EEPROM. It can be read from the product information field (see Section 9.2.1 on page 13). The electrical specification can be found in Section 13.3.3 on page 101. Table 27. Pin TX2 configurations TxControl register configuration Envelope TX2 signal TX2RFEn FORCE100ASK TX2CW TX2Inv 0 X X X X LOW 1 0 0 0 0 13.56 MHz carrier frequency modulated 1 0 0 0 1 13.56 MHz carrier frequency 1 0 0 1 0 13.56 MHz carrier frequency modulated, 180 phase-shift relative to TX1 1 0 0 1 1 13.56 MHz carrier frequency, 180 phase-shift relative to TX1 1 0 1 0 X 13.56 MHz carrier frequency 1 0 1 1 X 13.56 MHz carrier frequency, 180 phase-shift relative to TX1 1 1 0 0 0 LOW 1 1 0 0 1 13.56 MHz carrier frequency 1 1 0 1 0 HIGH 1 1 0 1 1 13.56 MHz carrier frequency, 180 phase-shift relative to TX1 1 1 1 0 X 13.56 MHz carrier frequency 1 1 1 1 X 13.56 MHz carrier frequency, 180 phase-shift relative to TX1CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 33 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.9.3.1 Source resistance table Table 28. TX1 and TX2 source resistance of n-channel driver transistor against GsCfgCW or GsCfgMod MANT = Mantissa; EXP= Exponent. GsCfgCW, GsCfgMod (decimal) EXPGsCfgCW, EXPGsCfgMod (decimal) MANTGsCfgCW, MANTGsCfgMod (decimal) RS(ref) () GsCfgCW, GsCfgMod (decimal) EXPGsCfgCW, EXPGsCfgMod (decimal) MANTGsCfgCW, MANTGsCfgMod (decimal) RS(ref) () 0 0 0 - 24 1 8 0.0652 16 1 0 - 25 1 9 0.0580 32 2 0 - 37 2 5 0.0541 48 3 0 - 26 1 10 0.0522 1 0 1 1.0000 27 1 11 0.0474 17 1 1 0.5217 51 3 3 0.0467 2 0 2 0.5000 38 2 6 0.0450 3 0 3 0.3333 28 1 12 0.0435 33 2 1 0.2703 29 1 13 0.0401 18 1 2 0.2609 39 2 7 0.0386 4 0 4 0.2500 30 1 14 0.0373 5 0 5 0.2000 52 3 4 0.0350 19 1 3 0.1739 31 1 15 0.0348 6 0 6 0.1667 40 2 8 0.0338 7 0 7 0.1429 41 2 9 0.0300 49 3 1 0.1402 53 3 5 0.0280 34 2 2 0.1351 42 2 10 0.0270 20 1 4 0.1304 43 2 11 0.0246 8 0 8 0.1250 54 3 6 0.0234 9 0 9 0.1111 44 2 12 0.0225 21 1 5 0.1043 45 2 13 0.0208 10 0 10 0.1000 55 3 7 0.0200 11 0 11 0.0909 46 2 14 0.0193 35 2 3 0.0901 47 2 15 0.0180 22 1 6 0.0870 56 3 8 0.0175 12 0 12 0.0833 57 3 9 0.0156 13 0 13 0.0769 58 3 10 0.0140 23 1 7 0.0745 59 3 11 0.0127 14 0 14 0.0714 60 3 12 0.0117 50 3 2 0.0701 61 3 13 0.0108 36 2 4 0.0676 62 3 14 0.0100 15 0 15 0.0667 63 3 15 0.0093CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 34 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.9.3.2 Calculating the relative source resistance The reference source resistance RS(ref) can be calculated using Equation 6. (6) The reference source resistance (RS(ref)) during the modulation phase can be calculated using ModConductance register’s GsCfgMod[5:0]. 9.9.3.3 Calculating the effective source resistance Wiring resistance (RS(wire)): Wiring and bonding add a constant offset to the driver resistance that is relevant when pins TX1 and TX2 are switched to low-impedance. The additional resistance for pin TX1 (RS(wire)TX1) can be set approximately as shown in Equation 7. (7) Effective resistance (RSx): The source resistances of the driver transistors (RsMaxP byte) read from the Product Information Field (see Section 9.2.1 on page 13) are measured during the production test with CwConductance register’s GsCfgCW[5:0] = 01h. To calculate the driver resistance for a specific value set in GsCfgMod[5:0], use Equation 8. (8) 9.9.4 Pulse width The envelope carries the data signal information that is transmitted to the card. It is an encoded data signal based on the Miller code. In addition, each pause of the Miller encoded signal is again encoded as a pulse of a fixed width. The width of the pulse is adjusted using the ModWidth register. The pulse width (tw) is calculated using Equation 9 where the frequency constant (fclk) = 13.56 MHz. (9) 9.10 Receiver circuitry The CLRC632 uses an integrated quadrature demodulation circuit enabling it to detect an ISO/IEC 14443 A or ISO/IEC 14443 B compliant subcarrier signal on pin RX. • ISO/IEC 14443 A subcarrier signal: defined as a Manchester coded ASK modulated signal • ISO/IEC 14443 B subcarrier signal: defined as an NRZ-L coded BPSK modulated ISO/IEC 14443 B subcarrier signal RS ref 1 MANTGsCfgCW 77 40 ----- EXPGsCfgCW = -------------------------------------------------------------------------------- RS wire TX1 500 m RSx RS ref maxP RS wire TX1 – RS rel RS wire TX1 = + tw 2ModWidth 1 + fc = -------------------------------------CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 35 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution The quadrature demodulator uses two different clocks (Q-clock and I-clock) with a phase-shift of 90 between them. Both resulting subcarrier signals are amplified, filtered and forwarded to the correlation circuitry. The correlation results are evaluated, digitized and then passed to the digital circuitry. Various adjustments can be made to obtain optimum performance for all processing units. 9.10.1 Receiver circuit block diagram Figure 12 shows the block diagram of the receiver circuit. The receiving process can be broken down in to several steps. Quadrature demodulation of the 13.56 MHz carrier signal is performed. To achieve the optimum performance, automatic Q-clock calibration is recommended (see Section 9.10.2.1 on page 35). The demodulated signal is amplified by an adjustable amplifier. A correlation circuit calculates the degree of similarity between the expected and the received signal. The BitPhase register enables correlation interval position alignment with the received signal’s bit grid. In the evaluation and digitizer circuitry, the valid bits are detected and the digital results are sent to the FIFO buffer. Several tuning steps are possible for this circuit. The signal can be observed on its way through the receiver as shown in Figure 12. One signal at a time can be routed to pin AUX using the TestAnaSelect register as described in Section 15.2.2 on page 112. 9.10.2 Receiver operation In general, the default settings programmed in the StartUp initialization file are suitable for use with the CLRC632 to MIFARE card data communication. However, in some environments specific user settings will achieve better performance. 9.10.2.1 Automatic Q-clock calibration The quadrature demodulation concept of the receiver generates a phase signal (I-clock) and a 90 phase-shifted quadrature signal (Q-clock). To achieve the optimum demodulator performance, the Q-clock and the I-clock must be phase-shifted by 90. After the reset phase, a calibration procedure is automatically performed. Fig 12. Receiver circuit block diagram 001aak615 ClkQDelay[4:0] ClkQCalib ClkQ180Deg BitPhase[7:0] CORRELATION CIRCUITRY EVALUATION AND DIGITIZER CIRCUITRY MinLevel[3:0] CollLevel[3:0] RxWait[7:0] RcvClkSell s_valid s_data s_coll s_clock Gain[1:0] to TestAnaOutSel clock I TO Q CONVERSION I-clock Q-clock 13.56 MHz DEMODULATOR RX VCorrDI VCorrNI VCorrDQ VCorrNQ VEvalR VEvalL VRxFollQ VRxFollI VRxAmpI VRxAmpQCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 36 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Automatic calibration can be set-up to execute at the end of each Transceive command if bit ClkQCalib = logic 0. Setting bit ClkQCalib = logic 1 disables all automatic calibrations except after the reset sequence. Automatic calibration can also be triggered by the software when bit ClkQCalib has a logic 0 to logic 1 transition. Remark: The duration of the automatic Q-clock calibration is 65 oscillator periods or approximately 4.8 s. The ClockQControl register’s ClkQDelay[4:0] value is proportional to the phase-shift between the Q-clock and the I-clock. The ClkQ180Deg status flag bit is set when the phase-shift between the Q-clock and the I-clock is greater than 180. Remark: • The StartUp configuration file enables automatic Q-clock calibration after a reset • If bit ClkQCalib = logic 1, automatic calibration is not performed. Leaving this bit set to logic 1 can be used to permanently disable automatic calibration. • It is possible to write data to the ClkQDelay[4:0] bits using the microprocessor. The aim could be to disable automatic calibration and set the delay using the software. Configuring the delay value using the software requires bit ClkQCalib to have been previously set to logic 1 and a time interval of at least 4.8 s has elapsed. Each delay value must be written with bit ClkQCalib set to logic 1. If bit ClkQCalib is logic 0, the configured delay value is overwritten by the next automatic calibration interval. 9.10.2.2 Amplifier The demodulated signal must be amplified by the variable amplifier to achieve the best performance. The gain of the amplifiers can be adjusted using the RxControl1 register Gain[1:0] bits; see Table 29. Fig 13. Automatic Q-clock calibration 001aak616 calibration impulse from reset sequence a rising edge initiates Q-clock calibration ClkQCalib bit calibration impulse from end of Transceive command Table 29. Gain factors for the internal amplifier See Table 86 “RxControl1 register bit descriptions” on page 64 for additional information. Register setting Gain factor [dB] (simulation results) 00 20 01 24 10 31 11 35CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 37 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.10.2.3 Correlation circuitry The correlation circuitry calculates the degree of matching between the received and an expected signal. The output is a measure of the amplitude of the expected signal in the received signal. This is done for both, the Q and I-channels. The correlator provides two outputs for each of the two input channels, resulting in a total of four output signals. The correlation circuitry needs the phase information for the incoming card signal for optimum performance. This information is defined for the microprocessor using the BitPhase register. This value defines the phase relationship between the transmitter and receiver clock in multiples of the BitPhase time (tBitPhase) = 1 / 13.56 MHz. 9.10.2.4 Evaluation and digitizer circuitry The correlation results are evaluated for each bit-half of the Manchester coded signal. The evaluation and digitizer circuit decides from the signal strengths of both bit-halves, if the current bit is valid • If the bit is valid, its value is identified • If the bit is not valid, it is checked to identify if it contains a bit-collision Select the following levels for optimal using RxThreshold register bits: • MinLevel[3:0]: defines the minimum signal strength of the stronger bit-halve’s signal which is considered valid. • CollLevel[3:0]: defines the minimum signal strength relative to the amplitude of the stronger half-bit that has to be exceeded by the weaker half-bit of the Manchester coded signal to generate a bit-collision. If the signal’s strength is below this value, logic 1 and logic 0 can be determined unequivocally. After data transmission, the card is not allowed to send its response before a preset time period which is called the frame guard time in the ISO/IEC 14443 standard. The length of this time period is set using the RxWait register’s RxWait[7:0] bits. The RxWait register defines when the receiver is switched on after data transmission to the card in multiples of one bit duration. If bit RcvClkSelI is set to logic 1, the I-clock is used to clock the correlator and evaluation circuits. If bit RcvClkSelI is set to logic 0, the Q-clock is used. Remark: It is recommended to use the Q-clock. 9.11 Serial signal switch The CLRC632 comprises two main blocks: • digital circuitry: comprising the state machines, encoder and decoder logic etc. • analog circuitry: comprising the modulator, antenna drivers, receiver and amplification circuitry The interface between these two blocks can be configured so that the interface signals are routed to pins MFIN and MFOUT. This makes it possible to connect the analog part of one CLRC632 to the digital part of another device. The serial signal switch can be used to measure MIFARE and ISO/IEC 14443 A as well as related I-CODE1 and ISO/IEC 15693 signals.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 38 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Remark: Pin MFIN can only be accessed at 106 kBd based on ISO/IEC 14443 A. The Manchester signal and the Manchester signal with subcarrier can only be accessed on pin MFOUT at 106 kBd based on ISO/IEC 14443 A. 9.11.1 Serial signal switch block diagram Figure 14 shows the serial signal switches. Three different switches are implemented in the serial signal switch enabling the CLRC632 to be used in different configurations. The serial signal switch can also be used to check the transmitted and received data during the design-in phase or for test purposes. Section 15.2.1 on page 110 describes the analog test signals and measurements at the serial signal switch. Remark: The SLR400 uses pin name SIGOUT for pin MFOUT. The CLRC632 functionality includes the test modes for the SLRC400 using pin MFOUT. Section 9.11.2, Section 9.11.2.1 and Section 9.11.2.2 describe the relevant registers and settings used to configure and control the serial signal switch. 9.11.2 Serial signal switch registers The RxControl2 register DecoderSource[1:0] bits define the input signal for the internal Manchester decoder and are described in Table 30. Fig 14. Serial signal switch block diagram 3 MFIN MFOUT 001aak617 MODULATOR DRIVER (part of) analog circuitry SUBCARRIER DEMODULATOR TX1 TX2 RX CARRIER DEMODULATOR 2 MILLER CODER 1 OUT OF 256 NRZ OR 1 OUT OF 4 MANCHESTER DECODER SERIAL SIGNAL SWITCH (part of) serial data processing Decoder Source[1:0] 2 Modulator Source[1:0] SUBCARRIER DEMODULATOR serial data out 0 0 1 internal 2 Manchester with subcarrier 3 0 1 2 3 4 5 6 0 1 envelope MFIN 0 1 2 3 Manchester Manchester out serial data in 7 0 0 1 1 envelope transmit NRZ Manchester with subcarrier Manchester reserved reserved MFOUTSelect[2:0] digital test signal signal to MFOUTCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 39 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution The TxControl register ModulatorSource[1:0] bits define the signal used to modulate the transmitted 13.56 MHz energy carrier. The modulated signal drives pins TX1 and TX2. The MFOUTSelect register MFOUTSelect[2:0] bits select the output signal which is to be routed to pin MFOUT. To use the MFOUTSelect[2:0] bits, the TestDigiSelect register SignalToMFOUT bit must be logic 0. 9.11.2.1 Active antenna concept The CLRC632 analog and digital circuitry is accessed using pins MFIN and MFOUT. Table 33 lists the required settings. Table 30. DecoderSource[1:0] values See Table 96 on page 67 for additional information. Number DecoderSource [1:0] Input signal to decoder 0 00 constant 0 1 01 output of the analog part. This is the default configuration 2 10 direct connection to pin MFIN; expects an 847.5 kHz subcarrier signal modulated by a Manchester encoded signal 3 11 direct connection to pin MFIN; expects a Manchester encoded signal Table 31. ModulatorSource[1:0] values See Table 96 on page 67 for additional information. Number ModulatorSource [1:0] Input signal to modulator 0 00 constant 0 (energy carrier off on pins TX1 and TX2) 1 01 constant 1 (continuous energy carrier on pins TX1 and TX2) 2 10 modulation signal (envelope) from the internal encoder. This is the default configuration. 3 11 direct connection to MFIN; expects a Miller pulse coded signal Table 32. MFOUTSelect[2:0] values See Table 110 on page 70 for additional information. Number MFOUTSelect [2:0] Signal routed to pin MFOUT 0 000 constant LOW 1 001 constant HIGH 2 010 modulation signal (envelope) from the internal encoder 3 011 serial data stream to be transmitted; the same as for MFOUTSelect[2:0] = 001 but not encoded by the selected pulse encoder 4 100 output signal of the receiver circuit; card modulation signal regenerated and delayed 5 101 output signal of the subcarrier demodulator; Manchester coded card signal 6 110 reserved 7 111 reservedCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 40 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution [1] The number column refers to the value in the number column of Table 30, Table 31 and Table 32. Two CLRC632 devices configured as described in Table 33 can be connected to each other using pins MFOUT and MFIN. Remark: The active antenna concept can only be used at 106 kBd based on ISO/IEC 14443 A. 9.11.2.2 Driving both RF parts It is possible to connect both passive and active antennas to a single IC. The passive antenna pins TX1, TX2 and RX are connected using the appropriate filter and matching circuit. At the same time an active antenna is connected to pins MFOUT and MFIN. In this configuration, two RF parts can be driven, one after another, by one microprocessor. 9.12 MIFARE higher baud rates The MIFARE system is specified with a fixed baud rate of 106 kBd for communication on the RF interface. The current version of ISO/IEC 14443 A also defines 106 kBd for the initial phase of a communication between Proximity Integrated Circuit Cards (PICC) and Proximity Coupling Devices (PCD). To cover requirements of large data transmissions and to speed up terminal to card communication, the CLRC632 supports communication at MIFARE higher baud rates in combination with a microcontroller IC such as the MIFARE ProX. The MIFARE higher baud rates concept is described in the application note: MIFARE Implementation of Higher Baud rates Ref. 5. This application covers the integration of the MIFARE higher baud rates communication concept in current applications. Table 33. Register settings to enable use of the analog circuitry Register Number[1] Signal CLRC632 pin Analog circuitry settings ModulatorSource 3 Miller pulse encoded MFIN MFOUTSelect 4 Manchester encoded with subcarrier MFOUT DecoderSource X - - Digital circuitry settings ModulatorSource X - - MFOUTSelect 2 Miller pulse encoded MFOUT DecoderSource 2 Manchester encoded with subcarrier MFIN Table 34. MIFARE higher baud rates Communication direction Baud rates (kBd) CLRC632 based PCD microcontroller PICC supporting higher baud rates 106, 212, 424 Microcontroller PICC supporting higher baud rates CLRC632 based PCD 106, 212, 424CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 41 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.13 ISO/IEC 14443 B communication scheme The international standard ISO/IEC 14443 covers two communication schemes; ISO/IEC 14443 A and ISO/IEC 14443 B. The CLRC632 reader IC fully supports both ISO/IEC 14443 variants. Table 35 describes the registers and flags covered by the ISO/IEC 14443 B communication protocol. As reference documentation, the international standard ISO/IEC 14443 Identification cards - Contactless integrated circuit(s) cards - Proximity cards, part 1-4 (Ref. 4) can be used. Remark: NXP Semiconductors does not offer a basic function library to design-in the ISO/IEC 14443 B protocol. Table 35. ISO/IEC 14443 B registers and flags Flag Register Bit Register address CharSpacing[2:0] TypeBFraming 4 to 2 17h CoderRate[2:0] CoderControl 5 to 3 14h EOFWidth TypeBFraming 5 17h FilterAmpDet BPSKDemControl 4 1Dh Force100ASK TxControl 4 11h GsCfgCW[5:0] CwConductance 5 to 0 12h GsCfgMod[5:0] ModConductance 5 to 0 13h MinLevel[3:0] RxThreshold 7 to 4 1Ch NoTxEOF TypeBFraming 6 17h NoTxSOF TypeBFraming 7 17h NoRxEGT BPSKDemControl 6 1Dh NoRxEOF BPSKDemControl 5 1Dh NoRxSOF BPSKDemControl 7 1Dh RxCoding DecoderControl 0 1Ah RxFraming[1:0] DecoderControl 4 to 3 1Ah SOFWidth[1:0] TypeBFraming 1 to 0 17h SubCPulses[2:0] RxControl1 7 to 5 19h TauB[1:0] BPSKDemControl 1 to 0 1Dh TauD[1:0] BPSKDemControl 3 to 2 1Dh TxCoding[2:0] CoderControl 2 to 0 14hCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 42 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.14 MIFARE authentication and Crypto1 The security algorithm used in the MIFARE products is called Crypto1. It is based on a proprietary stream cipher with a 48-bit key length. To access data on MIFARE cards, knowledge of the key format is needed. The correct key must be available in the CLRC632 to enable successful card authentication and access to the card’s data stored in the EEPROM. After a card is selected as defined in ISO/IEC 14443 A standard, the user can continue with the MIFARE protocol. It is mandatory that card authentication is performed. Crypto1 authentication is a 3-pass authentication which is automatically performed when the Authent1 and Authent2 commands are executed (see Section 11.7.3 on page 98 and Section 11.7.4 on page 98). During the card authentication procedure, the security algorithm is initialized. After a successful authentication, communication with the MIFARE card is encrypted. 9.14.1 Crypto1 key handling On execution of the authentication command, the CLRC632 reads the key from the key buffer. The key is always read from the key buffer and ensures Crypto1 authentication commands do not require addressing of a key. The user must ensure the correct key is prepared in the key buffer before triggering card authentication. The key buffer can be loaded from: • the EEPROM using the LoadKeyE2 command (see Section 11.7.1 on page 97) • the microprocessor’s FIFO buffer using the LoadKey command (see Section 11.7.2 on page 97). This is shown in Figure 15. Fig 15. Crypto1 key handling block diagram 001aak624 FIFO BUFFER from the microcontroller WriteE2 LoadKey EEPROM KEYS KEY BUFFER LoadKeyE2 during Authent1 CRYPTO1 MODULE serial data stream in serial data stream out (plain) (encrypted)CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 43 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.14.2 Authentication procedure The Crypto1 security algorithm enables authentication of MIFARE cards. To obtain valid authentication, the correct key has to be available in the key buffer of the CLRC632. This can be ensured as follows: 1. Load the internal key buffer by using the LoadKeyE2 (see Section 11.7.1 on page 97) or the LoadKey (see Section 11.7.2 on page 97) commands. 2. Start the Authent1 command (see Section 11.7.3 on page 98). When finished, check the error flags to obtain the command execution status. 3. Start the Authent2 command (see Section 11.7.4 on page 98). When finished, check the error flags and bit Crypto1On to obtain the command execution status. 10. CLRC632 registers 10.1 Register addressing modes Three methods can be used to operate the CLRC632: • initiating functions and controlling data by executing commands • configuring the functional operation using a set of configuration bits • monitoring the state of the CLRC632 by reading status flags The commands, configuration bits and flags are accessed using the microprocessor interface. The CLRC632 can internally address 64 registers using six address lines. 10.1.1 Page registers The CLRC632 register set is segmented into eight pages contain eight registers each. A Page register can always be addressed, irrespective of which page is currently selected. 10.1.2 Dedicated address bus When using the CLRC632 with the dedicated address bus, the microprocessor defines three address lines using address pins A0, A1 and A2. This enables addressing within a page. To switch between registers in different pages a paging mechanism needs to be used. Table 36 shows how the register address is assembled. 10.1.3 Multiplexed address bus The microprocessor may define all six address lines at once using the CLRC632 with a multiplexed address bus. In this case either the paging mechanism or linear addressing can be used. Table 37 shows how the register address is assembled. Table 36. Dedicated address bus: assembling the register address Register bit: UsePageSelect Register address 1 PageSelect2 PageSelect1 PageSelect0 A2 A1 A0CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 44 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.2 Register bit behavior Bits and flags for different registers behave differently, depending on their functions. In principle, bits with same behavior are grouped in common registers. Table 38 describes the function of the Access column in the register tables. Table 37. Multiplexed address bus: assembling the register address Multiplexed address bus type UsePage Select Register address Paging mode 1 PageSelect2 PageSelect1 PageSelect0 AD2 AD1 AD0 Linear addressing 0 AD5 AD4 AD3 AD2 AD1 AD0 Table 38. Behavior and designation of register bits Abbreviation Behavior Description R/W read and write These bits can be read and written by the microprocessor. Since they are only used for control, their content is not influenced by internal state machines. Example: TimerReload register may be read and written by the microprocessor. It will also be read by internal state machines but never changed by them. D dynamic These bits can be read and written by the microprocessor. Nevertheless, they may also be written automatically by internal state machines. Example: the Command register changes its value automatically after the execution of the command. R read only These registers hold flags which have a value determined by internal states only. Example: the ErrorFlag register cannot be written externally but shows internal states. W write only These registers are used for control only. They may be written by the microprocessor but cannot be read. Reading these registers returns an undefined value. Example: The TestAnaSelect register is used to determine the signal on pin AUX however, it is not possible to read its content.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 45 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.3 Register overview Table 39. CLRC632 register overview Sub address (Hex) Register name Function Refer to Page 0: Command and status 00h Page selects the page register Table 41 on page 50 01h Command starts and stops command execution Table 43 on page 50 02h FIFOData input and output of 64-byte FIFO buffer Table 45 on page 51 03h PrimaryStatus receiver and transmitter and FIFO buffer status flags Table 47 on page 51 04h FIFOLength number of bytes buffered in the FIFO buffer Table 49 on page 52 05h SecondaryStatus secondary status flags Table 51 on page 53 06h InterruptEn enable and disable interrupt request control bits Table 53 on page 53 07h InterruptRq interrupt request flags Table 55 on page 54 Page 1: Control and status 08h Page selects the page register Table 41 on page 50 09h Control control flags for timer unit, power saving etc Table 57 on page 55 0Ah ErrorFlag show the error status of the last command executed Table 59 on page 55 0Bh CollPos bit position of the first bit-collision detected on the RF interface Table 61 on page 56 0Ch TimerValue value of the timer Table 63 on page 57 0Dh CRCResultLSB LSB of the CRC coprocessor register Table 65 on page 57 0Eh CRCResultMSB MSB of the CRC coprocessor register Table 67 on page 57 0Fh BitFraming adjustments for bit oriented frames Table 69 on page 58 Page 2: Transmitter and coder control 10h Page selects the page register Table 41 on page 50 11h TxControl controls the operation of the antenna driver pins TX1 and TX2 Table 71 on page 59 12h CwConductance selects the conductance of the antenna driver pins TX1 and TX2 Table 73 on page 60 13h ModConductance defines the driver output conductance Table 75 on page 60 14h CoderControl sets the clock frequency and the encoding Table 77 on page 61 15h ModWidth selects the modulation pulse width Table 79 on page 62 16h ModWidthSOF selects the SOF pulse-width modulation (I-CODE1 fast mode) Table 81 on page 62 17h TypeBFraming defines the framing for ISO/IEC 14443 B communication Table 83 on page 63 Page 3: Receiver and decoder control 18 Page selects the page register Table 41 on page 50 19 RxControl1 controls receiver behavior Table 85 on page 64 1A DecoderControl controls decoder behavior Table 87 on page 65 1B BitPhase selects the bit-phase between transmitter and receiver clock Table 89 on page 65 1C RxThreshold selects thresholds for the bit decoder Table 91 on page 66 1D BPSKDemControl controls BPSK receiver behavior Table 93 on page 66 1Eh RxControl2 controls decoder and defines the receiver input source Table 95 on page 67 1Fh ClockQControl clock control for the 90 phase-shifted Q-channel clock Table 97 on page 67CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 46 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Page 4: RF Timing and channel redundancy 20h Page selects the page register Table 41 on page 50 21h RxWait selects the interval after transmission before the receiver starts Table 99 on page 68 22h ChannelRedundancy selects the method and mode used to check data integrity on the RF channel Table 101 on page 68 23h CRCPresetLSB preset LSB value for the CRC register Table 103 on page 69 24h CRCPresetMSB preset MSB value for the CRC register Table 105 on page 69 25h TimeSlotPeriod selects the time between automatically transmitted frames Table 107 on page 69 26h MFOUTSelect selects internal signal applied to pin MFOUT, includes the MSB of value TimeSlotPeriod; see Table 107 on page 69 Table 109 on page 70 27h PreSet27 these values are not changed Table 111 on page 70 Page 5: FIFO, timer and IRQ pin configuration 28h Page selects the page register Table 41 on page 50 29h FIFOLevel defines the FIFO buffer overflow and underflow warning levels Table 49 on page 52 2Ah TimerClock selects the timer clock divider Table 114 on page 71 2Bh TimerControl selects the timer start and stop conditions Table 116 on page 72 2Ch TimerReload defines the timer preset value Table 118 on page 72 2Dh IRQPinConfig configures pin IRQ output stage Table 120 on page 73 2Eh PreSet2E these values are not changed Table 122 on page 73 2Fh PreSet2F these values are not changed Table 123 on page 73 Page 6: reserved registers 30h Page selects the page register Table 41 on page 50 31h reserved reserved Table 124 on page 73 32h reserved reserved 33h reserved reserved 34h reserved reserved 35h reserved reserved 36h reserved reserved 37h reserved reserved Page 7: Test control 38h Page selects the page register Table 41 on page 50 39h reserved reserved Table 125 on page 74 3Ah TestAnaSelect selects analog test mode Table 126 on page 74 3Bh reserved reserved Table 128 on page 75 3Ch reserved reserved Table 129 on page 75 3Dh TestDigiSelect selects digital test mode Table 130 on page 75 3Eh reserved reserved Table 132 on page 76 3Fh reserved reserved Table 39. CLRC632 register overview …continued Sub address (Hex) Register name Function Refer toCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 47 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.4 CLRC632 register flags overview Table 40. CLRC632 register flags overview Flag(s) Register Bit Address AccessErr ErrorFlag 5 0Ah BitPhase[7:0] BitPhase 7 to 0 1Bh CharSpacing[2:0] TypeBFraming 4 to 2 17h, ClkQ180Deg ClockQControl 7 1Fh ClkQCalib ClockQControl 6 1Fh ClkQDelay[4:0] ClockQControl 4 to 0 1Fh CoderRate[2:0] CoderControl 5 to 3 14h CollErr ErrorFlag 0 0Ah CollLevel[3:0] RxThreshold 3 to 0 1Ch CollPos[7:0] CollPos 7 to 0 0Bh Command[5:0] Command 5 to 0 01h CRC3309 ChannelRedundancy 5 22h CRC8 ChannelRedundancy 4 22h CRCErr ErrorFlag 3 0Ah CRCPresetLSB[7:0] CRCPresetLSB 7 to 0 23h CRCPresetMSB[7:0] CRCPresetMSB 7 to 0 24h CRCReady SecondaryStatus 5 05h CRCResultMSB[7:0] CRCResultMSB 7 to 0 0Eh CRCResultLSB[7:0] CRCResultLSB 7 to 0 0Dh Crypto1On Control 3 09h DecoderSource[1:0] RxControl2 1 to 0 1Eh E2Ready SecondaryStatus 6 05h EOFWidth TypeBFraming 5 17h Err PrimaryStatus 2 03h FIFOData[7:0] FIFOData 7 to 0 02h FIFOLength[6:0] FIFOLength 6 to 0 04h FIFOOvfl ErrorFlag 4 0Ah FilterAmpDet BPSKDemControl 4 1Dh FlushFIFO Control 0 09h Force100ASK TxControl 4 11h FramingErr ErrorFlag 2 0Ah Gain[1:0] RxControl1 1 to 0 19h GsCfgCW[5:0] CwConductance 5 to 0 12h GsCfgMod[5:0] ModConductance 5 to 0 13h HiAlert PrimaryStatus 1 03h HiAlertIEn InterruptEn 1 06h HiAlertIRq InterruptRq 1 07h IdleIEn InterruptEn 2 06h IdleIRq InterruptRq 2 07hCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 48 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution IFDetectBusy Command 7 01h IRq PrimaryStatus 3 03h IRQInv IRQPinConfig 1 2Dh IRQPushPull IRQPinConfig 0 2Dh ISO Selection[1:0] RxControl1 4 to 3 19h KeyErr ErrorFlag 6 0Ah LoAlert PrimaryStatus 0 03h LoAlertIEn InterruptEn 0 06h LoAlertIRq InterruptRq 0 07h LPOff RxControl1 2 19h MFOUTSelect[2:0] MFOUTSelect 2 to 0 26h MinLevel[3:0] RxThreshold 7 to 4 1Ch ModemState[2:0] PrimaryStatus 6 to 4 03h ModulatorSource[1:0] TxControl 6 to 5 11h ModWidth[7:0] ModWidth 7 to 0 15h NoRxEGT BPSKDemControl 6 1Dh NoRxEOF BPSKDemControl 5 1Dh NoRxSOF BPSKDemControl 7 1Dh NoTxEOF TypeBFraming 6 17h NoTxSOF TypeBFraming 7 17h PageSelect[2:0] Page 2 to 0 00h, 08h, 10h, 18h, 20h, 28h, 30h and 38h ParityEn ChannelRedundancy 0 22h ParityErr ErrorFlag 1 0Ah ParityOdd ChannelRedundancy 1 22h PowerDown Control 4 09h RcvClkSelI RxControl2 7 1Eh RxAlign[2:0] BitFraming 6 to 4 0Fh RxAutoPD RxControl2 6 1Eh RxCRCEn ChannelRedundancy 3 22h RxCoding DecoderControl 0 1Ah RxFraming[1:0] DecoderControl 4 to 3 1Ah RxIEn InterruptEn 3 06h RxIRq InterruptRq 3 07h RxLastBits[2:0] SecondaryStatus 2 to 0 05h RxMultiple DecoderControl 6 1Ah RxWait[7:0] RxWait 7 to 0 21h SetIEn InterruptEn 7 06h SetIRq InterruptRq 7 07h SignalToMFOUT TestDigiSelect 7 3Dh SOFWidth[1:0] TypeBFraming 1 to 0 17h Table 40. CLRC632 register flags overview …continued Flag(s) Register Bit AddressCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 49 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution StandBy Control 5 09h SubCPulses[2:0] RxControl1 7 to 5 19h TauB[1:0] BPSKDemControl 1 to 0 1Dh TauD[1:0] BPSKDemControl 3 to 2 1Dh TAutoRestart TimerClock 5 2Ah TestAnaOutSel[4:0] TestAnaSelect 3 to 0 3Ah TestDigiSignalSel[6:0] TestDigiSelect 6 to 0 3Dh TimerIEn InterruptEn 5 06h TimerIRq InterruptRq 5 07h TimerValue[7:0] TimerValue 7 to 0 0Ch TimeSlotPeriod[7:0] TimeSlotPeriod 7 to 0 25h TimeSlotPeriodMSB MFOUTSelect 4 26h TPreScaler[4:0] TimerClock 4 to 0 2Ah TReloadValue[7:0] TimerReload 7 to 0 2Ch TRunning SecondaryStatus 7 05h TStartTxBegin TimerControl 0 2Bh TStartTxEnd TimerControl 1 2Bh TStartNow Control 1 09h TStopRxBegin TimerControl 2 2Bh TStopRxEnd TimerControl 3 2Bh TStopNow Control 2 09h TX1RFEn TxControl 0 11h TX2Cw TxControl 3 11h TX2Inv TxControl 3 11h TX2RFEn TxControl 1 11h TxCoding[2:0] CoderControl 2 to 0 14h TxCRCEn ChannelRedundancy 2 22h TxIEn InterruptEn 4 06h TxIRq InterruptRq 4 07h TxLastBits[2:0] BitFraming 2 to 0 0Fh UsePageSelect Page 7 00h, 08h, 10h, 18h, 20h, 28h, 30h and 38h WaterLevel[5:0] FIFOLevel 5 to 0 29h ZeroAfterColl DecoderControl 7 1Ah, bit 5 Table 40. CLRC632 register flags overview …continued Flag(s) Register Bit AddressCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 50 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5 Register descriptions 10.5.1 Page 0: Command and status 10.5.1.1 Page register Selects the page register. 10.5.1.2 Command register Starts and stops the command execution. Table 41. Page register (address: 00h, 08h, 10h, 18h, 20h, 28h, 30h, 38h) reset value: 1000 0000b, 80h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol UsePageSelect 0000 PageSelect[2:0] Access R/W R/W R/W R/W R/W Table 42. Page register bit descriptions Bit Symbol Value Description 7 UsePageSelect 1 the value of PageSelect[2:0] is used as the register address A5, A4, and A3. The LSBs of the register address are defined using the address pins or the internal address latch, respectively. 0 the complete content of the internal address latch defines the register address. The address pins are used as described in Table 5 on page 8. 6 to 3 0000 - reserved 2 to 0 PageSelect[2:0] - when UsePageSelect = logic 1, the value of PageSelect is used to specify the register page (A5, A4 and A3 of the register address) Table 43. Command register (address: 01h) reset value: x000 0000b, x0h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol IFDetectBusy 0 Command[5:0] Access R R D Table 44. Command register bit descriptions Bit Symbol Value Description 7 IFDetectBusy - shows the status of interface detection logic 0 interface detection finished successfully 1 interface detection ongoing 6 0 - reserved 5 to 0 Command[5:0] - activates a command based on the Command code. Reading this register shows which command is being executed.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 51 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.1.3 FIFOData register Input and output of the 64 byte FIFO buffer. 10.5.1.4 PrimaryStatus register Bits relating to receiver, transmitter and FIFO buffer status flags. Table 45. FIFOData register (address: 02h) reset value: xxxx xxxxb, 05h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol FIFOData[7:0] Access D Table 46. FIFOData register bit descriptions Bit Symbol Description 7 to 0 FIFOData[7:0] data input and output port for the internal 64-byte FIFO buffer. The FIFO buffer acts as a parallel in to parallel out converter for all data streams. Table 47. PrimaryStatus register (address: 03h) reset value: 0000 0101b, 05h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 0 ModemState[2:0] IRq Err HiAlert LoAlert Access R R R R R R Table 48. PrimaryStatus register bit descriptions Bit Symbol Value Status Description 7 0 - reserved 6 to 4 ModemState[2:0] shows the state of the transmitter and receiver state machines: 000 Idle neither the transmitter or receiver are operating; neither of them are started or have input data 001 TxSOF transmit start of frame pattern 010 TxData transmit data from the FIFO buffer (or redundancy CRC check bits) 011 TxEOF transmit End Of Frame (EOF) pattern 100 GoToRx1 intermediate state 1; receiver starts GoToRx2 intermediate state 2; receiver finishes 101 PrepareRx waiting until the RxWait register time period expires 110 AwaitingRx receiver activated; waiting for an input signal on pin RX 111 Receiving receiving data 3 IRq - shows any interrupt source requesting attention based on the InterruptEn register flag settingsCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 52 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.1.5 FIFOLength register Number of bytes in the FIFO buffer. 2 Err 1 any error flag in the ErrorFlag register is set 1 HiAlert 1 the alert level for the number of bytes in the FIFO buffer (FIFOLength[6:0]) is: otherwise value = logic 0 Example: FIFOLength = 60, WaterLevel = 4 then HiAlert = logic 1 FIFOLength = 59, WaterLevel = 4 then HiAlert = logic 0 0 LoAlert 1 the alert level for number of bytes in the FIFO buffer (FIFOLength[6:0]) is: otherwise value = logic 0 Example: FIFOLength = 4, WaterLevel = 4 then LoAlert = logic 1 FIFOLength = 5, WaterLevel = 4 then LoAlert = logic 0 Table 48. PrimaryStatus register bit descriptions …continued Bit Symbol Value Status Description HiAlert 64 FIFOLength = – WaterLevel LoAlert FIFOLe = ngth WaterLevel Table 49. FIFOLength register (address: 04h) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 0 FIFOLength[6:0] Access R R Table 50. FIFOLength bit descriptions Bit Symbol Description 7 0 reserved 6 to 0 FIFOLength[6:0] gives the number of bytes stored in the FIFO buffer. Writing increments the FIFOLength register value while reading decrements the FIFOLength register valueCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 53 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.1.6 SecondaryStatus register Various secondary status flags. 10.5.1.7 InterruptEn register Control bits to enable and disable passing of interrupt requests. [1] This bit can only be set or cleared using bit SetIEn. Table 51. SecondaryStatus register (address: 05h) reset value: 01100 000b, 60h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol TRunning E2Ready CRCReady 00 RxLastBits[2:0] Access R R R R R Table 52. SecondaryStatus register bit descriptions Bit Symbol Value Description 7 TRunning 1 the timer unit is running and the counter decrements the TimerValue register on the next timer clock cycle 0 the timer unit is not running 6 E2Ready 1 EEPROM programming is finished 0 EEPROM programming is ongoing 5 CRCReady 1 CRC calculation is finished 0 CRC calculation is ongoing 4 to 3 00 - reserved 2 to 0 RxLastBits [2:0] - shows the number of valid bits in the last received byte. If zero, the whole byte is valid Table 53. InterruptEn register (address: 06h) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SetIEn 0 TimerIEn TxIEn RxIEn IdleIEn HiAlertIEn LoAlertIEn Access W R/W R/W R/W R/W R/W R/W R/W Table 54. InterruptEn register bit descriptions Bit Symbol Value Description 7 SetIEn 1 indicates that the marked bits in the InterruptEn register are set 0 clears the marked bits 6 0 - reserved 5 TimerIEn - sends the TimerIRq timer interrupt request to pin IRQ[1] 4 TxIEn - sends the TxIRq transmitter interrupt request to pin IRQ[1] 3 RxIEn - sends the RxIRq receiver interrupt request to pin IRQ[1] 2 IdleIEn - sends the IdleIRq idle interrupt request to pin IRQ[1] 1 HiAlertIEn - sends the HiAlertIRq high alert interrupt request to pin IRQ[1] 0 LoAlertIEn - sends the LoAlertIRq low alert interrupt request to pin IRQ[1]CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 54 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.1.8 InterruptRq register Interrupt request flags. [1] PrimaryStatus register Bit HiAlertIRq stores this event and it can only be reset using bit SetIRq. Table 55. InterruptRq register (address: 07h) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SetIRq 0 TimerIRq TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq Access W R/W D D D D D D Table 56. InterruptRq register bit descriptions Bit Symbol Value Description 7 SetIRq 1 sets the marked bits in the InterruptRq register 0 clears the marked bits in the InterruptRq register 6 0 - reserved 5 TimerIRq 1 timer decrements the TimerValue register to zero 0 timer decrements are still greater than zero 4 TxIRq 1 TxIRq is set to logic 1 if one of the following events occurs: Transceive command; all data transmitted Authent1 and Authent2 commands; all data transmitted WriteE2 command; all data is programmed CalcCRC command; all data is processed 0 when not acted on by Transceive, Authent1, Authent2, WriteE2 or CalcCRC commands 3 RxIRq 1 the receiver terminates 0 reception still ongoing 2 IdleIRq 1 command terminates correctly. For example; when the Command register changes its value from any command to the Idle command. If an unknown command is started the IdleIRq bit is set. Microprocessor start-up of the Idle command does not set the IdleIRq bit. 0 IdleIRq = logic 0 in all other instances 1 HiAlertIRq 1 PrimaryStatus register HiAlert bit is set[1] 0 PrimaryStatus register HiAlert bit is not set 0 LoAlertIRq 1 PrimaryStatus register LoAlert bit is set[1] 0 PrimaryStatus register LoAlert bit is not setCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 55 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.2 Page 1: Control and status 10.5.2.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 50. 10.5.2.2 Control register Various control flags, for timer, power saving, etc. 10.5.2.3 ErrorFlag register Error flags show the error status of the last executed command. Table 57. Control register (address: 09h) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 00 StandBy PowerDown Crypto1On TStopNow TStartNow FlushFIFO Access R/W D D D D D D Table 58. Control register bit descriptions Bit Symbol Value Description 7 to 6 00 - reserved 5 StandBy 1 activates Standby mode. The current consuming blocks are switched off but the clock keeps running 4 PowerDown 1 activates Power-down mode. The current consuming blocks are switched off including the clock 3 Crypto1On 1 Crypto1 unit is switched on and all data communication with the card is encrypted. This bit can only be set to logic 1 by successful execution of the Authent2 command 0 Crypto1 unit is switched off. All data communication with the card is unencrypted (plain) 2 TStopNow 1 immediately stops the timer. Reading this bit always returns logic 0 1 TStartNow 1 immediately starts the timer. Reading this bit will always returns logic 0 0 FlushFIFO 1 immediately clears the internal FIFO buffer’s read and write pointer, the FIFOLength[6:0] bits are set to logic 0 and the FIFOOvfl flag. Reading this bit always returns logic 0 Table 59. ErrorFlag register (address: 0Ah) reset value: 0100 0000b, 40h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 0 KeyErr AccessErr FIFOOvfl CRCErr FramingErr ParityErr CollErr Access R R R R R R R R Table 60. ErrorFlag register bit descriptions Bit Symbol Value Description 7 0 - reserved 6 KeyErr 1 set when the LoadKeyE2 or LoadKey command recognize that the input data is not encoded based on the Key format definition 0 set when the LoadKeyE2 or the LoadKey command startsCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 56 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution [1] Only valid for communication using ISO/IEC 14443 A. 10.5.2.4 CollPos register Bit position of the first bit-collision detected on the RF interface. Remark: A bit collision is not indicated in the CollPos register when using the ISO/IEC 14443 B protocol standard. 5 AccessErr 1 set when the access rights to the EEPROM are violated 0 set when an EEPROM related command starts 4 FIFOOvfl 1 set when the microprocessor or CLRC632 internal state machine (e.g. receiver) tries to write data to the FIFO buffer when it is full 3 CRCErr 1 set when RxCRCEn is set and the CRC fails 0 automatically set during the PrepareRx state in the receiver start phase 2 FramingErr 1 set when the SOF is incorrect 0 automatically set during the PrepareRx state in the receiver start phase 1 ParityErr 1 set when the parity check fails 0 automatically set during the PrepareRx state in the receiver start phase 0 CollErr 1 set when a bit-collision is detected[1] 0 automatically set during the PrepareRx state in the receiver start phase[1] Table 60. ErrorFlag register bit descriptions …continued Bit Symbol Value Description Table 61. CollPos register (address: 0Bh) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CollPos[7:0] Access R Table 62. CollPos register bit descriptions Bit Symbol Description 7 to 0 CollPos[7:0] this register shows the bit position of the first detected collision in a received frame. Example: 00h indicates a bit collision in the start bit 01h indicates a bit collision in the 1st bit ... 08h indicates a bit collision in the 8th bitCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 57 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.2.5 TimerValue register Value of the timer. 10.5.2.6 CRCResultLSB register LSB of the CRC coprocessor register. 10.5.2.7 CRCResultMSB register MSB of the CRC coprocessor register. Table 63. TimerValue register (address: 0Ch) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol TimerValue[7:0] Access R Table 64. TimerValue register bit descriptions Bit Symbol Description 7 to 0 TimerValue[7:0] this register shows the timer counter value Table 65. CRCResultLSB register (address: 0Dh) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CRCResultLSB[7:0] Access R Table 66. CRCResultLSB register bit descriptions Bit Symbol Description 7 to 0 CRCResultLSB[7:0] gives the CRC register’s least significant byte value; only valid if CRCReady = logic 1 Table 67. CRCResultMSB register (address: 0Eh) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CRCResultMSB[7:0] Access R Table 68. CRCResultMSB register bit descriptions Bit Symbol Description 7 to 0 CRCResultMSB[7:0] gives the CRC register’s most significant byte value; only valid if CRCReady = logic 1. The register’s value is undefined for 8-bit CRC calculation.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 58 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.2.8 BitFraming register Adjustments for bit oriented frames. Table 69. BitFraming register (address: 0Fh) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 0 RxAlign[2:0] 0 TxLastBits[2:0] Access R/W D R/W D Table 70. BitFraming register bit descriptions Bit Symbol Value Description 7 0 - reserved 6 to 4 RxAlign[2:0] defines the bit position for the first bit received to be stored in the FIFO buffer. Additional received bits are stored in the next subsequent bit positions. After reception, RxAlign[2:0] is automatically cleared. For example: 000 the LSB of the received bit is stored in bit position 0 and the second received bit is stored in bit position 1 001 the LSB of the received bit is stored in bit position 1, the second received bit is stored in bit position 2 ... 111 the LSB of the received bit is stored in bit position 7, the second received bit is stored in the next byte in bit position 0 3 0 - reserved 2 to 0 TxLastBits[2:0] - defines the number of bits of the last byte that shall be transmitted. 000 indicates that all bits of the last byte will be transmitted. TxLastBits[2:0] is automatically cleared after transmission.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 59 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.3 Page 2: Transmitter and control 10.5.3.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 50. 10.5.3.2 TxControl register Controls the logical behavior of the antenna pin TX1 and TX2. Table 71. TxControl register (address: 11h) reset value: 0101 1000b, 58h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 0 ModulatorSource [1:0] Force 100ASK TX2Inv TX2Cw TX2RFEn TX1RFEn Access R/W R/W R/W R/W R/W R/W R/W Table 72. TxControl register bit descriptions Bit Symbol Value Description 7 0 - this value must not be changed 6 to 5 ModulatorSource[1:0] selects the source for the modulator input: 00 modulator input is LOW 01 modulator input is HIGH 10 modulator input is the internal encoder 11 modulator input is pin MFIN 4 Force100ASK - forces a 100 % ASK modulation independent ModConductance register setting 3 TX2Inv 0 delivers an inverted 13.56 MHz energy carrier output signal on pin TX2 2 TX2Cw 1 delivers a continuously unmodulated 13.56 MHz energy carrier output signal on pin TX2 0 enables modulation of the 13.56 MHz energy carrier 1 TX2RFEn 1 the output signal on pin TX2 is the 13.56 MHz energy carrier modulated by the transmission data 0 TX2 is driven at a constant output level 0 TX1RFEn 1 the output signal on pin TX1 is the 13.56 MHz energy carrier modulated by the transmission data 0 TX1 is driven at a constant output levelCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 60 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.3.3 CwConductance register Selects the conductance of the antenna driver pins TX1 and TX2. See Section 9.9.3 on page 32 for detailed information about GsCfgCW[5:0]. 10.5.3.4 ModConductance register Defines the driver output conductance. Remark: When Force100ASK = logic 1, the GsCfgMod[5:0] value has no effect. See Section 9.9.3 on page 32 for detailed information about GsCfgMod[5:0]. Table 73. CwConductance register (address: 12h) reset value: 0011 1111b, 3Fh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 00 GsCfgCW[5:0] Access R/W R/W R/W Table 74. CwConductance register bit descriptions Bit Symbol Description 7 to 6 00 these values must not be changed 5 to 0 GsCfgCW[5:0] defines the conductance register value for the output driver. This can be used to regulate the output power/current consumption and operating distance. Table 75. ModConductance register (address: 13h) reset value: 0011 1111b, 3Fh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 00 GsCfgMod[5:0] Access R/W R/W R/W Table 76. ModConductance register bit descriptions Bit Symbol Description 7 to 6 00 these values must not be changed 5 to 0 GsCfgMod[5:0] defines the ModConductance register value for the output driver during modulation. This is used to regulate the modulation index.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 61 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.3.5 CoderControl register Sets the clock rate and the coding mode. Table 77. CoderControl register (address: 14h) reset value: 0001 1001b, 19h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SendOnePulse 0 CoderRate[2:0] TxCoding[2:0] Access R/W R/W R/W R/W Table 78. CoderControl register bit descriptions Bit Symbol Value Description 7 SendOnePulse 1 forced ISO/IEC 15693 modulation. This is used to switch to the next TimeSlot if the Inventory command is used. 0 this bit is not cleared automatically, it must be reset by the user to logic 0 6 0 - this value must not be changed 5 to 3 CoderRate[2:0] this register defines the clock rate for the encoder circuit 000 MIFARE 848 kBd 001 MIFARE 424 kBd 010 MIFARE 212 kBd 011 MIFARE 106 kBd; ISO/IEC 14443 A 100 ISO/IEC 14443 B 101 I-CODE1 standard mode and ISO/IEC 15693 (~52.97 kHz) 110 I-CODE1 fast mode (~26.48 kHz) 111 reserved 2 to 0 TxCoding[2:0] this register defines the bit coding mode and framing during transmission 000 NRZ according to ISO/IEC 14443 B 001 MIFARE, ISO/IEC 14443 A, (Miller coded) 010 reserved 011 reserved 100 I-CODE1 standard mode (1 out of 256 coding) 101 I-CODE1 fast mode (NRZ coding) 110 ISO/IEC 15693 standard mode (1 out of 256 coding) 111 ISO/IEC 15693 fast mode (1 out of 4 coding)CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 62 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.3.6 ModWidth register Selects the pulse-modulation width. 10.5.3.7 ModWidthSOF register Table 79. ModWidth register (address: 15h) reset value: 0001 0011b, 13h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol ModWidth[7:0] Access R/W Table 80. ModWidth register bit descriptions Bit Symbol Description 7 to 0 ModWidth[7:0] defines the width of the modulation pulse based on tmod = 2(ModWidth + 1) / fclk Table 81. ModWidthSOF register (address: 16h) reset value: 0011 1111b, 3Fh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol ModWidthSOF[7:0] Access R/W Table 82. ModWidthSOF register bit descriptions Bit Symbol Value Description 7 to 0 ModWidthSOF defines the width of the modulation pulse for SOF as tmod = 2(ModWidth + 1) / fclk the register settings are: 3Fh MIFARE and ISO/IEC 14443; modulation width SOF = 9.44 s 3Fh I-CODE1 standard mode; modulation width SOF = 9.44 s 73h I-CODE1 fast mode; modulation width SOF = 18.88 s 3Fh ISO/IEC 15693; modulation width SOF = 9.44 sCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 63 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.3.8 TypeBFraming Defines the framing for ISO/IEC 14443 B communication. Table 83. TypeBFraming register (address: 17h) reset value: 0011 1011b, 3Bh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol NoTxSOF NoTxEOF EOFWidth CharSpacing[2:0] SOFWidth[1:0] Access R/W R/W R/W R/W R/W Table 84. TypeBFraming register bit descriptions Bit Symbol Value Description 7 NoTxSOF 1 TxCoder suppresses the SOF 0 TxCoder does not suppress SOF 6 NoTxEOF 1 TxCoder suppresses the EOF 0 TxCoder does not suppress the EOF 5 EOFWidth 1 set the EOF to a length to 11 ETU 0 set the EOF to a length of 10 ETU 4 to 2 CharSpacing[2:0] set the EGT length between 0 and 7 ETU 1 to 0 SOFWidth[1:0] 00 sets the SOF to a length to 10 ETU LOW and 2 ETU HIGH 01 sets the SOF to a length of 10 ETU LOW and 3 ETU HIGH 10 sets the SOF to a length of 11 ETU LOW and 2 ETU HIGH 11 sets the SOF to a length of 11 ETU LOW and 3 ETU HIGHCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 64 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.4 Page 3: Receiver and decoder control 10.5.4.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 50. 10.5.4.2 RxControl1 register Controls receiver operation. Table 85. RxControl1 register (address: 19h) reset value: 0111 0011b, 73h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SubCPulses[2:0] ISOSelection[1:0] LPOff Gain[1:0] Access R/W R/W R/W R/W Table 86. RxControl1 register bit descriptions Bit Symbol Value Description 7 to 5 SubCPulses[2:0] defines the number of subcarrier pulses for each bit 000 1 pulse for each bit 001 2 pulses for each bit 010 4 pulses for each bit 011 8 pulses for each bit ISO/IEC 14443 A and ISO/IEC 14443 B 100 16 pulses for each bit I-CODE1, ISO/IEC 15693 101 reserved 110 reserved 111 reserved 4 to 3 ISOSelection[1:0] used to select the communication protocol 00 reserved 10 ISO/IEC 14443 A and ISO/IEC 14443 B 01 I-CODE1, ISO/IEC 15693 11 reserved 2 LPOff switches off a low-pass filter at the internal amplifier 1 to 0 Gain[1:0] defines the receiver’s signal voltage gain factor 00 20 dB gain factor 01 24 dB gain factor 10 31 dB gain factor 11 35 dB gain factorCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 65 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.4.3 DecoderControl register Controls decoder operation. 10.5.4.4 BitPhase register Selects the bit-phase between transmitter and receiver clock. Table 87. DecoderControl register (address: 1Ah) reset value: 0000 1000b, 08h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 0 RxMultiple ZeroAfterColl RxFraming[1:0] RxInvert 0 RxCoding Access R/W R/W R/W R/W R/W R/W R/W Table 88. DecoderControl register bit descriptions Bit Symbol Value Description 7 0 - this value must not be changed 6 RxMultiple 0 after receiving one frame, the receiver is deactivated 1 enables reception of more than one frame 5 ZeroAfterColl 1 any bits received after a bit-collision are masked to zero. This helps to resolve the anti-collision procedure as defined in ISO/IEC 14443 A 4 to 3 RxFraming[1:0] 00 I-CODE1 01 MIFARE or ISO/IEC 14443 A 10 ISO/IEC 15693 11 ISO/IEC 14443 B 2 RxInvert 0 modulation at the first half-bit results in logic 1 (I-CODE1) 1 modulation at the first half-bit results in logic 0 (ISO/IEC 15693) 1 0 - this value must not be changed 0 RxCoding 0 Manchester encoding 1 BPSK encoding Table 89. BitPhase register (address: 1Bh) reset value: 1010 1101b, ADh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol BitPhase[7:0] Access R/W Table 90. BitPhase register bit descriptions Bit Symbol Description 7 to 0 BitPhase defines the phase relationship between transmitter and receiver clock Remark: The correct value of this register is essential for proper operation.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 66 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.4.5 RxThreshold register Selects thresholds for the bit decoder. 10.5.4.6 BPSKDemControl Controls BPSK demodulation. Table 91. RxThreshold register (address: 1Ch) reset value: 1111 1111b, FFh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol MinLevel[3:0] CollLevel[3:0] Access R/W R/W Table 92. RxThreshold register bit descriptions Bit Symbol Description 7 to 4 MinLevel[3:0] the minimum signal strength the decoder will accept. If the signal strength is below this level, it is not evaluated. 3 to 0 CollLevel[3:0] the minimum signal strength the decoder input that must be reached by the weaker half-bit of the Manchester encoded signal to generate a bit-collision (relative to the amplitude of the stronger half-bit) Table 93. BPSKDemControl register (address: 1Dh) reset value: 0001 1110b, 1Eh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol NoRxSOF NoRxEGT NoRxEOF FilterAmpDet TauD[1:0] TauB[1:0] Access R/W R/W R/W R/W R/W R/W Table 94. BPSKDemControl register bit descriptions Bit Symbol Value Description 7 NoRxSOF 1 a missing SOF in the received data stream is ignored and no framing errors are indicated 0 a missing SOF in the received data stream generates framing errors 6 NoRxEGT 1 an EGT which is too short or too long in the received data stream is ignored and no framing errors are indicated 0 an EGT which is too short or too long in the received data stream will cause framing errors 5 NoRxEOF 1 a missing EOF in the received data stream is ignored and no framing errors indicated 0 a missing EOF in the receiving data stream produces framing errors 4 FilterAmpDet - switches on a high-pass filter for amplitude detection 3 to 2 TauD[1:0] - changes the time constant of the internal PLL whilst receiving data 1 to 0 TauB[1:0] - changes the time constant of the internal PLL during data burstsCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 67 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.4.7 RxControl2 register Controls decoder behavior and defines the input source for the receiver. [1] I-clock and Q-clock are 90 phase-shifted from each other. 10.5.4.8 ClockQControl register Controls clock generation for the 90 phase-shifted Q-clock. Table 95. RxControl2 register (address: 1Eh) reset value: 0100 0001b, 41h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol RcvClkSelI RxAutoPD 0000 DecoderSource[1:0] Access R/W R/W R/W R/W Table 96. RxControl2 register bit descriptions Bit Symbol Value Description 7 RcvClkSelI 1 I-clock is used as the receiver clock[1] 0 Q-clock is used as the receiver clock[1] 6 RxAutoPD 1 receiver circuit is automatically switched on before receiving and switched off afterwards. This can be used to reduce current consumption. 0 receiver is always activated 5 to 2 0000 - these values must not be changed 1 to 0 DecoderSource[1:0] selects the source for the decoder input 00 LOW 01 internal demodulator 10 a subcarrier modulated Manchester encoded signal on pin MFIN 11 a baseband Manchester encoded signal on pin MFIN Table 97. ClockQControl register (address: 1Fh) reset value: 000x xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol ClkQ180Deg ClkQCalib 0 ClkQDelay[4:0] Access R R/W R/W D Table 98. ClockQControl register bit descriptions Bit Symbol Value Description 7 ClkQ180Deg 1 Q-clock is phase-shifted more than 180 compared to the I-clock 0 Q-clock is phase-shifted less than 180 compared to the I-clock 6 ClkQCalib 0 Q-clock is automatically calibrated after the reset phase and after data reception from the card 1 no calibration is performed automatically 5 0 - this value must not be changed 4 to 0 ClkQDelay[4:0] - this register shows the number of delay elements used to generate a 90 phase-shift of the I-clock to obtain the Q-clock. It can be written directly by the microprocessor or by the automatic calibration cycle.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 68 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.5 Page 4: RF Timing and channel redundancy 10.5.5.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 50. 10.5.5.2 RxWait register Selects the time interval after transmission, before the receiver starts. 10.5.5.3 ChannelRedundancy register Selects kind and mode of checking the data integrity on the RF channel. Table 99. RxWait register (address: 21h) reset value: 0000 0101b, 06h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol RxWait[7:0] Access R/W Table 100. RxWait register bit descriptions Bit Symbol Function 7 to 0 RxWait[7:0] after data transmission, the activation of the receiver is delayed for RxWait bit-clock cycles. During this frame guard time any signal on pin RX is ignored. Table 101. ChannelRedundancy register (address: 22h) reset value: 0000 0011b, 03h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 00 CRC3309 CRC8 RxCRCEn TxCRCEn ParityOdd ParityEn Access R/W R/W R/W R/W R/W R/W R/W R/W Table 102. ChannelRedundancy bit descriptions Bit Symbol Value Function 7 to 6 00 - this value must not be changed 5 CRC3309 1 CRC calculation is performed using ISO/IEC 3309 (ISO/IEC 14443 B) and ISO/IEC 15693 0 CRC calculation is performed using ISO/IEC 14443 A and I-CODE1 4 CRC8 1 an 8-bit CRC is calculated 0 a 16-bit CRC is calculated 3 RxCRCEn 1 the last byte(s) of a received frame are interpreted as CRC bytes. If the CRC is correct, the CRC bytes are not passed to the FIFO. If the CRC bytes are incorrect, the CRCErr flag is set. 0 no CRC is expected 2 TxCRCEn 1 a CRC is calculated over the transmitted data and the CRC bytes are appended to the data stream 0 no CRC is transmittedCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 69 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution [1] When used with ISO/IEC 14443 A, this bit must be set to logic 1. 10.5.5.4 CRCPresetLSB register LSB of the preset value for the CRC register. [1] To use the ISO/IEC 15693 functionality, the CRCPresetLSB register has to be set to FFh. 10.5.5.5 CRCPresetMSB register MSB of the preset value for the CRC register. 10.5.5.6 TimeSlotPeriod register Defines the time-slot period for I-CODE1 protocol. 1 ParityOdd 1 odd parity is generated or expected[1] 0 even parity is generated or expected 0 ParityEn 1 a parity bit is inserted in the transmitted data stream after each byte and expected in the received data stream after each byte (MIFARE, ISO/IEC 14443 A) 0 no parity bit is inserted or expected (ISO/IEC 14443 B) Table 102. ChannelRedundancy bit descriptions …continued Bit Symbol Value Function Table 103. CRCPresetLSB register (address: 23h) reset value: 0101 0011b, 63h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CRCPresetLSB[7:0] Access R/W Table 104. CRCPresetLSB register bit descriptions Bit Symbol Description 7 to 0 CRCPresetLSB[7:0] defines the start value for CRC calculation. This value is loaded into the CRC at the beginning of transmission, reception and the CalcCRC command (if CRC calculation is enabled)[1]. Table 105. CRCPresetMSB register (address: 24h) reset value: 0101 0011b, 63h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CRCPresetMSB[7:0] Access R/W Table 106. CRCPresetMSB bit descriptions Bit Symbol Description 7 to 0 CRCPresetMSB[7:0] defines the starting value for CRC calculation. This value is loaded into the CRC at the beginning of transmission, reception and the CalcCRC command (if the CRC calculation is enabled) Remark: This register is not relevant if CRC8 is set to logic 1. Table 107. TimeSlotPeriod register (address: 25h) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol TimeSlotPeriod[7:0] Access R/WCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 70 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.5.7 MFOUTSelect register Selects the internal signal applied to pin MFOUT. [1] Only valid for MIFARE and ISO/IEC 14443 A communication at 106 kBd. 10.5.5.8 PreSet27 register Table 108. TimeSlotPeriod register bit descriptions Bit Symbol Description 7 to 0 TimeSlotPeriod[7:0] defines the time between automatically transmitted frames. To send a Quit frame using the I-CODE1 protocol it is necessary to relate to the beginning of the command frame. The TimeSlotPeriod starts at the end of the command transmission. See Section 9.5.1.5 on page 26 for additional information. Table 109. MFOUTSelect register (address: 26h) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 000 TimeSlotPeriodMSB 0 MFOUTSelect[2:0] Access R/W R/W R/W R/W R/W R/W Table 110. MFOUTSelect register bit descriptions Bit Symbol Value Description 7 to 5 000 - these values must not be changed 4 TimeSlotPeriodMSB - MSB of value TimeSlotPeriod; see Table 107 on page 69 for more detailed information 3 0 - this value must not be changed 2 to 0 MFOUTSelect[2:0] defines which signal is routed to pin MFOUT: 000 constant LOW 001 constant HIGH 010 modulation signal (envelope) from the internal encoder, (Miller coded) 011 serial data stream, not Miller encoded 100 output signal of the energy carrier demodulator (card modulation signal)[1] 101 output signal of the subcarrier demodulator (Manchester encoded card signal)[1] 110 reserved 111 reserved Table 111. PreSet27 (address: 27h) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol x x x x x x x x Access W W W W W W W WCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 71 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.6 Page 5: FIFO, timer and IRQ pin configuration 10.5.6.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 50. 10.5.6.2 FIFOLevel register Defines the levels for FIFO underflow and overflow warning. 10.5.6.3 TimerClock register Selects the divider for the timer clock. Table 112. FIFOLevel register (address: 29h) reset value: 0000 1000b, 08h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 00 WaterLevel[5:0] Access R/W R/W R/W Table 113. FIFOLevel register bit descriptions Bit Symbol Description 7 to 6 00 these values must not be changed 5 to 0 WaterLevel[5:0] defines, the warning level of a FIFO buffer overflow or underflow: HiAlert is set to logic 1 if the remaining FIFO buffer space is equal to, or less than, WaterLevel[5:0] bits in the FIFO buffer. LoAlert is set to logic 1 if equal to, or less than, WaterLevel[5:0] bits in the FIFO buffer. Table 114. TimerClock register (address: 2Ah) reset value: 0000 0111b, 07h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 00 TAutoRestart TPreScaler[4:0] Access RW RW RW RW Table 115. TimerClock register bit descriptions Bit Symbol Value Function 7 to 6 00 - these values must not be changed 5 TAutoRestart 1 the timer automatically restarts its countdown from the TReloadValue[7:0] instead of counting down to zero 0 the timer decrements to zero and register InterruptIrq TimerIRq bit is set to logic 1 4 to 0 TPreScaler[4:0] - defines the timer clock frequency (fTimerClock). The TPreScaler[4:0] can be adjusted from 0 to 21. The following formula is used to calculate the TimerClock frequency (fTimerClock): fTimerClock = 13.56 MHz / 2TPreScaler [MHz]CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 72 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.6.4 TimerControl register Selects start and stop conditions for the timer. 10.5.6.5 TimerReload register Defines the preset value for the timer. Table 116. TimerControl register (address: 2Bh) reset value: 0000 0110b, 06h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 0000 TStopRxEnd TStopRxBegin TStartTxEnd TStartTxBegin Access R/W R/W R/W R/W R/W Table 117. TimerControl register bit descriptions Bit Symbol Value Description 7 to 4 0000 - these values must not be changed 3 TStopRxEnd 1 the timer automatically stops when data reception ends 0 the timer is not influenced by this condition 2 TStopRxBegin 1 the timer automatically stops when the first valid bit is received 0 the timer is not influenced by this condition 1 TStartTxEnd 1 the timer automatically starts when data transmission ends. If the timer is already running, the timer restarts by loading TReloadValue[7:0] into the timer. 0 the timer is not influenced by this condition 0 TStartTxBegin 1 the timer automatically starts when the first bit is transmitted. If the timer is already running, the timer restarts by loading TReloadValue[7:0] into the timer. 0 the timer is not influenced by this condition Table 118. TimerReload register (address: 2Ch) reset value: 0000 1010b, 0Ah bit allocation Bit 7 6 5 4 3 2 1 0 Symbol TReloadValue[7:0] Access R/W Table 119. TimerReload register bit descriptions Bit Symbol Description 7 to 0 TReloadValue[7:0] on a start event, the timer loads the TReloadValue[7:0] value. Changing this register only affects the timer on the next start event. If TReloadValue[7:0] is set to logic 0 the timer cannot start.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 73 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.6.6 IRQPinConfig register Configures the output stage for pin IRQ. 10.5.6.7 PreSet2E register 10.5.6.8 PreSet2F register 10.5.7 Page 6: reserved 10.5.7.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 50. 10.5.7.2 Reserved registers 31h, 32h, 33h, 34h, 35h, 36h and 37h Remark: These registers are reserved for future use. Table 120. IRQPinConfig register (address: 2Dh) reset value: 0000 0010b, 02h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 000000 IRQInv IRQPushPull Access R/W R/W R/W Table 121. IRQPinConfig register bit descriptions Bit Symbol Value Description 7 to 2 000000 - these values must not be changed 1 IRQInv 1 inverts the signal on pin IRQ with respect to bit IRq 0 the signal on pin IRQ is not inverted and is the same as bit IRq 0 IRQPushPull 1 pin IRQ functions as a standard CMOS output pad 0 pin IRQ functions as an open-drain output pad Table 122. PreSet2E register (address: 2Eh) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol x x x x x x x x Access W W W W W W W W Table 123. PreSet2F register (address: 2Fh) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol x x x x x x x x Access W W W W W W W W Table 124. Reserved registers (address: 31h, 32h, 33h, 34h, 35h, 36h, 37h) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol x x x x x x x x Access R/W R/W R/W R/W R/W R/W R/W R/WCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 74 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.8 Page 7: Test control 10.5.8.1 Page register Selects the page register; see Section 10.5.1.1 “Page register” on page 50. 10.5.8.2 Reserved register 39h Remark: This register is reserved for future use. 10.5.8.3 TestAnaSelect register Selects analog test signals. Table 125. Reserved register (address: 39h) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol x x x x x x x x Access W W W W W W W W Table 126. TestAnaSelect register (address: 3Ah) reset value: 0000 0000b, 00h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 0000 TestAnaOutSel[4:0] Access W W Table 127. TestAnaSelect bit descriptions Bit Symbol Value Description 7 to 4 0000 - these values must not be changed 3 to 0 TestAnaOutSel[4:0] selects the internal analog signal to be routed to pin AUX. See Section 15.2.2 on page 112 for detailed information. The settings are as follows: 0 VMID 1 Vbandgap 2 VRxFollI 3 VRxFollQ 4 VRxAmpI 5 VRxAmpQ 6 VCorrNI 7 VCorrNQ 8 VCorrDI 9 VCorrDQ A VEvalL B VEvalR C VTemp D reserved E reserved F reservedCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 75 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.8.4 Reserved register 3Bh Remark: This register is reserved for future use. 10.5.8.5 Reserved register 3Ch Remark: This register is reserved for future use. 10.5.8.6 TestDigiSelect register Selects digital test mode. Table 128. Reserved register (address: 3Bh) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol x x x x x x x x Access W W W W W W W W Table 129. Reserved register (address: 3Ch) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol x x x x x x x x Access W W W W W W W W Table 130. TestDigiSelect register (address: 3Dh) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SignalToMFOUT TestDigiSignalSel[6:0] Access W W Table 131. TestDigiSelect register bit descriptions Bit Symbol Value Description 7 SignalToMFOUT 1 overrules the MFOUTSelect[2:0] setting and routes the digital test signal defined with the TestDigiSignalSel[6:0] bits to pin MFOUT 0 MFOUTSelect[2:0] defines the signal on pin MFOUT 6 to 0 TestDigiSignalSel[6:0] - selects the digital test signal to be routed to pin MFOUT. Refer to Section 15.2.3 on page 113 for detailed information. The following lists the signal names for the TestDigiSignalSel[6:0] addresses: F4h s_data E4h s_valid D4h s_coll C4h s_clock B5h rd_sync A5h wr_sync 96h int_clock 83h BPSK_out E2h BPSK_sigCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 76 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 10.5.8.7 Reserved registers 3Eh, 3Fh Remark: This register is reserved for future use. 11. CLRC632 command set CLRC632 operation is determined by an internal state machine capable of performing a command set. The commands can be started by writing the command code to the Command register. Arguments and/or data necessary to process a command are mainly exchanged using the FIFO buffer. • Each command needing a data stream (or data byte stream) as an input immediately processes the data in the FIFO buffer • Each command that requires arguments only starts processing when it has received the correct number of arguments from the FIFO buffer • The FIFO buffer is not automatically cleared at the start of a command. It is, therefore, possible to write command arguments and/or the data bytes into the FIFO buffer before starting a command. • Each command (except the StartUp command) can be interrupted by the microprocessor writing a new command code to the Command register e.g. the Idle command. 11.1 CLRC632 command overview Table 132. Reserved register (address: 3Eh, 3Fh) reset value: xxxx xxxxb, xxh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol x x x x x x x x Access W W W W W W W W Table 133. CLRC632 commands overview Command Value Action FIFO communication Arguments and data sent Data received StartUp 3Fh runs the reset and initialization phase. See Section 11.1.2 on page 78. Remark: This command can only be activated by Power-On or Hard resets. - - Idle 00h no action; cancels execution of the current command. See Section 11.1.3 on page 78 - - Transmit 1Ah transmits data from the FIFO buffer to the card. See Section 11.2.1 on page 79 data stream - Receive 16h activates receiver circuitry. Before the receiver starts, the state machine waits until the time defined in the RxWait register has elapsed. See Section 11.2.2 on page 82. Remark: This command may be used for test purposes only, since there is no timing relationship to the Transmit command. - data streamCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 77 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution [1] This command is the combination of the Transmit and Receive commands. [2] Relates to MIFARE Mini/MIFARE 1K/MIFARE 4K security. Transceive[1] 1Eh transmits data from FIFO buffer to the card and automatically activates the receiver after transmission. The receiver waits until the time defined in the RxWait register has elapsed before starting. See Section 11.2.3 on page 85. data stream data stream WriteE2 01h reads data from the FIFO buffer and writes it to the EEPROM. See Section 11.4.1 on page 93. start address LSB - start address MSB data byte stream ReadE2 03h reads data from the EEPROM and sends it to the FIFO buffer. See Section 11.4.2 on page 95. Remark: Keys cannot be read back start address LSB data bytes start address MSB number of data bytes LoadKeyE2 0Bh copies a key from the EEPROM into the key buffer[2] See Section 11.7.1 on page 97. start address LSB - start address MSB LoadKey 19h reads a key from the FIFO buffer and loads it into the key buffer[2]. See Section 11.7.2 on page 97. Remark: The key has to be prepared in a specific format (refer to Section 9.2.3.1 “Key format” on page 18) byte 0 LSB - byte 1 … byte 10 byte 11 MSB Authent1 0Ch performs the first part of card authentication using the Crypto1 algorithm[2]. See Section 11.7.3 on page 98. card Authent1 command - card block address card serial number LSB card serial number byte 1 card serial number byte 2 card serial number MSB Authent2 14h performs the second part of card authentication using the Crypto1 algorithm[2]. See Section 11.7.4 on page 98. - - LoadConfig 07h reads data from EEPROM and initializes the CLRC632 registers. See Section 11.5.1 on page 95. start address LSB - start address MSB CalcCRC 12h activates the CRC coprocessor Remark: The result of the CRC calculation is read from the CRCResultLSB and CRCResultMSB registers. See Section 11.5.2 on page 96. data byte stream - Table 133. CLRC632 commands overview …continued Command Value Action FIFO communication Arguments and data sent Data receivedCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 78 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.1.1 Basic states 11.1.2 StartUp command 3Fh Remark: This command can only be activated by a Power-On or Hard reset. The StartUp command runs the reset and initialization phases. It does not need or return, any data. It cannot be activated by the microprocessor but is automatically started after one of the following events: • Power-On Reset (POR) caused by power-up on pin DVDD • POR caused by power-up on pin AVDD • Negative edge on pin RSTPD The reset phase comprises an asynchronous reset and configuration of certain register bits. The initialization phase configures several registers with values stored in the EEPROM. When the StartUp command finishes, the Idle command is automatically executed. Remark: • The microprocessor must not write to the CLRC632 while it is still executing the StartUp command. To avoid this, the microprocessor polls for the Idle command to determine when the initialization phase has finished; see Section 9.7.4 on page 30. • When the StartUp command is active, it is only possible to read from the Page 0 register. • The StartUp command cannot be interrupted by the microprocessor. 11.1.3 Idle command 00h The Idle command switches the CLRC632 to its inactive state where it waits for the next command. It does not need or return, any data. The device automatically enters the idle state when a command finishes. When this happens, the CLRC632 sends an interrupt request by setting bit IdleIRq. When triggered by the microprocessor, the Idle command can be used to stop execution of all other commands (except the StartUp command) but this does not generate an interrupt request (IdleIRq). Remark: Stopping command execution with the Idle command does not clear the FIFO buffer. Table 134. StartUp command 3Fh Command Value Action Arguments and data Returned data StartUp 3Fh runs the reset and initialization phase - - Table 135. Idle command 00h Command Value Action Arguments and data Returned data Idle 00h no action; cancels current command execution - -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 79 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.2 Commands for ISO/IEC 14443 A card communication The CLRC632 is a fully ISO/IEC 14443 A, ISO/IEC 14443 B, ISO/IEC 15693 and I-CODE1 compliant reader IC. This enables the command set to be more flexible and generalized when compared to dedicated MIFARE or I-CODE1 reader ICs. Section 11.2.1 to Section 11.2.5 describe the command set for ISO/IEC 14443 A card communication and related communication protocols. 11.2.1 Transmit command 1Ah The Transmit command reads data from the FIFO buffer and sends it to the transmitter. It does not return any data. The Transmit command can only be started by the microprocessor. 11.2.1.1 Using the Transmit command To transmit data, one of the following sequences can be used: 1. All data to be transmitted to the card is written to the FIFO buffer while the Idle command is active. Then the command code for the Transmit command is written to the Command register. Remark: This is possible for transmission of a data stream up to 64 bytes. 2. The command code for the Transmit command is stored in the Command register. Since there is not any data available in the FIFO buffer, the command is only enabled but transmission is not activated. Data transmission starts when the first data byte is written to the FIFO buffer. To generate a continuous data stream on the RF interface, the microprocessor must write the subsequent data bytes into the FIFO buffer in time. Remark: This allows transmission of any data stream length but it requires data to be written to the FIFO buffer in time. 3. Part of the data transmitted to the card is written to the FIFO buffer while the Idle command is active. Then the command code for the Transmit command is written to the Command register. While the Transmit command is active, the microprocessor can send further data to the FIFO buffer. This is then appended by the transmitter to the transmitted data stream. Remark: This allows transmission of any data stream length but it requires data to be written to the FIFO buffer in time. When the transmitter requests the next data byte to ensure the data stream on the RF interface is continuous and the FIFO buffer is empty, the Transmit command automatically terminates. This causes the internal state machine to change its state from transmit to idle. When the data transmission to the card is finished, the TxIRq flag is set by the CLRC632 to indicate to the microprocessor transmission is complete. Remark: If the microprocessor overwrites the transmit code in the Command register with another command, transmission stops immediately on the next clock cycle. This can produce output signals that are not in accordance with ISO/IEC 14443 A. Table 136. Transmit command 1Ah Command Value Action Arguments and data Returned data Transmit 1Ah transmits data from FIFO buffer to card data stream -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 80 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.2.1.2 RF channel redundancy and framing Each ISO/IEC 14443 A transmitted frame consists of a Start Of Frame (SOF) pattern, followed by the data stream and is closed by an End Of Frame (EOF) pattern. These different phases of the transmission sequence can be monitored using the PrimaryStatus register ModemState[2:0] bit; see Section 11.2.4 on page 85. Depending on the setting of the ChannelRedundancy register bit TxCRCEn, the CRC is calculated and appended to the data stream. The CRC is calculated according to the settings in the ChannelRedundancy register. Parity generation is handled according to the ChannelRedundancy register ParityEn and ParityOdd bits settings. 11.2.1.3 Transmission of bit oriented frames The transmitter can be configured to send an incomplete last byte. To achieve this the BitFraming register’s TxLastBits[2:0] bits must be set at above zero (for example, 1). This is shown in Figure 16. Figure 16 shows the data stream if bit ParityEn is set in the ChannelRedundancy register. All fully transmitted bytes are followed by a parity check bit but the incomplete byte is not followed by a parity check bit. After transmission, the TxLastBits[2:0] bits are automatically cleared. Remark: If the TxLastBits[2:0] bits are not equal to zero, CRC generation must be disabled. This is done by clearing the ChannelRedundancy register TxCRCEn bit. 11.2.1.4 Transmission of frames with more than 64 bytes To generate frames of more than 64 bytes, the microprocessor must write data to the FIFO buffer while the Transmit command is active. The state machine checks the FIFO buffer status when it starts transmitting the last bit of the data stream; the check time is marked in Figure 17 with arrows. Fig 16. Transmitting bit oriented frames 001aak618 TxLastBits = 0 TxLastBits = 7 TxLastBits = 1 SOF 0 7 P 0 7 P SOF SOF EOF EOF EOF 0 7 P 0 6 0 7 P 0CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 81 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution As long as the internal accept further data signal is logic 1, further data can be written to the FIFO buffer. The CLRC632 appends this data to the data stream transmitted using the RF interface. If the internal accept further data signal is logic 0, the transmission terminates. All data written to the FIFO buffer after accept further data signal was set to logic 0 is not transmitted, however, it remains in the FIFO buffer. Remark: If parity generation is enabled (ParityEn = logic 1), the parity bit is the last bit transmitted. This delays the accept further data signal by a duration of one bit. If the TxLastBits[2:0] bits are not zero, the last byte is not transmitted completely. Only the number of bits set by TxLastBits[2:0], starting with the least significant bit are transmitted. This means that the internal state machine has to check the FIFO buffer status at an earlier point in time; see Figure 18. Since in this example TxLastBits[2:0] = 4, transmission stops after bit 3 is transmitted and the frame is completed with an EOF, if configured. Fig 17. Timing for transmitting byte oriented frames Fig 18. Timing for transmitting bit oriented frames 001aak619 accept further data check FIFO empty TxData FIFO empty FIFOLength[6:0] 01h 00h TxLastBits[2:0] TxLastBits = 0 7 0 7 0 7 001aak620 accept further data check FIFO empty TxData FIFO empty FIFOLength[6:0] 01h 00h 01h 00h TxLastBits[2:0] TxLastBits = 4 NWR (FIFO data) 4 7 0 3 4 7 0 3CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 82 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Figure 18 also shows write access to the FIFOData register just before the FIFO buffer’s status is checked. This leads to FIFO empty state being held LOW which keeps the accept further data active. The new byte written to the FIFO buffer is transmitted using the RF interface. Accept further data is only changed by the check FIFO empty function. This function verifies FIFO empty for one bit duration before the last expected bit transmission. 11.2.2 Receive command 16h The Receive command activates the receiver circuitry. All data received from the RF interface is written to the FIFO buffer. The Receive command can be started either using the microprocessor or automatically during execution of the Transceive command. Remark: This command can only be used for test purposes since there is no timing relationship to the Transmit command. 11.2.2.1 Using the Receive command After starting the Receive command, the internal state machine decrements to the RxWait register value on every bit-clock. The analog receiver circuitry is prepared and activated from 3 down to 1. When the counter reaches 0, the receiver starts monitoring the incoming signal at the RF interface. When the signal strength reaches a level higher than the RxThreshold register MinLevel[3:0] bits value, it starts decoding. The decoder stops when the signal can longer be detected on the receiver input pin RX. The decoder sets bit RxIRq indicating receive termination. The different phases of the receive sequence are monitored using the PrimaryStatus register ModemState[2:0] bits; see Section 11.2.4 on page 85. Remark: Since the counter values from 3 to 0 are needed to initialize the analog receiver circuitry, the minimum value for RxWait[7:0] is 3. 11.2.2.2 RF channel redundancy and framing The decoder expects the SOF pattern at the beginning of each data stream. When the SOF is detected, it activates the serial-to-parallel converter and gathers the incoming data bits. Every completed byte is forwarded to the FIFO buffer. Table 137. Transmission of frames of more than 64 bytes Frame definition Verification at: 8-bit with parity 8th bit 8-bit without parity 7th bit x-bit without parity (x 1)th bit Table 138. Receive command 16h Command Value Action Arguments and data Returned data Receive 16h activates receiver circuitry - data streamCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 83 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution If an EOF pattern is detected or the signal strength falls below the RxThreshold register MinLevel[3:0] bits setting, both the receiver and the decoder stop. Then the Idle command is entered and an appropriate response for the microprocessor is generated (interrupt request activated, status flags set). When the ChannelRedundancy register bit RxCRCEn is set, a CRC block is expected. The CRC block can be one byte or two bytes depending on the ChannelRedundancy register CRC8 bit setting. Remark: If the CRC block received is correct, it is not sent to the FIFO buffer. This is realized by shifting the incoming data bytes through an internal buffer of either one or two bytes (depending on the defined CRC). The CRC block remains in this internal buffer. Consequently, all data bytes in the FIFO buffer are delayed by one or two bytes. If the CRC fails, all received bytes are sent to the FIFO buffer including the faulty CRC. If ParityEn is set in the ChannelRedundancy register, a parity bit is expected after each byte. If ParityOdd = logic 1, the expected parity is odd, otherwise even parity is expected. 11.2.2.3 Collision detection If more than one card is within the RF field during the card selection phase, they both respond simultaneously. The CLRC632 supports the algorithm defined in ISO/IEC 14443 A to resolve card serial number data collisions by performing the anti-collision procedure. The basis for this procedure is the ability to detect bit-collisions. Bit-collision detection is supported by the Manchester coding bit encoding scheme used in the CLRC632. If in the first and second half-bit of a subcarrier, modulation is detected, instead of forwarding a 1-bit or 0-bit, a bit-collision is indicated. The CLRC632 uses the RxThreshold register CollLevel[3:0] bits setting to distinguish between a 1-bit or 0-bit and a bit-collision. If the amplitude of the half-bit with smaller amplitude is larger than that defined by the CollLevel[3:0] bits, the CLRC632 flags a bit-collision using the error flag CollErr. If a bit-collision is detected in a parity bit, the ParityErr flag is set. On a detected collision, the receiver continues receiving the incoming data stream. In the case of a bit-collision, the decoder sends logic 1 at the collision position. Remark: As an exception, if bit ZeroAfterColl is set, all bits received after the first bit-collision are forced to zero, regardless whether a bit-collision or an unequivocal state has been detected. This feature makes it easier for the control software to perform the anti-collision procedure as defined in ISO/IEC 14443 A. When the first bit collision in a frame is detected, the bit-collision position is stored in the CollPos register. Table 139 shows the collision positions.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 84 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Parity bits are not counted in the CollPos register because bit-collisions in parity bit occur after bit-collisions in the data bits. If a collision is detected in the SOF, a frame error is flagged and no data is sent to the FIFO buffer. In this case, the receiver continues to monitor the incoming signal. It generates the correct notifications to the microprocessor when the end of the faulty input stream is detected. This helps the microprocessor to determine when it is next allowed to send data to the card. 11.2.2.4 Receiving bit oriented frames The receiver can manage byte streams with incomplete bytes which result in bit-oriented frames. To support this, the following values may be used: • BitFraming register’s RxAlign[2:0] bits select a bit offset for the first incoming byte. For example, if RxAlign[2:0] = 3, the first 5 bits received are forwarded to the FIFO buffer. Further bits are packed into bytes and forwarded. After reception, RxAlign[2:0] is automatically cleared. If RxAlign[2:0] = logic 0, all incoming bits are packed into one byte. • RxLastBits[2:0] returns the number of bits valid in the last received byte. For example, if RxLastBits[2:0] evaluates to 5 bits at the end of the received command, the 5 least significant bits are valid. If the last byte is complete, RxLastBits[2:0] evaluates to zero. RxLastBits[2:0] is only valid if a frame error is not indicated by the FramingErr flag. If RxAlign[2:0] is not zero and ParityEn is active, the first parity bit is ignored and not checked. 11.2.2.5 Communication errors The events which can set error flags are shown in Table 140. Table 139. Return values for bit-collision positions Collision in bit CollPos register value (Decimal) SOF 0 Least Significant Bit (LSB) of the Least Significant Byte (LSByte) 1 … … Most Significant Bit (MSB) of the LSByte 8 LSB of second byte 9 … … MSB of second byte 16 LSB of third byte 17 … … Table 140. Communication error table Cause Flag bit Received data did not start with the SOF pattern FramingErr CRC block is not equal to the expected value CRCErr Received data is shorter than the CRC block CRCErr The parity bit is not equal to the expected value (i.e. a bit-collision, not parity) ParityErr A bit-collision is detected CollErrCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 85 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.2.3 Transceive command 1Eh The Transceive command first executes the Transmit command (see Section 11.2.1 on page 79) and then starts the Receive command (see Section 11.2.2 on page 82). All data transmitted is sent using the FIFO buffer and all data received is written to the FIFO buffer. The Transceive command can only be started by the microprocessor. Remark: To adjust the timing relationship between transmitting and receiving, use the RxWait register. This register is used to define the time delay between the last bit transmitted and activation of the receiver. In addition, the BitPhase register determines the phase-shift between the transmitter and receiver clock. 11.2.4 States of the card communication The status of the transmitter and receiver state machine can be read from bits ModemState[2:0] in the PrimaryStatus register. The assignment of ModemState[2:0] to the internal action is shown in Table 142. Table 141. Transceive command 1Eh Command Value Action Arguments and data Returned data Transceive 1Eh transmits data from FIFO buffer to the card and then automatically activates the receiver data stream data stream Table 142. Meaning of ModemState ModemState [2:0] State Description 000 Idle transmitter and/or receiver are not operating 001 TxSOF transmitting the SOF pattern 010 TxData transmitting data from the FIFO buffer (or redundancy CRC check bits) 011 TxEOF transmitting the EOF pattern 100 GoToRx1 intermediate state passed, when receiver starts GoToRx2 intermediate state passed, when receiver finishes 101 PrepareRx waiting until the RxWait register time period expires 110 AwaitingRx receiver activated; waiting for an input signal on pin RXCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 86 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.2.5 Card communication state diagram Fig 19. Card communication state diagram 001aak621 end of receive frame and RxMultiple = 0 RxMultiple = 1 EOF transmitted and command = Transceive FIFO not empty and command = Transmit or Transceive command = Receive COMMAND = TRANSMIT, RECEIVE OR TRANSCEIVE SET COMMAND REGISTER = IDLE (000) Awaiting Rx (110) RECEIVING (111) GoToRx2 (100) Prepare Rx (101) GoToRx1 (100) TxEOF (011) TxData (010) TxSOF (001) IDLE (000) SOF transmitted next bit clock data transmitted RxWaitC[7:0] = 0 EOF transmitted and command = Transmit signal strength > MinLevel[3:0] frame receivedCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 87 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.3 I-CODE1 and ISO/IEC 15693 label communication commands The CLRC632 is a fully ISO/IEC 14443 A, ISO/IEC 14443 B, ISO/IEC 15693 and I-CODE1 compliant reader IC. This enables the command set to be more flexible and generalized when compared to dedicated MIFARE or I-CODE1 reader ICs. Section 11.3.1 to Section 11.3.5 give an overview of the command set for I-CODE1 and ISO/IEC 15693 card communication and related communication protocols. 11.3.1 Transmit command 1Ah The Transmit command reads data from the FIFO buffer and sends it to the transmitter. It does not return any data. The Transmit command can only be started by the microprocessor. 11.3.1.1 Using the Transmit command To transmit data, one of the following sequences can be used: 1. All data to be transmitted to the label is written to the FIFO buffer while the Idle command is active. Then the command code for the Transmit command is written to the Command register. Remark: This is possible for transmission of a data stream up to 64 bytes long. 2. The command code for the Transmit command is stored in the Command register. Since there is not any data available in the FIFO buffer, the command is only enabled but transmission is not triggered. Data transmission starts when the first data byte is written to the FIFO buffer. To generate a continuous data stream on the RF interface, the microprocessor must write the subsequent data bytes into the FIFO buffer in time. Remark: This allows transmission of any data stream length but it requires data to be written to the FIFO buffer in time. 3. Part of the data transmitted to the label is written to the FIFO buffer while the Idle command is active. Then the command code for the Transmit command is written to the Command register. While the Transmit command is active, the microprocessor can send further data to the FIFO buffer. This is then appended by the transmitter to the transmitted data stream. Remark: This allows transmission of any data stream length but it requires data to be written to the FIFO buffer in time. When the transmitter requests the next data byte, to ensure that the data stream on the RF interface is continuous and the FIFO buffer is empty, the Transmit command automatically terminates. This causes the internal state machine to change its state from transmit to idle. When the data transmission to the label is finished, the TxIRq flag is set by the CLRC632 to indicate transmission is complete to the microprocessor. Remark: If the microprocessor overwrites the transmit code in the Command register with another command, transmission stops immediately on the next clock cycle. This can produce output signals that do not comply with the ISO/IEC 15693 standard or the I-CODE1 protocol. Table 143. Transmit command 1Ah Command Value Action Arguments and data Returned data Transmit 1Ah transmits data from FIFO buffer to the label data stream -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 88 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.3.1.2 RF channel redundancy and framing Each transmitted ISO/IEC 15693 frame consists of a Start Of Frame (SOF) pattern, followed by the data stream and is closed by an End Of Frame (EOF) pattern. All I-CODE1 command frames consists of a start pulse followed by the data stream. The I-CODE1 commands have a fixed length and do not need an EOF. The phases of the transmission sequence are monitored using the PrimaryStatus register’s ModemState[2:0] bits; see Section 11.2.4 on page 85. Depending on the ChannelRedundancy register TxCRCEn bit setting, the CRC is calculated and appended to the data stream. The CRC is calculated using the ChannelRedundancy register settings. 11.3.1.3 Transmission of frames of more than 64 bytes To generate frames of more than 64 bytes of data, the microprocessor has to write data to the FIFO buffer while the Transmit command is active. The state machine checks the FIFO buffer status when it starts transmitting the last bit of the data stream (the check time is shown in Figure 20 with arrows). As long as the internal accept further data signal is logic 1 further data can be written to the FIFO buffer. The CLRC632 appends this data to the data stream transmitted using the RF interface. If the internal accept further data signal is logic 0 the transmission terminates. All data written to the FIFO buffer after accept further data signal was set to logic 0 is not transmitted, however, it remains in the FIFO buffer. 11.3.2 Receive command 16h The Receive command activates the receiver circuitry. All data received from the RF interface is written to the FIFO buffer. The Receive command can be started either by the microprocessor or automatically during execution of the Transceive command. Fig 20. Timing for transmitting byte oriented frames 001aak619 accept further data check FIFO empty TxData FIFO empty FIFOLength[6:0] 01h 00h TxLastBits[2:0] TxLastBits = 0 7 0 7 0 7 Table 144. Receive command 16h Command Value Action Arguments and data Returned data Receive 16h activates receiver circuitry - data streamCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 89 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Remark: This command may be used for test purposes only, since there is no timing relation to the Transmit command. 11.3.2.1 Using the Receive command After starting the Receive command the internal state machine decrements the RxWait register value on every bit-clock. The analog receiver circuitry is prepared and activated from 3 down to 1. When the counter reaches 0, the receiver starts monitoring the incoming signal using the RF interface. If the signal strength reaches a level above the value set in the RxThreshold register’s MinLevel[3:0] bits, the receiver starts decoding. The decoder stops when the signal cannot be detected on the receiver input pin RX. The decoder sets the RxIRq flag bit to indicate that the operation has finished. The receive sequence phases can be monitored using bits ModemStatus[2:0] in the PrimaryStatus register; see Section 11.2.4 on page 85. Remark: The minimum value for RxWait[7:0] is 3 because counter values from 3 to 0 are needed to initialize the analog receiver circuitry. 11.3.2.2 RF channel redundancy and framing In ISO/IEC 15693 mode, the decoder expects a SOF pattern at the beginning of each data stream. When a SOF is detected, it activates the serial-to-parallel converter and gathers the incoming data bits. If an EOF pattern (ISO/IEC 15693) is detected or the signal strength falls below the MinLevel value, the receiver and the decoder stop, the Idle command is entered and an appropriate response for the microprocessor is generated (interrupt request activated, status flags set). In I-CODE1 mode, the decoder does not expect a SOF pattern at the beginning of each data stream. It activates the serial-to-parallel converter on the first received bit of the data. Every full byte is then sent to the FIFO buffer. If ChannelRedundancy register bit RxCRCEn is set a CRC block is expected. The CRC block may be one byte or two bytes based on the ChannelRedundancy register’s CRC8 bit. Remark: If it is correct, the CRC block is not forwarded to the FIFO buffer. The CRC is realized by shifting the incoming data bytes through an internal buffer of one or two bytes (depending on the defined CRC). The CRC block remains in this internal buffer. Consequently, all data bytes in the FIFO buffer are delayed by one or two bytes. If the CRC fails, all bytes received are forwarded to the FIFO buffer (including the faulty CRC). 11.3.2.3 Collision detection If more than one label is within the RF field during the label selection phase, they will respond simultaneously. The CLRC632 supports the algorithm defined in ISO/IEC 15693 as well as the I-CODE1 anti-collision algorithm to resolve label serial number data collisions using the anti-collision procedure. The basis for this procedure is the ability to detect bit-collisions. Bit-collision detection is supported by the Manchester coding bit encoding scheme used. If in the first and second half-bit of a bit a subcarrier modulation is detected, instead of forwarding a 1-bit or a 0-bit, a bit-collision is flagged.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 90 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution To distinguish between a 1-bit or 0-bit from a bit-collision, the RxThreshold register’s CollLevel[3:0] value is used. If the amplitude of the half-bit with smaller amplitude is larger than defined by CollLevel[3:0], a bit-collision is flagged by setting the CollErr error flag. The receiver continues receiving the incoming data stream independently from the detected collision. In case of a bit-collision, the decoder forwards logic 1 at the collision position. Remark: As an exception, if bit ZeroAfterColl is set, all bits received after the first bit-collision are forced to zero, regardless of whether a bit-collision or an unequivocal state has been detected. This feature makes it easier for the software to carry out the anti-collision procedure as defined in ISO/IEC 15693. When the first bit-collision in a frame is detected, the bit position of the collision is stored in the CollPos register. The collision positions are shown in Table 145. If a collision is detected in the SOF, a frame error is reported and no data is sent to the FIFO buffer. In this case the receiver continues to monitor the incoming signal and generates the correct notifications to the microprocessor when the end of the faulty input stream is detected. This helps the microprocessor to determine the time when it is next allowed to send data to the label. 11.3.2.4 Communication errors Table 146 shows the events that set error flags. Table 145. Return values for bit-collision positions Collision in bit CollPos register value (Decimal) SOF 0 Least Significant Bit (LSB) of the Least Significant Byte (LSByte) 1 … … Most Significant Bit (MSB) of the LSByte 8 LSB of second byte 9 … … MSB of second byte 16 LSB of third byte 17 … … Table 146. Communication error table Cause Bit set Received data did not start with a SOF pattern FramingErr CRC block is not equal to the expected value CRCErr Received data is shorter than the CRC block CRCErr A collision is detected CollErrCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 91 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.3.3 Transceive command 1Eh The Transceive command first executes the Transmit command (see Section 11.2.1 on page 79) and then starts the Receive command (see Section 11.2.2 on page 82). All data to be transmitted is sent using the FIFO buffer and all received data is written to the FIFO buffer. The Transceive command can be started only by the microprocessor. Remark: To adjust the timing relationship between transmitting and receiving, use the RxWait register. This enables the time delay from the last bit transmitted until the receiver is activated to be defined. The BitPhase register is used to set-up the phase-shift between the transmitter and the receiver clock. 11.3.4 Label communication states The status of the transmitter and receiver state machine can be read from the PrimaryStatus register ModemState[2:0] bits. The assignment of ModemState[2:0] to the internal action is shown in Table 148. Table 147. Transceive command 1Eh Command Value Action Arguments and data Returned data Transceive 1Eh transmits data from FIFO buffer to the label and then activates the receiver data stream data stream Table 148. ModemState values ModemState [2:0] Name Description 000 Idle transmitter and/or receiver are not operating 001 TxSOF transmitting the start of frame pattern 010 TxData transmitting data from the FIFO buffer (or CRC check bits) 011 TxEOF transmitting the end of frame pattern 100 GoToRx1 intermediate state passed, when receiver starts GoToRx2 intermediate state passed, when receiver finishes 101 PrepareRx waiting until the RxWait register wait time has elapsed 110 AwaitingRx receiver activated; awaiting an input signal on pin RX 111 Receiving receiving dataCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 92 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.3.5 Label communication state diagram (1) I-CODE1 does not have a SOF and an EOF. Fig 21. Label communication state diagram 001aak622 end of receive frame and RxMultiple = 0 time slot period = 0 RxMultiple = 1 time slot period > 0 time slot trigger and data FIFO preparing to send the quit value EOF transmitted and command = Transceive FIFO not empty and command = Transmit or Transceive command = Receive COMMAND = TRANSMIT, RECEIVE OR TRANSCEIVE SET COMMAND REGISTER = IDLE (000) Awaiting Rx (110) RECEIVING (111) GoToRx2 (100) Prepare Rx (101) GoToRx1 (100) TxEOF (011) TxData (010) TxSOF (001) IDLE (000) IDLE (000) SOF transmitted next bit clock data transmitted RxWaitC[7:0] = 0 EOF transmitted and command = Transmit signal strength > MinLevel[3:0] frame received RxMultiple = 0 time slot period > 0 time slot trigger and FIFO dataCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 93 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.4 EEPROM commands 11.4.1 WriteE2 command 01h The WriteE2 command interprets the first two bytes in the FIFO buffer as the EEPROM start byte address. Any further bytes are interpreted as data bytes and are programmed into the EEPROM, starting from the given EEPROM start byte address. This command does not return any data. The WriteE2 command can only be started by the microprocessor. It will not stop automatically but has to be stopped explicitly by the microprocessor by issuing the Idle command. 11.4.1.1 Programming process One byte up to 16-byte can be programmed into the EEPROM during a single programming cycle. The time needed is approximately 5.8 ms. The state machine copies all the prepared data bytes to the FIFO buffer and then to the EEPROM input buffer. The internal EEPROM input buffer is 16 bytes long which is equal to the block size of the EEPROM. A programming cycle is started if the last position of the EEPROM input buffer is written or if the last byte of the FIFO buffer has been read. The E2Ready flag remains logic 0 when there are unprocessed bytes in the FIFO buffer or the EEPROM programming cycle is still in progress. When all the data from the FIFO buffer are programmed into the EEPROM, the E2Ready flag is set to logic 1. Together with the rising edge of E2Ready the TxIRq interrupt request flag shows logic 1. This can be used to generate an interrupt when programming of all data is finished. Remark: During the E2PROM programming indicated by E2Ready = logic 0, the WriteE2 command cannot be stopped using any other command. Once E2Ready = logic 1, the WriteE2 command can be stopped by the microprocessor by sending the Idle command. Table 149. WriteE2 command 01h Command Value Action FIFO Arguments and data Returned data WriteE2 01h get data from FIFO buffer and write it to the EEPROM start address LSB - start address MSB - data byte stream -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 94 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.4.1.2 Timing diagram Figure 22 shows programming five bytes into the EEPROM. Assuming that the CLRC632 finds and reads byte 0 before the microprocessor is able to write byte 1 (tprog,del = 300 ns). This causes the CLRC632 to start the programming cycle (tprog), which takes approximately 5.8 ms to complete. In the meantime, the microprocessor stores byte 1 to byte 4 in the FIFO buffer. If the EEPROM start byte address is 16Ch then byte 0 is stored at that address. The CLRC632 copies the subsequent data bytes into the EEPROM input buffer. Whilst copying byte 3, it detects that this data byte has to be programmed at the EEPROM byte address 16Fh. As this is the end of the memory block, the CLRC632 automatically starts a programming cycle. Next, byte 4 is programmed at the EEPROM byte address 170h. As this is the last data byte, the E2Ready and TxIRq flags are set indicating the end of the EEPROM programming activity. Although all data has been programmed into the E2PROM, the CLRC632 stays in the WriteE2 command. Writing more data to the FIFO buffer would lead to another EEPROM programming cycle continuing from EEPROM byte address 171h. The command is stopped using the Idle command. 11.4.1.3 WriteE2 command error flags Programming is restricted for EEPROM block 0 (EEPROM byte address 00h to 0Fh). If you program these addresses, the AccessErr flag is set and a programming cycle is not started. Addresses above 1FFh are taken modulo 200h; see Section 9.2 on page 12 for the EEPROM memory organization. Fig 22. EEPROM programming timing diagram 001aak623 NWR data WriteE2 command active EEPROM programming E2Ready TxIRq write E2 addr LSB addr MSB byte 0 byte 1 tprog,del byte 2 byte 3 byte 4 programming byte 0 tprog programming byte 1, byte 2 and byte 3 tprog programming byte 4 tprog Idle commandCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 95 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.4.2 ReadE2 command 03h The ReadE2 command interprets the first two bytes stored in the FIFO buffer as the EEPROM starting byte address. The next byte specifies the number of data bytes returned. When all three argument bytes are available in the FIFO buffer, the specified number of data bytes is copied from the EEPROM into the FIFO buffer, starting from the given EEPROM starting byte address. The ReadE2 command can only be triggered by the microprocessor and it automatically stops when all data has been copied. 11.4.2.1 ReadE2 command error flags Reading is restricted to EEPROM blocks 8h to 1Fh (key memory area). Reading from these addresses sets the flag AccessErr = logic 1. Addresses above 1FFh are taken as modulo 200h; see Section 9.2 on page 12 for the EEPROM memory organization. 11.5 Diverse commands 11.5.1 LoadConfig command 07h The LoadConfig command interprets the first two bytes found in the FIFO buffer as the EEPROM starting byte address. When the two argument bytes are available in the FIFO buffer, 32 bytes from the EEPROM are copied into the Control and other relevant registers, starting at the EEPROM starting byte address. The LoadConfig command can only be started by the microprocessor and it automatically stops when all relevant registers have been copied. 11.5.1.1 Register assignment The 32 bytes of EEPROM content are written to the CLRC632 registers 10h to register 2Fh; see Section 9.2 on page 12 for the EEPROM memory organization. Remark: The procedure for the register assignment is the same as it is for the startup initialization (see Section 9.7.3 on page 30). The difference is, the EEPROM starting byte address for the startup initialization is fixed to 10h (block 1, byte 0). However, it can be chosen with the LoadConfig command. Table 150. ReadE2 command 03h Command Value Action Arguments Returned data ReadE2 03h reads EEPROM data and stores it in the FIFO buffer start address LSB data bytes start address MSB number of data bytes Table 151. LoadConfig command 07h Command Value Action Arguments and data Returned data LoadConfig 07h reads data from EEPROM and initializes the registers start address LSB - start address MSB -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 96 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.5.1.2 Relevant LoadConfig command error flags Valid EEPROM starting byte addresses are between 10h and 60h. Copying from block 8h to 1Fh (keys) is restricted. Reading from these addresses sets the flag AccessErr = logic 1. Addresses above 1FFh are taken as modulo 200h; see Section 9.2 on page 12 for the EEPROM memory organization. 11.5.2 CalcCRC command 12h The CalcCRC command takes all the data from the FIFO buffer as the input bytes for the CRC coprocessor. All data stored in the FIFO buffer before the command is started is processed. This command does not return any data to the FIFO buffer but the content of the CRC can be read using the CRCResultLSB and CRCResultMSB registers. The CalcCRC command can only be started by the microprocessor and it does not automatically stop. It must be stopped by the microprocessor sending the Idle command. If the FIFO buffer is empty, the CalcCRC command waits for further input before proceeding. 11.5.2.1 CRC coprocessor settings Table 153 shows the parameters that can be configured for the CRC coprocessor. The CRC polynomial for the 8-bit CRC is fixed to x8 + x4 + x3 + x2 + 1. The CRC polynomial for the 16-bit CRC is fixed to x16 + x12 + x5 + 1. 11.5.2.2 CRC coprocessor status flags The CRCReady status flag indicates that the CRC coprocessor has finished processing all the data bytes in the FIFO buffer. When the CRCReady flag is set to logic 1, an interrupt is requested which sets the TxIRq flag. This supports interrupt driven use of the CRC coprocessor. When CRCReady and TxIRq flags are set to logic 1 the content of the CRCResultLSB and CRCResultMSB registers and the CRCErr flag are valid. The CRCResultLSB and CRCResultMSB registers hold the content of the CRC, the CRCErr flag indicates CRC validity for the processed data. Table 152. CalcCRC command 12h Command Value Action Arguments and data Returned data CalcCRC 12h activates the CRC coprocessor data byte stream - Table 153. CRC coprocessor parameters Parameter Value Bit Register CRC register length 8-bit or 16-bit CRC CRC8 ChannelRedundancy CRC algorithm ISO/IEC 14443 A or ISO/IEC 3309 CRC3309 ChannelRedundancy CRC preset value any CRCPresetLSB CRCPresetLSB CRCPresetMSB CRCPresetMSBCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 97 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.6 Error handling during command execution If an error is detected during command execution, the PrimaryStatus register Err flag is set. The microprocessor can evaluate the status flags in the ErrorFlag register to get information about the cause of the error. 11.7 MIFARE security commands 11.7.1 LoadKeyE2 command 0Bh The LoadKeyE2 command interprets the first two bytes found in the FIFO buffer as the EEPROM starting byte address. The EEPROM bytes starting from the given starting byte address are interpreted as the key when stored in the correct key format as described in Section 9.2.3.1 “Key format” on page 18. When both argument bytes are available in the FIFO buffer, the command executes. The LoadKeyE2 command can only be started by the microprocessor and it automatically stops after copying the key from the EEPROM to the key buffer. 11.7.1.1 Relevant LoadKeyE2 command error flags If the key format is incorrect (see Section 9.2.3.1 “Key format” on page 18) an undefined value is copied into the key buffer and the KeyErr flag is set. 11.7.2 LoadKey command 19h Table 154. ErrorFlag register error flags overview Error flag Related commands KeyErr LoadKeyE2, LoadKey AccessErr WriteE2, ReadE2, LoadConfig FIFOOvlf no specific commands CRCErr Receive, Transceive, CalcCRC FramingErr Receive, Transceive ParityErr Receive, Transceive CollErr Receive, Transceive Table 155. LoadKeyE2 command 0Bh Command Value Action Arguments and data Returned data LoadKeyE2 0Bh reads a key from the EEPROM and puts it into the internal key buffer start address LSB - start address MSB - Table 156. LoadKey command 19h Command Value Action Arguments and data Returned data LoadKey 19h reads a key from the FIFO buffer and puts it into the key buffer byte 0 (LSB) - byte 1 - … - byte 10 - byte 11 (MSB) -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 98 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution The LoadKey command interprets the first twelve bytes it finds in the FIFO buffer as the key when stored in the correct key format as described in Section 9.2.3.1 “Key format” on page 18. When the twelve argument bytes are available in the FIFO buffer they are checked and, if valid, are copied into the key buffer. The LoadKey command can only be started by the microprocessor and it automatically stops after copying the key from the FIFO buffer to the key buffer. 11.7.2.1 Relevant LoadKey command error flags All bytes requested are copied from the FIFO buffer to the key buffer. If the key format is not correct (see Section 9.2.3.1 “Key format” on page 18) an undefined value is copied into the key buffer and the KeyErr flag is set. 11.7.3 Authent1 command 0Ch The Authent1 command is a special Transceive command; it sends six argument bytes to the card. The card’s response is not sent to the microprocessor, it is used instead to authenticate the card to the CLRC632 and vice versa. The Authent1 command can be triggered only by the microprocessor. The sequence of states for this command are the same as those for the Transceive command; see Section 11.2.3 on page 85. 11.7.4 Authent2 command 14h The Authent2 command is a special Transceive command. It does not need any argument byte, however all the data needed to be sent to the card is assembled by the CLRC632. The card response is not sent to the microprocessor but is used to authenticate the card to the CLRC632 and vice versa. The Authent2 command can only be started by the microprocessor. The sequence of states for this command are the same as those for the Transceive command; see Section 11.2.3 on page 85. Table 157. Authent1 command 0Ch Command Value Action Arguments and data Returned data Authent1 0Ch performs the first part of the Crypto1 card authentication card Authent1 command - card block address - card serial number LSB - card serial number byte1 - card serial number byte2 - card serial number MSB - Table 158. Authent2 command 14h Command Value Action Arguments and data Returned data Authent2 14h performs the second part of the card authentication using the Crypto1 algorithm - -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 99 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 11.7.4.1 Authent2 command effects If the Authent2 command is successful, the authenticity of card and the CLRC632 are proved. This automatically sets the Crypto1On control bit. When bit Crypto1On = logic 1, all further card communication is encrypted using the Crypto1 security algorithm. If the Authent2 command fails, bit Crypto1On is cleared (Crypto1On = logic 0). Remark: The Crypto1On flag can only be set by a successfully executed Authent2 command and not by the microprocessor. The microprocessor can clear bit Crypto1On to continue with unencrypted (plain) card communication. Remark: The Authent2 command must be executed immediately after a successful Authent1 command; see Section 11.7.3 “Authent1 command 0Ch”. In addition, the keys stored in the key buffer and those on the card must match. 12. Limiting values 13. Characteristics 13.1 Operating condition range Table 159. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Tamb ambient temperature 40 +150 C Tstg storage temperature 40 +150 C VDDD digital supply voltage 0.5 +6 V VDDA analog supply voltage 0.5 +6 V VDD(TVDD) TVDD supply voltage 0.5 +6 V Vi input voltage (absolute value) on any digital pin to DVSS 0.5 VDDD + 0.5 V on pin RX to AVSS 0.5 VDDA + 0.5 V Table 160. Operating condition range Symbol Parameter Conditions Min Typ Max Unit Tamb ambient temperature - 25 +25 +85 C VDDD digital supply voltage DVSS = AVSS = TVSS = 0 V 3.0 3.3 3.6 V 4.5 5.0 5.5 V VDDA analog supply voltage DVSS = AVSS = TVSS = 0 V 4.5 5.0 5.5 V VDD(TVDD) TVDD supply voltage DVSS = AVSS = TVSS = 0 V 3.0 5.0 5.5 V VESD electrostatic discharge voltage Human Body Model (HBM); 1.5 k, 100 pF - - 1000 V Machine Model (MM); 0.75 H, 200 pF - - 100 VCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 100 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 13.2 Current consumption 13.3 Pin characteristics 13.3.1 Input pin characteristics Pins D0 to D7, A0, and A1 have TTL input characteristics and behave as defined in Table 162. The digital input pins NCS, NWR, NRD, ALE, A2, and MFIN have Schmitt trigger characteristics, and behave as defined in Table 163. Table 161. Current consumption Symbol Parameter Conditions Min Typ Max Unit IDDD digital supply current Idle command - 8 11 mA Standby mode - 3 5 mA Soft power-down mode - 800 1000 A Hard power-down mode - 1 10 A IDDA analog supply current Idle command; receiver on - 25 40 mA Idle command; receiver off - 12 15 mA Standby mode - 10 13 mA Soft power-down mode - 1 10 A Hard power-down mode - 1 10 A IDD(TVDD) TVDD supply current continuous wave - - 150 mA pins TX1 and TX2 unconnected; TX1RFEn and TX2RFEn = logic 1 - 5.5 7 mA pins TX1 and TX2 unconnected; TX1RFEn and TX2RFEn = logic 0 - 65 130 A Table 162. Standard input pin characteristics Symbol Parameter Conditions Min Typ Max Unit ILI input leakage current 1.0 - +1.0 A Vth threshold voltage CMOS: VDDD < 3.6 V 0.35VDDD - 0.65VDDD V TTL: 4.5 < VDDD 0.8 - 2.0 V Table 163. Schmitt trigger input pin characteristics Symbol Parameter Conditions Min Typ Max Unit ILI input leakage current 1.0 - +1.0 A Vth threshold voltage positive-going threshold; TTL = 4.5 < VDDD 1.4 - 2.0 V CMOS = VDDD < 3.6 V 0.65VDDD - 0.75VDDD V negative-going threshold; TTL = 4.5 < VDDD 0.8 - 1.3 V CMOS = VDDD < 3.6 V 0.25VDDD - 0.4VDDD VCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 101 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Pin RSTPD has Schmitt trigger CMOS characteristics. In addition, it is internally filtered by a RC low-pass filter which causes a propagation delay on the reset signal. The analog input pin RX has the input capacitance and input voltage range shown in Table 165. 13.3.2 Digital output pin characteristics Pins D0 to D7, MFOUT and IRQ have CMOS output characteristics and behave as defined in Table 166. Remark: Pin IRQ can be configured as open collector which causes the VOH values to be no longer applicable. 13.3.3 Antenna driver output pin characteristics The source conductance of the antenna driver pins TX1 and TX2 for driving the HIGH-level can be configured using the CwConductance register’s GsCfgCW[5:0] bits, while their source conductance for driving the LOW-level is constant. The antenna driver default configuration output characteristics are specified in Table 167. Table 164. RSTPD input pin characteristics Symbol Parameter Conditions Min Typ Max Unit ILI input leakage current 1.0 - +1.0 A Vth threshold voltage positive-going threshold; CMOS = VDDD < 3.6 V 0.65VDDD - 0.75VDDD V negative-going threshold; CMOS = VDDD < 3.6 V 0.25VDDD - 0.4VDDD V tPD propagation delay - - 20 s Table 165. RX input capacitance and input voltage range Symbol Parameter Conditions Min Typ Max Unit Ci input capacitance - - 15 pF Vi(dyn) dynamic input voltage VDDA = 5 V; Tamb = 25 C 1.1 - 4.4 V Table 166. Digital output pin characteristics Symbol Parameter Conditions Min Typ Max Unit VOH HIGH-level output voltage VDDD = 5 V; IOH = 1 mA 2.4 4.9 - V VDDD = 5 V; IOH = 10 mA 2.4 4.2 - V VOL LOW-level output voltage VDDD = 5 V; IOL = 1 mA - 25 400 mV VDDD = 5 V; IOL = 10 mA - 250 400 mV IO output current source or sink; VDDD = 5 V - - 10 mACLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 102 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 13.4 AC electrical characteristics 13.4.1 Separate read/write strobe bus timing Table 167. Antenna driver output pin characteristics Symbol Parameter Conditions Min Typ Max Unit VOH HIGH-level output voltage VDD(TVDD) = 5.0 V; IOL = 20 mA - 4.97 - V VDD(TVDD) = 5.0 V; IOL = 100 mA - 4.85 - V VOL LOW-level output voltage VDD(TVDD) = 5.0 V; IOL = 20 mA - 30 - mV VDD(TVDD) = 5.0 V; IOL = 100 mA - 150 - mV IO output current transmitter; continuous wave; peak-to-peak - - 200 mA Table 168. Timing specification for separate read/write strobe Symbol Parameter Conditions Min Typ Max Unit tLHLL ALE HIGH time 20 - - ns tAVLL address valid to ALE LOW time 15 - - ns tLLAX address hold after ALE LOW time 8 - - ns tLLRWL ALE LOW to read/write LOW time ALE LOW to NRD or NWR LOW 15 - - ns tSLRWL chip select LOW to read/write LOW time NCS LOW to NRD or NWR LOW 0 - - ns tRWHSH read/write HIGH to chip select HIGH time NRD or NWR HIGH to NCS HIGH 0 - - ns tRLDV read LOW to data input valid time NRD LOW to data valid - - 65 ns tRHDZ read HIGH to data input high impedance time NRD HIGH to data high-impedance - - 20 ns tWLQV write LOW to data output valid time NWR LOW to data valid - - 35 ns tWHDX data output hold after write HIGH time data hold time after NWR HIGH 8 - - ns tRWLRWH read/write LOW time NRD or NWR 65 - - ns tAVRWL address valid to read/write LOW time NRD or NWR LOW (set-up time) 30 - - ns tWHAX address hold after write HIGH time NWR HIGH (hold time) 8 - - ns tRWHRWL read/write HIGH time 150 - - nsCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 103 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Remark: The signal ALE is not relevant for separate address/data bus and the multiplexed addresses on the data bus do not care. The multiplexed address and data bus address lines (A0 to A2) must be connected as described in Section 9.1.3 on page 8. 13.4.2 Common read/write strobe bus timing Fig 23. Separate read/write strobe timing diagram 001aaj638 tSLRWL tRWHSH tRWHRWL tWHDX tRHDZ tWLQV tRLDV tAVRWL tWHAX tAVLL tLLAX tRWLRWH tLLRWL tRWHRWL tLHLL A0 to A2 A0 to A2 D0 to D7 D0 to D7 NWR NRD NCS ALE A0 to A2 Multiplexed address bus Separated address bus Table 169. Common read/write strobe timing specification Symbol Parameter Conditions Min Typ Max Unit tLHLL ALE HIGH time 20 - - ns tAVLL address valid to ALE LOW time 15 - - ns tLLAX address hold after ALE LOW time 8 - - ns tLLDSL ALE LOW to data strobe LOW time NWR or NRD LOW 15 - - ns tSLDSL chip select LOW to data strobe LOW time NCS LOW to NDS LOW 0 - - ns tDSHSH data strobe HIGH to chip select HIGH time 0 - - ns tDSLDV data strobe LOW to data input valid time - - 65 ns tDSHDZ data strobe HIGH to data input high impedance time - - 20 ns tDSLQV data strobe LOW to data output valid time NDS/NCS LOW - - 35 ns tDSHQX data output hold after data strobe HIGH time NDS HIGH (write cycle hold time) 8 - - ns tDSHRWX RW hold after data strobe HIGH time after NDS HIGH 8 - - ns tDSLDSH data strobe LOW time NDS/NCS 65 - - nsCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 104 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 13.4.3 EPP bus timing tAVDSL address valid to data strobe LOW time 30 - - ns tRHAX address hold after read HIGH time 8 - - ns tDSHDSL data strobe HIGH time period between write sequences 150 - - ns tWLDSL write LOW to data strobe LOW time R/NW valid to NDS LOW 8 - - ns Fig 24. Common read/write strobe timing diagram Table 169. Common read/write strobe timing specification …continued Symbol Parameter Conditions Min Typ Max Unit 001aaj639 tSLDSL tDSHSH tDSHDSL tDSHQX tDSHDZ tDSLDV tDSLQV tAVDSL tRHAX tAVLL tLLAX tDSLDSH tLLDSL tDSHDSL tLHLL tWLDSL tDSHRWX A0 to A2 A0 to A2 D0 to D7 D0 to D7 NRD R/NW NCS/NDS ALE A0 to A2 Multiplexed address bus Separated address bus Table 170. Common read/write strobe timing specification for EPP Symbol Parameter Conditions Min Typ Max Unit tASLASH address strobe LOW time nAStrb 20 - - ns tAVASH address valid to address strobe HIGH time multiplexed address bus set-up time 15 - - ns tASHAV address valid after address strobe HIGH time multiplexed address bus hold time 8 - - ns tSLDSL chip select LOW to data strobe LOW time NCS LOW to nDStrb LOW 0 - - ns tDSHSH data strobe HIGH to chip select HIGH time nDStrb HIGH to NCS HIGH 0 - - ns tDSLDV data strobe LOW to data input valid time read cycle - - 65 nsCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 105 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Remark: Figure 25 does not distinguish between the address write cycle and a data write cycle. The timings for the address write and data write cycle are different. In EPP mode, the address lines (A0 to A2) must be connected as described in Section 9.1.3 on page 8. tDSHDZ data strobe HIGH to data input high impedance time read cycle - - 20 ns tDSLQV data strobe LOW to data output valid time nDStrb LOW - - 35 ns tDSHQX data output hold after data strobe HIGH time NCS HIGH 8 - - ns tDSHWX write hold after data strobe HIGH time nWrite 8 - - ns tDSLDSH data strobe LOW time nDStrb 65 - - ns tWLDSL write LOW to data strobe LOW time nWrite valid to nDStrb LOW 8 - - ns tDSL-WAITH data strobe LOW to WAIT HIGH time nDStrb LOW to nWrite HIGH - - 75 ns tDSH-WAITL data strobe HIGH to WAIT LOW time nDStrb HIGH to nWrite LOW - - 75 ns Fig 25. Timing diagram for common read/write strobe; EPP Table 170. Common read/write strobe timing specification for EPP …continued Symbol Parameter Conditions Min Typ Max Unit 001aaj640 nWait tDSL-WAITH tDSLDV tDSLQV tWLDSL tSLDSL tDSHSH tDSLDSH D0 to D7 A0 to A7 tDSHQX tDSHDZ tDSH-WAITL tDSHWX D0 to D7 nDStrb nAStrb nWrite NCSCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 106 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 13.4.4 SPI timing Remark: To send more bytes in one data stream the NSS signal must be LOW during the send process. To send more than one data stream the NSS signal must be HIGH between each data stream. 13.4.5 Clock frequency The clock input is pin OSCIN. The clock applied to the CLRC632 acts as a time constant for the synchronous system’s encoder and decoder. The stability of the clock frequency is an important factor for ensuring proper performance. To obtain highest performance, clock jitter must be as small as possible. This is best achieved using the internal oscillator buffer and the recommended circuitry; see Section 9.8 on page 30. Table 171. SPI timing specification Symbol Parameter Conditions Min Typ Max Unit tSCKL SCK LOW time 100 - - ns tSCKH SCK HIGH time 100 - - ns tDSHQX data output hold after data strobe HIGH time 20 - - ns tDQXCH data input/output changing to clock HIGH time 20 - - ns th(SCKL-Q) SCK LOW to data output hold time - - 15 ns t(SCKL-NSSH) SCK LOW to NSS HIGH time 20 - - ns Fig 26. Timing diagram for SPI 001aaj64 tNSSH tSCKL tSCKH tSCKL th(SCKL-Q) tsu(D-SCKH) th(SCKH-D) th(SCKL-Q) t(SCKL-NSSH) SCK OSI ISO MSB MSB LSB LSB NSS Table 172. Clock frequency Symbol Parameter Conditions Min Typ Max Unit fclk clock frequency checked by the clock filter - 13.56 - MHz clk clock duty cycle 40 50 60 % tjit jitter time of clock edges - - 10 psCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 107 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 14. EEPROM characteristics The EEPROM size is 32 16 8 = 4096 bit. 15. Application information 15.1 Typical application 15.1.1 Circuit diagram Figure 27 shows a typical application where the antenna is directly matched to the CLRC632: Table 173. EEPROM characteristics Symbol Parameter Conditions Min Typ Max Unit Nendu(W_ER) write or erase endurance erase/write cycles 100.000 - - Hz tret retention time Tamb 55 C 10 - - year ter erase time - - 2.9 ms ta(W) write access time - - 2.9 ms Fig 27. Application example circuit diagram: directly matched antenna 001aak625 DVDD RSTPD AVDD TVDD DVDD Reset AVDD TVDD DVSS control lines data bus IRQ OSCIN OSCOUT 13.56 MHz AVSS VMID RX TX2 TVSS TX1 IRQ 15 pF 15 pF C0 C0 C2a C2b C3 R2 R1 L0 L0 C1 C1 C4 100 nF MICROPROCESSOR BUS MICROPROCESSOR DEVICECLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 108 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 15.1.2 Circuit description The matching circuit consists of an EMC low-pass filter (L0 and C0), matching circuitry (C1 and C2), a receiver circuit (R1, R2, C3 and C4) and the antenna itself. Refer to the following application notes for more detailed information about designing and tuning an antenna. • MICORE reader IC family; Directly Matched Antenna Design Ref. 1 • MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas Ref. 2. 15.1.2.1 EMC low-pass filter The MIFARE system operates at a frequency of 13.56 MHz. This frequency is generated by a quartz oscillator to clock the CLRC632. It is also the basis for driving the antenna using the 13.56 MHz energy carrier. This not only causes power emissions at 13.56 MHz, it also emits power at higher harmonics. International EMC regulations define the amplitude of the emitted power over a broad frequency range. To meet these regulations, appropriate filtering of the output signal is required. A multilayer board is recommended to implement a low-pass filter as shown in Figure 27. The low-pass filter consists of the components L0 and C0. The recommended values are given in Application notes MICORE reader IC family; Directly Matched Antenna Design Ref. 1 and MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas Ref. 2. Remark: To achieve best performance, all components must be at least equal in quality to those recommended. Remark: The layout has a major influence on the overall performance of the filter. 15.1.2.2 Antenna matching Due to the impedance transformation of the low-pass filter, the antenna coil has to be matched to a given impedance. The matching elements C1 and C2 can be estimated and have to be fine tuned depending on the design of the antenna coil. The correct impedance matching is important to ensure optimum performance. The overall quality factor has to be considered to guarantee a proper ISO/IEC 14443 A and ISO/IEC 14443 B communication schemes. Environmental influences have to considered and common EMC design rules. Refer to Application notes MICORE reader IC family; Directly Matched Antenna Design Ref. 1 and MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas Ref. 2 for details. Remark: Do not exceed the current limits (IDD(TVDD)), otherwise the chip might be destroyed. Remark: The overall 13.56 MHz RFID proximity antenna design in combination with the CLRC632 IC does not require any specialist RF knowledge. However, all relevant parameters have to be considered to guarantee optimum performance and international EMC compliance. 15.1.2.3 Receiver circuit The internal receiver of the CLRC632 makes use of both subcarrier load modulation side-bands. No external filtering is required.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 109 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution It is recommended to use the internally generated VMID potential as the input potential for pin RX. This VMID DC voltage level has to be coupled to pin RX using resistor (R2). To provide a stable DC reference voltage, a capacitor (C4) must be connected between VMID and ground. The AC voltage divider of R1 + C3 and R2 has to be designed taking in to account the AC voltage limits on pin RX. Depending on the antenna coil design and the impedance, matching the voltage at the antenna coil will differ. Therefore the recommended way to design the receiver circuit is to use the given values for R1, R2, and C3; refer to Application note; MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas Ref. 2. The voltage on pin RX can be altered by varying R1 within the given limits. Remark: R2 is AC connected to ground using C4. 15.1.2.4 Antenna coil The precise calculation of the antenna coil’s inductance is not practicable but the inductance can be estimated using Equation 10. We recommend designing an antenna that is either circular or rectangular. (10) • l1 = length of one turn of the conductor loop • D1 = diameter of the wire or width of the PCB conductor, respectively • K = antenna shape factor (K = 1.07 for circular antennas and K = 1.47 for square antennas) • N1 = number of turns • ln = natural logarithm function The values of the antenna inductance, resistance, and capacitance at 13.56 MHz depend on various parameters such as: • antenna construction (type of PCB) • thickness of conductor • distance between the windings • shielding layer • metal or ferrite in the near environment Therefore a measurement of these parameters under real life conditions or at least a rough measurement and a tuning procedure is highly recommended to guarantee a reasonable performance. Refer to Application notes MICORE reader IC family; Directly Matched Antenna Design Ref. 1 and MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas Ref. 2 for details. L1 nH = 2 I1 cm I1 D1 ln K ------ – N1 1.8 CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 110 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 15.2 Test signals The CLRC632 allows different kinds of signal measurements. These measurements can be used to check the internally generated and received signals using the serial signal switch as described in Section 9.11 on page 37. In addition, the CLRC632 enables users to select between: • internal analog signals for measurement on pin AUX • internal digital signals for observation on pin MFOUT (based on register selections) These measurements can be helpful during the design-in phase to optimize the receiver’s behavior, or for test purposes. 15.2.1 Measurements using the serial signal switch Using the serial signal switch on pin MFOUT, data is observed that is sent to the card or received from the card. Table 174 gives an overview of the different signals available. Remark: The routing of the Manchester or the Manchester with subcarrier signal to pin MFOUT is only possible at 106 kBd based on ISO/IEC 14443 A. 15.2.1.1 TX control Figure 28 shows as an example of an ISO/IEC 14443 A communication. The signal is measured on pin MFOUT using the serial signal switch to control the data sent to the card. Setting the flag MFOUTSelect[2:0] = 3 sends the data to the card coded as NRZ. Setting MFOUTSelect[2:0] = 2 shows the data as a Miller coded signal. The RFOut signal is measured directly on the antenna and gives the RF signal pulse shape. Refer to Application note Directly matched Antenna - Excel calculation (Ref. 3) for detail information on the RF signal pulse. Table 174. Signal routed to pin MFOUT SignalToMFOUT MFOUTSelect Signal routed to pin MFOUT 0 0 LOW 0 1 HIGH 0 2 envelope 0 3 transmit NRZ 0 4 Manchester with subcarrier 0 5 Manchester 0 6 reserved 0 7 reserved 1 X digital test signalCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 111 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 15.2.1.2 RX control Figure 29 shows an example of ISO/IEC 14443 A communication which represents the beginning of a card’s answer to a request signal. The RF signal shows the RF voltage measured directly on the antenna so that the card’s load modulation is visible. Setting MFOUTSelect[2:0] = 4 shows the Manchester decoded signal with subcarrier. Setting MFOUTSelect[2:0] = 5 shows the Manchester decoded signal. (1) MFOUTSelect[2:0] = 3; serial data stream; 2 V per division. (2) MFOUTSelect[2:0] = 2; serial data stream; 2 V per division. (3) RFOut; 1 V per division. Fig 28. TX control signals 001aak626 (1) (2) (3) 10 μs per divisionCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 112 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 15.2.2 Analog test signals The analog test signals can be routed to pin AUX by selecting them using the TestAnaSelect register TestAnaOutSel[4:0] bits. (1) RFOut; 1 V per division. (2) MFOUTSelect[2:0] = 4; Manchester with subcarrier; 2 V per division. (3) MFOUTSelect[2:0] = 5; Manchester; 2 V per division. Fig 29. RX control signals 001aak627 10 μs per division (1) (2) (3) Table 175. Analog test signal selection Value Signal Name Description 0 VMID voltage at internal node VMID 1 Vbandgap internal reference voltage generated by the bandgap 2 VRxFollI output signal from the demodulator using the I-clock 3 VRxFollQ output signal from the demodulator using the Q-clock 4 VRxAmpI I-channel subcarrier signal amplified and filtered 5 VRxAmpQ Q-channel subcarrier signal amplified and filtered 6 VCorrNI output signal of N-channel correlator fed by the I-channel subcarrier signal 7 VCorrNQ output signal of N-channel correlator fed by the Q-channel subcarrier signal 8 VCorrDI output signal of D-channel correlator fed by the I-channel subcarrier signal 9 VCorrDQ output signal of D-channel correlator fed by the Q-channel subcarrier signal A VEvalL evaluation signal from the left half-bitCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 113 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 15.2.3 Digital test signals Digital test signals can be routed to pin MFOUT by setting bit SignalToMFOUT = logic 1. A digital test signal is selected using the TestDigiSelect register TestDigiSignalSel[6:0] bits. The signals selected by the TestDigiSignalSel[6:0] bits are shown in Table 176. If test signals are not used, the TestDigiSelect register address value must be 00h. Remark: All other values for TestDigiSignalSel[6:0] are for production test purposes only. 15.2.4 Examples of ISO/IEC 14443 A analog and digital test signals Figure 30 shows a MIFARE card’s answer to a request command using the Q-clock receiving path. RX reference is given to show the Manchester modulated signal on pin RX. The signal is demodulated and amplified in the receiver circuitry. Signal VRXAmpQ is the amplified side-band signal using the Q-clock for demodulation. The signals VCorrDQ and VCorrNQ were generated in the correlation circuitry. They are processed further in the evaluation and digitizer circuitry. B VEvalR evaluation signal from the right half-bit C VTemp temperature voltage derived from band gap D reserved reserved for future use E reserved reserved for future use F reserved reserved for future use Table 175. Analog test signal selection …continued Value Signal Name Description Table 176. Digital test signal selection TestDigiSignalSel [6:0] Signal name Description F4h s_data data received from the card E4h s_valid when logic 1 is returned the s_data and s_coll signals are valid D4h s_coll when logic 1 is returned a collision has been detected in the current bit C4h s_clock internal serial clock: during transmission, this is the encoder clock during reception this is the receiver clock B5h rd_sync internal synchronized read signal which is derived from the parallel microprocessor interface A5h wr_sync internal synchronized write signal which is derived from the parallel microprocessor interface 96h int_clock internal 13.56 MHz clock 83h BPSK_out BPSK output signal E2h BPSK_sig BPSK signal’s amplitude detected 00h no test signal output as defined by the MFOUTSelect register MFOUTSelect[2:0] bits routed to pin MFOUTCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 114 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Signals VEvalR and VEvalL show the evaluation of the signal’s right and left half-bit. Finally, the digital test signal s_data shows the received data. This is then sent to the internal digital circuit and s_valid which indicates the received data stream is valid. 15.2.5 Examples of I-CODE1 analog and digital test signals Figure 31 shows the answer of an I-CODE1 label IC to an unselected read command using the Q-clock receiving path. RX reference is given to show the Manchester modulated signal on pin RX. The signal is demodulated and amplified in the receiver circuitry. Signal VRXAmpQ is the amplified side-band signal using the Q-clock for demodulation. The signals VCorrDQ and VCorrNQ generated in the correlation circuitry are processed further in the evaluation and digitizer circuitry. Signals VEvalR and VEvalL are the evaluation signal of the right and left half-bit. Finally, the digital test-signal s_data shows the received data. This is then routed to the internal digital circuit and s_valid indicates that the received data stream is valid. Fig 30. ISO/IEC 14443 A receiving path Q-clock 001aak628 RX reference VRxAmpQ VCorrDQ VCorrNQ VEvalR VEvalL s_data s_valid 50 μs per divisionCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 115 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Fig 31. I-CODE1 receiving path Q-clock VRxAmpQ VCorrDQ VCorrNQ VEvalR VEvalL s_data s_valid receiving path Q-Clock 50 μs per division 001aak629 500 μs per divisionCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 116 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 16. Package outline Fig 32. Package outline SOT287-1 UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp Q Z ywv θ OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches 2.65 0.1 0.25 0.01 1.4 0.055 0.3 0.1 2.45 2.25 0.49 0.36 0.27 0.18 20.7 20.3 7.6 7.4 1.27 10.65 10.00 1.2 1.0 0.95 0.55 8 0 o o 0.25 0.1 0.004 0.25 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 SOT287-1 MO-119 (1) 0.012 0.004 0.096 0.089 0.02 0.01 0.05 0.047 0.039 0.419 0.394 0.30 0.29 0.81 0.80 0.011 0.007 0.037 0.022 0.01 0.01 0.043 0.016 w M bp D HE Z e c v M A X A y 32 17 1 16 θ A A1 A2 Lp Q detail X L (A ) 3 E pin 1 index 0 5 10 mm scale SO32: plastic small outline package; 32 leads; body width 7.5 mm SOT287-1 00-08-17 03-02-19CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 117 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 17. Abbreviations 18. References [1] Application note — MICORE reader IC family; Directly Matched Antenna Design. [2] Application note — MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas. [3] Application note — Directly matched Antenna - Excel calculation. [4] ISO standard — ISO/IEC 14443 Identification cards - Contactless integrated circuit(s) cards - Proximity cards, part 1-4. [5] Application note — MIFARE Implementation of Higher Baud rates. Table 177. Abbreviations and acronyms Acronym Description ASK Amplitude-Shift Keying BPSK Binary Phase-Shift Keying CMOS Complementary Metal-Oxide Semiconductor CRC Cyclic Redundancy Check EOF End Of Frame EPP Enhanced Parallel Port ETU Elementary Time Unit FIFO First In, First Out HBM Human Body Model LSB Least Significant Bit MM Machine Model MSB Most Significant Bit NRZ None Return to Zero POR Power-On Reset PCD Proximity Coupling Device PICC Proximity Integrated Circuit Card SOF Start Of Frame SPI Serial Peripheral InterfaceCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 118 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 19. Revision history Table 178. Revision history Document ID Release date Data sheet status Change notice Supersedes CLRC632 v. 3.7 20140227 Product data sheet - CLRC632 v. 3.6 Modifications: • Section 2 “General description”: 1st paragraph updated CLRC632 v. 3.6 20140130 Product data sheet - CLRC632_35 Modifications: • Section 2 “General description”: updated • Change of descriptive title CLRC632_35 20091110 Product data sheet - CLRC632_34 Modifications: • Data sheet security status changed from COMPANY CONFIDENTIAL to COMPANY PUBLIC • RATP/Innovatron Technologies license statement added to the legal page CLRC632_34 20091014 Product data sheet - 073933 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors • Legal texts have been adapted to the new company name where appropriate • The symbols for electrical characteristics and their parameters have been updated to meet the NXP Semiconductors’ guidelines • A number of inconsistencies in pin, register and bit names have been eliminated from the data sheet • All drawings have been updated • Several symbol changes made to drawings in Figure 23 on page 103 to Figure 26 on page 106 • Section 5 “Quick reference data” on page 3: section added • Section 6 “Ordering information” on page 3: updated • Section 15.1.2.4 “Antenna coil” on page 109: added missing formula and updated the last clause • Section 16 “Package outline” on page 116: updated • Section 18 “References” on page 117: added section and updated the references in the document 073933 December 2005 Product data sheet 073932 073932 April 2005 Product data sheet 073931 073931 May 2004 Product data sheet 073930 073930 November 2002 Product data sheet 073920 073920 June 2002 Preliminary data sheet 073910 073910 January 2002 internal version -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 119 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 20. Legal information 20.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 20.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. 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Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 120 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 20.4 Licenses 20.5 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. MIFARE — is a trademark of NXP Semiconductors N.V. ICODE and I-CODE — are trademarks of NXP Semiconductors N.V. MIFARE Ultralight — is a trademark of NXP Semiconductors N.V. 21. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Purchase of NXP ICs with ISO/IEC 14443 type B functionality This NXP Semiconductors IC is ISO/IEC 14443 Type B software enabled and is licensed under Innovatron’s Contactless Card patents license for ISO/IEC 14443 B. The license includes the right to use the IC in systems and/or end-user equipment. RATP/Innovatron TechnologyCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 121 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 22. Tables Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .3 Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Table 4. Supported microprocessor and EPP interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Table 5. Connection scheme for detecting the parallel interface type . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Table 6. SPI compatibility . . . . . . . . . . . . . . . . . . . . . . .10 Table 7. SPI read data . . . . . . . . . . . . . . . . . . . . . . . . . .10 Table 8. SPI read address . . . . . . . . . . . . . . . . . . . . . . . 11 Table 9. SPI write data . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 10. SPI write address . . . . . . . . . . . . . . . . . . . . . . 11 Table 11. EEPROM memory organization diagram . . . . .12 Table 12. Product information field . . . . . . . . . . . . . . . . .13 Table 13. Product type identification definition . . . . . . . .13 Table 14. Byte assignment for register initialization at start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Table 15. Shipment content of StartUp configuration file .15 Table 16. Byte assignment for register initialization at startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 17. Content of I-CODE1 startup configuration . . . .17 Table 18. FIFO buffer access . . . . . . . . . . . . . . . . . . . . .19 Table 19. Associated FIFO buffer registers and flags . . .20 Table 20. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . .21 Table 21. Interrupt control registers . . . . . . . . . . . . . . . .21 Table 22. Associated Interrupt request system registers and flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Table 23. TimeSlotPeriod . . . . . . . . . . . . . . . . . . . . . . . .26 Table 24. Associated timer unit registers and flags . . . . .27 Table 25. Signal on pins during Hard power-down . . . . .28 Table 26. Pin TX1 configurations . . . . . . . . . . . . . . . . . .31 Table 27. Pin TX2 configurations . . . . . . . . . . . . . . . . . .32 Table 28. TX1 and TX2 source resistance of n-channel driver transistor against GsCfgCW or GsCfgMod . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Table 29. Gain factors for the internal amplifier . . . . . . . .36 Table 30. DecoderSource[1:0] values . . . . . . . . . . . . . . .39 Table 31. ModulatorSource[1:0] values . . . . . . . . . . . . . .39 Table 32. MFOUTSelect[2:0] values . . . . . . . . . . . . . . . .39 Table 33. Register settings to enable use of the analog circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Table 34. MIFARE higher baud rates . . . . . . . . . . . . . . .40 Table 35. ISO/IEC 14443 B registers and flags . . . . . . . .41 Table 36. Dedicated address bus: assembling the register address . . . . . . . . . . . . . . . . . . . . . . . .43 Table 37. Multiplexed address bus: assembling the register address . . . . . . . . . . . . . . . . . . . . . . . .44 Table 38. Behavior and designation of register bits . . . . .44 Table 39. CLRC632 register overview . . . . . . . . . . . . . . .45 Table 40. CLRC632 register flags overview . . . . . . . . . .47 Table 41. Page register (address: 00h, 08h, 10h, 18h, 20h, 28h, 30h, 38h) reset value: 1000 0000b, 80h bit allocation . . . . . . . . . . . . . . . . . . . . . . .50 Table 42. Page register bit descriptions . . . . . . . . . . . . .50 Table 43. Command register (address: 01h) reset value: x000 0000b, x0h bit allocation . . . . . . .50 Table 44. Command register bit descriptions . . . . . . . . . 50 Table 45. FIFOData register (address: 02h) reset value: xxxx xxxxb, 05h bit allocation . . . . . . . . . . . . . 51 Table 46. FIFOData register bit descriptions . . . . . . . . . 51 Table 47. PrimaryStatus register (address: 03h) reset value: 0000 0101b, 05h bit allocation . . . . . . . 51 Table 48. PrimaryStatus register bit descriptions . . . . . . 51 Table 49. FIFOLength register (address: 04h) reset value: 0000 0000b, 00h bit allocation . . . . . . . 52 Table 50. FIFOLength bit descriptions . . . . . . . . . . . . . . 52 Table 51. SecondaryStatus register (address: 05h) reset value: 01100 000b, 60h bit allocation . . . 53 Table 52. SecondaryStatus register bit descriptions . . . . 53 Table 53. InterruptEn register (address: 06h) reset value: 0000 0000b, 00h bit allocation . . . . . . . 53 Table 54. InterruptEn register bit descriptions . . . . . . . . 53 Table 55. InterruptRq register (address: 07h) reset value: 0000 0000b, 00h bit allocation . . . . . . . 54 Table 56. InterruptRq register bit descriptions . . . . . . . . 54 Table 57. Control register (address: 09h) reset value: 0000 0000b, 00h bit allocation . . . . . . . . . . . . 55 Table 58. Control register bit descriptions . . . . . . . . . . . 55 Table 59. ErrorFlag register (address: 0Ah) reset value: 0100 0000b, 40h bit allocation . . . . . . . . . . . . 55 Table 60. ErrorFlag register bit descriptions . . . . . . . . . . 55 Table 61. CollPos register (address: 0Bh) reset value: 0000 0000b, 00h bit allocation . . . . . . . . . . . . 56 Table 62. CollPos register bit descriptions . . . . . . . . . . . 56 Table 63. TimerValue register (address: 0Ch) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . 57 Table 64. TimerValue register bit descriptions . . . . . . . . 57 Table 65. CRCResultLSB register (address: 0Dh) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . 57 Table 66. CRCResultLSB register bit descriptions . . . . . 57 Table 67. CRCResultMSB register (address: 0Eh) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . 57 Table 68. CRCResultMSB register bit descriptions . . . . 57 Table 69. BitFraming register (address: 0Fh) reset value: 0000 0000b, 00h bit allocation . . . . . . . . . . . . 58 Table 70. BitFraming register bit descriptions . . . . . . . . . 58 Table 71. TxControl register (address: 11h) reset value: 0101 1000b, 58h bit allocation . . . . . . . . . . . . 59 Table 72. TxControl register bit descriptions . . . . . . . . . 59 Table 73. CwConductance register (address: 12h) reset value: 0011 1111b, 3Fh bit allocation . . . . . . . 60 Table 74. CwConductance register bit descriptions . . . . 60 Table 75. ModConductance register (address: 13h) reset value: 0011 1111b, 3Fh bit allocation . . . . . . . 60 Table 76. ModConductance register bit descriptions . . . 60 Table 77. CoderControl register (address: 14h) reset value: 0001 1001b, 19h bit allocation . . . . . . . . . . . . 61 Table 78. CoderControl register bit descriptions . . . . . . . 61 Table 79. ModWidth register (address: 15h) reset value: 0001 0011b, 13h bit allocation . . . . . . . . . . . . 62 Table 80. ModWidth register bit descriptions . . . . . . . . . 62 Table 81. ModWidthSOF register (address: 16h) reset CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 122 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution value: 0011 1111b, 3Fh bit allocation . . . . . . . .62 Table 82. ModWidthSOF register bit descriptions . . . . . .62 Table 83. TypeBFraming register (address: 17h) reset value: 0011 1011b, 3Bh bit allocation . . . . . . .63 Table 84. TypeBFraming register bit descriptions . . . . . .63 Table 85. RxControl1 register (address: 19h) reset value: 0111 0011b, 73h bit allocation . . . . . . . . . . . . .64 Table 86. RxControl1 register bit descriptions . . . . . . . . .64 Table 87. DecoderControl register (address: 1Ah) reset value: 0000 1000b, 08h bit allocation . . . . . . .65 Table 88. DecoderControl register bit descriptions . . . . .65 Table 89. BitPhase register (address: 1Bh) reset value: 1010 1101b, ADh bit allocation . . . . . . . . . . . .65 Table 90. BitPhase register bit descriptions . . . . . . . . . .65 Table 91. RxThreshold register (address: 1Ch) reset value: 1111 1111b, FFh bit allocation . . . . . . . . . . . . .66 Table 92. RxThreshold register bit descriptions . . . . . . .66 Table 93. BPSKDemControl register (address: 1Dh) reset value: 0001 1110b, 1Eh bit allocation . . . . . . .66 Table 94. BPSKDemControl register bit descriptions . . .66 Table 95. RxControl2 register (address: 1Eh) reset value: 0100 0001b, 41h bit allocation . . . . . . . . . . . . .67 Table 96. RxControl2 register bit descriptions . . . . . . . . .67 Table 97. ClockQControl register (address: 1Fh) reset value: 000x xxxxb, xxh bit allocation . . . . . . . .67 Table 98. ClockQControl register bit descriptions . . . . . .67 Table 99. RxWait register (address: 21h) reset value: 0000 0101b, 06h bit allocation . . . . . . . . . . . . .68 Table 100. RxWait register bit descriptions . . . . . . . . . . .68 Table 101. ChannelRedundancy register (address: 22h) reset value: 0000 0011b, 03h bit allocation . . .68 Table 102. ChannelRedundancy bit descriptions . . . . . . .68 Table 103. CRCPresetLSB register (address: 23h) reset value: 0101 0011b, 63h bit allocation . . . . . . .69 Table 104. CRCPresetLSB register bit descriptions . . . . .69 Table 105. CRCPresetMSB register (address: 24h) reset value: 0101 0011b, 63h bit allocation . . . . . . .69 Table 106. CRCPresetMSB bit descriptions . . . . . . . . . . .69 Table 107. TimeSlotPeriod register (address: 25h) reset value: 0000 0000b, 00h bit allocation . . . . . . .69 Table 108. TimeSlotPeriod register bit descriptions . . . . .70 Table 109. MFOUTSelect register (address: 26h) reset value: 0000 0000b, 00h bit allocation . . . . . . .70 Table 110. MFOUTSelect register bit descriptions . . . . . .70 Table 111. PreSet27 (address: 27h) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . .70 Table 112. FIFOLevel register (address: 29h) reset value: 0000 1000b, 08h bit allocation . . . . . . .71 Table 113. FIFOLevel register bit descriptions . . . . . . . . .71 Table 114. TimerClock register (address: 2Ah) reset value: 0000 0111b, 07h bit allocation . . . . . . . .71 Table 115. TimerClock register bit descriptions . . . . . . . .71 Table 116. TimerControl register (address: 2Bh) reset value: 0000 0110b, 06h bit allocation . . . . . . .72 Table 117. TimerControl register bit descriptions . . . . . . .72 Table 118. TimerReload register (address: 2Ch) reset value: 0000 1010b, 0Ah bit allocation . . . . . . .72 Table 119. TimerReload register bit descriptions . . . . . . .72 Table 120. IRQPinConfig register (address: 2Dh) reset value: 0000 0010b, 02h bit allocation . . . . . . . 73 Table 121. IRQPinConfig register bit descriptions . . . . . . 73 Table 122. PreSet2E register (address: 2Eh) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . 73 Table 123. PreSet2F register (address: 2Fh) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . 73 Table 124. Reserved registers (address: 31h, 32h, 33h, 34h, 35h, 36h, 37h) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . 73 Table 125. Reserved register (address: 39h) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . 74 Table 126. TestAnaSelect register (address: 3Ah) reset value: 0000 0000b, 00h bit allocation . . . . . . . 74 Table 127. TestAnaSelect bit descriptions . . . . . . . . . . . . 74 Table 128. Reserved register (address: 3Bh) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . 75 Table 129. Reserved register (address: 3Ch) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . . . . . . 75 Table 130. TestDigiSelect register (address: 3Dh) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . 75 Table 131. TestDigiSelect register bit descriptions . . . . . 75 Table 132. Reserved register (address: 3Eh, 3Fh) reset value: xxxx xxxxb, xxh bit allocation . . . . . . . . 76 Table 133. CLRC632 commands overview . . . . . . . . . . . 76 Table 134. StartUp command 3Fh . . . . . . . . . . . . . . . . . . 78 Table 135. Idle command 00h . . . . . . . . . . . . . . . . . . . . . 78 Table 136. Transmit command 1Ah . . . . . . . . . . . . . . . . . 79 Table 137. Transmission of frames of more than 64 bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 138. Receive command 16h . . . . . . . . . . . . . . . . . 82 Table 139. Return values for bit-collision positions . . . . . 84 Table 140. Communication error table . . . . . . . . . . . . . . . 84 Table 141. Transceive command 1Eh . . . . . . . . . . . . . . . 85 Table 142. Meaning of ModemState . . . . . . . . . . . . . . . . 85 Table 143. Transmit command 1Ah . . . . . . . . . . . . . . . . . 87 Table 144. Receive command 16h . . . . . . . . . . . . . . . . . 88 Table 145. Return values for bit-collision positions . . . . . 90 Table 146. Communication error table . . . . . . . . . . . . . . . 90 Table 147. Transceive command 1Eh . . . . . . . . . . . . . . . 91 Table 148. ModemState values . . . . . . . . . . . . . . . . . . . . 91 Table 149. WriteE2 command 01h . . . . . . . . . . . . . . . . . . 93 Table 150. ReadE2 command 03h . . . . . . . . . . . . . . . . . 95 Table 151. LoadConfig command 07h . . . . . . . . . . . . . . . 95 Table 152. CalcCRC command 12h . . . . . . . . . . . . . . . . 96 Table 153. CRC coprocessor parameters . . . . . . . . . . . . 96 Table 154. ErrorFlag register error flags overview . . . . . . 97 Table 155. LoadKeyE2 command 0Bh . . . . . . . . . . . . . . 97 Table 156. LoadKey command 19h . . . . . . . . . . . . . . . . . 97 Table 157. Authent1 command 0Ch . . . . . . . . . . . . . . . . 98 Table 158. Authent2 command 14h . . . . . . . . . . . . . . . . . 98 Table 159. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 160. Operating condition range . . . . . . . . . . . . . . . 99 Table 161. Current consumption . . . . . . . . . . . . . . . . . . 100 Table 162. Standard input pin characteristics . . . . . . . . 100 Table 163. Schmitt trigger input pin characteristics . . . . 100 Table 164. RSTPD input pin characteristics . . . . . . . . . 101 Table 165. RX input capacitance and input voltage CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 123 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Table 166. Digital output pin characteristics . . . . . . . . . .101 Table 167. Antenna driver output pin characteristics . . .102 Table 168. Timing specification for separate read/write strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 Table 169. Common read/write strobe timing specification . . . . . . . . . . . . . . . . . . . . . . . . . .103 Table 170. Common read/write strobe timing specification for EPP . . . . . . . . . . . . . . . . . . .104 Table 171. SPI timing specification . . . . . . . . . . . . . . . . .106 Table 172. Clock frequency . . . . . . . . . . . . . . . . . . . . . .106 Table 173. EEPROM characteristics . . . . . . . . . . . . . . .107 Table 174. Signal routed to pin MFOUT . . . . . . . . . . . . . 110 Table 175. Analog test signal selection . . . . . . . . . . . . . 112 Table 176. Digital test signal selection . . . . . . . . . . . . . . 113 Table 177. Abbreviations and acronyms . . . . . . . . . . . . . 117 Table 178. Revision history . . . . . . . . . . . . . . . . . . . . . . . 118CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 124 of 127 NXP Semiconductors CLRC632 Standard multi-protocol reader solution 23. Figures Fig 1. CLRC632 block diagram . . . . . . . . . . . . . . . . . . . .4 Fig 2. CLRC632 pin configuration . . . . . . . . . . . . . . . . . .5 Fig 3. Connection to microprocessor: separate read and write strobes . . . . . . . . . . . . . . . . . . . . . . . . . .8 Fig 4. Connection to microprocessor: common read and write strobes . . . . . . . . . . . . . . . . . . . . . . . . . .9 Fig 5. Connection to microprocessor: EPP common read/write strobes and handshake. . . . . . . . . . . . .9 Fig 6. Connection to microprocessor: SPI . . . . . . . . . . .10 Fig 7. Key storage format . . . . . . . . . . . . . . . . . . . . . . .18 Fig 8. Timer module block diagram . . . . . . . . . . . . . . . .24 Fig 9. TimeSlotPeriod . . . . . . . . . . . . . . . . . . . . . . . . . .26 Fig 10. The StartUp procedure. . . . . . . . . . . . . . . . . . . . .29 Fig 11. Quartz clock connection . . . . . . . . . . . . . . . . . . .30 Fig 12. Receiver circuit block diagram. . . . . . . . . . . . . . .35 Fig 13. Automatic Q-clock calibration . . . . . . . . . . . . . . .36 Fig 14. Serial signal switch block diagram. . . . . . . . . . . .38 Fig 15. Crypto1 key handling block diagram . . . . . . . . . .42 Fig 16. Transmitting bit oriented frames . . . . . . . . . . . . .80 Fig 17. Timing for transmitting byte oriented frames . . . .81 Fig 18. Timing for transmitting bit oriented frames. . . . . .81 Fig 19. Card communication state diagram . . . . . . . . . . .86 Fig 20. Timing for transmitting byte oriented frames . . . .88 Fig 21. Label communication state diagram . . . . . . . . . .92 Fig 22. EEPROM programming timing diagram. . . . . . . .94 Fig 23. Separate read/write strobe timing diagram . . . .103 Fig 24. Common read/write strobe timing diagram . . . .104 Fig 25. Timing diagram for common read/write strobe; EPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 Fig 26. Timing diagram for SPI . . . . . . . . . . . . . . . . . . .106 Fig 27. Application example circuit diagram: directly matched antenna . . . . . . . . . . . . . . . . . . . . . . . .107 Fig 28. TX control signals . . . . . . . . . . . . . . . . . . . . . . . 111 Fig 29. RX control signals . . . . . . . . . . . . . . . . . . . . . . . 112 Fig 30. ISO/IEC 14443 A receiving path Q-clock. . . . . . 114 Fig 31. I-CODE1 receiving path Q-clock . . . . . . . . . . . . 115 Fig 32. Package outline SOT287-1 . . . . . . . . . . . . . . . . 116CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 125 of 127 continued >> NXP Semiconductors CLRC632 Standard multi-protocol reader solution 24. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 General description . . . . . . . . . . . . . . . . . . . . . . 1 3 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 3.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Quick reference data . . . . . . . . . . . . . . . . . . . . . 3 6 Ordering information. . . . . . . . . . . . . . . . . . . . . 3 7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5 8.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 Functional description . . . . . . . . . . . . . . . . . . . 7 9.1 Digital interface. . . . . . . . . . . . . . . . . . . . . . . . . 7 9.1.1 Overview of supported microprocessor interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 9.1.2 Automatic microprocessor interface detection . 7 9.1.3 Connection to different microprocessor types . 8 9.1.3.1 Separate read and write strobe . . . . . . . . . . . . 8 9.1.3.2 Common read and write strobe . . . . . . . . . . . . 9 9.1.3.3 Common read and write strobe: EPP with handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9.1.4 Serial Peripheral Interface . . . . . . . . . . . . . . . . 9 9.1.4.1 SPI read data . . . . . . . . . . . . . . . . . . . . . . . . . 10 9.1.4.2 SPI write data . . . . . . . . . . . . . . . . . . . . . . . . . 11 9.2 Memory organization of the EEPROM . . . . . . 12 9.2.1 Product information field (read only). . . . . . . . 13 9.2.2 Register initialization files (read/write) . . . . . . 13 9.2.2.1 StartUp register initialization file (read/write) . 14 9.2.2.2 Factory default StartUp register initialization file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9.2.2.3 Register initialization file (read/write) . . . . . . . 16 9.2.2.4 Content of I-CODE1 and ISO/IEC 15693 StartUp register values . . . . . . . . . . . . . . . . . . 16 9.2.3 Crypto1 keys (write only) . . . . . . . . . . . . . . . . 18 9.2.3.1 Key format . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.2.3.2 Storage of keys in the EEPROM . . . . . . . . . . 18 9.3 FIFO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.3.1 Accessing the FIFO buffer . . . . . . . . . . . . . . . 19 9.3.1.1 Access rules . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.3.2 Controlling the FIFO buffer . . . . . . . . . . . . . . . 19 9.3.3 FIFO buffer status information . . . . . . . . . . . . 20 9.3.4 FIFO buffer registers and flags. . . . . . . . . . . . 20 9.4 Interrupt request system. . . . . . . . . . . . . . . . . 20 9.4.1 Interrupt sources overview . . . . . . . . . . . . . . . 21 9.4.2 Interrupt request handling. . . . . . . . . . . . . . . . 21 9.4.2.1 Controlling interrupts and getting their status . 21 9.4.2.2 Accessing the interrupt registers . . . . . . . . . . 22 9.4.3 Configuration of pin IRQ . . . . . . . . . . . . . . . . 22 9.4.4 Register overview interrupt request system. . 23 9.5 Timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.5.1 Timer unit implementation . . . . . . . . . . . . . . . 24 9.5.1.1 Timer unit block diagram . . . . . . . . . . . . . . . . 24 9.5.1.2 Controlling the timer unit . . . . . . . . . . . . . . . . 24 9.5.1.3 Timer unit clock and period . . . . . . . . . . . . . . 25 9.5.1.4 Timer unit status. . . . . . . . . . . . . . . . . . . . . . . 25 9.5.1.5 TimeSlotPeriod. . . . . . . . . . . . . . . . . . . . . . . . 26 9.5.2 Using the timer unit functions. . . . . . . . . . . . . 27 9.5.2.1 Time-out and WatchDog counters . . . . . . . . . 27 9.5.2.2 Stopwatch . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.5.2.3 Programmable one shot timer and periodic trigger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.5.3 Timer unit registers . . . . . . . . . . . . . . . . . . . . 27 9.6 Power reduction modes . . . . . . . . . . . . . . . . . 28 9.6.1 Hard power-down. . . . . . . . . . . . . . . . . . . . . . 28 9.6.2 Soft power-down mode . . . . . . . . . . . . . . . . . 28 9.6.3 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . 29 9.6.4 Automatic receiver power-down. . . . . . . . . . . 29 9.7 StartUp phase . . . . . . . . . . . . . . . . . . . . . . . . 29 9.7.1 Hard power-down phase . . . . . . . . . . . . . . . . 29 9.7.2 Reset phase. . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.7.3 Initialization phase . . . . . . . . . . . . . . . . . . . . . 30 9.7.4 Initializing the parallel interface type . . . . . . . 30 9.8 Oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . 30 9.9 Transmitter pins TX1 and TX2 . . . . . . . . . . . . 31 9.9.1 Configuring pins TX1 and TX2. . . . . . . . . . . . 31 9.9.2 Antenna operating distance versus power consumption. . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.9.3 Antenna driver output source resistance . . . . 32 9.9.3.1 Source resistance table . . . . . . . . . . . . . . . . . 33 9.9.3.2 Calculating the relative source resistance . . . 34 9.9.3.3 Calculating the effective source resistance . . 34 9.9.4 Pulse width. . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.10 Receiver circuitry . . . . . . . . . . . . . . . . . . . . . . 34 9.10.1 Receiver circuit block diagram . . . . . . . . . . . . 35 9.10.2 Receiver operation. . . . . . . . . . . . . . . . . . . . . 35 9.10.2.1 Automatic Q-clock calibration . . . . . . . . . . . . 35 9.10.2.2 Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.10.2.3 Correlation circuitry . . . . . . . . . . . . . . . . . . . . 37 9.10.2.4 Evaluation and digitizer circuitry . . . . . . . . . . 37 9.11 Serial signal switch . . . . . . . . . . . . . . . . . . . . 37 9.11.1 Serial signal switch block diagram . . . . . . . . . 38 9.11.2 Serial signal switch registers . . . . . . . . . . . . . 38 9.11.2.1 Active antenna concept . . . . . . . . . . . . . . . . . 39 9.11.2.2 Driving both RF parts . . . . . . . . . . . . . . . . . . . 40 9.12 MIFARE higher baud rates. . . . . . . . . . . . . . . 40CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.7 — 27 February 2014 073937 126 of 127 continued >> NXP Semiconductors CLRC632 Standard multi-protocol reader solution 9.13 ISO/IEC 14443 B communication scheme . . . 41 9.14 MIFARE authentication and Crypto1 . . . . . . . 42 9.14.1 Crypto1 key handling . . . . . . . . . . . . . . . . . . . 42 9.14.2 Authentication procedure . . . . . . . . . . . . . . . . 43 10 CLRC632 registers. . . . . . . . . . . . . . . . . . . . . . 43 10.1 Register addressing modes . . . . . . . . . . . . . . 43 10.1.1 Page registers . . . . . . . . . . . . . . . . . . . . . . . . 43 10.1.2 Dedicated address bus. . . . . . . . . . . . . . . . . . 43 10.1.3 Multiplexed address bus. . . . . . . . . . . . . . . . . 43 10.2 Register bit behavior. . . . . . . . . . . . . . . . . . . . 44 10.3 Register overview . . . . . . . . . . . . . . . . . . . . . . 45 10.4 CLRC632 register flags overview . . . . . . . . . . 47 10.5 Register descriptions . . . . . . . . . . . . . . . . . . . 50 10.5.1 Page 0: Command and status . . . . . . . . . . . . 50 10.5.1.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.5.1.2 Command register . . . . . . . . . . . . . . . . . . . . . 50 10.5.1.3 FIFOData register. . . . . . . . . . . . . . . . . . . . . . 51 10.5.1.4 PrimaryStatus register . . . . . . . . . . . . . . . . . . 51 10.5.1.5 FIFOLength register . . . . . . . . . . . . . . . . . . . . 52 10.5.1.6 SecondaryStatus register . . . . . . . . . . . . . . . . 53 10.5.1.7 InterruptEn register. . . . . . . . . . . . . . . . . . . . . 53 10.5.1.8 InterruptRq register. . . . . . . . . . . . . . . . . . . . . 54 10.5.2 Page 1: Control and status . . . . . . . . . . . . . . . 55 10.5.2.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.5.2.2 Control register . . . . . . . . . . . . . . . . . . . . . . . . 55 10.5.2.3 ErrorFlag register . . . . . . . . . . . . . . . . . . . . . . 55 10.5.2.4 CollPos register . . . . . . . . . . . . . . . . . . . . . . . 56 10.5.2.5 TimerValue register. . . . . . . . . . . . . . . . . . . . . 57 10.5.2.6 CRCResultLSB register . . . . . . . . . . . . . . . . . 57 10.5.2.7 CRCResultMSB register. . . . . . . . . . . . . . . . . 57 10.5.2.8 BitFraming register . . . . . . . . . . . . . . . . . . . . . 58 10.5.3 Page 2: Transmitter and control . . . . . . . . . . . 59 10.5.3.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.5.3.2 TxControl register . . . . . . . . . . . . . . . . . . . . . . 59 10.5.3.3 CwConductance register . . . . . . . . . . . . . . . . 60 10.5.3.4 ModConductance register. . . . . . . . . . . . . . . . 60 10.5.3.5 CoderControl register . . . . . . . . . . . . . . . . . . . 61 10.5.3.6 ModWidth register. . . . . . . . . . . . . . . . . . . . . . 62 10.5.3.7 ModWidthSOF register . . . . . . . . . . . . . . . . . . 62 10.5.3.8 TypeBFraming . . . . . . . . . . . . . . . . . . . . . . . . 63 10.5.4 Page 3: Receiver and decoder control . . . . . . 64 10.5.4.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.5.4.2 RxControl1 register. . . . . . . . . . . . . . . . . . . . . 64 10.5.4.3 DecoderControl register . . . . . . . . . . . . . . . . . 65 10.5.4.4 BitPhase register . . . . . . . . . . . . . . . . . . . . . . 65 10.5.4.5 RxThreshold register . . . . . . . . . . . . . . . . . . . 66 10.5.4.6 BPSKDemControl. . . . . . . . . . . . . . . . . . . . . . 66 10.5.4.7 RxControl2 register. . . . . . . . . . . . . . . . . . . . . 67 10.5.4.8 ClockQControl register . . . . . . . . . . . . . . . . . . 67 10.5.5 Page 4: RF Timing and channel redundancy . 68 10.5.5.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.5.5.2 RxWait register. . . . . . . . . . . . . . . . . . . . . . . . 68 10.5.5.3 ChannelRedundancy register . . . . . . . . . . . . 68 10.5.5.4 CRCPresetLSB register . . . . . . . . . . . . . . . . . 69 10.5.5.5 CRCPresetMSB register . . . . . . . . . . . . . . . . 69 10.5.5.6 TimeSlotPeriod register . . . . . . . . . . . . . . . . . 69 10.5.5.7 MFOUTSelect register . . . . . . . . . . . . . . . . . . 70 10.5.5.8 PreSet27 register . . . . . . . . . . . . . . . . . . . . . . 70 10.5.6 Page 5: FIFO, timer and IRQ pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.5.6.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.5.6.2 FIFOLevel register . . . . . . . . . . . . . . . . . . . . . 71 10.5.6.3 TimerClock register . . . . . . . . . . . . . . . . . . . . 71 10.5.6.4 TimerControl register . . . . . . . . . . . . . . . . . . . 72 10.5.6.5 TimerReload register . . . . . . . . . . . . . . . . . . . 72 10.5.6.6 IRQPinConfig register . . . . . . . . . . . . . . . . . . 73 10.5.6.7 PreSet2E register. . . . . . . . . . . . . . . . . . . . . . 73 10.5.6.8 PreSet2F register. . . . . . . . . . . . . . . . . . . . . . 73 10.5.7 Page 6: reserved . . . . . . . . . . . . . . . . . . . . . . 73 10.5.7.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.5.7.2 Reserved registers 31h, 32h, 33h, 34h, 35h, 36h and 37h . . . . . . . . . . . . . . . . . . . . . . 73 10.5.8 Page 7: Test control . . . . . . . . . . . . . . . . . . . . 74 10.5.8.1 Page register . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.5.8.2 Reserved register 39h . . . . . . . . . . . . . . . . . . 74 10.5.8.3 TestAnaSelect register . . . . . . . . . . . . . . . . . . 74 10.5.8.4 Reserved register 3Bh . . . . . . . . . . . . . . . . . . 75 10.5.8.5 Reserved register 3Ch . . . . . . . . . . . . . . . . . . 75 10.5.8.6 TestDigiSelect register . . . . . . . . . . . . . . . . . . 75 10.5.8.7 Reserved registers 3Eh, 3Fh . . . . . . . . . . . . . 76 11 CLRC632 command set . . . . . . . . . . . . . . . . . 76 11.1 CLRC632 command overview . . . . . . . . . . . . 76 11.1.1 Basic states . . . . . . . . . . . . . . . . . . . . . . . . . . 78 11.1.2 StartUp command 3Fh . . . . . . . . . . . . . . . . . . 78 11.1.3 Idle command 00h . . . . . . . . . . . . . . . . . . . . . 78 11.2 Commands for ISO/IEC 14443 A card communication. . . . . . . . . . . . . . . . . . . . . . . . 79 11.2.1 Transmit command 1Ah. . . . . . . . . . . . . . . . . 79 11.2.1.1 Using the Transmit command . . . . . . . . . . . . 79 11.2.1.2 RF channel redundancy and framing. . . . . . . 80 11.2.1.3 Transmission of bit oriented frames. . . . . . . . 80 11.2.1.4 Transmission of frames with more than 64 bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 11.2.2 Receive command 16h . . . . . . . . . . . . . . . . . 82 11.2.2.1 Using the Receive command . . . . . . . . . . . . . 82 11.2.2.2 RF channel redundancy and framing. . . . . . . 82 11.2.2.3 Collision detection . . . . . . . . . . . . . . . . . . . . . 83 11.2.2.4 Receiving bit oriented frames . . . . . . . . . . . . 84 11.2.2.5 Communication errors . . . . . . . . . . . . . . . . . . 84 11.2.3 Transceive command 1Eh . . . . . . . . . . . . . . . 85NXP Semiconductors CLRC632 Standard multi-protocol reader solution © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 February 2014 073937 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 11.2.4 States of the card communication. . . . . . . . . . 85 11.2.5 Card communication state diagram . . . . . . . . 86 11.3 I-CODE1 and ISO/IEC 15693 label communication commands. . . . . . . . . . . . . . . 87 11.3.1 Transmit command 1Ah . . . . . . . . . . . . . . . . . 87 11.3.1.1 Using the Transmit command. . . . . . . . . . . . . 87 11.3.1.2 RF channel redundancy and framing . . . . . . . 88 11.3.1.3 Transmission of frames of more than 64 bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 11.3.2 Receive command 16h. . . . . . . . . . . . . . . . . . 88 11.3.2.1 Using the Receive command . . . . . . . . . . . . . 89 11.3.2.2 RF channel redundancy and framing . . . . . . . 89 11.3.2.3 Collision detection . . . . . . . . . . . . . . . . . . . . . 89 11.3.2.4 Communication errors . . . . . . . . . . . . . . . . . . 90 11.3.3 Transceive command 1Eh . . . . . . . . . . . . . . . 91 11.3.4 Label communication states . . . . . . . . . . . . . . 91 11.3.5 Label communication state diagram. . . . . . . . 92 11.4 EEPROM commands . . . . . . . . . . . . . . . . . . . 93 11.4.1 WriteE2 command 01h . . . . . . . . . . . . . . . . . . 93 11.4.1.1 Programming process . . . . . . . . . . . . . . . . . . 93 11.4.1.2 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . 94 11.4.1.3 WriteE2 command error flags. . . . . . . . . . . . . 94 11.4.2 ReadE2 command 03h. . . . . . . . . . . . . . . . . . 95 11.4.2.1 ReadE2 command error flags. . . . . . . . . . . . . 95 11.5 Diverse commands. . . . . . . . . . . . . . . . . . . . . 95 11.5.1 LoadConfig command 07h . . . . . . . . . . . . . . . 95 11.5.1.1 Register assignment. . . . . . . . . . . . . . . . . . . . 95 11.5.1.2 Relevant LoadConfig command error flags . . 96 11.5.2 CalcCRC command 12h. . . . . . . . . . . . . . . . . 96 11.5.2.1 CRC coprocessor settings . . . . . . . . . . . . . . . 96 11.5.2.2 CRC coprocessor status flags . . . . . . . . . . . . 96 11.6 Error handling during command execution. . . 97 11.7 MIFARE security commands . . . . . . . . . . . . . 97 11.7.1 LoadKeyE2 command 0Bh. . . . . . . . . . . . . . . 97 11.7.1.1 Relevant LoadKeyE2 command error flags . . 97 11.7.2 LoadKey command 19h . . . . . . . . . . . . . . . . . 97 11.7.2.1 Relevant LoadKey command error flags . . . . 98 11.7.3 Authent1 command 0Ch. . . . . . . . . . . . . . . . . 98 11.7.4 Authent2 command 14h . . . . . . . . . . . . . . . . . 98 11.7.4.1 Authent2 command effects . . . . . . . . . . . . . . . 99 12 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 99 13 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 99 13.1 Operating condition range . . . . . . . . . . . . . . . 99 13.2 Current consumption . . . . . . . . . . . . . . . . . . 100 13.3 Pin characteristics . . . . . . . . . . . . . . . . . . . . 100 13.3.1 Input pin characteristics . . . . . . . . . . . . . . . . 100 13.3.2 Digital output pin characteristics. . . . . . . . . . 101 13.3.3 Antenna driver output pin characteristics . . . 101 13.4 AC electrical characteristics . . . . . . . . . . . . . 102 13.4.1 Separate read/write strobe bus timing . . . . . 102 13.4.2 Common read/write strobe bus timing . . . . . 103 13.4.3 EPP bus timing . . . . . . . . . . . . . . . . . . . . . . 104 13.4.4 SPI timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 106 13.4.5 Clock frequency . . . . . . . . . . . . . . . . . . . . . . 106 14 EEPROM characteristics . . . . . . . . . . . . . . . 107 15 Application information . . . . . . . . . . . . . . . . 107 15.1 Typical application . . . . . . . . . . . . . . . . . . . . 107 15.1.1 Circuit diagram. . . . . . . . . . . . . . . . . . . . . . . 107 15.1.2 Circuit description . . . . . . . . . . . . . . . . . . . . 108 15.1.2.1 EMC low-pass filter . . . . . . . . . . . . . . . . . . . 108 15.1.2.2 Antenna matching . . . . . . . . . . . . . . . . . . . . 108 15.1.2.3 Receiver circuit . . . . . . . . . . . . . . . . . . . . . . 108 15.1.2.4 Antenna coil . . . . . . . . . . . . . . . . . . . . . . . . . 109 15.2 Test signals . . . . . . . . . . . . . . . . . . . . . . . . . . 110 15.2.1 Measurements using the serial signal switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 15.2.1.1 TX control. . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 15.2.1.2 RX control . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 15.2.2 Analog test signals. . . . . . . . . . . . . . . . . . . . . 112 15.2.3 Digital test signals . . . . . . . . . . . . . . . . . . . . . 113 15.2.4 Examples of ISO/IEC 14443 A analog and digital test signals . . . . . . . . . . . . . . . . . . 113 15.2.5 Examples of I-CODE1 analog and digital test signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 16 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 116 17 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 117 18 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . 118 20 Legal information . . . . . . . . . . . . . . . . . . . . . . 119 20.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 119 20.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 20.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 119 20.4 Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 20.5 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 120 21 Contact information . . . . . . . . . . . . . . . . . . . 120 22 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 23 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 24 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 1. General description The NTAG I2C is the first product of NXP’s NTAG family offering both contactless and contact interfaces (see Figure 1). In addition to the passive NFC Forum compliant contactless interface, the IC features an I2C contact interface, which can communicate with a microcontroller if the NTAG I2C is powered from an external power supply. An additional externally powered SRAM mapped into the memory allows a fast data transfer between the RF and I2C interfaces and vice versa, without the write cycle limitations of the EEPROM memory. The NTAG I2C product features a configurable Field Detection Pin, which provides a trigger to an external device depending on the activities at the RF interface. The NTAG I2C product can also supply power to external (low power) devices (e.g., a microcontroller) via the embedded energy harvesting circuitry. 2. Features and benefits 2.1 Key features RF interface NFC forum Type 2 Tag compliant I 2C interface NT3H1101/NT3H1201 NTAG I2C , NFC Forum type 2 Tag compliant IC with I2C interface Rev. 3.1 — 9 October 2014 265431 Product data sheet COMPANY PUBLIC Fig 1. Contactless and contact system aaa-010357 NFC enabled device Data Energy Data Energy I 2C EEPROM 1 1 1 0 0 0 1 Energy Harvesting Field detection Micro controllerNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 2 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Configurable field detection pin based on open drain implementation that can be triggered upon the following events: A RF field presence The first Start-of-Frame The selection of the tag only 64 byte SRAM buffer for fast transfer of data (Pass-through mode) between the RF and the I2C interfaces located outside the User Memory Wake up signal at the field detect pin when: New data has arrived from one interface Data has been read by the receiving interface Clear arbitration between RF and I2C interfaces: First come, first serve strategy Status flag bits to signal if one interface is busy writing to or reading data from the EEPROM Energy harvesting functionality to power external devices (e.g. microcontroller) FAST READ command for faster data reading 2.2 RF interface Contactless transmission of data NFC Forum Type 2 tag compliant (see Ref. 1) Operating frequency of 13.56 MHz Data transfer of 106 kbit/s 4 bytes (one page) written including all overhead in 4,8 ms via EEPROM or 0,8 ms via SRAM (Pass-through mode) Data integrity of 16-bit CRC, parity, bit coding, bit counting Operating distance of up to 100 mm (depending on various parameters, such as field strength and antenna geometry) True anticollision Unique 7 byte serial number (cascade level 2 according to ISO/IEC 14443-3 (see Ref. 2) 2.3 Memory 1904 bytes freely available with User Read/Write area (476 pages with 4 bytes per pages) for the NTAG I2C 2k version 888 bytes freely available with User Read/Write area (222 pages with 4 bytes per pages) for the NTAG I2C 1k version Field programmable RF read-only locking function with static and dynamic lock bits configurable from both I²C and NFC interfaces 64 bytes SRAM volatile memory without write endurance limitation Data retention time of 20 years Write endurance 200,000 cycles 2.4 I2C interface I 2C slave interface supports Standard (100 kHz) and Fast (up to 400 kHz) mode (see Ref. 3)NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 3 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 16 bytes (one block) written in 4,5ms (EEPROM) or 0,4 ms (SRAM - Pass-through mode) including all overhead RFID chip can be used as standard I2C EEPROM 2.5 Security Manufacturer-programmed 7-byte UID for each device Capability container with one time programmable bits Field programmable read-only locking function per page (per 32 pages for the extended memory section) 2.6 Key benefits The Pass-through mode allows fast download and upload of data from RF to I²C and vice versa without the cycling limitation of EEPROM NDEF message storage up to 1904 bytes (2k version) or up to 888 bytes (1k version) The mapping of the SRAM inside the User Memory buffer allows dynamic update of NDEF message content 3. Applications With all its integrated features and functions the NTAG I2C is the ideal solution to enable a contactless communication via an NFC device (e.g., NFC enabled mobile phone) to an electronic device for: Zero power configuration (late customization) Smart customer interaction (e.g., easier after sales service, such as firmware update) Advanced pairing (for e.g., WiFi or Blue tooth) for dynamic generation of sessions keys Easier product customization and customer experience for the following applications: Home automation Home appliances Consumer electronics Healthcare Printers Smart meters 4. Ordering information Table 1. Ordering information Type number Package Name Description Version NT3H1101W0FHK XQFN8 Plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.6mm; 1k bytes memory, 50pF input capacitance SOT902-3 NT3H1201W0FHK XQFN8 Plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.6mm; 2k bytes memory, 50pF input capacitance SOT902-3NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 4 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 5. Marking 6. Block diagram Table 2. Marking codes Type number Marking code NT3H1201FHK N12 NT3H1101FHK N11 Fig 2. Block diagram aaa-010358 I 2C SLAVE I 2C CONTROL RF INTERFACE LA LB POWER MANAGEMENT/ ENERGY HARVESTING DIGITAL CONTROL UNIT MEMORY EEPROM SRAM ARBITER/STATUS REGISTERS ANTICOLLISION COMMAND INTERPRETER MEMORY INTERFACE SDA SCL GND FD VCC VoutNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 5 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 7. Pinning information 7.1 Pinning 7.2 Pin description NXP recommends leaving the central pad of the package unconnected. (1) Dimension A: 1.6 mm (2) Dimension B: 0.5 mm Fig 3. Pin configuration aaa-010359 FD Transparent top view side view 4 8 6 5 7 3 1 2VSS LA SCL A B LB A VCC SDA VOUT Table 3. Pin description Pin Symbol Description 1 LA Antenna connection LA 2 VSS GND 3 SCL Serial Clock I2C 4 FD Field detection 5 SDA Serial data I2C 6 VCC VCC in connection (external power supply) 7 Vout Voltage out (energy harvesting) 8 LB Antenna connection LBNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 6 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 8. Functional description 8.1 Block description NTAG I2C ICs consist of (see details below): 2016 bytes of EEPROM memory, 64 Bytes of SRAM, a RF interface, Digital Control Unit (DCU), Power Management Unit (PMU) and an I²C interface. Energy and data are transferred via an antenna consisting of a coil with a few turns, which is directly connected to NTAG I2C IC. No further external components are necessary. • RF interface: – modulator/demodulator – rectifier – clock regenerator – Power-On Reset (POR) – voltage regulator • Anticollision: multiple cards may be selected and managed in sequence • Command interpreter: processes memory access commands supported by the NTAG I 2C • EEPROM interface 8.2 RF interface The RF-interface is based on the ISO/IEC 14443 Type A standard. During operation, the NFC device generates an RF field. The RF field must always be present (with short pauses for data communication), as it is used for both communication and as power supply for the tag. For both directions of data communication, there is one start bit at the beginning of each frame. Each byte is transmitted with an odd parity bit at the end. The LSB of the byte with the lowest address of the selected block is transmitted first. The maximum length of an NFC device to tag frame is 163 bits (16 data bytes + 2 CRC bytes = 16×9 + 2×9 + 1 start bit). The maximum length of a fixed size tag to NFC device frame is 307 bits (32 data bytes + 2 CRC bytes = 32 9 + 2 9 + 1 start bit). The FAST_READ command has a variable frame length, which depends on the start and end address parameters. The maximum frame length supported by the NFC device must be taken into account when issuing this command. For a multi-byte parameter, the least significant byte is always transmitted first. For example, when reading from the memory using the READ command, byte 0 from the addressed block is transmitted first, followed by bytes 1 to byte 3 out of this block. The same sequence continues for the next block and all subsequent blocks. 8.2.1 Data integrity The following mechanisms are implemented in the contactless communication link between the NFC device and the NTAG I²C IC to ensure very reliable data transmission: • 16 bits CRC per blockNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 7 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface • Parity bits for each byte • Bit count checking • Bit coding to distinguish between “1”, “0” and “no information” • Channel monitoring (protocol sequence and bit stream analysis) The commands are initiated by the NFC device and controlled by the Digital Control Unit of the NTAG I2C IC. The command response depends on the state of the IC, and for memory operations, also on the access conditions valid for the corresponding page. 8.2.2 RF communication principle The overall RF communication principle is summarized in Figure 4. 8.2.2.1 IDLE state After a power-on reset (POR), the NTAG I2C switches to the IDLE state. It only exits this state when a REQA or a WUPA command is received from the NFC device. Any other data received while in this state is interpreted as an error, and the NTAG I2C remains in the IDLE state. Fig 4. RF communication principle of NTAG I2C SELECT cascade level 2 READY 1 READY 2 SELECT cascade level 1 ACTIVE HALT IDLE POR ANTICOLLISION ANTICOLLISION HLTA identification and selection procedure memory operations aaa-012797 REQA WUPA WUPA READ (16 Byte) FAST_READ WRITE SECTOR_SELECT GET_VERSION NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 8 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface After a correctly executed HLTA command e.g., out of the ACTIVE state, the default waiting state changes from the IDLE state to the HALT state. This state can then only be exited with a WUPA command. 8.2.2.2 READY 1 state In the READY 1 state, the NFC device resolves the first part of the UID (3 bytes) using the ANTICOLLISION or SELECT commands in cascade level 1. This state is correctly exited after execution of the following command: • SELECT command from cascade level 1: the NFC device switches the NTAG I2C into READY2 state where the second part of the UID is resolved. 8.2.2.3 READY 2 state In the READY 2 state, the NTAG I2C supports the NFC device in resolving the second part of its UID (4 bytes) with the cascade level 2 ANTICOLLISION command. This state is usually exited using the cascade level 2 SELECT command. Remark: The response of the NTAG I2C to the cascade level 2 SELECT command is the Select AcKnowledge (SAK) byte. In accordance with ISO/IEC 14443, this byte indicates if the anticollision cascade procedure has finished. NTAG I2C is now uniquely selected and only this device will communicate with the NFC device even when other contactless devices are present in the NFC device field. 8.2.2.4 ACTIVE state All memory operations are operated in the ACTIVE state. The ACTIVE state is exited with the HLTA command and upon reception, the NTAG I2C transits to the HALT state. Any other data received when the device is in this state is interpreted as an error. Depending on its previous state, the NTAG I2C returns to either the IDLE state or HALT state. 8.2.2.5 HALT state HALT and IDLE states constitute the two wait states implemented in the NTAG I2C. An already processed NTAG I2C can be set into the HALT state using the HLTA command. In the anticollision phase, this state helps the NFC device distinguish between processed tags and tags yet to be selected. The NTAG I2C can only exit this state upon execution of the WUPA command. Any other data received when the device is in this state is interpreted as an error, and NTAG I2C state remains unchanged. 8.3 Memory organization The memory map is detailed in Figure 5 (1k memory) and Figure 6 (2k memory) from the RF interface and in Figure 7 (1k memory) and Figure 8 (2k memory) from the I2C interface. The SRAM memory is not mapped from the RF interface, because in the default settings of the NTAG I2C the Pass-through mode is not enabled. Please refer to Section 11 for examples of memory map from the RF interface with SRAM mapping. The structure of manufacturing data, static lock bytes, capability container and user memory pages (except of the user memory length) are compatible with other NTAG products.NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 9 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Any memory access which starts at a valid address and extends into an invalid access region will return 0x00 value in the invalid region. 8.3.1 Memory map from RF interface Memory access from the RF interface is organized in pages of 4 bytes each. Fig 5. NTAG I²C 1k memory organization from the RF interface aaa-012798 Sector adr. Hex. Dec. Hex. 0 1 2 3 conditions Page address 0h 0 0h 1h ...... 1 1h 2 2h 3 3h 4 4h 15 0Fh 225 E1h 226 E2h 227 E3h 228 E4h 229 E5h 230 E6h 231 E7h 232 E8h 233 E9h 234 EAh 255 FFh ...... ...... ...... ... Serial number Invalid access - returns NAK Serial number Internal data 00h Internal data Lock bytes Byte number within a page READ Capability Container (CC) READ&WRITE READ READ/R&W n.a. Dynamic lock bytes R&W/R 2h ...... Invalid access - returns NAK n.a. 3h 0 0h Invalid access - returns NAK n.a. Invalid access - returns NAK n.a. Invalid access - returns NAK n.a. User memory READ&WRITE 249 F9H 248 F8H Session registers See section 8.5.9 Configuration See section 8.5.9 255 FFH ...... Invalid access - returns NAK n.a. AccessNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 10 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 8.3.2 Memory map from I²C interface The memory access of NTAG I²C from the I²C interface is organized in blocks of 16 bytes each. Fig 6. NTAG I²C 2k memory organization from the RF interface aaa-012799 Sector adr. Hex. Dec. Hex. 0 1 2 3 conditions Page address 0h 0 0h 2h ...... 1 1h 1h 2 2h 3 3h 4 4h 15 0Fh 225 FFh 226 E2h 227 E3h 228 E4h 223 DFh 224 E0h 225 E1h 229 E5h 230 E6h 231 E7h 232 E8h 233 E9h 234 EAh 255 FFh ...... ...... ... Serial number Invalid access - returns NAK Serial number Internal data 00h Internal data Lock bytes Byte number within a page READ Capability Container (CC) READ&WRITE READ READ/R&W n.a. Dynamic lock bytes R&W/R 3h 0 0h Invalid access - returns NAK n.a. Invalid access - returns NAK n.a. Invalid access - returns NAK n.a. User memory READ&WRITE 249 F9H 248 F8H Session registers See section 8.5.9 Configuration See section 8.5.9 255 FFH ...... Invalid access - returns NAK n.a. Access 0 0h 1 1h ...... ...... ... ... ... ...NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 11 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Remark: * The Byte 0 of Block 0 is always read as 04h. Writing to this byte modifies the I²C address. Fig 7. NTAG I²C 1k memory organization from the I²C interface aaa-012800 Dec. Hex. 12 13 14 15 I 2C block address 1 1h 0 0h ... ... 55 37h 56 38h Serial number Serial number Internal data Internal data Lock bytes I 2C addr.* Byte number within a block 00h 00h 00h 00h R&W/READ Capability Container (CC) READ&WRITE User memory READ&WRITE User memory READ&WRITE Invalid access - returns NAK n.a. READ Dynamic lock bytes 00h R&W READ 57 39h Invalid access - returns NAK n.a. READ/R&W User memory READ&WRITE Access conditions 8 910 11 4567 0123 58 3Ah fixed 00h fixed 00h fixed 00h fixed 00h fixed 00h fixed 00h fixed 00h Configuration See section 8.5.9 fixed 00h READ READ 254 FEh fixed 00h fixed 00h fixed 00h fixed 00h fixed 00h fixed 00h fixed 00h Session registers (requires READ-Register command) See section 8.5.9 fixed 00h READ READ 59 3Bh ... ... 247 F7h Invalid access - returns NAK n.a. 248 F8h ... ... ... ... ... ... Invalid access - returns NAK n.a. 251 FBh SRAM memory (64 bytes) READ&WRITENT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 12 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 8.3.3 EEPROM The EEPROM is a non volatile memory that stores the 7 byte UID, the memory lock conditions, IC configuration information and the 1904 bytes User Data (888 byte User Data in case of the NTAG I2C 1k version). 8.3.4 SRAM For frequently changing data, a volatile memory of 64 bytes with unlimited endurance is built in. The 64 bytes are mapped in a similar way as is done in the EEPROM, i.e., 64 bytes are seen as 16 pages of 4 bytes. Remark: *The Byte 0 of Block 0 is always read as 04h. Writing to this byte modifies the I²C address. Fig 8. NTAG I²C 2k memory organization from the I²C interface aaa-012801 Dec. Hex. 12 13 14 15 I 2C block address 1 1h 0 0h ... ... 119 77h 120 78h Serial number Serial number Internal data Internal data Lock bytes I 2C addr.* Byte number within a block R&W/READ Capability Container (CC) READ&WRITE Dynamic lock bytes R&W Invalid access - returns NAK n.a. READ 00h 00h 00h 00h 00h 00h 00h 00h 00h READ 00h 00h 00h 00h 121 79h Invalid access - returns NAK n.a. READ/R&W User memory READ&WRITE Access conditions 8 910 11 4567 0123 122 7Ah fixed 00h fixed 00h fixed 00h fixed 00h fixed 00h fixed 00h fixed 00h Configuration See section 8.5.9 fixed 00h READ READ 254 FEh fixed 00h fixed 00h fixed 00h fixed 00h fixed 00h fixed 00h fixed 00h Session registers (requires READ-Register command) See section 8.9 fixed 00h READ READ 123 7Bh ... ... 247 F7h Invalid access - returns NAK n.a. 248 F8h ... ... ... ... ... ... Invalid access - returns NAK n.a. 251 FBh SRAM memory (64 bytes) READ&WRITENT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 13 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface The SRAM is only available if the tag is powered via the VCC pin. The SRAM is located at the end of the memory space and it is always directly accessible by the I2C host (addresses F8h to FBh). An RF reader cannot access the SRAM memory in normal mode (i.e., outside the Pass-through mode). The SRAM is only accessible by the RF reader if the SRAM is mirrored onto the EEPROM memory space. With Memory Mirror enabled (SRAM_MIRROR_ON_OFF=1 - see Section 11.2), the SRAM can be mirrored in the User Memory (page 1 to page 119 - see Section 11.2) for access from the RF side. The Memory mirror must be enabled once both interfaces are ON as this feature is disabled after each POR. The register SRAM_MIRROR_BLOCK (see Table 10) indicates the address of the first page of the SRAM buffer. In the case where the SRAM mirror is enabled and the READ command is addressing blocks where the SRAM mirror is located, the SRAM mirror byte values will be returned instead of the EEPROM byte values. Similarly, if the tag is not VCC powered, the SRAM mirror is disabled and reading out the bytes related to the SRAM mirror position would return the values from the EEPROM. In the Pass-through mode (PTHRU_ON_OFF=1 - see Section 8.3.11), the SRAM is mirrored to the fixed address 240 -255 for RF access (see Section 11) in the first memory sector for NTAG I2C 1k and in the second memory sector for NTAG I2C 2k. 8.3.5 UID/serial number The unique 7-byte serial number (UID) is programmed into the first 7 bytes of memory covering page addresses 00h and 01h - see Figure 9. These bytes are programmed and write protected in the production test. SN0 holds the Manufacturer ID for NXP Semiconductors (04h) in accordance with ISO/IEC 14443-3. 8.3.6 Static lock bytes The bits of byte 2 and byte 3 of page 02h (via RF) or byte 10 and 11 address 0h (via I2C) represent the field programmable, read-only locking mechanism (see Figure 10). Each page from 03h (CC) to 0Fh can be individually locked by setting the corresponding locking bit Lx to logic 1 to prevent further write access. After locking, the corresponding page becomes read-only memory. Fig 9. UID/serial number aaa-012802 MSB LSB page 0 byte 00000100 manufacturer ID for NXP Semiconductors (04h) UID0 UID1 UID2 UID3 UID4 UID5 UID6 SAK page 1 page 2 0123 ATQA1 7 bytes UID ATQA0 lock bytesNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 14 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface The three least significant bits of lock byte 0 are the block-locking bits. Bit 2 controls pages 0Ah to 0Fh (via RF), bit 1 controls pages 04h to 09h (via RF) and bit 0 controls page 03h (CC). Once the block-locking bits are set, the locking configuration for the corresponding memory area is frozen. For example, if BL15-10 is set to logic 1, then bits L15 to L10 (lock byte 1, bit[7:2]) can no longer be changed. The static locking and block-locking bits are set by the bytes 2 and 3 of the WRITE command to page 02h. The contents of the lock bytes are bit-wise OR’ed and the result then becomes the new content of the lock bytes. This process is irreversible from RF perspective. If a bit is set to logic 1, it cannot be changed back to logic 0. From I²C perspective, the bits can be reset to “0”. The contents of bytes 0 and 1 of page 02h are unaffected by the corresponding data bytes of the WRITE. The default value of the static lock bytes is 00 00h. 8.3.7 Dynamic Lock Bytes To lock the pages of NTAG I2C starting at page address 0Fh and onwards, the dynamic lock bytes are used. The dynamic lock bytes are located at page E2h sector 0h (NTAG I2C 1k) or address E0h sector 1 (NTAG I2C 2k). The three lock bytes cover the memory area of 830 data bytes (NTAG I2C 1k) or 1846 data bytes (NTAG I2C 2k). The granularity is 16 pages for NTAG I2C 1k and 32 pages for NTAG I2C 2k compared to a single page for the first 48 bytes (NTAG I2C 1k) or the first 64 bytes (NTAG I2C 2k) as shown in Figure 11 and Figure 12. Remark: Set all bits marked with RFUI to 0 when writing to the dynamic lock bytes. Fig 10. Static lock bytes 0 and 1 L 7 L 6 L 5 L 4 L CC BL 15-10 BL 9-4 BL CC MSB 0 page 2 Lx locks page x to read-only BLx blocks further locking for the memory area x lock byte 0 lock byte 1 123 LSB L 15 L 14 L 13 L 12 L 11 L 10 L 9 L 8 MSB LSB aaa-006983NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 15 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Fig 11. NTAG I2C 1k Dynamic lock bytes 0, 1 and 2 Fig 12. NTAG I2C 2k Dynamic lock bytes 0, 1 and 2 aaa-008092 page 226 (E2h) 0 1 2 3 LOCK PAGE 128-143 MSB LSB bit 7 6LOCK PAGE 112-127 LOCK PAGE 96-111 LOCK PAGE 80-95 LOCK PAGE 64-79 LOCK PAGE 48-63 LOCK PAGE 32-47 LOCK PAGE 16-31 LOCK PAGE 224-225 543210 RFUI MSB LSB bit 7 6RFUI LOCK PAGE 208-223 LOCK PAGE 192-207 LOCK PAGE 176-191 LOCK PAGE 160-175 LOCK PAGE 144-159 543210 RFUI MSB LSB bit 7 6BL 208-225 BL 176-207 BL 144-175 BL 112-143 BL 80-111 BL 48-79 BL 16-47 543210 page 224 (E0h) 0 1 2 3 Block Locking (BL) bits LOCK PAGE 240-271 MSB LSB bit 7 6 5 4 3 2 1 0 MSB LSB bit 7 6 5 4 3 2 1 0 MSB LSB bit 7 6 5 4 3 2 1 0 aaa-012803 LOCK PAGE 208-239 LOCK PAGE 176-207 LOCK PAGE 144-175 LOCK PAGE 112-143 LOCK PAGE 80-111 LOCK PAGE 48-79 LOCK PAGE 16-47 RFUI BL 464-479 LOCK PAGE 464-479 LOCK PAGE 432-463 LOCK PAGE 400-431 LOCK PAGE 368-399 LOCK PAGE 336-367 LOCK PAGE 304-335 LOCK PAGE 272-303 BL 400-463 BL 336-399 BL 272-335 BL 208-271 BL 144-207 BL 80-143 BL 16-79NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 16 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface The default value of the dynamic lock bytes is 00 00 00h. The value of Byte 3 is always 00h when read. Reading the 3 bytes for the dynamic lock bytes and the Byte 3 (00h) from RF interface (address E2h sector 0 (NTAG I2C 1k) or E0h sector 1 (NTAG I2C 2k) or from I2C (address 38h (NTAG I2C 1k) or 78h (NTAG I2C 2k)) will also return a fixed value for the next 12 bytes of 00h. Like for the static lock bytes, this process of modifying the dynamic lock bytes is irreversible from RF perspective. If a bit is set to logic 1, it cannot be changed back to logic 0. From I²C perspective, the bits can be reset to “0”. 8.3.8 Capability Container (CC bytes) The Capability Container CC (page 3) is programmed during the IC production according to the NFC Forum Type 2 Tag specification (see Ref. 1). These bytes may be bit-wise modified by a WRITE command from the I²C or RF interface. See examples for NTAG I2C 1k version in Figure 13 and for NTAG I2C 2k version in Figure 14. The default values of the CC bytes at delivery are defined in Section 8.3.10. Fig 13. CC bytes of NTAG I2C 1k version Fig 14. CC bytes of NTAG I2C 2k version aaa-012804 byte E1h 10h 6Dh 00h Example NTAG I2C 1k version CC bytes CC bytes byte 0123 page 3 default value (initialized state) 11100001 00010000 01101101 00000000 write command to page 3 00000000 00000000 00000000 00001111 result in page 3 (read-only state) 11100001 00010000 01101101 00001111 aaa-012805 Example NTAG I2C 2k version default value (initialized state) CC bytes 11100001 00010000 11101010 00000000 write command to page 3 00000000 00000000 00000000 00001111 result in page 3 (read-only state) 11100001 00010000 11101010 00001111 data E1h 10h EAh 00h CC bytes byte 0 1 2 3 page 3NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 17 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 8.3.9 User Memory pages Pages 04h to E1h via the RF interface - Block 1h to 37h, plus the first 8 bytes of block 38h via the I2C interface are the user memory read/write areas for NTAG I2C 1k version. Pages 04h (sector 0) to DFh (sector 1) via the RF interface - Block 1h to 77h via the I2C interface are the user memory read/write areas for NTAG I2C 2k version. The default values of the data pages at delivery are defined in Section 8.3.10.NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 18 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 8.3.10 Memory content at delivery The capability container in page 03h and the page 04h and 05h of NTAG I2C is pre-programmed to the initialized state according to the NFC Forum Type 2 Tag specification (see Ref. 1) as defined in Table 4 (NTAG I2C 1k version) and Table 5 (NTAG I 2C 2k version). This content is READ only from the RF side and READ&WRITE from the I²C side. The User memory contains an empty NDEF TLV. Remark: The default content of the data pages from page 05h onwards is not defined at delivery. 8.3.11 NTAG I2C configuration and session registers NTAG I2C functionalities can be configured and read in two separate locations depending if the configurations shall be effective within the communication session (session registers) or by default after Power On Reset (POR) (configuration bits). The configuration registers of pages E8h to E9h (sector 0 or 1 depending if it is for NTAG I²C 1k or 2k) via the RF interface or block 3Ah or 7Ah (depending if it is for NTAG I²C 1k or 2k) via the I2C interface, see Figure 5, Figure 6, Figure 7 and Figure 8, are used to configure the default functionalities of the NTAG I2C - see Table 6. Those bits values are stored in the EEPROM and represent the default settings to be effective after POR. Their values can be read & written by both interfaces when applicable and when not locked by the register lock bits (see REG_LOCK in Table 9). Table 4. Memory content at delivery NTAG I2C 1k version Page Address Byte number within page 0 1 2 3 03h E1h 10h 6Dh 00h 04h 03h 00h FEh 00h 05h 00h 00h 00h 00h Table 5. Memory content at delivery NTAG I2C 2k version Page Address Byte number within page 0 1 2 3 03h E1h 10h EAh 00h 04h 03h 00h FEh 00h 05h 00h 00h 00h 00h Table 6. Configuration memory NTAG I²C 1k RF address (sector 0) I 2C Address Byte number Dec Hex Dec Hex 0 1 2 3 232 E8h 58 3Ah NC_REG LAST_NDEF_BLOCK SRAM_MIRROR_ BLOCK WDT_LS 233 E9h WDT_MS I2C_CLOCK_STR REG_LOCK 00h fixedNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 19 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface The session registers Pages F8h to F9h (sector 3) via the RF interface or block FEh via I 2C, see Table 8, are used to configure or monitor the values of the current communication session- see Figure 6 and Figure 8. Those bits can only be read via the RF interface but both read and written via the I2C interface. Both the session and the configuration bits have the same register except the REG_LOCK bits, which are only available in the configuration bits and the NS_REG bits which are only available in the session registers. After POR, the configuration bits are loaded into the session registers. During the communication session, the values can be changed, but the related effect will only be visible within the communication session for the session registers or after POR for the configuration bits. After POR, the registers values will be again brought back to the default configuration values. All registers and configuration default values, access and descriptions are described in Table 9 and Table 10. Reading and writing the session registers via I²C can only be done via the READ & WRITE registers operation - see Section 9.8. Table 7. Configuration memory NTAG I²C 2k RF address (sector 1) I 2C Address Byte number Dec Hex Dec Hex 0 1 2 3 232 E8h 122 7Ah NC_REG LAST_NDEF_BLOCK SRAM_MIRROR_ BLOCK WDT_LS 233 E9h WDT_MS I2C_CLOCK_STR REG_LOCK 00h fixed Table 8. Session registers NTAG I²C 1k and 2k RF address (sector 3h) I 2C Address Byte number Dec Hex Dec Hex 0 1 2 3 248 F8h 254 FEh NC_REG LAST_NDEF_BLOCK SRAM_MIRROR _BLOCK WDT_LS 249 F9h WDT_MS I2C_CLOCK_STR NS_REG 00h fixed Table 9. Configuration bytes Bit Field Access via RF Access via I²C Default values Description NC_REG 7 I2C_RST_ON_OFF R&W R&W 0b enables soft reset through I²C repeated start - see Section 9.3 6 - READ R&W 0b No function - keep at 0b 5 FD_OFF R&W R&W 00b defines the event upon which the signal output on the FD pin is brought up 00b… if the field is switched off 01b… if the field is switched off or the tag is set to the HALT state 10b… if the field is switched off or the last page of the NDEF message has been read (defined in LAST_NDEF_BLOCK)NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 20 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 4 11b... (if FD_ON = 11b) if the field is switched off or if last data is read by I²C (in pass-through mode RF ---> I²C) or last data is written by I²C (in passthrough mode I²C---> RF) 11b... (if FD_ON = 00b or 01b or 10b) if the field is switched off See Section 8.4 for more details 3 FD_ON R&W R&W 00b defines the event upon which the signal output on the FD pin is brought down 00b… if the field is switched on 01b... by first valid Start-of-Frame (SoF) 10b... by selection of the tag 2 11b (in passthrough mode RF-->I²C) if the data is ready to be read from the I²C interface 11b (in passthrough mode I²C--> RF) if the data is read by the RF interface See Section 8.4for more details 1 - READ R&W 0b No function - keep at 0b 0 TRANSFER_DIR R&W R&W 1b defines the data flow direction for the data transfer 0b… From I²C to RF interface 1b… From RF to I²C interface In case the passthrough mode is not enabled 0b… no WRITE access from the RF side Table 9. …continuedConfiguration bytes Bit Field Access via RF Access via I²C Default values DescriptionNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 21 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface LAST_NDEF_BLOCK 7 Address of last BLOCK (16bytes) of NDEF message from I²C addressing. An RF read of the last page of the I2C block, specified by LAST_NDEF_BLOCK sets the register NDEF_DATA_READ to 1b and triggers FD_OFF if FD_OFF is set to 10b 1h is page 4h (first page of the User Memory) from RF addressing 2h is page 8h 3h is page Ch ……… 37h is page DEh - memory sector 0h (last possible page of User memory for NTAG I²C 1k) ...... 77h is page DCh - memory sector 1h (last page possible of the User Memory for NTAG I²C 2k) 6 5 4 LAST_NDEF_BLOCK R&W R&W 00h 3 2 1 0 SRAM_MIRROR_BLOCK 7 Address of first BLOCK (16bytes) of SRAM buffer when mirrored into the User memory from I²C addressing 1h is page 4h (first page of the User Memory) from RF addressing 2h is page 8h 3h is page Ch ……… 34h is page DEh - memory sector 0h (last possible page of User memory for NTAG I²C 1k) ...... 74h is page DCh - memory sector 1h (last page possible of the User Memory for NTAG I²C 2k) 6 5 4 SRAM_MIRROR_ R&W R&W F8h 3 BLOCK 2 1 0 WDT_LS 7 6 5 4 WDT_LS R&W R&W 48h Least Significant byte of watchdog time 3 control register 2 1 0 Table 9. …continuedConfiguration bytes Bit Field Access via RF Access via I²C Default values DescriptionNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 22 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface WDT_MS 7 6 5 4 WDT_MS R&W R&W 08h Most Significant byte of watchdog time 3 control register 2 1 0 I2C_CLOCK_STR 7 0b 6 0b 5 0b 4 READ READ 0b locked to 0b 3 0b 2 0b 1 0b 0 I2C_CLOCK_STR R&W R&W 1b Enables (1b) or disable (0b) the I²C clock stretching REG_LOCK 7 0b 6 0b 5 READ READ 0b locked to 0b 4 0b 3 0b 2 0b 1 R&W R&W 0b… Enable writing of the configuration bytes via I²C 1b… Disable writing of the configuration bytes via I²C One time programmable 0 REG_LOCK R&W R&W 00b 0b… Enable writing of the configuration bytes via RF 1b… Disable writing of the configuration bytes via RF One time programmable Table 9. …continuedConfiguration bytes Bit Field Access via RF Access via I²C Default values DescriptionNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 23 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Table 10. Session register bytes Bit Field Access via RF Access via I²C Default values Description NC_REG 7 I2C_RST_ON_OFF READ R&W - see configuration bytes description 6 PTHRU_ON_OFF READ R&W 0b 1b… enables data transfer via the SRAM buffer (Passthrough mode) 5 FD_OFF READ R&W 4 3 FD_ON READ R&W - see configuration bytes description 2 1 SRAM_MIRROR_ ON_OFF READ R&W 0b 1b enables SRAM mirroring 0 PTHRU_DIR READ R&W see configuration bytes description LAST_NDEF_BLOCK 7 6 5 4 LAST_NDEF_ BLOCK READ R&W - see configuration bytes description 3 2 1 0 SRAM_MIRROR_BLOCK 7 6 5 4 SRAM_MIRROR_ BLOCK READ R&W - see configuration bytes description 3 2 1 0 WDT_LS 7 6 5 4 WDT_LS READ R&W - see configuration bytes description 3 2 1 0NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 24 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 8.4 Configurable Field Detection Pin The field detection feature provides the capability to trigger an external device (e.g. Controller) or switch on the connected circuitry by an external power management unit depending on activities on the RF interface. WDT_MS 7 6 5 4 WDT_MS READ R&W - see configuration bytes description 3 2 1 0 I2C_CLOCK_STR 7 6 5 4 READ READ - Locked to 0b 3 2 1 0 I2C_CLOCK_STR READ READ See configuration bytes description NS_REG 7 NDEF_DATA_READ READ READ 0b 1b… all data bytes read from the address specified in LAST_NDEF_BLOCK. value is reset to 0b when read 6 I2C_LOCKED READ R&W 0b 1b… Memory access is locked to the I²C interface 5 RF_LOCKED READ READ 0b 1b… Memory access is locked to the RF interface 4 SRAM_I2C_READY READ READ 0b 1b… data is ready in SRAM buffer to be read by I2C 3 SRAM_RF_READY READ READ 0b 1b… data is ready in SRAM buffer to be read by RF 2 EEPROM_WR_ERR READ R&W 0b 1b… HV voltage error during EEPROM write or erase cycle via I²C needs to be written back to "0b" to be cleared 1 EEPROM_WR_BUSY READ READ 0b 1b… EEPROM write cycle in progress - access to EEPROM disabled 0b… EEPROM access possible 0 RF_FIELD_PRESENT READ READ 0b 1b… RF field is detected Table 10. …continuedSession register bytes Bit Field Access via RF Access via I²C Default values DescriptionNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 25 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface The conditions for the activation of the field detection signal (FD_ON) can be: • The presence of the RF field • The detection of a valid command (Start-of-Frame) • The selection of the IC. The conditions for the de-activation of the field detection signal (FD_OFF) can be: • The absence of the RF field • The detection of the HALT state • The RF interface has read the last part of the NDEF message defined with LAST_NDEF_MESSAGE All the various combinations of configurations are described in Table 9 and illustrated in Figure 15, Figure 16 and Figure 17 for all various combination of the filed detection signal configuration. The field detection pin can also be used as a handshake mechanism in the Pass-through mode to signal to the external microcontroller if • New data are written to SRAM on the RF interface • Data written to SRAM from the microcontroller are read via the RF interface. See Section 11 for more information on this handshake mechanism.NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 26 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Fig 15. Illustration of the field detection feature when configured for simple field detection aaa-012808 I 2C RF NDEF_DATA_READ I2C_LOCKED RF_LOCKED SRAM_I2C_READY SRAM_RF_READY EEPROM_WR_ERR EEPROM_WR_BUSY RF_FIELD_PRESENT 0b 1b 1b 0b I2C_RST_ON_OFF PTHRU_ON_OFF SRAM_MIRROR_ON_OFF PTHRU_DIR RF field switches ON RF field switches OFF RF field FD pin EVENT ON OFF HIGH LOW REGISTERS NS_REG NC_REG FD_ON FD_OFF 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 1b 1b 0b 0b 0b 0b 0b 0b 0b 0b 0bNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 27 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Fig 16. Illustration of the field detection feature when configured for First valid state of Frame detection aaa-012809 I 2C RF NDEF_DATA_READ I2C_LOCKED RF_LOCKED SRAM_I2C_READY SRAM_RF_READY EEPROM_WR_ERR EEPROM_WR_BUSY RF_FIELD_PRESENT 0b 1b 1b 0b I2C_RST_ON_OFF PTHRU_ON_OFF SRAM_MIRROR_ON_OFF PTHRU_DIR RF field ON OFF FD pin HIGH LOW EVENT First valid State-ofFrame RF field switches OFF or tag set to the HALT state REGISTERS NS_REG 0b 0b 0b 0b 0b 0b 0b 0b 1b 0b 0b 0b 0b 0b 0b 0b NC_REG 0b 0b 0b 0b FD_ON 0b 0b 1b 1b 1b FD_OFF 0b 0b 1b 1b 0bNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 28 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 8.5 Watchdog timer In order to allow the I²C interface to perform all necessary commands (READ, WRITE...), the memory access remains locked to the I²C interface til the register I2C_LOCKED is cleared by the host - see Table 10. In order however to avoid that the memory stays 'locked' to the I²C for a long period of time, it is possible to program a watchdog timer to unlock the I2C host from the tag, so that the RF reader can access the tag after a period of time of inactivity. The host itself will not be notified of this event directly, but the NS_REG register is updated accordingly (the register bit I2C_LOCKED will be cleared - see Table 10). The default value is set to 20 ms (848h), but the watch dog timer can be freely set from 0001h (9.43 s) up to FFFFh (617.995 s). The timer starts ticking when the communication between the NTAG I2C and the I2C interface starts. In case the Fig 17. Illustration of the field detection feature when configured for selection of the tag detection aaa-012810 I 2C RF NDEF_DATA_READ I2C_LOCKED RF_LOCKED SRAM_I2C_READY SRAM_RF_READY EEPROM_WR_ERR EEPROM_WR_BUSY RF_FIELD_PRESENT 0b 1b 1b 0b I2C_RST_ON_OFF PTHRU_ON_OFF 1b 1b 1b 1b 1b 1b 1b 1b SRAM_MIRROR_ON_OFF PTHRU_DIR 1b 1b 1b 1b RF field ON OFF FD pin HIGH LOW EVENT Selection of the tag RF field switches OFF or RF read the last 4 bytes of the NDEF message defined in LAST_NDEF_MESSAGE REGISTERS NS_REG 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b NC_REG 0b 0b 0b 0b FD_ON 0b 0b 0b 0b FD_OFF 0b 0bNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 29 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface communication with the I2C is still going on after the watchdog timer expires, the communication will continue until the communication has completed. Then the status register I2C_LOCKED will be immediately cleared. In the case where the communication with the I2C interface has completed before the end of the timer and the status register I2C_LOCKED was not cleared by the host, it will be cleared at the end of the watchdog timer. The watchdog timer is only effective if the VCC pin is powered and will be reset and stopped if the NTAG I2C is not VCC powered or if the register status I2C_LOCKED is set to 0 and RF_LOCKED is set to 1. 8.6 Energy harvesting The NTAG I2C provides the capability to supply external low power devices with energy generated from the RF field of a NFC device. The voltage and current from the energy harvesting depend on various parameters, such as the strength of the RF field, the tag antenna size, or the distance from the NFC device. At room temperature, NTAG I2C could provide typically 5 mA at 2 V on the VOUT pin with an NFC Phone. Operating NTAG I2C in energy harvesting mode requires a number of precautions: • A significant buffer capacitor in the range of typically 10nF up to 100 nF maximum shall be connected between VOUT and GND close to the terminals. • If NTAG I2C also powers the I2C bus, then VCC must be connected to VOUT, and pull-up resistors on the SCL and SDA pins must be sized to control SCL and SDA sink current when those lines are pulled low by NTAG I2C or the I2C host • If NTAG I2C also powers the Field Detect bus, then the pull-up resistor on the Field Detect line must be sized to control the sink current into the Field Detect pin when NTAG I2C pulls it low • The NFC reader device communicating with NTAG I2C shall apply polling cycles including an RF Field Off condition of at least 5.1 ms as defined in NFC Forum Activity specification (see Ref. 4, chapter 6). Note that increasing the output current on the Vout decreases the RF communication range.NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 30 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 9. I²C commands For details about I2C interface refer to Ref. 3. The NTAG I2C supports the I2C protocol. This protocol is summarized in Figure 18. Any device that sends data onto the bus is defined as a transmitter, and any device that reads the data from the bus is defined as a receiver. The device that controls the data transfer is known as the “bus master”, and the other as the “slave” device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The NTAG I2C is always a slave in all communications. 9.1 Start condition Start is identified by a falling edge of Serial Data (SDA), while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer command. The NTAG I 2C continuously monitors SDA (except during a Write cycle) and SCL for a Start condition, and will not respond unless one is given. 9.2 Stop condition Stop is identified by a rising edge of SDA while SCL is stable and driven high. A Stop condition terminates communication between the NTAG I2C and the bus master. A Stop condition at the end of a Write command triggers the internal Write cycle. Fig 18. I2C bus protocol SCL SDA SCL 1 2 3 7 8 9 1 2 3 7 8 9 MSB ACK MSB ACK Start Condition SDA Input SDA Change Stop Condition Stop Condition Start Condition SDA SCL SDA 001aao231NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 31 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 9.3 Soft reset feature In the case where the I2C interface is constantly powered on, NTAG I2C can trigger a reset of the I2C interface via its soft reset feature- see Table 9. When this feature is enabled, if the microcontroller does not issue a stop condition between two start conditions, this situation will trigger a reset of the I2C interface and hence may hamper the communication via the I2C interface. 9.4 Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it is the bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits. 9.5 Data input During data input, the NTAG I2C samples SDA on the rising edge of SCL. For correct device operation, SDA must be stable during the rising edge of SCL, and the SDA signal must change only when SCL is driven low. 9.6 Addressing To start communication between a bus master and the NTAG I2C slave device, the bus master must initiate a Start condition. Following this initiation, the bus master sends the device address. The NTAG I2C address from I2C consists of a 7-bit device identifier (see Table 11 for default value). The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the device address, the NTAG I2C gives an acknowledgment on SDA during the 9th bit time. If the NTAG I2C does not match the device select code, it deselects itself from the bus and clear the register I2C_LOCKED (see Table 8). [1] Initial values - can be changed. The I2C address of the NTAG I2C (byte 0 - block 0h) can only be modified by the I2C interface. Both interfaces have no READ access to this address and a READ command from the RF or I²C interface to this byte will only return 04h (manufacturer ID for NXP Semiconductors - see Figure 9). Table 11. Default NTAG I2C address from I2C Device address R/W b7 b6 b5 b4 b3 b2 b1 b0 Value 1[1] 0[1] 1[1] 0[1] 1 [1] 0 [1] 1 [1] 1/0xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. COMPANY PUBLIC Product data sheet Rev. 3.1 — 9 October 2014 265431 32 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 9.7 READ and WRITE Operation Fig 19. I2C READ and WRITE operation aaa-012811 Host 7 bits SA and ‘0’ Tag Tag Start Stop Stop D0 D1 D0 D1 D15 MEMA D15 A A A A A A A A A Host Start 7 bits SA and ‘0’ Write: Read: MEMA Stop Start 7 bits SA and ‘1’ A ANT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 33 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface The READ and WRITE operation handle always 16 bytes to be read or written (one block - see Figure 8) For the READ operation (see Figure 19), following a Start condition, the bus master/host sends the NTAG I2C slave address code (SA - 7 bits) with the Read/Write bit (RW) reset to 0. The NTAG I2C acknowledges this (A), and waits for one address byte (MEMA), which should correspond to the address of the block of memory (SRAM or EEPROM) that is intended to be read. The NTAG I2C responds to a valid address byte with an acknowledge (A). A Stop condition can be then issued. Then the host again issues a start condition followed by the NTAG I2C slave address with the Read/Write bit set to “1”. The NTAG I2C acknowledges this (A) and sends the first byte of data read (D0).The bus master/host acknowledges it (A) and the NTAG I2C will subsequently transmit the following 15 bytes of memory read with an acknowledge from the host after every byte. After the last byte of memory data has been transmitted by the NTAG I2C, the bus master/host will acknowledge it and issue a Stop condition. For the WRITE operation (see Figure 19), following a Start condition, the bus master/host sends the NTAG I2C slave address code (SA - 7 bits) with the Read/Write bit (RW) reset to 0. The NTAG I2C acknowledges this (A), and waits for one address byte (MEMA), which should correspond to the address of the block of memory (SRAM or EEPROM) that is intended to be written. The NTAG I2C responds to a valid address byte with an acknowledge (A) and, in the case of a WRITE operation, the bus master/host starts transmitting each 16 bytes (D0...D15) that shall be written at the specified address with an acknowledge of the NTAG I²C after each byte (A). After the last byte acknowledge from the NTAG I²C, the bus master/host issues a Stop condition. The memory address accessible via the READ and WRITE operations can only correspond to the EEPROM or SRAM (respectively 00h to 3Ah or F8h to FBh for NTAG I²C 1k and 00h to 7Ah or F8h to FBh for NTAG I²C 2k).xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. COMPANY PUBLIC Product data sheet Rev. 3.1 — 9 October 2014 265431 34 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 9.8 WRITE and READ register operation In order to modify or read the session register bytes (see Table 10), NTAG I²C requires the WRITE and READ register operation (see Figure 20). Fig 20. WRITE and READ register operation aaa-012812 Host 7 bits SA and ‘0’ Tag Tag Start Stop MEMA REGA A A A Host Start 7 bits SA and ‘0’ A Write: Read: Stop Start 7 bits SA and ‘1’ Stop MEMA MASK REGDAT REGDAT A REGA A A A A ANT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 35 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface For the READ register operation, following a Start condition the bus master/host sends the NTAG I²C slave address code (SA - 7 bits) with the Read/Write bit (RW) reset to 0. The NTAG I2C acknowledges this (A), and waits for one address byte (MEMA) which corresponds to the address of the block of memory with the session register bytes (FEh). The NTAG I2C responds to the address byte with an acknowledge (A). Then the bus master/host issues a register address (REGA), which corresponds to the address of the targeted byte inside the block FEh (00h, 01h...to 07h) and then waits for the Stop condition. Then the bus master/host again issues a start condition followed by the NTAG I²C slave address with the Read/Write bit set to “1”. The NTAG I²C acknowledges this (A), and sends the selected byte of session register data (REGDAT) within the block FEh. The bus master/host will acknowledge it and issue a Stop condition. For the WRITE register operation, following a Start condition, the bus master/host sends the NTAG I²C slave address code (SA - 7 bits) with the Read/Write bit (RW) reset to 0. The NTAG I2C acknowledges this (A), and waits for one address byte (MEMA), which corresponds to the address of the block of memory within the session register bytes (FEh). After the NTAG I2C acknowledge (A), the bus master/host issues a MASK byte that defines exactly which bits shall be modified by a “1” bit value at the corresponding bit position. Following the NTAG I²C acknowledge (A), the new register data (one byte - REGDAT) to be written is transmitted by the bus master/host. The NTAG I²C acknowledges it (A), and the bus master/host issues a stop condition.NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 36 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 10. RF Command NTAG activation follows the ISO/IEC 14443 Type A specification. After NTAG I2C has been selected, it can either be deactivated using the ISO/IEC 14443 HALT command, or NTAG commands (e.g., READ or WRITE) can be performed. For more details about the card activation refer to Ref. 2. 10.1 NTAG I2C command overview All available commands for NTAG I2C are shown in Table 12. [1] Unless otherwise specified, all commands use the coding and framing as described in Ref. 1. 10.2 Timing The command and response timing shown in this document are not to scale and values are rounded to 1 s. All given command and response times refer to the data frames, including start of communication and end of communication. They do not include the encoding (like the Miller pulses). An NFC device data frame contains the start of communication (1 “start bit”) and the end of communication (one logic 0 + 1 bit length of unmodulated carrier). An NFC tag data frame contains the start of communication (1 “start bit”) and the end of communication (1 bit length of no subcarrier). The minimum command response time is specified according to Ref. 1 as an integer n, which specifies the NFC device to NFC tag frame delay time. The frame delay time from NFC tag to NFC device is at least 87 s. The maximum command response time is specified as a time-out value. Depending on the command, the TACK value specified for command responses defines the NFC device to NFC tag frame delay time. It does it for either the 4-bit ACK value specified or for a data frame. All timing can be measured according to the ISO/IEC 14443-3 frame specification as shown for the Frame Delay Time in Figure 21. For more details refer to Ref. 2. Table 12. Command overview Command[1] ISO/IEC 14443 NFC FORUM Command code (hexadecimal) Request REQA SENS_REQ 26h (7 bit) Wake-up WUPA ALL_REQ 52h (7 bit) Anticollision CL1 Anticollision CL1 SDD_REQ CL1 93h 20h Select CL1 Select CL1 SEL_REQ CL1 93h 70h Anticollision CL2 Anticollision CL2 SDD_REQ CL2 95h 20h Select CL2 Select CL2 SEL_REQ CL2 95h 70h Halt HLTA SLP_REQ 50h 00h GET_VERSION - - 60h READ - READ 30h FAST_READ - - 3Ah WRITE - WRITE A2h SECTOR_SELECT SECTOR_SELECT C2hNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 37 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Remark: Due to the coding of commands, the measured timings usually excludes (a part of) the end of communication. Consider this factor when comparing the specified with the measured times. 10.3 NTAG ACK and NAK NTAG uses a 4 bit ACK / NAK as shown in Table 13. 10.4 ATQA and SAK responses NTAG I2C replies to a REQA or WUPA command with the ATQA value shown in Table 14. It replies to a Select CL2 command with the SAK value shown in Table 15. The 2-byte ATQA value is transmitted with the least significant byte first (44h). Fig 21. Frame Delay Time (from NFC device to NFC tag), TACK and TNAK last data bit transmitted by the NFC device FDT = (n* 128 + 84)/fc first modulation of the NFC TAG FDT = (n* 128 + 20)/fc aaa-006986 128/fc logic „1“ 128/fc logic „0“ 256/fc end of communication (E) 256/fc end of communication (E) 128/fc start of communication (S) communication (S) 128/fc start of Table 13. ACK and NAK values Code (4-bit) ACK/NAK Ah Acknowledge (ACK) 0h NAK for invalid argument (i.e. invalid page address) 1h NAK for parity or CRC error 3h NAK for Arbiter locked to I²C 7h NAK for EEPROM write error Table 14. ATQA response of the NTAG I2C Bit number Sales type Hex value 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 NTAG I2C 00 44h 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 Table 15. SAK response of the NTAG I2C Bit number Sales type Hex value 8 7 6 5 4 3 2 1 NTAG I2C 00h 00000000NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 38 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Remark: The ATQA coding in bits 7 and 8 indicate the UID size according to ISO/IEC 14443 independent from the settings of the UID usage. Remark: The bit numbering in the ISO/IEC 14443 specification starts with LSB = bit 1 and not with LSB = bit 0. So 1 byte counts bit 1 to bit 8 instead of bit 0 to 7. 10.5 GET_VERSION The GET_VERSION command is used to retrieve information about the NTAG family, the product version, storage size and other product data required to identify the specific NTAG I 2C. This command is also available on other NTAG products to have a common way of identifying products across platforms and evolution steps. The GET_VERSION command has no arguments and returns the version information for the specific NTAG I2C type. The command structure is shown in Figure 22 and Table 16. Table 17 shows the required timing. [1] Refer to Section 10.2 “Timing”. Fig 22. GET_VERSION command Table 16. GET_VERSION command Name Code Description Length Cmd 60h Get product version 1 byte CRC - CRC according to Ref. 1 2 bytes Data - Product version information 8 bytes NAK see Table 13 see Section 10.3 4-bit Table 17. GET_VERSION timing These times exclude the end of communication of the NFC device. TACK/NAK min TACK/NAK max TTimeOut GET_VERSION n=9[1] TTimeOut 5 ms CRC CRC NFC device Cmd NTAG ,,ACK'' Data 283 µs 868 µs NTAG ,,NAK'' NAK Time out TTimeOut TNAK TACK 57 µs aaa-006987NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 39 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface The most significant 7 bits of the storage size byte are interpreted as an unsigned integer value n. As a result, it codes the total available user memory size as 2n. If the least significant bit is 0b, the user memory size is exactly 2n. If the least significant bit is 1b, the user memory size is between 2n and 2n+1. The user memory for NTAG I²C 1k is 888 bytes. This memory size is between 512 bytes and 1024 bytes. Therefore, the most significant 7 bits of the value 13h, are interpreted as 9d, and the least significant bit is 1b. The user memory for NTAG I²C 2k is 1904 bytes. This memory size is between 1024 bytes and 2048 bytes. Therefore, the most significant 7 bits of the value 15h, are interpreted as 10d, and the least significant bit is 1b. 10.6 READ The READ command requires a start page address, and returns the 16 bytes of four NTAG I2C pages. For example, if address (Addr) is 03h then pages 03h, 04h, 05h, 06h are returned. Special conditions apply if the READ command address is near the end of the accessible memory area. For details on those cases and the command structure refer to Figure 23 and Table 19. Table 20 shows the required timing. Table 18. GET_VERSION response for NTAG I²C 1k and 2k Byte no. Description NTAG I²C 1k NTAG I²C 2k Interpretation 0 fixed Header 00h 00h 1 vendor ID 04h 04h NXP Semiconductors 2 product type 04h 04h NTAG 3 product subtype 05h 05h 50 pF I2C, Field detection 4 major product version 02h 02h 2 5 minor product version 01h 01h V1 6 storage size 13h 15h see following information 7 protocol type 03h 03h ISO/IEC 14443-3 compliant Fig 23. READ command CRC CRC NFC device Cmd Addr Data NTAG ,,ACK'' 368 µs 1548 µs NTAG ,,NAK'' NAK Time out TTimeOut TNAK TACK 57 µs aaa-006988NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 40 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface [1] Refer to Section 10.2 “Timing”. In the initial state of NTAG I2C, all memory pages are allowed as Addr parameter to the READ command: • Page address from 00h to E2h and E8h for NTAG I²C 1k • Page address from 00h to FFh (sector 0h), from page 00h to E0h and E8h (sector 1h) for NTAG I²C 2k • SRAM buffer when Passthrough is ON Addressing a start memory page beyond the limits above results in a NAK response from NTAG I2C. In case a READ command addressing start with a valid memory area but extends over an invalid memory area, the content of the invalid memory area will be reported as 00h. 10.7 FAST_READ The FAST_READ command requires a start page address and an end page address and returns all n*4 bytes of the addressed pages. For example, if the start address is 03h and the end address is 07h, then pages 03h, 04h, 05h, 06h and 07h are returned. For details on those cases and the command structure, refer to Figure 24 and Table 21. Table 22 shows the required timing. Table 19. READ command Name Code Description Length Cmd 30h read four pages 1 byte Addr - start page address 1 byte CRC - CRC according to Ref. 1 2 bytes Data - Data content of the addressed pages 16 bytes NAK see Table 13 see Section 10.3 4-bit Table 20. READ timing These times exclude the end of communication of the NFC device. TACK/NAK min TACK/NAK max TTimeOut READ n=9[1] TTimeOut 5 msNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 41 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface [1] Refer to Section 10.2 “Timing”. In the initial state of NTAG I2C, all memory pages are allowed as StartAddr parameter to the FAST_READ command: • Page address from 00h to E2h and E8h for NTAG I²C 1k • Page address from 00h to FFh (sector 0h), from page 00h to E0h and E8h (sector 1h) for NTAG I²C 2k • SRAM buffer when Passthrough mode s ON If the start addressed memory page (StartAddr) is outside of accessible area, NTAG I2C replies a NAK. In case the FAST_READ command starts with a valid memory area but extends over an invalid memory area, the content of the invalid memory area will be reported as 00h. The EndAddr parameter must be equal to or higher than the StartAddr. Remark: The FAST_READ command is able to read out the entire memory of one sector with one command. Nevertheless, the receive buffer of the NFC device must be able to handle the requested amount of data as no chaining is possible. Fig 24. FAST_READ command Table 21. FAST_READ command Name Code Description Length Cmd 3Ah read multiple pages 1 byte StartAddr - start page address 1 byte EndAddr - end page address 1 byte CRC - CRC according to Ref. 1 2 bytes Data - data content of the addressed pages n*4 bytes NAK see Table 13 see Section 10.3 4-bit Table 22. FAST_READ timing These times exclude the end of communication of the NFC device. TACK/NAK min TACK/NAK max TTimeOut FAST_READ n=9[1] TTimeOut 5 ms CRC CRC NFC device Cmd StartAddr NTAG ,,ACK'' Data 453 µs depending on nr of read pages NTAG ,,NAK'' NAK Time out TTimeOut TNAK TACK 57 µs EndAddr aaa-006989NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 42 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 10.8 WRITE The WRITE command requires a block address, and writes 4 bytes of data into the addressed NTAG I2C page. The WRITE command is shown in Figure 25 and Table 23. Table 24 shows the required timing. [1] Refer to Section 10.2 “Timing”. In the initial state of NTAG I2C, the following memory pages are valid Addr parameters to the WRITE command: • Page address from 02h to E2h, E8h and E9h (sector 0h) for NTAG I²C 1k • Page address from 02h to FFh (sector 0h), from 00h to E2h, E8h and E9h (sector 1h) for NTAG I²C 2k • SRAM buffer address in Passthrough mode Addressing a memory page beyond the limits above results in a NAK response from NTAG I2C. Pages that are locked against writing cannot be reprogrammed using any write command. The locking mechanisms include static and dynamic lock bits, as well as the locking of the configuration pages. Fig 25. WRITE command Table 23. WRITE command Name Code Description Length Cmd A2h write one page 1 byte Addr - page address 1 byte CRC - CRC according to Ref. 1 2 bytes Data - data 4 bytes NAK see Table 13 see Section 10.3 4-bit Table 24. WRITE timing These times exclude the end of communication of the NFC device. TACK/NAK min TACK/NAK max TTimeOut WRITE n=9[1] TTimeOut 10 ms NFC device Cmd Addr CRC NTAG ,,ACK'' 708 µs NTAG ,,NAK'' NAK Time out TTimeOut TNAK TACK 57 µs ACK 57 µs Data aaa-006990NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 43 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 10.9 SECTOR SELECT The SECTOR SELECT command consists of two commands packet: the first one is the SECTOR SELECT command (C2h), FFh and CRC. Upon an ACK answer from the Tag, the second command packet needs to be issued with the related sector address to be accessed and 3 bytes RFU. To successfully access to the requested memory sector, the tag shall issue a passive ACK, which is sending NO REPLY for more than 1ms after the CRC of the second command set. The SECTOR SELECT command is shown in Figure 26 and Table 25. Table 26 shows the required timing. Fig 26. SECTOR_SELECT command Table 25. SECTOR_SELECT command Name Code Description Length Cmd C2h sector select 1 byte FFh - 1 byte CRC - CRC according to Ref. 1 2 bytes SecNo - Memory sector to be selected (00h-FEh) 1 byte NAK see Table 13 see Section 10.3 4-bit aaa-014051 NFC device Cmd FFh CRC SecNo 00h 00h 00h CRC 708 µs NTAG I2C ,,NAK'' NTAG I2C ,,ACK'' NTAG I2C ,,NAK'' NTAG I2C ,,ACK'' NAK Time out NFC device TTimeOut TNAK TACK 57 µs ACK 57 µs NAK <1ms >1ms 57 µs Passive ACK SECTOR SELECT packet 2 SECTOR SELECT packet 1 (any reply) (no reply)NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 44 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface [1] Refer to Section 10.2 “Timing”. Table 26. SECTOR_SELECT timing These times exclude the end of communication of the NFC device. TACK/NAK min TACK/NAK max TTimeOut SECTOR SELECT n=9[1] TTimeOut 10 msNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 45 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 11. Communication and arbitration between RF and I²C interface If both interfaces are powered by their corresponding source, only one interface shall have access according to the "first-come, first-serve" principle. In NS_REG, the two status bits I2C_LOCKED and RF_LOCKED reflect the status of the NTAG I²C memory access and indicate which interface is locking the memory access. At power on, both bits are 0, setting the arbitration in idle mode. In the case arbiter locks to the I²C interface, an RF reader still can access the session registers. If the ISO state machine is in 'active' state, only the SECTOR SELECT command is allowed. But any other command requiring EEPROM access like READ or WRITE is handled as an illegal command and replied to with a special NAK value. In the case where the memory access is locked to the RF interface, the I²C host still can access the NFC register, by issuing a 'Register READ/WRITE' command. All other read or write commands will be replied to with a NACK to the I²C host. 11.1 Non Pass-through Mode PTHRU_ON_OFF = 0 (see Table 10) indicates non-Pass-through mode. 11.1.1 I²C interface access If the tag is in the IDLE or HALT state (RF state after POR or HALT-command) and the correct I²C slave address of NTAG I²C is specified following the START condition, bit I2C_LOCKED will be automatically set to “1b”. If I2C_LOCKED=,1 the I²C interface has access to the tag memory and the tag will respond with a NACK to any memory READ/WRITE command on the RF interface other than reading the register bytes command during this time. I2C_LOCKED must be either reset to 0 at the end of the I²C sequence or wait until the end of the watch dog timer. 11.1.2 RF interface access The arbitration will allow the RF interface to read and write accesses to EEPROM only when I2C_LOCKED is not set to “1b”. RF_LOCKED is automatically set to “1b” if the tag receives a valid command (EEPROM Access Commands) on the RF interface. If RF_LOCKED=1, the tag is locked to the RF interface and will not respond to any command from the I²C interface other than READ register command (see Table 10). RF_LOCKED is automatically set to 0 in one of the following conditions • At POR or if the RF field is switched off • If the tag is set to the HALT state with a HALT command on the RF interface • If the memory access command is finished on the RF interface When the RF interface has read the last page of the NDEF message specified in LAST_NDEF_BLOCK (see Table 9 and Table 10) the bit NDEF_DATA_READ - in the register NS_REG see Table 10 - is set to “1b” and indicates to the I²C interface that, for example, new NDEF data can be written. NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 46 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 11.2 SRAM buffer mapping with Memory Mirror enabled With SRAM_MIRROR_ON_OFF= 1, the SRAM buffer mirroring is enabled. This mode cannot be combined with the pass through mode (see Section 11.3). With the Memory Mirror enabled, the SRAM is now mapped into the User Memory from the RF interface perspective using the SRAM mirror lower page address specified in SRAM_MIRROR_BLOCK byte (Table 9 and Table 10). See Figure 27 (NTAG I²C 1k) and Figure 28(NTAG I²C 2k) for an illustration of this SRAM memory mapping when SRAM_MIRROR_BLOCK is set to 1h. The SRAM buffer will be then available in 2 locations: inside the User memory and at the end of the first or second memory sector (respectively NTAG I²C 1k or NTAG I²C 2k). The tag must be VCC powered to make this mode work, because without VCC, the SRAM will not be accessible via RF powered only. When mapping the SRAM buffer to the User Memory, the User shall be aware that all data written into the SRAM part of the User memory will be lost once the NTAG I²C is no longer powered from the I²C side (as SRAM is a volatile memory).NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 47 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Fig 27. Illustration of the SRAM memory addressing via the RF interface (with Memory mirror enabled and SRAM_MIRROR_BLOCK set to 1h) for the NTAG I²C 1k aaa-012813 Sector adr. Hex. Dec. Hex. 0 1 2 3 conditions Page address 0h 0 0h 1h ...... 1 1h 2 2h 3 3h 4 4h 19 13h 225 E1h 226 E2h 227 E3h 228 E4h 229 E5h 230 E6h 231 E7h 232 E8h 233 E9h 234 EAh 255 FFh ...... ...... ...... ... Serial number Invalid access - returns NAK Serial number Internal data 00h Internal data Lock bytes Byte number within a page READ Capability Container (CC) READ READ READ/R&W n.a. Dynamic lock bytes R&W/R 2h ...... Invalid access - returns NAK n.a. 3h 0 0h Invalid access - returns NAK n.a. Invalid access - returns NAK n.a. Invalid access - returns NAK n.a. User memory SRAM memory (16 pages) with memory mirror mode enabled only with SRAM_MIRROR_BLOCK set to 1h READ&WRITE 249 F9H 248 F8H Session registers See section 8.5.9 Configuration See section 8.5.9 255 FFH ...... Invalid access - returns NAK n.a. AccessNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 48 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 11.3 Pass-through mode PTHRU_ON_OFF = 1 (see Table 10) enables and indicates Pass-through mode. To handle large amount of data transfer from one interface to the other, NTAG I²C offers the Pass-through mode where data is transferred via a 64 byte SRAM buffer. This buffer offers fast write access and unlimited WRITE endurance as well as an easy handshake mechanism between the 2 interfaces. Fig 28. Illustration of the SRAM memory addressing via the RF interface (with Memory mirror enabled and SRAM_MIRROR_BLOCK set to 1h) for the NTAG I²C 2k aaa-012814 Sector adr. Hex. Dec. Hex. 0 1 2 3 conditions Page address 0h 0 0h 2h ...... 1 1h 1h 2 2h 3 3h 4 4h 19 13h 225 FFh 226 E2h 227 E3h 228 E4h 223 DFh 224 E0h 225 E1h 229 E5h 230 E6h 231 E7h 232 E8h 233 E9h 234 EAh 255 FFh ...... ...... ...... ...... ... Serial number Invalid access - returns NAK Serial number Internal data 00h Internal data Lock bytes Byte number within a page READ Capability Container (CC) READ READ READ/R&W n.a. Dynamic lock bytes R&W/R 3h 0 0h Invalid access - returns NAK n.a. Invalid access - returns NAK n.a. Invalid access - returns NAK n.a. User memory READ&WRITE 249 F9H 248 F8H Session registers See section 8.5.9 Configuration See section 8.5.9 255 FFH ...... Invalid access - returns NAK n.a. Access 0 0h 1 1h ...... ...... SRAM memory (16 pages) with memory mirror mode enabled only with SRAM_MIRROR_BLOCK set to 1hNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 49 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface This buffer is mapped directly at the end of the sector 0h (NTAG I²C 1k) or sector 1h (NTAG I²C 2k) of the memory (from the RF interface perspective). In both cases, the principle of access to the SRAM buffer via the RF and I²C interface is exactly the same (see Section 11.3.2 and Section 11.3.3). The data flow direction must be set with the PTHRU_DIR bit (see Table 10) within the current communication session with the session registers (in this case, it can only be set via the I²C interfaces) or for the configuration bits after POR (in this case both RF and I²C interface can set it). This pass through direction settings avoids locking the memory access during the data transfer from one interface to the SRAM buffer. The pass-through mode can only be enabled when both interfaces are ON and only via the I²C interface via the bit PTHRU_ON_OFF located in the session registers NC_REG (see Section 8.3.11). In case one interface powers off, the pass-through mode is disabled automatically. 11.3.1 SRAM buffer mapping In Pass-through mode, the SRAM is mirrored to pages F0h to FFh sector 0h for the NTAG I²C 1k - see Figure 29 - or sector 1h for the NTAG I²C 2k - see Figure 30 - outside the User memory. The last page/block of the SRAM buffer (page 16) is used as the terminator page. Once the terminator page/block in the respective interfaces is read/written, the control would be transferred to other interface (RF/I²C) - see Section 11.3.2 and Section 11.3.3 for more details. Accordingly, the application can align on the Reader & Host side to transfer 16/32/48/64 bytes of data in one pass through step by only using the last blocks/page of the SRAM buffer. When using FAST_READ to read the SRAM buffer from RF, the EndAddress input of the FAST_READ command has to be always set to FFh.NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 50 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Fig 29. Illustration of the SRAM memory addressing via the RF interface in Pass-through mode for the NTAG I²C 1k aaa-012815 Sector adr. Hex. Dec. Hex. 0 1 2 3 conditions Page address 0h 0 0h 1h ...... 1 1h 2 2h 3 3h 4 4h 15 0Fh 225 E1h 226 E2h 227 E3h 228 E4h 229 E5h 230 E6h 231 E7h 232 E8h 233 E9h 234 EAh ... 240 F0h 255 FFh ...... ...... ...... ... Serial number Invalid access - returns NAK Serial number Internal data 00h Internal data Lock bytes Byte number within a page READ Capability Container (CC) READ READ READ/R&W n.a. Dynamic lock bytes R&W/R 2h ...... Invalid access - returns NAK n.a. 3h 0 0h Invalid access - returns NAK n.a. SRAM memory (16 pages) in Pass Through mode only READ&WRITE Invalid access - returns NAK n.a. User memory READ&WRITE 249 F9H 248 F8H Session registers See section 8.5.9 Invalid access - returns NAK n.a. Configuration See section 8.5.9 255 FFH ...... Invalid access - returns NAK n.a. AccessNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 51 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 11.3.2 RF to I²C Data transfer If the RF interface is enabled (RF_LOCKED=1) and data is written to the terminator block/page of the SRAM via the RF interface, at the end of the WRITE command, bit SRAM_I2C_READY is set to 1 and bit RF_LOCKED is set to 0 automatically, and the NTAG I²C is locked to the I²C interface. Fig 30. Illustration of the SRAM memory addressing via the RF interface in Pass-through mode for the NTAG I²C 2k aaa-012816 Sector adr. Hex. Dec. Hex. 0 1 2 3 conditions Page address 0h 0 0h 2h ...... 1 1h 1h 2 2h 3 3h 4 4h 225 FFh 226 E2h 227 E3h 228 E4h 223 DFh 224 E0h 225 E1h 229 E5h 230 E6h 231 E7h 232 E8h 233 E9h 234 EAh 235 EBh 236 ECh 237 EDh 238 EEh 239 EFh 240 F0h 255 FFh ...... ...... ...... Serial number Invalid access - returns NAK Serial number Internal data 00h Internal data Lock bytes Byte number within a page READ Capability Container (CC) READ READ READ/R&W n.a. Dynamic lock bytes R&W/R 3h 0 0h Invalid access - returns NAK n.a. SRAM memory (16 pages) in Pass Through mode only READ&WRITE. Invalid access - returns NAK n.a. Invalid access - returns NAK n.a. User memory READ&WRITE 249 F9H 248 F8H Session registers See section 8.5.9 Configuration See section 8.5.9 255 FFH ...... Invalid access - returns NAK n.a. Access 0 0h 1 1h ...... ......NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 52 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface To signal to the host that data is ready to be read following mechanisms are in place: • The host polls/reads bit SRAM_I2C_READY from NS_REG (see Table 10) to know if data is ready in SRAM • A trigger on the "FD" pin indicates to the host that data is ready to be read from SRAM. This feature can be enabled by programming bits 5:2 (FD_OFF, FD_ON) of the NC_REG appropriately (see Table 9) This is illustrated in the Figure 31. If the tag is addressed with the correct I²C slave address, the I2C_LOCKED bit is automatically set to 1 (according to the interface arbitration). After a READ from the terminator page of the SRAM, bit SRAM_I2C_READY and bit I2C_LOCKED are automatically reset to 0, and the tag returns to the arbitration idle mode where, for example, further data from the RF interface can be transferred.xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. COMPANY PUBLIC Product data sheet Rev. 3.1 — 9 October 2014 265431 53 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Fig 31. Illustration of the Field detection feature in combination with the Pass Through mode for data transfer from RF to I²C aaa-012807 I 2C RF RF writing data to the SRAM buffer RF writing data to the SRAM buffer NDEF_DATA_READ 0b I2C_LOCKED 0b 0b RF_LOCKED 0b 1b SRAM_I2C_READY 0b 0b SRAM_RF_READY 0b EEPROM_WR_ERR 0b EEPROM_WR_BUSY 0b RF_FIELD_PRESENT 0b 1b 0b I2C_RST_ON_OFF PTHRU_ON_OFF SRAM_MIRROR_ON_OFF PTHRU_DIR ON OFF HIGH LOW NC_REGFD_ON FD_OFF Last 4 bytes of SRAM written by RF Last 4 bytes of SRAM written by RF RF field switches ON RF field FD pin EVENT RF field switches OFF 1b 0b 0b 0b REGISTERS NS_REG 0b 1b 1b 0b 1b Last 16 bytes of SRAM read by I2C Last 16 bytes of SRAM read by I2C 0b 0b 1b 0b 1b 0b 1b 0b 0b 0b 0b 0b 1b 0b 1b 0b 0b 1b 1b 0b 0b 0b 0b 1b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 1b 0b 1b Set data direction from RF to I2C + set FD for Switch ON Pass through modeNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 54 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 11.3.3 I²C to RF Data transfer If the I²C interface is enabled (I2C_LOCKED is 1) and data is written to the terminator page of the SRAM via the I²C interface, at the end of the WRITE command, bit SRAM_RF_READY is set to 1 and bit I2C_LOCKED is automatically reset to 0 to set the tag in the arbitration idle state. The RF_LOCKED bit is then automatically set to 1 (according to the interface arbitration). After a READ or FAST_READ command involving the terminator block/page of the SRAM, bit SRAM_RF_READY and bit RF_LOCKED are automatically reset to 0 allowing the I²C interface to further write data into the SRAM buffer. To signal to the host that further data is ready to be written, the following mechanisms are in place: • The RF interface polls/reads the bit SRAM_RF_READY from NS_REG (see Table 10) to know if new data has been written by the I²C interface in the SRAM • A trigger on the "FD" pin indicates to the host that data has been read from SRAM by the RF interface. This feature can be enabled by programming bits 5:2 (FD_OFF, FD_ON) of the NC_REG appropriately (see Table 9) The above mechanism is illustrated in the Figure 32.xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. COMPANY PUBLIC Product data sheet Rev. 3.1 — 9 October 2014 265431 55 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Fig 32. Illustration of the Field detection signal feature in combination with Pass-through mode for data transfer from I²C to RF aaa-012806 I 2C Switch ON Pass through mode I 2C writing data to the SRAM buffer I 2C writing data to the SRAM buffer RF NDEF_DATA_READ 0b 0b 0b I2C_LOCKED 0b 1b 0b 0b RF_LOCKED 0b 0b 0b 0b SRAM_I2C_READY 0b 0b 0b SRAM_RF_READY 0b 0b 0b 0b EEPROM_WR_ERR 0b 0b 0b EEPROM_WR_BUSY 0b 0b 0b RF_FIELD_PRESENT 0b 1b 0b I2C_RST_ON_OFF 0b 0b 0b PTHRU_ON_OFF 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b SRAM_MIRROR_ON_OFF 0b 0b 0b PTHRU_DIR 1b 0b 0b RF field switches OFF REGISTERS 16 bytes of SRAM read by RF 16 bytes of SRAM written by I2C 16 bytes of SRAM read by RF LOW HIGH ON OFF EVENT FD pin RF field NS_REG NC_REGFD_ON FD_OFF RF field switches ON 16 bytes of SRAM written by I2C 0b 0b 0b 0b 0b 0b 1b 1b 0b 0b 1b 1b 1b 1b 0b 0b 0b 1b 0b 1b 1b 1b 1b Set data direction from I 2C to RF + set FD for 1b 0b 1b 0b 0b 0b 0b 0b 0bNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 56 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 12. Limiting values Exceeding the limits of one or more values in reference may cause permanent damage to the device. Exposure to limiting values for extended periods may affect device reliability. [1] ANSI/ESDA/JEDEC JS-001; Human body model: C = 100 pF, R = 1.5 k. 13. Characteristics 13.1 Electrical characteristics [1] Stresses above one or more of the limiting values may cause permanent damage to the device. [2] These are stress ratings only. Operation of the device at these or any other conditions above those given in the Characteristics section of the specification is not implied. [3] Exposure to limiting values for extended periods may affect device reliability. Table 27. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Tstg storage temperature 55 +125 C Tamb ambient temperature 40 +85 C VESD electrostatic discharge voltage 2 - kV VFD Voltage on the FD pin - 3.6 V VSDA Voltage on the SDA line - 3.6 V VSCL Voltage on the SCL line - 3.6 V Table 28. Characteristics In accordance with the Absolute Maximum Rating System (IEC 60134).[1][2][3] Symbol Parameter Conditions Min Typ Max Unit Ci input capacitance LA - LB 44 50 56 pF fi input frequency - 13.56 - MHz Energy harvesting characteristics Vout voltage generated at the Vout pin - - 3.2 V I²C interface characteristics VCC supply voltage I²C on VCC input 1.8 3.6 V IDD supply current - 155 - A EEPROM characteristics tret retention time Tamb = 22 C 20 - - year Nendu(W) write endurance Tamb = 22 C 200000 - - cycleNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 57 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 14. Package outline Fig 33. Package outline SOT902-3 (XQFN8) Outline References version European projection Issue date IEC JEDEC JEITA SOT902-3 - - - - - - MO-255 sot902-3_po 11-08-16 11-08-18 Unit mm max nom min 0.5 0.05 0.00 1.65 1.60 1.55 1.65 1.60 1.55 0.6 0.5 0.1 0.05 A Dimensions Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. XQFN8: plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm SOT902-3 A1 b 0.25 0.20 0.15 DE ee1 L 0.45 0.40 0.35 v w 0.05 y y1 0.05 0 1 2 mm scale terminal 1 index area D B A E X C y1 C y terminal 1 index area 3 L e1 e v AC B w C 2 1 5 6 7 metal area not for soldering 8 4 e1 e b A1 A detail XNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 58 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 15. Abbreviations 16. References [1] NFC Forum Tag 2 Type Operation, Technical Specification - NFC Forum, 31.05.2011, Version 1.1 [2] ISO/IEC 14443 - International Organization for Standardization [3] I2C-bus specification and user manual (NXP standard UM10204.pdf / Rev. 03 - 19 June 2007) [4] NFC Forum Activity, Technical Specification V1.1 Table 29. Pin description Pin no. Symbol Description 1 LA Antenna connection LA 2 VSS GND 3 SCL Serial Clock I2C 4 FD Field detection 5 SDA Serial data I2C 6 VCC VCC in connection (external power supply) 7 Vout Voltage out (energy harvesting) 8 LB Antenna connection LB Table 30. Abbreviations Acronym Description POR Power On ResetNT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 59 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 17. Revision history Table 31. Revision history Document ID Release date Data sheet status Change notice Supersedes NT3H1101_1201 v. 3.1 20141009 Product data sheet - NT3H1101_1201 v. 3.0 Modifications: • Section 8.6 “Energy harvesting”: updated • Section 10.5 “GET_VERSION”: updated • Figure 31 and Figure 32: updated • Section 12 “Limiting values” and Section 13 “Characteristics”: remark removed NT3H1101_1201 v. 3.0 20140806 Product data sheet - NT3H1101_1201 v. 2.3 Modifications: • Section 8.6 “Energy harvesting” updated • Section 16 “References”: updated • Data sheet status changed to “Product data sheet” NT3H1101_1201 v. 2.3 20140708 Objective data sheet - NT3H1201_1101 v. 2.2 Modifications: • Figures updated • General update NT3H1101_1201 v. 2.2 20140306 Objective data sheet - NT3H1201_1101 v. 2.1 Modifications: • General updates NT3H1101_1201 v. 2.1 20131218 Objective data sheet - NT3H1201_1101 v. 2.0 Modifications: • Section 4 “Ordering information”: type number corrected NT3H1101_1201 v. 2.0 20131212 Objective data sheet NT3H1201 v. 1.4 Modifications: • Additional description for the Field detection functionality for Pass-through mode • General update NT3H1201 v. 1.4 20130802 Objective data sheet - NT3H1201 v. 1.3 Modifications: • Update for 1k memory version and RF commands NT3H1201 v. 1.3 20130613 Objective data sheet - Modifications: • Pinning package update NT3H1201 v. 1.0 NT3H1201 v. 1.0 20130425 Objective data sheet - -NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 60 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface 18. Legal information 18.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. NT3H1101/NT3H1201 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet COMPANY PUBLIC Rev. 3.1 — 9 October 2014 265431 61 of 62 NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 18.4 Licenses 18.5 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. MIFARE — is a trademark of NXP Semiconductors N.V. I 2C-bus — logo is a trademark of NXP Semiconductors N.V. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Purchase of NXP ICs with NFC technology Purchase of an NXP Semiconductors IC that complies with one of the Near Field Communication (NFC) standards ISO/IEC 18092 and ISO/IEC 21481 does not convey an implied license under any patent right infringed by implementation of any of those standards.NXP Semiconductors NT3H1101/NT3H1201 NFC Forum type 2 Tag compliant IC with I2C interface © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 October 2014 265431 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 RF interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.4 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.5 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.6 Key benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Functional description . . . . . . . . . . . . . . . . . . . 6 8.1 Block description . . . . . . . . . . . . . . . . . . . . . . . 6 8.2 RF interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.2.1 Data integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.2.2 RF communication principle . . . . . . . . . . . . . . . 7 8.2.2.1 IDLE state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8.2.2.2 READY 1 state . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.2.2.3 READY 2 state . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.2.2.4 ACTIVE state . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.2.2.5 HALT state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.3 Memory organization . . . . . . . . . . . . . . . . . . . . 8 8.3.1 Memory map from RF interface . . . . . . . . . . . . 9 8.3.2 Memory map from I²C interface . . . . . . . . . . . 10 8.3.3 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.3.4 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.3.5 UID/serial number. . . . . . . . . . . . . . . . . . . . . . 13 8.3.6 Static lock bytes . . . . . . . . . . . . . . . . . . . . . . . 13 8.3.7 Dynamic Lock Bytes . . . . . . . . . . . . . . . . . . . . 14 8.3.8 Capability Container (CC bytes) . . . . . . . . . . . 16 8.3.9 User Memory pages . . . . . . . . . . . . . . . . . . . . 17 8.3.10 Memory content at delivery . . . . . . . . . . . . . . 18 8.3.11 NTAG I2C configuration and session registers 18 8.4 Configurable Field Detection Pin . . . . . . . . . . 24 8.5 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 28 8.6 Energy harvesting. . . . . . . . . . . . . . . . . . . . . . 29 9 I²C commands . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.1 Start condition. . . . . . . . . . . . . . . . . . . . . . . . . 30 9.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.3 Soft reset feature . . . . . . . . . . . . . . . . . . . . . . 31 9.4 Acknowledge bit (ACK). . . . . . . . . . . . . . . . . . 31 9.5 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.6 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.7 READ and WRITE Operation. . . . . . . . . . . . . 32 9.8 WRITE and READ register operation . . . . . . 34 10 RF Command . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.1 NTAG I2C command overview . . . . . . . . . . . . 36 10.2 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.3 NTAG ACK and NAK . . . . . . . . . . . . . . . . . . 37 10.4 ATQA and SAK responses. . . . . . . . . . . . . . . 37 10.5 GET_VERSION . . . . . . . . . . . . . . . . . . . . . . . 38 10.6 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10.7 FAST_READ . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.8 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.9 SECTOR SELECT . . . . . . . . . . . . . . . . . . . . . 43 11 Communication and arbitration between RF and I²C interface . . . . . . . . . . . . . . . . . . . . 45 11.1 Non Pass-through Mode . . . . . . . . . . . . . . . . 45 11.1.1 I²C interface access . . . . . . . . . . . . . . . . . . . . 45 11.1.2 RF interface access . . . . . . . . . . . . . . . . . . . . 45 11.2 SRAM buffer mapping with Memory Mirror enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.3 Pass-through mode . . . . . . . . . . . . . . . . . . . . 48 11.3.1 SRAM buffer mapping . . . . . . . . . . . . . . . . . . 49 11.3.2 RF to I²C Data transfer . . . . . . . . . . . . . . . . . 51 11.3.3 I²C to RF Data transfer . . . . . . . . . . . . . . . . . 54 12 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 56 13 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 56 13.1 Electrical characteristics . . . . . . . . . . . . . . . . 56 14 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 57 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 58 16 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . 59 18 Legal information . . . . . . . . . . . . . . . . . . . . . . 60 18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 60 18.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 60 18.4 Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 18.5 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 61 19 Contact information . . . . . . . . . . . . . . . . . . . . 61 20 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 1. General description The LPC1769/68/67/66/65/64/63 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration. The LPC1768/67/66/65/64/63 operate at CPU frequencies of up to 100 MHz. The LPC1769 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching. The peripheral complement of the LPC1769/68/67/66/65/64/63 includes up to 512 kB of flash memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG interface, 8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers, SPI interface, 3 I2C-bus interfaces, 2-input plus 2-output I2S-bus interface, 8-channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, four general purpose timers, 6-output general purpose PWM, ultra-low power Real-Time Clock (RTC) with separate battery supply, and up to 70 general purpose I/O pins. The LPC1769/68/67/66/65/64/63 are pin-compatible to the 100-pin LPC236x ARM7-based microcontroller series. For additional documentation, see Section 19 “References”. 2. Features and benefits ARM Cortex-M3 processor, running at frequencies of up to 100 MHz (LPC1768/67/66/65/64/63) or of up to 120 MHz (LPC1769). A Memory Protection Unit (MPU) supporting eight regions is included. ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC). Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator enables high-speed 120 MHz operation with zero wait states. In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software. On-chip SRAM includes: 32/16 kB of SRAM on the CPU with local code/data bus for high-performance CPU access. LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN Rev. 9.5 — 24 June 2014 Product data sheetLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 2 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Two/one 16 kB SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as for general purpose CPU instruction and data storage. Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with SSP, I2S-bus, UART, Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers. Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, and the USB interface. This interconnect provides communication with no arbitration delays. Split APB bus allows high throughput with few stalls between the CPU and DMA. Serial interfaces: Ethernet MAC with RMII interface and dedicated DMA controller. (Not available on all parts, see Table 2.) USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions. (Not available on all parts, see Table 2.) Four UARTs with fractional baud rate generation, internal FIFO, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support, and one UART has IrDA support. CAN 2.0B controller with two channels. (Not available on all parts, see Table 2.) SPI controller with synchronous, serial, full duplex communication and programmable data length. Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller. Three enhanced I2C bus interfaces, one with an open-drain output supporting full I 2C specification and Fast mode plus with data rates of 1 Mbit/s, two with standard port pins. Enhancements include multiple address recognition and monitor mode. I 2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S-bus interface can be used with the GPDMA. The I2S-bus interface supports 3-wire and 4-wire data transmit and receive as well as master clock input/output. (Not available on all parts, see Table 2.) Other peripherals: 70 (100 pin package) General Purpose I/O (GPIO) pins with configurable pull-up/down resistors. All GPIOs support a new, configurable open-drain operating mode. The GPIO block is accessed through the AHB multilayer bus for fast access and located in memory such that it supports Cortex-M3 bit banding and use by the General Purpose DMA Controller. 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins, conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller. 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support. (Not available on all parts, see Table 2) Four general purpose timers/counters, with a total of eight capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests. One motor control PWM with support for three-phase motor control.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 3 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Quadrature encoder interface that can monitor one external quadrature encoder. One standard PWM/timer block with external count input. RTC with a separate power domain and dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers. WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock. ARM Cortex-M3 system tick timer, including an external clock input option. Repetitive interrupt timer provides programmable and repeating timed interrupts. Each peripheral has its own clock divider for further power savings. Standard JTAG test/debug interface for compatibility with existing tools. Serial Wire Debug and Serial Wire Trace Port options. Emulation trace module enables non-intrusive, high-speed real-time tracing of instruction execution. Integrated PMU (Power Management Unit) automatically adjusts internal regulators to minimize power consumption during Sleep, Deep sleep, Power-down, and Deep power-down modes. Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down. Single 3.3 V power supply (2.4 V to 3.6 V). Four external interrupt inputs configurable as edge/level sensitive. All pins on Port 0 and Port 2 can be used as edge sensitive interrupt sources. Non-maskable Interrupt (NMI) input. Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock, CPU clock, and the USB clock. The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in deep sleep, Power-down, and Deep power-down modes. Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt, CAN bus activity, Port 0/2 pin interrupt, and NMI). Brownout detect with separate threshold for interrupt and forced reset. Power-On Reset (POR). Crystal oscillator with an operating range of 1 MHz to 25 MHz. 4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock. PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator. USB PLL for added flexibility. Code Read Protection (CRP) with different security levels. Unique device serial number for identification purposes. Available as LQFP100 (14 mm 14 mm 1.4 mm), TFBGA1001 (9 mm 9 mm 0.7 mm), and WLCSP100 (5.074 5.074 0.6 mm) package. 1. LPC1768/65 only.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 4 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 3. Applications 4. Ordering information 4.1 Ordering options eMetering Alarm systems Lighting White goods Industrial networking Motor control Table 1. Ordering information Type number Package Name Description Version LPC1769FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1 LPC1768FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1 LPC1768FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1 LPC1768UK WLCSP100 wafer level chip-scale package; 100 balls; 5.074 5.074 0.6 mm - LPC1767FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1 LPC1766FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1 LPC1765FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1 LPC1765FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1 LPC1764FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1 LPC1763FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1 Table 2. Ordering options Type number Flash SRAM in kB Ethernet USB CAN I 2S DAC Maximum CPU operating frequency CPU AHB SRAM0 AHB SRAM1 Total LPC1769FBD100 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 120 MHz LPC1768FBD100 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz LPC1768FET100 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz LPC1768UK 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz LPC1767FBD100 512 kB 32 16 16 64 yes no no yes yes 100 MHz LPC1766FBD100 256 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz LPC1765FBD100 256 kB 32 16 16 64 no Device/Host/OTG 2 yes yes 100 MHz LPC1765FET100 256 kB 32 16 16 64 no Device/Host/OTG 2 yes yes 100 MHz LPC1764FBD100 128 kB 16 16 - 32 yes Device only 2 no no 100 MHz LPC1763FBD100 256 kB 32 16 16 64 no no no yes yes 100 MHzLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 5 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 5. Marking The LPC176x devices typically have the following top-side marking: LPC176xxxx xxxxxxx xxYYWWR[x] The last/second to last letter in the third line (field ‘R’) will identify the device revision. This data sheet covers the following revisions of the LPC176x: Field ‘YY’ states the year the device was manufactured. Field ‘WW’ states the week the device was manufactured during that year. Table 3. Device revision table Revision identifier (R) Revision description ‘-’ Initial device revision ‘A’ Second device revision ‘B’ Third device revisionLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 6 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 6. Block diagram (1) Not available on all parts. See Table 2. Fig 1. Block diagram SRAM 32/64 kB ARM CORTEX-M3 TEST/DEBUG INTERFACE EMULATION TRACE MODULE FLASH ACCELERATOR FLASH 512/256/128 kB DMA CONTROLLER ETHERNET CONTROLLER WITH DMA(1) USB HOST/ DEVICE/OTG CONTROLLER WITH DMA(1) I-code bus D-code bus system bus AHB TO APB BRIDGE 0 HIGH-SPEED GPIO AHB TO APB BRIDGE 1 CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS XTAL1 XTAL2 RESET clocks and controls JTAG interface debug port USB PHY SSP0 UART2/3 I2S(1) I2C2 RI TIMER TIMER2/3 EXTERNAL INTERRUPTS SYSTEM CONTROL MOTOR CONTROL PWM QUADRATURE ENCODER SSP1 UART0/1 CAN1/2(1) I2C0/1 SPI0 TIMER 0/1 WDT PWM1 12-bit ADC PIN CONNECT GPIO INTERRUPT CONTROL RTC BACKUP REGISTERS 32 kHz OSCILLATOR APB slave group 1 APB slave group 0 DAC(1) RTC POWER DOMAIN LPC1769/68/67/ 66/65/64/63 master master master 002aad944 slave slave slave slave slave ROM slave MULTILAYER AHB MATRIX P0 to P4 SDA2 SCL2 SCK0 SSEL0 MISO0 MOSI0 SCK1 SSEL1 MISO1 MOSI1 RXD2/3 TXD2/3 PHA, PHB INDEX EINT[3:0] AOUT MCOA[2:0] MCOB[2:0] MCI[2:0] MCABORT 4 × MAT2 2 × MAT3 2 × CAP2 2 × CAP3 3 × I2SRX 3 × I2STX TX_MCLK RX_MCLK RTCX1 RTCX2 VBAT PWM1[7:0] 2 × MAT0/1 2 × CAP0/1 RD1/2 TD1/2 SDA0/1 SCL0/1 AD0[7:0] SCK/SSEL MOSI/MISO 8 × UART1 RXD0/TXD0 P0, P2 PCAP1[1:0] RMII pins USB pins CLKOUT MPU = connected to DMALPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 7 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 7. Pinning information 7.1 Pinning Fig 2. Pin configuration LQFP100 package Fig 3. Pin configuration TFBGA100 package LPC176xFBD100 50 1 25 75 51 26 76 100 002aad945 002aaf723 LPC1768/65FET100 Transparent top view J G K H F E D C B A 13579 2 4 6 8 10 ball A1 index areaLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 8 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Fig 4. Pin configuration WLCSP100 package Transparent top view 1 A B C D E F G H J K 2 3 4 5 6 7 8 9 10 LPC1768UK bump A1 index area aaa-009522 Table 4. Pin allocation table TFBGA100 Pin Symbol Pin Symbol Pin Symbol Pin Symbol Row A 1 TDO/SWO 2 P0[3]/RXD0/AD0[6] 3 VDD(3V3) 4 P1[4]/ENET_TX_EN 5 P1[10]/ENET_RXD1 6 P1[16]/ENET_MDC 7 VDD(REG)(3V3) 8 P0[4]/I2SRX_CLK/ RD2/CAP2[0] 9 P0[7]/I2STX_CLK/ SCK1/MAT2[1] 10 P0[9]/I2STX_SDA/ MOSI1/MAT2[3] 11 - 12 - Row B 1 TMS/SWDIO 2 RTCK 3 VSS 4 P1[1]/ENET_TXD1 5 P1[9]/ENET_RXD0 6 P1[17]/ ENET_MDIO 7 VSS 8 P0[6]/I2SRX_SDA/ SSEL1/MAT2[0] 9 P2[0]/PWM1[1]/TXD1 10 P2[1]/PWM1[2]/RXD1 11 - 12 - Row C 1 TCK/SWDCLK 2 TRST 3 TDI 4 P0[2]/TXD0/AD0[7] 5 P1[8]/ENET_CRS 6 P1[15]/ ENET_REF_CLK 7 P4[28]/RX_MCLK/ MAT2[0]/TXD3 8 P0[8]/I2STX_WS/ MISO1/MAT2[2] 9 VSS 10 VDD(3V3) 11 - 12 - Row D 1 P0[24]/AD0[1]/ I2SRX_WS/CAP3[1] 2 P0[25]/AD0[2]/ I2SRX_SDA/TXD3 3 P0[26]/AD0[3]/ AOUT/RXD3 4 n.c. 5 P1[0]/ENET_TXD0 6 P1[14]/ENET_RX_ER 7 P0[5]/I2SRX_WS/ TD2/CAP2[1] 8 P2[2]/PWM1[3]/ CTS1/TRACEDATA[3] 9 P2[4]/PWM1[5]/ DSR1/TRACEDATA[1] 10 P2[5]/PWM1[6]/ DTR1/TRACEDATA[0] 11 - 12 - Row E 1 VSSA 2 VDDA 3 VREFP 4 n.c. 5 P0[23]/AD0[0]/ I2SRX_CLK/CAP3[0] 6 P4[29]/TX_MCLK/ MAT2[1]/RXD3 7 P2[3]/PWM1[4]/ DCD1/TRACEDATA[2] 8 P2[6]/PCAP1[0]/ RI1/TRACECLKLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 9 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 9 P2[7]/RD2/RTS1 10 P2[8]/TD2/TXD2 11 - 12 - Row F 1 VREFN 2 RTCX1 3 RESET 4 P1[31]/SCK1/ AD0[5] 5 P1[21]/MCABORT/ PWM1[3]/SSEL0 6 P0[18]/DCD1/ MOSI0/MOSI 7 P2[9]/USB_CONNECT/ RXD2 8 P0[16]/RXD1/ SSEL0/SSEL 9 P0[17]/CTS1/ MISO0/MISO 10 P0[15]/TXD1/ SCK0/SCK 11 - 12 - Row G 1 RTCX2 2 VBAT 3 XTAL2 4 P0[30]/USB_D 5 P1[25]/MCOA1/ MAT1[1] 6 P1[29]/MCOB2/ PCAP1[1]/MAT0[1] 7 VSS 8 P0[21]/RI1/RD1 9 P0[20]/DTR1/SCL1 10 P0[19]/DSR1/SDA1 11 - 12 - Row H 1 P1[30]/VBUS/ AD0[4] 2 XTAL1 3 P3[25]/MAT0[0]/ PWM1[2] 4 P1[18]/USB_UP_LED/ PWM1[1]/CAP1[0] 5 P1[24]/MCI2/ PWM1[5]/MOSI0 6 VDD(REG)(3V3) 7 P0[10]/TXD2/ SDA2/MAT3[0] 8 P2[11]/EINT1/ I2STX_CLK 9 VDD(3V3) 10 P0[22]/RTS1/TD1 11 - 12 - Table 4. Pin allocation table TFBGA100 …continued Pin Symbol Pin Symbol Pin Symbol Pin SymbolLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 10 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 7.2 Pin description Row J 1 P0[28]/SCL0/ USB_SCL 2 P0[27]/SDA0/ USB_SDA 3 P0[29]/USB_D+ 4 P1[19]/MCOA0/ USB_PPWR/ CAP1[1] 5 P1[22]/MCOB0/ USB_PWRD/ MAT1[0] 6 VSS 7 P1[28]/MCOA2/ PCAP1[0]/ MAT0[0] 8 P0[1]/TD1/RXD3/SCL1 9 P2[13]/EINT3/ I2STX_SDA 10 P2[10]/EINT0/NMI 11 - 12 - Row K 1 P3[26]/STCLK/ MAT0[1]/PWM1[3] 2 VDD(3V3) 3 VSS 4 P1[20]/MCI0/ PWM1[2]/SCK0 5 P1[23]/MCI1/ PWM1[4]/MISO0 6 P1[26]/MCOB1/ PWM1[6]/CAP0[0] 7 P1[27]/CLKOUT /USB_OVRCR/ CAP0[1] 8 P0[0]/RD1/TXD3/SDA1 9 P0[11]/RXD2/ SCL2/MAT3[1] 10 P2[12]/EINT2/ I2STX_WS 11 - 12 - Table 4. Pin allocation table TFBGA100 …continued Pin Symbol Pin Symbol Pin Symbol Pin Symbol Table 5. Pin description Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100 P0[0] to P0[31] I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the pin connect block. Pins 12, 13, 14, and 31 of this port are not available. P0[0]/RD1/TXD3/ SDA1 46 K8 H10 [1] I/O P0[0] — General purpose digital input/output pin. I RD1 — CAN1 receiver input. (LPC1769/68/66/65/64 only). O TXD3 — Transmitter output for UART3. I/O SDA1 — I 2C1 data input/output. (This is not an I2C-bus compliant open-drain pin). P0[1]/TD1/RXD3/ SCL1 47 J8 H9 [1] I/O P0[1] — General purpose digital input/output pin. O TD1 — CAN1 transmitter output. (LPC1769/68/66/65/64 only). I RXD3 — Receiver input for UART3. I/O SCL1 — I 2C1 clock input/output. (This is not an I2C-bus compliant open-drain pin). P0[2]/TXD0/AD0[7] 98 C4 B1 [2] I/O P0[2] — General purpose digital input/output pin. O TXD0 — Transmitter output for UART0. I AD0[7] — A/D converter 0, input 7. P0[3]/RXD0/AD0[6] 99 A2 C3 [2] I/O P0[3] — General purpose digital input/output pin. I RXD0 — Receiver input for UART0. I AD0[6] — A/D converter 0, input 6.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 11 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P0[4]/ I2SRX_CLK/ RD2/CAP2[0] 81 A8 G2 [1] I/O P0[4] — General purpose digital input/output pin. I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I 2S-bus specification. (LPC1769/68/67/66/65/63 only). I RD2 — CAN2 receiver input. (LPC1769/68/66/65/64 only). I CAP2[0] — Capture input for Timer 2, channel 0. P0[5]/ I2SRX_WS/ TD2/CAP2[1] 80 D7 H1 [1] I/O P0[5] — General purpose digital input/output pin. I/O I2SRX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). O TD2 — CAN2 transmitter output. (LPC1769/68/66/65/64 only). I CAP2[1] — Capture input for Timer 2, channel 1. P0[6]/ I2SRX_SDA/ SSEL1/MAT2[0] 79 B8 G3 [1] I/O P0[6] — General purpose digital input/output pin. I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). I/O SSEL1 — Slave Select for SSP1. O MAT2[0] — Match output for Timer 2, channel 0. P0[7]/ I2STX_CLK/ SCK1/MAT2[1] 78 A9 J1 [1] I/O P0[7] — General purpose digital input/output pin. I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I 2S-bus specification. (LPC1769/68/67/66/65/63 only). I/O SCK1 — Serial Clock for SSP1. O MAT2[1] — Match output for Timer 2, channel 1. P0[8]/ I2STX_WS/ MISO1/MAT2[2] 77 C8 H2 [1] I/O P0[8] — General purpose digital input/output pin. I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I 2S-bus specification. (LPC1769/68/67/66/65/63 only). I/O MISO1 — Master In Slave Out for SSP1. O MAT2[2] — Match output for Timer 2, channel 2. P0[9]/ I2STX_SDA/ MOSI1/MAT2[3] 76 A10 H3 [1] I/O P0[9] — General purpose digital input/output pin. I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I 2S-bus specification. (LPC1769/68/67/66/65/63 only). I/O MOSI1 — Master Out Slave In for SSP1. O MAT2[3] — Match output for Timer 2, channel 3. P0[10]/TXD2/ SDA2/MAT3[0] 48 H7 H8 [1] I/O P0[10] — General purpose digital input/output pin. O TXD2 — Transmitter output for UART2. I/O SDA2 — I 2C2 data input/output (this is not an open-drain pin). O MAT3[0] — Match output for Timer 3, channel 0. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 12 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P0[11]/RXD2/ SCL2/MAT3[1] 49 K9 J10 [1] I/O P0[11] — General purpose digital input/output pin. I RXD2 — Receiver input for UART2. I/O SCL2 — I 2C2 clock input/output (this is not an open-drain pin). O MAT3[1] — Match output for Timer 3, channel 1. P0[15]/TXD1/ SCK0/SCK 62 F10 H6 [1] I/O P0[15] — General purpose digital input/output pin. O TXD1 — Transmitter output for UART1. I/O SCK0 — Serial clock for SSP0. I/O SCK — Serial clock for SPI. P0[16]/RXD1/ SSEL0/SSEL 63 F8 J5 [1] I/O P0[16] — General purpose digital input/output pin. I RXD1 — Receiver input for UART1. I/O SSEL0 — Slave Select for SSP0. I/O SSEL — Slave Select for SPI. P0[17]/CTS1/ MISO0/MISO 61 F9 K6 [1] I/O P0[17] — General purpose digital input/output pin. I CTS1 — Clear to Send input for UART1. I/O MISO0 — Master In Slave Out for SSP0. I/O MISO — Master In Slave Out for SPI. P0[18]/DCD1/ MOSI0/MOSI 60 F6 J6 [1] I/O P0[18] — General purpose digital input/output pin. I DCD1 — Data Carrier Detect input for UART1. I/O MOSI0 — Master Out Slave In for SSP0. I/O MOSI — Master Out Slave In for SPI. P0[19]/DSR1/ SDA1 59 G10 K7 [1] I/O P0[19] — General purpose digital input/output pin. I DSR1 — Data Set Ready input for UART1. I/O SDA1 — I 2C1 data input/output (this is not an I2C-bus compliant open-drain pin). P0[20]/DTR1/SCL1 58 G9 J7 [1] I/O P0[20] — General purpose digital input/output pin. O DTR1 — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. I/O SCL1 — I 2C1 clock input/output (this is not an I2C-bus compliant open-drain pin). P0[21]/RI1/RD1 57 G8 H7 [1] I/O P0[21] — General purpose digital input/output pin. I RI1 — Ring Indicator input for UART1. I RD1 — CAN1 receiver input. (LPC1769/68/66/65/64 only). P0[22]/RTS1/TD1 56 H10 K8 [1] I/O P0[22] — General purpose digital input/output pin. O RTS1 — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. O TD1 — CAN1 transmitter output. (LPC1769/68/66/65/64 only). Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 13 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P0[23]/AD0[0]/ I2SRX_CLK/ CAP3[0] 9 E5 D5 [2] I/O P0[23] — General purpose digital input/output pin. I AD0[0] — A/D converter 0, input 0. I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I 2S-bus specification. (LPC1769/68/67/66/65/63 only). I CAP3[0] — Capture input for Timer 3, channel 0. P0[24]/AD0[1]/ I2SRX_WS/ CAP3[1] 8 D1 B4 [2] I/O P0[24] — General purpose digital input/output pin. I AD0[1] — A/D converter 0, input 1. I/O I2SRX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I 2S-bus specification. (LPC1769/68/67/66/65/63 only). I CAP3[1] — Capture input for Timer 3, channel 1. P0[25]/AD0[2]/ I2SRX_SDA/ TXD3 7 D2 A3 [2] I/O P0[25] — General purpose digital input/output pin. I AD0[2] — A/D converter 0, input 2. I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I 2S-bus specification. (LPC1769/68/67/66/65/63 only). O TXD3 — Transmitter output for UART3. P0[26]/AD0[3]/ AOUT/RXD3 6 D3 C5 [3] I/O P0[26] — General purpose digital input/output pin. I AD0[3] — A/D converter 0, input 3. O AOUT — DAC output (LPC1769/68/67/66/65/63 only). I RXD3 — Receiver input for UART3. P0[27]/SDA0/ USB_SDA 25 J2 C8 [4] I/O P0[27] — General purpose digital input/output pin. Output is open-drain. I/O SDA0 — I 2C0 data input/output. Open-drain output (for I2C-bus compliance). I/O USB_SDA — USB port I2C serial data (OTG transceiver, LPC1769/68/66/65 only). P0[28]/SCL0/ USB_SCL 24 J1 B9 [4] I/O P0[28] — General purpose digital input/output pin. Output is open-drain. I/O SCL0 — I 2C0 clock input/output. Open-drain output (for I2C-bus compliance). I/O USB_SCL — USB port I2C serial clock (OTG transceiver, LPC1769/68/66/65 only). P0[29]/USB_D+ 29 J3 B10 [5] I/O P0[29] — General purpose digital input/output pin. I/O USB_D+ — USB bidirectional D+ line. (LPC1769/68/66/65/64 only). P0[30]/USB_D 30 G4 C9 [5] I/O P0[30] — General purpose digital input/output pin. I/O USB_D — USB bidirectional D line. (LPC1769/68/66/65/64 only). Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 14 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P1[0] to P1[31] I/O Port 1: Port 1 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block. Pins 2, 3, 5, 6, 7, 11, 12, and 13 of this port are not available. P1[0]/ ENET_TXD0 95 D5 C1 [1] I/O P1[0] — General purpose digital input/output pin. O ENET_TXD0 — Ethernet transmit data 0. (LPC1769/68/67/66/64 only). P1[1]/ ENET_TXD1 94 B4 C2 [1] I/O P1[1] — General purpose digital input/output pin. O ENET_TXD1 — Ethernet transmit data 1. (LPC1769/68/67/66/64 only). P1[4]/ ENET_TX_EN 93 A4 D2 [1] I/O P1[4] — General purpose digital input/output pin. O ENET_TX_EN — Ethernet transmit data enable. (LPC1769/68/67/66/64 only). P1[8]/ ENET_CRS 92 C5 D1 [1] I/O P1[8] — General purpose digital input/output pin. I ENET_CRS — Ethernet carrier sense. (LPC1769/68/67/66/64 only). P1[9]/ ENET_RXD0 91 B5 D3 [1] I/O P1[9] — General purpose digital input/output pin. I ENET_RXD0 — Ethernet receive data. (LPC1769/68/67/66/64 only). P1[10]/ ENET_RXD1 90 A5 E3 [1] I/O P1[10] — General purpose digital input/output pin. I ENET_RXD1 — Ethernet receive data. (LPC1769/68/67/66/64 only). P1[14]/ ENET_RX_ER 89 D6 E2 [1] I/O P1[14] — General purpose digital input/output pin. I ENET_RX_ER — Ethernet receive error. (LPC1769/68/67/66/64 only). P1[15]/ ENET_REF_CLK 88 C6 E1 [1] I/O P1[15] — General purpose digital input/output pin. I ENET_REF_CLK — Ethernet reference clock. (LPC1769/68/67/66/64 only). P1[16]/ ENET_MDC 87 A6 F3 [1] I/O P1[16] — General purpose digital input/output pin. O ENET_MDC — Ethernet MIIM clock (LPC1769/68/67/66/64 only). P1[17]/ ENET_MDIO 86 B6 F2 [1] I/O P1[17] — General purpose digital input/output pin. I/O ENET_MDIO — Ethernet MIIM data input and output. (LPC1769/68/67/66/64 only). Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 15 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P1[18]/ USB_UP_LED/ PWM1[1]/ CAP1[0] 32 H4 D9 [1] I/O P1[18] — General purpose digital input/output pin. O USB_UP_LED — USB GoodLink LED indicator. It is LOW when the device is configured (non-control endpoints enabled), or when the host is enabled and has detected a device on the bus. It is HIGH when the device is not configured, or when host is enabled and has not detected a device on the bus, or during global suspend. It transitions between LOW and HIGH (flashes) when the host is enabled and detects activity on the bus. (LPC1769/68/66/65/64 only). O PWM1[1] — Pulse Width Modulator 1, channel 1 output. I CAP1[0] — Capture input for Timer 1, channel 0. P1[19]/MCOA0/ USB_PPWR/ CAP1[1] 33 J4 C10 [1] I/O P1[19] — General purpose digital input/output pin. O MCOA0 — Motor control PWM channel 0, output A. O USB_PPWR — Port Power enable signal for USB port. (LPC1769/68/66/65 only). I CAP1[1] — Capture input for Timer 1, channel 1. P1[20]/MCI0/ PWM1[2]/SCK0 34 K4 E8 [1] I/O P1[20] — General purpose digital input/output pin. I MCI0 — Motor control PWM channel 0, input. Also Quadrature Encoder Interface PHA input. O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I/O SCK0 — Serial clock for SSP0. P1[21]/MCABORT/ PWM1[3]/ SSEL0 35 F5 E9 [1] I/O P1[21] — General purpose digital input/output pin. O MCABORT — Motor control PWM, LOW-active fast abort. O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I/O SSEL0 — Slave Select for SSP0. P1[22]/MCOB0/ USB_PWRD/ MAT1[0] 36 J5 D10 [1] I/O P1[22] — General purpose digital input/output pin. O MCOB0 — Motor control PWM channel 0, output B. I USB_PWRD — Power Status for USB port (host power switch, LPC1769/68/66/65 only). O MAT1[0] — Match output for Timer 1, channel 0. P1[23]/MCI1/ PWM1[4]/MISO0 37 K5 E7 [1] I/O P1[23] — General purpose digital input/output pin. I MCI1 — Motor control PWM channel 1, input. Also Quadrature Encoder Interface PHB input. O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I/O MISO0 — Master In Slave Out for SSP0. P1[24]/MCI2/ PWM1[5]/MOSI0 38 H5 F8 [1] I/O P1[24] — General purpose digital input/output pin. I MCI2 — Motor control PWM channel 2, input. Also Quadrature Encoder Interface INDEX input. O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I/O MOSI0 — Master Out Slave in for SSP0. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 16 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P1[25]/MCOA1/ MAT1[1] 39 G5 F9 [1] I/O P1[25] — General purpose digital input/output pin. O MCOA1 — Motor control PWM channel 1, output A. O MAT1[1] — Match output for Timer 1, channel 1. P1[26]/MCOB1/ PWM1[6]/CAP0[0] 40 K6 E10 [1] I/O P1[26] — General purpose digital input/output pin. O MCOB1 — Motor control PWM channel 1, output B. O PWM1[6] — Pulse Width Modulator 1, channel 6 output. I CAP0[0] — Capture input for Timer 0, channel 0. P1[27]/CLKOUT /USB_OVRCR/ CAP0[1] 43 K7 G9 [1] I/O P1[27] — General purpose digital input/output pin. O CLKOUT — Clock output pin. I USB_OVRCR — USB port Over-Current status. (LPC1769/68/66/65 only). I CAP0[1] — Capture input for Timer 0, channel 1. P1[28]/MCOA2/ PCAP1[0]/ MAT0[0] 44 J7 G10 [1] I/O P1[28] — General purpose digital input/output pin. O MCOA2 — Motor control PWM channel 2, output A. I PCAP1[0] — Capture input for PWM1, channel 0. O MAT0[0] — Match output for Timer 0, channel 0. P1[29]/MCOB2/ PCAP1[1]/ MAT0[1] 45 G6 G8 [1] I/O P1[29] — General purpose digital input/output pin. O MCOB2 — Motor control PWM channel 2, output B. I PCAP1[1] — Capture input for PWM1, channel 1. O MAT0[1] — Match output for Timer 0, channel 1. P1[30]/VBUS/ AD0[4] 21 H1 B8 [2] I/O P1[30] — General purpose digital input/output pin. I VBUS — Monitors the presence of USB bus power. (LPC1769/68/66/65/64 only). Note: This signal must be HIGH for USB reset to occur. I AD0[4] — A/D converter 0, input 4. P1[31]/SCK1/ AD0[5] 20 F4 C7 [2] I/O P1[31] — General purpose digital input/output pin. I/O SCK1 — Serial Clock for SSP1. I AD0[5] — A/D converter 0, input 5. P2[0] to P2[31] I/O Port 2: Port 2 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 2 pins depends upon the pin function selected via the pin connect block. Pins 14 through 31 of this port are not available. P2[0]/PWM1[1]/ TXD1 75 B9 K1 [1] I/O P2[0] — General purpose digital input/output pin. O PWM1[1] — Pulse Width Modulator 1, channel 1 output. O TXD1 — Transmitter output for UART1. P2[1]/PWM1[2]/ RXD1 74 B10 J2 [1] I/O P2[1] — General purpose digital input/output pin. O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I RXD1 — Receiver input for UART1. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 17 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P2[2]/PWM1[3]/ CTS1/ TRACEDATA[3] 73 D8 K2 [1] I/O P2[2] — General purpose digital input/output pin. O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I CTS1 — Clear to Send input for UART1. O TRACEDATA[3] — Trace data, bit 3. P2[3]/PWM1[4]/ DCD1/ TRACEDATA[2] 70 E7 K3 [1] I/O P2[3] — General purpose digital input/output pin. O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I DCD1 — Data Carrier Detect input for UART1. O TRACEDATA[2] — Trace data, bit 2. P2[4]/PWM1[5]/ DSR1/ TRACEDATA[1] 69 D9 J3 [1] I/O P2[4] — General purpose digital input/output pin. O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I DSR1 — Data Set Ready input for UART1. O TRACEDATA[1] — Trace data, bit 1. P2[5]/PWM1[6]/ DTR1/ TRACEDATA[0] 68 D10 H4 [1] I/O P2[5] — General purpose digital input/output pin. O PWM1[6] — Pulse Width Modulator 1, channel 6 output. O DTR1 — Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. O TRACEDATA[0] — Trace data, bit 0. P2[6]/PCAP1[0]/ RI1/TRACECLK 67 E8 K4 [1] I/O P2[6] — General purpose digital input/output pin. I PCAP1[0] — Capture input for PWM1, channel 0. I RI1 — Ring Indicator input for UART1. O TRACECLK — Trace Clock. P2[7]/RD2/ RTS1 66 E9 J4 [1] I/O P2[7] — General purpose digital input/output pin. I RD2 — CAN2 receiver input. (LPC1769/68/66/65/64 only). O RTS1 — Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. P2[8]/TD2/ TXD2 65 E10 H5 [1] I/O P2[8] — General purpose digital input/output pin. O TD2 — CAN2 transmitter output. (LPC1769/68/66/65/64 only). O TXD2 — Transmitter output for UART2. P2[9]/ USB_CONNECT/ RXD2 64 F7 K5 [1] I/O P2[9] — General purpose digital input/output pin. O USB_CONNECT — Signal used to switch an external 1.5 k resistor under software control. Used with the SoftConnect USB feature. (LPC1769/68/66/65/64 only). I RXD2 — Receiver input for UART2. P2[10]/EINT0/NMI 53 J10 K9 [6] I/O P2[10] — General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler. I EINT0 — External interrupt 0 input. I NMI — Non-maskable interrupt input. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 18 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller P2[11]/EINT1/ I2STX_CLK 52 H8 J8 [6] I/O P2[11] — General purpose digital input/output pin. I EINT1 — External interrupt 1 input. I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I 2S-bus specification. (LPC1769/68/67/66/65/63 only). P2[12]/EINT2/ I2STX_WS 51 K10 K10 [6] I/O P2[12] — General purpose digital input/output pin. I EINT2 — External interrupt 2 input. I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I 2S-bus specification. (LPC1769/68/67/66/65/63 only). P2[13]/EINT3/ I2STX_SDA 50 J9 J9 [6] I/O P2[13] — General purpose digital input/output pin. I EINT3 — External interrupt 3 input. I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I 2S-bus specification. (LPC1769/68/67/66/65/63 only). P3[0] to P3[31] I/O Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 3 pins depends upon the pin function selected via the pin connect block. Pins 0 through 24, and 27 through 31 of this port are not available. P3[25]/MAT0[0]/ PWM1[2] 27 H3 D8 [1] I/O P3[25] — General purpose digital input/output pin. O MAT0[0] — Match output for Timer 0, channel 0. O PWM1[2] — Pulse Width Modulator 1, output 2. P3[26]/STCLK/ MAT0[1]/PWM1[3] 26 K1 A10 [1] I/O P3[26] — General purpose digital input/output pin. I STCLK — System tick timer clock input. The maximum STCLK frequency is 1/4 of the ARM processor clock frequency CCLK. O MAT0[1] — Match output for Timer 0, channel 1. O PWM1[3] — Pulse Width Modulator 1, output 3. P4[0] to P4[31] I/O Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 4 pins depends upon the pin function selected via the pin connect block. Pins 0 through 27, 30, and 31 of this port are not available. P4[28]/RX_MCLK/ MAT2[0]/TXD3 82 C7 G1 [1] I/O P4[28] — General purpose digital input/output pin. O RX_MCLK — I 2S receive master clock. (LPC1769/68/67/66/65 only). O MAT2[0] — Match output for Timer 2, channel 0. O TXD3 — Transmitter output for UART3. P4[29]/TX_MCLK/ MAT2[1]/RXD3 85 E6 F1 [1] I/O P4[29] — General purpose digital input/output pin. O TX_MCLK — I 2S transmit master clock. (LPC1769/68/67/66/65 only). O MAT2[1] — Match output for Timer 2, channel 1. I RXD3 — Receiver input for UART3. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 19 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller TDO/SWO 1 A1 A1 [1][7] O TDO — Test Data out for JTAG interface. O SWO — Serial wire trace output. TDI 2 C3 C4 [1][8] I TDI — Test Data in for JTAG interface. TMS/SWDIO 3 B1 B3 [1][8] I TMS — Test Mode Select for JTAG interface. I/O SWDIO — Serial wire debug data input/output. TRST 4 C2 A2 [1][8] I TRST — Test Reset for JTAG interface. TCK/SWDCLK 5 C1 D4 [1][7] I TCK — Test Clock for JTAG interface. I SWDCLK — Serial wire clock. RTCK 100 B2 B2 [1][7] O RTCK — JTAG interface control signal. RSTOUT 14 - - - O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates the microcontroller being in Reset state. RESET 17 F3 C6 [9] I External reset input: A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant. XTAL1 22 H2 D7 [10][11] I Input to the oscillator circuit and internal clock generator circuits. XTAL2 23 G3 A9 [10][11] O Output from the oscillator amplifier. RTCX1 16 F2 A7 [10][11] I Input to the RTC oscillator circuit. RTCX2 18 G1 B7 [10] O Output from the RTC oscillator circuit. VSS 31, 41, 55, 72, 83, 97 B3, B7, C9, G7, J6, K3 E5, F5, F6, G5, G6, G7 [10] I ground: 0 V reference. VSSA 11 E1 B5 [10] I analog ground: 0 V reference. This should nominally be the same voltage as VSS, but should be isolated to minimize noise and error. VDD(3V3) 28, 54, 71, 96 K2, H9, C10 , A3 E4, E6, F7, G4 [10] I 3.3 V supply voltage: This is the power supply voltage for the I/O ports. VDD(REG)(3V3) 42, 84 H6, A7 F4, F0 [10] I 3.3 V voltage regulator supply voltage: This is the supply voltage for the on-chip voltage regulator only. VDDA 10 E2 A4 [10] I analog 3.3 V pad supply voltage: This should be nominally the same voltage as VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to power the ADC and DAC. This pin should be tied to 3.3 V if the ADC and DAC are not used. VREFP 12 E3 A5 [10] I ADC positive reference voltage: This should be nominally the same voltage as VDDA but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC and DAC. This pin should be tied to 3.3 V if the ADC and DAC are not used. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 20 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller [1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [4] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. This pad requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [5] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). This pad is not 5 V tolerant. [6] 5 V tolerant pad with 10 ns glitch filter providing digital I/O functions with TTL levels and hysteresis. This pin is pulled up to a voltage level of 2.3 V to 2.6 V. [7] 5 V tolerant pad with TTL levels and hysteresis. Internal pull-up and pull-down resistors disabled. [8] 5 V tolerant pad with TTL levels and hysteresis and internal pull-up resistor. [9] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis. [10] Pad provides special analog functionality. A 32 kHz crystal oscillator must be used with the RTC. [11] When the system oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTAL2 should be left floating. [12] When the RTC is not used, connect VBAT to VDD(REG)(3V3) and leave RTCX1 floating. VREFN 15 F1 A6 I ADC negative reference voltage: This should be nominally the same voltage as VSS but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC and DAC. VBAT 19 G2 A8 [10][12] I RTC pin power supply: 3.3 V on this pin supplies the power to the RTC peripheral. n.c. 13 D4, E4 B6, D6 - not connected. Table 5. Pin description …continued Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 21 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8. Functional description 8.1 Architectural overview Remark: In the following, the notation LPC17xx refers to all parts: LPC1769/68/67/66/65/64/63. The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus (see Figure 1). The I-code and D-code core buses are faster than the system bus and are used similarly to TCM interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices. The LPC17xx use a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slaves ports of the matrix to be accessed simultaneously by different bus masters. 8.2 ARM Cortex-M3 processor The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. The ARM Cortex-M3 offers many new features, including a Thumb-2 instruction set, low interrupt latency, hardware divide, interruptible/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller with wake-up interrupt controller, and multiple core buses capable of simultaneous accesses. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical Reference Manual that can be found on official ARM website. 8.3 On-chip flash program memory The LPC17xx contain up to 512 kB of on-chip flash memory. A new two-port flash accelerator maximizes performance for use with the two fast AHB-Lite buses. 8.4 On-chip SRAM The LPC17xx contain a total of 64 kB on-chip static RAM memory. This includes the main 32 kB SRAM, accessible by the CPU and DMA controller on a higher-speed bus, and two additional 16 kB each SRAM blocks situated on a separate slave port on the AHB multilayer matrix. This architecture allows CPU and DMA accesses to be spread over three separate RAMs that can be accessed simultaneously. 8.5 Memory Protection Unit (MPU) The LPC17xx have a Memory Protection Unit (MPU) which can be used to improve the reliability of an embedded system by protecting critical data within the user application.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 22 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller The MPU allows separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only and detecting unexpected memory accesses that could potentially break the system. The MPU separates the memory into distinct regions and implements protection by preventing disallowed accesses. The MPU supports up to 8 regions each of which can be divided into 8 subregions. Accesses to memory locations that are not defined in the MPU regions, or not permitted by the region setting, will cause the Memory Management Fault exception to take place. 8.6 Memory map The LPC17xx incorporates several distinct memory regions, shown in the following figures. Figure 5 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals. The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals. Each peripheral of either type is allocated 16 kB of space. This allows simplifying the address decoding for each peripheral.xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 23 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller (1) Not available on all parts. See Table 2. Fig 5. LPC17xx memory map 0x5000 0000 0x5000 4000 0x5000 8000 0x5000 C000 0x5020 0000 0x5001 0000 AHB peripherals Ethernet controller(1) USB controller(1) reserved 127- 4 reserved GPDMA controller 0 1 2 3 APB0 peripherals 0x4000 4000 0x4000 8000 0x4000 C000 0x4001 0000 0x4001 8000 0x4002 0000 0x4002 8000 0x4002 C000 0x4003 4000 0x4003 0000 0x4003 8000 0x4003 C000 0x4004 0000 0x4004 4000 0x4004 8000 0x4004 C000 0x4005 C000 0x4006 0000 0x4008 0000 0x4002 4000 0x4001 C000 0x4001 4000 WDT 0x4000 0000 timer 0 timer 1 UART0 UART1 reserved reserved SPI RTC + backup registers GPIO interrupts pin connect SSP1 ADC CAN AF RAM(1) CAN AF registers(1) CAN common(1) CAN1(1) CAN2(1) 22 - 19 reserved I2C1 31 - 24 reserved 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 23 reserved reserved 32 kB local SRAM (LPC1769/8/7/6/5/3) 16 kB local SRAM (LPC1764) reserved reserved private peripheral bus 0 GB 0x0000 0000 0.5 GB 4 GB 1 GB 0x0004 0000 0x0002 0000 0x0008 0000 0x1000 4000 0x1000 0000 0x1000 8000 0x1FFF 0000 0x1FFF 2000 0x2008 0000 0x2007 C000 0x2008 4000 0x2200 0000 0x200A 0000 0x2009 C000 0x2400 0000 0x4000 0000 0x4008 0000 0x4010 0000 0x4200 0000 0x4400 0000 0x5000 0000 0x5020 0000 0xE000 0000 0xE010 0000 0xFFFF FFFF reserved reserved GPIO reserved reserved reserved reserved APB0 peripherals AHB peripherals APB1 peripherals AHB SRAM bit-band alias addressing peripheral bit-band alias addressing 16 kB AHB SRAM1 (LPC1769/8/7/6/5) 16 kB AHB SRAM0 256 kB on-chip flash (LPC1766/65/63) 128 kB on-chip flash (LPC1764) 512 kB on-chip flash (LPC1769/8/7) PWM1 8 kB boot ROM 0x0000 0000 0x0000 0400 active interrupt vectors + 256 words I-code/D-code memory space 002aad946 APB1 peripherals 0x4008 0000 0x4008 8000 0x4008 C000 0x4009 0000 0x4009 4000 0x4009 8000 0x4009 C000 0x400A 0000 0x400A 4000 0x400A 8000 0x400A C000 0x400B 0000 0x400B 4000 0x400B 8000 0x400B C000 0x400C 0000 0x400F C000 0x4010 0000 SSP0 DAC(1) timer 2 timer 3 UART2 UART3 reserved I2S(1) I2C2 1 - 0 reserved 2 3 4 5 6 7 8 9 10 reserved repetitive interrupt timer 11 12 reserved motor control PWM 30 - 16 reserved 13 14 15 31 system control QEI LPC1769/68/67/66/65/64/63LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 24 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.7 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 8.7.1 Features • Controls system exceptions and peripheral interrupts • In the LPC17xx, the NVIC supports 33 vectored interrupts • 32 programmable interrupt priority levels, with hardware priority level masking • Relocatable vector table • Non-Maskable Interrupt (NMI) • Software interrupt generation 8.7.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Any pin on Port 0 and Port 2 (total of 42 pins) regardless of the selected function, can be programmed to generate an interrupt on a rising edge, a falling edge, or both. 8.8 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. Most pins can also be configured as open-drain outputs or to have a pull-up, pull-down, or no resistor enabled. 8.9 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. The source and destination areas can each be either a memory region or a peripheral, and can be accessed through the AHB master. The GPDMA controller allows data transfers between the USB and Ethernet controllers and the various on-chip SRAM areas. The supported APB peripherals are SSP0/1, all UARTs, the I2S-bus interface, the ADC, and the DAC. Two match signals for each timer can be used to trigger DMA transfers. Remark: The Ethernet controller is available on parts LPC1769/68/67/66/64. The USB controller is available on parts LPC1769/68/66/65/64. The I2S-bus interface is available on parts LPC1769/68/67/66/65. The DAC is available on parts LPC1769/68/67/66/65/63.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 25 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.9.1 Features • Eight DMA channels. Each channel can support an unidirectional transfer. • 16 DMA request lines. • Single DMA and burst DMA request signals. Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller. • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers are supported. • Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory. • Hardware DMA channel priority. • AHB slave DMA programming interface. The DMA Controller is programmed by writing to the DMA control registers over the AHB slave interface. • One AHB bus master for transferring data. The interface transfers data when a DMA request goes active. • 32-bit AHB master bus width. • Incrementing or non-incrementing addressing for source and destination. • Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data. • Internal four-word FIFO per channel. • Supports 8, 16, and 32-bit wide transactions. • Big-endian and little-endian support. The DMA Controller defaults to little-endian mode on reset. • An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred. • Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking. 8.10 Fast general purpose parallel I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins. LPC17xx use accelerated GPIO functions: • GPIO registers are accessed through the AHB multilayer bus so that the fastest possible I/O timing can be achieved. • Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. • All GPIO registers are byte and half-word addressable. • Entire port value can be written in one instruction. • Support for Cortex-M3 bit banding. • Support for use with the GPDMA controller.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 26 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller Additionally, any pin on Port 0 and Port 2 (total of 42 pins) providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous, so it may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode. 8.10.1 Features • Bit level set and clear registers allow a single instruction to set or clear any number of bits in one port. • Direction control of individual bits. • All I/O default to inputs after reset. • Pull-up/pull-down resistor configuration and open-drain configuration can be programmed through the pin connect block for each GPIO pin. 8.11 Ethernet Remark: The Ethernet controller is available on parts LPC1769/68/67/66/64. The Ethernet block supports bus clock rates of up to 100 MHz (LPC1768/67/66/64) or 120 MHz (LPC1769). See Table 2. The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU. The Ethernet block and the CPU share the ARM Cortex-M3 D-code and system bus through the AHB-multilayer matrix to access the various on-chip SRAM blocks for Ethernet data, control, and status information. The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus. 8.11.1 Features • Ethernet standards support: – Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX, 100 Base-FX, and 100 Base-T4. – Fully compliant with IEEE standard 802.3. – Fully compliant with 802.3x full duplex flow control and half duplex back pressure. – Flexible transmit and receive frame options. – Virtual Local Area Network (VLAN) frame support. • Memory management: – Independent transmit and receive buffers memory mapped to shared SRAM. – DMA managers with scatter/gather DMA and arrays of frame descriptors. – Memory traffic optimized by buffering and pre-fetching.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 27 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller • Enhanced Ethernet features: – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Cyclic Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision back-off and frame retransmission. – Includes power management by clock switching. – Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter. • Physical interface: – Attachment of external PHY chip through standard RMII interface. – PHY register access is available via the MIIM interface. 8.12 USB interface Remark: The USB controller is available as device/Host/OTG controller on parts LPC1769/68/66/65 and as device-only controller on part LPC1764. The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the host controller. The USB interface includes a device, Host, and OTG controller with on-chip PHY for device and Host functions. The OTG switching protocol is supported through the use of an external controller. Details on typical USB interfacing solutions can be found in Section 15.1. 8.12.1 USB device controller The device controller enables 12 Mbit/s data exchange with a USB Host controller. It consists of a register interface, serial interface engine, endpoint buffer memory, and a DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. When enabled, the DMA controller transfers data between the endpoint buffer and the on-chip SRAM. 8.12.1.1 Features • Fully compliant with USB 2.0 specification (full speed). • Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM. • Supports Control, Bulk, Interrupt and Isochronous endpoints. • Scalable realization of endpoints at run time.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 28 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller • Endpoint Maximum packet size selection (up to USB maximum specification) by software at run time. • Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, the part can enter one of the reduced power modes and wake up on USB activity. • Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints. • Allows dynamic switching between CPU-controlled slave and DMA modes. • Double buffer implementation for Bulk and Isochronous endpoints. 8.12.2 USB host controller The host controller enables full- and low-speed data exchange with USB devices attached to the bus. It consists of a register interface, a serial interface engine, and a DMA controller. The register interface complies with the OHCI specification. 8.12.2.1 Features • OHCI compliant. • One downstream port. • Supports port power switching. 8.12.3 USB OTG controller USB OTG is a supplement to the USB 2.0 specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. The OTG Controller integrates the host controller, device controller, and a master-only I 2C-bus interface to implement OTG dual-role device functionality. The dedicated I2C-bus interface controls an external OTG transceiver. 8.12.3.1 Features • Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision 1.0a. • Hardware support for Host Negotiation Protocol (HNP). • Includes a programmable timer required for HNP and Session Request Protocol (SRP). • Supports any OTG transceiver compliant with the OTG Transceiver Specification (CEA-2011), Rev. 1.0. 8.13 CAN controller and acceptance filters Remark: The CAN controllers are available on parts LPC1769/68/66/65/64. See Table 2. The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high-speed networks to low cost multiplex wiring. The CAN block is intended to support multiple CAN buses simultaneously, allowing the device to be used as a gateway, switch, or router among a number of CAN buses in industrial or automotive applications.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 29 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.13.1 Features • Two CAN controllers and buses. • Data rates to 1 Mbit/s on each bus. • 32-bit register and RAM access. • Compatible with CAN specification 2.0B, ISO 11898-1. • Global Acceptance Filter recognizes standard (11-bit) and extended-frame (29-bit) receive identifiers for all CAN buses. • Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • FullCAN messages can generate interrupts. 8.14 12-bit ADC The LPC17xx contain a single 12-bit successive approximation ADC with eight channels and DMA support. 8.14.1 Features • 12-bit successive approximation ADC. • Input multiplexing among 8 pins. • Power-down mode. • Measurement range VREFN to VREFP. • 12-bit conversion rate: 200 kHz. • Individual channels can be selected for conversion. • Burst conversion mode for single or multiple inputs. • Optional conversion on transition of input pin or Timer Match signal. • Individual result registers for each ADC channel to reduce interrupt overhead. • DMA support. 8.15 10-bit DAC The DAC allows to generate a variable analog output. The maximum output value of the DAC is VREFP. Remark: The DAC is available on parts LPC1769/68/67/66/65/63. See Table 2. 8.15.1 Features • 10-bit DAC • Resistor string architecture • Buffered output • Power-down mode • Selectable output drive • Dedicated conversion timer • DMA supportLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 30 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.16 UARTs The LPC17xx each contain four UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface and support for RS-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode. The UARTs include a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 8.16.1 Features • Maximum UART data bit rate of 6.25 Mbit/s. • 16 B Receive and Transmit FIFOs. • Register locations conform to 16C550 industry standard. • Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. • Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • Auto baud capabilities and FIFO control mechanism that enables software flow control implementation. • UART1 equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). • Support for RS-485/9-bit/EIA-485 mode (UART1). • UART3 includes an IrDA mode to support infrared communication. • All UARTs have DMA support. 8.17 SPI serial I/O controller The LPC17xx contain one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master. 8.17.1 Features • Maximum SPI data bit rate of 12.5 Mbit/s • Compliant with SPI specification • Synchronous, serial, full duplex communication • Combined SPI master and slave • Maximum data bit rate of one eighth of the input clock rate • 8 bits to 16 bits per transfer 8.18 SSP serial I/O controller The LPC17xx contain two SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 31 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 8.18.1 Features • Maximum SSP speed of 33 Mbit/s (master) or 8 Mbit/s (slave) • Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses • Synchronous serial communication • Master or slave operation • 8-frame FIFOs for both transmit and receive • 4-bit to 16-bit frame • DMA transfers supported by GPDMA 8.19 I2C-bus serial I/O controllers The LPC17xx each contain three I2C-bus controllers. The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line (SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it. 8.19.1 Features • I 2C0 is a standard I2C compliant bus interface with open-drain pins. I2C0 also supports Fast mode plus with bit rates up to 1 Mbit/s. • I 2C1 and I2C2 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus). • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • The I2C-bus can be used for test and diagnostic purposes. • All I2C-bus controllers support multiple address recognition and a bus monitor mode.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 32 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.20 I2S-bus serial I/O controllers Remark: The I2S-bus interface is available on parts LPC1769/68/67/66/65/63. See Table 2. The I2S-bus provides a standard communication interface for digital audio applications. The I 2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I2S-bus connection has one master, which is always the master, and one slave. The I2S-bus interface provides a separate transmit and receive channel, each of which can operate as either a master or a slave. 8.20.1 Features • The interface has separate input/output channels each of which can operate in master or slave mode. • Capable of handling 8-bit, 16-bit, and 32-bit word sizes. • Mono and stereo audio data supported. • The sampling frequency can range from 16 kHz to 96 kHz (16, 22.05, 32, 44.1, 48, 96) kHz. • Support for an audio master clock. • Configurable word select period in master mode (separately for I2S-bus input and output). • Two 8-word FIFO data buffers are provided, one for transmit and one for receive. • Generates interrupt requests when buffer levels cross a programmable boundary. • Two DMA requests, controlled by programmable buffer levels. These are connected to the GPDMA block. • Controls include reset, stop and mute options separately for I2S-bus input and I2S-bus output. 8.21 General purpose 32-bit timers/external event counters The LPC17xx include four 32-bit timer/counters. The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers. Each timer/counter also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 8.21.1 Features • A 32-bit timer/counter with a programmable 32-bit prescaler. • Counter or timer operation. • Two 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt. • Four 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 33 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller • Up to four external outputs corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. • Up to two match registers can be used to generate timed DMA requests. 8.22 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC17xx. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is in addition to these features, and is based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. One match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs. Three match registers can be used to provide a PWM output with both edges controlled. Again, the PWMMR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge). 8.22.1 Features • One PWM block with Counter or Timer operation (may use the peripheral clock or one of the capture inputs as the clock source). • Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM outputs, or a mix of both types. The match registers also allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 34 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller • Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses. • Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. • Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. • Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must ‘release’ new match values before they can become effective. • May be used as a standard 32-bit timer/counter with a programmable 32-bit prescaler if the PWM mode is not enabled. 8.23 Motor control PWM The motor control PWM is a specialized PWM supporting 3-phase motors and other combinations. Feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down. An abort input is also provided that causes the PWM to immediately release all motor drive outputs. At the same time, the motor control PWM is highly configurable for other generalized timing, counting, capture, and compare applications. 8.24 Quadrature Encoder Interface (QEI) A quadrature encoder, also known as a 2-channel incremental encoder, converts angular displacement into two pulse signals. By monitoring both the number of pulses and the relative phase of the two signals, the user can track the position, direction of rotation, and velocity. In addition, a third channel, or index signal, can be used to reset the position counter. The quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, the QEI can capture the velocity of the encoder wheel. 8.24.1 Features • Tracks encoder position. • Increments/decrements depending on direction. • Programmable for 2 or 4 position counting. • Velocity capture using built-in timer. • Velocity compare function with “less than” interrupt. • Uses 32-bit registers for position and velocity. • Three position compare registers with interrupts. • Index counter for revolution counting. • Index compare register with interrupts. • Can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 35 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller • Digital filter with programmable delays for encoder input signals. • Can accept decoded signal inputs (clk and direction). • Connected to APB. 8.25 Repetitive Interrupt (RI) timer The repetitive interrupt timer provides a free-running 32-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. Any bits of the timer/compare can be masked such that they do not contribute to the match detection. The repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals. 8.25.1 Features • 32-bit counter running from PCLK. Counter can be free-running or be reset by a generated interrupt. • 32-bit compare value. • 32-bit compare mask. An interrupt is generated when the counter value equals the compare value, after masking. This allows for combinations not possible with a simple compare. 8.26 ARM Cortex-M3 system tick timer The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a 10 ms interval. In the LPC17xx, this timer can be clocked from the internal AHB clock or from a device pin. 8.27 Watchdog timer The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined amount of time. 8.27.1 Features • Internally resets chip if not periodically reloaded. • Debug mode. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 32-bit timer with internal prescaler. • Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 232 4) in multiples of Tcy(WDCLK) 4. • The Watchdog Clock (WDCLK) source can be selected from the Internal RC (IRC) oscillator, the RTC oscillator, or the APB peripheral clock. This gives a wide range of potential timing choices of Watchdog operation under different power reduction LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 36 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability. • Includes lock/safe feature. 8.28 RTC and backup registers The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. The RTC on the LPC17xx is designed to have extremely low power consumption, i.e. less than 1 A. The RTC will typically run from the main chip power supply, conserving battery power while the rest of the device is powered up. When operating from a battery, the RTC will continue working down to 2.1 V. Battery power can be provided from a standard 3 V Lithium button cell. An ultra-low power 32 kHz oscillator will provide a 1 Hz clock to the time counting portion of the RTC, moving most of the power consumption out of the time counting function. The RTC includes a calibration mechanism to allow fine-tuning the count rate in a way that will provide less than 1 second per day error when operated at a constant voltage and temperature. A clock output function (see Section 8.29.4) makes measuring the oscillator rate easy and accurate. The RTC contains a small set of backup registers (20 bytes) for holding data while the main part of the LPC17xx is powered off. The RTC includes an alarm function that can wake up the LPC17xx from all reduced power modes with a time resolution of 1 s. 8.28.1 Features • Measures the passage of time to maintain a calendar and clock. • Ultra low power design to support battery powered systems. • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. • Dedicated power supply pin can be connected to a battery or to the main 3.3 V. • Periodic interrupts can be generated from increments of any field of the time registers. • Backup registers (20 bytes) powered by VBAT. • RTC power supply is isolated from the rest of the chip. 8.29 Clocking and power control 8.29.1 Crystal oscillators The LPC17xx include three independent oscillators. These are the main oscillator, the IRC oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Any of the three clock sources can be chosen by software to drive the main PLL and ultimately the CPU. Following reset, the LPC17xx will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 37 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller See Figure 6 for an overview of the LPC17xx clock generation. 8.29.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC17xx use the IRC as the clock source. Software may later switch to one of the other available clock sources. 8.29.1.2 Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using the PLL. The main oscillator also provides the clock source for the dedicated USB PLL. The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the main PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock frequency is referred to as CCLK elsewhere in this document. The frequencies of PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The clock frequency for each peripheral can be selected individually and is referred to as PCLK. Refer to Section 8.29.2 for additional information. 8.29.1.3 RTC oscillator The RTC oscillator can be used as the clock source for the RTC block, the main PLL, and/or the CPU. Fig 6. LPC17xx clocking generation block diagram MAIN OSCILLATOR INTERNAL RC OSCILLATOR RTC OSCILLATOR MAIN PLL WATCHDOG TIMER REAL-TIME CLOCK CPU CLOCK DIVIDER PERIPHERAL CLOCK GENERATOR USB BLOCK ARM CORTEX-M3 ETHERNET BLOCK DMA GPIO NVIC USB CLOCK DIVIDER system clock select (CLKSRCSEL) USB clock config (USBCLKCFG) CPU clock config (CCLKCFG) pllclk CCLK/8 CCLK/6 CCLK/4 CCLK/2 CCLK pclkWDT rtclk = 1Hz usbclk (48 MHz) cclk USB PLL USB PLL enable main PLL enable 32 kHz APB peripherals LPC17xx 002aad947LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 38 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.29.2 Main PLL (PLL0) The PLL0 accepts an input clock frequency in the range of 32 kHz to 25 MHz. The input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the CPU and/or the USB block. The PLL0 input, in the range of 32 kHz to 25 MHz, may initially be divided down by a value ‘N’, which may be in the range of 1 to 256. This input division provides a wide range of output frequencies from the same input frequency. Following the PLL0 input divider is the PLL0 multiplier. This can multiply the input divider output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to 550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a phase-frequency detector to compare the divided CCO output to the multiplier input. The error value is used to adjust the CCO frequency. The PLL0 is turned off and bypassed following a chip Reset and by entering Power-down mode. PLL0 is enabled by software only. The program must configure and activate the PLL0, wait for the PLL0 to lock, and then connect to the PLL0 as a clock source. 8.29.3 USB PLL (PLL1) The LPC17xx contain a second, dedicated USB PLL1 to provide clocking for the USB interface. The PLL1 receives its clock input from the main oscillator only and provides a fixed 48 MHz clock to the USB block only. The PLL1 is disabled and powered off on reset. If the PLL1 is left disabled, the USB clock will be supplied by the 48 MHz clock from the main PLL0. The PLL1 accepts an input clock frequency in the range of 10 MHz to 25 MHz only. The input frequency is multiplied up the range of 48 MHz for the USB clock using a Current Controlled Oscillators (CCO). It is insured that the PLL1 output has a 50 % duty cycle. 8.29.4 RTC clock output The LPC17xx feature a clock output function intended for synchronizing with external devices and for use during system development to allow checking the internal clocks CCLK, IRC clock, main crystal, RTC clock, and USB clock in the outside world. The RTC clock output allows tuning the RTC frequency without probing the pin, which would distort the results. 8.29.5 Wake-up timer The LPC17xx begin operation at power-up and when awakened from Power-down mode by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. When the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. This is important at power on, all types of Reset, and LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 39 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the wake-up timer. The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin code execution. When power is applied to the chip, or when some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. 8.29.6 Power control The LPC17xx support a variety of power control features. There are four special modes of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, Peripheral Power Control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Each of the peripherals has its own clock divider which provides even better power control. Integrated PMU (Power Management Unit) automatically adjust internal regulators to minimize power consumption during Sleep, Deep sleep, Power-down, and Deep power-down modes. The LPC17xx also implement a separate power domain to allow turning off power to the bulk of the device while maintaining operation of the RTC and a small set of registers for storing data during any of the power-down modes. 8.29.6.1 Sleep mode When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core. In Sleep mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 8.29.6.2 Deep-sleep mode In Deep-sleep mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Deep-sleep mode and the logic levels of chip pins remain static. The output of the IRC is disabled but the IRC is not powered down for a fast wake-up later. The RTC oscillator is not stopped because the RTC interrupts may be used as the wake-up source. The PLL is automatically turned off and disconnected. The CCLK and USB clock dividers automatically get reset to zero.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 40 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller The Deep-sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Deep-sleep mode reduces chip power consumption to a very low value. Power to the flash memory is left on in Deep-sleep mode, allowing a very quick wake-up. On wake-up from Deep-sleep mode, the code execution and peripherals activities will resume after 4 cycles expire if the IRC was used before entering Deep-sleep mode. If the main external oscillator was used, the code execution will resume when 4096 cycles expire. PLL and clock dividers need to be reconfigured accordingly. 8.29.6.3 Power-down mode Power-down mode does everything that Deep-sleep mode does, but also turns off the power to the IRC oscillator and the flash memory. This saves more power but requires waiting for resumption of flash operation before execution of code or data access in the flash memory can be accomplished. On the wake-up of Power-down mode, if the IRC was used before entering Power-down mode, it will take IRC 60 s to start-up. After this 4 IRC cycles will expire before the code execution can then be resumed if the code was running from SRAM. In the meantime, the flash wake-up timer then counts 4 MHz IRC clock cycles to make the 100 s flash start-up time. When it times out, access to the flash will be allowed. Users need to reconfigure the PLL and clock dividers accordingly. 8.29.6.4 Deep power-down mode The Deep power-down mode can only be entered from the RTC block. In Deep power-down mode, power is shut off to the entire chip with the exception of the RTC module and the RESET pin. The LPC17xx can wake up from Deep power-down mode via the RESET pin or an alarm match event of the RTC. 8.29.6.5 Wake-up interrupt controller The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up from any enabled priority interrupt that can occur while the clocks are stopped in Deep sleep, Power-down, and Deep power-down modes. The WIC works in connection with the Nested Vectored Interrupt Controller (NVIC). When the CPU enters Deep sleep, Power-down, or Deep power-down mode, the NVIC sends a mask of the current interrupt situation to the WIC.This mask includes all of the interrupts that are both enabled and of sufficient priority to be serviced immediately. With this information, the WIC simply notices when one of the interrupts has occurred and then it wakes up the CPU. The WIC eliminates the need to periodically wake up the CPU and poll the interrupts resulting in additional power savings. 8.29.7 Peripheral power control A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 41 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.29.8 Power domains The LPC17xx provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup Registers. On the LPC17xx, I/O pads are powered by the 3.3 V (VDD(3V3)) pins, while the VDD(REG)(3V3) pin powers the on-chip voltage regulator which in turn provides power to the CPU and most of the peripherals. Depending on the LPC17xx application, a design can use two power options to manage power consumption. The first option assumes that power consumption is not a concern and the design ties the VDD(3V3) and VDD(REG)(3V3) pins together. This approach requires only one 3.3 V power supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the I/O pad ring “on the fly” while keeping the CPU and peripherals alive. The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and a dedicated 3.3 V supply for the CPU (VDD(REG)(3V3)). Having the on-chip voltage regulator powered independently from the I/O pad ring enables shutting down of the I/O pad power supply “on the fly”, while the CPU and peripherals stay active. The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of power to operate, which can be supplied by an external battery. The device core power (VDD(REG)(3V3)) is used to operate the RTC whenever VDD(REG)(3V3) is present. Therefore, there is no power drain from the RTC battery when VDD(REG)(3V3) is available. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 42 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.30 System control 8.30.1 Reset Reset has four sources on the LPC17xx: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, causes the RSTOUT pin to go LOW and starts the wake-up timer (see description in Section 8.29.5). The wake-up timer ensures that reset remains asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the flash controller has completed its initialization. Once reset is de-asserted, or, in case of a BOD-triggered reset, once the voltage rises above the BOD threshold, the RSTOUT pin goes HIGH. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the Boot Block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. Fig 7. Power distribution REAL-TIME CLOCK BACKUP REGISTERS REGULATOR 32 kHz OSCILLATOR RTC POWER DOMAIN MAIN POWER DOMAIN 002aad978 RTCX1 VBAT VDD(REG)(3V3) RTCX2 VDD(3V3) VSS to memories, peripherals, oscillators, PLLs to core to I/O pads ADC DAC ADC POWER DOMAIN VDDA VREFP VREFN VSSA LPC17xx ULTRA LOW-POWER REGULATOR POWER SELECTORLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 43 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.30.2 Brownout detection The LPC17xx include 2-stage monitoring of the voltage on the VDD(REG)(3V3) pins. If this voltage falls below 2.2 V, the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. The second stage of low-voltage detection asserts reset to inactivate the LPC17xx when the voltage on the VDD(REG)(3V3) pins falls below 1.85 V. This reset prevents alteration of the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the power-on reset circuitry maintains the overall reset. Both the 2.2 V and 1.85 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.2 V detection to reliably interrupt, or a regularly executed event loop to sense the condition. 8.30.3 Code security (Code Read Protection - CRP) This feature of the LPC17xx allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. There are three levels of the Code Read Protection. CRP1 disables access to chip via the JTAG and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. CRP2 disables access to chip via the JTAG and only allows full flash erase and update using a reduced set of the ISP commands. Running an application with level CRP3 selected fully disables any access to chip via the JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too. It is up to the user’s application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART0. 8.30.4 APB interface The APB peripherals are split into two separate APB buses in order to distribute the bus bandwidth and thereby reducing stalls caused by contention between the CPU and the GPDMA controller. CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 44 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 8.30.5 AHB multilayer matrix The LPC17xx use an AHB multilayer matrix. This matrix connects the instruction (I-code) and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the main (32 kB) static RAM, and the Boot ROM. The GPDMA can also access all of these memories. The peripheral DMA controllers, Ethernet, and USB can access all SRAM blocks. Additionally, the matrix connects the CPU system bus and all of the DMA controllers to the various peripheral functions. 8.30.6 External interrupt inputs The LPC17xx include up to 46 edge sensitive interrupt inputs combined with up to four level sensitive external interrupt inputs as selectable pin functions. The external interrupt inputs can optionally be used to wake up the processor from Power-down mode. 8.30.7 Memory mapping control The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register contained in the NVIC. The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address space. The vector table must be located on a 128 word (512 byte) boundary because the NVIC on the LPC17xx is configured for 128 total interrupts. 8.31 Emulation and debugging Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four watch points.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 45 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 9. Limiting values [1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. c) The limiting values are stress ratings only. Operating the part at these values is not recommended, and proper operation is not guaranteed. The conditions for functional operation are specified in Table 8. [2] Maximum/minimum voltage above the maximum operating voltage (see Table 8) and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device. [3] See Table 19 for maximum operating voltage. [4] Including voltage on outputs in 3-state mode. [5] VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down. [6] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details. [7] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VDD(3V3) supply voltage (3.3 V) external rail [2] 0.5 +4.6 V VDD(REG)(3V3) regulator supply voltage (3.3 V) [2] 0.5 +4.6 V VDDA analog 3.3 V pad supply voltage [2] 0.5 +4.6 V Vi(VBAT) input voltage on pin VBAT for the RTC [2] 0.5 +4.6 V Vi(VREFP) input voltage on pin VREFP [2] 0.5 +4.6 V VIA analog input voltage on ADC related pins [2][3] 0.5 +5.1 V VI input voltage 5 V tolerant digital I/O pins; VDD 2.4 V [2][4] 0.5 +5.5 VI VDD = 0 V 0.5 +3.6 5 V tolerant open-drain pins PIO0_27 and PIO0_28 [2][5] 0.5 +5.5 IDD supply current per supply pin - 100 mA ISS ground current per ground pin - 100 mA Ilatch I/O latch-up current (0.5VDD(3V3)) < VI < (1.5VDD(3V3)); Tj < 125 C - 100 mA Tstg storage temperature [6] 65 +150 C Tj(max) maximum junction temperature 150 C Ptot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 W VESD electrostatic discharge voltage human body model; all pins [7] 4000 +4000 VLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 46 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 10. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: (1) • Tamb = ambient temperature (C) • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant in some applications. Table 7. Thermal resistance (15 %) Symbol Parameter Conditions Max/Min Unit LQFP100 Rth(j-a) thermal resistance from junction to ambient JEDEC (4.5 in 4 in); still air 38.01 C/W Single-layer (4.5 in 3 in); still air 55.09 C/W Rth(j-c) thermal resistance from junction to case 9.065 C/W TFBGA100 Rth(j-a) thermal resistance from junction to ambient JEDEC (4.5 in 4 in); still air 55.2 C/W Single-layer (4.5 in 3 in); still air 45.6 C/W Rth(j-c) thermal resistance from junction to case 9.5 C/W Tj Tamb PD Rth j a – += LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 47 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller 11. Static characteristics Table 8. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Supply pins VDD(3V3) supply voltage (3.3 V) external rail [2] 2.4 3.3 3.6 V VDD(REG)(3V3) regulator supply voltage (3.3 V) 2.4 3.3 3.6 V VDDA analog 3.3 V pad supply voltage [3][4] 2.5 3.3 3.6 V Vi(VBAT) input voltage on pin VBAT [5] 2.1 3.3 3.6 V Vi(VREFP) input voltage on pin VREFP [3] 2.5 3.3 VDDA V IDD(REG)(3V3) regulator supply current (3.3 V) active mode; code while(1){} executed from flash; all peripherals disabled; PCLK = CCLK⁄ 8 CCLK = 12 MHz; PLL disabled [6][7] - 7- mA CCLK = 100 MHz; PLL enabled [6][7] - 42- mA CCLK = 100 MHz; PLL enabled (LPC1769) [6][8] - 50- mA CCLK = 120 MHz; PLL enabled (LPC1769) [6][8] - 67- mA sleep mode [6][9] - 2- mA deep sleep mode [6][10] - 240 - A power-down mode [6][10] - 31 - A deep power-down mode; RTC running [11] - 630- nA IBAT battery supply current deep power-down mode; RTC running VDD(REG)(3V3) present [12] - 530- nA VDD(REG)(3V3) not present [13] - 1.1 - A IDD(IO) I/O supply current deep sleep mode [14][15] - 40- nA power-down mode [14][15] - 40- nA deep power-down mode [14] - 10- nALPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 48 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller IDD(ADC) ADC supply current active mode; ADC powered [16][17] - 1.95- mA ADC in Power-down mode [16][18] - <0.2 - A deep sleep mode [16] - 38- nA power-down mode [16] - 38- nA deep power-down mode [16] - 24- nA II(ADC) ADC input current on pin VREFP deep sleep mode [19] - 100- nA power-down mode [19] - 100- nA deep power-down mode [19] - 100- nA Standard port pins, RESET, RTCK IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD(3V3); on-chip pull-down resistor disabled - 0.5 10 nA IOZ OFF-state output current VO = 0 V; VO = VDD(3V3); on-chip pull-up/down resistors disabled - 0.5 10 nA VI input voltage pin configured to provide a digital function [20][21] [22] 0- 5.0 V VO output voltage output active 0 - VDD(3V3) V VIH HIGH-level input voltage 0.7VDD(3V3) --V VIL LOW-level input voltage - - 0.3VDD(3V3) V Vhys hysteresis voltage 0.4 - - V VOH HIGH-level output voltage IOH = 4 mA VDD(3V3) 0.4 --V VOL LOW-level output voltage IOL = 4 mA --0.4 V IOH HIGH-level output current VOH = VDD(3V3) 0.4 V 4 - - mA IOL LOW-level output current VOL = 0.4 V 4- - mA IOHS HIGH-level short-circuit output current VOH =0V [23] - - 45 mA IOLS LOW-level short-circuit output current VOL = VDD(3V3) [23] --50 mA Ipd pull-down current VI =5V 10 50 150 A Ipu pull-up current VI =0V 15 50 85 A VDD(3V3) < VI <5V 0 0 0 A Table 8. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max UnitLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9.5 — 24 June 2014 49 of 89 NXP Semiconductors LPC1769/68/67/66/65/64/63 32-bit ARM Cortex-M3 microcontroller [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] For USB operation 3.0 V VDD((3V3) 3.6 V. Guaranteed by design. [3] VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used. [4] VDDA for DAC specs are from 2.7 V to 3.6 V. I 2C-bus pins (P0[27] and P0[28]) VIH HIGH-level input voltage 0.7VDD(3V3) --V VIL LOW-level input voltage - - 0.3VDD(3V3) V Vhys hysteresis voltage - 0.05 VDD(3V3) - V VOL LOW-level output voltage IOLS = 3 mA --0.4 V ILI input leakage current VI = VDD(3V3) [24] - 24 A VI =5V - 10 22 A Oscillator pins Vi(XTAL1) input voltage on pin XTAL1 0.5 1.8 1.95 V Vo(XTAL2) output voltage on pin XTAL2 0.5 1.8 1.95 V Vi(RTCX1) input voltage on pin RTCX1 0.5 - 3.6 V Vo(RTCX2) output voltage on pin RTCX2 0.5 - 3.6 V USB pins (LPC1769/68/66/65/64 only) IOZ OFF-state output current 0V