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Farnell-Fairchild-2N4403-PDF.htm - Farnell Element 14
Farnell-Fairchild-2N4403-PDF.htm - Farnell Element 14
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Farnell Element 14 :
See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…
Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.
Puce électronique / Microchip :
Sans fil - Wireless :
Texas instrument :
Ordinateurs :
Logiciels :
Tutoriels :
Autres documentations :
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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1
15-V Digital or ±7.5-V Peak-to-Peak
Switching
125-Ω Typical On-State Resistance for 15-V
Operation
Switch On-State Resistance Matched to
Within 5 Ω Over 15-V Signal-Input Range
On-State Resistance Flat Over Full
Peak-to-Peak Signal Range
High On/Off Output-Voltage Ratio: 80 dB
Typical at fis = 10 kHz, RL = 1 kΩ
High Degree of Linearity: <0.5% Distortion
Typical at fis = 1 kHz, Vis = 5 V p-p,
VDD − VSS ≥ 10 V, RL = 10 kΩ
Extremely Low Off-State Switch Leakage,
Resulting in Very Low Offset Current and
High Effective Off-State Resistance: 10 pA
Typical at VDD − VSS = 10 V, TA = 25°C
Extremely High Control Input Impedance
(Control Circuit Isolated From Signal
Circuit): 1012 Ω Typical
Low Crosstalk Between Switches: −50 dB
Typical at fis = 8 MHz, RL = 1 kΩ
Matched Control-Input to Signal-Output
Capacitance: Reduces Output Signal
Transients
Frequency Response, Switch On = 40 MHz
Typical
100% Tested for Quiescent Current at 20 V
5-V, 10-V, and 15-V Parametric Ratings
Meets All Requirements of JEDEC Tentative
Standard No. 13-B, Standard Specifications
for Description of “B” Series CMOS
Devices
Applications:
− Analog Signal Switching/Multiplexing:
Signal Gating, Modulator, Squelch
Control, Demodulator, Chopper,
Commutating Switch
− Digital Signal Switching/Multiplexing
− Transmission-Gate Logic Implementation
− Analog-to-Digital and Digital-to-Analog
Conversion
− Digital Control of Frequency, Impedance,
Phase, and Analog-Signal Gain
description/ordering information
The CD4066B is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals.
It is pin-for-pin compatible with the CD4016B, but exhibits a much lower on-state resistance. In addition, the
on-state resistance is relatively constant over the full signal-input range.
The CD4066B consists of four bilateral switches, each with independent controls. Both the p and the n devices
in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 1, the well of the
n-channel device on each switch is tied to either the input (when the switch is on) or to VSS (when the switch
is off). This configuration eliminates the variation of the switch-transistor threshold voltage with input signal and,
thus, keeps the on-state resistance low over the full operating-signal range.
The advantages over single-channel switches include peak input-signal voltage swings equal to the full supply
voltage and more constant on-state impedance over the input-signal range. However, for sample-and-hold
applications, the CD4016B is recommended.
!" #!$% & "' Copyright 2003, Texas Instruments Incorporated &! #" #" (" " ") !"
& & * +' &! # " , &" " " %+ %!&" " , %% # " " '
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
SIG A IN/OUT
SIG A OUT/IN
SIG B OUT/IN
SIG B IN/OUT
CONTROL B
CONTROL C
VSS
VDD
CONTROL A
CONTROL D
SIG D IN/OUT
SIG D OUT/IN
SIG C OUT/IN
SIG C IN/OUT
E, F, M, NS, OR PW PACKAGE
(TOP VIEW)
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
ORDERING INFORMATION
TA PACKAGE† ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
CDIP − F Tube of 25 CD4066BF3A CD4066BF3A
PDIP − E Tube of 25 CD4066BE CD4066BE
Tube of 50 CD4066BM
−55°C to 125°C SOIC − M Reel of 2500 CD4066BM96 CD4066BM
−55°C to 125°C SOIC − M
Reel of 250 CD4066BMT
CD4066BM
SOP − NS Reel of 2000 CD4066BNSR CD4066B
TSSOP − PW
Tube of 90 CD4066BPW
CM066B
Reel of 2000 CD4066BPWR
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
† All control inputs are protected by the CMOS protection network.
NOTES: A. All p substrates are connected to VDD.
B. Normal operation control-line biasing: switch on (logic 1), VC = VDD; switch off (logic 0), VC = VSS
C. Signal-level range: VSS ≤ Vis ≤ VDD
Control
VC†
VDD
VSS
VSS
n
n
p
Out
Vos
Control
Switch
In
92CS-29113
p n
Vis
Figure 1. Schematic Diagram of One-of-Four Identical Switches and Associated Control Circuitry
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
DC supply-voltage range, VDD (voltages referenced to VSS terminal) −0.5 V to 20 V . . . . . . . . . . . . . . . . . . . .
Input voltage range, Vis (all inputs) −0.5 V to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DD + 0.5 V
DC input current, IIN (any one input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Package thermal impedance, θJA (see Note 1): E package 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C/W
M package 86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C/W
NS package 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C/W
PW package 113 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C/W
Lead temperature (during soldering):
At distance 1/16 ± 1/32 inch (1,59 ± 0,79 mm) from case for 10 s max 265 . . . . . . . . . . . . . . . . . . . . . . . °C
Storage temperature range, Tstg −65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
MIN MAX UNIT
VDD Supply voltage 3 18 V
TA Operating free-air temperature −55 125 °C
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics
LIMITS AT INDICATED TEMPERATURES
PARAMETER TEST CONDITIONS VIN VDD −55°C −40°C 85°C 125°C
PARAMETER TEST CONDITIONS 25°C UNIT VIN
(V)
VDD
(V) −55°C −40°C 85°C 125°C TYP MAX
UNIT
0, 5 5 0.25 0.25 7.5 7.5 0.01 0.25
IDD
Quiescent device 0, 10 10 0.5 0.5 15 15 0.01 0.5
IDD A Quiescent device
current 0, 15 15 1 1 30 30 0.01 1 µA current
0, 20 20 5 5 150 150 0.02 5
Signal Inputs (Vis) and Outputs (Vos)
VC = VDD,
RL = 10 kΩ returned
5 800 850 1200 1300 470 1050
ron On-state resistance
(max)
RL = 10 kΩ returned
to ,
VDD VSS
2 on 10 310 330 500 550 180 400 Ω (max) to ,
Vis = VSS to VDD
2
15 200 210 300 320 125 240
On-state resistance 5 15
∆ron
On-state resistance
difference between
any two switches
RL = 10 kΩ, VC = VDD ∆ron difference between 10 10 Ω
any two switches
RL = 10 kΩ, VC = VDD
15 5
Ω
THD Total harmonic
distortion
VC = VDD = 5 V, VSS = −5 V,
Vis(p-p) = 5 V (sine wave centered on 0 V),
RL = 10 kΩ, fis = 1-kHz sine wave
0.4 %
−3-dB cutoff
frequency
(switch on)
VC = VDD = 5 V, VSS = −5 V, Vis(p-p) = 5 V
(sine wave centered on 0 V), RL = 1 kΩ 40 MHz
−50-dB feedthrough
frequency (switch off)
VC = VSS = −5 V, Vis(p-p) = 5 V
(sine wave centered on 0 V), RL = 1 kΩ 1 MHz
Iis
Input/output leakage
current (switch off)
(max)
VC = 0 V, Vis = 18 V, Vos = 0 V;
and
VC = 0 V, Vis = 0 V, Vos = 18 V
18 ±0.1 ±0.1 ±1 ±1 ±10−5 ±0.1 µA
−50-dB crosstalk
frequency
VC(A) = VDD = 5 V,
VC(B) = VSS = −5 V,
Vis(A) = 5 Vp-p, 50-Ω source,
RL = 1 kΩ
8 MHz
Propagation delay
RL = 200 kΩ, VC = VDD,
VSS = GND, CL = 50 pF,
5 20 40
tpd
Propagation delay
(signal input to
signal output)
VSS = GND, CL = 50 pF,
Vis = 10 V
(square wave centered on 5 V),
pd (signal input to 10 10 20 ns
signal output)
is
(square wave centered on 5 V),
tr, tf = 20 ns 15 7 15
Cis Input capacitance VDD = 5 V, VC = VSS = −5 V 8 pF
Cos Output capacitance VDD = 5 V, VC = VSS = −5 V 8 pF
Cios Feedthrough VDD = 5 V, VC = VSS = −5 V 0.5 pF
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5
electrical characteristics (continued)
LIMITS AT INDICATED TEMPERATURES
CHARACTERISTIC TEST CONDITIONS VDD −55°C −40°C 85°C 125°C
CHARACTERISTIC TEST CONDITIONS 25°C UNIT VDD
(V) −55°C −40°C 85°C 125°C TYP MAX
UNIT
Control (VC)
Control input, |Iis| < 10 µA, 5 1 1 1 1 1
VILC
Control input,
low voltage (max)
|Iis| < 10 µA,
Vis = VSS, VOS = VDD, and
V = V , V = V
VILC 10 2 2 2 2 2 V low voltage (max) Vis = VSS, VOS = VDD, and
Vis = VDD, VOS = VSS 15 2 2 2 2 2
V
Control input,
5 3.5 (MIN)
VIHC high voltage VIHC See Figure 6 10 7 (MIN) V high voltage See Figure 6
15 11 (MIN)
V
IIN Input current (max) Vis ≤ VDD, VDD − VSS = 18 V,
VCC ≤ VDD − VSS
18 ±0.1 ±0.1 ±1 ±1 ±10−5 ±0.1 µA
Crosstalk (control input
to signal output)
VC = 10 V (square wave),
tr, tf = 20 ns, RL = 10 kΩ 10 50 mV
Turn-on and turn-off VIN = VDD, tr, tf = 20 ns,
5 35 70
Turn-on and turn-off
propagation delay
VIN = VDD, tr, tf = 20 ns,
CL = 50 pF, RL = 1 kΩ 10 20 40 ns propagation delay CL = 50 pF, RL = 1 kΩ
15 15 30
ns
Vis = VDD, VSS = GND,
RL = 1 kΩ to GND, CL = 50 pF,
5 6
Maximum control input
repetition rate
RL = 1 kΩ to GND, CL = 50 pF,
VC = 10 V (square wave
centered on 5 V), tr, tf = 20 ns,
10 9 MHz repetition rate C
centered on 5 V), tr, tf = 20 ns,
Vos = 1/2 Vos at 1 kHz 15 9.5
CI Input capacitance 5 7.5 pF
switching characteristics
VDD
SWITCH INPUT SWITCH
VDD OUTPUT, Vos
(V) Vis
(V)
Iis (mA)
OUTPUT, Vos (V) (V) Vis
(V) −55°C −40°C 25°C 85°C 125°C MIN MAX
5 0 0.64 0.61 0.51 0.42 0.36 0.4
5 5 −0.64 −0.61 −0.51 −0.42 −0.36 4.6
10 0 1.6 1.5 1.3 1.1 0.9 0.5
10 10 −1.6 −1.5 −1.3 −1.1 −0.9 9.5
15 0 4.2 4 3.4 2.8 2.4 1.5
15 15 −4.2 −4 −3.4 −2.8 −2.4 13.5
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Vis − Input Signal Voltage − V
600
500
400
300
200
100
0
−4 −3 −2 −1 0 1 2 3 4
TYPICAL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE (ALL TYPES)
92CS-27326RI
Figure 2
TA = 125°C
+25°C
−55°C
Supply Voltage (VDD − VSS) = 5 V
− Channel On-State Resistance − on
Ω r
Figure 3
TYPICAL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE (ALL TYPES)
300
250
200
150
100
50
0
−10 −7.5 −5 −2.5 0 2.5 5 7.5 10
Supply Voltage (VDD − VSS) = 10 V
TA = 125°C
Vis − Input Signal Voltage − V
+25°C
−55°C
92CS-27327RI
− Channel On-State Resistance − on
Ω r
Vis − Input Signal Voltage − V
TYPICAL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE (ALL TYPES)
Figure 4
300
250
200
150
100
50
0
−10 −7.5 −5 −2.5 0 2.5 5 7.5 10
Supply Voltage (VDD − VSS) = 15 V
TA = 125°C
+25°C
−55°C
92CS-27329RI
− Channel On-State Resistance − on
Ω r
Vis − Input Signal Voltage − V
Figure 5
TYPICAL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE (ALL TYPES)
600
500
400
300
200
100
0
−10 −7.5 −5 −2.5 0 2.5 5 7.5 10
Supply Voltage (VDD − VSS) = 5 V
TA = 125°C
10 V
−15 V
92CS-27330RI
− Channel On-State Resistance − on
Ω r
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7
TYPICAL CHARACTERISTICS
CD4066B
1 of 4 Switches
Iis Vis Vos
92CS-30966
|Vis − Vos|
|Iis| ron =
Figure 6. Determination of ron as a Test Condition for Control-Input High-Voltage (VIHC) Specification
X-Y
Plotter
1-kΩ
Range
TG
On
Keithley
160 Digital
Multimeter
H. P.
Moseley
7030A
X
VSS
VDD
10 kΩ
92CS-22716
Y
Figure 7. Channel On-State Resistance Measurement Circuit
Figure 8
TYPICAL ON CHARACTERISTICS
FOR 1 OF 4 CHANNELS
3
2
1
0
−1
−2
−3
−3 −2 −1 0 1 2 3 4
VI − Input Voltage − V
92CS-30919
Output Voltage − V V −
VC = VDD VDD
Vis
Vos
RL
VSS
All unused terminals are
connected to VSS
CD4066B
1 of 4
Switches
O
Figure 9
10 102 103 10
101
102
103
104
f − Switching Frequency − kHz
POWER DISSIPATION PER PACKAGE
vs
SWITCHING FREQUENCY
TA = 25°C
Power Dissipation Per Package − W
D µ
6
4
2
6
4
2
6
4
2
6
4
2
2 46 2 46
92C-30920
5 V
10 V
VSS
VDD
5
6
13
12
7
CD4066B
P −
14
Supply Voltage
(VDD) = 15 V
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
V VDD = 5 V C = −5 V
VSS = −5 V
Cios
Cis Cos
CD4066B
1 of 4
Switches
Measured on Boonton capacitance bridge, model 75a (1 MHz);
test-fixture capacitance nulled out.
92CS-30921
Figure 10. Typical On Characteristics
for One of Four Channels
VDD VC = VSS
Vos
VSS
CD4066B
1 of 4
Switches
Vis = VDD
I
92CS-30922
Figure 11. Off-Switch Input or Output Leakage
All unused terminals are connected to VSS.
VDD VC = VDD
Vos
VSS
CD4066B
1 of 4
Switches
Vis
Figure 12. Propagation Delay Time Signal Input
(Vis) to Signal Output (Vos)
92CS-30923
200 kΩ
50 pF
VDD
tr = tf = 20 ns
All unused terminals are connected to VSS.
VC VDD
Vos
VSS
CD4066B
1 of 4
Switches
Vis
Figure 13. Crosstalk-Control Input
to Signal Output
+10 V
tr = tf = 20 ns
92CS-30924
1 kΩ 10 kΩ
All unused terminals are connected to VSS.
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9
TYPICAL CHARACTERISTICS
VDD
VC = VDD
Vos
VSS
CD4066B
1 of 4
Switches
VDD
92CS-30925
1 kΩ
50 pF
VDD
NOTES: A. All unused terminals are connected to VSS.
B. Delay is measured at Vos level of +10% from ground (turn-on) or on-state output level (turn-off).
tr = tf = 20 ns
Figure 14. Propagation Delay, tPLH, tPHL Control-Signal Output
VDD = 10 V
VC
VSS
CD4066B
1 of 4
Switches
Vis = 10 V
92CS-30925
50 pF 1 kΩ
tr = tf = 20 ns
VC
Vos
90%
10%
All unused terminals are connected to VSS.
VOS VOS at 1 kHz
2
VOS VOS at 1 kHz
2
Repetition
Rate
50%
tr tf
10 V
0 V
Figure 15. Maximum Allowable Control-Input Repetition Rate
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Inputs
VSS
Measure inputs sequentially to both VDD and VSS. Connect all unused inputs to either VDD or VSS. Measure control inputs only.
I
VSS
VDD
92CS-27555
Figure 16. Input Leakage-Current Test Circuit
VDD
Channel 1
Channel 2
Channel 3
Channel 4
Channel 1
Channel 2
Channel 3
Channel 4
1/4 CD4066B CD4066B
CD4066B
CD4018B CD4018B
1/4 CD4066B
CD4001B
LPF
LPF
LPF
LPF
1
10 2 3 7 9 12
5 4
14
15 13
1 2
3
5
2
4
1
2
5
6
8
9
12
13
3
4
10
1
8
4
11
11
12
6 5 13
9
10
2
3
10 2 3 7 9 12
14
15
1
5 4
7
9
6
10
13 12 9 8 6 5 2 1
11 10 4 3
12 6 5 11
11 12
5
4 3 8
11
4
1
2
3
9
10
PE J1 J2 J3 J4 J5
Q1 Q2
1/3 CD4049B
CD4001B
Signal
Inputs
Clock
Reset
Package Count
2 - CD4001B
1 - CD4049B
3 - CD4066B
2 - CD4018B
1/3 CD4049B
1/6 CD4049B 10 k
Signal
Outputs
PE J1 J2 J3 J4 J5
Q1 Q2
External
Reset
Clock
Chan 1 Chan 2 Chan 3 Chan 4
VDD
30% (VDD − VSS)
Clock Maximum
Allowable
Signal Level VSS
92CM-30928
Ω
10 kΩ
10 kΩ
10 kΩ
10 kΩ
Figure 17. Four-Channel PAM Multiplex System Diagram
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11
TYPICAL CHARACTERISTICS
SWA
SWB
SWC
SWD
92CS-30927
Analog Inputs (±5 V)
VDD = 5 V
VDD = 5 V
5 V
−5 V
5 V CD4066B
Analog Outputs (±5 V)
VSS = −5 V
CD4054B
VSS = 0 V
VEE = −5 V
IN
0
Digital
Control
Inputs
0
Figure 18. Bidirectional Signal Transmission Via Digital Control Logic
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
In applications that employ separate power sources to drive VDD and the signal inputs, the VDD current capability
should exceed VDD/RL (RL = effective external load of the four CD4066B bilateral switches). This provision avoids
any permanent current flow or clamp action on the VDD supply when power is applied or removed from the CD4066B.
In certain applications, the external load-resistor current can include both VDD and signal-line components. To avoid
drawing VDD current when switch current flows into terminals 1, 4, 8, or 11, the voltage drop across the bidirectional
switch must not exceed 0.8 V (calculated from ron values shown).
No VDD current will flow through RL if the switch current flows into terminals 2, 3, 9, or 10.
PACKAGE OPTION ADDENDUM
www.ti.com 29-Mar-2015
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
CD4066BE ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU | CU SN N / A for Pkg Type -55 to 125 CD4066BE
CD4066BEE4 ACTIVE PDIP N 14 25 Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type -55 to 125 CD4066BE
CD4066BF ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 CD4066BF
CD4066BF3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 CD4066BF3A
CD4066BF3AS2283 OBSOLETE CDIP J 14 TBD Call TI Call TI
CD4066BF3AS2534 OBSOLETE CDIP J 14 TBD Call TI Call TI
CD4066BM ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM
CD4066BM96 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 CD4066BM
CD4066BM96E4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM
CD4066BM96G4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM
CD4066BME4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM
CD4066BMG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM
CD4066BMT ACTIVE SOIC D 14 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM
CD4066BNSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066B
CD4066BPW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM066B
CD4066BPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM066B
CD4066BPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 CM066B
CD4066BPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM066B
PACKAGE OPTION ADDENDUM
www.ti.com 29-Mar-2015
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
JM38510/05852BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
05852BCA
M38510/05852BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
05852BCA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 29-Mar-2015
Addendum-Page 3
OTHER QUALIFIED VERSIONS OF CD4066B, CD4066B-MIL :
•
Catalog: CD4066B
•
Automotive: CD4066B-Q1, CD4066B-Q1
•
Military: CD4066B-MIL
NOTE: Qualified Version Definitions:
•
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
CD4066BM96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4066BM96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4066BM96 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1
CD4066BM96G4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4066BM96G4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4066BMT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD4066BNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD4066BPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Apr-2014
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD4066BM96 SOIC D 14 2500 333.2 345.9 28.6
CD4066BM96 SOIC D 14 2500 367.0 367.0 38.0
CD4066BM96 SOIC D 14 2500 364.0 364.0 27.0
CD4066BM96G4 SOIC D 14 2500 367.0 367.0 38.0
CD4066BM96G4 SOIC D 14 2500 333.2 345.9 28.6
CD4066BMT SOIC D 14 250 367.0 367.0 38.0
CD4066BNSR SO NS 14 2000 367.0 367.0 38.0
CD4066BPWR TSSOP PW 14 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 7-Apr-2014
Pack Materials-Page 2
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2015, Texas Instruments Incorporated
TAS5707, TAS5707A
www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009
20-W STEREO DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC
Check for Samples: TAS5707 TAS5707A
1FEATURES
23• Audio Input/Output Night-Mode Listening
– 20-W Into an 8-Ω Load From an 18-V Supply – Autobank Switching: Preload Coefficients
– Wide PVDD Range, From 8 V to 26 V for Different Sample Rates. No Need to
Write New Coefficients to the Part When
– Efficient Class-D Operation Eliminates Sample Rate Changes. Need for Heatsinks
– Autodetect: Automatically Detects
– Requires Only 3.3 V and PVDD Sample-Rate Changes. No Need for
– One Serial Audio Input (Two Audio External Microprocessor Intervention Channels)
– Supports 8-kHz to 48-kHz Sample Rate APPLICATIONS
(LJ/RJ/I2S) • Television
• Audio/PWM Processing • iPod™ Dock
– Independent Channel Volume Controls With • Sound Bar
24 dB to Mute
– Soft Mute (50% Duty Cycle) DESCRIPTION
– Programmable Dynamic Range Control The TAS5707 is a 20-W, efficient, digital-audio power
– 14 Programmable Biquads for Speaker EQ amplifier for driving stereo bridge-tied speakers. One
and Other Audio Processing Features serial data input allows processing of up to two
discrete audio channels and seamless integration to
– Programmable Coefficients for DRC Filters most digital audio processors and MPEG decoders.
– DC Blocking Filters The device accepts a wide range of input data and
• General Features data rates. A fully programmable data path routes
these channels to the internal speaker drivers.
– Serial Control Interface Operational Without
MCLK The TAS5707 is a slave-only device receiving all
clocks from external sources. The TAS5707 operates – Factory-Trimmed Internal Oscillator for
with a PWM carrier between a 384-kHz switching rate Automatic Rate Detection and 352-KHz switching rate, depending on the input
– Surface Mount, 48-PIN, 7-mm × 7-mm sample rate. Oversampling combined with a
HTQFP Package fourth-order noise shaper provides a flat noise floor
– Thermal and Short-Circuit Protection and excellent dynamic range from 20 Hz to 20 kHz..
• Benefits The TAS5707A is identical in function to the HTQFP
packaged TAS5707, but has a unique I
2
– EQ: Speaker Equalization Improves Audio C device
Performance address. The address of the TAS5707 is 0x36. The
address of the TAS5707A is 0x3A.
– DRC: Dynamic Range Compression. Can
Be Used As Power Limiter. Enables
Speaker Protection, Easy Listening,
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2iPod is a trademark of Apple Inc.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SDIN
LRCLK
SCLK
MCLK
RESET
PDN
SDA
PLL_FLTM
PLL_FLTP
AVDD/DVDD PVDD
OUT_A
OUT_C
OUT_B
OUT_D
BST_A
BST_C
BST_B
BST_D
3.3 V 8 V–26 V
SCL
Digital
Audio
Source
I C
Control
2
Control
Inputs
LC
LC
Left
Right
B0264-11
Loop
Filter(1)
TAS5707, TAS5707A
SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
SIMPLIFIED APPLICATION DIAGRAM
(1)See user's guide for loop-filter details.
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Product Folder Link(s): TAS5707 TAS5707A
SDIN
MCLK
SCLK
LRCLK
Serial
Audio
Port
7 BQ L
R
V
O
L
U
M
E
DRC
Protection
Logic
Click and Pop
Control
7 BQ
SDA
SCL
4
Order
th
Noise
Shaper
and
PWM
S
R
C
mDAP
Sample Rate
Autodetect
and PLL
Serial
Control
Microcontroller
Based
System
Control
Terminal Control
OUT_A
OUT_B
2 HB ´
FET Out
OUT_C
OUT_D
2 HB ´
FET Out
B0262-02
TAS5707, TAS5707A
www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009
FUNCTIONAL VIEW
Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TAS5707 TAS5707A
Temp.
Sense
VALID
FAULT
AGND
OC_ADJ
Power
On
Reset
Undervoltage
Protection
GND
PWM_D
OUT_D
PGND_CD
PVDD_D
BST_D
Gate
Drive
PWM
Rcv
Overcurrent
Protection
4
Protection
and
I/O Logic
PWM_C
OUT_C
PGND_CD
PVDD_C
BST_C
Timing Gate
Drive Ctrl PWM
Rcv
GVDD_CD
PWM_B
OUT_B
PGND_AB
PVDD_B
BST_B
Timing Gate
Drive Ctrl PWM
Rcv
PWM_A
OUT_A
PGND_AB
PVDD_A
BST_A
Timing Gate
Drive Ctrl PWM
Rcv
GVDD_AB
Ctrl
Pulldown Resistor
Pulldown Resistor
Pulldown Resistor
Pulldown Resistor
4
GVDD_CD
Regulator
GVDD_AB
Regulator
Timing
I
sense
B0034-05
PWM Controller
FAULT
TAS5707, TAS5707A
SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com
Figure 1. Power Stage Functional Block Diagram
4 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): TAS5707 TAS5707A
Vol1
R
L
7 BQ EQ ´
´
ealpha
ealpha
´
´
7 BQ EQ
Input Muxing
Vol2
B0341-01
1
Energy
MAXMUX
Attack
Decay DRC1
DRC
ON/OFF
50[D7]
30–36
29–2F
3A
3A
3B–3C
46[D0]
To PWM
Hex numbers refer to I2C subaddresses
[Di] = bit "i" of subaddress
SSTIMER
OC_ADJ
PLL_FLTP
VR_ANA
NC
AVSS
PLL_FLTM
BST_A
GVDD_OUT
PVDD_A
OUT_A
RESET
PVDD_A
STEST
PDN
VR_DIG
OSC_RES
DVSSO
DVDD
FAULT
MCLK
SCLK
SDIN
LRCLK
AVDD
SDA
SCL
DVSS
GND
VREG
PVDD_B
BST_B
PVDD_C
OUT_C
PVDD_D
BST_D
PGND_AB
OUT_B
PGND_CD
OUT_D
AGND
PGND_AB
PVDD_B
PGND_CD
PVDD_D
BST_C
PVDD_C
GVDD_OUT
P0075-01
PHP Package
(Top View)
TAS5707
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
25
26
27
28
29
30
31
32
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
TAS5707, TAS5707A
www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009
DAP Process Structure
48-TERMINAL, HTQFP PACKAGE (TOP VIEW)
Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TAS5707 TAS5707A
TAS5707, TAS5707A
SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com
PIN FUNCTIONS
PIN TYPE 5-V TERMINATION
(1) DESCRIPTION TOLERANT (2) NAME NO.
AGND 30 P Analog ground for power stage
AVDD 13 P 3.3-V analog power supply
AVSS 9 P Analog 3.3-V supply ground
BST_A 4 P High-side bootstrap supply for half-bridge A
BST_B 43 P High-side bootstrap supply for half-bridge B
BST_C 42 P High-side bootstrap supply for half-bridge C
BST_D 33 P High-side bootstrap supply for half-bridge D
DVDD 27 P 3.3-V digital power supply
DVSSO 17 P Oscillator ground
DVSS 28 P Digital ground
FAULT 14 DO Backend error indicator. Asserted LOW for over temperature, over
current, over voltage, and under voltage error conditions. De-asserted
upon recovery from error condition.
GND 29 P Analog ground for power stage
GVDD_OUT 5, 32 P Gate drive internal regulator output
LRCLK 20 DI 5-V Pulldown Input serial audio data left/right clock (sample rate clock)
MCLK 15 DI 5-V Pulldown Master clock input
NC 8 – No connection
OC_ADJ 7 AO Analog overcurrent programming. Requires resistor to ground.
OSC_RES 16 AO Oscillator trim resistor. Connect an 18.2-kΩ 1% resistor to DVSSO.
OUT_A 1 O Output, half-bridge A
OUT_B 46 O Output, half-bridge B
OUT_C 39 O Output, half-bridge C
OUT_D 36 O Output, half-bridge D
PDN 19 DI 5-V Pullup Power down, active-low. PDN prepares the device for loss of power
supplies by shutting down the noise shaper and initiating PWM stop
sequence.
PGND_AB 47, 48 P Power ground for half-bridges A and B
PGND_CD 37, 38 P Power ground for half-bridges C and D
PLL_FLTM 10 AO PLL negative loop filter terminal
PLL_FLTP 11 AO PLL positive loop filter terminal
PVDD_A 2, 3 P Power supply input for half-bridge output A
PVDD_B 44, 45 P Power supply input for half-bridge output B
PVDD_C 40, 41 P Power supply input for half-bridge output C
PVDD_D 34, 35 P Power supply input for half-bridge output D
RESET 25 DI 5-V Pullup Reset, active-low. A system reset is generated by applying a logic low
to this pin. RESET is an asynchronous control signal that restores the
DAP to its default conditions, and places the PWM in the hard mute
state (tristated).
SCL 24 DI 5-V I
2C serial control clock input
SCLK 21 DI 5-V Pulldown Serial audio data clock (shift clock). SCLK is the serial audio port input
data bit clock.
SDA 23 DIO 5-V I
2C serial control data interface input/output
SDIN 22 DI 5-V Pulldown Serial audio data input. SDIN supports three discrete (stereo) data
formats.
(1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
(2) All pullups are weak pullups and all pulldowns are weak pulldowns. The pullups and pulldowns are included to assure proper input logic
levels if the pins are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input).
6 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): TAS5707 TAS5707A
TAS5707, TAS5707A
www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009
PIN FUNCTIONS (continued)
PIN TYPE 5-V TERMINATION
(1) DESCRIPTION TOLERANT (2) NAME NO.
SSTIMER 6 AI Controls ramp time of OUT_X to minimize pop. Leave this pin floating
for BD mode. Requires capacitor of 2.2 nF to GND in AD mode. The
capacitor determines the ramp time.
STEST 26 DI Factory test pin. Connect directly to DVSS.
VR_ANA 12 P Internally regulated 1.8-V analog supply voltage. This pin must not be
used to power external devices.
VR_DIG 18 P Internally regulated 1.8-V digital supply voltage. This pin must not be
used to power external devices.
VREG 31 P Digital regulator output. Not to be used for powering external circuitry.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE UNIT
DVDD, AVDD –0.3 to 3.6 V
Supply voltage
PVDD_X –0.3 to 30 V
OC_ADJ –0.3 to 4.2 V
3.3-V digital input –0.5 to DVDD + 0.5 V
Input voltage
5-V tolerant(2) digital input (except MCLK) –0.5 to DVDD + 2.5(3) V
5-V tolerant MCLK input –0.5 to AVDD + 2.5(3) V
OUT_x to PGND_X 32(4) V
BST_x to PGND_X 43(4) V
Input clamp current, IIK ±20 mA
Output clamp current, IOK ±20 mA
Operating free-air temperature 0 to 85 °C
Operating junction temperature range 0 to 150 °C
Storage temperature range, Tstg –40 to 125 °C
(1) Stresses beyond those listed under absolute ratings may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under recommended operation conditions are
not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
(2) 5-V tolerant inputs are PDN, RESET, SCLK, LRCLK, MCLK, SDIN, SDA, and SCL.
(3) Maximum pin voltage should not exceed 6.0Vele
(4) DC voltage + peak ac waveform measured at the pin should be below the allowed limit for all conditions.
DISSIPATION RATINGS(1)
DERATING FACTOR TA ≤ 25°C TA = 45°C TA = 70°C
PACKAGE ABOVE TA = 25°C POWER RATING POWER RATING POWER RATING
7-mm × 7-mm HTQFP 40 mW/°C 5 W 4.2 W 3.2 W
(1) This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must
be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SLMA002 for more information about using the
HTQFP thermal pad
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
Digital/analog supply voltage DVDD, AVDD 3 3.3 3.6 V
Half-bridge supply voltage PVDD_X 8 26 V
VIH High-level input voltage 5-V tolerant 2 V
VIL Low-level input voltage 5-V tolerant 0.8 V
TA Operating ambient temperature range 0 85 °C
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TAS5707, TAS5707A
SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com
RECOMMENDED OPERATING CONDITIONS (continued)
MIN NOM MAX UNIT
TJ
(1) Operating junction temperature range 0 125 °C
RL (BTL) Load impedance Output filter: L = 15 μH, C = 680 nF. 6 8 Ω
Minimum output inductance under 10 LO (BTL) Output-filter inductance μH
short-circuit condition
(1) Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device.
PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS
PARAMETER TEST CONDITIONS VALUE UNIT
11.025/22.05/44.1-kHz data rate ±2% 352.8 kHz
Output sample rate
48/24/12/8/16/32-kHz data rate ±2% 384
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Product Folder Link(s): TAS5707 TAS5707A
TAS5707, TAS5707A
www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009
PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fMCLKI MCLK Frequency 2.8224 24.576 MHz
MCLK duty cycle 40% 50% 60%
tr /
Rise/fall time for MCLK 5 ns tf(MCLK)
LRCLK allowable drift before LRCLK reset 4 MCLKs
External PLL filter capacitor C1 SMD 0603 Y5V 47 nF
External PLL filter capacitor C2 SMD 0603 Y5V 4.7 nF
External PLL filter resistor R SMD 0603, metal film 470 Ω
ELECTRICAL CHARACTERISTICS
DC Characteristics
TA = 25°, PVCC_X = 18V, DVDD = AVDD = 3.3V, RL= 8Ω, BTL AD Mode, FS = 48KHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage FAULTZ and SDA IOH = –4 mA 2.4 V
DVDD = AVDD = 3 V
VOL Low-level output voltage FAULTZ and SDA IOL = 4 mA 0.5 V
DVDD = AVDD = 3 V
VI < VIL ; DVDD = AVDD 75 IIL Low-level input current μA
= 3.6V
VI > VIH ; DVDD = 75 IIH High-level input current μA
AVDD = 3.6V
Normal Mode 48 83
3.3 V supply voltage (DVDD, IDD 3.3 V supply current Reset (RESET = low, 24 32 mA AVDD)
PDN = high)
Normal Mode 30 55
IPVDD Half-bridge supply current No load (PVDD_X) Reset (RESET = low, 5 13 mA
PDN = high)
Drain-to-source resistance, LS TJ = 25°C, includes metallization resistance 180
rDS(on)
(1) Drain-to-source resistance, mΩ
TJ = 25°C, includes metallization resistance 180 HS
I/O Protection
Vuvp Undervoltage protection limit PVDD falling 7.2 V
Vuvp,hyst Undervoltage protection limit PVDD rising 7.6 V
OTE(2) Overtemperature error 150 °C
Extra temperature drop OTEHYST
(2) 30 °C
required to recover from error
OTW Overtemperature warning 125 °C
Temperature drop required to OTWHYST 25 °C
recover from warning
OLPC Overload protection counter fPWM = 384 kHz 0.63 ms
IOC Overcurrent limit protection Resistor—programmable, max. current, ROCP = 22 kΩ 4.5 A
IOCT Overcurrent response time 150 ns
OC programming resistor Resistor tolerance = 5% for typical value; the minimum ROCP 20 22 kΩ
range resistance should not be less than 20 kΩ.
Internal pulldown resistor at Connected when drivers are tristated to provide bootstrap RPD 3 kΩ the output of each half-bridge capacitor charge.
(1) This does not include bond-wire or pin resistance.
(2) Specified by design
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TAS5707, TAS5707A
SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com
AC Characteristics (BTL)
PVDD_X = 18 V, BTL AD mode, FS = 48 KHz, RL = 8 Ω, ROCP = 22 KΩ, CBST = 33 nF, audio frequency = 1 kHz, AES17 filter,
fPWM = 384 kHz, TA = 25°C (unless otherwise noted). All performance is in accordance with recommended operating
conditions, unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PVDD = 18 V,10% THD, 1-kHz input signal 20.6
PVDD = 18 V, 7% THD, 1-kHz input signal 19.5
PVDD = 12 V, 10% THD, 1-kHz input 9.4
P signal O Power output per channel W
PVDD = 12 V, 7% THD, 1-kHz input signal 8.9
PVDD = 8 V, 10% THD, 1-kHz input signal 4.1
PVDD = 8 V, 7% THD, 1-kHz input signal 3.8
PVDD= 18 V; PO = 1 W 0.06%
THD+N Total harmonic distortion + noise PVDD= 12 V; PO = 1 W 0.13%
PVDD= 8 V; PO = 1 W 0.2%
Vn Output integrated noise (rms) A-weighted 56 μV
PO = 0.25 W, f = 1kHz (BD Mode) –82 dB
Crosstalk
PO = 0.25 W, f = 1kHz (AD Mode) -69 dB
A-weighted, f = 1 kHz, maximum power at SNR Signal-to-noise ratio (1) 106 dB THD < 1%
(1) SNR is calculated relative to 0-dBFS input level.
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Product Folder Link(s): TAS5707 TAS5707A
th1
t
su1
t
(edge)
t
su2
th2
SCLK
(Input)
LRCLK
(Input)
SDIN
T0026-04
t
r
t
f
TAS5707, TAS5707A
www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009
SERIAL AUDIO PORTS SLAVE MODE
over recommended operating conditions (unless otherwise noted)
TEST PARAMETER MIN TYP MAX UNIT CONDITIONS
fSCLKIN Frequency, SCLK 32 × fS, 48 × fS, 64 × fS CL = 30 pF 1.024 12.288 MHz
tsu1 Setup time, LRCLK to SCLK rising edge 10 ns
th1 Hold time, LRCLK from SCLK rising edge 10 ns
tsu2 Setup time, SDIN to SCLK rising edge 10 ns
th2 Hold time, SDIN from SCLK rising edge 10 ns
LRCLK frequency 8 48 48 kHz
SCLK duty cycle 40% 50% 60%
LRCLK duty cycle 40% 50% 60%
SCLK SCLK rising edges between LRCLK rising edges 32 64 edges
t(edge) SCLK LRCLK clock edge with respect to the falling edge of SCLK –1/4 1/4 period
tr / ns Rise/fall time for SCLK/LRCLK 8
tf(SCLK/LRCLK)
Figure 2. Slave Mode Serial Data Interface Timing
Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TAS5707 TAS5707A
SCL
SDA
tw(H) tw(L) t
r
t
f
t
su1 th1
T0027-01
SCL
SDA
th2 t
(buf)
t
su2 t
su3
Start
Condition
Stop
Condition
T0028-01
TAS5707, TAS5707A
SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com
I
2C SERIAL CONTROL PORT OPERATION
Timing characteristics for I
2C Interface signals over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
fSCL Frequency, SCL No wait states 400 kHz
tw(H) Pulse duration, SCL high 0.6 μs
tw(L) Pulse duration, SCL low 1.3 μs
tr Rise time, SCL and SDA 300 ns
tf Fall time, SCL and SDA 300 ns
tsu1 Setup time, SDA to SCL 100 ns
th1 Hold time, SCL to SDA 0 ns
t(buf) Bus free time between stop and start condition 1.3 μs
tsu2 Setup time, SCL to start condition 0.6 μs
th2 Hold time, start condition to SCL 0.6 μs
tsu3 Setup time, SCL to stop condition 0.6 μs
CL Load capacitance for each bus line 400 pF
Figure 3. SCL and SDA Timing
Figure 4. Start and Stop Conditions Timing
12 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): TAS5707 TAS5707A
tw(RESET)
RESET
td(I2C_ready)
System Initialization.
Enable via I C. 2
T0421-01
I C Active 2
I C Active 2
f − Frequency − Hz
20
PVDD = 18 V
RL = 8 Ω
100 1k 10k
THD+N − Total Harmonic Distortion + Noise − %
20k
G001
P = 1 W
P = 5 W
0.001
0.01
10
0.1
1
f − Frequency − Hz
20
PVDD = 12 V
RL = 8 Ω
100 1k 10k
THD+N − Total Harmonic Distortion + Noise − %
20k
G002
P = 2.5 W
0.001
0.01
10
0.1
1
P = 0.5 W
TAS5707, TAS5707A
www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009
RESET TIMING (RESET)
Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to Recommended
Use Model section on usage of all terminals.
PARAMETER MIN TYP MAX UNIT
tw(RESET) Pulse duration, RESET active 100 us
td(I2C_ready) Time to enable I
2C 13.5 ms
NOTE: On power up, it is recommended that the TAS5707 RESET be held LOW for at least 100 μs after DVDD has reached
3.0 V
NOTE: If the RESET is asserted LOW while PDN is LOW, then the RESET must continue to be held LOW for at least 100 μs
after PDN is deasserted (HIGH).
Figure 5. Reset Timing
TYPICAL CHARACTERISTICS, BTL CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs vs
FREQUENCY FREQUENCY
Figure 6. Figure 7.
Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TAS5707 TAS5707A
f − Frequency − Hz
20
PVDD = 8 V
RL = 8 Ω
100 1k 10k
THD+N − Total Harmonic Distortion + Noise − %
20k
G003
P = 0.5 W P = 1 W
0.001
0.01
10
0.1
1 P = 2.5 W
PO − Output Power − W
0.01
PVDD = 18 V
RL = 8 Ω
0.1 1 10
THD+N − Total Harmonic Distortion + Noise − %
0.001
0.01
10
40
0.1
G004
1
f = 20 Hz
f = 1 kHz
f = 10 kHz
PO − Output Power − W
0.01
PVDD = 12 V
RL = 8 Ω
0.1 1 10
THD+N − Total Harmonic Distortion + Noise − %
0.001
0.01
10
40
0.1
G005
1
f = 20 Hz
f = 1 kHz
f = 10 kHz
PO − Output Power − W
0.01
PVDD = 8 V
RL = 8 Ω
0.1 1 10
THD+N − Total Harmonic Distortion + Noise − %
0.001
0.01
10
40
0.1
G006
1
f = 20 Hz
f = 1 kHz
f = 10 kHz
TAS5707, TAS5707A
SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com
TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs vs
FREQUENCY OUTPUT POWER
Figure 8. Figure 9.
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs vs
OUTPUT POWER OUTPUT POWER
Figure 10. Figure 11.
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Product Folder Link(s): TAS5707 TAS5707A
PVDD − Supply Voltage − V
2
4
6
8
10
12
14
16
18
20
8 9 10 11 12 13 14 15 16 17 18
PO − Output Power − W
G010
RL = 8 Ω
THD+N = 1%
THD+N = 10%
PO − Output Power (Per Channel) − W
0
10
20
30
40
50
60
70
80
90
100
0 4 8 12 16 20 24 28 32 36 40
Efficiency − %
G012
PVDD = 12 V
PVDD = 18 V
RL = 8 Ω
PVDD = 8 V
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
f − Frequency − Hz
Crosstalk − dB
G013
20 100 1k 10k 20k
Left to Right
Right to Left
PO = 0.25 W
PVDD = 18 V
RL = 8 Ω
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
f − Frequency − Hz
Crosstalk − dB
G014
20 100 1k 10k 20k
Left to Right
Right to Left
PO = 0.25 W
PVDD = 12 V
RL = 8 Ω
TAS5707, TAS5707A
www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009
TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
OUTPUT POWER EFFICIENCY
vs vs
SUPPLY VOLTAGE OUTPUT POWER
Figure 12. Figure 13.
CROSSTALK CROSSTALK
vs vs
FREQUENCY FREQUENCY
Figure 14. Figure 15.
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Product Folder Link(s): TAS5707 TAS5707A
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
f − Frequency − Hz
Crosstalk − dB
G015
20 100 1k 10k 20k
Left to Right
Right to Left
PO = 0.25 W
PVDD = 8 V
RL = 8 Ω
TAS5707, TAS5707A
SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com
TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
CROSSTALK
vs
FREQUENCY
Figure 16.
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DETAILED DESCRIPTION
POWER SUPPLY
To facilitate system design, the TAS5707 needs only a 3.3-V supply in addition to the (typical) 18-V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all
circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap
circuitry requiring only a few external capacitors.
In order to provide good electrical and acoustical characteristics, the PWM signal path for the output stage is
designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins
(BST_X), and power-stage supply pins (PVDD_X). The gate drive voltages (GVDD_AB and GVDD_CD) are
derived from the PVDD voltage. Special attention should be paid to placing all decoupling capacitors as close to
their associated pins as possible. In general, inductance between the power-supply pins and decoupling
capacitors must be avoided.
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive regulator output pin (GVDD_X) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 352 kHz to 384 kHz, it is recommended to use 33-nF ceramic capacitors,
size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even
during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the
remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is
decoupled with a 100-nF ceramic capacitor placed as close as possible to each supply pin.
The TAS5707 is fully protected against erroneous power-stage turnon due to parasitic gate charging.
ERROR REPORTING
Any fault resulting in device shutdown is signaled by the FAULT pin going low (see Table 1). A sticky version of
this pin is available on D1 of register 0X02.
Table 1. FAULT Output States
FAULT DESCRIPTION
0 Overcurrent (OC) or undervoltage (UVP) error or overtemperature error (OTE) or over
voltage ERROR
1 No faults (normal operation)
DEVICE PROTECTION SYSTEM
Overcurrent (OC) Protection With Current Limiting
The device has independent, fast-reacting current detectors on all high-side and low-side power-stage FETs. The
detector outputs are closely monitored by two protection systems. The first protection system controls the power
stage in order to prevent the output current further increasing, i.e., it performs a cycle-by-cycle current-limiting
function, rather than prematurely shutting down during combinations of high-level music transients and extreme
speaker load impedance drops. If the high-current condition situation persists, i.e., the power stage is being
overloaded, a second protection system triggers a latching shutdown, resulting in the power stage being set in
the high-impedance (Hi-Z) state. The device returns to normal operation once the fault condition (i.e., a short
circuit on the output) is removed. Current limiting and overcurrent protection are not independent for half-bridges.
That is, if the bridge-tied load between half-bridges A and B causes an overcurrent fault, half-bridges A, B, C,
and D are shut down.
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Overtemperature Protection
The TAS5707 has a two-level temperature-protection system that asserts an active-high warning signal (OTW)
when the device junction temperature exceeds 125°C (nominal) and, if the device junction temperature exceeds
150°C (nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the
high-impedance (Hi-Z) state and FAULT being asserted low. The TAS5707 recovers from shutdown
automatically once the temperature drops approximately 30°C. The overtemperature warning (OTW) is disabled
once the temperature drops approximately 25°C.
Undervoltage Protection (UVP) and Power-On
Reset (POR)
The UVP and POR circuits of the TAS5707 fully protect the device in any power-up/down and brownout situation.
While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully
operational when the PVDD and AVDD supply voltages reach 7.6 V and 2.7 V, respectively. Although PVDD and
AVDD are independently monitored, a supply voltage drop below the UVP threshold on AVDD or either PVDD
pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and FAULT being
asserted low.
SSTIMER FUNCTIONALITY
The SSTIMER pin uses a capacitor connected between this pin and ground to control the output duty cycle when
exiting all-channel shutdown. The capacitor on the SSTIMER pin is slowly charged through an internal current
source, and the charge time determines the rate at which the output transitions from a near zero duty cycle to the
desired duty cycle. This allows for a smooth transition that minimizes audible pops and clicks. When the part is
shutdown the drivers are tristated and transition slowly down through a 3K resistor, similarly minimizing pops and
clicks. The shutdown transition time is independent of SSTIMER pin capacitance. Larger capacitors will increase
the start-up time, while capacitors smaller than 2.2 nF will decrease the start-up time. The SSTIMER pin should
be left floating for BD modulation.
CLOCK, AUTO DETECTION, AND PLL
The TAS5707 is a slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP)
supports all the sample rates and MCLK rates that are defined in the clock control register .
The TAS5707 checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a 1 ×
fS LRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The clock section
uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the
internal clock (DCLK) running at 512 time the PWM switching frequency.
The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock
rates as defined in the clock control register.
TAS5707 has robust clock error handling that uses the bulit-in trimmed oscillator clock to quickly detect
changes/errors. Once the system detects a clock change/error, it will mute the audio (through a single step mute)
and then force PLL to limp using the internal oscillator as a reference clock. Once the clocks are stable, the
system will auto detect the new rate and revert to normal operation. During this process, the default volume will
be restored in a single step (also called hard unmute). The ramp process can be programmed to ramp back
slowly (also called soft unmute) as defined in volume register (0X0E).
SERIAL DATA INTERFACE
Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5707 DAP accepts serial data in
16-, 20-, or 24-bit left-justified, right-justified, and I
2S serial data formats.
PWM Section
The TAS5707 DAP device uses noise-shaping and sophisticated non-linear correction algorithms to achieve high
power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to
increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP
and outputs two BTL PWM audio output channels.
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23 22
SCLK
32 Clks
LRCLK (Note Reversed Phase) Left Channel
24-Bit Mode
1
19 18
20-Bit Mode
16-Bit Mode
15 14
MSB LSB
32 Clks
Right Channel
2-Channel I S (Philips Format) Stereo Input 2
T0034-01
9 8 5 4
1 0
0
5 4
1 0
23 22 1
19 18
15 14
MSB LSB
9 8 5 4
1 0
0
5 4
1 0
SCLK
TAS5707, TAS5707A
www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009
The PWM section has individual channel dc blocking filters that can be enabled and disabled. The filter cutoff
frequency is less than 1 Hz. Individual channel de-emphasis filters for 44.1- and 48-kHz are included and can be
enabled and disabled.
Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%.
For detailed description of using audio processing features like DRC and EQ, please refer to User's Guide and
TAS570X GDE software development tool documentation. Also refer to GDE software development tool for
device data path.
I
2C COMPATIBLE SERIAL CONTROL INTERFACE
The TAS5707 DAP has an I
2C serial control slave interface to receive commands from a system controller. The
serial control interface supports both normal-speed (100-kHz) and high-speed (400-kHz) operations without wait
states. As an added feature, this interface operates even if MCLK is absent.
The serial control interface supports both single-byte and multi-byte read and write operations for status registers
and the general control registers associated with the PWM.
SERIAL INTERFACE CONTROL AND TIMING
I
2S Timing
I
2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or
64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes
state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit
clock. The DAP masks unused trailing data bit positions.
NOTE: All data presented in 2s-complement form with MSB first.
Figure 17. I
2S 64-fS Format
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23 22
SCLK
24 Clks
LRCLK Left Channel
24-Bit Mode
1
19 18
20-Bit Mode
16-Bit Mode
15 14
MSB LSB
24 Clks
Right Channel
2-Channel I S (Philips Format) Stereo Input/Output (24-Bit Transfer Word Size) 2
T0092-01
17 16 9 8 5 4 3 2
1 0
0
13 12 5 4
9 8 1 0
23 22
SCLK
1
19 18
15 14
MSB LSB
17 16 9 8 5 4 3 2
13 12 5 4 1 0
9 8 1 0
SCLK
16 Clks
LRCLK Left Channel
16-Bit Mode
15 14 1 15 14 1
MSB LSB
16 Clks
Right Channel
2-Channel I S (Philips Format) Stereo Input 2
T0266-01
13 12 11 10 9 8 5 4 3 2 0 13 12 11 10 9 8 5 4 3 2
SCLK
MSB LSB
TAS5707, TAS5707A
SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com
NOTE: All data presented in 2s-complement form with MSB first.
Figure 18. I
2S 48-fS Format
NOTE: All data presented in 2s-complement form with MSB first.
Figure 19. I
2S 32-fS Format
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23 22
SCLK
32 Clks
LRCLK
Left Channel
24-Bit Mode
1
19 18
20-Bit Mode
16-Bit Mode
15 14
MSB LSB
32 Clks
Right Channel
2-Channel Left-Justified Stereo Input
T0034-02
9 8 5 4
5 4 1
1
0
0
0
23 22 1
19 18
15 14
MSB LSB
9 8 5 4
5 4 1
1
0
0
0
SCLK
TAS5707, TAS5707A
www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009
Left-Justified
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it
is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,
48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK
toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused
trailing data bit positions.
NOTE: All data presented in 2s-complement form with MSB first.
Figure 20. Left-Justified 64-fS Format
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23 22
SCLK
24 Clks
LRCLK
Left Channel
24-Bit Mode
1
19 18
20-Bit Mode
16-Bit Mode
15 14
MSB LSB
24 Clks
Right Channel
2-Channel Left-Justified Stereo Input (24-Bit Transfer Word Size)
T0092-02
17 16 9 8 5 4
13 12 5 4 1
9 8 1
0
0
0
21
17
13
23 22
SCLK
1
19 18
15 14
MSB LSB
17 16 9 8 5 4
13 12 5 4 1
9 8 1
0
0
0
21
17
13
SCLK
16 Clks
LRCLK
Left Channel
16-Bit Mode
15 14 1 15 14 1
MSB LSB
16 Clks
Right Channel
2-Channel Left-Justified Stereo Input
T0266-02
13 12 11 10 9 8 5 4 3 2 0 13 12 11 10 9 8 5 4 3 2 0
SCLK
MSB LSB
TAS5707, TAS5707A
SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com
NOTE: All data presented in 2s-complement form with MSB first.
Figure 21. Left-Justified 48-fS Format
NOTE: All data presented in 2s-complement form with MSB first.
Figure 22. Left-Justified 32-fS Format
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23 22
SCLK
32 Clks
LRCLK
Left Channel
24-Bit Mode
1
20-Bit Mode
16-Bit Mode
15 14
MSB LSB
SCLK
32 Clks
Right Channel
2-Channel Right-Justified (Sony Format) Stereo Input
T0034-03
19 18
19 18 1
1
0
0
0
15 14
15 14 23 22 1
15 14
MSB LSB
19 18
19 18 1
1
0
0
0
15 14
15 14
TAS5707, TAS5707A
www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009
Right-Justified
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when
it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for
24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before
LRCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock. The DAP masks
unused leading data bit positions.
Figure 23. Right Justified 64-fS Format
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23 22
SCLK
24 Clks
LRCLK
Left Channel
24-Bit Mode
1
20-Bit Mode
16-Bit Mode
15 14
MSB LSB
SCLK
24 Clks
Right Channel
MSB
2-Channel Right-Justified Stereo Input (24-Bit Transfer Word Size)
T0092-03
19 18 5
19 18 5 1
5 1
0
0
0
2
2
2
6
6
6
15 14
15 14 23 22 1
15 14
19 18 5
19 18 5 1
5 1
0
0
0
2
2
2
6
6
6
15 14
15 14
LSB
TAS5707, TAS5707A
SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com
Figure 24. Right Justified 48-fS Format
Figure 25. Right Justified 32-fS Format
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7-Bit Slave Address R/
W
A 8-Bit Register Address (N) 8-Bit Register Data For
Address (N)
Start Stop
SDA
SCL
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
A
8-Bit Register Data For
Address (N) A A
T0035-01
TAS5707, TAS5707A
www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009
I
2C SERIAL CONTROL INTERFACE
The TAS5707 DAP has a bidirectional I
2C interface that compatible with the I
2C (Inter IC) bus protocol and
supports both 100-kHz and 400-kHz data transfer rates for single and multiple byte write and read operations.
This is a slave only device that does not support a multimaster bus environment or wait state insertion. The
control interface is used to program the registers of the device and to read device status.
The DAP supports the standard-mode I
2C bus operation (100 kHz maximum) and the fast I
2C bus operation
(400 kHz maximum). The DAP performs all I
2C operations without I
2C wait cycles.
General I
2C Operation
The I
2C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially one bit at a time. The address and data can be transferred in byte
(8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data pin (SDA) while the clock is high to indicate a start and stop conditions. A
high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data bit
transitions must occur within the low time of the clock period. These conditions are shown in Figure 26. The
master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another
device and then waits for an acknowledge condition. The TAS5707 holds SDA low during the acknowledge clock
period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence.
Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the
same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for
the SDA and SCL signals to set the high level for the bus.
Figure 26. Typical I
2C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 26.
The 7-bit address for TAS5707 is 0011 011 (0x36). The 7-bit address for the TAS5707A is 0011 101 (0x3A).
The TAS5707 address can be changed from 0x36 to 0x38 by writing 0x38 to device slave address register 0xF9.
The TAS5707A address can be changed from 0x3A to 0x3C by writing 0x3C to device slave address register
0xF9.
Single- and Multiple-Byte Transfers
The serial control interface supports both single-byte and multiple-byte read/write operations for subaddresses
0x00 to 0x1F. However, for the subaddresses 0x20 to 0xFF, the serial control interface supports only
multiple-byte read/write operations (in multiples of 4 bytes).
During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress
assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does
not contain 32 bits, the unused bits are read as logic 0.
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A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
I C Device Address and 2
Read/Write Bit
Subaddress Data Byte
T0036-01
D7 D0 ACK
Stop
Condition
Acknowledge
I C Device Address and 2
Read/Write Bit
Subaddress Last Data Byte
A6 A5 A1 A0 R/W ACK A7 A5 A1 A0 ACK D7 ACK
Start
Condition Acknowledge Acknowledge Acknowledge
First Data Byte
A6 A4 A3
Other Data Bytes
ACK
Acknowledge
D0 D7 D0
T0036-02
TAS5707, TAS5707A
SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com
During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes
that are required for each specific subaddress. For example, if a write command is received for a biquad
subaddress, the DAP expects to receive five 32-bit words. If fewer than five 32-bit data words have been
received when a stop command (or another start command) is received, the data received is discarded.
Supplying a subaddress for each subaddress transaction is referred to as random I
2C addressing. The TAS5707
also supports sequential I
2C addressing. For write transactions, if a subaddress is issued followed by data for
that subaddress and the 15 subaddresses that follow, a sequential I
2C write transaction has taken place, and the
data for all 16 subaddresses is successfully received by the TAS5707. For I
2C sequential write transactions, the
subaddress then serves as the start address, and the amount of data subsequently transmitted, before a stop or
start is transmitted, determines how many subaddresses are written. As was true for random addressing,
sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to
the last subaddress, the data for the last subaddress is discarded. However, all other data written is accepted;
only the incomplete data is discarded.
Single-Byte Write
As shown in Figure 27, a single-byte data write transfer begins with the master device transmitting a start
condition followed by the I
2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit will be a 0. After receiving the correct I
2C device
address and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the
address byte or bytes corresponding to the TAS5707 internal memory address being accessed. After receiving
the address byte, the TAS5707 again responds with an acknowledge bit. Next, the master device transmits the
data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5707 again
responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the
single-byte data write transfer.
Figure 27. Single-Byte Write Transfer
Multiple-Byte Write
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the DAP as shown in Figure 28. After receiving each data byte, the
TAS5707 responds with an acknowledge bit.
Figure 28. Multiple-Byte Write Transfer
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A6 A5 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
I C Device Address and 2
Read/Write Bit
Subaddress Data Byte
D7 D6 D1 D0 ACK
I C Device Address and
Read/Write Bit
2
Not
Acknowledge
A1 A1 R/W
Repeat Start
Condition
T0036-03
A6 A0 ACK
Acknowledge
I C Device Address and
Read/Write Bit
2
A6 A0 R/W ACK A0 ACK R/W D7 D0 ACK
Start
Condition
Stop
Condition
Acknowledge Acknowledge Acknowledge
Last Data Byte
ACK
First Data Byte
Repeat Start
Condition
Not
Acknowledge
I C Device Address and
Read/Write Bit
2
Subaddress Other Data Bytes
A7 A6 A5 D7 D0 ACK
Acknowledge
D7 D0
T0036-04
TAS5707, TAS5707A
www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009
Single-Byte Read
As shown in Figure 29, a single-byte data read transfer begins with the master device transmitting a start
condition followed by the I
2C device address and the read/write bit. For the data read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal
memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5707 address
and the read/write bit, TAS5707 responds with an acknowledge bit. In addition, after sending the internal memory
address byte or bytes, the master device transmits another start condition followed by the TAS5707 address and
the read/write bit again. This time the read/write bit becomes a 1, indicating a read transfer. After receiving the
address and the read/write bit, the TAS5707 again responds with an acknowledge bit. Next, the TAS5707
transmits the data byte from the memory address being read. After receiving the data byte, the master device
transmits a not acknowledge followed by a stop condition to complete the single byte data read transfer.
Figure 29. Single-Byte Read Transfer
Multiple-Byte Read
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes
are transmitted by the TAS5707 to the master device as shown in Figure 30. Except for the last data byte, the
master device responds with an acknowledge bit after receiving each data byte.
Figure 30. Multiple Byte Read Transfer
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Output Level (dB)
Input Level (dB)
T
O
K
M0091-02
1:1 Transfer Function
Implemented Transfer Function S
Z
–1
Alpha Filter Structure
w
a
B0265-01
Energy
Filter
a w, T, K, O a w a
, a d d / , a w
DRC 0x3A 0x40, 0x41, 0x42 0x3B / 0x3C
Compression
Control
Attack
and
Decay
Filters
Audio Input DRC Coefficient
NOTE:
w a = 1 –
TAS5707, TAS5707A
SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com
Dynamic Range Control (DRC)
The DRC scheme has a single threshold, offset, and slope (all programmable). There is one ganged DRC for the
left/right channels.
The DRC input/output diagram is shown in Figure 31.
Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.
• One DRC for left/right
• The DRC has adjustable threshold, offset, and compression levels
• Programmable energy, attack, and decay time constants
• Transparent compression: compressors can attack fast enough to avoid apparent clipping before engaging,
and decay times can be set slow enough to avoid pumping.
Figure 31. Dynamic Range Control
Figure 32. DRC Structure
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2 Bit –23
S_xx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx
2 Bit –5
2 Bit –1
2 Bit 0
Sign Bit
2 Bit 1
M0125-01
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BANK SWITCHING
The TAS5707 uses an approach called bank switching together with automatic sample-rate detection. All
processing features that must be changed for different sample rates are stored internally in three banks. The
user can program which sample rates map to each bank. By default, bank 1 is used in 32kHz mode, bank 2 is
used in 44.1/48 kHz mode, and bank 3 is used for all other rates. Combined with the clock-rate autodetection
feature, bank switching allows the TAS5707 to detect automatically a change in the input sample rate and switch
to the appropriate bank without any MCU intervention.
An external controller configures bankable locations (0x29-0x36 and 0x3A-0x3C) for all three banks during the
initialization sequence.
If auto bank switching is enabled (register 0x50, bits 2:0) , then the TAS5707 automatically swaps the coefficients
for subsequent sample rate changes, avoiding the need for any external controller intervention for a sample rate
change.
By default, bits 2:0 have the value 000; indicating that bank switching is disabled. In that state, updates to
bankable locations take immediate effect. A write to register 0x50 with bits 2:0 being 001, 010, or 011 brings the
system into the coefficient-bank-update state update bank1, update bank2, or update bank3, respectively. Any
subsequent write to bankable locations updates the coefficient banks stored outside the DAP. After updating all
the three banks, the system controller should issue a write to register 0x50 with bits 2:0 being 100; this changes
the system state to automatic bank switching mode. In automatic bank switching mode, the TAS5707
automatically swaps banks based on the sample rate.
Command sequences for updating DAP coefficients can be summarized as follows:
1. Bank switching disabled (default): DAP coefficient writes take immediate effect and are not
influenced by subsequent sample rate changes.
OR
Bank switching enabled:
(a) Update bank-1 mode: Write "001" to bits 2:0 of reg 0x50. Load the 32 kHz coefficients.
(b) Update bank-2 mode: Write "010" to bits 2:0 of reg 0x50. Load the 48 kHz coefficients.
(c) Update bank-3 mode: Write "011" to bits 2:0 of reg 0x50. Load the other coefficients.
(d) Enable automatic bank switching by writing "100" to bits 2:0 of reg 0x50.
26-Bit 3.23 Number Format
All mixer gain coefficients are 26-bit coefficients using a 3.23 number format. Numbers formatted as 3.23
numbers means that there are 3 bits to the left of the decimal point and 23 bits to the right of the decimal point.
This is shown in Figure 33 .
Figure 33. 3.23 Format
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(1 or 0) 2 + ´
1
(1 or 0) 2 + (1 or 0) 2 + ....... (1 or 0) 2 + ....... (1 or 0) 2 ´ ´ ´ ´
0 –1 –4 –23
2 Bit 1
2 Bit 0
2 Bit –1 2 Bit –4 2 Bit –23
M0126-01
u
Coefficient
Digit 8
u u u u u S x
Coefficient
Digit 7
x. x x x
Coefficient
Digit 6
x x x x
Coefficient
Digit 5
x x x x
Coefficient
Digit 4
x x x x
Coefficient
Digit 3
x x x x
Coefficient
Digit 2
x x x x
Coefficient
Digit 1
Fraction
Digit 5
Fraction
Digit 4
Fraction
Digit 3
Fraction
Digit 2
Fraction
Integer Digit 1
Digit 1
Sign
Bit
Fraction
Digit 6
u = unused or don’t care bits
Digit = hexadecimal digit
M0127-01
0
TAS5707, TAS5707A
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The decimal value of a 3.23 format number can be found by following the weighting shown in Figure 33. If the
most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct
number. If the most significant bit is a logic 1, then the number is a negative number. In this case every bit must
be inverted, a 1 added to the result, and then the weighting shown in Figure 34 applied to obtain the magnitude
of the negative number.
Figure 34. Conversion Weighting Factors—3.23 Format to Floating Point
Gain coefficients, entered via the I
2C bus, must be entered as 32-bit binary numbers. The format of the 32-bit
number (4-byte or 8-digit hexadecimal number) is shown in Figure 35
Figure 35. Alignment of 3.23 Coefficient in 32-Bit I
2C Word
Table 2. Sample Calculation for 3.23 Format
db Linear Decimal Hex (3.23 Format)
0 1 8388608 00800000
5 1.7782794 14917288 00E39EA8
–5 0.5623413 4717260 0047FACC
X L = 10(X/20) D = 8388608 × L H = dec2hex (D, 8)
Table 3. Sample Calculation for 9.17 Format
db Linear Decimal Hex (9.17 Format)
0 1 131072 20000
5 1.77 231997 38A3D
–5 0.56 73400 11EB8
X L = 10(X/20) D = 131072 × L H = dec2hex (D, 8)
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Initialization
50 ms
50 ms
2 sm
2 sm
2 sm
2 sm
AVDD/DVDD
PDN
PVDD
RESET
T0419-01
3 V 3 V
0 ns
0 ns
0 ns
10 sm
100 sμ
13.5 ms
100 sm
6 V 6 V
8 V 8 V
2I S
MCLK
LRCLK
SCLK
SDIN
2I C SCL SDA Trim Volume and Mute Commands
Clock Changes/Errors OK Stable and Valid Clocks Stable and Valid Clocks
Exit
SD
Enter
SD
DAP
Config
Other
Config
1 ms + 1.3 tstart(2)
1 ms + 1.3 tstart(2)
tPLL(1)
tPLL(1)
1 ms + 1.3 tstop(2)
0 ns
Normal Operation Shutdown Powerdown
(1) t has to be greater than 240 ms + 1.3 t .
This constraint only applies to the first trim command following AVDD/DVDD power-up.
It does not apply to trim commands following subsequent resets.
(2) t /t = PWM start/stop time as defined in register 0X1A
PLL start
start stop
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Recommended Use Model
Figure 36. Recommended Command Sequence
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2 sm
2 sm
2 sm
AVDD/DVDD
PDN
PVDD
RESET
T0420-01
3 V
8 V
6 V
I S2
I C2
2 ms
0 ns
0 ns
0 ns
0 ns
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Figure 37. Power Loss Sequence
Recommended Command Sequences
The DAP has two groups of commands. One set is for configuration and is intended for use only during
initialization. The other set has built-in click and pop protection and may be used during normal operation while
audio is streaming. The following supported command sequences illustrate how to initialize, operate, and
shutdown the device.
Initialization Sequence
Use the following sequence to power-up and initialize the device:
1. Hold all digital inputs low and ramp up AVDD/DVDD to at least 3V.
2. Initialize digital inputs and PVDD supply as follows:
• Drive RESETZ=0, PDNZ=1, and other digital inputs to their desired state while ensuring that
all are never more than 2.5V above AVDD/DVDD. Provide stable and valid I2S clocks
(MCLK, LRCLK, and SCLK). Wait at least 100us, drive RESETZ=1, and wait at least another
13.5ms.
• Ramp up PVDD to at least 8V while ensuring that it remains below 6V for at least 100us after
AVDD/DVDD reaches 3V. Then wait at least another 10us.
3. Trim oscillator (write 0x00 to register 0x1B) and wait at least 50ms.
4. Configure the DAP via I
2C (see Users's Guide for typical values):
Biquads (0x29-36)
DRC parameters (0x3A-3C, 0x40-42, and 0x46)
Bank select (0x50)
5. Configure remaining registers
6. Exit shutdown (sequence defined below).
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Normal Operation
The following are the only events supported during normal operation:
(a) Writes to master/channel volume registers
(b) Writes to soft mute register
(c) Enter and exit shutdown (sequence defined below)
(d) Clock errors and rate changes
Note: Events (c) and (d) are not supported for 240ms+1.3*Tstart after trim following AVDD/DVDD powerup
ramp (where Tstart is specified by register 0x1A).
Shutdown Sequence
Enter:
1. Ensure I2S clocks have been stable and valid for at least 50ms.
2. Write 0x40 to register 0x05.
3. Wait at least 1ms+1.3*Tstop (where Tstop is specified by register 0x1A).
4. Once in shutdown, stable clocks are not required while device remains idle.
5. If desired, reconfigure by ensuring that clocks have been stable and valid for at least 50ms before
returning to step 4 of initialization sequence.
Exit:
1. Ensure I2S clocks have been stable and valid for at least 50ms.
2. Write 0x00 to register 0x05 (exit shutdown command may not be serviced for as much as 240ms
after trim following AVDD/DVDD powerup ramp).
3. Wait at least 1ms+1.3*Tstart (where Tstart is specified by register 0x1A).
4. Proceed with normal operation.
Powerdown Sequence
Use the following sequence to powerdown the device and its supplies:
1. If time permits, enter shutdown (sequence defined above); else, in case of sudden power loss,
assert PDNZ=0 and wait at least 2ms.
2. Assert RESETZ=0.
3. Drive digital inputs low and ramp down PVDD supply as follows:
• Drive all digital inputs low after RESETZ has been low for at least 2us.
• Ramp down PVDD while ensuring that it remains above 8V until RESETZ has been low for at
least 2us.
4. Ramp down AVDD/DVDD while ensuring that it remains above 3V until PVDD is below 6V and
that it is never more than 2.5V below the digital inputs.
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Table 4. Serial Control Interface Register Summary
NO. OF INITIALIZATION SUBADDRESS REGISTER NAME CONTENTS BYTES VALUE
A u indicates unused bits.
0x00 Clock control register 1 Description shown in subsequent section 0x6C
0x01 Device ID register 1 Description shown in subsequent section 0x70
0x02 Error status register 1 Description shown in subsequent section 0x00
0x03 System control register 1 1 Description shown in subsequent section 0xA0
0x04 Serial data interface 1 Description shown in subsequent section 0x05
register
0x05 System control register 2 1 Description shown in subsequent section 0x40
0x06 Soft mute register 1 Description shown in subsequent section 0x00
0x07 Master volume 1 Description shown in subsequent section 0xFF (mute)
0x08 Channel 1 vol 1 Description shown in subsequent section 0x30 (0 dB)
0x09 Channel 2 vol 1 Description shown in subsequent section 0x30 (0 dB)
0x0A Fine master volume 1 Description shown in subsequent section 0x00 (0 dB)
0x0B–0X0D 1 Reserved(1)
0x0E Volume configuration 1 Description shown in subsequent section 0x91
register
0x0F 1 Reserved(1)
0x10 Modulation limit register 1 Description shown in subsequent section 0x02
0x11 IC delay channel 1 1 Description shown in subsequent section 0xAC
0x12 IC delay channel 2 1 Description shown in subsequent section 0x54
0x13 IC delay channel 3 1 Description shown in subsequent section 0xAC
0x14 IC delay channel 4 1 Description shown in subsequent section 0x54
0x15–0x19 1 Reserved(1)
0x1A Start/stop period register 1 Description shown in subsequent section 0x0F
0x1B Oscillator trim register 1 Description shown in subsequent section 0x82
0x1C BKND_ERR register 1 Description shown in subsequent section 0x02
0x1D–0x1F 1 Reserved(1)
0x20 Input MUX register 4 Description shown in subsequent section 0x0001 7772
0x21-0X24 4 Reserved(1)
0x25 PWM MUX register 4 Description shown in subsequent section 0x0102 1345
0x26–0x28 4 Reserved(1)
0x29 ch1_bq[0] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x2A ch1_bq[1] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x2B ch1_bq[2] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
(1) Reserved registers should not be accessed.
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Table 4. Serial Control Interface Register Summary (continued)
NO. OF INITIALIZATION SUBADDRESS REGISTER NAME CONTENTS BYTES VALUE
0x2C ch1_bq[3] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x2D ch1_bq[4] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x2E ch1_bq[5] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x2F ch1_bq[6] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x30 ch2_bq[0] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x31 ch2_bq[1] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x32 ch2_bq[2] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x33 ch2_bq[3] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x34 ch2_bq[4] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
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Table 4. Serial Control Interface Register Summary (continued)
NO. OF INITIALIZATION SUBADDRESS REGISTER NAME CONTENTS BYTES VALUE
0x35 ch2_bq[5] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x36 ch2_bq[6] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x37–0x39 Reserved(2)
DRC ae(3) u[31:26], ae[25:0] 0x0080 0000
0x3A 8
DRC (1 – ae) u[31:26], (1 – ae)[25:0] 0x0000 0000
DRC aa u[31:26], aa[25:0] 0x0080 0000
0x3B 8
DRC (1 – aa) u[31:26], (1 – aa)[25:0] 0x0000 0000
DRC ad u[31:26], ad[25:0] 0x0080 0000
0x3C 8
DRC (1 – ad) u[31:26], (1 – ad)[25:0] 0x0000 0000
0x3D–0x3F Reserved(2)
0x40 DRC-T 4 T[31:0] (9.23 format) 0xFDA2 1490
0x41 DRC-K 4 u[31:26], K[25:0] 0x0384 2109
0x42 DRC-O 4 u[31:26], O[25:0] 0x0008 4210
0x43–0x45 Reserved(2)
0x46 DRC control 4 Description shown in subsequent section 0x0000 0000
0x47–0x4F Reserved(2)
0x50 Bank switch control 4 Description shown in subsequent section 0x0F70 8000
0x51–0xC9 Reserved(2)
0xCA 8 Reserved(2)
0xCB–0xF8 Reserved(2)
Update device address 4 New Dev Id[7:1], ZERO[0] (New Dev Id = 0x38), 0x00000036 0xF9 register (7:1) defines the new device address
0xFA-0xFF Reserved(2)
(2) Reserved registers should not be accessed.
(3) "ae" stands for µ of energy filter, "aa" stands for µ of attack filter and "ad" stands for µ of decay filter and 1- µ = ω.
All DAP coefficients are 3.23 format unless specified otherwise.
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CLOCK CONTROL REGISTER (0x00)
The clocks and data rates are automatically determined by the TAS5707. The clock control register contains the
auto-detected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency. The
device accepts a 64-fS or 32-fS SCLK rate for all MCLK rates, but accepts a 48-fS SCLK rate for MCLK rates of
192 fS and 384 fS only.
Table 5. Clock Control Register (0x00)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 – – – – – fS = 32-kHz sample rate
0 0 1 – – – – – Reserved(1)
0 1 0 – – – – – Reserved(1)
0 1 1 – – – – – fS = 44.1/48-kHz sample rate (2)
1 0 0 – – – – – fs = 16-kHz sample rate
1 0 1 – – – – – fs = 22.05/24 -kHz sample rate
1 1 0 – – – – – fs = 8-kHz sample rate
1 1 1 – – – – – fs = 11.025/12 -kHz sample rate
– – – 0 0 0 – – MCLK frequency = 64 × fS
(3)
– – – 0 0 1 – – MCLK frequency = 128 × fS
(3)
– – – 0 1 0 – – MCLK frequency = 192 × fS
(4)
– – – 0 1 1 – – MCLK frequency = 256 × fS
(2) (5)
– – – 1 0 0 – – MCLK frequency = 384 × fS
– – – 1 0 1 – – MCLK frequency = 512 × fS
– – – 1 1 0 – – Reserved(1)
– – – 1 1 1 – – Reserved(1)
– – – – – – 0 – Reserved(1)
– – – – – – – 0 Reserved(1)
(1) Reserved registers should not be accessed.
(2) Default values are in bold.
(3) Only available for 44.1 kHz and 48 kHz rates.
(4) Rate only available for 32/44.1/48 KHz sample rates
(5) Not available at 8 kHz
DEVICE ID REGISTER (0x01)
The device ID register contains the ID code for the firmware revision.
Table 6. General Status Register (0x01)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
X – – – – – – – Reserved
– 1 1 1 0 0 0 0 Identification code
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ERROR STATUS REGISTER (0x02)
The error bits are sticky and are not cleared by the hardware. This means that the software must clear the
register (write zeroes) and then read them to determine if they are persistent errors.
Error Definitions:
• MCLK Error : MCLK frequency is changing. The number of MCLKs per LRCLK is changing.
• SCLK Error: The number of SCLKs per LRCLK is changing.
• LRCLK Error: LRCLK frequency is changing.
• Frame Slip: LRCLK phase is drifting with respect to internal frame sync.
Table 7. Error Status Register (0x02)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
1 - – – – – – – MCLK error
– 1 – – – – – – PLL autolock error
– – 1 – – – – – SCLK error
– – – 1 – – – – LRCLK error
– – – – 1 – – – Frame slip
– – – – – – 1 – Overcurrent, overtemperature, overvoltage or undervoltage error
– – – – – – – 1 Overtemperature warning (sets around 125°)
0 0 0 0 0 0 0 0 No errors (1)
(1) Default values are in bold.
SYSTEM CONTROL REGISTER 1 (0x03)
The system control register 1 has several functions:
Bit D7: If 0, the dc-blocking filter for each channel is disabled.
If 1, the dc-blocking filter (–3 dB cutoff <1 Hz) for each channel is enabled (default).
Bit D5: If 0, use soft unmute on recovery from clock error. This is a slow recovery. Unmute takes same
time as volume ramp defined in reg 0X0E.
If 1, use hard unmute on recovery from clock error (default). This is a fast recovery, a single step
volume ramp
Bits D1–D0: Select de-emphasis
Table 8. System Control Register 1 (0x03)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 – – – – – – – PWM high-pass (dc blocking) disabled
1 – – – – – – – PWM high-pass (dc blocking) enabled (1)
– 0 – – – – – – Reserved (1)
– – 0 – – – – – Soft unmute on recovery from clock error
– – 1 – – – – – Hard unmute on recovery from clock error (1)
– – – 0 – – – – Reserved (1)
– – – – 0 – – – Reserved (1)
– – – – – 0 – – Reserved(1)
– – – – – – 0 0 No de-emphasis (1)
– – – – – – 0 1 De-emphasis for fS = 32 kHz
– – – – – – 1 0 Reserved
– – – – – – 1 1 De-emphasis for fS = 48 kHz
(1) Default values are in bold.
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SERIAL DATA INTERFACE REGISTER (0x04)
As shown in Table 9, the TAS5707 supports 9 serial data modes. The default is 24-bit, I
2S mode,
Table 9. Serial Data Interface Control Register (0x04) Format
RECEIVE SERIAL DATA WORD D7–D4 D3 D2 D1 D0 INTERFACE FORMAT LENGTH
Right-justified 16 0000 0 0 0 0
Right-justified 20 0000 0 0 0 1
Right-justified 24 0000 0 0 1 0
I
2S 16 000 0 0 1 1
I
2S 20 0000 0 1 0 0
I
2S
(1) 24 0000 0 1 0 1
Left-justified 16 0000 0 1 1 0
Left-justified 20 0000 0 1 1 1
Left-justified 24 0000 1 0 0 0
Reserved 0000 1 0 0 1
Reserved 0000 1 0 1 0
Reserved 0000 1 0 1 1
Reserved 0000 1 1 0 0
Reserved 0000 1 1 0 1
Reserved 0000 1 1 1 0
Reserved 0000 1 1 1 1
(1) Default values are in bold.
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SYSTEM CONTROL REGISTER 2 (0x05)
When bit D6 is set low, the system exits all channel shutdown and starts playing audio; otherwise, the outputs
are shut down(hard mute).
Table 10. System Control Register 2 (0x05)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 – – – – – – – Reserved (1)
– 1 – – – – – – Enter all channel shut down (hard mute).(1)
– 0 – – – – – – Exit all-channel shutdown (normal operation)
– – 0 0 0 0 0 0 Reserved (1)
(1) Default values are in bold.
SOFT MUTE REGISTER (0x06)
Writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle (soft mute).
Table 11. Soft Mute Register (0x06)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
– – – – – – – 1 Soft mute channel 1
– – – – – – – 0 Soft unmute channel 1
– – – – – – 1 – Soft mute channel 2
– – – – – – 0 – Soft unmute channel 2
0 0 0 0 0 0 – – Reserved
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VOLUME REGISTERS (0x07, 0x08, 0x09)
Step size is 0.5 dB.
Master volume – 0x07 (default is mute)
Channel-1 volume – 0x08 (default is 0 dB)
Channel-2 volume – 0x09 (default is 0 dB)
Table 12. Volume Registers (0x07, 0x08, 0x09)
D D D D D D D D
FUNCTION 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 24 dB
0 0 1 1 0 0 0 0 0 dB (default for individual channel volume) (1)
1 1 0 0 1 1 0 1 –78.5 dB
1 1 0 0 1 1 1 0 –79.0 dB
1 1 0 0 1 1 1 1 Values between 0xCF and 0xFE are Reserved
1 1 1 1 1 1 1 1 MUTE (default for master volume)
(1) Default values are in bold.
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MASTER FINE VOLUME REGISTER (0x0A)
This register can be used to provide precision tuning of master volume.
Table 13. Master Fine Volume Register (0x0A)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
– – – – – – 0 0 0 dB (1)
– – – – – – 0 1 0.125 dB
– – – – – – 1 0 0.25 dB
– – – – – – 1 1 0.375 dB
1 – – – – – – – Write enable bit
0 – – – – – – – Ignore Write to register 0X0A
(1) Default values are in bold.
VOLUME CONFIGURATION REGISTER (0x0E)
Bits Volume slew rate (Used to control volume change and MUTE ramp rates). These bits control the
D2–D0: number of steps in a volume ramp.Volume steps occur at a rate that depends on the sample rate of
the I2S data as follows
Sample Rate (KHz) Approximate Ramp Rate
8/16/32 125 us/step
11.025/22.05/44.1 90.7 us/step
12/24/48 83.3 us/step
Table 14. Volume Control Register (0x0E)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
1 0 0 1 0 – – – Reserved (1)
– – – – – 0 0 0 Volume slew 512 steps (43 ms volume ramp time at 48kHz)
– – – – – 0 0 1 Volume slew 1024 steps (85 ms volume ramp time at 48kHz) (1)
– – – – – 0 1 0 Volume slew 2048 steps (171 ms volume ramp time at 48kHz)
– – – – – 0 1 1 Volume slew 256 steps (21ms volume ramp time at 48kHz)
– – – – – 1 X X Reserved
(1) Default values are in bold.
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MODULATION LIMIT REGISTER (0x10)
The modulation limit is the maximum duty cycle of the PWM output waveform.
Table 15. Modulation Limit Register (0x10)
D7 D6 D5 D4 D3 D2 D1 D0 MODULATION LIMIT
– – – – – 0 0 0 99.2%
– – – – – 0 0 1 98.4%
– – – – – 0 1 0 97.7%
– – – – – 0 1 1 96.9%
– – – – – 1 0 0 96.1%
– – – – – 1 0 1 95.3%
– – – – – 1 1 0 94.5%
– – – – – 1 1 1 93.8%
0 0 0 0 0 – – – RESERVED
INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, and 0x14)
Internal PWM channels 1, 2, 1, and 2 are mapped into registers 0x11, 0x12, 0x13, and 0x14.
Table 16. Channel Interchannel Delay Register Format
BITS DEFINITION D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 0 – – Minimum absolute delay, 0 DCLK cycles
0 1 1 1 1 1 – – Maximum positive delay, 31 × 4 DCLK cycles
1 0 0 0 0 0 – – Maximum negative delay, –32 × 4 DCLK cycles
0 0 RESERVED
SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 Delay = (value) × 4 DCLKs
0x11 1 0 1 0 1 1 – – Default value for channel 1
(1)
0x12 0 1 0 1 0 1 – – Default value for channel 2
(1)
0x13 1 0 1 0 1 1 – – Default value for channel 1
(1)
0x14 0 1 0 1 0 1 – – Default value for channel 2
(1)
(1) Default values are in bold.
ICD settings have high impact on audio performance (e.g., dynamic range, THD, crosstalk etc.) Therefore,
appropriate ICD settings must be used. By default, the device has ICD settings for AD mode. If used in BD
mode, then update these registers before coming out of all-channel shutdown.
REGISTER AD MODE BD MODE
0x11 0xAC 0xB8
0x12 0x54 0x60
0x13 0xAC 0xA0
0x14 0x54 0x48
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START/STOP PERIOD REGISTER (0x1A)
This register is used to control the soft-start and soft-stop period following an enter/exit all channel shut down
command or change in the PDN state. This helps reduce pops and clicks at start-up and shutdown.The times are
only approximate and vary depending on device activity level and I2S clock stability.
Table 17. Start/Stop Period Register (0x1A)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 – – – – – Reserved
– – – 0 0 – – – No 50% duty cycle start/stop period
– – – 0 1 0 0 0 16.5-ms 50% duty cycle start/stop period
– – – 0 1 0 0 1 23.9-ms 50% duty cycle start/stop period
– – – 0 1 0 1 0 31.4-ms 50% duty cycle start/stop period
– – – 0 1 0 1 1 40.4-ms 50% duty cycle start/stop period
– – – 0 1 1 0 0 53.9-ms 50% duty cycle start/stop period
– – – 0 1 1 0 1 70.3-ms 50% duty cycle start/stop period
– – – 0 1 1 1 0 94.2-ms 50% duty cycle start/stop period
– – – 0 1 1 1 1 125.7-ms 50% duty cycle start/stop period(1)
– – – 1 0 0 0 0 164.6-ms 50% duty cycle start/stop period
– – – 1 0 0 0 1 239.4-ms 50% duty cycle start/stop period
– – – 1 0 0 1 0 314.2-ms 50% duty cycle start/stop period
– – – 1 0 0 1 1 403.9-ms 50% duty cycle start/stop period
– – – 1 0 1 0 0 538.6-ms 50% duty cycle start/stop period
– – – 1 0 1 0 1 703.1-ms 50% duty cycle start/stop period
– – – 1 0 1 1 0 942.5-ms 50% duty cycle start/stop period
– – – 1 0 1 1 1 1256.6-ms 50% duty cycle start/stop period
– – – 1 1 0 0 0 1728.1-ms 50% duty cycle start/stop period
– – – 1 1 0 0 1 2513.6-ms 50% duty cycle start/stop period
– – – 1 1 0 1 0 3299.1-ms 50% duty cycle start/stop period
– – – 1 1 0 1 1 4241.7-ms 50% duty cycle start/stop period
– – – 1 1 1 0 0 5655.6-ms 50% duty cycle start/stop period
– – – 1 1 1 0 1 7383.7-ms 50% duty cycle start/stop period
– – – 1 1 1 1 0 9897.3-ms 50% duty cycle start/stop period
– – – 1 1 1 1 1 13,196.4-ms 50% duty cycle start/stop period
(1) Default values are in bold.
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OSCILLATOR TRIM REGISTER (0x1B)
The TAS5707 PWM processor contains an internal oscillator to support autodetect of I2S clock rates. This
reduces system cost because an external reference is not required. Currently, TI recommends a reference
resistor value of 18.2 kΩ (1%). This should be connected between OSC_RES and DVSSO.
Writing 0X00 to reg 0X1B enables the trim that was programmed at the factory.
Note that trim must always be run following reset of the device.
Table 18. Oscillator Trim Register (0x1B)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
1 – – – – – – – Reserved (1)
– 0 – – – – – – Oscillator trim not done (read-only) (1)
– 1 – – – – – – Oscillator trim done (read only)
– – 0 0 0 0 – – Reserved (1)
– – – – – – 0 – Select factory trim (Write a 0 to select factory trim; default is 1.)
– – – – – – 1 – Factory trim disabled (1)
– – – – – – – 0 Reserved (1)
(1) Default values are in bold.
BKND_ERR REGISTER (0x1C)
When a back-end error signal is received from the internal power stage, the power stage is reset stopping all
PWM activity. Subsequently, the modulator waits approximately for the time listed in Table 19 before attempting
to re-start the power stage.
Table 19. BKND_ERR Register (0x1C)(1)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 0 0 X Reserved
– – – – 0 0 1 0 Set back-end reset period to 299 ms (2)
– – – – 0 0 1 1 Set back-end reset period to 449 ms
– – – – 0 1 0 0 Set back-end reset period to 598 ms
– – – – 0 1 0 1 Set back-end reset period to 748 ms
– – – – 0 1 1 0 Set back-end reset period to 898 ms
– – – – 0 1 1 1 Set back-end reset period to 1047 ms
– – – – 1 0 0 0 Set back-end reset period to 1197 ms
– – – – 1 0 0 1 Set back-end reset period to 1346 ms
– – – – 1 0 1 X Set back-end reset period to 1496 ms
– – – – 1 1 X X Set back-end reset period to 1496 ms
(1) This register can be written only with a "non-Reserved" value. Also this register can be written once after the reset.
(2) Default values are in bold.
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INPUT MULTIPLEXER REGISTER (0x20)
This register controls the modulation scheme (AD or BD mode) as well as the routing of I2S audio to the internal
channels.
Table 20. Input Multiplexer Register (0x20)
D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION
0 0 0 0 0 0 0 0 Reserved (1)
D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION
0 – – – – – – – Channel-1 AD mode
1 – – – – – – – Channel-1 BD mode
– 0 0 0 – – – – SDIN-L to channel 1
(1)
– 0 0 1 – – – – SDIN-R to channel 1
– 0 1 0 – – – – Reserved
– 0 1 1 – – – – Reserved
– 1 0 0 – – – – Reserved
– 1 0 1 – – – – Reserved
– 1 1 0 – – – – Ground (0) to channel 1
– 1 1 1 – – – – Reserved
– – – – 0 – – – Channel 2 AD mode
– – – – 1 – – – Channel 2 BD mode
– – – – – 0 0 0 SDIN-L to channel 2
– – – – – 0 0 1 SDIN-R to channel 2
(1)
– – – – – 0 1 0 Reserved
– – – – – 0 1 1 Reserved
– – – – – 1 0 0 Reserved
– – – – – 1 0 1 Reserved
– – – – – 1 1 0 Ground (0) to channel 2
– – – – – 1 1 1 Reserved
D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION
0 1 1 1 0 1 1 1 Reserved (1)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 1 1 1 0 0 1 0 Reserved (1)
(1) Default values are in bold.
PWM OUTPUT MUX REGISTER (0x25)
This DAP output mux selects which internal PWM channel is output to the external pins. Any channel can be
output to any external output pin.
Bits D21–D20: Selects which PWM channel is output to OUT_A
Bits D17–D16: Selects which PWM channel is output to OUT_B
Bits D13–D12: Selects which PWM channel is output to OUT_C
Bits D09–D08: Selects which PWM channel is output to OUT_D
Note that channels are enclosed so that channel 1 = 0x00, channel 2 = 0x01, channet 1 = 0x02, and channel 2 =
0x03.
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Table 21. PWM Output Mux Register (0x25)
D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION
0 0 0 0 0 0 0 1 Reserved(1)
D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION
0 0 – – – – – – Reserved(1)
– – 0 0 – – – – Multiplex channel 1 to OUT_A (1)
– – 0 1 – – – – Multiplex channel 2 to OUT_A
– – 1 0 – – – – Multiplex channel 1 to OUT_A
– – 1 1 – – – – Multiplex channel 2 to OUT_A
– – – – 0 0 – – Reserved (1)
– – – – – – 0 0 Multiplex channel 1 to OUT_B
– – – – – – 0 1 Multiplex channel 2 to OUT_B
– – – – – – 1 0 Multiplex channel 1 to OUT_B (1)
– – – – – – 1 1 Multiplex channel 2 to OUT_B
D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION
0 0 – – – – – – Reserved (1)
– – 0 0 – – – – Multiplex channel 1 to OUT_C
– – 0 1 – – – – Multiplex channel 2 to OUT_C(1)
– – 1 0 – – – – Multiplex channel 1 to OUT_C
– – 1 1 – – – – Multiplex channel 2 to OUT_C
– – – – 0 0 – – Reserved (1)
– – – – – – 0 0 Multiplex channel 1 to OUT_D
– – – – – – 0 1 Multiplex channel 2 to OUT_D
– – – – – – 1 0 Multiplex channel 1 to OUT_D
– – – – – – 1 1 Multiplex channel 2 to OUT_D (1)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 1 0 0 0 1 0 1 RESERVED
(1) Default values are in bold.
DRC CONTROL (0x46)
Each DRC can be enabled independently using the DRC control register. The DRCs are disabled by default.
Table 22. DRC Control Register (0x46)
D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION
0 0 0 0 0 0 0 0 Reserved (1)
D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION
0 0 0 0 0 0 0 0 Reserved (1)
D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION
0 0 0 0 0 0 0 0 Reserved (1)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
– – – – – – – 0 DRC turned OFF (1)
– – – – – – – 1 DRC turned ON
0 0 0 0 0 0 0 – Reserved (1)
(1) Default values are in bold.
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BANK SWITCH AND EQ CONTROL (0x50)
Table 23. Bank Switching Command
D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION
0 – – – – – – – 32 kHz, does not use bank 3
(1)
1 – – – – – – – 32 kHz, uses bank 3
– 0 – – – – – – Reserved(1)
– – 0 – – – – – Reserved(1)
– – – 0 – – – – 44.1/48 kHz, does not use bank 3
(1)
– – – 1 – – – – 44.1/48 kHz, uses bank 3
– – – – 0 – – – 16 kHz, does not use bank 3
– – – – 1 – – – 16 kHz, uses bank 3
(1)
– – – – – 0 – – 22.025/24 kHz, does not use bank 3
– – – – – 1 – – 22.025/24 kHz, uses bank 3
(1)
– – – – – – 0 – 8 kHz, does not use bank 3
– – – – – – 1 – 8 kHz, uses bank 3
(1)
– – – – – – – 0 11.025 kHz/12, does not use bank 3
– – – – – – – 1 11.025/12 kHz, uses bank 3
(1)
D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION
0 – – – – – – – 32 kHz, does not use bank 2
(1)
1 – – – – – – – 32 kHz, uses bank 2
– 1 – – – – – – Reserved (1)
– – 1 – – – – – Reserved (1)
– – – 0 – – – – 44.1/48 kHz, does not use bank 2
– – – 1 – – – – 44.1/48 kHz, uses bank 2
(1)
– – – – 0 – – – 16 kHz, does not use bank 2
(1)
– – – – 1 – – – 16 kHz, uses bank 2
– – – – – 0 – – 22.025/24 kHz, does not use bank 2
(1)
– – – – – 1 – – 22.025/24 kHz, uses bank 2
– – – – – – 0 – 8 kHz, does not use bank 2
(1)
– – – – – – 1 – 8 kHz, uses bank 2
– – – – – – – 0 11.025/12 kHz, does not use bank 2
(1)
– – – – – – – 1 11.025/12 kHz, uses bank 2
D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION
0 – – – – – – – 32 kHz, does not use bank 1
1 – – – – – – – 32 kHz, uses bank 1
(1)
– 0 – – – – – – Reserved(1)
– – 0 – – – – – Reserved(1)
– – – 0 – – – – 44.1/48 kHz, does not use bank 1
(1)
– – – 1 – – – – 44.1/48 kHz, uses bank 1
– – – – 0 – – – 16 kHz, does not use bank 1
(1)
– – – – 1 – – – 16 kHz, uses bank 1
– – – – – 0 – – 22.025/24 kHz, does not use bank 1
(1)
– – – – – 1 – – 22.025/24 kHz, uses bank 1
– – – – – – 0 – 8 kHz, does not use bank 1
(1)
– – – – – – 1 – 8 kHz, uses bank 1
– – – – – – – 0 11.025/12 kHz, does not use bank 1
(1)
– – – – – – – 1 11.025/12 kHz, uses bank 1
(1) Default values are in bold.
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Table 23. Bank Switching Command (continued)
D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 EQ ON
1 – – – – – – – EQ OFF (bypass BQ 0-6 of channels 1 and 2)
– 0 – – – – – – Reserved (2)
– – 0 – – – – – Ignore bank-mapping in bits D31–D8.Use default mapping. (2)
1 Use bank-mapping in bits D31–D8.
– – – 0 – – – – L and R can be written independently. (2)
L and R are ganged for EQ biquads; a write to Left channel BQ is
– – – 1 – – – –
also written to Right channel BQ. (0X29-2F is ganged to 0X30-0X36).
– – – – 0 – – – Reserved (2)
– – – – – 0 0 0 No bank switching. All updates to DAP (2)
– – – – – 0 0 1 Configure bank 1 (32 kHz by default)
– – – – – 0 1 0 Configure bank 2 (44.1/48 kHz by default)
– – – – – 0 1 1 Configure bank 3 (other sample rates by default)
– – – – – 1 0 0 Automatic bank selection
– – – – – 1 0 1 Reserved
– – – – – 1 1 X Reserved
(2) Default values are in bold.
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Changes from Revision A (November 2008) to Revision B Page
• Added TAS5707A device to data sheet ................................................................................................................................ 1
• Changed PVDD maximum voltage to 26 V in Features ....................................................................................................... 1
• Added Applications section ................................................................................................................................................... 1
• Inserted paragraph on TAS5707A into Description section .................................................................................................. 1
• Changed PVDD maximum voltage to 26 V in simplified application diagram ...................................................................... 2
• Changed PVDD maximum voltage to 26 V in recommended operating conditions ............................................................. 7
• Added AVDD to output voltage test conditions ..................................................................................................................... 9
• Added rows to Electrical Characteristics fro OTW and OTW ............................................................................................... 9
• Changed OLPC typical value to 0.63 ms. ............................................................................................................................. 9
• Replaced text of Overtemperature Protection section ........................................................................................................ 18
• Added address information for the TAS5707A ................................................................................................................... 25
• Revised Sample Calculation for 3.23 Format table ............................................................................................................ 30
• Added 0xCA row to Register Summary table ..................................................................................................................... 36
• Revised 0xF9 row of Register Summary table ................................................................................................................... 36
• Corrected temperature from 145°C to 125°C ..................................................................................................................... 38
• Changed de-emphasis settings in register 0x03 table ........................................................................................................ 38
• Added text to Modulationi Limit Register section ................................................................................................................ 43
• Added text to the DRC Control section ............................................................................................................................... 47
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PACKAGE OPTION ADDENDUM
www.ti.com 9-Sep-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TAS5707APHP ACTIVE HTQFP PHP 48 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR 0 to 85 TAS5707A
TAS5707APHPR ACTIVE HTQFP PHP 48 1000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR 0 to 85 TAS5707A
TAS5707PHP ACTIVE HTQFP PHP 48 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR 0 to 85 TAS5707
TAS5707PHPR ACTIVE HTQFP PHP 48 1000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR 0 to 85 TAS5707
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com 9-Sep-2014
Addendum-Page 2
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TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
TAS5707APHPR HTQFP PHP 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
TAS5707APHPR HTQFP PHP 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
TAS5707PHPR HTQFP PHP 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 4-Jun-2014
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TAS5707APHPR HTQFP PHP 48 1000 367.0 367.0 38.0
TAS5707APHPR HTQFP PHP 48 1000 336.6 336.6 31.8
TAS5707PHPR HTQFP PHP 48 1000 336.6 336.6 31.8
PACKAGE MATERIALS INFORMATION
www.ti.com 4-Jun-2014
Pack Materials-Page 2
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tm
March 2009
FDS6679AZ P-Channel PowerTrench
® MOSFET
©2009 Fairchild Semiconductor Corporation
FDS6679AZ Rev. B2
1 www.fairchildsemi.com
FDS6679AZ
P-Channel PowerTrench® MOSFET
-30V, -13A, 9mΩ
General Description
This P-Channel MOSFET is producted using Fairchild
Semiconductor’s advanced PowerTrench process that has
been especially tailored to minimize the on-state
resistance.
This device is well suited for Power Management and load
switching applications common in Notebook Computers
and Portable Battery Packs.
Features
Max rDS(on) = 9.3mΩ at VGS = -10V, ID = -13A
Max rDS(on) = 14.8mΩ at VGS = -4.5V, ID = -11A
Extended VGS range (-25V) for battery applications
HBM ESD protection level of 6kV typical (note 3)
High performance trench technology for extremely low
rDS(on)
High power and current handing capability
RoHS Compliant
S
D
S S SO-8
D
D
D
G
1
7
5
2
8
4
6 3
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Thermal Characteristics
Package Marking and Ordering Information
Symbol Parameter Ratings Units
VDS Drain to Source Voltage -30 V
VGS Gate to Source Voltage ±25 V
ID
Drain Current -Continuous (Note 1a) -13 A
-Pulsed -65
PD
Power Dissipation for Single Operation (Note 1a) 2.5
(Note 1b) 1.2 W
(Note 1c) 1.0
TJ, TSTG Operating and Storage Temperature -55 to +150 °C
RθJA Thermal Resistance , Junction to Ambient (Note 1a) 50 °C/W
RθJC Thermal Resistance , Junction to Case (Note 1) 25 °C/W
Device Marking Device Reel Size Tape Width Quantity
FDS6679AZ FDS6679AZ 13’’ 12mm 2500 units
FDS6679AZ P-Channel PowerTrench® MOSFET
©2009 Fairchild Semiconductor Corporation
2 www.fairchildsemi.com
FDS6679AZ Rev. B2
Electrical Characteristics
T
J = 25°C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics BVDSS Drain to Source Breakdown Voltage
I
D = -250
µA, VGS = 0V -30
V
∆
BVDSS
∆
T
J
Breakdown Voltage Temperature
Coefficient
I
D = -250
µA, referenced to
25
°
C -20 mV/°C
IDSS Zero Gate Voltage Drain Current
VDS = -24V, VGS=0V -1
µ
A
IGSS Gate to Source Leakage Current
VGS = ±25V, VDS=0V ±10
µ
A
On Characteristics VGS(th) Gate to Source Threshold Voltage
VGS = VDS, I
D = -250
µ
A -1 -1.9 -3
V
∆
VGS(th)
∆
T
J
Gate to Source Threshold Voltage
Temperature Coefficient
I
D = -250
µA, referenced to
25°C 6.5 mV/°C
rDS(on) Drain to Source On Resistance
VGS = -10V, I
D = -13A 7.7 9.3
m
Ω
VGS = -4.5V, I
D = -11A 11.8 14.8
VGS = -10V, I
D = -13A,
T
J = 125
°
C 10.7 13.4
gFS Forward Transconductance
VDS = -5V, I
D = -13A 55
S
(Note 2)
Dynamic Characteristics Ciss Input Capacitance
VDS = -15V, VGS = 0V,
f = 1MHz
2890 3845 pF
Coss Output Capacitance 500 665 pF Crss Reverse Transfer Capacitance 495 745 pF
Switching Characteristics (Note 2) td(on) Turn-On Delay Time
VDD = -15V, I
D = -1A
VGS = -10V, RGS = 6
Ω
13 24 ns
t
r Rise Time 15 27 ns
td(off) Turn-Off Delay Time 210 336 ns tf Fall Time 92 148 ns Qg Total Gate Charge VDS = -15V, VGS = -10V, ID = -13A 68 96 nC Qg Total Gate Charge VDS = -15V, VGS = -5V, ID = -13A
38 54 nC
Qgs Gate to Source Gate Charge 10 nC Qgd Gate to Drain Charge 17 nC
Drain-Source Diode Characteristic VSD Source to Drain Diode Forward Voltage
VGS = 0V, I
S = -2.1A -0.7 -1.2
V
trr Reverse Recovery Time
I
F = -13A, di/dt = 100A/
µ
s 40 ns
Qrr Reverse Recovery Charge
I
F = -13A, di/dt = 100A/
µ
s -31 nC
Notes:
1:
R
θJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the
drain pins. R
θJC is guaranteed by design while
R
θCA is determined by the user’s board design.
Scale 1 : 1 on letter size paper
2: Pulse Test:Pulse Width <300
µs, Duty Cycle <2.0%
3: The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
a) 50
°C/W when
mounted on a 1 in
2
pad of 2 oz copper
b)105
°C/W when
mounted on a .04 in
2
pad of 2 oz copper
minimun pad
c) 125
°C/W when
mounted on a
FDS6679AZ P-Channel PowerTrench® MOSFET
©2009 Fairchild Semiconductor Corporation
3 www.fairchildsemi.com
FDS6679AZ Rev. B2
Typical Characteristics
T
J = 25°C unless otherwise noted
Figure 1. On Region Characteristics
01234
0
10
20
30
40
50
60
70
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5%MAX
VGS = -5V
VGS = -4V
VGS = -3V
VGS = -3.5V
VGS = -4.5V
VGS = -10V
-ID, DRAIN CURRENT (A)
-VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 2. Normalized
0 10 20 30 40 50 60 70
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5%MAX
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
-I
D, DRAIN CURRENT(A) VGS = -10V VGS = -5V VGS = -4.5V VGS = -4V
VGS = -3.5V
On-Resistance vs Drain
Current and Gate Voltage
Figure 3.
-80 -40 0 40 80 120 160
0.6
0.8
1.0
1.2
1.4
1.6
I
D = -13A VGS = -10V
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
T
J, JUNCTION TEMPERATURE
(
o
C
)
Normalized On Resistance vs Junction
Temperature
Figure 4.
3.0 4.5 6.0 7.5 9.0 0
10
20
30
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5%MAX TJ = 150oC TJ = 25oC
ID = -13A
rDS(on), DRAIN TO SOURCE
ON-RESISTANCE (mΩ)
-VGS, GATE TO SOURCE VOLTAGE (V)
10
On-Resistance vs Gate to Source
Voltage
Figure 5. Transfer Characteristics
2.0 2.5 3.0 3.5 4.0 4.5 0
10
20
30
40
50
60
70
PULSE DURATION = 80
µ
s
DUTY CYCLE = 0.5%MAX
T
J = -55
o
C
T
J = 25
o
C
TJ = 150
o
C
-ID, DRAIN CURRENT (A)
-VGS, GATE TO SOURCE VOLTAGE (V)
Figure 6.
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
1E-3
0.01
0.11
10
100
T
J = -55
o
C
T
J = 25
o
C
TJ = 150
o
C
VGS = 0V
-IS, REVERSE DRAIN CURRENT (A)
-VSD, BODY DIODE FORWARD VOLTAGE (V)
Source to Drain Diode Forward
Voltage vs Source Current
FDS6679AZ P-Channel PowerTrench® MOSFET
©2009 Fairchild Semiconductor Corporation
4 www.fairchildsemi.com
FDS6679AZ Rev. B2
Figure 7.
0 15 30 45 60 75
02468
10
VDD = -20V
VDD = -10V
-VGS, GATE TO SOURCE VOLTAGE(V)
Q
g, GATE CHARGE(nC) VDD = -15V
Gate Charge Characteristics Figure 8.
0.1 1 10
100
1000
10000
f = 1MHz VGS = 0V
CAPACITANCE (pF)
-VDS, DRAIN TO SOURCE VOLTAGE (V) Crss Coss Ciss
30
Capacitance vs Drain to Source Voltage
Figure 9. I
g vs VGS
0 5 10 15 20 25 30 35
1E-4
1E-3
0.01
0.11
10
100
1000
TJ = 150
o
CT
J = 25
o
C
-Ig(uA)
-VGS(V)
Figure 10.
10-2 10-1 10
0 10
1 10
2
1
10
TJ = 25
o
C
TJ = 125
o
C
-IAS, AVALANCHE CURRENT(A)
20
t
AV, TIME IN AVALANCHE(ms)
Unclamped Inductive Switching
Capability
Figure 11.
25 50 75 100 125 150 02468
10
12
14
16
VGS = -10V
VGS = -4.5V
-ID, DRAIN CURRENT (A)
TA, AMBIENT TEMPERATURE
(
o
C
)
Maximum Continuous Drain Current vs
Ambient Temperature
Figure 12. Forward Bias Safe Operating Area
0.01 0.1 1 10 100
0.01
0.11
10
100
100 us
1 s
10 s
DC
100 ms
10 ms
1 ms
ID, DRAIN CURRENT (A)
VDS, DRAIN to SOURCE VOLTAGE (V)
THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE TJ = MAX RATED RθJA = 125 o
C/W
TA = 25
o
C
200
Typical Characteristics
T
J = 25°C unless otherwise noted
FDS6679AZ P-Channel PowerTrench® MOSFET
©2009 Fairchild Semiconductor Corporation
5 www.fairchildsemi.com
FDS6679AZ Rev. B2
Figure 13.
10-4 10-3 10-2 10-1 1 10 10
2 10
3
0.51
10
10
2
10
3
10
4
SINGLE PULSE RθJA = 125 o
C/W
TA = 25
o
C
VGS = -10 V
P(PK), PEAK TRANSIENT POWER (W)
t, PULSE WIDTH (sec)
Single Pulse Maximum Power Dissipation
Figure 14.
10-4 10-3 10-2 10-1 1 10 10
2 10
3 10-4
10-3
10-2
10-11
SINGLE PULSE RθJA = 125 o
C/W
DUTY CYCLE-DESCENDING ORDER
NORMALIZED THERMAL
IMPEDANCE, ZθJA
t, RECTANGULAR PULSE DURATION (sec)
D = 0.5
0.2
0.1
0.05
0.02
0.01
2
PDM
t
1
t
2
NOTES:
DUTY FACTOR: D = t
1/t
2
PEAK T
J = PDM x Z
θJA x R
θJA + TA
Junction-to-Ambient Transient Thermal Response Curve
Typical Characteristics
T
J = 25°C unless otherwise noted
6 www.fairchildsemi.com
FDS6679AZ P-Channel PowerTrench
® MOSFET
©2009 Fairchild Semiconductor Corporation
FDS6679AZ Rev. B2
Rev. I39
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The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not
intended to be an exhaustive list of all such trademarks.
*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE
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As used herein:
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and (c) whose failure to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury of the user.
2. A critical component in any component of a life support, device, or
system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Build it Now™
CorePLUS™
CorePOWER™
CROSSVOLT™
CTL™
Current Transfer Logic™
EcoSPARK®
EfficentMax™
EZSWITCH™ *
™
Fairchild®
Fairchild Semiconductor®
FACT Quiet Series™
FACT®
FAST®
FastvCore™
FlashWriter® *
FPS™
F-PFS™
FRFET®
Global Power ResourceSM
Green FPS™
Green FPS™ e-Series™
GTO™
IntelliMAX™
ISOPLANAR™
MegaBuck™
MICROCOUPLER™
MicroFET™
MicroPak™
MillerDrive™
MotionMax™
Motion-SPM™
OPTOLOGIC®
OPTOPLANAR®
®
PDP SPM™
Power-SPM™
PowerTrench®
PowerXS™
Programmable Active Droop™
QFET®
QS™
Quiet Series™
RapidConfigure™
™
Saving our world, 1mW /W /kW at a time™
SmartMax™
SMART START™
SPM®
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SupreMOS™
SyncFET™
®
The Power Franchise®
TinyBoost™
TinyBuck™
TinyLogic®
TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
TriFault Detect™
TRUECURRENT™*
µSerDes™
UHC®
Ultra FRFET™
UniFET™
VCX™
VisualMax™
XS™
tm
®
tm
tm
Datasheet Identification Product Status Definition
Advance Information Formative / In Design Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.
Preliminary First Production
Datasheet contains preliminary data; supplementary data will be published at a later
date. Fairchild Semiconductor reserves the right to make changes at any time without
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No Identification Needed Full Production Datasheet contains final specifications. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve the design.
Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild
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Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website,
www.Fairchildsemi.com, under Sales Support.
Counterfeiting of semiconductor parts is a growing problem in the industry. All manufactures of semiconductor products are experiencing counterfeiting of their
parts. Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed
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Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use.
Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail.
－ FC32 －
Plastic Film Capacitors
Metallized Polyester Film Capacitor
Type:ECQE(F)
Non-inductive construction using metallized Polyester
film with flame retardant epoxy resin coating
■Features
•Self-healing property
•Excellent electrical characteristics
•Flame retardant epoxy resin coating
•RoHS directive compliant
■Recommended Applications
•General purpose usage
❈Please contact us when applications are CD , ignitor etc.
■Explanation of Part Numbers
1 2 3 4 5 6 7 8 9 10 11 12
E C Q E
Product code Dielectric &
construction
Rated volt. Capacitance
F
Cap. Tol. Suffix Suffix
1
2
4
6
100 VDC
250 VDC
400 VDC
630 VDC
10
12
1A
2A
1000 VDC
1250 VDC
125 VAC
250 VAC
J
K
±5 %
±10 %
E C Q E
Product code Dielectric &
construction
Rated volt. Capacitance
R F
Suffix Cap. Tol. Suffix
■Specifications
●Explanation of Part Number for Odd Size Taping
Category temp. range
(Including temperature-rise on unit surface)
Rated voltage
Capacitance range
Capacitance tolerance
Dissipation factor (tan )
Withstand voltage
Insulation resistance (IR)
100 VDC, 250 VDC,400 VDC, 630 VDC, 1000 VDC, 1250 VDC,
125 VAC, 250 VAC
–40 ˚C to +105 ˚C
–40 ˚C to +105 ˚C
100 VDC, 250 VDC, 400 VDC, 630 VDC, 1000 VDC, 1250 VDC,
(Derating of rated voltage by 1.25 %/˚C at more than 85 ˚C)
125 VAC, 250 VAC
0.0010 µF to 10 µF (E12)
±5 %(J), ±10 %(K)
tan <=1.0 % (20 ˚C, 1 kHz)
•Rated volt. 100 V to 630 VDC
Between terminals : Rated volt.(VDC)✕150 % 60 s
•Rated volt. 1000 VDC, 1250 VDC
Between terminals : Rated volt. (VDC)✕175 % 2 s to 5 s or 1000 VAC 60 s
Between terminals to enclosure : 1500 VAC 60 s
•Rated volt. 125 VAC, 250 VAC
Between terminals : Rated volt.(VAC)✕230 % 60 s
Between terminals to enclosure : 1500 VAC 60 s
100 V to 630 VDC: C <= 0.33 µF : IR>=9000 MΩ (20 ˚C, 100 VDC, 60 s)
C > 0.33 µF : IR>=3000 MΩ . µF
1000 VDC, 1250 VDC: IR>=10000 MΩ (20 ˚C, 100 VDC, 60 s)
IR>=2000 MΩ (20 ˚C, 500 VDC, 60 s)
125 VAC, 250 VAC: C <= 0.47 µF : IR>=2000 MΩ (20 ˚C, 500 VDC, 60 s)
C > 0.47 µF : IR>=3000 MΩ . µF (20 ˚C, 100 VDC, 60 s)
❈ In case of applying voltage in alternating current (50 Hz or 60 Hz sine wave) to a capacitor with DC rated voltage, please
refer to the page of “Permissible voltage (R.M.S) in alternating current corresponding to DC rated voltage”.
❈ Voltage to be applied to ECQE1A (F) & ECQE2A (F) is only sine wave (50 Hz or 60 Hz).
Suffix
Blank
B
Z
3
6
Lead Form
Straight
Crimped lead
Cut lead
Crimped taping (Ammo)
Crimped taping (Ammo)
p Œ ¯ ¶ ‚ /P33-52 12.11.14 19:29 y [ W 32
Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use.
Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail.
－ FC33 －
Plastic Film Capacitors
■Dimensions in mm (not to scale)
Cut lead
■Packaging Specifications for Bulk Package
Packing quantity:100 pcs./bag
■Taping Specifications for Automatic Insertion
●Taping style
❈Refer to the page of taping specifications.
100 VDC
250 VDC
400 VDC
630 VDC
1000 VDC
1250 VDC
125 VAC
250 VAC
ECQE (F)
AD AS AB BCD E
0.56 to 0.68 ○ Ammo ( ) F3
0.82 to 1.0 ○ Ammo ( ) F3
1.2 to 3.3 ○ Ammo ( ) F3
1.2 to 3.3 ○ Ammo R( ) F
0.010 to 0.27 ○ Ammo ( ) F3
0.33 ○ Ammo ( ) F3
0.39 to 1.5 ○ Ammo ( ) F3
0.010 to 0.33 ○ Ammo R( ) F
0.39 to 1.5 ○ Ammo R( ) F
0.010 to 0.10 ○ Ammo ( ) F3
0.12 to 0.47 ○ Ammo ( ) F3
0.010 to 0.10 ○ Ammo R( ) F
0.12 to 0.47 ○ Ammo R( ) F
0.0010 to 0.033 ○ Ammo ( ) F3
0.039 to 0.047 ○ Ammo ( ) F3
0.056 to 0.22 ○ Ammo ( ) F3
0.0010 to 0.047 ○ Ammo R( ) F
0.056 to 0.22 ○ Ammo R( ) F
0.010 to 0.10 ○ Ammo R( ) F
0.0010 to 0.022 ○ Ammo R( ) F
0.010 to 0.068 ○ Ammo ( ) F6
0.010 to 0.068 ○ Ammo R( ) F
0.010 to 0.033 ○ Ammo ( ) F6
0.010 to 0.047 ○ Ammo R( ) F
0.056 to 0.22 ○ Ammo R( ) F
●Packaging Specifications
Cap. range
(µF)
Taping style Type Rated volt. Packing suffix Style
AD
AB
B
C
D
E
Lead Spacing
5.0 mm
5.0 mm
5.0 mm
5.0 mm
7.5 mm
7.5 mm
❈See the column
“Rating, Dimensions
& Quantity Box” for
packing quantity.
●Lead Spacing
Metallized Film
p Œ ¯ ¶ ‚ /P33-52 12.11.14 19:29 y [ W 33
Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use.
Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail.
－ FC34 －
Plastic Film Capacitors
■Rating, Dimensions & Quantity/Ammo Box
●Rated voltage : 250 VDC, Capacitance tolerance : ±5 %(J), ±10 %(K)
Style D: 0.010 µF to 0.33 µF
Style B: 0.39 µF to 10.0 µF Suffix for lead crimped or taped type
Cap. tol. code
▲ ▲
Suffix for lead crimped or taped type
Cap. tol. code
▲ ▲
■Rating, Dimensions & Quantity/Ammo Box
●Rated voltage : 100 VDC, Capacitance tolerance : ± 5 %(J), ±10 %(K)
0.56 12.0 5.5 10.9 15.9 10.0 10.0 1.0 0.60
0.68 12.0 6.0 11.9 16.9 10.0 10.0 1.0 0.60
0.82 12.0 6.0 13.5 18.5 10.0 10.0 1.0 0.60
1.0 12.0 6.7 14.0 19.0 10.0 10.0 1.0 0.60
1.2 18.5 5.5 12.8 17.8 15.0 10.0 1.0 0.60
1.5 18.5 6.0 13.4 18.4 15.0 10.0 1.0 0.80
1.8 18.5 6.5 14.4 19.4 15.0 10.0 1.0 0.80
2.2 18.5 7.0 15.0 20.0 15.0 10.0 1.0 0.80
2.7 18.5 8.0 15.8 20.8 15.0 10.0 1.0 0.80
3.3 18.5 8.5 16.5 21.5 15.0 10.0 1.0 0.80
3.9 26.0 7.0 16.4 21.4 22.5 15.0 1.0 0.80
4.7 26.0 7.5 17.0 22.0 22.5 15.0 1.0 0.80
5.6 26.0 8.3 17.5 22.5 22.5 15.0 1.0 0.80
6.8 26.0 9.0 18.5 23.5 22.5 15.0 1.0 0.80
8.2 26.0 10.0 20.0 25.0 22.5 15.0 1.5 0.80
10.0 26.0 11.5 21.0 26.0 22.5 15.0 1.5 0.80
Part No. Cap.
(µF)
Min. order Q'ty
Taping
500 －
－ －
－
Dimensions (mm)
L max. T max. Standard
5 mm Odd size
5 mm Odd size
7.5 mm
ø d
ECQE1564□F( )
ECQE1684□F( )
ECQE1824□F( )
ECQE1105□F( )
ECQE1125□F( )
ECQE1155□F( )
ECQE1185□F( )
ECQE1225□F( )
ECQE1275□F( )
ECQE1335□F( )
ECQE1395□F( )
ECQE1475□F( )
ECQE1565□F( )
ECQE1685□F( )
ECQE1825□F( )
ECQE1106□F( )
500
1,000
400 400
500
600
－
H max.
Straight Crimped lead Straight
F
Crimped lead
S
Straight
G max.
Bulk
500
style D: 0.056 µF to 1.0 µF
style B: 1.2 µF to 10.0 µF
Part No. Cap.
(µF)
Dimensions (mm)
L max. T max. ø d
ECQE2103□F( ) 0.010 10.3 4.3 7.4 12.4 7.5 7.5 1.0 0.60
ECQE2123□F( ) 0.012 10.3 4.4 7.5 12.5 7.5 7.5 1.0 0.60
ECQE2153□F( ) 0.015 10.3 4.4 7.5 12.5 7.5 7.5 1.0 0.60
ECQE2183□F( ) 0.018 10.3 4.4 7.5 12.5 7.5 7.5 1.0 0.60
ECQE2223□F( ) 0.022 10.3 4.4 7.5 12.5 7.5 7.5 1.0 0.60
ECQE2273□F( ) 0.027 10.3 4.4 7.5 12.5 7.5 7.5 1.0 0.60
ECQE2333□F( ) 0.033 10.3 4.5 7.5 12.5 7.5 7.5 1.0 0.60
ECQE2393□F( ) 0.039 10.3 4.5 7.5 12.5 7.5 7.5 1.0 0.60
ECQE2473□F( ) 0.047 10.3 4.5 7.5 12.5 7.5 7.5 1.0 0.60
ECQE2563□F( ) 0.056 10.3 4.8 7.9 12.9 7.5 7.5 1.0 0.60
ECQE2683□F( ) 0.068 10.3 4.5 7.5 12.5 7.5 7.5 1.0 0.60
ECQE2823□F( ) 0.082 10.3 4.9 8.0 13.0 7.5 7.5 1.0 0.60
ECQE2104□F( ) 0.10 10.3 5.8 8.4 13.4 7.5 7.5 1.0 0.60
ECQE2124□F( ) 0.12 10.3 6.0 9.0 14.0 7.5 7.5 1.0 0.60
ECQE2154□F( ) 0.15 10.3 6.0 10.8 15.8 7.5 7.5 1.0 0.60
ECQE2184□F( ) 0.18 12.0 5.0 10.3 15.3 10.0 10.0 1.0 0.60
ECQE2224□F( ) 0.22 12.0 5.5 10.5 15.5 10.0 10.0 1.0 0.60
ECQE2274□F( ) 0.27 12.0 6.0 11.5 16.5 10.0 10.0 1.0 0.60
ECQE2334□F( ) 0.33 12.0 6.5 12.0 17.0 10.0 10.0 1.0 0.60
ECQE2394□F( ) 0.39 18.5 4.9 12.0 17.0 15.0 10.0 1.0 0.60
ECQE2474□F( ) 0.47 18.5 5.3 12.5 17.5 15.0 10.0 1.0 0.60
ECQE2564□F( ) 0.56 18.5 5.5 13.0 18.0 15.0 10.0 1.0 0.60
ECQE2684□F( ) 0.68 18.5 6.0 13.5 18.5 15.0 10.0 1.0 0.80
ECQE2824□F( ) 0.82 18.5 6.5 14.5 19.5 15.0 10.0 1.0 0.80
ECQE2105□F( ) 1.0 18.5 7.4 15.0 20.0 15.0 10.0 1.0 0.80
ECQE2125□F( ) 1.2 18.5 8.0 15.9 20.9 15.0 10.0 1.0 0.80
ECQE2155□F( ) 1.5 18.5 9.0 16.8 21.8 15.0 10.0 1.0 0.80
ECQE2185□F( ) 1.8 26.0 7.5 15.5 20.5 22.5 15.0 1.0 0.80
ECQE2225□F( ) 2.2 26.0 8.5 16.3 21.3 22.5 15.0 1.0 0.80
ECQE2275□F( ) 2.7 26.0 9.4 17.0 22.0 22.5 15.0 1.0 0.80
ECQE2335□F( ) 3.3 26.0 10.3 18.0 23.0 22.5 15.0 1.5 0.80
ECQE2395□F( ) 3.9 26.0 11.0 20.5 25.5 22.5 15.0 1.5 0.80
ECQE2475□F( ) 4.7 26.0 12.0 21.5 26.5 22.5 15.0 1.5 0.80
ECQE2565□F( ) 5.6 31.0 11.8 21.0 26.0 27.5 22.5 1.5 0.80
ECQE2685□F( ) 6.8 31.0 13.0 22.4 27.4 27.5 22.5 1.5 0.80
ECQE2825□F( ) 8.2 31.0 14.3 23.5 28.5 27.5 22.5 1.5 0.80
ECQE2106□F( )10.0 31.0 15.9 25.8 30.8 27.5 22.5 1.5 0.80
1000
－
－ 1000
500
500
1000
400
500
400
300
－ －
H max.
Straight Crimped lead Straight
F
Crimped lead
S
Straight
G max.
500
Min. order Q'ty
Taping Standard
5 mm Odd size
5 mm Odd size
7.5 mm
Bulk
p Œ ¯ ¶ ‚ /P33-52 12.11.14 19:29 y [ W 34
Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use.
Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail.
－ FC35 －
Plastic Film Capacitors
■Rating, Dimensions & Quantity/Ammo Box
●Rated voltage : 400 VDC, Capacitance tolerance : ±5 %(J), ±10 %(K)
style D:0.010 µF to 0.10 µF
style B:0.12 µF to 2.2 µF
Suffix for lead crimped or taped type
Cap. tol. code
▲ ▲
Part No.
0.010 10.3 4.3 7.4 12.4 7.5 7.5 1.0 0.60
0.012 10.3 4.4 7.5 12.5 7.5 7.5 1.0 0.60
0.015 10.3 4.4 7.5 12.5 7.5 7.5 1.0 0.60
0.018 10.3 4.4 7.5 12.5 7.5 7.5 1.0 0.60
0.022 10.3 4.8 7.9 12.9 7.5 7.5 1.0 0.60
0.027 10.3 5.5 8.0 13.0 7.5 7.5 1.0 0.60
0.033 10.3 6.0 9.0 14.0 7.5 7.5 1.0 0.60
0.039 12.0 4.9 8.0 13.0 10.0 10.0 1.0 0.60
0.047 12.0 5.0 8.3 13.3 10.0 10.0 1.0 0.60
0.056 12.0 5.0 10.0 15.0 10.0 10.0 1.0 0.60
0.068 12.0 5.4 10.5 15.5 10.0 10.0 1.0 0.60
0.082 12.0 5.8 11.0 16.0 10.0 10.0 1.0 0.60
0.10 12.0 6.3 12.0 17.0 10.0 10.0 1.0 0.60
0.12 18.5 5.0 10.0 15.0 15.0 10.0 1.0 0.60
0.15 18.5 5.0 12.4 17.4 15.0 10.0 1.0 0.60
0.18 18.5 5.4 12.5 17.5 15.0 10.0 1.0 0.60
0.22 18.5 5.9 13.0 18.0 15.0 10.0 1.0 0.60
0.27 18.5 6.5 14.3 19.3 15.0 10.0 1.0 0.80
0.33 18.5 7.0 14.9 19.9 15.0 10.0 1.0 0.80
0.39 18.5 7.5 15.4 20.4 15.0 10.0 1.0 0.80
0.47 18.5 7.8 17.0 22.0 15.0 10.0 1.0 0.80
0.56 26.0 6.5 16.0 21.0 22.5 15.0 1.0 0.80
0.68 26.0 7.0 16.5 21.5 22.5 15.0 1.0 0.80
0.82 26.0 7.9 17.3 22.3 22.5 15.0 1.0 0.80
1.0 26.0 8.5 18.0 23.0 22.5 15.0 1.0 0.80
1.2 26.0 9.5 18.9 23.9 22.5 15.0 1.0 0.80
1.5 31.0 9.5 19.0 24.0 27.5 22.5 1.0 0.80
1.8 31.0 11.0 20.5 25.5 27.5 22.5 1.5 0.80
2.2 31.0 11.0 22.0 27.0 27.5 22.5 1.5 0.80
ECQE4103□F( )
ECQE4123□F( )
ECQE4153□F( )
ECQE4183□F( )
ECQE4223□F( )
ECQE4273□F( )
ECQE4333□F( )
ECQE4393□F( )
ECQE4473□F( )
ECQE4563□F( )
ECQE4683□F( )
ECQE4823□F( )
ECQE4104□F( )
ECQE4124□F( )
ECQE4154□F( )
ECQE4184□F( )
ECQE4224□F( )
ECQE4274□F( )
ECQE4334□F( )
ECQE4394□F( )
ECQE4474□F( )
ECQE4564□F( )
ECQE4684□F( )
ECQE4824□F( )
ECQE4105□F( )
ECQE4125□F( )
ECQE4155□F( )
ECQE4185□F( )
ECQE4225□F( )
Cap.
(µF)
1000
500
－
－
500
500
400
－ －
1000
Dimensions (mm)
L max. T max. φd H max.
Straight Crimped lead Straight
F
Crimped lead
S
Straight
G max.
500
Min. order Q'ty
Taping Standard
5 mm Odd size
5 mm Odd size
7.5 mm
Bulk
Metallized Film
p Œ ¯ ¶ ‚ /P33-52 12.11.14 19:29 y [ W 35
Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use.
Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail.
－ FC36 －
Plastic Film Capacitors
●Rated voltage : 630 VDC, Capacitance tolerance : ±5 %(J), ±10 %(K)
Suffix for lead crimped or taped type.
Cap. tol. code
▲ ▲
style D:0.010 µF to 0.047 µF
style B:0.0010 µF to 0.0082 µF, 0.056 µF to 2.2 µF
Part No.
0.0010 10.0 4.5 9.5 14.5 7.5 5.0 1.0 0.60
0.0012 10.0 4.5 10.0 15.0 7.5 5.0 1.0 0.60
0.0015 10.0 4.5 10.0 15.0 7.5 5.0 1.0 0.60
0.0018 10.0 4.5 10.0 15.0 7.5 5.0 1.0 0.60
0.0022 10.0 4.5 10.0 15.0 7.5 5.0 1.0 0.60
0.0027 10.0 4.5 10.0 15.0 7.5 5.0 1.0 0.60
0.0033 10.0 4.5 10.0 15.0 7.5 5.0 1.0 0.60
0.0039 10.0 4.5 10.0 15.0 7.5 5.0 1.0 0.60
0.0047 12.0 4.5 10.0 15.0 10.0 7.5 1.0 0.60
0.0056 12.0 4.5 10.0 15.0 10.0 7.5 1.0 0.60
0.0068 12.0 4.9 10.0 15.0 10.0 7.5 1.0 0.60
0.0082 12.0 4.5 10.0 15.0 10.0 7.5 1.0 0.60
0.010 12.0 4.5 7.5 12.5 10.0 10.0 1.0 0.60
0.012 12.0 4.5 7.8 12.8 10.0 10.0 1.0 0.60
0.015 12.0 5.0 8.2 13.2 10.0 10.0 1.0 0.60
0.018 12.0 4.9 10.0 15.0 10.0 10.0 1.0 0.60
0.022 12.0 5.3 10.5 15.5 10.0 10.0 1.0 0.60
0.027 12.0 5.5 10.9 15.9 10.0 10.0 1.0 0.60
0.033 12.0 6.0 11.9 16.9 10.0 10.0 1.0 0.60
0.039 12.0 6.0 13.4 18.4 10.0 10.0 1.0 0.60
0.047 12.0 6.5 13.5 18.5 10.0 10.0 1.0 0.60
0.056 18.5 5.4 10.5 15.5 15.0 10.0 1.0 0.60
0.068 18.5 5.8 11.0 16.0 15.0 10.0 1.0 0.60
0.082 18.5 6.5 12.0 17.0 15.0 10.0 1.0 0.60
0.10 18.5 6.3 14.0 19.0 15.0 10.0 1.0 0.60
0.12 18.5 6.3 14.5 19.5 15.0 10.0 1.0 0.80
0.15 18.5 7.5 15.4 20.4 15.0 10.0 1.0 0.80
0.18 18.5 8.0 16.0 21.0 15.0 10.0 1.0 0.80
0.22 18.5 9.0 16.5 21.5 15.0 10.0 1.0 0.80
0.27 26.0 7.0 16.5 21.5 22.5 15.0 1.0 0.80
0.33 26.0 7.8 17.0 22.0 22.5 15.0 1.0 0.80
0.39 26.0 8.5 17.9 22.9 22.5 15.0 1.0 0.80
0.47 26.0 9.3 18.5 23.5 22.5 15.0 1.0 0.80
0.56 26.0 10.0 20.0 25.0 22.5 15.0 1.5 0.80
0.68 26.0 11.5 21.0 26.0 22.5 15.0 1.5 0.80
0.82 31.0 11.3 20.5 25.5 27.5 22.5 1.5 0.80
1.0 31.0 12.5 21.9 26.9 27.5 22.5 1.5 0.80
1.2 31.0 13.5 23.0 28.0 27.5 22.5 1.5 0.80
1.5 31.0 15.3 24.7 29.7 27.5 22.5 1.5 0.80
1.8 31.0 16.8 27.0 32.0 27.5 22.5 1.5 0.80
2.2 31.0 19.5 29.0 34.0 27.5 22.5 1.5 0.80
ECQE6102□F( )
ECQE6122□F( )
ECQE6152□F( )
ECQE6182□F( )
ECQE6222□F( )
ECQE6272□F( )
ECQE6332□F( )
ECQE6392□F( )
ECQE6472□F( )
ECQE6562□F( )
ECQE6682□F( )
ECQE6822□F( )
ECQE6103□F( )
ECQE6123□F( )
ECQE6153□F( )
ECQE6183□F( )
ECQE6223□F( )
ECQE6273□F( )
ECQE6333□F( )
ECQE6393□F( )
ECQE6473□F( )
ECQE6563□F( )
ECQE6683□F( )
ECQE6823□F( )
ECQE6104□F( )
ECQE6124□F( )
ECQE6154□F( )
ECQE6184□F( )
ECQE6224□F( )
ECQE6274□F( )
ECQE6334□F( )
ECQE6394□F( )
ECQE6474□F( )
ECQE6564□F( )
ECQE6684□F( )
ECQE6824□F( )
ECQE6105□F( )
ECQE6125□F( )
ECQE6155□F( )
ECQE6185□F( )
ECQE6225□F( )
Cap.
(µF)
1000 －
1000
500
400
300
1000
500
400
－ －
500
－
Dimensions (mm)
L max. T max. φd H max.
Straight Crimped lead Straight
F
Crimped lead
S
Straight
G max.
500
Min. order Q'ty
Taping Standard
5 mm Odd size
5 mm Odd size
7.5 mm
Bulk
p Œ ¯ ¶ ‚ /P33-52 12.11.14 19:29 y [ W 36
Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use.
Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail.
－ FC37 －
Plastic Film Capacitors
■Rating, Dimensions & Quantity/Ammo Box
●Rated voltage : 1000 VDC, Note) 125 VAC, Capacitance tolerance : ±5 %(J), ±10 %(K)
Note) This type has two rated voltage, one is DC rated voltage another is AC rated voltage..
DC rated voltage is 1000 V, AC rated voltage is 125 V.
Making for rated voltage is「1000 V, 125 V 」
When capacitors use in secondary side of power source, and in case of applying voltage in altering current (50 Hz or 60 Hz sine wave)
to a capacitor, please refer to the page of ''Permissible voltage (R.M.S) in altering current corresponding to DC rated voltage''.
When capacitors use in primary side of power source, the rated voltage is shown 125 VAC. Voltage to be applied to capacitors in only
sine wave (50 Hz or 60 Hz).
AC rated capacitors complying with clause 1 of ''Electrical Appliance and Material Safety Law''. And not complying with clause 2 of
''Electrical Appliance and Material Safety Law'', in this case please use ECQUL type or ECQUG type
Part No.
0.010 15.5 6.0 11.0 16.0 12.5 12.5 1.0 0.60
0.012 15.5 6.0 12.0 17.0 12.5 12.5 1.0 0.60
0.015 15.5 7.0 12.5 17.5 12.5 12.5 1.0 0.60
0.018 15.5 7.5 13.0 20.0 12.5 12.5 1.0 0.80
0.022 15.5 7.5 15.5 22.5 12.5 12.5 1.0 0.80
0.027 21.0 6.0 13.0 18.0 17.5 12.5 1.0 0.80
0.033 21.0 6.5 14.0 19.0 17.5 12.5 1.0 0.80
0.039 21.0 7.0 14.5 19.5 17.5 12.5 1.0 0.80
0.047 21.0 7.5 15.5 20.5 17.5 12.5 1.0 0.80
0.056 21.0 7.5 17.0 22.0 17.5 12.5 1.0 0.80
0.068 21.0 8.5 18.0 23.0 17.5 12.5 1.0 0.80
0.082 21.0 9.0 18.5 23.5 17.5 12.5 1.0 0.80
0.10 21.0 10.0 20.0 25.0 17.5 12.5 1.0 0.80
0.12 26.0 9.0 18.5 23.5 22.5 17.5 1.0 0.80
0.15 26.0 10.0 20.0 25.0 22.5 17.5 1.5 0.80
0.18 26.0 10.5 22.0 27.0 22.5 17.5 1.5 0.80
0.22 26.0 12.0 23.0 28.0 22.5 17.5 1.5 0.80
ECQE10103□F( )
ECQE10123□F( )
ECQE10153□F( )
ECQE10183□F( )
ECQE10223□F( )
ECQE10273□F( )
ECQE10333□F( )
ECQE10393□F( )
ECQE10473□F( )
ECQE10563□F( )
ECQE10683□F( )
ECQE10823□F( )
ECQE10104□F( )
ECQE10124□F( )
ECQE10154□F( )
ECQE10184□F( )
ECQE10224□F( )
Cap.
(µF)
Min. order Q'ty
500
400
500
400
300
－
Dimensions (mm)
L max. T max. ø d 7.5 mm
H max.
Straight Crimped lead Straight
F
Crimped lead
S
Straight
G max.
500
Bulk Taping
Style D: 0.010 µF to 0.022 µF
Style B: 0.027 µF to 0.22 µF
Suffix for lead crimped or taped type.
Cap. tol. code
▲ ▲
Metallized Film
p Œ ¯ ¶ ‚ /P33-52 12.11.14 19:29 y [ W 37
Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use.
Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail.
－ FC38 －
Plastic Film Capacitors
■Rating, Dimensions & Quantity/Ammo Box
●Rated voltage : 1250 VDC, Note) 125 VAC, Capacitance tolerance : ±5 %(J), ±10 %(K)
Note) This type has two rated voltage, one is DC rated voltage another is AC rated voltage..
DC rated voltage is 1250 V, AC rated voltage is 125 V.
Making for rated voltage is「1250 V, 125 V 」
When capacitors use in secondary side of power source, and in case of applying voltage in altering current (50 Hz or 60 Hz sine wave)
to a capacitor, please refer to the page of ''Permissible voltage (R.M.S) in altering current corresponding to DC rated voltage''.
When capacitors use in primary side of power source, the rated voltage is shown 125 VAC. Voltage to be applied to capacitors in only
sine wave (50 Hz or 60 Hz).
AC rated capacitors complying with clause 1 of ''Electrical Appliance and Material Safety Law''. And not complying with clause 2 of
''Electrical Appliance and Material Safety Law'', in this case please use ECQUL type or ECQUG type
Style D: 0.0010 µF to 0.0068 µF
Style B: 0.0082 µF to 0.22 µF
Part No.
0.0010 15.5 6.0 11.0 16.0 12.5 10.0 1.0 0.60
0.0012 15.5 6.0 11.0 16.0 12.5 10.0 1.0 0.60
0.0015 15.5 6.0 11.0 16.0 12.5 10.0 1.0 0.60
0.0018 15.5 6.0 11.0 16.0 12.5 10.0 1.0 0.60
0.0022 15.5 6.0 11.5 16.5 12.5 10.0 1.0 0.60
0.0027 15.5 6.5 12.0 17.0 12.5 10.0 1.0 0.60
0.0033 15.5 6.0 11.5 16.5 12.5 10.0 1.0 0.60
0.0039 15.5 6.5 12.0 17.0 12.5 10.0 1.0 0.60
0.0047 15.5 7.0 12.5 17.5 12.5 10.0 1.0 0.60
0.0056 15.5 7.5 13.0 18.0 12.5 10.0 1.0 0.60
0.0068 15.5 7.5 15.0 20.0 12.5 10.0 1.0 0.60
0.0082 21.0 5.0 12.0 17.0 17.5 12.5 1.0 0.60
0.010 21.0 5.0 12.5 17.5 17.5 12.5 1.0 0.60
0.012 21.0 5.5 13.0 18.0 17.5 12.5 1.0 0.60
0.015 21.0 6.0 13.5 18.5 17.5 12.5 1.0 0.60
0.018 21.0 6.5 14.5 19.5 17.5 12.5 1.0 0.80
0.022 21.0 7.0 15.0 20.0 17.5 12.5 1.0 0.80
0.027 26.0 6.0 15.5 20.5 22.5 17.5 1.0 0.80
0.033 26.0 6.5 16.0 21.0 22.5 17.5 1.0 0.80
0.039 26.0 7.0 16.5 21.5 22.5 17.5 1.0 0.80
0.047 26.0 8.0 17.0 22.0 22.5 17.5 1.0 0.80
0.056 31.0 7.5 17.0 22.0 27.5 22.5 1.0 0.80
0.068 31.0 8.0 17.5 22.5 27.5 22.5 1.0 0.80
0.082 31.0 9.0 18.5 23.5 27.5 22.5 1.0 0.80
0.10 31.0 10.0 19.5 24.5 27.5 22.5 1.0 0.80
0.12 31.0 11.5 20.5 25.5 27.5 22.5 1.5 0.80
0.15 31.0 12.0 23.0 28.0 27.5 22.5 1.5 0.80
0.18 31.0 13.0 24.5 29.5 27.5 22.5 1.5 0.80
0.22 31.0 14.5 26.5 31.5 27.5 22.5 1.5 0.80
ECQE12102□F( )
ECQE12122□F( )
ECQE12152□F( )
ECQE12182□F( )
ECQE12222□F( )
ECQE12272□F( )
ECQE12332□F( )
ECQE12392□F( )
ECQE12472□F( )
ECQE12562□F( )
ECQE12682□F( )
ECQE12822□F( )
ECQE12103□F( )
ECQE12123□F( )
ECQE12153□F( )
ECQE12183□F( )
ECQE12223□F( )
ECQE12273□F( )
ECQE12333□F( )
ECQE12393□F( )
ECQE12473□F( )
ECQE12563□F( )
ECQE12683□F( )
ECQE12823□F( )
ECQE12104□F( )
ECQE12124□F( )
ECQE12154□F( )
ECQE12184□F( )
ECQE12224□F( )
Cap.
(µF)
Min. order Q'ty
500
400
500
Dimensions (mm)
L max. T max. ø d 7.5 mm
H max.
Straight Crimped lead Straight
F
Crimped lead
S
Straight
G max.
Bulk Taping
500
Suffix for lead crimped or taped type.
Cap. tol. code
▲ ▲
p Œ ¯ ¶ ‚ /P33-52 12.11.14 19:29 y [ W 38
Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use.
Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail.
－ FC39 －
Plastic Film Capacitors
■Rating, Dimensions & Quantity/Ammo Box
●Rated voltage : 125 VAC, Capacitance tolerance : ±5 %(J), ±10 %(K)
●Noise suppression Capacitors (Across-the-line)
style D:0.010 µF to 0.068 µF
Suffix for lead crimped or taped type.
Cap. tol. code
MF( )
Table 1
Notice for AC rated
AC rated capacitors complying with clause 1 of ''Electrical Appliance and Material Safety Law''.
As for clause 2 of ''Electrical Appliance and Material Safety Law'', please use ECQUL type or ECQUG type.
When using these capacitors as a across-the-line capacitor, it shall be required to follow either item 1. or item 2. condition.
1. Capacitor shall be connected in parallel with varistor (Specified varistor voltage in table 1.)
2. Voltage applied for capacitor shall not exceed other than specified in table 1, when using these capacitors.
Cap. Rated Voltage
125 VAC
Varistor voltage
250 V
Pulse voltage
250 V0–P
Part No.
0.010 10.5 4.5 7.5 12.5 7.5 7.5 1.0 0.60
0.012 10.5 4.4 7.5 12.5 7.5 7.5 1.0 0.60
0.015 10.5 4.4 7.5 12.5 7.5 7.5 1.0 0.60
0.018 10.5 4.4 7.5 12.5 7.5 7.5 1.0 0.60
0.022 10.5 4.4 7.5 12.5 7.5 7.5 1.0 0.60
0.027 10.5 4.4 7.5 12.5 7.5 7.5 1.0 0.60
0.033 10.5 4.5 7.8 12.8 7.5 7.5 1.0 0.60
0.039 10.5 4.5 7.8 12.8 7.5 7.5 1.0 0.60
0.047 10.5 5.5 8.0 13.0 7.5 7.5 1.0 0.60
0.056 10.5 5.9 8.5 13.5 7.5 7.5 1.0 0.60
0.068 10.5 6.3 9.4 14.4 7.5 7.5 1.0 0.60
ECQE1A103□F( )
ECQE1A123□F( )
ECQE1A153□F( )
ECQE1A183□F( )
ECQE1A223□F( )
ECQE1A273□F( )
ECQE1A333□F( )
ECQE1A393□F( )
ECQE1A473□F( )
ECQE1A563□F( )
ECQE1A683□F( )
Cap.
(µF)
1000
－
1000
500
Dimensions (mm)
L max. T max. φd H max.
Straight Crimped lead Straight
F
Crimped lead
S
Straight
G max.
500
Min. order Q'ty
Taping Standard
5 mm Odd size
5 mm Odd size
7.5 mm
Bulk
Metallized Film
p Œ ¯ ¶ ‚ /P33-52 12.11.14 19:29 y [ W 39
Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use.
Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail.
－ FC40 －
Plastic Film Capacitors
●Rated voltage : 250 VAC, Capacitance tolerance : ±5 %(J), ±10 %(K)
Noise suppression Capacitors (Across-the-line)
Style D:0.010 µF to 0.047 µF
Style B:0.056 µF to 0.47 µF
Table 1
❈Please consult us about Crimed lead type of 0.56 µF to 2.2 µF.
Notice for AC rated
AC rated capacitors complying with clause 1 of ''Electrical Appliance and Material Safety Law''.
As for clause 2 of ''Electrical Appliance and Material Safety Law'', please use ECQUL type or ECQUG type.
When using these capacitors as a across-the-line capacitor, it shall be required to follow either item 1. or item 2. condition.
1. Capacitor shall be connected in parallel with varistor (Specified varistor voltage in table 1.)
2. Voltage applied for capacitor shall not exceed other than specified in table 1, when using these capacitors.
Cap. Rated Voltage
250 VAC
Varistor voltage
470 V
Pulse voltage
630 V0–P
Suffix for lead crimped or taped type.
Cap. tol. code
MF( )
Part No.
0.010 12.5 5.5 10.8 15.8 10.0 10.0 1.0 0.60
0.012 12.5 6.0 11.5 16.5 10.0 10.0 1.0 0.60
0.015 12.5 6.3 9.9 14.9 10.0 10.0 1.0 0.60
0.018 12.5 6.0 11.9 16.9 10.0 10.0 1.0 0.60
0.022 12.5 6.0 11.5 16.5 10.0 10.0 1.0 0.60
0.027 12.5 5.5 10.9 15.9 10.0 10.0 1.0 0.60
0.033 12.5 6.0 11.9 16.9 10.0 10.0 1.0 0.60
0.039 12.5 6.0 13.4 18.4 10.0 10.0 1.0 0.60
0.047 12.5 6.5 14.4 19.4 10.0 10.0 1.0 0.60
0.056 18.5 5.4 10.5 15.5 15.0 10.0 1.0 0.60
0.068 18.5 5.8 11.0 16.0 15.0 10.0 1.0 0.60
0.082 18.5 6.3 12.0 17.0 15.0 10.0 1.0 0.60
0.10 18.5 6.3 14.0 19.0 15.0 10.0 1.0 0.60
0.12 18.5 6.8 14.5 19.5 15.0 10.0 1.0 0.80
0.15 18.5 7.5 15.4 20.4 15.0 10.0 1.0 0.80
0.18 18.5 8.0 16.0 21.0 15.0 10.0 1.0 0.80
0.22 18.5 9.0 16.9 21.9 15.0 10.0 1.0 0.80
0.27 26.0 7.0 16.5 21.5 22.5 15.0 1.0 0.80
0.33 26.0 7.8 17.0 22.0 22.5 15.0 1.0 0.80
0.39 26.0 8.5 17.9 22.9 22.5 15.0 1.0 0.80
0.47 26.0 9.3 18.5 23.5 22.5 15.0 1.0 0.80
0.56 26.0 10.0 20.0 ─ 22.5 ─ 1.0 0.80
0.68 26.0 11.5 21.0 ─ 22.5 ─ 1.0 0.80
0.82 26.0 13.0 22.5 ─ 22.5 ─ 1.0 0.80
1.0 31.0 12.5 21.9 ─ 27.5 ─ 1.5 0.80
1.2 31.0 13.5 23.0 ─ 27.5 ─ 1.5 0.80
1.5 31.0 15.3 24.7 ─ 27.5 ─ 1.5 0.80
1.8 31.0 16.8 27.0 ─ 27.5 ─ 1.5 0.80
2.2 31.0 19.5 29.0 ─ 27.5 ─ 1.5 0.80
ECQE2A103□F( )
ECQE2A123□F( )
ECQE2A153□F( )
ECQE2A183□F( )
ECQE2A223□F( )
ECQE2A273□F( )
ECQE2A333□F( )
ECQE2A393□F( )
ECQE2A473□F( )
ECQE2A563□F( )
ECQE2A683□F( )
ECQE2A823□F( )
ECQE2A104□F( )
ECQE2A124□F( )
ECQE2A154□F( )
ECQE2A184□F( )
ECQE2A224□F( )
ECQE2A274□F( )
ECQE2A334□F( )
ECQE2A394□F( )
ECQE2A474□F( )
ECQE2A564P( )( )
ECQE2A684P( )( )
ECQE2A824P( )( )
ECQE2A105P( )( )
ECQE2A125P( )( )
ECQE2A155P( )( )
ECQE2A185P( )( )
ECQE2A225P( )( )
Cap.
(µF)
500
1000
500
400
300
－
－
Dimensions (mm)
L max. T max. φd H max.
Straight Crimped lead Straight
F
Crimped lead
S
Straight
G max.
500
Min. order Q'ty
Taping Standard
5 mm Odd size
7.5 mm
Bulk
p Œ ¯ ¶ ‚ /P33-52 12.11.14 19:29 y [ W 40
Temperature Characteristics Frequency Characteristics
0.01
0.1
1
10
100
1000
10000
1 10 100 1000 10000
0
2
4
6
8
10
1 10 100 1000 10000
-10
-5
0
5
10
1 10 100 1000 10000
1.E+06
1.E+07
1.E+08
1.E+09
1.E+10
1.E+11
1.E+12
-60 -40 -20 0 20 40 60 80 100
0
2
4
6
8
10
-60 -40 -20 0 20 40 60 80 100
-10
-5
0
5
10
-60 -40 -20 0 20 40 60 80 100
ECQE(F) Type 100VDC Series (Metallized Polyester Film)
Erectrical Characteristics
at 1kHz
Temperature (Degree C)
Capacitance change (%) Dissipation factor (%)
Temperature (Degree C)
at 1kHz
at DC100V
Temperature (Degree C)
Insuration resistance (ohm)
Capacitance change (%)
Frequency (kHz)
Frequency (kHz)
Dissipation factor (%)
Frequency (kHz)
Impedance (ohm)
10uF
4.7uF
1.0uF
10uF
4.7uF
1.0uF
10uF
4.7uF
1.0uF
10uF
4.7uF
1.0uF
1.0uF
4.7uF
10uF
1.0uF
4.7uF
10uF
Rating
Voltage
Capacitance
Value(uF) Code dV/dt(V/us) Current(o-p)
(A)
0.56 564 12.32
0.68 684 15.0
0.82 824 18.0
1.00 105 22.0
1.20 125 13.2
1.50 155 17.1
1.80 185 19.8
2.20 225 24.2
2.70 275 29.7
3.30 335 36.3
3.90 395 23.4
4.70 475 28.2
5.60 565 33.6
6.80 685 40.8
8.20 825 49.2
10.00 106 60.0
Pulse Handling Capability (dV/dt)
(Max 10000cycles)
Voltage Derating by Temperature
Permissible Current Permissible Voltage
6
22
100VDC
11
0
20
40
60
80
100
120
-60 -40 -20 0 20 40 60 80 100 120
0.1
1
10
100
10 100 1000
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
10 100 1000
* Please consult Panasonic if your condition exceeds the above spec.
ECQE(F) Type 100VDC Series (Metallized Polyester Film)
Applicable Specifications
Frequency (kHz)
Permissible Current (Arms)
Permissible Voltage (Vrms)
(at sinewave)
Frequency (kHz)
Rated Voltage (VDC)
Surface Temperature of Capacitor(Degree C)
1.0uF
2.2uF
4.7uF
10uF
1.0uF
2.2uF
4.7uF
10uF
From 0.56uF to 10uF
Temperature Characteristics Frequency Characteristics
0.01
0.1
1
10
100
1000
10000
1 10 100 1000 10000 100000
0
2
4
6
8
10
1 10 100 1000 10000
-10
-5
0
5
10
1 10 100 1000 10000
1.E+06
1.E+07
1.E+08
1.E+09
1.E+10
1.E+11
1.E+12
-60 -40 -20 0 20 40 60 80 100
0
2
4
6
8
10
-60 -40 -20 0 20 40 60 80 100
-10
-5
0
5
10
-60 -40 -20 0 20 40 60 80 100
ECQE(F) Type 250VDC Series (Metallized Polyester Film)
Erectrical Characteristics
at 1kHz
Temperature (Degree C)
Capacitance change (%) Dissipation factor (%)
Temperature (Degree C)
at 1kHz
at DC100V
Temperature (Degree C)
Insuration resistance (ohm)
Capacitance change (%)
Frequency (kHz)
Frequency (kHz)
Dissipation factor (%)
Frequency (kHz)
Impedance (ohm)
10uF
1.0uF
0.1uF
10uF
1.0uF
0.1uF
10uF
1.0uF
0.01uF
10uF
1.0uF
0.1uF
0.1uF
1.0uF
10uF
0.1uF
1.0uF
10uF
0.01uF
0.01uF
0.1uF
0.01uF
0.01uF
0.01uF
Rating
Voltage
Capacitance
Value(uF) Code dV/dt(V/us) Current(o-p)
(A)
0.010 103 0.48
0.015 153 0.72
0.022 223 1.06
0.033 333 1.58
0.047 473 2.26
0.068 683 3.26
0.100 104 4.80
0.150 154 7.20
0.220 224 7.26
0.330 334 10.89
0.470 474 8.46
0.680 684 12.24
1.000 105 18.00
1.500 155 27.00
2.200 225 22.00
3.300 335 33.00
4.700 475 47.00
6.800 685 54.40
10.000 106 80.00
250VDC
Pulse Handling Capability (dV/dt) Voltage Derating by Temperature
(Max 10000cycles)
48
8
10
18
33
Permissible Current Permissible Voltage
0
50
100
150
200
250
300
-60 -40 -20 0 20 40 60 80 100 120
1
10
100
10 100 1000
0
1
2
3
4
5
10 100 1000
* Please consult Panasonic if your condition exceeds the above spec.
ECQE(F) Type 250VDC Series (Metallized Polyester Film)
Applicable Specifications
Frequency (kHz)
Permissible Current (Arms)
Permissible Voltage (Vrms)
(at sinewave)
Frequency (kHz)
Rated Voltage (VDC)
Surface Temperature of Capacitor(Degree C)
1.0uF
2.2uF
4.7uF
10uF
From 0.01uF to 10uF
0.47uF
0.22uF
0.10uF
0.047u
0.022u
0.01uF
0.01uF
0.022uF
0.047uF
0.10uF
0.22uF
0.47uF
1.0uF
2.2uF
4.7uF
10uF
Temperature Characteristics Frequency Characteristics
0.01
0.1
1
10
100
1000
10000
1 10 100 1000 10000 100000
0
2
4
6
8
10
1 10 100 1000 10000
-10
-5
0
5
10
-60 -40 -20 0 20 40 60 80 100
-10
-5
0
5
10
1 10 100 1000 10000
1.E+07
1.E+08
1.E+09
1.E+10
1.E+11
1.E+12
1.E+13
-60 -40 -20 0 20 40 60 80 100
0
2
4
6
8
10
-60 -40 -20 0 20 40 60 80 100
ECQE(F) Type 400VDC Series (Metallized Polyester Film)
Erectrical Characteristics
at 1kHz
Temperature (Degree C)
Capacitance change (%) Dissipation factor (%)
Temperature (Degree C)
at 1kHz
at DC100V
Temperature (Degree C)
Insuration resistance (ohm)
Capacitance change (%)
Frequency (kHz)
Frequency (kHz)
Dissipation factor (%)
Frequency (kHz)
Impedance (ohm)
2.2uF
1.0uF
0.1uF
2.2uF
1.0uF
0.1uF
2.2uF
1.0uF
0.1uF
0.01uF
0.01uF
0.01uF
0.01uF
0.1uF
1.0uF
2.2uF
0.01uF
0.1uF
1.0uF
2.2uF
2.2uF
1.0uF
0.1uF
0.01uF
Rating
Voltage
Capacitance
Value(uF) Code dV/dt(V/us) Current(o-p)
(A)
0.010 103 1.31
0.015 153 1.97
0.022 223 2.88
0.033 333 4.32
0.047 473 3.67
0.068 683 5.30
0.100 104 7.80
0.150 154 5.55
0.220 224 8.14
0.330 334 12.21
0.470 474 17.39
0.680 684 14.96
1.000 105 22.00
1.200 155 27.00
2.200 225 39.60
Permissible Voltage
Voltage Derating by Temperature
131
Permissible Current
Pulse Handling Capability (dV/dt)
(Max 10000cycles)
400VDC
78
37
22
18
0
100
200
300
400
500
-60 -40 -20 0 20 40 60 80 100 120
0
0.5
1
1.5
2
2.5
3
10 100 1000
1
10
100
10 100 1000
* Please consult Panasonic if your condition exceeds the above spec.
ECQE(F) Type 400VDC Series (Metallized Polyester Film)
Applicable Specifications
Frequency (kHz)
Permissible Current (Arms)
Permissible Voltage (Vrms)
(at sinewave)
Frequency (kHz)
Rated Voltage (VDC)
Surface Temperature of Capacitor(Degree C)
From 0.01uF to 2.2uF
2.2uF
1.0uF
0.47uF
0.22uF
0.1uF
0.047uF
0.022uF
0.01uF
0.01uF
0.022uF
0.047uF
0.1uF
0.22uF
0.47uF
1.0uF
2.2uF
Temperature Characteristics Frequency Characteristics
0.01
0.1
1
10
100
1000
10000
1 10 100 1000 10000 100000
0
2
4
6
8
10
1 10 100 1000 10000
-10
-5
0
5
10
1 10 100 1000 10000
1.E+07
1.E+08
1.E+09
1.E+10
1.E+11
1.E+12
1.E+13
-60 -40 -20 0 20 40 60 80 100
0
2
4
6
8
10
-60 -40 -20 0 20 40 60 80 100
-10
-5
0
5
10
-60 -40 -20 0 20 40 60 80 100
ECQE(F) Type 630VDC Series (Metallized Polyester Film)
Erectrical Characteristics
at 1kHz
Temperature (Degree C)
Capacitance change (%) Dissipation factor (%)
Temperature (Degree C)
at 1kHz
at DC100V
Temperature (Degree C)
Insuration resistance (ohm)
Capacitance change (%)
Frequency (kHz)
Frequency (kHz)
Dissipation factor (%)
Frequency (kHz)
Impedance (ohm)
2.2uF
1.0uF
0.1uF
2.2uF
1.0uF
0.1uF
1.0uF
0.1uF
0.01uF
0.01uF
0.01uF
0.01uF
0.1uF
1.0uF
2.2uF
0.01uF
0.1uF
1.0uF
2.2uF
2.2uF
1.0uF
0.1uF
0.01uF
2.2uF
Rating
Voltage
Capacitance
Value(uF) Code dV/dt(V/us) Current(o-p)
(A)
0.010 103 2.73
0.015 153 4.10
0.022 223 6.01
0.033 333 9.01
0.047 473 12.83
0.068 683 7.89
0.100 104 11.60
0.150 154 17.40
0.220 224 25.52
0.330 334 20.79
0.470 474 29.61
0.680 684 42.84
1.000 105 48.00
1.500 155 72.00
2.200 225 105.60
(Max 10000cycles)
273
Voltage Derating by Temperature
630VDC
Permissible Current Permissible Voltage
116
63
48
Pulse Handling Capability (dV/dt)
0
100
200
300
400
500
600
700
800
-60 -40 -20 0 20 40 60 80 100 120
1
10
100
10 100 1000
0
1
2
3
4
5
10 100 1000
* Please consult Panasonic if your condition exceeds the above spec.
ECQE(F) Type 630VDC Series (Metallized Polyester Film)
Applicable Specifications
Frequency (kHz)
Permissible Current (Arms)
Permissible Voltage (Vrms)
(at sinewave)
Frequency (kHz)
Rated Voltage (VDC)
Surface Temperature of Capacitor(Degree C)
From 0.01uF to 2.2uF
2.2uF
1.0uF
0.47uF
0.22uF
0.1uF
0.047uF
0.022uF
0.01uF
0.01uF
0.022uF
0.047uF
0.1uF
0.22uF
0.47uF
1.0uF
2.2uF
Temperature Characteristics Frequency Characteristics
0.01
0.1
1
10
100
1000
10000
1 10 100 1000 10000 100000
0
2
4
6
8
10
1 10 100 1000 10000
-10
-5
0
5
10
1 10 100 1000 10000
1.E+07
1.E+08
1.E+09
1.E+10
1.E+11
1.E+12
1.E+13
-60 -40 -20 0 20 40 60 80 100
0
2
4
6
8
10
-10
-5
0
5
10
-60 -40 -20 0 20 40 60 80 100
ECQE(F) Type 125VAC Series (Metallized Polyester Film)
Erectrical Characteristics
at 1kHz
Temperature (Degree C)
Capacitance change (%) Dissipation factor (%)
Temperature (Degree C)
at 1kHz
at DC100V
Temperature (Degree C)
Insuration resistance (ohm)
Capacitance change (%)
Frequency (kHz)
Frequency (kHz)
Dissipation factor (%)
Frequency (kHz)
Impedance (ohm)
0.47uF
0.1uF
0.047uF
0.47uF
0.1uF
0.047uF
0.47uF
0.1uF
0.01uF
0.47uF
0.1uF
0.047uF
0.047uF
0.1uF
0.47uF
0.047uF
0.1uF
0.47uF
0.01uF
0.01uF
0.047uF
0.01uF
0.01uF
0.01uF
Temperature Characteristics Frequency Characteristics
0.01
0.1
1
10
100
1000
10000
1 10 100 1000 10000 100000
0
2
4
6
8
10
1 10 100 1000 10000
-10
-5
0
5
10
1 10 100 1000 10000
1.E+07
1.E+08
1.E+09
1.E+10
1.E+11
1.E+12
1.E+13
-60 -40 -20 0 20 40 60 80 100
0
2
4
6
8
10
-60 -40 -20 0 20 40 60 80 100
-10
-5
0
5
10
-60 -40 -20 0 20 40 60 80 100
ECQE(F) Type 250VAC Series (Metallized Polyester Film)
Erectrical Characteristics
at 1kHz
Temperature (Degree C)
Capacitance change (%) Dissipation factor (%)
Temperature (Degree C)
at 1kHz
at DC100V
Temperature (Degree C)
Insuration resistance (ohm)
Capacitance change (%)
Frequency (kHz)
Frequency (kHz)
Dissipation factor (%)
Frequency (kHz)
Impedance (ohm)
0.47uF
0.1uF
0.047uF
0.47uF
0.1uF
0.047uF
0.47uF
0.1uF
0.01uF
0.47uF
0.1uF
0.047uF
0.047uF
0.1uF
0.47uF
0.047uF
0.1uF
0.47uF
0.01uF
0.01uF
0.047uF
0.01uF
0.01uF
0.01uF
Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use.
Should a safety concern arise regarding this product, please be sure to contact us immediately.
Aluminum Electrolytic Capacitors/ FR
– EEE-82 –
010 Sleeve
L 14 min. 3 min. =
=
L 16 : L±1.5
L 20 : L±2.0
Pressure relief
06.3 +
–
08
0D±0.5
F±0.5
0D±0.5
fd±0.05
■ Country of origin
Malaysia
Radial Lead Type
Series: FR Type: A
■ Specifi cations
Category Temp. Range –40 °C to +105 °C
Rated W.V. Range 6.3 V.DC to 100 V.DC
Nominal Cap. Range 4.7 μF to 8200 μF
Capacitance Tolerance ±20 % (120 Hz/+20 °C)
DC Leakage Cur rent I < 0.01 CV (μA) After 2 minutes
tan d
W.V. 6.3 10 16 25 35 50 63 100 (120 Hz/+20 °C) tan d 0.22 0.19 0.16 0.14 0.12 0.10 0.09 0.08
Add 0.02 per 1000 μF for products of 1000 μF or more.
Endurance
After following life test with DC voltage and +105 °C±2 °C ripple current value applied. (The sum
of DC and ripple peak voltage shall not exceed the rated working voltage) when the capacitors
are restored to 20 °C, the capacitors shall meet the limits specifi ed below.
Duration
05×11/ 06.3×11.2 : 5000 hours
08×11.5/ 010×12.5 : 6000 hours (✽ Only EEUFR1V331U (010×12.5) 5000 hours)
08×15/ 010×16 : 8000 hours, 08×20 : 9000 hours
010×20 to 010×25/ 012.5×20 to 012.5×35/ 016×20 to 016×25 : 10000 hours
Capacitance change ±25 % of initial measured value (6.3 V to 10 V : ±30 %)
tan d < 200 % of initial specifi ed value
DC leakage current < initial specifi ed value
Shelf Life After storage for 1000 hours at +105 °C±2 °C with no voltage applied and then being stabilized
at +20 °C, capacitors shall meet the limits specifi ed in Endurance. (With voltage treatment)
■ Di men sions in mm (not to scale)
W.V.(V.DC) Cap (μF) Frequency (Hz)
60 120 1 k 10 k 100 k
6.3 to 100
4.7 to 33 0.45 0.55 0.75 0.90 1.00
47 to 330 0.60 0.70 0.85 0.95 1.00
390 to 1000 0.65 0.75 0.90 0.98 1.00
1200 to 8200 0.75 0.80 0.95 1.00 1.00
■ Frequency correction factor for ripple current
Body Dia. 0D 5 6.3 8 10 12.5 16
Body Length L — — — — 12.5 to 25 30 to 35 —
Lead Dia. 0d 0.5 0.5 0.6 0.6 0.6 0.8 0.8
Lead space F 2.0 2.5 3.5 5.0 5.0 7.5
■ Features
● Low ESR (Same as FM Series)
● Endurance : 5000 h to 10000 h at +105 °C
● RoHS directive compliant
■ Attention
Not applicable for automotive
(Unit : mm)
06 Nov. 2014
Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use.
Should a safety concern arise regarding this product, please be sure to contact us immediately.
Aluminum Electrolytic Capacitors/ FR
– EEE-83 –
■ Case size/Impedance/Ripple current
W.V.(V.DC) 6.3 V to 35 V 50 V
Case size
(0D×L)
Imped ance
(Ω/100 kHz)
Ripple Current
(mA r.m.s./100 kHz)
Imped ance
(Ω/100 kHz)
Ripple Current
(mA r.m.s./100 kHz)
+20 °C –10 °C +105 °C +20 °C –10 °C +105 °C
5 × 11 0.300 1.000 280 0.340 1.130 250
6.3 × 11.2 0.130 0.430 455 0.140 0.460 405
8 × 11.5 0.056 0.168 950 0.061 0.183 870
8 × 15 0.041 0.123 1240 0.045 0.135 1140
8 × 20 0.030 0.090 1560 0.033 0.099 1430
10 × 12.5 0.043 0.114 1290 0.042 0.126 1170
10 × 16 0.028 0.078 1790 0.030 0.090 1650
10 × 20 0.020 0.057 2180 0.023 0.069 1890
10 × 25 0.018 0.054 2470 0.022 0.066 2150
12.5 × 20 0.018 0.045 2600 0.022 0.055 2260
12.5 × 25 0.015 0.038 3190 0.018 0.045 2660
12.5 × 30 0.013 0.033 3630 0.016 0.040 3160
12.5 × 35 0.012 0.030 3750 0.014 0.035 3270
16 × 20 0.017 0.043 3300 0.019 0.048 2870
16 × 25 0.014 0.035 3820 0.016 0.040 3320
W.V.(V.DC) 63 V
Case size
(0D×L)
Imped ance
(Ω/100 kHz)
Ripple Current
(mA r.m.s./100 kHz)
+20 °C –10 °C +105 °C
5 × 11 0.510 2.040 175
6.3 × 11.2 0.210 0.840 284
8 × 11.5 0.092 0.368 566
8 × 15 0.068 0.272 741
8 × 20 0.050 0.200 930
10 × 12.5 0.063 0.252 761
10 × 16 0.045 0.180 1073
10 × 20 0.035 0.140 1229
10 × 25 0.033 0.132 1500
12.5 × 20 0.033 0.125 1582
12.5 × 25 0.027 0.092 1995
12.5 × 30 0.024 0.082 2528
12.5 × 35 0.021 0.071 2780
16 × 20 0.029 0.093 2153
16 × 25 0.024 0.074 2988
W.V.(V.DC) 100 V
Case size
(0D×L)
Imped ance
(Ω/100 kHz)
Ripple Current
(mA r.m.s./100 kHz)
+20 °C –10 °C +105 °C
10 × 20 0.084 0.336 1500
06 Nov. 2014
Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use.
Should a safety concern arise regarding this product, please be sure to contact us immediately.
Aluminum Electrolytic Capacitors/ FR
– EEE-84 –
■ Standard Prod ucts
W.V. Cap.
(±20 %)
Case size Specifi cation Lead Length
Part No.
Min. Packaging Q'ty
Dia. Length
Ripple
Current
(100 kHz)
(+105 °C)
Impedance
(100 kHz)
(+20 °C)
Endurance
Lead
Dia.
Lead Space
Straight
Leads Taping Straight Taping
✽B
Taping
✽H
(V) (μF) (mm) (mm) (mA r.m.s.) (Ω) (hours) (mm) (mm) (mm) (mm) (pcs) (pcs)
6.3
150 5 11 280 0.300 5000 0.5 2.0 5.0 2.5 EEUFR0J151( ) 200 2000
220 6.3 11.2 455 0.130 5000 0.5 2.5 5.0 2.5 EEUFR0J221( ) 200 2000
330 6.3 11.2 455 0.130 5000 0.5 2.5 5.0 2.5 EEUFR0J331( ) 200 2000
470 6.3 11.2 455 0.130 5000 0.5 2.5 5.0 2.5 EEUFR0J471( ) 200 2000
820 8 11.5 950 0.056 6000 0.6 3.5 5.0 EEUFR0J821( ) 200 1000
1000 8 11.5 950 0.056 6000 0.6 3.5 5.0 EEUFR0J102( ) 200 1000
1200
8 15 1240 0.041 8000 0.6 3.5 5.0 EEUFR0J122L( ) 200 1000
10 12.5 1290 0.043 6000 0.6 5.0 5.0 EEUFR0J122( ) 200 500
1500 8 20 1560 0.030 9000 0.6 3.5 5.0 EEUFR0J152L( ) 200 1000
1800 10 16 1790 0.028 8000 0.6 5.0 5.0 EEUFR0J182( ) 200 500
2200 10 20 2180 0.020 10000 0.6 5.0 5.0 EEUFR0J222( ) 200 500
2700 10 25 2470 0.018 10000 0.6 5.0 5.0 EEUFR0J272L( ) 200 500
3300 10 25 2470 0.018 10000 0.6 5.0 5.0 EEUFR0J332L( ) 200 500
3900 12.5 20 2600 0.018 10000 0.6 5.0 5.0 EEUFR0J392( ) 200 500
4700 12.5 25 3190 0.015 10000 0.6 5.0 5.0 EEUFR0J472( ) 200 500
5600 12.5 30 3630 0.013 10000 0.8 5.0 EEUFR0J562L 100
6800
12.5 35 3750 0.012 10000 0.8 5.0 EEUFR0J682L 100
16 20 3300 0.017 10000 0.8 7.5 7.5 EEUFR0J682S( ) 100 250
8200 16 25 3820 0.014 10000 0.8 7.5 7.5 EEUFR0J822( ) 100 250
10
100 5 11 280 0.300 5000 0.5 2.0 5.0 2.5 EEUFR1A101( ) 200 2000
150 5 11 280 0.300 5000 0.5 2.0 5.0 2.5 EEUFR1A151( ) 200 2000
220 6.3 11.2 455 0.130 5000 0.5 2.5 5.0 2.5 EEUFR1A221( ) 200 2000
270 6.3 11.2 455 0.130 5000 0.5 2.5 5.0 2.5 EEUFR1A271( ) 200 2000
470 8 11.5 950 0.056 6000 0.6 3.5 5.0 EEUFR1A471( ) 200 1000
680 8 11.5 950 0.056 6000 0.6 3.5 5.0 EEUFR1A681( ) 200 1000
820 10 12.5 1290 0.043 6000 0.6 5.0 5.0 EEUFR1A821( ) 200 500
1000
10 16 1790 0.028 8000 0.6 5.0 5.0 EEUFR1A102( ) 200 500
8 15 1240 0.041 8000 0.6 3.5 5.0 EEUFR1A102L( ) 200 1000
1500
8 20 1560 0.030 9000 0.6 3.5 5.0 EEUFR1A152L( ) 200 1000
10 16 1790 0.028 8000 0.6 5.0 5.0 EEUFR1A152( ) 200 500
1800 10 20 2180 0.020 10000 0.6 5.0 5.0 EEUFR1A182( ) 200 500
2200 10 25 2470 0.018 10000 0.6 5.0 5.0 EEUFR1A222L( ) 200 500
3300 12.5 20 2600 0.018 10000 0.6 5.0 5.0 EEUFR1A332( ) 200 500
3900 12.5 25 3190 0.015 10000 0.6 5.0 5.0 EEUFR1A392( ) 200 500
4700
12.5 30 3630 0.013 10000 0.8 5.0 EEUFR1A472L 100
16 20 3300 0.017 10000 0.8 7.5 7.5 EEUFR1A472S( ) 100 250
5600 12.5 35 3750 0.012 10000 0.8 5.0 EEUFR1A562L 100
6800 12.5 35 3750 0.012 10000 0.8 5.0 EEUFR1A682L 100
16 25 3820 0.014 10000 0.8 7.5 7.5 EEUFR1A682( ) 100 250
· When requesting taped product, please put the letter "B" or "H" be tween the "( )". Lead wire pitch ✽B=5 mm, 7.5 mm, H=2.5 mm.
· Please refer to the page of “Taping Dimensions”.
06 Nov. 2014
Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use.
Should a safety concern arise regarding this product, please be sure to contact us immediately.
Aluminum Electrolytic Capacitors/ FR
– EEE-85 –
■ Standard Prod ucts
W.V. Cap.
(±20 %)
Case size Specifi cation Lead Length
Part No.
Min. Packaging Q'ty
Dia. Length
Ripple
Current
(100 kHz)
(+105 °C)
Impedance
(100 kHz)
(+20 °C)
Endurance
Lead
Dia.
Lead Space
Straight
Leads Taping Straight Taping
✽B
Taping
✽H
(V) (μF) (mm) (mm) (mA r.m.s.) (Ω) (hours) (mm) (mm) (mm) (mm) (pcs) (pcs)
16
68 5 11 280 0.300 5000 0.5 2.0 5.0 2.5 EEUFR1C680( ) 200 2000
100 5 11 280 0.300 5000 0.5 2.0 5.0 2.5 EEUFR1C101( ) 200 2000
120 6.3 11.2 455 0.130 5000 0.5 2.5 5.0 2.5 EEUFR1C121( ) 200 2000
220 6.3 11.2 455 0.130 5000 0.5 2.5 5.0 2.5 EEUFR1C221( ) 200 2000
470 8 11.5 950 0.056 6000 0.6 3.5 5.0 EEUFR1C471( ) 200 1000
680 8 15 1240 0.041 8000 0.6 3.5 5.0 EEUFR1C681L( ) 200 1000
10 12.5 1290 0.043 6000 0.6 5.0 5.0 EEUFR1C681( ) 200 500
1000 8 20 1560 0.030 9000 0.6 3.5 5.0 EEUFR1C102L( ) 200 1000
10 16 1790 0.028 8000 0.6 5.0 5.0 EEUFR1C102( ) 200 500
1500 10 20 2180 0.020 10000 0.6 5.0 5.0 EEUFR1C152( ) 200 500
10 25 2470 0.018 10000 0.6 5.0 5.0 EEUFR1C152L( ) 200 500
1800 10 25 2470 0.018 10000 0.6 5.0 5.0 EEUFR1C182L( ) 200 500
2200 12.5 20 2600 0.018 10000 0.6 5.0 5.0 EEUFR1C222( ) 200 500
2700 12.5 25 3190 0.015 10000 0.6 5.0 5.0 EEUFR1C272( ) 200 500
3300 12.5 30 3630 0.013 10000 0.8 5.0 EEUFR1C332L 100
16 20 3300 0.017 10000 0.8 7.5 7.5 EEUFR1C332S( ) 100 250
3900 12.5 35 3750 0.012 10000 0.8 5.0 EEUFR1C392L 100
16 20 3300 0.017 10000 0.8 7.5 7.5 EEUFR1C392S( ) 100 250
4700 12.5 35 3750 0.012 10000 0.8 5.0 EEUFR1C472L 100
16 25 3820 0.014 10000 0.8 7.5 7.5 EEUFR1C472( ) 100 250
5600 16 25 3820 0.014 10000 0.8 7.5 7.5 EEUFR1C562( ) 100 250
25
47 5 11 280 0.300 5000 0.5 2.0 5.0 2.5 EEUFR1E470( ) 200 2000
68 5 11 280 0.300 5000 0.5 2.0 5.0 2.5 EEUFR1E680( ) 200 2000
100 6.3 11.2 455 0.130 5000 0.5 2.5 5.0 2.5 EEUFR1E101( ) 200 2000
150 6.3 11.2 455 0.130 5000 0.5 2.5 5.0 2.5 EEUFR1E151( ) 200 2000
220 8 11.5 950 0.056 6000 0.6 3.5 5.0 EEUFR1E221( ) 200 1000
330 8 11.5 950 0.056 6000 0.6 3.5 5.0 EEUFR1E331( ) 200 1000
390 8 15 1240 0.041 8000 0.6 3.5 5.0 EEUFR1E391L( ) 200 1000
470
8 15 1240 0.041 8000 0.6 3.5 5.0 EEUFR1E471Y( ) 200 1000
8 20 1560 0.030 9000 0.6 3.5 5.0 EEUFR1E471L( ) 200 1000
10 12.5 1290 0.043 6000 0.6 5.0 5.0 EEUFR1E471( ) 200 500
560 8 20 1560 0.030 9000 0.6 3.5 5.0 EEUFR1E561L( ) 200 1000
680 8 20 1560 0.030 9000 0.6 3.5 5.0 EEUFR1E681L( ) 200 1000
10 16 1790 0.028 8000 0.6 5.0 5.0 EEUFR1E681( ) 200 500
820 10 20 2180 0.020 10000 0.6 5.0 5.0 EEUFR1E821( ) 200 500
1000 10 20 2180 0.020 10000 0.6 5.0 5.0 EEUFR1E102( ) 200 500
10 25 2470 0.018 10000 0.6 5.0 5.0 EEUFR1E102L( ) 200 500
1200 10 25 2470 0.018 10000 0.6 5.0 5.0 EEUFR1E122L( ) 200 500
1500 12.5 20 2600 0.018 10000 0.6 5.0 5.0 EEUFR1E152( ) 200 500
1800 12.5 25 3190 0.015 10000 0.6 5.0 5.0 EEUFR1E182( ) 200 500
16 20 3300 0.017 10000 0.8 7.5 7.5 EEUFR1E182S( ) 100 250
2200 12.5 30 3630 0.013 10000 0.8 5.0 EEUFR1E222L 100
16 20 3300 0.017 10000 0.8 7.5 7.5 EEUFR1E222S( ) 100 250
2700 12.5 35 3750 0.012 10000 0.8 5.0 EEUFR1E272L 100
16 20 3300 0.017 10000 0.8 7.5 7.5 EEUFR1E272S( ) 100 250
3300 16 25 3820 0.014 10000 0.8 7.5 7.5 EEUFR1E332( ) 100 250
· When requesting taped product, please put the letter "B" or "H" be tween the "( )". Lead wire pitch ✽B=5 mm, 7.5 mm, H=2.5 mm.
· Please refer to the page of “Taping Dimensions”.
06 Nov. 2014
Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use.
Should a safety concern arise regarding this product, please be sure to contact us immediately.
Aluminum Electrolytic Capacitors/ FR
– EEE-86 –
■ Standard Prod ucts
W.V. Cap.
(±20 %)
Case size Specifi cation Lead Length
Part No.
Min. Packaging Q'ty
Dia. Length
Ripple
Current
(100 kHz)
(+105 °C)
Impedance
(100 kHz)
(+20 °C)
Endurance
Lead
Dia.
Lead Space
Straight
Leads Taping Straight Taping
✽B
Taping
✽H
(V) (μF) (mm) (mm) (mA r.m.s.) (Ω) (hours) (mm) (mm) (mm) (mm) (pcs) (pcs)
35
33 5 11 280 0.300 5000 0.5 2.0 5.0 2.5 EEUFR1V330( ) 200 2000
68 6.3 11.2 455 0.130 5000 0.5 2.5 5.0 2.5 EEUFR1V680( ) 200 2000
100 8 11.5 950 0.056 6000 0.6 3.5 5.0 EEUFR1V101( ) 200 1000
180 8 11.5 950 0.056 6000 0.6 3.5 5.0 EEUFR1V181( ) 200 1000
220 8 11.5 950 0.056 6000 0.6 3.5 5.0 EEUFR1V221( ) 200 1000
270 8 15 1240 0.041 8000 0.6 3.5 5.0 EEUFR1V271L( ) 200 1000
10 12.5 1290 0.043 6000 0.6 5.0 5.0 EEUFR1V271( ) 200 500
330 10 12.5 1330 0.043 5000 0.6 5.0 5.0 EEUFR1V331U( ) 200 500
390 8 20 1560 0.030 9000 0.6 3.5 5.0 EEUFR1V391L( ) 200 1000
470 8 20 1560 0.030 9000 0.6 3.5 5.0 EEUFR1V471L( ) 200 1000
10 16 1790 0.028 8000 0.6 5.0 5.0 EEUFR1V471( ) 200 500
560 10 20 2180 0.020 10000 0.6 5.0 5.0 EEUFR1V561( ) 200 500
680 10 20 2180 0.020 10000 0.6 5.0 5.0 EEUFR1V681( ) 200 500
10 25 2470 0.018 10000 0.6 5.0 5.0 EEUFR1V681L( ) 200 500
820 10 25 2470 0.018 10000 0.6 5.0 5.0 EEUFR1V821L( ) 200 500
1000 12.5 20 2600 0.018 10000 0.6 5.0 5.0 EEUFR1V102( ) 200 500
1200 12.5 25 3190 0.015 10000 0.6 5.0 5.0 EEUFR1V122( ) 200 500
1500 12.5 30 3630 0.013 10000 0.8 5.0 EEUFR1V152L 100
16 20 3300 0.017 10000 0.8 7.5 7.5 EEUFR1V152S( ) 100 250
1800 12.5 35 3750 0.012 10000 0.8 5.0 EEUFR1V182L 100
16 25 3820 0.014 10000 0.8 7.5 7.5 EEUFR1V182( ) 100 250
2200 12.5 35 3750 0.012 10000 0.8 5.0 EEUFR1V222L 100
16 25 3820 0.014 10000 0.8 7.5 7.5 EEUFR1V222( ) 100 250
50
4.7 5 11 185 0.620 5000 0.5 2.0 5.0 2.5 EEUFR1H4R7( ) 200 2000
10 5 11 250 0.340 5000 0.5 2.0 5.0 2.5 EEUFR1H100( ) 200 2000
22 5 11 250 0.340 5000 0.5 2.0 5.0 2.5 EEUFR1H220( ) 200 2000
47 6.3 11.2 405 0.140 5000 0.5 2.5 5.0 EEUFR1H470( ) 200 2000
56 6.3 11.2 405 0.140 5000 0.5 2.5 5.0 2.5 EEUFR1H560( ) 200 2000
100 8 11.5 870 0.061 6000 0.6 3.5 5.0 EEUFR1H101( ) 200 1000
120 8 15 1140 0.045 8000 0.6 3.5 5.0 EEUFR1H121L( ) 200 1000
150 10 12.5 1170 0.042 6000 0.6 5.0 5.0 EEUFR1H151( ) 200 500
180 8 20 1430 0.033 9000 0.6 3.5 5.0 EEUFR1H181L( ) 200 1000
220 10 16 1650 0.030 8000 0.6 5.0 5.0 EEUFR1H221( ) 200 500
270 10 20 1890 0.023 10000 0.6 5.0 5.0 EEUFR1H271( ) 200 500
330 10 25 2150 0.022 10000 0.6 5.0 5.0 EEUFR1H331L( ) 200 500
470 12.5 20 2260 0.022 10000 0.6 5.0 5.0 EEUFR1H471( ) 200 500
560 12.5 25 2660 0.018 10000 0.6 5.0 5.0 EEUFR1H561( ) 200 500
680 12.5 30 3160 0.016 10000 0.8 5.0 EEUFR1H681L 100
820 12.5 35 3270 0.014 10000 0.8 5.0 EEUFR1H821L 100
16 20 2870 0.019 10000 0.8 7.5 7.5 EEUFR1H821S( ) 100 250
1000 16 25 3320 0.016 10000 0.8 7.5 7.5 EEUFR1H102( ) 100 250
63
18 5 11 175 0.510 5000 0.5 2.0 5.0 2.5 EEUFR1J180( ) 200 2000
47 6.3 11.2 284 0.210 5000 0.5 2.5 5.0 2.5 EEUFR1J470( ) 200 2000
82 8 11.5 566 0.092 6000 0.6 3.5 5.0 EEUFR1J820( ) 200 1000
100 8 15 741 0.068 8000 0.6 3.5 5.0 EEUFR1J101L( ) 200 1000
10 12.5 761 0.063 6000 0.6 5.0 5.0 EEUFR1J101( ) 200 500
120 8 20 930 0.050 9000 0.6 3.5 5.0 EEUFR1J121L( ) 200 1000
10 16 1073 0.045 8000 0.6 5.0 5.0 EEUFR1J121( ) 200 500
150 8 20 930 0.050 9000 0.6 3.5 5.0 EEUFR1J151L( ) 200 1000
10 16 1073 0.045 8000 0.6 5.0 5.0 EEUFR1J151( ) 200 500
180 10 20 1229 0.035 10000 0.6 5.0 5.0 EEUFR1J181( ) 200 500
220 10 25 1500 0.033 10000 0.6 5.0 5.0 EEUFR1J221L( ) 200 500
270
10 20 1229 0.035 10000 0.6 5.0 5.0 EEUFR1J271U( ) 200 500
10 25 1500 0.033 10000 0.6 5.0 5.0 EEUFR1J271L( ) 200 500
12.5 20 1582 0.033 10000 0.6 5.0 5.0 EEUFR1J271( ) 200 500
330 12.5 20 1582 0.033 10000 0.6 5.0 5.0 EEUFR1J331( ) 200 500
390 12.5 25 1995 0.027 10000 0.6 5.0 5.0 EEUFR1J391( ) 200 500
470 12.5 25 1995 0.027 10000 0.6 5.0 5.0 EEUFR1J471( ) 200 500
560 12.5 30 2528 0.024 10000 0.8 5.0 EEUFR1J561L 100
16 20 2153 0.029 10000 0.8 7.5 7.5 EEUFR1J561S( ) 100 250
680 12.5 35 2780 0.021 10000 0.8 5.0 EEUFR1J681L 100
820 16 25 2988 0.024 10000 0.8 7.5 7.5 EEUFR1J821( ) 100 250
100 100 10 20 1500 0.084 10000 0.6 5.0 5.0 EEUFR2A101( ) 200 500
· When requesting taped product, please put the letter "B" or "H" be tween the "( )". Lead wire pitch ✽B=5 mm, 7.5 mm, H=2.5 mm.
· Please refer to the page of “Taping Dimensions”.
06 Nov. 2014
Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use.
Should a safety concern arise regarding this product, please be sure to contact us immediately.
Aluminum Electrolytic Capacitors/ M
– EEE-111 –
010 Sleeve
L 14 min. 3 min. =
06.3
=L 16
: L±1.0
L 20 : L±2.0
Pressure relief +
–
08
0D+0.5
F±0.5
0D+0.5
fd±0.05
■ Features
● Endurance : 85 °C 2000 h
● Smaller than series SU
● RoHS directive compliant
Radial Lead Type
Series: M Type: A
■ Specifi cations
Category Temp. Range –40 °C to + 85 °C –25 °C to +85 °C
Rated W.V. Range 6.3 V.DC to 100 V.DC 160 V.DC to 450 V.DC
Nominal Cap. Range 2.2 μF to 22000 μF 1 μF to 470 μF
Capacitance Tolerance ±20 % (120 Hz/+20 °C)
DC Leakage Cur rent I < 0.01 CV or 3 (μA) After 2 minutes
(Whichever is greater) I < 0.06 CV +10 (μA) After 2 minutes
tan d Please see the attached standard products list
Endurance
After applying rated working voltage for 2000 hours at +85°C±2 °C, when the capacitors are
restored to 20 °C, capacitors shall meet the following limits.
Capacitance change ±20 % of initial measured value
tan d <150 % of initial specifi ed value
DC leakage current >
NXP Semiconductors LPC2468
Single-chip 16-bit/32-bit micro
20. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3
4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8
7 Functional description . . . . . . . . . . . . . . . . . . 24
7.1 Architectural overview . . . . . . . . . . . . . . . . . . 24
7.2 On-chip flash programming memory . . . . . . . 25
7.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 25
7.4 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.5 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 27
7.5.1 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 28
7.6 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 28
7.7 External memory controller. . . . . . . . . . . . . . . 28
7.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.8 General purpose DMA controller . . . . . . . . . . 29
7.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.9 Fast general purpose parallel I/O . . . . . . . . . . 30
7.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.10 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.11 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.11.1 USB device controller . . . . . . . . . . . . . . . . . . . 32
7.11.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.11.2 USB host controller. . . . . . . . . . . . . . . . . . . . . 32
7.11.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.11.3 USB OTG controller . . . . . . . . . . . . . . . . . . . . 33
7.11.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.12 CAN controller and acceptance filters . . . . . . 33
7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.13 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.14 10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.15 UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.16 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 35
7.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.17 SSP serial I/O controller . . . . . . . . . . . . . . . . . 35
7.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.18 SD/MMC card interface . . . . . . . . . . . . . . . . . 35
7.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.19 I2C-bus serial I/O controller . . . . . . . . . . . . . . 36
7.19.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.20 I2S-bus serial I/O controllers . . . . . . . . . . . . . 36
7.20.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.21 General purpose 32-bit timers/external event
counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.21.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.22 Pulse width modulator . . . . . . . . . . . . . . . . . . 38
7.22.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.23 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 39
7.23.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.24 RTC and battery RAM . . . . . . . . . . . . . . . . . . 39
7.24.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.25 Clocking and power control . . . . . . . . . . . . . . 40
7.25.1 Crystal oscillators. . . . . . . . . . . . . . . . . . . . . . 40
7.25.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 40
7.25.1.2 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 40
7.25.1.3 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 41
7.25.2 PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.25.3 Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 41
7.25.4 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.25.4.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.25.4.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.25.4.3 Power-down mode . . . . . . . . . . . . . . . . . . . . . 42
7.25.4.4 Deep power-down mode . . . . . . . . . . . . . . . . 43
7.25.4.5 Power domains . . . . . . . . . . . . . . . . . . . . . . . 43
7.26 System control . . . . . . . . . . . . . . . . . . . . . . . . 44
7.26.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.26.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 44
7.26.3 Code security (Code Read Protection - CRP) 44
7.26.4 AHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.26.5 External interrupt inputs . . . . . . . . . . . . . . . . . 45
7.26.6 Memory mapping control . . . . . . . . . . . . . . . . 45
7.27 Emulation and debugging . . . . . . . . . . . . . . . 45
7.27.1 EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 45
7.27.2 Embedded trace. . . . . . . . . . . . . . . . . . . . . . . 46
7.27.3 RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 47
9 Thermal characteristics . . . . . . . . . . . . . . . . . 48
10 Static characteristics . . . . . . . . . . . . . . . . . . . 49
10.1 Power-down mode . . . . . . . . . . . . . . . . . . . . . 52
10.2 Deep power-down mode . . . . . . . . . . . . . . . . 53
10.3 Electrical pin characteristics. . . . . . . . . . . . . . 55
11 Dynamic characteristics. . . . . . . . . . . . . . . . . 56
11.1 Internal oscillators . . . . . . . . . . . . . . . . . . . . . 57
11.2 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
11.3 USB interface. . . . . . . . . . . . . . . . . . . . . . . . . 57
11.4 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 58
NXP Semiconductors LPC2468
Single-chip 16-bit/32-bit micro
© NXP B.V. 2013. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 January 2013
Document identifier: LPC2468
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
11.5 Static external memory interface . . . . . . . . . . 59
11.6 Dynamic external memory interface . . . . . . . . 61
11.7 Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12 ADC electrical characteristics . . . . . . . . . . . . 65
13 DAC electrical characteristics . . . . . . . . . . . . 68
14 Application information. . . . . . . . . . . . . . . . . . 69
14.1 Suggested USB interface solutions . . . . . . . . 69
14.2 Crystal oscillator XTAL input and component
selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
14.3 RTC 32 kHz oscillator component selection. . 75
14.4 XTAL and RTCX Printed Circuit Board (PCB)
layout guidelines. . . . . . . . . . . . . . . . . . . . . . . 76
14.5 Standard I/O pin configuration . . . . . . . . . . . . 76
14.6 Reset pin configuration. . . . . . . . . . . . . . . . . . 77
15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 78
16 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 80
17 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 81
18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 82
18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 82
18.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
18.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 83
19 Contact information. . . . . . . . . . . . . . . . . . . . . 83
20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
1. General description
The LPC2141/42/44/46/48 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S
CPU with real-time emulation and embedded trace support, that combine the
microcontroller with embedded high-speed flash memory ranging from 32 kB to 512 kB. A
128-bit wide memory interface and a unique accelerator architecture enable 32-bit code
execution at the maximum clock rate. For critical code size applications, the alternative
16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty.
Due to their tiny size and low power consumption, LPC2141/42/44/46/48 are ideal for
applications where miniaturization is a key requirement, such as access control and
point-of-sale. Serial communications interfaces ranging from a USB 2.0 Full-speed
device, multiple UARTs, SPI, SSP to I2C-bus and on-chip SRAM of 8 kB up to 40 kB,
make these devices very well suited for communication gateways and protocol
converters, soft modems, voice recognition and low end imaging, providing both large
buffer size and high processing power. Various 32-bit timers, single or dual 10-bit ADC(s),
10-bit DAC, PWM channels and 45 fast GPIO lines with up to nine edge or level sensitive
external interrupt pins make these microcontrollers suitable for industrial control and
medical systems.
2. Features and benefits
2.1 Key features
16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.
8 kB to 40 kB of on-chip static RAM and 32 kB to 512 kB of on-chip flash memory.
128-bit wide interface/accelerator enables high-speed 60 MHz operation.
In-System Programming/In-Application Programming (ISP/IAP) via on-chip boot
loader software. Single flash sector or full chip erase in 400 ms and programming of
256 B in 1 ms.
EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging with the
on-chip RealMonitor software and high-speed tracing of instruction execution.
USB 2.0 Full-speed compliant device controller with 2 kB of endpoint RAM.
In addition, the LPC2146/48 provides 8 kB of on-chip RAM accessible to USB by DMA.
One or two (LPC2141/42 vs. LPC2144/46/48) 10-bit ADCs provide a total of 6/14
analog inputs, with conversion times as low as 2.44 s per channel.
Single 10-bit DAC provides variable analog output (LPC2142/44/46/48 only).
Two 32-bit timers/external event counters (with four capture and four compare
channels each), PWM unit (six outputs) and watchdog.
Low power Real-Time Clock (RTC) with independent power and 32 kHz clock input.
LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash
with ISP/IAP, USB 2.0 full-speed device, 10-bit ADC and DAC
Rev. 5 — 12 August 2011 Product data sheet
LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 12 August 2011 2 of 45
NXP Semiconductors LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers
Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400 kbit/s),
SPI and SSP with buffering and variable data length capabilities.
Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses.
Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package.
Up to 21 external interrupt pins available.
60 MHz maximum CPU clock available from programmable on-chip PLL with settling
time of 100 s.
On-chip integrated oscillator operates with an external crystal from 1 MHz to 25 MHz.
Power saving modes include Idle and Power-down.
Individual enable/disable of peripheral functions as well as peripheral clock scaling for
additional power optimization.
Processor wake-up from Power-down mode via external interrupt or BOD.
Single power supply chip with POR and BOD circuits:
CPU operating voltage range of 3.0 V to 3.6 V (3.3 V 10 %) with 5 V tolerant I/O
pads.
3. Ordering information
3.1 Ordering options
[1] While the USB DMA is the primary user of the additional 8 kB RAM, this RAM is also accessible at any time by the CPU as a general
purpose RAM for data and code storage.
Table 1. Ordering information
Type number Package
Name Description Version
LPC2141FBD64 LQFP64 plastic low profile quad flat package; 64 leads;
body 10 10 1.4 mm
SOT314-2
LPC2142FBD64
LPC2144FBD64
LPC2146FBD64
LPC2148FBD64
Table 2. Ordering options
Type number Flash
memory
RAM Endpoint
USB RAM
ADC (channels
overall)
DAC Temperature
range
LPC2141FBD64 32 kB 8 kB 2 kB 1 (6 channels) - 40 C to +85 C
LPC2142FBD64 64 kB 16 kB 2 kB 1 (6 channels) 1 40 C to +85 C
LPC2144FBD64 128 kB 16 kB 2 kB 2 (14 channels) 1 40 C to +85 C
LPC2146FBD64 256 kB 32 kB + 8 kB shared with
USB DMA[1]
2 kB 2 (14 channels) 1 40 C to +85 C
LPC2148FBD64 512 kB 32 kB + 8 kB shared with
USB DMA[1]
2 kB 2 (14 channels) 1 40 C to +85 C
LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 12 August 2011 3 of 45
NXP Semiconductors LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers
4. Block diagram
(1) Pins shared with GPIO.
(2) LPC2144/46/48 only.
(3) USB DMA controller with 8 kB of RAM accessible as general purpose RAM and/or DMA is available in LPC2146/48 only.
(4) LPC2142/44/46/48 only.
Fig 1. Block diagram
002aab560
system
clock
TRST(1)
TMS(1)
TCK(1)
TDI(1)
TDO(1)
XTAL2
XTAL1
AMBA AHB
(Advanced High-performance Bus)
INTERNAL
FLASH
CONTROLLER
AHB BRIDGE
EMULATION TRACE
MODULE
TEST/DEBUG
INTERFACE
AHB
AHB TO APB DECODER
BRIDGE
APB
DIVIDER
VECTORED
INTERRUPT
CONTROLLER
SYSTEM
FUNCTIONS
PLL0
USB
clock
PLL1
SYSTEM
CONTROL
32 kB/64 kB/128 kB/
256 kB/512 kB
FLASH
ARM7TDMI-S
LPC2141/42/44/46/48
INTERNAL
SRAM
CONTROLLER
8 kB/16 kB/
32 kB
SRAM
ARM7 local bus
SCL0, SCL1
SDA0, SDA1
4 × CAP0
4 × CAP1
8 × MAT0
8 × MAT1
I
2C-BUS SERIAL
INTERFACES 0 AND 1
CAPTURE/COMPARE
(W/EXTERNAL CLOCK)
TIMER 0/TIMER 1
EINT3 to EINT0 EXTERNAL
INTERRUPTS
D+
D−
UP_LED
CONNECT
VBUS
USB 2.0 FULL-SPEED
DEVICE CONTROLLER
WITH DMA(3)
SCK0, SCK1
MOSI0, MOSI1
MISO0, MISO1
AD0[7:6] and
AD0[4:1]
AD1[7:0](2)
SSEL0, SSEL1
SPI AND SSP
SERIAL INTERFACES
A/D CONVERTERS
0 AND 1(2)
TXD0, TXD1
RXD0, RXD1
DSR1(2),CTS1(2),
RTS1(2), DTR1(2)
DCD1(2),RI1(2)
AOUT(4) D/A CONVERTER UART0/UART1
P0[31:28] and
P0[25:0]
P1[31:16]
RTXC2
RTXC1
VBAT
REAL-TIME CLOCK GENERAL
PURPOSE I/O
PWM6 to PWM0 WATCHDOG
TIMER PWM0
P0[31:28] and
P0[25:0]
P1[31:16]
FAST GENERAL
PURPOSE I/O
8 kB RAM
SHARED WITH
USB DMA(3)
RST
LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 12 August 2011 4 of 45
NXP Semiconductors LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers
5. Pinning information
5.1 Pinning
Fig 2. LPC2141 pinning
LPC2141
P0.21/PWM5/CAP1.3 P1.20/TRACESYNC
P0.22/CAP0.0/MAT0.0 P0.17/CAP1.2/SCK1/MAT1.2
RTCX1 P0.16/EINT0/MAT0.2/CAP0.2
P1.19/TRACEPKT3 P0.15/EINT2
RTCX2 P1.21/PIPESTAT0
VSS VDD
VDDA VSS
P1.18/TRACEPKT2 P0.14/EINT1/SDA1
P0.25/AD0.4 P1.22/PIPESTAT1
D+ P0.13/MAT1.1
D− P0.12/MAT1.0
P1.17/TRACEPKT1 P0.11/CAP1.1/SCL1
P0.28/AD0.1/CAP0.2/MAT0.2 P1.23/PIPESTAT2
P0.29/AD0.2/CAP0.3/MAT0.3 P0.10/CAP1.0
P0.30/AD0.3/EINT3/CAP0.0 P0.9/RXD1/PWM6/EINT3
P1.16/TRACEPKT0 P0.8/TXD1/PWM4 P0.31/UP_LED/CONNECT P1.27/TDO
VSS VREF
P0.0/TXD0/PWM1 XTAL1
P1.31/TRST XTAL2
P0.1/RXD0/PWM3/EINT0 P1.28/TDI
P0.2/SCL0/CAP0.0
VSSA
VDD P0.23/VBUS
P1.26/RTCK RESET
VSS P1.29/TCK
P0.3/SDA0/MAT0.0/EINT1 P0.20/MAT1.3/SSEL1/EINT3
P0.4/SCK0/CAP0.1/AD0.6 P0.19/MAT1.2/MOSI1/CAP1.2
P1.25/EXTIN0 P0.18/CAP1.3/MISO1/MAT1.3
P0.5/MISO0/MAT0.1/AD0.7 P1.30/TMS
P0.6/MOSI0/CAP0.2
VDD
P0.7/SSEL0/PWM2/EINT2
VSS
P1.24/TRACECLK VBAT
002aab733
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 12 August 2011 5 of 45
NXP Semiconductors LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers
Fig 3. LPC2142 pinning
LPC2142
P0.21/PWM5/CAP1.3 P1.20/TRACESYNC
P0.22/CAP0.0/MAT0.0 P0.17/CAP1.2/SCK1/MAT1.2
RTCX1 P0.16/EINT0/MAT0.2/CAP0.2
P1.19/TRACEPKT3 P0.15/EINT2
RTCX2 P1.21/PIPESTAT0
VSS VDD
VDDA VSS
P1.18/TRACEPKT2 P0.14/EINT1/SDA1
P0.25/AD0.4/AOUT P1.22/PIPESTAT1
D+ P0.13/MAT1.1
D− P0.12/MAT1.0
P1.17/TRACEPKT1 P0.11/CAP1.1/SCL1
P0.28/AD0.1/CAP0.2/MAT0.2 P1.23/PIPESTAT2
P0.29/AD0.2/CAP0.3/MAT0.3 P0.10/CAP1.0
P0.30/AD0.3/EINT3/CAP0.0 P0.9/RXD1/PWM6/EINT3
P1.16/TRACEPKT0 P0.8/TXD1/PWM4 P0.31/UP_LED/CONNECT P1.27/TDO
VSS VREF
P0.0/TXD0/PWM1 XTAL1
P1.31/TRST XTAL2
P0.1/RXD0/PWM3/EINT0 P1.28/TDI
P0.2/SCL0/CAP0.0
VSSA
VDD P0.23/VBUS
P1.26/RTCK RESET
VSS P1.29/TCK
P0.3/SDA0/MAT0.0/EINT1 P0.20/MAT1.3/SSEL1/EINT3
P0.4/SCK0/CAP0.1/AD0.6 P0.19/MAT1.2/MOSI1/CAP1.2
P1.25/EXTIN0 P0.18/CAP1.3/MISO1/MAT1.3
P0.5/MISO0/MAT0.1/AD0.7 P1.30/TMS
P0.6/MOSI0/CAP0.2
VDD
P0.7/SSEL0/PWM2/EINT2
VSS
P1.24/TRACECLK VBAT
002aab734
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 12 August 2011 6 of 45
NXP Semiconductors LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers
Fig 4. LPC2144/46/48 pinning
LPC2144/2146/2148
P0.21/PWM5/AD1.6/CAP1.3 P1.20/TRACESYNC
P0.22/AD1.7/CAP0.0/MAT0.0 P0.17/CAP1.2/SCK1/MAT1.2
RTCX1 P0.16/EINT0/MAT0.2/CAP0.2
P1.19/TRACEPKT3 P0.15/RI1/EINT2/AD1.5
RTCX2 P1.21/PIPESTAT0
VSS VDD
VDDA VSS
P1.18/TRACEPKT2 P0.14/DCD1/EINT1/SDA1
P0.25/AD0.4/AOUT P1.22/PIPESTAT1
D+ P0.13/DTR1/MAT1.1/AD1.4
D− P0.12/DSR1/MAT1.0/AD1.3
P1.17/TRACEPKT1 P0.11/CTS1/CAP1.1/SCL1
P0.28/AD0.1/CAP0.2/MAT0.2 P1.23/PIPESTAT2
P0.29/AD0.2/CAP0.3/MAT0.3 P0.10/RTS1/CAP1.0/AD1.2
P0.30/AD0.3/EINT3/CAP0.0 P0.9/RXD1/PWM6/EINT3
P1.16/TRACEPKT0 P0.8/TXD1/PWM4/AD1.1 P0.31/UP_LED/CONNECT P1.27/TDO
VSS VREF
P0.0/TXD0/PWM1 XTAL1
P1.31/TRST XTAL2
P0.1/RXD0/PWM3/EINT0 P1.28/TDI
P0.2/SCL0/CAP0.0
VSSA
VDD P0.23/VBUS
P1.26/RTCK RESET
VSS P1.29/TCK
P0.3/SDA0/MAT0.0/EINT1 P0.20/MAT1.3/SSEL1/EINT3
P0.4/SCK0/CAP0.1/AD0.6 P0.19/MAT1.2/MOSI1/CAP1.2
P1.25/EXTIN0 P0.18/CAP1.3/MISO1/MAT1.3
P0.5/MISO0/MAT0.1/AD0.7 P1.30/TMS
P0.6/MOSI0/CAP0.2/AD1.0
VDD
P0.7/SSEL0/PWM2/EINT2
VSS
P1.24/TRACECLK VBAT
002aab735
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 12 August 2011 7 of 45
NXP Semiconductors LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers
5.2 Pin description
Table 3. Pin description
Symbol Pin Type Description
P0.0 to P0.31 I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for
each bit. Total of 31 pins of the Port 0 can be used as a general
purpose bidirectional digital I/Os while P0.31 is output only pin. The
operation of port 0 pins depends upon the pin function selected via the
pin connect block.
Pins P0.24, P0.26 and P0.27 are not available.
P0.0/TXD0/
PWM1
19[1] I/O P0.0 — General purpose input/output digital pin (GPIO).
O TXD0 — Transmitter output for UART0.
O PWM1 — Pulse Width Modulator output 1.
P0.1/RXD0/
PWM3/EINT0
21[2] I/O P0.1 — General purpose input/output digital pin (GPIO).
I RXD0 — Receiver input for UART0.
O PWM3 — Pulse Width Modulator output 3.
I EINT0 — External interrupt 0 input.
P0.2/SCL0/
CAP0.0
22[3] I/O P0.2 — General purpose input/output digital pin (GPIO).
I/O SCL0 — I
2C0 clock input/output. Open-drain output (for I2C-bus
compliance).
I CAP0.0 — Capture input for Timer 0, channel 0.
P0.3/SDA0/
MAT0.0/EINT1
26[3] I/O P0.3 — General purpose input/output digital pin (GPIO).
I/O SDA0 — I
2C0 data input/output. Open-drain output (for I2C-bus
compliance).
O MAT0.0 — Match output for Timer 0, channel 0.
I EINT1 — External interrupt 1 input.
P0.4/SCK0/
CAP0.1/AD0.6
27[4] I/O P0.4 — General purpose input/output digital pin (GPIO).
I/O SCK0 — Serial clock for SPI0. SPI clock output from master or input
to slave.
I CAP0.1 — Capture input for Timer 0, channel 1.
I AD0.6 — ADC 0, input 6.
P0.5/MISO0/
MAT0.1/AD0.7
29[4] I/O P0.5 — General purpose input/output digital pin (GPIO).
I/O MISO0 — Master In Slave Out for SPI0. Data input to SPI master or
data output from SPI slave.
O MAT0.1 — Match output for Timer 0, channel 1.
I AD0.7 — ADC 0, input 7.
P0.6/MOSI0/
CAP0.2/AD1.0
30[4] I/O P0.6 — General purpose input/output digital pin (GPIO).
I/O MOSI0 — Master Out Slave In for SPI0. Data output from SPI master
or data input to SPI slave.
I CAP0.2 — Capture input for Timer 0, channel 2.
I AD1.0 — ADC 1, input 0. Available in LPC2144/46/48 only.
P0.7/SSEL0/
PWM2/EINT2
31[2] I/O P0.7 — General purpose input/output digital pin (GPIO).
I SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave.
O PWM2 — Pulse Width Modulator output 2.
I EINT2 — External interrupt 2 input.
LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 12 August 2011 8 of 45
NXP Semiconductors LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers
P0.8/TXD1/
PWM4/AD1.1
33[4] I/O P0.8 — General purpose input/output digital pin (GPIO).
O TXD1 — Transmitter output for UART1.
O PWM4 — Pulse Width Modulator output 4.
I AD1.1 — ADC 1, input 1. Available in LPC2144/46/48 only.
P0.9/RXD1/
PWM6/EINT3
34[2] I/O P0.9 — General purpose input/output digital pin (GPIO).
I RXD1 — Receiver input for UART1.
O PWM6 — Pulse Width Modulator output 6.
I EINT3 — External interrupt 3 input.
P0.10/RTS1/
CAP1.0/AD1.2
35[4] I/O P0.10 — General purpose input/output digital pin (GPIO).
O RTS1 — Request to Send output for UART1. LPC2144/46/48 only.
I CAP1.0 — Capture input for Timer 1, channel 0.
I AD1.2 — ADC 1, input 2. Available in LPC2144/46/48 only.
P0.11/CTS1/
CAP1.1/SCL1
37[3] I/O P0.11 — General purpose input/output digital pin (GPIO).
I CTS1 — Clear to Send input for UART1. Available in LPC2144/46/48
only.
I CAP1.1 — Capture input for Timer 1, channel 1.
I/O SCL1 — I
2C1 clock input/output. Open-drain output (for I2C-bus
compliance)
P0.12/DSR1/
MAT1.0/AD1.3
38[4] I/O P0.12 — General purpose input/output digital pin (GPIO).
I DSR1 — Data Set Ready input for UART1. Available in
LPC2144/46/48 only.
O MAT1.0 — Match output for Timer 1, channel 0.
I AD1.3 — ADC 1 input 3. Available in LPC2144/46/48 only.
P0.13/DTR1/
MAT1.1/AD1.4
39[4] I/O P0.13 — General purpose input/output digital pin (GPIO).
O DTR1 — Data Terminal Ready output for UART1. LPC2144/46/48
only.
O MAT1.1 — Match output for Timer 1, channel 1.
I AD1.4 — ADC 1 input 4. Available in LPC2144/46/48 only.
P0.14/DCD1/
EINT1/SDA1
41[3] I/O P0.14 — General purpose input/output digital pin (GPIO).
I DCD1 — Data Carrier Detect input for UART1. LPC2144/46/48 only.
I EINT1 — External interrupt 1 input.
I/O SDA1 — I
2C1 data input/output. Open-drain output (for I2C-bus
compliance).
Note: LOW on this pin while RESET is LOW forces on-chip boot
loader to take over control of the part after reset.
P0.15/RI1/
EINT2/AD1.5
45[4] I/O P0.15 — General purpose input/output digital pin (GPIO).
I RI1 — Ring Indicator input for UART1. Available in LPC2144/46/48
only.
I EINT2 — External interrupt 2 input.
I AD1.5 — ADC 1, input 5. Available in LPC2144/46/48 only.
Table 3. Pin description …continued
Symbol Pin Type Description
LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 12 August 2011 9 of 45
NXP Semiconductors LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers
P0.16/EINT0/
MAT0.2/CAP0.2
46[2] I/O P0.16 — General purpose input/output digital pin (GPIO).
I EINT0 — External interrupt 0 input.
O MAT0.2 — Match output for Timer 0, channel 2.
I CAP0.2 — Capture input for Timer 0, channel 2.
P0.17/CAP1.2/
SCK1/MAT1.2
47[1] I/O P0.17 — General purpose input/output digital pin (GPIO).
I CAP1.2 — Capture input for Timer 1, channel 2.
I/O SCK1 — Serial Clock for SSP. Clock output from master or input to
slave.
O MAT1.2 — Match output for Timer 1, channel 2.
P0.18/CAP1.3/
MISO1/MAT1.3
53[1] I/O P0.18 — General purpose input/output digital pin (GPIO).
I CAP1.3 — Capture input for Timer 1, channel 3.
I/O MISO1 — Master In Slave Out for SSP. Data input to SPI master or
data output from SSP slave.
O MAT1.3 — Match output for Timer 1, channel 3.
P0.19/MAT1.2/
MOSI1/CAP1.2
54[1] I/O P0.19 — General purpose input/output digital pin (GPIO).
O MAT1.2 — Match output for Timer 1, channel 2.
I/O MOSI1 — Master Out Slave In for SSP. Data output from SSP master
or data input to SSP slave.
I CAP1.2 — Capture input for Timer 1, channel 2.
P0.20/MAT1.3/
SSEL1/EINT3
55[2] I/O P0.20 — General purpose input/output digital pin (GPIO).
O MAT1.3 — Match output for Timer 1, channel 3.
I SSEL1 — Slave Select for SSP. Selects the SSP interface as a slave.
I EINT3 — External interrupt 3 input.
P0.21/PWM5/
AD1.6/CAP1.3
1[4] I/O P0.21 — General purpose input/output digital pin (GPIO).
O PWM5 — Pulse Width Modulator output 5.
I AD1.6 — ADC 1, input 6. Available in LPC2144/46/48 only.
I CAP1.3 — Capture input for Timer 1, channel 3.
P0.22/AD1.7/
CAP0.0/MAT0.0
2[4] I/O P0.22 — General purpose input/output digital pin (GPIO).
I AD1.7 — ADC 1, input 7. Available in LPC2144/46/48 only.
I CAP0.0 — Capture input for Timer 0, channel 0.
O MAT0.0 — Match output for Timer 0, channel 0.
P0.23/VBUS 58[1] I/O P0.23 — General purpose input/output digital pin (GPIO).
I VBUS — Indicates the presence of USB bus power.
Note: This signal must be HIGH for USB reset to occur.
P0.25/AD0.4/
AOUT
9[5] I/O P0.25 — General purpose input/output digital pin (GPIO).
I AD0.4 — ADC 0, input 4.
O AOUT — DAC output. Available in LPC2142/44/46/48 only.
P0.28/AD0.1/
CAP0.2/MAT0.2
13[4] I/O P0.28 — General purpose input/output digital pin (GPIO).
I AD0.1 — ADC 0, input 1.
I CAP0.2 — Capture input for Timer 0, channel 2.
O MAT0.2 — Match output for Timer 0, channel 2.
Table 3. Pin description …continued
Symbol Pin Type Description
LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 12 August 2011 10 of 45
NXP Semiconductors LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers
P0.29/AD0.2/
CAP0.3/MAT0.3
14[4] I/O P0.29 — General purpose input/output digital pin (GPIO).
I AD0.2 — ADC 0, input 2.
I CAP0.3 — Capture input for Timer 0, channel 3.
O MAT0.3 — Match output for Timer 0, channel 3.
P0.30/AD0.3/
EINT3/CAP0.0
15[4] I/O P0.30 — General purpose input/output digital pin (GPIO).
I AD0.3 — ADC 0, input 3.
I EINT3 — External interrupt 3 input.
I CAP0.0 — Capture input for Timer 0, channel 0.
P0.31/UP_LED/
CONNECT
17[6] O P0.31 — General purpose output only digital pin (GPO).
O UP_LED — USB GoodLink LED indicator. It is LOW when device is
configured (non-control endpoints enabled). It is HIGH when the
device is not configured or during global suspend.
O CONNECT — Signal used to switch an external 1.5 k resistor under
the software control. Used with the SoftConnect USB feature.
Important: This is an digital output only pin. This pin MUST NOT be
externally pulled LOW when RESET pin is LOW or the JTAG port will
be disabled.
P1.0 to P1.31 I/O Port 1: Port 1 is a 32-bit bidirectional I/O port with individual direction
controls for each bit. The operation of port 1 pins depends upon the
pin function selected via the pin connect block. Pins 0 through 15 of
port 1 are not available.
P1.16/
TRACEPKT0
16[6] I/O P1.16 — General purpose input/output digital pin (GPIO). Standard
I/O port with internal pull-up.
O TRACEPKT0 — Trace Packet, bit 0.
P1.17/
TRACEPKT1
12[6] I/O P1.17 — General purpose input/output digital pin (GPIO). Standard
I/O port with internal pull-up.
O TRACEPKT1 — Trace Packet, bit 1.
P1.18/
TRACEPKT2
8[6] I/O P1.18 — General purpose input/output digital pin (GPIO). Standard
I/O port with internal pull-up.
O TRACEPKT2 — Trace Packet, bit 2.
P1.19/
TRACEPKT3
4[6] I/O P1.19 — General purpose input/output digital pin (GPIO). Standard
I/O port with internal pull-up.
O TRACEPKT3 — Trace Packet, bit 3.
P1.20/
TRACESYNC
48[6] I/O P1.20 — General purpose input/output digital pin (GPIO). Standard
I/O port with internal pull-up.
O TRACESYNC — Trace Synchronization.
Note: LOW on this pin while RESET is LOW enables pins P1.25:16 to
operate as Trace port after reset.
P1.21/
PIPESTAT0
44[6] I/O P1.21 — General purpose input/output digital pin (GPIO). Standard
I/O port with internal pull-up.
O PIPESTAT0 — Pipeline Status, bit 0.
P1.22/
PIPESTAT1
40[6] I/O P1.22 — General purpose input/output digital pin (GPIO). Standard
I/O port with internal pull-up.
O PIPESTAT1 — Pipeline Status, bit 1.
Table 3. Pin description …continued
Symbol Pin Type Description
LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 12 August 2011 11 of 45
NXP Semiconductors LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers
P1.23/
PIPESTAT2
36[6] I/O P1.23 — General purpose input/output digital pin (GPIO). Standard
I/O port with internal pull-up.
O PIPESTAT2 — Pipeline Status, bit 2.
P1.24/
TRACECLK
32[6] I/O P1.24 — General purpose input/output digital pin (GPIO). Standard
I/O port with internal pull-up.
O TRACECLK — Trace Clock.
P1.25/EXTIN0 28[6] I/O P1.25 — General purpose input/output digital pin (GPIO). Standard
I/O port with internal pull-up.
I EXTIN0 — External Trigger Input.
P1.26/RTCK 24[6] I/O P1.26 — General purpose input/output digital pin (GPIO).
I/O RTCK — Returned Test Clock output. Extra signal added to the JTAG
port. Assists debugger synchronization when processor frequency
varies. Bidirectional pin with internal pull-up.
Note: LOW on RTCK while RESET is LOW enables pins P1[31:26] to
operate as Debug port after reset.
P1.27/TDO 64[6] I/O P1.27 — General purpose input/output digital pin (GPIO).
O TDO — Test Data out for JTAG interface.
P1.28/TDI 60[6] I/O P1.28 — General purpose input/output digital pin (GPIO).
I TDI — Test Data in for JTAG interface.
P1.29/TCK 56[6] I/O P1.29 — General purpose input/output digital pin (GPIO).
I TCK — Test Clock for JTAG interface. This clock must be slower than
16 of the CPU clock (CCLK) for the JTAG interface to operate.
P1.30/TMS 52[6] I/O P1.30 — General purpose input/output digital pin (GPIO).
I TMS — Test Mode Select for JTAG interface.
P1.31/TRST 20[6] I/O P1.31 — General purpose input/output digital pin (GPIO).
I TRST — Test Reset for JTAG interface.
D+ 10[7] I/O USB bidirectional D+ line.
D 11[7] I/O USB bidirectional D line.
RESET 57[8] I External reset input: A LOW on this pin resets the device, causing
I/O ports and peripherals to take on their default states, and processor
execution to begin at address 0. TTL with hysteresis, 5 V tolerant.
XTAL1 62[9] I Input to the oscillator circuit and internal clock generator circuits.
XTAL2 61[9] O Output from the oscillator amplifier.
RTCX1 3[9][10] I Input to the RTC oscillator circuit.
RTCX2 5[9][10] O Output from the RTC oscillator circuit.
VSS 6, 18, 25, 42,
50
I Ground: 0 V reference.
VSSA 59 I Analog ground: 0 V reference. This should nominally be the same
voltage as VSS, but should be isolated to minimize noise and error.
VDD 23, 43, 51 I 3.3 V power supply: This is the power supply voltage for the core and
I/O ports.
Table 3. Pin description …continued
Symbol Pin Type Description
LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 12 August 2011 12 of 45
NXP Semiconductors LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers
[1] 5 V tolerant pad (no built-in pull-up resistor) providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.
[2] 5 V tolerant pad (no built-in pull-up resistor) providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. If
configured for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns.
[3] Open-drain 5 V tolerant digital I/O I2C-bus 400 kHz specification compatible pad. It requires external pull-up to provide an output
functionality.
[4] 5 V tolerant pad (no built-in pull-up resistor) providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog
input function. If configured for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. When
configured as an ADC input, digital section of the pad is disabled.
[5] 5 V tolerant pad (no built-in pull-up resistor) providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog
output function. When configured as the DAC output, digital section of the pad is disabled.
[6] 5 V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.
The pull-up resistor’s value typically ranges from 60 k to 300 k.
[7] Pad is designed in accordance with the Universal Serial Bus (USB) specification, revision 2.0 (Full-speed and Low-speed mode only).
[8] 5 V tolerant pad providing digital input (with TTL levels and hysteresis) function only.
[9] Pad provides special analog functionality.
[10] When unused, the RTCX1 pin can be grounded or left floating. For lowest power leave it floating.
The other RTC pin, RTCX2, should be left floating.
VDDA 7 I Analog 3.3 V power supply: This should be nominally the same
voltage as VDD but should be isolated to minimize noise and error.
This voltage is only used to power the on-chip ADC(s) and DAC.
VREF 63 I ADC reference voltage: This should be nominally less than or equal
to the VDD voltage but should be isolated to minimize noise and error.
Level on this pin is used as a reference for ADC(s) and DAC.
VBAT 49 I RTC power supply voltage: 3.3 V on this pin supplies the power to
the RTC.
Table 3. Pin description …continued
Symbol Pin Type Description
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6. Functional description
6.1 Architectural overview
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers (CISC). This simplicity results in a high instruction throughput
and impressive real-time interrupt response from a small and cost-effective processor
core.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
• The standard 32-bit ARM set.
• A 16-bit Thumb set.
The Thumb set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code.
Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM processor connected to a 16-bit memory system.
The particular flash implementation in the LPC2141/42/44/46/48 allows for full speed
execution also in ARM mode. It is recommended to program performance critical and
short code sections (such as interrupt service routines and DSP algorithms) in ARM
mode. The impact on the overall code size will be minimal but the speed can be increased
by 30 % over Thumb mode.
6.2 On-chip flash program memory
The LPC2141/42/44/46/48 incorporate a 32 kB, 64 kB, 128 kB, 256 kB and 512 kB flash
memory system respectively. This memory may be used for both code and data storage.
Programming of the flash memory may be accomplished in several ways. It may be
programmed In System via the serial port. The application program may also erase and/or
program the flash while the application is running, allowing a great degree of flexibility for
data storage field firmware upgrades, etc. Due to the architectural solution chosen for an
on-chip boot loader, flash memory available for user’s code on LPC2141/42/44/46/48 is
32 kB, 64 kB, 128 kB, 256 kB and 500 kB respectively.
The LPC2141/42/44/46/48 flash memory provides a minimum of 100000 erase/write
cycles and 20 years of data-retention.
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6.3 On-chip static RAM
On-chip static RAM may be used for code and/or data storage. The SRAM may be
accessed as 8-bit, 16-bit, and 32-bit. The LPC2141, LPC2142/44 and LPC2146/48
provide 8 kB, 16 kB and 32 kB of static RAM respectively.
In case of LPC2146/48 only, an 8 kB SRAM block intended to be utilized mainly by the
USB can also be used as a general purpose RAM for data storage and code storage and
execution.
6.4 Memory map
The LPC2141/42/44/46/48 memory map incorporates several distinct regions, as shown
in Figure 5.
In addition, the CPU interrupt vectors may be remapped to allow them to reside in either
flash memory (the default) or on-chip static RAM. This is described in Section 6.19
“System control”.
Fig 5. LPC2141/42/44/46/48 memory map
AHB PERIPHERALS
VPB PERIPHERALS
RESERVED ADDRESS SPACE
BOOT BLOCK (12 kB REMAPPED FROM
ON-CHIP FLASH MEMORY
RESERVED ADDRESS SPACE
0xFFFF FFFF
0xF000 0000
0xE000 0000
0xC000 0000
0x8000 0000
0x7FFF FFFF
0x7FD0 2000
TOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY
(LPC2148) 0x0004 0000
0x0007 FFFF
TOTAL OF 256 kB ON-CHIP NON-VOLATILE MEMORY
(LPC2146) 0x0002 0000
0x0003 FFFF
TOTAL OF 128 kB ON-CHIP NON-VOLATILE MEMORY
(LPC2144) 0x0001 0000
0x0001 FFFF
TOTAL OF 64 kB ON-CHIP NON-VOLATILE MEMORY
(LPC2142) 0x0000 8000
0x0000 FFFF
TOTAL OF 32 kB ON-CHIP NON-VOLATILE MEMORY
(LPC2141) 0x0000 0000
0x0000 7FFF
RESERVED ADDRESS SPACE 0x0008 0000
0x3FFF FFFF
8 kB ON-CHIP STATIC RAM (LPC2141) 0x4000 0000
0x4000 1FFF
16 kB ON-CHIP STATIC RAM (LPC2142/2144) 0x4000 2000
0x4000 3FFF
32 kB ON-CHIP STATIC RAM (LPC2146/2148) 0x4000 4000
0x4000 7FFF
RESERVED ADDRESS SPACE 0x4000 8000
0x7FCF FFFF
8 kB ON-CHIP USB DMA RAM (LPC2146/2148) 0x7FD0 0000
0x7FD0 1FFF
0x7FFF D000
0x7FFF CFFF
4.0 GB
3.75 GB
3.5 GB
3.0 GB
2.0 GB
1.0 GB
0.0 GB
002aab558
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6.5 Interrupt controller
The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and
categorizes them as Fast Interrupt reQuest (FIQ), vectored Interrupt ReQuest (IRQ), and
non-vectored IRQ as defined by programmable settings. The programmable assignment
scheme means that priorities of interrupts from the various peripherals can be dynamically
assigned and adjusted.
FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC
combines the requests to produce the FIQ signal to the ARM processor. The fastest
possible FIQ latency is achieved when only one request is classified as FIQ, because then
the FIQ service routine does not need to branch into the interrupt service routine but can
run from the interrupt vector location. If more than one request is assigned to the FIQ
class, the FIQ service routine will read a word from the VIC that identifies which FIQ
source(s) is (are) requesting an interrupt.
Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned
to this category. Any of the interrupt requests can be assigned to any of the 16 vectored
IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.
Non-vectored IRQs have the lowest priority.
The VIC combines the requests from all the vectored and non-vectored IRQs to produce
the IRQ signal to the ARM processor. The IRQ service routine can start by reading a
register from the VIC and jumping there. If any of the vectored IRQs are pending, the VIC
provides the address of the highest-priority requesting IRQs service routine, otherwise it
provides the address of a default routine that is shared by all the non-vectored IRQs. The
default routine can read another VIC register to see what IRQs are active.
6.5.1 Interrupt sources
Each peripheral device has one interrupt line connected to the Vectored Interrupt
Controller, but may have several internal interrupt flags. Individual interrupt flags may also
represent more than one interrupt source.
6.6 Pin connect block
The pin connect block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on chip peripherals. Peripherals should be connected to the appropriate pins
prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any
enabled peripheral function that is not mapped to a related pin should be considered
undefined.
The Pin Control Module with its pin select registers defines the functionality of the
microcontroller in a given hardware environment.
After reset all pins of Port 0 and Port 1 are configured as input with the following
exceptions: If debug is enabled, the JTAG pins will assume their JTAG functionality; if
trace is enabled, the Trace pins will assume their trace functionality. The pins associated
with the I2C0 and I2C1 interface are open drain.
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6.7 Fast general purpose parallel I/O (GPIO)
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back, as well as the current state of the port pins.
LPC2141/42/44/46/48 introduce accelerated GPIO functions over prior LPC2000 devices:
• GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing.
• Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
• All GPIO registers are byte addressable.
• Entire port value can be written in one instruction.
6.7.1 Features
• Bit-level set and clear registers allow a single instruction set or clear of any number of
bits in one port.
• Direction control of individual bits.
• Separate control of output set and clear.
• All I/O default to inputs after reset.
6.8 10-bit ADC
The LPC2141/42 contain one and the LPC2144/46/48 contain two analog to digital
converters. These converters are single 10-bit successive approximation analog to digital
converters. While ADC0 has six channels, ADC1 has eight channels. Therefore, total
number of available ADC inputs for LPC2141/42 is 6 and for LPC2144/46/48 is 14.
6.8.1 Features
• 10 bit successive approximation analog to digital converter.
• Measurement range of 0 V to VREF (2.5 V VREF VDDA).
• Each converter capable of performing more than 400000 10-bit samples per second.
• Every analog input has a dedicated result register to reduce interrupt overhead.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition on input pin or timer match signal.
• Global Start command for both converters (LPC2142/44/46/48 only).
6.9 10-bit DAC
The DAC enables the LPC2141/42/44/46/48 to generate a variable analog output. The
maximum DAC output voltage is the VREF voltage.
6.9.1 Features
• 10-bit DAC.
• Buffered output.
• Power-down mode available.
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• Selectable speed versus power.
6.10 USB 2.0 device controller
The USB is a 4-wire serial bus that supports communication between a host and a
number (127 max) of peripherals. The host controller allocates the USB bandwidth to
attached devices through a token based protocol. The bus supports hot plugging,
unplugging, and dynamic configuration of the devices. All transactions are initiated by the
host controller.
The LPC2141/42/44/46/48 is equipped with a USB device controller that enables
12 Mbit/s data exchange with a USB host controller. It consists of a register interface,
serial interface engine, endpoint buffer memory and DMA controller. The serial interface
engine decodes the USB data stream and writes data to the appropriate end point buffer
memory. The status of a completed USB transfer or error condition is indicated via status
registers. An interrupt is also generated if enabled.
A DMA controller (available in LPC2146/48 only) can transfer data between an endpoint
buffer and the USB RAM.
6.10.1 Features
• Fully compliant with USB 2.0 Full-speed specification.
• Supports 32 physical (16 logical) endpoints.
• Supports control, bulk, interrupt and isochronous endpoints.
• Scalable realization of endpoints at run time.
• Endpoint maximum packet size selection (up to USB maximum specification) by
software at run time.
• RAM message buffer size based on endpoint realization and maximum packet size.
• Supports SoftConnect and GoodLink LED indicator. These two functions are sharing
one pin.
• Supports bus-powered capability with low suspend current.
• Supports DMA transfer on all non-control endpoints (LPC2146/48 only).
• One duplex DMA channel serves all endpoints (LPC2146/48 only).
• Allows dynamic switching between CPU controlled and DMA modes (only in
LPC2146/48).
• Double buffer implementation for bulk and isochronous endpoints.
6.11 UARTs
The LPC2141/42/44/46/48 each contain two UARTs. In addition to standard transmit and
receive data lines, the LPC2144/46/48 UART1 also provides a full modem control
handshake interface.
Compared to previous LPC2000 microcontrollers, UARTs in LPC2141/42/44/46/48
introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers
to achieve standard baud rates such as 115200 with any crystal frequency above 2 MHz.
In addition, auto-CTS/RTS flow-control functions are fully implemented in hardware
(UART1 in LPC2144/46/48 only).
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6.11.1 Features
• 16 B Receive and Transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B
• Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• Transmission FIFO control enables implementation of software (XON/XOFF) flow
control on both UARTs.
• LPC2144/46/48 UART1 equipped with standard modem interface signals. This
module also provides full support for hardware flow control (auto-CTS/RTS).
6.12 I2C-bus serial I/O controller
The LPC2141/42/44/46/48 each contain two I2C-bus controllers.
The I2C-bus is bidirectional, for inter-IC control using only two wires: a Serial Clock Line
(SCL), and a Serial DAta line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the
capability to both receive and send information (such as memory)). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus, it can be
controlled by more than one bus master connected to it.
The I2C-bus implemented in LPC2141/42/44/46/48 supports bit rates up to 400 kbit/s
(Fast I2C-bus).
6.12.1 Features
• Compliant with standard I2C-bus interface.
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus can be used for test and diagnostic purposes.
6.13 SPI serial I/O controller
The LPC2141/42/44/46/48 each contain one SPI controller. The SPI is a full duplex serial
interface, designed to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master always sends a byte of data to the slave, and
the slave always sends a byte of data to the master.
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6.13.1 Features
• Compliant with SPI specification.
• Synchronous, Serial, Full Duplex, Communication.
• Combined SPI master and slave.
• Maximum data bit rate of one eighth of the input clock rate.
6.14 SSP serial I/O controller
The LPC2141/42/44/46/48 each contain one Serial Synchronous Port controller (SSP).
The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. However, only a single master and a
single slave can communicate on the bus during a given data transfer. The SSP supports
full duplex transfers, with data frames of 4 bits to 16 bits of data flowing from the master to
the slave and from the slave to the master. Often only one of these data flows carries
meaningful data.
6.14.1 Features
• Compatible with Motorola’s SPI, TI’s 4-wire SSI and National Semiconductor’s
Microwire buses.
• Synchronous serial communication.
• Master or slave operation.
• 8-frame FIFOs for both transmit and receive.
• Four bits to 16 bits per frame.
6.15 General purpose timers/external event counters
The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an
externally supplied clock and optionally generate interrupts or perform other actions at
specified timer values, based on four match registers. It also includes four capture inputs
to trap the timer value when an input signal transitions, optionally generating an interrupt.
Multiple pins can be selected to perform a single capture or match function, providing an
application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them.
The LPC2141/42/44/46/48 can count external events on one of the capture inputs if the
minimum external pulse is equal or longer than a period of the PCLK. In this configuration,
unused capture lines can be selected as regular timer capture inputs, or used as external
interrupts.
6.15.1 Features
• A 32-bit timer/counter with a programmable 32-bit prescaler.
• External event counter or timer operation.
• Four 32-bit capture channels per timer/counter that can take a snapshot of the timer
value when an input signal transitions. A capture event may also optionally generate
an interrupt.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
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– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Four external outputs per timer/counter corresponding to match registers, with the
following capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
6.16 Watchdog timer
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined
amount of time.
6.16.1 Features
• Internally resets chip if not periodically reloaded.
• Debug mode.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
• Flag to indicate watchdog reset.
• Programmable 32-bit timer with internal pre-scaler.
• Selectable time period from (Tcy(PCLK) 256 4) to (Tcy(PCLK) 232 4) in multiples of
Tcy(PCLK) 4.
6.17 Real-time clock
The RTC is designed to provide a set of counters to measure time when normal or idle
operating mode is selected. The RTC has been designed to use little power, making it
suitable for battery powered systems where the CPU is not running continuously (Idle
mode).
6.17.1 Features
• Measures the passage of time to maintain a calendar and clock.
• Ultra-low power design to support battery powered systems.
• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and
Day of Year.
• Can use either the RTC dedicated 32 kHz oscillator input or clock derived from the
external crystal/oscillator input at XTAL1. Programmable reference clock divider
allows fine adjustment of the RTC.
• Dedicated power supply pin can be connected to a battery or the main 3.3 V.
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6.18 Pulse width modulator
The PWM is based on the standard timer block and inherits all of its features, although
only the PWM function is pinned out on the LPC2141/42/44/46/48. The timer is designed
to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or
perform other actions when specified timer values occur, based on seven match registers.
The PWM function is also based on match register events.
The ability to separately control rising and falling edge locations allows the PWM to be
used for more applications. For instance, multi-phase motor control typically requires
three non-overlapping PWM outputs with individual control of all three pulse widths and
positions.
Two match registers can be used to provide a single edge controlled PWM output. One
match register (MR0) controls the PWM cycle rate, by resetting the count upon match.
The other match register controls the PWM edge position. Additional single edge
controlled PWM outputs require only one match register each, since the repetition rate is
the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a
rising edge at the beginning of each PWM cycle, when an MR0 match occurs.
Three match registers can be used to provide a PWM output with both edges controlled.
Again, the MR0 match register controls the PWM cycle rate. The other match registers
control the two PWM edge positions. Additional double edge controlled PWM outputs
require only two match registers each, since the repetition rate is the same for all PWM
outputs.
With double edge controlled PWM outputs, specific match registers control the rising and
falling edge of the output. This allows both positive going PWM pulses (when the rising
edge occurs prior to the falling edge), and negative going PWM pulses (when the falling
edge occurs prior to the rising edge).
6.18.1 Features
• Seven match registers allow up to six single edge controlled or three double edge
controlled PWM outputs, or a mix of both types.
• The match registers also allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Supports single edge controlled and/or double edge controlled PWM outputs. Single
edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the
output is a constant LOW. Double edge controlled PWM outputs can have either edge
occur at any position within a cycle. This allows for both positive going and negative
going pulses.
• Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will
occur at the same repetition rate.
• Double edge controlled PWM outputs can be programmed to be either positive going
or negative going pulses.
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• Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must ‘release’ new match values before they can become
effective.
• May be used as a standard timer if the PWM mode is not enabled.
• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
6.19 System control
6.19.1 Crystal oscillator
On-chip integrated oscillator operates with external crystal in range of 1 MHz to 25 MHz.
The oscillator output frequency is called fosc and the ARM processor clock frequency is
referred to as CCLK for purposes of rate equations, etc. fosc and CCLK are the same
value unless the PLL is running and connected. Refer to Section 6.19.2 “PLL” for
additional information.
6.19.2 PLL
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled
Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the
multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper
frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so
there is an additional divider in the loop to keep the CCO within its frequency range while
the PLL is providing the desired output frequency. The output divider may be set to divide
by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,
it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and
bypassed following a chip reset and may be enabled by software. The program must
configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a
clock source. The PLL settling time is 100 s.
6.19.3 Reset and wake-up timer
Reset has two sources on the LPC2141/42/44/46/48: the RESET pin and watchdog reset.
The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of
chip reset by any source starts the Wake-up Timer (see Wake-up Timer description
below), causing the internal chip reset to remain asserted until the external reset is
de-asserted, the oscillator is running, a fixed number of clocks have passed, and the
on-chip flash controller has completed its initialization.
When the internal reset is removed, the processor begins executing at address 0, which is
the reset vector. At that point, all of the processor and peripheral registers have been
initialized to predetermined values.
The Wake-up Timer ensures that the oscillator and other analog functions required for
chip operation are fully functional before the processor is allowed to execute instructions.
This is important at power on, all types of reset, and whenever any of the aforementioned
functions are turned off for any reason. Since the oscillator and other functions are turned
off during Power-down mode, any wake-up of the processor from Power-down mode
makes use of the Wake-up Timer.
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The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of VDD ramp (in the case of power on), the type of crystal
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.
6.19.4 Brownout detector
The LPC2141/42/44/46/48 include 2-stage monitoring of the voltage on the VDD pins. If
this voltage falls below 2.9 V, the BOD asserts an interrupt signal to the VIC. This signal
can be enabled for interrupt; if not, software can monitor the signal by reading dedicated
register.
The second stage of low voltage detection asserts reset to inactivate the
LPC2141/42/44/46/48 when the voltage on the VDD pins falls below 2.6 V. This reset
prevents alteration of the flash as operation of the various elements of the chip would
otherwise become unreliable due to low voltage. The BOD circuit maintains this reset
down below 1 V, at which point the POR circuitry maintains the overall reset.
Both the 2.9 V and 2.6 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.9 V detection to reliably interrupt, or a regularly-executed event
loop to sense the condition.
6.19.5 Code security
This feature of the LPC2141/42/44/46/48 allow an application to control whether it can be
debugged or protected from observation.
If after reset on-chip boot loader detects a valid checksum in flash and reads 0x8765 4321
from address 0x1FC in flash, debugging will be disabled and thus the code in flash will be
protected from observation. Once debugging is disabled, it can be enabled only by
performing a full chip erase using the ISP.
6.19.6 External interrupt inputs
The LPC2141/42/44/46/48 include up to nine edge or level sensitive External Interrupt
Inputs as selectable pin functions. When the pins are combined, external events can be
processed as four independent interrupt signals. The External Interrupt Inputs can
optionally be used to wake-up the processor from Power-down mode.
Additionally capture input pins can also be used as external interrupts without the option
to wake the device up from Power-down mode.
6.19.7 Memory mapping control
The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip
flash memory, or to the on-chip static RAM. This allows code running in different memory
spaces to have control of the interrupts.
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Single-chip 16-bit/32-bit microcontrollers
6.19.8 Power control
The LPC2141/42/44/46/48 supports two reduced power modes: Idle mode and
Power-down mode.
In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs.
Peripheral functions continue operation during Idle mode and may generate interrupts to
cause the processor to resume execution. Idle mode eliminates power used by the
processor itself, memory systems and related controllers, and internal buses.
In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Power-down mode and the logic levels of chip output pins remain
static. The Power-down mode can be terminated and normal operation resumed by either
a reset or certain specific interrupts that are able to function without clocks. Since all
dynamic operation of the chip is suspended, Power-down mode reduces chip power
consumption to nearly zero.
Selecting an external 32 kHz clock instead of the PCLK as a clock-source for the on-chip
RTC will enable the microcontroller to have the RTC active during Power-down mode.
Power-down current is increased with RTC active. However, it is significantly lower than in
Idle mode.
A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings during active
and Idle mode.
6.19.9 APB bus
The APB divider determines the relationship between the processor clock (CCLK) and the
clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first
is to provide peripherals with the desired PCLK via APB bus so that they can operate at
the speed chosen for the ARM processor. In order to achieve this, the APB bus may be
slowed down to 12 to 14 of the processor clock rate. Because the APB bus must work
properly at power-up (and its timing cannot be altered if it does not work since the APB
divider control registers reside on the APB bus), the default condition at reset is for the
APB bus to run at 14 of the processor clock rate. The second purpose of the APB divider
is to allow power savings when an application does not require any peripherals to run at
the full processor rate. Because the APB divider is connected to the PLL output, the PLL
remains active (if it was running) during Idle mode.
6.20 Emulation and debugging
The LPC2141/42/44/46/48 support emulation and debugging via a JTAG serial port. A
trace port allows tracing program execution. Debugging and trace functions are
multiplexed only with GPIOs on Port 1. This means that all communication, timer and
interface peripherals residing on Port 0 are available during the development and
debugging phase as they are when the application is run in the embedded system itself.
6.20.1 EmbeddedICE
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of
the target system requires a host computer running the debugger software and an
EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the remote
debug protocol commands to the JTAG data needed to access the ARM core.
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Single-chip 16-bit/32-bit microcontrollers
The ARM core has a Debug Communication Channel (DCC) function built-in. The DCC
allows a program running on the target to communicate with the host debugger or another
separate host without stopping the program flow or even entering the debug state. The
DCC is accessed as a co-processor 14 by the program running on the ARM7TDMI-S
core. The DCC allows the JTAG port to be used for sending and receiving data without
affecting the normal program flow. The DCC data and control registers are mapped in to
addresses in the EmbeddedICE logic.
This clock must be slower than 16 of the CPU clock (CCLK) for the JTAG interface to
operate.
6.20.2 Embedded trace
Since the LPC2141/42/44/46/48 have significant amounts of on-chip memory, it is not
possible to determine how the processor core is operating simply by observing the
external pins. The Embedded Trace Macrocell (ETM) provides real-time trace capability
for deeply embedded processor cores. It outputs information about processor execution to
the trace port.
The ETM is connected directly to the ARM core and not to the main AMBA system bus. It
compresses the trace information and exports it through a narrow trace port. An external
trace port analyzer must capture the trace information under software debugger control.
Instruction trace (or PC trace) shows the flow of execution of the processor and provides a
list of all the instructions that were executed. Instruction trace is significantly compressed
by only broadcasting branch addresses as well as a set of status signals that indicate the
pipeline status on a cycle by cycle basis. Trace information generation can be controlled
by selecting the trigger resource. Trigger resources include address comparators,
counters and sequencers. Since trace information is compressed the software debugger
requires a static image of the code being executed. Self-modifying code can not be traced
because of this restriction.
6.20.3 RealMonitor
RealMonitor is a configurable software module, developed by ARM Inc., which enables
real-time debug. It is a lightweight debug monitor that runs in the background while users
debug their foreground application. It communicates with the host using the DCC, which is
present in the EmbeddedICE logic. The LPC2141/42/44/46/48 contain a specific
configuration of RealMonitor software programmed into the on-chip flash memory.
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Single-chip 16-bit/32-bit microcontrollers
7. Limiting values
[1] The following applies to the Limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
[2] Including voltage on outputs in 3-state mode.
[3] Not to exceed 4.6 V.
[4] The peak current is limited to 25 times the corresponding maximum current.
[5] Dependent on package type.
[6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol Parameter Conditions Min Max Unit
VDD supply voltage (core and external rail) 0.5 +3.6 V
VDDA analog 3.3 V pad supply voltage 0.5 +4.6 V
Vi(VBAT) input voltage on pin VBAT for the RTC 0.5 +4.6 V
Vi(VREF) input voltage on pin VREF 0.5 +4.6 V
VIA analog input voltage on ADC related
pins
0.5 +5.1 V
VI input voltage 5 V tolerant I/O
pins; only valid
when the VDD
supply voltage is
present
[2] 0.5 +6.0 V
other I/O pins [2][3] 0.5 VDD + 0.5 V
IDD supply current per supply pin [4] - 100 mA
ISS ground current per ground pin [4] - 100 mA
Isink sink current for I2C-bus; DC;
T = 85 C
- 20 mA
Tstg storage temperature [5] 65 +150 C
Ptot(pack) total power dissipation (per package) based on package
heat transfer, not
device power
consumption
- 1.5 W
Vesd electrostatic discharge voltage human body model [6]
all pins 4000 +4000 V
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8. Static characteristics
Table 5. Static characteristics
Tamb = 40 C to +85 C for commercial applications, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
VDD supply voltage [2] 3.0 3.3 3.6 V
VDDA analog supply voltage 3.3 V pad 3.0 3.3 3.6 V
Vi(VBAT) input voltage on pin
VBAT
[3] 2.0 3.3 3.6 V
Vi(VREF) input voltage on pin
VREF
2.5 3.3 VDDA V
Standard port pins, RESET, P1.26/RTCK
IIL LOW-level input current VI = 0 V; no pull-up - - 3 A
IIH HIGH-level input current VI = VDD; no pull-down - - 3 A
IOZ OFF-state output
current
VO = 0 V; VO = VDD; no
pull-up/down
--3 A
Ilatch I/O latch-up current (0.5VDD) < VI < (1.5VDD);
Tj
< 125 C
- - 100 mA
VI input voltage pin configured to provide a
digital function
[4][5][6]
[7]
0- 5.5 V
VO output voltage output active 0 - VDD V
VIH HIGH-level input voltage 2.0 - - V
VIL LOW-level input voltage - - 0.8 V
Vhys hysteresis voltage 0.4 - - V
VOH HIGH-level output
voltage
IOH = 4 mA [8] VDD 0.4 - - V
VOL LOW-level output
voltage
IOL = 4 mA [8] --0.4 V
IOH HIGH-level output
current
VOH = VDD 0.4 V [8] 4 - - mA
IOL LOW-level output
current
VOL = 0.4 V [8] 4- - mA
IOHS HIGH-level short-circuit
output current
VOH =0V [9] - - 45 mA
IOLS LOW-level short-circuit
output current
VOL = VDDA [9] --50 mA
Ipd pull-down current VI =5V [10] 10 50 150 A
Ipu pull-up current VI =0V [11] 15 50 85 A
VDD < VI <5V [10] 000 A
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Single-chip 16-bit/32-bit microcontrollers
IDD(act) active mode supply
current
VDD = 3.3 V; Tamb = 25 C;
code
while(1){}
executed from flash, no active
peripherals
CCLK = 10 MHz
- 15 50
mA
CCLK = 60 MHz - 40 70 mA
VDD = 3.3 V; Tamb = 25 C;
code executed from flash; USB
enabled and active; all other
peripherals disabled
CCLK = 12 MHz
- 27 70
mA
CCLK = 60 MHz - 57 90 mA
IDD(pd) Power-down mode
supply current
VDD = 3.3 V; Tamb = 25 C - 40 100 A
VDD = 3.3 V; Tamb = 85 C -250 500 A
IBATpd Power-down mode
battery supply current
RTC clock = 32 kHz
(from RTCXn pins);
Tamb = 25 C
VDD = 3.0 V; Vi(VBAT) = 2.5 V
[12] - 15 30
A
VDD = 3.0 V; Vi(VBAT) = 3.0 V - 20 40 A
IBATact active mode battery
supply current
CCLK = 60 MHz;
PCLK = 15 MHz;
PCLK enabled to RTCK;
RTC clock = 32 kHz
(from RTCXn pins);
Tamb = 25 C
VDD = 3.0 V; Vi(VBAT) = 3.0 V
[12] - 78 -
A
IBATact(opt) optimized active mode
battery supply current
PCLK disabled to RTCK in the
PCONP register;
RTC clock = 32 kHz
(from RTCXn pins);
Tamb = 25 C; Vi(VBAT) = 3.3 V
CCLK = 25 MHz
[12][13] - 23 -
A
CCLK = 60 MHz - 30 - A
I
2C-bus pins
VIH HIGH-level input voltage 0.7VDD --V
VIL LOW-level input voltage - - 0.3VDD V
Vhys hysteresis voltage - 0.05VDD - V
VOL LOW-level output
voltage
IOLS = 3 mA [8] --0.4 V
ILI input leakage current VI = VDD [14] - 24 A
VI = 5 V - 10 22 A
Oscillator pins
Vi(XTAL1) input voltage on pin
XTAL1
0.5 1.8 1.95 V
Table 5. Static characteristics …continued
Tamb = 40 C to +85 C for commercial applications, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
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Single-chip 16-bit/32-bit microcontrollers
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
[2] Core and external rail.
[3] The RTC typically fails when Vi(VBAT) drops below 1.6 V.
[4] Including voltage on outputs in 3-state mode.
[5] VDD supply voltages must be present.
[6] 3-state outputs go into 3-state mode when VDD is grounded.
[7] Please also see the errata note mentioned in errata sheet.
[8] Accounts for 100 mV voltage drop in all supply lines.
[9] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[10] Minimum condition for VI = 4.5 V, maximum condition for VI = 5.5 V.
[11] Applies to P1.16 to P1.31.
[12] On pin VBAT.
[13] Optimized for low battery consumption.
[14] To VSS.
[15] Includes external resistors of 33 ± 1 % on D+ and D.
Vo(XTAL2) output voltage on pin
XTAL2
0.5 1.8 1.95 V
Vi(RTCX1) input voltage on pin
RTCX1
0.5 1.8 1.95 V
Vo(RTCX2) output voltage on pin
RTCX2
0.5 1.8 1.95 V
USB pins
IOZ OFF-state output
current
0V 85 C [12] 15 50 100 A
VDD(3V3) < VI <5V [11] 00 0 A
I
2C-bus pins (P0[27] and P0[28])
VIH HIGH-level input
voltage
0.7VDD(3V3) - -V
VIL LOW-level input voltage - - 0.3VDD(3V3) V
Vhys hysteresis voltage - 0.05VDD(3V3) - V
VOL LOW-level output
voltage
IOLS = 3 mA [9] -- 0.4 V
ILI input leakage current VI = VDD(3V3) [13] -2 4 A
VI = 5 V - 10 22 A
Oscillator pins
Vi(XTAL1) input voltage on pin
XTAL1
0.5 1.8 1.95 V
Vo(XTAL2) output voltage on pin
XTAL2
0.5 1.8 1.95 V
Vi(RTCX1) input voltage on pin
RTCX1
0.5 1.8 1.95 V
Vo(RTCX2) output voltage on pin
RTCX2
0.5 1.8 1.95 V
Table 8. Static characteristics …continued
Tamb = 40 C to +85 C for standard devices, 40 C to +125 C for LPC2364HBD only, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
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Single-chip 16-bit/32-bit microcontrollers
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
[2] The RTC typically fails when Vi(VBAT) drops below 1.6 V.
[3] VDD(DCDC)(3V3) = 3.3 V; VDD(3V3) = 3.3 V; Vi(VBAT) = 3.3 V; Tamb = 25 C.
[4] On pin VBAT.
[5] Including voltage on outputs in 3-state mode.
[6] VDD(3V3) supply voltages must be present.
[7] 3-state outputs go into 3-state mode when VDD(3V3) is grounded.
[8] Please also see the errata note in errata sheet.
[9] Accounts for 100 mV voltage drop in all supply lines.
[10] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[11] Minimum condition for VI = 4.5 V, maximum condition for VI = 5.5 V.
[12] LPC2364HBD only.
[13] To VSS.
[14] Includes external resistors of 33 1 % on D+ and D.
USB pins (LPC2364/66/68 only)
IOZ OFF-state output
current
0V 85 C [3] 1 -60 MHz
IRC; 40 C to +85 C 3.96 4 4.04 MHz
IRC; > 85 C [3] 3.98 4.02 4.06 MHz
External clock
fosc oscillator frequency 1 - 25 MHz
Tcy(clk) clock cycle time 40 - 1000 ns
tCHCX clock HIGH time Tcy(clk) 0.4 - - ns
tCLCX clock LOW time Tcy(clk) 0.4 - - ns
tCLCH clock rise time - - 5 ns
tCHCL clock fall time - - 5 ns
I
2C-bus pins (P0[27] and P0[28])
tf(o) output fall time VIH to VIL 20 + 0.1 Cb
[4] - - ns
SSP interface
tsu(SPI_MISO) SPI_MISO set-up time Tamb = 25 C; measured
in SPI Master mode; see
Figure 15
- 11- ns
Fig 13. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
tCHCL tCLCX
tCHCX
Tcy(clk)
tCLCH
002aaa907
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Single-chip 16-bit/32-bit microcontrollers
11.1 Internal oscillators
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
11.2 I/O pins
[1] Applies to standard I/O pins and RESET pin.
11.3 USB interface
[1] Characterized but not implemented as production test. Guaranteed by design.
Table 10. Dynamic characteristic: internal oscillators
Tamb = 40 C to +85 C; 3.0 V VDD(3V3) 3.6 V.[1]
Symbol Parameter Conditions Min Typ[2] Max Unit
fosc(RC) internal RC oscillator frequency - 3.96 4.02 4.04 MHz
fi(RTC) RTC input frequency - - 32.768 - kHz
Table 11. Dynamic characteristic: I/O pins[1]
Tamb = 40 C to +85 C; VDD(3V3) over specified ranges.
Symbol Parameter Conditions Min Typ Max Unit
tr rise time pin configured as output 3.0 - 5.0 ns
tf fall time pin configured as output 2.5 - 5.0 ns
Table 12. Dynamic characteristics of USB pins (full-speed) (LPC2364/66/68 only)
CL = 50 pF; Rpu = 1.5 k on D+ to VDD(3V3), unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
tr rise time 10 % to 90 % 8.5 - 13.8 ns
tf fall time 10 % to 90 % 7.7 - 13.7 ns
tFRFM differential rise and fall time
matching
tr / tf - -109 %
VCRS output signal crossover voltage 1.3 - 2.0 V
tFEOPT source SE0 interval of EOP see Figure 14 160 - 175 ns
tFDEOP source jitter for differential transition
to SE0 transition
see Figure 14 2 - +5 ns
tJR1 receiver jitter to next transition 18.5 - +18.5 ns
tJR2 receiver jitter for paired transitions 10 % to 90 % 9 - +9 ns
tEOPR1 EOP width at receiver must reject as
EOP; see
Figure 14
[1] 40 - - ns
tEOPR2 EOP width at receiver must accept as
EOP; see
Figure 14
[1] 82 - - ns
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11.4 Flash memory
[1] Number of program/erase cycles.
[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes.
Table 13. Dynamic characteristics of flash
Tamb = 40 C to +85 C for standard devices, 40 C to +125 C for LPC2364HBD only, unless otherwise specified;
VDD(3V3) = 3.0 V to 3.6 V; all voltages are measured with respect to ground.
Symbol Parameter Conditions Min Typ Max Unit
Nendu endurance [1] 10000 100000 - cycles
tret retention time powered; 100 cycles 10 - - years
unpowered; 100 cycles 20 - - years
ter erase time sector or multiple
consecutive sectors
95 100 105 ms
tprog programming time [2] 0.95 1 1.05 ms
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11.5 Timing
Fig 14. Differential data-to-EOP transition skew and EOP width
002aab561
TPERIOD
differential
data lines
crossover point
source EOP width: tFEOPT
receiver EOP width: tEOPR1, tEOPR2
crossover point
extended
differential data to
SE0/EOP skew
n × TPERIOD + tFDEOP
Fig 15. MISO line set-up time in SSP Master mode
tsu(SPI_MISO)
SCK
shifting edges
MOSI
MISO
002aad326
sampling edges
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12. ADC electrical characteristics
[1] Conditions: VSSA = 0 V, VDDA = 3.3 V.
[2] The ADC is monotonic, there are no missing codes.
[3] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 16.
[4] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 16.
[5] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 16.
[6] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 16.
[7] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve. See Figure 16.
[8] See Figure 17.
Table 14. ADC characteristics
VDDA = 2.5 V to 3.6 V; Tamb = 40 C to +85 C, unless otherwise specified; ADC frequency 4.5 MHz.
Symbol Parameter Conditions Min Typ Max Unit
VIA analog input voltage 0 - VDDA V
Cia analog input capacitance - - 1 pF
ED differential linearity error [1][2][3] - - 1 LSB
EL(adj) integral non-linearity [1][4] - - 2 LSB
EO offset error [1][5] - - 3 LSB
EG gain error [1][6] - - 0.5 %
ET absolute error [1][7] - - 4 LSB
Rvsi voltage source interface
resistance
[8] --40 k
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(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 16. ADC characteristics
1023
1022
1021
1020
1019
(2)
(1)
123456 7 1018 1019 1020 1021 1022 1023 1024
7
6
5
4
3
2
1
0
1018
(5)
(4)
(3)
1 LSB
(ideal)
code
out
offset
error
EO
gain
error
EG
offset error
EO
VIA (LSBideal)
002aae604
Vi(VREF) − VSSA
1024
1 LSB =
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Fig 17. Suggested ADC interface - LPC2364/65/66/67/68 AD0[y] pin
LPC23XX
AD0[y]SAMPLE
AD0[y] 20 kΩ
3 pF 5 pF
Rvsi
VSS
VEXT
002aac610
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13. DAC electrical characteristics
14. Application information
14.1 Suggested USB interface solutions (LPC2364/66/68 only)
Table 15. DAC electrical characteristics
VDDA = 3.0 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified
Symbol Parameter Conditions Min Typ Max Unit
ED differential linearity error - 1 - LSB
EL(adj) integral non-linearity - 1.5 - LSB
EO offset error - 0.6 - %
EG gain error - 0.6 - %
CL load capacitance - 200 - pF
RL load resistance 1 - - k
Fig 18. LPC2364/66/68 USB interface on a self-powered device
LPC23XX
USB-B
connector
USB_D+
USB_CONNECT
SoftConnect switch
USB_D−
VBUS
VSS
VDD(3V3)
R1
1.5 kΩ
RS = 33 Ω
002aac578
RS = 33 Ω
USB_UP_LED
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14.2 Crystal oscillator XTAL input and component selection
The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a
clock in slave mode, it is recommended that the input be coupled through a capacitor with
Ci
= 100 pF. To limit the input voltage to the specified range, choose an additional
capacitor to ground Cg which attenuates the input voltage by a factor Ci
/ (Ci
+ Cg). In
slave mode, a minimum of 200 mV (RMS) is needed.
In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF
(Figure 20), with an amplitude between 200 mV (RMS) and 1000 mV (RMS). This
corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V.
The XTAL2 pin in this configuration can be left unconnected.
External components and models used in oscillation mode are shown in Figure 21 and in
Table 16 and Table 17. Since the feedback resistance is integrated on chip, only a crystal
and the capacitances CX1 and CX2 need to be connected externally in case of
fundamental mode oscillation (the fundamental frequency is represented by L, CL and
RS). Capacitance CP in Figure 21 represents the parallel package capacitance and should
not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal
manufacturer.
Fig 19. LPC2364/66/68 USB interface on a bus-powered device
LPC23XX
VDD(3V3)
R1
1.5 kΩ
R2
USB_UP_LED
002aac579
USB-B
connector USB_D+
USB_D−
VBUS
VSS
RS = 33 Ω
RS = 33 Ω
Fig 20. Slave mode operation of the on-chip oscillator
LPC2xxx
XTAL1
Ci
100 pF
Cg
002aae718
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Single-chip 16-bit/32-bit microcontrollers
Fig 21. Oscillator modes and models: oscillation mode of operation and external crystal
model used for CX1/CX2 evaluation
Table 16. Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters): low frequency mode
Fundamental oscillation
frequency FOSC
Crystal load
capacitance CL
Maximum crystal
series resistance RS
External load
capacitors CX1/CX2
1 MHz to 5 MHz 10 pF < 300 18 pF, 18 pF
20 pF < 300 39 pF, 39 pF
30 pF < 300 57 pF, 57 pF
5 MHz to 10 MHz 10 pF < 300 18 pF, 18 pF
20 pF < 200 39 pF, 39 pF
30 pF < 100 57 pF, 57 pF
10 MHz to 15 MHz 10 pF < 160 18 pF, 18 pF
20 pF < 60 39 pF, 39 pF
15 MHz to 20 MHz 10 pF < 80 18 pF, 18 pF
Table 17. Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters): high frequency mode
Fundamental oscillation
frequency FOSC
Crystal load
capacitance CL
Maximum crystal
series resistance RS
External load
capacitors CX1, CX2
15 MHz to 20 MHz 10 pF < 180 18 pF, 18 pF
20 pF < 100 39 pF, 39 pF
20 MHz to 25 MHz 10 pF < 160 18 pF, 18 pF
20 pF < 80 39 pF, 39 pF
002aag469
LPC2xxx
XTAL1 XTAL2
CX1 CX2
XTAL
= CL CP
RS
L
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Single-chip 16-bit/32-bit microcontrollers
14.3 RTC 32 kHz oscillator component selection
The RTC external oscillator circuit is shown in Figure 22. Since the feedback resistance is
integrated on chip, only a crystal, the capacitances CX1 and CX2 need to be connected
externally to the microcontroller.
Table 18 gives the crystal parameters that should be used. CL is the typical load
capacitance of the crystal and is usually specified by the crystal manufacturer. The actual
CL influences oscillation frequency. When using a crystal that is manufactured for a
different load capacitance, the circuit will oscillate at a slightly different frequency
(depending on the quality of the crystal) compared to the specified one. Therefore for an
accurate time reference it is advised to use the load capacitors as specified in Table 18
that belong to a specific CL. The value of external capacitances CX1 and CX2 specified in
this table are calculated from the internal parasitic capacitances and the CL. Parasitics
from PCB and package are not taken into account.
14.4 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines
The crystal should be connected on the PCB as close as possible to the oscillator input
and output pins of the chip. Take care that the load capacitors Cx1, Cx2, and Cx3 in case of
third overtone crystal usage have a common ground plane. The external components
must also be connected to the ground plain. Loops must be made as small as possible in
order to keep the noise coupled in via the PCB as small as possible. Also parasitics
should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller
accordingly to the increase in parasitics of the PCB layout.
Fig 22. RTC oscillator modes and models: oscillation mode of operation and external
crystal model used for CX1/CX2 evaluation
Table 18. Recommended values for the RTC external 32 kHz oscillator CX1/CX2 components
Crystal load capacitance
CL
Maximum crystal series
resistance RS
External load capacitors CX1/CX2
11 pF < 100 k 18 pF, 18 pF
13 pF < 100 k 22 pF, 22 pF
15 pF < 100 k 27 pF, 27 pF
002aaf495
LPC2xxx
RTCX1 RTCX2
CX1 CX2
32 kHz XTAL
= CL CP
RS
L
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Product data sheet Rev. 7.1 — 16 October 2013 59 of 69
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14.5 Standard I/O pin configuration
Figure 23 shows the possible pin modes for standard I/O pins with analog input function:
• Digital output driver
• Digital input: Pull-up enabled/disabled
• Digital input: Pull-down enabled/disabled
• Analog input (for ADC input channels)
The default configuration for standard I/O pins is input with pull-up enabled. The weak
MOS devices provide a drive capability equivalent to pull-up and pull-down resistors.
Fig 23. Standard I/O pin configuration with analog input
PIN
VDD
ESD
VSS
ESD
VDD
weak
pull-up
weak
pull-down
output enable
output
pull-up enable
pull-down enable
data input
analog input
select analog input
002aaf496
pin configured
as digital output
driver
pin configured
as digital input
pin configured
as analog input
LPC2364_65_66_67_68 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7.1 — 16 October 2013 60 of 69
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Single-chip 16-bit/32-bit microcontrollers
14.6 Reset pin configuration
Fig 24. Reset pin configuration
VSS
reset
002aaf274
VDD
VDD
VDD
Rpu ESD
ESD
20 ns RC
GLITCH FILTER PIN
LPC2364_65_66_67_68 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7.1 — 16 October 2013 61 of 69
NXP Semiconductors LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers
15. Package outline
Fig 25. Package outline SOT407-1 (LQFP100)
UNIT
A
max. A1 A2 A3 bp c E(1) e HE L Lp ywv Z θ
OUTLINE REFERENCES
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 1.6 0.15
0.05
1.45
1.35 0.25 0.27
0.17
0.20
0.09
14.1
13.9 0.5 16.25
15.75
1.15
0.85
7
0
o
1 0.2 0.08 0.08 o
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.75
0.45
SOT407-1 136E20 MS-026 00-02-01
03-02-20
D(1) (1)(1)
14.1
13.9
HD
16.25
15.75
Z E
1.15
0.85
D
bp
e
θ
E
A1
A
Lp
detail X
L
(A ) 3
B
25
c
DH
bp
EH A2
v M B
D
ZD
A
ZE
e
v M A
X
1
100
76
75 51
50
26
y
pin 1 index
w M
w M
0 5 10 mm
scale
LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1
LPC2364_65_66_67_68 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7.1 — 16 October 2013 62 of 69
NXP Semiconductors LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers
Fig 26. Package outline SOT926-1 (TFBGA100)
OUTLINE REFERENCES
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT926-1 - - - - - - - - -
SOT926-1
05-12-09
05-12-22
UNIT A
max
mm 1.2 0.4
0.3
0.8
0.65
0.5
0.4
9.1
8.9
9.1
8.9
A1
DIMENSIONS (mm are the original dimensions)
TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm
A2 b D E e2
7.2
e
0.8
e1
7.2
v
0.15
w
0.05
y
0.08
y1
0.1
0 2.5 5 mm
scale
b
e2
e1
e
e
1/2 e
1/2 e
∅ v M AC B
∅ w M C
ball A1
index area
A
B
C
D
E
F
H
K
G
J
13579 2 4 6 8 10
ball A1
index area
B A
E
D
C
y1 C y
X
detail X
A
A1
A2
LPC2364_65_66_67_68 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7.1 — 16 October 2013 63 of 69
NXP Semiconductors LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers
16. Abbreviations
Table 19. Abbreviations
Acronym Description
ADC Analog-to-Digital Converter
AHB Advanced High-performance Bus
AMBA Advanced Microcontroller Bus Architecture
APB Advanced Peripheral Bus
BOD BrownOut Detection
CAN Controller Area Network
DAC Digital-to-Analog Converter
DCC Debug Communication Channel
DMA Direct Memory Access
DSP Digital Signal Processing
EOP End Of Packet
ETM Embedded Trace Macrocell
GPIO General Purpose Input/Output
IrDA Infrared Data Association
JTAG Joint Test Action Group
MII Media Independent Interface
MIIM Media Independent Interface Management
PHY Physical Layer
PLL Phase-Locked Loop
PWM Pulse Width Modulator
RMII Reduced Media Independent Interface
SE0 Single Ended Zero
SPI Serial Peripheral Interface
SSI Serial Synchronous Interface
SSP Synchronous Serial Port
TTL Transistor-Transistor Logic
UART Universal Asynchronous Receiver/Transmitter
USB Universal Serial Bus
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Product data sheet Rev. 7.1 — 16 October 2013 64 of 69
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Single-chip 16-bit/32-bit microcontrollers
17. Revision history
Table 20. Revision history
Document ID Release date Data sheet status Change
notice
Supersedes
LPC2364_65_66_67_68 v.7.1 20131016 Product data sheet - LPC2364_65_66_67_68 v.7
Modifications: • Table 4 “Pin description”, Table note 6: Changed glitch filter spec from 5 ns to 10 ns.
• Table 9 “Dynamic characteristics”: Changed min clock cycle time from 42 to 40.
LPC2364_65_66_67_68 v.7 20111020 Product data sheet - LPC2364_65_66_67_68 v.6
Modifications: • Table 13 “Dynamic characteristics of flash”: Added characteristics for ter and tprog.
• Table 4 “Pin description”: Updated description for USB_UP_LED.
• Table 4 “Pin description”: Added Table note 12 “If the RTC is not used, these pins can
be left floating.” for RTCX1 and RTCX2 pins.
• Table 4 “Pin description”: Added Table note 8 “This pin has a built-in pull-up resistor.”
for DBGEN, TMS, TDI, TRST, and RTCK pins.
• Table 4 “Pin description”: Added Table note 7 “This pin has no built-in pull-up and no
built-in pull-down resistor.” for TCK and TDO pins.
• Table 5 “Limiting values”: Added “non-operating” to conditions column of Tstg.
• Table 5 “Limiting values”: Updated Table note 5 “The maximum non-operating
storage temperature is different than the temperature for required shelf life which
should be determined based on required shelf lifetime. Please refer to the JEDEC
spec (J-STD-033B.1) for further details.”.
• Table 5 “Limiting values”: Updated storage temperature min/max to 65/+150.
• Added Table 7 “Thermal resistance value (C/W): ±15 %”.
• Added Table 10 “Dynamic characteristic: internal oscillators”.
• Added Table 11 “Dynamic characteristic: I/O pins[1]”.
• Table 8 “Static characteristics”: Changed Vhys typ value from 0.5VDD(3V3) to
0.05VDD(3V3).
• Table 13 “Dynamic characteristics of flash”: Updated table.
• Added Section 9 “Thermal characteristics”.
• Added Section 10.3 “Electrical pin characteristics”.
• Added Section 14.2 “Crystal oscillator XTAL input and component selection”.
• Added Section 14.3 “RTC 32 kHz oscillator component selection”.
• Added Section 14.4 “XTAL and RTCX Printed Circuit Board (PCB) layout guidelines”.
• Added Section 14.5 “Standard I/O pin configuration”.
• Added Section 14.6 “Reset pin configuration”.
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Product data sheet Rev. 7.1 — 16 October 2013 65 of 69
NXP Semiconductors LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers
LPC2364_65_66_67_68 v.6 20100201 Product data sheet - LPC2364_65_66_67_68 v.5
Modifications: • Table 5 “Limiting values”: Changed VESD min/max to 2500/+2500.
• Table 6: Updated min, typical and max values for oscillator pins.
• Table 6: Updated conditions and typical values for IDD(DCDC)pd(3V3), IBATact;
IDD(DCDC)dpd(3V3) and IBAT added.
• Table 9 “Dynamic characteristics of flash”: Changed flash endurance spec from
100000 to 10000 minimum cycles.
• Added Table 11 “DAC electrical characteristics”.
• Section 7.2 “On-chip flash programming memory”: Removed text regarding flash
endurance minimum specs.
• Added Section 7.24.4.4 “Deep power-down mode”.
• Section 7.25.2 “Brownout detection”: Changed VDD(3V3) to VDD(DCDC)(3V3).
• Added Section 9.2 “Deep power-down mode”.
• Added Section 13.2 “XTAL1 input”.
• Added Section 13.3 “XTAL and RTC Printed-Circuit Board (PCB) layout guidelines”.
• Added table note for XTAL1 and XTAL2 pins in Table 3.
LPC2364_65_66_67_68 v.5 20090409 Product data sheet - LPC2364_65_66_67_68 v.4
Modifications: • Added part LPC2364HBD100.
• Section 7.2: Added sentence clarifying SRAM speeds for LPC2364HBD.
• Table 5: Updated Vesd min/max.
• Table 6: Updated ZDRV Table note [14].
• Table 6: Vhys, moved 0.4 from typ to min column.
• Table 6: Ipu, added specs for >85 C.
• Table 6: Removed Rpu.
• Table 7: CCLK and IRC, added specs for >85 C.
• Added Table 9.
• Updated Figure 14.
• Updated Figure 11.
LPC2364_65_66_67_68 v.4 20080417 Product data sheet - LPC2364_66_68 v.3
LPC2364_66_68 v.3 20071220 Product data sheet - LPC2364_66_68 v.2
LPC2364_66_68 v.2 20071001 Preliminary data sheet - LPC2364_66_68 v.1
LPC2364_66_68 v.1 20070103 Preliminary data sheet - -
Table 20. Revision history …continued
Document ID Release date Data sheet status Change
notice
Supersedes
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Single-chip 16-bit/32-bit microcontrollers
18. Legal information
18.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
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Single-chip 16-bit/32-bit microcontrollers
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I
2C-bus — logo is a trademark of NXP B.V.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
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Product data sheet Rev. 7.1 — 16 October 2013 68 of 69
continued >>
NXP Semiconductors LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers
20. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3
4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 6
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10
7 Functional description . . . . . . . . . . . . . . . . . . 18
7.1 Architectural overview . . . . . . . . . . . . . . . . . . 18
7.2 On-chip flash programming memory . . . . . . . 19
7.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 19
7.4 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.5 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 20
7.5.1 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 21
7.6 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 21
7.7 General purpose DMA controller . . . . . . . . . . 21
7.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.8 Fast general purpose parallel I/O . . . . . . . . . . 22
7.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.9 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.10 USB interface (LPC2364/66/68 only) . . . . . . . 24
7.10.1 USB device controller . . . . . . . . . . . . . . . . . . . 24
7.10.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.11 CAN controller and acceptance filters
(LPC2364/66/68 only). . . . . . . . . . . . . . . . . . . 25
7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.12 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.13 10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.14 UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.15 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 26
7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.16 SSP serial I/O controller . . . . . . . . . . . . . . . . . 27
7.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.17 SD/MMC card interface (LPC2367/68 only) . . 27
7.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.18 I2C-bus serial I/O controllers. . . . . . . . . . . . . . 27
7.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.19 I2S-bus serial I/O controllers. . . . . . . . . . . . . . 28
7.19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.20 General purpose 32-bit timers/external
event counters . . . . . . . . . . . . . . . . . . . . . . . . 29
7.20.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.21 Pulse width modulator . . . . . . . . . . . . . . . . . . 29
7.21.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.22 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 30
7.22.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.23 RTC and battery RAM . . . . . . . . . . . . . . . . . . 31
7.23.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.24 Clocking and power control . . . . . . . . . . . . . . 31
7.24.1 Crystal oscillators. . . . . . . . . . . . . . . . . . . . . . 31
7.24.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 32
7.24.1.2 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 32
7.24.1.3 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 32
7.24.2 PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.24.3 Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 32
7.24.4 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.24.4.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.24.4.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.24.4.3 Power-down mode . . . . . . . . . . . . . . . . . . . . . 34
7.24.4.4 Deep power-down mode . . . . . . . . . . . . . . . . 34
7.24.4.5 Power domains . . . . . . . . . . . . . . . . . . . . . . . 34
7.25 System control . . . . . . . . . . . . . . . . . . . . . . . . 35
7.25.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.25.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 35
7.25.3 Code security
(Code Read Protection - CRP) . . . . . . . . . . . 36
7.25.4 AHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.25.5 External interrupt inputs . . . . . . . . . . . . . . . . . 36
7.25.6 Memory mapping control . . . . . . . . . . . . . . . . 37
7.26 Emulation and debugging . . . . . . . . . . . . . . . 37
7.26.1 EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 37
7.26.2 Embedded trace. . . . . . . . . . . . . . . . . . . . . . . 37
7.26.3 RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 39
9 Thermal characteristics . . . . . . . . . . . . . . . . . 40
10 Static characteristics . . . . . . . . . . . . . . . . . . . 41
10.1 Power-down mode . . . . . . . . . . . . . . . . . . . . . 44
10.2 Deep power-down mode . . . . . . . . . . . . . . . . 45
10.3 Electrical pin characteristics. . . . . . . . . . . . . . 47
11 Dynamic characteristics. . . . . . . . . . . . . . . . . 48
11.1 Internal oscillators . . . . . . . . . . . . . . . . . . . . . 49
11.2 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
11.3 USB interface. . . . . . . . . . . . . . . . . . . . . . . . . 49
11.4 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 50
11.5 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12 ADC electrical characteristics . . . . . . . . . . . . 52
13 DAC electrical characteristics . . . . . . . . . . . . 55
14 Application information . . . . . . . . . . . . . . . . . 55
NXP Semiconductors LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers
© NXP B.V. 2013. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 16 October 2013
Document identifier: LPC2364_65_66_67_68
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
14.1 Suggested USB interface solutions
(LPC2364/66/68 only). . . . . . . . . . . . . . . . . . . 55
14.2 Crystal oscillator XTAL input and component
selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
14.3 RTC 32 kHz oscillator component selection. . 58
14.4 XTAL and RTCX Printed Circuit Board
(PCB) layout guidelines . . . . . . . . . . . . . . . . . 58
14.5 Standard I/O pin configuration . . . . . . . . . . . . 59
14.6 Reset pin configuration. . . . . . . . . . . . . . . . . . 60
15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 61
16 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 63
17 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 64
18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 66
18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 66
18.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
18.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 67
19 Contact information. . . . . . . . . . . . . . . . . . . . . 67
20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
©2002 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.1
Features
• 5V ±1% Reference
• Oscillator Sync Terminal
• Internal Soft Start
• Deadtime Control
• Under Voltage Lockout
Description
The KA3525A is a monolithic integrated circuit that
includes all of the control circuits necessary for a pulse width
modulating regulator. There are a voltage reference, an error
amplifier, a pulse width modulator, an oscillator, an under
voltage lockout, a soft start circuit, and the output driver in
the chip.
16-DIP
1
Internal Block Diagram
16
15
12
1
2
9
8
10
5
7
3 6 4
14
11
13
U.V.L.O. BAND GAP
REF 5V
LATCH
S R
F/F Q
Q 5K
VC
OUTPUT A
OUTPUT B
OSCILLATOR
DISCHARGE
5K
ERR
AMP
PWM
COMP
_
+
_
+
CT
VREF
VCC
GND
EA(-)
EA(+)
EAOUT
C
(SOFT
START)
SHUT DOWN
SYNC RT OSC
OUTPUT
KA3525A
SMPS Controller
KA3525A
2
Absolute Maximum Ratings
Electrical Characteristics
(VCC = 20V, TA = 0 to +70°C, unless otherwise specified)
Parameter Symbol Value Unit
Supply Voltage VCC 40 V
Collector Supply Voltage VC 40 V
Output Current, Sink or Source IO 500 mA
Reference Output Current IREF 50 mA
Oscillator Charging Current ICHG(OSC) 5 mA
Power Dissipation (TA = 25°C) PD 1000 m/W
Operating Temperature TOPR 0 ~ +70 °C
Storage Temperature TSTG -65 ~ +150 °C
Lead Temperature (Soldering, 10sec) TLEAD +300 °C
Parameter Symbol Conditions Min. Typ. Max. Unit
REFERENCE SECTION
Reference Output Voltage VREF TJ = 25°C 5.0 5.1 5.2 V
Line Regulation ∆VREF VCC = 8 to 35V - 9 20 mV
Load Regulation ∆VREF IREF = 0 to 20mA - 20 50 mV
Short Circuit Output Current ISC VREF = 0, TJ = 25°C - 80 100 mA
Total Output Variation (Note1) ∆VREF Line, Load and Temperature 4.95 - 5.25 V
Temperature Stability (Note1) STT - - 20 50 mV
Long Term Stability (Note1) ST TJ = 125°C ,1KHRS - 20 50 mV
OSCILLATOR SECTION
Initial Accuracy (Note1, 2) ACCUR TJ = 25°C - ±3 ±6 %
Frequency Change With Voltage ∆f/∆VCC VCC = 8 to 35V (Note1, 2) - ±0.8 ±2 %
Maximum Frequency f(MAX) RT = 2kΩ, CT = 470pF 400 430 - kHz
Minimum Frequency f(MIN) RT = 200kΩ, CT = 0.1uF - 60 120 Hz
Clock Amplitude (Note1, 2) V(CLK) - 34- V
Clock Width (Note1, 2) tW(CLK) TJ = 25°C 0.3 0.6 1 µs
Sync Threshold VTH(SYNC) - 1.2 2 2.8 V
Sync Input Current II(SYNC) Sync = 3.5V - 1.3 2.5 mA
KA3525A
3
Electrical Characteristics (Continued)
(VCC = 20V, TA = 0 to +70°C, unless otherwise specified)
Note :
1. These parameters. although guaranteed over the recommended operating conditions, are not 100% tested in production
2. Tested at fOSC=40kHz (RT =3.6K, CT =0.01uF, RI = 0Ω)
Parameter Symbol Conditions Min. Typ. Max. Unit
ERROR AMPLIFIER SECTION (VCM = 5.1V)
Input Offset Voltage VIO - - 1.5 10 mV
Input Bias Current IBIAS - - 1 10 µA
Input Offset Current IIO - - 0.1 1 µA
Open Loop Voltage Gain GVO RL ≥ 10MΩ 60 80 - dB
Common Mode Rejection Ratio CMRR VCM = 1.5 to 5.2V 60 90 - dB
Power Supply Rejection Ratio PSRR VCC = 8 to 3.5V 50 60 - dB
PWM COMPARATOR SECTION
Minimum Duty Cycle D(MIN) - - - 0%
Maximum Duty Cycle D(MAX) - 45 49 - %
Input Threshold Voltage (Note2) VTH1 Zero Duty Cycle 0.7 0.9 - V
Input Threshold Voltage (Note2) VTH2 Max Duty Cycle - 3.2 3.6 V
SOFT-START SECTION
Soft Start Current ISOFT VSD = 0V, VSS = 0V 25 51 80 µA
Soft Start Low Level Voltage VSL VSD = 25V - 0.3 0.7 V
Shutdown Threshold Voltage VTH(SD) - 0.9 1.3 1.7 V
Shutdown Input Current IN(SD) VSD = 2.5V - 0.3 1 mA
OUTPUT SECTION
Low Output Voltage I VOL I ISINK = 20mA - 0.1 0.4 V
Low Output Voltage II VOL II ISINK = 100mA - 0.05 2 V
High Output Voltage I VCH I ISOURCE = 20mA 18 19 - V
High Output Voltage II VCH II ISOURCE = 100mA 17 18 - V
Under Voltage Lockout VUV V8 and V9 = High 6 7 8 V
Collector Leakage Current ILKG VCC = 35V - 80 200 µA
Rise Time (Note1) tR CL = 1uF, TJ = 25°C - 80 600 ns
Fall Time (Note1) tF CL = 1uF, TJ = 25°C - 70 300 ns
STANDBY CURRENT
Supply Current ICC VCC = 35V - 12 20 mA
KA3525A
4
Test Circuit
16
15
12
1
2
9
8
10
5 7
13
11
14
3 6
BAND GAP
REF 5V U.V.L.O.
A
B
0.1
Vcc
0.1
3k
RWM
ADJ
10k
1.5K
10K
0.01
5.0uF
5.0k
5.0k
5.0k
100
F/F
ERR
AMP ERR
AMP
OSCILLATOR
LATCH
S
S R
SOFT START +
SHUTDOWN
VREF
CT
RAMP
0.009 0.1
+
3.6k
0.001
DEAD
TIME
OUT B
10k
10k
OUT A
VC
CLOCK
_
+
+
_
RT
KA3525A
5
Mechanical Dimensions
Package
#1
#8 #9
#16
6.40 ±0.20
7.62
0.300
2.54
0.100
0.252 ±0.008
0~15° 0.25 +0.10
–0.05
0.010 +0.004
–0.002
3.30 ±0.30
0.130 ±0.012
3.25 ±0.20
0.128 ±0.008 19.40 ±0.20 0.764 ±0.008
19.80
0.780 MAX
5.08
0.200
0.38
0.014
MAX
MIN
0.81
0.032 ( ) 0.46 ±0.10
0.018 ±0.004
0.059 ±0.004
1.50 ±0.10
16-DIP
KA3525A
10/2/02 0.0m 001
Stock#DSxxxxxxxx
2002 Fairchild Semiconductor Corporation
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
Ordering Information
Product Number Package Operating Temperature
KA3525A 16-DIP 0 ~ +70°C
©2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FPS Rev.1.0.6 TM is a trademark of Fairchild Semiconductor Corporation.
Features
• Internal Avalanche Rugged Sense FET
• Advanced Burst-Mode operation consumes under 1 W at
240VAC & 0.5W load
• Precision Fixed Operating Frequency (66kHz)
• Internal Start-up Circuit
• Improved Pulse by Pulse Current Limiting
• Over Voltage Protection (OVP)
• Over Load Protection (OLP)
• Internal Thermal Shutdown Function (TSD)
• Auto-Restart Mode
• Under Voltage Lock Out (UVLO) with hysteresis
• Low Operating Current (2.5mA)
• Built-in Soft Start
Application
• SMPS for LCD monitor and STB
• Adaptor
Description
The FSDM0565RB is an integrated Pulse Width Modulator
(PWM) and Sense FET specifically designed for high
performance offline Switch Mode Power Supplies (SMPS)
with minimal external components. This device is an
integrated high voltage power switching regulator which
combine an avalanche rugged Sense FET with a current mode
PWM control block. The PWM controller includes integrated
fixed frequency oscillator, under voltage lockout, leading edge
blanking (LEB), optimized gate driver, internal soft start,
temperature compensated precise current sources for a loop
compensation and self protection circuitry. Compared with
discrete MOSFET and PWM controller solution, it can reduce
total cost, component count, size and weight simultaneously
increasing efficiency, productivity, and system reliability. This
device is a basic platform well suited for cost effective
designs of flyback converters.
Table 1. Maximum Output Power
Notes:
1. Typical continuous power in a non-ventilated enclosed
adapter measured at 50°C ambient.
2. Maximum practical continuous power in an open frame
design at 50°C ambient.
3. 230 VAC or 100/115 VAC with doubler.
Typical Circuit
Figure 1. Typical Flyback Application
OUTPUT POWER TABLE
PRODUCT
230VAC ±15%(3) 85-265VAC
Adapter(1)
Open
Frame(2)
Adapter(1)
Open
Frame(2)
FSDM0565RB 60W 70W 50W 60W
FSDM0565RBI 60W 70W 50W 60W
FSDM07652RB 70W 80W 60W 70W
Drain
Source
Vstr
Vfb Vcc
PWM
AC
IN DC
OUT
FSDM0565RB
Green Mode Fairchild Power Switch (FPSTM)
FSDM0565RB
2
Internal Block Diagram
Figure 2. Functional Block Diagram of FSDM0565RB
8V/12V
3 1
2
4
5
Vref Internal
Bias
S
Q
Q
R
OSC
Vcc Vref
Idelay IFB
VSD
TSD
Vovp
Vcc
VCL
S
Q
Q
R
R
2.5R
Vcc good
Vcc Drain
N.C
FB
GND
Gate
driver
6
Vstr
Istart
Vcc good
0.5/0.7V
LEB
PWM
Soft start
+
-
FSDM0565RB
3
Pin Definitions
Pin Configuration
Figure 3. Pin Configuration (Top View)
Pin Number Pin Name Pin Function Description
1 Drain This pin is the high voltage power Sense FET drain. It is designed to drive the
transformer directly.
2 GND This pin is the control ground and the Sense FET source.
3 Vcc
This pin is the positive supply voltage input. During start up, the power is supplied
by an internal high voltage current source that is connected to the Vstr pin.
When Vcc reaches 12V, the internal high voltage current source is disabled and
the power is supplied from the auxiliary transformer winding.
4 Vfb
This pin is internally connected to the inverting input of the PWM comparator.
The collector of an opto-coupler is typically tied to this pin. For stable operation,
a capacitor should be placed between this pin and GND. If the voltage of this pin
reaches 6.0V, the over load protection is activated resulting in shutdown of the
FPSTM.
5 N.C -
6 Vstr
This pin is connected directly to the high voltage DC link. At startup, the internal
high voltage current source supplies internal bias and charges the external capacitor
that is connected to the Vcc pin. Once Vcc reaches 12V, the internal current
source is disabled.
6.Vstr
5.N.C.
4.Vfb
3.Vcc
2.GND
1.Drain
TO-220F-6L
6.Vstr
5.N.C.
4.Vfb
3.Vcc
2.GND
1.Drain
I2-PAK-6L
FSDM0565RB
4
Absolute Maximum Ratings
(Ta=25°C, unless otherwise specified)
Notes:
1. Repetitive rating: Pulse width limited by maximum junction temperature
2. L=14mH, starting Tj=25°C
3. L=13uH, starting Tj=25°C
Thermal Impedance
Notes:
1. Free standing with no heat-sink under natural convection.
2. Infinite cooling condition - Refer to the SEMI G30-88.
Parameter Symbol Value Unit
Drain-source voltage VDSS 650 V
Vstr Max Voltage VSTR 650 V
Pulsed Drain current (Tc=25°C)(1) IDM 11 ADC
Continuous Drain Current(Tc=25°C) ID
2.8 A
Continuous Drain Current(Tc=100°C) 1.7 A
Single pulsed avalanche energy (2) EAS 190 mJ
Single pulsed avalanche current (3) IAS - A
Supply voltage VCC 20 V
Input voltage range VFB -0.3 to VCC V
Total power dissipation(Tc=25°C) PD(Watt H/S)
45
(TO-220-6L) W
75
(I2-PAK-6L)
Operating junction temperature Tj Internally limited °C
Operating ambient temperature TA -25 to +85 °C
Storage temperature range TSTG -55 to +150 °C
ESD Capability, HBM Model (All pins
excepts for Vstr and Vfb)
- 2.0
(GND-Vstr/Vfb=1.5kV)
kV
ESD Capability, Machine Model (All pins
excepts for Vstr and Vfb)
- 300
(GND-Vstr/Vfb=225V)
V
Parameter Symbol Package Value Unit
Junction-to-Ambient Thermal θJA(1) TO-220F-6L 49.90 °C/W
I2-PAK-6L 30
Junction-to-Case Thermal θJC(2) TO-220F-6L 2.78 °C/W
I2-PAK-6L 1.67
FSDM0565RB
5
Electrical Characteristics
(Ta = 25°C unless otherwise specified)
Parameter Symbol Condition Min. Typ. Max. Unit
Sense FET SECTION
Drain source breakdown voltage BVDSS VGS = 0V, ID = 250μA 650 - - V
Zero gate voltage drain current IDSS
VDS = 650V, VGS = 0V - - 500 μA
VDS= 520V
VGS = 0V, TC = 125°C - - 500 μA
Static drain source on resistance (1) RDS(ON) VGS = 10V, ID = 2.5A - 1.76 2.2 Ω
Output capacitance COSS
VGS = 0V, VDS = 25V,
f = 1MHz - 78 - pF
Turn on delay time TD(ON) VDD= 325V, ID= 5A
(MOSFET switching
time is essentially
independent of
operating temperature)
- 22 -
ns
Rise time TR - 52 -
Turn off delay time TD(OFF) - 95 -
Fall time TF - 50 -
CONTROL SECTION
Initial frequency FOSC VFB = 3V 60 66 72 kHz
Voltage stability FSTABLE 13V ≤ Vcc ≤ 18V 0 1 3 %
Temperature stability (2) ΔFOSC -25°C ≤ Ta ≤ 85°C 0 ±5 ±10 %
Maximum duty cycle DMAX - 77 82 87 %
Minimum duty cycle DMIN - - - 0%
Start threshold voltage VSTART VFB=GND 11 12 13 V
Stop threshold voltage VSTOP VFB=GND 7 8 9 V
Feedback source current IFB VFB=GND 0.7 0.9 1.1 mA
Soft-start time TS Vfb=3 - 10 15 ms
Leading Edge Blanking time TLEB - - 250 - ns
BURST MODE SECTION
Burst Mode Voltages (2)
VBURH Vcc=14V - 0.7 - V
VBURL Vcc=14V - 0.5 - V
PROTECTION SECTION
Peak current limit (4) IOVER VFB=5V, VCC=14V 2.0 2.25 2.5 A
Over voltage protection VOVP - 18 19 20 V
Thermal shutdown temperature (2) TSD 130 145 160 °C
Shutdown feedback voltage VSD VFB ≥ 5.5V 5.5 6.0 6.5 V
Shutdown delay current IDELAY VFB=5V 2.8 3.5 4.2 μA
FSDM0565RB
6
Notes:
1. Pulse test : Pulse width ≤ 300μS, duty ≤ 2%
2. These parameters, although guaranteed at the design, are not tested in mass production.
3. These parameters, although guaranteed, are tested in EDS(wafer test) process.
4. These parameters indicate the inductor current.
5. This parameter is the current flowing into the control IC.
TOTAL DEVICE SECTION
Operating supply current (5)
IOP VFB=GND, VCC=14V
IOP(MIN) VFB=GND, VCC=10V - 2.5 5 mA
IOP(MAX) VFB=GND, VCC=18V
FSDM0565RB
7
Comparison Between FS6M07652RTC and FSDM0565RB
Function FS6M07652RTC FSDM0565RB FSDM0565RB Advantages
Soft-Start Adjustable soft-start
time using an
external capacitor
Internal soft-start with
typically 10ms (fixed)
• Gradually increasing current limit
during soft-start further reduces peak
current and voltage component
stresses
• Eliminates external components used
for soft-start in most applications
• Reduces or eliminates output
overshoot
Burst Mode Operation • Built into controller
• Output voltage
drops to around
half
• Built into controller
• Output voltage fixed
• Improve light load efficiency
• Reduces no-load consumption
FSDM0565RB
8
Typical Performance Characteristics
(These Characteristic Graphs are Normalized at Ta= 25°C)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-25 0 25 50 75 100 125 150
Junction Temperature(℃)
Operating Frequency
(Fosc)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-25 0 25 50 75 100 125 150
Junction Temperature(℃)
Start Thershold Voltage
(Vstart)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-25 0 25 50 75 100 125 150
Junction Temperature(℃)
Stop Threshold Voltage
(Vstop)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-25 0 25 50 75 100 125 150
Junction Temperature(℃)
Maximum Duty Cycle
(Dmax)
Operating Current vs. Temp Start Threshold Voltage vs. Temp
Stop Threshold Voltage vs. Temp Operating Freqency vs. Temp
Maximum Duty vs. Temp Feedback Source Current vs. Temp
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-25 0 25 50 75 100 125 150
Junction Temperature(℃)
Operating Current
(Iop)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-25 0 25 50 75 100 125 150
Junction Temperature(℃)
FB Source Current
(Ifb)
FSDM0565RB
9
Typical Performance Characteristics (Continued)
(These Characteristic Graphs are Normalized at Ta= 25°C)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-25 0 25 50 75 100 125 150
Junction Temperature(℃)
Shutdown Delay Current
(Idelay)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-25 0 25 50 75 100 125 150
Junction Temperature(℃)
Over Voltage Protection
(Vovp)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-50 -25 0 25 50 75 100 125
Junction Temperature(℃)
Peak Current Limit(Self protection)
(Iover)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-25 0 25 50 75 100 125 150
Junction Temperature(℃)
FB Burst Mode Enable Voltage
(Vfbe)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-25 0 25 50 75 100 125 150
Junction Temperature(℃)
FB Burst Mode Disable Voltage
(Vfbd)
ShutDown Feedback Voltage vs. Temp ShutDown Delay Current vs. Temp
Over Voltage Protection vs. Temp Burst Mode Enable Voltage vs. Temp
Burst Mode Disable Voltage vs. Temp Current Limit vs. Temp
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-25 0 25 50 75 100 125 150
Junction Temperature(℃)
Shutdown FB Voltage
(Vsd)
FSDM0565RB
10
Typical Performance Characteristics (Continued)
(These Characteristic Graphs are Normalized at Ta= 25°C)
Soft Start Time vs. Temp
0.0
0.2
0.4
0.6
0.8
1.0
1.2
-50 -25 0 25 50 75 100 125
Junction Temperature(℃)
Soft Start Time
(Normalized to 25℃)
FSDM0565RB
11
Functional Description
1. Startup : In previous generations of Fairchild Power
Switches (FPSTM) the Vcc pin had an external start-up
resistor to the DC input voltage line. In this generation the
startup resistor is replaced by an internal high voltage current
source. At startup, an internal high voltage current source
supplies the internal bias and charges the external capacitor
(Cvcc) that is connected to the Vcc pin as illustrated in
Figure 4. When Vcc reaches 12V, the FSDM0565RB begins
switching and the internal high voltage current source is
disabled. Then, the FSDM0565RB continues its normal
switching operation and the power is supplied from the
auxiliary transformer winding unless Vcc goes below the
stop voltage of 8V.
Figure 4. Internal startup circuit
2. Feedback Control : FSDM0565RB employs current
mode control, as shown in Figure 5. An opto-coupler (such
as the H11A817A) and shunt regulator (such as the KA431)
are typically used to implement the feedback network.
Comparing the feedback voltage with the voltage across the
Rsense resistor plus an offset voltage makes it possible to
control the switching duty cycle. When the reference pin
voltage of the KA431 exceeds the internal reference voltage
of 2.5V, the H11A817A LED current increases, thus pulling
down the feedback voltage and reducing the duty cycle. This
event typically happens when the input voltage is increased
or the output load is decreased.
2.1 Pulse-by-pulse current limit: Because current mode
control is employed, the peak current through the Sense FET
is limited by the inverting input of PWM comparator (Vfb*)
as shown in Figure 5. Assuming that the 0.9mA current
source flows only through the internal resistor (2.5R +R= 2.8
kΩ), the cathode voltage of diode D2 is about 2.5V. Since D1
is blocked when the feedback voltage (Vfb) exceeds 2.5V,
the maximum voltage of the cathode of D2 is clamped at this
voltage, thus clamping Vfb*. Therefore, the peak value of
the current through the Sense FET is limited.
2.2 Leading edge blanking (LEB) : At the instant the
internal Sense FET is turned on, there usually exists a high
current spike through the Sense FET, caused by primary-side
capacitance and secondary-side rectifier reverse recovery.
Excessive voltage across the Rsense resistor would lead to
incorrect feedback operation in the current mode PWM
control. To counter this effect, the FSDM0565RB employs a
leading edge blanking (LEB) circuit. This circuit inhibits the
PWM comparator for a short time (TLEB) after the Sense
FET is turned on.
Figure 5. Pulse width modulation (PWM) circuit
3. Protection Circuit : The FSDM0565RB has several self
protective functions such as over load protection (OLP), over
voltage protection (OVP) and thermal shutdown (TSD).
Because these protection circuits are fully integrated into the
IC without external components, the reliability can be
improved without increasing cost. Once the fault condition
occurs, switching is terminated and the Sense FET remains
off. This causes Vcc to fall. When Vcc reaches the UVLO
stop voltage, 8V, the protection is reset and the internal high
voltage current source charges the Vcc capacitor via the Vstr
pin. When Vcc reaches the UVLO start voltage,12V, the
FSDM0565RB resumes its normal operation. In this manner,
the auto-restart can alternately enable and disable the
switching of the power Sense FET until the fault condition is
eliminated (see Figure 6).
8V/12V
3
Vref
Internal
Bias
Vcc
6 Vstr
Istart
Vcc good
VDC
CVcc
4 OSC
Vcc Vref
Idelay IFB
VSD
R
2.5R
Gate
driver
OLP
D1 D2
+
Vfb*
-
Vfb
KA431
CB
Vo
H11A817A
Rsense
SenseFET
FSDM0565RB
12
Figure 6. Auto restart operation
3.1 Over Load Protection (OLP) : Overload is defined as
the load current exceeding a pre-set level due to an
unexpected event. In this situation, the protection circuit
should be activated in order to protect the SMPS. However,
even when the SMPS is in the normal operation, the over
load protection circuit can be activated during the load
transition. In order to avoid this undesired operation, the over
load protection circuit is designed to be activated after a
specified time to determine whether it is a transient situation
or an overload situation. Because of the pulse-by-pulse
current limit capability, the maximum peak current through
the Sense FET is limited, and therefore the maximum input
power is restricted with a given input voltage. If the output
consumes beyond this maximum power, the output voltage
(Vo) decreases below the set voltage. This reduces the
current through the opto-coupler LED, which also reduces
the opto-coupler transistor current, thus increasing the
feedback voltage (Vfb). If Vfb exceeds 2.5V, D1 is blocked
and the 3.5uA current source starts to charge CB slowly up to
Vcc. In this condition, Vfb continues increasing until it
reaches 6V, when the switching operation is terminated as
shown in Figure 7. The delay time for shutdown is the time
required to charge CB from 2.5V to 6.0V with 3.5uA. In
general, a 10 ~ 50 ms delay time is typical for most
applications.
Figure 7. Over load protection
3.2 Over voltage Protection (OVP) : If the secondary side
feedback circuit were to malfunction or a solder defect
caused an open in the feedback path, the current through the
opto-coupler transistor becomes almost zero. Then, Vfb
climbs up in a similar manner to the over load situation,
forcing the preset maximum current to be supplied to the
SMPS until the over load protection is activated. Because
more energy than required is provided to the output, the
output voltage may exceed the rated voltage before the over
load protection is activated, resulting in the breakdown of the
devices in the secondary side. In order to prevent this
situation, an over voltage protection (OVP) circuit is
employed. In general, Vcc is proportional to the output
voltage and the FSDM0565RB uses Vcc instead of directly
monitoring the output voltage. If VCC exceeds 19V, an OVP
circuit is activated resulting in the termination of the
switching operation. In order to avoid undesired activation of
OVP during normal operation, Vcc should be designed to be
below 19V.
3.3 Thermal Shutdown (TSD) : The Sense FET and the
control IC are built in one package. This makes it easy for
the control IC to detect the heat generation from the Sense
FET. When the temperature exceeds approximately 150°C,
the thermal shutdown is activated.
4. Soft Start : The FSDM0565RB has an internal soft start
circuit that increases PWM comparator inverting input
voltage together with the Sense FET current slowly after it
starts up. The typical soft start time is 10msec, The pulse
width to the power switching device is progressively
increased to establish the correct working conditions for
transformers, inductors, and capacitors. The voltage on the
output capacitors is progressively increased with the
intention of smoothly establishing the required output
voltage. It also helps to prevent transformer saturation and
reduce the stress on the secondary diode during startup.
Fault
situation
8V
12V
Vcc
Vds
t
Fault
occurs Fault
removed
Normal
operation
Normal
operation
Power
on
VFB
t
2.5V
6.0V
Over load protection
T12= Cfb*(6.0-2.5)/I delay
T1 T2
FSDM0565RB
13
5. Burst operation : In order to minimize power dissipation
in standby mode, the FSDM0565RB enters burst mode
operation. As the load decreases, the feedback voltage
decreases. As shown in Figure 8, the device automatically
enters burst mode when the feedback voltage drops below
VBURL(500mV). At this point switching stops and the
output voltages start to drop at a rate dependent on standby
current load. This causes the feedback voltage to rise. Once
it passes VBURH(700mV) switching resumes. The feedback
voltage then falls and the process repeats. Burst mode
operation alternately enables and disables switching of the
power Sense FET thereby reducing switching loss in
Standby mode.
Figure 8. Waveforms of burst operation
VFB
Vds
0.5V
0.7V
Ids
Vo
Voset
time
Switching
disabled
T1 T2 T3
Switching
disabled T4
FSDM0565RB
14
Typical application circuit
Features
• High efficiency (>81% at 85Vac input)
• Low zero load power consumption (<300mW at 240Vac input)
• Low standby mode power consumption (<800mW at 240Vac input and 0.3W load)
• Low component count
• Enhanced system reliability through various protection functions
• Internal soft-start (10ms)
Key Design Notes
• Resistors R102 and R105 are employed to prevent start-up at low input voltage. After startup, there is no power loss in these
resistors since the startup pin is internally disconnected after startup.
• The delay time for over load protection is designed to be about 50ms with C106 of 47nF. If a faster triggering of OLP is
required, C106 can be reduced to 10nF.
• Zener diode ZD102 is used for a safety test such as UL. When the drain pin and feedback pin are shorted, the zener diode
fails and remains short, which causes the fuse (F1) blown and prevents explosion of the opto-coupler (IC301). This zener
diode also increases the immunity against line surge.
1. Schematic
Application Output power Input voltage Output voltage (Max current)
LCD Monitor 40W Universal input
(85-265Vac)
5V (2.0A)
12V (2.5A)
3
4
C102
220nF
275VAC
LF101
23mH
C101
220nF
275VAC
RT1
5D-9
F1
FUSE
250V
2A
C103
100uF
400V
R102
30kΩ
R105
40kΩ
R103
56kΩ
2W
C104
2.2nF
1kV D101
UF 4007
C106
47nF
50V
C105
22uF
50V
D102
TVR10G
R104
5Ω
1
2
3
4
5
T1
EER3016
BD101
2KBP06M3N257
1
2
R101
560kΩ
1W
IC1
FSDM0565RB
Vstr
NC
Vfb
Vcc
Drain
GND
1
2
3 4
5
6
ZD101
22V
8
10
D202
MBRF10100
C201
1000uF
25V
C202
1000uF
25V
L201
12V, 2.5A
6
7
D201
MBRF1045
C203
1000uF
10V
C204
1000uF
10V
L202
5V, 2A
R201
1kΩ
R202
1.2kΩ
R204
5.6kΩ
R203
12kΩ C205
47nF
R205
5.6kΩ
C301
4.7nF
IC301
H11A817A IC201
KA431
ZD102
10V
FSDM0565RB
15
2. Transformer Schematic Diagram
3.Winding Specification
4.Electrical Characteristics
5. Core & Bobbin
Core : EER 3016
Bobbin : EER3016
Ae(mm2) : 96
No Pin (s→f) Wire Turns Winding Method
Na 4 → 5 0.2φ × 1 8 Center Winding
Insulation: Polyester Tape t = 0.050mm, 2Layers
Np/2 2 → 1 0.4φ × 1 18 Solenoid Winding
Insulation: Polyester Tape t = 0.050mm, 2Layers
N12V 10 → 8 0.3φ × 3 7 Center Winding
Insulation: Polyester Tape t = 0.050mm, 2Layers
N5V 7 → 6 0.3φ × 3 3 Center Winding
Insulation: Polyester Tape t = 0.050mm, 2Layers
Np/2 3 → 2 0.4φ × 1 18 Solenoid Winding
Outer Insulation: Polyester Tape t = 0.050mm, 2Layers
Pin Specification Remarks
Inductance 1 - 3 520uH ± 10% 100kHz, 1V
Leakage Inductance 1 - 3 10uH Max 2nd all short
EER3016
Np
/2 N12V
Na
1
2
3
4
5 6
7
8
9
10
Np
/2
N5V
FSDM0565RB
16
6.Demo Circuit Part List
Part Value Note Part Value Note
Fuse C301 4.7nF Polyester Film Cap.
F101 2A/250V
NTC Inductor
RT101 5D-9 L201 5uH Wire 1.2mm
Resistor L202 5uH Wire 1.2mm
R101 560K 1W
R102 30K 1/4W
R103 56K 2W
R104 5 1/4W Diode
R105 40K 1/4W D101 UF4007
R201 1K 1/4W D102 TVR10G
R202 1.2K 1/4W D201 MBRF1045
R203 12K 1/4W D202 MBRF10100
R204 5.6K 1/4W ZD101 Zener Diode 22V
R205 5.6K 1/4W ZD102 Zener Diode 10V
Bridge Diode
BD101 2KBP06M 3N257 Bridge Diode
Capacitor
C101 220nF/275VAC Box Capacitor Line Filter
C102 220nF/275VAC Box Capacitor LF101 23mH Wire 0.4mm
C103 100uF/400V Electrolytic Capacitor IC
C104 2.2nF/1kV Ceramic Capacitor IC101 FSDM0565RB FPSTM(5A,650V)
C105 22uF/50V Electrolytic Capacitor IC201 KA431(TL431) Voltage reference
C106 47nF/50V Ceramic Capacitor IC301 H11A817A Opto-coupler
C201 1000uF/25V Electrolytic Capacitor
C202 1000uF/25V Electrolytic Capacitor
C203 1000uF/10V Electrolytic Capacitor
C204 1000uF/10V Electrolytic Capacitor
C205 47nF/50V Ceramic Capacitor
FSDM0565RB
17
7. Layout
Figure 9. Layout Considerations for FSDM0565RB
Figure 10. Layout Considerations for FSDM0565RB
FSDM0565RB
18
Package Dimensions
TO-220F-6L(Forming)
FSDM0565RB
19
Package Dimensions (Continued)
I2-PAK-6L(Forming)
FSDM0565RB
1/9/06 0.0m 001
© 2006 Fairchild Semiconductor Corporation
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
Ordering Information
WDTU : Forming Type
Product Number Package Marking Code BVdss Rds(on)Max.
FSDM0565RBWDTU TO-220F-6L(Forming) DM0565R 650V 2.2 Ω
FSDM0565RBIWDTU I2-PAK-6L (Forming) DM0565R 650V 2.2 Ω
Data Sheet: JN5148-001
IEEE802.15.4 Wireless Microcontroller
© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 1
Overview Features: Transceiver
• 2.4GHz IEEE802.15.4 compliant
• Time of Flight ranging engine
• 128-bit AES security processor
• MAC accelerator with packet
formatting, CRCs, address check,
auto-acks, timers
• 500 & 667kbps data rate modes
• Integrated sleep oscillator for low
power
• On chip power regulation for 2.0V
to 3.6V battery operation
• Deep sleep current 100nA
• Sleep current with active sleep
timer 1.25µA
• <$0.50 external component cost
• Rx current 17.5mA
• Tx current 15.0mA
• Receiver sensitivity -95dBm
• Transmit power 2.5dBm
Features: Microcontroller
• Low power 32-bit RISC CPU, 4 to
32MHz clock speed
• Variable instruction width for high
coding efficiency
• Multi-stage instruction pipeline
• 128kB ROM and 128kB RAM for
bootloaded program code & data
• JTAG debug interface
• 4-input 12-bit ADC, 2 12-bit
DACs, 2 comparators
• 3 application timer/counters,
• 2 UARTs
• SPI port with 5 selects
• 2-wire serial interface
• 4-wire digital audio interface
• Watchdog timer
• Low power pulse counters
• Up to 21 DIO
Industrial temp (-40°C to +85°C)
8x8mm 56-lead Punched QFN
Lead-free and RoHS compliant
The JN5148-001 is an ultra low power, high performance wireless
microcontroller targeted at JenNet and ZigBee PRO networking
applications. The device features an enhanced 32-bit RISC processor
offering high coding efficiency through variable width instructions, a multistage
instruction pipeline and low power operation with programmable clock
speeds. It also includes a 2.4GHz IEEE802.15.4 compliant transceiver,
128kB of ROM, 128kB of RAM, and a rich mix of analogue and digital
peripherals. The large memory footprint allows the device to run both a
network stack (e.g. ZigBee PRO) and an embedded application or in a coprocessor
mode. The operating current is below 18mA, allowing operation
direct from a coin cell.
Enhanced peripherals include low power pulse counters running in sleep
mode designed for pulse counting in AMR applications and a unique Time
of Flight ranging engine, allowing accurate location services to be
implemented on wireless sensor networks. It also includes a 4-wire I2
S
audio interface, to interface directly to mainstream audio CODECs, as well
as conventional MCU peripherals.
Block Diagram
32-bit
RISC CPU Timers
UAR Ts
12-bit ADC,
Comparators
12-bit DACs,
Temp Sensor
2-Wire Serial
RAM SPI 128kB
128-bit AES
Encryption
Accelerator
2.4GHz
Radio
ROM
128kB
Power
Management
XTAL
O-QPSK
Modem
IEEE802.15.4
MAC
Accelerator
32-byte
OTP eFuse
4-Wire Audio
Sleep Counters
Time of Flight
Engine
Watchdog
Timer
Benefits
• Single chip integrates
transceiver and
microcontroller for wireless
sensor networks
• Large memory footprint to
run ZigBee PRO or JenNet
together with an application
• Very low current solution for
long battery life
• Highly featured 32-bit RISC
CPU for high performance
and low power
• System BOM is low in
component count and cost
• Extensive user peripherals
Applications
• Robust and secure low power
wireless applications
• ZigBee PRO and JenNet
networks
• Smart metering
(e.g. AMR)
• Home and commercial building
automation
• Location Aware services – e.g.
Asset Tracking
• Industrial systems
• Telemetry
• Remote Control
• Toys and gaming peripherals2 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
Contents
1 Introduction 6
1.1 Wireless Transceiver 6
1.2 RISC CPU and Memory 6
1.3 Peripherals 7
1.4 Block Diagram 8
2 Pin Configurations 9
2.1 Pin Assignment 10
2.2 Pin Descriptions 12
2.2.1 Power Supplies 12
2.2.2 Reset 12
2.2.3 32MHz Oscillator 12
2.2.4 Radio 12
2.2.5 Analogue Peripherals 13
2.2.6 Digital Input/Output 13
3 CPU 15
4 Memory Organisation 16
4.1 ROM 16
4.2 RAM 17
4.3 OTP eFuse Memory 17
4.4 External Memory 17
4.4.1 External Memory Encryption 18
4.5 Peripherals 18
4.6 Unused Memory Addresses 18
5 System Clocks 19
5.1 16MHz System Clock 19
5.1.1 32MHz Oscillator 19
5.1.2 24MHz RC Oscillator 19
5.2 32kHz System Clock 20
5.2.1 32kHz RC Oscillator 20
5.2.2 32kHz Crystal Oscillator 20
5.2.3 32kHz External Clock 20
6 Reset 21
6.1 Internal Power-on Reset 21
6.2 External Reset 22
6.3 Software Reset 22
6.4 Brown-out Detect 23
6.5 Watchdog Timer 23
7 Interrupt System 24
7.1 System Calls 24
7.2 Processor Exceptions 24
7.2.1 Bus Error 24
7.2.2 Alignment 24
7.2.3 Illegal Instruction 24
7.2.4 Stack Overflow 24
7.3 Hardware Interrupts 25© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 3
8 Wireless Transceiver 26
8.1 Radio 26
8.1.1 Radio External Components 27
8.1.2 Antenna Diversity 27
8.2 Modem 29
8.3 Baseband Processor 30
8.3.1 Transmit 30
8.3.2 Reception 30
8.3.3 Auto Acknowledge 31
8.3.4 Beacon Generation 31
8.3.5 Security 31
8.4 Security Coprocessor 31
8.5 Location Awareness 31
8.6 Higher Data Rates 32
9 Digital Input/Output 33
10 Serial Peripheral Interface 35
11 Timers 38
11.1 Peripheral Timer/Counters 38
11.1.1 Pulse Width Modulation Mode 39
11.1.2 Capture Mode 39
11.1.3 Counter/Timer Mode 40
11.1.4 Delta-Sigma Mode 40
11.1.5 Example Timer / Counter Application 41
11.2 Tick Timer 41
11.3 Wakeup Timers 42
11.3.1 RC Oscillator Calibration 43
12 Pulse Counters 44
13 Serial Communications 45
13.1 Interrupts 46
13.2 UART Application 46
14 JTAG Debug Interface 47
15 Two-Wire Serial Interface 48
15.1 Connecting Devices 48
15.2 Clock Stretching 49
15.3 Master Two-wire Serial Interface 49
15.4 Slave Two-wire Serial Interface 50
16 Four-Wire Digital Audio Interface 51
17 Random Number Generator 53
18 Sample FIFO 54
19 Intelligent Peripheral Interface 55
19.1 Data Transfer Format 55
19.2 JN5148 (Slave) Initiated Data Transfer 56
19.3 Remote (Master) Processor Initiated Data Transfer 564 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
20 Analogue Peripherals 58
20.1 Analogue to Digital Converter 59
20.1.1 Operation 59
20.1.2 Supply Monitor 60
20.1.3 Temperature Sensor 60
20.2 Digital to Analogue Converter 60
20.2.1 Operation 60
20.3 Comparators 61
21 Power Management and Sleep Modes 62
21.1 Operating Modes 62
21.1.1 Power Domains 62
21.2 Active Processing Mode 62
21.2.1 CPU Doze 62
21.3 Sleep Mode 62
21.3.1 Wakeup Timer Event 63
21.3.2 DIO Event 63
21.3.3 Comparator Event 63
21.3.4 Pulse Counter 63
21.4 Deep Sleep Mode 63
22 Electrical Characteristics 64
22.1 Maximum Ratings 64
22.2 DC Electrical Characteristics 64
22.2.1 Operating Conditions 64
22.2.2 DC Current Consumption 65
22.2.3 I/O Characteristics 66
22.3 AC Characteristics 66
22.3.1 Reset and Voltage Brown-Out 66
22.3.2 SPI MasterTiming 68
22.3.3 Intelligent Peripheral (SPI Slave) Timing 68
22.3.4 Two-wire Serial Interface 69
22.3.5 Four-Wire Digital Audio Interface 70
22.3.6 Wakeup and Boot Load Timings 70
22.3.7 Bandgap Reference 71
22.3.8 Analogue to Digital Converters 71
22.3.9 Digital to Analogue Converters 72
22.3.10 Comparators 73
22.3.11 32kHz RC Oscillator 73
22.3.12 32kHz Crystal Oscillator 74
22.3.13 32MHz Crystal Oscillator 74
22.3.14 24MHz RC Oscillator 75
22.3.15 Temperature Sensor 75
22.3.16 Radio Transceiver 76© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 5
Appendix A Mechanical and Ordering Information 81
A.1 56-pin QFN Package Drawing 81
A.2 PCB Decal 82
A.3 Ordering Information 83
A.4 Device Package Marking 84
A.5 Tape and Reel Information 85
A.5.1 Tape Orientation and Dimensions 85
A.5.2 Reel Information: 180mm Reel 86
A.5.3 Reel Information: 330mm Reel 87
A.5.4 Dry Pack Requirement for Moisture Sensitive Material 87
Appendix B Development Support 88
B.1 Crystal Oscillators 88
B.1.1 Crystal Equivalent Circuit 88
B.1.2 Crystal Load Capacitance 88
B.1.3 Crystal ESR and Required Transconductance 89
B.2 32MHz Oscillator 90
B.3 32kHz Oscillator 92
B.4 JN5148 Module Reference Designs 94
B.4.1 Schematic Diagram 94
B.4.2 PCB Design and Reflow Profile 96
Related Documents 97
RoHS Compliance 97
Status Information 97
Disclaimers 98
Trademarks 98
Version Control 99
Contact Details 1006 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
1 Introduction
The JN5148-001 is an IEEE802.15.4 wireless microcontroller that provides a fully integrated solution for applications
using the IEEE802.15.4 standard in the 2.4 - 2.5GHz ISM frequency band [1], including JenNet and ZigBee PRO. It
includes all of the functionality required to meet the IEEE802.15.4, JenNet and ZigBee PRO specifications and has
additional processor capability to run a wide range of applications including, but not limited to Smart Energy,
Automatic Meter Reading, Remote Control, Home and Building Automation, Toys and Gaming.
Applications that transfer data wirelessly tend to be more complex than wired ones. Wireless protocols make
stringent demands on frequencies, data formats, timing of data transfers, security and other issues. Application
development must consider the requirements of the wireless network in addition to the product functionality and user
interfaces. To minimise this complexity, NXP provides a series of software libraries and interfaces that control the
transceiver and peripherals of the JN5148. These libraries and interfaces remove the need for the developer to
understand wireless protocols and greatly simplifies the programming complexities of power modes, interrupts and
hardware functionality.
In view of the above, the register details of the JN5148 are not provided in the datasheet.
The device includes a Wireless Transceiver, RISC CPU, on chip memory and an extensive range of peripherals.
Hereafter, the JN5148-001 will be referred to as JN5148.
1.1 Wireless Transceiver
The Wireless Transceiver comprises a 2.45GHz radio, a modem, a baseband controller and a security coprocessor.
In addition, the radio also provides an output to control transmit-receive switching of external devices such as power
amplifiers allowing applications that require increased transmit power to be realised very easily. Appendix B.4,
describes a complete reference design including Printed Circuit Board (PCB) design and Bill Of Materials (BOM).
The security coprocessor provides hardware-based 128-bit AES-CCM* modes as specified by the IEEE802.15.4
2006 standard. Specifically this includes encryption and authentication covered by the MIC –32/ -64/ -128, ENC and
ENC-MIC –32/ -64/ -128 modes of operation.
The transceiver elements (radio, modem and baseband) work together to provide IEEE802.15.4 Medium Access
Control (MAC) under the control of a protocol stack. Applications incorporating IEEE802.15.4 functionality can be
rapidly developed by combining user-developed application software with a protocol stack library.
1.2 RISC CPU and Memory
A 32-bit RISC CPU allows software to be run on chip, its processing power being shared between the IEEE802.15.4
MAC protocol, other higher layer protocols and the user application. The JN5148 has a unified memory architecture,
code memory, data memory, peripheral devices and I/O ports are organised within the same linear address space.
The device contains 128kbytes of ROM, 128kbytes of RAM and a 32-byte One Time Programmable (OTP) eFuse
memory. © NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 7
1.3 Peripherals
The following peripherals are available on chip:
• Master SPI port with five select outputs
• Two UARTs with support for hardware or software flow control
• Three programmable Timer/Counters – all three support Pulse Width Modulation (PWM) capability, two have
capture/compare facility
• Two programmable Sleep Timers and a Tick Timer
• Two-wire serial interface (compatible with SMbus and I2
C) supporting master and slave operation
• Four-wire digital audio interface (compatible with I²S)
• Slave SPI port for Intelligent peripheral mode (shared with digital I/O)
• Twenty-one digital I/O lines (multiplexed with peripherals such as timers and UARTs)
• Four channel, 12-bit, Analogue to Digital converter
• Two 12-bit Digital to Analogue converters
• Two programmable analogue comparators
• Internal temperature sensor and battery monitor
• Time Of Flight ranging engine
• Two low power pulse counters
• Random number generator
• Watchdog Timer and Voltage Brown-out
• Sample FIFO for digital audio interface or ADC/DAC
• JTAG hardware debug port
User applications access the peripherals using the Integrated Peripherals API. This allows applications to use a
tested and easily understood view of the peripherals allowing rapid system development. 8 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
1.4 Block Diagram
32-bit RISC CPU
Reset
SPI
Master
MUX
UART0
UART1
Wakeup
Timer1
Wakeup
Timer0
Security
Coprocessor
DIO6/TXD0/JTAG_TDO
DIO7/RXD0/JTAG_TDI
DIO4/CTS0/JTAG_TCK
DIO5/RTS0/JTAG_TMS
DIO19/TXD1/JTAG_TDO
DIO17/CTS1/IP_SEL/DAI_SCK/
JTAG_TCK
DIO18/RTS1/IP_INT/DAI_SDOUT/
JTAG_TMS
Digital
Baseband
Radio
Programmable
Interrupt
Controller
Timer0
2-wire
Interf ace
Timer1
SPICLK
DIO10/TIM0OUT/32KXTALOUT
SPIMOSI
SPIMISO
SPISEL0
DIO0/SPISEL1
DIO3/SPISEL4/RFTX
DIO2/SPISEL3/RFRX
DIO1/SPISEL2/PC0
DIO9/TIM0CAP/32KXTALIN/32KIN
DIO8/TIM0CK_GT/PC1
DIO13/TIM1OUT/ADE/DAI_SDIN
DIO11/TIM1CK_GT/TIM2OUT
DIO12/TIM1CAP/ADO/DAI_WS
DIO14/SIF_CLK/IP_CLK
DIO15/SIF_D/IP_DO
DIO16/RXD1/IP_DI/JTAG_TDI
From Peripherals
RESETN
Wireless
Transceiv er
32MHz Clock
Generator
XTAL_IN
XTAL_OUT
RF_IN
VCOTUNE
Tick Timer
Voltage
Regulators 1.8V VDD1
VDD2
Intelligent
Peripheral
IBAIS
VB_XX
Clock Divider
Multiplier
Timer2
SPISEL1
SPISEL2
SPISEL3
SPISEL4
TXD0
RXD0
RTS0
CTS0
TXD1
RXD1
RTS1
CTS1
TIM0CK_GT
TIM0CAP
TIM0OUT
TIM1CK_GT
TIM1CAP
TIM1OUT
TIM2OUT
SIF_D
SIF_CLK
IP_DO
IP_DI
IP_INT
IP_CLK
IP_SEL
4-wire
Digital
Audio
Interf ace
I2S_OUT
I2S_DIN
I2S_CLK
I2S_SYNC
Pulse
Counters
PC0
PC1
JTAG
Debug
JTAG_TDI
JTAG_TMS
JTAG_TCK
JTAG_TDO
RAM
128kB
ROM
128kB
OTP
eFuse
32kHz
RC
Osc
32kHz Clock
Select 32KIN
32kHz
Clock
Gen
32KXTALIN
32KXTALOUT
Antenna
Div ersity
ADO
ADE
Time
Of
Flight
Sample
FIFO
DIO20/RXD1/JTAG_TDI
24MHz
RC Osc
Comparator2 COMP2P
COMP2M
COMP1P/ Comparator1
EXT_PA_C
COMP1M/
EXT_PA_B
DAC1
DAC2
DAC1
DAC2
ADC
M
U ADC4 X
ADC1
ADC2
ADC3
Temperature
Sensor
Supply Monitor
CPU and 16MHz
System Clock
Watchdog
Timer
Brown-out
Detect
Figure 1: JN5148 Block Diagram
DIO 16/IP_DI© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 9
2 Pin Configurations
DIO16/RXD 1/IP_DI/JTAG_TDI
DIO17/CTS1/IP_SEL/DAI_SC K/JTAG_TCK
VSS3
DIO18/RTS1/IP_INT/DAI_SDOUT/JTAG_TMS
DIO19/TXD1/JTAG_TDO
VSS2
VSSS
XTAL_OUT
XTAL_IN
VB_SYNTH
VCOTUNE
VB_VCO
VDD1
IBIAS
VREF
VB_RF2
RF_IN
VB_RF
COMP1M
COMP1P
ADC1
ADC2
ADC3
ADC4
COMP2M
COMP2P
VB_A
NC
DAC1
DAC2
DIO20/RXD 1/JTAG_TDI
VSS1
SPICLK
SPIMISO
VB_RAM
SPIMOSI
SPISEL0
DIO0/SPISEL1
RESETN
VB_DIG
DIO1/SPISEL2/PC0
DIO2/SPISEL3/RFRX
DIO15/SIF_D/IP_DO
DIO14/SIF_C LK/IP_CLK
DIO13/T IM1OUT/ADE/DAI_SDIN
DIO12/T IM1CAP/ADO/DAI_WS
DIO11/T IM1CK_GT /TIM2OUT
DIO10/T IM0OUT/32KXT ALOUT
DIO9/TIM0CAP/32KXT ALIN/32KIN
VDD2
DIO8/TIM0CK_GT/PC 1
DIO7/RXD0/JT AG_TDI
DIO6/TXD0/JTAG_TDO
DIO5/RTS0/JTAG_TMS
DIO4/CTS0/JTAG_TCK
DIO3/SPISEL4/RFTX
VSSA
(Paddl e)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28 29
30
31
32
33
34
35
36
37
38
39
40
41
42
56
55
54
53
52
51
50
49
48
47
46
45
44
43
Figure 2: 56-pin QFN Configuration (top view)
Note: Please refer to Appendix B.4 JN5148 Module Reference
Design for important applications information regarding the
connection of the PADDLE to the PCB.
DIO 16/IP_DI10 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
2.1 Pin Assignment
Pin No Power supplies Signal
Type
Description
10, 12, 16, 18, 27,
35, 40
VB_SYNTH, VB_VCO, VB_RF2, VB_RF, VB_A, VB_RAM,
VB_DIG
1.8V Regulated supply voltage
13, 49 VDD1, VDD2 3.3V Supplies: VDD1 for analogue,
VDD2 for digital
32, 6, 3, 7, Paddle VSS1, VSS2, VSS3, VSSS, VSSA 0V Grounds (see appendix A.2 for
paddle details)
28 NC No connect
General
39 RESETN CMOS Reset input
8, 9 XTAL_OUT, XTAL_IN 1.8V System crystal oscillator
Radio
11 VCOTUNE 1.8V VCO tuning RC network
14 IBIAS 1.8V Bias current control
17 RF_IN 1.8V RF antenna
Analogue Peripheral I/O
21, 22, 23, 24 ADC1, ADC2, ADC3, ADC4 3.3V ADC inputs
15 VREF 1.8V Analogue peripheral reference
voltage
29, 30 DAC1, DAC2 3.3V DAC outputs
19, 20 COMP1M/EXT_PA_B, COMP1P/EXT_PA_C 3.3V Comparator 1 inputs and
external PA control
25, 26 COMP2M, COMP2P 3.3V Comparator 2 inputs
Digital Peripheral I/O
Primary Alternate Functions
33 SPICLK CMOS SPI Clock Output
36 SPIMOSI CMOS SPI Master Out Slave In Output
34 SPIMISO CMOS SPI Master In Slave Out Input
37 SPISEL0 CMOS SPI Slave Select Output 0
38 DIO0 SPISEL1 CMOS DIO0 or SPI Slave Select Output
1
41 DIO1 SPISEL2 PC0 CMOS DIO1, SPI Slave Select Output 2
or Pulse Counter0 Input
42 DIO2 SPISEL3 RFRX CMOS DIO2, SPI Slave Select Output 3
or Radio Receive Control Output
43 DIO3 SPISEL4 RFTX CMOS DIO3, SPI Slave Select Output 4
or Radio Transmit Control Output
44 DIO4 CTS0 JTAG_TCK CMOS DIO4, UART 0 Clear To Send
Input or JTAG CLK
45 DIO5 RTS0 JTAG_TMS CMOS DIO5, UART 0 Request To Send
Output or JTAG Mode Select
46 DIO6 TXD0 JTAG_TDO CMOS DIO6, UART 0 Transmit Data
Output or JTAG Data Output
47 DIO7 RXD0 JTAG_TDI CMOS DIO7, UART 0 Receive Data
Input or JTAG Data Input
48 DIO8 TIM0CK_GT PC1 CMOS DIO8, Timer0 Clock/Gate Input
or Pulse Counter1 Input
50 DIO9 TIM0CAP 32KXTALIN 32KIN CMOS DIO9, Timer0 Capture Input, 32K
External Crystal Input or 32K
Clock Input© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 11
Pin
No
Digital Peripheral I/O Signal
Type
Description
Primary Alternate Functions
51 DIO10 TIM0OUT 32KXTALOUT CMOS DIO10, Timer0 PWM Output or
32K External Crystal Output
52 DIO11 TIM1CK_GT TIM2OUT CMOS DIO11, Timer1 Clock/Gate
Input or Timer2 PWM Output
53 DIO12 TIM1CAP ADO DAI_WS CMOS DIO12, Timer1 Capture Input,
Antenna Diversity or Digital
Audio Word Select
54 DIO13 TIM1OUT ADE DAI_SDIN CMOS DIO13, Timer1 PWM Output,
Antenna Diversity or Digital
Audio Data Input
55 DIO14 SIF_CLK IP_CLK CMOS DIO14, Serial Interface Clock
or Intelligent Peripheral Clock
Input
56 DIO15 SIF_D IP_DO CMOS DIO15, Serial Interface Data or
Intelligent Peripheral Data Out
1 DIO16 IP_DI CMOS DIO16 or Intelligent Peripheral
Data In
2 DIO17 CTS1 IP_SEL DAI_SCK JTAG_TCK CMOS DIO17, UART 1 Clear To Send
Input, Intelligent Peripheral
Device Select Input or Digital
Audio Clock or JTAG CLK
4 DIO18 RTS1 IP_INT DAI_SDOUT JTAG_TMS CMOS DIO18, UART 1 Request To
Send Output, Intelligent
Peripheral Interrupt Output or
Digital Audio Data Output or
JTAG Mode Select
5 DIO19 TXD1 JTAG_TDO CMOS DIO19 or UART 1 Transmit
Data Output or JTAG Data Out
31 DIO 20 RXD1 JTAG_TDI CMOS DIO 20, UART 1 Receive Data
Input or JTAG data In
The PCB schematic and layout rules detailed in Appendix B.4
must be followed. Failure to do so will likely result in the
JN5148 failing to meet the performance specification detailed
herein and worst case may result in device not functioning in
the end application.12 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
2.2 Pin Descriptions
2.2.1 Power Supplies
The device is powered from the VDD1 and VDD2 pins, each being decoupled with a 100nF ceramic capacitor. VDD1
is the power supply to the analogue circuitry; it should be decoupled to ground. VDD2 is the power supply for the
digital circuitry; and should also be decoupled to ground. A 10uF tantalum capacitor is required. Decoupling pins for
the internal 1.8V regulators are provided which require a 100nF capacitor located as close to the device as practical.
VB_RF, VB_A and VB_SYNTH should be decoupled with an additional 47pF capacitor, while VB_RAM and VB_DIG
require only 100nF. VB_RF and VB_RF2 should be connected together as close to the device as practical, and only
require one 100nF capacitor and one 47pF capacitor. The pin VB_VCO requires a 10nF capacitor in parallel with a
47pF capacitor. Refer to B.4.1 for schematic diagram.
VSSA, VSSS, VSS1, VSS2, VSS3 are the ground pins.
Users are strongly discouraged from connecting their own circuits to the 1.8v regulated supply pins, as the regulators
have been optimised to supply only enough current for the internal circuits.
2.2.2 Reset
RESETN is a bi-directional active low reset pin that is connected to a 40kΩ internal pull-up resistor. It may be pulled
low by an external circuit, or can be driven low by the JN5148 if an internal reset is generated. Typically, it will be
used to provide a system reset signal. Refer to section 6.2, External Reset, for more details.
2.2.3 32MHz Oscillator
A crystal is connected between XTALIN and XTALOUT to form the reference oscillator, which drives the system
clock. A capacitor to analogue ground is required on each of these pins. Refer to section 5.1 16MHz System Clock
for more details. The 32MHz reference frequency is divided down to 16MHz and this is used as the system clock
throughout the device.
2.2.4 Radio
The radio is a single ended design, requiring a capacitor and just two inductors to match to 50Ω microstrip line to the
RF_IN pin.
An external resistor (43kΩ) is required between IBIAS and analogue ground to set various bias currents and
references within the radio.© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 13
2.2.5 Analogue Peripherals
Several of the analogue peripherals require a reference voltage to use as part of their operations. They can use
either an internal reference voltage or an external reference connected to VREF. This voltage is referenced to
analogue ground and the performance of the analogue peripherals is dependant on the quality of this reference.
There are four ADC inputs, two pairs of comparator inputs and two DAC outputs. The analogue I/O pins on the
JN5148 can have signals applied up to 0.3v higher than VDD1. A schematic view of the analogue I/O cell is shown in
Figure 3: Analogue I/O Cell
In reset and deep sleep, the analogue peripherals are all off and the DAC outputs are in a high impedance state.
In sleep, the ADC and DACs are off, with the DAC outputs in high impedance state. The comparators may optionally
be used as a wakeup source.
Unused ADC and comparator inputs should be left unconnected.
VDD1
Analogue
I/O Pin
VSSA
Analogue
Peripheral
Figure 3: Analogue I/O Cell
2.2.6 Digital Input/Output
Digital I/O pins on the JN5148 can have signals applied up to 2V higher than VDD2 (with the exception of pins DIO9
and DIO10 that are 3V tolerant) and are therefore TTL-compatible with VDD2 > 3V. For other DC properties of these
pins see section 22.2.3 I/O Characteristics.
When used in their primary function all Digital Input/Output pins are bi-directional and are connected to weak internal
pull up resistors (40kΩ nominal) that can be disabled. When used in their secondary function (selected when the
appropriate peripheral block is enabled through software library calls) then their direction is fixed by the function. The
pull up resistor is enabled or disabled independently of the function and direction; the default state from reset is
enabled.
A schematic view of the digital I/O cell is in Figure 4: DIO Pin Equivalent Schematic.14 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
I
O
IE
VDD2
VSS
Pu
RPU
RPROT
OE
DIO[x] Pin
Figure 4: DIO Pin Equivalent Schematic
In reset, the digital peripherals are all off and the DIO pins are set as high-impedance inputs. During sleep and deep
sleep, the DIO pins retain both their input/output state and output level that was set as sleep commences. If the DIO
pins were enabled as inputs and the interrupts were enabled then these pins may be used to wake up the JN5148
from sleep.© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 15
3 CPU
The CPU of the JN5148 is a 32-bit load and store RISC processor. It has been architected for three key
requirements:
• Low power consumption for battery powered applications
• High performance to implement a wireless protocol at the same time as complex applications
• Efficient coding of high-level languages such as C provided with the NXP Software Developer’s Kit
It features a linear 32-bit logical address space with unified memory architecture, accessing both code and data in the
same address space. Registers for peripheral units, such as the timers, UARTs and the baseband processor are
also mapped into this space.
The CPU has access to a block of 15 32-bit General-Purpose (GP) registers together with a small number of special
purpose registers which are used to store processor state and control interrupt handling. The contents of any GP
register can be loaded from or stored to memory, while arithmetic and logical operations, shift and rotate operations,
and signed and unsigned comparisons can be performed either between two registers and stored in a third, or
between registers and a constant carried in the instruction. Operations between general or special-purpose registers
execute in one cycle while those that access memory require a further cycle to allow the memory to respond.
The instruction set manipulates 8, 16 and 32-bit data; this means that programs can use objects of these sizes very
efficiently. Manipulation of 32-bit quantities is particularly useful for protocols and high-end applications allowing
algorithms to be implemented in fewer instructions than on smaller word-size processors, and to execute in fewer
clock cycles. In addition, the CPU supports hardware Multiply that can be used to efficiently implement algorithms
needed by Digital Signal Processing applications.
The instruction set is designed for the efficient implementation of high-level languages such as C. Access to fields in
complex data structures is very efficient due to the provision of several addressing modes, together with the ability to
be able to use any of the GP registers to contain the address of objects. Subroutine parameter passing is also made
more efficient by using GP registers rather than pushing objects onto the stack. The recommended programming
method for the JN5148 is by using C, which is supported by a software developer kit comprising a C compiler, linker
and debugger.
The CPU architecture also contains features that make the processor suitable for embedded, real-time applications.
In some applications, it may be necessary to use a real-time operating system to allow multiple tasks to run on the
processor. To provide protection for device-wide resources being altered by one task and affecting another, the
processor can run in either supervisor or user mode, the former allowing access to all processor registers, while the
latter only allows the GP registers to be manipulated. Supervisor mode is entered on reset or interrupt; tasks starting
up would normally run in user mode in a RTOS environment.
Embedded applications require efficient handling of external hardware events. When using JenOS, prioritised
interrupts are supported, with 15 priority levels, and can be configured as required by the application.
To improve power consumption a number of power-saving modes are implemented in the JN5148, described more
fully in section 21 - Power Management and Sleep Modes. One of these modes is the CPU doze mode; under
software control, the processor can be shut down and on an interrupt it will wake up to service the request.
Additionally, it is possible under software control, to set the speed of the CPU to 4, 8, 16 or 32MHz. This feature can
be used to trade-off processing power against current consumption.16 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
4 Memory Organisation
This section describes the different memories found within the JN5148. The device contains ROM, RAM, OTP eFuse
memory, the wireless transceiver and peripherals all within the same linear address space.
0x00000000
0x00020000
RAM
(128kB)
0xF0000000
0xFFFFFFFF
Unpopulated
ROM
(128kB)
0xF0020000
RAM Echo
0x04000000
Peripherals
0x02000000
Figure 5: JN5148 Memory Map
4.1 ROM
The ROM is 128k bytes in size, and can be accessed by the processor in a single CPU clock cycle. The ROM
contents include bootloader to allow external Flash memory contents to be bootloaded into RAM at runtime, a default
interrupt vector table, an interrupt manager, IEEE802.15.4 MAC and APIs for interfacing on-chip peripherals. The
operation of the boot loader is described in detail in Application Note [7]. The interrupt manager routes interrupt calls
to the application’s soft interrupt vector table contained within RAM. Section 7 contains further information regarding
the handling of interrupts. ROM contents are shown in Figure 6.
Interrupt Vectors
Interrupt Manager
Boot Loader
IEEE802.15.4
Stack
0x00000000
0x00020000
APIs
Spare
Figure 6: Typical ROM contents© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 17
4.2 RAM
The JN5148 contains 128kBytes of high speed RAM. It can be used for both code and data storage and is accessed
by the CPU in a single clock cycle. At reset, a boot loader controls the loading of segments of code and data from an
external memory connected to the SPI port, into RAM. Software can control the power supply to the RAM allowing
the contents to be maintained during a sleep period when other parts of the device are un-powered. Typical RAM
contents are shown in Figure 7.
MAC Data
Interrupt Vector Table
Application
CPU Stack
(Grows Down)
0x04000000
0x04020000
MAC Address
Figure 7: Typical RAM Contents
4.3 OTP eFuse Memory
The JN5148 contains a total of 32bytes of eFuse memory; this is a One Time Programmable (OTP) memory that can
be used to support on chip 64-bit MAC ID and a 128-bit AES security key. A limited number of bits are available for
customer use for storage of configuration information; configuration of these is made through use of software APIs.
For further information on how to program and use the eFuse memory, please contact technical support via the online
tech-support system.
Alternatively, NXP can provide an eFuse programming service for customers that wish to use the eFuse but do not
wish to undertake this for themselves. For further details of this service, please contact your local NXP sales office.
4.4 External Memory
An external memory with an SPI interface may be used to provide storage for program code and data for the device
when external power is removed. The memory is connected to the SPI interface using select line SPISEL0; this
select line is dedicated to the external memory interface and is not available for use with other external devices. See
Figure 8 for connection details.
JN5148 Serial
Memory
SPISEL0
SPIMISO
SPIMOSI
SPICLK
SS
SDO
SDI
CLK
Figure 8: Connecting External Serial Memory18 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
At reset, the contents of this memory are copied into RAM by the software boot loader. The Flash memory devices
that are supported as standard through the JN5148 bootloader are given in Table 1. NXP recommends that where
possible one of these devices should be selected.
Manufacturer Device Number
SST (Silicon Storage Technology) 25VF010A (1Mbit device)
Numonyx M25P10-A (1Mbit device),
M25P40 (4Mbit device)
Table 1: Supported Flash Memories
Applications wishing to use an alternate Flash memory device should refer to application note [2] JN-AN-1038
Programming Flash devices not supported by the JN51xx ROM-based bootloader. This application note provides
guidance on developing an interface to an alternate device.
4.4.1 External Memory Encryption
The contents of the external serial memory may be encrypted. The AES security processor combined with a user
programmable 128-bit encryption key is used to encrypt the contents of the external memory. The encryption key is
stored in eFuse.
When bootloading program code from external serial memory, the JN5148 automatically accesses the encryption key
to execute the decryption process. User program code does not need to handle any of the decryption process; it is
transparent.
With encryption enabled, the time taken to boot code from external flash is increased.
4.5 Peripherals
All peripherals have their registers mapped into the memory space. Access to these registers requires 3 clock
cycles. Applications have access to the peripherals through the software libraries that present a high-level view of
the peripheral’s functions through a series of dedicated software routines. These routines provide both a tested
method for using the peripherals and allow bug-free application code to be developed more rapidly. For details, see
the JN51xx Integrated Peripherals API User Guide (JN-UG-3066)[5].
4.6 Unused Memory Addresses
Any attempt to access an unpopulated memory area will result in a bus error exception (interrupt) being generated.© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 19
5 System Clocks
Two system clocks are used to provide timing references into the on-chip subsystems of the JN5148. A 16MHz clock,
generated by a crystal-controlled 32MHz oscillator, is used by the transceiver, processor, memory and digital and
analogue peripherals. A 32kHz clock is used by the sleep timer and during the startup phase of the chip.
5.1 16MHz System Clock
The 16MHz system clock is used by the digital and analogue peripherals and the transceiver. A scaled version
(4,8,16 or 32MHz) of this clock is also used by the processor and memories. For most operations it is necessary to
source this clock from the 32MHz oscillator.
Crystal oscillators are generally slow to start. Hence to provide a faster start-up following a sleep cycle a fast RC
oscillator is provided that can be used as the source for the 16MHz system clock. The oscillator starts very quickly
and is typically 24MHz causing the system clock to run at 12MHz. Using a clock of this speed scales down the speed
of the processor and any peripherals in use. For the SPI interface this causes no functional issues as the generated
SPI clock is slightly slower and is used to clock the external SPI slave. Use of the radio is not possible when using the
24MHz RC oscillator. Additionally, timers and UARTs should not be used as the exact frequency will not be known.
The JN5148 device can be configured to wake up from sleep using the fast RC oscillator and automatically switch
over to use the 32MHz xtal as the clock source, when it has started up. This could allow application code to be
downloaded from the flash before the xtal is ready, typically improving start-up time by 550usec. Alternatively, the
switch over can be controlled by software, or the system could always use the 32MHz oscillator as the clock source.
5.1.1 32MHz Oscillator
The JN5148 contains the necessary on chip components to build a 32MHz reference oscillator with the addition of an
external crystal resonator and two tuning capacitors. The schematic of these components are shown in Figure 9.
The two capacitors, C1 and C2, should typically be 15pF and use a COG dielectric. Due to the small size of these
capacitors, it is important to keep the traces to the external components as short as possible. The on chip
transconductance amplifier is compensated for temperature variation, and is self-biasing by means of the internal
resistor R1. The electrical specification of the oscillator can be found in section 22.3.13. Please refer to Appendix B
for development support with the crystal oscillator circuit.
XTALOUT
C1 C2
R1 XTALIN
JN5148
Figure 9: 32MHz Crystal Oscillator Connections
5.1.2 24MHz RC Oscillator
An on-chip 24MHz RC oscillator is provided. No external components are required for this oscillator. The electrical
specification of the oscillator can be found in section 22.3.14.20 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
5.2 32kHz System Clock
The 32kHz system clock is used for timing the length of a sleep period (see section 21 Power Management and
Sleep Modes) and also to generate the system clock used internally during reset. The clock can be selected from
one of three sources through the application software:
• 32kHz RC Oscillator
• 32kHz Crystal Oscillator
• 32kHz External Clock
Upon a chip reset or power-up the JN5148 defaults to using the internal 32kHz RC Oscillator. If another clock source
is selected then it will remain in use for all 32kHz timing until a chip reset is performed.
5.2.1 32kHz RC Oscillator
The internal 32kHz RC oscillator requires no external components. The internal timing components of the oscillator
have a wide tolerance due to manufacturing process variation and so the oscillator runs nominally at 32kHz ±30%. To
make this useful as a timing source for accurate wakeup from sleep, a frequency calibration factor derived from the
more accurate 16MHz clock may be applied. The calibration factor is derived through software, details can be found
in section 11.3.1. For detailed electrical specifications, see section 22.3.11.
5.2.2 32kHz Crystal Oscillator
In order to obtain more accurate sleep periods, the JN5148 contains the necessary on-chip components to build a
32kHz oscillator with the addition of an external 32.768kHz crystal and two tuning capacitors. The crystal should be
connected between 32KXTALIN and 32KXTALOUT (DIO9 and DIO10), with two equal capacitors to ground, one on
each pin. Due to the small size of the capacitors, it is important to keep the traces to the external components as
short as possible.
The electrical specification of the oscillator can be found in section 22.3.12. The oscillator cell is flexible and can
operate with a range of commonly available 32.768kHz crystals with load capacitances from 6 to 12.5pF. However,
the maximum ESR of the crystal and the supply current are both functions of the actual crystal used, see appendix
B.1 for more details.
32KXTALIN 32KXTALOUT
JN5148
Figure 10: 32kHz crystal oscillator connections
5.2.3 32kHz External Clock
An externally supplied 32kHz reference clock on the 32KIN input (DIO9) may be provided to the JN5148. This would
allow the 32kHz system clock to be sourced from a very stable external oscillator module, allowing more accurate
sleep cycle timings compared to the internal RC oscillator. (See section 22.2.3 I/O Characteristics, DIO9 is a 3V
tolerant input)© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 21
6 Reset
A system reset initialises the device to a pre-defined state and forces the CPU to start program execution from the
reset vector. The reset process that the JN5148 goes through is as follows.
When power is applied, the 32kHz RC oscillator starts up and stabilises, which takes approximately 100µsec. At this
point, the 32MHz crystal oscillator is enabled and power is applied to the processor and peripheral logic. The logic
blocks are held in reset until the 32MHz crystal oscillator stabilises, typically this takes 0.75ms. Then the internal
reset is removed from the CPU and peripheral logic and the CPU starts to run code beginning at the reset vector,
consisting of initialisation code and the resident boot loader. [7] Section 22.3.1 provides detailed electrical data and
timing.
The JN5148 has five sources of reset:
• Internal Power-on Reset
• External Reset
• Software Reset
• Watchdog timer
• Brown-out detect
Note: When the device exits a reset condition, device operating
parameters (voltage, frequency, temperature, etc.) must be met to ensure
operation. If these conditions are not met, then the device must be held in
reset until the operating conditions are met. (See section 22.3)
6.1 Internal Power-on Reset
For the majority of applications the internal power-on reset is capable of generating the required reset signal. When
power is applied to the device, the power-on reset circuit monitors the rise of the VDD supply. When the VDD
reaches the specified threshold, the reset signal is generated and can be observed as a rising edge on the RESETN
pin. This signal is held internally until the power supply and oscillator stabilisation time has elapsed, when the internal
reset signal is then removed and the CPU is allowed to run.
RESETN Pin
Internal RESET
VDD
Figure 11: Internal Power-on Reset
When the supply drops below the power on reset ‘falling’ threshold, it will re-trigger the reset. Use of the external
reset circuit show in Figure 12 is suggested. 22 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
RESETN
C1
R1
JN5148
VDD
18k
470nF
Figure 12: External Reset Generation
The external resistor and capacitor provide a simple reset operation when connected to the RESETN pin.
6.2 External Reset
An external reset is generated by a low level on the RESETN pin. Reset pulses longer than the minimum pulse width
will generate a reset during active or sleep modes. Shorter pulses are not guaranteed to generate a reset. The
JN5148 is held in reset while the RESETN pin is low. When the applied signal reaches the Reset Threshold Voltage
(VRST) on its positive edge, the internal reset process starts.
Multiple devices may connect to the RESETN pin in an open-collector mode. The JN5148 has an internal pull-up
resistor connect to the RESETN pin. The pin is an input for an external reset, an output during the power-on reset
and may optionally be an output during a software reset. No devices should drive the RESETN pin high.
Internal Reset
RESETN pin
Reset
Figure 13: External Reset
6.3 Software Reset
A system reset can be triggered at any time through software control, causing a full chip reset and invalidating the
RAM contents. For example this can be executed within a user’s application upon detection of a system failure. When
performing the reset, the RESETN pin is driven low for 1µsec; depending on the external components this may or
may not be visible on the pin.
In addition, the RESETN line can be driven low by the JN5148 to provide a reset to other devices in the system (e.g.
external sensors) without resetting itself. When the RESETN line is not driven it will pull back high through either the
internal pull-up resistor or any external circuitry. It is essential to ensure that the RESETN line pulls back high within
100µsec after the JN5148 stops driving the line; otherwise a system reset will occur. Due to this, careful consideration
should be taken of any capacitance on this line. For instance, the RC values recommended in section 6.1 may need
to be replaced with a suitable reset IC© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 23
6.4 Brown-out Detect
An internal brown-out detect module is used to monitor the supply voltage to the JN5148; this can be used whilst the
device is awake or is in CPU doze mode. Dips in the supply voltage below a variable threshold can be detected and
can be used to cause the JN5148 to perform a chip reset. Equally, dips in the supply voltage can be detected and
used to cause an interrupt to the processor, when the voltage either drops below the threshold or rises above it.
The brown-out detect is enabled by default from power-up and can extend the reset during power-up. This will keep
the CPU in reset until the voltage exceeds the brown-out threshold voltage. The threshold voltage is configurable to
2.0V, 2.3V, 2.7V and 3.0V and is controllable by software. From power-up the threshold is set by eFuse settings and
the default chip configuration is for the 2.3V threshold. It is recommended that the threshold is set so that, as a
minimum, the chip is held in reset until the voltage reaches the level required by the external memory device on the
SPI interface.
6.5 Watchdog Timer
A watchdog timer is provided to guard against software lockups. It operates by counting cycles of the 32kHz system
clock. A pre-scaler is provided to allow the expiry period to be set between typically 8ms and 16.4 seconds. Failure
to restart the watchdog timer within the pre-configured timer period will cause a chip reset to be performed. A status
bit is set if the watchdog was triggered so that the software can differentiate watchdog initiated resets from other
resets, and can perform any required recovery once it restarts. If the source of the 32kHz system clock is the 32kHz
RC oscillator then the watchdog expiry periods are subject to the variation in period of the RC oscillator.
After power up, reset, start from deep sleep or start from sleep, the watchdog is always enabled with the largest
timeout period and will commence counting as if it had just been restarted. Under software control the watchdog can
be disabled. If it is enabled, the user must regularly restart the watchdog timer to stop it from expiring and causing a
reset. The watchdog runs continuously, even during doze, however the watchdog does not operate during sleep or
deep sleep, or when the hardware debugger has taken control of the CPU. It will recommence automatically if
enabled once the debugger un-stalls the CPU. 24 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
7 Interrupt System
The interrupt system on the JN5148 is a hardware-vectored interrupt system. The JN5148 provides several interrupt
sources, some associated with CPU operations (CPU exceptions) and others which are used by hardware in the
device. When an interrupt occurs, the CPU stops executing the current program and loads its program counter with a
fixed hardware address specific to that interrupt. The interrupt handler or interrupt service routine is stored at this
location and is run on the next CPU cycle. Execution of interrupt service routines is always performed in supervisor
mode. Interrupt sources and their vector locations are listed in Table 2 below:
Interrupt Source Vector Location Interrupt Definition
Bus error 0x08 Typically cause by an attempt to access an invalid address or a
disabled peripheral
Tick timer 0x0e Tick timer interrupt asserted
Alignment error 0x14 Load/store address to non-naturally-aligned location
Illegal instruction 0x1a Attempt to execute an unrecognised instruction
Hardware interrupt 0x20 interrupt asserted
System call 0x26 System call initiated by b.sys instruction
Trap 0x2c caused by the b.trap instruction or the debug unit
Reset 0x38 Caused by software or hardware reset.
Stack Overflow 0x3e Stack overflow
Table 2: Interrupt Vectors
7.1 System Calls
The b.trap and b.sys instructions allow processor exceptions to be generated by software.
A system call exception will be generated when the b.sys instruction is executed. This exception can, for example, be
used to enable a task to switch the processor into supervisor mode when a real time operating system is in use. (See
section 3 for further details.)
The b.trap instruction is commonly used for trapping errors and for debugging.
7.2 Processor Exceptions
7.2.1 Bus Error
A bus error exception is generated when software attempts to access a memory address that does not exist, or is not
populated with memory or peripheral registers or when writing to ROM.
7.2.2 Alignment
Alignment exceptions are generated when software attempts to access objects that are not aligned to natural word
boundaries. 16-bit objects must be stored on even byte boundaries, while 32-bit objects must be stored on quad byte
boundaries. For instance, attempting to read a 16-bit object from address 0xFFF1 will trigger an alignment exception
as will a read of a 32-bit object from 0xFFF1, 0xFFF2 or 0xFFF3. Examples of legal 32-bit object addresses are
0xFFF0, 0xFFF4, 0xFFF8 etc.
7.2.3 Illegal Instruction
If the CPU reads an unrecognised instruction from memory as part of its instruction fetch, it will cause an illegal
instruction exception.
7.2.4 Stack Overflow
When enabled, a stack overflow exception occurs if the stack pointer reaches a programmable location.© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 25
7.3 Hardware Interrupts
Hardware interrupts generated from the transceiver, analogue or digital peripherals and DIO pins are individually
masked using the Programmable Interrupt Controller (PIC). Management of interrupts is provided in the peripherals
library [5]. For details of the interrupts generated from each peripheral see the respective section in this datasheet.
Interrupts can be used to wake the JN5148 from sleep. The peripherals, baseband controller, security coprocessor
and PIC are powered down during sleep but the DIO interrupts and optionally the pulse counters, wake-up timers and
analogue comparator interrupts remain powered to bring the JN5148 out of sleep.
Prioritised external interrupt handling (i.e., interrupts from hardware peripherals) is provided to enable an application
to control an events priority to provide for deterministic program execution.
The priority Interrupt controller provides 15 levels of prioritised interrupts. The priority level of all interrupts can be set,
with value 0 being used to indicate that the source can never produce an external interrupt, 1 for the lowest priority
source(s) and 15 for the highest priority source(s). Note that multiple interrupt sources can be assigned the same
priority level if desired.
If while processing an interrupt, a new event occurs at the same or lower priority level, a new external interrupt will
not be triggered. However, if a new higher priority event occurs, the external interrupt will again be asserted,
interrupting the current interrupt service routine.
Once the interrupt service routine is complete, lower priority events can be serviced. 26 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
8 Wireless Transceiver
The wireless transceiver comprises a 2.45GHz radio, modem, a baseband processor, a security coprocessor and
PHY controller. These blocks, with protocol software provided as a library, implement an IEEE802.15.4 standardsbased
wireless transceiver that transmits and receives data over the air in the unlicensed 2.4GHz band.
8.1 Radio
Figure 14 shows the single ended radio architecture.
LNA
synth
PA
ADC Reference
& Bias
Switch
Radio
Calibration
Lim1
Lim2
Lim3
Lim4
sigma
delta
D-Type
Figure 14: Radio Architecture
The radio comprises a low-IF receive path and a direct modulation transmit path, which converge at the TX/RX
switch. The switch connects to the external single ended matching network, which consists of two inductors and a
capacitor, this arrangement creates a 50Ω port and removes the need for a balun. A 50Ω single ended antenna can
be connected directly to this port.
The 32MHz crystal oscillator feeds a divider, which provides the frequency synthesiser with a reference frequency.
The synthesiser contains programmable feedback dividers, phase detector, charge pump and internal Voltage
Controlled Oscillator (VCO). The VCO has no external components, and includes calibration circuitry to compensate
for differences in internal component values due to process and temperature variations. The VCO is controlled by a
Phase Locked Loop (PLL) that has an internal loop filter. A programmable charge pump is also used to tune the loop
characteristic.
The receiver chain starts with the low noise amplifier / mixer combination whose outputs are passed to a lowpass
filter, which provides the channel definition. The signal is then passed to a series of amplifier blocks forming a limiting
strip. The signal is converted to a digital signal before being passed to the Modem. The gain control for the RX path
is derived in the automatic gain control (AGC) block within the Modem, which samples the signal level at various
points down the RX chain. To improve the performance and reduce current consumption, automatic calibration is
applied to various blocks in the RX path.
In the transmit direction, the digital stream from the Modem is passed to a digital sigma-delta modulator which
controls the feedback dividers in the synthesiser, (dual point modulation). The VCO frequency now tracks the applied
modulation. The 2.4 GHz signal from the VCO is then passed to the RF Power Amplifier (PA), whose power control
can be selected from one of three settings. The output of the PA drives the antenna via the RX/TX switch© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 27
8.1.1 Radio External Components
In order to realise the full performance of the radio it is essential that the reference PCB layout and BOM are carefully
followed. See Appendix B.4.
The radio is powered from a number of internal 1.8V regulators fed from the analogue supply VDD1, in order to
provide good noise isolation between the digital logic of the JN5148 and the analogue blocks. These regulators are
also controlled by the baseband controller and protocol software to minimise power consumption. Decoupling for
internal regulators is required as described in section 2.2.1, Power Supplies
For single ended antennas or connectors, a balun is not required, however a matching network is needed.
The RF matching network requires three external components and the IBIAS pin requires one external component as
shown in schematic in B.4.1. These components are critical and should be placed close to the JN5148 pins and
analogue ground as defined in Table 8: JN5148 Printed Antenna Reference Module Components and PCB Layout
Constraints. Specifically, the output of the network comprising L2, C1 and L1 is designed to present an accurate
match to a 50 ohm resistive network as well as provide a DC path to the final output stage or antenna. Users wishing
to match to other active devices such as amplifiers should design their networks to match to 50 ohms at the output of
L1
R1 43K
IBIAS
C20 100nF
L2 2.7nH
VB_RF
VREF
VB_RF2
RF_IN C12 47pF
C3 100nF
VB_RF1
C1 47pF L1 5.6nH
To Coaxial Socket
or Integrated Antenna
VB_RF
Figure 15 External Radio Components
8.1.2 Antenna Diversity
Support is provided for antenna diversity. Antenna diversity is a technique that maximises the performance of an
antenna system. It allows the radio to switch between two antennas that have very low correlation between their
received signals. Typically, this is achieved by spacing two antennas around 0.25 wavelengths apart or by using two
orthogonal polarisations. So, if a packet is transmitted and no acknowledgement is received, the radio system can
switch to the other antenna for the retry, with a different probability of success.
The JN5148 provides an output (ADO) on DIO12 that is asserted on odd numbered retries and optionally its
complement (ADE) on DIO13, that can be used to control an antenna switch; this enables antenna diversity to be
implemented easily (see Figure 16 and Figure 17).28 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
Antenna A Antenna B
A B
COM
SEL
SELB
ADO (DIO[12])
ADE (DIO[13])
Device RF Port
RF Switch: Single-Pole, Double-Throw (SPDT)
Figure 16 Simple Antenna Diversity Implementation using External RF Switch
ADO (DIO[12])
TX Active
RX Active
ADE (DIO[13])
1st TX-RX Cycle 2nd TX-RX Cycle (1st Retry)
Figure 17 Antenna Diversity ADO Signal for TX with Acknowledgement
If two DIO pins cannot be spared, DIO13 can be configured to be a normal DIO pin, and the inverse of ADO
generated with an inverter on the PCB. © NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 29
8.2 Modem
The modem performs all the necessary modulation and spreading functions required for digital transmission and
reception of data at 250kbps in the 2450MHz radio frequency band in compliance with the IEEE802.15.4 standard. It
also provides a high data rate modes at 500 and 667kbps.
AGC Demodulation
Symbol
Detection
(Despreading)
Modulation Spreading
TX
RX
TX Data
Interface
RX Data
Interface
VCO
Sigma-Delta
Modulator
IF Signal
Gain
Figure 18 Modem Architecture
Features provided to support network channel selection algorithms include Energy Detection (ED), Link Quality
Indication (LQI) and fully programmable Clear Channel Assessment (CCA).
The Modem provides a digital Receive Signal Strength Indication (RSSI) that facilitates the implementation of the
IEEE 802.15.4 ED function and LQI function.
The ED and LQI are both related to receiver power in the same way, as shown in Fig19. LQI is associated with a
received packet, whereas ED is an indication of signal power on air at a particular moment.
The CCA capability of the Modem supports all modes of operation defined in the IEEE 802.15.4 standard, namely
Energy above ED threshold, Carrier Sense and Carrier Sense and/or energy above ED threshold.
Figure 19 Energy Detect Value vs Receive Power Level30 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
8.3 Baseband Processor
The baseband processor provides all time-critical functions of the IEEE802.15.4 MAC layer. Dedicated hardware
guarantees air interface timing is precise. The MAC layer hardware/software partitioning, enables software to
implement the sequencing of events required by the protocol and to schedule timed events with millisecond
resolution, and the hardware to implement specific events with microsecond timing resolution. The protocol software
layer performs the higher-layer aspects of the protocol, sending management and data messages between endpoint
and coordinator nodes, using the services provided by the baseband processor.
Append
Checksum
Verify
Checksum
CSMA CCA Backoff
Control
Deserialiser
Serialiser
Tx/Rx
Frame
Buffer
Tx
Bitstream
Rx
Bitstream
Protocol Timing Engine
Supervisor
Radio
Status
Control
Processor
Bus
Protocol
Timers
Security Coprocessor
Decrypt
Port
Encrypt
Port
AES
Codec
Figure 20: Baseband Processor
8.3.1 Transmit
A transmission is performed by software writing the data to be transferred into the Tx/Rx Frame Buffer, together with
parameters such as the destination address and the number of retries allowed, and programming one of the protocol
timers to indicate the time at which the frame is to be sent. This time will be determined by the software tracking the
higher-layer aspects of the protocol such as superframe timing and slot boundaries. Once the packet is prepared and
protocol timer set, the supervisor block controls the transmission. When the scheduled time arrives, the supervisor
controls the sequencing of the radio and modem to perform the type of transmission required. It can perform all the
algorithms required by IEEE802.15.4 such as CSMA/CA, GTS without processor intervention including retries and
random backoffs.
When the transmission begins, the header of the frame is constructed from the parameters programmed by the
software and sent with the frame data through the serialiser to the Modem. At the same time, the radio is prepared
for transmission. During the passage of the bitstream to the modem, it passes through a CRC checksum generator
that calculates the checksum on-the-fly, and appends it to the end of the frame.
If using slotted access, it is possible for a transmission to overrun the time in its allocated slot; the Baseband
Processor handles this situation autonomously and notifies the protocol software via interrupt, rather than requiring it
to handle the overrun explicitly.
8.3.2 Reception
During reception, the radio is set to receive on a particular channel. On receipt of data from the modem, the frame is
directed into the Tx/Rx Frame Buffer where both header and frame data can be read by the protocol software. An
interrupt may be provided on receipt of the frame header. As the frame data is being received from the modem it is
passed through a checksum generator; at the end of the reception the checksum result is compared with the
checksum at the end of the message to ensure that the data has been received correctly. An interrupt may be © NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 31
provided to indicate successful packet reception. During reception, the modem determines the Link Quality, which is
made available at the end of the reception as part of the requirements of IEEE802.15.4.
8.3.3 Auto Acknowledge
Part of the protocol allows for transmitted frames to be acknowledged by the destination sending an acknowledge
packet within a very short window after the transmitted frame has been received. The JN5148 baseband processor
can automatically construct and send the acknowledgement packet without processor intervention and hence avoid
the protocol software being involved in time-critical processing within the acknowledge sequence. The JN5148
baseband processor can also request an acknowledge for packets being transmitted and handle the reception of
acknowledged packets without processor intervention.
8.3.4 Beacon Generation
In beaconing networks, the baseband processor can automatically generate and send beacon frames; the repetition
rate of the beacons is programmed by the CPU, and the baseband then constructs the beacon contents from data
delivered by the CPU. The baseband processor schedules the beacons and transmits them without CPU
intervention.
8.3.5 Security
The transmission and reception of secured frames using the Advanced Encryption Standard (AES) algorithm is
handled by the security coprocessor and the stack software. The application software must provide the appropriate
encrypt/decrypt keys for the transmission or reception. On transmission, the key can be programmed at the same
time as the rest of the frame data and setup information.
8.4 Security Coprocessor
The security coprocessor is available to the application software to perform encryption/decryption operations. A
hardware implementation of the encryption engine significantly speeds up the processing of the encrypted packets
over a pure software implementation. The AES library for the JN5148 provides operations that utilise the encryption
engine in the device and allow the contents of memory buffers to be transformed. Information such as the type of
security operation to be performed and the encrypt/decrypt key to be used must also be provided.
Processor
Interface
AES
Block
Encrpytion
Controller
AES Encoder
Key Generation
Figure 21: Security Coprocessor Architecture
8.5 Location Awareness
The JN5148 provides the ability for an application to obtain the Time Of Flight (TOF) between two network nodes.
The TOF information is an alternative metric to that of the existing Energy Detect value (RSSI) that has been typically
used for calculating the relative inter-nodal separation, for subsequent use in a location awareness system.
For short ranges RSSI will typically give a better accuracy than TOF, however for distances above 5 to 10 meters
TOF will offer significant improvements in accuracy compared to RSSI. In general, the RSSI error scales with
distance, such that if the distance doubles then the error doubles.32 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
8.6 Higher Data Rates
To support the demands of applications that require high data throughputs such as in audio or data streaming
applications, the JN5148 supports higher data rate modes that offer 500kbps or 667kbps on air transmission rates.
The switching between standard and higher data rates is controlled via software, When operating in a higher data
rate mode standard IEEE802.15.4 features, such as clear channel assessment, can still be used. This allows the
JN5148 in a higher data rate mode to co-exist in an IEEE802.15.4 based network (adhering to the correct bit rates
and frame timing etc.) whilst at the same time providing the benefit of the higher data rate where required.
When operating in a higher data rate mode, the receive sensitivity will be degraded by at least 3dB.© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 33
9 Digital Input/Output
There are 21 Digital I/O (DIO) pins, which can be configured as either an input or an output, and each has a
selectable internal pull-up resistor. Most DIO pins are multiplexed with alternate peripheral features of the device,
see section 2.1. Once a peripheral is enabled it takes precedence over the device pins. Refer to the individual
module sections for a full description of the alternate peripherals functions. Following a reset (and whilst the reset
input is held low), all peripherals are off and the DIO pins are configured as inputs with the internals pull-ups turned
on.
When a peripheral is not enabled, the DIO pins associated with it can be used as digital inputs or outputs. Each pin
can be controlled individually by setting the direction and then reading or writing to the pin.
The individual pull-up resistors, RPU, can also be enabled or disabled as needed and the setting is held through sleep
cycles. The pull-ups are generally configured once after reset depending on the external components and
functionality. For instance, outputs should generally have the pull-ups disabled. An input that is always driven should
also have the pull-up disabled.
When configured as an input each pin can be used to generate an interrupt upon a change of state (selectable
transition either from low to high or high to low); the interrupt can be enabled or disabled. When the device is
sleeping, these interrupts become events that can be used to wake the device up. Equally the status of the interrupt
may be read. See section 21 Power Management and Sleep Modes for further details on sleep and wakeup.
The state of all DIO pins can be read, irrespective of whether the DIO is configured as an input or an output.
Throughout a sleep cycle the direction of the DIO, and the state of the outputs, is held. This is based on the resultant
of the GPIO Data/ Direction registers and the effect of any enabled peripherals at the point of entering sleep.
Following a wake-up these directions and output values are maintained under control of the GPIO data / direction
registers. Any peripherals enabled before the sleep cycle are not automatically re-enabled, this must be done through
software after the wake-up.
For example, if DIO0 is configured to be SPISEL1 then it becomes an output. The output value is controlled by the
SPI functional block. If the device then enters a sleep cycle, the DIO will remain an output and hold the value being
output when entering sleep. After wake-up the DIO will still be an output with the same value but controlled from the
GPIO Data/Direction registers. It can be altered with the software functions that adjust the DIO, or the application may
re-configure it to be SPISEL1.
Unused DIO pins are recommended to be set as inputs with the pull-up enabled.
Two DIO pins can optionally be used to provide control signals for RF circuitry (eg switches and PA) in high power
range extenders.
DIO3 / RFTX is asserted when the radio is in the transmit state and similarly, DIO2 / RFRX is asserted when the radio
is in the receiver state.34 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
4-wire
Digital Audio
Interface
Antenna
Diversity
JTAG
Debug
Pulse
Counters
Intelligent
Peripheral
MUX
2-wire
Interface
Timer2
Timer1
Timer0
UART1
UART0
SPI
Master SPISEL1
SPISEL2
SPISEL3
SPISEL4
TXD0
RXD0
RTS0
CTS0
TXD1
RXD1
RTS1
CTS1
TIM0CK_GT
TIM0OUT
TIM0CAP
TIM1CK_GT
TIM1OUT
TIM1CAP
TIM2OUT
SIF_D
SIF_CLK
IP_DO
IP_DI
IP_INT
IP_CLK
IP_SEL
PC0
PC1
JTAG_TDI
JTAG_TMS
JTAG_TCK
JTAG_TDO
ADO
ADE
I2S_OUT
I2S_DIN
I2S_CLK
I2S_SYNC
SPICLK
SPIMOSI
SPIMISO
SPISEL0
DIO0/SPISEL1
DIO1/SPISEL2/PC0
DIO2/SPISEL3/RFRX
DIO3/SPISEL4/RFTX
DIO4/CTS0/JTAG_TCK
DIO5/RTS0/JTAG_TMS
DIO6/TXD0/JTAG_TDO
DIO7/RXD0/JTAG_TDI
DIO8/TIM0CK_GT/PC1
DIO9/TIM0CAP/32KXTALIN/32KIN
DIO10/TIM0OUT/32KXTALOUT
DIO11/TIM1CK_GT/TIM2OUT
DIO12/TIM1CAP/ADO/DAI_WS
DIO13/TIM1OUT/ADE/DAI_SDN
DIO14/SIF_CLK/IP_CLK
DIO15/SIF_D/IP_DO
DIO16/IP_DI
DIO17/CTS1/IP_SEL/DAI_SCK/
JTAG_TCK
DIO18/RTS1/IP_INT/DAI_SDOUT/
JTAG_TMS
DIO19/TXD1/JTAG_TDO
DIO20/RXD1/JTAG_TDI
Figure 22 DIO Block Diagram© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 35
10 Serial Peripheral Interface
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the JN5148 and
peripheral devices. The JN5148 operates as a master on the SPI bus and all other devices connected to the SPI are
expected to be slave devices under the control of the JN5148 CPU. The SPI includes the following features:
• Full-duplex, three-wire synchronous data transfer
• Programmable bit rates (up to 16Mbit/s)
• Programmable transaction size up to 32-bits
• Standard SPI modes 0,1,2 and 3
• Manual or Automatic slave select generation (up to 5 slaves)
• Maskable transaction complete interrupt
• LSB First or MSB First Data Transfer
• Supports delayed read edges
Clock
Divider
SPI Bus
Cycle
Controller
Data Buffer
DIV
Clock Edge
Select
Data
CHAR_LEN
LSB
SPIMISO
SPIMOSI
SPICLK
Select
Latch
SPISEL [4..0]
16 MHz
Figure 23: SPI Block Diagram
The SPI bus employs a simple shift register data transfer scheme. Data is clocked out of and into the active devices
in a first-in, first-out fashion allowing SPI devices to transmit and receive data simultaneously.
There are three dedicated pins SPICLK, SPIMOSI, SPIMISO that are shared across all devices on the bus. MasterOut-Slave-In
or Master-In-Slave-Out data transfer is relative to the clock signal SPICLK generated by the JN5148.
The JN5148 provides five slave selects, SPISEL0 to SPISEL4 to allow five SPI peripherals on the bus. SPISEL0 is a
dedicated pin; this is generally connected to a serial Flash/ EEPROM memory holding application code that is
downloaded to internal RAM via software from reset. SPISEL1 to 4, are alternate functions of pins DIO0 to 3
respectively.
The interface can transfer from 1 to 32-bits without software intervention and can keep the slave select lines asserted
between transfers when required, to enable longer transfers to be performed.
When the device reset is active, the three outputs SPISEL, SPICLK and SPI_MOSI are tri-stated and SPI_MISO is
set to be an input. The pull-up resistors associated with all four pins will be active at this time. 36 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013 SI
C
SO
SS
Slave 0
Flash/
EEPROM
Memory
JN5148
37
38
41
42
43
36
33
34
SI
C
SO
SS
Slave 1
User
Defined
SI
C
SO
SS
Slave 2
User
Defined
SI
C
SO
SS
Slave 3
User
Defined
SI
C
SO
SS
Slave 4
User
Defined
SPIMISO
SPIMOSI
SPICLK
SPISEL4
SPISEL2
SPISEL3
SPISEL1
SPISEL0
Figure 24: Typical JN5148 SPI Peripheral Connection
The data transfer rate on the SPI bus is determined by the SPICLK signal. The JN5148 supports transfers at
selectable data rates from 16MHz to 125kHz selected by a clock divider. Both SPICLK clock phase and polarity are
configurable. The clock phase determines which edge of SPICLK is used by the JN5148 to present new data on the
SPIMOSI line; the opposite edge will be used to read data from the SPIMISO line. The interface should be configured
appropriately for the SPI slave being accessed.
SPICLK
Mode Description
Polarity
(CPOL)
Phase
(CPHA)
0 0 0 SPICLK is low when idle – the first edge is positive.
Valid data is output on SPIMOSI before the first clock and changes every
negative edge. SPIMISO is sampled every positive edge.
0 1 1 SPICLK is low when idle – the first edge is positive.
Valid data is output on SPIMOSI every positive edge. SPIMISO is sampled every
negative edge.
1 0 2 SPICLK is high when idle – the first edge is negative.
Valid data is output on SPIMOSI before the first clock edge and is changed
every positive edge. SPIMISO is sampled every negative edge.
1 1 3 SPICLK is high when idle – the first edge is negative.
Valid data is output on SPIMOSI every negative edge. SPIMISO is sampled
every positive edge.
Table 3 SPI Configurations
If more than one SPISEL line is to be used in a system they must be used in numerical order starting from SPISEL0.
For instance if 3 SPI select lines are to be used, they must be SPISEL0, 1 and 2. A SPISEL line can be automatically
deasserted between transactions if required, or it may stay asserted over a number of transactions. For devices such
as memories where a large amount of data can be received by the master by continually providing SPICLK
transitions, the ability for the select line to stay asserted is an advantage since it keeps the slave enabled over the
whole of the transfer.
A transaction commences with the SPI bus being set to the correct configuration, and then the slave device is
selected. Upon commencement of transmission (1 to 32 bits) data is placed in the FIFO data buffer and clocked out,
at the same time generating the corresponding SPICLK transitions. Since the transfer is full-duplex, the same
number of data bits is being received from the slave as it transmits. The data that is received during this transmission
can be read (1 to 32 bits). If the master simply needs to provide a number of SPICLK transitions to allow data to be © NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 37
sent from a slave, it should perform transmit using dummy data. An interrupt can be generated when the transaction
has completed or alternatively the interface can be polled.
If a slave device wishes to signal the JN5148 indicating that it has data to provide, it may be connected to one of the
DIO pins that can be enabled as an interrupt.
Figure 25 shows a complex SPI transfer, reading data from a FLASH device, that can be achieved using the SPI
master interface. The slave select line must stay low for many separate SPI accesses, and therefore manual slave
select mode must be used. The required slave select can then be asserted (active low) at the start of the transfer. A
sequence 8 and 32 bit transfers can be used to issue the command and address to the FLASH device and then to
read data back. Finally, the slave select can be deselected to end the transaction.
0 1 2 3 4 5 6 7
Instruction (0x03)
23 22 21 3 2 1 0
8 9 10 28 29 30 31
24-bit Address
MSB
Instruction Transaction
7 6 5 4 3 2 1 0
MSB
0 1 2 3 4 5 7 8N-1
3 2 1 0
LSB
Read Data Bytes Transaction(s) 1-N
SPISEL
SPICLK
SPIMOSI
SPIMISO
SPISEL
SPICLK
SPIMOSI
SPIMISO
8 9 10
7 6 5
MSB
Byte 1 Byte 2 Byte N
value unused by peripherals
6
Figure 25: Example SPI Waveforms – Reading from FLASH device using Mode 038 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
11 Timers
11.1 Peripheral Timer/Counters
Three general-purpose timer/counter units are available that can be independently configured to operate in one of
five possible modes. Timer 0 and 1 support all 5 modes of operation and Timer 2 supports PWM and Delta-Sigma
modes only. The timers have the following:
• 5-bit prescaler, divides system clock by 2 prescale value as the clock to the timer (prescaler range is 0 to 16)
• Clocked from internal system clock (16MHz)
• 16-bit counter, 16-bit Rise and Fall (period) registers
• Timer: can generate interrupts off Rise and Fall counts. Can be gated by external signal
• Counter: counts number of transitions on external event signal. Can use low-high, high-low or both
transitions
• PWM/Single pulse: outputs repeating Pulse Width Modulation signal or a single pulse. Can set period and
mark-space ratio
• Capture: measures times between transitions of an applied signal
• Delta-Sigma: Return-To-Zero (RTZ) and Non-Return-to-Zero (NRZ) modes
• Timer usage of external IO can be controlled on a pin by pin basis
Interrupt
Generator
Rise
Fall
Delta-Sigma
Counter
Reset Generator
=
Prescaler
INT
Int Enable
SYSCLK
S/w
Reset
System
Reset
Single
Shot
=
S
R
OE
Gate
Gate
Edge
Select
Reset
PWM/DeltaSigma
Capture
Generator
Capture
Enable
PWM/∆−Σ
PWM/∆−Σ
TIMxCK_GT
TIMxOUT
TIMxCAP
Figure 26: Timer Unit Block Diagram© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 39
The clock source for the timer unit is fed from the 16MHz system clock. This clock passes to a 5-bit prescaler where a
value of 0 leaves the clock unmodified and other values divide it by 2 prescale value. For example, a prescale value of
2 applied to the 16MHz system clock source results in a timer clock of 4MHz.
The counter is optionally gated by a signal on the clock/gate input (TIMxCK_GT). If the gate function is selected,
then the counter is frozen when the clock/gate input is high.
An interrupt can be generated whenever the counter is equal to the value in either of the High or Low registers.
The internal Output Enable (OE) signal enables or disables the timer output.
The Timer 0 signals CK_GT, CAP and OUT are alternate functions of pins DIO8, 9 and 10 respectively and Timer 1
signals CK_GT, CAP and OUT are alternate functions of pins DIO11, 12, and 13 respectively. Timer 2 OUT is an
alternate function of DIO11 If operating in timer mode it is not necessary to use any of the DIO pins, allowing the
standard DIO functionality to be available to the application.
Note, timer 0 may only be used as an internal timer or in counter mode (counting events) if an external 32kHz crystal
is used. If timer 2 is used in PWM or Delta-Sigma mode then timer 1 does not have access to its clock/gate pin.
Therefore, it can not operate in counter mode (counting events) or use the gate function.
11.1.1 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode allows the user to specify an overall cycle time and pulse length within the
cycle. The pulse can be generated either as a single shot or as a train of pulses with a repetition rate determined by
the cycle time.
In this mode, the cycle time and low periods of the PWM output signal can be set by the values of two independent
16-bit registers (Fall and Rise). The counter increments and its output is compared to the 16-bit Rise and Fall
registers. When the counter is equal to the Rise register, the PWM output is set to high; when the counter reaches
the Fall value, the output returns to low. In continuous mode, when the counter reaches the Fall value, it will reset
and the cycle repeats. The PWM waveform is available on TIMxOUT when the output driver is enabled.
Rise
Fall
Figure 27: PWM Output Timings
11.1.2 Capture Mode
The capture mode can be used to measure the time between transitions of a signal applied to the capture input
(TIMxCAP). When the capture is started, on the next low-to-high transition of the captured signal, the count value is
stored in the Rise register, and on the following high-to-low transition, the counter value is stored in the Fall register.
The pulse width is the difference in counts in the two registers multiplied by the period of the prescaled clock. Upon
reading the capture registers the counter is stopped. The values in the High and Low registers will be updated
whenever there is a corresponding transition on the capture input, and the value stored will be relative to when the
mode was started. Therefore, if multiple pulses are seen on TIMxCAP before the counter is stopped only the last
pulse width will be stored.40 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
CLK
CAPT
x 9 3
x 14
t
RISE t
RISE
t
FALL t
FALL
Rise
Fall
9 5 3 4
7
Capture Mode Enabled
Figure 28: Capture Mode
11.1.3 Counter/Timer Mode
The counter/timer can be used to generate interrupts, based on the timers or event counting, for software to use. As
a timer the clock source is from the system clock, prescaled if required. The timer period is programmed into the Fall
register and the Fall register match interrupt enabled. The timer is started as either a single-shot or a repeating timer,
and generates an interrupt when the counter reaches the Fall register value.
When used to count external events on TIMxCK_GT the clock source is selected from the input pin and the number
of events programmed into the Fall register. The Fall register match interrupt is enabled and the counter started,
usually in single shot mode. An interrupt is generated when the programmed number of transitions is seen on the
input pin. The transitions counted can configured to be rising, falling or both rising and falling edges.
Edges on the event signal must be at least 100nsec apart, i.e. pulses must be wider than 100nsec.
11.1.4 Delta-Sigma Mode
A separate delta-sigma mode is available, allowing a low speed delta-sigma DAC to be implemented with up to 16-bit
resolution. This requires that a resistor-capacitor network is placed between the output DIO pin and digital ground. A
stream of pulses with digital voltage levels is generated which is integrated by the RC network to give an analogue
voltage. A conversion time is defined in terms of a number of clock cycles. The width of the pulses generated is the
period of a clock cycle. The number of pulses output in the cycle, together with the integrator RC values, will
determine the resulting analogue voltage. For example, generating approximately half the number of pulses that
make up a complete conversion period will produce a voltage on the RC output of VDD1/2, provided the RC time
constant is chosen correctly. During a conversion, the pulses will be pseudo-randomly dispersed throughout the
cycle in order to produce a steady voltage on the output of the RC network.
The output signal is asserted for the number of clock periods defined in the High register, with the total period being
216 cycles. For the same value in the High register, the pattern of pulses on subsequent cycles is different, due to the
pseudo-random distribution.
The delta-sigma convertor output can operate in a Return-To-Zero (RTZ) or a Non-Return-to-Zero (NRZ) mode. The
NRZ mode will allow several pulses to be output next to each other. The RTZ mode ensures that each pulse is
separated from the next by at least one period. This improves linearity if the rise and fall times of the output are
different to one another. Essentially, the output signal is low on every other output clock period, and the conversion
cycle time is twice the NRZ cycle time ie 217 clocks. The integrated output will only reach half VDD2 in RTZ mode,
since even at full scale only half the cycle contains pulses. Figure 29 and Figure 30 illustrate the difference between
RTZ and NRZ for the same programmed number of pulses.© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 41
1 2 3 1 2 N
Conversion cycle 1
217
N
Conversion cycle 2
3
Figure 29: Return To Zero Mode in Operation
1 2 3 1 2 N
Conversion cycle 1
N 3
216 Conversion cycle 2
Figure 30: Non-Return to Zero Mode
11.1.5 Example Timer / Counter Application
Figure 31 shows an application of the JN5148 timers to provide closed loop speed control. Timer 0 is configured in
PWM mode to provide a variable mark-space ratio switching waveform to the gate of the NFET. This in turn controls
the power in the DC motor.
Timer 1 is configured to count the rising edge events on the clk/gate pin over a constant period. This converts the
tacho pulse stream output into a count proportional to the motor speed. This value is then used by the application
software executing the control algorithm.
If required for other functionality, then the unused IO associated with the timers could be used as general purpose
DIO.
JN5148
Timer 0
Timer 1
CLK/GATE
CLK/GATE
CAPTURE
CAPTURE
PWM
PWM
M Tacho
48
50
52
53
54
1N4007
+12V
IRF521 51
1 pulse/rev
Figure 31: Closed Loop PWM Speed Control Using JN5148 Timers
11.2 Tick Timer
The JN5148 contains a hardware timer that can be used for generating timing interrupts to software. It may be used
to implement regular events such as ticks for software timers or an operating system, as a high-precision timing
reference or can be used to implement system monitor timeouts as used in a watchdog timer. Features include:
• 32-bit counter42 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
• 28-bit match value
• Maskable timer interrupt
• Single-shot, Restartable or Continuous modes of operation
Match Value
Counter
=
Mode
Control
&
&
SysClk
Run
Match
Int
Enable
Tick Timer
Interrupt
Reset
Mode
Figure 32: Tick Timer
The Tick Timer is clocked from a continuous 16MHz clock, which is fed to a 32-bit wide resettable up-counter, gated
by a signal from the mode control block. A match register allows comparison between the counter and a
programmed value. The match value, measured in 16MHz clock cycles is programmed through software, in the
range 0 to 0x0FFFFFFF. The output of the comparison can be used to generate an interrupt if the interrupt is
enabled and used in controlling the counter in the different modes. Upon configuring the timer mode, the counter is
also reset.
If the mode is programmed as single shot, the counter begins to count from zero until the match value is reached.
The match signal will be generated which will cause an interrupt if enabled, and the counter will stop counting. The
counter is restarted by reprogramming the mode.
If the mode is programmed as restartable, the operation of the counter is the same as for the single shot mode,
except that when the match value is reached the counter is reset and begins counting from zero. An interrupt will be
generated when the match value is reached if it is enabled.
Continuous mode operation is similar to restartable, except that when the match value is reached, the counter is not
reset but continues to count. An interrupt will be generated when the match value is reached if enabled.
11.3 Wakeup Timers
Two 32-bit wakeup timers are available in the JN5148 driven from the 32kHz internal clock. They may run during
sleep periods when the majority of the rest of the device is powered down, to time sleep periods or other long period
timings that may be required by the application. The wakeup timers do not run during deep sleep and may optionally
be disabled in sleep mode through software control. When a wakeup timer expires it typically generates an interrupt,
if the device is asleep then the interrupt may be used as an event to end the sleep period. See Section 21 for further
details on how they are used during sleep periods. Features include:
• 35-bit down-counter
• Optionally runs during sleep periods
• Clocked by 32kHz system clock; either 32kHz RC oscillator, 32kHz XTAL oscillator or 32kHz clock input© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 43
A wakeup timer consists of a 35-bit down counter clocked from the selected 32 kHz clock. An interrupt or wakeup
event can be generated when the counter reaches zero. On reaching zero the counter will continue to count down
until stopped, which allows the latency in responding to the interrupt to be measured. If an interrupt or wakeup event
is required, the timer interrupt should be enabled before loading the count value for the period. Once the count value
is loaded and counter started, the counter begins to count down; the counter can be stopped at any time through
software control. The counter will remain at the value it contained when the timer was stopped and no interrupt will
be generated. The status of the timers can be read to indicate if the timers are running and/or have expired; this is
useful when the timer interrupts are masked. This operation will reset any expired status flags.
11.3.1 RC Oscillator Calibration
The RC oscillator that can be used to time sleep periods is designed to require very little power to operate and be
self-contained, requiring no external timing components and hence is lower cost. As a consequence of using on-chip
resistors and capacitors, the inherent absolute accuracy and temperature coefficient is lower than that of a crystal
oscillator, but once calibrated the accuracy approaches that of a crystal oscillator. Sleep time periods should be as
close to the desired time as possible in order to allow the device to wake up in time for important events, for example
beacon transmissions in the IEEE802.15.4 protocol. If the sleep time is accurate, the device can be programmed to
wake up very close to the calculated time of the event and so keep current consumption to a minimum. If the sleep
time is less accurate, it will be necessary to wake up earlier in order to be certain the event will be captured. If the
device wakes earlier, it will be awake for longer and so reduce battery life.
In order to allow sleep time periods to be as close to the desired length as possible, the true frequency of the RC
oscillator needs to be determined to better than the initial 30% accuracy. The calibration factor can then be used to
calculate the true number of nominal 32kHz periods needed to make up a particular sleep time. A calibration
reference counter, clocked from the 16MHz system clock, is provided to allow comparisons to be made between the
32kHz RC clock and the 16MHz system clock when the JN5148 is awake.
Wakeup timer0 counts for a set number of 32kHz clock periods during which time the reference counter runs. When
the wakeup timer reaches zero the reference counter is stopped, allowing software to read the number of 16MHz
clock ticks generated during the time represented by the number of 32kHz ticks programmed in the wakeup timer.
The true period of the 32kHz clock can thus be determined and used when programming a wakeup timer to achieve a
better accuracy and hence more accurate sleep periods
For a RC oscillator running at exactly 32,000Hz the value returned by the calibration procedure should be 10000, for
a calibration period of twenty 32,000Hz clock periods. If the oscillator is running faster than 32,000Hz the count will
be less than 10000, if running slower the value will be higher. For a calibration count of 9000, indicating that the RC
oscillator period is running at approximately 35kHz, to time for a period of 2 seconds the timer should be loaded with
71,111 ((10000/9000) x (32000 x 2)) rather than 64000.44 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
12 Pulse Counters
Two 16-bit counters are provided that can increment during all modes of operation (including sleep), based on pulses
received on 2 dedicated DIO inputs; DIO1 and DIO8. The pulses can be de-bounced using the 32kHz clock to guard
against false counting on slow or noisy edges. Increments occur from a configurable rising or falling edge on the
respective DIO input.
Each counter has an associated 16-bit reference that is loaded by the user. An interrupt (and wakeup event if
asleep) may be generated when a counter reaches its pre-configured reference value. The two counters may
optionally be cascaded together to provide a single 32-bit counter, linked to DIO1. The counters do not saturate at
65535, but naturally roll-over to 0. Additionally, the pulse counting continues when the reference value is reached
without software interaction so that pulses are not missed even if there is a long delay before an interrupt is serviced
or during the wakeup process.
The system can work with signals up to 100kHz, with no debounce, or from 5.3kHz to 1.7kHz with debounce. When
using debounce the 32kHz clock must be active, so for minimum sleep currents the debounce mode should not be
used.© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 45
13 Serial Communications
The JN5148 has two independent Universal Asynchronous Receiver/Transmitter (UART) serial communication
interfaces. These provide similar operating features to the industry standard 16550A device operating in FIFO mode.
Each interface performs serial-to-parallel conversion on incoming serial data and parallel-to-serial conversion on
outgoing data from the CPU to external devices. In both directions, a 16-byte deep FIFO buffer allows the CPU to
read and write multiple characters on each transaction. This means that the CPU is freed from handling data on a
character-by-character basis, with the associated high processor overhead. The UARTs have the following features:
• Emulates behaviour of industry standard NS16450 and NS16550A UARTs
• 16 byte transmit and receive FIFO buffers reduce interrupts to CPU, with direct access to fill levels of each
• Adds / deletes standard start, stop and parity communication bits to or from the serial data
• Independently controlled transmit, receive, status and data sent interrupts
• Optional modem flow control signals CTS and RTS
• Fully programmable data formats: baud rate, start, stop and parity settings
• False start bit detection, parity, framing and FIFO overrun error detect and break indication
• Internal diagnostic capabilities: loop-back controls for communications link fault isolation
• Flow control by software or automatically by hardware Processor Bus
Divisor
Latch
Registers
Line
Status
Register
Line
Control
Register
FIFO
Control
Register
Receiver FIFO
Transmitter FIFO
Baud Generator
Logic
Transmitter Shift
Register
Receiver Shift
Register
Transmitter
Logic
Receiver
Logic
RXD
TXD
Modem
Control
Register
Modem
Status
Register Modem
Signals
Logic
RTS
CTS
Interrupt
ID
Register
Interrupt
Enable
Register
Interrupt
Logic
Internal
Interrupt
Figure 33: UART Block Diagram
The serial interface contains programmable fields that can be used to set number of data bits (5, 6,7 or 8), even, odd,
set-at-1, set-at-0 or no-parity detection and generation of single or multiple stop bit, (for 5 bit data, multiple is 1.5 stop
bits; for 6, 7 or 8 data bits, multiple is 2 bits).
The baud rate is programmable up to 1Mbps, standard baud rates such as 4800, 9600, 19.2k, 38.4k etc. can be
configured.
For applications requiring hardware flow control, two control signals are provided: Clear-To-Send (CTS) and RequestTo-Send
(RTS). CTS is an indication sent by an external device to the UART that it is ready to receive data. RTS is
an indication sent by the UART to the external device that it is ready to receive data. RTS is controlled from software,
while the value of CTS can be read. Monitoring and control of CTS and RTS is a software activity, normally
performed as part of interrupt processing. The signals do not control parts of the UART hardware, but simply indicate
to software the state of the UART external interface. Alternatively, the Automatic Flow Control mode can be set 46 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
where the hardware controls the value of the generated RTS (negated if the receive FIFO fill level is greater than a
programmable threshold of 8, 11, 13 or 15 bytes), and only transmits data when the incoming CTS is asserted.
Software can read characters, one byte at a time, from the Receive FIFO and can also write to the Transmit FIFO,
one byte at a time. The Transmit and Receive FIFOs can be cleared and reset independently of each other. The
status of the transmitter can be checked to see if it is empty, and if there is a character being transmitted. The status
of the receiver can also be checked, indicating if conditions such as parity error, framing error or break indication
have occurred. It also shows if an overrun error occurred (receive buffer full and another character arrives) and if
there is data held in the receive FIFO.
UART 0 signals CTS, RTS, TXD and RXD are alternate functions of pins DIO4, 5, 6 and 7 respectively and UART 1
signals CTS, RTS, TXD and RXD are alternate functions of pins DIO17, 18, 19 and 20 respectively. If CTS and RTS
are not required on the devices external pins, then they may be disabled, this allows the DIOx function to be used for
other purposes.
Note: With the automatic flow control threshold set to 15, the hardware flow control within the UART block negates
RTS when the receive FIFO is about to become full. In some instances it has been observed that remote devices that
are transmitting data do not respond quickly enough to the de-asserted CTS and continue to transmit data. In these
instances the data will be lost in a receive FIFO overflow.
13.1 Interrupts
Interrupt generation can be controlled for the UART block, and is divided into four categories:
• Received Data Available: Is set when data in the Rx FIFO queue reaches a particular level (the trigger level can
be configured as 1, 4, 8 or 14) or if no character has been received for 4 character times.
• Transmit FIFO Empty: set when the last character from the Tx FIFO is read and starts to be transmitted.
• Receiver Line Status: set when one of the following occur (1) Parity Error - the character at the head of the
receive FIFO has been received with a parity error, (2) Overrun Error - the Rx FIFO is full and another character
has been received at the Receiver shift register, (3) Framing Error - the character at the head of the receive
FIFO does not have a valid stop bit and (4) Break Interrupt – occurs when the RxD line has been held low for an
entire character.
• Modem Status: Generated when the CTS (Clear To Send) input control line changes.
13.2 UART Application
The following example shows the UART connected to a 9-pin connector compatible with a PC. As the JN5148
device pins do not provide the RS232 line voltage, a level shifter is used.
JN5148
RTS
CTS
TXD
UART0 RXD
RS232
Lev el
Shif ter
1
2
3
4
5
6
7
8
9
CD
RD
TD
DTR
SG
DSR
RTS
CTS
RI
PC COM Port
1 5 Pin Signal
6 9
46
47
45
44
Figure 34: JN5148 Serial Communication Link© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 47
14 JTAG Debug Interface
The JN5148 includes an IEEE1149.1 compliant JTAG port for the sole purpose of software code debug with NXP's
Software Developer’s Kit. The JTAG interface is disabled by default and is enabled under software control.
Therefore, debugging is only possible if enabled by the application. Once enabled, the application executes as
normal until the external debugger controller initiates debug activity.
The Debugger supports breakpoints and watchpoints based on four comparisons between any of program counter,
load/store effective address and load/store data. There is the ability to chain the comparisons together. There is also
the ability, under debugger control to perform the following commands: go, stop, reset, step over/into/out/next, run to
cursor and breakpoints. In addition, under control of the debugger, it is possible to:
• Read and write registers on the wishbone bus
• Read ROM and RAM, and write to RAM
• Read and write CPU internal registers
The Debugger interface is accessed, depending upon the configuration, through the pins used for UART0 or UART1.
This is enabled under software control and is dealt with in JN-AN-1118 JN5148 Application Debugging [4]. The
following table details which DIO are used for the JTAG interface depending upon the configuration.
Signal DIO Assignment
UART0 pins UART1 pins
clock (TCK) 4 17
control (TMS) 5 18
data out (TDO) 6 19
data in (TDI) 7 20
Table 4 Hardware Debugger IO
If doze mode is active when debugging is started, the processor will be woken and then respond to debugger
commands. It is not possible to wake the device from sleep using the debug interface and debugging is not available
while the device is sleeping.
When using the debug interface, program execution is halted, and control of the CPU is handed to the debugger. The
watchdog, tick timer and the three timers described in section 11 are stalled while the debugger is in control of the
CPU.
When control is handed from the CPU to the debugger or back a small number of CPU clock cycles are taken
flushing or reloading the CPU pipeline. Because of this, when a program is halted by the debugger and then restarted
again, a small number of tick timer cycles will elapse.
It is possible to prevent all hardware debugging by blowing the relevant Efuse bit.
The JTAG interface does not support boundary scan testing. It is recommended that the JN5148 is not connected as
part of the board scan chain.48 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
15 Two-Wire Serial Interface
The JN5148 includes industry standard two-wire synchronous Serial Interface operates as a Master (MSIF) or Slave
(SSIF) that provides a simple and efficient method of data exchange between devices. The system uses a serial data
line (SIF_D) and a serial clock line (SIF_CLK) to perform bi-directional data transfers and includes the following
features:
Common to both master and slave:
• Compatible with both I2
C and SMbus peripherals
• Support for 7 and 10-bit addressing modes
• Optional pulse suppression on signal inputs
Master only:
• Multi-master operation
• Software programmable clock frequency
• Clock stretching and wait state generation
• Software programmable acknowledge bit
• Interrupt or bit-polling driven byte-by-byte data-transfers
• Bus busy detection
Slave only:
• Programmable slave address
• Simple byte level transfer protocol
• Write data flow control with optional clock stretching or acknowledge mechanism
• Read data preloaded or provided as required
15.1 Connecting Devices
The clock and data lines, SIF_D and SIF_CLK, are alternate functions of DIO15 and DIO14 respectively. The serial
interface function of these pins is selected when the interface is enabled. They are both bi-directional lines,
connected internally to the positive supply voltage via weak (45kΩ) programmable pull-up resistors. However, it is
recommended that external 4.7kΩ pull-ups be used for reliable operation at high bus speeds, as shown in Figure 35.
When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an opendrain
or open-collector in order to perform the wired-AND function. The number of devices connected to the bus is
solely dependent on the bus capacitance limit of 400pF.
SIF_CLK
SIF_D
VDD
D1_OUT
D1_IN CLK1_IN
CLK1_OUT
D2_IN CLK2_IN
CLK2_OUT
DEVICE 1 DEVICE 2
RP RP Pullup
Resistors
D2_OUT
JN5148
SIF
DIO14
DIO15
Figure 35: Connection Details© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 49
15.2 Clock Stretching
Slave devices can use clock stretching to slow down the transfer bit rate. After the master has driven SIF_CLK low,
the slave can drive SIF_CLK low for the required period and then release it. If the slave’s SIF_CLK low period is
greater than the master’s low period the resulting SIF_CLK bus signal low period is stretched thus inserting wait
states.
SIF_CLK
SIF_CLK
SIF_CLK
Master SIF_CLK
Slave SIF_CLK
Wired-AND SIF_CLK
Clock held low
by Slave
Figure 36: Clock Stretching
15.3 Master Two-wire Serial Interface
When operating as a master device, it provides the clock signal and a prescale register determines the clock rate,
allowing operation up to 400kbit/s.
Data transfer is controlled from the processor bus interface at a byte level, with the processor responsible for
indicating when start, stop, read, write and acknowledge control should be generated. Write data written into a
transmit buffer will be written out across the two-wire interface when indicated, and read data received on the
interface is made available in a receive buffer. Indication of when a particular transfer has completed may be
indicated by means of an interrupt or by polling a status bit.
The first byte of data transferred by the device after a start bit is the slave address. The JN5148 supports both 7-bit
and 10-bit slave addresses by generating either one or two address transfers. Only the slave with a matching address
will respond by returning an acknowledge bit.
The master interface provides a true multi-master bus including collision detection and arbitration that prevents data
corruption. If two or more masters simultaneously try to control the bus, a clock synchronization procedure
determines the bus clock. Because of the wired-AND connection of the interface, a high-to-low transition on the bus
affects all connected devices. This means a high-to-low transition on the SIF_CLK line causes all concerned devices
to count off their low period. Once the clock input of a device has gone low, it will hold the SIF_CLK line in that state
until the clock high state is reached when it releases the SIF_CLK line. Due to the wired-AND connection, the
SIF_CLK line will therefore be held low by the device with the longest low period, and held high by the device with the
shortest high period.
SIF_CLK1
SIF_CLK2
SIF_CLK
Master1 SIF_CLK
Master2 SIF_CLK
Wired-AND SIF_CLK
Start counting
low period
Start counting
high period
Wait
State
Figure 37: Multi-Master Clock Synchronisation
After each transfer has completed, the status of the device must be checked to ensure that the data has been
acknowledged correctly, and that there has been no loss of arbitration. (N.B. Loss of arbitration may occur at any
point during the transfer, including data cycles). An interrupt will be generated when arbitration has been lost.50 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
15.4 Slave Two-wire Serial Interface
When operating as a slave device, the interface does not provide a clock signal, although it may drive the clock signal
low if it is required to apply clock stretching.
Only transfers whose address matches the value programmed into the interface’s address register are accepted. The
interface allows both 7 and 10 bit addresses to be programmed, but only responds with an acknowledge to a single
address. Addresses defined as “reserved” will not be responded to, and should not be programmed into the address
register. A list of reserved addresses is shown in Table 5.
Address Name Behaviour
0000 000 General Call/Start Byte Ignored
0000 001 CBUS address Ignored
0000 010 Reserved Ignored
0000 011 Reserved Ignored
0000 1XX Hs-mode master code Ignored
1111 1XX Reserved Ignored
1111 0XX 10-bit address Only responded to if 10 bit address
set in address register
Table 5 : List of two-wire serial interface reserved addresses
Data transfer is controlled from the processor bus interface at a byte level, with the processor responsible for taking
write data from a receive buffer and providing read data to a transmit buffer when indicated. A series of interrupt
status bits are provided to control the flow of data.
For writes, in to the slave interface, it is important that data is taken from the receive buffer by the processor before
the next byte of data arrives. To enable this, the interface may be configured to work in two possible backoff modes:
• Not Acknowledge mode – where the interface returns a Not Acknowledge (NACK) to the master if more data
is received before the previous data has been taken. This will lead to the termination of the current data
transfer.
• Clock Stretching mode – where the interface holds the clock line low until the previous data has been taken.
This will occur after transfer of the next data but before issuing an acknowledge
For reads, from the slave interface, the data may be preloaded into the transmit buffer when it is empty (i.e. at the
start of day, or when the last data has been read), or fetched each time a read transfer is requested. When using data
preload, read data in the buffer must be replenished following a data write, as the transmit and received data is
contained in a shared buffer. The interface will hold the bus using clock stretching when the transmit buffer is empty.
Interrupts may be triggered when:
• Data Buffer read data is required – a byte of data to be read should be provided to avoid the interface from
clock stretching
• Data Buffer read data has been taken – this indicates when the next data may be preloaded into the data
buffer
• Data Buffer write data is available – a byte of data should be taken from the data buffer to avoid data backoff
as defined above
• The last data in a transfer has completed – i.e. the end of a burst of data, when a Stop or Restart is seen
• A protocol error has been spotted on the interface© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 51
16 Four-Wire Digital Audio Interface
The JN5148 includes a four-wire digital audio interface that can be used for interfacing to audio CODECs. The
following features are supported:
• Compatible with the industry standard I²S interface
• Option to support I²S, left justified and right justified modes
• Optional support for connection to mono sample FIFO with data transferred on the left or right channel
• Master only
• Transmit on falling edge and receive on rising edge
• Up to 8MHz maximum clock range
• Maximum system size of 32-bits, allowing up to 16-bits per channel (left or right channels)
• Option for pad bit insertion, allowing length of transfer per channel to be anything from 16 to 32 bits
• Data Transfer size range of 1 to 16-bits per channel
• Option to invert WS (normally 0 for left, but allow 1 for left instead)
• Continuous clock output option to support CODECs which use it as a clock source
• Separate input and output data lines
• Option to invert idle state of WS (to indicate left or right)
The Word Select (WS), Data In (SDIN), Clock (SCK) and Data Out (SDOUT) lines are alternate functions of DIO
lines 12,13,17 and 18 respectively.
Data transfer is always bidirectional. Data placed in the Data Buffer before a transfer command is issued will be
transmitted on SDOUT whilst the data received on SDIN will be placed in the Data Buffer at the end of the transfer.
Indication that a transfer has completed is by means of an interrupt or by polling a status bit.
Left channel data is always sent first, with MSB first on each channel. The interface will always transfer both left and
right channel data. For mono data transfer, the user should pad out the unused channel with 0’s, and ignore any data
returned on the unused channel.
The length of a data transfer is derived as follows:
• When padding is disabled – Data Transfer Length = 2 x Data Transfer Size
• When padding is enabled – Data Transfer Length = 2 x (16 + Extra Pad Length)
Timing of the 3 main modes is shown in Figure 38, Figure 39 and Figure 40. The Data Buffer shows how the data is
stored and how it will be transferred onto the interface. SD Max Size indicates how the maximum transfer size (16
with no additional padding) will transfer, whilst SD 3-bits indicates how 3 bits of data will be aligned when padding is
enabled. Received data in the Data Buffer will always be padded out with 0’s if the Data Transfer Size is less than 16-
bits, and any bits received beyond 16-bits when extra padding is used, will be discarded. In the examples, the polarity
of WS is shown with Left channel = 0, and the idle state is Right Channel. 52 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
Data Buffer Right R2 R1 R0 Left L2 L1 L0
SCK
WS
SD Max Size
SD 3-bits
MSB LSB MSB LSB
Left Right
L2 L1 L0 0 R2 R1 R0
MSB-1 MSB-2 MSB-1 MSB-2
0 0 0
Figure 38: I²S Mode
Data Buffer Right R2 R1 R0 Left L2 L1 L0
SCK
WS
SD Max Size
SD 3-bits
MSB LSB MSB LSB
Left Right
L2 L1 L0 0 R2 R1 R0
MSB-1 MSB-2 MSB-1 MSB-2
0 0 0
Figure 39: Left Justified Mode
Data Buffer Right R2 R1 R0 Left L2 L1 L0
SCK
WS
SD Max Size
SD 3-bits
MSB LSB MSB LSB
Left Right
0 L2 L1 L0 R2 R1 R0
MSB-1 MSB-1
0 0 0
Figure 40: Right Justified Mode© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 53
17 Random Number Generator
A random number generator is provided which creates a 16-bit random number each time it is invoked. Consecutive
calls can be made to build up any length of random number required. Each call takes approximately 0.25msec to
complete. Alternatively, continuous generation mode can be used where a new number is generated approximately
every 0.25msec. In either mode of operation an interrupt can be generated to indicate when the number is available,
or a status bit can be polled.
The random bits are generated by sampling the state of the 32MHz clock every 32kHz system clock edge. As these
clocks are asynchronous to each other, each sampled bit is unpredictable and hence random.54 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
18 Sample FIFO
A 10 deep FIFO is provided to buffer data between the CPU and either the four-wire digital audio interface or the
DAC/ ADC. It supports single channel input and output data, up to 16 bits wide. When used it can reduce the rate at
which the processor has to generate/process data, and this may allow more efficient operation. Interrupts can be
generated based on fill levels and also FIFO empty and full conditions. Normal configuration of the digital audio
interface or the DAC/ ADC is still required when accessing the data via the FIFO.
When used with the DAC / ADC functions a timing signal is generated by the DAC/ ADC functions to control the
transfer of data to and from the FIFO and the analogue peripherals. The transfers will occur at the sample rate
configured within the DAC / ADC functions.
When the FIFO is linked to the four-wire digital audio interface, timer 2 must be used to generate an internal timing
signal to control the flow of data across the interface. The timer does not require any external pins to be enabled. The
timer should be set up to produce a PWM output with a rising edge generated every time a digital audio transfer is
required. The transfer rate is typically configured to be the audio sample rate, e.g. 8kHz. If the transfer rate is too fast
or slow data will be transferred correctly between the FIFO and the digital audio block.© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 55
19 Intelligent Peripheral Interface
The Intelligent Peripheral (IP) Interface is provided for systems that are more complex, where there is a processor
that requires a wireless peripheral. As an example, the JN5148 may provide a complete JenNet or ZigBee PRO
wireless network interface to a phone, computer, PDA, set-top box or games console. No resources are required from
the main processor compared to a transceiver as the complete wireless protocol may be run on the internal JN5148
CPU. The wireless peripheral may be controlled via one of the UARTs but the IP interface is intended to provide a
high-speed, low-processor-overhead interface.
The intelligent peripheral interface is a SPI slave interface and uses pins shared with other DIO signals. The
interface is designed to allow message passing and data transfer. Data received and transmitted on the IP interface
is copied directly to and from a dedicated area of memory without intervention from the CPU. This memory area, the
intelligent peripheral memory block, contains 64 32-bit word receive and transmit buffers.
JN5148
Intelligent
Peripheral
Interface SPI
MASTER
System Processor
(e.g. in cellphone, computer)
CPU
IP_DO SPIMISO
IP_INT SPIINT
IP_DI SPIMOSI
IP_SEL SPISEL
IP_CLK SPICLK
Figure 41: Intelligent Peripheral Connection
The interface functions as a SPI slave. It is possible to select the clock edge of IP_CLK on which data on the IP_DIN
line of the interface is sampled, and the state of data output IP_DOUT is changed. The order of transmission is MSB
first. The IP_DO data output is tri-stated when the device is inactive, i.e. the device is not selected via IP_SEL. An
interrupt output line IP_INT is available so that the JN5148 can indicate to an external master that it has data to
transfer. The interface can be clocked at up to 8MHz
The IP interface signals IP_CLK, IP_DO, IP_DI, IP_SEL, IP_INT are alternate functions of pins DIO14 to 18
respectively.
19.1 Data Transfer Format
Transfers are started by the remote processor asserting the IP_SEL line and terminated by the remote processor deasserting
IP_SEL.
Data transfers are bi-directional and traffic in both directions has a format of status byte, data length byte (of the
number of 32-bit words to transfer) and data packet (from the receive and transmit buffers), as shown in Figure 42
The first byte transferred into the JN5148 is a status byte with the format shown in Table 6. This is followed by a
padding byte that should be set to zero. The first byte output by the JN5148 is a padding byte, that should be ignored,
followed by a status byte with the format shown in Table 6
Bit Field Description
7:2 RSVD Reserved, set to 0
1 TXQ 1: Data queued for transmission
0 RXRDY 1: Buffer ready to receive data
Table 6: IP Status Byte Format56 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
If data is queued for transmission and the recipient has indicated that they are ready for it (RXRDY in incoming status
byte was 1), the next byte to be transmitted is the data length in words (N). If either the JN5148 or the remote
processor has no data to transfer, then the data length should be set to zero. The transaction can be terminated by
the master after the status and padding bytes have been sent if it is not possible to send data in either direction. This
may be because neither party has data to send or because the receiver does not have a buffer available. If the data
length is non-zero, the data in the JN5148 transmit memory buffer is sent, beginning at the start of the buffer. At the
same time that data bytes are being sent from the transmit buffer, the JN5148 receive buffer is being filled with
incoming data, beginning from the start of the buffer.
The remote processor, acting as the master, must determine the larger of its incoming or outgoing data transfers and
deassert IP_SEL when all of the transmit and receive data has been transferred. The data is transferred into or out of
the buffers starting from the lowest address in the buffer, and each word is assembled with the MSB first on the serial
data lines. Following a transaction, IP_SEL must be high (deasserted) for at least 400nsec before a further
transaction can begin.
IP_SEL
IP_CLK
IP_DI Status (8-bit) N words of data
IP_DO
data length or 0s (8-bit)
padding (8-bit) Status (8-bit) data length or 0s (8-bit) N words of data
padding (8-bit)
Figure 42: Intelligent Peripheral Data Transfer Waveforms
The N words of data transferred on the interface are also formatted. The first three bytes, of the first word, must be
zero. These are followed by a one byte length field that must be one less than the data length shown in the data
length field in Figure 42, i.e. N-1. Following this are the (N-1) words of data.
The application running on the JN5148 has high level software functions for sending and receiving data on this
interface. The function of generating and interpreting the individual bytes on the interface is handled by hardware
within the device. The remote processor must generate, and interpret, the signals in the interface. For instance, this
may be done with a configurable SPI master interface.
19.2 JN5148 (Slave) Initiated Data Transfer
To send data, the data is written into either buffer 0 or 1 of the intelligent peripheral memory area. Then the buffer
number is written together with the data length. If the call is successful, the interrupt line IP_INT will signal to the
remote processor that there is a message ready to be sent from the JN5148. When a remote processor starts a
transfer to the JN5148 by deasserting IP_SEL, then IP_INT is deasserted. If the transfer is unsuccessful and the
data is not output then IP_INT is reasserted after the transfer to indicate that data is still waiting to be sent.
The interface can be configured to generate an internal interrupt whenever a transaction completes (for example
IP_SEL becomes inactive after a transfer starts). It is also possible to mask the interrupt. The end of the
transmission can be signalled by an interrupt, or the interface can be polled.
To receive data the interface must be firstly initialised and when this is done, the bit RXRDY sent in the status byte
from the IP block will show that data can be received by the JN5148. Successful data arrival can be indicated by an
interrupt, or the interface can be polled. IP_INT is asserted if the JN5148 is configured to be able to receive, and the
remote processor has previously attempted to send data but the RXRDY indicated that it could not be sent.
To send and receive at the same time, the transmit and receive buffers must be set to be different.
19.3 Remote (Master) Processor Initiated Data Transfer
The remote processor (master) must initiate a transfer to send data to the JN5148 (slave) by asserting the slave
select pin, IP_SEL, and generating its status byte on IP_DI with TXRDY set. After receiving the status byte from the
JN5148, the master should check that the JN5148 has a buffer ready by reading the RXRDY bit of the received
status byte. If the RXRDY bit is 0 indicating that the JN5148 cannot accept data, it must terminate the transfer by
deasserting IP_SEL unless it is receiving data from the JN5148. If the RXRDY bit is 1, indicating that the JN5148 can
accept data, then the master should generate a further 8 clocks on IP_CLK in order to transfer its own message
length on IP_DI. The master must continue clocking the interface until sufficient clocks have been generated to send © NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 57
all the data specified in the length field to the JN5148. The master must then deassert IP_SEL to show the transfer
is complete.
The master may initiate a transfer to read data from the JN5148 by asserting the slave select pin, IP_SEL, and
generating its status byte on IP_DI with RXRDY set. After receiving the status byte from the JN5148, it should check
that the JN5148 has a buffer ready by reading the TXRDY bit of the received status byte. If the TXRDY bit is 0,
indicating that the JN5148 does not have data to send, it must terminate the transfer by deasserting IP_SEL unless it
is transmitting data to the JN5148. If the TXRDY bit is 1, indicating that the JN5148 can send data, then the master
must generate a further 8 clocks on IP_CLK in order to receive the message length on IP_DO. The master must
continue clocking the interface until sufficient clocks have been generated to receive all the data specified in the
length field from the JN5148. The master should then deassert IP_SEL to show the transfer is complete.
Data can be sent in both directions at once and the master must ensure both transfers have completed before
deasserting IP_SEL.58 JN-DS-JN5148-001 1v9 © NXP Laboratories UK 2013
20 Analogue Peripherals
The JN5148 contains a number of analogue peripherals allowing the direct connection of a wide range of external
sensors, switches and actuators.
ADC
DAC1
DAC2
VREF
Chip
Boundary
Internal Reference
Processor Bus
Supply Voltage
(VDD1)
Vref select
Temp
Sensor
Comparator 2
Comparator 1
COMP2M
COMP1M
COMP1P
COMP2P
DAC1
DAC2
ADC1
ADC2
ADC3
ADC4
Vref
Figure 43: Analogue Peripherals
In order to provide good isolation from digital noise, the analogue peripherals are powered by a separate regulator,
supplied from the analogue supply VDD1 and referenced to analogue ground VSSA.
A common reference Vref for the ADC and DAC can be selected between an internal bandgap reference or an
external voltage reference supplied to the VREF pin. Gain settings for the ADC and DAC are independent of each
other.
The ADC and DAC are clocked from a common clock source derived from the 16MHz clock© NXP Laboratories UK 2013 JN-DS-JN5148-001 1v9 59
20.1 Analogue to Digital Converter
The 12-bit analogue to digital converter (ADC) uses a successive approximation design to perform high accuracy
conversions as typically required in wireless sensor network applications. It has six multiplexed single-ended input
channels: four available externally, one connected to an internal temperature sensor, and one connected to an
internal supply monitoring circuit.
20.1.1 Operation
The input range of the ADC can be set between 0V to either the reference voltage or twice the reference voltage