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Farnell PDF
LPC1769/68/67/66/65/64/63 - NXP Semiconductors - Farnell Element 14
LPC1769/68/67/66/65/64/63 - NXP Semiconductors - Farnell Element 14
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Farnell Element 14 :
See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…
Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.
Puce électronique / Microchip :
Sans fil - Wireless :
Texas instrument :
Ordinateurs :
Logiciels :
Tutoriels :
Autres documentations :
![[TXT]](http://www.audentia-gestion.fr/icons/text.gif)
Analog-Devices-ADC-S..> 09-Sep-2014 08:21 2.4M
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1. General description
The LPC1769/68/67/66/65/64/63 are ARM Cortex-M3 based microcontrollers for
embedded applications featuring a high level of integration and low power consumption.
The ARM Cortex-M3 is a next generation core that offers system enhancements such as
enhanced debug features and a higher level of support block integration.
The LPC1768/67/66/65/64/63 operate at CPU frequencies of up to 100 MHz. The
LPC1769 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU
incorporates a 3-stage pipeline and uses a Harvard architecture with separate local
instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3
CPU also includes an internal prefetch unit that supports speculative branching.
The peripheral complement of the LPC1769/68/67/66/65/64/63 includes up to 512 kB of
flash memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG
interface, 8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP
controllers, SPI interface, 3 I2C-bus interfaces, 2-input plus 2-output I2S-bus interface,
8-channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface,
four general purpose timers, 6-output general purpose PWM, ultra-low power Real-Time
Clock (RTC) with separate battery supply, and up to 70 general purpose I/O pins.
The LPC1769/68/67/66/65/64/63 are pin-compatible to the 100-pin LPC236x
ARM7-based microcontroller series.
For additional documentation, see Section 19 “References”.
2. Features and benefits
ARM Cortex-M3 processor, running at frequencies of up to 100 MHz
(LPC1768/67/66/65/64/63) or of up to 120 MHz (LPC1769). A Memory Protection Unit
(MPU) supporting eight regions is included.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator
enables high-speed 120 MHz operation with zero wait states.
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
On-chip SRAM includes:
32/16 kB of SRAM on the CPU with local code/data bus for high-performance CPU
access.
LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and
64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN
Rev. 9.5 — 24 June 2014 Product data sheetLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 2 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
Two/one 16 kB SRAM blocks with separate access paths for higher throughput.
These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as
for general purpose CPU instruction and data storage.
Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer
matrix that can be used with SSP, I2S-bus, UART, Analog-to-Digital and
Digital-to-Analog converter peripherals, timer match signals, and for
memory-to-memory transfers.
Multilayer AHB matrix interconnect provides a separate bus for each AHB master.
AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, and
the USB interface. This interconnect provides communication with no arbitration
delays.
Split APB bus allows high throughput with few stalls between the CPU and DMA.
Serial interfaces:
Ethernet MAC with RMII interface and dedicated DMA controller. (Not available on
all parts, see Table 2.)
USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and
on-chip PHY for device, Host, and OTG functions. (Not available on all parts, see
Table 2.)
Four UARTs with fractional baud rate generation, internal FIFO, and DMA support.
One UART has modem control I/O and RS-485/EIA-485 support, and one UART
has IrDA support.
CAN 2.0B controller with two channels. (Not available on all parts, see Table 2.)
SPI controller with synchronous, serial, full duplex communication and
programmable data length.
Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces
can be used with the GPDMA controller.
Three enhanced I2C bus interfaces, one with an open-drain output supporting full
I
2C specification and Fast mode plus with data rates of 1 Mbit/s, two with standard
port pins. Enhancements include multiple address recognition and monitor mode.
I
2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate
control. The I2S-bus interface can be used with the GPDMA. The I2S-bus interface
supports 3-wire and 4-wire data transmit and receive as well as master clock
input/output. (Not available on all parts, see Table 2.)
Other peripherals:
70 (100 pin package) General Purpose I/O (GPIO) pins with configurable
pull-up/down resistors. All GPIOs support a new, configurable open-drain operating
mode. The GPIO block is accessed through the AHB multilayer bus for fast access
and located in memory such that it supports Cortex-M3 bit banding and use by the
General Purpose DMA Controller.
12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins,
conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can
be used with the GPDMA controller.
10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA
support. (Not available on all parts, see Table 2)
Four general purpose timers/counters, with a total of eight capture inputs and ten
compare outputs. Each timer block has an external count input. Specific timer
events can be selected to generate DMA requests.
One motor control PWM with support for three-phase motor control.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 3 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
Quadrature encoder interface that can monitor one external quadrature encoder.
One standard PWM/timer block with external count input.
RTC with a separate power domain and dedicated RTC oscillator. The RTC block
includes 20 bytes of battery-powered backup registers.
WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,
the RTC oscillator, or the APB clock.
ARM Cortex-M3 system tick timer, including an external clock input option.
Repetitive interrupt timer provides programmable and repeating timed interrupts.
Each peripheral has its own clock divider for further power savings.
Standard JTAG test/debug interface for compatibility with existing tools. Serial Wire
Debug and Serial Wire Trace Port options.
Emulation trace module enables non-intrusive, high-speed real-time tracing of
instruction execution.
Integrated PMU (Power Management Unit) automatically adjusts internal regulators to
minimize power consumption during Sleep, Deep sleep, Power-down, and Deep
power-down modes.
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.
Single 3.3 V power supply (2.4 V to 3.6 V).
Four external interrupt inputs configurable as edge/level sensitive. All pins on Port 0
and Port 2 can be used as edge sensitive interrupt sources.
Non-maskable Interrupt (NMI) input.
Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock,
CPU clock, and the USB clock.
The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up from
any priority interrupt that can occur while the clocks are stopped in deep sleep,
Power-down, and Deep power-down modes.
Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet
wake-up interrupt, CAN bus activity, Port 0/2 pin interrupt, and NMI).
Brownout detect with separate threshold for interrupt and forced reset.
Power-On Reset (POR).
Crystal oscillator with an operating range of 1 MHz to 25 MHz.
4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a
system clock.
PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the main oscillator, the internal RC oscillator,
or the RTC oscillator.
USB PLL for added flexibility.
Code Read Protection (CRP) with different security levels.
Unique device serial number for identification purposes.
Available as LQFP100 (14 mm 14 mm 1.4 mm), TFBGA1001 (9 mm 9 mm 0.7
mm), and WLCSP100 (5.074 5.074 0.6 mm) package.
1. LPC1768/65 only.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 4 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
3. Applications
4. Ordering information
4.1 Ordering options
eMetering Alarm systems
Lighting White goods
Industrial networking Motor control
Table 1. Ordering information
Type number Package
Name Description Version
LPC1769FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1
LPC1768FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1
LPC1768FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC1768UK WLCSP100 wafer level chip-scale package; 100 balls; 5.074 5.074 0.6 mm -
LPC1767FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1
LPC1766FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1
LPC1765FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1
LPC1765FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC1764FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1
LPC1763FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm SOT407-1
Table 2. Ordering options
Type number Flash SRAM in kB Ethernet USB CAN I
2S DAC Maximum
CPU
operating
frequency
CPU AHB
SRAM0
AHB
SRAM1
Total
LPC1769FBD100 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 120 MHz
LPC1768FBD100 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz
LPC1768FET100 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz
LPC1768UK 512 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz
LPC1767FBD100 512 kB 32 16 16 64 yes no no yes yes 100 MHz
LPC1766FBD100 256 kB 32 16 16 64 yes Device/Host/OTG 2 yes yes 100 MHz
LPC1765FBD100 256 kB 32 16 16 64 no Device/Host/OTG 2 yes yes 100 MHz
LPC1765FET100 256 kB 32 16 16 64 no Device/Host/OTG 2 yes yes 100 MHz
LPC1764FBD100 128 kB 16 16 - 32 yes Device only 2 no no 100 MHz
LPC1763FBD100 256 kB 32 16 16 64 no no no yes yes 100 MHzLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 5 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
5. Marking
The LPC176x devices typically have the following top-side marking:
LPC176xxxx
xxxxxxx
xxYYWWR[x]
The last/second to last letter in the third line (field ‘R’) will identify the device revision. This
data sheet covers the following revisions of the LPC176x:
Field ‘YY’ states the year the device was manufactured. Field ‘WW’ states the week the
device was manufactured during that year.
Table 3. Device revision table
Revision identifier (R) Revision description
‘-’ Initial device revision
‘A’ Second device revision
‘B’ Third device revisionLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 6 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
6. Block diagram
(1) Not available on all parts. See Table 2.
Fig 1. Block diagram
SRAM 32/64 kB
ARM
CORTEX-M3
TEST/DEBUG
INTERFACE
EMULATION
TRACE MODULE
FLASH
ACCELERATOR
FLASH
512/256/128 kB
DMA
CONTROLLER
ETHERNET
CONTROLLER
WITH DMA(1)
USB HOST/
DEVICE/OTG
CONTROLLER
WITH DMA(1)
I-code
bus
D-code
bus
system
bus
AHB TO
APB
BRIDGE 0
HIGH-SPEED
GPIO AHB TO
APB
BRIDGE 1
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
XTAL1
XTAL2
RESET
clocks and
controls
JTAG
interface
debug
port
USB PHY
SSP0
UART2/3
I2S(1)
I2C2
RI TIMER
TIMER2/3
EXTERNAL INTERRUPTS
SYSTEM CONTROL
MOTOR CONTROL PWM
QUADRATURE ENCODER
SSP1
UART0/1
CAN1/2(1)
I2C0/1
SPI0
TIMER 0/1
WDT
PWM1
12-bit ADC
PIN CONNECT
GPIO INTERRUPT CONTROL
RTC
BACKUP REGISTERS
32 kHz
OSCILLATOR
APB slave group 1 APB slave group 0
DAC(1)
RTC POWER DOMAIN
LPC1769/68/67/
66/65/64/63
master master master
002aad944
slave slave slave slave
slave
ROM
slave
MULTILAYER AHB MATRIX
P0 to
P4
SDA2
SCL2
SCK0
SSEL0
MISO0
MOSI0
SCK1
SSEL1
MISO1
MOSI1
RXD2/3
TXD2/3
PHA, PHB
INDEX
EINT[3:0]
AOUT
MCOA[2:0]
MCOB[2:0]
MCI[2:0]
MCABORT
4 × MAT2
2 × MAT3
2 × CAP2
2 × CAP3
3 × I2SRX
3 × I2STX
TX_MCLK
RX_MCLK
RTCX1
RTCX2
VBAT
PWM1[7:0]
2 × MAT0/1
2 × CAP0/1
RD1/2
TD1/2
SDA0/1
SCL0/1
AD0[7:0]
SCK/SSEL
MOSI/MISO
8 × UART1
RXD0/TXD0
P0, P2
PCAP1[1:0]
RMII pins USB pins
CLKOUT
MPU
= connected to DMALPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 7 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
7. Pinning information
7.1 Pinning
Fig 2. Pin configuration LQFP100 package
Fig 3. Pin configuration TFBGA100 package
LPC176xFBD100
50
1
25
75
51
26
76
100
002aad945
002aaf723
LPC1768/65FET100
Transparent top view
J
G
K
H
F
E
D
C
B
A
13579 2 4 6 8 10
ball A1
index areaLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 8 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
Fig 4. Pin configuration WLCSP100 package
Transparent top view
1
A
B
C
D
E
F
G
H
J
K
2 3 4 5 6 7 8 9 10
LPC1768UK
bump A1
index area
aaa-009522
Table 4. Pin allocation table TFBGA100
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
Row A
1 TDO/SWO 2 P0[3]/RXD0/AD0[6] 3 VDD(3V3) 4 P1[4]/ENET_TX_EN
5 P1[10]/ENET_RXD1 6 P1[16]/ENET_MDC 7 VDD(REG)(3V3) 8 P0[4]/I2SRX_CLK/
RD2/CAP2[0]
9 P0[7]/I2STX_CLK/
SCK1/MAT2[1]
10 P0[9]/I2STX_SDA/
MOSI1/MAT2[3]
11 - 12 -
Row B
1 TMS/SWDIO 2 RTCK 3 VSS 4 P1[1]/ENET_TXD1
5 P1[9]/ENET_RXD0 6 P1[17]/
ENET_MDIO
7 VSS 8 P0[6]/I2SRX_SDA/
SSEL1/MAT2[0]
9 P2[0]/PWM1[1]/TXD1 10 P2[1]/PWM1[2]/RXD1 11 - 12 -
Row C
1 TCK/SWDCLK 2 TRST 3 TDI 4 P0[2]/TXD0/AD0[7]
5 P1[8]/ENET_CRS 6 P1[15]/
ENET_REF_CLK
7 P4[28]/RX_MCLK/
MAT2[0]/TXD3
8 P0[8]/I2STX_WS/
MISO1/MAT2[2]
9 VSS 10 VDD(3V3) 11 - 12 -
Row D
1 P0[24]/AD0[1]/
I2SRX_WS/CAP3[1]
2 P0[25]/AD0[2]/
I2SRX_SDA/TXD3
3 P0[26]/AD0[3]/
AOUT/RXD3
4 n.c.
5 P1[0]/ENET_TXD0 6 P1[14]/ENET_RX_ER 7 P0[5]/I2SRX_WS/
TD2/CAP2[1]
8 P2[2]/PWM1[3]/
CTS1/TRACEDATA[3]
9 P2[4]/PWM1[5]/
DSR1/TRACEDATA[1]
10 P2[5]/PWM1[6]/
DTR1/TRACEDATA[0]
11 - 12 -
Row E
1 VSSA 2 VDDA 3 VREFP 4 n.c.
5 P0[23]/AD0[0]/
I2SRX_CLK/CAP3[0]
6 P4[29]/TX_MCLK/
MAT2[1]/RXD3
7 P2[3]/PWM1[4]/
DCD1/TRACEDATA[2]
8 P2[6]/PCAP1[0]/
RI1/TRACECLKLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 9 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
9 P2[7]/RD2/RTS1 10 P2[8]/TD2/TXD2 11 - 12 -
Row F
1 VREFN 2 RTCX1 3 RESET 4 P1[31]/SCK1/
AD0[5]
5 P1[21]/MCABORT/
PWM1[3]/SSEL0
6 P0[18]/DCD1/
MOSI0/MOSI
7 P2[9]/USB_CONNECT/
RXD2
8 P0[16]/RXD1/
SSEL0/SSEL
9 P0[17]/CTS1/
MISO0/MISO
10 P0[15]/TXD1/
SCK0/SCK
11 - 12 -
Row G
1 RTCX2 2 VBAT 3 XTAL2 4 P0[30]/USB_D
5 P1[25]/MCOA1/
MAT1[1]
6 P1[29]/MCOB2/
PCAP1[1]/MAT0[1]
7 VSS 8 P0[21]/RI1/RD1
9 P0[20]/DTR1/SCL1 10 P0[19]/DSR1/SDA1 11 - 12 -
Row H
1 P1[30]/VBUS/
AD0[4]
2 XTAL1 3 P3[25]/MAT0[0]/
PWM1[2]
4 P1[18]/USB_UP_LED/
PWM1[1]/CAP1[0]
5 P1[24]/MCI2/
PWM1[5]/MOSI0
6 VDD(REG)(3V3) 7 P0[10]/TXD2/
SDA2/MAT3[0]
8 P2[11]/EINT1/
I2STX_CLK
9 VDD(3V3) 10 P0[22]/RTS1/TD1 11 - 12 -
Table 4. Pin allocation table TFBGA100 …continued
Pin Symbol Pin Symbol Pin Symbol Pin SymbolLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 10 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
7.2 Pin description
Row J
1 P0[28]/SCL0/
USB_SCL
2 P0[27]/SDA0/
USB_SDA
3 P0[29]/USB_D+ 4 P1[19]/MCOA0/
USB_PPWR/
CAP1[1]
5 P1[22]/MCOB0/
USB_PWRD/
MAT1[0]
6 VSS 7 P1[28]/MCOA2/
PCAP1[0]/
MAT0[0]
8 P0[1]/TD1/RXD3/SCL1
9 P2[13]/EINT3/
I2STX_SDA
10 P2[10]/EINT0/NMI 11 - 12 -
Row K
1 P3[26]/STCLK/
MAT0[1]/PWM1[3]
2 VDD(3V3) 3 VSS 4 P1[20]/MCI0/
PWM1[2]/SCK0
5 P1[23]/MCI1/
PWM1[4]/MISO0
6 P1[26]/MCOB1/
PWM1[6]/CAP0[0]
7 P1[27]/CLKOUT
/USB_OVRCR/
CAP0[1]
8 P0[0]/RD1/TXD3/SDA1
9 P0[11]/RXD2/
SCL2/MAT3[1]
10 P2[12]/EINT2/
I2STX_WS
11 - 12 -
Table 4. Pin allocation table TFBGA100 …continued
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
Table 5. Pin description
Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100
P0[0] to P0[31] I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for
each bit. The operation of port 0 pins depends upon the pin function
selected via the pin connect block. Pins 12, 13, 14, and 31 of this
port are not available.
P0[0]/RD1/TXD3/
SDA1
46 K8 H10 [1] I/O P0[0] — General purpose digital input/output pin.
I RD1 — CAN1 receiver input. (LPC1769/68/66/65/64 only).
O TXD3 — Transmitter output for UART3.
I/O SDA1 — I
2C1 data input/output. (This is not an I2C-bus compliant
open-drain pin).
P0[1]/TD1/RXD3/
SCL1
47 J8 H9 [1] I/O P0[1] — General purpose digital input/output pin.
O TD1 — CAN1 transmitter output. (LPC1769/68/66/65/64 only).
I RXD3 — Receiver input for UART3.
I/O SCL1 — I
2C1 clock input/output. (This is not an I2C-bus compliant
open-drain pin).
P0[2]/TXD0/AD0[7] 98 C4 B1 [2] I/O P0[2] — General purpose digital input/output pin.
O TXD0 — Transmitter output for UART0.
I AD0[7] — A/D converter 0, input 7.
P0[3]/RXD0/AD0[6] 99 A2 C3 [2] I/O P0[3] — General purpose digital input/output pin.
I RXD0 — Receiver input for UART0.
I AD0[6] — A/D converter 0, input 6.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 11 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
P0[4]/
I2SRX_CLK/
RD2/CAP2[0]
81 A8 G2 [1] I/O P0[4] — General purpose digital input/output pin.
I/O I2SRX_CLK — Receive Clock. It is driven by the master and
received by the slave. Corresponds to the signal SCK in the I
2S-bus
specification. (LPC1769/68/67/66/65/63 only).
I RD2 — CAN2 receiver input. (LPC1769/68/66/65/64 only).
I CAP2[0] — Capture input for Timer 2, channel 0.
P0[5]/
I2SRX_WS/
TD2/CAP2[1]
80 D7 H1 [1] I/O P0[5] — General purpose digital input/output pin.
I/O I2SRX_WS — Receive Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I2S-bus
specification. (LPC1769/68/67/66/65/63 only).
O TD2 — CAN2 transmitter output. (LPC1769/68/66/65/64 only).
I CAP2[1] — Capture input for Timer 2, channel 1.
P0[6]/
I2SRX_SDA/
SSEL1/MAT2[0]
79 B8 G3 [1] I/O P0[6] — General purpose digital input/output pin.
I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read
by the receiver. Corresponds to the signal SD in the I2S-bus
specification. (LPC1769/68/67/66/65/63 only).
I/O SSEL1 — Slave Select for SSP1.
O MAT2[0] — Match output for Timer 2, channel 0.
P0[7]/
I2STX_CLK/
SCK1/MAT2[1]
78 A9 J1 [1] I/O P0[7] — General purpose digital input/output pin.
I/O I2STX_CLK — Transmit Clock. It is driven by the master and
received by the slave. Corresponds to the signal SCK in the I
2S-bus
specification. (LPC1769/68/67/66/65/63 only).
I/O SCK1 — Serial Clock for SSP1.
O MAT2[1] — Match output for Timer 2, channel 1.
P0[8]/
I2STX_WS/
MISO1/MAT2[2]
77 C8 H2 [1] I/O P0[8] — General purpose digital input/output pin.
I/O I2STX_WS — Transmit Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I
2S-bus
specification. (LPC1769/68/67/66/65/63 only).
I/O MISO1 — Master In Slave Out for SSP1.
O MAT2[2] — Match output for Timer 2, channel 2.
P0[9]/
I2STX_SDA/
MOSI1/MAT2[3]
76 A10 H3 [1] I/O P0[9] — General purpose digital input/output pin.
I/O I2STX_SDA — Transmit data. It is driven by the transmitter and
read by the receiver. Corresponds to the signal SD in the I
2S-bus
specification. (LPC1769/68/67/66/65/63 only).
I/O MOSI1 — Master Out Slave In for SSP1.
O MAT2[3] — Match output for Timer 2, channel 3.
P0[10]/TXD2/
SDA2/MAT3[0]
48 H7 H8 [1] I/O P0[10] — General purpose digital input/output pin.
O TXD2 — Transmitter output for UART2.
I/O SDA2 — I
2C2 data input/output (this is not an open-drain pin).
O MAT3[0] — Match output for Timer 3, channel 0.
Table 5. Pin description …continued
Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 12 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
P0[11]/RXD2/
SCL2/MAT3[1]
49 K9 J10 [1] I/O P0[11] — General purpose digital input/output pin.
I RXD2 — Receiver input for UART2.
I/O SCL2 — I
2C2 clock input/output (this is not an open-drain pin).
O MAT3[1] — Match output for Timer 3, channel 1.
P0[15]/TXD1/
SCK0/SCK
62 F10 H6 [1] I/O P0[15] — General purpose digital input/output pin.
O TXD1 — Transmitter output for UART1.
I/O SCK0 — Serial clock for SSP0.
I/O SCK — Serial clock for SPI.
P0[16]/RXD1/
SSEL0/SSEL
63 F8 J5 [1] I/O P0[16] — General purpose digital input/output pin.
I RXD1 — Receiver input for UART1.
I/O SSEL0 — Slave Select for SSP0.
I/O SSEL — Slave Select for SPI.
P0[17]/CTS1/
MISO0/MISO
61 F9 K6 [1] I/O P0[17] — General purpose digital input/output pin.
I CTS1 — Clear to Send input for UART1.
I/O MISO0 — Master In Slave Out for SSP0.
I/O MISO — Master In Slave Out for SPI.
P0[18]/DCD1/
MOSI0/MOSI
60 F6 J6 [1] I/O P0[18] — General purpose digital input/output pin.
I DCD1 — Data Carrier Detect input for UART1.
I/O MOSI0 — Master Out Slave In for SSP0.
I/O MOSI — Master Out Slave In for SPI.
P0[19]/DSR1/
SDA1
59 G10 K7 [1] I/O P0[19] — General purpose digital input/output pin.
I DSR1 — Data Set Ready input for UART1.
I/O SDA1 — I
2C1 data input/output (this is not an I2C-bus compliant
open-drain pin).
P0[20]/DTR1/SCL1 58 G9 J7 [1] I/O P0[20] — General purpose digital input/output pin.
O DTR1 — Data Terminal Ready output for UART1. Can also be
configured to be an RS-485/EIA-485 output enable signal.
I/O SCL1 — I
2C1 clock input/output (this is not an I2C-bus compliant
open-drain pin).
P0[21]/RI1/RD1 57 G8 H7 [1] I/O P0[21] — General purpose digital input/output pin.
I RI1 — Ring Indicator input for UART1.
I RD1 — CAN1 receiver input. (LPC1769/68/66/65/64 only).
P0[22]/RTS1/TD1 56 H10 K8 [1] I/O P0[22] — General purpose digital input/output pin.
O RTS1 — Request to Send output for UART1. Can also be
configured to be an RS-485/EIA-485 output enable signal.
O TD1 — CAN1 transmitter output. (LPC1769/68/66/65/64 only).
Table 5. Pin description …continued
Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 13 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
P0[23]/AD0[0]/
I2SRX_CLK/
CAP3[0]
9 E5 D5 [2] I/O P0[23] — General purpose digital input/output pin.
I AD0[0] — A/D converter 0, input 0.
I/O I2SRX_CLK — Receive Clock. It is driven by the master and
received by the slave. Corresponds to the signal SCK in the I
2S-bus
specification. (LPC1769/68/67/66/65/63 only).
I CAP3[0] — Capture input for Timer 3, channel 0.
P0[24]/AD0[1]/
I2SRX_WS/
CAP3[1]
8 D1 B4 [2] I/O P0[24] — General purpose digital input/output pin.
I AD0[1] — A/D converter 0, input 1.
I/O I2SRX_WS — Receive Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I
2S-bus
specification. (LPC1769/68/67/66/65/63 only).
I CAP3[1] — Capture input for Timer 3, channel 1.
P0[25]/AD0[2]/
I2SRX_SDA/
TXD3
7 D2 A3 [2] I/O P0[25] — General purpose digital input/output pin.
I AD0[2] — A/D converter 0, input 2.
I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read
by the receiver. Corresponds to the signal SD in the I
2S-bus
specification. (LPC1769/68/67/66/65/63 only).
O TXD3 — Transmitter output for UART3.
P0[26]/AD0[3]/
AOUT/RXD3
6 D3 C5 [3] I/O P0[26] — General purpose digital input/output pin.
I AD0[3] — A/D converter 0, input 3.
O AOUT — DAC output (LPC1769/68/67/66/65/63 only).
I RXD3 — Receiver input for UART3.
P0[27]/SDA0/
USB_SDA
25 J2 C8 [4] I/O P0[27] — General purpose digital input/output pin. Output is
open-drain.
I/O SDA0 — I
2C0 data input/output. Open-drain output (for I2C-bus
compliance).
I/O USB_SDA — USB port I2C serial data (OTG transceiver,
LPC1769/68/66/65 only).
P0[28]/SCL0/
USB_SCL
24 J1 B9 [4] I/O P0[28] — General purpose digital input/output pin. Output is
open-drain.
I/O SCL0 — I
2C0 clock input/output. Open-drain output (for I2C-bus
compliance).
I/O USB_SCL — USB port I2C serial clock (OTG transceiver,
LPC1769/68/66/65 only).
P0[29]/USB_D+ 29 J3 B10 [5] I/O P0[29] — General purpose digital input/output pin.
I/O USB_D+ — USB bidirectional D+ line. (LPC1769/68/66/65/64 only).
P0[30]/USB_D 30 G4 C9 [5] I/O P0[30] — General purpose digital input/output pin.
I/O USB_D — USB bidirectional D line. (LPC1769/68/66/65/64 only).
Table 5. Pin description …continued
Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 14 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
P1[0] to P1[31] I/O Port 1: Port 1 is a 32-bit I/O port with individual direction controls for
each bit. The operation of port 1 pins depends upon the pin function
selected via the pin connect block. Pins 2, 3, 5, 6, 7, 11, 12, and 13
of this port are not available.
P1[0]/
ENET_TXD0
95 D5 C1 [1] I/O P1[0] — General purpose digital input/output pin.
O ENET_TXD0 — Ethernet transmit data 0. (LPC1769/68/67/66/64
only).
P1[1]/
ENET_TXD1
94 B4 C2 [1] I/O P1[1] — General purpose digital input/output pin.
O ENET_TXD1 — Ethernet transmit data 1. (LPC1769/68/67/66/64
only).
P1[4]/
ENET_TX_EN
93 A4 D2 [1] I/O P1[4] — General purpose digital input/output pin.
O ENET_TX_EN — Ethernet transmit data enable.
(LPC1769/68/67/66/64 only).
P1[8]/
ENET_CRS
92 C5 D1 [1] I/O P1[8] — General purpose digital input/output pin.
I ENET_CRS — Ethernet carrier sense. (LPC1769/68/67/66/64 only).
P1[9]/
ENET_RXD0
91 B5 D3 [1] I/O P1[9] — General purpose digital input/output pin.
I ENET_RXD0 — Ethernet receive data. (LPC1769/68/67/66/64
only).
P1[10]/
ENET_RXD1
90 A5 E3 [1] I/O P1[10] — General purpose digital input/output pin.
I ENET_RXD1 — Ethernet receive data. (LPC1769/68/67/66/64
only).
P1[14]/
ENET_RX_ER
89 D6 E2 [1] I/O P1[14] — General purpose digital input/output pin.
I ENET_RX_ER — Ethernet receive error. (LPC1769/68/67/66/64
only).
P1[15]/
ENET_REF_CLK
88 C6 E1 [1] I/O P1[15] — General purpose digital input/output pin.
I ENET_REF_CLK — Ethernet reference clock.
(LPC1769/68/67/66/64 only).
P1[16]/
ENET_MDC
87 A6 F3 [1] I/O P1[16] — General purpose digital input/output pin.
O ENET_MDC — Ethernet MIIM clock (LPC1769/68/67/66/64 only).
P1[17]/
ENET_MDIO
86 B6 F2 [1] I/O P1[17] — General purpose digital input/output pin.
I/O ENET_MDIO — Ethernet MIIM data input and output.
(LPC1769/68/67/66/64 only).
Table 5. Pin description …continued
Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 15 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
P1[18]/
USB_UP_LED/
PWM1[1]/
CAP1[0]
32 H4 D9 [1] I/O P1[18] — General purpose digital input/output pin.
O USB_UP_LED — USB GoodLink LED indicator. It is LOW when the
device is configured (non-control endpoints enabled), or when the
host is enabled and has detected a device on the bus. It is HIGH
when the device is not configured, or when host is enabled and has
not detected a device on the bus, or during global suspend. It
transitions between LOW and HIGH (flashes) when the host is
enabled and detects activity on the bus. (LPC1769/68/66/65/64
only).
O PWM1[1] — Pulse Width Modulator 1, channel 1 output.
I CAP1[0] — Capture input for Timer 1, channel 0.
P1[19]/MCOA0/
USB_PPWR/
CAP1[1]
33 J4 C10 [1] I/O P1[19] — General purpose digital input/output pin.
O MCOA0 — Motor control PWM channel 0, output A.
O USB_PPWR — Port Power enable signal for USB port.
(LPC1769/68/66/65 only).
I CAP1[1] — Capture input for Timer 1, channel 1.
P1[20]/MCI0/
PWM1[2]/SCK0
34 K4 E8 [1] I/O P1[20] — General purpose digital input/output pin.
I MCI0 — Motor control PWM channel 0, input. Also Quadrature
Encoder Interface PHA input.
O PWM1[2] — Pulse Width Modulator 1, channel 2 output.
I/O SCK0 — Serial clock for SSP0.
P1[21]/MCABORT/
PWM1[3]/
SSEL0
35 F5 E9 [1] I/O P1[21] — General purpose digital input/output pin.
O MCABORT — Motor control PWM, LOW-active fast abort.
O PWM1[3] — Pulse Width Modulator 1, channel 3 output.
I/O SSEL0 — Slave Select for SSP0.
P1[22]/MCOB0/
USB_PWRD/
MAT1[0]
36 J5 D10 [1] I/O P1[22] — General purpose digital input/output pin.
O MCOB0 — Motor control PWM channel 0, output B.
I USB_PWRD — Power Status for USB port (host power switch,
LPC1769/68/66/65 only).
O MAT1[0] — Match output for Timer 1, channel 0.
P1[23]/MCI1/
PWM1[4]/MISO0
37 K5 E7 [1] I/O P1[23] — General purpose digital input/output pin.
I MCI1 — Motor control PWM channel 1, input. Also Quadrature
Encoder Interface PHB input.
O PWM1[4] — Pulse Width Modulator 1, channel 4 output.
I/O MISO0 — Master In Slave Out for SSP0.
P1[24]/MCI2/
PWM1[5]/MOSI0
38 H5 F8 [1] I/O P1[24] — General purpose digital input/output pin.
I MCI2 — Motor control PWM channel 2, input. Also Quadrature
Encoder Interface INDEX input.
O PWM1[5] — Pulse Width Modulator 1, channel 5 output.
I/O MOSI0 — Master Out Slave in for SSP0.
Table 5. Pin description …continued
Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 16 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
P1[25]/MCOA1/
MAT1[1]
39 G5 F9 [1] I/O P1[25] — General purpose digital input/output pin.
O MCOA1 — Motor control PWM channel 1, output A.
O MAT1[1] — Match output for Timer 1, channel 1.
P1[26]/MCOB1/
PWM1[6]/CAP0[0]
40 K6 E10 [1] I/O P1[26] — General purpose digital input/output pin.
O MCOB1 — Motor control PWM channel 1, output B.
O PWM1[6] — Pulse Width Modulator 1, channel 6 output.
I CAP0[0] — Capture input for Timer 0, channel 0.
P1[27]/CLKOUT
/USB_OVRCR/
CAP0[1]
43 K7 G9 [1] I/O P1[27] — General purpose digital input/output pin.
O CLKOUT — Clock output pin.
I USB_OVRCR — USB port Over-Current status. (LPC1769/68/66/65
only).
I CAP0[1] — Capture input for Timer 0, channel 1.
P1[28]/MCOA2/
PCAP1[0]/
MAT0[0]
44 J7 G10 [1] I/O P1[28] — General purpose digital input/output pin.
O MCOA2 — Motor control PWM channel 2, output A.
I PCAP1[0] — Capture input for PWM1, channel 0.
O MAT0[0] — Match output for Timer 0, channel 0.
P1[29]/MCOB2/
PCAP1[1]/
MAT0[1]
45 G6 G8 [1] I/O P1[29] — General purpose digital input/output pin.
O MCOB2 — Motor control PWM channel 2, output B.
I PCAP1[1] — Capture input for PWM1, channel 1.
O MAT0[1] — Match output for Timer 0, channel 1.
P1[30]/VBUS/
AD0[4]
21 H1 B8 [2] I/O P1[30] — General purpose digital input/output pin.
I VBUS — Monitors the presence of USB bus power.
(LPC1769/68/66/65/64 only).
Note: This signal must be HIGH for USB reset to occur.
I AD0[4] — A/D converter 0, input 4.
P1[31]/SCK1/
AD0[5]
20 F4 C7 [2] I/O P1[31] — General purpose digital input/output pin.
I/O SCK1 — Serial Clock for SSP1.
I AD0[5] — A/D converter 0, input 5.
P2[0] to P2[31] I/O Port 2: Port 2 is a 32-bit I/O port with individual direction controls for
each bit. The operation of port 2 pins depends upon the pin function
selected via the pin connect block. Pins 14 through 31 of this port
are not available.
P2[0]/PWM1[1]/
TXD1
75 B9 K1 [1] I/O P2[0] — General purpose digital input/output pin.
O PWM1[1] — Pulse Width Modulator 1, channel 1 output.
O TXD1 — Transmitter output for UART1.
P2[1]/PWM1[2]/
RXD1
74 B10 J2 [1] I/O P2[1] — General purpose digital input/output pin.
O PWM1[2] — Pulse Width Modulator 1, channel 2 output.
I RXD1 — Receiver input for UART1.
Table 5. Pin description …continued
Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 17 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
P2[2]/PWM1[3]/
CTS1/
TRACEDATA[3]
73 D8 K2 [1] I/O P2[2] — General purpose digital input/output pin.
O PWM1[3] — Pulse Width Modulator 1, channel 3 output.
I CTS1 — Clear to Send input for UART1.
O TRACEDATA[3] — Trace data, bit 3.
P2[3]/PWM1[4]/
DCD1/
TRACEDATA[2]
70 E7 K3 [1] I/O P2[3] — General purpose digital input/output pin.
O PWM1[4] — Pulse Width Modulator 1, channel 4 output.
I DCD1 — Data Carrier Detect input for UART1.
O TRACEDATA[2] — Trace data, bit 2.
P2[4]/PWM1[5]/
DSR1/
TRACEDATA[1]
69 D9 J3 [1] I/O P2[4] — General purpose digital input/output pin.
O PWM1[5] — Pulse Width Modulator 1, channel 5 output.
I DSR1 — Data Set Ready input for UART1.
O TRACEDATA[1] — Trace data, bit 1.
P2[5]/PWM1[6]/
DTR1/
TRACEDATA[0]
68 D10 H4 [1] I/O P2[5] — General purpose digital input/output pin.
O PWM1[6] — Pulse Width Modulator 1, channel 6 output.
O DTR1 — Data Terminal Ready output for UART1. Can also be
configured to be an RS-485/EIA-485 output enable signal.
O TRACEDATA[0] — Trace data, bit 0.
P2[6]/PCAP1[0]/
RI1/TRACECLK
67 E8 K4 [1] I/O P2[6] — General purpose digital input/output pin.
I PCAP1[0] — Capture input for PWM1, channel 0.
I RI1 — Ring Indicator input for UART1.
O TRACECLK — Trace Clock.
P2[7]/RD2/
RTS1
66 E9 J4 [1] I/O P2[7] — General purpose digital input/output pin.
I RD2 — CAN2 receiver input. (LPC1769/68/66/65/64 only).
O RTS1 — Request to Send output for UART1. Can also be
configured to be an RS-485/EIA-485 output enable signal.
P2[8]/TD2/
TXD2
65 E10 H5 [1] I/O P2[8] — General purpose digital input/output pin.
O TD2 — CAN2 transmitter output. (LPC1769/68/66/65/64 only).
O TXD2 — Transmitter output for UART2.
P2[9]/
USB_CONNECT/
RXD2
64 F7 K5 [1] I/O P2[9] — General purpose digital input/output pin.
O USB_CONNECT — Signal used to switch an external 1.5 k
resistor under software control. Used with the SoftConnect USB
feature. (LPC1769/68/66/65/64 only).
I RXD2 — Receiver input for UART2.
P2[10]/EINT0/NMI 53 J10 K9 [6] I/O P2[10] — General purpose digital input/output pin. A LOW level on
this pin during reset starts the ISP command handler.
I EINT0 — External interrupt 0 input.
I NMI — Non-maskable interrupt input.
Table 5. Pin description …continued
Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 18 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
P2[11]/EINT1/
I2STX_CLK
52 H8 J8 [6] I/O P2[11] — General purpose digital input/output pin.
I EINT1 — External interrupt 1 input.
I/O I2STX_CLK — Transmit Clock. It is driven by the master and
received by the slave. Corresponds to the signal SCK in the I
2S-bus
specification. (LPC1769/68/67/66/65/63 only).
P2[12]/EINT2/
I2STX_WS
51 K10 K10 [6] I/O P2[12] — General purpose digital input/output pin.
I EINT2 — External interrupt 2 input.
I/O I2STX_WS — Transmit Word Select. It is driven by the master and
received by the slave. Corresponds to the signal WS in the I
2S-bus
specification. (LPC1769/68/67/66/65/63 only).
P2[13]/EINT3/
I2STX_SDA
50 J9 J9 [6] I/O P2[13] — General purpose digital input/output pin.
I EINT3 — External interrupt 3 input.
I/O I2STX_SDA — Transmit data. It is driven by the transmitter and
read by the receiver. Corresponds to the signal SD in the I
2S-bus
specification. (LPC1769/68/67/66/65/63 only).
P3[0] to P3[31] I/O Port 3: Port 3 is a 32-bit I/O port with individual direction controls for
each bit. The operation of port 3 pins depends upon the pin function
selected via the pin connect block. Pins 0 through 24, and 27
through 31 of this port are not available.
P3[25]/MAT0[0]/
PWM1[2]
27 H3 D8 [1] I/O P3[25] — General purpose digital input/output pin.
O MAT0[0] — Match output for Timer 0, channel 0.
O PWM1[2] — Pulse Width Modulator 1, output 2.
P3[26]/STCLK/
MAT0[1]/PWM1[3]
26 K1 A10 [1] I/O P3[26] — General purpose digital input/output pin.
I STCLK — System tick timer clock input. The maximum STCLK
frequency is 1/4 of the ARM processor clock frequency CCLK.
O MAT0[1] — Match output for Timer 0, channel 1.
O PWM1[3] — Pulse Width Modulator 1, output 3.
P4[0] to P4[31] I/O Port 4: Port 4 is a 32-bit I/O port with individual direction controls for
each bit. The operation of port 4 pins depends upon the pin function
selected via the pin connect block. Pins 0 through 27, 30, and 31 of
this port are not available.
P4[28]/RX_MCLK/
MAT2[0]/TXD3
82 C7 G1 [1] I/O P4[28] — General purpose digital input/output pin.
O RX_MCLK — I
2S receive master clock. (LPC1769/68/67/66/65
only).
O MAT2[0] — Match output for Timer 2, channel 0.
O TXD3 — Transmitter output for UART3.
P4[29]/TX_MCLK/
MAT2[1]/RXD3
85 E6 F1 [1] I/O P4[29] — General purpose digital input/output pin.
O TX_MCLK — I
2S transmit master clock. (LPC1769/68/67/66/65
only).
O MAT2[1] — Match output for Timer 2, channel 1.
I RXD3 — Receiver input for UART3.
Table 5. Pin description …continued
Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 19 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
TDO/SWO 1 A1 A1 [1][7] O TDO — Test Data out for JTAG interface.
O SWO — Serial wire trace output.
TDI 2 C3 C4 [1][8] I TDI — Test Data in for JTAG interface.
TMS/SWDIO 3 B1 B3 [1][8] I TMS — Test Mode Select for JTAG interface.
I/O SWDIO — Serial wire debug data input/output.
TRST 4 C2 A2 [1][8] I TRST — Test Reset for JTAG interface.
TCK/SWDCLK 5 C1 D4 [1][7] I TCK — Test Clock for JTAG interface.
I SWDCLK — Serial wire clock.
RTCK 100 B2 B2 [1][7] O RTCK — JTAG interface control signal.
RSTOUT 14 - - - O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates the
microcontroller being in Reset state.
RESET 17 F3 C6 [9] I External reset input: A LOW-going pulse as short as 50 ns on this
pin resets the device, causing I/O ports and peripherals to take on
their default states, and processor execution to begin at address 0.
TTL with hysteresis, 5 V tolerant.
XTAL1 22 H2 D7 [10][11] I Input to the oscillator circuit and internal clock generator circuits.
XTAL2 23 G3 A9 [10][11] O Output from the oscillator amplifier.
RTCX1 16 F2 A7 [10][11] I Input to the RTC oscillator circuit.
RTCX2 18 G1 B7 [10] O Output from the RTC oscillator circuit.
VSS 31,
41,
55,
72,
83,
97
B3,
B7,
C9,
G7,
J6,
K3
E5,
F5,
F6,
G5,
G6,
G7
[10] I ground: 0 V reference.
VSSA 11 E1 B5 [10] I analog ground: 0 V reference. This should nominally be the same
voltage as VSS, but should be isolated to minimize noise and error.
VDD(3V3) 28,
54,
71,
96
K2,
H9,
C10
, A3
E4,
E6,
F7,
G4
[10] I 3.3 V supply voltage: This is the power supply voltage for the I/O
ports.
VDD(REG)(3V3) 42,
84
H6,
A7
F4,
F0
[10] I 3.3 V voltage regulator supply voltage: This is the supply voltage
for the on-chip voltage regulator only.
VDDA 10 E2 A4 [10] I analog 3.3 V pad supply voltage: This should be nominally the
same voltage as VDD(3V3) but should be isolated to minimize noise
and error. This voltage is used to power the ADC and DAC. This pin
should be tied to 3.3 V if the ADC and DAC are not used.
VREFP 12 E3 A5 [10] I ADC positive reference voltage: This should be nominally the
same voltage as VDDA but should be isolated to minimize noise and
error. Level on this pin is used as a reference for ADC and DAC.
This pin should be tied to 3.3 V if the ADC and DAC are not used.
Table 5. Pin description …continued
Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 20 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis. This pin is pulled up to a voltage level of 2.3 V to 2.6 V.
[2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input,
digital section of the pad is disabled and the pin is not 5 V tolerant. This pin is pulled up to a voltage level of 2.3 V to 2.6 V.
[3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output,
digital section of the pad is disabled. This pin is pulled up to a voltage level of 2.3 V to 2.6 V.
[4] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. This pad requires an external pull-up to provide
output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines.
Open-drain configuration applies to all functions on this pin.
[5] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and
Low-speed mode only). This pad is not 5 V tolerant.
[6] 5 V tolerant pad with 10 ns glitch filter providing digital I/O functions with TTL levels and hysteresis. This pin is pulled up to a voltage
level of 2.3 V to 2.6 V.
[7] 5 V tolerant pad with TTL levels and hysteresis. Internal pull-up and pull-down resistors disabled.
[8] 5 V tolerant pad with TTL levels and hysteresis and internal pull-up resistor.
[9] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.
[10] Pad provides special analog functionality. A 32 kHz crystal oscillator must be used with the RTC.
[11] When the system oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding
is preferred to reduce susceptibility to noise). XTAL2 should be left floating.
[12] When the RTC is not used, connect VBAT to VDD(REG)(3V3) and leave RTCX1 floating.
VREFN 15 F1 A6 I ADC negative reference voltage: This should be nominally the
same voltage as VSS but should be isolated to minimize noise and
error. Level on this pin is used as a reference for ADC and DAC.
VBAT 19 G2 A8 [10][12] I RTC pin power supply: 3.3 V on this pin supplies the power to the
RTC peripheral.
n.c. 13 D4,
E4
B6,
D6
- not connected.
Table 5. Pin description …continued
Symbol Pin/ball Type Description LQFP100 TFBGA100 WLCSP100LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 21 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
8. Functional description
8.1 Architectural overview
Remark: In the following, the notation LPC17xx refers to all parts:
LPC1769/68/67/66/65/64/63.
The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and
the D-code bus (see Figure 1). The I-code and D-code core buses are faster than the
system bus and are used similarly to TCM interfaces: one bus dedicated for instruction
fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for
simultaneous operations if concurrent operations target different devices.
The LPC17xx use a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and
other bus masters to peripherals in a flexible manner that optimizes performance by
allowing peripherals that are on different slaves ports of the matrix to be accessed
simultaneously by different bus masters.
8.2 ARM Cortex-M3 processor
The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM Cortex-M3 offers many new
features, including a Thumb-2 instruction set, low interrupt latency, hardware divide,
interruptible/continuable multiple load and store instructions, automatic state save and
restore for interrupts, tightly integrated interrupt controller with wake-up interrupt
controller, and multiple core buses capable of simultaneous accesses.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical
Reference Manual that can be found on official ARM website.
8.3 On-chip flash program memory
The LPC17xx contain up to 512 kB of on-chip flash memory. A new two-port flash
accelerator maximizes performance for use with the two fast AHB-Lite buses.
8.4 On-chip SRAM
The LPC17xx contain a total of 64 kB on-chip static RAM memory. This includes the main
32 kB SRAM, accessible by the CPU and DMA controller on a higher-speed bus, and two
additional 16 kB each SRAM blocks situated on a separate slave port on the AHB
multilayer matrix.
This architecture allows CPU and DMA accesses to be spread over three separate RAMs
that can be accessed simultaneously.
8.5 Memory Protection Unit (MPU)
The LPC17xx have a Memory Protection Unit (MPU) which can be used to improve the
reliability of an embedded system by protecting critical data within the user application.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 22 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
The MPU allows separating processing tasks by disallowing access to each other's data,
disabling access to memory regions, allowing memory regions to be defined as read-only
and detecting unexpected memory accesses that could potentially break the system.
The MPU separates the memory into distinct regions and implements protection by
preventing disallowed accesses. The MPU supports up to 8 regions each of which can be
divided into 8 subregions. Accesses to memory locations that are not defined in the MPU
regions, or not permitted by the region setting, will cause the Memory Management Fault
exception to take place.
8.6 Memory map
The LPC17xx incorporates several distinct memory regions, shown in the following
figures. Figure 5 shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.
The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals.
Each peripheral of either type is allocated 16 kB of space. This allows simplifying the
address decoding for each peripheral.xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
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LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 23 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller (1) Not available on all parts. See Table 2. Fig 5. LPC17xx memory map
0x5000 0000
0x5000 4000
0x5000 8000
0x5000 C000
0x5020 0000
0x5001 0000
AHB peripherals
Ethernet controller(1)
USB controller(1)
reserved
127- 4 reserved
GPDMA controller
0
1
2
3
APB0 peripherals
0x4000 4000
0x4000 8000
0x4000 C000
0x4001 0000
0x4001 8000
0x4002 0000
0x4002 8000
0x4002 C000
0x4003 4000
0x4003 0000
0x4003 8000
0x4003 C000
0x4004 0000
0x4004 4000
0x4004 8000
0x4004 C000
0x4005 C000
0x4006 0000
0x4008 0000
0x4002 4000
0x4001 C000
0x4001 4000
WDT 0x4000 0000
timer 0
timer 1
UART0
UART1
reserved
reserved
SPI
RTC + backup registers
GPIO interrupts
pin connect
SSP1
ADC
CAN AF RAM(1)
CAN AF registers(1)
CAN common(1)
CAN1(1)
CAN2(1)
22 - 19 reserved
I2C1
31 - 24 reserved
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
23
reserved
reserved
32 kB local SRAM (LPC1769/8/7/6/5/3)
16 kB local SRAM (LPC1764)
reserved
reserved
private peripheral bus
0 GB 0x0000 0000
0.5 GB
4 GB
1 GB
0x0004 0000
0x0002 0000
0x0008 0000
0x1000 4000
0x1000 0000
0x1000 8000
0x1FFF 0000
0x1FFF 2000
0x2008 0000
0x2007 C000
0x2008 4000
0x2200 0000
0x200A 0000
0x2009 C000
0x2400 0000
0x4000 0000
0x4008 0000
0x4010 0000
0x4200 0000
0x4400 0000
0x5000 0000
0x5020 0000
0xE000 0000
0xE010 0000
0xFFFF FFFF
reserved
reserved
GPIO
reserved
reserved
reserved
reserved
APB0 peripherals
AHB peripherals
APB1 peripherals
AHB SRAM bit-band alias addressing
peripheral bit-band alias addressing
16 kB AHB SRAM1 (LPC1769/8/7/6/5)
16 kB AHB SRAM0
256 kB on-chip flash (LPC1766/65/63)
128 kB on-chip flash (LPC1764)
512 kB on-chip flash (LPC1769/8/7)
PWM1
8 kB boot ROM
0x0000 0000
0x0000 0400
active interrupt vectors
+ 256 words
I-code/D-code
memory space
002aad946
APB1 peripherals
0x4008 0000
0x4008 8000
0x4008 C000
0x4009 0000
0x4009 4000
0x4009 8000
0x4009 C000
0x400A 0000
0x400A 4000
0x400A 8000
0x400A C000
0x400B 0000
0x400B 4000
0x400B 8000
0x400B C000
0x400C 0000
0x400F C000
0x4010 0000
SSP0
DAC(1)
timer 2
timer 3
UART2
UART3
reserved
I2S(1)
I2C2
1 - 0 reserved
2
3
4
5
6
7
8
9
10
reserved
repetitive interrupt timer
11
12
reserved
motor control PWM
30 - 16 reserved
13
14
15
31 system control
QEI
LPC1769/68/67/66/65/64/63LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 24 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
8.7 Nested Vectored Interrupt Controller (NVIC)
The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low
interrupt latency and efficient processing of late arriving interrupts.
8.7.1 Features
• Controls system exceptions and peripheral interrupts
• In the LPC17xx, the NVIC supports 33 vectored interrupts
• 32 programmable interrupt priority levels, with hardware priority level masking
• Relocatable vector table
• Non-Maskable Interrupt (NMI)
• Software interrupt generation
8.7.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
Any pin on Port 0 and Port 2 (total of 42 pins) regardless of the selected function, can be
programmed to generate an interrupt on a rising edge, a falling edge, or both.
8.8 Pin connect block
The pin connect block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
Most pins can also be configured as open-drain outputs or to have a pull-up, pull-down, or
no resistor enabled.
8.9 General purpose DMA controller
The GPDMA is an AMBA AHB compliant peripheral allowing selected peripherals to have
DMA support.
The GPDMA enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. The source and
destination areas can each be either a memory region or a peripheral, and can be
accessed through the AHB master. The GPDMA controller allows data transfers between
the USB and Ethernet controllers and the various on-chip SRAM areas. The supported
APB peripherals are SSP0/1, all UARTs, the I2S-bus interface, the ADC, and the DAC.
Two match signals for each timer can be used to trigger DMA transfers.
Remark: The Ethernet controller is available on parts LPC1769/68/67/66/64. The USB
controller is available on parts LPC1769/68/66/65/64. The I2S-bus interface is available on
parts LPC1769/68/67/66/65. The DAC is available on parts LPC1769/68/67/66/65/63.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 25 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
8.9.1 Features
• Eight DMA channels. Each channel can support an unidirectional transfer.
• 16 DMA request lines.
• Single DMA and burst DMA request signals. Each peripheral connected to the DMA
Controller can assert either a burst DMA request or a single DMA request. The DMA
burst size is set by programming the DMA Controller.
• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral transfers are supported.
• Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.
• Hardware DMA channel priority.
• AHB slave DMA programming interface. The DMA Controller is programmed by
writing to the DMA control registers over the AHB slave interface.
• One AHB bus master for transferring data. The interface transfers data when a DMA
request goes active.
• 32-bit AHB master bus width.
• Incrementing or non-incrementing addressing for source and destination.
• Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data.
• Internal four-word FIFO per channel.
• Supports 8, 16, and 32-bit wide transactions.
• Big-endian and little-endian support. The DMA Controller defaults to little-endian
mode on reset.
• An interrupt to the processor can be generated on a DMA completion or when a DMA
error has occurred.
• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read
prior to masking.
8.10 Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back as well as the current state of the port pins.
LPC17xx use accelerated GPIO functions:
• GPIO registers are accessed through the AHB multilayer bus so that the fastest
possible I/O timing can be achieved.
• Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
• All GPIO registers are byte and half-word addressable.
• Entire port value can be written in one instruction.
• Support for Cortex-M3 bit banding.
• Support for use with the GPDMA controller.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 26 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
Additionally, any pin on Port 0 and Port 2 (total of 42 pins) providing a digital function can
be programmed to generate an interrupt on a rising edge, a falling edge, or both. The
edge detection is asynchronous, so it may operate when clocks are not present such as
during Power-down mode. Each enabled interrupt can be used to wake up the chip from
Power-down mode.
8.10.1 Features
• Bit level set and clear registers allow a single instruction to set or clear any number of
bits in one port.
• Direction control of individual bits.
• All I/O default to inputs after reset.
• Pull-up/pull-down resistor configuration and open-drain configuration can be
programmed through the pin connect block for each GPIO pin.
8.11 Ethernet
Remark: The Ethernet controller is available on parts LPC1769/68/67/66/64. The
Ethernet block supports bus clock rates of up to 100 MHz (LPC1768/67/66/64) or 120
MHz (LPC1769). See Table 2.
The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC
designed to provide optimized performance through the use of DMA hardware
acceleration. Features include a generous suite of control registers, half or full duplex
operation, flow control, control frames, hardware acceleration for transmit retry, receive
packet filtering and wake-up on LAN activity. Automatic frame transmission and reception
with scatter-gather DMA off-loads many operations from the CPU.
The Ethernet block and the CPU share the ARM Cortex-M3 D-code and system bus
through the AHB-multilayer matrix to access the various on-chip SRAM blocks for
Ethernet data, control, and status information.
The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII
(RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial
bus.
8.11.1 Features
• Ethernet standards support:
– Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,
100 Base-FX, and 100 Base-T4.
– Fully compliant with IEEE standard 802.3.
– Fully compliant with 802.3x full duplex flow control and half duplex back pressure.
– Flexible transmit and receive frame options.
– Virtual Local Area Network (VLAN) frame support.
• Memory management:
– Independent transmit and receive buffers memory mapped to shared SRAM.
– DMA managers with scatter/gather DMA and arrays of frame descriptors.
– Memory traffic optimized by buffering and pre-fetching.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 27 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
• Enhanced Ethernet features:
– Receive filtering.
– Multicast and broadcast frame support for both transmit and receive.
– Optional automatic Frame Check Sequence (FCS) insertion with Cyclic
Redundancy Check (CRC) for transmit.
– Selectable automatic transmit frame padding.
– Over-length frame support for both transmit and receive allows any length frames.
– Promiscuous receive mode.
– Automatic collision back-off and frame retransmission.
– Includes power management by clock switching.
– Wake-on-LAN power management support allows system wake-up: using the
receive filters or a magic frame detection filter.
• Physical interface:
– Attachment of external PHY chip through standard RMII interface.
– PHY register access is available via the MIIM interface.
8.12 USB interface
Remark: The USB controller is available as device/Host/OTG controller on parts
LPC1769/68/66/65 and as device-only controller on part LPC1764.
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
The USB interface includes a device, Host, and OTG controller with on-chip PHY for
device and Host functions. The OTG switching protocol is supported through the use of an
external controller. Details on typical USB interfacing solutions can be found in
Section 15.1.
8.12.1 USB device controller
The device controller enables 12 Mbit/s data exchange with a USB Host controller. It
consists of a register interface, serial interface engine, endpoint buffer memory, and a
DMA controller. The serial interface engine decodes the USB data stream and writes data
to the appropriate endpoint buffer. The status of a completed USB transfer or error
condition is indicated via status registers. An interrupt is also generated if enabled. When
enabled, the DMA controller transfers data between the endpoint buffer and the on-chip
SRAM.
8.12.1.1 Features
• Fully compliant with USB 2.0 specification (full speed).
• Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM.
• Supports Control, Bulk, Interrupt and Isochronous endpoints.
• Scalable realization of endpoints at run time.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 28 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
• Endpoint Maximum packet size selection (up to USB maximum specification) by
software at run time.
• Supports SoftConnect and GoodLink features.
• While USB is in the Suspend mode, the part can enter one of the reduced power
modes and wake up on USB activity.
• Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints.
• Allows dynamic switching between CPU-controlled slave and DMA modes.
• Double buffer implementation for Bulk and Isochronous endpoints.
8.12.2 USB host controller
The host controller enables full- and low-speed data exchange with USB devices attached
to the bus. It consists of a register interface, a serial interface engine, and a DMA
controller. The register interface complies with the OHCI specification.
8.12.2.1 Features
• OHCI compliant.
• One downstream port.
• Supports port power switching.
8.12.3 USB OTG controller
USB OTG is a supplement to the USB 2.0 specification that augments the capability of
existing mobile devices and USB peripherals by adding host functionality for connection to
USB peripherals.
The OTG Controller integrates the host controller, device controller, and a master-only
I
2C-bus interface to implement OTG dual-role device functionality. The dedicated I2C-bus
interface controls an external OTG transceiver.
8.12.3.1 Features
• Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision
1.0a.
• Hardware support for Host Negotiation Protocol (HNP).
• Includes a programmable timer required for HNP and Session Request Protocol
(SRP).
• Supports any OTG transceiver compliant with the OTG Transceiver Specification
(CEA-2011), Rev. 1.0.
8.13 CAN controller and acceptance filters
Remark: The CAN controllers are available on parts LPC1769/68/66/65/64. See Table 2.
The Controller Area Network (CAN) is a serial communications protocol which efficiently
supports distributed real-time control with a very high level of security. Its domain of
application ranges from high-speed networks to low cost multiplex wiring.
The CAN block is intended to support multiple CAN buses simultaneously, allowing the
device to be used as a gateway, switch, or router among a number of CAN buses in
industrial or automotive applications.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 29 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
8.13.1 Features
• Two CAN controllers and buses.
• Data rates to 1 Mbit/s on each bus.
• 32-bit register and RAM access.
• Compatible with CAN specification 2.0B, ISO 11898-1.
• Global Acceptance Filter recognizes standard (11-bit) and extended-frame (29-bit)
receive identifiers for all CAN buses.
• Acceptance Filter can provide FullCAN-style automatic reception for selected
Standard Identifiers.
• FullCAN messages can generate interrupts.
8.14 12-bit ADC
The LPC17xx contain a single 12-bit successive approximation ADC with eight channels
and DMA support.
8.14.1 Features
• 12-bit successive approximation ADC.
• Input multiplexing among 8 pins.
• Power-down mode.
• Measurement range VREFN to VREFP.
• 12-bit conversion rate: 200 kHz.
• Individual channels can be selected for conversion.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition of input pin or Timer Match signal.
• Individual result registers for each ADC channel to reduce interrupt overhead.
• DMA support.
8.15 10-bit DAC
The DAC allows to generate a variable analog output. The maximum output value of the
DAC is VREFP.
Remark: The DAC is available on parts LPC1769/68/67/66/65/63. See Table 2.
8.15.1 Features
• 10-bit DAC
• Resistor string architecture
• Buffered output
• Power-down mode
• Selectable output drive
• Dedicated conversion timer
• DMA supportLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 30 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
8.16 UARTs
The LPC17xx each contain four UARTs. In addition to standard transmit and receive data
lines, UART1 also provides a full modem control handshake interface and support for
RS-485/9-bit mode allowing both software address detection and automatic address
detection using 9-bit mode.
The UARTs include a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
8.16.1 Features
• Maximum UART data bit rate of 6.25 Mbit/s.
• 16 B Receive and Transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
• Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• Auto baud capabilities and FIFO control mechanism that enables software flow
control implementation.
• UART1 equipped with standard modem interface signals. This module also provides
full support for hardware flow control (auto-CTS/RTS).
• Support for RS-485/9-bit/EIA-485 mode (UART1).
• UART3 includes an IrDA mode to support infrared communication.
• All UARTs have DMA support.
8.17 SPI serial I/O controller
The LPC17xx contain one SPI controller. SPI is a full duplex serial interface designed to
handle multiple masters and slaves connected to a given bus. Only a single master and a
single slave can communicate on the interface during a given data transfer. During a data
transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave
always sends 8 bits to 16 bits of data to the master.
8.17.1 Features
• Maximum SPI data bit rate of 12.5 Mbit/s
• Compliant with SPI specification
• Synchronous, serial, full duplex communication
• Combined SPI master and slave
• Maximum data bit rate of one eighth of the input clock rate
• 8 bits to 16 bits per transfer
8.18 SSP serial I/O controller
The LPC17xx contain two SSP controllers. The SSP controller is capable of operation on
a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the
bus. Only a single master and a single slave can communicate on the bus during a given LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 31 of 89
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32-bit ARM Cortex-M3 microcontroller
data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of
data flowing from the master to the slave and from the slave to the master. In practice,
often only one of these data flows carries meaningful data.
8.18.1 Features
• Maximum SSP speed of 33 Mbit/s (master) or 8 Mbit/s (slave)
• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
• Synchronous serial communication
• Master or slave operation
• 8-frame FIFOs for both transmit and receive
• 4-bit to 16-bit frame
• DMA transfers supported by GPDMA
8.19 I2C-bus serial I/O controllers
The LPC17xx each contain three I2C-bus controllers.
The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line
(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be
controlled by more than one bus master connected to it.
8.19.1 Features
• I
2C0 is a standard I2C compliant bus interface with open-drain pins. I2C0 also
supports Fast mode plus with bit rates up to 1 Mbit/s.
• I
2C1 and I2C2 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus).
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus can be used for test and diagnostic purposes.
• All I2C-bus controllers support multiple address recognition and a bus monitor mode.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 32 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
8.20 I2S-bus serial I/O controllers
Remark: The I2S-bus interface is available on parts LPC1769/68/67/66/65/63. See
Table 2.
The I2S-bus provides a standard communication interface for digital audio applications.
The I
2S-bus specification defines a 3-wire serial bus using one data line, one clock line,
and one word select signal. The basic I2S-bus connection has one master, which is
always the master, and one slave. The I2S-bus interface provides a separate transmit and
receive channel, each of which can operate as either a master or a slave.
8.20.1 Features
• The interface has separate input/output channels each of which can operate in master
or slave mode.
• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
• Mono and stereo audio data supported.
• The sampling frequency can range from 16 kHz to 96 kHz (16, 22.05, 32, 44.1, 48,
96) kHz.
• Support for an audio master clock.
• Configurable word select period in master mode (separately for I2S-bus input and
output).
• Two 8-word FIFO data buffers are provided, one for transmit and one for receive.
• Generates interrupt requests when buffer levels cross a programmable boundary.
• Two DMA requests, controlled by programmable buffer levels. These are connected
to the GPDMA block.
• Controls include reset, stop and mute options separately for I2S-bus input and I2S-bus
output.
8.21 General purpose 32-bit timers/external event counters
The LPC17xx include four 32-bit timer/counters. The timer/counter is designed to count
cycles of the system derived clock or an externally-supplied clock. It can optionally
generate interrupts, generate timed DMA requests, or perform other actions at specified
timer values, based on four match registers. Each timer/counter also includes two capture
inputs to trap the timer value when an input signal transitions, optionally generating an
interrupt.
8.21.1 Features
• A 32-bit timer/counter with a programmable 32-bit prescaler.
• Counter or timer operation.
• Two 32-bit capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event may also generate an interrupt.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 33 of 89
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32-bit ARM Cortex-M3 microcontroller
• Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
• Up to two match registers can be used to generate timed DMA requests.
8.22 Pulse width modulator
The PWM is based on the standard Timer block and inherits all of its features, although
only the PWM function is pinned out on the LPC17xx. The Timer is designed to count
cycles of the system derived clock and optionally switch pins, generate interrupts or
perform other actions when specified timer values occur, based on seven match registers.
The PWM function is in addition to these features, and is based on match register events.
The ability to separately control rising and falling edge locations allows the PWM to be
used for more applications. For instance, multi-phase motor control typically requires
three non-overlapping PWM outputs with individual control of all three pulse widths and
positions.
Two match registers can be used to provide a single edge controlled PWM output. One
match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon
match. The other match register controls the PWM edge position. Additional single edge
controlled PWM outputs require only one match register each, since the repetition rate is
the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a
rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs.
Three match registers can be used to provide a PWM output with both edges controlled.
Again, the PWMMR0 match register controls the PWM cycle rate. The other match
registers control the two PWM edge positions. Additional double edge controlled PWM
outputs require only two match registers each, since the repetition rate is the same for all
PWM outputs.
With double edge controlled PWM outputs, specific match registers control the rising and
falling edge of the output. This allows both positive going PWM pulses (when the rising
edge occurs prior to the falling edge), and negative going PWM pulses (when the falling
edge occurs prior to the rising edge).
8.22.1 Features
• One PWM block with Counter or Timer operation (may use the peripheral clock or one
of the capture inputs as the clock source).
• Seven match registers allow up to 6 single edge controlled or 3 double edge
controlled PWM outputs, or a mix of both types. The match registers also allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 34 of 89
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32-bit ARM Cortex-M3 microcontroller
• Supports single edge controlled and/or double edge controlled PWM outputs. Single
edge controlled PWM outputs all go high at the beginning of each cycle unless the
output is a constant low. Double edge controlled PWM outputs can have either edge
occur at any position within a cycle. This allows for both positive going and negative
going pulses.
• Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will
occur at the same repetition rate.
• Double edge controlled PWM outputs can be programmed to be either positive going
or negative going pulses.
• Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must ‘release’ new match values before they can become
effective.
• May be used as a standard 32-bit timer/counter with a programmable 32-bit prescaler
if the PWM mode is not enabled.
8.23 Motor control PWM
The motor control PWM is a specialized PWM supporting 3-phase motors and other
combinations. Feedback inputs are provided to automatically sense rotor position and use
that information to ramp speed up or down. An abort input is also provided that causes the
PWM to immediately release all motor drive outputs. At the same time, the motor control
PWM is highly configurable for other generalized timing, counting, capture, and compare
applications.
8.24 Quadrature Encoder Interface (QEI)
A quadrature encoder, also known as a 2-channel incremental encoder, converts angular
displacement into two pulse signals. By monitoring both the number of pulses and the
relative phase of the two signals, the user can track the position, direction of rotation, and
velocity. In addition, a third channel, or index signal, can be used to reset the position
counter. The quadrature encoder interface decodes the digital pulses from a quadrature
encoder wheel to integrate position over time and determine direction of rotation. In
addition, the QEI can capture the velocity of the encoder wheel.
8.24.1 Features
• Tracks encoder position.
• Increments/decrements depending on direction.
• Programmable for 2 or 4 position counting.
• Velocity capture using built-in timer.
• Velocity compare function with “less than” interrupt.
• Uses 32-bit registers for position and velocity.
• Three position compare registers with interrupts.
• Index counter for revolution counting.
• Index compare register with interrupts.
• Can combine index and position interrupts to produce an interrupt for whole and
partial revolution displacement.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 35 of 89
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32-bit ARM Cortex-M3 microcontroller
• Digital filter with programmable delays for encoder input signals.
• Can accept decoded signal inputs (clk and direction).
• Connected to APB.
8.25 Repetitive Interrupt (RI) timer
The repetitive interrupt timer provides a free-running 32-bit counter which is compared to
a selectable value, generating an interrupt when a match occurs. Any bits of the
timer/compare can be masked such that they do not contribute to the match detection.
The repetitive interrupt timer can be used to create an interrupt that repeats at
predetermined intervals.
8.25.1 Features
• 32-bit counter running from PCLK. Counter can be free-running or be reset by a
generated interrupt.
• 32-bit compare value.
• 32-bit compare mask. An interrupt is generated when the counter value equals the
compare value, after masking. This allows for combinations not possible with a simple
compare.
8.26 ARM Cortex-M3 system tick timer
The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a 10 ms interval. In the LPC17xx, this timer can be
clocked from the internal AHB clock or from a device pin.
8.27 Watchdog timer
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined
amount of time.
8.27.1 Features
• Internally resets chip if not periodically reloaded.
• Debug mode.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
• Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
• Flag to indicate watchdog reset.
• Programmable 32-bit timer with internal prescaler.
• Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 232 4) in
multiples of Tcy(WDCLK) 4.
• The Watchdog Clock (WDCLK) source can be selected from the Internal RC (IRC)
oscillator, the RTC oscillator, or the APB peripheral clock. This gives a wide range of
potential timing choices of Watchdog operation under different power reduction LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 36 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
conditions. It also provides the ability to run the WDT from an entirely internal source
that is not dependent on an external crystal and its associated components and wiring
for increased reliability.
• Includes lock/safe feature.
8.28 RTC and backup registers
The RTC is a set of counters for measuring time when system power is on, and optionally
when it is off. The RTC on the LPC17xx is designed to have extremely low power
consumption, i.e. less than 1 A. The RTC will typically run from the main chip power
supply, conserving battery power while the rest of the device is powered up. When
operating from a battery, the RTC will continue working down to 2.1 V. Battery power can
be provided from a standard 3 V Lithium button cell.
An ultra-low power 32 kHz oscillator will provide a 1 Hz clock to the time counting portion
of the RTC, moving most of the power consumption out of the time counting function.
The RTC includes a calibration mechanism to allow fine-tuning the count rate in a way
that will provide less than 1 second per day error when operated at a constant voltage and
temperature. A clock output function (see Section 8.29.4) makes measuring the oscillator
rate easy and accurate.
The RTC contains a small set of backup registers (20 bytes) for holding data while the
main part of the LPC17xx is powered off.
The RTC includes an alarm function that can wake up the LPC17xx from all reduced
power modes with a time resolution of 1 s.
8.28.1 Features
• Measures the passage of time to maintain a calendar and clock.
• Ultra low power design to support battery powered systems.
• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and
Day of Year.
• Dedicated power supply pin can be connected to a battery or to the main 3.3 V.
• Periodic interrupts can be generated from increments of any field of the time registers.
• Backup registers (20 bytes) powered by VBAT.
• RTC power supply is isolated from the rest of the chip.
8.29 Clocking and power control
8.29.1 Crystal oscillators
The LPC17xx include three independent oscillators. These are the main oscillator, the IRC
oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose
as required in a particular application. Any of the three clock sources can be chosen by
software to drive the main PLL and ultimately the CPU.
Following reset, the LPC17xx will operate from the Internal RC oscillator until switched by
software. This allows systems to operate without any external crystal and the bootloader
code to operate at a known frequency. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 37 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
See Figure 6 for an overview of the LPC17xx clock generation.
8.29.1.1 Internal RC oscillator
The IRC may be used as the clock source for the WDT, and/or as the clock that drives the
PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is
trimmed to 1 % accuracy over the entire voltage and temperature range.
Upon power-up or any chip reset, the LPC17xx use the IRC as the clock source. Software
may later switch to one of the other available clock sources.
8.29.1.2 Main oscillator
The main oscillator can be used as the clock source for the CPU, with or without using the
PLL. The main oscillator also provides the clock source for the dedicated USB PLL.
The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the main
PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock
frequency is referred to as CCLK elsewhere in this document. The frequencies of
PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The
clock frequency for each peripheral can be selected individually and is referred to as
PCLK. Refer to Section 8.29.2 for additional information.
8.29.1.3 RTC oscillator
The RTC oscillator can be used as the clock source for the RTC block, the main PLL,
and/or the CPU.
Fig 6. LPC17xx clocking generation block diagram
MAIN
OSCILLATOR
INTERNAL
RC
OSCILLATOR
RTC
OSCILLATOR
MAIN PLL
WATCHDOG
TIMER
REAL-TIME
CLOCK
CPU
CLOCK
DIVIDER
PERIPHERAL
CLOCK
GENERATOR
USB BLOCK
ARM
CORTEX-M3
ETHERNET
BLOCK
DMA
GPIO
NVIC
USB
CLOCK
DIVIDER
system
clock
select
(CLKSRCSEL)
USB clock config
(USBCLKCFG)
CPU clock config
(CCLKCFG)
pllclk
CCLK/8
CCLK/6
CCLK/4
CCLK/2
CCLK
pclkWDT
rtclk = 1Hz
usbclk
(48 MHz)
cclk
USB PLL
USB PLL enable
main PLL enable
32 kHz
APB peripherals
LPC17xx
002aad947LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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32-bit ARM Cortex-M3 microcontroller
8.29.2 Main PLL (PLL0)
The PLL0 accepts an input clock frequency in the range of 32 kHz to 25 MHz. The input
frequency is multiplied up to a high frequency, then divided down to provide the actual
clock used by the CPU and/or the USB block.
The PLL0 input, in the range of 32 kHz to 25 MHz, may initially be divided down by a
value ‘N’, which may be in the range of 1 to 256. This input division provides a wide range
of output frequencies from the same input frequency.
Following the PLL0 input divider is the PLL0 multiplier. This can multiply the input divider
output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the
range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to
550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a
phase-frequency detector to compare the divided CCO output to the multiplier input. The
error value is used to adjust the CCO frequency.
The PLL0 is turned off and bypassed following a chip Reset and by entering Power-down
mode. PLL0 is enabled by software only. The program must configure and activate the
PLL0, wait for the PLL0 to lock, and then connect to the PLL0 as a clock source.
8.29.3 USB PLL (PLL1)
The LPC17xx contain a second, dedicated USB PLL1 to provide clocking for the USB
interface.
The PLL1 receives its clock input from the main oscillator only and provides a fixed
48 MHz clock to the USB block only. The PLL1 is disabled and powered off on reset. If the
PLL1 is left disabled, the USB clock will be supplied by the 48 MHz clock from the main
PLL0.
The PLL1 accepts an input clock frequency in the range of 10 MHz to 25 MHz only. The
input frequency is multiplied up the range of 48 MHz for the USB clock using a Current
Controlled Oscillators (CCO). It is insured that the PLL1 output has a 50 % duty cycle.
8.29.4 RTC clock output
The LPC17xx feature a clock output function intended for synchronizing with external
devices and for use during system development to allow checking the internal clocks
CCLK, IRC clock, main crystal, RTC clock, and USB clock in the outside world. The RTC
clock output allows tuning the RTC frequency without probing the pin, which would distort
the results.
8.29.5 Wake-up timer
The LPC17xx begin operation at power-up and when awakened from Power-down mode
by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to
resume quickly. If the main oscillator or the PLL is needed by the application, software will
need to enable these features and wait for them to stabilize before they are used as a
clock source.
When the main oscillator is initially activated, the wake-up timer allows software to ensure
that the main oscillator is fully functional before the processor uses it as a clock source
and starts to execute instructions. This is important at power on, all types of Reset, and LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 39 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
whenever any of the aforementioned functions are turned off for any reason. Since the
oscillator and other functions are turned off during Power-down mode, any wake-up of the
processor from Power-down mode makes use of the wake-up timer.
The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin
code execution. When power is applied to the chip, or when some event caused the chip
to exit Power-down mode, some time is required for the oscillator to produce a signal of
sufficient amplitude to drive the clock logic. The amount of time depends on many factors,
including the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its
electrical characteristics (if a quartz crystal is used), as well as any other external circuitry
(e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient
conditions.
8.29.6 Power control
The LPC17xx support a variety of power control features. There are four special modes of
processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and
Deep power-down mode. The CPU clock rate may also be controlled as needed by
changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider
value. This allows a trade-off of power versus processing speed based on application
requirements. In addition, Peripheral Power Control allows shutting down the clocks to
individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all
dynamic power use in any peripherals that are not required for the application. Each of the
peripherals has its own clock divider which provides even better power control.
Integrated PMU (Power Management Unit) automatically adjust internal regulators to
minimize power consumption during Sleep, Deep sleep, Power-down, and Deep
power-down modes.
The LPC17xx also implement a separate power domain to allow turning off power to the
bulk of the device while maintaining operation of the RTC and a small set of registers for
storing data during any of the power-down modes.
8.29.6.1 Sleep mode
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a Reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
8.29.6.2 Deep-sleep mode
In Deep-sleep mode, the oscillator is shut down and the chip receives no internal clocks.
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Deep-sleep mode and the logic levels of chip pins remain static.
The output of the IRC is disabled but the IRC is not powered down for a fast wake-up later.
The RTC oscillator is not stopped because the RTC interrupts may be used as the
wake-up source. The PLL is automatically turned off and disconnected. The CCLK and
USB clock dividers automatically get reset to zero.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 40 of 89
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32-bit ARM Cortex-M3 microcontroller
The Deep-sleep mode can be terminated and normal operation resumed by either a
Reset or certain specific interrupts that are able to function without clocks. Since all
dynamic operation of the chip is suspended, Deep-sleep mode reduces chip power
consumption to a very low value. Power to the flash memory is left on in Deep-sleep
mode, allowing a very quick wake-up.
On wake-up from Deep-sleep mode, the code execution and peripherals activities will
resume after 4 cycles expire if the IRC was used before entering Deep-sleep mode. If the
main external oscillator was used, the code execution will resume when 4096 cycles
expire. PLL and clock dividers need to be reconfigured accordingly.
8.29.6.3 Power-down mode
Power-down mode does everything that Deep-sleep mode does, but also turns off the
power to the IRC oscillator and the flash memory. This saves more power but requires
waiting for resumption of flash operation before execution of code or data access in the
flash memory can be accomplished.
On the wake-up of Power-down mode, if the IRC was used before entering Power-down
mode, it will take IRC 60 s to start-up. After this 4 IRC cycles will expire before the code
execution can then be resumed if the code was running from SRAM. In the meantime, the
flash wake-up timer then counts 4 MHz IRC clock cycles to make the 100 s flash start-up
time. When it times out, access to the flash will be allowed. Users need to reconfigure the
PLL and clock dividers accordingly.
8.29.6.4 Deep power-down mode
The Deep power-down mode can only be entered from the RTC block. In Deep
power-down mode, power is shut off to the entire chip with the exception of the RTC
module and the RESET pin.
The LPC17xx can wake up from Deep power-down mode via the RESET pin or an alarm
match event of the RTC.
8.29.6.5 Wake-up interrupt controller
The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up from
any enabled priority interrupt that can occur while the clocks are stopped in Deep sleep,
Power-down, and Deep power-down modes.
The WIC works in connection with the Nested Vectored Interrupt Controller (NVIC). When
the CPU enters Deep sleep, Power-down, or Deep power-down mode, the NVIC sends a
mask of the current interrupt situation to the WIC.This mask includes all of the interrupts
that are both enabled and of sufficient priority to be serviced immediately. With this
information, the WIC simply notices when one of the interrupts has occurred and then it
wakes up the CPU.
The WIC eliminates the need to periodically wake up the CPU and poll the interrupts
resulting in additional power savings.
8.29.7 Peripheral power control
A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 41 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
8.29.8 Power domains
The LPC17xx provide two independent power domains that allow the bulk of the device to
have power removed while maintaining operation of the RTC and the backup Registers.
On the LPC17xx, I/O pads are powered by the 3.3 V (VDD(3V3)) pins, while the
VDD(REG)(3V3) pin powers the on-chip voltage regulator which in turn provides power to the
CPU and most of the peripherals.
Depending on the LPC17xx application, a design can use two power options to manage
power consumption.
The first option assumes that power consumption is not a concern and the design ties the
VDD(3V3) and VDD(REG)(3V3) pins together. This approach requires only one 3.3 V power
supply for both pads, the CPU, and peripherals. While this solution is simple, it does not
support powering down the I/O pad ring “on the fly” while keeping the CPU and
peripherals alive.
The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and
a dedicated 3.3 V supply for the CPU (VDD(REG)(3V3)). Having the on-chip voltage regulator
powered independently from the I/O pad ring enables shutting down of the I/O pad power
supply “on the fly”, while the CPU and peripherals stay active.
The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of
power to operate, which can be supplied by an external battery. The device core power
(VDD(REG)(3V3)) is used to operate the RTC whenever VDD(REG)(3V3) is present. Therefore,
there is no power drain from the RTC battery when VDD(REG)(3V3) is available. LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 42 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
8.30 System control
8.30.1 Reset
Reset has four sources on the LPC17xx: the RESET pin, the Watchdog reset, power-on
reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt
trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains
a usable level, causes the RSTOUT pin to go LOW and starts the wake-up timer (see
description in Section 8.29.5). The wake-up timer ensures that reset remains asserted
until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks
have passed, and the flash controller has completed its initialization. Once reset is
de-asserted, or, in case of a BOD-triggered reset, once the voltage rises above the BOD
threshold, the RSTOUT pin goes HIGH.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the Boot Block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
Fig 7. Power distribution
REAL-TIME CLOCK
BACKUP REGISTERS
REGULATOR
32 kHz
OSCILLATOR
RTC POWER DOMAIN
MAIN POWER DOMAIN
002aad978
RTCX1
VBAT
VDD(REG)(3V3)
RTCX2
VDD(3V3)
VSS
to memories,
peripherals,
oscillators,
PLLs
to core
to I/O pads
ADC
DAC
ADC POWER DOMAIN
VDDA
VREFP
VREFN
VSSA
LPC17xx
ULTRA LOW-POWER
REGULATOR
POWER
SELECTORLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 43 of 89
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32-bit ARM Cortex-M3 microcontroller
8.30.2 Brownout detection
The LPC17xx include 2-stage monitoring of the voltage on the VDD(REG)(3V3) pins. If this
voltage falls below 2.2 V, the BOD asserts an interrupt signal to the Vectored Interrupt
Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the
NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading
a dedicated status register.
The second stage of low-voltage detection asserts reset to inactivate the LPC17xx when
the voltage on the VDD(REG)(3V3) pins falls below 1.85 V. This reset prevents alteration of
the flash as operation of the various elements of the chip would otherwise become
unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at
which point the power-on reset circuitry maintains the overall reset.
Both the 2.2 V and 1.85 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.2 V detection to reliably interrupt, or a regularly executed event
loop to sense the condition.
8.30.3 Code security (Code Read Protection - CRP)
This feature of the LPC17xx allows user to enable different levels of security in the system
so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When
needed, CRP is invoked by programming a specific pattern into a dedicated flash location.
IAP commands are not affected by the CRP.
There are three levels of the Code Read Protection.
CRP1 disables access to chip via the JTAG and allows partial flash update (excluding
flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is
required and flash field updates are needed but all sectors can not be erased.
CRP2 disables access to chip via the JTAG and only allows full flash erase and update
using a reduced set of the ISP commands.
Running an application with level CRP3 selected fully disables any access to chip via the
JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too.
It is up to the user’s application to provide (if needed) flash update mechanism using IAP
calls or call reinvoke ISP command to enable flash update via UART0.
8.30.4 APB interface
The APB peripherals are split into two separate APB buses in order to distribute the bus
bandwidth and thereby reducing stalls caused by contention between the CPU and the
GPDMA controller.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 44 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
8.30.5 AHB multilayer matrix
The LPC17xx use an AHB multilayer matrix. This matrix connects the instruction (I-code)
and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the main
(32 kB) static RAM, and the Boot ROM. The GPDMA can also access all of these
memories. The peripheral DMA controllers, Ethernet, and USB can access all SRAM
blocks. Additionally, the matrix connects the CPU system bus and all of the DMA
controllers to the various peripheral functions.
8.30.6 External interrupt inputs
The LPC17xx include up to 46 edge sensitive interrupt inputs combined with up to four
level sensitive external interrupt inputs as selectable pin functions. The external interrupt
inputs can optionally be used to wake up the processor from Power-down mode.
8.30.7 Memory mapping control
The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table
to alternate locations in the memory map. This is controlled via the Vector Table Offset
Register contained in the NVIC.
The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address
space. The vector table must be located on a 128 word (512 byte) boundary because the
NVIC on the LPC17xx is configured for 128 total interrupts.
8.31 Emulation and debugging
Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and
trace functions are supported in addition to a standard JTAG debug and parallel trace
functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four
watch points.LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 45 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
9. Limiting values
[1] The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
c) The limiting values are stress ratings only. Operating the part at these values is not recommended, and proper operation is not
guaranteed. The conditions for functional operation are specified in Table 8.
[2] Maximum/minimum voltage above the maximum operating voltage (see Table 8) and below ground that can be applied for a short time
(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.
[3] See Table 19 for maximum operating voltage.
[4] Including voltage on outputs in 3-state mode.
[5] VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down.
[6] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined
based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details.
[7] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol Parameter Conditions Min Max Unit
VDD(3V3) supply voltage (3.3 V) external rail [2] 0.5 +4.6 V
VDD(REG)(3V3) regulator supply voltage (3.3 V) [2] 0.5 +4.6 V
VDDA analog 3.3 V pad supply
voltage
[2] 0.5 +4.6 V
Vi(VBAT) input voltage on pin VBAT for the RTC [2] 0.5 +4.6 V
Vi(VREFP) input voltage on pin VREFP [2] 0.5 +4.6 V
VIA analog input voltage on ADC related pins [2][3] 0.5 +5.1 V
VI input voltage 5 V tolerant digital I/O pins;
VDD 2.4 V
[2][4] 0.5 +5.5 VI
VDD = 0 V 0.5 +3.6
5 V tolerant open-drain pins
PIO0_27 and PIO0_28
[2][5] 0.5 +5.5
IDD supply current per supply pin - 100 mA
ISS ground current per ground pin - 100 mA
Ilatch I/O latch-up current (0.5VDD(3V3)) < VI <
(1.5VDD(3V3)); Tj
< 125 C
- 100 mA
Tstg storage temperature [6] 65 +150 C
Tj(max) maximum junction temperature 150 C
Ptot(pack) total power dissipation (per
package)
based on package heat
transfer, not device power
consumption
- 1.5 W
VESD electrostatic discharge voltage human body model; all pins [7] 4000 +4000 VLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 46 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
10. Thermal characteristics
The average chip junction temperature, Tj (C), can be calculated using the following
equation:
(1)
• Tamb = ambient temperature (C)
• Rth(j-a) = the package junction-to-ambient thermal resistance (C/W)
• PD = sum of internal and I/O power dissipation
The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of
the I/O pins is often small and many times can be negligible. However it can be significant
in some applications.
Table 7. Thermal resistance (15 %)
Symbol Parameter Conditions Max/Min Unit
LQFP100
Rth(j-a) thermal resistance from
junction to ambient
JEDEC (4.5 in 4 in); still air 38.01 C/W
Single-layer (4.5 in 3 in); still air 55.09 C/W
Rth(j-c) thermal resistance from
junction to case
9.065 C/W
TFBGA100
Rth(j-a) thermal resistance from
junction to ambient
JEDEC (4.5 in 4 in); still air 55.2 C/W
Single-layer (4.5 in 3 in); still air 45.6 C/W
Rth(j-c) thermal resistance from
junction to case
9.5 C/W
Tj Tamb PD Rth j a – += LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 47 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
11. Static characteristics
Table 8. Static characteristics
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
Supply pins
VDD(3V3) supply voltage (3.3 V) external rail [2] 2.4 3.3 3.6 V
VDD(REG)(3V3) regulator supply voltage
(3.3 V)
2.4 3.3 3.6 V
VDDA analog 3.3 V pad supply
voltage
[3][4] 2.5 3.3 3.6 V
Vi(VBAT) input voltage on pin
VBAT
[5] 2.1 3.3 3.6 V
Vi(VREFP) input voltage on pin
VREFP
[3] 2.5 3.3 VDDA V
IDD(REG)(3V3) regulator supply current
(3.3 V)
active mode; code
while(1){}
executed from flash; all
peripherals disabled;
PCLK = CCLK⁄
8
CCLK = 12 MHz; PLL
disabled
[6][7] - 7- mA
CCLK = 100 MHz; PLL
enabled
[6][7] - 42- mA
CCLK = 100 MHz; PLL
enabled (LPC1769)
[6][8] - 50- mA
CCLK = 120 MHz; PLL
enabled (LPC1769)
[6][8] - 67- mA
sleep mode [6][9] - 2- mA
deep sleep mode [6][10] - 240 - A
power-down mode [6][10] - 31 - A
deep power-down mode;
RTC running
[11] - 630- nA
IBAT battery supply current deep power-down mode;
RTC running
VDD(REG)(3V3) present [12] - 530- nA
VDD(REG)(3V3) not
present
[13] -
1.1 - A
IDD(IO) I/O supply current deep sleep mode [14][15] - 40- nA
power-down mode [14][15] - 40- nA
deep power-down mode [14] - 10- nALPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 48 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
IDD(ADC) ADC supply current active mode;
ADC powered
[16][17] - 1.95- mA
ADC in Power-down
mode
[16][18] - <0.2 - A
deep sleep mode [16] - 38- nA
power-down mode [16] - 38- nA
deep power-down mode [16] - 24- nA
II(ADC) ADC input current on pin VREFP
deep sleep mode [19] - 100- nA
power-down mode [19] - 100- nA
deep power-down
mode
[19] - 100- nA
Standard port pins, RESET, RTCK
IIL LOW-level input current VI = 0 V; on-chip pull-up
resistor disabled
- 0.5 10 nA
IIH HIGH-level input
current
VI = VDD(3V3); on-chip
pull-down resistor
disabled
- 0.5 10 nA
IOZ OFF-state output
current
VO = 0 V; VO = VDD(3V3);
on-chip pull-up/down
resistors disabled
- 0.5 10 nA
VI input voltage pin configured to provide
a digital function
[20][21]
[22]
0- 5.0 V
VO output voltage output active 0 - VDD(3V3) V
VIH HIGH-level input
voltage
0.7VDD(3V3) --V
VIL LOW-level input voltage - - 0.3VDD(3V3) V
Vhys hysteresis voltage 0.4 - - V
VOH HIGH-level output
voltage
IOH = 4 mA VDD(3V3)
0.4
--V
VOL LOW-level output
voltage
IOL = 4 mA --0.4 V
IOH HIGH-level output
current
VOH = VDD(3V3) 0.4 V 4 - - mA
IOL LOW-level output
current
VOL = 0.4 V 4- - mA
IOHS HIGH-level short-circuit
output current
VOH =0V [23] - - 45 mA
IOLS LOW-level short-circuit
output current
VOL = VDD(3V3) [23] --50 mA
Ipd pull-down current VI =5V 10 50 150 A
Ipu pull-up current VI =0V 15 50 85 A
VDD(3V3) < VI <5V 0 0 0 A
Table 8. Static characteristics …continued
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max UnitLPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.5 — 24 June 2014 49 of 89
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
[2] For USB operation 3.0 V VDD((3V3) 3.6 V. Guaranteed by design.
[3] VDDA and VREFP should be tied to VDD(3V3) if the ADC and DAC are not used.
[4] VDDA for DAC specs are from 2.7 V to 3.6 V.
I
2C-bus pins (P0[27] and P0[28])
VIH HIGH-level input
voltage
0.7VDD(3V3) --V
VIL LOW-level input voltage - - 0.3VDD(3V3) V
Vhys hysteresis voltage - 0.05
VDD(3V3)
- V
VOL LOW-level output
voltage
IOLS = 3 mA --0.4 V
ILI input leakage current VI = VDD(3V3) [24] - 24 A
VI =5V - 10 22 A
Oscillator pins
Vi(XTAL1) input voltage on pin
XTAL1
0.5 1.8 1.95 V
Vo(XTAL2) output voltage on pin
XTAL2
0.5 1.8 1.95 V
Vi(RTCX1) input voltage on pin
RTCX1
0.5 - 3.6 V
Vo(RTCX2) output voltage on pin
RTCX2
0.5 - 3.6 V
USB pins (LPC1769/68/66/65/64 only)
IOZ OFF-state output
current
0V>
NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
23. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 4
4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4
5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6
7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 7
7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10
8 Functional description . . . . . . . . . . . . . . . . . . 21
8.1 Architectural overview . . . . . . . . . . . . . . . . . . 21
8.2 ARM Cortex-M3 processor . . . . . . . . . . . . . . . 21
8.3 On-chip flash program memory . . . . . . . . . . . 21
8.4 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 21
8.5 Memory Protection Unit (MPU). . . . . . . . . . . . 21
8.6 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.7 Nested Vectored Interrupt Controller (NVIC) . 24
8.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.7.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 24
8.8 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 24
8.9 General purpose DMA controller . . . . . . . . . . 24
8.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8.10 Fast general purpose parallel I/O . . . . . . . . . . 25
8.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.11 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.12 USB interface . . . . . . . . . . . . . . . . . . . . . . . . 27
8.12.1 USB device controller . . . . . . . . . . . . . . . . . . . 27
8.12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.12.2 USB host controller . . . . . . . . . . . . . . . . . . . . 28
8.12.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.12.3 USB OTG controller . . . . . . . . . . . . . . . . . . . . 28
8.12.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.13 CAN controller and acceptance filters . . . . . . 28
8.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.14 12-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.15 10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.16 UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.17 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 30
8.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.18 SSP serial I/O controller . . . . . . . . . . . . . . . . . 30
8.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.19 I2C-bus serial I/O controllers . . . . . . . . . . . . . 31
8.19.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.20 I2S-bus serial I/O controllers . . . . . . . . . . . . . 32
8.20.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.21 General purpose 32-bit timers/external event
counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.21.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.22 Pulse width modulator . . . . . . . . . . . . . . . . . . 33
8.22.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.23 Motor control PWM . . . . . . . . . . . . . . . . . . . . 34
8.24 Quadrature Encoder Interface (QEI) . . . . . . . 34
8.24.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.25 Repetitive Interrupt (RI) timer. . . . . . . . . . . . . 35
8.25.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.26 ARM Cortex-M3 system tick timer . . . . . . . . . 35
8.27 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 35
8.27.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.28 RTC and backup registers . . . . . . . . . . . . . . . 36
8.28.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.29 Clocking and power control . . . . . . . . . . . . . . 36
8.29.1 Crystal oscillators. . . . . . . . . . . . . . . . . . . . . . 36
8.29.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 37
8.29.1.2 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 37
8.29.1.3 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 37
8.29.2 Main PLL (PLL0) . . . . . . . . . . . . . . . . . . . . . . 38
8.29.3 USB PLL (PLL1) . . . . . . . . . . . . . . . . . . . . . . 38
8.29.4 RTC clock output . . . . . . . . . . . . . . . . . . . . . . 38
8.29.5 Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 38
8.29.6 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.29.6.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.29.6.2 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 39
8.29.6.3 Power-down mode . . . . . . . . . . . . . . . . . . . . . 40
8.29.6.4 Deep power-down mode . . . . . . . . . . . . . . . . 40
8.29.6.5 Wake-up interrupt controller . . . . . . . . . . . . . 40
8.29.7 Peripheral power control . . . . . . . . . . . . . . . . 40
8.29.8 Power domains . . . . . . . . . . . . . . . . . . . . . . . 41
8.30 System control . . . . . . . . . . . . . . . . . . . . . . . . 42
8.30.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.30.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 43
8.30.3 Code security (Code Read Protection - CRP) 43
8.30.4 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.30.5 AHB multilayer matrix . . . . . . . . . . . . . . . . . . 44
8.30.6 External interrupt inputs . . . . . . . . . . . . . . . . . 44
8.30.7 Memory mapping control . . . . . . . . . . . . . . . . 44
8.31 Emulation and debugging . . . . . . . . . . . . . . . 44
9 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 45
10 Thermal characteristics . . . . . . . . . . . . . . . . . 46NXP Semiconductors LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
© NXP Semiconductors N.V. 2014. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 24 June 2014
Document identifier: LPC1769_68_67_66_65_64_63
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
11 Static characteristics. . . . . . . . . . . . . . . . . . . . 47
11.1 Power consumption . . . . . . . . . . . . . . . . . . . . 50
11.2 Peripheral power consumption . . . . . . . . . . . . 53
11.3 Electrical pin characteristics . . . . . . . . . . . . . . 54
12 Dynamic characteristics . . . . . . . . . . . . . . . . . 56
12.1 Flash memory. . . . . . . . . . . . . . . . . . . . . . . . . 56
12.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.3 Internal oscillators. . . . . . . . . . . . . . . . . . . . . . 57
12.4 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.5 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
12.6 I2S-bus interface . . . . . . . . . . . . . . . . . . . . . . 59
12.7 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 61
12.8 USB interface . . . . . . . . . . . . . . . . . . . . . . . . 63
12.9 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
13 ADC electrical characteristics . . . . . . . . . . . . 66
14 DAC electrical characteristics . . . . . . . . . . . . 69
15 Application information. . . . . . . . . . . . . . . . . . 70
15.1 Suggested USB interface solutions . . . . . . . . 70
15.2 Crystal oscillator XTAL input and component
selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
15.3 XTAL and RTCX Printed Circuit Board (PCB)
layout guidelines. . . . . . . . . . . . . . . . . . . . . . . 74
15.4 Standard I/O pin configuration . . . . . . . . . . . . 75
15.5 Reset pin configuration. . . . . . . . . . . . . . . . . . 76
15.6 ElectroMagnetic Compatibility (EMC). . . . . . . 77
16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 78
17 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
18 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 83
19 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
20 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 84
21 Legal information. . . . . . . . . . . . . . . . . . . . . . . 86
21.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 86
21.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
21.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
21.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 87
22 Contact information. . . . . . . . . . . . . . . . . . . . . 87
23 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
1. General description
NXP’s UCODE G2iM series transponder ICs offers in addition to the leading-edge read
range features such as a Tag Tamper Alarm, Data Transfer, Digital Switch, advanced
privacy-protection modes and a 640 bit configurable User Memory.
Very high chip sensitivity (17.5 dBm) enables longer read ranges with simple, single-port
antenna designs. In fashion and retail the UCODE G2iM series improve read rates and
provide for theft deterrence. In the electronic device market, they are ideally suited for
device configuration, activation, production control and PCB tagging. In authentication
applications, they protect brands and guard against counterfeiting. They can also be used
to tag containers, electronic vehicles, airline baggage, and more.
In addition to the EPC specifications the UCODE G2iM offers an integrated Product Status
Flag (PSF) feature and read protection of the memory content.
The UCODE G2iM+ offers on top of the UCODE G2iM features an integrated tag tamper
alarm, digital switch, external supply mode, data transfer mode and real read range
reduction. A special feature is the conditional, automatic real read range reduction, where
the activation condition can be defined by the user, is newly introduced in the UCODE
G2iM+. When connected to a power supply, the READ as well as the WRITE range can
be boosted to a sensitivity of 27 dBm.
The UCODE G2iM+ also allows the segmentation of the 640 bit User Memory in up to
three segments (open, protected, private) with different access levels (Access- and User
Password). For applications which require a longer EPC number the UCODE G2iM+
offers the possibility of up to 448 bit.
2. Features and benefits
2.1 Key features
UHF RFID Gen2 tag chip according EPCglobal v1.2.0
256 bit EPC for UCODE G2iM and up to 448 bit EPC for UCODE G2iM+
Up to 640 bit User Memory which can be segmented in the UCODE G2iM+
Private User Memory area protected by special User Password
Memory read protection
Integrated Product Status Flag (PSF)
Tag tamper alarm
Digital switch
Data transfer mode
SL3S1003_1013
UCODE G2iM and G2iM+
Rev. 3.6 — 17 October 2014
201236
Product data sheet
COMPANY PUBLICSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 17 October 2014
201236 2 of 43
NXP Semiconductors SL3S1003_1013
UCODE G2iM and G2iM+
Real Read Range Reduction (Privacy Mode)
Conditional Real Read Range Reduction
External supply mode
Long read/write ranges due to extremely low power design
Reliable operation of multiple tags due to advanced anti-collision
Broad international operating frequency: from 840 MHz to 960 MHz
Data retention: 20 years
Wide specified temperature range: 40 C up to +85 C
2.1.1 Memory
256 bit of EPC memory / up to 448 bit in G2iM+
96 bit Tag IDentifier (TID) including 48-bit factory locked unique serial number
112 bit User TID memory
32 bit Kill Password to permanently disable the tag
32 bit Access Password to allow a transition into the secured state
32 bit User Password to allow access to the private user memory segment
Read protection
BlockWrite (32 bit)
Write Lock
BlockPermalock
2.2 Key benefits
2.2.1 End user benefit
Outstanding User Memory size of 640 bit
Prevention of unauthorized memory access through different levels of read protection
Indication of tag tampering attempt by use of the tag tamper alarm feature
Electronic device configuration and / or activation by the use of the digital switch / data
transfer mode
Theft deterrence supported by the PSF feature (PSF alarm or EPC code)
Small label sizes, long read ranges due to high chip sensitivity
Product identification through unalterable TID range, including a 48 bit serial number
Reliable operation in dense reader and noisy environments through high interference
suppression
2.2.2 Antenna design benefits
High sensitivity enables small and cost efficient antenna designs
Low Q-Value eases broad band antenna design for global usage
2.2.3 Label manufacturer benefit
Consistent performance on different materials due to low Q-factor
Ease of assembly and high assembly yields through large chip input capacitance and
Polyimide spacer
Fast first WRITE or BLOCKWRITE of the EPC memory for fast label initializationSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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2.3 Custom commands
PSF Alarm
Built-in PSF (Product Status Flag), enables the UHF RFID tag to be used as EAS tag
(Electronic Article Surveillance) tag without the need for a back-end data base.
Read Protect
Protects all memory content from unauthorized reading.
ChangeConfig
Configures the additional features of the chip like external supply mode, tamper alarm,
digital switch, read range reduction, privacy mode activation condition or data transfer.
The UCODE G2iM+ is equipped with a number of additional features. Nevertheless, the
chip is designed in a way standard EPCglobal READ/WRITE/ACCESS commands can be
used to operate the features. No custom commands are needed to take advantage of all
the features in case of unlocked EPC memory.
3. Applications
3.1 Markets
Fashion (apparel and footwear)
Retail
Electronics
Fast moving consumer goods
Asset management
Electronic vehicle identification
3.2 Applications
Supply chain management
Item level tagging
Pallet and case tracking
Container identification
Product authentication
PCB tagging
Cost efficient, low level seals
Wireless firmware download
Wireless product activationSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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4. Ordering information
5. Marking
Table 1. Ordering information
Type number Package
Name IC type Description Version
SL3S1003FUD/BG Wafer G2iM bumped G2iM die on sawn 8” 120 mm wafer,
7 mm Polyimide spacer
not applicable
SL3S1013FUD/BG Wafer G2iM+ bumped G2iM+ die on sawn 8” 120 mm wafer,
7 mm Polyimide spacer
not applicable
SL3S1013FTB0 XSON6 G2iM+ plastic extremely thin small outline package;
no leads; 6 terminals; body 1 1.45 0.5 mm
SOT886F1
Table 2. Marking codes
Type number Marking code Comment Version
SL3S1013FTB0 US UCODE G2iM+ SOT886SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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6. Block diagram
The SL3S10x3 IC consists of three major blocks:
- Analog Interface
- Digital Control
- EEPROM
The analog part provides stable supply voltage and demodulates data received from the
reader for being processed by the digital part. Further, the modulation transistor of the
analog part transmits data back to the reader.
The digital section includes the state machines, processes the protocol and handles
communication with the EEPROM, which contains the EPC and the user data.
Fig 1. Block diagram of SL3S10x3 IC
001aam226
MOD
DEMOD
VREG
VDD
VDD
data
in
data
out
R/W
ANALOG
RF INTERFACE
PAD
PAD
RECT
DIGITAL CONTROL
ANTENNA
ANTICOLLISION
READ/WRITE
CONTROL
ACCESS CONTROL
EEPROM INTERFACE
CONTROL
RF INTERFACE
CONTROL
I/O CONTROL
I/O
CONTROL
EEPROM
MEMORY
SEQUENCER
CHARGE PUMP
PAD
OUT
PADSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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NXP Semiconductors SL3S1003_1013
UCODE G2iM and G2iM+
7. Pinning information
7.1 Pin description
Fig 2. Pinning bare die Fig 3. Pin configuration for SOT886
001aan572
VDD
OUT RFN
RFP
NXP trademark
SL3S10x3FTB0
n.c.
aaa-001689
RFP
RFN
n.c.
VDD
OUT
Transparent top view
2
3
1
5
4
6
Table 3. Pin description bare die
Symbol Description
OUT output pin
RFN grounded antenna connector
VDD external supply
RFP ungrounded antenna connector
Table 4. Pin description SOT886
Pin Symbol Description
1 RFP ungrounded antenna connector
2 n.c. not connected
3 RFN grounded antenna connector
4 OUT output pin
5 n.c. not connected
6 VDD external supplySL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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8. Wafer layout
8.1 Wafer layout
(1) Die to Die distance (metal sealring - metal sealring) 21,4 m, (X-scribe line width: 15 m)
(2) Die to Die distance (metal sealring - metal sealring) 21,4 m, (Y-scribe line width: 15 m)
(3) Chip step, x-length: 615 m
(4) Chip step, y-length: 475 m
(5) Bump to bump distance X (OUT - RFN): 513 m
(6) Bump to bump distance Y (RFN - RFP): 333 m
(7) Distance bump to metal sealring X: 43,5 m (outer edge - top metal)
(8) Distance bump to metal sealring (RFP, VDD) Y: 40,3 m
(9) Distance bump to metal sealring (RFN, OUT) Y: 80,3 m
Bump size X Y: 60 m ´ 60 m
Remark: OUT and VDD are used with G2iM+ only
Fig 4. SL3S10x3 wafer layout
not to scale! 001aan642
(1)
(7)
(2)
(8)
(5)
(6)
(4)
(3)
Y
X
VDD
(9)
OUT
RFN
RFPSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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9. Mechanical specification
The SL3S10x3 wafers are offered with 120 mm thickness and 7mm Polyimide spacer.
This robust structure with the enhanced Polyimide spacer supports easy assembly due to
low assembly variations.
9.1 Wafer specification
See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on
UV-tape with electronic fail die marking, BU-ID document number: 1093**”.
9.1.1 Wafer
Table 5. Specifications
Wafer
Designation each wafer is scribed with batch number and
wafer number
Diameter 200 mm (8”)
Thickness 120 m 15 m
Number of pads 4
Pad location non diagonal/ placed in chip corners
Distance pad to pad RFN-RFP 333.0 µm
Distance pad to pad OUT-RFN 513.0 µm
Process CMOS 0.14 mm
Batch size 25 wafers
Potential good dies per wafer 100544
Wafer backside
Material Si
Treatment ground and stress release
Roughness Ra max. 0.5 m, Rt max. 5 m
Chip dimensions
Die size including scribe 0.615 mm 0.475 mm = 0.292 mm2
Scribe line width: x-dimension = 15 m
y-dimension = 15 m
Passivation on front
Type Sandwich structure
Material PE-Nitride (on top)
Thickness 1.75 m total thickness of passivation
Polyimide spacer 7 m
Au bump
Bump material > 99.9% pure Au
Bump hardness 35 – 80 HV 0.005
Bump shear strength > 70 MPa
Bump height 25 m[1]
Bump height uniformitySL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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[1] Because of the 7 m spacer, the bump will measure 18 m relative height protruding the spacer.
9.1.2 Fail die identification
No inkdots are applied to the wafer.
Electronic wafer mapping (SECS II format) covers the electrical test results and
additionally the results of mechanical/visual inspection.
See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on
UV-tape with electronic fail die marking, BU-ID document number: 1093**”
9.1.3 Map file distribution
See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on
UV-tape with electronic fail die marking, BU-ID document number: 1093**”
– within a die 2 m
– within a wafer 3 m
– wafer to wafer 4 m
Bump flatness 1.5 m
Bump size
– RFP, RFN 60 60 m
– OUT, VDD 60 60 m
Bump size variation 5 m
Table 5. Specifications …continuedSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10. Functional description
10.1 Air interface standards
The UCODE G2iM fully supports all parts of the "Specification for RFID Air Interface
EPCglobal, EPCTM Radio-Frequency Identity Protocols, Class-1 Generation-2 UHF
RFID, Protocol for Communications at 860 MHz to 960 MHz, Version 1.2.0".
10.2 Power transfer
The interrogator provides an RF field that powers the tag, equipped with a UCODE G2iM.
The antenna transforms the impedance of free space to the chip input impedance in order
to get the maximum possible power for the UCODE G2iM on the tag. The UCODE G2iM+
can also be supplied externally.
The RF field, which is oscillating on the operating frequency provided by the interrogator,
is rectified to provide a smoothed DC voltage to the analog and digital modules of the IC.
The antenna attached to the chip may use a DC connection between the two antenna
pads which also enables loop antenna design.
10.3 Data transfer
10.3.1 Reader to tag Link
An interrogator transmits information to the UCODE G2iM by modulating an UHF RF
signal. The UCODE G2iM receives both information and operating energy from this RF
signal. Tags are passive, meaning that they receive all of their operating energy from the
interrogator's RF waveform. In order to further improve the read range the UCODE G2iM
can be externally supplied as well so the energy to operate the chip does not need to be
transmitted by the reader.
An interrogator is using a fixed modulation and data rate for the duration of at least one
inventory round. It communicates to the UCODE G2iM by modulating an RF carrier using
DSB-ASK with PIE encoding.
For further details refer to Section 17, Ref. 1. Interrogator-to-tag (R=>T) communications.
10.3.2 Tag to reader Link
An interrogator receives information from a UCODE G2iM by transmitting an unmodulated
RF carrier and listening for a backscattered reply. The UCODE G2iM backscatters by
switching the reflection coefficient of its antenna between two states in accordance with
the data being sent. For further details refer to Section 17, Ref. 1, chapter 6.3.1.3.
The UCODE G2iM communicates information by backscatter-modulating the amplitude
and/or phase of the RF carrier. Interrogators shall be capable of demodulating either
demodulation type.
The encoding format, selected in response to interrogator commands, is either FM0
baseband or Miller-modulated subcarrier.SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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UCODE G2iM and G2iM+
10.4 UCODE G2iM and UCODE G2iM+ differences
The UCODE G2iM is tailored for application where EPC or TID number space, and User
Memory is needed. The UCODE G2iM+ provides beside the segmented memory
additional functionality such as tag tamper alarm, external supply operation to further
boost read/write range (external supply mode), a privacy mode reducing the read range
where the activation criteria (open or short) can be defined or I/O functionality (data
transfer to externally connected devices) where required.
The following table provides an overview of UCODE G2iM, UCODE G2iM+ special
features.
10.5 Supported commands
The UCODE G2iM supports all mandatory EPCglobal V1.2.0 commands.
In addition the UCODE G2iM supports the following optional commands:
• ACCESS
• BlockWrite (32 bit)
• BlockPermalock
The UCODE G2iM features the following custom commands described more in detail
later:
• ResetReadProtect (backward compatible to UCODE G2X; UCODE G2iL)
• ReadProtect(backward compatible to UCODE G2X; UCODE G2iL)
• ChangeEAS (backward compatible to UCODE G2X; UCODE G2iL)
• EAS_Alarm(backward compatible to UCODE G2X; UCODE G2iL)
• ChangeConfig(backward compatible to UCODE G2iL)
Table 6. Overview of UCODE G2iM and UCODE G2iM+ features
Features UCODE G2iM UCODE G2iM+
Read protection (bankwise) yes yes
PSF (Built-in Product Status Flag) yes yes
Backscatter strength reduction yes yes
BlockWrite (32 bit) yes yes
BlockPermalock yes yes
User TID (112 bit) yes yes
Segmented user memory (open, protected, private) - yes
Additional User Password for private memory - yes
EPC size selectable (448bit max.) - yes
Tag tamper alarm - yes
Digital switch / Digital input - yes
External supply mode - yes
Data transfer - yes
Real read range reduction - yes
Conditional Real Read Range Reduction - yesSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.6 UCODE G2iM and UCODE G2iM+ memory
The UCODE G2iM and UCODE G2iM+ memory is implemented according EPCglobal
Class1Gen2 and organized in four banks:
The logical address of all memory banks begin at zero (00h).
In addition to the four memory banks two configuration words are available. The first to
handle the UCODE G2iM memory configuration (Mem-Config-Word) is available at EPC
bank 01 address 1F0h and the second to handle UCODE G2iM specific features
Config-Word) is available at EPC bank 01 address 200h. The configuration words are
described in detail in Section 10.7.1 “ChangeConfig” and Section 10.7.3 “UCODE G2iM+
memory configuration control mechanism”.
Memory pages (16 bit words) pre-programmed to zero will not execute an erase cycle
before writing data to it. This approach accelerates initialization of the chip and enables
faster programming of the memory.
Table 7. UCODE G2iM and UCODE G2iM+ memory sections
Name Size Bank
Reserved memory (32 bit ACCESS and 32 bit KILL password) 64 bit 00b
EPC (excluding 16 bit CRC-16 and 16 bit PC) (UCODE G2iM)
EPC (excluding 16 bit CRC-16 and 16 bit PC) (UCODE G2iM+)
256 bit
128 bit
up to
448 bit
01b
G2iM Configuration Word (Config-Word) 16 bit 01b
G2iM Memory Configuration Word (Mem-Config-Word) 16 bit 01b
TID (including permalocked unique 48 bit serial number; 16bit unalterable
XTID-header)
96 bit 10b
User TID 112 bit 10b
User memory (UCODE G2iM)
User memory can be segmented and configured (UCODE G2iM+)
512 bit
320 bit
up to
640 bit
11bSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.6.1 UCODE G2iM and UCODE G2iM+ overall memory map
Table 8. UCODE G2iM and UCODE G2iM+ overall memory map
Bank
address
Memory
address
Type Content Initial Remark
Bank 00 00h to 1Fh reserved Kill Password all 00h unlocked memory
20h to 3Fh reserved Access Password all 00h unlocked memory
Bank 01
EPC
00h to 0Fh EPC CRC-16: refer to Ref. 16 memory mapped
calculated CRC
10h to 14h EPC backscatter length 00110b unlocked memory
15h EPC UMI 0b calculated according EPC
16h EPC reserved for future use 0b hardwired to 0
17h to 1Fh EPC numbering system indicator 00h unlocked memory
20h to 9Fh EPC EPC [1] unlocked memory
Bank 01
Memory
Config Word
1F0h to 1F3h EPC RFU 0000b hardwired to 0000b
1F4h to 1F7h EPC Number of EPC blocks 0h unlocked memory
1F8h to 1FBh EPC Number protected memory
blocks
0h unlocked memory
1FCh to 1FFh EPC Number of private memory
blocks
0h unlocked memory
Bank 01
Config Word
200h EPC tamper alarm flag 0b[4] indicator bit
201h EPC external supply flag or input
signal
0b[4] indicator bit
202h EPC RFU 0b[4] locked memory
203h EPC RFU 0b[4] locked memory
204h EPC invert digital output: 0b[4] temporary bit
205h EPC transparent mode on/off 0b[4] temporary bit
206h EPC transparent mode data/raw 0b[4] temporary bit
207h EPC conditional read range
reduction
0b[4] unlocked memory
208h EPC conditional read range
reduction
open/short
0b[4] unlocked memory
209h EPC max. backscatter strength 1b[4] unlocked memory
20Ah EPC digital output 0b[4] unlocked memory
20Bh EPC read range reduction on/off 0b[4] unlocked memory
20Ch EPC read protect User Memory 0b[4] locked memory
20Dh EPC read protect EPC Bank 0b[4] unlocked memory
20Eh EPC read protect TID 0b[4] unlocked memory
20Fh EPC PSF alarm flag 0b[4] unlocked memorySL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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UCODE G2iM and G2iM+
[1] UCODE G2iM: HEX E200 680A 0000 0000 0000 0000 (0000 0000)
UCODE G2iM+: HEX E200 680B 0000 0000 0000 0000 (0000 0000)
[2] Indicates the existence of a Configuration Word at the end of the EPC number
[3] See Figure 5
[4] See also Table 13 for further details.
Bank 10
TID
00h to 07h TID allocation class identifier 1110 0010b locked memory
08h to 13h TID tag mask designer identifier 0000 0000 0110b locked memory
14h TIG config word indicator 1b[2] locked memory
14h to 1Fh TID tag model number TMNR[3] locked memory
20h to 2Fh TID XTID Header 00h locked memory
30h to 5Fh TID serial number SNR locked memory
60h to CFh TID User TID memory all ’0’ unlocked memory
Bank 11
USER
000h to 27Fh USER User Memory undefined unlocked memory
Table 8. UCODE G2iM and UCODE G2iM+ overall memory map
Bank
address
Memory
address
Type Content Initial Remarkxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
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10.6.2 UCODE G2iM and UCODE G2iM+ TID memory details
Table 9. G2iM TID description
Model number
Type First 32 bit of
TID memory
Class ID Mask designer
ID
Config Word
indicator
Sub version
number
Version (Silicon)
number
UCODE G2iM E200680A E2h 006h 1 0000b 0001010
UCODE G2iM+ E200680B E2h 006h 1 0000b 0001011
Fig 5. G2iM TID memory structure
001aan573
Class Identifier
MS Byte
MS Bit LS Bit
TID
Mask-Designer Identifier Model Number XTID Header Serial Number
7Bits 000 11 11 15 0 47 0
Addresses 00h 07h 13h 1Fh 5Fh
Addresses 00h CFh
08h 14h 20h 2Fh 30h
E2h
(EAN.UCC)
TID Example
(UCODE G2iM)
006h
(NXP)
80Ah
(UCODE G2iM)
0000h
Sub Version Number Version Number
000b 0001010b
(UCODE G2iM)
Bits 0 3 0 6 0
Addresses 14h 18h 19h 1Fh
LS Byte
User TID
112 0
60h CFhSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.7 Custom commands
The UCODE G2iM and UCODE G2iM+ supports a number of additional features and
custom commands. Nevertheless, the chip is designed in a way standard EPCglobal
READ/WRITE/ACCESS commands can be used to operate the features.
The memory map stated in the previous section describes the Config-Word used to
control the additional features located at address 200h as well as the Mem-Config-Word
located at 1F0h of the EPC memory. For this reason the standard READ/WRITE
commands of an UHF EPCglobal compliant reader can be used to select the flags,
activate/deactivate features or define memory segments.
The features can only be activated/deactivated (written) using standard EPC WRITE
command as long the EPC is not locked. In case the EPC is locked either the bank needs
to be unlocked to apply changes or the ChangeConfig custom command is used to
change the settings.
The UCODE G2iM products supports the complete UCODE G2iL command set for
backward compatibility reasons.
Bit 14h of the TID indicates the existence of a Configuration Word. This flag will enable
selecting Config-Word enhanced transponders in mixed tag populations.
10.7.1 ChangeConfig
Although UCODE G2iM is tailored for supply chain management, item level tagging and
product authentication the UCODE G2iM+ version enables active interaction with
products. Among the password protected features are the capability of download firmware
to electronics, activate/deactivate electronics which can also be used as theft deterrence,
a dedicated privacy mode by reducing the read range, integrated PSF (Product Status
Flag) or Tag Tamper Alarm. In addition to the UCODE G2iL/G2iL+ the activation condition
(open/short) for the Read Range Reduction can be defined by the user.
The UCODE G2iM ChangeConfig custom command allows handling the special NXP
Semiconductors features described in the following paragraph. Please also see the
memory map in Section 10.6 “UCODE G2iM and UCODE G2iM+ memory” and “Section
10.7.2 “UCODE G2iM and UCODE G2iM+ special features control mechanism”. If the
EPC memory is not write locked the standard EPC READ/WRITE command can be used
to change the settings.
UCODE G2iM and UCODE G2iM+ special features1
UCODE G2iM and UCODE G2iM+ common special features are:
• Bank wise read protection (separate for EPC, TID and User Memory)
EPC bank (except of configuration words), the serial number part of the TID as well as
the User TID and the User Memory (open segment) can be read protected
independently. When protected reading of the particular memory will return '0'. The
flags of the Config-Word can be selected using the standard SELECT command. Only
read protected parts will then participate an inventory round.
1. The features can only be manipulated (enabled/disabled) with unlocked EPC bank, otherwise the ChangeConfig command can be
used.SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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UCODE G2iM and G2iM+
• Integrated PSF (Product Status Flag)
The PSF is a general purpose flag that can be used as an EAS (Electronic Article
Surveillance) flag, quality checked flag or similar.
The UCODE G2iM offers two ways of detecting an activated PSF. In cases extremely
fast detection is needed the EAS_Alarm command can be used. The UCODE G2iM
will reply a 64 bit alarm code like described in section EAS_Alarm upon sending the
command. As a second option the EPC SELECT command selecting the PSF flag of
the Config-Word can be used. In the following inventory round only PSF enabled
chips will reply their EPC number.
• Backscatter strength reduction
The UCODE G2iM features two levels of backscatter strengths. Per default maximum
backscatter is enabled in order to enable maximum read rates. When clearing the flag
the strength can be reduced if needed.
UCODE G2iM+ specific special features are:1
• Real Read Range Reduction 4R (UCODE G2iM+ only)
Some applications require the reduction of the read range to close proximity for
privacy reasons. Setting the 4R flag will significantly reduce the chip sensitivity to
+12 dBm. The +12 dBm have to be available at chip start up (slow increase of field
strength is not applicable). For additional privacy, the read protection can be activated
in the same configuration step. The related flag of the configuration word can be
selected using the standard SELECT command so only chips with reduced read
range will be part of an inventory.
Remark: The attenuation will result in only a few centimeter of read range at 36 dBm
EIRP!
• Tag Tamper Alarm (UCODE G2iM+ only)
The UCODE G2iM+ Tamper Alarm will flag the status of the VDD to OUT pad
connection which can be designed as an predetermined breaking point (see
Figure 6).
The status of the pad connection (open/closed) can be read in the configuration register
and/or selected using the EPC SELECT. This feature enables the design of a wireless
RFID safety seal. When breaking the connection by peeling off the label or manipulating a
lock an alarm can be triggered.
Fig 6. Schematic of connecting VDD and OUT pad with a predetermined breaking point
to turn a standard RFID label into a wireless safety seal
001aan668
OUT VDD
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UCODE G2iM and G2iM+
• Conditional Real Read Range Reduction (UCODE G2iM+ only)
In addition to the 4R and the Tag Tamper Alarm feature the UCODE G2iM+ offers a
feature which combines both in one functionality. This feature allow the automatic
activation of the 4R depending on the status of the VDD to OUT pad connection. To
offer high flexibility for the applications the 4R activation can be done on short (bit 8 =
’1’) or open (bit 8 =’0’) of the VDD to OUT pad connection. For activation of this
feature bit 7 and bit 11 of the Config-Word have to be set to ’1’.
• Digital Switch (UCODE G2iM+ only)
The UCODE G2iM+ OUT pin can be used as digital switch. The state of the output
pad can be switched to VDD or GND depending on the Digital OUT bit of the
Config-Word register. The state of the output is persistent in the memory even after
KILL or switching off the supply. This feature will allow activating/deactivating
externally connected peripherals or can be used as theft deterrence of electronics.
The state of the OUT pin can also be changed temporary by toggling the 'Invert Digital
Output' bit.
• Data transfer Mode (UCODE G2iM+ only)
In applications where not switching the output like described in "Digital Switch" but
external device communication is needed the UCODE G2iM+ Data Transfer Mode
can be used by setting the according bit of the Config-Word register. When activated
the air interface communication will be directly transferred to the OUT pad of the chip.
Two modes of data transfer are available and can be switched using the Transparent
Mode DATA/RAW bit.
The default Transparent Mode DATA will remove the Frame Sync of the
communication and toggle the output with every raising edge in the RF field. This will
allow implementing a Manchester type of data transmission.
The Transparent Mode RAW will switch the demodulated air interface communication
to the OUT pad.
• External Supply Indicator - Digital Input (UCODE G2iM+ only)
The VDD pad of the UCODE G2iM+ can be used as a digital input pin. The state of
the pad is directly associated with the External Supply Indicator bit of the configuration
register. A simple return signaling (chip to reader) can be implemented by polling this
Configuration Word register flag. RF reset is necessary for proper polling.
• External Supply Mode (G2iM+ only)
The UCODE G2iM+ can be supplied externally by connecting 1.85 V (Iout = 0µA)
supply. When externally supplied less energy from the RF field is needed to operate
the chip. This will not just enable further improved sensitivity and read ranges (up to
-27 dBm) but also enable a write range that is equal to the read range.
The figure schematically shows the supply connected to the UCODE G2iM+.
Remark: When permanently externally supplied there will not be a power-on-reset. This
will result in the following limitations:
• When externally supplied session flag S0 will keep it’s state during RF-OFF phase.
• When externally supplied session flag S2, S3, SL will have infinite persistence time
and will behave similar to S0.
• Session flag S1 will behave regular like in pure passive operation.SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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The bits to be toggled in the configuration register need to be set to '1'.
E.g. sending 0000 0000 0001 0001 XOR RN16 will activate the 4R and PSF. Sending the
very same command a second time will disable the features again.
The reply of the ChangeConfig will return the current register setting.
Fig 7. Schematic of external power supply
Table 10. ChangeConfig custom command
Command RFU Data RN CRC-16
No. of bits 16 8 16 16 16
Description 11100000
00000111
00000000 Toggle bits
XOR RN 16
handle -
Table 11. ChangeConfig custom command reply
Header Status bits RN CRC-16
No. of bits 1 16 16 16
Description 0 Config-Word Handle -
Table 12. ChangeConfig command-response table
Starting state Condition Response Next state
ready all - ready
arbitrate, reply,
acknowledged
all - arbitrate
open valid handle Status word
needs to change
Backscatter unchanged
Config-Word immediately
open
valid handle Status word does
not need to change
Backscatter Config-Word
immediately
open
secured valid handle Status word
needs to change
Backscatter modified
Config-Word, when done
secured
valid handle Status word does
not need to change
Backscatter Config-Word
immediately
secured
killed all - killed
001aan669
OUT VDD
Vsupply
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UCODE G2iM and G2iM+
The features can only be activated/deactivated using standard EPC WRITE if the EPC
bank is unlocked. The permanent and temporary bits of the Configuration Word can be
toggled without the need for an Access Password in case the Access Password is set to
zero. In case the EPC bank is locked the lock needs to be removed before applying
changes or the ChangeConfig command has to be used.
10.7.2 UCODE G2iM and UCODE G2iM+ special features control mechanism
Special features of the UCODE G2iM are managed using a configuration word
(Config-Word) located at address 200h in the EPC memory bank.
The entire Config-Word is selectable (using the standard EPC SELECT command), as
well as single bits, and can be read using standard EPC READ command and modified
using the standard EPC WRITE or ChangeConfig custom command in case the EPC
memory is locked for writing.
ChangeConfig can be executed from the OPEN and SECURED state.
The chip will take all “Toggle Bits” for ’0’ if the chip is in the OPEN state or the ACCESS
password is zero; therefore it will not alter any status bits, but report the current status
only. The command will be ignored with an invalid CRC-16 or an invalid handle. The chip
will then remain in the current state. The CRC-16 is calculated from the first
command-code bit to the last handle bit.
A ChangeConfig command without frame-sync and proceeding Req_RN will be ignored.
The command will also be ignored if any of the RFU bits are toggled.
In order to change the configuration, to activate/deactivate a feature a ’1’ has to be written
to the corresponding register flag to toggle the status. E.g. sending 0x0002 to the register
will activate the read protection of the TID. Sending the same command a second time will
again clear the read protection of the TID. Invalid toggling on indicator or RFU bits are
ignored.
Executing the command with zero as payload or in the OPEN state will return the current
register settings. The chip will reply to a successful ChangeStatus with an extended
preamble regardless of the TRext value of the Query command.
After sending a ChangeConfig an interrogator shall transmit CW for less than TReply or
20ms, where TReply is the time between the interrogator's ChangeConfig command and
the chip’s backscattered reply. An interrogator may observe three possible responses
after sending a ChangeConfig, depending on the success or failure of the operation
• ChangeConfig succeeded: The chip will backscatter the reply shown above
comprising a header (a 0-bit), the current Config-Word setting, the handle, and a
CRC-16 calculated over the 0-bit, the Config-Word and the handle. If the interrogator
observes this reply within 20 ms then the ChangeConfig completed successfully.
• The chip encounters an error: The chip will backscatter an error code during the CW
period rather than the reply shown below (see EPCglobal Spec for error-code
definitions and for the reply format).
• ChangeConfig does not succeed: If the interrogator does not observe a reply within
20 ms then the ChangeConfig did not complete successfully. The interrogator may
issue a Req_RN command (containing the handle) to verify that the chip is still in the
interrogator's field, and may reissue the ChangeConfig command.SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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The UCODE G2iM configuration word (Config-Word) is located at address 200h of the
EPC memory and is structured as following:
The configuration word contains three different type of bits:
• Indicator bits cannot be changed by command:
Tag Tamper Alarm Indicator
External Supply Indicator (digital input)
• Temporary bits are reset at power up:
Invert Output
Transparent Mode on/off
Data Mode data/raw
• Permanent bits: permanently stored bits in the memory
Conditional Read Range Reduction on/off
Conditional Read Range Reduction short/open
Max. Backscatter Strength
Digital Output
Read Range Reduction
Read Protect User Memory
Read Protect EPC
Read Protect TID
PSF Alarm
Table 13. Address 200h to 207h
Indicator bits Temporary bits Permanent bits
Tamper
indicator
External supply
indicator
RFU RFU Invert Output Transparent
mode
on/off
Data mode
data/raw
Conditional Read
Range Reduction
on/off
0 1 2 34 5 6 7
Table 14. Address 208h to 20Fh
Permanent bits
Conditional
Read Range
Reduction
open/short
max. backscatter
strength
Digital
output
Read
Range
Reduction
Protect UM Protect EPC Protect TID PSF Alarm
bit
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10.7.3 UCODE G2iM+ memory configuration control mechanism
The segmented user memory available in the UCODE G2iM+ enables a flexible
configuration of the device with respect to EPC size and access rights to the User
Memory.
The standard configuration offers 256 bit EPC memory and 512 bit open User Memory for
UCODE G2iM and 128 bit EPC memory and 640 bit open User Memory for UCODE
G2iM+. For applications where more EPC memory is required the UCODE G2iM+ offers
the flexibility to extend the 128 bit EPC up to 448 bit (in steps of 64 bit) by reducing the
User Memory size accordingly. See Table 15 and Table 17.
Beside the possibility to extend the EPC memory the UCDOE G2iM+ offers the possibility
to segment the User Memory in up to three areas with different access rights.
• Open: no read/write protection
• Protected: read/write protected by the Access Password
• Private: read/write protected by the User Password (see Section 10.7.4)
Table 15. EPC / User Memory Standard Configuration (UCODE G2iM)
EPC Memory User Memory
Open
256 bit 512 bit
Table 16. EPC / User Memory Standard Configuration (UCODE G2iM+)
EPC Memory User Memory
Open
128 bit 640 bit
Table 17. EPC / User Memory Max. EPC Configuration (UCODE G2iM+)
EPC Memory User Memory
Open
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The memory configuration can be defined one time, by programming the memory
configuration word, at the initialization of the UCODE G2iM+. The UCODE G2iM+
Memory Configuration Word (Mem-Config-Word) is located at address 1F0h of the EPC
memory and is structured as following:
• RFU-Bits:
The four RFU bits are fixed to 0000b. These four bits are ignored for access
commands (e.g. WRITE).
• Number of EPC blocks:
The 4 bit of this region specify the number of blocks (max. 5) which should be added
on top of the standard EPC Memory of 128bit.
• Number of Protected memory blocks:
The 4 bit of this region specify the number of blocks which should be used for the
Protected memory region.
• Number of Private memory blocks:
The 4 bit of this region specify the number of blocks which should be used for the
Private memory region.
The total amount of User Memory is defined by the number of blocks for EPC-, Open-,
Protected- and Private- memory area. Based on the total User Memory size (640 bit) and
the defined block size of 64 bit, the overall number of blocks results in ten blocks. As
described in the examples (Table 19 to Table 21) below the blocks used for the EPC-,
Open-, Protected- or Private segment can be exchanged according to the application
requirements as long as the overall block number is below ten.
The number of blocks allocated to the Open Memory Area are defined by the number of
blocks specified in the Mem-Config-Word, therefore the size of the Open Memory area is
derived by subtracting the number of defined blocks (Mem-Config-Word) from the total
available number of blocks of the User Memory (10 blocks). Undefined blocks are always
added to the Open Memory area.
In case an invalid total amount of blocks (exceeds ten) is written to the Mem-Config-Word,
the configuration fails and the error code (Locked Memory) will be returned.
The entire Mem-Config-Word is selectable (using the standard EPC SELECT command),
as well as single bits, and can be read using standard EPC READ command and modified
using the standard EPC WRITE command.
NOTE:
THE MEM-CONFIG-WORD IS ONE TIME PROGRAMMABLE.
Programming has be performed in the secured state.
In case no programming of the memory configuration word is done at the initialization of
the UCODE G2iM+ it will be automatically locked upon a lock of any part of the memory.
The following tables will provide a few examples for different memory configurations.
Table 18. Memory Configuration Word, Address 1F0h to 1FFh
RFU Number
of EPC blocks
Number of
Protected memory blocks
Number of
Private memory blocks
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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• Standard EPC size, 4 blocks Protected and 3 blocks Private memory which results in
3 blocks Open memory.
(Mem-Config-Word value: 0043h)
See Table 19
• Standard EPC size, 3 blocks Protected memory which results in 7 blocks Open
memory. (Mem-Config-Word value: 0030h).
See Table 20
• 192 bit EPC (1 block EPC added), 6 blocks Private memory which results in 4 blocks
Open memory. (Mem-Config-Word value: 0106h)
See Table 21
10.7.4 Private Memory Segment
The Private memory is a part of the User Memory which can be accessed out of the
secured state only. Private regions will appear as non existent to not authorized users.
The address of the location of the User Password is not fixed and has therefore to be
calculated based on the applied memory configuration.
The 32 bit User Password is located at the end of the User Memory. Since the UCODE
G2iM+ memory is configurable and can be segmented the address location of the User
Password depends on the Memory configuration done at the initialization.
User Password address calculation:
HEX[(Total number of memory blocks - blocks appointed to EPC)*Blocksize)]
Example:
EPC length: 192
This means that 1 block from the User Memory is required (128 bit + 64 bit)
HEX[(101)*64]=HEX[9*64]=HEX[384]=240h
Therefore the User Password for this configuration is located at address 240h to 25Fh
Table 19. User Memory Configuration with 3 segments
EPC Memory User Memory
Open Protected Private
128 bit 192 bit 256 bit 192 bit
Table 20. User Memory Configuration with 2 segments (no Private segment)
EPC Memory User Memory
Open Protected
128 bit 448 bit 192 bit
Table 21. User Memory Configuration with 2 areas (no Access password protected area)
EPC Memory User Memory
Open Private
192 bit 192 bit 384 bitSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.7.5 ReadProtect2
The UCODE G2iM ReadProtect custom command enables reliable read protection of the
entire UCODE G2iM memory. Executing ReadProtect from the Secured state will set the
ProtectEPC and ProtectTID bits of the Configuration Word to '1'. With the ReadProtect-Bit
set the UCODE G2iM will continue to work unaffected but veil its protected content.
The read protection can be removed by executing Reset ReadProtect. The
ReadProtect-Bits will than be cleared.
Devices whose access password is zero will ignore the command. A frame-sync must be
pre-pended the command.
After sending the ReadProtect command an interrogator shall transmit CW for the lesser
of TReply or 20 ms, where TReply is the time between the interrogator's ReadProtect
command and the backscattered reply. An interrogator may observe three possible
responses after sending a ReadProtect, depending on the success or failure of the
operation:
• ReadProtect succeeds: After completing the ReadProtect the UCODE G2iM shall
backscatter the reply shown in Table 23 comprising a header (a 0-bit), the tag's
handle, and a CRC-16 calculated over the 0-bit and handle. Immediately after this
reply the UCODE G2iM will render itself to this ReadProtect mode. If the interrogator
observes this reply within 20 ms then the ReadProtect completed successfully.
• The UCODE G2iM encounters an error: The UCODE G2iM will backscatter an error
code during the CW period rather than the reply shown in the EPCglobal Spec (see
Annex I for error-code definitions and for the reply format).
• ReadProtect does not succeed: If the interrogator does not observe a reply within
20 ms then the ReadProtect did not complete successfully. The interrogator may
issue a Req_RN command (containing the handle) to verify that the UCODE G2iM is
still in the interrogation zone, and may re-initiate the ReadProtect command.
The UCODE G2iM reply to the ReadProtect command will use the extended preamble
shown in EPCglobal Spec (Figure 6.11 or Figure 6.15), as appropriate (i.e. a Tag shall
reply as if TRext=1) regardless of the TRext value in the Query that initiated the round.
2. Note: The ChangeConfig command can be used instead of “ReadProtect”, “ResetReadProtect”, “ChangeEAS”.
Table 22. ReadProtect command
Command RN CRC-16
# of bits 16 16 16
description 11100000 00000001 handle -
Table 23. UCODE G2iM reply to a successful ReadProtect procedure
Header RN CRC-16
# of bits 1 16 16
description 0 handle -SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.7.6 Reset ReadProtect2
Reset ReadProtect allows an interrogator to clear the ProtectEPC and ProtectTID bits of
the Configuration Word. This will re-enable reading of the related UCODE G2iM memory
content.
For details on the command response please refer to Table 25 “Reset ReadProtect
command”.
After sending a Reset ReadProtect an interrogator shall transmit CW for the lesser of
TReply or 20 ms, where TReply is the time between the interrogator's Reset ReadProtect
command and the UCODE G2iM backscattered reply. A Req_RN command prior to the
Reset ReadProtect is necessary to successfully execute the command. A frame-sync
must be pre-pended the command.
An interrogator may observe three possible responses after sending a Reset
ReadProtect, depending on the success or failure of the operation:
• Reset ReadProtect succeeds: After completing the Reset ReadProtect a UCODE
G2iM will backscatter the reply shown in Table 26 comprising a header (a 0-bit), the
handle, and a CRC-16 calculated over the 0-bit and handle. If the interrogator
observes this reply within 20 ms then the Reset ReadProtect completed successfully.
• The UCODE G2iM encounters an error: The UCODE G2iM will backscatter an error
code during the CW period rather than the reply shown in Table 26 (see EPCglobal
Spec for error-code definitions and for the reply format).
• Reset ReadProtect does not succeed: If the interrogator does not observe a reply
within 20 ms then the Reset ReadProtect did not complete successfully. The
interrogator may issue a Req_RN command (containing the handle) to verify that the
G2iM is still in the interrogation zone, and may reissue the Reset ReadProtect
command.
The UCODE G2iM reply to the Reset ReadProtect command will use the extended
preamble shown in EPCglobal Spec (Figure 6.11 or Figure 6.15), as appropriate (i.e. a
UCODE G2iM will reply as if TRext=1 regardless of the TRext value in the Query that
initiated the round.
Table 24. ReadProtect command-response table
Starting State Condition Response Next State
ready all – ready
arbitrate, reply,
acknowledged
all – arbitrate
open all - open
secured valid handle & invalid
access password
– arbitrate
valid handle & valid
non zero access
password
Backscatter handle,
when done
secured
invalid handle – secured
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The Reset ReadProtect command is structured as following:
• 16 bit command
• Password: 32 bit Access-Password XOR with 2 times current RN16
Remark: To generate the 32 bit password the 16 bit RN16 is duplicated and used two
times to generate the 32 bit (e.g. a RN16 of 1234 will result in 1234 1234).
• 16 bit handle
• CRC-16 calculate over the first command-code bit to the last handle bit
Table 25. Reset ReadProtect command
Command Password RN CRC-16
# of bits 16 32 16 16
description 11100000
00000010
(access
password)
2*RN16
handle -
Table 26. UCODE G2iM reply to a successful Reset ReadProtect command
Header RN CRC-16
# of bits 1 16 16
description 0 handle -
Table 27. Reset ReadProtect command-response table
Starting State Condition Response Next State
ready all – ready
arbitrate, reply,
acknowledged
all – arbitrate
open valid handle & valid access password Backscatter handle,
when done
open
valid handle & invalid access password – arbitrate
invalid handle – open
secured valid handle & valid access password Backscatter handle,
when done
secured
valid handle & invalid access password – arbitrate
invalid handle – secured
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10.7.7 ChangeEAS2
UCODE G2iM equipped RFID tags will also feature a stand-alone operating EAS alarm
mechanism for fast and offline electronic article surveillance. The PSF bit of the
Config-Word directly relates to the EAS Alarm feature. With an PSF bit set to '1' the tag
will reply to an EAS_Alarm command by backscattering a 64 bit alarm code without the
need of a Select or Query. The EAS is a built-in solution so no connection to a backend
database is required. In case the EAS_Alarm command is not implemented in the reader
a standard EPC SELCET to the Config-Word and Query can be used. When using
standard SELECT/QUERY the EPC will be returned during inventory.
ChangeEAS can be executed from the Secured state only. The command will be ignored
if the Access Password is zero, the command will also be ignored with an invalid CRC-16
or an invalid handle, the UCODE G2iM will than remain in the current state. The CRC-16
is calculated from the first command-code bit to the last handle bit. A frame-sync must be
pre-pended the command.
The UCODE G2iM reply to a successful ChangeEAS will use the extended preamble, as
appropriate (i.e. a Tag shall reply as if TRext=1) regardless of the TRext value in the
Query that initiated the round.
After sending a ChangeEAS an interrogator shall transmit CW for less than TReply or
20 ms, where TReply is the time between the interrogator's ChangeEAS command and
the UCODE G2iM backscattered reply. An interrogator may observe three possible
responses after sending a ChangeEAS, depending on the success or failure of the
operation
• ChangeEAS succeeds: After completing the ChangeEAS a UCODE G2iM will
backscatter the reply shown in Table 29 comprising a header (a 0-bit), the handle, and
a CRC-16 calculated over the 0-bit and handle. If the interrogator observes this reply
within
20 ms then the ChangeEAS completed successfully.
• The UCODE G2iM encounters an error: The UCODE G2iM will backscatter an error
code during the CW period rather than the reply shown in Table 29 (see EPCglobal
Spec for error-code definitions and for the reply format).
• ChangeEAS does not succeed: If the interrogator does not observe a reply within
20 ms then the ChangeEAS did not complete successfully. The interrogator may
issue a Req_RN command (containing the handle) to verify that the G2iM is still in the
interrogator's field, and may reissue the ChangeEAS command.
Upon receiving a valid ChangeEAS command a G2iM will perform the commanded
set/reset operation of the PSF bit of the Configuration Word.
If PSF bit is set, the EAS_Alarm command will be available after the next power up and
reply the 64 bit EAS code upon execution. Otherwise the EAS_Alarm command will be
ignored.
Table 28. ChangeEAS command
Command ChangeEas RN CRC-16
# of bits 16 1 16 16
description 11100000
00000011
1 ... set PSF bit
0 ... reset PSF bit
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10.7.8 EAS_Alarm
Upon receiving an EAS_Alarm custom command the UCODE G2iM will immediately
backscatter an EAS-Alarmcode in case the PSF bit of the Config-Word is set. The alarm
code is returned without any delay caused by Select, Query and without the need for a
backend database.
The EAS feature of the UCODE G2iM is available after enabling it by sending a
ChangeEAS command described in Section 10.7.7 “ChangeEAS2” or after setting the
PSF bit of the Config-Word to ’1’. With the EAS-Alarm enabled the UCODE G2iM will
reply to an EAS_Alarm command by backscattering a fixed 64 bit alarm code. A UCODE
G2iM will reply to an EAS_Alarm command from the ready state only. As an alternative to
the fast EAS_Alarm command a standard SELECT (upon the Config-Word) and QUERY
can be used.
If the PSF bit is reset to '0' by sending a ChangeEAS command in the password protected
Secure state or clearing the PSF bit the UCODE G2iM will not reply to an EAS_Alarm
command.
The EAS_Alarm command is structured as following:
• 16 bit command
• 16 bit inverted command
• DR (TRcal divide ratio) sets the T=>R link frequency as described in EPCglobal Spec.
6.3.1.2.8 and Table 6.9.
• M (cycles per symbol) sets the T=>R data rate and modulation format as shown in
EPCglobal Spec. Table 6.10.
• TRext chooses whether the T=>R preamble is pre-pended with a pilot tone as
described in EPCglobal Spec. 6.3.1.3.
A preamble must be pre-pended the EAS_Alarm command according EPCglobal Spec,
6.3.1.2.8.
Table 29. UCODE G2iM reply to a successful ChangeEAS command
Header RN CRC-16
# of bits 1 16 16
description 0 handle -
Table 30. ChangeEAS command-response table
Starting State Condition Response Next state
ready all – ready
arbitrate, reply,
acknowledged
all – arbitrate
open all – open
secured valid handle backscatter handle,
when done
secured
invalid handle – secured
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Upon receiving an EAS_Alarm command the tag loads the CRC5 register with 01001b
and backscatters the 64 bit alarm code accordingly. The reader is now able to calculate
the CRC5 over the backscattered 64 bits received to verify the received code.
Table 31. EAS_Alarm command
Command Inv_Command DR M TRext CRC-16
# of bits 16 16 1 2 1 16
description 11100000
00000100
00011111
11111011
0: DR=8
1: DR=64/3
00: M=1
01: M=2
10: M=4
11: M=8
0: no pilot
tone
1: use pilot
tone
-
Table 32. UCODE G2iM reply to a successful EAS_Alarm command
Header EAS Code
# of bits 1 64
description 0 CRC5 (MSB)
Table 33. EAS_Alarm command-response table
Starting State Condition Response Next state
ready PSF bit is set
PSF bit is cleard
backscatter alarm code
--
ready
arbitrate, reply,
acknowledged
all – arbitrate
open all – open
secured all – secured
killed all – killedSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
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201236 31 of 43
NXP Semiconductors SL3S1003_1013
UCODE G2iM and G2iM+
11. Limiting values
[1] Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any conditions other
than those described in the Operating Conditions and Electrical Characteristics section of this specification
is not implied.
[2] This product includes circuitry specifically designed for the protection of its internal devices from the
damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be
taken to avoid applying greater than the rated maxima.
[3] For ESD measurement, the die chip has been mounted into a CDIP20 package.
Table 34. Limiting values[1][2]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages are referenced to RFN
Symbol Parameter Conditions Min Max Unit
Bare die limitations
Tstg storage temperature 55 +125 C
Tamb ambient temperature 40 +85 C
VESD electrostatic discharge
voltage
Human body
model
[3] - ±2 kV
Pad limitations
Vi input voltage absolute limits,
VDD-OUT pad
0.5 +2.5 V
Io output current absolute limits
input/output
current, VDD-OUT
pad
0.5 +0.5 mA
Pi input power maximum power
dissipation, RFP
pad
- 100 mWSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
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NXP Semiconductors SL3S1003_1013
UCODE G2iM and G2iM+
12. Characteristics
12.1 UCODE G2iM and UCODE G2iM+ bare die characteristics
[1] Power to process a Query command.
[2] Measured with a 50 source impedance.
[3] At minimum operating power.
[4] It has to be assured the reader (system) is capable of providing enough field strength to give +10 dBm at the chip otherwise
communication with the chip will not be possible.
[5] Enables tag designs to be within ETSI limits for return link data rates of e.g. 320 kHz/M4.
[6] Will result in up to 10 dB higher tag backscatter power at high field strength.
[7] Results in approx. 18 dBm tag sensitivity on a 2 dBi gain antenna.
Table 35. UCODE G2iM and UCODE G2iM+ RF interface characteristics (RFN, RFP)
Symbol Parameter Conditions Min Typ Max Unit
fi input frequency 840 - 960 MHz
Normal mode - no external supply, read range reduction OFF
Pi(min) minimum input power READ sensitivity [1][2][7] - 17.5 - dBm
Pi(min) minimum input power WRITE,
BLOCKWRITE
sensitivity, (write
range/read range -
ratio)
-
-
30
20
- %
Ci input capacitance parallel [3] - 0.77 - pF
Q quality factor 915 MHz [3] - 9.2 - -
Z impedance 866 MHz [3] - 27 j234 -
915 MHz [3] - 24 j222 -
953MHz [3] - 23 j213 -
External supply mode - VDD pad supplied, read range reduction OFF
Pi(min) minimum input power Ext. supplied READ [1][2] - 27 - dBm
Ext. supplied WRITE [2] - 27 - dBm
Z impedance externally supplied,
915 MHz
[3] - 8 -j228 -
Read range reduction ON - no external supply
Pi(min) minimum input power 4R on READ [1][2][4] - +10 - dBm
4R on WRITE [2][4] - +10 - dBm
Z impedance 4R on, 915 MHz [3] - 16 j1 -
Modulation resistance
R resistance modulation
resistance, max.
backscatter = off
[5] - 170 -
modulation
resistance, max.
backscatter = on
[6] - 55 - SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
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NXP Semiconductors SL3S1003_1013
UCODE G2iM and G2iM+
[1] Activates Digital Output (OUT pin), increases read range (external supplied).
[2] Activates Digital Output (OUT pin), increases read and write range (external supplied).
[3] Operating the chip outside the specified voltage range may lead to undefined behaviour.1925.
[4] Either the voltage or the current needs to be above given values to guarantee specified functionality.
[5] No proper operation is guaranteed if both, voltage and current, limits are exceeded.
[1] Is the sum of the allowed capacitance of the VDD and OUT pin referenced to RFN.
[2] Is the maximum allowed RF input voltage coupling to the VDD/OUT pin to guarantee undisturbed chip functionality.
[3] Resistance between VDD and OUT pin in checked during power up only.
[4] Resistance range to achieve tamper alarm flag = 1.
[5] Resistance range to achieve tamper alarm flag = 0:
Table 36. VDD pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
Minimum supply voltage/current - without assisted EEPROM WRITE [1][3][4]
VDD supply voltage minimum voltage - - 1.8 V
IDD supply current minimum current,
Iout = 0 mA
- - 14 mA
Iout = 100 mA - - 120 mA
Minimum supply voltage/current - assisted EEPROM READ and WRITE [2][3][4]
VDD supply voltage minimum voltage,
Iout = 0 mA
- 1.8 1.85 V
Iout = 100 mA - - 1.95 V
IDD supply current minimum current,
Iout = 0 mA
- - 135 mA
Iout = 100 mA - - 265 mA
Maximum supply voltage/current [3][5]
VDD supply voltage absolute maximum
voltage
2.2 - - V
Ii(max) maximum input current absolute maximum
current
280 - - mA
Table 37. G2iM, G2iM+ VDD and OUT pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
OUT pin characteristics
VOL Low-level output voltage Isink = 1mA - - 100 mV
VOH HIGH-level output voltage VDD = 1.8 V; Isource
= 100µA
1.5 - - V
VDD/OUT pin characteristics
CL load capacitance VDD - OUT pin max. [1] - - 5 pF
Vo output voltage maximum RF peak
voltage on VDD-OUT
pins
[2] - - 500 mV
VDD/OUT pin tamper alarm characteristics [3]
RL(max) maximum load resistance resistance range high [4] - - <2 M
RL(min) minimum load resistance resistance range low [5] >20 - - MSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 17 October 2014
201236 34 of 43
NXP Semiconductors SL3S1003_1013
UCODE G2iM and G2iM+
[1] Tamb 25 C
12.2 UCODE G2iM+ SOT886 characteristics
[1] Power to process a Query command.
[2] Measured with a 50 source impedance.
[3] At minimum operating power.
Remark: For DC and memory characteristics refer to Table 36, Table 37 and Table 38.
Table 38. UCODE G2iM and UCODE G2iM+ memory characteristics
Symbol Parameter Conditions Min Typ Max Unit
EEPROM characteristics
tret retention time Tamb 55 C 20 - - year
Nendu(W) write endurance 1000 10000[1] - cycle
Table 39. G2iM+ RF interface characteristics (RFN, RFP)
Symbol Parameter Conditions Min Typ Max Unit
Normal mode - no external supply, read range reduction OFF
Pi(min) minimum input power READ
sensitivity
[1][2] - 17.6 - dBm
Z impedance 915 MHz [3] - 21.2 -j199.7 -
Normal mode - externally supply VDD = 1.8V, read range reduction OFF
Z impedance 915 MHz [3] - 6.9 -j205.5 - SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
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NXP Semiconductors SL3S1003_1013
UCODE G2iM and G2iM+
13. Package outline
Fig 8. Package outline SOT886
terminal 1
index area
OUTLINE REFERENCES
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT886 MO-252
SOT886
04-07-15
04-07-22
DIMENSIONS (mm are the original dimensions)
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
D
E
e1
e
A1
b
L L 1
e1
0 1 2 mm
scale
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
UNIT
mm 0.25
0.17
1.5
1.4
0.35
0.27
A1 max b E
1.05
0.95
D e e1 L
0.40
0.32
L1
0.50.6
A(1)
max
0.5 0.04
1
6
2
5
3
4
6×
(2)
4×
(2)
ASL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
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NXP Semiconductors SL3S1003_1013
UCODE G2iM and G2iM+
14. Handling information
14.1 Assembly conditions
14.1.1 General assembly recommendations
While pads OUT and VDD are not used for UCODE G2iM (SL3S1003), they are still
electrically active and therefore must not be connected to the antenna and the RFN and
RFP pads.
In case of any doubts, the customer is constrained to contact NXP Semiconductors for
further clarification.
14.1.2 Label converting
Generally, an optimization of the entire lamination process by label manufacturer is
recommended in order to minimize the stress onto the module and guarantee high
assembly yield. Roller diameter must not be smaller than 45 mm.
15. Packing information
15.1 Wafer
See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on
UV-tape with electronic fail die marking, BU-ID document number: 1093**”SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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NXP Semiconductors SL3S1003_1013
UCODE G2iM and G2iM+
16. Abbreviations
Table 40. Abbreviations
Acronym Description
CRC Cyclic Redundancy Check
CW Continuous Wave
DC Direct Current
EAS Electronic Article Surveillance
EEPROM Electrically Erasable Programmable Read Only Memory
EPC Electronic Product Code (containing Header, Domain Manager, Object Class
and Serial Number)
ESD ElectroStatic Discharge
FCS Flip Chip Strap
FM0 Bi phase space modulation
G2 Generation 2
HBM Human Body Model
IC Integrated Circuit
PSF Product Status Flag
PCB Printed Circuit Board
RF Radio Frequency
UHF Ultra High Frequency
TID Tag IDentifier SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
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NXP Semiconductors SL3S1003_1013
UCODE G2iM and G2iM+
17. References
[1] EPCglobal: EPC Radio-Frequency Identity Protocols Class-1 Generation-2 UHF
RFID Protocol for Communications at 860 MHz – 960 MHz, Version 1.1.0
(December 17, 2005)
[2] EPCglobal: EPC Tag Data Standards
[3] EPCglobal (2004): FMCG RFID Physical Requirements Document (draft)
[4] EPCglobal (2004): Class-1 Generation-2 UHF RFID Implementation Reference
(draft)
[5] European Telecommunications Standards Institute (ETSI), EN 302 208:
Electromagnetic compatibility and radio spectrum matters (ERM) – Radio-frequency
identification equipment operating in the band 865 MHz to 868 MHz with power
levels up to 2 W, Part 1 – Technical characteristics and test methods
[6] European Telecommunications Standards Institute (ETSI), EN 302 208:
Electromagnetic compatibility and radio spectrum matters (ERM) – Radio-frequency
identification equipment operating in the band 865 MHz to 868 MHz with power
levels up to 2 W, Part 2 – Harmonized EN under article 3.2 of the R&TTE directive
[7] [CEPT1]: CEPT REC 70-03 Annex 1
[8] [ETSI1]: ETSI EN 330 220-1, 2
[9] [ETSI3]: ETSI EN 302 208-1, 2 V<1.1.1> (2004-09-Electromagnetic compatibility
And Radio spectrum Matters (ERM) Radio Frequency Identification Equipment
operating in the band 865 - MHz to 868 MHz with power levels up to 2 W Part 1:
Technical characteristics and test methods.
[10] [FCC1]: FCC 47 Part 15 Section 247
[11] ISO/IEC Directives, Part 2: Rules for the structure and drafting of International
Standards
[12] ISO/IEC 3309: Information technology – Telecommunications and information
exchange between systems – High-level data link control (HDLC) procedures –
Frame structure
[13] ISO/IEC 15961: Information technology, Automatic identification and data capture –
Radio frequency identification (RFID) for item management – Data protocol:
application interface
[14] ISO/IEC 15962: Information technology, Automatic identification and data capture
techniques – Radio frequency identification (RFID) for item management – Data
protocol: data encoding rules and logical memory functions
[15] ISO/IEC 15963: Information technology — Radio frequency identification for item
management — Unique identification for RF tags
[16] ISO/IEC 18000-1: Information technology — Radio frequency identification for item
management — Part 1: Reference architecture and definition of parameters to be
standardized
[17] ISO/IEC 18000-6: Information technology automatic identification and data capture
techniques — Radio frequency identification for item management air interface —
Part 6: Parameters for air interface communications at 860–960 MHz
[18] ISO/IEC 19762: Information technology AIDC techniques – Harmonized vocabulary
– Part 3: radio-frequency identification (RFID) SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
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Rev. 3.6 — 17 October 2014
201236 39 of 43
NXP Semiconductors SL3S1003_1013
UCODE G2iM and G2iM+
[19] U.S. Code of Federal Regulations (CFR), Title 47, Chapter I, Part 15:
Radio-frequency devices, U.S. Federal Communications Commission.
[20] Data sheet - Delivery type description – General specification for 8” wafer on
UV-tape with electronic fail die marking, BU-ID document number: 1093**3
3. ** ... document version numberSL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.6 — 17 October 2014
201236 40 of 43
NXP Semiconductors SL3S1003_1013
UCODE G2iM and G2iM+
18. Revision history
Table 41. Revision history
Document ID Release date Data sheet status Change notice Supersedes
SL2S1003_1013 v. 3.6 20141017 Product data sheet - SL2S1003_1013 v. 3.5
Modifications: • Table 21 “User Memory Configuration with 2 areas (no Access password protected area)”:
corrected
• Table 39 “G2iM+ RF interface characteristics (RFN, RFP)”: corrected
SL2S1003_1013 v. 3.5 20131107 Product data sheet - SL2S1003_1013 v. 3.4
Modifications: • Table 1 “Ordering information”: updated
• Table 2 “Marking codes”: updated
• Section 2.2 “Key benefits”: title updated
• Table 39 “G2iM+ RF interface characteristics (RFN, RFP)”: title updated
SL2S1003_1013 v. 3.4 20120227 Product data sheet - SL2S1003_1013 v. 3.3
Modifications: • Figure 4 “SL3S10x3 wafer layout”: Figure notes (1) and (2) updated
SL2S1003_1013 v. 3.3 20120130 Product data sheet SL2S1003_1013 v. 3.2
Modifications: • Section 14 “Handling information”: added
SL2S1003_1013 v. 3.2 20120111 Product data sheet - SL2S1003_1013 v. 3.1
Modifications: • Section 8.1 “Wafer layout”: figure notes (1), (2), (8) and (9) updated
SL2S1003_1013 v. 3.1 20111117 Product data sheet - SL2S1003_1013 v. 3.0
Modifications: • Security status changed into COMPANY PUBLIC
• Package delivery form SOT886 added
• Section 5 “Marking”, Section 13 “Package outline”: added
SL2S1003_1013 v. 3.0 20110503 Product data sheet - SL2S1003_1013 v. 2.0
Modifications: • Specification status changed into product
• Some EPC bit values changed
• Table 16 added
SL2S1003_1013 v. 2.0 20110415 Preliminary data sheet - -SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
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201236 41 of 43
NXP Semiconductors SL3S1003_1013
UCODE G2iM and G2iM+
19. Legal information
19.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification. SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
COMPANY PUBLIC
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UCODE G2iM and G2iM+
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
UCODE — is a trademark of NXP Semiconductors N.V.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.comNXP Semiconductors SL3S1003_1013
UCODE G2iM and G2iM+
© NXP Semiconductors N.V. 2014. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 17 October 2014
201236
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
21. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
2.1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.1.1 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2 Key benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2.1 End user benefit . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2.2 Antenna design benefits . . . . . . . . . . . . . . . . . . 2
2.2.3 Label manufacturer benefit. . . . . . . . . . . . . . . . 2
2.3 Custom commands. . . . . . . . . . . . . . . . . . . . . . 3
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Markets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 4
5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 6
7.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 Wafer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
8.1 Wafer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
9 Mechanical specification . . . . . . . . . . . . . . . . . 8
9.1 Wafer specification . . . . . . . . . . . . . . . . . . . . . . 8
9.1.1 Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
9.1.2 Fail die identification . . . . . . . . . . . . . . . . . . . . 9
9.1.3 Map file distribution. . . . . . . . . . . . . . . . . . . . . . 9
10 Functional description . . . . . . . . . . . . . . . . . . 10
10.1 Air interface standards . . . . . . . . . . . . . . . . . . 10
10.2 Power transfer . . . . . . . . . . . . . . . . . . . . . . . . 10
10.3 Data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . 10
10.3.1 Reader to tag Link . . . . . . . . . . . . . . . . . . . . . 10
10.3.2 Tag to reader Link. . . . . . . . . . . . . . . . . . . . . . 10
10.4 UCODE G2iM and UCODE G2iM+ differences 11
10.5 Supported commands . . . . . . . . . . . . . . . . . . 11
10.6 UCODE G2iM and UCODE G2iM+ memory . 12
10.6.1 UCODE G2iM and UCODE G2iM+ overall
memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 13
10.6.2 UCODE G2iM and UCODE G2iM+ TID
memory details . . . . . . . . . . . . . . . . . . . . . . . . 15
10.7 Custom commands. . . . . . . . . . . . . . . . . . . . . 16
10.7.1 ChangeConfig. . . . . . . . . . . . . . . . . . . . . . . . . 16
UCODE G2iM and UCODE G2iM+ special
features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
10.7.2 UCODE G2iM and UCODE G2iM+ special
features control mechanism . . . . . . . . . . . . . . 20
10.7.3 UCODE G2iM+ memory configuration control
mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10.7.4 Private Memory Segment . . . . . . . . . . . . . . . . 24
10.7.5 ReadProtect . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10.7.6 Reset ReadProtect2 . . . . . . . . . . . . . . . . . . . . 26
10.7.7 ChangeEAS2 . . . . . . . . . . . . . . . . . . . . . . . . . 28
10.7.8 EAS_Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . 29
11 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 31
12 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32
12.1 UCODE G2iM and UCODE G2iM+ bare die
characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32
12.2 UCODE G2iM+ SOT886 characteristics . . . . 34
13 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 35
14 Handling information . . . . . . . . . . . . . . . . . . . 36
14.1 Assembly conditions . . . . . . . . . . . . . . . . . . . 36
14.1.1 General assembly recommendations . . . . . . 36
14.1.2 Label converting. . . . . . . . . . . . . . . . . . . . . . . 36
15 Packing information . . . . . . . . . . . . . . . . . . . . 36
15.1 Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 37
17 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
18 Revision history . . . . . . . . . . . . . . . . . . . . . . . 40
19 Legal information . . . . . . . . . . . . . . . . . . . . . . 41
19.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 41
19.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
19.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 41
19.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 42
20 Contact information . . . . . . . . . . . . . . . . . . . . 42
21 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
1. General description
NXP’s UCODE G2iL series transponder ICs offer leading-edge read range and support
industry-first features such as a Tag Tamper Alarm, Data Transfer, Digital Switch, and
advanced privacy-protection modes.
Very high chip sensitivity (18 dBm) enables longer read ranges with simple, single-port
antenna designs. When connected to a power supply, the READ as well as the WRITE
range can be boosted to a sensitivity of 27 dBm. In fashion and retail the UCODE G2iL
series improve read rates and provide for theft deterrence. For consumer electronics the
UCODE G2iL series is suited for device configuration, activation, production control, and
PCB tagging. In authentication applications the transponders can be used to protect
brands and guard against counterfeiting. They can also be used to tag containers,
electronic vehicles, airline baggage, and more.
In addition to the EPC specifications the G2iL offers an integrated Product Status Flag
(PSF) feature and read protection of the memory content.
On top of the G2iL features the G2iL+ offers an integrated tag tamper alarm, RF field
detection, digital switch, external supply mode, read range reduction and data transfer
mode.
2. Features and benefits
2.1 Key features
UHF RFID Gen2 tag chip according EPCglobal v1.2.0 with 128 bit EPC memory
Memory read protection
Integrated Product Status Flag (PSF)
Tag tamper alarm
RF field detection
Digital switch
Data transfer mode
Real Read Range Reduction (Privacy Mode)
External supply mode where both the READ & WRITE range are boosted to -27dBm
2.1.1 Memory
128-bit of EPC memory
64-bit Tag IDentifier (TID) including 32-bit factory locked unique serial number
32-bit kill password to permanently disable the tag
32-bit access password to allow a transition into the secured state
SL3S1203_1213
UCODE G2iL and G2iL+
Rev. 4.4 — 17 March 2014
178844
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Data retention: 20 years
Broad international operating frequency: from 840 MHz to 960 MHz
Long read/write ranges due to extremely low power design
Reliable operation of multiple tags due to advanced anti-collision
READ protection
WRITE Lock
Wide specified temperature range: 40 C up to +85 C
2.2 Key benefits
2.2.1 End user benefit
Prevention of unauthorized memory access through read protection
Indication of tag tampering attempt by use of the tag tamper alarm feature
Electronic device configuration and / or activation by the use of the digital switch / data
transfer mode
Theft deterrence supported by the PSF feature (PSF alarm or EPC code)
Small label sizes, long read ranges due to high chip sensitivity
Product identification through unalterable extended TID range, including a 32-bit serial
number
Reliable operation in dense reader and noisy environments through high interference
suppression
2.2.2 Antenna design benefits
High sensitivity enables small and cost efficient antenna designs
Low Q-Value eases broad band antenna design for global usage
2.2.3 Label manufacturer benefit
Consistent performance on different materials due to low Q-factor
Ease of assembly and high assembly yields through large chip input capacitance
Fast first WRITE of the EPC memory for fast label initialization
2.3 Custom commands
PSF Alarm
Built-in PSF (Product Status Flag), enables the UHF RFID tag to be used as EAS tag
(Electronic Article Surveillance) tag without the need for a back-end data base.
Read Protect
Protects all memory content including CRC16 from unauthorized reading.
ChangeConfig
Configures the additional features of the chip like external supply mode, tamper alarm,
digital switch, read range reduction or data transfer.
The UCODE G2iL is equipped with a number of additional features and custom
commands. Nevertheless, the chip is designed in a way standard EPCglobal
READ/WRITE/ACCESS commands can be used to operate the features. No custom
commands are needed to take advantage of all the features in case of unlocked EPC
memory.SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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3. Applications
3.1 Markets
Fashion (Apparel and footwear)
Retail
Electronics
Fast Moving Consumer Goods
Asset management
Electronic Vehicle Identification
3.2 Applications
Supply chain management
Item level tagging
Pallet and case tracking
Container identification
Product authentication
PCB tagging
Cost efficient, low level seals
Wireless firmware download
Wireless product activation
Outside above mentioned applications, please contact NXP Semiconductors for support.
4. Ordering information
5. Marking
Table 1. Ordering information
Type number Package
Name IC type Description Version
SL3S1203FUF Wafer G2iL bumped die on sawn 8” 75 m wafer not applicable
SL3S1213FUF Wafer G2iL+ bumped die on sawn 8” 75 m wafer not applicable
SL3S1203FUD/BG Wafer G2iL bumped die on sawn 8” 120 m wafer,
7 m Polyimide spacer
not applicable
SL3S1213FUD/BG Wafer G2iL+ bumped die on sawn 8” 120 m wafer,
7 m Polyimide spacer
not applicable
SL3S1203FTB0 XSON6 G2iL plastic extremely thin small outline package;
no leads; 6 terminals; body 1 1.45 0.5 mm
SOT886F1
Table 2. Marking codes
Type number Marking code Comment Version
SL3S1203FTB0 UN UCODE G2iL SOT886SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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6. Block diagram
The SL3S12x3 IC consists of three major blocks:
- Analog Interface
- Digital Control
- EEPROM
The analog part provides stable supply voltage and demodulates data received from the
reader for being processed by the digital part. Further, the modulation transistor of the
analog part transmits data back to the reader.
The digital section includes the state machines, processes the protocol and handles
communication with the EEPROM, which contains the EPC and the user data.
Fig 1. Block diagram of G2iL IC
001aam226
MOD
DEMOD
VREG
VDD
VDD
data
in
data
out
R/W
ANALOG
RF INTERFACE
PAD
PAD
RECT
DIGITAL CONTROL
ANTENNA
ANTICOLLISION
READ/WRITE
CONTROL
ACCESS CONTROL
EEPROM INTERFACE
CONTROL
RF INTERFACE
CONTROL
I/O CONTROL
I/O
CONTROL
EEPROM
MEMORY
SEQUENCER
CHARGE PUMP
PAD
OUT
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7. Pinning information
7.1 Pin description
Fig 2. Pinning bare die Fig 3. Pin configuration for SOT886
001aam529
VDD
OUT RFN
NXP trademark RFP
SL3S12x3FTB0
n.c.
001aan103
RFP
RFN
n.c.
VDD
OUT
Transparent top view
2
3
1
5
4
6
Table 3. Pin description bare die
Symbol Description
OUT output pin
RFN grounded antenna connector
VDD external supply
RFP ungrounded antenna connector
Table 4. Pin description SOT886
Pin Symbol Description
1 RFP ungrounded antenna connector
2 n.c. not connected
3 RFN grounded antenna connector
4 OUT output pin
5 n.c. not connected
6 VDD external supplySL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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8. Wafer layout
8.1 Wafer layout
(1) Die to Die distance (metal sealring - metal sealring) 21,4 m, (X-scribe line width: 15 m)
(2) Die to Die distance (metal sealring - metal sealring) 21,4 m, (Y-scribe line width: 15 m)
(3) Chip step, x-length: 485 m
(4) Chip step, y-length: 435 m
(5) Bump to bump distance X (OUT - RFN): 383 m
(6) Bump to bump distance Y (RFN - RFP): 333 m
(7) Distance bump to metal sealring X: 40,3 m (outer edge - top metal)
(8) Distance bump to metal sealring Y: 40,3 m
Bump size X x Y: 60 m x 60 m
Remark: OUT and VDD are used with G2iL+ only
Fig 4. G2iL wafer layout
not to scale! 001aak871
(1)
(7)
(2)
(8)
(5)
(6) (4)
(3)
Y
X
VDD
OUT RFN
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9. Mechanical specification
The UCODE G2iL/G2iL+ wafers are available in 75 m and 120 m thickness. The 75m
thick wafer allows ultra thin label design but require a proper tuning of the glue dispenser
during production. Because of the more robust structure of the 120m wafer, the wafer is
ideal for harsh applications. The 120 m thick wafer is also enhanced with 7m Polyimide
spacer allowing additional protection of the active circuit.
9.1 Wafer specification
See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on
UV-tape with electronic fail die marking, BU-ID document number: 1093**”.
9.1.1 Wafer
Table 5. Specifications
Wafer
Designation each wafer is scribed with batch number
and wafer number
Diameter 200 mm (8”)
Thickness
SL3S12x3FUF 75 m 15 m
SL3S12x3FUD 120 m 15 m
Number of pads 4
Pad location non diagonal/ placed in chip corners
Distance pad to pad RFN-RFP 333.0 m
Distance pad to pad OUT-RFN 383.0 m
Process CMOS 0.14 m
Batch size 25 wafers
Potential good dies per wafer 139.351
Wafer backside
Material Si
Treatment ground and stress release
Roughness Ra max. 0.5 m, Rt max. 5 m
Chip dimensions
Die size including scribe 0.485 mm 0.435 mm = 0.211 mm2
Scribe line width: x-dimension = 15 m
y-dimension = 15 m
Passivation on front
Type Sandwich structure
Material PE-Nitride (on top)
Thickness 1.75 m total thickness of passivation
Polyimide spacer 7 m 1 m (SL3S12x3FUD only)
Au bump
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[1] Because of the 7 m spacer, the bump will measure 18 m relative height protruding the spacer.
9.1.2 Fail die identification
No inkdots are applied to the wafer.
Electronic wafer mapping (SECS II format) covers the electrical test results and
additionally the results of mechanical/visual inspection.
See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on
UV-tape with electronic fail die marking, BU-ID document number: 1093**”
9.1.3 Map file distribution
See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on
UV-tape with electronic fail die marking, BU-ID document number: 1093**”
10. Functional description
10.1 Air interface standards
The UCODE G2iL fully supports all parts of the "Specification for RFID Air Interface
EPCglobal, EPC Radio-Frequency Identity Protocols, Class-1 Generation-2 UHF RFID,
Protocol for Communications at 860 MHz to 960 MHz, Version 1.2.0".
10.2 Power transfer
The interrogator provides an RF field that powers the tag, equipped with a UCODE G2iL.
The antenna transforms the impedance of free space to the chip input impedance in order
to get the maximum possible power for the G2iL on the tag. The G2iL+ can also be
supplied externally.
The RF field, which is oscillating on the operating frequency provided by the interrogator,
is rectified to provide a smoothed DC voltage to the analog and digital modules of the IC.
Bump hardness 35 – 80 HV 0.005
Bump shear strength > 70 MPa
Bump height
SL3S12x3FUF 18 m
SL3S12x3FUD 25 m[1]
Bump height uniformity
within a die 2 m
– within a wafer 3 m
– wafer to wafer 4 m
Bump flatness 1.5 m
Bump size
– RFP, RFN 60 60 m
– OUT, VDD 60 60 m
Bump size variation 5 m
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The antenna that is attached to the chip may use a DC connection between the two
antenna pads. Therefore the G2iL also enables loop antenna design. Possible examples
of supported antenna structures can be found in the reference antenna design guide.
10.3 Data transfer
10.3.1 Reader to tag Link
An interrogator transmits information to the UCODE G2iL by modulating an UHF RF
signal. The G2iL receives both information and operating energy from this RF signal. Tags
are passive, meaning that they receive all of their operating energy from the interrogator's
RF waveform. In order to further improve the read range the UCODE G2iL+ can be
externally supplied as well so the energy to operate the chip does not need to be
transmitted by the reader.
An interrogator is using a fixed modulation and data rate for the duration of at least one
inventory round. It communicates to the G2iL by modulating an RF carrier using DSB-ASK
with PIE encoding.
For further details refer to Section 16, Ref. 1. Interrogator-to-tag (R=>T) communications.
10.3.2 Tag to reader Link
An interrogator receives information from a G2iL by transmitting an unmodulated RF
carrier and listening for a backscattered reply. The G2iL backscatters by switching the
reflection coefficient of its antenna between two states in accordance with the data being
sent. For further details refer to Section 16, Ref. 1, chapter 6.3.1.3.
The UCODE G2iL communicates information by backscatter-modulating the amplitude
and/or phase of the RF carrier. Interrogators shall be capable of demodulating either
demodulation type.
The encoding format, selected in response to interrogator commands, is either FM0
baseband or Miller-modulated subcarrier.
10.4 G2iL and G2iL+ differences
The UCODE G2iL is tailored for application where mainly EPC or TID number space is
needed. The G2iL+ in addition provides functionality such as tag tamper alarm, external
supply operation to further boost read/write range (external supply mode), a Privacy mode
reducing the read range or I/O functionality (data transfer to externally connected devices)
required.
The following table provides an overview of G2iL, G2iL+ special features.
Table 6. Overview of G2iL and G2iL+ features
Features G2iL G2iL+
Read protection (bankwise) yes yes
PSF (Built-in Product Status Flag) yes yes
Backscatter strength reduction yes yes
Real read range reduction yes yes
Digital switch / Digital input - yes
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10.5 Supported commands
The G2iL supports all mandatory EPCglobal V1.2.0 commands.
In addition the G2iL supports the following optional commands:
• ACCESS
• Block Write (32 bit)
The G2iL features the following custom commands described more in detail later:
• ResetReadProtect (backward compatible to G2X)
• ReadProtect (backward compatible to G2X)
• ChangeEAS (backward compatible to G2X)
• EAS_Alarm (backward compatible to G2X)
• ChangeConfig (new with G2iL)
10.6 G2iL, G2iL+ memory
The G2iL, G2iL+ memory is implemented according EPCglobal Class1Gen2 and
organized in three sections:
The logical address of all memory banks begin at zero (00h).
In addition to the three memory banks one configuration word to handle the G2iL specific
features is available at EPC bank 01 address 200h. The configuration word is described in
detail in Section 10.7.1 “ChangeConfig”.
Memory pages (16 bit words) pre-programmed to zero will not execute an erase cycle
before writing data to it. This approach accelerates initialization of the chip and enables
faster programming of the memory.
RF field detection - yes
Data transfer - yes
Tag tamper alarm - yes
Table 6. Overview of G2iL and G2iL+ features …continued
Features G2iL G2iL+
Table 7. G2iL memory sections
Name Size Bank
Reserved memory (32 bit ACCESS and 32 bit KILL password) 64 bit 00b
EPC (excluding 16 bit CRC-16 and 16 bit PC) 128 bit 01b
G2iL Configuration Word 16 bit 01b
TID (including permalocked unique 32 bit serial number) 64 bit 10bSL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.6.1 G2iL, G2iL+ overall memory map
[1] See Figure 5
[2] Indicates the existence of a Configuration Word at the end of the EPC number
[3] See also Table 12 for further details.
Table 8. G2iL, G2iL+ overall memory map
Bank
address
Memory
address
Type Content Initial Remark
Bank 00 00h to 1Fh reserved kill password all 00h unlocked memory
20h to 3Fh reserved access password all 00h unlocked memory
Bank 01
EPC
00h to 0Fh EPC CRC-16: refer to Ref. 16 memory mapped
calculated CRC
10h to 14h EPC backscatter length 00110b unlocked memory
15h EPC UMI 0b unlocked memory
16h EPC XPC indicator 0b hardwired to 0
17h to 1Fh EPC numbering system indicator 00h unlocked memory
20h to 9Fh EPC EPC [1] unlocked memory
Bank 01
Config Word
200h EPC tamper alarm flag 0b[3] indicator bit
201h EPC external supply flag or input
signal
0b[3] indicator bit
202h EPC RFU 0b[3] locked memory
203h EPC RFU 0b[3] locked memory
204h EPC invert digital output: 0b[3] temporary bit
205h EPC transparent mode on/off 0b[3] temporary bit
206h EPC transparent mode data/raw 0b[3] temporary bit
207h EPC RFU 0b[3] locked memory
208h EPC RFU 0b[3] locked memory
209h EPC max. backscatter strength 1b[3] unlocked memory
20Ah EPC digital output 0b[3] unlocked memory
20Bh EPC read range reduction on/off 0b[3] unlocked memory
20Ch EPC RFU 0b[3] locked memory
20Dh EPC read protect EPC Bank 0b[3] unlocked memory
20Eh EPC read protect TID 0b[3] unlocked memory
20Fh EPC PSF alarm flag 0b[3] unlocked memory
Bank 10
TID
00h to 07h TID allocation class identifier 1110 0010b locked memory
08h to 13h TID tag mask designer identifier 0000 0000 0110b locked memory
14h TID config word indicator 1b[2] locked memory
14h to 1Fh TID tag model number TMNR[1] locked memory
20h to 3Fh TID serial number SNR locked memoryxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
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UCODE G2iL and G2iL+
10.6.2 G2iL TID memory details
Fig 5. G2iL TID memory structure
aaa-010217
E2006906 E2h 006h 1 0010b 0000110b
Ucode G2iL+ E2006807 E2h 006h 1 0000b 0000111b
E2006907 E2h 006h 1 0010b 0000111b
Ucode G2iL E2006806 E2h 006h 1 0000b 0000110b
First 32 bit of TID
memory
Class ID
Mask
Designer
ID Config Word Indicator Sub Version Nr.
Model Number
Version
(Silicon) Nr.
Class Identifier
MS Byte
MS Bit LS Bit
LS Byte
TID
MS Bit LS Bit
Mask-Designer Identifier Model Number Serial Number
Bits 7 0 00 11 11 31 0
Addresses 00h 07h 13h 1Fh 3Fh
Addresses 00h 3Fh
08h 14h 20h
E2h
(EAN.UCC)
006h
(NXP)
806h or 906h or B06h
(UCODE G2iL)
00000001h to FFFFFFFFh
Sub Version Number Version Number
000b or 001b or 0110b 0000110b
(UCODE G2iL)
Bits 0 3 0 6 0
Addresses 14h 18h 19h 1Fh
E2006B06 E2h 006h 1 0110b 0000110b
E2006B07 E2h 006h 1 0110b 0000111bSL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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UCODE G2iL and G2iL+
10.7 Custom commands
The UCODE G2iL, G2iL+ is equipped with a number of additional features and custom
commands.
Nevertheless, the chip is designed in a way standard EPCglobal READ/WRITE/ACCESS
commands can be used to operate the features.
The memory map stated in the previous section describes the Configuration Word used to
control the additional features located at address 200h of the EPC memory. For this
reason the standard READ/WRITE commands of an UHF EPCglobal compliant reader
can be used to select the flags or activate/deactivate features.
The features can only be activated/deactivated (written) using standard EPC WRITE
command as long the EPC is not locked. In case the EPC is locked either the bank needs
to be unlocked to apply changes or the ChangeConfig custom command is used to
change the settings.
The UCODE G2iL is also equipped with the complete UCODE G2X command set for
backward compatibility reasons. Nevertheless, the one ChangeConfig command of the
G2iL can be used instead of the entire G2X command set.
Bit 14h of the TID indicates the existence of a Configuration Word. This flag will enable
selecting Config-Word enhanced transponders in mixed tag populations.
10.7.1 ChangeConfig
Although G2iL is tailored for supply chain management, item level tagging and product
authentication the G2iL+ version enables active interaction with products. Among the
password protected features are the capability of download firmware to electronics,
activate/deactivate electronics which can also be used as theft deterrence, a dedicated
privacy mode by reducing the read range, integrated PSF (Product Status Flag) or Tag
Tamper Alarm.
The G2iL ChangeConfig custom command allows handling the special NXP
Semiconductors features described in the following paragraph. Please also see the
memory map in Section 10.6 “G2iL, G2iL+ memory” and “Section 10.7.2 “G2iL, G2iL+
special features control mechanism”. If the EPC memory is not write locked the standard
EPC READ/WRITE command can be used to change the settings.
G2iL, G2iL+ special features1
UCODE G2iL and G2iL+ common special features are:
• Bank wise read protection (separate for EPC and TID)
EPC bank and the serial number part of the TID can be read protected independently.
When protected reading of the particular memory will return '0'. The flags of the
configuration word can be selected using the standard SELECT2 command. Only
read protected parts will then participate an inventory round. The G2X ReadProtect
command will set both EPC and TID read protect flags.
1. The features can only be manipulated (enabled/disabled) with unlocked EPC bank, otherwise the ChangeConfig command can be
used.
2. SELECT has to be applied onto the Configuration Word with pointer address 200h. Selecting bits within the Configuration Word
using a pointer address not equal to 200h is not possible.SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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UCODE G2iL and G2iL+
• Integrated PSF (Product Status Flag)
The PSF is a general purpose flag that can be used as an EAS (Electronic Article
Surveillance) flag, quality checked flag or similar.
The G2iL offers two ways of detecting an activated PSF. In cases extremely fast
detection is needed the EAS_Alarm command can be used. The UCODE G2iL will
reply a 64-bit alarm code like described in section EAS_Alarm upon sending the
command. As a second option the EPC SELECT2 command selecting the PSF flag of
the configuration word can be used. In the following inventory round only PSF
enabled chips will reply their EPC number.
• Backscatter strength reduction
The UCODE G2iL features two levels of backscatter strengths. Per default maximum
backscatter is enabled in order to enable maximum read rates. When clearing the flag
the strength can be reduced if needed.
• Real Read Range Reduction 4R
Some applications require the reduction of the read range to close proximity for
privacy reasons. Setting the 4R flag will significantly reduce the chip sensitivity to
+12 dBm. The +12 dBm have to be available at chip start up (slow increase of field
strength is not applicable). For additional privacy, the read protection can be activated
in the same configuration step. The related flag of the configuration word can be
selected using the standard SELECT2 command so only chips with reduced read
range will be part of an inventory.
Remark: The attenuation will result in only a few centimeter of read range at 36 dBm
EIRP!
UCODE G2iL+ specific special features are:1
• Tag Tamper Alarm (G2iL+ only)
The UCODE G2iL+ Tamper Alarm will flag the status of the VDD to OUT pad
connection which can be designed as an predetermined breaking point (see
Figure 6).
The status of the pad connection (open/closed) can be read in the configuration register
and/or selected using the EPC SELECT2. This feature will enable designing a wireless
RFID safety seal. When breaking the connection by peeling off the label or manipulating a
lock an alarm can be triggered.
Fig 6. Schematic of connecting VDD and OUT pad with a predetermined breaking point
to turn a standard RFID label into a wireless safety seal
001aam228
OUT VDD
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UCODE G2iL and G2iL+
• RF field detection (G2iL+ only)
The UCODE G2iL+ VDD pin can be also used as a RF field detector. Upon bringing
the tag within an RF field, a pulse signal will be immediately sent from the VDD test
pad. (for details see Ref. 21).
• Digital Switch (G2iL+ only)
The UCODE G2iL+ OUT pin can be used as digital switch. The state of the output pad
can be switched to VDD or GND depending on the Digital OUT bit of the Configuration
Word register. The state of the output is persistent in the memory even after KILL or
switching off the supply. This feature will allow activating/deactivating externally
connected peripherals or can be used as theft deterrence of electronics.
The state of the OUT pin can also be changed temporary by toggling the 'Invert Digital
Output' bit.
• Data transfer Mode (G2iL+ only)
In applications where not switching the output like described in "Digital Switch" but
external device communication is needed the G2iL+ Data Transfer Mode can be used
by setting the according bit of the Configuration Word register. When activated the air
interface communication will be directly transferred to the OUT pad of the chip.
Two modes of data transfer are available and can be switched using the Transparent
Mode DATA/RAW bit.
The default Transparent Mode DATA will remove the Frame Sync of the
communication and toggle the output with every raising edge in the RF field. This will
allow implementing a Manchester type of data transmission.
The Transparent Mode RAW will switch the demodulated air interface communication
to the OUT pad.
• External Supply Indicator - Digital Input (G2iL+ only)
The VDD pad of the UCODE G2iL+ can be used as a single bit digital input pin. The
state of the pad is directly associated with the External Supply Indicator bit of the
configuration register. Simple one bit return signaling (chip to reader) can be
implemented by polling this Configuration Word register flag. RF reset is necessary
for proper polling.
• External Supply Mode (G2iL+ only)
The UCODE G2iL+ can be supplied externally by connecting 1.85 V (Iout = 0µA)
supply. When externally supplied less energy from the RF field is needed to operate
the chip. This will not just enable further improved sensitivity and read ranges (up to
27 dBm) but also enable a write range that is equal to the read range.
The figure schematically shows the supply connected to the UCODE G2iL+.
Remark: When permanently externally supplied there will not be a power-on-reset. This
will result in the following limitations:
• When externally supplied session flag S0 will keep it’s state during RF-OFF phase.
• When externally supplied session flag S2, S3, SL will have infinite persistence time
and will behave similar to S0.
• Session flag S1 will behave regular like in pure passive operation.SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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UCODE G2iL and G2iL+
The bits to be toggled in the configuration register need to be set to '1'.
E.g. sending 0000 0000 0001 0001 XOR RN16 will activate the 4R and PSF. Sending the
very same command a second time will disable the features again.
The reply of the ChangeConfig will return the current register setting.
Fig 7. Schematic of external power supply
Table 9. ChangeConfig custom command
Command RFU Data RN CRC-16
No. of bits 16 8 16 16 16
Description 11100000
00000111
00000000 Toggle bits
XOR RN 16
handle -
Table 10. ChangeConfig custom command reply
Header Status bits RN CRC-16
No. of bits 1 16 16 16
Description 0 Config-Word Handle -
Table 11. ChangeConfig command-response table
Starting state Condition Response Next state
ready all - ready
arbitrate, reply,
acknowledged
all - arbitrate
open valid handle Status word
needs to change
Backscatter unchanged
Config-WordConfig-Word
immediately
open
valid handle Status word does
not need to change
Backscatter Config-Word
immediately
open
secured valid handle Status word
needs to change
Backscatter modified
Config-Word, when done
secured
valid handle Status word does
not need to change
Backscatter Config-Word
immediately
secured
killed all - killed
001aam229
OUT VDD
Vsupply
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UCODE G2iL and G2iL+
The features can only be activated/deactivated using standard EPC WRITE if the EPC
bank is unlocked. The permanent and temporary bits of the Configuration Word can be
toggled without the need for an ACCESS password in case the ACCESS password is set
to zero. In case the EPC bank is locked the lock needs to be removed before applying
changes or the ChangeConfig command has to be used.
10.7.2 G2iL, G2iL+ special features control mechanism
Special features of the G2iL are managed using a configuration word (Config-Word)
located at address 200h in the EPC memory bank.
The entire Config-Word is selectable (using the standard EPC SELECT2 command) and
can be read using standard EPC READ command and modified using the standard EPC
WRITE or ChangeConfig custom command in case the EPC memory is locked for writing.
ChangeConfig can be executed from the OPEN and SECURED state.
The chip will take all “Toggle Bits” for ’0’ if the chip is in the OPEN state or the ACCESS
password is zero; therefore it will not alter any status bits, but report the current status
only. The command will be ignored with an invalid CRC-16 or an invalid handle. The chip
will then remain in the current state. The CRC-16 is calculated from the first
command-code bit to the last handle bit.
A ChangeConfig command without frame-sync and proceeding Req_RN will be ignored.
The command will also be ignored if any of the RFU bits are toggled.
In order to change the configuration, to activate/deactivate a feature a ’1’ has to be written
to the corresponding register flag to toggle the status. E.g. sending 0x0002 to the register
will activate the read protection of the TID. Sending the same command a second time will
again clear the read protection of the TID. Invalid toggling on indicator or RFU bits are
ignored.
Executing the command with zero as payload or in the OPEN state will return the current
register settings. The chip will reply to a successful ChangeConfig with an extended
preamble regardless of the TRext value of the Query command.
After sending a ChangeConfig an interrogator shall transmit CW for less than TReply or
20 ms, where TReply is the time between the interrogator's ChangeConfig command and
the chip’s backscattered reply. An interrogator may observe three possible responses
after sending a ChangeConfig, depending on the success or failure of the operation
• ChangeConfigChangeConfig succeeded: The chip will backscatter the reply shown
above comprising a header (a 0-bit), the current Status Word setting, the handle, and
a CRC-16 calculated over the 0-bit, the status word and the handle. If the interrogator
observes this reply within 20 ms then the ChangeConfig completed successfully.
• The chip encounters an error: The chip will backscatter an error code during the CW
period rather than the reply shown below (see EPCglobal Spec for error-code
definitions and for the reply format).
• ChangeConfig does not succeed: If the interrogator does not observe a reply within
20 ms then the ChangeStatus did not complete successfully. The interrogator may
issue a Req_RN command (containing the handle) to verify that the chip is still in the
interrogator's field, and may reissue the ChangeConfig command.
The G2iL configuration word is located at address 200h of the EPC memory and is
structured as following:SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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UCODE G2iL and G2iL+
The configuration word contains three different type of bits:
• Indicator bits cannot be changed by command:
Tag Tamper Alarm Indicator
External Supply Indicator (digital input)
• Temporary bits are reset at power up:
Invert Output
Transparent Mode on/off
Data Mode data/raw
• Permanent bits: permanently stored bits in the memory
Max. Backscatter Strength
Digital Output
Read Range Reduction
Read Protect EPC
Read Protect TID
PSF Alarm
10.7.3 ReadProtect3
The G2iL ReadProtect custom command enables reliable read protection of the entire
G2iL memory. Executing ReadProtect from the Secured state will set the ProtectEPC and
ProtectTID bits of the Configuration Word to '1'. With the ReadProtect-Bit set the G2iL will
continue to work unaffected but veil its protected content.
The read protection can be removed by executing Reset ReadProtect. The
ReadProtect-Bits will than be cleared.
Devices whose access password is zero will ignore the command. A frame-sync must be
pre-pended the command.
After sending the ReadProtect command an interrogator shall transmit CW for the lesser
of TReply or 20 ms, where TReply is the time between the interrogator's ReadProtect
command and the backscattered reply. An interrogator may observe three possible
responses after sending a ReadProtect, depending on the success or failure of the
operation:
Table 12. Address 200h to 207h
Indicator bits Temporary bits
Tamper
indicator
External supply
indicator
RFU RFU Invert Output Transparent
mode on/off
Data mode
data/raw
RFU
0 1 2 34 5 6 7
Table 13. Address 208h to 20Fh
Permanent bits
RFU max. backscatter
strength
Digital
output
Privacy
mode
RFU Protect EPC Protect TID PSF Alarm
bit
8 9 10 11 12 13 14 15
3. Note: The ChangeConfig command can be used instead of “ReadProtect”, “ResetReadProtect”, “ChangeEAS”.SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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UCODE G2iL and G2iL+
• ReadProtect succeeds: After completing the ReadProtect the G2iL shall backscatter
the reply shown in Table 15 comprising a header (a 0-bit), the tag's handle, and a
CRC-16 calculated over the 0-bit and handle. Immediately after this reply the G2iL will
render itself to this ReadProtect mode. If the interrogator observes this reply within
20 ms then the ReadProtect completed successfully.
• The G2iL encounters an error: The G2iL will backscatter an error code during the CW
period rather than the reply shown in the EPCglobal Spec (see Annex I for error-code
definitions and for the reply format).
• ReadProtect does not succeed: If the interrogator does not observe a reply within
20 ms then the ReadProtect did not complete successfully. The interrogator may
issue a Req_RN command (containing the handle) to verify that the G2iL is still in the
interrogation zone, and may re-initiate the ReadProtect command.
The G2iL reply to the ReadProtect command will use the extended preamble shown in
EPCglobal Spec (Figure 6.11 or Figure 6.15), as appropriate (i.e. a Tag shall reply as if
TRext=1) regardless of the TRext value in the Query that initiated the round.
10.7.4 Reset ReadProtect3
Reset ReadProtect allows an interrogator to clear the ProtectEPC and ProtectTID bits of
the Configuration Word. This will re-enable reading of the related G2iL memory content.
For details on the command response please refer to Table 17 “Reset ReadProtect
command”.
Table 14. ReadProtect command
Command RN CRC-16
# of bits 16 16 16
description 11100000 00000001 handle -
Table 15. G2iL reply to a successful ReadProtect procedure
Header RN CRC-16
# of bits 1 16 16
description 0 handle -
Table 16. ReadProtect command-response table
Starting State Condition Response Next State
ready all – ready
arbitrate, reply,
acknowledged
all – arbitrate
open all - open
secured valid handle & invalid
access password
– arbitrate
valid handle & valid
non zero access
password
Backscatter handle,
when done
secured
invalid handle – secured
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After sending a Reset ReadProtect an interrogator shall transmit CW for the lesser of
TReply or 20 ms, where TReply is the time between the interrogator's Reset ReadProtect
command and the G2iL backscattered reply. A Req_RN command prior to the Reset
ReadProtect is necessary to successfully execute the command. A frame-sync must be
pre-pended the command.
An interrogator may observe three possible responses after sending a Reset
ReadProtect, depending on the success or failure of the operation:
• Reset ReadProtect succeeds: After completing the Reset ReadProtect a G2iL will
backscatter the reply shown in Table 18 comprising a header (a 0-bit), the handle, and
a CRC-16 calculated over the 0-bit and handle. If the interrogator observes this reply
within 20 ms then the Reset ReadProtect completed successfully.
• The G2iL encounters an error: The G2iL will backscatter an error code during the CW
period rather than the reply shown in Table 18 (see EPCglobal Spec for error-code
definitions and for the reply format).
• Reset ReadProtect does not succeed: If the interrogator does not observe a reply
within 20 ms then the Reset ReadProtect did not complete successfully. The
interrogator may issue a Req_RN command (containing the handle) to verify that the
G2iL is still in the interrogation zone, and may reissue the Reset ReadProtect
command.
The G2iL reply to the Reset ReadProtect command will use the extended preamble
shown in EPCglobal Spec (Figure 6.11 or Figure 6.15), as appropriate (i.e. a G2iL will
reply as if TRext=1 regardless of the TRext value in the Query that initiated the round.
The Reset ReadProtect command is structured as following:
• 16 bit command
• Password: 32 bit Access-Password XOR with 2 times current RN16
Remark: To generate the 32 bit password the 16 bit RN16 is duplicated and used two
times to generate the 32 bit (e.g. a RN16 of 1234 will result in 1234 1234).
• 16 bit handle
• CRC-16 calculate over the first command-code bit to the last handle bit
Table 17. Reset ReadProtect command
Command Password RN CRC-16
# of bits 16 32 16 16
description 11100000
00000010
(access
password)
2*RN16
handle -
Table 18. G2iL reply to a successful Reset ReadProtect command
Header RN CRC-16
# of bits 1 16 16
description 0 handle -SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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UCODE G2iL and G2iL+
10.7.5 ChangeEAS3
UCODE G2iL equipped RFID tags will also feature a stand-alone operating EAS alarm
mechanism for fast and offline electronic article surveillance. The PSF bit of the
Configuration Word directly relates to the EAS Alarm feature. With an PSF bit set to '1' the
tag will reply to an EAS_Alarm command by backscattering a 64 bit alarm code without
the need of a Select or Query. The EAS is a built-in solution so no connection to a
backend database is required. In case the EAS_Alarm command is not implemented in
the reader a standard EPC SELCET to the Configuration Word and Query can be used.
When using standard SELECT/QUERY the EPC will be returned during inventory.
ChangeEAS can be executed from the Secured state only. The command will be ignored
if the Access Password is zero, the command will also be ignored with an invalid CRC-16
or an invalid handle, the G2iL will than remain in the current state. The CRC-16 is
calculated from the first command-code bit to the last handle bit. A frame-sync must be
pre-pended the command.
The G2iL reply to a successful ChangeEAS will use the extended preamble, as
appropriate (i.e. a Tag shall reply as if TRext=1) regardless of the TRext value in the
Query that initiated the round.
After sending a ChangeEAS an interrogator shall transmit CW for less than TReply or
20 ms, where TReply is the time between the interrogator's ChangeEAS command and the
G2iL backscattered reply. An interrogator may observe three possible responses after
sending a ChangeEAS, depending on the success or failure of the operation
• ChangeEAS succeeds: After completing the ChangeEAS a G2iL will backscatter the
reply shown in Table 21 comprising a header (a 0-bit), the handle, and a CRC-16
calculated over the 0-bit and handle. If the interrogator observes this reply within
20 ms then the ChangeEAS completed successfully.
• The G2iL encounters an error: The G2iL will backscatter an error code during the CW
period rather than the reply shown in Table 21 (see EPCglobal Spec for error-code
definitions and for the reply format).
Table 19. Reset ReadProtect command-response table
Starting State Condition Response Next State
ready all – ready
arbitrate, reply,
acknowledged
all – arbitrate
open valid handle & valid access password Backscatter handle,
when done
open
valid handle & invalid access password – arbitrate
invalid handle – open
secured valid handle & valid access password Backscatter handle,
when done
secured
valid handle & invalid access password – arbitrate
invalid handle – secured
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UCODE G2iL and G2iL+
• ChangeEAS does not succeed: If the interrogator does not observe a reply within
20 ms then the ChangeEAS did not complete successfully. The interrogator may
issue a Req_RN command (containing the handle) to verify that the G2iL is still in the
interrogator's field, and may reissue the ChangeEAS command.
Upon receiving a valid ChangeEAS command a G2iL will perform the commanded
set/reset operation of the PSF bit of the Configuration Word.
If PSF bit is set, the EAS_Alarm command will be available after the next power up and
reply the 64 bit EAS code upon execution. Otherwise the EAS_Alarm command will be
ignored.
10.7.6 EAS_Alarm
Upon receiving an EAS_Alarm custom command the UCODE G2iL will immediately
backscatter an EAS-Alarmcode in case the PSF bit of the Configuration Word is set. The
alarm code is returned without any delay caused by Select, Query and without the need
for a backend database.
The EAS feature of the G2iL is available after enabling it by sending a ChangeEAS
command described in Section 10.7.5 “ChangeEAS3” or after setting the PSF bit of the
Configuration Word to ’1’. With the EAS-Alarm enabled the G2iL will reply to an
EAS_Alarm command by backscattering a fixed 64 bit alarm code. A G2iL will reply to an
EAS_Alarm command from the ready state only. As an alternative to the fast EAS_Alarm
command a standard SELECT2 (upon the Configuration Word) and QUERY can be used.
If the PSF bit is reset to '0' by sending a ChangeEAS command in the password protected
Secure state or clearing the PSF bit the G2iL will not reply to an EAS_Alarm command.
Table 20. ChangeEAS command
Command ChangeEAS RN CRC-16
# of bits 16 1 16 16
description 11100000
00000011
1 ... set PSF bit
0 ... reset PSF bit
handle
Table 21. G2iL reply to a successful ChangeEAS command
Header RN CRC-16
# of bits 1 16 16
description 0 handle -
Table 22. ChangeEAS command-response table
Starting State Condition Response Next state
ready all – ready
arbitrate, reply,
acknowledged
all – arbitrate
open all – open
secured valid handle backscatter handle,
when done
secured
invalid handle – secured
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UCODE G2iL and G2iL+
The EAS_Alarm command is structured as following:
• 16 bit command
• 16 bit inverted command
• DR (TRcal divide ratio) sets the T=>R link frequency as described in EPCglobal Spec.
6.3.1.2.8 and Table 6.9.
• M (cycles per symbol) sets the T=>R data rate and modulation format as shown in
EPCglobal Spec. Table 6.10.
• TRext chooses whether the T=>R preamble is pre-pended with a pilot tone as
described in EPCglobal Spec. 6.3.1.3.
A preamble must be pre-pended the EAS_Alarm command according EPCglobal Spec,
6.3.1.2.8.
Upon receiving an EAS_Alarm command the tag loads the CRC5 register with 01001b
and backscatters the 64 bit alarm code accordingly. The reader is now able to calculate
the CRC5 over the backscattered 64 bits received to verify the received code.
Table 23. EAS_Alarm command
Command Inv_Command DR M TRext CRC-16
# of bits 16 16 1 2 1 16
description 11100000
00000100
00011111
11111011
0: DR = 8
1: DR = 64/3
00: M = 1
01: M = 2
10: M = 4
11: M = 8
0: no pilot
tone
1: use pilot
tone
-
Table 24. G2iL reply to a successful EAS_Alarm command
Header EAS Code
# of bits 1 64
description 0 CRC5 (MSB)
Table 25. EAS_Alarm command-response table
Starting State Condition Response Next state
ready PSF bit is set
PSF bit is cleard
backscatter alarm code
--
ready
arbitrate, reply,
acknowledged
all – arbitrate
open all – open
secured all – secured
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UCODE G2iL and G2iL+
11. Limiting values
[1] Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any conditions other
than those described in the Operating Conditions and Electrical Characteristics section of this specification
is not implied.
[2] This product includes circuitry specifically designed for the protection of its internal devices from the
damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be
taken to avoid applying greater than the rated maxima.
[3] For ESD measurement, the die chip has been mounted into a CDIP20 package.
Table 26. Limiting values[1][2]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages are referenced to RFN
Symbol Parameter Conditions Min Max Unit
Bare die and SOT886 limitations
Tstg storage temperature 55 +125 C
Tamb ambient temperature 40 +85 C
VESD electrostatic discharge
voltage
Human body
model
[3] - 2 kV
Pad limitations
Vi input voltage absolute limits,
VDD-OUT pad
0.5 +2.5 V
Io output current absolute limits
input/output
current, VDD-OUT
pad
0.5 +0.5 mA
Pi input power maximum power
dissipation, RFP
pad
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UCODE G2iL and G2iL+
12. Characteristics
12.1 UCODE G2iL, G2iL+ bare die characteristics
[1] Power to process a Query command.
[2] Measured with a 50 source impedance.
[3] At minimum operating power.
[4] It has to be assured the reader (system) is capable of providing enough field strength to give +12 dBm at the chip otherwise
communication with the chip will not be possible.
[5] Enables tag designs to be within ETSI limits for return link data rates of e.g. 320 kHz/M4.
[6] Will result in up to 10 dB higher tag backscatter power at high field strength.
[7] Results in approx. 18.5 dBm tag sensitivity on a 2 dBi gain antenna.
Table 27. G2iL, G2iL+ RF interface characteristics (RFN, RFP)
Symbol Parameter Conditions Min Typ Max Unit
fi input frequency 840 - 960 MHz
Normal mode - no external supply, read range reduction OFF
Pi(min) minimum input power READ sensitivity [1][2][7] - 18 - dBm
Pi(min) minimum input power WRITE sensitivity,
(write range/read
range - ratio)
- 30 - %
Ci input capacitance parallel [3] - 0.77 - pF
Q quality factor 915 MHz [3] - 9.7 - -
Z impedance 866 MHz [3] - 25 -j237 -
915 MHz [3] - 23 -j224 -
953 MHz [3] - 21 -j216 -
External supply mode - VDD pad supplied, read range reduction OFF
Pi(min) minimum input power Ext. supplied READ [1][2] - 27 - dBm
Ext. supplied WRITE [2] - 27 - dBm
Z impedance externally supplied,
915 MHz
[3] - 7 -j230 -
Read range reduction ON - no external supply
Pi(min) minimum input power 4R on READ [1][2][4] - +12 - dBm
4R on WRITE [2][4] - +12 - dBm
Z impedance 4R on, 915 MHz [3] - 18 -j2 -
Modulation resistance
R resistance modulation
resistance, max.
backscatter = off
[5] - 170 -
modulation
resistance, max.
backscatter = on
[6] - 55 - SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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[1] Activates Digital Output (OUT pin), increases read range (external supplied).
[2] Activates Digital Output (OUT pin), increases read and write range (external supplied).
[3] Operating the chip outside the specified voltage range may lead to undefined behaviour.
[4] Either the voltage or the current needs to be above given values to guarantee specified functionality.
[5] No proper operation is guaranteed if both, voltage and current, limits are exceeded.
[1] Is the sum of the allowed capacitance of the VDD and OUT pin referenced to RFN.
[2] Is the maximum allowed RF input voltage coupling to the VDD/OUT pin to guarantee undisturbed chip functionality.
[3] Resistance between VDD and OUT pin in checked during power up only.
[4] Resistance range to achieve tamper alarm flag = 1.
[5] Resistance range to achieve tamper alarm flag = 0:
Table 28. VDD pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
Minimum supply voltage/current - without assisted EEPROM WRITE [1][3][4]
VDD supply voltage minimum voltage - - 1.8 V
IDD supply current minimum current,
Iout-^- = 0 A
-- 7 A
Iout = 100 A -- 110 A
Minimum supply voltage/current - assisted EEPROM READ and WRITE [2][3][4]
VDD supply voltage minimum voltage,
Iout = 0 A
- 1.8 1.85 V
Iout = 100 A -- 1.95 V
IDD supply current minimum current,
Iout = 0 A
- - 125 A
Iout = 100 A -- 265 A
Maximum supply voltage/current [3][5]
VDD supply voltage absolute maximum
voltage
2.2 - - V
Ii(max) maximum input current absolute maximum
current
280 - - A
Table 29. G2iL, G2iL+ VDD and OUT pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
OUT pin characteristics
VOL Low-level output voltage Isink = 1 mA - - 100 mV
VOH HIGH-level output voltage VDD = 1.8 V; Isource
= 100 µA
1.5 - - V
VDD/OUT pin characteristics
CL load capacitance VDD - OUT pin max. [1] - - 5 pF
Vo output voltage maximum RF peak
voltage on VDD-OUT
pins
[2] - - 500 mV
VDD/OUT pin tamper alarm characteristics [3]
RL(max) maximum load resistance resistance range high [4] - - <2 M
RL(min) minimum load resistance resistance range low [5] >20 - - MSL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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For further reading we recommend application note “FAQ UCODE G2iL+“ (Ref. 21)
describing the output characteristics more in detail. An example schematic is available in
application note “UCODE G2iL+ Demo board Manual“ (Ref. 22). The documents are
available at NXP Document Control or at the website www.nxp.com.
[1] Tamb 25 C
12.2 UCODE G2iL SOT886 characteristics
[1] Power to process a Query command.
[2] Measured with a 50 source impedance.
[3] At minimum operating power.
Remark: For DC and memory characteristics refer to Table 28, Table 29 and Table 30.
Table 30. G2iL, G2iL+ memory characteristics
Symbol Parameter Conditions Min Typ Max Unit
EEPROM characteristics
tret retention time Tamb 55 C 20 - - year
Nendu(W) write endurance 1000 10000[1] - cycle
Table 31. G2iL RF interface characteristics (RFN, RFP)
Symbol Parameter Conditions Min Typ Max Unit
Normal mode - no external supply, read range reduction OFF
Pi(min) minimum input power READ
sensitivity
[1][2] - 17.6 - dB
m
Z impedance 915 MHz [3] - 21 j199 -
Normal mode - externally supplied, read range reduction OFF
Pi(min) minimum input power READ
sensitivity
[1][2] - 27 - dB
m
Z impedance 915 MHz [3] - 5.6 j204 - SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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13. Package outline
Fig 8. Package outline SOT886
Outline References
version
European
projection Issue date
IEC JEDEC JEITA
SOT886 MO-252
sot886_po
04-07-22
12-01-05
Unit
mm
max
nom
min
0.5 0.04 1.50
1.45
1.40
1.05
1.00
0.95
0.35
0.30
0.27
0.40
0.35
0.32
0.6
A(1)
Dimensions (mm are the original dimensions)
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886
A1 b
0.25
0.20
0.17
D E ee1
0.5
L L1
terminal 1
index area
D
E
e1
e
A1
b
L L 1
e1
0 1 2 mm
scale
1
6
2
5
3
4
6x
(2)
4x
(2)
ASL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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14. Packing information
14.1 Wafer
See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on
UV-tape with electronic fail die marking, BU-ID document number: 1093**”
14.2 SOT886
Part orientation T1. For details please refer to
http://www.standardics.nxp.com/packaging/packing/pdf/sot886.t1.t4.pdf
15. Abbreviations
Table 32. Abbreviations
Acronym Description
CRC Cyclic Redundancy Check
CW Continuous Wave
DSB-ASK Double Side Band-Amplitude Shift Keying
DC Direct Current
EAS Electronic Article Surveillance
EEPROM Electrically Erasable Programmable Read Only Memory
EPC Electronic Product Code (containing Header, Domain Manager, Object Class
and Serial Number)
FM0 Bi phase space modulation
G2 Generation 2
IC Integrated Circuit
PIE Pulse Interval Encoding
RRRR Real Read Range Reduction
PSF Product Status Flag
RF Radio Frequency
UHF Ultra High Frequency
SECS Semi Equipment Communication Standard
TID Tag IDentifier SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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16. References
[1] EPCglobal: EPC Radio-Frequency Identity Protocols Class-1 Generation-2 UHF
RFID Protocol for Communications at 860 MHz – 960 MHz, Version 1.1.0
(December 17, 2005)
[2] EPCglobal: EPC Tag Data Standards
[3] EPCglobal (2004): FMCG RFID Physical Requirements Document (draft)
[4] EPCglobal (2004): Class-1 Generation-2 UHF RFID Implementation Reference
(draft)
[5] European Telecommunications Standards Institute (ETSI), EN 302 208:
Electromagnetic compatibility and radio spectrum matters (ERM) – Radio-frequency
identification equipment operating in the band 865 MHz to 868 MHz with power
levels up to 2 W, Part 1 – Technical characteristics and test methods
[6] European Telecommunications Standards Institute (ETSI), EN 302 208:
Electromagnetic compatibility and radio spectrum matters (ERM) – Radio-frequency
identification equipment operating in the band 865 MHz to 868 MHz with power
levels up to 2 W, Part 2 – Harmonized EN under article 3.2 of the R&TTE directive
[7] [CEPT1]: CEPT REC 70-03 Annex 1
[8] [ETSI1]: ETSI EN 330 220-1, 2
[9] [ETSI3]: ETSI EN 302 208-1, 2 V<1.1.1> (2004-09-Electromagnetic compatibility
And Radio spectrum Matters (ERM) Radio Frequency Identification Equipment
operating in the band 865 - MHz to 868 MHz with power levels up to 2 W Part 1:
Technical characteristics and test methods.
[10] [FCC1]: FCC 47 Part 15 Section 247
[11] ISO/IEC Directives, Part 2: Rules for the structure and drafting of International
Standards
[12] ISO/IEC 3309: Information technology – Telecommunications and information
exchange between systems – High-level data link control (HDLC) procedures –
Frame structure
[13] ISO/IEC 15961: Information technology, Automatic identification and data capture –
Radio frequency identification (RFID) for item management – Data protocol:
application interface
[14] ISO/IEC 15962: Information technology, Automatic identification and data capture
techniques – Radio frequency identification (RFID) for item management – Data
protocol: data encoding rules and logical memory functions
[15] ISO/IEC 15963: Information technology — Radio frequency identification for item
management — Unique identification for RF tags
[16] ISO/IEC 18000-1: Information technology — Radio frequency identification for item
management — Part 1: Reference architecture and definition of parameters to be
standardized
[17] ISO/IEC 18000-6: Information technology automatic identification and data capture
techniques — Radio frequency identification for item management air interface —
Part 6: Parameters for air interface communications at 860–960 MHz
[18] ISO/IEC 19762: Information technology AIDC techniques – Harmonized vocabulary
– Part 3: radio-frequency identification (RFID) SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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[19] U.S. Code of Federal Regulations (CFR), Title 47, Chapter I, Part 15:
Radio-frequency devices, U.S. Federal Communications Commission.
[20] Data sheet - Delivery type description – General specification for 8” wafer on
UV-tape with electronic fail die marking, BU-ID document number: 1093**4
[21] Application note - FAQ UCODE G2i, BU-ID document number: AN10940
[22] Application note - UCODE G2iM+ demo board documentation, BU-ID document
number: AN11237
4. ** ... document version numberSL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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17. Revision history
Table 33. Revision history
Document ID Release date Data sheet status Change notice Supersedes
SL3S1203_1213 v.4.4 20140317 Product data sheet - SL3S1203_1213 v.4.3
Modifications: • Table 8 “G2iL, G2iL+ overall memory map”: Table notes updated
• Figure 5 “G2iL TID memory structure”: TIDs updated
SL3S1203_1213 v.4.3 20131127 Product data sheet - SL3S1203_1213 v.4.2
Modifications: • Figure 5 “G2iL TID memory structure”: updated
SL3S1203_1213 v.4.2 20130701 Product data sheet - SL3S1203_1213 v.4.1
Modifications: • Update of delivery form
• Update RF field detection
SL3S1203_1213 v.4.1 20120917 Product data sheet - SL3S1203_1213 v.4.0
Modifications: • Update of delivery form
SL3S1203_1213 v.4.0 20120227 Product data sheet - SL3S1203_1213 v.3.9
Modifications: • Figure 4 “G2iL wafer layout”: Figure notes (1) and (2) updated
SL3S1203_1213 v.3.9 20120130 Product data sheet - SL3S1203_1213 v.3.8
Modifications: • Table 6 “Specifications”: “Passivation on front” updated
• Section 15.2.1 “General assembly recommendations”: updated
SL3S1203_1213 v.3.8 20120111 Product data sheet - SL3S1203_1213 v.3.7
Modifications: • Section 8.1 “Wafer layout”: Figure notes (1) and (2) updated
SL3S1203_1213 v.3.7 20111124 Product data sheet - SL3S1203_1213 v.3.6
Modifications: • Table 11 “G2iL, G2iL+ overall memory map”: updated
• Table 34 “G2iL, G2iL+ RF interface characteristics (RFN, RFP)”: updated
SL3S1203_1213 v.3.6 20110803 Product data sheet - SL3S1203_1213 v.3.5
Modifications: • Real Read Range Reduction feature added to G2iL
SL3S1203_1213 v.3.5 20110531 Product data sheet - SL3S1203_1213 v.3.4
Modifications: • Superfluous text removed from Table 6
SL3S1203_1213 v.3.4 20110511 Product data sheet - SL3S1203_1213 v.3.3
Modifications: • Security status changed into COMPANY PUBLIC
• Delivery form of FCS2 strap added
• Section 13 “Package information”, Section 15 “Handling information” and Section 16
“Packing information” added
SL3S1203_1213 v.3.3 20110131 Product data sheet - SL3S1203_1213 v.3.2
Modifications: • Section 4 “Ordering information”: new types SL3S1203FUD and SL3S1213FUD added
• Section 9 “Mechanical specification”: updated according to the new types
• Replaced wording of “ChangeStatus” with “ChangeConfig”
SL3S1203_1213 v.3.2 20101109 Product data sheet - SL3S1203_1213 v.3.1
Modifications: • Version SOT886F1 added
• Section 5 “Marking”, Section 13 “Package outline” and Section 14 “Packing information”
added
SL3S1203_1213 v.3.1 20100922 Product data sheet - SL3S1203_1213 v.3.0
Modifications: • General Modifications
SL3S1203_1213 v.3.0 20100621 Product data sheet - 178810SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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Modifications: • General update
178810 20100304 Objective data sheet - -
Table 33. Revision history …continued
Document ID Release date Data sheet status Change notice SupersedesSL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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18. Legal information
18.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification. SL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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UCODE G2iL and G2iL+
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
UCODE — is a trademark of NXP Semiconductors N.V.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.comSL3S1203_1213 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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20. Tables
Table 1. Ordering information. . . . . . . . . . . . . . . . . . . . . .3
Table 2. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .3
Table 3. Pin description bare die . . . . . . . . . . . . . . . . . . .5
Table 4. Pin description SOT886 . . . . . . . . . . . . . . . . . . .5
Table 5. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 6. Overview of G2iL and G2iL+ features . . . . . . . .9
Table 7. G2iL memory sections . . . . . . . . . . . . . . . . . . .10
Table 8. G2iL, G2iL+ overall memory map. . . . . . . . . . . 11
Table 9. ChangeConfig custom command . . . . . . . . . . .16
Table 10. ChangeConfig custom command reply. . . . . . .16
Table 11. ChangeConfig command-response table . . . . .16
Table 12. Address 200h to 207h . . . . . . . . . . . . . . . . . . .18
Table 13. Address 208h to 20Fh . . . . . . . . . . . . . . . . . . .18
Table 14. ReadProtect command. . . . . . . . . . . . . . . . . . .19
Table 15. G2iL reply to a successful ReadProtect
procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 16. ReadProtect command-response table . . . . . .19
Table 17. Reset ReadProtect command . . . . . . . . . . . . .20
Table 18. G2iL reply to a successful Reset
ReadProtect command. . . . . . . . . . . . . . . . . . .20
Table 19. Reset ReadProtect command-response
table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 20. ChangeEAS command . . . . . . . . . . . . . . . . . . 22
Table 21. G2iL reply to a successful ChangeEAS
command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 22. ChangeEAS command-response table . . . . . . 22
Table 23. EAS_Alarm command . . . . . . . . . . . . . . . . . . . 23
Table 24. G2iL reply to a successful EAS_Alarm c
ommand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 25. EAS_Alarm command-response table . . . . . . 23
Table 26. Limiting values[1][2] . . . . . . . . . . . . . . . . . . . . . . 24
Table 27. G2iL, G2iL+ RF interface characteristics
(RFN, RFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 28. VDD pin characteristics . . . . . . . . . . . . . . . . . . 26
Table 29. G2iL, G2iL+ VDD and OUT
pin characteristics . . . . . . . . . . . . . . . . . . . . . . 26
Table 30. G2iL, G2iL+ memory characteristics . . . . . . . . 27
Table 31. G2iL RF interface characteristics
(RFN, RFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 32. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 33. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 32
21. Figures
Fig 1. Block diagram of G2iL IC . . . . . . . . . . . . . . . . . . .4
Fig 2. Pinning bare die. . . . . . . . . . . . . . . . . . . . . . . . . . .5
Fig 3. Pin configuration for SOT886 . . . . . . . . . . . . . . . .5
Fig 4. G2iL wafer layout. . . . . . . . . . . . . . . . . . . . . . . . . .6
Fig 5. G2iL TID memory structure . . . . . . . . . . . . . . . . .12
Fig 6. Schematic of connecting VDD and OUT pad
with a predetermined breaking point to turn a
standard RFID label into a wireless safety seal. .14
Fig 7. Schematic of external power supply . . . . . . . . . .16
Fig 8. Package outline SOT886. . . . . . . . . . . . . . . . . . .28NXP Semiconductors SL3S1203_1213
UCODE G2iL and G2iL+
© NXP Semiconductors N.V. 2014. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 17 March 2014
178844
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
22. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
2.1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.1.1 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.2 Key benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2.1 End user benefit . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2.2 Antenna design benefits . . . . . . . . . . . . . . . . . . 2
2.2.3 Label manufacturer benefit. . . . . . . . . . . . . . . . 2
2.3 Custom commands. . . . . . . . . . . . . . . . . . . . . . 2
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.1 Markets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3
5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
7.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Wafer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8.1 Wafer layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
9 Mechanical specification . . . . . . . . . . . . . . . . . 7
9.1 Wafer specification . . . . . . . . . . . . . . . . . . . . . . 7
9.1.1 Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
9.1.2 Fail die identification . . . . . . . . . . . . . . . . . . . . 8
9.1.3 Map file distribution. . . . . . . . . . . . . . . . . . . . . . 8
10 Functional description . . . . . . . . . . . . . . . . . . . 8
10.1 Air interface standards . . . . . . . . . . . . . . . . . . . 8
10.2 Power transfer . . . . . . . . . . . . . . . . . . . . . . . . . 8
10.3 Data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . 9
10.3.1 Reader to tag Link . . . . . . . . . . . . . . . . . . . . . . 9
10.3.2 Tag to reader Link. . . . . . . . . . . . . . . . . . . . . . . 9
10.4 G2iL and G2iL+ differences . . . . . . . . . . . . . . . 9
10.5 Supported commands . . . . . . . . . . . . . . . . . . 10
10.6 G2iL, G2iL+ memory . . . . . . . . . . . . . . . . . . . 10
10.6.1 G2iL, G2iL+ overall memory map. . . . . . . . . . 11
10.6.2 G2iL TID memory details . . . . . . . . . . . . . . . . 12
10.7 Custom commands. . . . . . . . . . . . . . . . . . . . . 13
10.7.1 ChangeConfig. . . . . . . . . . . . . . . . . . . . . . . . . 13
G2iL, G2iL+ special features . . . . . . . . . . . . . .13
10.7.2 G2iL, G2iL+ special features
control mechanism . . . . . . . . . . . . . . . . . . . . . 17
10.7.3 ReadProtect . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10.7.4 Reset ReadProtect3 . . . . . . . . . . . . . . . . . . . . 19
10.7.5 ChangeEAS3 . . . . . . . . . . . . . . . . . . . . . . . . . 21
10.7.6 EAS_Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . 22
11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 24
12 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25
12.1 UCODE G2iL, G2iL+ bare die characteristics 25
12.2 UCODE G2iL SOT886 characteristics . . . . . . 27
13 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 28
14 Packing information . . . . . . . . . . . . . . . . . . . . 29
14.1 Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
14.2 SOT886 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 29
16 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
17 Revision history . . . . . . . . . . . . . . . . . . . . . . . 32
18 Legal information . . . . . . . . . . . . . . . . . . . . . . 34
18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 34
18.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 34
18.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 35
19 Contact information . . . . . . . . . . . . . . . . . . . . 35
20 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
21 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
22 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
1. Introduction
This document describes the functionality and electrical specifications of the
transceiver IC PN512.
The PN512 is a highly integrated transceiver IC for contactless communication at
13.56 MHz. This transceiver IC utilizes an outstanding modulation and demodulation
concept completely integrated for different kinds of contactless communication methods
and protocols at 13.56 MHz.
1.1 Different available versions
The PN512 is available in three versions:
• PN5120A0HN1/C2 (HVQFN32), PN5120A0HN/C2 (HVQFN40) and PN5120A0ET/C2
(TFBGA64), hereafter named as version 2.0
• PN512AA0HN1/C2 (HVQFN32) and PN512AA0HN1/C2BI (HVQFN32 with Burn In),
hereafter named as industrial version, fulfilling the automotive qualification stated in
AEC-Q100 grade 3 from the Automotive Electronics Council, defining the critical
stress test qualification for automotive integrated circuits (ICs).
• PN5120A0HN1/C1(HVQFN32) and PN5120A0HN/C1 (HVQFN40), hereafter named
as version 1.0
The data sheet describes the functionality for the industrial version and version 2.0. The
differences of the version 1.0 to the version 2.0 are summarized in Section 21. The
industrial version has only differences within the outlined characteristics and limitations.
2. General description
The PN512 transceiver ICs support 4 different operating modes
• Reader/Writer mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme
• Reader/Writer mode supporting ISO/IEC 14443B
• Card Operation mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme
• NFCIP-1 mode
Enabled in Reader/Writer mode for ISO/IEC 14443A/MIFARE, the PN512’s internal
transmitter part is able to drive a reader/writer antenna designed to communicate with
ISO/IEC 14443A/ MIFARE cards and transponders without additional active circuitry. The
receiver part provides a robust and efficient implementation of a demodulation and
PN512
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decoding circuitry for signals from ISO/IEC 14443A/MIFARE compatible cards and
transponders. The digital part handles the complete ISO/IEC 14443A framing and error
detection (Parity & CRC).
The PN512 supports MIFARE 1K or MIFARE 4K emulation products. The PN512 supports
contactless communication using MIFARE higher transfer speeds up to 424 kbit/s in both
directions.
Enabled in Reader/Writer mode for FeliCa, the PN512 transceiver IC supports the FeliCa
communication scheme. The receiver part provides a robust and efficient implementation
of the demodulation and decoding circuitry for FeliCa coded signals. The digital part
handles the FeliCa framing and error detection like CRC. The PN512 supports contactless
communication using FeliCa Higher transfer speeds up to 424 kbit/s in both directions.
The PN512 supports all layers of the ISO/IEC 14443B reader/writer communication
scheme, given correct implementation of additional components, like oscillator, power
supply, coil etc. and provided that standardized protocols, e.g. like ISO/IEC 14443-4
and/or ISO/IEC 14443B anticollision are correctly implemented.
In Card Operation mode, the PN512 transceiver IC is able to answer to a reader/writer
command either according to the FeliCa or ISO/IEC 14443A/MIFARE card interface
scheme. The PN512 generates the digital load modulated signals and in addition with an
external circuit the answer can be sent back to the reader/writer. A complete card
functionality is only possible in combination with a secure IC using the S2C interface.
Additionally, the PN512 transceiver IC offers the possibility to communicate directly to an
NFCIP-1 device in the NFCIP-1 mode. The NFCIP-1 mode offers different communication
mode and transfer speeds up to 424 kbit/s according to the Ecma 340 and ISO/IEC 18092
NFCIP-1 Standard. The digital part handles the complete NFCIP-1 framing and error
detection.
Various host controller interfaces are implemented:
• 8-bit parallel interface1
• SPI interface
• serial UART (similar to RS232 with voltage levels according pad voltage supply)
• I
2C interface.
A purchaser of this NXP IC has to take care for appropriate third party patent licenses.
1. 8-bit parallel Interface only available in HVQFN40 package.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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3. Features and benefits
Highly integrated analog circuitry to demodulate and decode responses
Buffered output drivers for connecting an antenna with the minimum number of
external components
Integrated RF Level detector
Integrated data mode detector
Supports ISO/IEC 14443 A/MIFARE
Supports ISO/IEC 14443 B Read/Write modes
Typical operating distance in Read/Write mode up to 50 mm depending on the
antenna size and tuning
Typical operating distance in NFCIP-1 mode up to 50 mm depending on the antenna
size and tuning and power supply
Typical operating distance in ISO/IEC 14443A/MIFARE card or FeliCa Card Operation
mode of about 100 mm depending on the antenna size and tuning and the external
field strength
Supports MIFARE 1K or MIFARE 4K emulation encryption in Reader/Writer mode
ISO/IEC 14443A higher transfer speed communication at 212 kbit/s and 424 kbit/s
Contactless communication according to the FeliCa scheme at 212 kbit/s and
424 kbit/s
Integrated RF interface for NFCIP-1 up to 424 kbit/s
S2C interface
Additional power supply to directly supply the smart card IC connected via S2C
Supported host interfaces
SPI up to 10 Mbit/s
I
2C-bus interface up to 400 kBd in Fast mode, up to 3400 kBd in High-speed mode
RS232 Serial UART up to 1228.8 kBd, with voltage levels dependant on pin
voltage supply
8-bit parallel interface with and without Address Latch Enable
FIFO buffer handles 64 byte send and receive
Flexible interrupt modes
Hard reset with low power function
Power-down mode per software
Programmable timer
Internal oscillator for connection to 27.12 MHz quartz crystal
2.5 V to 3.6 V power supply
CRC coprocessor
Programmable I/O pins
Internal self-testPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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4. Quick reference data
[1] Supply voltages below 3 V reduce the performance in, for example, the achievable operating distance.
[2] VDDA, VDDD and VDD(TVDD) must always be the same voltage.
[3] VDD(PVDD) must always be the same or lower voltage than VDDD.
[4] Ipd is the total current for all supplies.
[5] IDD(PVDD) depends on the overall load at the digital pins.
[6] IDD(TVDD) depends on VDD(TVDD) and the external circuit connected to pins TX1 and TX2.
[7] During typical circuit operation, the overall current is below 100 mA.
[8] Typical value using a complementary driver configuration and an antenna matched to 40 between pins TX1 and TX2 at 13.56 MHz.
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
VDDA analog supply voltage VDD(PVDD) VDDA = VDDD = VDD(TVDD);
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) =0V
[1][2] 2.5 - 3.6 V
VDDD digital supply voltage
VDD(TVDD) TVDD supply voltage
VDD(PVDD) PVDD supply voltage [3] 1.6 - 3.6 V
VDD(SVDD) SVDD supply voltage VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V 1.6 - 3.6 V
Ipd power-down current VDDA = VDDD = VDD(TVDD) =VDD(PVDD) =3V
hard power-down; pin NRSTPD set LOW [4] --5 A
soft power-down; RF level detector on [4] - - 10 A
IDDD digital supply current pin DVDD; VDDD =3V - 6.5 9 mA
IDDA analog supply current pin AVDD; VDDA = 3 V, CommandReg register’s
RcvOff bit = 0
- 7 10 mA
pin AVDD; receiver switched off; VDDA = 3 V,
CommandReg register’s RcvOff bit = 1
- 3 5 mA
IDD(PVDD) PVDD supply current pin PVDD [5] - - 40 mA
IDD(TVDD) TVDD supply current pin TVDD; continuous wave [6][7][8] - 60 100 mA
Tamb ambient temperature HVQFN32, HVQFN40, TFBGA64 30 +85 C
lndustrial version:
Ipd power-down current VDDA = VDDD = VDD(TVDD) =VDD(PVDD) =3V
hard power-down; pin NRSTPD set LOW [4] - - 15 A
soft power-down; RF level detector on [4] - - 30 A
Tamb ambient temperature HVQFN32 40 - +90 CPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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5. Ordering information
Table 2. Ordering information
Type number Package
Name Description Version
PN5120A0HN1/C2 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;
32 terminal; body 5 5 0.85 mm
SOT617-1
PN5120A0HN/C2 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6 6 0.85 mm
SOT618-1
PN512AA0HN1/C2 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;
32 terminal; body 5 5 0.85 mm
SOT617-1
PN512AA0HN1/C2BI HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;
32 terminal; body 5 5 0.85 mm
SOT617-1
PN5120A0HN1/C1 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;
32 terminal; body 5 5 0.85 mm
SOT617-1
PN5120A0HN/C1 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6 6 0.85 mm
SOT618-1
PN5120A0ET/C2 TFBGA64 plastic thin fine-pitch ball grid array package; 64 balls SOT1336-1PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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6. Block diagram
The analog interface handles the modulation and demodulation of the analog signals
according to the Card Receiving mode, Reader/Writer mode and NFCIP-1 mode
communication scheme.
The RF level detector detects the presence of an external RF-field delivered by the
antenna to the RX pin.
The Data mode detector detects a MIFARE, FeliCa or NFCIP-1 mode in order to prepare
the internal receiver to demodulate signals, which are sent to the PN512.
The communication (S2C) interface provides digital signals to support communication for
transfer speeds above 424 kbit/s and digital signals to communicate to a secure IC.
The contactless UART manages the protocol requirements for the communication
protocols in cooperation with the host. The FIFO buffer ensures fast and convenient data
transfer to and from the host and the contactless UART and vice versa.
Various host interfaces are implemented to meet different customer requirements.
Fig 1. Simplified block diagram of the PN512
001aaj627
HOST
ANTENNA FIFO
BUFFER
ANALOG
INTERFACE
CONTACTLESS
UART SERIAL UART
SPI
I
2C-BUS
REGISTER BANKPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Fig 2. Detailed block diagram of the PN512
001aak602
DVDD
NRSTPD
IRQ
MFIN
MFOUT
SVDD
OSCIN
OSCOUT
VMID AUX1 AUX2 RX TVSS TX1 TX2 TVDD
16 19 20 17 10, 14 11 13 12
DVSS
AVDD
SDA/NSS/RX EA I2C PVDD PVSS
24 32 1 52
D1/ADR_5
25
D2/ADR_4
26
D3/ADR_3
27
D4/ADR_2
28
D5/ADR_1/
SCK/DTRQ
29
D6/ADR_0/
MOSI/MX
30
D7/SCL/
MISO/TX
31
AVSS
3
6
23
7
8
9
21
22
4
15
18
FIFO CONTROL
MIFARE CLASSIC UNIT
STATE MACHINE
COMMAND REGISTER
PROGRAMABLE TIMER
INTERRUPT CONTROL
CRC16
GENERATION AND CHECK
PARALLEL/SERIAL
CONVERTER
SERIAL DATA SWITCH
TRANSMITTER CONTROL
BIT COUNTER
PARITY GENERATION AND CHECK
FRAME GENERATION AND CHECK
BIT DECODING BIT ENCODING
RANDOM NUMBER
GENERATOR
ANALOG TO DIGITAL
CONVERTER
I-CHANNEL
AMPLIFIER
ANALOG TEST
MULTIPLEXOR
AND
DIGITAL TO
ANALOG
CONVERTER
I-CHANNEL
DEMODULATOR
Q-CHANNEL
AMPLIFIER
CLOCK
GENERATION,
FILTERING AND
DISTRIBUTION
Q-CLOCK
GENERATION
OSCILLATOR
TEMPERATURE
SENSOR
Q-CHANNEL
DEMODULATOR
AMPLITUDE
RATING
REFERENCE
VOLTAGE
64-BYTE FIFO
BUFFER
CONTROL REGISTER
BANK
SPI, UART, I2C-BUS INTERFACE CONTROL
VOLTAGE
MONITOR
AND
POWER ON
DETECT
RESET
CONTROL
POWER-DOWN
CONTROLPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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7. Pinning information
7.1 Pinning
Fig 3. Pinning configuration HVQFN32 (SOT617-1)
Fig 4. Pinning configuration HVQFN40 (SOT618-1)
001aan212
PN512
Transparent top view
RX
SIGIN
SIGOUT
AVSS
NRSTPD AUX1
PVSS AUX2
DVSS OSCIN
DVDD OSCOUT
PVDD IRQ
A1 ALE SVDD TVSS TX1 TVDD TX2 TVSS AVDD VMID A0D7 D6 D5 D4 D3 D2 D1
8 17
7 18
6 19
5 20
4 21
3 22
2 23
1 24
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
terminal 1
index area
001aan213
PN512
AVSS
NRSTPD
SIGIN
AUX1
PVSS AUX2
DVSS OSCIN
DVDD OSCOUT
PVDD IRQ
A5 NWR
A4 NRD
A3 ALE
A2 NCS SIGOUT SVDD TVSS TX1 TVDD TX2 TVSS AVDD VMIDRX A1A0D7 D6 D5 D4 D3 D2 D1 D0
10 21
9 22
8 23
7 24
6 25
5 26
4 27
3 28
2 29
1 30 11121314151617181920 40393837363534333231
terminal 1
index area
Transparent top viewPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Fig 5. Pin configuration TFBGA64 (SOT1336-1)
aaa-005873
TFBGA64
Transparent top view
ball A1
index area
H
G
F
E
D
C
B
A
1 3 5 78 246PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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7.2 Pin description
Table 3. Pin description HVQFN32
Pin Symbol Type Description
1 A1 I Address Line
2 PVDD PWR Pad power supply
3 DVDD PWR Digital Power Supply
4 DVSS PWR Digital Ground
5 PVSS PWR Pad power supply ground
6 NRSTPD I Not Reset and Power Down: When LOW, internal current sinks are switched off, the
oscillator is inhibited, and the input pads are disconnected from the outside world. With
a positive edge on this pin the internal reset phase starts.
7 SIGIN I Communication Interface Input: accepts a digital, serial data stream
8 SIGOUT O Communication Interface Output: delivers a serial data stream
9 SVDD PWR S2C Pad Power Supply: provides power to the S2C pads
10 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2
11 TX1 O Transmitter 1: delivers the modulated 13.56 MHz energy carrier
12 TVDD PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2
13 TX2 O Transmitter 2: delivers the modulated 13.56 MHz energy carrier
14 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2
15 AVDD PWR Analog Power Supply
16 VMID PWR Internal Reference Voltage: This pin delivers the internal reference voltage.
17 RX I Receiver Input
18 AVSS PWR Analog Ground
19 AUX1 O Auxiliary Outputs: These pins are used for testing.
20 AUX2 O
21 OSCIN I Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is
also the input for an externally generated clock (fosc = 27.12 MHz).
22 OSCOUT O Crystal Oscillator Output: Output of the inverting amplifier of the oscillator.
23 IRQ O Interrupt Request: output to signal an interrupt event
24 ALE I Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch
when HIGH.
25 to 31 D1 to D7 I/O 8-bit Bi-directional Data Bus.
Remark: An 8-bit parallel interface is not available.
Remark: If the host controller selects I2C as digital host controller interface, these pins
can be used to define the I2C address.
Remark: For serial interfaces this pins can be used for test signals or I/Os.
32 A0 I Address LinePN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Table 4. Pin description HVQFN40
Pin Symbol Type Description
1 to 4 A2 to A5 I Address Line
5 PVDD PWR Pad power supply
6 DVDD PWR Digital Power Supply
7 DVSS PWR Digital Ground
8 PVSS PWR Pad power supply ground
9 NRSTPD I Not Reset and Power Down: When LOW, internal current sinks are switched off, the
oscillator is inhibited, and the input pads are disconnected from the outside world. With
a positive edge on this pin the internal reset phase starts.
10 SIGIN I Communication Interface Input: accepts a digital, serial data stream
11 SIGOUT O Communication Interface Output: delivers a serial data stream
12 SVDD PWR S2C Pad Power Supply: provides power to the S2C pads
13 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2
14 TX1 O Transmitter 1: delivers the modulated 13.56 MHz energy carrier
15 TVDD PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2
16 TX2 O Transmitter 2: delivers the modulated 13.56 MHz energy carrier
17 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2
18 AVDD PWR Analog Power Supply
19 VMID PWR Internal Reference Voltage: This pin delivers the internal reference voltage.
20 RX I Receiver Input
21 AVSS PWR Analog Ground
22 AUX1 O Auxiliary Outputs: These pins are used for testing.
23 AUX2 O
24 OSCIN I Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is
also the input for an externally generated clock (fosc = 27.12 MHz).
25 OSCOUT O Crystal Oscillator Output: Output of the inverting amplifier of the oscillator.
26 IRQ O Interrupt Request: output to signal an interrupt event
27 NWR I Not Write: strobe to write data (applied on D0 to D7) into the PN512 register
28 NRD I Not Read: strobe to read data from the PN512 register (applied on D0 to D7)
29 ALE I Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch
when HIGH.
30 NCS I Not Chip Select: selects and activates the host controller interface of the PN512
31 to 38 D0 to D7 I/O 8-bit Bi-directional Data Bus.
Remark: For serial interfaces this pins can be used for test signals or I/Os.
Remark: If the host controller selects I2C as digital host controller interface, these pins
can be used to define the I2C address.
39 to 40 A0 to A1 I Address LinePN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Table 5. Pin description TFBGA64
Pin Symbol Type Description
A1 to A5, A8,
B3, B4, B8, E1
PVSS PWR Pad power supply ground
A6 D4 I/O 8-bit Bi-directional Data Bus.
Remark: For serial interfaces this pins can be used for test signals or I/Os.
Remark: If the host controller selects I2C as digital host controller interface, these
pins can be used to define the I2C address.
A7 D2 I/O
B1 PVDD PWR Pad power supply
B2 A0 I Address Line
B5 D5 I/O 8-bit Bi-directional Data Bus.
Remark: For serial interfaces this pins can be used for test signals or I/Os.
Remark: If the host controller selects I2C as digital host controller interface, these
pins can be used to define the I2C address.
B6 D3 I/O
B7 D1 I/O
C1 DVDD PWR Digital Power Supply
C2 A1 I Address Line
C3 D7 I/O 8-bit Bi-directional Data Bus.
Remark: For serial interfaces this pins can be used for test signals or I/Os.
Remark: If the host controller selects I2C as digital host controller interface, these
pins can be used to define the I2C address.
C4 D6 I/O
C5 IRQ O Interrupt Request: output to signal an interrupt event
C6 ALE I Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch
when HIGH.
C7, C8, D6, D8,
E6, E8, F7, G8,
H8
AVSS PWR Analog Ground
D1 DVSS PWR Digital Ground
D2 NRSTPD I Not Reset and Power Down: When LOW, internal current sinks are switched off,
the oscillator is inhibited, and the input pads are disconnected from the outside
world. With a positive edge on this pin the internal reset phase starts.
D3 to D5, E3 to
E5, F3, F4,
G1 to G6,
H1, H2, H6
TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2
D7 OSCOUT O Crystal Oscillator Output: Output of the inverting amplifier of the oscillator.
E2 SIGIN I Communication Interface Input: accepts a digital, serial data stream
E7 OSCIN I Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin
is also the input for an externally generated clock (fosc = 27.12 MHz).
F1 SVDD PWR S2C Pad Power Supply: provides power to the S2C pads
F2 SIGOUT O Communication Interface Output: delivers a serial data stream
F5 AUX1 O Auxiliary Outputs: These pins are used for testing.
F6 AUX2 O
F8 RX I Receiver Input
G7 VMID PWR Internal Reference Voltage: This pin delivers the internal reference voltage.
H3 TX1 O Transmitter 1: delivers the modulated 13.56 MHz energy carrierPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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H4 TVDD PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2
H5 TX2 O Transmitter 2: delivers the modulated 13.56 MHz energy carrier
H7 AVDD PWR Analog Power Supply
Table 5. Pin description TFBGA64
Pin Symbol Type DescriptionPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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8. Functional description
The PN512 transmission module supports the Read/Write mode for
ISO/IEC 14443 A/MIFARE and ISO/IEC 14443 B using various transfer speeds and
modulation protocols.
PN512 transceiver IC supports the following operating modes:
• Reader/Writer mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme
• Card Operation mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme
• NFCIP-1 mode
The modes support different transfer speeds and modulation schemes. The following
chapters will explain the different modes in detail.
Note: All indicated modulation indices and modes in this chapter are system parameters.
This means that beside the IC settings a suitable antenna tuning is required to achieve the
optimum performance.
8.1 ISO/IEC 14443 A/MIFARE functionality
The physical level communication is shown in Figure 7.
The physical parameters are described in Table 4.
Fig 6. PN512 Read/Write mode
001aan218
BATTERY
reader/writer
contactless card
MICROCONTROLLER
PN512 ISO/IEC 14443 A CARD
Fig 7. ISO/IEC 14443 A/MIFARE Read/Write mode communication diagram
Table 6. Communication overview for ISO/IEC 14443 A/MIFARE reader/writer
Communication
direction
Signal type Transfer speed
106 kBd 212 kBd 424 kBd
Reader to card (send
data from the PN512
to a card)
reader side
modulation
100 % ASK 100 % ASK 100 % ASK
bit encoding modified Miller
encoding
modified Miller
encoding
modified Miller
encoding
bit length 128 (13.56 s) 64 (13.56 s) 32 (13.56 s)
(1)
(2)
001aan219
PN512
ISO/IEC 14443 A CARD
ISO/IEC 14443 A
READERPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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The PN512’s contactless UART and dedicated external host must manage the complete
ISO/IEC 14443 A/MIFARE protocol. Figure 8 shows the data coding and framing
according to ISO/IEC 14443 A/MIFARE.
The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 A
part 3 and handles parity generation internally according to the transfer speed. Automatic
parity generation can be switched off using the ManualRCVReg register’s ParityDisable
bit.
8.2 ISO/IEC 14443 B functionality
The PN512 reader IC fully supports international standard ISO 14443 which includes
communication schemes ISO 14443 A and ISO 14443 B.
Refer to the ISO 14443 reference documents Identification cards - Contactless integrated
circuit cards - Proximity cards (parts 1 to 4).
Remark: NXP Semiconductors does not offer a software library to enable design-in of the
ISO 14443 B protocol.
Card to reader
(PN512 receives data
from a card)
card side
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier
frequency
13.56 MHz/16 13.56 MHz/16 13.56 MHz/16
bit encoding Manchester
encoding
BPSK BPSK
Table 6. Communication overview for ISO/IEC 14443 A/MIFARE reader/writer …continued
Communication
direction
Signal type Transfer speed
106 kBd 212 kBd 424 kBd
Fig 8. Data coding and framing according to ISO/IEC 14443 A
001aak585
ISO/IEC 14443 A framing at 106 kBd
8-bit data 8-bit data 8-bit data
odd
parity
odd
parity
start
odd
start bit is 1 parity
ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd
8-bit data 8-bit data 8-bit data
odd
parity
odd
parity
start
even
parity
start bit is 0
burst of 32
subcarrier clocks
even parity at the
end of the framePN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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8.3 FeliCa reader/writer functionality
The FeliCa mode is the general reader/writer to card communication scheme according to
the FeliCa specification. The following diagram describes the communication on a
physical level, the communication overview describes the physical parameters.
The contactless UART of PN512 and a dedicated external host controller are required to
handle the complete FeliCa protocol.
8.3.1 FeliCa framing and coding
To enable the FeliCa communication a 6 byte preamble (00h, 00h, 00h, 00h, 00h, 00h)
and 2 bytes Sync bytes (B2h, 4Dh) are sent to synchronize the receiver.
The following Len byte indicates the length of the sent data bytes plus the LEN byte itself.
The CRC calculation is done according to the FeliCa definitions with the MSB first.
To transmit data on the RF interface, the host controller has to send the Len- and databytes
to the PN512's FIFO-buffer. The preamble and the sync bytes are generated by the
PN512 automatically and must not be written to the FIFO by the host controller. The
PN512 performs internally the CRC calculation and adds the result to the data frame.
Example for FeliCa CRC Calculation:
Fig 9. FeliCa reader/writer communication diagram
Table 7. Communication overview for FeliCa reader/writer
Communication
direction
FeliCa FeliCa Higher
transfer speeds
Transfer speed 212 kbit/s 424 kbit/s
PN512 card Modulation on reader side 8-30 % ASK 8-30 % ASK
bit coding Manchester Coding Manchester Coding
Bitlength (64/13.56) s (32/13.56) s
card PN512 Loadmodulation on card side > 12 % ASK > 12 % ASK
bit coding Manchester coding Manchester coding
2. PICC to PCD, > 12 % ASK loadmodulation
Manchester coded, baudrate 212 to 424 kbaud
1. PCD to PICC, 8-30 % ASK
Manchester coded, baudrate 212 to 424 kbaud
001aan214
PN512
FeliCa CARD
(PICC)
Felica READER
(PCD)
Table 8. FeliCa framing and coding
Preamble Sync Len n-Data CRC
00h 00h 00h 00h 00h 00h B2h 4Dh
Table 9. Start value for the CRC Polynomial: (00h), (00h)
Preamble Sync Len 2 Data Bytes CRC
00h 00h 00h 00h 00h 00h B2h 4Dh 03h ABh CDh 90h 35hPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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8.4 NFCIP-1 mode
The NFCIP-1 communication differentiates between an active and a Passive
Communication mode.
• Active Communication mode means both the initiator and the target are using their
own RF field to transmit data.
• Passive Communication mode means that the target answers to an initiator command
in a load modulation scheme. The initiator is active in terms of generating the RF field.
• Initiator: generates RF field at 13.56 MHz and starts the NFCIP-1 communication
• Target: responds to initiator command either in a load modulation scheme in Passive
Communication mode or using a self generated and self modulated RF field for Active
Communication mode.
In order to fully support the NFCIP-1 standard the PN512 supports the Active and Passive
Communication mode at the transfer speeds 106 kbit/s, 212 kbit/s and 424 kbit/s as
defined in the NFCIP-1 standard.
Fig 10. NFCIP-1 mode
001aan215
BATTERY
initiator: active target:
passive or active
MICROCONTROLLER
PN512
BATTERY
MICROCONTROLLER
PN512PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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8.4.1 Active communication mode
Active communication mode means both the initiator and the target are using their own
RF field to transmit data.
The contactless UART of PN512 and a dedicated host controller are required to handle
the NFCIP-1 protocol.
Note: Transfer Speeds above 424 kbit/s are not defined in the NFCIP-1 standard. The
PN512 supports these transfer speeds only with dedicated external circuits.
Fig 11. Active communication mode
Table 10. Communication overview for Active communication mode
Communication
direction
106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s 1.69 Mbit/s,
3.39 Mbit/s
Initiator Target According to
ISO/IEC 14443A
100 % ASK,
Modified
Miller Coded
According to FeliCa, 8-30 %
ASK Manchester Coded
digital capability to handle
this communication Target Initiator
host NFC INITIATOR
powered to
generate RF field
1. initiator starts communication at
selected transfer speed
Initial command
response
2. target answers at
the same transfer speed
host NFC INITIATOR
powered for digital
processing
host
host
NFC TARGET
NFC TARGET
powered for
digital processing
powered to
generate RF field
001aan216PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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8.4.2 Passive communication mode
Passive Communication mode means that the target answers to an initiator command in a
load modulation scheme. The initiator is active meaning generating the RF field.
The contactless UART of PN512 and a dedicated host controller are required to handle
the NFCIP-1 protocol.
Note: Transfer Speeds above 424 kbit/s are not defined in the NFCIP-1 standard. The
PN512 supports these transfer speeds only with dedicated external circuits.
Fig 12. Passive communication mode
Table 11. Communication overview for Passive communication mode
Communication
direction
106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s 1.69 Mbit/s,
3.39 Mbit/s
Initiator Target According to
ISO/IEC 14443A
100 % ASK,
Modified
Miller Coded
According to FeliCa, 8-30
% ASK Manchester Coded
digital capability to handle
this communication
Target Initiator According to
ISO/IEC 14443A
subcarrier load
modulation,
Manchester Coded
According to FeliCa, > 12 %
ASK Manchester Coded
host NFC INITIATOR
powered to
generate RF field
1. initiator starts communication
at selected transfer speed
2. targets answers using
load modulated data
at the same transfer speed
host NFC TARGET
powered for
digital processing
001aan217PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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8.4.3 NFCIP-1 framing and coding
The NFCIP-1 framing and coding in Active and Passive Communication mode is defined
in the NFCIP-1 standard.
8.4.4 NFCIP-1 protocol support
The NFCIP-1 protocol is not completely described in this document. For detailed
explanation of the protocol refer to the NFCIP-1 standard. However the datalink layer is
according to the following policy:
• Speed shall not be changed while continuum data exchange in a transaction.
• Transaction includes initialization and anticollision methods and data exchange (in
continuous way, meaning no interruption by another transaction).
In order not to disturb current infrastructure based on 13.56 MHz general rules to start
NFCIP-1 communication are defined in the following way.
1. Per default NFCIP-1 device is in Target mode meaning its RF field is switched off.
2. The RF level detector is active.
3. Only if application requires the NFCIP-1 device shall switch to Initiator mode.
4. Initiator shall only switch on its RF field if no external RF field is detected by RF Level
detector during a time of TIDT.
5. The initiator performs initialization according to the selected mode.
8.4.5 MIFARE Card operation mode
Table 12. Framing and coding overview
Transfer speed Framing and Coding
106 kbit/s According to the ISO/IEC 14443A/MIFARE scheme
212 kbit/s According to the FeliCa scheme
424 kbit/s According to the FeliCa scheme
Table 13. MIFARE Card operation mode
Communication
direction
ISO/IEC 14443A/
MIFARE
MIFARE Higher transfer speeds
transfer speed 106 kbit/s 212 kbit/s 424 kbit/s
reader/writer
PN512
Modulation on
reader side
100 % ASK 100 % ASK 100 % ASK
bit coding Modified Miller Modified Miller Modified Miller
Bitlength (128/13.56) s (64/13.56) s (32/13.56) s
PN512 reader/
writer
Modulation on
PN512 side
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier
frequency
13.56 MHz/16 13.56 MHz/16 13.56 MHz/16
bit coding Manchester coding BPSK BPSKPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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8.4.6 FeliCa Card operation mode
9. PN512 register SET
9.1 PN512 registers overview
Table 14. FeliCa Card operation mode
Communication
direction
FeliCa FeliCa Higher
transfer speeds
Transfer speed 212 kbit/s 424 kbit/s
reader/writer
PN512
Modulation on reader side 8-30 % ASK 8-30 % ASK
bit coding Manchester Coding Manchester Coding
Bitlength (64/13.56) s (32/13.56) s
PN512 reader/
writer
Load modulation on PN512
side
> 12 % ASK load
modulation
> 12 % ASK load
modulation
bit coding Manchester coding Manchester coding
Table 15. PN512 registers overview
Addr
(hex)
Register Name Function
Page 0: Command and Status
0 PageReg Selects the register page
1 CommandReg Starts and stops command execution
2 ComlEnReg Controls bits to enable and disable the passing of Interrupt Requests
3 DivlEnReg Controls bits to enable and disable the passing of Interrupt Requests
4 ComIrqReg Contains Interrupt Request bits
5 DivIrqReg Contains Interrupt Request bits
6 ErrorReg Error bits showing the error status of the last command executed
7 Status1Reg Contains status bits for communication
8 Status2Reg Contains status bits of the receiver and transmitter
9 FIFODataReg In- and output of 64 byte FIFO-buffer
A FIFOLevelReg Indicates the number of bytes stored in the FIFO
B WaterLevelReg Defines the level for FIFO under- and overflow warning
C ControlReg Contains miscellaneous Control Registers
D BitFramingReg Adjustments for bit oriented frames
E CollReg Bit position of the first bit collision detected on the RF-interface
F RFU Reserved for future use
Page 1: Command
0 PageReg Selects the register page
1 ModeReg Defines general modes for transmitting and receiving
2 TxModeReg Defines the data rate and framing during transmission
3 RxModeReg Defines the data rate and framing during receiving
4 TxControlReg Controls the logical behavior of the antenna driver pins TX1 and TX2
5 TxAutoReg Controls the setting of the antenna driversPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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6 TxSelReg Selects the internal sources for the antenna driver
7 RxSelReg Selects internal receiver settings
8 RxThresholdReg Selects thresholds for the bit decoder
9 DemodReg Defines demodulator settings
A FelNFC1Reg Defines the length of the valid range for the receive package
B FelNFC2Reg Defines the length of the valid range for the receive package
C MifNFCReg Controls the communication in ISO/IEC 14443/MIFARE and NFC
target mode at 106 kbit
D ManualRCVReg Allows manual fine tuning of the internal receiver
E TypeBReg Configure the ISO/IEC 14443 type B
F SerialSpeedReg Selects the speed of the serial UART interface
Page 2: CFG
0 PageReg Selects the register page
1 CRCResultReg Shows the actual MSB and LSB values of the CRC calculation
2
3 GsNOffReg Selects the conductance of the antenna driver pins TX1 and TX2 for
modulation, when the driver is switched off
4 ModWidthReg Controls the setting of the ModWidth
5 TxBitPhaseReg Adjust the TX bit phase at 106 kbit
6 RFCfgReg Configures the receiver gain and RF level
7 GsNOnReg Selects the conductance of the antenna driver pins TX1 and TX2 for
modulation when the drivers are switched on
8 CWGsPReg Selects the conductance of the antenna driver pins TX1 and TX2 for
modulation during times of no modulation
9 ModGsPReg Selects the conductance of the antenna driver pins TX1 and TX2 for
modulation during modulation
A TModeReg
TPrescalerReg
Defines settings for the internal timer
B
C TReloadReg Describes the 16-bit timer reload value
D
E TCounterValReg Shows the 16-bit actual timer value
F
Page 3: TestRegister
0 PageReg selects the register page
1 TestSel1Reg General test signal configuration
2 TestSel2Reg General test signal configuration and PRBS control
3 TestPinEnReg Enables pin output driver on 8-bit parallel bus (Note: For serial
interfaces only)
4 TestPin
ValueReg
Defines the values for the 8-bit parallel bus when it is used as I/O bus
5 TestBusReg Shows the status of the internal testbus
6 AutoTestReg Controls the digital selftest
Table 15. PN512 registers overview …continued
Addr
(hex)
Register Name FunctionPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.1.1 Register bit behavior
Depending on the functionality of a register, the access conditions to the register can vary.
In principle bits with same behavior are grouped in common registers. In Table 16 the
access conditions are described.
7 VersionReg Shows the version
8 AnalogTestReg Controls the pins AUX1 and AUX2
9 TestDAC1Reg Defines the test value for the TestDAC1
A TestDAC2Reg Defines the test value for the TestDAC2
B TestADCReg Shows the actual value of ADC I and Q
C-F RFT Reserved for production tests
Table 15. PN512 registers overview …continued
Addr
(hex)
Register Name Function
Table 16. Behavior of register bits and its designation
Abbreviation Behavior Description
r/w read and write These bits can be written and read by the -Controller. Since they
are used only for control means, there content is not influenced by
internal state machines, e.g. the PageSelect-Register may be
written and read by the -Controller. It will also be read by internal
state machines, but never changed by them.
dy dynamic These bits can be written and read by the -Controller.
Nevertheless, they may also be written automatically by internal
state machines, e.g. the Command-Register changes its value
automatically after the execution of the actual command.
r read only These registers hold bits, which value is determined by internal
states only, e.g. the CRCReady bit can not be written from
external but shows internal states.
w write only Reading these registers returns always ZERO.
RFU - These registers are reserved for future use.
In case of a PN512 Version version 2.0 (VersionReg = 82h) a
read access to these registers returns always the value “0”.
Nevertheless this is not guaranteed for future chips versions
where the value is undefined. In case of a write access, it is
recommended to write always the value “0”.
RFT - These registers are reserved for production tests and shall not be
changed.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2 Register description
9.2.1 Page 0: Command and status
9.2.1.1 PageReg
Selects the register page.
9.2.1.2 CommandReg
Starts and stops command execution.
Table 17. PageReg register (address 00h); reset value: 00h, 0000000b
7 6 5 4 3 2 1 0
UsePage Select 0 0 0 0 0 PageSelect
Access
Rights
r/w RFU RFU RFU RFU RFU r/w r/w
Table 18. Description of PageReg bits
Bit Symbol Description
7 UsePageSelect Set to logic 1, the value of PageSelect is used as register address A5
and A4. The LSB-bits of the register address are defined by the
address pins or the internal address latch, respectively.
Set to logic 0, the whole content of the internal address latch defines
the register address. The address pins are used as described in
Section 10.1 “Automatic microcontroller interface detection”.
6 to 2 - Reserved for future use.
1 to 0 PageSelect The value of PageSelect is used only if UsePageSelect is set to
logic 1. In this case it specifies the register page (which is A5 and A4
of the register address).
Table 19. CommandReg register (address 01h); reset value: 20h, 00100000b
7 6 5 4 3 2 1 0
0 0 RcvOff Power Down Command
Access
Rights
RFU RFU r/w dy dy dy dy dy
Table 20. Description of CommandReg bits
Bit Symbol Description
7 to 6 - Reserved for future use.
5 RcvOff Set to logic 1, the analog part of the receiver is switched off.
4 PowerDown Set to logic 1, Soft Power-down mode is entered.
Set to logic 0, the PN512 starts the wake up procedure. During this
procedure this bit still shows a 1. A 0 indicates that the PN512 is ready
for operations; see Section 16.2 “Soft power-down mode”.
Note: The bit Power Down cannot be set, when the command
SoftReset has been activated.
3 to 0 Command Activates a command according to the Command Code. Reading this
register shows, which command is actually executed (see Section 19.3
“PN512 command overview”).PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.1.3 CommIEnReg
Control bits to enable and disable the passing of interrupt requests.
Table 21. CommIEnReg register (address 02h); reset value: 80h, 10000000b
7 6 5 4 3 2 1 0
IRqInv TxIEn RxIEn IdleIEn HiAlertIEn LoAlertIEn ErrIEn TimerIEn
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 22. Description of CommIEnReg bits
Bit Symbol Description
7 IRqInv Set to logic 1, the signal on pin IRQ is inverted with respect to bit IRq in the
register Status1Reg. Set to logic 0, the signal on pin IRQ is equal to bit IRq.
In combination with bit IRqPushPull in register DivIEnReg, the default value
of 1 ensures, that the output level on pin IRQ is 3-state.
6 TxIEn Allows the transmitter interrupt request (indicated by bit TxIRq) to be
propagated to pin IRQ.
5 RxIEn Allows the receiver interrupt request (indicated by bit RxIRq) to be
propagated to pin IRQ.
4 IdleIEn Allows the idle interrupt request (indicated by bit IdleIRq) to be propagated to
pin IRQ.
3 HiAlertIEn Allows the high alert interrupt request (indicated by bit HiAlertIRq) to be
propagated to pin IRQ.
2 LoAlertIEn Allows the low alert interrupt request (indicated by bit LoAlertIRq) to be
propagated to pin IRQ.
1 ErrIEn Allows the error interrupt request (indicated by bit ErrIRq) to be propagated
to pin IRQ.
0 TimerIEn Allows the timer interrupt request (indicated by bit TimerIRq) to be
propagated to pin IRQ. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.1.4 DivIEnReg
Control bits to enable and disable the passing of interrupt requests.
Table 23. DivIEnReg register (address 03h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
IRQPushPull 0 0 SiginActIEn ModeIEn CRCIEn RFOnIEn RFOffIEn
Access
Rights
r/w RFU RFU r/w r/w r/w r/w r/w
Table 24. Description of DivIEnReg bits
Bit Symbol Description
7 IRQPushPull Set to logic 1, the pin IRQ works as standard CMOS output pad.
Set to logic 0, the pin IRQ works as open drain output pad.
6 to 5 - Reserved for future use.
4 SiginActIEn Allows the SIGIN active interrupt request to be propagated to pin IRQ.
3 ModeIEn Allows the mode interrupt request (indicated by bit ModeIRq) to be
propagated to pin IRQ.
2 CRCIEn Allows the CRC interrupt request (indicated by bit CRCIRq) to be
propagated to pin IRQ.
1 RfOnIEn Allows the RF field on interrupt request (indicated by bit RfOnIRq) to
be propagated to pin IRQ.
0 RfOffIEn Allows the RF field off interrupt request (indicated by bit RfOffIRq) to
be propagated to pin IRQ.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.1.5 CommIRqReg
Contains Interrupt Request bits.
Table 25. CommIRqReg register (address 04h); reset value: 14h, 00010100b
7 6 5 4 3 2 1 0
Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq
Access
Rights
w dy dy dy dy dy dy dy
Table 26. Description of CommIRqReg bits
All bits in the register CommIRqReg shall be cleared by software.
Bit Symbol Description
7 Set1 Set to logic 1, Set1 defines that the marked bits in the register CommIRqReg
are set.
Set to logic 0, Set1 defines, that the marked bits in the register CommIRqReg
are cleared.
6 TxIRq Set to logic 1 immediately after the last bit of the transmitted data was sent out.
5 RxIRq Set to logic 1 when the receiver detects the end of a valid datastream.
If the bit RxNoErr in register RxModeReg is set to logic 1, bit RxIRq is only set
to logic 1 when data bytes are available in the FIFO.
4 IdleIRq Set to logic 1, when a command terminates by itself e.g. when the
CommandReg changes its value from any command to the Idle Command.
If an unknown command is started, the CommandReg changes its content to
the idle state and the bit IdleIRq is set. Starting the Idle Command by the
-Controller does not set bit IdleIRq.
3 HiAlertIRq Set to logic 1, when bit HiAlert in register Status1Reg is set. In opposition to
HiAlert, HiAlertIRq stores this event and can only be reset as indicated by bit
Set1.
2 LoAlertIRq Set to logic 1, when bit LoAlert in register Status1Reg is set. In opposition to
LoAlert, LoAlertIRq stores this event and can only be reset as indicated by bit
Set1.
1 ErrIRq Set to logic 1 if any error bit in the Error Register is set.
0 TimerIRq Set to logic 1 when the timer decrements the TimerValue Register to zero.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.1.6 DivIRqReg
Contains Interrupt Request bits
Table 27. DivIRqReg register (address 05h); reset value: XXh, 000X00XXb
7 6 5 4 3 2 1 0
Set2 0 0 SiginActIRq ModeIRq CRCIRq RFOnIRq RFOffIRq
Access
Rights
w RFU RFU dy dy dy dy dy
Table 28. Description of DivIRqReg bits
All bits in the register DivIRqReg shall be cleared by software.
Bit Symbol Description
7 Set2 Set to logic 1, Set2 defines that the marked bits in the register
DivIRqReg are set.
Set to logic 0, Set2 defines, that the marked bits in the register
DivIRqReg are cleared
6 to 5 - Reserved for future use.
4 SiginActIRq Set to logic 1, when SIGIN is active. See Section 12.6 “S2C interface
support”. This interrupt is set when either a rising or falling signal edge
is detected.
3 ModeIRq Set to logic 1, when the mode has been detected by the Data mode
detector.
Note: The Data mode detector can only be activated by the AutoColl
command and is terminated automatically having detected the
Communication mode.
Note: The Data mode detector is automatically restarted after each RF
Reset.
2 CRCIRq Set to logic 1, when the CRC command is active and all data are
processed.
1 RFOnIRq Set to logic 1, when an external RF field is detected.
0 RFOffIRq Set to logic 1, when a present external RF field is switched off.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.1.7 ErrorReg
Error bit register showing the error status of the last command executed.
[1] Command execution will clear all error bits except for bit TempErr. A setting by software is impossible.
Table 29. ErrorReg register (address 06h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
WrErr TempErr RFErr BufferOvfl CollErr CRCErr ParityErr ProtocolErr
Access
Rights
r rr r r r r r
Table 30. Description of ErrorReg bits
Bit Symbol Description
7 WrErr Set to logic 1, when data is written into FIFO by the host controller
during the AutoColl command or MFAuthent command or if data is
written into FIFO by the host controller during the time between
sending the last bit on the RF interface and receiving the last bit on the
RF interface.
6 TempErr[1] Set to logic 1, if the internal temperature sensor detects overheating.
In this case, the antenna drivers are switched off automatically.
5 RFErr Set to logic 1, if in Active Communication mode the counterpart does
not switch on the RF field in time as defined in NFCIP-1 standard.
Note: RFErr is only used in Active Communication mode. The bits
RxFraming or the bits TxFraming has to be set to 01 to enable this
functionality.
4 BufferOvfl Set to logic 1, if the host controller or a PN512’s internal state machine
(e.g. receiver) tries to write data into the FIFO-bufferFIFO-buffer
although the FIFO-buffer is already full.
3 CollErr Set to logic 1, if a bit-collision is detected. It is cleared automatically at
receiver start-up phase. This bit is only valid during the bitwise
anticollision at 106 kbit. During communication schemes at 212 and
424 kbit this bit is always set to logic 1.
2 CRCErr Set to logic 1, if bit RxCRCEn in register RxModeReg is set and the
CRC calculation fails. It is cleared to 0 automatically at receiver
start-up phase.
1 ParityErr Set to logic 1, if the parity check has failed. It is cleared automatically
at receiver start-up phase. Only valid for ISO/IEC 14443A/MIFARE or
NFCIP-1 communication at 106 kbit.
0 ProtocolErr Set to logic 1, if one out of the following cases occur:
• Set to logic 1 if the SOF is incorrect. It is cleared automatically at
receiver start-up phase. The bit is only valid for 106 kbit in Active
and Passive Communication mode.
• If bit DetectSync in register ModeReg is set to logic 1 during
FeliCa communication or active communication with transfer
speeds higher than 106 kbit, the bit ProtocolErr is set to logic 1 in
case of a byte length violation.
• During the AutoColl command, bit ProtocolErr is set to logic 1, if
the bit Initiator in register ControlReg is set to logic 1.
• During the MFAuthent Command, bit ProtocolErr is set to logic 1,
if the number of bytes received in one data stream is incorrect.
• Set to logic 1, if the Miller Decoder detects 2 pulses below the
minimum time according to the ISO/IEC 14443A definitions.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.1.8 Status1Reg
Contains status bits of the CRC, Interrupt and FIFO-buffer.
Table 31. Status1Reg register (address 07h); reset value: XXh, X100X01Xb
7 6 5 4 3 2 1 0
RFFreqOK CRCOk CRCReady IRq TRunning RFOn HiAlert LoAlert
Access
Rights
r r r r r rr r
Table 32. Description of Status1Reg bits
Bit Symbol Description
7 RFFreqOK Indicates if the frequency detected at the RX pin is in the range of
13.56 MHz.
Set to logic 1, if the frequency at the RX pin is in the range
12 MHz < RX pin frequency < 15 MHz.
Note: The value of RFFreqOK is not defined if the external RF
frequency is in the range from 9 to 12 MHz or in the range from
15 to 19 MHz.
6 CRCOk Set to logic 1, if the CRC Result is zero. For data transmission and
reception the bit CRCOk is undefined (use CRCErr in register
ErrorReg). CRCOk indicates the status of the CRC co-processor,
during calculation the value changes to ZERO, when the calculation is
done correctly, the value changes to ONE.
5 CRCReady Set to logic 1, when the CRC calculation has finished. This bit is only
valid for the CRC co-processor calculation using the command
CalcCRC.
4 IRq This bit shows, if any interrupt source requests attention (with respect
to the setting of the interrupt enable bits, see register CommIEnReg
and DivIEnReg).
3 TRunning Set to logic 1, if the PN512’s timer unit is running, e.g. the timer will
decrement the TCounterValReg with the next timer clock.
Note: In the gated mode the bit TRunning is set to logic 1, when the
timer is enabled by the register bits. This bit is not influenced by the
gated signal.
2 RFOn Set to logic 1, if an external RF field is detected. This bit does not store
the state of the RF field.
1 HiAlert Set to logic 1, when the number of bytes stored in the FIFO-buffer
fulfills the following equation:
Example:
FIFOLength = 60, WaterLevel = 4 HiAlert = 1
FIFOLength = 59, WaterLevel = 4 HiAlert = 0
0 LoAlert Set to logic 1, when the number of bytes stored in the FIFO-buffer
fulfills the following equation:
Example:
FIFOLength = 4, WaterLevel = 4 LoAlert = 1
FIFOLength = 5, WaterLevel = 4 LoAlert = 0
HiAlert 64 FIFOLength = – WaterLevel
LoAlert FIFOLength WaterLevel = PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.1.9 Status2Reg
Contains status bits of the Receiver, Transmitter and Data mode detector.
Table 33. Status2Reg register (address 08h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
TempSensClear I2CForceHS 0 TargetActivated MFCrypto1On Modem State
Access
Rights
r/w r/w RFU dy dy r r r
Table 34. Description of Status2Reg bits
Bit Symbol Description
7 TempSensClear Set to logic 1, this bit clears the temperature error, if the temperature
is below the alarm limit of 125 C.
6 I2CForceHS I2C input filter settings. Set to logic 1, the I2C input filter is set to the
High-speed mode independent of the I2C protocol. Set to logic 0, the
I
2C input filter is set to the used I2C protocol.
5 - Reserved for future use.
4 TargetActivated Set to logic 1 if the Select command or if the Polling command was
answered. Note: This bit can only be set during the AutoColl
command in Passive Communication mode.
Note: This bit is cleared automatically by switching off the external
RF field.
3 MFCrypto1On This bit indicates that the MIFARE Crypto1 unit is switched on and
therefore all data communication with the card is encrypted.
This bit can only be set to logic 1 by a successful execution of the
MFAuthent Command. This bit is only valid in Reader/Writer mode
for MIFARE cards. This bit shall be cleared by software.
2 to 0 Modem State ModemState shows the state of the transmitter and receiver state
machines.
Value Description
000 IDLE
001 Wait for StartSend in register BitFramingReg
010 TxWait: Wait until RF field is present, if the bit TxWaitRF is
set to logic 1. The minimum time for TxWait is defined by the
TxWaitReg register.
011 Sending
100 RxWait: Wait until RF field is present, if the bit RxWaitRF is
set to logic 1. The minimum time for RxWait is defined by the
RxWaitReg register.
101 Wait for data
110 ReceivingPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.1.10 FIFODataReg
In- and output of 64 byte FIFO-buffer.
9.2.1.11 FIFOLevelReg
Indicates the number of bytes stored in the FIFO.
Table 35. FIFODataReg register (address 09h); reset value: XXh, XXXXXXXXb
7 6 5 4 3 2 1 0
FIFOData
Access
Rights
dy dy dy dy dy dy dy dy
Table 36. Description of FIFODataReg bits
Bit Symbol Description
7 to 0 FIFOData Data input and output port for the internal 64 byte FIFO-buffer. The
FIFO-buffer acts as parallel in/parallel out converter for all serial data
stream in- and outputs.
Table 37. FIFOLevelReg register (address 0Ah); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
FlushBuffer FIFOLevel
Access
Rights
w rrrrrrr
Table 38. Description of FIFOLevelReg bits
Bit Symbol Description
7 FlushBuffer Set to logic 1, this bit clears the internal FIFO-buffer’s read- and
write-pointer and the bit BufferOvfl in the register ErrReg immediately.
Reading this bit will always return 0.
6 to 0 FIFOLevel Indicates the number of bytes stored in the FIFO-buffer. Writing to the
FIFODataReg increments, reading decrements the FIFOLevel.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.1.12 WaterLevelReg
Defines the level for FIFO under- and overflow warning.
9.2.1.13 ControlReg
Miscellaneous control bits.
Table 39. WaterLevelReg register (address 0Bh); reset value: 08h, 00001000b
7 6 5 4 3 2 1 0
0 0 WaterLevel
Access
Rights
RFU RFU r/w r/w r/w r/w r/w r/w
Table 40. Description of WaterLevelReg bits
Bit Symbol Description
7 to 6 - Reserved for future use.
5 to 0 WaterLevel This register defines a warning level to indicate a FIFO-buffer over- or
underflow:
The bit HiAlert in Status1Reg is set to logic 1, if the remaining number
of bytes in the FIFO-buffer space is equal or less than the defined
number of WaterLevel bytes.
The bit LoAlert in Status1Reg is set to logic 1, if equal or less than
WaterLevel bytes are in the FIFO.
Note: For the calculation of HiAlert and LoAlert see Table 31
Table 41. ControlReg register (address 0Ch); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
TStopNow TStartNow WrNFCIDtoFIFO Initiator 0 RxLastBits
Access
Rights
w w dy r/w RFU r r r
Table 42. Description of ControlReg bits
Bit Symbol Description
7 TStopNow Set to logic 1, the timer stops immediately.
Reading this bit will always return 0.
6 TStartNow Set to logic 1 starts the timer immediately.
Reading this bit will always return 0.
5 WrNFCIDtoFIFO Set to logic 1, the internal stored NFCID (10 bytes) is copied into the
FIFO.
Afterwards the bit is cleared automatically
4 Initiator Set to logic 1, the PN512 acts as initiator, otherwise it acts as target
3 - Reserved for future use.
2 to 0 RxLastBits Shows the number of valid bits in the last received byte. If zero, the
whole byte is valid.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.1.14 BitFramingReg
Adjustments for bit oriented frames.
Table 43. BitFramingReg register (address 0Dh); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
StartSend RxAlign 0 TxLastBits
Access
Rights
w r/w r/w r/w RFU r/w r/w r/w
Table 44. Description of BitFramingReg bits
Bit Symbol Description
7 StartSend Set to logic 1, the transmission of data starts.
This bit is only valid in combination with the Transceive command.
6 to 4 RxAlign Used for reception of bit oriented frames: RxAlign defines the bit position
for the first bit received to be stored in the FIFO. Further received bits are
stored at the following bit positions.
Example:
RxAlign = 0: the LSB of the received bit is stored at bit 0, the second
received bit is stored at bit position 1.
RxAlign = 1: the LSB of the received bit is stored at bit 1, the second
received bit is stored at bit position 2.
RxAlign = 7: the LSB of the received bit is stored at bit 7, the second
received bit is stored in the following byte at bit position 0.
This bit shall only be used for bitwise anticollision at 106 kbit/s in Passive
Communication mode. In all other modes it shall be set to logic 0.
3 - Reserved for future use.
2 to 0 TxLastBits Used for transmission of bit oriented frames: TxLastBits defines the
number of bits of the last byte that shall be transmitted. A 000 indicates
that all bits of the last byte shall be transmitted.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.1.15 CollReg
Defines the first bit collision detected on the RF interface.
Table 45. CollReg register (address 0Eh); reset value: XXh, 101XXXXXb
7 6 5 4 3 2 1 0
Values
AfterColl
0 CollPos
NotValid
CollPos
Access
Rights
r/w RFU r r r r r r
Table 46. Description of CollReg bits
Bit Symbol Description
7 ValuesAfterColl If this bit is set to logic 0, all receiving bits will be cleared after a
collision. This bit shall only be used during bitwise anticollision at
106 kbit, otherwise it shall be set to logic 1.
6 - Reserved for future use.
5 CollPosNotValid Set to logic 1, if no Collision is detected or the Position of the
Collision is out of the range of bits CollPos. This bit shall only be
interpreted in Passive Communication mode at 106 kbit or
ISO/IEC 14443A/MIFARE Reader/Writer mode.
4 to 0 CollPos These bits show the bit position of the first detected collision in a
received frame, only data bits are interpreted.
Example:
00h indicates a bit collision in the 32th bit
01h indicates a bit collision in the 1st bit
08h indicates a bit collision in the 8th bit
These bits shall only be interpreted in Passive Communication mode
at 106 kbit or ISO/IEC 14443A/MIFARE Reader/Writer mode if bit
CollPosNotValid is set to logic 0.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2 Page 1: Communication
9.2.2.1 PageReg
Selects the register page.
Table 47. PageReg register (address 10h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
UsePage Select 0 0 0 0 0 PageSelect
Access
Rights
r/w RFU RFU RFU RFU RFU r/w r/w
Table 48. Description of PageReg bits
Bit Symbol Description
7 UsePage Select Set to logic 1, the value of PageSelect is used as register address A5
and A4. The LSB-bits of the register address are defined by the
address pins or the internal address latch, respectively.
Set to logic 0, the whole content of the internal address latch defines
the register address. The address pins are used as described in
Section 10.1 “Automatic microcontroller interface detection”.
6 to 2 - Reserved for future use.
1 to 0 PageSelect The value of PageSelect is used only, if UsePageSelect is set to
logic 1. In this case it specifies the register page (which is A5 and A4
of the register address).PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2.2 ModeReg
Defines general mode settings for transmitting and receiving.
Table 49. ModeReg register (address 11h); reset value: 3Bh, 00111011b
7 6 5 4 3 2 1 0
MSBFirst Detect Sync TxWaitRF RxWaitRF PolSigin ModeDetOff CRCPreset
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 50. Description of ModeReg bits
Bit Symbol Description
7 MSBFirst Set to logic 1, the CRC co-processor calculates the CRC with MSB
first and the CRCResultMSB and the CRCResultLSB in the
CRCResultReg register are bit reversed.
Note: During RF communication this bit is ignored.
6 Detect Sync If set to logic 1, the contactless UART waits for the value F0h before
the receiver is activated and F0h is added as a Sync-byte for
transmission.
This bit is only valid for 106 kbit during NFCIP-1 data exchange
protocol.
In all other modes it shall be set to logic 0.
5 TxWaitRF Set to logic 1 the transmitter in reader/writer or initiator mode for
NFCIP-1 can only be started, if an RF field is generated.
4 RxWaitRF Set to logic 1, the counter for RxWait starts only if an external RF field
is detected in Target mode for NFCIP-1 or in Card Communication
mode.
3 PolSigin PolSigin defines the polarity of the SIGIN pin. Set to logic 1, the
polarity of SIGIN pin is active high. Set to logic 0 the polarity of SIGIN
pin is active low.
Note: The internal envelope signal is coded active low.
Note: Changing this bit will generate a SiginActIRq event.
2 ModeDetOff Set to logic 1, the internal mode detector is switched off.
Note: The mode detector is only active during the AutoColl command.
1 to 0 CRCPreset Defines the preset value for the CRC co-processor for the command
CalCRC.
Note: During any communication, the preset values is selected
automatically according to the definition in the bits RxMode and
TxMode.
Value Description
00 0000
01 6363
10 A671
11 FFFFPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2.3 TxModeReg
Defines the data rate and framing during transmission.
Table 51. TxModeReg register (address 12h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
TxCRCEn TxSpeed InvMod TxMix TxFraming
Access
Rights
r/w dy dy dy r/w r/w dy dy
Table 52. Description of TxModeReg bits
Bit Symbol Description
7 TxCRCEn Set to logic 1, this bit enables the CRC generation during data
transmission.
Note: This bit shall only be set to logic 0 at 106 kbit.
6 to 4 TxSpeed Defines the bit rate while data transmission.
Value Description
000 106 kbit
001 212 kbit
010 424 kbit
011 848 kbit
100 1696 kbit
101 3392 kbit
110 Reserved
111 Reserved
Note: The bit coding for transfer speeds above 424 kbit is equivalent to
the bit coding of Active Communication mode 424 kbit (Ecma 340).
3 InvMod Set to logic 1, the modulation for transmitting data is inverted.
2 TxMix Set to logic 1, the signal at pin SIGIN is mixed with the internal coder
(see Section 12.6 “S2C interface support”).
1 to 0 TxFraming Defines the framing used for data transmission.
Value Description
00 ISO/IEC 14443A/MIFARE and Passive Communication mode
106 kbit
01 Active Communication mode
10 FeliCa and Passive communication mode 212 and 424 kbit
11 ISO/IEC 14443BPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2.4 RxModeReg
Defines the data rate and framing during reception.
Table 53. RxModeReg register (address 13h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
RxCRCEn RxSpeed RxNoErr RxMultiple RxFraming
Access
Rights
r/w dy dy dy r/w r/w dy dy
Table 54. Description of RxModeReg bits
Bit Symbol Description
7 RxCRCEn Set to logic 1, this bit enables the CRC calculation during reception.
Note: This bit shall only be set to logic 0 at 106 kbit.
6 to 4 RxSpeed Defines the bit rate while data transmission.
The PN512’s analog part handles only transfer speeds up to 424 kbit
internally, the digital UART handles the higher transfer speeds as well.
Value Description
000 106 kbit
001 212 kbit
010 424 kbit
011 848 kbit
100 1696 kbit
101 3392 kbit
110 Reserved
111 Reserved
Note: The bit coding for transfer speeds above 424 kbit is equivalent to
the bit coding of Active Communication mode 424 kbit (Ecma 340).
3 RxNoErr If set to logic 1 a not valid received data stream (less than 4 bits
received) will be ignored. The receiver will remain active.
For ISO/IEC14443B also RxSOFReq logic 1 is required to ignore a non
valid datastream.
2 RxMultiple Set to logic 0, the receiver is deactivated after receiving a data frame.
Set to logic 1, it is possible to receive more than one data frame. Having
set this bit, the receive and transceive commands will not terminate
automatically. In this case the multiple receiving can only be deactivated
by writing any command (except the Receive command) to the
CommandReg register or by clearing the bit by the host controller.
At the end of a received data stream an error byte is added to the FIFO.
The error byte is a copy of the ErrorReg register.
The behaviour for version 1.0 is described in Section 21 “Errata sheet”
on page 109.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2.5 TxControlReg
Controls the logical behavior of the antenna driver pins Tx1 and Tx2.
1 to 0 RxFraming Defines the expected framing for data reception.
Value Description
00 ISO/IEC 14443A/MIFARE and Passive Communication
mode 106 kbit
01 Active Communication mode
10 FeliCa and Passive Communication mode 212 and 424 kbit
11 ISO/IEC 14443B
Table 54. Description of RxModeReg bits
Bit Symbol Description
Table 55. TxControlReg register (address 14h); reset value: 80h, 10000000b
7 6 5 4 3 2 1 0
InvTx2RF
On
InvTx1RF
On
InvTx2RF
Off
InvTx1RF
Off
Tx2CW CheckRF Tx2RF
En
Tx1RF
En
Access
Rights
r/w r/w r/w r/w r/w w r/w r/w
Table 56. Description of TxControlReg bits
Bit Symbol Description
7 InvTx2RFOn Set to logic 1, the output signal at pin TX2 will be inverted, if driver TX2
is enabled.
6 InvTx1RFOn Set to logic 1, the output signal at pin TX1 will be inverted, if driver TX1
is enabled.
5 InvTx2RFOff Set to logic 1, the output signal at pin TX2 will be inverted, if driver TX2
is disabled.
4 InvTx1RFOff Set to logic 1, the output signal at pin TX1 will be inverted, if driver TX1
is disabled.
3 Tx2CW Set to logic 1, the output signal on pin TX2 will deliver continuously the
un-modulated 13.56 MHz energy carrier.
Set to logic 0, Tx2CW is enabled to modulate the 13.56 MHz energy
carrier.
2 CheckRF Set to logic 1, Tx2RFEn and Tx1RFEn can not be set if an external RF
field is detected. Only valid when using in combination with bit
Tx2RFEn or Tx1RFEn
1 Tx2RFEn Set to logic 1, the output signal on pin TX2 will deliver the 13.56 MHz
energy carrier modulated by the transmission data.
0 Tx1RFEn Set to logic 1, the output signal on pin TX1 will deliver the 13.56 MHz
energy carrier modulated by the transmission data.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2.6 TxAutoReg
Controls the settings of the antenna driver.
Table 57. TxAutoReg register (address 15h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
AutoRF
OFF
Force100
ASK
Auto
WakeUp
0 CAOn InitialRF
On
Tx2RFAut
oEn
Tx1RFAuto
En
Access
Rights
r/w r/w r/w RFU r/w r/w r/w r/w
Table 58. Description of TxAutoReg bits
Bit Symbol Description
7 AutoRFOFF Set to logic 1, all active antenna drivers are switched off after the last
data bit has been transmitted as defined in the NFCIP-1.
6 Force100ASK Set to logic 1, Force100ASK forces a 100% ASK modulation
independent of the setting in register ModGsPReg.
5 AutoWakeUp Set to logic 1, the PN512 in soft Power-down mode will be started by
the RF level detector.
4 - Reserved for future use.
3 CAOn Set to logic 1, the collision avoidance is activated and internally the
value n is set in accordance to the NFCIP-1 Standard.
2 InitialRFOn Set to logic 1, the initial RF collision avoidance is performed and the bit
InitialRFOn is cleared automatically, if the RF is switched on.
Note: The driver, which should be switched on, has to be enabled by
bit Tx2RFAutoEn or bit Tx1RFAutoEn.
1 Tx2RFAutoEn Set to logic 1, the driver Tx2 is switched on after the external RF field
is switched off according to the time TADT. If the bits InitialRFOn and
Tx2RFAutoEn are set to logic 1, Tx2 is switched on if no external RF
field is detected during the time TIDT.
Note: The times TADT and TIDT are defined in the NFC IP-1 standard
(ISO/IEC 18092).
0 Tx1RFAutoEn Set to logic 1, the driver Tx1 is switched on after the external RF field
is switched off according to the time TADT. If the bit InitialRFOn and
Tx1RFAutoEn are set to logic 1, Tx1 is switched on if no external RF
field is detected during the time TIDT.
Note: The times TADT and TIDT are defined in the NFC IP-1 standard
(ISO/IEC 18092).PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2.7 TxSelReg
Selects the sources for the analog part.
Table 59. TxSelReg register (address 16h); reset value: 10h, 00010000b
7 6 5 4 3 2 1 0
0 0 DriverSel SigOutSel
Access
Rights
RFU RFU r/w r/w r/w r/w r/w r/w
Table 60. Description of TxSelReg bits
Bit Symbol Description
7 to 6 - Reserved for future use.
5 to 4 DriverSel Selects the input of driver Tx1 and Tx2.
Value Description
00 Tristate
Note: In soft power down the drivers are only in Tristate mode
if DriverSel is set to Tristate mode.
01 Modulation signal (envelope) from the internal coder
10 Modulation signal (envelope) from SIGIN
11 HIGH
Note: The HIGH level depends on the setting of InvTx1RFOn/
InvTx1RFOff and InvTx2RFOn/InvTx2RFOff.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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3 to 0 SigOutSel Selects the input for the SIGOUT Pin.
Value Description
0000 Tristate
0001 Low
0010 High
0011 TestBus signal as defined by bit TestBusBitSel in register
TestSel1Reg.
0100 Modulation signal (envelope) from the internal coder
0101 Serial data stream to be transmitted
0110 Output signal of the receiver circuit (card modulation signal
regenerated and delayed). This signal is used as data output
signal for SAM interface connection using 3 lines.
Note: To have a valid signal the PN512 has to be set to the
receiving mode by either the Transceive or Receive
command. The bit RxMultiple can be used to keep the PN512
in receiving mode.
Note: Do not use this setting in MIFARE mode. Manchester
coding as data collisions will not be transmitted on the
SIGOUT line.
0111 Serial data stream received.
Note: Do not use this setting in MIFARE mode. Miller coding
parameters as the bit length can vary.
1000-1011 FeliCa Sam modulation
1000 RX*
1001 TX
1010 Demodulator comparator output
1011 RFU
Note: * To have a valid signal the PN512 has to be set to the
receiving mode by either the Transceive or Receive
command. The bit RxMultiple can be used to keep the PN512
in receiving mode.
1100-1111 MIFARE Sam modulation
1100 RX* with RF carrier
1101 TX with RF carrier
1110 RX with RF carrier un-filtered
1111 RX envelope un-filtered
Note: *To have a valid signal the PN512 has to be set to the
receiving mode by either the Transceive or Receive
command. The bit RxMultiple can be used to keep the PN512
in receiving mode.
Table 60. Description of TxSelReg bits …continued
Bit Symbol DescriptionPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2.8 RxSelReg
Selects internal receiver settings.
9.2.2.9 RxThresholdReg
Selects thresholds for the bit decoder.
Table 61. RxSelReg register (address 17h); reset value: 84h, 10000100b
7 6 5 4 3 2 1 0
UartSel RxWait
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 62. Description of RxSelReg bits
Bit Symbol Description
7 to 6 UartSel Selects the input of the contactless UART
Value Description
00 Constant Low
01 Envelope signal at SIGIN
10 Modulation signal from the internal analog part
11 Modulation signal from SIGIN pin. Only valid for transfer
speeds above 424 kbit
5 to 0 RxWait After data transmission, the activation of the receiver is delayed for
RxWait bit-clocks. During this ‘frame guard time’ any signal at pin RX
is ignored. This parameter is ignored by the Receive command. All
other commands (e.g. Transceive, Autocoll, MFAuthent) use this
parameter. Depending on the mode of the PN512, the counter starts
different. In Passive Communication mode the counter starts with the
last modulation pulse of the transmitted data stream. In Active
Communication mode the counter starts immediately after the external
RF field is switched on.
Table 63. RxThresholdReg register (address 18h); reset value: 84h, 10000100b
7 6 5 4 3 2 1 0
MinLevel 0 CollLevel
Access
Rights
r/w r/w r/w r/w RFU r/w r/w r/w
Table 64. Description of RxThresholdReg bits
Bit Symbol Description
7 to 4 MinLevel Defines the minimum signal strength at the decoder input that shall be
accepted. If the signal strength is below this level, it is not evaluated.
3 - Reserved for future use.
2 to 0 CollLevel Defines the minimum signal strength at the decoder input that has to be
reached by the weaker half-bit of the Manchester-coded signal to
generate a bit-collision relatively to the amplitude of the stronger half-bit.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2.10 DemodReg
Defines demodulator settings.
Table 65. DemodReg register (address 19h); reset value: 4Dh, 01001101b
7 6 5 4 3 2 1 0
AddIQ FixIQ TPrescal
Even
TauRcv TauSync
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 66. Description of DemodReg bits
Bit Symbol Description
7 to 6 AddIQ Defines the use of I and Q channel during reception
Note: FixIQ has to be set to logic 0 to
enable the following settings.
Value Description
00 Select the stronger channel
01 Select the stronger and freeze the selected during communication
10 combines the I and Q channel
11 Reserved
5 FixIQ If set to logic 1 and the bits of AddIQ are set to X0, the reception is fixed to
I channel.
If set to logic 1 and the bits of AddIQ are set to X1, the reception is fixed to
Q channel.
NOTE: If SIGIN/SIGOUT is used as S2C interface FixIQ set to 1 and AddIQ
set to X0 is rewired.
4 TPrescalE
ven
If set to logic 0 the following formula is used to calculate fTimer of the
prescaler:
fTimer = 13.56 MHz / (2 * TPreScaler + 1).
If set to logic 1 the following formula is used to calculate fTimer of the
prescaler:
fTimer = 13.56 MHz / (2 * TPreScaler + 2).
(Default TPrescalEven is logic 0)
The behaviour for the version 1.0 is described in Section 21 “Errata
sheet” on page 109.
3 to 2 TauRcv Changes the time constant of the internal during data reception.
Note: If set to 00, the PLL is frozen during data reception.
1 to 0 TauSync Changes the time constant of the internal PLL during burst.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2.11 FelNFC1Reg
Defines the length of the FeliCa Sync bytes and the minimum length of the received
packet.
Table 67. FelNFC1Reg register (address 1Ah); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
FelSyncLen DataLenMin
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 68. Description of FelNFC1Reg bits
Bit Symbol Description
7 to 6 FelSyncLen Defines the length of the Sync bytes.
Value Sync- bytes in hex
00 B2 4D
01 00 B2 4D
10 00 00 B2 4D
11 00 00 00 B2 4D
5 to 0 DataLenMin These bits define the minimum length of the accepted packet length:
DataLenMin * 4 data packet length
This parameter is ignored at 106 kbit if the bit DetectSync in register
ModeReg is set to logic 0. If a received data packet is shorter than the
defined DataLenMin value, the data packet will be ignored.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2.12 FelNFC2Reg
Defines the maximum length of the received packet.
Table 69. FelNFC2Reg register (address1Bh); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
WaitForSelected ShortTimeSlot DataLenMax
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 70. Description of FelNFC2Reg bits
Bit Symbol Description
7 WaitForSelected Set to logic 1, the AutoColl command is only terminated
automatically when:
1. A valid command has been received after performing a valid
Select procedure according ISO/IEC 14443A.
2. A valid command has been received after performing a valid
Polling procedure according to the FeliCa specification.
Note: If this bit is set, no active communication is possible.
Note: Setting this bit reduces the host controller interaction in case
of a communication to another device in the same RF field during
Passive Communication mode.
6 ShortTimeSlot Defines the time slot length for Passive Communication mode at
424 kbit. Set to logic 1 a short time slot is used (half of the timeslot
at 212 kbit). Set to logic 0 a long timeslot is used (equal to the
timeslot for 212 kbit).
5 to 0 DataLenMax These bits define the maximum length of the accepted packet
length: DataLenMax * 4 data packet length
Note: If set to logic 0 the maximum data length is 256 bytes.
This parameter is ignored at 106 kbit if the bit DetectSync in
register ModeReg is set to logic 0. If a received packet is larger
than the defined DataLenMax value, the packet will be ignored.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2.13 MifNFCReg
Defines ISO/IEC 14443A/MIFARE/NFC specific settings in target or Card Operating
mode.
Table 71. MifNFCReg register (address 1Ch); reset value: 62h, 01100010b
7 6 5 4 3 2 1 0
SensMiller TauMiller MFHalted TxWait
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 72. Description of MifNFCReg bits
Bit Symbol Description
7 to 5 SensMiller These bits define the sensitivity of the Miller decoder.
4 to 3 TauMiller These bits define the time constant of the Miller decoder.
2 MFHalted Set to logic 1, this bit indicates that the PN512 is set to HALT mode in
Card Operation mode at 106 kbit. This bit is either set by the host
controller or by the internal state machine and indicates that only the
code 52h is accepted as a request command. This bit is cleared
automatically by a RF reset.
1 to 0 TxWait These bits define the minimum response time between receive and
transmit in number of data bits + 7 data bits.
The shortest possible minimum response time is 7 data bits.
(TxWait=0). The minimum response time can be increased by the
number of bits defined in TxWait. The longest minimum response time
is 10 data bits (TxWait = 3).
If a transmission of a frame is started before the minimum response
time is over, the PN512 waits before transmitting the data until the
minimum response time is over.
If a transmission of a frame is started after the minimum response time
is over, the frame is started immediately if the data bit synchronization
is correct. (adjustable with TxBitPhase).PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2.14 ManualRCVReg
Allows manual fine tuning of the internal receiver.
Remark: For standard applications it is not recommended to change this register settings.
Table 73. ManualRCVReg register (address 1Dh); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
0 FastFilt
MF_SO
Delay
MF_SO
Parity
Disable
LargeBW
PLL
Manual
HPCF
HPFC
Access
Rights
RFU r/w r/w r/w r/w r/w r/w r/w
Table 74. Description of ManualRCVReg bits
Bit Symbol Description
7 - Reserved for future use.
6 FastFilt
MF_SO
If this bit is set to logic 1, the internal filter for the Miller-Delay Circuit is
set to Fast mode.
Note: This bit should only set to logic 1, if Millerpulses of less than
400 ns Pulse length are expected. At 106 kBaud the typical value is
3 us.
5 Delay MF_SO If this bit is set to logic 1, the Signal at SIGOUT-pin is delayed, so that
in SAM mode the Signal at SIGIN must be 128/fc faster compared to
the ISO/IEC 14443A, to reach the ISO/IEC 14443A restrictions on the
RF-Field.
Note: This delay shall only be activated for setting bits SigOutSel to
(1110b) or (1111b) in register TxSelReg.
4 Parity Disable If this bit is set to logic 1, the generation of the Parity bit for
transmission and the Parity-Check for receiving is switched off. The
received Parity bit is handled like a data bit.
3 LargeBWPLL Set to logic 1, the bandwidth of the internal PLL used for clock
recovery is extended.
2 ManualHPCF Set to logic 0, the HPCF bits are ignored and the HPCF settings are
adapted automatically to the receiving mode. Set to logic 1, values of
HPCF are valid.
1 to 0 HPFC Selects the High Pass Corner Frequency (HPCF) of the filter in the
internal receiver chain
00 For signals with frequency spectrum down to 106 kHz.
01 For signals with frequency spectrum down to 212 kHz.
10 For signals with frequency spectrum down to 424 kHz.
11 For signals with frequency spectrum down to 848 kHzPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2.15 TypeBReg
9.2.2.16 SerialSpeedReg
Selects the speed of the serial UART interface.
Table 75. TypeBReg register (address 1Eh); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
RxSOF
Req
RxEOF
Req
0 EOFSO
FWidth
NoTxSOF NoTxEOF TxEGT
Access
Rights
r/w r/w RFU r/w r/w r/w r/w r/w
Table 76. Description of TypeBReg bits
Bit Symbol Description
7 RxSOFReq If this bit is set to logic 1, the SOF is required. A datastream starting
without SOF is ignored.
If this bit is cleared, a datastream with and without SOF is accepted.
The SOF will be removed and not written into the FIFO.
6 RxEOFReq If this bit is set to logic 1, the EOF is required. A datastream ending
without EOF will generate a Protocol-Error. If this bit is cleared, a
datastream with and without EOF is accepted. The EOF will be
removed and not written into the FIFO.
For the behaviour in version 1.0, see Section 21 “Errata sheet” on
page 109.
5 - Reserved for future use.
4 EOFSOFWidth If this bit is set to logic 1 and EOFSOFAdjust bit is logic 0, the SOF
and EOF will have the maximum length defined in ISO/IEC 14443B.
If this bit is cleared and EOFSOFAdjust bit is logic 0, the SOF and
EOF will have the minimum length defined in ISO/IEC 14443B.
If this bit is set to 1 and the EOFSOFadjust bit is logic 1 will result in
SOF low = (11etu 8 cycles)/fc
SOF high = (2 etu + 8 cycles)/fc
EOF low = (11 etu 8 cycles)/fc
If this bit is set to 0 and the EOFSOFAdjust bit is logic 1 will result in
an incorrect system behavior in respect to ISO specification.
For the behaviour in version 1.0, see Section 21 “Errata sheet” on
page 109.
3 NoTxSOF If this bit is set to logic 1, the generation of the SOF is suppressed.
2 NoTxEOF If this bit is set to logic 1, the generation of the EOF is suppressed.
1 to 0 TxEGT These bits define the length of the EGT.
Value Description
00 0 bit
01 1 bit
10 2 bits
11 3 bitsPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Table 77. SerialSpeedReg register (address 1Fh); reset value: EBh, 11101011b
7 6 5 4 3 2 1 0
BR_T0 BR_T1
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 78. Description of SerialSpeedReg bits
Bit Symbol Description
7 to 5 BR_T0 Factor BR_T0 to adjust the transfer speed, for description see Section
10.3.2 “Selectable UART transfer speeds”.
3 to 0 BR_T1 Factor BR_T1 to adjust the transfer speed, for description see Section
10.3.2 “Selectable UART transfer speeds”.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.3 Page 2: Configuration
9.2.3.1 PageReg
Selects the register page.
9.2.3.2 CRCResultReg
Shows the actual MSB and LSB values of the CRC calculation.
Note: The CRC is split into two 8-bit register.
Note: Setting the bit MSBFirst in ModeReg register reverses the bit order, the byte order is
not changed.
Table 79. PageReg register (address 20h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
UsePageSelect 0 0 0 0 0 PageSelect
Access Rights r/w RFU RFU RFU RFU RFU r/w r/w
Table 80. Description of PageReg bits
Bit Symbol Description
7 UsePageSelect Set to logic 1, the value of PageSelect is used as register address A5
and A4. The LSB-bits of the register address are defined by the
address pins or the internal address latch, respectively.
Set to logic 0, the whole content of the internal address latch defines
the register address. The address pins are used as described in
Section 10.1 “Automatic microcontroller interface detection”.
6 to 2 - Reserved for future use.
1 to 0 PageSelect The value of PageSelect is used only if UsePageSelect is set to
logic 1. In this case, it specifies the register page (which is A5 and
A4of the register address).
Table 81. CRCResultReg register (address 21h); reset value: FFh, 11111111b
7 6 5 4 3 2 1 0
CRCResultMSB
Access Rights r r r r r r r r
Table 82. Description of CRCResultReg bits
Bit Symbol Description
7 to 0 CRCResultMSB This register shows the actual value of the most significant byte of
the CRCResultReg register. It is valid only if bit CRCReady in
register Status1Reg is set to logic 1.
Table 83. CRCResultReg register (address 22h); reset value: FFh, 11111111b
7 6 5 4 3 2 1 0
CRCResultLSB
Access Rights r r r r r r r r
Table 84. Description of CRCResultReg bits
Bit Symbol Description
7 to 0 CRCResultLSB This register shows the actual value of the least significant byte of
the CRCResult register. It is valid only if bit CRCReady in register
Status1Reg is set to logic 1.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.3.3 GsNOffReg
Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the
driver is switched off.
Table 85. GsNOffReg register (address 23h); reset value: 88h, 10001000b
7 6 5 4 3 2 1 0
CWGsNOff ModGsNOff
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 86. Description of GsNOffReg bits
Bit Symbol Description
7 to 4 CWGsNOff The value of this register defines the conductance of the output
N-driver during times of no modulation.
Note: The conductance value is binary weighted.
Note: During soft Power-down mode the highest bit is forced to 1.
Note: The value of the register is only used if the driver is switched
off. Otherwise the bit value CWGsNOn of register GsNOnReg is
used.
Note: This value is used for LoadModulation.
3 to 0 ModGsNOff The value of this register defines the conductance of the output
N-driver for the time of modulation. This may be used to regulate the
modulation index.
Note: The conductance value is binary weighted.
Note: During soft Power-down mode the highest bit is forced to 1.
Note: The value of the register is only used if the driver is switched
off. Otherwise the bit value ModGsNOn of register GsNOnReg is
used
Note: This value is used for LoadModulation.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.3.4 ModWidthReg
Controls the modulation width settings.
9.2.3.5 TxBitPhaseReg
Adjust the bitphase at 106 kbit during transmission.
Table 87. ModWidthReg register (address 24h); reset value: 26h, 00100110b
7 6 5 4 3 2 1 0
ModWidth
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 88. Description of ModWidthReg bits
Bit Symbol Description
7 to 0 ModWidth These bits define the width of the Miller modulation as initiator in Active
and Passive Communication mode as multiples of the carrier
frequency (ModWidth + 1/fc). The maximum value is half the bit
period.
Acting as a target in Passive Communication mode at 106 kbit or in
Card Operating mode for ISO/IEC 14443A/MIFARE these bits are
used to change the duty cycle of the subcarrier frequency.
The resulting number of carrier periods are calculated according to the
following formulas:
LOW value: #clocksLOW = (ModWidth modulo 8) + 1.
HIGH value: #clocksHIGH = 16-#clocksLOW.
Table 89. TxBitPhaseReg register (address 25h); reset value: 87h, 10000111b
7 6 5 4 3 2 1 0
RcvClkChange TxBitPhase
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 90. Description of TxBitPhaseReg bits
Bit Symbol Description
7 RcvClkChange Set to logic 1, the demodulator’s clock is derived by the external RF
field.
6 to 0 TxBitPhase These bits are representing the number of carrier frequency clock
cycles, which are added to the waiting period before transmitting
data in all communication modes. TXBitPhase is used to adjust the
TX bit synchronization during passive NFCIP-1 communication mode
at 106 kbit and in ISO/IEC 14443A/MIFARE card mode.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.3.6 RFCfgReg
Configures the receiver gain and RF level detector sensitivity.
Table 91. RFCfgReg register (address 26h); reset value: 48h, 01001000b
7 6 5 4 3 2 1 0
RFLevelAmp RxGain RFLevel
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 92. Description of RFCfgReg bits
Bit Symbol Description
7 RFLevelAmp Set to logic 1, this bit activates the RF level detectors’ amplifier.
6 to 4 RxGain This register defines the receivers signal voltage gain factor:
Value Description
000 18 dB
001 23 dB
010 18 dB
011 23 dB
100 33 dB
101 38 dB
110 43 dB
111 48 dB
3 to 0 RFLevel Defines the sensitivity of the RF level detector, for description see
Section 12.3 “RF level detector”.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.3.7 GsNOnReg
Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the
driver is switched on.
9.2.3.8 CWGsPReg
Defines the conductance of the P-driver during times of no modulation
Table 93. GsNOnReg register (address 27h); reset value: 88h, 10001000b
7 6 5 4 3 2 1 0
CWGsNOn ModGsNOn
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 94. Description of GsNOnReg bits
Bit Symbol Description
7 to 4 CWGsNOn The value of this register defines the conductance of the output
N-driver during times of no modulation. This may be used to regulate
the output power and subsequently current consumption and
operating distance.
Note: The conductance value is binary weighted.
Note: During soft Power-down mode the highest bit is forced to 1.
Note: This value is only used if the driver TX1 or TX2 are switched on.
Otherwise the value of the bits CWGsNOff of register GsNOffReg is
used.
3 to 0 ModGsNOn The value of this register defines the conductance of the output
N-driver for the time of modulation. This may be used to regulate the
modulation index.
Note: The conductance value is binary weighted.
Note: During soft Power-down mode the highest bit is forced to 1.
Note: This value is only used if the driver TX1 or Tx2 are switched on.
Otherwise the value of the bits ModsNOff of register GsNOffReg is
used.
Table 95. CWGsPReg register (address 28h); reset value: 20h, 00100000b
7 6 5 4 3 2 1 0
0 0 CWGsP
Access
Rights
RFU RFU r/w r/w r/w r/w r/w r/w
Table 96. Description of CWGsPReg bits
Bit Symbol Description
7 to 6 - Reserved for future use.
5 to 0 CWGsP The value of this register defines the conductance of the output
P-driver. This may be used to regulate the output power and
subsequently current consumption and operating distance.
Note: The conductance value is binary weighted.
Note: During soft Power-down mode the highest bit is forced to 1.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.3.9 ModGsPReg
Defines the driver P-output conductance during modulation.
[1] If Force100ASK is set to logic 1, the value of ModGsP has no effect.
9.2.3.10 TMode Register, TPrescaler Register
Defines settings for the timer.
Note: The Prescaler value is split into two 8-bit registers
Table 97. ModGsPReg register (address 29h); reset value: 20h, 00100000b
7 6 5 4 3 2 1 0
0 0 ModGsP
Access
Rights
RFU RFU r/w r/w r/w r/w r/w r/w
Table 98. Description of ModGsPReg bits
Bit Symbol Description
7 to 6 - Reserved for future use.
5 to 0 ModGsP[1] The value of this register defines the conductance of the output
P-driver for the time of modulation. This may be used to regulate the
modulation index.
Note: The conductance value is binary weighted.
Note: During soft Power-down mode the highest bit is forced to 1.
Table 99. TModeReg register (address 2Ah); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
TAuto TGated TAutoRestart TPrescaler_Hi
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 100. Description of TModeReg bits
Bit Symbol Description
7 TAuto Set to logic 1, the timer starts automatically at the end of the transmission
in all communication modes at all speeds or when bit InitialRFOn is set to
logic 1 and the RF field is switched on.
In mode MIFARE and ISO14443-B 106kbit/s the timer stops after the 5th
bit (1 startbit, 4 databits) if the bit RxMultiple in the register RxModeReg is
not set. In all other modes, the timer stops after the 4th bit if the bit
RxMultiple the register RxModeReg is not set.
If RxMultiple is set to logic 1, the timer never stops. In this case the timer
can be stopped by setting the bit TStopNow in register ControlReg to 1.
Set to logic 0 indicates, that the timer is not influenced by the protocol.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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6 to 5 TGated The internal timer is running in gated mode.
Note: In the gated mode, the bit TRunning is 1 when the timer is enabled
by the register bits. This bit does not influence the gating signal.
Value Description
00 Non gated mode
01 Gated by SIGIN
10 Gated by AUX1
11 Gated by A3
4 TAutoRestart Set to logic 1, the timer automatically restart its count-down from
TReloadValue, instead of counting down to zero.
Set to logic 0 the timer decrements to ZERO and the bit TimerIRq is set
to logic 1.
3 to 0 TPrescaler_Hi Defines higher 4 bits for TPrescaler.
The following formula is used to calculate fTimer if TPrescalEven bit in
Demot Reg is set to logic 0:
fTimer = 13.56 MHz/(2*TPreScaler+1).
Where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] (TPrescaler value
on 12 bits) (Default TPrescalEven is logic 0)
The following formula is used to calculate fTimer if TPrescalEven bit in
Demot Reg is set to logic 1:
fTimer = 13.56 MHz/(2*TPreScaler+2).
For detailed description see Section 15 “Timer unit”. For the behaviour
within version 1.0, see Section 21 “Errata sheet” on page 109.
Table 101. TPrescalerReg register (address 2Bh); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
TPrescaler_Lo
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 102. Description of TPrescalerReg bits
Bit Symbol Description
7 to 0 TPrescaler_Lo Defines lower 8 bits for TPrescaler.
The following formula is used to calculate fTimer if TPrescalEven bit in
Demot Reg is set to logic 0:
fTimer = 13.56 MHz/(2*TPreScaler+1).
Where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] (TPrescaler value
on 12 bits)
The following formula is used to calculate fTimer if TPrescalEven bit in
Demot Reg is set to logic 1:
fTimer = 13.56 MHz/(2*TPreScaler+2).
Where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] (TPrescaler value
on 12 bits)
For detailed description see Section 15 “Timer unit”.
Table 100. Description of TModeReg bits …continued
Bit Symbol DescriptionPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.3.11 TReloadReg
Describes the 16-bit long timer reload value.
Note: The Reload value is split into two 8-bit registers.
Table 103. TReloadReg (Higher bits) register (address 2Ch); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
TReloadVal_Hi
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 104. Description of the higher TReloadReg bits
Bit Symbol Description
7 to 0 TReloadVal_Hi Defines the higher 8 bits for the TReloadReg.
With a start event the timer loads the TReloadVal. Changing this
register affects the timer only at the next start event.
Table 105. TReloadReg (Lower bits) register (address 2Dh); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
TReloadVal_Lo
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 106. Description of lower TReloadReg bits
Bit Symbol Description
7 to 0 TReloadVal_Lo Defines the lower 8 bits for the TReloadReg.
With a start event the timer loads the TReloadVal. Changing this
register affects the timer only at the next start event. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.3.12 TCounterValReg
Contains the current value of the timer.
Note: The Counter value is split into two 8-bit register.
9.2.4 Page 3: Test
9.2.4.1 PageReg
Selects the register page.
Table 107. TCounterValReg (Higher bits) register (address 2Eh); reset value: XXh,
XXXXXXXXb
7 6 5 4 3 2 1 0
TCounterVal_Hi
Access
Rights
rrrrrrrr
Table 108. Description of the higher TCounterValReg bits
Bit Symbol Description
7 to 0 TCounterVal_Hi Current value of the timer, higher 8 bits.
Table 109. TCounterValReg (Lower bits) register (address 2Fh); reset value: XXh,
XXXXXXXXb
7 6 5 4 3 2 1 0
TCounterVal_Lo
Access
Rights
rrrrrrrr
Table 110. Description of lower TCounterValReg bits
Bit Symbol Description
7 to 0 TCounterVal_Lo Current value of the timer, lower 8 bits.
Table 111. PageReg register (address 30h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
UsePageSelect 0 0 0 0 0 PageSelect
Access
Rights
r/w RFU RFU RFU RFU RFU r/w r/wPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Table 112. Description of PageReg bits
Bit Symbol Description
7 UsePageSelect Set to logic 1, the value of PageSelect is used as register address
A5 and A4. The LSB-bits of the register address are defined by the
address pins or the internal address latch, respectively.
Set to logic 0, the whole content of the internal address latch defines
the register address. The address pins are used as described in
Section 10.1 “Automatic microcontroller interface detection”.
6 to 2 - Reserved for future use.
1 to 0 PageSelect The value of PageSelect is used only if UsePageSelect is set to
logic 1. In this case, it specifies the register page (which is A5 and
A4 of the register address).PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.4.2 TestSel1Reg
General test signal configuration.
9.2.4.3 TestSel2Reg
General test signal configuration and PRBS control
Table 113. TestSel1Reg register (address 31h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
- - SAMClockSel SAMClkD1 TstBusBitSel
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 114. Description of TestSel1Reg bits
Bit Symbol Description
7 to 6 - Reserved for future use.
5 to 4 SAMClockSel Defines the source for the 13.56 MHz SAM clock
Value Description
00 GND- Sam Clock switched off
01 clock derived by the internal oscillator
10 internal UART clock
11 clock derived by the RF field
3 SAMClkD1 Set to logic 1, the SAM clock is delivered to D1.
Note: Only possible if the 8bit parallel interface is not used.
2 to 0 TstBusBitSel Select the TestBus bit from the testbus to be propagated to SIGOUT.
Table 115. TestSel2Reg register (address 32h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
TstBusFlip PRBS9 PRBS15 TestBusSel
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 116. Description of TestSel2Reg bits
Bit Symbol Description
7 TstBusFlip If set to logic 1, the testbus is mapped to the parallel port by the
following order:
D4, D3, D2, D6, D5, D0, D1. See Section 20 “Testsignals”.
6 PRBS9 Starts and enables the PRBS9 sequence according ITU-TO150.
Note: All relevant registers to transmit data have to be configured
before entering PRBS9 mode.
Note: The data transmission of the defined sequence is started by the
send command.
5 PRBS15 Starts and enables the PRBS15 sequence according ITU-TO150.
Note: All relevant registers to transmit data have to be configured
before entering PRBS15 mode.
Note: The data transmission of the defined sequence is started by the
send command.
4 to 0 TestBusSel Selects the testbus. See Section 20 “Testsignals”PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.4.4 TestPinEnReg
Enables the pin output driver on the 8-bit parallel bus.
9.2.4.5 TestPinValueReg
Defines the values for the 7-bit parallel port when it is used as I/O.
Table 117. TestPinEnReg register (address 33h); reset value: 80h, 10000000b
7 6 5 4 3 2 1 0
RS232LineEn TestPinEn
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 118. Description of TestPinEnReg bits
Bit Symbol Description
7 RS232LineEn Set to logic 0, the lines MX and DTRQ for the serial UART are
disabled.
6 to 0 TestPinEn Enables the pin output driver on the 8-bit parallel interface.
Example:
Setting bit 0 to 1 enables D0
Setting bit 5 to 1 enables D5
Note: Only valid if one of serial interfaces is used.
If the SPI interface is used only D0 to D4 can be used. If the serial
UART interface is used and RS232LineEn is set to logic 1 only D0 to
D4 can be used.
Table 119. TestPinValueReg register (address 34h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
UseIO TestPinValue
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 120. Description of TestPinValueReg bits
Bit Symbol Description
7 UseIO Set to logic 1, this bit enables the I/O functionality for the 7-bit parallel
port in case one of the serial interfaces is used. The input/output
behavior is defined by TestPinEn in register TestPinEnReg. The value
for the output behavior is defined in the bits TestPinVal.
Note: If SAMClkD1 is set to logic 1, D1 can not be used as I/O.
6 to 0 TestPinValue Defines the value of the 7-bit parallel port, when it is used as I/O. Each
output has to be enabled by the TestPinEn bits in register
TestPinEnReg.
Note: Reading the register indicates the actual status of the pins D6 -
D0 if UseIO is set to logic 1. If UseIO is set to logic 0, the value of the
register TestPinValueReg is read back. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.4.6 TestBusReg
Shows the status of the internal testbus.
9.2.4.7 AutoTestReg
Controls the digital selftest.
9.2.4.8 VersionReg
Shows the version.
Table 121. TestBusReg register (address 35h); reset value: XXh, XXXXXXXXb
7 6 5 4 3 2 1 0
TestBus
Access Rights r r r r r r r r
Table 122. Description of TestBusReg bits
Bit Symbol Description
7 to 0 TestBus Shows the status of the internal testbus. The testbus is selected by the
register TestSel2Reg. See Section 20 “Testsignals”.
Table 123. AutoTestReg register (address 36h); reset value: 40h, 01000000b
7 6 5 4 3 2 1 0
0 AmpRcv EOFSO
FAdjust
- SelfTest
Access Rights RFT r/w RFU RFU r/w r/w r/w r/w
Table 124. Description of bits
Bit Symbol Description
7 - Reserved for production tests.
6 AmpRcv If set to logic 1, the internal signal processing in the receiver chain is
performed non-linear. This increases the operating distance in
communication modes at 106 kbit.
Note: Due to the non linearity the effect of the bits MinLevel and
CollLevel in the register RxThreshholdReg are as well non linear.
5 EOFSOFAdjust If set to logic 0 and the EOFSOFwidth is set to 1 will result in the
Maximum length of SOF and EOF according to ISO/IEC14443B
If set to logic 0 and the EOFSOFwidth is set to 0 will result in the
Minimum length of SOF and EOF according to ISO/IEC14443B
If this bit is set to 1 and the EOFSOFwidth bit is logic 1 will result in
SOF low = (11 etu 8 cycles)/fc
SOF high = (2 etu + 8 cycles)/fc
EOF low = (11 etu 8 cycles)/fc
For the behaviour in version 1.0, see Section 21 “Errata sheet” on
page 109.
4 - Reserved for future use.
3 to 0 SelfTest Enables the digital self test. The selftest can be started by the selftest
command in the command register. The selftest is enabled by 1001.
Note: For default operation the selftest has to be disabled by 0000.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Table 125. VersionReg register (address 37h); reset value: XXh, XXXXXXXXb
7 6 5 4 3 2 1 0
Version
Access Rights r r r r r r r r
Table 126. Description of VersionReg bits
Bit Symbol Description
7 to 0 Version 80h indicates PN512 version 1.0, differences to version 2.0 are
described within Section 21 “Errata sheet” on page 109.
82h indicates PN512 version 2.0, which covers also the industrial
version.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.4.9 AnalogTestReg
Controls the pins AUX1 and AUX2
Table 127. AnalogTestReg register (address 38h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
AnalogSelAux1 AnalogSelAux2
Access Rights r/w r/w r/w r/w r/w r/w r/w r/w
Table 128. Description of AnalogTestReg bits
Bit Symbol Description
7 to 4
3 to 0
AnalogSelAux1
AnalogSelAux2
Controls the AUX pin.
Note: All test signals are described in Section 20 “Testsignals”.
Value Description
0000 Tristate
0001 Output of TestDAC1 (AUX1), output of TESTDAC2 (AUX2)
Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.
0010 Testsignal Corr1
Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.
0011 Testsignal Corr2
Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.
0100 Testsignal MinLevel
Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.
0101 Testsignal ADC channel I
Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.
0110 Testsignal ADC channel Q
Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.
0111 Testsignal ADC channel I combined with Q
Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.
1000 Testsignal for production test
Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.
1001 SAM clock (13.56 MHz)
1010 HIGH
1011 LOW
1100 TxActive
At 106 kbit: HIGH during Startbit, Data bit, Parity and CRC. At 212 and 424 kbit: High
during Preamble, Sync, Data and CRC.
1101 RxActive
At 106 kbit: High during databit, Parity and CRC.
At 212 and 424 kbit: High during data and CRC.
1110 Subcarrier detected
106 kbit: not applicable
212 and 424 kbit: High during last part of Preamble, Sync data and CRC
1111 TestBus-Bit as defined by the TstBusBitSel in register TestSel1Reg.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.4.10 TestDAC1Reg
Defines the testvalues for TestDAC1.
9.2.4.11 TestDAC2Reg
Defines the testvalue for TestDAC2.
9.2.4.12 TestADCReg
Shows the actual value of ADC I and Q channel.
Table 129. TestDAC1Reg register (address 39h); reset value: XXh, 00XXXXXXb
7 6 5 4 3 2 1 0
0 0 TestDAC1
Access
Rights
RFT RFU r/w r/w r/w r/w r/w r/w
Table 130. Description of TestDAC1Reg bits
Bit Symbol Description
7 - Reserved for production tests.
6 - Reserved for future use.
5 to 0 TestDAC1 Defines the testvalue for TestDAC1. The output of the DAC1 can be
switched to AUX1 by setting AnalogSelAux1 to 0001 in register
AnalogTestReg.
Table 131. TestDAC2Reg register (address 3Ah); reset value: XXh, 00XXXXXXb
7 6 5 4 3 2 1 0
0 0 TestDAC2
Access
Rights
RFU RFU r/w r/w r/w r/w r/w r/w
Table 132. Description ofTestDAC2Reg bits
Bit Symbol Description
7 to 6 - Reserved for future use.
5 to 0 TestDAC2 Defines the testvalue for TestDAC2. The output of the DAC2 can be
switched to AUX2 by setting AnalogSelAux2 to 0001 in register
AnalogTestReg.
Table 133. TestADCReg register (address 3Bh); reset value: XXh, XXXXXXXXb
7 6 5 4 3 2 1 0
ADC_I ADC_Q
Access
Rights
Table 134. Description of TestADCReg bits
Bit Symbol Description
7 to 4 ADC_I Shows the actual value of ADC I channel.
3 to 0 ADC_Q Shows the actual value of ADC Q channel. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.4.13 RFTReg
10. Digital interfaces
10.1 Automatic microcontroller interface detection
The PN512 supports direct interfacing of hosts using SPI, I2C-bus or serial UART
interfaces. The PN512 resets its interface and checks the current host interface type
automatically after performing a power-on or hard reset. The PN512 identifies the host
interface by sensing the logic levels on the control pins after the reset phase. This is done
using a combination of fixed pin connections. Table 141 shows the different connection
configurations.
Table 135. RFTReg register (address 3Ch); reset value: FFh, 11111111b
7 6 5 4 3 2 1 0
11111111
Access
Rights
RFT RFT RFT RFT RFT RFT RFT RFT
Table 136. Description of RFTReg bits
Bit Symbol Description
7 to 0 - Reserved for production tests.
Table 137. RFTReg register (address 3Dh, 3Fh); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
00000000
Access
Rights
RFT RFT RFT RFT RFT RFT RFT RFT
Table 138. Description of RFTReg bits
Bit Symbol Description
7 to 0 - Reserved for production tests.
Table 139. RFTReg register (address 3Eh); reset value: 03h, 00000011b
7 6 5 4 3 2 1 0
00000011
Access
Rights
RFT RFT RFT RFT RFT RFT RFT RFT
Table 140. Description of RFTReg bits
Bit Symbol Description
7 to 0 - Reserved for production tests.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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[1] only available in HVQFN 40.
Table 141. Connection protocol for detecting different interface types
Pin Interface type
UART (input) SPI (output) I
2C-bus (I/O)
SDA RX NSS SDA
I
2C0 0 1
EA 0 1 EA
D7 TX MISO SCL
D6 MX MOSI ADR_0
D5 DTRQ SCK ADR_1
D4 - - ADR_2
D3 - - ADR_3
D2 - - ADR_4
D1 - - ADR_5
Table 142. Connection scheme for detecting the different interface types
PN512 Parallel Interface Type Serial Interface Types
Separated Read/Write Strobe Common Read/Write Strobe
Pin Dedicated
Address Bus
Multiplexed
Address Bus
Dedicated
Address Bus
Multiplexed
Address Bus
UART SPI I
2C
ALE 1 ALE 1 AS RX NSS SDA
A5[1] A5 0 A5 0 0 0 0
A4[1] A4 0 A4 0 0 0 0
A3[1] A3 0 A3 0 0 0 0
A2[1] A2 1 A2 1 0 0 0
A1 A1 1 A1 1 0 0 1
A0 A0 1 A0 0 0 1 EA
NRD[1] NRD NRD NDS NDS 1 1 1
NWR[1] NWR NWR RD/NWR RD/NWR 1 1 1
NCS[1] NCS NCS NCS NCS NCS NCS NCS
D7 D7 D7 D7 D7 TX MISO SCL
D6 D6 D6 D6 D6 MX MOSI ADR_0
D5 D5 AD5 D5 AD5 DTRQ SCK ADR_1
D4 D4 AD4 D4 AD4 - - ADR_2
D3 D3 AD3 D3 AD3 - - ADR_3
D2 D2 AD2 D2 AD2 - - ADR_4
D1 D1 AD1 D1 AD1 - - ADR_5
D0 D0 AD0 D0 AD0 - - ADR_6
Remark: Overview on the pin behavior
Pin behavior Input Output In/OutPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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10.2 Serial Peripheral Interface
A serial peripheral interface (SPI compatible) is supported to enable high-speed
communication to the host. The interface can handle data speeds up to 10 Mbit/s. When
communicating with a host, the PN512 acts as a slave, receiving data from the external
host for register settings, sending and receiving data relevant for RF interface
communication.
An interface compatible with SPI enables high-speed serial communication between the
PN512 and a microcontroller. The implemented interface is in accordance with the SPI
standard.
The timing specification is given in Section 26.1 on page 117.
The PN512 acts as a slave during SPI communication. The SPI clock signal SCK must be
generated by the master. Data communication from the master to the slave uses the
MOSI line. The MISO line is used to send data from the PN512 to the master.
Data bytes on both MOSI and MISO lines are sent with the MSB first. Data on both MOSI
and MISO lines must be stable on the rising edge of the clock and can be changed on the
falling edge. Data is provided by the PN512 on the falling clock edge and is stable during
the rising clock edge.
10.2.1 SPI read data
Reading data using SPI requires the byte order shown in Table 143 to be used. It is
possible to read out up to n-data bytes.
The first byte sent defines both the mode and the address.
[1] X = Do not care.
Remark: The MSB must be sent first.
10.2.2 SPI write data
To write data to the PN512 using SPI requires the byte order shown in Table 144. It is
possible to write up to n data bytes by only sending one address byte.
Fig 13. SPI connection to host
001aan220
PN512
SCK SCK
MOSI MOSI
MISO MISO
NSS NSS
Table 143. MOSI and MISO byte order
Line Byte 0 Byte 1 Byte 2 To Byte n Byte n + 1
MOSI address 0 address 1 address 2 ... address n 00
MISO X[1] data 0 data 1 ... data n 1 data nPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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The first send byte defines both the mode and the address byte.
[1] X = Do not care.
Remark: The MSB must be sent first.
10.2.3 SPI address byte
The address byte has to meet the following format.
The MSB of the first byte defines the mode used. To read data from the PN512 the MSB is
set to logic 1. To write data to the PN512 the MSB must be set to logic 0. Bits 6 to 1 define
the address and the LSB is set to logic 0.
10.3 UART interface
10.3.1 Connection to a host
Remark: Signals DTRQ and MX can be disabled by clearing TestPinEnReg register’s
RS232LineEn bit.
10.3.2 Selectable UART transfer speeds
The internal UART interface is compatible with an RS232 serial interface.
The default transfer speed is 9.6 kBd. To change the transfer speed, the host controller
must write a value for the new transfer speed to the SerialSpeedReg register. Bits
BR_T0[2:0] and BR_T1[4:0] define the factors for setting the transfer speed in the
SerialSpeedReg register.
The BR_T0[2:0] and BR_T1[4:0] settings are described in Table 10. Examples of different
transfer speeds and the relevant register settings are given in Table 11.
Table 144. MOSI and MISO byte order
Line Byte 0 Byte 1 Byte 2 To Byte n Byte n + 1
MOSI address 0 data 0 data 1 ... data n 1 data n
MISO X[1] X[1] X[1] ... X[1] X[1]
Table 145. Address byte 0 register; address MOSI
7 (MSB) 6 5 4 3 2 1 0 (LSB)
1 = read
0 = write
address 0
Fig 14. UART connection to microcontrollers
001aan221
PN512
RX RX
TX TX
DTRQ DTRQ
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[1] The resulting transfer speed error is less than 1.5 % for all described transfer speeds.
The selectable transfer speeds shown in Table 11 are calculated according to the
following equations:
If BR_T0[2:0] = 0:
(1)
If BR_T0[2:0] > 0:
(2)
Remark: Transfer speeds above 1228.8 kBd are not supported.
10.3.3 UART framing
Table 146. BR_T0 and BR_T1 settings
BR_Tn Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
BR_T0 factor 1 1 2 4 8 16 32 64
BR_T1 range 1 to 32 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64
Table 147. Selectable UART transfer speeds
Transfer speed (kBd) SerialSpeedReg value Transfer speed accuracy (%)[1]
Decimal Hexadecimal
7.2 250 FAh 0.25
9.6 235 EBh 0.32
14.4 218 DAh 0.25
19.2 203 CBh 0.32
38.4 171 ABh 0.32
57.6 154 9Ah 0.25
115.2 122 7Ah 0.25
128 116 74h 0.06
230.4 90 5Ah 0.25
460.8 58 3Ah 0.25
921.6 28 1Ch 1.45
1228.8 21 15h 0.32
transfer speed 27.12 106
BR_T0 1 + = --------------------------------
transfer speed 27.12 106
BR_T1 33 +
2
BR_T0 1 – -----------------------------------
-----------------------------------
=
Table 148. UART framing
Bit Length Value
Start 1-bit 0
Data 8 bits data
Stop 1-bit 1PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Remark: The LSB for data and address bytes must be sent first. No parity bit is used
during transmission.
Read data: To read data using the UART interface, the flow shown in Table 149 must be
used. The first byte sent defines both the mode and the address.
Write data: To write data to the PN512 using the UART interface, the structure shown in
Table 150 must be used.
The first byte sent defines both the mode and the address.
Table 149. Read data byte order
Pin Byte 0 Byte 1
RX (pin 24) address -
TX (pin 31) - data 0
(1) Reserved.
Fig 15. UART read data timing diagram
001aak588
SA
ADDRESS
RX
TX
MX
DTRQ
A0 A1 A2 A3 A4 A5 (1) SO
SA D0 D1 D2 D3 D4 D5 D6 D7 SO
DATA
R/W
Table 150. Write data byte order
Pin Byte 0 Byte 1
RX (pin 24) address 0 data 0
TX (pin 31) - address 0xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Remark: The data byte can be sent directly after the address byte on pin RX.
Address byte: The address byte has to meet the following format:
(1) Reserved.
Fig 16. UART write data timing diagram
001aak589
SA
ADDRESS
RX
TX
MX
DTRQ
A0 A1 A2 A3 A4 A5 (1) SO SA D0 D1 D2 D3 D4 D5 D6 D7 SO
SA A0 A1 A2 A3 A4 A5 (1) SO
DATA
ADDRESS
R/W
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The MSB of the first byte sets the mode used. To read data from the PN512, the MSB is
set to logic 1. To write data to the PN512 the MSB is set to logic 0. Bit 6 is reserved for
future use, and bits 5 to 0 define the address; see Table 151.
10.4 I2C Bus Interface
An I2C-bus (Inter-IC) interface is supported to enable a low-cost, low pin count serial bus
interface to the host. The I2C-bus interface is implemented according to
NXP Semiconductors’ I
2C-bus interface specification, rev. 2.1, January 2000. The
interface can only act in Slave mode. Therefore the PN512 does not implement clock
generation or access arbitration.
The PN512 can act either as a slave receiver or slave transmitter in Standard mode, Fast
mode and High-speed mode.
SDA is a bidirectional line connected to a positive supply voltage using a current source or
a pull-up resistor. Both SDA and SCL lines are set HIGH when data is not transmitted. The
PN512 has a 3-state output stage to perform the wired-AND function. Data on the I2C-bus
can be transferred at data rates of up to 100 kBd in Standard mode, up to 400 kBd in Fast
mode or up to 3.4 Mbit/s in High-speed mode.
If the I2C-bus interface is selected, spike suppression is activated on lines SCL and SDA
as defined in the I2C-bus interface specification.
See Table 171 on page 117 for timing requirements.
Table 151. Address byte 0 register; address MOSI
7 (MSB) 6 5 4 3 2 1 0 (LSB)
1 = read
0 = write
reserved address
Fig 17. I2C-bus interface
001aan222
PN512
SDA
SCL
I2C
EA
ADR_[5:0]
PULL-UP
NETWORK
CONFIGURATION
WIRING
PULL-UP
NETWORK
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10.4.1 Data validity
Data on the SDA line must be stable during the HIGH clock period. The HIGH or LOW
state of the data line must only change when the clock signal on SCL is LOW.
10.4.2 START and STOP conditions
To manage the data transfer on the I2C-bus, unique START (S) and STOP (P) conditions
are defined.
• A START condition is defined with a HIGH-to-LOW transition on the SDA line while
SCL is HIGH.
• A STOP condition is defined with a LOW-to-HIGH transition on the SDA line while
SCL is HIGH.
The I2C-bus master always generates the START and STOP conditions. The bus is busy
after the START condition. The bus is free again a certain time after the STOP condition.
The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition.
The START (S) and repeated START (Sr) conditions are functionally identical. Therefore,
S is used as a generic term to represent both the START (S) and repeated START (Sr)
conditions.
10.4.3 Byte format
Each byte must be followed by an acknowledge bit. Data is transferred with the MSB first;
see Figure 22. The number of transmitted bytes during one data transfer is unrestricted
but must meet the read/write cycle format.
Fig 18. Bit transfer on the I2C-bus
mbc621
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 19. START and STOP conditions
mbc622
SDA
SCL
P
STOP condition
SDA
SCL
S
START conditionPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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10.4.4 Acknowledge
An acknowledge must be sent at the end of one data byte. The acknowledge-related clock
pulse is generated by the master. The transmitter of data, either master or slave, releases
the SDA line (HIGH) during the acknowledge clock pulse. The receiver pulls down the
SDA line during the acknowledge clock pulse so that it remains stable LOW during the
HIGH period of this clock pulse.
The master can then generate either a STOP (P) condition to stop the transfer or a
repeated START (Sr) condition to start a new transfer.
A master-receiver indicates the end of data to the slave-transmitter by not generating an
acknowledge on the last byte that was clocked out by the slave. The slave-transmitter
releases the data line to allow the master to generate a STOP (P) or repeated START (Sr)
condition.
Fig 20. Acknowledge on the I2C-bus
mbc602
S
START
condition
1 2 8 9
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from
master
Fig 21. Data transfer on the I2C-bus
msc608
Sr
or
P
SDA
Sr
P
SCL
STOP or
repeated START
condition
S
or
Sr
START or
repeated START
condition
1 2 3 - 8 9
ACK
9
ACK
1 2 7 8
MSB acknowledgement
signal from slave
byte complete,
interrupt within slave
clock line held LOW while
interrupts are serviced
acknowledgement
signal from receiverPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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10.4.5 7-Bit addressing
During the I2C-bus address procedure, the first byte after the START condition is used to
determine which slave will be selected by the master.
Several address numbers are reserved. During device configuration, the designer must
ensure that collisions with these reserved addresses cannot occur. Check the I
2C-bus
specification for a complete list of reserved addresses.
The I2C-bus address specification is dependent on the definition of pin EA. Immediately
after releasing pin NRSTPD or after a power-on reset, the device defines the I2C-bus
address according to pin EA.
If pin EA is set LOW, the upper 4 bits of the device bus address are reserved by
NXP Semiconductors and set to 0101b for all PN512 devices. The remaining 3 bits
(ADR_0, ADR_1, ADR_2) of the slave address can be freely configured by the customer
to prevent collisions with other I2C-bus devices.
If pin EA is set HIGH, ADR_0 to ADR_5 can be completely specified at the external pins
according to Table 141 on page 69. ADR_6 is always set to logic 0.
In both modes, the external address coding is latched immediately after releasing the
reset condition. Further changes at the used pins are not taken into consideration.
Depending on the external wiring, the I2C-bus address pins can be used for test signal
outputs.
10.4.6 Register write access
To write data from the host controller using the I2C-bus to a specific register in the PN512
the following frame format must be used.
• The first byte of a frame indicates the device address according to the I2C-bus rules.
• The second byte indicates the register address followed by up to n-data bytes.
In one frame all data bytes are written to the same register address. This enables fast
FIFO buffer access. The Read/Write (R/W) bit is set to logic 0.
Fig 22. First byte following the START procedure
slave address 001aak591
bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
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10.4.7 Register read access
To read out data from a specific register address in the PN512, the host controller must
use the following procedure:
• Firstly, a write access to the specific register address must be performed as indicated
in the frame that follows
• The first byte of a frame indicates the device address according to the I2C-bus rules
• The second byte indicates the register address. No data bytes are added
• The Read/Write bit is 0
After the write access, read access can start. The host sends the device address of the
PN512. In response, the PN512 sends the content of the read access register. In one
frame all data bytes can be read from the same register address. This enables fast FIFO
buffer access or register polling.
The Read/Write (R/W) bit is set to logic 1.
Fig 23. Register read and write access
001aak592
S A 0 0
I
2C-BUS
SLAVE ADDRESS
[A7:A0]
JOINER REGISTER
ADDRESS [A5:A0]
write cycle
0
(W) A DATA
[7:0] [0:n]
[0:n]
[0:n]
A
P
S A 0 0
I
2C-BUS
SLAVE ADDRESS
[A7:A0]
JOINER REGISTER
ADDRESS [A5:A0]
read cycle
optional, if the previous access was on the same register address
0
(W) A P
P
S
S start condition
P stop condition
A acknowledge
A not acknowledge
W write cycle
R read cycle
A
I
2C-BUS
SLAVE ADDRESS
[A7:A0]
sent by master
sent by slave
DATA
[7:0]
1
(R) A
DATA
[7:0]
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10.4.8 High-speed mode
In High-speed mode (HS mode), the device can transfer information at data rates of up to
3.4 Mbit/s, while remaining fully downward-compatible with Fast or Standard mode
(F/S mode) for bidirectional communication in a mixed-speed bus system.
10.4.9 High-speed transfer
To achieve data rates of up to 3.4 Mbit/s the following improvements have been made to
I
2C-bus operation.
• The inputs of the device in HS mode incorporate spike suppression, a Schmitt trigger
on the SDA and SCL inputs and different timing constants when compared to
F/S mode
• The output buffers of the device in HS mode incorporate slope control of the falling
edges of the SDA and SCL signals with different fall times compared to F/S mode
10.4.10 Serial data transfer format in HS mode
The HS mode serial data transfer format meets the Standard mode I2C-bus specification.
HS mode can only start after all of the following conditions (all of which are in F/S mode):
1. START condition (S)
2. 8-bit master code (00001XXXb)
3. Not-acknowledge bit (A)
When HS mode starts, the active master sends a repeated START condition (Sr) followed
by a 7-bit slave address with a R/W bit address and receives an acknowledge bit (A) from
the selected PN512.
Data transfer continues in HS mode after the next repeated START (Sr), only switching
back to F/S mode after a STOP condition (P). To reduce the overhead of the master code,
a master links a number of HS mode transfers, separated by repeated START conditions
(Sr).
Fig 24. I2C-bus HS mode protocol switch
F/S mode HS mode (current-source for SCL HIGH enabled) F/S mode
001aak749
A A/A A DATA
(n-bytes + A)
S MASTER CODE Sr SLAVE ADDRESS R/W
HS mode continues
Sr SLAVE ADDRESS
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Fig 25. I2C-bus HS mode protocol frame
msc618
8-bit master code 0000 1xxx A
tH
t1
S
F/S mode
HS mode
If P then
F/S mode
If Sr (dotted lines)
then HS mode
1 6789 6789 1
1 2 to 5
2 to 5 2 to 5
67 89
SDA high
SCL high
SDA high
SCL high
tH tFS
Sr Sr P 7-bit SLA R/W A n + (8-bit data + A/A)
= Master current source pull-up
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10.4.11 Switching between F/S mode and HS mode
After reset and initialization, the PN512 is in Fast mode (which is in effect F/S mode as
Fast mode is downward-compatible with Standard mode). The connected PN512
recognizes the “S 00001XXX A” sequence and switches its internal circuitry from the Fast
mode setting to the HS mode setting.
The following actions are taken:
1. Adapt the SDA and SCL input filters according to the spike suppression requirement
in HS mode.
2. Adapt the slope control of the SDA output stages.
It is possible for system configurations that do not have other I2C-bus devices involved in
the communication to switch to HS mode permanently. This is implemented by setting
Status2Reg register’s I2CForceHS bit to logic 1. In permanent HS mode, the master code
is not required to be sent. This is not defined in the specification and must only be used
when no other devices are connected on the bus. In addition, spikes on the I2C-bus lines
must be avoided because of the reduced spike suppression.
10.4.12 PN512 at lower speed modes
PN512 is fully downward-compatible and can be connected to an F/S mode I2C-bus
system. The device stays in F/S mode and communicates at F/S mode speeds because a
master code is not transmitted in this configuration.
11. 8-bit parallel interface
The PN512 supports two different types of 8-bit parallel interfaces, Intel and Motorola
compatible modes.
11.1 Overview of supported host controller interfaces
The PN512 supports direct interfacing to various -Controllers. The following table shows
the parallel interface types supported by the PN512.
Table 152. Supported interface types
Supported interface types Bus Separated Address and
Data Bus
Multiplexed Address
and Data Bus
Separated Read and Write
Strobes (INTEL compatible)
control NRD, NWR, NCS NRD, NWR, NCS, ALE
address A0 … A3 [..A5*] AD0 … AD7
data D0 … D7 AD0 … AD7
Multiplexed Read and Write
Strobe (Motorola compatible)
control R/NW, NDS, NCS R/NW, NDS, NCS, AS
address A0 … A3 [..A5*] AD0 … AD7
data D0 … D7 AD0 … AD7PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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11.2 Separated Read/Write strobe
For timing requirements refer to Section 26.2 “8-bit parallel interface timing”.
11.3 Common Read/Write strobe
For timing requirements refer to Section 26.2 “8-bit parallel interface timing”
Fig 26. Connection to host controller with separated Read/Write strobes
001aan223
PN512
NCS
A0...A3[A5*]
D0...D7
A0
A1
A2
A3
A4*
A5*
address bus (A0...A3[A5*])
ALE
NRD
NWR
ADDRESS
DECODER
data bus (D0...D7)
high
not data strobe (NRD)
not write (NWR)
address bus
remark: *depending on the package type.
multiplexed address/data AD0...AD7)
PN512
NCS
D0...D7
ALE
NRD
NWR
ADDRESS
DECODER
low
low
high
high
high
low
address latch enable (ALE)
not read strobe (NRD)
not write (NWR)
non multiplexed
address
Fig 27. Connection to host controller with common Read/Write strobes
001aan224
PN512
NCS
A0...A3[A5*]
D0...D7
A0
A1
A2
A3
A4*
A5*
address bus (A0...A3[A5*])
ALE
NRD
NWR
ADDRESS
DECODER
Data bus (D0...D7)
high
not data strobe (NDS)
read not write (RD/NWR)
address bus
remark: *depending on the package type.
multiplexed address/data AD0...AD7)
PN512
NCS
D0...D7
ALE
NRD
NWR
ADDRESS
DECODER
low
low
high
high
low
low
address strobe (AS)
not data strobe (NDS)
read not write (RD/NWR)
non multiplexed
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12. Analog interface and contactless UART
12.1 General
The integrated contactless UART supports the external host online with framing and error
checking of the protocol requirements up to 848 kBd. An external circuit can be connected
to the communication interface pins MFIN and MFOUT to modulate and demodulate the
data.
The contactless UART handles the protocol requirements for the communication
protocols in cooperation with the host. Protocol handling generates bit and byte-oriented
framing. In addition, it handles error detection such as parity and CRC, based on the
various supported contactless communication protocols.
Remark: The size and tuning of the antenna and the power supply voltage have an
important impact on the achievable operating distance.
12.2 TX driver
The signal on pins TX1 and TX2 is the 13.56 MHz energy carrier modulated by an
envelope signal. It can be used to drive an antenna directly using a few passive
components for matching and filtering; see Section 15 on page 96. The signal on pins TX1
and TX2 can be configured using the TxControlReg register; see Section 9.2.2.5 on
page 40.
The modulation index can be set by adjusting the impedance of the drivers. The
impedance of the p-driver can be configured using registers CWGsPReg and
ModGsPReg. The impedance of the n-driver can be configured using the GsNReg
register. The modulation index also depends on the antenna design and tuning.
The TxModeReg and TxSelReg registers control the data rate and framing during
transmission and the antenna driver setting to support the different requirements at the
different modes and transfer speeds.
[1] X = Do not care.
Table 153. Register and bit settings controlling the signal on pin TX1
Bit
Tx1RFEn
Bit
Force
100ASK
Bit
InvTx1RFOn
Bit
InvTx1RFOff
Envelope Pin
TX1
GSPMos GSNMos Remarks
0 X[1] X[1] X[1] X[1] X[1] CWGsNOff CWGsNOff not specified if RF is
switched off
1 00 X[1] 0 RF pMod nMod 100 % ASK: pin TX1
pulled to logic 0,
independent of the
InvTx1RFOff bit
1 RF pCW nCW
01 X[1] 0 RF pMod nMod
1 RF pCW nCW
11 X[1] 0 0 pMod nMod
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[1] X = Do not care.
The following abbreviations have been used in Table 153 and Table 154:
• RF: 13.56 MHz clock derived from 27.12 MHz quartz crystal oscillator divided by 2
• RF_n: inverted 13.56 MHz clock
• GSPMos: conductance, configuration of the PMOS array
• GSNMos: conductance, configuration of the NMOS array
• pCW: PMOS conductance value for continuous wave defined by the CWGsPReg
register
• pMod: PMOS conductance value for modulation defined by the ModGsPReg register
• nCW: NMOS conductance value for continuous wave defined by the GsNReg
register’s CWGsN[3:0] bits
• nMod: NMOS conductance value for modulation defined by the GsNReg register’s
ModGsN[3:0] bits
• X = do not care.
Remark: If only one driver is switched on, the values for CWGsPReg, ModGsPReg and
GsNReg registers are used for both drivers.
12.3 RF level detector
The RF level detector is integrated to fulfill NFCIP1 protocol requirements (e.g. RF
collision avoidance). Furthermore the RF level detector can be used to wake up the
PN512 and to generate an interrupt.
Table 154. Register and bit settings controlling the signal on pin TX2
Bit
Tx1RFEn
Bit
Force
100ASK
Bit
Tx2CW
Bit
InvTx2RFOn
Bit
InvTx2RFOff
Envelope
Pin
TX2
GSPMos GSNMos Remarks
0 X[1] X[1] X[1] X[1] X[1] X[1] CWGsNOff CWGsNOff not specified if
RF is switched
off
1 0 00 X[1] 0 RF pMod nMod -
1 RF pCW nCW
1 X[1] 0 RF_n pMod nMod
1 RF_n pCW nCW
10 X[1] X[1] RF pCW nCW conductance
always CW for
the Tx2CW bit
1 X[1] X[1] RF_n pCW nCW
1 00 X[1] 0 0 pMod nMod 100 % ASK: pin
TX2 pulled
to logic 0
(independent of
the
InvTx2RFOn/In
vTx2RFOff bits)
1 RF pCW nCW
1 X[1] 0 0 pMod nMod
1 RF_n pCW nCW
10 X[1] X[1] RF pCW nCW
1 X[1] X[1] RF_n pCW nCWPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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The sensitivity of the RF level detector is adjustable in a 4-bit range using the bits RFLevel
in register RFCfgReg. The sensitivity itself depends on the antenna configuration and
tuning.
Possible sensitivity levels at the RX pin are listed in the Table 154.
To increase the sensitivity of the RF level detector an amplifier can be activated by setting
the bit RFLevelAmp in register RFCfgReg to 1.
Remark: During soft Power-down mode the RF level detector amplifier is automatically
switched off to ensure that the power consumption is less than 10 A at 3 V.
Remark: With typical antennas lower sensitivity levels can provoke misleading results
because of intrinsic noise in the environment.
Note: It is recommended to use the bit RFLevelAmp only with higher RF level settings.
12.4 Data mode detector
The Data mode detector gives the possibility to detect received signals according to the
ISO/IEC 14443A/MIFARE, FeliCa or NFCIP-1 schemes at the standard transfer speeds
for 106 kbit, 212 kbit and 424 kbit in order to prepare the internal receiver in a fast and
convenient way for further data processing.
The Data mode detector can only be activated by the AutoColl command. The mode
detector resets, when no external RF field is detected by the RF level detector. The Data
mode detector could be switched off during the AutoColl command by setting bit
ModeDetOff in register ModeReg to 1.
Table 155. Setting of the bits RFlevel in register RFCfgReg (RFLevel amplifier deactivated)
V~Rx [Vpp] RFLevel
~2 1111
~1.4 1110
~0.99 1101
~0.69 1100
~0.49 1011
~0.35 1010
~0.24 1001
~0.17 1000
~0.12 0111
~0.083 0110
~0.058 0101
~0.041 0100
~0.029 0011
~0.020 0010
~0.014 0001
~0.010 0000PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Fig 28. Data mode detector
001aan225
HOST INTERFACES
RECEIVER
I/Q DEMODULATOR
REGISTERS
REGISTERSETTING
FOR THE
DETECTED MODE
DATA MODE DETECTOR
PN512 RX
NFC @ 106 kbit/s
NFC @ 212 kbit/s
NFC @ 424 kbit/sPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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12.5 Serial data switch
Two main blocks are implemented in the PN512. The digital block comprises the state
machines, encoder/decoder logic. The analog block comprises the modulator and
antenna drivers, the receiver and amplifiers. The interface between these two blocks can
be configured in the way, that the interfacing signals may be routed to the pins SIGIN and
SIGOUT. SIGIN is capable of processing digital NFC signals on transfer speeds above
424 kbit. The SIGOUT pin can provide a digital signal that can be used with an additional
external circuit to generate transfer speeds above 424 kbit (including 106, 212 and
424 kbit). Furthermore SIGOUT and SIGIN can be used to enable the S2C interface in the
card SAM mode to emulate a card functionality with the PN512 and a secure IC. A secure
IC can be the SmartMX smart card controller IC.
This topology allows the analog block of the PN512 to be connected to the digital block of
another device.
The serial signal switch is controlled by the TxSelReg and RxSelReg registers.
Figure 29 shows the serial data switch for TX1 and TX2.
12.6 S2C interface support
The S2C provides the possibility to directly connect a secure IC to the PN512 in order act
as a contactless smart card IC via the PN512. The interfacing signals can be routed to the
pins SIGIN and SIGOUT. SIGIN can receive either a digital FeliCa or digitized
ISO/IEC 14443A signal sent by the secure IC. The SIGOUT pin can provide a digital
signal and a clock to communicate to the secure IC. A secure IC can be the smart card IC
provided by NXP Semiconductors.
The PN512 has an extra supply pin (SVDD and PVSS as Ground line) for the SIGIN and
SIGOUT pads.
Figure 31 outlines possible ways of communications via the PN512 to the secure IC.
Fig 29. Serial data switch for TX1 and TX2
001aak593
INTERNAL
CODER
INVERT IF
InvMod = 1
DriverSel[1:0]
00
01
10
11
3-state
to driver TX1 and TX2
0 = impedance = modulated
1 = impedance = CW 1
INVERT IF
PolMFin = 0 MFIN
envelopePN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Configured in the Secure Access Mode the host controller can directly communicate to
the Secure IC via SIGIN/SIGOUT. In this mode the PN512 generates the RF clock and
performs the communication on the SIGOUT line. To enable the Secure Access module
mode the clock has to be derived by the internal oscillator of the PN512, see bits
SAMClockSel in register TestSel1Reg.
Configured in Contactless Card mode the secure IC can act as contactless smart card IC
via the PN512. In this mode the signal on the SIGOUT line is provided by the external RF
field of the external reader/writer. To enable the Contactless Card mode the clock derived
by the external RF field has to be used.
The configuration of the S2C interface differs for the FeliCa and MIFARE scheme as
outlined in the following chapters.
Fig 30. Communication flows using the S2C interface
001aan226
CONTACTLESS UART
SERIAL SIGNAL SWITCH
FIFO AND STATE MACHINE
SPI, I2C, SERIAL UART
HOST CONTROLLER
PN512
SECURE CORE IC
SIGOUT
SIGIN
2. contactless
card mode
1. secure access
module (SAM) mode PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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12.6.1 Signal shape for Felica S2C interface support
The FeliCa secure IC is connected to the PN512 via the pins SIGOUT and SIGIN.
The signal at SIGOUT contains the information of the 13.56 MHz clock and the digitized
demodulated signal. The clock and the demodulated signal is combined by using the
logical function exclusive or.
To ensure that this signal is free of spikes, the demodulated signal is digitally filtered first.
The time delay for that digital filtering is in the range of one bit length. The demodulated
signal changes only at a positive edge of the clock.
The register TxSelReg controls the setting at SIGOUT.
The answer of the FeliCa SAM is transferred from SIGIN directly to the antenna driver.
The modulation is done according to the register settings of the antenna drivers.
The clock is switched to AUX1 or AUX2 (see AnalogSelAux).
Note: A HIGH signal on AUX1 and AUX2 has the same level as AVDD. A HIGH signal at
SIGOUT has the same level as SVDD. Alternatively it is possible to use pin D0 as clock
output if a serial interface is used. The HIGH level at D0 is the same as PVDD.
Note: The signal on the antenna is shown in principle only. In reality the waveform is
sinusoidal.
Fig 31. Signal shape for SIGOUT in FeliCa card SAM mode
Fig 32. Signal shape for SIGIN in SAM mode
001aan227
clock
signal on
SIGIN
signal on
antenna
001aan228
clock
demodulated
signal
signal on
SIGOUTPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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12.6.2 Waveform shape for ISO/IEC 14443A and MIFARE S2C support
The secure IC, e.g. the SmartMX is connected to the PN512 via the pins SIGOUT and
SIGIN.
The waveform shape at SIGOUT is a digital 13.56 MHz Miller coded signal with levels
between PVSS and PVDD derived out of the external 13.56 MHz carrier signal in case of
the Contactless Card mode or internally generated in terms of Secure Access mode.
The register TxSelReg controls the setting at SIGOUT.
Note: The clock settings for the Secure Access mode and the Contactless Card mode
differ, refer to the description of the bits SAMClockSel in register TestSel1Reg.
The signal at SIGIN is a digital Manchester coded signal according to the requirements of
the ISO/IEC 14443A with the subcarrier frequency of 847.5 kHz generated by the secure
IC.
Fig 33. Signal shape for SIGOUT in MIFARE Card SAM mode
Fig 34. Signal shape for SIGIN in MIFARE Card SAM mode
001aan229
1
0
bit
value RF
signal on
antenna
signal on
SIGOUT
01001
001aan230
0
1
0
1 1 0 0
bit
value
signal on
antenna
signal on
SIGINPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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12.7 Hardware support for FeliCa and NFC polling
12.7.1 Polling sequence functionality for initiator
1. Timer: The PN512 has a timer, which can be programmed in a way that it generates
an interrupt at the end of each timeslot, or if required an interrupt is generated at the
end of the last timeslot.
2. The receiver can be configured in a way to receive continuously. In this mode it can
receive any number of packets. The receiver is ready to receive the next packet
directly after the last packet has been received. This mode is active by setting the bit
RxMultiple in register RxModeReg to 1 and has to be stopped by software.
3. The internal UART adds one byte to the end of every received packet, before it is
transferred into the FIFO-buffer. This byte indicates if the received byte packet is
correct (see register ErrReg). The first byte of each packet contains the length byte of
the packet.
4. The length of one packet is 18 or 20 bytes (+ 1 byte Error-Info). The FIFO has a
length of 64 bytes. This means three packets can be stored in the FIFO at the same
time. If more than three packets are expected, the host controller has to empty the
FIFO, before the FIFO is filled completely. In case of a FIFO-overflow data is lost (See
bit BufferOvfl in register ErrorReg).
12.7.2 Polling sequence functionality for target
1. The host controller has to configure the PN512 with the correct polling response
parameters for the polling command.
2. To activate the automatic polling in Target mode, the AutoColl Command has to be
activated.
3. The PN512 receives the polling command send out by an initiator and answers with
the polling response. The timeslot is selected automatically (The timeslot itself is
randomly generated, but in the range 0 to TSN, which is defined by the Polling
command). The PN512 compares the system code, stored in byte 17 and 18 of the
Config Command with the system code received by the polling command of an
initiator. If the system code is equal, the PN512 answers according to the configured
polling response. The system code FF (hex) acts as a wildcard for the system code
bytes, i.e. a target of a system code 1234 (hex) answers to the polling command with
one of the following system codes 1234 (hex), 12FF (hex), FF34 (hex) or FFFF (hex).
If the system code does not match no answer is sent back by the PN512.
If a valid command is received by the PN512, which is not a Polling command, no
answer is sent back and the command AutoColl is stopped. The received packet is
stored in the FIFO.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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12.7.3 Additional hardware support for FeliCa and NFC
Additionally to the polling sequence support for the Felica mode, the PN512 supports the
check of the Len-byte.
The received Len-byte in accordance to the registers FelNFC1Reg and FelNFC2Reg:
DataLenMin in register FelNFC1Reg defines the minimum length of the accepted packet
length. This register is six bit long. Each bit represents a length of four bytes.
DataLenMax in register FelNFC2Reg defines the maximum length of the accepted
package. This register is six bit long. Each bit represents a length of four bytes. If set to
logic 1 this limit is ignored. If the length is not in the supposed range, the packet is not
transferred to the FIFO and receiving is kept active.
Example 1:
• DataLenMin = 4
– The length shall be greater or equal 16.
• DataLenMax = 5
– The length shall be smaller than 20. Valid area: 16, 17, 18, 19
Example 2:
• DataLenMin = 9
– The length shall be greater or equal 36.
• DataLenMax = 0
– The length shall be smaller than 256. Valid area: 36 to 255
12.7.4 CRC coprocessor
The following CRC coprocessor parameters can be configured:
• The CRC preset value can be either 0000h, 6363h, A671h or FFFFh depending on
the ModeReg register’s CRCPreset[1:0] bits setting
• The CRC polynomial for the 16-bit CRC is fixed to x16 + x12 + x5 + 1
• The CRCResultReg register indicates the result of the CRC calculation. This register
is split into two 8-bit registers representing the higher and lower bytes.
• The ModeReg register’s MSBFirst bit indicates that data will be loaded with the MSB
first.
Table 156. CRC coprocessor parameters
Parameter Value
CRC register length 16-bit CRC
CRC algorithm algorithm according to ISO/IEC 14443 A and ITU-T
CRC preset value 0000h, 6363h, A671h or FFFFh depending on the setting of the
ModeReg register’s CRCPreset[1:0] bitsPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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13. FIFO buffer
An 8 64 bit FIFO buffer is used in the PN512. It buffers the input and output data stream
between the host and the PN512’s internal state machine. This makes it possible to
manage data streams up to 64 bytes long without the need to take timing constraints into
account.
13.1 Accessing the FIFO buffer
The FIFO buffer input and output data bus is connected to the FIFODataReg register.
Writing to this register stores one byte in the FIFO buffer and increments the internal FIFO
buffer write pointer. Reading from this register shows the FIFO buffer contents stored in
the FIFO buffer read pointer and decrements the FIFO buffer read pointer. The distance
between the write and read pointer can be obtained by reading the FIFOLevelReg
register.
When the microcontroller starts a command, the PN512 can, while the command is in
progress, access the FIFO buffer according to that command. Only one FIFO buffer has
been implemented which can be used for input and output. The microcontroller must
ensure that there are not any unintentional FIFO buffer accesses.
13.2 Controlling the FIFO buffer
The FIFO buffer pointers can be reset by setting FIFOLevelReg register’s FlushBuffer bit
to logic 1. Consequently, the FIFOLevel[6:0] bits are all set to logic 0 and the ErrorReg
register’s BufferOvfl bit is cleared. The bytes stored in the FIFO buffer are no longer
accessible allowing the FIFO buffer to be filled with another 64 bytes.
13.3 FIFO buffer status information
The host can get the following FIFO buffer status information:
• Number of bytes stored in the FIFO buffer: FIFOLevelReg register’s FIFOLevel[6:0]
• FIFO buffer almost full warning: Status1Reg register’s HiAlert bit
• FIFO buffer almost empty warning: Status1Reg register’s LoAlert bit
• FIFO buffer overflow warning: ErrorReg register’s BufferOvfl bit. The BufferOvfl bit
can only be cleared by setting the FIFOLevelReg register’s FlushBuffer bit.
The PN512 can generate an interrupt signal when:
• ComIEnReg register’s LoAlertIEn bit is set to logic 1. It activates pin IRQ when
Status1Reg register’s LoAlert bit changes to logic 1.
• ComIEnReg register’s HiAlertIEn bit is set to logic 1. It activates pin IRQ when
Status1Reg register’s HiAlert bit changes to logic 1.
If the maximum number of WaterLevel bytes (as set in the WaterLevelReg register) or less
are stored in the FIFO buffer, the HiAlert bit is set to logic 1. It is generated according to
Equation 3:
HiAlert 64 FIFOLength = – WaterLevel (3)PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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If the number of WaterLevel bytes (as set in the WaterLevelReg register) or less are
stored in the FIFO buffer, the LoAlert bit is set to logic 1. It is generated according to
Equation 4:
(4)
14. Interrupt request system
The PN512 indicates certain events by setting the Status1Reg register’s IRq bit and, if
activated, by pin IRQ. The signal on pin IRQ can be used to interrupt the host using its
interrupt handling capabilities. This allows the implementation of efficient host software.
14.1 Interrupt sources overview
Table 157 shows the available interrupt bits, the corresponding source and the condition
for its activation. The ComIrqReg register’s TimerIRq interrupt bit indicates an interrupt set
by the timer unit which is set when the timer decrements from 1 to 0.
The ComIrqReg register’s TxIRq bit indicates that the transmitter has finished. If the state
changes from sending data to transmitting the end of the frame pattern, the transmitter
unit automatically sets the interrupt bit. The CRC coprocessor sets the DivIrqReg
register’s CRCIRq bit after processing all the FIFO buffer data which is indicated by
CRCReady bit = 1.
The ComIrqReg register’s RxIRq bit indicates an interrupt when the end of the received
data is detected. The ComIrqReg register’s IdleIRq bit is set if a command finishes and
the Command[3:0] value in the CommandReg register changes to idle (see Table 158 on
page 101).
The ComIrqReg register’s HiAlertIRq bit is set to logic 1 when the Status1Reg register’s
HiAlert bit is set to logic 1 which means that the FIFO buffer has reached the level
indicated by the WaterLevel[5:0] bits.
The ComIrqReg register’s LoAlertIRq bit is set to logic 1 when the Status1Reg register’s
LoAlert bit is set to logic 1 which means that the FIFO buffer has reached the level
indicated by the WaterLevel[5:0] bits.
The ComIrqReg register’s ErrIRq bit indicates an error detected by the contactless UART
during send or receive. This is indicated when any bit is set to logic 1 in register ErrorReg.
LoAlert FIFOLength WaterLevel =
Table 157. Interrupt sources
Interrupt flag Interrupt source Trigger action
TimerIRq timer unit the timer counts from 1 to 0
TxIRq transmitter a transmitted data stream ends
CRCIRq CRC coprocessor all data from the FIFO buffer has been processed
RxIRq receiver a received data stream ends
IdleIRq ComIrqReg register command execution finishes
HiAlertIRq FIFO buffer the FIFO buffer is almost full
LoAlertIRq FIFO buffer the FIFO buffer is almost empty
ErrIRq contactless UART an error is detectedPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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15. Timer unit
A timer unit is implemented in the PN512. The external host controller may use this timer
to manage timing relevant tasks. The timer unit may be used in one of the following
configurations:
• Time-out counter
• Watch-dog counter
• Stop watch
• Programmable one-shot
• Periodical trigger
The timer unit can be used to measure the time interval between two events or to indicate
that a specific event occurred after a specific time. The timer can be triggered by events
which will be explained in the following, but the timer itself does not influence any internal
event (e.g. A time-out during data reception does not influence the reception process
automatically). Furthermore, several timer related bits are set and these bits can be used
to generate an interrupt.
Timer
The timer has an input clock of 13.56 MHz (derived from the 27.12 MHz quartz). The timer
consists of two stages: 1 prescaler and 1 counter.
The prescaler is a 12-bit counter. The reload value for TPrescaler can be defined between
0 and 4095 in register TModeReg and TPrescalerReg.
The reload value for the counter is defined by 16 bits in a range of 0 to 65535 in the
register TReloadReg.
The current value of the timer is indicated by the register TCounterValReg.
If the counter reaches 0 an interrupt will be generated automatically indicated by setting
the TimerIRq bit in the register CommonIRqReg. If enabled, this event can be indicated on
the IRQ line. The bit TimerIRq can be set and reset by the host controller. Depending on
the configuration the timer will stop at 0 or restart with the value from register
TReloadReg.
The status of the timer is indicated by bit TRunning in register Status1Reg.
The timer can be manually started by TStartNow in register ControlReg or manually
stopped by TStopNow in register ControlReg.
Furthermore the timer can be activated automatically by setting the bit TAuto in the
register TModeReg to fulfill dedicated protocol requirements automatically.
The time delay of a timer stage is the reload value +1.
The definition of total time is: t = ((TPrescaler*2+1)*TReload+1)/13.56MHz or if
TPrescaleEven bit is set: t = ((TPrescaler*2+2)*TReload+1)/13.56MHz
Maximum time: TPrescaler = 4095,TReloadVal = 65535
=> (2*4095 +2)*65536/13.56 MHz = 39.59 s
Example:PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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To indicate 25 us it is required to count 339 clock cycles. This means the value for
TPrescaler has to be set to TPrescaler = 169.The timer has now an input clock of 25 us.
The timer can count up to 65535 timeslots of each 25 s. For the behaviour in version
1.0, see Section 21 “Errata sheet” on page 109.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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16. Power reduction modes
16.1 Hard power-down
Hard power-down is enabled when pin NRSTPD is LOW. This turns off all internal current
sinks including the oscillator. All digital input buffers are separated from the input pins and
clamped internally (except pin NRSTPD). The output pins are frozen at either a HIGH or
LOW level.
16.2 Soft power-down mode
Soft Power-down mode is entered immediately after the CommandReg register’s
PowerDown bit is set to logic 1. All internal current sinks are switched off, including the
oscillator buffer. However, the digital input buffers are not separated from the input pins
and keep their functionality. The digital output pins do not change their state.
During soft power-down, all register values, the FIFO buffer content and the configuration
keep their current contents.
After setting the PowerDown bit to logic 0, it takes 1024 clocks until the Soft power-down
mode is exited indicated by the PowerDown bit. Setting it to logic 0 does not immediately
clear it. It is cleared automatically by the PN512 when Soft power-down mode is exited.
Remark: If the internal oscillator is used, you must take into account that it is supplied by
pin AVDD and it will take a certain time (tosc) until the oscillator is stable and the clock
cycles can be detected by the internal logic. It is recommended for the serial UART, to first
send the value 55h to the PN512. The oscillator must be stable for further access to the
registers. To ensure this, perform a read access to address 0 until the PN512 answers to
the last read command with the register content of address 0. This indicates that the
PN512 is ready.
16.3 Transmitter power-down mode
The Transmitter Power-down mode switches off the internal antenna drivers thereby,
turning off the RF field. Transmitter power-down mode is entered by setting either the
TxControlReg register’s Tx1RFEn bit or Tx2RFEn bit to logic 0.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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17. Oscillator circuitry
The clock applied to the PN512 provides a time basis for the synchronous system’s
encoder and decoder. The stability of the clock frequency, therefore, is an important factor
for correct operation. To obtain optimum performance, clock jitter must be reduced as
much as possible. This is best achieved using the internal oscillator buffer with the
recommended circuitry.
If an external clock source is used, the clock signal must be applied to pin OSCIN. In this
case, special care must be taken with the clock duty cycle and clock jitter and the clock
quality must be verified.
18. Reset and oscillator start-up time
18.1 Reset timing requirements
The reset signal is filtered by a hysteresis circuit and a spike filter before it enters the
digital circuit. The spike filter rejects signals shorter than 10 ns. In order to perform a reset,
the signal must be LOW for at least 100 ns.
18.2 Oscillator start-up time
If the PN512 has been set to a Power-down mode or is powered by a VDDX supply, the
start-up time for the PN512 depends on the oscillator used and is shown in Figure 36.
The time (tstartup) is the start-up time of the crystal oscillator circuit. The crystal oscillator
start-up time is defined by the crystal.
The time (td) is the internal delay time of the PN512 when the clock signal is stable before
the PN512 can be addressed.
The delay time is calculated by:
(5)
The time (tosc) is the sum of td and tstartup.
Fig 35. Quartz crystal connection
001aan231
PN512
27.12 MHz
OSCOUT OSCIN
td
1024
27 s = = -------------- 37.74 sPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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19. PN512 command set
The PN512 operation is determined by a state machine capable of performing a set of
commands. A command is executed by writing a command code (see Table 158) to the
CommandReg register.
Arguments and/or data necessary to process a command are exchanged via the FIFO
buffer.
19.1 General description
The PN512 operation is determined by a state machine capable of performing a set of
commands. A command is executed by writing a command code (see Table 158) to the
CommandReg register.
Arguments and/or data necessary to process a command are exchanged via the FIFO
buffer.
19.2 General behavior
• Each command that needs a data bit stream (or data byte stream) as an input
immediately processes any data in the FIFO buffer. An exception to this rule is the
Transceive command. Using this command, transmission is started with the
BitFramingReg register’s StartSend bit.
• Each command that needs a certain number of arguments, starts processing only
when it has received the correct number of arguments from the FIFO buffer.
• The FIFO buffer is not automatically cleared when commands start. This makes it
possible to write command arguments and/or the data bytes to the FIFO buffer and
then start the command.
• Each command can be interrupted by the host writing a new command code to the
CommandReg register, for example, the Idle command.
Fig 36. Oscillator start-up time
001aak596
tstartup td
tosc
t
device activation
oscillator
clock stable
clock readyPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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19.3 PN512 command overview
19.3.1 PN512 command descriptions
19.3.1.1 Idle
Places the PN512 in Idle mode. The Idle command also terminates itself.
19.3.1.2 Config command
To use the automatic MIFARE Anticollision, FeliCa Polling and NFCID3 the data used for
these transactions has to be stored internally. All the following data have to be written to
the FIFO in this order:
SENS_RES (2 bytes); in order byte 0, byte 1
NFCID1 (3 Bytes); in order byte 0, byte 1, byte 2; the first NFCID1 byte is fixed to 08h and
the check byte is calculated automatically.
SEL_RES (1 Byte)
polling response (2 bytes (shall be 01h, FEh) + 6 bytes NFCID2 + 8 bytes Pad + 2 bytes
system code)
NFCID3 (1 byte)
In total 25 bytes are transferred into an internal buffer.
The complete NFCID3 is 10 bytes long and consists of the 3 NFCID1 bytes, the 6 NFCID2
bytes and the one NFCID3 byte which are listed above.
To read out this configuration the command Config with an empty FIFO-buffer has to be
started. In this case the 25 bytes are transferred from the internal buffer to the FIFO.
Table 158. Command overview
Command Command
code
Action
Idle 0000 no action, cancels current command execution
Configure 0001 Configures the PN512 for FeliCa, MIFARE and NFCIP-1
communication
Generate RandomID 0010 generates a 10-byte random ID number
CalcCRC 0011 activates the CRC coprocessor or performs a self test
Transmit 0100 transmits data from the FIFO buffer
NoCmdChange 0111 no command change, can be used to modify the
CommandReg register bits without affecting the command,
for example, the PowerDown bit
Receive 1000 activates the receiver circuits
Transceive 1100 transmits data from FIFO buffer to antenna and automatically
activates the receiver after transmission
AutoColl 1101 Handles FeliCa polling (Card Operation mode only) and
MIFARE anticollision (Card Operation mode only)
MFAuthent 1110 performs the MIFARE standard authentication as a reader
SoftReset 1111 resets the PN512PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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The PN512 has to be configured after each power up, before using the automatic
Anticollision/Polling function (AutoColl command). During a hard power down (reset pin)
this configuration remains unchanged.
This command terminates automatically when finished and the active command is idle.
19.3.1.3 Generate RandomID
This command generates a 10-byte random number which is initially stored in the internal
buffer. This then overwrites the 10 bytes in the internal 25-byte buffer. This command
automatically terminates when finished and the PN512 returns to Idle mode.
19.3.1.4 CalcCRC
The FIFO buffer content is transferred to the CRC coprocessor and the CRC calculation is
started. The calculation result is stored in the CRCResultReg register. The CRC
calculation is not limited to a dedicated number of bytes. The calculation is not stopped
when the FIFO buffer is empty during the data stream. The next byte written to the FIFO
buffer is added to the calculation.
The CRC preset value is controlled by the ModeReg register’s CRCPreset[1:0] bits. The
value is loaded in to the CRC coprocessor when the command starts.
This command must be terminated by writing a command to the CommandReg register,
such as, the Idle command.
If the AutoTestReg register’s SelfTest[3:0] bits are set correctly, the PN512 enters Self
Test mode. Starting the CalcCRC command initiates a digital self test. The result of the
self test is written to the FIFO buffer.
19.3.1.5 Transmit
The FIFO buffer content is immediately transmitted after starting this command. Before
transmitting the FIFO buffer content, all relevant registers must be set for data
transmission.
This command automatically terminates when the FIFO buffer is empty. It can be
terminated by another command written to the CommandReg register.
19.3.1.6 NoCmdChange
This command does not influence any running command in the CommandReg register. It
can be used to manipulate any bit except the CommandReg register Command[3:0] bits,
for example, the RcvOff bit or the PowerDown bit.
19.3.1.7 Receive
The PN512 activates the receiver path and waits for a data stream to be received. The
correct settings must be chosen before starting this command.
This command automatically terminates when the data stream ends. This is indicated
either by the end of frame pattern or by the length byte depending on the selected frame
type and speed.
Remark: If the RxModeReg register’s RxMultiple bit is set to logic 1, the Receive
command will not automatically terminate. It must be terminated by starting another
command in the CommandReg register.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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19.3.1.8 Transceive
This command continuously repeats the transmission of data from the FIFO buffer and the
reception of data from the RF field. The first action is transmit and after transmission the
command is changed to receive a data stream.
Each transmit process must be started by setting the BitFramingReg register’s StartSend
bit to logic 1. This command must be cleared by writing any command to the
CommandReg register.
Remark: If the RxModeReg register’s RxMultiple bit is set to logic 1, the Transceive
command never leaves the receive state because this state cannot be cancelled
automatically.
19.3.1.9 AutoColl
This command automatically handles the MIFARE activation and the FeliCa polling in the
Card Operation mode. The bit Initiator in the register ControlReg has to be set to logic 0
for correct operation. During this command also the mode detector is active if not
deactivated by setting the bit ModeDetOff in the ModeReg register. After the mode
detector detects a mode, all the mode dependent registers are set according to the
received data. In case of no external RF field the command resets the internal state
machine and returns to the initial state but it will not be terminated. When the command
terminates the transceive command gets active.
During protocol processing the IRQ bits are not supported. Only the last received frame
will serve the IRQ’s. The treatment of the TxCRCEn and RxCRCEn bits is different to the
protocol. During ISO/IEC 14443A activation the enable bits are defined by the command
AutoColl. The changes cannot be observed at the register TXModeReg and RXModeReg.
After the Transceive command is active, the value of the register bit is relevant.
The FIFO will also receive the two CRC check bytes of the last command even if they
already checked and correct, if the state machine (Anticollision and Select routine) has to
not been executed and 106 kbit is detected.
During Felica activation the register bit is always relevant and is not overruled by the
command settings. This command can be cleared by software by writing any other
command to the CommandReg register, e.g. the idle command. Writing the same content
again to the CommandReg register resets the state machine.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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NFCIP-1 106 kbps Passive Communication mode:
The MIFARE anticollision is finished and the command has automatically changed to
Transceive. The FIFO contains the ATR_REQ frame including the start byte F0h. The bit
TargetActivated in the Status2Reg register is set to logic 1.
NFCIP-1 212/424 kbps Passive Communication mode:
The FeliCa polling command is finished and the command has automatically changed to
Transceive. The FIFO contains the ATR_REQ. The bit TargetActivated in the Status2Reg
register is set to logic 1.
NFCIP-1 106/212/424 kbps Active Communication mode:
This command is changing the automatically to the command Transceive. The FIFO
contains the ATR REQ The bit TargetActivated in the Status2Reg register is set to logic 0.
For 106 kbps only, the first byte in the FIFO indicates the start byte F0h and the CRC is
added to the FIFO.
Fig 37. Autocoll Command
NFCIP-1 106 kB aud
ISO14443-3
NPCIP-1 > 106 kB aud
FELICA
IDLE MODEO
MODE
detection
RXF
raming
MFHalted = 1
HALT
AC
nAC
SELECT
nSELECT
HLTA
AC
polling,
polling response
next frame
received
next frame
received
REQA, WUPA
READY
ACTIVE
WUPA
SELECT SELECT
READY*
ACTIVE*
TRANSCEIVE
wait for
transmit
next frame
received
J N
HLTA
REQA,
WUPA,
AC,
nAC,
SELECT,
nSELECT,
error
REQA,
AC,
nAC,
SELECT,
nSELECT,
HLTA
REQA,
WUPA,
nAC,
nSELECT,
HLTA,
error
REQA,
WUPA,
nAC,
nSELECT,
HLTA,
error
REQA,
WUPA,
AC,
SELECT,
nSELECT,
error
00 10
AC
aaa-001826PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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MIFARE (Card Operation mode):
The MIFARE anticollision is finished and the command has automatically changed to
transceive. The FIFO contains the first command after the Select. The bit TargetActivated
in the Status2Reg register is set to logic 1.
Felica (Card Operation mode):
The FeliCa polling command is finished and the command has automatically changed to
transceive. The FIFO contains the first command followed after the Poling by the FeliCa
protocol. The bit TargetActivated in the Status2Reg register is set to logic 1.
19.3.1.10 MFAuthent
This command manages MIFARE authentication to enable a secure communication to
any MIFARE Mini, MIFARE 1K and MIFARE 4K card. The following data is written to the
FIFO buffer before the command can be activated:
• Authentication command code (60h, 61h)
• Block address
• Sector key byte 0
• Sector key byte 1
• Sector key byte 2
• Sector key byte 3
• Sector key byte 4
• Sector key byte 5
• Card serial number byte 0
• Card serial number byte 1
• Card serial number byte 2
• Card serial number byte 3
In total 12 bytes are written to the FIFO.
Remark: When the MFAuthent command is active all access to the FIFO buffer is
blocked. However, if there is access to the FIFO buffer, the ErrorReg register’s WrErr bit is
set.
This command automatically terminates when the MIFARE card is authenticated and the
Status2Reg register’s MFCrypto1On bit is set to logic 1.
This command does not terminate automatically if the card does not answer, so the timer
must be initialized to automatic mode. In this case, in addition to the IdleIRq bit, the
TimerIRq bit can be used as the termination criteria. During authentication processing, the
RxIRq bit and TxIRq bit are blocked. The Crypto1On bit is only valid after termination of
the MFAuthent command, either after processing the protocol or writing Idle to the
CommandReg register.
If an error occurs during authentication, the ErrorReg register’s ProtocolErr bit is set to
logic 1 and the Status2Reg register’s Crypto1On bit is set to logic 0.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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19.3.1.11 SoftReset
This command performs a reset of the device. The configuration data of the internal buffer
remains unchanged. All registers are set to the reset values. This command automatically
terminates when finished.
Remark: The SerialSpeedReg register is reset and therefore the serial data rate is set to
9.6 kBd.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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20. Testsignals
20.1 Selftest
The PN512 has the capability to perform a digital selftest. To start the selftest the following
procedure has to be performed:
1. Perform a soft reset.
2. Clear the internal buffer by writing 25 bytes of 00h and perform the Config Command.
3. Enable the Selftest by writing the value 09h to the register AutoTestReg.
4. Write 00h to the FIFO.
5. Start the Selftest with the CalcCRC Command.
6. The Selftest will be performed.
7. When the Selftest is finished, the FIFO contains the following bytes:
Version 1.0 has a different Selftest answer, explained in Section 21.
Correct answer for VersionReg equal to 82h:
00h, EBh, 66h, BAh, 57h, BFh, 23h, 95h, D0h, E3h, 0Dh, 3Dh, 27h, 89h, 5Ch, DEh,
9Dh, 3Bh, A7h, 00h, 21h, 5Bh, 89h, 82h, 51h, 3Ah, EBh, 02h, 0Ch, A5h, 00h,
49h, 7Ch, 84h, 4Dh, B3h, CCh, D2h, 1Bh, 81h, 5Dh, 48h, 76h, D5h, 71h, 61h,
21h, A9h, 86h, 96h, 83h, 38h, CFh, 9Dh, 5Bh, 6Dh, DCh, 15h, BAh, 3Eh, 7Dh,
95h, 3Bh, 2Fh
20.2 Testbus
The testbus is implemented for production test purposes. The following configuration can
be used to improve the design of a system using the PN512. The testbus allows to route
internal signals to the digital interface. The testbus signals are selected by accessing
TestBusSel in register TestSel2Reg.
Table 159. Testsignal routing (TestSel2Reg = 07h)
Pins D6 D5 D4 D3 D2 D1 D0
Testsignal sdata scoll svalid sover RCV_reset RFon,
filtered
Envelope
Table 160. Description of Testsignals
Pins Testsignal Description
D6 sdata shows the actual received data stream.
D5 scoll shows if in the actual bit a collision has been detected (106 kbit only)
D4 svalid shows if sdata and scoll are valid
D3 sover shows that the receiver has detected a stop condition
(ISO/IEC 14443A/ MIFARE mode only).
D2 RCV_reset shows if the receiver is reset
D1 RFon, filtered shows the value of the internal RF level detector
D0 Envelope shows the output of the internal coderPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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20.3 Testsignals at pin AUX
Table 161. Testsignal routing (TestSel2Reg = 0Dh)
Pins D6 D5 D4 D3 D2 D1 D0
Testsignal clkstable clk27/8 clk27rf/8 clkrf13rf/4 clk27 clk27rf clk13rf
Table 162. Description of Testsignals
Pins Testsignal Description
D6 clkstable shows if the oscillator delivers a stable signal.
D5 clk27/8 shows the output signal of the oscillator divided by 8
D4 clk27rf/8 shows the clk27rf signal divided by 8
D3 clkrf13/4 shows the clk13rf divided by 4.
D2 clk27 shows the output signal of the oscillator
D1 clk27rf shows the RF clock multiplied by 2.
D0 clk13rf shows the RF clock of 13.56 MHz
Table 163. Testsignal routing (TestSel2Reg = 19h)
Pins D6 D5 D4 D3 D2 D1 D0
Testsignal - TRunning - - - - -
Table 164. Description of Testsignals
Pins Testsignal Description
D6 - -
D5 TRunning TRunning stops 1 clockcycle after TimerIRQ is raised
D4 - -
D3 - -
D2 - -
D1 - -
D0 - -
Table 165. Testsignals description
SelAux Description for Aux1 / Aux2
0000 Tristate
0001 DAC: register TestDAC 1/2
0010 DAC: testsignal corr1
0011 DAC: testsignal corr2
0100 DAC: testsignal MinLevel
0101 DAC: ADC_I
0110 DAC: ADC_Q
0111 DAC: testsignal ADC_I combined with ADC_Q
1000 Testsignal for production test
1001 SAM clock
1010 High
1011 low
1100 TxActivePN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Each signal can be switched to pin AUX1 or AUX2 by setting SelAux1 or SelAux2 in the
register AnalogTestReg.
Note: The DAC has a current output, it is recommended to use a 1 k pull-down
resistance at pins AUX1/AUX2.
20.4 PRBS
Enables the PRBS9 or PRBS15 sequence according to ITU-TO150. To start the
transmission of the defined datastream the command send has to be activated. The
preamble/Sync byte/start bit/parity bit are generated automatically depending on the
selected mode.
Note: All relevant register to transmit data have to be configured before entering PRBS
mode according ITU-TO150.
21. Errata sheet
This data sheet is describing the functionality for version 2.0 and the industrial version.
This chapter lists all differences from version 1.0 to version 2.0:
The value of the version in Section 9.2.4.8 is set to80h.
The behaviour ‘RFU’ for the register is undefined.
The answer to the Selftest (see Section 20.1) for version 1.0 (VersionReg equal to 80h):
00h, AAh, E3h, 29h, 0Ch, 10h, 29zhh, 6Bh,
76h, 8Dh, AFh, 4Bh, A2h, DAh, 76h, 99h
C7h, 5Eh, 24h, 69h, D2h, BAh, FAh, BCh
3Eh, DAh, 96h, B5h, F5h, 94h, B0h, 3Ah
4Eh, C3h, 9Dh, 94h, 76h, 4Ch, EAh, 5Eh
38h, 10h, 8Fh, 2Dh, 21h, 4Bh, 52h, BFh
4Eh, C3h, 9Dh, 94h, 76h, 4Ch, EAh, 5Eh
38h, 10h, 8Fh, 2Dh, 21h, 4Bh, 52h, BFh
FBh, F4h, 19h, 94h, 82h, 5Ah, 72h, 9Dh
BAh, 0Dh, 1Fh, 17h, 56h, 22h, B9h, 08h
Only the default setting for the prescaler (see Section 15 “Timer unit” on page 96): t =
((TPreScaler*2+1)*TReload+1)/13,56 MHz is supported. As such only the formula fTimer =
13,56 MHz/(2*PreScaler+1) is applicable for the TPrescalerHigh in Table 100 “Description
of TModeReg bits” on page 57 and TPrescalerLo in Table 101 “TPrescalerReg register
(address 2Bh); reset value: 00h, 00000000b” on page 58. As there is no option for the
prescaler available, also the TPrescalEven is not available Section 9.2.2.10 on page 45.
This bit is set to ‘RFU’.
1101 RxActive
1110 Subcarrier detected
1111 TstBusBit
Table 165. Testsignals description
SelAux Description for Aux1 / Aux2PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Especially when using time slot protocols, it is needed that the error flag is copied into the
status information of the frame. When using the RxMultiple feature (see Section 9.2.2.4
on page 39) within version 1.0 the protocol error flag is not included in the status
information for the frame. In addition the CRCOk is copied instead of the CRCErr. This
can be a problem in frames without length information e.g. ISO/IEC 14443-B.
The version 1.0 does not accept a Type B EOF if there is no 1 bit after the series of 0 bits,
as such the configuration within Section 9.2.2.15 “TypeBReg” on page 50 bit 4 for
RxEOFReq does not exist. In addition the IC only has the possibility to select the
minimum or maximum timings for SOF/EOF generation defined in ISO/IEC14443B. As
such the configuration possible in version 2.0 through the EOFSOFAdjust bit (see Section
9.2.4.7 “AutoTestReg” on page 64) does not exist and the configuration is limited to only
setting minimum and maximum length according ISO/IEC 14443-B, see Section 9.2.2.15
“TypeBReg” on page 50, bit 4.
22. Application design-in information
The figure below shows a typical circuit diagram, using a complementary antenna
connection to the PN512.
The antenna tuning and RF part matching is described in the application note “NFC
Transmission Module Antenna and RF Design Guide”.
Fig 38. Typical circuit diagram
AVDD TVDD
RX
VMID
supply
TX1
TVSS
TX2
DVSS
DVDD
DVDD
PVDD
SVDD
AVSS
IRQ
NRSTPD
R1
R2
L0
C0
C0
C2
C1
CRX
RQ
C1 RQ
C2
L0
Cvmid
001aan232
27.12 MHz
OSCIN OSCOUT
HOST
CONTROLLER
interface
PN512
antenna
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23. Limiting values
24. Recommended operating conditions
Table 166. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDDA analog supply voltage 0.5 +4.0 V
VDDD digital supply voltage 0.5 +4.0 V
VDD(PVDD) PVDD supply voltage 0.5 +4.0 V
VDD(TVDD) TVDD supply voltage 0.5 +4.0 V
VDD(SVDD) SVDD supply voltage 0.5 +4.0 V
VI input voltage all input pins except pins SIGIN and
RX
VSS(PVSS) 0.5 VDD(PVDD) + 0.5 V
pin MFIN VSS(PVSS) 0.5 VDD(SVDD) + 0.5 V
Ptot total power dissipation per package; and VDDD in shortcut
mode
- 200 mW
Tj junction temperature - 125 C
VESD electrostatic discharge
voltage
HBM; 1500 , 100 pF;
JESD22-A114-B
- 2000 V
MM; 0.75 H, 200 pF;
JESD22-A114-A
- 200 V
Charged device model;
JESD22-C101-A
on all pins - 200 V
on all pins except SVDD in
TFBGA64 package
- 500 V
Industrial version:
VESD electrostatic discharge
voltage
HBM; 1500 , 100 pF;
JESD22-A114-B
- 2000 V
MM; 0.75 H, 200 pF;
JESD22-A114-A
- 200 V
Charged device model;
AEC-Q100-011
on all pins - 200 V
on all pins except SVDD - 500 V
Table 167. Operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VDDA analog supply voltage VDD(PVDD) VDDA = VDDD = VDD(TVDD);
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) =0V
[1][2] 2.5 - 3.6 V
VDDD digital supply voltage VDD(PVDD) VDDA = VDDD = VDD(TVDD);
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) =0V
[1][2] 2.5 - 3.6 V
VDD(TVDD) TVDD supply voltage VDD(PVDD) VDDA = VDDD = VDD(TVDD);
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) =0V
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[1] Supply voltages below 3 V reduce the performance (the achievable operating distance).
[2] VDDA, VDDD and VDD(TVDD) must always be the same voltage.
[3] VDD(PVDD) must always be the same or lower voltage than VDDD.
25. Thermal characteristics
26. Characteristics
VDD(PVDD) PVDD supply voltage VDD(PVDD) VDDA = VDDD = VDD(TVDD);
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) =0V
[3] 1.6 - 3.6 V
VDD(SVDD) SVDD supply voltage VSSA = VSSD = VSS(PVSS) = VSS(TVSS) =0V 1.6 - 3.6 V
Tamb ambient temperature HVQFN32, HVQFN40, TFBGA64 30 - +85 C
Industrial version:
Tamb ambient temperature HVQFN32 40 - +90 C
Table 167. Operating conditions …continued
Symbol Parameter Conditions Min Typ Max Unit
Table 168. Thermal characteristics
Symbol Parameter Conditions Package Typ Unit
Rthj-a Thermal resistance from
junction to ambient
In still air with exposed pad
soldered on a 4 layer Jedec PCB
In still air
HVQFN32 40 K/W
HVQFN40 35 K/W
TFBGA64 K/W
Table 169. Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Input characteristics
Pins A0, A1 and NRSTPD
ILI input leakage current 1 - +1 A
VIH HIGH-level input voltage 0.7VDD(PVDD) -- V
VIL LOW-level input voltage - - 0.3VDD(PVDD) V
Pin SIGIN
ILI input leakage current 1 - +1 A
VIH HIGH-level input voltage 0.7VDD(SVDD) -- V
VIL LOW-level input voltage - - 0.3VDD(SVDD) V
Pin ALE
ILI input leakage current 1 - +1 A
VIH HIGH-level input voltage 0.7VDD(PVDD) -- V
VIL LOW-level input voltage - - 0.3VDD(PVDD) V
Pin RX[1]
Vi input voltage 1 -VDDA +1 V
Ci input capacitance VDDA = 3 V; receiver active;
VRX(p-p) = 1 V; 1.5 V (DC)
offset
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Ri input resistance VDDA = 3 V; receiver active;
VRX(p-p) = 1 V; 1.5 V (DC)
offset
- 350 -
Input voltage range; see Figure 39
Vi(p-p)(min) minimum peak-to-peak input
voltage
Manchester encoded;
VDDA =3V
- 100 - mV
Vi(p-p)(max) maximum peak-to-peak input
voltage
Manchester encoded;
VDDA =3V
- 4- V
Input sensitivity; see Figure 39
Vmod modulation voltage minimum Manchester
encoded; VDDA = 3 V;
RxGain[2:0] = 111b (48 dB)
- 5 - mV
Pin OSCIN
ILI input leakage current 1 - +1 A
VIH HIGH-level input voltage 0.7VDDA -- V
VIL LOW-level input voltage - - 0.3VDDA V
Ci input capacitance VDDA = 2.8 V; DC = 0.65 V;
AC = 1 V (p-p)
- 2 - pF
Input/output characteristics
pins D1, D2, D3, D4, D5, D6 and D7
ILI input leakage current 1 - +1 A
VIH HIGH-level input voltage 0.7VDD(PVDD) -- V
VIL LOW-level input voltage - - 0.3VDD(PVDD) V
VOH HIGH-level output voltage VDD(PVDD) = 3 V; IO = 4 mA VDD(PVDD)
0.4
- VDD(PVDD) V
VOL LOW-level output voltage VDD(PVDD) = 3 V; IO = 4 mA VSS(PVSS) - VSS(PVSS) +
0.4
V
IOH HIGH-level output current VDD(PVDD) =3V - - 4 mA
IOL LOW-level output current VDD(PVDD) =3V - - 4 mA
Output characteristics
Pin SIGOUT
VOH HIGH-level output voltage VDD(SVDD) = 3 V; IO = 4 mA VDD(SVDD)
0.4
- VDD(SVDD) V
VOL LOW-level output voltage VDD(SVDD) = 3 V; IO = 4 mA VSS(PVSS) - VSS(PVSS) +
0.4
V
IOL LOW-level output current VDD(SVDD) =3V - - 4 mA
IOH HIGH-level output current VDD(SVDD) =3V - - 4 mA
Pin IRQ
VOH HIGH-level output voltage VDD(PVDD) = 3 V; IO = 4 mA VDD(PVDD)
0.4
- VDD(PVDD) V
VOL LOW-level output voltage VDD(PVDD) = 3 V; IO = 4 mA VSS(PVSS) - VSS(PVSS) +
0.4
V
IOL LOW-level output current VDD(PVDD) =3V - - 4 mA
IOH HIGH-level output current VDD(PVDD) =3V - - 4 mA
Table 169. Characteristics …continued
Symbol Parameter Conditions Min Typ Max UnitPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Pins AUX1 and AUX2
VOH HIGH-level output voltage VDDD = 3 V; IO = 4 mA VDDD 0.4 - VDDD V
VOL LOW-level output voltage VDDD = 3 V; IO = 4 mA VSS(PVSS) - VSS(PVSS) +
0.4
V
IOL LOW-level output current VDDD =3V - - 4 mA
IOH HIGH-level output current VDDD =3V - - 4 mA
Pins TX1 and TX2
VOL LOW-level output voltage VDD(TVDD) = 3 V;
IDD(TVDD) = 32 mA;
CWGsP[5:0] = 0Fh
- - 0.15 V
VDD(TVDD) = 3 V;
IDD(TVDD) = 80 mA;
CWGsP[5:0] = 0Fh
- - 0.4 V
VDD(TVDD) = 2.5 V;
IDD(TVDD) = 32 mA;
CWGsP[5:0] = 0Fh
- - 0.24 V
VDD(TVDD) = 2.5 V;
IDD(TVDD) = 80 mA;
CWGsP[5:0] = 0Fh
- - 0.64 V
VOH HIGH-level output voltage VDD(TVDD) = 3 V;
IDD(TVDD) = 32 mA;
CWGsP[5:0] = 3Fh
VDD(TVDD)
0.15
-- V
VDD(TVDD) = 3 V;
IDD(TVDD) = 80 mA;
CWGsP[5:0] = 3Fh
VDD(TVDD)
0.4
-- V
VDD(TVDD) = 2.5 V;
IDD(TVDD) = 32 mA;
CWGsP[5:0] = 3Fh
VDD(TVDD)
0.24
-- V
VDD(TVDD) = 2.5 V;
IDD(TVDD) = 80 mA;
CWGsP[5:0] = 3Fh
VDD(TVDD)
0.64
-- V
Industrial version:
VOL LOW-level output voltage VDD(TVDD) = 2.5 V;
IDD(TVDD) = 32 mA;
CWGsP[5:0] = 3Fh
- - 0.18 V
VDD(TVDD) = 2.5 V;
IDD(TVDD) = 80 mA;
CWGsP[5:0] = 3Fh
- -0.44 V
VOH HIGH-level output voltage VDD(TVDD) = 3 V;
IDD(TVDD) = 32 mA;
CWGsP[5:0] = 3Fh
VDD(TVDD)
0.18
-- V
VDD(TVDD) = 3 V;
IDD(TVDD) = 80 mA;
CWGsP[5:0] = 3Fh
VDD(TVDD)
0.44
-- V
Output resistance for TX1/TX2,
Industrial Version:
ROP,01H High level output resistance TVDD = 3 V, VTX = TVDD -
100 mV, CWGsP = 01h
123 180 261
Table 169. Characteristics …continued
Symbol Parameter Conditions Min Typ Max UnitPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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ROP,02H High level output resistance TVDD = 3 V, VTX = TVDD -
100 mV, CWGsP = 02h
61 90 131
ROP,04H High level output resistance TVDD = 3 V, VTX = TVDD -
100 mV, CWGsP = 04h
30 46 68
ROP,08H High level output resistance TVDD = 3 V, VTX = TVDD -
100 mV, CWGsP = 08h
15 23 35
ROP,10H High level output resistance TVDD = 3 V, VTX = TVDD -
100 mV, CWGsP = 10h
7.5 12 19
ROP,20H High level output resistance TVDD = 3 V, VTX = TVDD -
100 mV, CWGsP = 20h
4.2 6 9
ROP,3FH High level output resistance TVDD = 3 V, VTX = TVDD -
100 mV, CWGsP = 3Fh
2 35
RON,10H Low level output resistance TVDD = 3 V, VTX = TVDD -
100 mV, CWGsN = 10h
30 46 68
RON,20H Low level output resistance TVDD = 3 V, VTX = TVDD -
100 mV, CWGsN = 20h
15 23 35
RON,40H Low level output resistance TVDD = 3 V, VTX = TVDD -
100 mV, CWGsN = 40h
7.5 12 19
RON,80H Low level output resistance TVDD = 3 V, VTX = TVDD -
100 mV, CWGsN = 80h
4.2 6 9
RON,F0H Low level output resistance TVDD = 3 V, VTX = TVDD -
100 mV, CWGsN = F0h
2 35
Current consumption
Ipd power-down current VDDA = VDDD = VDD(TVDD) =
VDD(PVDD) =3V
hard power-down; pin
NRSTPD set LOW
[2] - -5 A
soft power-down; RF
level detector on
[2] - -10 A
IDD(PVDD) PVDD supply current pin PVDD [3] - -40 mA
IDD(TVDD) TVDD supply current pin TVDD; continuous wave [4][5][6] - 60 100 mA
IDD(SVDD) SVDD supply current pin SVDD [7] - -4 mA
IDDD digital supply current pin DVDD; VDDD =3V - 6.5 9 mA
IDDA analog supply current pin AVDD; VDDA = 3 V,
CommandReg register’s
RcvOff bit = 0
- 7 10 mA
pin AVDD; receiver
switched off; VDDA = 3 V,
CommandReg register’s
RcvOff bit = 1
- 3 5 mA
Industrial version:
IDDD digital supply current pin DVDD; VDDD =3V - 6.5 9,5 mA
Table 169. Characteristics …continued
Symbol Parameter Conditions Min Typ Max UnitPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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[1] The voltage on pin RX is clamped by internal diodes to pins AVSS and AVDD.
[2] Ipd is the total current for all supplies.
[3] IDD(PVDD) depends on the overall load at the digital pins.
[4] IDD(TVDD) depends on VDD(TVDD) and the external circuit connected to pins TX1 and TX2.
[5] During typical circuit operation, the overall current is below 100 mA.
[6] Typical value using a complementary driver configuration and an antenna matched to 40 between pins TX1 and TX2 at 13.56 MHz.
[7] IDD(SVDD) depends on the load at pin MFOUT.
Ipd power-down current VDDA = VDDD = VDD(TVDD) =
VDD(PVDD) =3V
hard power-down; pin
NRSTPD set LOW
[2] - -15 A
soft power-down; RF
level detector on
[2] - -30 A
Clock frequency
fclk clock frequency - 27.12 - MHz
clk clock duty cycle 40 50 60 %
tjit jitter time RMS - - 10 ps
Crystal oscillator
VOH HIGH-level output voltage pin OSCOUT - 1.1 - V
VOL LOW-level output voltage pin OSCOUT - 0.2 - V
Ci input capacitance pin OSCOUT - 2 - pF
pin OSCIN - 2 - pF
Typical input requirements
fxtal crystal frequency - 27.12 - MHz
ESR equivalent series resistance - - 100
CL load capacitance - 10 - pF
Pxtal crystal power dissipation - 50 100 W
Table 169. Characteristics …continued
Symbol Parameter Conditions Min Typ Max UnitPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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26.1 Timing characteristics
Fig 39. Pin RX input voltage range
001aak012
VMID
0 V
Vmod
Vi(p-p)(max) Vi(p-p)(min)
13.56 MHz
carrier
Table 170. SPI timing characteristics
Symbol Parameter Conditions Min Typ Max Unit
tWL pulse width LOW line SCK 50 - - ns
tWH pulse width HIGH line SCK 50 - - ns
th(SCKH-D) SCK HIGH to data input
hold time
SCK to changing
MOSI
25 - - ns
tsu(D-SCKH) data input to SCK HIGH
set-up time
changing MOSI to
SCK
25 - - ns
th(SCKL-Q) SCK LOW to data output
hold time
SCK to changing
MISO
- - 25 ns
t(SCKL-NSSH) SCK LOW to NSS HIGH
time
0 - - ns
Table 171. I2C-bus timing in Fast mode
Symbol Parameter Conditions Fast mode High-speed
mode
Unit
Min Max Min Max
fSCL SCL clock frequency 0 400 0 3400 kHz
tHD;STA hold time (repeated) START
condition
after this period,
the first clock pulse
is generated
600 - 160 - ns
tSU;STA set-up time for a repeated
START condition
600 - 160 - ns
tSU;STO set-up time for STOP condition 600 - 160 - ns
tLOW LOW period of the SCL clock 1300 - 160 - ns
tHIGH HIGH period of the SCL clock 600 - 60 - ns
tHD;DAT data hold time 0 900 0 70 nsPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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tSU;DAT data set-up time 100 - 10 - ns
tr rise time SCL signal 20 300 10 40 ns
tf fall time SCL signal 20 300 10 40 ns
tr rise time SDA and SCL
signals
20 300 10 80 ns
tf fall time SDA and SCL
signals
20 300 10 80 ns
tBUF bus free time between a STOP
and START condition
1.3 - 1.3 - s
Remark: The signal NSS must be LOW to be able to send several bytes in one data stream.
To send more than one data stream NSS must be set HIGH between the data streams.
Fig 40. Timing diagram for SPI
Fig 41. Timing for Fast and Standard mode devices on the I2C-bus
Table 171. I2C-bus timing in Fast mode …continued
Symbol Parameter Conditions Fast mode High-speed
mode
Unit
Min Max Min Max
001aaj634
tSCKL tSCKH tSCKL
tDXSH tSHDX tDXSH
tSLDX
tSLNH
MOSI
SCK
MISO
MSB
MSB
LSB
LSB
NSS
001aaj635
SDA
tf
SCL
tLOW tf
tSP tr
tHD;STA
tHD;DAT
tHD;STA
tr tHIGH
tSU;DAT
S Sr P S
tSU;STA
tSU;STO
tBUFPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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26.2 8-bit parallel interface timing
26.2.1 AC symbols
Each timing symbol has five characters. The first character is always 't' for time. The other
characters indicate the name of a signal or the logic state of that signal (depending on
position):
Example: tAVLL = time for address valid to ALE low
26.2.2 AC operating specification
26.2.2.1 Bus timing for separated Read/Write strobe
Table 172. AC symbols
Designation Signal Designation Logic Level
A address H HIGH
D data L LOW
W NWR or nWait Z high impedance
R NRD or R/NW or nWrite X any level or data
L ALE or AS V any valid signal or data
C NCS N NSS
S NDS or nDStrb and nAStrb, SCK
Table 173. Timing specification for separated Read/Write strobe
Symbol Parameter Min Max Unit
tLHLL ALE pulse width 10 - ns
tAVLL Multiplexed Address Bus valid to ALE low (Address Set Up Time) 5 - ns
tLLAX Multiplexed Address Bus valid after ALE low (Address Hold Time) 5 - ns
tLLWL ALE low to NWR, NRD low 10 - ns
tCLWL NCS low to NRD, NWR low 0 - ns
tWHCH NRD, NWR high to NCS high 0 - ns
tRLDV NRD low to DATA valid - 35 ns
tRHDZ NRD high to DATA high impedance - 10 ns
tDVWH DATA valid to NWR high 5 - ns
tWHDX DATA hold after NWR high (Data Hold Time) 5 - ns
tWLWH NRD, NWR pulse width 40 - ns
tAVWL Separated Address Bus valid to NRD, NWR low (Set Up Time) 30 - ns
tWHAX Separated Address Bus valid after NWR high (Hold Time) 5 - ns
tWHWL period between sequenced read/write accesses 40 - nsPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Remark: For separated address and data bus the signal ALE is not relevant and the
multiplexed addresses on the data bus don’t care.
For the multiplexed address and data bus the address lines A0 to A3 have to be
connected as described in chapter Automatic host controller Interface Type Detection.
26.2.2.2 Bus timing for common Read/Write strobe
Fig 42. Timing diagram for separated Read/Write strobe
001aan233
tLHLL
tCLWL
tLLWL
tWHWL tWLWH tWHWL
tWHDX
tRHDZ
tWLDV
tRLDV
tWHCH
tWHAX
tAVLL tLLAX
tAVWL
ALE
NCS
NWR
NRD
D0...D7 D0...D7
A0...A3
multiplexed
addressbus
A0...A3
SEPARATED ADDRESSBUS A0...A3
Table 174. Timing specification for common Read/Write strobe
Symbol Parameter Min Max Unit
tLHLL AS pulse width 10 - ns
tAVLL Multiplexed Address Bus valid to AS low (Address Set Up Time) 5 - ns
tLLAX Multiplexed Address Bus valid after AS low (Address Hold Time) 5 - ns
tLLSL AS low to NDS low 10 - ns
tCLSL NCS low to NDS low 0 - ns
tSHCH NDS high to NCS high 0 - ns
tSLDV,R NDS low to DATA valid (for read cycle) - 35 ns
tSHDZ NDS low to DATA high impedance (read cycle) - 10 ns
tDVSH DATA valid to NDS high (for write cycle) 5 - ns
tSHDX DATA hold after NDS high (write cycle, Hold Time) 5 - ns
tSHRX R/NW hold after NDS high 5 - ns
tSLSH NDS pulse width 40 - ns
tAVSL Separated Address Bus valid to NDS low (Hold Time) 30 - ns
tSHAX Separated Address Bus valid after NDS high (Set Up Time) 5 - nsPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Remark: For separated address and data bus the signal ALE is not relevant and the
multiplexed addresses on the data bus don’t care. For the multiplexed address and data
bus the address lines A0 to A3 have to be connected as described in Automatic
-Controller Interface Type Detection.
Fig 43. Timing diagram for common Read/Write strobe
SEPARATED ADDRESSBUS A0...A3
multiplexed
addressbus
A0...A3
ALE
tLHLL
tCLSL
R/NW
NDS
D0...D7 D0...D7
A0...A3
NCS
tSHCH
tSHRX tRVSL
tLLSL
tSLSH tSHSL
tAVLL
tLLAX
tSLDV, R
tSLDV, W tSHDX
tSHDZ
tSHAX tAVSL
tSHSL
001aan234PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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27. Package information
The PN512 can be delivered in 3 different packages.
Table 175. Package information
Package Remarks
HVQFN32 8-bit parallel interface not supported
HVQFN40 Supports the 8-bit parallel interface
TFBGA64 Ball grid array facilitating development of an PCI compliant devicePN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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28. Package outline
Fig 44. Package outline package version (HVQFN32)
1 0.5
UNIT A1 b Eh e y
0.2
c
OUTLINE REFERENCES
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 5.1
4.9
Dh
3.25
2.95
y1
5.1
4.9
3.25
2.95
e1
3.5
e2
3.5 0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT617-1 MO-220 - - - - - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT617-1
HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm
A(1)
max.
A
A1
c
detail X
y y e 1 C
L
Eh
Dh
e
e1
b
9 16
32 25
24
17
8
1
X
D
E
C
B A
e2
terminal 1
index area
terminal 1
index area
01-08-08
02-10-18
1/2 e
1/2 e AC
C
v M B
w M
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Fig 45. Package outline package version (HVQFN40)
Outline References
version
European
projection Issue date
IEC JEDEC JEITA
SOT618-1 MO-220
sot618-1_po
02-10-22
13-11-05
Unit
mm
max
nom
min
1.00 0.05 0.2 6.1 4.25 6.1
0.4
A(1)
Dimensions (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
HVQFN40: plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6 x 6 x 0.85 mm SOT618-1
A1 b
0.30
c D(1) Dh E(1) Eh
4.10
e e1 e2 Lvw
0.05
y
0.05
y1
0.1
0.85 0.02 6.0 4.10 6.0 0.21
0.80 0.00 0.18 5.9 3.95 5.9 3.95 0.3
4.25 0.5 4.5 0.5 4.5 0.1
e
e
1/2 e
1/2 e
y
terminal 1
index area
A A1
c
L
Eh
Dh
b
11 20
40 31
30
21 10
1
D
E
terminal 1
index area
0 2.5 5 mm
scale
e1
AC
C
v B
w y1 C
C
e2
X
detail X
B APN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Fig 46. Package outline package version (TFBGA64)
Outline References
version
European
projection Issue date
IEC JEDEC JEITA
SOT1336-1 - - -
sot1336-1_po
12-06-19
12-08-28
Unit
mm
max
nom
min
1.15 0.35 0.45 5.6 5.6
4.55 0.15 0.1
A
Dimensions (mm are the original dimensions)
TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls
A1 A2
0.80
1.00 0.30 0.40 5.5 5.5 0.65 0.70
b DE ee1
4.55
0.90 0.25 0.35 5.4 5.4 0.65
e2 v w
0.08
y y1
0.1
SOT1336-1
C
y1 C y
0 5 mm
scale
X
A
A2
A1
detail X
ball A1
index area
ball A1
index area
A
E
D B
e2
e
A
B
C
D
E
F
G
H
1 3 5 78 246
e1
e Ø v AC B
Ø w C b
1/2 e
1/2 ePN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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29. Abbreviations
30. Glossary
Modulation index — Defined as the voltage ratio (Vmax Vmin) / (Vmax + Vmin).
Load modulation index — Defined as the voltage ratio for the card
(Vmax Vmin) / (Vmax + Vmin) measured at the card’s coil.
Initiator — Generates RF field at 13.56 MHz and starts the NFCIP-1 communication.
Target — Responds to command either using load modulation scheme (RF field
generated by Initiator) or using modulation of self generated RF field (no RF field
generated by initiator).
31. References
[1] Application note — NFC Transmission Module Antenna and RF Design Guide
Table 176. Abbreviations
Acronym Description
ADC Analog-to-Digital Converter
ASK Amplitude Shift keying
BPSK Binary Phase Shift Keying
CRC Cyclic Redundancy Check
CW Continuous Wave
DAC Digital-to-Analog Converter
EOF End of frame
HBM Human Body Model
I
2C Inter-integrated Circuit
LSB Least Significant Bit
MISO Master In Slave Out
MM Machine Model
MOSI Master Out Slave In
MSB Most Significant Bit
NSS Not Slave Select
PCB Printed-Circuit Board
PLL Phase-Locked Loop
PRBS Pseudo-Random Bit Sequence
RX Receiver
SOF Start Of Frame
SPI Serial Peripheral Interface
TX Transmitter
UART Universal Asynchronous Receiver TransmitterPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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32. Revision history
Table 177. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PN512 v.4.5 20131217 Product data sheet - PN512 v.4.4
Modifications: • Typo corrected
PN512 v.4.4 20130730 Product data sheet - PN512 v.4.3
Modifications: • Value added in Table 166 “Limiting values”
• Change of descriptive title
PN512 v.4.3 20130507 Product data sheet - PN512 v.4.2
Modifications: • New type PN5120A0ET/C2 added
• Table 72 “Description of MifNFCReg bits”: description of TxWait updated
• Table 153 “Register and bit settings controlling the signal on pin TX1” and Table 153 “Register
and bit settings controlling the signal on pin TX1”: updated
• Table 166 “Limiting values”: VESD values added
PN512 v.4.2 20120828 Product data sheet - PN512 v.4.1
Modifications: • Table 123 “AutoTestReg register (address 36h); reset value: 40h, 01000000b”: description of
bits 4 and 5 corrected
PN512 v.4.1 20120821 Product data sheet - PN512 v.4.0
Modifications: • Table 124 “Description of bits”: description of bits 4 and 5 corrected
PN512 v.4.0 20120712 Product data sheet - PN512 v.3.9
Modifications: • Section 33.4 “Licenses”: updated
PN512 v.3.9 20120201 Product data sheet - PN512 v.3.8
Modifications: • Adding information on the different version in General description.
• Adding Section 21 “Errata sheet” on page 109 for explanation of differences between 1.0 and
2.0.
• Adding ordering information for version 1.0 and industrial version in Table 2 “Ordering
information” on page 5
• Adding the limitations and characteristics for the industrial version, see Table 1 “Quick
reference data” on page 4, Table 166 “Limiting values” on page 111, Table 1 “Quick reference
data” on page 4
• Referring to the Section 21 “Errata sheet” on page 109 within the following sections: Section
9.2.2.4 “RxModeReg” on page 39, Section 9.2.2.10 “DemodReg” on page 45, Section 9.2.2.15
“TypeBReg” on page 50, Section 9.2.3.10 “TMode Register, TPrescaler Register” on page 57,
Section 9.2.4.7 “AutoTestReg” on page 64, Section 9.2.4.8 “VersionReg” on page 64, Section
9.1.1 “Register bit behavior” on page 23, Section 15 “Timer unit” on page 96, Section 20
“Testsignals” on page 107;
• Update of command ‘Mem’ to ‘Configure’ and ‘RFU’ to ‘Autocoll’ in Table 158 “Command
overview” on page 101.
• Change of ‘Mem’ to ‘Configure’ in ‘Mem’ in Section 19.3.1.2 “Config command” on page 101
• Adding Autocoll in Section 19.3.1.9 “AutoColl” on page 103
PN512 v.3.8 20111025 Product data sheet - PN512 v.3.7
Modifications: • Table 168 “Characteristics”: unit of Pxtal corrected
111310 June 2005 Objective data sheet -
Modifications: • Initial versionPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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33. Legal information
33.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
33.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
33.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 4.5 — 17 December 2013
111345 129 of 136
NXP Semiconductors PN512
Full NFC Forum compliant solution
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
33.4 Licenses
33.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I
2C-bus — logo is a trademark of NXP B.V.
MIFARE — is a trademark of NXP B.V.
34. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Purchase of NXP ICs with ISO/IEC 14443 type B functionality
This NXP Semiconductors IC is ISO/IEC 14443 Type B
software enabled and is licensed under Innovatron’s
Contactless Card patents license for ISO/IEC 14443 B.
The license includes the right to use the IC in systems
and/or end-user equipment.
RATP/Innovatron
Technology
Purchase of NXP ICs with NFC technology
Purchase of an NXP Semiconductors IC that complies with one of the Near
Field Communication (NFC) standards ISO/IEC 18092 and ISO/IEC 21481
does not convey an implied license under any patent right infringed by
implementation of any of those standards.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 4.5 — 17 December 2013
111345 130 of 136
NXP Semiconductors PN512
Full NFC Forum compliant solution
35. Tables
Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .4
Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .5
Table 3. Pin description HVQFN32 . . . . . . . . . . . . . . . .10
Table 4. Pin description HVQFN40 . . . . . . . . . . . . . . . . 11
Table 5. Pin description TFBGA64 . . . . . . . . . . . . . . . . .12
Table 6. Communication overview for
ISO/IEC 14443 A/MIFARE reader/writer . . . . .14
Table 7. Communication overview for FeliCa
reader/writer . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 8. FeliCa framing and coding . . . . . . . . . . . . . . . .16
Table 9. Start value for the CRC Polynomial: (00h),
(00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 10. Communication overview for Active
communication mode . . . . . . . . . . . . . . . . . . . .18
Table 11. Communication overview for Passive
communication mode . . . . . . . . . . . . . . . . . . . .19
Table 12. Framing and coding overview. . . . . . . . . . . . . .20
Table 13. MIFARE Card operation mode . . . . . . . . . . . . .20
Table 14. FeliCa Card operation mode . . . . . . . . . . . . . .21
Table 15. PN512 registers overview . . . . . . . . . . . . . . . .21
Table 16. Behavior of register bits and its designation. . .23
Table 17. PageReg register (address 00h); reset value:
00h, 0000000b . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 18. Description of PageReg bits . . . . . . . . . . . . . . .24
Table 19. CommandReg register (address 01h); reset
value: 20h, 00100000b . . . . . . . . . . . . . . . . . . .24
Table 20. Description of CommandReg bits. . . . . . . . . . .24
Table 21. CommIEnReg register (address 02h); reset
value: 80h, 10000000b . . . . . . . . . . . . . . . . . . .25
Table 22. Description of CommIEnReg bits . . . . . . . . . . .25
Table 23. DivIEnReg register (address 03h); reset value:
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .26
Table 24. Description of DivIEnReg bits. . . . . . . . . . . . . .26
Table 25. CommIRqReg register (address 04h); reset
value: 14h, 00010100b . . . . . . . . . . . . . . . . . . .27
Table 26. Description of CommIRqReg bits . . . . . . . . . . .27
Table 27. DivIRqReg register (address 05h); reset
value: XXh, 000X00XXb . . . . . . . . . . . . . . . . . .28
Table 28. Description of DivIRqReg bits . . . . . . . . . . . . .28
Table 29. ErrorReg register (address 06h); reset value:
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .29
Table 30. Description of ErrorReg bits . . . . . . . . . . . . . . .29
Table 31. Status1Reg register (address 07h); reset
value: XXh, X100X01Xb . . . . . . . . . . . . . . . . . .30
Table 32. Description of Status1Reg bits . . . . . . . . . . . . .30
Table 33. Status2Reg register (address 08h); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .31
Table 34. Description of Status2Reg bits . . . . . . . . . . . . .31
Table 35. FIFODataReg register (address 09h); reset
value: XXh, XXXXXXXXb . . . . . . . . . . . . . . . . .32
Table 36. Description of FIFODataReg bits . . . . . . . . . . .32
Table 37. FIFOLevelReg register (address 0Ah); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .32
Table 38. Description of FIFOLevelReg bits. . . . . . . . . . .32
Table 39. WaterLevelReg register (address 0Bh); reset
value: 08h, 00001000b . . . . . . . . . . . . . . . . . . .33
Table 40. Description of WaterLevelReg bits. . . . . . . . . . 33
Table 41. ControlReg register (address 0Ch); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 33
Table 42. Description of ControlReg bits . . . . . . . . . . . . 33
Table 43. BitFramingReg register (address 0Dh); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 34
Table 44. Description of BitFramingReg bits . . . . . . . . . . 34
Table 45. CollReg register (address 0Eh); reset
value: XXh, 101XXXXXb . . . . . . . . . . . . . . . . . 35
Table 46. Description of CollReg bits. . . . . . . . . . . . . . . . 35
Table 47. PageReg register (address 10h); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 36
Table 48. Description of PageReg bits . . . . . . . . . . . . . . 36
Table 49. ModeReg register (address 11h); reset value:
3Bh, 00111011b . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 50. Description of ModeReg bits . . . . . . . . . . . . . . 37
Table 51. TxModeReg register (address 12h); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 38
Table 52. Description of TxModeReg bits . . . . . . . . . . . . 38
Table 53. RxModeReg register (address 13h); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 39
Table 54. Description of RxModeReg bits . . . . . . . . . . . . 39
Table 55. TxControlReg register (address 14h); reset
value: 80h, 10000000b . . . . . . . . . . . . . . . . . . 40
Table 56. Description of TxControlReg bits . . . . . . . . . . . 40
Table 57. TxAutoReg register (address 15h); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 41
Table 58. Description of TxAutoReg bits . . . . . . . . . . . . . 41
Table 59. TxSelReg register (address 16h); reset value:
10h, 00010000b. . . . . . . . . . . . . . . . . . . . . . . . 42
Table 60. Description of TxSelReg bits . . . . . . . . . . . . . . 42
Table 61. RxSelReg register (address 17h); reset value:
84h, 10000100b. . . . . . . . . . . . . . . . . . . . . . . . 44
Table 62. Description of RxSelReg bits . . . . . . . . . . . . . . 44
Table 63. RxThresholdReg register (address 18h);
reset value: 84h, 10000100b . . . . . . . . . . . . . . 44
Table 64. Description of RxThresholdReg bits . . . . . . . . 44
Table 65. DemodReg register (address 19h); reset
value: 4Dh, 01001101b . . . . . . . . . . . . . . . . . . 45
Table 66. Description of DemodReg bits . . . . . . . . . . . . . 45
Table 67. FelNFC1Reg register (address 1Ah); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 46
Table 68. Description of FelNFC1Reg bits . . . . . . . . . . . 46
Table 69. FelNFC2Reg register (address1Bh); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 47
Table 70. Description of FelNFC2Reg bits . . . . . . . . . . . 47
Table 71. MifNFCReg register (address 1Ch); reset
value: 62h, 01100010b. . . . . . . . . . . . . . . . . . . 48
Table 72. Description of MifNFCReg bits. . . . . . . . . . . . . 48
Table 73. ManualRCVReg register (address 1Dh);
reset value: 00h, 00000000b . . . . . . . . . . . . . . 49
Table 74. Description of ManualRCVReg bits . . . . . . . . . 49
Table 75. TypeBReg register (address 1Eh); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 50
Table 76. Description of TypeBReg bits. . . . . . . . . . . . . . 50
Table 77. SerialSpeedReg register (address 1Fh); PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 4.5 — 17 December 2013
111345 131 of 136
NXP Semiconductors PN512
Full NFC Forum compliant solution
reset value: EBh, 11101011b . . . . . . . . . . . . . .51
Table 78. Description of SerialSpeedReg bits . . . . . . . . .51
Table 79. PageReg register (address 20h); reset value:
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .52
Table 80. Description of PageReg bits . . . . . . . . . . . . . . .52
Table 81. CRCResultReg register (address 21h); reset
value: FFh, 11111111b. . . . . . . . . . . . . . . . . . . .52
Table 82. Description of CRCResultReg bits . . . . . . . . . .52
Table 83. CRCResultReg register (address 22h); reset
value: FFh, 11111111b. . . . . . . . . . . . . . . . . . . .52
Table 84. Description of CRCResultReg bits . . . . . . . . . .52
Table 85. GsNOffReg register (address 23h); reset
value: 88h, 10001000b . . . . . . . . . . . . . . . . . . .53
Table 86. Description of GsNOffReg bits . . . . . . . . . . . . .53
Table 87. ModWidthReg register (address 24h); reset
value: 26h, 00100110b . . . . . . . . . . . . . . . . . . .54
Table 88. Description of ModWidthReg bits . . . . . . . . . . .54
Table 89. TxBitPhaseReg register (address 25h); reset
value: 87h, 10000111b . . . . . . . . . . . . . . . . . . .54
Table 90. Description of TxBitPhaseReg bits . . . . . . . . . .54
Table 91. RFCfgReg register (address 26h); reset
value: 48h, 01001000b . . . . . . . . . . . . . . . . . . .55
Table 92. Description of RFCfgReg bits . . . . . . . . . . . . .55
Table 93. GsNOnReg register (address 27h); reset
value: 88h, 10001000b . . . . . . . . . . . . . . . . . . .56
Table 94. Description of GsNOnReg bits . . . . . . . . . . . . .56
Table 95. CWGsPReg register (address 28h); reset
value: 20h, 00100000b . . . . . . . . . . . . . . . . . . .56
Table 96. Description of CWGsPReg bits. . . . . . . . . . . . .56
Table 97. ModGsPReg register (address 29h); reset
value: 20h, 00100000b . . . . . . . . . . . . . . . . . . .57
Table 98. Description of ModGsPReg bits . . . . . . . . . . . .57
Table 99. TModeReg register (address 2Ah); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .57
Table 100. Description of TModeReg bits . . . . . . . . . . . . .57
Table 101. TPrescalerReg register (address 2Bh); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .58
Table 102. Description of TPrescalerReg bits . . . . . . . . . .58
Table 103. TReloadReg (Higher bits) register (address
2Ch); reset value: 00h, 00000000b . . . . . . . . .59
Table 104. Description of the higher TReloadReg bits . . .59
Table 105. TReloadReg (Lower bits) register (address
2Dh); reset value: 00h, 00000000b . . . . . . . . .59
Table 106. Description of lower TReloadReg bits . . . . . . .59
Table 107. TCounterValReg (Higher bits) register (address
2Eh); reset value: XXh, XXXXXXXXb . . . . . . .60
Table 108. Description of the higher TCounterValReg bits 60
Table 109. TCounterValReg (Lower bits) register (address
2Fh); reset value: XXh, XXXXXXXXb. . . . . . . .60
Table 110. Description of lower TCounterValReg bits . . . .60
Table 111. PageReg register (address 30h); reset value:
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .60
Table 112. Description of PageReg bits. . . . . . . . . . . . . . .61
Table 113. TestSel1Reg register (address 31h); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .62
Table 114. Description of TestSel1Reg bits . . . . . . . . . . . .62
Table 115. TestSel2Reg register (address 32h); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .62
Table 116. Description of TestSel2Reg bits. . . . . . . . . . . . 62
Table 117. TestPinEnReg register (address 33h); reset
value: 80h, 10000000b . . . . . . . . . . . . . . . . . . 63
Table 118. Description of TestPinEnReg bits . . . . . . . . . . 63
Table 119. TestPinValueReg register (address 34h); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 63
Table 120. Description of TestPinValueReg bits . . . . . . . . 63
Table 121. TestBusReg register (address 35h); reset
value: XXh, XXXXXXXXb . . . . . . . . . . . . . . . . 64
Table 122. Description of TestBusReg bits . . . . . . . . . . . . 64
Table 123. AutoTestReg register (address 36h); reset
value: 40h, 01000000b . . . . . . . . . . . . . . . . . . 64
Table 124. Description of bits . . . . . . . . . . . . . . . . . . . . . . 64
Table 125. VersionReg register (address 37h); reset
value: XXh, XXXXXXXXb . . . . . . . . . . . . . . . . 65
Table 126. Description of VersionReg bits . . . . . . . . . . . . 65
Table 127. AnalogTestReg register (address 38h); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 66
Table 128. Description of AnalogTestReg bits . . . . . . . . . 66
Table 129. TestDAC1Reg register (address 39h); reset
value: XXh, 00XXXXXXb . . . . . . . . . . . . . . . . . 67
Table 130. Description of TestDAC1Reg bits . . . . . . . . . . 67
Table 131. TestDAC2Reg register (address 3Ah); reset
value: XXh, 00XXXXXXb . . . . . . . . . . . . . . . . . 67
Table 132. Description ofTestDAC2Reg bits. . . . . . . . . . . 67
Table 133. TestADCReg register (address 3Bh); reset
value: XXh, XXXXXXXXb . . . . . . . . . . . . . . . . 67
Table 134. Description of TestADCReg bits . . . . . . . . . . . 67
Table 135. RFTReg register (address 3Ch); reset value:
FFh, 11111111b . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 136. Description of RFTReg bits . . . . . . . . . . . . . . . 68
Table 137. RFTReg register (address 3Dh, 3Fh); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 68
Table 138. Description of RFTReg bits . . . . . . . . . . . . . . . 68
Table 139. RFTReg register (address 3Eh); reset value:
03h, 00000011b . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 140. Description of RFTReg bits . . . . . . . . . . . . . . . 68
Table 141. Connection protocol for detecting different
interface types . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 142. Connection scheme for detecting the different
interface types . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 143. MOSI and MISO byte order . . . . . . . . . . . . . . 70
Table 144. MOSI and MISO byte order . . . . . . . . . . . . . . 71
Table 145. Address byte 0 register; address MOSI . . . . . 71
Table 146. BR_T0 and BR_T1 settings . . . . . . . . . . . . . . 72
Table 147. Selectable UART transfer speeds . . . . . . . . . 72
Table 148. UART framing . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 149. Read data byte order . . . . . . . . . . . . . . . . . . . 73
Table 150. Write data byte order . . . . . . . . . . . . . . . . . . . 73
Table 151. Address byte 0 register; address MOSI . . . . . 75
Table 152. Supported interface types . . . . . . . . . . . . . . . . 82
Table 153. Register and bit settings controlling the
signal on pin TX1 . . . . . . . . . . . . . . . . . . . . . . 84
Table 154. Register and bit settings controlling the
signal on pin TX2 . . . . . . . . . . . . . . . . . . . . . . 85
Table 155. Setting of the bits RFlevel in register
RFCfgReg (RFLevel amplifier deactivated) . . . 86
Table 156. CRC coprocessor parameters . . . . . . . . . . . . 93PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 4.5 — 17 December 2013
111345 132 of 136
NXP Semiconductors PN512
Full NFC Forum compliant solution
Table 157. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . .95
Table 158. Command overview . . . . . . . . . . . . . . . . . . .101
Table 159. Testsignal routing (TestSel2Reg = 07h) . . . . .107
Table 160. Description of Testsignals . . . . . . . . . . . . . . .107
Table 161. Testsignal routing (TestSel2Reg = 0Dh) . . . .108
Table 162. Description of Testsignals . . . . . . . . . . . . . . .108
Table 163. Testsignal routing (TestSel2Reg = 19h) . . . . .108
Table 164. Description of Testsignals . . . . . . . . . . . . . . .108
Table 165. Testsignals description. . . . . . . . . . . . . . . . . .108
Table 166. Limiting values . . . . . . . . . . . . . . . . . . . . . . . 111
Table 167. Operating conditions . . . . . . . . . . . . . . . . . . . 111
Table 168. Thermal characteristics . . . . . . . . . . . . . . . . . 112
Table 169. Characteristics . . . . . . . . . . . . . . . . . . . . . . . 112
Table 170. SPI timing characteristics . . . . . . . . . . . . . . . 117
Table 171. I2C-bus timing in Fast mode . . . . . . . . . . . . . 117
Table 172. AC symbols . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 173. Timing specification for separated
Read/Write strobe. . . . . . . . . . . . . . . . . . . . . . 119
Table 174. Timing specification for common
Read/Write strobe. . . . . . . . . . . . . . . . . . . . . .120
Table 175. Package information . . . . . . . . . . . . . . . . . . .122
Table 176. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . .126
Table 177. Revision history . . . . . . . . . . . . . . . . . . . . . . .127PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 4.5 — 17 December 2013
111345 133 of 136
NXP Semiconductors PN512
Full NFC Forum compliant solution
36. Figures
Fig 1. Simplified block diagram of the PN512 . . . . . . . . .6
Fig 2. Detailed block diagram of the PN512 . . . . . . . . . .7
Fig 3. Pinning configuration HVQFN32 (SOT617-1) . . . .8
Fig 4. Pinning configuration HVQFN40 (SOT618-1) . . . .8
Fig 5. Pin configuration TFBGA64 (SOT1336-1) . . . . . . .9
Fig 6. PN512 Read/Write mode. . . . . . . . . . . . . . . . . . .14
Fig 7. ISO/IEC 14443 A/MIFARE Read/Write mode
communication diagram. . . . . . . . . . . . . . . . . . . .14
Fig 8. Data coding and framing according to
ISO/IEC 14443 A . . . . . . . . . . . . . . . . . . . . . . . . .15
Fig 9. FeliCa reader/writer communication diagram . . .16
Fig 10. NFCIP-1 mode. . . . . . . . . . . . . . . . . . . . . . . . . . .17
Fig 11. Active communication mode . . . . . . . . . . . . . . . .18
Fig 12. Passive communication mode . . . . . . . . . . . . . . .19
Fig 13. SPI connection to host. . . . . . . . . . . . . . . . . . . . .70
Fig 14. UART connection to microcontrollers . . . . . . . . .71
Fig 15. UART read data timing diagram . . . . . . . . . . . . .73
Fig 16. UART write data timing diagram . . . . . . . . . . . . .74
Fig 17. I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . . .75
Fig 18. Bit transfer on the I2C-bus . . . . . . . . . . . . . . . . . .76
Fig 19. START and STOP conditions . . . . . . . . . . . . . . .76
Fig 20. Acknowledge on the I2C-bus . . . . . . . . . . . . . . . .77
Fig 21. Data transfer on the I2C-bus . . . . . . . . . . . . . . . .77
Fig 22. First byte following the START procedure . . . . . .78
Fig 23. Register read and write access . . . . . . . . . . . . . .79
Fig 24. I2C-bus HS mode protocol switch . . . . . . . . . . . .80
Fig 25. I2C-bus HS mode protocol frame. . . . . . . . . . . . .81
Fig 26. Connection to host controller with separated
Read/Write strobes . . . . . . . . . . . . . . . . . . . . . . .83
Fig 27. Connection to host controller with common
Read/Write strobes . . . . . . . . . . . . . . . . . . . . . . .83
Fig 28. Data mode detector . . . . . . . . . . . . . . . . . . . . . . .87
Fig 29. Serial data switch for TX1 and TX2 . . . . . . . . . . .88
Fig 30. Communication flows using the S2C interface. . .89
Fig 31. Signal shape for SIGOUT in FeliCa card SAM
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Fig 32. Signal shape for SIGIN in SAM mode . . . . . . . . .90
Fig 33. Signal shape for SIGOUT in MIFARE Card SAM
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Fig 34. Signal shape for SIGIN in MIFARE Card SAM
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Fig 35. Quartz crystal connection . . . . . . . . . . . . . . . . . .99
Fig 36. Oscillator start-up time. . . . . . . . . . . . . . . . . . . .100
Fig 37. Autocoll Command . . . . . . . . . . . . . . . . . . . . . .104
Fig 38. Typical circuit diagram . . . . . . . . . . . . . . . . . . . . 110
Fig 39. Pin RX input voltage range . . . . . . . . . . . . . . . . 116
Fig 40. Timing diagram for SPI . . . . . . . . . . . . . . . . . . . 118
Fig 41. Timing for Fast and Standard mode devices
on the I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Fig 42. Timing diagram for separated Read/Write
strobe. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
Fig 43. Timing diagram for common Read/Write strobe 121
Fig 44. Package outline package version (HVQFN32) .123
Fig 45. Package outline package version (HVQFN40) .124
Fig 46. Package outline package version (TFBGA64). .125PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 4.5 — 17 December 2013
111345 134 of 136
continued >>
NXP Semiconductors PN512
Full NFC Forum compliant solution
37. Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Different available versions. . . . . . . . . . . . . . . . 1
2 General description . . . . . . . . . . . . . . . . . . . . . . 1
3 Features and benefits . . . . . . . . . . . . . . . . . . . . 3
4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 4
5 Ordering information. . . . . . . . . . . . . . . . . . . . . 5
6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6
7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 8
7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10
8 Functional description . . . . . . . . . . . . . . . . . . 14
8.1 ISO/IEC 14443 A/MIFARE functionality . . . . . 14
8.2 ISO/IEC 14443 B functionality . . . . . . . . . . . . 15
8.3 FeliCa reader/writer functionality . . . . . . . . . . 16
8.3.1 FeliCa framing and coding . . . . . . . . . . . . . . . 16
8.4 NFCIP-1 mode . . . . . . . . . . . . . . . . . . . . . . . . 17
8.4.1 Active communication mode . . . . . . . . . . . . . 18
8.4.2 Passive communication mode . . . . . . . . . . . . 19
8.4.3 NFCIP-1 framing and coding . . . . . . . . . . . . . 20
8.4.4 NFCIP-1 protocol support. . . . . . . . . . . . . . . . 20
8.4.5 MIFARE Card operation mode . . . . . . . . . . . . 20
8.4.6 FeliCa Card operation mode . . . . . . . . . . . . . 21
9 PN512 register SET . . . . . . . . . . . . . . . . . . . . . 21
9.1 PN512 registers overview. . . . . . . . . . . . . . . . 21
9.1.1 Register bit behavior. . . . . . . . . . . . . . . . . . . . 23
9.2 Register description . . . . . . . . . . . . . . . . . . . . 24
9.2.1 Page 0: Command and status . . . . . . . . . . . . 24
9.2.1.1 PageReg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.2.1.2 CommandReg . . . . . . . . . . . . . . . . . . . . . . . . 24
9.2.1.3 CommIEnReg . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.2.1.4 DivIEnReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9.2.1.5 CommIRqReg. . . . . . . . . . . . . . . . . . . . . . . . . 27
9.2.1.6 DivIRqReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.2.1.7 ErrorReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9.2.1.8 Status1Reg . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.2.1.9 Status2Reg . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.2.1.10 FIFODataReg . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.2.1.11 FIFOLevelReg . . . . . . . . . . . . . . . . . . . . . . . . 32
9.2.1.12 WaterLevelReg. . . . . . . . . . . . . . . . . . . . . . . . 33
9.2.1.13 ControlReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.2.1.14 BitFramingReg . . . . . . . . . . . . . . . . . . . . . . . . 34
9.2.1.15 CollReg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.2.2 Page 1: Communication . . . . . . . . . . . . . . . . . 36
9.2.2.1 PageReg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.2.2.2 ModeReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.2.2.3 TxModeReg . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.2.2.4 RxModeReg . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.2.2.5 TxControlReg. . . . . . . . . . . . . . . . . . . . . . . . . 40
9.2.2.6 TxAutoReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.2.2.7 TxSelReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.2.2.8 RxSelReg. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.2.2.9 RxThresholdReg . . . . . . . . . . . . . . . . . . . . . . 44
9.2.2.10 DemodReg. . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.2.2.11 FelNFC1Reg . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.2.2.12 FelNFC2Reg . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.2.2.13 MifNFCReg . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.2.2.14 ManualRCVReg . . . . . . . . . . . . . . . . . . . . . . . 49
9.2.2.15 TypeBReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.2.2.16 SerialSpeedReg. . . . . . . . . . . . . . . . . . . . . . . 50
9.2.3 Page 2: Configuration . . . . . . . . . . . . . . . . . . 52
9.2.3.1 PageReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.2.3.2 CRCResultReg . . . . . . . . . . . . . . . . . . . . . . . 52
9.2.3.3 GsNOffReg . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.2.3.4 ModWidthReg . . . . . . . . . . . . . . . . . . . . . . . . 54
9.2.3.5 TxBitPhaseReg . . . . . . . . . . . . . . . . . . . . . . . 54
9.2.3.6 RFCfgReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.2.3.7 GsNOnReg . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.2.3.8 CWGsPReg . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.2.3.9 ModGsPReg . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.2.3.10 TMode Register, TPrescaler Register . . . . . . 57
9.2.3.11 TReloadReg. . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.2.3.12 TCounterValReg . . . . . . . . . . . . . . . . . . . . . . 60
9.2.4 Page 3: Test . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.2.4.1 PageReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.2.4.2 TestSel1Reg. . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.2.4.3 TestSel2Reg. . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.2.4.4 TestPinEnReg . . . . . . . . . . . . . . . . . . . . . . . . 63
9.2.4.5 TestPinValueReg . . . . . . . . . . . . . . . . . . . . . . 63
9.2.4.6 TestBusReg . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.2.4.7 AutoTestReg . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.2.4.8 VersionReg . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.2.4.9 AnalogTestReg. . . . . . . . . . . . . . . . . . . . . . . . 66
9.2.4.10 TestDAC1Reg . . . . . . . . . . . . . . . . . . . . . . . . 67
9.2.4.11 TestDAC2Reg . . . . . . . . . . . . . . . . . . . . . . . . 67
9.2.4.12 TestADCReg . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.2.4.13 RFTReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . 68
10.1 Automatic microcontroller interface detection 68
10.2 Serial Peripheral Interface . . . . . . . . . . . . . . . 70
10.2.1 SPI read data . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.2.2 SPI write data. . . . . . . . . . . . . . . . . . . . . . . . . 70
10.2.3 SPI address byte . . . . . . . . . . . . . . . . . . . . . . 71
10.3 UART interface . . . . . . . . . . . . . . . . . . . . . . . 71
10.3.1 Connection to a host . . . . . . . . . . . . . . . . . . . 71PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 4.5 — 17 December 2013
111345 135 of 136
continued >>
NXP Semiconductors PN512
Full NFC Forum compliant solution
10.3.2 Selectable UART transfer speeds . . . . . . . . . 71
10.3.3 UART framing. . . . . . . . . . . . . . . . . . . . . . . . . 72
10.4 I2C Bus Interface . . . . . . . . . . . . . . . . . . . . . . 75
10.4.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10.4.2 START and STOP conditions . . . . . . . . . . . . . 76
10.4.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10.4.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 77
10.4.5 7-Bit addressing . . . . . . . . . . . . . . . . . . . . . . . 78
10.4.6 Register write access . . . . . . . . . . . . . . . . . . . 78
10.4.7 Register read access . . . . . . . . . . . . . . . . . . . 79
10.4.8 High-speed mode . . . . . . . . . . . . . . . . . . . . . . 80
10.4.9 High-speed transfer . . . . . . . . . . . . . . . . . . . . 80
10.4.10 Serial data transfer format in HS mode . . . . . 80
10.4.11 Switching between F/S mode and HS mode . 82
10.4.12 PN512 at lower speed modes . . . . . . . . . . . . 82
11 8-bit parallel interface . . . . . . . . . . . . . . . . . . . 82
11.1 Overview of supported host controller
interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.2 Separated Read/Write strobe . . . . . . . . . . . . . 83
11.3 Common Read/Write strobe . . . . . . . . . . . . . . 83
12 Analog interface and contactless UART . . . . 84
12.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
12.2 TX driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
12.3 RF level detector . . . . . . . . . . . . . . . . . . . . . . 85
12.4 Data mode detector . . . . . . . . . . . . . . . . . . . . 86
12.5 Serial data switch . . . . . . . . . . . . . . . . . . . . . . 88
12.6 S2C interface support . . . . . . . . . . . . . . . . . . . 88
12.6.1 Signal shape for Felica S2C interface support 90
12.6.2 Waveform shape for ISO/IEC 14443A and
MIFARE S2C support . . . . . . . . . . . . . . . . . . . 91
12.7 Hardware support for FeliCa and NFC polling 92
12.7.1 Polling sequence functionality for initiator. . . . 92
12.7.2 Polling sequence functionality for target. . . . . 92
12.7.3 Additional hardware support for FeliCa and
NFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.7.4 CRC coprocessor . . . . . . . . . . . . . . . . . . . . . . 93
13 FIFO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
13.1 Accessing the FIFO buffer . . . . . . . . . . . . . . . 94
13.2 Controlling the FIFO buffer . . . . . . . . . . . . . . . 94
13.3 FIFO buffer status information . . . . . . . . . . . . 94
14 Interrupt request system. . . . . . . . . . . . . . . . . 95
14.1 Interrupt sources overview . . . . . . . . . . . . . . . 95
15 Timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
16 Power reduction modes . . . . . . . . . . . . . . . . . 98
16.1 Hard power-down . . . . . . . . . . . . . . . . . . . . . . 98
16.2 Soft power-down mode. . . . . . . . . . . . . . . . . . 98
16.3 Transmitter power-down mode . . . . . . . . . . . . 98
17 Oscillator circuitry . . . . . . . . . . . . . . . . . . . . . . 99
18 Reset and oscillator start-up time . . . . . . . . . 99
18.1 Reset timing requirements . . . . . . . . . . . . . . . 99
18.2 Oscillator start-up time . . . . . . . . . . . . . . . . . . 99
19 PN512 command set . . . . . . . . . . . . . . . . . . . 100
19.1 General description . . . . . . . . . . . . . . . . . . . 100
19.2 General behavior . . . . . . . . . . . . . . . . . . . . . 100
19.3 PN512 command overview . . . . . . . . . . . . . 101
19.3.1 PN512 command descriptions . . . . . . . . . . . 101
19.3.1.1 Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
19.3.1.2 Config command . . . . . . . . . . . . . . . . . . . . . 101
19.3.1.3 Generate RandomID . . . . . . . . . . . . . . . . . . 102
19.3.1.4 CalcCRC . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
19.3.1.5 Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
19.3.1.6 NoCmdChange . . . . . . . . . . . . . . . . . . . . . . 102
19.3.1.7 Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
19.3.1.8 Transceive . . . . . . . . . . . . . . . . . . . . . . . . . . 103
19.3.1.9 AutoColl . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
19.3.1.10 MFAuthent . . . . . . . . . . . . . . . . . . . . . . . . . . 105
19.3.1.11 SoftReset . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
20 Testsignals. . . . . . . . . . . . . . . . . . . . . . . . . . . 107
20.1 Selftest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
20.2 Testbus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
20.3 Testsignals at pin AUX . . . . . . . . . . . . . . . . . 108
20.4 PRBS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
21 Errata sheet . . . . . . . . . . . . . . . . . . . . . . . . . . 109
22 Application design-in information. . . . . . . . . 110
23 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 111
24 Recommended operating conditions . . . . . . 111
25 Thermal characteristics . . . . . . . . . . . . . . . . . 112
26 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 112
26.1 Timing characteristics . . . . . . . . . . . . . . . . . . 117
26.2 8-bit parallel interface timing . . . . . . . . . . . . . 119
26.2.1 AC symbols . . . . . . . . . . . . . . . . . . . . . . . . . . 119
26.2.2 AC operating specification . . . . . . . . . . . . . . . 119
26.2.2.1 Bus timing for separated Read/Write strobe . 119
26.2.2.2 Bus timing for common Read/Write strobe . 120
27 Package information. . . . . . . . . . . . . . . . . . . 122
28 Package outline. . . . . . . . . . . . . . . . . . . . . . . 123
29 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 126
30 Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
31 References. . . . . . . . . . . . . . . . . . . . . . . . . . . 126
32 Revision history . . . . . . . . . . . . . . . . . . . . . . 127
33 Legal information . . . . . . . . . . . . . . . . . . . . . 128
33.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . 128
33.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 128
33.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . 128
33.4 Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
33.5 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 129NXP Semiconductors PN512
Full NFC Forum compliant solution
© NXP B.V. 2013. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 17 December 2013
111345
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
34 Contact information. . . . . . . . . . . . . . . . . . . . 129
35 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
36 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
37 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
1. Product profile
1.1 General description
Unidirectional double ElectroStatic Discharge (ESD) protection diodes in a common
cathode configuration, encapsulated in a SOT23 (TO-236AB) small Surface-Mounted
Device (SMD) plastic package. The devices are designed for ESD and transient
overvoltage protection of up to two signal lines.
[1] All types available as /DG halogen-free version.
1.2 Features
1.3 Applications
MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage
suppression
Rev. 01 — 3 September 2008 Product data sheet
Table 1. Product overview
Type number[1] Package Configuration
NXP JEDEC
MMBZ12VDL SOT23 TO-236AB dual common cathode
MMBZ15VDL
MMBZ18VCL
MMBZ20VCL
MMBZ27VCL
MMBZ33VCL
■ Unidirectional ESD protection of
two lines
■ ESD protection up to 30 kV (contact
discharge)
■ Bidirectional ESD protection of one line ■ IEC 61000-4-2; level 4 (ESD)
■ Low diode capacitance: Cd ≤ 140 pF ■ IEC 61643-321
■ Rated peak pulse power: PPPM ≤ 40 W ■ AEC-Q101 qualified
■ Ultra low leakage current: IRM ≤ 5 nA
■ Computers and peripherals ■ Automotive electronic control units
■ Audio and video equipment ■ Portable electronics
■ Cellular handsets and accessoriesMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 3 September 2008 2 of 15
NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
1.4 Quick reference data
2. Pinning information
Table 2. Quick reference data
Tamb = 25 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Per diode
VRWM reverse standoff voltage
MMBZ12VDL
MMBZ12VDL/DG
- - 8.5 V
MMBZ15VDL
MMBZ15VDL/DG
- - 12.8 V
MMBZ18VCL
MMBZ18VCL/DG
- - 14.5 V
MMBZ20VCL
MMBZ20VCL/DG
- - 17 V
MMBZ27VCL
MMBZ27VCL/DG
- - 22 V
MMBZ33VCL
MMBZ33VCL/DG
- - 26 V
Cd diode capacitance f = 1 MHz; VR =0V
MMBZ12VDL
MMBZ12VDL/DG
- 110 140 pF
MMBZ15VDL
MMBZ15VDL/DG
- 85 105 pF
MMBZ18VCL
MMBZ18VCL/DG
- 70 90 pF
MMBZ20VCL
MMBZ20VCL/DG
- 65 80 pF
MMBZ27VCL
MMBZ27VCL/DG
- 48 60 pF
MMBZ33VCL
MMBZ33VCL/DG
- 45 55 pF
Table 3. Pinning
Pin Description Simplified outline Graphic symbol
1 anode (diode 1)
2 anode (diode 2)
3 common cathode
1 2
3
006aaa150
1 2
3MMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 3 September 2008 3 of 15
NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
3. Ordering information
4. Marking
[1] * = -: made in Hong Kong
* = p: made in Hong Kong
* = t: made in Malaysia
* = W: made in China
Table 4. Ordering information
Type number Package
Name Description Version
MMBZ12VDL - plastic surface-mounted package; 3 leads SOT23
MMBZ15VDL
MMBZ18VCL
MMBZ20VCL
MMBZ27VCL
MMBZ33VCL
MMBZ12VDL/DG - plastic surface-mounted package; 3 leads SOT23
MMBZ15VDL/DG
MMBZ18VCL/DG
MMBZ20VCL/DG
MMBZ27VCL/DG
MMBZ33VCL/DG
Table 5. Marking codes
Type number Marking code[1] Type number Marking code[1]
MMBZ12VDL *MA MMBZ12VDL/DG TJ*
MMBZ15VDL *MB MMBZ15VDL/DG TL*
MMBZ18VCL *MC MMBZ18VCL/DG TN*
MMBZ20VCL *MD MMBZ20VCL/DG TQ*
MMBZ27VCL *ME MMBZ27VCL/DG TS*
MMBZ33VCL *MF MMBZ33VCL/DG TU*MMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 3 September 2008 4 of 15
NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
5. Limiting values
[1] In accordance with IEC 61643-321 (10/1000 µs current waveform).
[2] Measured from pin 1 or 2 to pin 3.
[3] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard
footprint.
[4] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for cathode 1 cm2.
[1] Device stressed with ten non-repetitive ESD pulses.
[2] Measured from pin 1 or 2 to pin 3.
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Per diode
PPPM rated peak pulse power tp = 10/1000 µs [1][2] - 40 W
IPPM rated peak pulse current tp = 10/1000 µs [1][2]
MMBZ12VDL
MMBZ12VDL/DG
- 2.35 A
MMBZ15VDL
MMBZ15VDL/DG
- 1.9 A
MMBZ18VCL
MMBZ18VCL/DG
- 1.6 A
MMBZ20VCL
MMBZ20VCL/DG
- 1.4 A
MMBZ27VCL
MMBZ27VCL/DG
- 1A
MMBZ33VCL
MMBZ33VCL/DG
- 0.87 A
Per device
Ptot total power dissipation Tamb ≤ 25 °C [3] - 350 mW
[4] - 440 mW
Tj junction temperature - 150 °C
Tamb ambient temperature −55 +150 °C
Tstg storage temperature −65 +150 °C
Table 7. ESD maximum ratings
Tamb = 25 °C unless otherwise specified.
Symbol Parameter Conditions Min Max Unit
Per diode
VESD electrostatic discharge voltage [1][2]
IEC 61000-4-2
(contact discharge)
- 30 kV
machine model - 2 kVMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 3 September 2008 5 of 15
NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
6. Thermal characteristics
[1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[2] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for cathode 1 cm2.
[3] Soldering point at pin 3.
Table 8. ESD standards compliance
Standard Conditions
Per diode
IEC 61000-4-2; level 4 (ESD) > 15 kV (air); > 8 kV (contact)
MIL-STD-883; class 3 (human body model) > 8 kV
Fig 1. 10/1000 µs pulse waveform according to
IEC 61643-321
Fig 2. ESD pulse waveform according to
IEC 61000-4-2
tp (ms)
0 4.0 1.0 2.0 3.0
006aab319
50
100
150
IPP
(%)
0
50 % IPP; 1000 µs
100 % IPP; 10 µs
001aaa631
IPP
100 %
90 %
t
30 ns
60 ns
10 %
tr = 0.7 ns to 1 ns
Table 9. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Per device
Rth(j-a) thermal resistance from junction
to ambient
in free air [1] - - 350 K/W
[2] - - 280 K/W
Rth(j-sp) thermal resistance from junction
to solder point
[3] - - 60 K/WMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 3 September 2008 6 of 15
NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
7. Characteristics
Table 10. Characteristics
Tamb = 25 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Per diode
VF forward voltage
MMBZ12VDL
MMBZ12VDL/DG
IF = 10 mA - - 0.9 V
MMBZ15VDL
MMBZ15VDL/DG
IF = 10 mA - - 0.9 V
MMBZ18VCL
MMBZ18VCL/DG
IF = 10 mA - - 0.9 V
MMBZ20VCL
MMBZ20VCL/DG
IF = 10 mA - - 0.9 V
MMBZ27VCL
MMBZ27VCL/DG
IF = 200 mA - - 1.1 V
MMBZ33VCL
MMBZ33VCL/DG
IF = 10 mA - - 0.9 V
VRWM reverse standoff
voltage
MMBZ12VDL
MMBZ12VDL/DG
- - 8.5 V
MMBZ15VDL
MMBZ15VDL/DG
- - 12.8 V
MMBZ18VCL
MMBZ18VCL/DG
- - 14.5 V
MMBZ20VCL
MMBZ20VCL/DG
- - 17 V
MMBZ27VCL
MMBZ27VCL/DG
- - 22 V
MMBZ33VCL
MMBZ33VCL/DG
- - 26 V
IRM reverse leakage current
MMBZ12VDL
MMBZ12VDL/DG
VRWM = 8.5 V - 0.1 5 nA
MMBZ15VDL
MMBZ15VDL/DG
VRWM = 12.8 V - 0.1 5 nA
MMBZ18VCL
MMBZ18VCL/DG
VRWM = 14.5 V - 0.1 5 nA
MMBZ20VCL
MMBZ20VCL/DG
VRWM = 17 V - 0.1 5 nA
MMBZ27VCL
MMBZ27VCL/DG
VRWM = 22 V - 0.1 5 nA
MMBZ33VCL
MMBZ33VCL/DG
VRWM = 26 V - 0.1 5 nAMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 3 September 2008 7 of 15
NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
VBR breakdown voltage IR = 1 mA
MMBZ12VDL
MMBZ12VDL/DG
11.4 12 12.6 V
MMBZ15VDL
MMBZ15VDL/DG
14.3 15 15.8 V
MMBZ18VCL
MMBZ18VCL/DG
17.1 18 18.9 V
MMBZ20VCL
MMBZ20VCL/DG
19 20 21 V
MMBZ27VCL
MMBZ27VCL/DG
25.65 27 28.35 V
MMBZ33VCL
MMBZ33VCL/DG
31.35 33 34.65 V
Cd diode capacitance f = 1 MHz; VR =0V
MMBZ12VDL
MMBZ12VDL/DG
- 110 140 pF
MMBZ15VDL
MMBZ15VDL/DG
- 85 105 pF
MMBZ18VCL
MMBZ18VCL/DG
- 70 90 pF
MMBZ20VCL
MMBZ20VCL/DG
- 65 80 pF
MMBZ27VCL
MMBZ27VCL/DG
- 48 60 pF
MMBZ33VCL
MMBZ33VCL/DG
- 45 55 pF
VCL clamping voltage [1][2]
MMBZ12VDL
MMBZ12VDL/DG
IPPM = 2.35 A - - 17 V
MMBZ15VDL
MMBZ15VDL/DG
IPPM = 1.9 A - - 21.2 V
MMBZ18VCL
MMBZ18VCL/DG
IPPM = 1.6 A - - 25 V
MMBZ20VCL
MMBZ20VCL/DG
IPPM = 1.4 A - - 28 V
MMBZ27VCL
MMBZ27VCL/DG
IPPM = 1 A - - 38 V
MMBZ33VCL
MMBZ33VCL/DG
IPPM = 0.87 A - - 46 V
Table 10. Characteristics …continued
Tamb = 25 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max UnitMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 3 September 2008 8 of 15
NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
[1] In accordance with IEC 61643-321 (10/1000 µs current waveform).
[2] Measured from pin 1 or 2 to pin 3.
SZ temperature coefficient IZ = 1 mA
MMBZ12VDL
MMBZ12VDL/DG
- 8.1 - mV/K
MMBZ15VDL
MMBZ15VDL/DG
- 11 - mV/K
MMBZ18VCL
MMBZ18VCL/DG
- 14 - mV/K
MMBZ20VCL
MMBZ20VCL/DG
- 15.8 - mV/K
MMBZ27VCL
MMBZ27VCL/DG
- 23 - mV/K
MMBZ33VCL
MMBZ33VCL/DG
- 29.4 - mV/K
Table 10. Characteristics …continued
Tamb = 25 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
MMBZ27VCL: unidirectional and bidirectional
Tamb = 25 °C
Fig 3. Rated peak pulse power as a function of
exponential pulse duration (rectangular
waveform); typical values
Fig 4. Relative variation of rated peak pulse power as
a function of junction temperature; typical
values
006aab327
102
10
103
PPPM
(W)
1
tp (ms)
10−2 103 102 10−1 1 10
Tj
(°C)
0 200 50 100 150
006aab321
0.4
0.8
1.2
PPPM
0
PPPM(25°C)MMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 3 September 2008 9 of 15
NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
f = 1 MHz; Tamb = 25 °C
(1) MMBZ15VDL: unidirectional
(2) MMBZ15VDL: bidirectional
(3) MMBZ27VCL: unidirectional
(4) MMBZ27VCL: bidirectional
MMBZ27VCL: VRWM = 22 V
Fig 5. Diode capacitance as a function of reverse
voltage; typical values
Fig 6. Reverse leakage current as a function of
junction temperature; typical values
Fig 7. V-I characteristics for a unidirectional
ESD protection diode
Fig 8. V-I characteristics for a bidirectional
ESD protection diode
VR (V)
0 25 5 10 15 20
006aab328
40
60
20
80
100
Cd
(pF)
0
(1)
(2)
(3)
(4)
006aab329
10−1
10−2
10
1
102
IRM
(nA)
10−3
Tamb (°C)
−75 175 −25 25 75 125
006aab324
−VCL −VBR −VRWM
−IRM
−IR
−IPP
V
I
P-N
− +
−IPPM 006aab325
−VCL −VBR −VRWM
−IRM VRWM VBR VCL
IRM
−IR
IR
−IPP
IPP
− +
IPPM
−IPPMMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 3 September 2008 10 of 15
NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
8. Application information
The MMBZxVCL series and the MMBZxVDL series are designed for the protection of up
to two unidirectional data or signal lines from the damage caused by ESD and surge
pulses. The devices may be used on lines where the signal polarities are either positive or
negative with respect to ground. The devices provide a surge capability of 40 W per line
for a 10/1000 µs waveform.
Circuit board layout and protection device placement
Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT)
and surge transients. The following guidelines are recommended:
1. Place the devices as close to the input terminal or connector as possible.
2. The path length between the device and the protected line should be minimized.
3. Keep parallel signal paths to a minimum.
4. Avoid running protected conductors in parallel with unprotected conductors.
5. Minimize all Printed-Circuit Board (PCB) conductive loops including power and
ground loops.
6. Minimize the length of the transient return path to ground.
7. Avoid using shared transient return paths to a common ground point.
8. Ground planes should be used whenever possible. For multilayer PCBs, use ground
vias.
9. Test information
9.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is
suitable for use in automotive applications.
Fig 9. Typical application: ESD and transient voltage protection of data lines
006aab330
MMBZxVCL/VDL
line 1 to be protected
unidirectional protection of two lines bidirectional protection of one line
line 2 to be protected
GND
MMBZxVCL/VDL
line 1 to be protected
GNDMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 3 September 2008 11 of 15
NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
10. Package outline
11. Packing information
[1] For further information and the availability of packing methods, see Section 15.
Fig 10. Package outline SOT23 (TO-236AB)
Dimensions in mm 04-11-04
0.45
0.15
1.9
1.1
0.9
3.0
2.8
2.5
2.1
1.4
1.2
0.48
0.38
0.15
0.09
1 2
3
Table 11. Packing methods
The indicated -xxx are the last three digits of the 12NC ordering code.[1]
Type number Package Description Packing quantity
3000 10000
MMBZ12VDL SOT23 4 mm pitch, 8 mm tape and reel -215 -235
MMBZ15VDL
MMBZ18VCL
MMBZ20VCL
MMBZ27VCL
MMBZ33VCL
MMBZ12VDL/DG SOT23 4 mm pitch, 8 mm tape and reel -215 -235
MMBZ15VDL/DG
MMBZ18VCL/DG
MMBZ20VCL/DG
MMBZ27VCL/DG
MMBZ33VCL/DGMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 3 September 2008 12 of 15
NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
12. Soldering
Fig 11. Reflow soldering footprint SOT23 (TO-236AB)
Fig 12. Wave soldering footprint SOT23 (TO-236AB)
solder lands
solder resist
occupied area
solder paste
sot023_fr
0.5
(3×)
0.6
(3×)
0.6
(3×)
0.7
(3×)
3
1
3.3
2.9
1.7
1.9
2
Dimensions in mm
solder lands
solder resist
occupied area
preferred transport direction during soldering
sot023_fw
2.8
4.5
1.4
4.6
1.4
(2×)
1.2
(2×)
2.2
2.6
Dimensions in mmMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 3 September 2008 13 of 15
NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
13. Revision history
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
MMBZXVCL_MMBZXVDL_SER_1 20080903 Product data sheet - -MMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 3 September 2008 14 of 15
NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
14. Legal information
14.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
14.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
ESD protection devices — These products are only intended for protection
against ElectroStatic Discharge (ESD) pulses and are not intended for any
other usage including, without limitation, voltage regulation applications. NXP
Semiconductors accepts no liability for use in such applications and therefore
such use is at the customer’s own risk.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
© NXP B.V. 2008. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 3 September 2008
Document identifier: MMBZXVCL_MMBZXVDL_SER_1
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
16. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description. . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 2
2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3
4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Thermal characteristics. . . . . . . . . . . . . . . . . . . 5
7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 Application information. . . . . . . . . . . . . . . . . . 10
9 Test information . . . . . . . . . . . . . . . . . . . . . . . . 10
9.1 Quality information . . . . . . . . . . . . . . . . . . . . . 10
10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
11 Packing information. . . . . . . . . . . . . . . . . . . . . 11
12 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
13 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
14.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
14.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
14.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15 Contact information. . . . . . . . . . . . . . . . . . . . . 14
16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1. Product profile
1.1 General description
The devices are 4-, 6- and 8-channel RC low-pass filter arrays which are designed to
provide filtering of undesired RF signals on the I/O ports of portable communication or
computing devices. In addition, the devices incorporate diodes to provide protection to
downstream components from ElectroStatic Discharge (ESD) voltages as high as ±30 kV.
The devices are fabricated using monolithic silicon technology and integrate up to eight
resistors and sixteen diodes in a 0.4 mm pitch 8-, 12- or 16-pin ultra-thin leadless Quad
Flat No-leads (QFN) plastic package with a height of 0.55 mm only.
1.2 Features and benefits
Pb-free, Restriction of Hazardous Substances (RoHS) compliant and free of halogen
and antimony (Dark Green compliant)
4-, 6- and 8-channel integrated π-type RC filter network
ESD protection to ±30 kV contact discharge according to IEC 61000-4-2 far exceeding
level 4
QFN plastic package with 0.4 mm pitch and 0.55 mm height
1.3 Applications
General-purpose ElectroMagnetic Interference (EMI) and Radio-Frequency
Interference (RFI) filtering and downstream ESD protection for:
Cellular phone and Personal Communication System (PCS) mobile handsets
Cordless telephones
Wireless data (WAN/LAN) systems
Mobile Internet Devices (MID)
Portable Media Players (PMP)
IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
with ESD protection
Rev. 2 — 5 May 2011 Product data sheetIP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 2 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
1.4 Quick reference data
[1] For the total channel.
2. Pinning information
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
IP4251CZ8-4-TTL; IP4251CZ12-6-TTL; IP4251CZ16-8-TTL
Cch channel capacitance f = 100 kHz;
Vbias(DC) = 2.5 V
[1] - 10 - pF
Rs(ch) channel series resistance 80 100 120 Ω
IP4252CZ8-4-TTL; IP4252CZ12-6-TTL; IP4252CZ16-8-TTL
Cch channel capacitance f = 100 kHz;
Vbias(DC) = 2.5 V
[1] - 12 - pF
Rs(ch) channel series resistance 32 40 48 Ω
IP4253CZ8-4-TTL; IP4253CZ12-6-TTL; IP4253CZ16-8-TTL
Cch channel capacitance f = 100 kHz;
Vbias(DC) = 2.5 V
[1] - 30 - pF
Rs(ch) channel series resistance 160 200 240 Ω
IP4254CZ8-4-TTL; IP4254CZ12-6-TTL; IP4254CZ16-8-TTL
Cch channel capacitance f = 100 kHz;
Vbias(DC) = 2.5 V
[1] - 30 - pF
Rs(ch) channel series resistance 80 100 120 Ω
Table 2. Pinning
Pin Description Simplified outline Graphic symbol
IP4251CZ8-4-TTL; IP4252CZ8-4-TTL; IP4253CZ8-4-TTL; IP4254CZ8-4-TTL (SOT1166-1)
1 and 8 filter channel 1
2 and 7 filter channel 2
3 and 6 filter channel 3
4 and 5 filter channel 4
ground pad ground
IP4251CZ12-6-TTL; IP4252CZ12-6-TTL; IP4253CZ12-6-TTL; IP4254CZ12-6-TTL (SOT1167-1)
1 and 12 filter channel 1
2 and 11 filter channel 2
3 and 10 filter channel 3
4 and 9 filter channel 4
5 and 8 filter channel 5
6 and 7 filter channel 6
ground pad ground
Transparent
top view
8
1
5
4
018aaa071
Rs(ch)
Cch
1 to 4 5 to 8
GND
2
Cch
2
Transparent
top view
12
1
7
6
018aaa072
Rs(ch)
1 to 6 7 to 12
GND
Cch
2
Cch
2IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 3 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
3. Ordering information
IP4251CZ16-8-TTL; IP4252CZ16-8-TTL; IP4253CZ16-8-TTL; IP4254CZ16-8-TTL (SOT1168-1)
1 and 16 filter channel 1
2 and 15 filter channel 2
3 and 14 filter channel 3
4 and 13 filter channel 4
5 and 12 filter channel 5
6 and 11 filter channel 6
7 and 10 filter channel 7
8 and 9 filter channel 8
ground pad ground
Table 2. Pinning …continued
Pin Description Simplified outline Graphic symbol
Transparent
top view
16
1
9
8
018aaa073
Rs(ch)
1 to 8 9 to 16
GND
Cch
2
Cch
2
Table 3. Ordering information
Type number Package
Name Description Version
IP4251CZ8-4-TTL HUSON8 plastic, thermal enhanced ultra thin small outline package; no leads;
8 terminals; body 1.35 × 1.7 × 0.55 mm
SOT1166-1
IP4251CZ12-6-TTL HUSON12 plastic, thermal enhanced ultra thin small outline package; no leads;
12 terminals; body 1.35 × 2.5 × 0.55 mm
SOT1167-1
IP4251CZ16-8-TTL HUSON16 plastic, thermal enhanced ultra thin small outline package; no leads;
16 terminals; body 1.35 × 3.3 × 0.55 mm
SOT1168-1
IP4252CZ8-4-TTL HUSON8 plastic, thermal enhanced ultra thin small outline package; no leads;
8 terminals; body 1.35 × 1.7 × 0.55 mm
SOT1166-1
IP4252CZ12-6-TTL HUSON12 plastic, thermal enhanced ultra thin small outline package; no leads;
12 terminals; body 1.35 × 2.5 × 0.55 mm
SOT1167-1
IP4252CZ16-8-TTL HUSON16 plastic, thermal enhanced ultra thin small outline package; no leads;
16 terminals; body 1.35 × 3.3 × 0.55 mm
SOT1168-1
IP4253CZ8-4-TTL HUSON8 plastic, thermal enhanced ultra thin small outline package; no leads;
8 terminals; body 1.35 × 1.7 × 0.55 mm
SOT1166-1
IP4253CZ12-6-TTL HUSON12 plastic, thermal enhanced ultra thin small outline package; no leads;
12 terminals; body 1.35 × 2.5 × 0.55 mm
SOT1167-1
IP4253CZ16-8-TTL HUSON16 plastic, thermal enhanced ultra thin small outline package; no leads;
16 terminals; body 1.35 × 3.3 × 0.55 mm
SOT1168-1
IP4254CZ8-4-TTL HUSON8 plastic, thermal enhanced ultra thin small outline package; no leads;
8 terminals; body 1.35 × 1.7 × 0.55 mm
SOT1166-1
IP4254CZ12-6-TTL HUSON12 plastic, thermal enhanced ultra thin small outline package; no leads;
12 terminals; body 1.35 × 2.5 × 0.55 mm
SOT1167-1
IP4254CZ16-8-TTL HUSON16 plastic, thermal enhanced ultra thin small outline package; no leads;
16 terminals; body 1.35 × 3.3 × 0.55 mm
SOT1168-1IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 4 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
4. Limiting values
[1] Device tested with 1000 pulses of ±15 kV contact discharges, according to the IEC 61000-4-2 model,
far exceeding IEC 61000-4-2 level 4 (8 kV contact discharge).
[2] Device tested with 1000 pulses of ±30 kV contact discharges, according to the IEC 61000-4-2 model,
far exceeding IEC 61000-4-2 level 4 (8 kV contact discharge).
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
IP4251CZ8-4-TTL; IP4251CZ12-6-TTL; IP4251CZ16-8-TTL
VESD electrostatic discharge
voltage
all pins to ground;
contact discharge
[1] - ±15 kV
IP4252CZ8-4-TTL; IP4252CZ12-6-TTL; IP4252CZ16-8-TTL
VESD electrostatic discharge
voltage
all pins to ground;
contact discharge
[1] - ±15 kV
IP4253CZ8-4-TTL; IP4253CZ12-6-TTL; IP4253CZ16-8-TTL
VESD electrostatic discharge
voltage
all pins to ground [2]
contact discharge - ±30 kV
air discharge - ±30 kV
IP4254CZ8-4-TTL; IP4254CZ12-6-TTL; IP4254CZ16-8-TTL
VESD electrostatic discharge
voltage
all pins to ground [2]
contact discharge - ±30 kV
air discharge - ±30 kV
Per device
VESD electrostatic discharge
voltage
IEC 61000-4-2, level 4;
all pins to ground
contact discharge - ±8 kV
air discharge - ±15 kV
VCC supply voltage −0.5 +5.6 V
Pch channel power dissipation Tamb = 85 °C - 60 mW
Ptot total power dissipation Tamb = 85 °C - 200 mW
Tstg storage temperature −55 +150 °C
Tamb ambient temperature −40 +85 °CIP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 5 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
5. Characteristics
[1] For the total channel.
[2] Guaranteed by design.
Table 5. Channel characteristics
Tamb = 25 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
IP4251CZ8-4-TTL; IP4251CZ12-6-TTL; IP4251CZ16-8-TTL
Cch channel capacitance f = 100 kHz [1]
Vbias(DC) = 2.5 V - 10 - pF
Vbias(DC) =0V [2] - 15 - pF
Rs(ch) channel series resistance 80 100 120 Ω
IP4252CZ8-4-TTL; IP4252CZ12-6-TTL; IP4252CZ16-8-TTL
Cch channel capacitance f = 100 kHz [1]
Vbias(DC) = 2.5 V - 12 - pF
Vbias(DC) =0V [2] - 18 - pF
Rs(ch) channel series resistance 32 40 48 Ω
IP4253CZ8-4-TTL; IP4253CZ12-6-TTL; IP4253CZ16-8-TTL
Cch channel capacitance f = 100 kHz [1]
Vbias(DC) = 2.5 V - 30 - pF
Vbias(DC) =0V [2] - 45 - pF
Rs(ch) channel series resistance 160 200 240 Ω
IP4254CZ8-4-TTL; IP4254CZ12-6-TTL; IP4254CZ16-8-TTL
Cch channel capacitance f = 100 kHz [1]
Vbias(DC) = 2.5 V - 30 - pF
Vbias(DC) =0V [2] - 45 - pF
Rs(ch) channel series resistance 80 100 120 Ω
Per device
ILR reverse leakage current per channel; VI = 3.5 V - - 0.1 μA
VBR breakdown voltage positive clamp; II = 1 mA 5.8 - 9 V
VF forward voltage negative clamp; IF = 1 mA 0.4 - 1.5 VIP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 6 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
Table 6. Frequency characteristics
Tamb = 25 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
IP4251CZ8-4-TTL; IP4251CZ12-6-TTL; IP4251CZ16-8-TTL
αil insertion loss Rsource = 50 Ω; RL = 50 Ω
800 MHz < f < 3 GHz - 16 - dB
f = 1 GHz - 20 - dB
αct crosstalk attenuation Rsource = 50 Ω; RL = 50 Ω;
800 MHz < f < 3 GHz
- 30 - dB
IP4252CZ8-4-TTL; IP4252CZ12-6-TTL; IP4252CZ16-8-TTL
αil insertion loss Rsource = 50 Ω; RL = 50 Ω
800 MHz < f < 3 GHz - 12 - dB
f = 1 GHz - 14 - dB
αct crosstalk attenuation Rsource = 50 Ω; RL = 50 Ω;
800 MHz < f < 3 GHz
- 40 - dB
IP4253CZ8-4-TTL; IP4253CZ12-6-TTL; IP4253CZ16-8-TTL
αil insertion loss Rsource = 50 Ω; RL = 50 Ω
800 MHz < f < 3 GHz - 33 - dB
f = 1 GHz 35 - - dB
αct crosstalk attenuation Rsource = 50 Ω; RL = 50 Ω;
800 MHz < f < 3 GHz
- 30 - dB
IP4254CZ8-4-TTL; IP4254CZ12-6-TTL; IP4254CZ16-8-TTL
αil insertion loss Rsource = 50 Ω; RL = 50 Ω
800 MHz < f < 3 GHz - 28 - dB
f = 1 GHz 30 - - dB
αct crosstalk attenuation Rsource = 50 Ω; RL = 50 Ω;
800 MHz < f < 3 GHz
- 30 - dBIP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 7 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
6. Application information
6.1 Insertion loss
The devices are designed as EMI/RFI filters for multichannel interfaces.
The block schematic for measuring insertion loss in a 50 Ω system is shown in Figure 1.
Typical measurements results are shown in Figure 2 to Figure 6 for the different devices.
(1) IP4252CZ16-8-TTL - channel 1 to channel 16
(2) IP4251CZ16-8-TTL - channel 1 to channel 16
(3) IP4254CZ16-8-TTL - channel 1 to channel 16
(4) IP4253CZ16-8-TTL - channel 1 to channel 16
Fig 1. Frequency response setup Fig 2. Frequency response curves overview
018aaa074
50 Ω
Vgen
50 Ω
DUT
IN OUT
001aaj308
−30
−20
−40
−10
0
S21
(dB)
−50
f (MHz)
10−1 104 103 1 102 10
(1)
(2)
(3)
(4)IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 8 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
Due to the optimized silicon dice and package design, all channels in a single package
show a very good matching performance as the insertion loss for a channel at the
package side (e.g. channel 1 to channel 16) is nearly identical with the center channels
(e.g. channel 4 to channel 13).
(1) Channel 1 to channel 16
(2) Channel 4 to channel 13
(1) Channel 1 to channel 16
(2) Channel 4 to channel 13
Fig 3. IP4251CZ16-8-TTL: frequency response
curves
Fig 4. IP4252CZ16-8-TTL: frequency response
curves
(1) Channel 1 to channel 16
(2) Channel 4 to channel 13
(1) Channel 4 to channel 13
(2) Channel 1 to channel 16
Fig 5. IP4253CZ16-8-TTL: frequency response
curves
Fig 6. IP4254CZ16-8-TTL: frequency response
curves
001aaj608
−30
−20
−40
−10
0
S21
(dB)
−50
f (MHz)
10−1 104 103 1 102 10
(1)
(2)
001aaj609
−30
−20
−40
−10
0
S21
(dB)
−50
f (MHz)
10−1 104 103 1 102 10
(1)
(2)
001aaj610
−30
−20
−40
−10
0
S21
(dB)
−50
f (MHz)
10−1 104 103 1 102 10
(1)
(2)
001aaj611
−30
−20
−40
−10
0
S21
(dB)
−50
f (MHz)
10−1 104 103 1 102 10
(1)
(2)IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 9 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
6.2 Selection
The selection of one of the filter devices has to be performed depending on the maximum
clock frequency, driver strength, capacitive load of the sink, and also the maximum
applicable rise and fall times.
6.2.1 SDHC and MMC memory interface
The Secure Digital High Capacity (SDHC) memory card interface standard specification
and the Multi Media Card (MMC) (JESD 84A43) standard specification recommend a rise
and fall time of 25 % to 62.5 % (62.5 % to 25 % respectively) of 3 ns or less for the input
signal of the receiving interface side.
Assuming a typical capacitance of about 20 pF for the SDHC memory card itself, and
approximately 4 pF to 7 pF for the Printed-Circuit Board (PCB) and the card holder,
IP4252CZ12-6-TTL (6 channels, Rs(ch) = 40 Ω, Cch = 12 pF at Vbias(DC) = 2.5 V) is a
matching selection to filter and protect all relevant interface pins such as CLK, CMD, and
DAT0 to DAT3/CD. Please refer to Figure 7 for a general example of the implementation
of the device in an SDHC card interface.
In case additional channels such as write-protect or a mechanical card-detection switch
are used, the IP4252CZ16-8-TTL (8 channels, Rs(ch) = 40 Ω, Cch = 12 pF at
Vbias(DC) = 2.5 V) offers two additional channels.IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 10 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
The capacitance values specified for the signal channels of the MMC interface differ from
the SDHC specification. The MMC card-side interface is specified to have an intrinsic
capacitance of 12 pF to 18 pF and the total channel is limited according to the
specification to 30 pF only. Therefore, any filter device capacitance is limited to a
maximum of up to 18 pF, including the card holder and PCB traces.
Please refer to Figure 8 for a general example of the implementation of the IP4252 in an
MMC interface application.
Fig 7. Example of IP4252 in an SDHC card interface
018aaa075
IP4252CZ12-6-TTL
(IP4252CZ16-8-TTL)
DAT1
pull-up resistors
10 kΩ − 100 kΩ
10 kΩ − 90 kΩ
DAT3/CD pull-up
10 kΩ − 100 kΩ
DAT3/CD pull-up
>270 kΩ
exact value
depends on
required
logic levels
DAT1 SD MEMORY
CARD
SET_CLR_
CARD_DETECT
(ACMD42)
to HOST
INTERFACE
DAT0
GND
CLK
VCC(VSD)
VCC(VSD)
DAT3/CD
CMD
DAT2
optional:
2-additional channels
of IP4252CZ16-8-TTL
optional:
write protect switch
optional:
electrical card detect
WP
DAT0
CLK
CMD
DAT3/CD
DAT2
CD
WP
optional:
card detect switch
CDIP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 11 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
To generate SDHC and MMC-compliant digital signals, the driver strength should not
significantly undercut 8 mA.
6.2.2 LCD interfaces, medium-speed interfaces
For digital interfaces such as LCD interfaces running at clock speeds between 10 MHz
and 25 MHz or more, IP4251, IP4252 or IP4254 can be used depending on the sink load,
clock speed, driver strength and rise and fall time requirements. Also the minimum
EMI filter requirements may be a decision-making factor.
6.2.3 Keypad, low-speed interfaces
Especially for lower-speed interfaces such as keypads, low-speed serial interfaces
(e.g. Recommended Standard (RS) 232) and low-speed control signals,
IP4253 (Rs(ch) = 200 Ω, Cch = 30 pF at Vbias(DC) = 2.5 V) offers a very robust
ESD protection and strong suppression of unwanted frequencies (EMI filtering).
Fig 8. Example of IP4252 in an MMC interface
018aaa076
IP4252CZ12-6-TTL
IP4252CZ8-4-TTL
DAT1
pull-up resistors
50 kΩ - 100 kΩ
CMD pull-up
4.7 kΩ - 100 kΩ
DAT1 C8
e.g.
RSMMC
HOST
INTERFACE
DAT0 C7
DAT7 C13
VSS2 C6
DAT6 C12
CLK C5
VCC(VMMC)
VCC(VMMC)
C4
VSS1 C3
DAT5 C11
CMD C2
DAT4 C10
DAT3 C1
DAT2
CMD
DAT4
DAT3
DAT2 C9
DAT0
DAT7
DAT6
CLK
DAT5IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 12 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
7. Package outline
Fig 9. Package outline SOT1166-1 (HUSON8)
Outline References
version
European
projection Issue date
IEC JEDEC JEITA
SOT1166-1 - - - - - - - - -
sot1166-1_po
10-03-18
10-03-22
Unit(1)
mm
max
nom
min
0.55 0.05
0.00
0.25
0.20
0.15
1.8
1.7
1.6
1.3
1.2
1.1
1.45
1.35
1.25
0.4 1.2
0.30
0.25
0.20
0.05
A
Dimensions
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
HUSON8: plastic, thermal enhanced ultra thin small outline package; no leads;
8 terminals; body 1.35 x 1.7 x 0.55 mm SOT1166-1
A1 c
0.127
b DDh E Eh
0.45
0.40
0.35
e e1 k
0.2
L v
0.1
w
0.05
y
0.05
y1
0 1 2 mm
scale
X
C
y1 C y
tiebars are indicated on
arbitrary location and size
detail X
A
A1
c
terminal 1
index area
D B A
E
b
terminal 1
index area
e1
e v C A B
w C
L
k
Eh
Dh
1
8
4
5IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 13 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
Fig 10. Package outline SOT1167-1 (HUSON12)
Outline References
version
European
projection Issue date
IEC JEDEC JEITA
SOT1167-1 - - - - - - - - -
sot1167-1_po
10-03-18
10-03-22
Unit(1)
mm
max
nom
min
0.55 0.05
0.00
0.25
0.20
0.15
2.6
2.5
2.4
2.1
2.0
1.9
1.45
1.35
1.25
0.4 2.0
0.30
0.25
0.20
0.05
A
Dimensions
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
HUSON12: plastic, thermal enhanced ultra thin small outline package; no leads;
12 terminals; body 1.35 x 2.5 x 0.55 mm SOT1167-1
A1 c
0.127
b DDh E Eh
0.45
0.40
0.35
e e1 k
0.2
L v
0.1
w
0.05
y
0.05
y1
0 1 2 mm
scale
X
C
y1 C y
tiebars are indicated on
arbitrary location and size
detail X
A
A1
c
terminal 1
index area
D B A
E
b
terminal 1
index area
e1
e v C A B
w C
L
k
Eh
Dh
1
12
6
7IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 14 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
Fig 11. Package outline SOT1168-1 (HUSON16)
Outline References
version
European
projection Issue date
IEC JEDEC JEITA
SOT1168-1 - - - - - - - - -
sot1168-1_po
10-03-18
10-03-22
Unit(1)
mm
max
nom
min
0.55 0.05
0.00
0.25
0.20
0.15
3.4
3.3
3.2
2.9
2.8
2.7
1.45
1.35
1.25
0.4 2.8
0.30
0.25
0.20
0.05
A
Dimensions
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
HUSON16: plastic, thermal enhanced ultra thin small outline package; no leads;
16 terminals; body 1.35 x 3.3 x 0.55 mm SOT1168-1
A1 c
0.127
b DDh E Eh
0.45
0.40
0.35
e e1 k
0.2
L v
0.1
w
0.05
y
0.05
y1
0 1 2 mm
scale
X
C
y1 C y
tiebars are indicated on
arbitrary location and size
detail X
A
A1
c
terminal 1
index area
D B A
E
b
terminal 1
index area
e1
e v C A B
w C
L
k
Eh
Dh
1
16
8
9IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 15 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
8. Revision history
Table 7. Revision history
Document ID Release date Data sheet status Change notice Supersedes
IP4251_52_53_54-TTL v.2 20110505 Product data sheet - IP4251_52_53_54-TTL v.1
Modifications: • Section 1 “Product profile”: updated.
• Table 2 “Pinning”: updated.
• Deleted section “Thermal characteristics”.
IP4251_52_53_54-TTL v.1 20110131 Objective data sheet - -IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 16 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
9. Legal information
9.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
9.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
9.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification. IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 17 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
9.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
10. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.comNXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 5 May 2011
Document identifier: IP4251_52_53_54-TTL
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
11. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . 2
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 3
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
5 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
6 Application information. . . . . . . . . . . . . . . . . . . 7
6.1 Insertion loss . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.2 Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.2.1 SDHC and MMC memory interface . . . . . . . . . 9
6.2.2 LCD interfaces, medium-speed interfaces . . . 11
6.2.3 Keypad, low-speed interfaces. . . . . . . . . . . . . 11
7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10 Contact information. . . . . . . . . . . . . . . . . . . . . 17
11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DATA SHEET
Product data sheet
Supersedes data of 2003 Nov 27
2004 Nov 04
DISCRETE SEMICONDUCTORS
PBSS5320X
20 V, 3 A
PNP low VCEsat (BISS) transistor
dbook, halfpage
M3D1092004 Nov 04 2
NXP Semiconductors Product data sheet
20 V, 3 A
PNP low VCEsat (BISS) transistor PBSS5320X
FEATURES
• SOT89 (SC-62) package
• Low collector-emitter saturation voltage VCEsat
• High collector current capability: IC and ICM
• Higher efficiency leading to less heat generation
• Reduced printed-circuit board requirements.
APPLICATIONS
• Power management
– DC/DC converters
– Supply line switching
– Battery charger
– LCD backlighting.
• Peripheral drivers
– Driver in low supply voltage applications (e.g. lamps
and LEDs)
– Inductive load driver (e.g. relays,
buzzers and motors).
DESCRIPTION
PNP low VCEsat transistor in a SOT89 plastic package.
NPN complement: PBSS4320X.
MARKING
TYPE NUMBER MARKING CODE
PBSS5320X S45
PINNING
PIN DESCRIPTION
1 emitter
2 collector
3 base
321 sym079
1
2
3
Fig.1 Simplified outline (SOT89) and symbol.
QUICK REFERENCE DATA
SYMBOL PARAMETER MAX. UNIT
VCEO collector-emitter voltage −20 V
IC collector current (DC) −3 A
ICM peak collector current −5 A
RCEsat equivalent on-resistance 105 mΩ
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
NAME DESCRIPTION VERSION
PBSS5320X SC-62 plastic surface mounted package; collector pad for good heat
transfer; 3 leads
SOT892004 Nov 04 3
NXP Semiconductors Product data sheet
20 V, 3 A
PNP low VCEsat (BISS) transistor PBSS5320X
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
Notes
1. Device mounted on a FR4 printed-circuit board; single-sided copper; tin-plated; standard footprint.
2. Device mounted on a FR4 printed-circuit board; single-sided copper; tin-plated; mounting pad for collector 1 cm2.
3. Device mounted on a FR4 printed-circuit board; single-sided copper; tin-plated; mounting pad for collector 6 cm2.
4. Device mounted on a ceramic printed-circuit board 7 cm2, single-sided copper, tin-plated.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCBO collector-base voltage open emitter − −20 V
VCEO collector-emitter voltage open base − −20 V
VEBO emitter-base voltage open collector − −5 V
IC collector current (DC) note 4 − −3 A
ICM peak collector current limited by Tj(max) − −5 A
IB base current (DC) − −0.5 A
Ptot total power dissipation Tamb ≤ 25 °C
note 1 − 550 mW
note 2 − 1 W
note 3 − 1.4 W
note 4 − 1.6 W
Tstg storage temperature −65 +150 °C
Tj junction temperature − 150 °C
Tamb ambient temperature −65 +150 °C2004 Nov 04 4
NXP Semiconductors Product data sheet
20 V, 3 A
PNP low VCEsat (BISS) transistor PBSS5320X
handbook, halfpage
0 40 80 160
Ptot
(W) (1)
(2)
(3)
2
0
1.6
120
1.2
0.8
0.4
MLE372
Tamb (°C)
(4)
Fig.2 Power derating curves.
(1) Ceramic PCB; 7 cm2
mounting pad for collector.
(2) FR4 PCB; 6 cm2 copper
mounting pad for collector.
(3) FR4 PCB; 1 cm2 copper
mounting pad for collector.
(4) Standard footprint.2004 Nov 04 5
NXP Semiconductors Product data sheet
20 V, 3 A
PNP low VCEsat (BISS) transistor PBSS5320X
THERMAL CHARACTERISTICS
Notes
1. Device mounted on a FR4 printed-circuit board; single-sided copper; tin-plated; standard footprint.
2. Device mounted on a FR4 printed-circuit board; single-sided copper; tin-plated; mounting pad for collector 1 cm2.
3. Device mounted on a FR4 printed-circuit board; single-sided copper; tin-plated; mounting pad for collector 6 cm2.
4. Device mounted on a ceramic printed-circuit board 7 cm2, single-sided copper, tin-plated.
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth(j-a) thermal resistance from junction to ambient in free air
note 1 225 K/W
note 2 125 K/W
note 3 90 K/W
note 4 80 K/W
Rth(j-s) thermal resistance from junction to soldering point 16 K/W
006aaa243
10
1
102
103
Zth(j-a)
(K/W)
10−1
10−5 10 10 −2 10−4 102 10−1
tp (s)
10−3 103 1
duty cycle =
1.00
0.75
0.50
0.33
0.20
0.10
0.05
0.02
0.01
0
Fig.3 Transient thermal impedance as a function of pulse time; typical values.
Mounted on FR4 printed-circuit board; standard footprint.2004 Nov 04 6
NXP Semiconductors Product data sheet
20 V, 3 A
PNP low VCEsat (BISS) transistor PBSS5320X
006aaa244
10
1
102
103
Zth(j-a)
(K/W)
10−1
10−5 10 10 −2 10−4 102 10−1
tp (s)
10−3 103 1
duty cycle =
1.00
0.75
0.50
0.20
0.05
0.02
0.01
0
0.33
0.10
Fig.4 Transient thermal impedance as a function of pulse time; typical values.
Mounted on FR4 printed-circuit board; mounting pad for collector 1 cm2.
006aaa245
10
1
102
103
Zth(j-a)
(K/W)
10−1
10−5 10 10 −2 10−4 102 10−1
tp (s)
10−3 103 1
duty cycle =
1.00
0.75
0.50
0.20
0.05
0.02
0.01
0
0.33
0.10
Fig.5 Transient thermal impedance as a function of pulse time; typical values.
Mounted on FR4 printed-circuit board; mounting pad for collector 6 cm2.2004 Nov 04 7
NXP Semiconductors Product data sheet
20 V, 3 A
PNP low VCEsat (BISS) transistor PBSS5320X
CHARACTERISTICS
Tamb = 25 °C unless otherwise specified.
Note
1. Pulse test: tp ≤ 300 μs; δ ≤ 0.02.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
ICBO collector-base cut-off current VCB = −20 V; IE = 0 A − − −100 nA
VCB = −20 V; IE = 0 A; Tj = 150 °C − − −50 μA
ICES collector-emitter cut-off current VCE = −20 V; VBE = 0 V − − −100 nA
IEBO emitter-base cut-off current VEB = −5 V; IC = 0 A − − −100 nA
hFE DC current gain VCE = −2 V
IC = −0.1 A 220 − −
IC = −0.5 A 220 − −
IC = −1 A; note 1 200 − −
IC = −2 A; note 1 150 − −
IC = −3 A; note 1 100 − −
VCEsat collector-emitter saturation
voltage
IC = −0.5 A; IB = −50 mA − − −70 mV
IC = −1 A; IB = −50 mA − − −130 mV
IC = −2 A; IB = −100 mA − − −230 mV
IC = −3 A; IB = −300 mA; note 1 − − −300 mV
RCEsat equivalent on-resistance IC = −3 A; IB = −300 mA; note 1 − 90 105 mΩ
VBEsat base-emitter saturation voltage IC = −2 A; IB = −100 mA − −1.1 − V
IC = −3 A; IB = −300 mA; note 1 − − −1.2 V
VBEon base-emitter turn-on voltage VCE = −2 V; IC = −1 A −1.1 − − V
fT transition frequency IC = −100 mA; VCE = −5 V;
f = 100 MHz
100 − − MHz
Cc collector capacitance VCB = −10 V; IE = ie = 0 A; f = 1 MHz − − 50 pF2004 Nov 04 8
NXP Semiconductors Product data sheet
20 V, 3 A
PNP low VCEsat (BISS) transistor PBSS5320X
0
800
200
400
600
MLE374
−10−1 −1
I
C (mA)
hFE
−10 −102 −103 −104
(2)
(3)
(1)
Fig.6 DC current gain as a function of collector
current; typical values.
VCE = −2 V.
(1) Tamb = 100 °C.
(2) Tamb = 25 °C.
(3) Tamb = −55 °C.
handbook, halfpage
MLE368
0
−1.2
−0.4
−0.8
−10−1 −1 −10
I
C (mA)
VBE
(V)
−102 −103 −104
(1)
(3)
(2)
Fig.7 Base-emitter voltage as a function of
collector current; typical values.
VCE = −2 V.
(1) Tamb = −55 °C.
(2) Tamb = 25 °C.
(3) Tamb = 100 °C.
handbook, halfpage
MLE370
−1
−10−1
−10−2
−10−3
−10−1 −1 −10
I
C (mA)
VCEsat
(V)
−102 −103 −104
(1)
(3)
(2)
Fig.8 Collector-emitter saturation voltage as a
function of collector current; typical values.
IC/IB = 20.
(1) Tamb = 100 °C.
(2) Tamb = 25 °C.
(3) Tamb = −55 °C.
handbook, halfpage
MLE371
−1
−10−1
−10−2
−10−3
−10−1 −1 −10
I
C (mA)
VCEsat
(V)
−102 −103 −104
(3)
(1)
(2)
Fig.9 Collector-emitter saturation voltage as a
function of collector current; typical values.
Tamb = 25 °C.
(1) IC/IB = 100.
(2) IC/IB = 50.
(3) IC/IB = 10.2004 Nov 04 9
NXP Semiconductors Product data sheet
20 V, 3 A
PNP low VCEsat (BISS) transistor PBSS5320X
handbook, halfpage −10
−1
−10−1 −1 −10 −102 −103 −104 −10−1
MLE369
I
C (mA)
VBEsat
(V)
(2)
(3)
(1)
Fig.10 Base-emitter saturation voltage as a
function of collector current; typical values.
IC/IB = 20.
(1) Tamb = −55 °C.
(2) Tamb = 25 °C.
(3) Tamb = 100 °C.
handbook, halfpage
103
102
10
1
10−2
10−1
MLE376
−10−1 −1 −10
I
C (mA)
RCEsat
(Ω)
−103 −102 −104
(1)
(3) (2)
Fig.11 Equivalent on-resistance as a function of
collector current; typical values.
Tamb = 25 °C.
(1) IC/IB = 100. (2) IC/IB = 50. (3) IC/IB = 10.
handbook, halfpage
MLE367
102
10
10−1
10−2
1
−10−1 −1
RCEsat
(Ω)
I
C (mA) −10 −102 −103 −104
(2)
(3)
(1)
Fig.12 Equivalent on-resistance as a function of
collector current; typical values.
IC/IB = 20.
(1) Tamb = 100 °C. (2) Tamb = 25 °C. (3) Tamb = −55 °C.
handbook, halfpage
0 −2
−5
0
−1
−2
−3
−4
−0.4
VCE (V)
I
C
(A)
−0.8 −1.2 −1.6
MLE375
(8)
(5)
(1)
(2)
(3)
(4)
(10)
(7)
(6)
(9)
Fig.13 Collector current as a function of
collector-emitter voltage; typical values.
(1) IB = −25 mA.
(2) IB = −22.5 mA.
(3) IB = −20 mA.
(4) IB = −17.5 mA.
(5) IB = −15 mA.
(6) IB = −12.5 mA.
(7) IB = −10 mA.
(8) IB = −7.5 mA.
(9) IB = −5 mA.
(10) IB = −2.5 mA.
Tamb = 25 °C.2004 Nov 04 10
NXP Semiconductors Product data sheet
20 V, 3 A
PNP low VCEsat (BISS) transistor PBSS5320X
PACKAGE OUTLINE
REFERENCES OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
DIMENSIONS (mm are the original dimensions)
SOT89 TO-243 SC-62 04-08-03
06-03-16
w M
e1
e
E
HE
B
0 2 4 mm
scale
bp3
bp2
bp1
c
D
Lp
A
Plastic surface-mounted package; collector pad for good heat transfer; 3 leads SOT89
1 23
UNIT A
mm 1.6
1.4
0.48
0.35
c
0.44
0.23
D
4.6
4.4
E
2.6
2.4
HE Lp
4.25
3.75
e
3.0
w
0.13
e1
1.5 1.2
0.8
bp1 bp2
0.53
0.40
bp3
1.8
1.42004 Nov 04 11
NXP Semiconductors Product data sheet
20 V, 3 A
PNP low VCEsat (BISS) transistor PBSS5320X
DATA SHEET STATUS
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
DOCUMENT
STATUS(1)
PRODUCT
STATUS(2) DEFINITION
Objective data sheet Development This document contains data from the objective specification for product
development.
Preliminary data sheet Qualification This document contains data from the preliminary specification.
Product data sheet Production This document contains the product specification.
DISCLAIMERS
General ⎯ Information in this document is believed to be
accurate and reliable. However, NXP Semiconductors
does not give any representations or warranties,
expressed or implied, as to the accuracy or completeness
of such information and shall have no liability for the
consequences of use of such information.
Right to make changes ⎯ NXP Semiconductors
reserves the right to make changes to information
published in this document, including without limitation
specifications and product descriptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
Suitability for use ⎯ NXP Semiconductors products are
not designed, authorized or warranted to be suitable for
use in medical, military, aircraft, space or life support
equipment, nor in applications where failure or malfunction
of an NXP Semiconductors product can reasonably be
expected to result in personal injury, death or severe
property or environmental damage. NXP Semiconductors
accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at
the customer’s own risk.
Applications ⎯ Applications that are described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values ⎯ Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) may cause permanent damage to
the device. Limiting values are stress ratings only and
operation of the device at these or any other conditions
above those given in the Characteristics sections of this
document is not implied. Exposure to limiting values for
extended periods may affect device reliability.
Terms and conditions of sale ⎯ NXP Semiconductors
products are sold subject to the general terms and
conditions of commercial sale, as published at
http://www.nxp.com/profile/terms, including those
pertaining to warranty, intellectual property rights
infringement and limitation of liability, unless explicitly
otherwise agreed to in writing by NXP Semiconductors. In
case of any inconsistency or conflict between information
in this document and such terms and conditions, the latter
will prevail.
No offer to sell or license ⎯ Nothing in this document
may be interpreted or construed as an offer to sell products
that is open for acceptance or the grant, conveyance or
implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control ⎯ This document as well as the item(s)
described herein may be subject to export control
regulations. Export might require a prior authorization from
national authorities.
Quick reference data ⎯ The Quick reference data is an
extract of the product data given in the Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaustive or legally binding. NXP Semiconductors
Contact information
For additional information please visit: http://www.nxp.com
For sales offices addresses send e-mail to: salesaddresses@nxp.com
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Printed in The Netherlands R75/03/pp12 Date of release: 2004 Nov 04 Document order number: 9397 750 13887
Features
• Utilizes the AVR® RISC Architecture
• AVR – High-performance and Low-power RISC Architecture
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
• Data and Non-volatile Program and Data Memories
– 2K Bytes of In-System Self Programmable Flash
Endurance 10,000 Write/Erase Cycles
– 128 Bytes In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– 128 Bytes Internal SRAM
– Programming Lock for Flash Program and EEPROM Data Security
• Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes
– Four PWM Channels
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– USI – Universal Serial Interface
– Full Duplex USART
• Special Microcontroller Features
– debugWIRE On-chip Debugging
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low-power Idle, Power-down, and Standby Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
• I/O and Packages
– 18 Programmable I/O Lines
– 20-pin PDIP, 20-pin SOIC, 20-pad QFN/MLF
• Operating Voltages
– 1.8 – 5.5V (ATtiny2313V)
– 2.7 – 5.5V (ATtiny2313)
• Speed Grades
– ATtiny2313V: 0 – 4 MHz @ 1.8 - 5.5V, 0 – 10 MHz @ 2.7 – 5.5V
– ATtiny2313: 0 – 10 MHz @ 2.7 - 5.5V, 0 – 20 MHz @ 4.5 – 5.5V
• Typical Power Consumption
– Active Mode
1 MHz, 1.8V: 230 µA
32 kHz, 1.8V: 20 µA (including oscillator)
– Power-down Mode
< 0.1 µA at 1.8V
8-bit
Microcontroller
with 2K Bytes
In-System
Programmable
Flash
ATtiny2313/V
Preliminary
Rev. 2543L–AVR–08/102
2543L–AVR–08/10
ATtiny2313
Pin
Configurations
Figure 1. Pinout ATtiny2313
Overview The ATtiny2313 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATtiny2313 achieves
throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption
versus processing speed.
(RESET/dW) PA2
(RXD) PD0
(TXD) PD1
(XTAL2) PA1
(XTAL1) PA0
(CKOUT/XCK/INT0) PD2
(INT1) PD3
(T0) PD4
(OC0B/T1) PD5
GND
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
VCC
PB7 (UCSK/SCL/PCINT7)
PB6 (MISO/DO/PCINT6)
PB5 (MOSI/DI/SDA/PCINT5)
PB4 (OC1B/PCINT4)
PB3 (OC1A/PCINT3)
PB2 (OC0A/PCINT2)
PB1 (AIN1/PCINT1)
PB0 (AIN0/PCINT0)
PD6 (ICP)
PDIP/SOIC
1
2
3
4
5
MLF
15
14
13
12
11
20
19
18
17
16
6
7
8
9
10
(TXD) PD1
XTAL2) PA1
(XTAL1) PA0
(CKOUT/XCK/INT0) PD2
(INT1) PD3
(T0) PD4
(OC0B/T1) PD5
GND
(ICP) PD6
(AIN0/PCINT0) PB0
PB5 (MOSI/DI/SDA/PCINT5)
PB4 (OC1B/PCINT4)
PB3 (OC1A/PCINT3)
PB2 (OC0A/PCINT2)
PB1 (AIN1/PCINT1)
PD0 (RXD)
PA2 (RESET/dW)
VCC
PB7 (UCSK/SCK/PCINT7)
PB6 (MISO/DO/PCINT6)
NOTE: Bottom pad should be soldered to ground.3
2543L–AVR–08/10
ATtiny2313
Block Diagram
Figure 2. Block Diagram
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
GND
VCC
INSTRUCTION
DECODER
CONTROL
LINES
STACK
POINTER
SRAM
GENERAL
PURPOSE
REGISTER
ALU
STATUS
REGISTER
PROGRAMMING
LOGIC SPI
8-BIT DATA BUS
XTAL1 XTAL2
RESET
INTERNAL
OSCILLATOR
OSCILLATOR
WATCHDOG
TIMER
TIMING AND
CONTROL
MCU CONTROL
REGISTER
MCU STATUS
REGISTER
TIMER/
COUNTERS
INTERRUPT
UNIT
EEPROM
USI
USART
ANALOG
COMPARATOR
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
DATA REGISTER
PORTA
DATA DIR.
REG. PORTA
PORTB DRIVERS
PB0 - PB7
PORTA DRIVERS
PA0 - PA2
DATA REGISTER
PORTD
DATA DIR.
REG. PORTD
PORTD DRIVERS
PD0 - PD6
ON-CHIP
DEBUGGER
INTERNAL
CALIBRATED
OSCILLATOR4
2543L–AVR–08/10
ATtiny2313
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than conventional
CISC microcontrollers.
The ATtiny2313 provides the following features: 2K bytes of In-System Programmable Flash,
128 bytes EEPROM, 128 bytes SRAM, 18 general purpose I/O lines, 32 general purpose working
registers, a single-wire Interface for On-chip Debugging, two flexible Timer/Counters with
compare modes, internal and external interrupts, a serial programmable USART, Universal
Serial Interface with Start Condition Detector, a programmable Watchdog Timer with internal
Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU
while allowing the SRAM, Timer/Counters, and interrupt system to continue functioning. The
Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip
functions until the next interrupt or hardware reset. In Standby mode, the crystal/resonator Oscillator
is running while the rest of the device is sleeping. This allows very fast start-up combined
with low-power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI
serial interface, or by a conventional non-volatile memory programmer. By combining an 8-bit
RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATtiny2313
is a powerful microcontroller that provides a highly flexible and cost effective solution to many
embedded control applications.
The ATtiny2313 AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators,
and Evaluation kits.5
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ATtiny2313
Pin Descriptions
VCC Digital supply voltage.
GND Ground.
Port A (PA2..PA0) Port A is a 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port A also serves the functions of various special features of the ATtiny2313 as listed on page
53.
Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny2313 as listed on page
53.
Port D (PD6..PD0) Port D is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATtiny2313 as listed on page
56.
RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page
34. Shorter pulses are not guaranteed to generate a reset. The Reset Input is an alternate function
for PA2 and dW.
XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. XTAL1
is an alternate function for PA0.
XTAL2 Output from the inverting Oscillator amplifier. XTAL2 is an alternate function for PA1.6
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ATtiny2313
General
Information
Resources A comprehensive set of development tools, application notes and datasheets are available for
downloadon http://www.atmel.com/avr.
Code Examples This documentation contains simple code examples that briefly show how to use various parts of
the device. These code examples assume that the part specific header file is included before
compilation. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation
for more details.
Disclaimer Typical values contained in this data sheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max values
will be available after the device is characterized.7
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ATtiny2313
AVR CPU Core
Introduction This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
Architectural
Overview
Figure 3. Block Diagram of the AVR Architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruction
is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical
ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle.
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
Direct Addressing
Indirect Addressing
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
I/O Module 2
I/O Module1
I/O Module n8
2543L–AVR–08/10
ATtiny2313
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointers
can also be used as an address pointer for look up tables in Flash program memory. These
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single register operations can also be executed in the ALU. After an arithmetic operation,
the Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most AVR instructions have a single 16-bit word format.
Every program memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack
Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position.
The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers,
and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space
locations following those of the Register File, 0x20 - 0x5F.
ALU – Arithmetic
Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general purpose
registers or between a register and an immediate are executed. The ALU operations are divided
into three main categories – arithmetic, logical, and bit-functions. Some implementations of the
architecture also provide a powerful multiplier supporting both signed/unsigned multiplication
and fractional format. See the “Instruction Set” section for a detailed description.
Status Register The Status Register contains information about the result of the most recently executed arithmetic
instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the Instruction Set Reference. This will in many cases remove the need for using the
dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored
when returning from an interrupt. This must be handled by software.9
2543L–AVR–08/10
ATtiny2313
The AVR Status Register – SREG – is defined as:
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt
enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination
for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful
in BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the negative flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
General Purpose
Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve
the required performance and flexibility, the following input/output schemes are supported by the
Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 4 shows the structure of the 32 general purpose working registers in the CPU.
Bit 7 6 5 4 3 2 1 0
I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 010
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ATtiny2313
Figure 4. AVR CPU General Purpose Working Registers
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 4, each register is also assigned a data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically implemented
as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
The X-register, Yregister,
and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers
are 16-bit address pointers for indirect addressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in Figure 5.
Figure 5. The X-, Y-, and Z-registers
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
7 0 Addr.
R0 0x00
R1 0x01
R2 0x02
…
R13 0x0D
General R14 0x0E
Purpose R15 0x0F
Working R16 0x10
Registers R17 0x11
…
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte
15 XH XL 0
X-register 7 0 7 0
R27 (0x1B) R26 (0x1A)
15 YH YL 0
Y-register 7 0 7 0
R29 (0x1D) R28 (0x1C)
15 ZH ZL 0
Z-register 7 0 7 0
R31 (0x1F) R30 (0x1E)11
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ATtiny2313
Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations
to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack
with the PUSH instruction, and it is decremented by two when the return address is pushed onto
the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is incremented by two when data is
popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementations
of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
Instruction
Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the
chip. No internal clock division is used.
Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Harvard
architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 6. The Parallel Instruction Fetches and Instruction Executions
Figure 7 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destination
register.
Bit 15 14 13 12 11 10 9 8
– – – – – – – – SPH
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R R R R R R R R
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU12
2543L–AVR–08/10
ATtiny2313
Figure 7. Single Cycle ALU Operation
Reset and
Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt.
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 44. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. Refer to “Interrupts” on page 44 for more information.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled.
The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
interrupt flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector
in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt
flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be
cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared,
the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared
by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable
bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global
Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clkCPU13
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ATtiny2313
CLI instruction. The following example shows how this can be used to avoid interrupts during the
timed EEPROM write sequence..
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed
before any pending interrupts, as shown in this example.
Interrupt Response
Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum.
After four clock cycles the program vector address for the actual interrupt handling routine
is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack.
The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If
an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed
before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt
execution response time is increased by four clock cycles. This increase comes in addition to the
start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock
cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is
incremented by two, and the I-bit in SREG is set.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
__disable_interrupt();
EECR |= (1< xxx
... ... ... ... 46
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ATtiny2313
I/O-Ports
Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.
This means that the direction of one port pin can be changed without unintentionally changing
the direction of any other pin with the SBI and CBI instructions. The same applies when changing
drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as
input). Each output buffer has symmetrical drive characteristics with both high sink and source
capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually
selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have
protection diodes to both VCC and Ground as indicated in Figure 21. Refer to “Electrical Characteristics”
on page 177 for a complete list of parameters.
Figure 21. I/O Pin Equivalent Schematic
All registers and bit references in this section are written in general form. A lower case “x” represents
the numbering letter for the port, and a lower case “n” represents the bit number. However,
when using the register or bit defines in a program, the precise form must be used. For example,
PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Registers
and bit locations are listed in “Register Description for I/O-Ports” on page 58.
Three I/O memory address locations are allocated for each port, one each for the Data Register
– PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins
I/O location is read only, while the Data Register and the Data Direction Register are read/write.
However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding
bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the
pull-up function for all pins in all ports when set.
Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page
47. Most port pins are multiplexed with alternate functions for the peripheral features on the
device. How each alternate function interferes with the port pin is described in “Alternate Port
Functions” on page 51. Refer to the individual module sections for a full description of the alternate
functions.
Note that enabling the alternate function of some of the port pins does not affect the use of the
other pins in the port as general digital I/O.
Cpin
Logic
Rpu
See Figure
"General Digital I/O" for
Details
Pxn47
2543L–AVR–08/10
ATtiny2313
Ports as General
Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 22 shows a functional
description of one I/O-port pin, here generically called Pxn.
Figure 22. General Digital I/O(1)
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,
SLEEP, and PUD are common to all ports.
Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register
Description for I/O-Ports” on page 58, the DDxn bits are accessed at the DDRx I/O address, the
PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to
be configured as an output pin. The port pins are tri-stated when reset condition becomes active,
even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven
high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port
pin is driven low (zero).
Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
Note that the SBI instruction can be used to toggle one single bit in a port.
clk
RPx
RRx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
PUD: PULLUP DISABLE
clkI/O: I/O CLOCK
RDx: READ DDRx
D
L
Q
Q
RESET
RESET
Q
D Q
Q
Q D
CLR
PORTxn
Q
Q D
CLR
DDxn
PINxn
DATA BUS
SLEEP
SLEEP: SLEEP CONTROL
Pxn
I/O
WPx
0
1
WRx
WPx: WRITE PINx REGISTER48
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Switching Between
Input and Output
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}
= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output
low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable,
as a high-impedant environment will not notice the difference between a strong high driver
and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all
pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}
= 0b11) as an intermediate step.
Table 22 summarizes the control signals for the pin value.
Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in Figure 22, the PINxn Register bit and the preceding latch constitute
a synchronizer. This is needed to avoid metastability if the physical pin changes value near
the edge of the internal clock, but it also introduces a delay. Figure 23 shows a timing diagram of
the synchronization when reading an externally applied pin value. The maximum and minimum
propagation delays are denoted tpd,max and tpd,min respectively.
Figure 23. Synchronization when Reading an Externally Applied Pin value
Table 22. Port Pin Configurations
DDxn PORTxn
PUD
(in MCUCR) I/O Pull-up Comment
0 0 X Input No Tri-state (Hi-Z)
0 1 0 Input Yes
Pxn will source current if ext. pulled
low.
0 1 1 Input No Tri-state (Hi-Z)
1 0 X Output No Output Low (Sink)
1 1 X Output No Output High (Source)
XXX in r17, PINx
0x00 0xFF
INSTRUCTIONS
SYNC LATCH
PINxn
r17
XXX
SYSTEM CLK
tpd, max
tpd, min49
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ATtiny2313
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated
by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed
between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indicated
in Figure 24. The out instruction sets the “SYNC LATCH” signal at the positive edge of the
clock. In this case, the delay tpd through the synchronizer is 1 system clock period.
Figure 24. Synchronization when Reading a Software Assigned Pin Value
out PORTx, r16 nop in r17, PINx
0xFF
0x00 0xFF
SYSTEM CLK
r16
INSTRUCTIONS
SYNC LATCH
PINxn
r17
t pd50
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The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define
the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin
values are read back again, but as previously discussed, a nop instruction is included to be able
to read back the value recently assigned to some of the pins.
Note: 1. For the assembly program, two temporary registers are used to minimize the time from pullups
are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3
as low and redefining bits 0 and 1 as strong high drivers.
Digital Input Enable
and Sleep Modes
As shown in Figure 22, the digital input signal can be clamped to ground at the input of the
Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in
Power-down mode, and Standby mode to avoid high power consumption if some input signals
are left floating, or have an analog signal level close to VCC/2.
SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt
request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various
other alternate functions as described in “Alternate Port Functions” on page 51.
If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as
“Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt
is not enabled, the corresponding External Interrupt Flag will be set when resuming from the
above mentioned Sleep mode, as the clamping in these sleep mode produces the requested
logic change.
Assembly Code Example(1)
...
; Define pull-ups and set outputs high
; Define directions for port pins
ldi r16,(1<