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Farnell PDF
LPC178x/7x - NXP Semiconductors - Farnell - Farnell Element 14
LPC178x/7x - NXP Semiconductors - Farnell - Farnell Element 14
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Farnell Element 14 :
See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…
Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.
Puce électronique / Microchip :
Sans fil - Wireless :
Texas instrument :
Ordinateurs :
Logiciels :
Tutoriels :
Autres documentations :
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Analog-Devices-ADC-S..> 09-Sep-2014 08:21 2.4M
Analog-Devices-ADMC2..> 09-Sep-2014 08:21 2.4M
Analog-Devices-ADMC4..> 09-Sep-2014 08:23 2.3M
Analog-Devices-AN300..> 08-Sep-2014 17:42 2.0M
Analog-Devices-ANF32..> 09-Sep-2014 08:18 2.6M
Analog-Devices-Basic..> 08-Sep-2014 17:49 1.9M
Analog-Devices-Compl..> 08-Sep-2014 17:38 2.0M
Analog-Devices-Convo..> 09-Sep-2014 08:26 2.1M
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Analog-Devices-Gloss..> 08-Sep-2014 17:36 2.0M
Analog-Devices-Intro..> 08-Sep-2014 17:39 1.9M
Analog-Devices-The-C..> 08-Sep-2014 17:41 1.9M
Analog-Devices-Visua..> 09-Sep-2014 08:18 2.5M
Analog-Devices-Wi-Fi..> 09-Sep-2014 08:23 2.3M
Electronique-Basic-o..> 08-Sep-2014 17:43 1.8M
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1. General description
The LPC178x/7x is an ARM Cortex-M3 based microcontroller for embedded applications
requiring a high level of integration and low power dissipation.
The ARM Cortex-M3 is a next generation core that offers better performance than the
ARM7 at the same clock rate and other system enhancements such as modernized
debug features and a higher level of support block integration. The ARM Cortex-M3 CPU
incorporates a 3-stage pipeline and has a Harvard architecture with separate local
instruction and data buses, as well as a third bus with slightly lower performance for
peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that
supports speculative branches.
The LPC178x/7x adds a specialized flash memory accelerator to accomplish optimal
performance when executing code from flash. The LPC178x/7x operates at up to
120 MHz CPU frequency.
The peripheral complement of the LPC178x/7x includes up to 512 kB of flash program
memory, up to 96 kB of SRAM data memory, up to 4032 byte of EEPROM data memory,
External Memory Controller (EMC), LCD (LPC178x only), Ethernet, USB
Device/Host/OTG, a General Purpose DMA controller, five UARTs, three SSP controllers,
three I2C-bus interfaces, a Quadrature Encoder Interface, four general purpose timers,
two general purpose PWMs with six outputs each and one motor control PWM, an
ultra-low power RTC with separate battery supply and event recorder, a windowed
watchdog timer, a CRC calculation engine, up to 165 general purpose I/O pins, and more.
The analog peripherals include one eight-channel 12-bit ADC and a 10-bit DAC.
The pinout of LPC178x/7x is intended to allow pin function compatibility with the LPC24xx
and LPC23xx.
For additional documentation, see Section 18 “References”.
2. Features and benefits
Functional replacement for the LPC23xx and LPC24xx family devices.
System:
ARM Cortex-M3 processor, running at frequencies of up to 120 MHz. A Memory
Protection Unit (MPU) supporting eight regions is included.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
LPC178x/7x
32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and
96 kB SRAM; USB Device/Host/OTG; Ethernet; LCD; EMC
Rev. 5 — 9 September 2014 Product data sheetLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 2 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
Multilayer AHB matrix interconnect provides a separate bus for each AHB master.
AHB masters include the CPU, USB, Ethernet, and the General Purpose DMA
controller. This interconnect provides communication with no arbitration delays
unless two masters attempt to access the same slave at the same time.
Split APB bus allows for higher throughput with fewer stalls between the CPU and
DMA. A single level of write buffering allows the CPU to continue without waiting for
completion of APB writes if the APB was not already busy.
Cortex-M3 system tick timer, including an external clock input option.
Standard JTAG test/debug interface as well as Serial Wire Debug and Serial
WireTrace Port options.
Embedded Trace Macrocell (ETM) module supports real-time trace.
Boundary scan for simplified board testing.
Non-maskable Interrupt (NMI) input.
Memory:
Up to 512 kB on-chip flash program memory with In-System Programming (ISP)
and In-Application Programming (IAP) capabilities. The combination of an
enhanced flash memory accelerator and location of the flash memory on the CPU
local code/data bus provides high code performance from flash.
Up to 96 kB on-chip SRAM includes:
64 kB of main SRAM on the CPU with local code/data bus for high-performance
CPU access.
Two 16 kB peripheral SRAM blocks with separate access paths for higher
throughput. These SRAM blocks may be used for DMA memory as well as for
general purpose instruction and data storage.
Up to 4032 byte on-chip EEPROM.
LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-Film
Transistors (TFT) displays.
Dedicated DMA controller.
Selectable display resolution (up to 1024 768 pixels).
Supports up to 24-bit true-color mode.
External Memory Controller (EMC) provides support for asynchronous static memory
devices such as RAM, ROM and flash, as well as dynamic memories such as single
data rate SDRAM with an SDRAM clock of up to 80 MHz.
Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer
matrix that can be used with the SSP, I2S, UART, CRC engine, Analog-to-Digital and
Digital-to-Analog converter peripherals, timer match signals, GPIO, and for
memory-to-memory transfers.
Serial interfaces:
Ethernet MAC with MII/RMII interface and associated DMA controller. These
functions reside on an independent AHB.
USB 2.0 full-speed dual-port device/host/OTG controller with on-chip PHY and
associated DMA controller.
Five UARTs with fractional baud rate generation, internal FIFO, DMA support, and
RS-485/EIA-485 support. One UART (UART1) has full modem control I/O, and one
UART (USART4) supports IrDA, synchronous mode, and a smart card mode
conforming to ISO7816-3.
Three SSP controllers with FIFO and multi-protocol capabilities. The SSP
controllers can be used with the GPDMA.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 3 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
Three enhanced I2C-bus interfaces, one with a true open-drain output supporting
the full I2C-bus specification and Fast-mode Plus with data rates of 1 Mbit/s, two
with standard port pins. Enhancements include multiple address recognition and
monitor mode.
I
2S-bus (Inter-IC Sound) interface for digital audio input or output. It can be used
with the GPDMA.
CAN controller with two channels.
Digital peripherals:
SD/MMC memory card interface.
Up to 165 General Purpose I/O (GPIO) pins depending on the packaging with
configurable pull-up/down resistors, open-drain mode, and repeater mode. All
GPIOs are located on an AHB bus for fast access and support Cortex-M3
bit-banding. GPIOs can be accessed by the General Purpose DMA Controller. Any
pin of ports 0 and 2 can be used to generate an interrupt.
Two external interrupt inputs configurable as edge/level sensitive. All pins on port 0
and port 2 can be used as edge sensitive interrupt sources.
Four general purpose timers/counters with a total of eight capture inputs and ten
compare outputs. Each timer block has an external count input. Specific timer
events can be selected to generate DMA requests.
Quadrature encoder interface that can monitor one external quadrature encoder.
Two standard PWM/timer blocks with external count input option.
One motor control PWM with support for three-phase motor control.
Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by a
dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered
backup registers, allowing system status to be stored when the rest of the chip is
powered off. Battery power can be supplied from a standard 3 V lithium button cell.
The RTC will continue working when the battery voltage drops to as low as 2.1 V.
An RTC interrupt can wake up the CPU from any reduced power mode.
Event Recorder that can capture the clock value when an event occurs on any of
three inputs. The event identification and the time it occurred are stored in
registers. The Event Recorder is located in the RTC power domain and can
therefore operate as long as there is RTC power.
Windowed Watchdog Timer (WWDT). Windowed operation, dedicated internal
oscillator, watchdog warning interrupt, and safety features.
CRC Engine block can calculate a CRC on supplied data using one of three
standard polynomials. The CRC engine can be used in conjunction with the DMA
controller to generate a CRC without CPU involvement in the data transfer.
Analog peripherals:
12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins,
conversion rates up to 400 kHz, and multiple result registers. The 12-bit ADC can
be used with the GPDMA controller.
10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and
GPDMA support.
Power control:
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 4 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up
from any priority interrupt that can occur while the clocks are stopped in
Deep-sleep, Power-down, and Deep power-down modes.
Processor wake-up from Power-down mode via any interrupt able to operate
during Power-down mode (includes external interrupts, RTC interrupt, PORT0/2
pin interrupt, and NMI).
Brownout detect with separate threshold for interrupt and forced reset.
On-chip Power-On Reset (POR).
Clock generation:
Clock output function that can reflect the main oscillator clock, IRC clock, RTC
clock, CPU clock, USB clock, or the watchdog timer clock.
On-chip crystal oscillator with an operating range of 1 MHz to 25 MHz.
12 MHz Internal RC oscillator (IRC) trimmed to 1% accuracy that can optionally be
used as a system clock.
An on-chip PLL allows CPU operation up to the maximum CPU rate without the
need for a high-frequency crystal. May be run from the main oscillator or the
internal RC oscillator.
A second, dedicated PLL may be used for USB interface in order to allow added
flexibility for the Main PLL settings.
Versatile pin function selection feature allows many possibilities for using on-chip
peripheral functions.
Unique device serial number for identification purposes.
Single 3.3 V power supply (2.4 V to 3.6 V). Temperature range of 40 C to 85 C.
Available as LQFP208, TFBGA208, TFBGA180, and LQFP144 package.
3. Applications
Communications:
Point-of-sale terminals, web servers, multi-protocol bridges
Industrial/Medical:
Automation controllers, application control, robotics control, HVAC, PLC, inverters,
circuit breakers, medical scanning, security monitoring, motor drive, video intercom
Consumer/Appliance:
Audio, MP3 decoders, alarm systems, displays, printers, scanners, small
appliances, fitness equipment
Automotive:
After-market, car alarms, GPS/fleet monitorsLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 5 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
4. Ordering information
Table 1. Ordering information
Type number Package
Name Description Version
LPC1788
LPC1788FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC1788FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body
15 ´ 15 ´ 0.7 mm
SOT950-1
LPC1788FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3
LPC1788FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC1787
LPC1787FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC1786
LPC1786FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC1785
LPC1785FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC1778
LPC1778FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC1778FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body
15 ´ 15 ´ 0.7 mm
SOT950-1
LPC1778FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3
LPC1778FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC1777
LPC1777FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC1776
LPC1776FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC1776FET180 TFBGA180 thin fine-pitch ball grid array package; 180 balls; body 12 ´ 12 ´ 0.8 mm SOT570-3
LPC1774
LPC1774FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm SOT459-1
LPC1774FBD144 LQFP144 plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 6 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
[1] Maximum data bus width of the External Memory Controller (EMC) depends on package size. Smaller widths may be used.
[2] USART4 not available.
Table 2. LPC178x/7x ordering options
All parts include two CAN channels, three SSP interfaces, three I2C interfaces, one I2S interface, DAC, and an 8-channel
12-bit ADC.
Type number Flash
(kB)
Main
SRAM
(kB)
Peripheral
SRAM
(kB)
Total
SRAM
(kB)
EEPROM
(byte)
Ethernet USB UART EMC
bus
width
(bit)
[1]
LCD QEI SD/
MMC
LPC178x
LPC1788FBD208 512 64 16 2 96 4032 Y H/O/D 5 32 Y Y Y
LPC1788FET208 512 64 16 2 96 4032 Y H/O/D 5 32 Y Y Y
LPC1788FET180 512 64 16 2 96 4032 Y H/O/D 5 16 Y Y Y
LPC1788FBD144 512 64 16 2 96 4032 Y H/O/D 5 8 Y Y Y
LPC1787FBD208 512 64 16 2 96 4032 N H/O/D 5 32 Y Y Y
LPC1786FBD208 256 64 16 80 4032 Y H/O/D 5 32 Y Y Y
LPC1785FBD208 256 64 16 80 4032 N H/O/D 5 32 Y N Y
LPC177x
LPC1778FBD208 512 64 16 2 96 4032 Y H/O/D 5 32 N Y Y
LPC1778FET208 512 64 16 2 96 4032 Y H/O/D 5 32 N Y Y
LPC1778FET180 512 64 16 2 96 4032 Y H/O/D 5 16 N Y Y
LPC1778FBD144 512 64 16 2 96 4032 Y H/O/D 5 8 N Y Y
LPC1777FBD208 512 64 16 2 96 4032 N H/O/D 5 32 N Y Y
LPC1776FBD208 256 64 16 80 4032 Y H/O/D 5 32 N Y Y
LPC1776FET180 256 64 16 80 4032 Y H/O/D 5 16 N Y Y
LPC1774FBD208 128 32 8 40 2048 N D 5 32 N N N
LPC1774FBD144 128 32 8 40 2048 N D 4[2] 8 N N NLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 7 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
5. Block diagram
(1) Not available on all parts. See Table 2.
Fig 1. Block diagram
SRAM
96/80/40 kB
ARM
CORTEX-M3
TEST/DEBUG
INTERFACE
EMULATION
TRACE MODULE
FLASH
ACCELERATOR
FLASH
512/256/128/64 kB
GPDMA
CONTROLLER
I-code
bus
D-code
bus
system
bus
AHB TO
APB
BRIDGE 0
HIGH-SPEED
GPIO AHB TO
APB
BRIDGE 1
4032 B/
2048 B
EEPROM
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
clocks and
controls
JTAG
interface
debug
port
SSP0/2
USART4(1)
UART2/3
SYSTEM CONTROL
SSP1
UART0/1
I
2C0/1
CAN 0/1
TIMER 0/1
WINDOWED WDT
12-bit ADC
PWM0/1
PIN CONNECT
GPIO INTERRUPT CONTROL
RTC
BACKUP REGISTERS
EVENT RECORDER
32 kHz
OSCILLATOR
APB slave group 1
APB slave group 0
RTC POWER DOMAIN
LPC178x/7x
master
ETHERNET(1)
master
USB
DEVICE/
HOST(1)/OTG(1)
master
002aaf528
slave slave
CRC
slave slave slave
slave
EMC ROM
slave slave
LCD(1)
slave
MULTILAYER AHB MATRIX
I
2C2
TIMER2/3
DAC
I
2S
QUADRATURE ENCODER(1)
MOTOR CONTROL PWM
MPU
SD/MMC(1)
= connected to GPDMALPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 8 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
6. Pinning information
6.1 Pinning
Fig 2. Pin configuration (LQFP208)
Fig 3. Pin configuration (TFBGA208)
LPC178x/7xFBD208
156
53
104
208
157
105
1
52
002aaf518
002aaf529
LPC178x/7x
Transparent top view
ball A1
index area
U
T
R
P
N
M
K
H
L
J
G
F
E
D
C
A
B
2 4 6 8 10 12
13
14
15 17
16
1 3 5 7 9 11LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 9 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
6.2 Pin description
I/O pins on the LPC178x/7x are 5 V tolerant and have input hysteresis unless otherwise
indicated in the table below. Crystal pins, power pins, and reference voltage pins are not
5 V tolerant. In addition, when pins are selected to be ADC inputs, they are no longer 5 V
tolerant and the input voltage must be limited to the voltage at the ADC positive reference
pin (VREFP).
All port pins Pn[m] are multiplexed, and the multiplexed functions appear in Table 3 in the
order defined by the FUNC bits of the corresponding IOCON register up to the highest
used function number. Each port pin can support up to eight multiplexed functions.
IOCON register FUNC values which are reserved are noted as ‘R’ in the pin configuration
table.
Fig 4. Pin configuration (TFBGA180)
Fig 5. Pin configuration (LQFP144)
002aaf519
LPC178x/7x
1 3 5 7 9 11 2 4 6 8 10 12 13 14
ball A1
index area
P
N
M
L
K
J
G
E
H
F
D
C
B
A
Transparent top view
LPC178x/7x
108
37
72
144
109
73
1
36
002aaf520LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 10 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
Table 3. Pin description
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Reset state[1]
Type[2]
Description
P0[0] to
P0[31]
I/O Port 0: Port 0 is a 32-bit I/O port with individual direction
controls for each bit. The operation of port 0 pins depends upon
the pin function selected via the pin connect block.
P0[0] 94 U15 M10 66 [3] I;
PU
I/O P0[0] — General purpose digital input/output pin.
I CAN_RD1 — CAN1 receiver input.
O U3_TXD — Transmitter output for UART3.
I/O I2C1_SDA — I
2C1 data input/output (this pin does not use a
specialized I2C pad).
O U0_TXD — Transmitter output for UART0.
P0[1] 96 T14 N11 67 [3] I;
PU
I/O P0[1] — General purpose digital input/output pin.
O CAN_TD1 — CAN1 transmitter output.
I U3_RXD — Receiver input for UART3.
I/O I2C1_SCL — I
2C1 clock input/output (this pin does not use a
specialized I2C pad).
I U0_RXD — Receiver input for UART0.
P0[2] 202 C4 D5 141 [3] I;
PU
I/O P0[2] — General purpose digital input/output pin.
O U0_TXD — Transmitter output for UART0.
O U3_TXD — Transmitter output for UART3.
P0[3] 204 D6 A3 142 [3] I;
PU
I/O P0[3] — General purpose digital input/output pin.
I U0_RXD — Receiver input for UART0.
I U3_RXD — Receiver input for UART3.
P0[4] 168 B12 A11 116 [3] I;
PU
I/O P0[4] — General purpose digital input/output pin.
I/O I2S_RX_SCK — I
2S Receive clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in the
I
2S-bus specification.
I CAN_RD2 — CAN2 receiver input.
I T2_CAP0 — Capture input for Timer 2, channel 0.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
O LCD_VD[0] — LCD data.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 11 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
P0[5] 166 C12 B11 115 [3] I;
PU
I/O P0[5] — General purpose digital input/output pin.
I/O I2S_RX_WS — I
2S Receive word select. It is driven by the
master and received by the slave. Corresponds to the signal WS
in the I
2S-bus specification.
O CAN_TD2 — CAN2 transmitter output.
I T2_CAP1 — Capture input for Timer 2, channel 1.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
O LCD_VD[1] — LCD data.
P0[6] 164 D13 D11 113 [3] I;
PU
I/O P0[6] — General purpose digital input/output pin.
I/O I2S_RX_SDA — I
2S Receive data. It is driven by the transmitter
and read by the receiver. Corresponds to the signal SD in the
I
2S-bus specification.
I/O SSP1_SSEL — Slave Select for SSP1.
O T2_MAT0 — Match output for Timer 2, channel 0.
O U1_RTS — Request to Send output for UART1. Can also be
configured to be an RS-485/EIA-485 output enable signal for
UART1.
- R — Function reserved.
- R — Function reserved.
O LCD_VD[8] — LCD data.
P0[7] 162 C13 B12 112 [4] I; IA I/O P0[7] — General purpose digital input/output pin.
I/O I2S_TX_SCK — I
2S transmit clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in the
I
2S-bus specification.
I/O SSP1_SCK — Serial Clock for SSP1.
O T2_MAT1 — Match output for Timer 2, channel 1.
I RTC_EV0 — Event input 0 to Event Monitor/Recorder.
- R — Function reserved.
- R — Function reserved.
O LCD_VD[9] — LCD data.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Reset state[1]
Type[2]
DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 12 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
P0[8] 160 A15 C12 111 [4] I; IA I/O P0[8] — General purpose digital input/output pin.
I/O I2S_TX_WS — I
2S Transmit word select. It is driven by the
master and received by the slave. Corresponds to the signal WS
in the I
2S-bus specification.
I/O SSP1_MISO — Master In Slave Out for SSP1.
O T2_MAT2 — Match output for Timer 2, channel 2.
I RTC_EV1 — Event input 1 to Event Monitor/Recorder.
- R — Function reserved.
- R — Function reserved.
O LCD_VD[16] — LCD data.
P0[9] 158 C14 A13 109 [4] I; IA I/O P0[9] — General purpose digital input/output pin.
I/O I2S_TX_SDA — I
2S transmit data. It is driven by the transmitter
and read by the receiver. Corresponds to the signal SD in the
I
2S-bus specification.
I/O SSP1_MOSI — Master Out Slave In for SSP1.
O T2_MAT3 — Match output for Timer 2, channel 3.
I RTC_EV2 — Event input 2 to Event Monitor/Recorder.
- R — Function reserved.
- R — Function reserved.
O LCD_VD[17] — LCD data.
P0[10] 98 T15 L10 69 [3] I;
PU
I/O P0[10] — General purpose digital input/output pin.
O U2_TXD — Transmitter output for UART2.
I/O I2C2_SDA — I
2C2 data input/output (this pin does not use a
specialized I2C pad).
O T3_MAT0 — Match output for Timer 3, channel 0.
P0[11] 100 R14 P12 70 [3] I;
PU
I/O P0[11] — General purpose digital input/output pin.
I U2_RXD — Receiver input for UART2.
I/O I2C2_SCL — I
2C2 clock input/output (this pin does not use a
specialized I2C pad).
O T3_MAT1 — Match output for Timer 3, channel 1.
P0[12] 41 R1 J4 29 [5] I;
PU
I/O P0[12] — General purpose digital input/output pin.
O USB_PPWR2 — Port Power enable signal for USB port 2.
I/O SSP1_MISO — Master In Slave Out for SSP1.
I ADC0_IN[6] — A/D converter 0, input 6. When configured as an
ADC input, the digital function of the pin must be disabled.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Reset state[1]
Type[2]
DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 13 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
P0[13] 45 R2 J5 32 [5] I;
PU
I/O P0[13] — General purpose digital input/output pin.
O USB_UP_LED2 — USB port 2 GoodLink LED indicator. It is
LOW when the device is configured (non-control endpoints
enabled), or when the host is enabled and has detected a
device on the bus. It is HIGH when the device is not configured,
or when host is enabled and has not detected a device on the
bus, or during global suspend. It transitions between LOW and
HIGH (flashes) when the host is enabled and detects activity on
the bus.
I/O SSP1_MOSI — Master Out Slave In for SSP1.
I ADC0_IN[7] — A/D converter 0, input 7. When configured as an
ADC input, the digital function of the pin must be disabled.
P0[14] 69 T7 M5 48 [3] I;
PU
I/O P0[14] — General purpose digital input/output pin.
O USB_HSTEN2 — Host Enabled status for USB port 2.
I/O SSP1_SSEL — Slave Select for SSP1.
O USB_CONNECT2 — SoftConnect control for USB port 2.
Signal used to switch an external 1.5 k resistor under software
control. Used with the SoftConnect USB feature.
P0[15] 128 J16 H13 89 [3] I;
PU
I/O P0[15] — General purpose digital input/output pin.
O U1_TXD — Transmitter output for UART1.
I/O SSP0_SCK — Serial clock for SSP0.
P0[16] 130 J14 H14 90 [3] I;
PU
I/O P0[16] — General purpose digital input/output pin.
I U1_RXD — Receiver input for UART1.
I/O SSP0_SSEL — Slave Select for SSP0.
P0[17] 126 K17 J12 87 [3] I;
PU
I/O P0[17] — General purpose digital input/output pin.
I U1_CTS — Clear to Send input for UART1.
I/O SSP0_MISO — Master In Slave Out for SSP0.
P0[18] 124 K15 J13 86 [3] I;
PU
I/O P0[18] — General purpose digital input/output pin.
I U1_DCD — Data Carrier Detect input for UART1.
I/O SSP0_MOSI — Master Out Slave In for SSP0.
P0[19] 122 L17 J10 85 [3] I;
PU
I/O P0[19] — General purpose digital input/output pin.
I U1_DSR — Data Set Ready input for UART1.
O SD_CLK — Clock output line for SD card interface.
I/O I2C1_SDA — I
2C1 data input/output (this pin does not use a
specialized I2C pad).
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Reset state[1]
Type[2]
DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 14 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
P0[20] 120 M17 K14 83 [3] I;
PU
I/O P0[20] — General purpose digital input/output pin.
O U1_DTR — Data Terminal Ready output for UART1. Can also
be configured to be an RS-485/EIA-485 output enable signal for
UART1.
I/O SD_CMD — Command line for SD card interface.
I/O I2C1_SCL — I
2C1 clock input/output (this pin does not use a
specialized I2C pad).
P0[21] 118 M16 K11 82 [3] I;
PU
I/O P0[21] — General purpose digital input/output pin.
I U1_RI — Ring Indicator input for UART1.
O SD_PWR — Power Supply Enable for external SD card power
supply.
O U4_OE — RS-485/EIA-485 output enable signal for UART4.
I CAN_RD1 — CAN1 receiver input.
I/O U4_SCLK — USART 4 clock input or output in synchronous
mode.
P0[22] 116 N17 L14 80 [6] I;
PU
I/O P0[22] — General purpose digital input/output pin.
O U1_RTS — Request to Send output for UART1. Can also be
configured to be an RS-485/EIA-485 output enable signal for
UART1.
I/O SD_DAT[0] — Data line 0 for SD card interface.
O U4_TXD — Transmitter output for USART4 (input/output in
smart card mode).
O CAN_TD1 — CAN1 transmitter output.
P0[23] 18 H1 F5 13 [5] I;
PU
I/O P0[23] — General purpose digital input/output pin.
I ADC0_IN[0] — A/D converter 0, input 0. When configured as an
ADC input, the digital function of the pin must be disabled.
I/O I2S_RX_SCK — Receive Clock. It is driven by the master and
received by the slave. Corresponds to the signal SCK in the
I
2S-bus specification.
I T3_CAP0 — Capture input for Timer 3, channel 0.
P0[24] 16 G2 E1 11 [5] I;
PU
I/O P0[24] — General purpose digital input/output pin.
I ADC0_IN[1] — A/D converter 0, input 1. When configured as an
ADC input, the digital function of the pin must be disabled.
I/O I2S_RX_WS — Receive Word Select. It is driven by the master
and received by the slave. Corresponds to the signal WS in the
I
2S-bus specification.
I T3_CAP1 — Capture input for Timer 3, channel 1.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Reset state[1]
Type[2]
DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 15 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
P0[25] 14 F1 E4 10 [5] I;
PU
I/O P0[25] — General purpose digital input/output pin.
I ADC0_IN[2] — A/D converter 0, input 2. When configured as an
ADC input, the digital function of the pin must be disabled.
I/O I2S_RX_SDA — Receive data. It is driven by the transmitter
and read by the receiver. Corresponds to the signal SD in the
I
2S-bus specification.
O U3_TXD — Transmitter output for UART3.
P0[26] 12 E1 D1 8 [7] I;
PU
I/O P0[26] — General purpose digital input/output pin.
I ADC0_IN[3] — A/D converter 0, input 3. When configured as an
ADC input, the digital function of the pin must be disabled.
O DAC_OUT — D/A converter output. When configured as the
DAC output, the digital function of the pin must be disabled.
I U3_RXD — Receiver input for UART3.
P0[27] 50 T1 L3 35 [8] I I/O P0[27] — General purpose digital input/output pin.
I/O I2C0_SDA — I
2C0 data input/output (this pin uses a specialized
I2C pad).
I/O USB_SDA1 — I2C serial data for communication with an
external USB transceiver.
P0[28] 48 R3 M1 34 [8] I I/O P0[28] — General purpose digital input/output pin.
I/O I2C0_SCL — I
2C0 clock input/output (this pin uses a
specialized I2C pad).
I/O USB_SCL1 — I2C serial clock for communication with an
external USB transceiver.
P0[29] 61 U4 K5 42 [9] I I/O P0[29] — General purpose digital input/output pin.
I/O USB_D+1 — USB port 1 bidirectional D+ line.
I EINT0 — External interrupt 0 input.
P0[30] 62 R6 N4 43 [9] I I/O P0[30] — General purpose digital input/output pin.
I/O USB_D1 — USB port 1 bidirectional D line.
I EINT1 — External interrupt 1 input.
P0[31] 51 T2 N1 36 [9] I I/O P0[31] — General purpose digital input/output pin.
I/O USB_D+2 — USB port 2 bidirectional D+ line.
P1[0] to
P1[31]
I/O Port 1: Port 1 is a 32 bit I/O port with individual direction
controls for each bit. The operation of port 1 pins depends upon
the pin function selected via the pin connect block
P1[0] 196 A3 B5 136 [3] I;
PU
I/O P1[0] — General purpose digital input/output pin.
O ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface).
- R — Function reserved.
I T3_CAP1 — Capture input for Timer 3, channel 1.
I/O SSP2_SCK — Serial clock for SSP2.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Reset state[1]
Type[2]
DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 16 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
P1[1] 194 B5 A5 135 [3] I;
PU
I/O P1[1] — General purpose digital input/output pin.
O ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface).
- R — Function reserved.
O T3_MAT3 — Match output for Timer 3, channel 3.
I/O SSP2_MOSI — Master Out Slave In for SSP2.
P1[2] 185 D9 B7 - [3] I;
PU
I/O P1[2] — General purpose digital input/output pin.
O ENET_TXD2 — Ethernet transmit data 2 (MII interface).
O SD_CLK — Clock output line for SD card interface.
O PWM0[1] — Pulse Width Modulator 0, output 1.
P1[3] 177 A10 A9 - [3] I;
PU
I/O P1[3] — General purpose digital input/output pin.
O ENET_TXD3 — Ethernet transmit data 3 (MII interface).
I/O SD_CMD — Command line for SD card interface.
O PWM0[2] — Pulse Width Modulator 0, output 2.
P1[4] 192 A5 C6 133 [3] I;
PU
I/O P1[4] — General purpose digital input/output pin.
O ENET_TX_EN — Ethernet transmit data enable (RMII/MII
interface).
- R — Function reserved.
O T3_MAT2 — Match output for Timer 3, channel 2.
I/O SSP2_MISO — Master In Slave Out for SSP2.
P1[5] 156 A17 B13 - [3] I;
PU
I/O P1[5] — General purpose digital input/output pin.
O ENET_TX_ER — Ethernet Transmit Error (MII interface).
O SD_PWR — Power Supply Enable for external SD card power
supply.
O PWM0[3] — Pulse Width Modulator 0, output 3.
P1[6] 171 B11 B10 - [3] I;
PU
I/O P1[6] — General purpose digital input/output pin.
I ENET_TX_CLK — Ethernet Transmit Clock (MII interface).
I/O SD_DAT[0] — Data line 0 for SD card interface.
O PWM0[4] — Pulse Width Modulator 0, output 4.
P1[7] 153 D14 C13 - [3] I;
PU
I/O P1[7] — General purpose digital input/output pin.
I ENET_COL — Ethernet Collision detect (MII interface).
I/O SD_DAT[1] — Data line 1 for SD card interface.
O PWM0[5] — Pulse Width Modulator 0, output 5.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Reset state[1]
Type[2]
DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 17 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
P1[8] 190 C7 B6 132 [3] I;
PU
I/O P1[8] — General purpose digital input/output pin.
I ENET_CRS (ENET_CRS_DV) — Ethernet Carrier Sense (MII
interface) or Ethernet Carrier Sense/Data Valid (RMII interface).
- R — Function reserved.
O T3_MAT1 — Match output for Timer 3, channel 1.
I/O SSP2_SSEL — Slave Select for SSP2.
P1[9] 188 A6 D7 131 [3] I;
PU
I/O P1[9] — General purpose digital input/output pin.
I ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface).
- R — Function reserved.
O T3_MAT0 — Match output for Timer 3, channel 0.
P1[10] 186 C8 A7 129 [3] I;
PU
I/O P1[10] — General purpose digital input/output pin.
I ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface).
- R — Function reserved.
I T3_CAP0 — Capture input for Timer 3, channel 0.
P1[11] 163 A14 A12 - [3] I;
PU
I/O P1[11] — General purpose digital input/output pin.
I ENET_RXD2 — Ethernet Receive Data 2 (MII interface).
I/O SD_DAT[2] — Data line 2 for SD card interface.
O PWM0[6] — Pulse Width Modulator 0, output 6.
P1[12] 157 A16 A14 - [3] I;
PU
I/O P1[12] — General purpose digital input/output pin.
I ENET_RXD3 — Ethernet Receive Data (MII interface).
I/O SD_DAT[3] — Data line 3 for SD card interface.
I PWM0_CAP0 — Capture input for PWM0, channel 0.
P1[13] 147 D16 D14 - [3] I;
PU
I/O P1[13] — General purpose digital input/output pin.
I ENET_RX_DV — Ethernet Receive Data Valid (MII interface).
P1[14] 184 A7 D8 128 [3] I;
PU
I/O P1[14] — General purpose digital input/output pin.
I ENET_RX_ER — Ethernet receive error (RMII/MII interface).
- R — Function reserved.
I T2_CAP0 — Capture input for Timer 2, channel 0.
P1[15] 182 A8 A8 126 [3] I;
PU
I/O P1[15] — General purpose digital input/output pin.
I ENET_RX_CLK (ENET_REF_CLK) — Ethernet Receive Clock
(MII interface) or Ethernet Reference Clock (RMII interface).
- R — Function reserved.
I/O I2C2_SDA — I
2C2 data input/output (this pin does not use a
specialized I2C pad).
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Reset state[1]
Type[2]
DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 18 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
P1[16] 180 D10 B8 125 [3] I;
PU
I/O P1[16] — General purpose digital input/output pin.
O ENET_MDC — Ethernet MIIM clock.
O I2S_TX_MCLK — I2S transmit master clock.
P1[17] 178 A9 C9 123 [3] I;
PU
I/O P1[17] — General purpose digital input/output pin.
I/O ENET_MDIO — Ethernet MIIM data input and output.
O I2S_RX_MCLK — I2S receive master clock.
P1[18] 66 P7 L5 46 [3] I;
PU
I/O P1[18] — General purpose digital input/output pin.
O USB_UP_LED1 — It is LOW when the device is configured
(non-control endpoints enabled), or when the host is enabled
and has detected a device on the bus. It is HIGH when the
device is not configured, or when host is enabled and has not
detected a device on the bus, or during global suspend. It
transitions between LOW and HIGH (flashes) when the host is
enabled and detects activity on the bus.
O PWM1[1] — Pulse Width Modulator 1, channel 1 output.
I T1_CAP0 — Capture input for Timer 1, channel 0.
- R — Function reserved.
I/O SSP1_MISO — Master In Slave Out for SSP1.
P1[19] 68 U6 P5 47 [3] I;
PU
I/O P1[19] — General purpose digital input/output pin.
O USB_TX_E1 — Transmit Enable signal for USB port 1 (OTG
transceiver).
O USB_PPWR1 — Port Power enable signal for USB port 1.
I T1_CAP1 — Capture input for Timer 1, channel 1.
O MC_0A — Motor control PWM channel 0, output A.
I/O SSP1_SCK — Serial clock for SSP1.
O U2_OE — RS-485/EIA-485 output enable signal for UART2.
P1[20] 70 U7 K6 49 [3] I;
PU
I/O P1[20] — General purpose digital input/output pin.
O USB_TX_DP1 — D+ transmit data for USB port 1 (OTG
transceiver).
O PWM1[2] — Pulse Width Modulator 1, channel 2 output.
I QEI_PHA — Quadrature Encoder Interface PHA input.
I MC_FB0 — Motor control PWM channel 0 feedback input.
I/O SSP0_SCK — Serial clock for SSP0.
O LCD_VD[6] — LCD data.
O LCD_VD[10] — LCD data.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Reset state[1]
Type[2]
DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 19 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
P1[21] 72 R8 N6 50 [3] I;
PU
I/O P1[21] — General purpose digital input/output pin.
O USB_TX_DM1 — D transmit data for USB port 1 (OTG
transceiver).
O PWM1[3] — Pulse Width Modulator 1, channel 3 output.
I/O SSP0_SSEL — Slave Select for SSP0.
I MC_ABORT — Motor control PWM, active low fast abort.
- R — Function reserved.
O LCD_VD[7] — LCD data.
O LCD_VD[11] — LCD data.
P1[22] 74 U8 M6 51 [3] I;
PU
I/O P1[22] — General purpose digital input/output pin.
I USB_RCV1 — Differential receive data for USB port 1 (OTG
transceiver).
I USB_PWRD1 — Power Status for USB port 1 (host power
switch).
O T1_MAT0 — Match output for Timer 1, channel 0.
O MC_0B — Motor control PWM channel 0, output B.
I/O SSP1_MOSI — Master Out Slave In for SSP1.
O LCD_VD[8] — LCD data.
O LCD_VD[12] — LCD data.
P1[23] 76 P9 N7 53 [3] I;
PU
I/O P1[23] — General purpose digital input/output pin.
I USB_RX_DP1 — D+ receive data for USB port 1 (OTG
transceiver).
O PWM1[4] — Pulse Width Modulator 1, channel 4 output.
I QEI_PHB — Quadrature Encoder Interface PHB input.
I MC_FB1 — Motor control PWM channel 1 feedback input.
I/O SSP0_MISO — Master In Slave Out for SSP0.
O LCD_VD[9] — LCD data.
O LCD_VD[13] — LCD data.
P1[24] 78 T9 P7 54 [3] I;
PU
I/O P1[24] — General purpose digital input/output pin.
I USB_RX_DM1 — D receive data for USB port 1 (OTG
transceiver).
O PWM1[5] — Pulse Width Modulator 1, channel 5 output.
I QEI_IDX — Quadrature Encoder Interface INDEX input.
I MC_FB2 — Motor control PWM channel 2 feedback input.
I/O SSP0_MOSI — Master Out Slave in for SSP0.
O LCD_VD[10] — LCD data.
O LCD_VD[14] — LCD data.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Reset state[1]
Type[2]
DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 20 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
P1[25] 80 T10 L7 56 [3] I;
PU
I/O P1[25] — General purpose digital input/output pin.
O USB_LS1 — Low Speed status for USB port 1 (OTG
transceiver).
O USB_HSTEN1 — Host Enabled status for USB port 1.
O T1_MAT1 — Match output for Timer 1, channel 1.
O MC_1A — Motor control PWM channel 1, output A.
O CLKOUT — Selectable clock output.
O LCD_VD[11] — LCD data.
O LCD_VD[15] — LCD data.
P1[26] 82 R10 P8 57 [3] I;
PU
I/O P1[26] — General purpose digital input/output pin.
O USB_SSPND1 — USB port 1 Bus Suspend status (OTG
transceiver).
O PWM1[6] — Pulse Width Modulator 1, channel 6 output.
I T0_CAP0 — Capture input for Timer 0, channel 0.
O MC_1B — Motor control PWM channel 1, output B.
I/O SSP1_SSEL — Slave Select for SSP1.
O LCD_VD[12] — LCD data.
O LCD_VD[20] — LCD data.
P1[27] 88 T12 M9 61 [3] I;
PU
I/O P1[27] — General purpose digital input/output pin.
I USB_INT1 — USB port 1 OTG transceiver interrupt (OTG
transceiver).
I USB_OVRCR1 — USB port 1 Over-Current status.
I T0_CAP1 — Capture input for Timer 0, channel 1.
O CLKOUT — Selectable clock output.
- R — Function reserved.
O LCD_VD[13] — LCD data.
O LCD_VD[21] — LCD data.
P1[28] 90 T13 P10 63 [3] I;
PU
I/O P1[28] — General purpose digital input/output pin.
I/O USB_SCL1 — USB port 1 I2C serial clock (OTG transceiver).
I PWM1_CAP0 — Capture input for PWM1, channel 0.
O T0_MAT0 — Match output for Timer 0, channel 0.
O MC_2A — Motor control PWM channel 2, output A.
I/O SSP0_SSEL — Slave Select for SSP0.
O LCD_VD[14] — LCD data.
O LCD_VD[22] — LCD data.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Reset state[1]
Type[2]
DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 21 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
P1[29] 92 U14 N10 64 [3] I;
PU
I/O P1[29] — General purpose digital input/output pin.
I/O USB_SDA1 — USB port 1 I2C serial data (OTG transceiver).
I PWM1_CAP1 — Capture input for PWM1, channel 1.
O T0_MAT1 — Match output for Timer 0, channel 1.
O MC_2B — Motor control PWM channel 2, output B.
O U4_TXD — Transmitter output for USART4 (input/output in
smart card mode).
O LCD_VD[15] — LCD data.
O LCD_VD[23] — LCD data.
P1[30] 42 P2 K3 30 [5] I;
PU
I/O P1[30] — General purpose digital input/output pin.
I USB_PWRD2 — Power Status for USB port 2.
I USB_VBUS — Monitors the presence of USB bus power.
This signal must be HIGH for USB reset to occur.
I ADC0_IN[4] — A/D converter 0, input 4. When configured as an
ADC input, the digital function of the pin must be disabled.
I/O I2C0_SDA — I
2C0 data input/output (this pin does not use a
specialized I2C pad).
O U3_OE — RS-485/EIA-485 output enable signal for UART3.
P1[31] 40 P1 K2 28 [5] I;
PU
I/O P1[31] — General purpose digital input/output pin.
I USB_OVRCR2 — Over-Current status for USB port 2.
I/O SSP1_SCK — Serial Clock for SSP1.
I ADC0_IN[5] — A/D converter 0, input 5. When configured as an
ADC input, the digital function of the pin must be disabled.
I/O I2C0_SCL — I
2C0 clock input/output (this pin does not use a
specialized I2C pad).
P2[0] to
P2[31]
I/O Port 2: Port 2 is a 32 bit I/O port with individual direction
controls for each bit. The operation of port 1 pins depends upon
the pin function selected via the pin connect block.
P2[0] 154 B17 D12 107 [3] I;
PU
I/O P2[0] — General purpose digital input/output pin.
O PWM1[1] — Pulse Width Modulator 1, channel 1 output.
O U1_TXD — Transmitter output for UART1.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
O LCD_PWR — LCD panel power enable.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Reset state[1]
Type[2]
DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 22 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
P2[1] 152 E14 C14 106 [3] I;
PU
I/O P2[1] — General purpose digital input/output pin.
O PWM1[2] — Pulse Width Modulator 1, channel 2 output.
I U1_RXD — Receiver input for UART1.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
O LCD_LE — Line end signal.
P2[2] 150 D15 E11 105 [3] I;
PU
I/O P2[2] — General purpose digital input/output pin.
O PWM1[3] — Pulse Width Modulator 1, channel 3 output.
I U1_CTS — Clear to Send input for UART1.
O T2_MAT3 — Match output for Timer 2, channel 3.
- R — Function reserved.
O TRACEDATA[3] — Trace data, bit 3.
- R — Function reserved.
O LCD_DCLK — LCD panel clock.
P2[3] 144 E16 E13 100 [3] I;
PU
I/O P2[3] — General purpose digital input/output pin.
O PWM1[4] — Pulse Width Modulator 1, channel 4 output.
I U1_DCD — Data Carrier Detect input for UART1.
O T2_MAT2 — Match output for Timer 2, channel 2.
- R — Function reserved.
O TRACEDATA[2] — Trace data, bit 2.
- R — Function reserved.
O LCD_FP — Frame pulse (STN). Vertical synchronization pulse
(TFT).
P2[4] 142 D17 E14 99 [3] I;
PU
I/O P2[4] — General purpose digital input/output pin.
O PWM1[5] — Pulse Width Modulator 1, channel 5 output.
I U1_DSR — Data Set Ready input for UART1.
O T2_MAT1 — Match output for Timer 2, channel 1.
- R — Function reserved.
O TRACEDATA[1] — Trace data, bit 1.
- R — Function reserved.
O LCD_ENAB_M — STN AC bias drive or TFT data enable
output.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Reset state[1]
Type[2]
DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 23 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
P2[5] 140 F16 F12 97 [3] I;
PU
I/O P2[5] — General purpose digital input/output pin.
O PWM1[6] — Pulse Width Modulator 1, channel 6 output.
O U1_DTR — Data Terminal Ready output for UART1. Can also
be configured to be an RS-485/EIA-485 output enable signal for
UART1.
O T2_MAT0 — Match output for Timer 2, channel 0.
- R — Function reserved.
O TRACEDATA[0] — Trace data, bit 0.
- R — Function reserved.
O LCD_LP — Line synchronization pulse (STN). Horizontal
synchronization pulse (TFT).
P2[6] 138 E17 F13 96 [3] I;
PU
I/O P2[6] — General purpose digital input/output pin.
I PWM1_CAP0 — Capture input for PWM1, channel 0.
I U1_RI — Ring Indicator input for UART1.
I T2_CAP0 — Capture input for Timer 2, channel 0.
O U2_OE — RS-485/EIA-485 output enable signal for UART2.
O TRACECLK — Trace clock.
O LCD_VD[0] — LCD data.
O LCD_VD[4] — LCD data.
P2[7] 136 G16 G11 95 [3] I;
PU
I/O P2[7] — General purpose digital input/output pin.
I CAN_RD2 — CAN2 receiver input.
O U1_RTS — Request to Send output for UART1. Can also be
configured to be an RS-485/EIA-485 output enable signal for
UART1.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
O LCD_VD[1] — LCD data.
O LCD_VD[5] — LCD data.
P2[8] 134 H15 G14 93 [3] I;
PU
I/O P2[8] — General purpose digital input/output pin.
O CAN_TD2 — CAN2 transmitter output.
O U2_TXD — Transmitter output for UART2.
I U1_CTS — Clear to Send input for UART1.
O ENET_MDC — Ethernet MIIM clock.
- R — Function reserved.
O LCD_VD[2] — LCD data.
O LCD_VD[6] — LCD data.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Reset state[1]
Type[2]
DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 24 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
P2[9] 132 H16 H11 92 [3] I;
PU
I/O P2[9] — General purpose digital input/output pin.
O USB_CONNECT1 — USB1 SoftConnect control. Signal used to
switch an external 1.5 k resistor under the software control.
Used with the SoftConnect USB feature.
I U2_RXD — Receiver input for UART2.
I U4_RXD — Receiver input for USART4.
I/O ENET_MDIO — Ethernet MIIM data input and output.
- R — Function reserved.
I LCD_VD[3] — LCD data.
I LCD_VD[7] — LCD data.
P2[10] 110 N15 M13 76 [10] I;
PU
I/O P2[10] — General purpose digital input/output pin. This pin
includes a 10 ns input .
A LOW on this pin while RESET is LOW forces the on-chip boot
loader to take over control of the part after a reset and go into
ISP mode.
I EINT0 — External interrupt 0 input.
I NMI — Non-maskable interrupt input.
P2[11] 108 T17 M12 75 [10] I;
PU
I/O P2[11] — General purpose digital input/output pin. This pin
includes a 10 ns input glitch filter.
I EINT1 — External interrupt 1 input.
I/O SD_DAT[1] — Data line 1 for SD card interface.
I/O I2S_TX_SCK — Transmit Clock. It is driven by the master and
received by the slave. Corresponds to the signal SCK in the
I
2S-bus specification.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
O LCD_CLKIN — LCD clock.
P2[12] 106 N14 N14 73 [10] I;
PU
I/O P2[12] — General purpose digital input/output pin. This pin
includes a 10 ns input glitch filter.
I EINT2 — External interrupt 2 input.
I/O SD_DAT[2] — Data line 2 for SD card interface.
I/O I2S_TX_WS — Transmit Word Select. It is driven by the master
and received by the slave. Corresponds to the signal WS in the
I
2S-bus specification.
O LCD_VD[4] — LCD data.
O LCD_VD[3] — LCD data.
O LCD_VD[8] — LCD data.
O LCD_VD[18] — LCD data.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Reset state[1]
Type[2]
DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 25 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
P2[13] 102 T16 M11 71 [10] I;
PU
I/O P2[13] — General purpose digital input/output pin. This pin
includes a 10 ns input glitch filter.
I EINT3 — External interrupt 3 input.
I/O SD_DAT[3] — Data line 3 for SD card interface.
I/O I2S_TX_SDA — Transmit data. It is driven by the transmitter
and read by the receiver. Corresponds to the signal SD in the
I
2S-bus specification.
- R — Function reserved.
O LCD_VD[5] — LCD data.
O LCD_VD[9] — LCD data.
O LCD_VD[19] — LCD data.
P2[14] 91 R12 - - [3] I;
PU
I/O P2[14] — General purpose digital input/output pin.
O EMC_CS2 — LOW active Chip Select 2 signal.
I/O I2C1_SDA — I
2C1 data input/output (this pin does not use a
specialized I2C pad).
I T2_CAP0 — Capture input for Timer 2, channel 0.
P2[15] 99 P13 - - [3] I;
PU
I/O P2[15] — General purpose digital input/output pin.
O EMC_CS3 — LOW active Chip Select 3 signal.
I/O I2C1_SCL — I
2C1 clock input/output (this pin does not use a
specialized I2C pad).
I T2_CAP1 — Capture input for Timer 2, channel 1.
P2[16] 87 R11 P9 - [3] I;
PU
I/O P2[16] — General purpose digital input/output pin.
O EMC_CAS — LOW active SDRAM Column Address Strobe.
P2[17] 95 R13 P11 - [3] I;
PU
I/O P2[17] — General purpose digital input/output pin.
O EMC_RAS — LOW active SDRAM Row Address Strobe.
P2[18] 59 U3 P3 - [6] I;
PU
I/O P2[18] — General purpose digital input/output pin.
O EMC_CLK[0] — SDRAM clock 0.
P2[19] 67 R7 N5 - [6] I;
PU
I/O P2[19] — General purpose digital input/output pin.
O EMC_CLK[1] — SDRAM clock 1.
P2[20] 73 T8 P6 - [3] I;
PU
I/O P2[20] — General purpose digital input/output pin.
O EMC_DYCS0 — SDRAM chip select 0.
P2[21] 81 U11 N8 - [3] I;
PU
I/O P2[21] — General purpose digital input/output pin.
O EMC_DYCS1 — SDRAM chip select 1.
P2[22] 85 U12 - - [3] I;
PU
I/O P2[22] — General purpose digital input/output pin.
O EMC_DYCS2 — SDRAM chip select 2.
I/O SSP0_SCK — Serial clock for SSP0.
I T3_CAP0 — Capture input for Timer 3, channel 0.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Reset state[1]
Type[2]
DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 26 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
P2[23] 64 U5 - - [3] I;
PU
I/O P2[23] — General purpose digital input/output pin.
O EMC_DYCS3 — SDRAM chip select 3.
I/O SSP0_SSEL — Slave Select for SSP0.
I T3_CAP1 — Capture input for Timer 3, channel 1.
P2[24] 53 P5 P1 - [3] I;
PU
I/O P2[24] — General purpose digital input/output pin.
O EMC_CKE0 — SDRAM clock enable 0.
P2[25] 54 R4 P2 - [3] I;
PU
I/O P2[25] — General purpose digital input/output pin.
O EMC_CKE1 — SDRAM clock enable 1.
P2[26] 57 T4 - - [3] I;
PU
I/O P2[26] — General purpose digital input/output pin.
O EMC_CKE2 — SDRAM clock enable 2.
I/O SSP0_MISO — Master In Slave Out for SSP0.
O T3_MAT0 — Match output for Timer 3, channel 0.
P2[27] 47 P3 - - [3] I;
PU
I/O P2[27] — General purpose digital input/output pin.
O EMC_CKE3 — SDRAM clock enable 3.
I/O SSP0_MOSI — Master Out Slave In for SSP0.
O T3_MAT1 — Match output for Timer 3, channel 1.
P2[28] 49 P4 M2 - [3] I;
PU
I/O P2[28] — General purpose digital input/output pin.
O EMC_DQM0 — Data mask 0 used with SDRAM and static
devices.
P2[29] 43 N3 L1 - [3] I;
PU
I/O P2[29] — General purpose digital input/output pin.
O EMC_DQM1 — Data mask 1 used with SDRAM and static
devices.
P2[30] 31 L4 - - [3] I;
PU
I/O P2[30] — General purpose digital input/output pin.
O EMC_DQM2 — Data mask 2 used with SDRAM and static
devices.
I/O I2C2_SDA — I
2C2 data input/output (this pin does not use a
specialized I2C pad).
O T3_MAT2 — Match output for Timer 3, channel 2.
P2[31] 39 N2 - - [3] I;
PU
I/O P2[31] — General purpose digital input/output pin.
O EMC_DQM3 — Data mask 3 used with SDRAM and static
devices.
I/O I2C2_SCL — I
2C2 clock input/output (this pin does not use a
specialized I2C pad).
O T3_MAT3 — Match output for Timer 3, channel 3.
P3[0] to
P3[31]
I/O Port 3: Port 3 is a 32-bit I/O port with individual direction
controls for each bit. The operation of port 3 pins depends upon
the pin function selected via the pin connect block.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Reset state[1]
Type[2]
DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 27 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
P3[0] 197 B4 D6 137 [3] I;
PU
I/O P3[0] — General purpose digital input/output pin.
I/O EMC_D[0] — External memory data line 0.
P3[1] 201 B3 E6 140 [3] I;
PU
I/O P3[1] — General purpose digital input/output pin.
I/O EMC_D[1] — External memory data line 1.
P3[2] 207 B1 A2 144 [3] I;
PU
I/O P3[2] — General purpose digital input/output pin.
I/O EMC_D[2] — External memory data line 2.
P3[3] 3 E4 G5 2 [3] I;
PU
I/O P3[3] — General purpose digital input/output pin.
I/O EMC_D[3] — External memory data line 3.
P3[4] 13 F2 D3 9 [3] I;
PU
I/O P3[4] — General purpose digital input/output pin.
I/O EMC_D[4] — External memory data line 4.
P3[5] 17 G1 E3 12 [3] I;
PU
I/O P3[5] — General purpose digital input/output pin.
I/O EMC_D[5] — External memory data line 5.
P3[6] 23 J1 F4 16 [3] I;
PU
I/O P3[6] — General purpose digital input/output pin.
I/O EMC_D[6] — External memory data line 6.
P3[7] 27 L1 G3 19 [3] I;
PU
I/O P3[7] — General purpose digital input/output pin.
I/O EMC_D[7] — External memory data line 7.
P3[8] 191 D8 A6 - [3] I;
PU
I/O P3[8] — General purpose digital input/output pin.
I/O EMC_D[8] — External memory data line 8.
P3[9] 199 C5 A4 - [3] I;
PU
I/O P3[9] — General purpose digital input/output pin.
I/O EMC_D[9] — External memory data line 9.
P3[10] 205 B2 B3 - [3] I;
PU
I/O P3[10] — General purpose digital input/output pin.
I/O EMC_D[10] — External memory data line 10.
P3[11] 208 D5 B2 - [3] I;
PU
I/O P3[11] — General purpose digital input/output pin.
I/O EMC_D[11] — External memory data line 11.
P3[12] 1 D4 A1 - [3] I;
PU
I/O P3[12] — General purpose digital input/output pin.
I/O EMC_D[12] — External memory data line 12.
P3[13] 7 C1 C1 - [3] I;
PU
I/O P3[13] — General purpose digital input/output pin.
I/O EMC_D[13] — External memory data line 13.
P3[14] 21 H2 F1 - [3] I;
PU
I/O P3[14] — General purpose digital input/output pin.
I/O EMC_D[14] — External memory data line 14.
P3[15] 28 M1 G4 - [3] I;
PU
I/O P3[15] — General purpose digital input/output pin.
I/O EMC_D[15] — External memory data line 15.
P3[16] 137 F17 - - [3] I;
PU
I/O P3[16] — General purpose digital input/output pin.
I/O EMC_D[16] — External memory data line 16.
O PWM0[1] — Pulse Width Modulator 0, output 1.
O U1_TXD — Transmitter output for UART1.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Reset state[1]
Type[2]
DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 28 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
P3[17] 143 F15 - - [3] I;
PU
I/O P3[17] — General purpose digital input/output pin.
I/O EMC_D[17] — External memory data line 17.
O PWM0[2] — Pulse Width Modulator 0, output 2.
I U1_RXD — Receiver input for UART1.
P3[18] 151 C15 - - [3] I;
PU
I/O P3[18] — General purpose digital input/output pin.
I/O EMC_D[18] — External memory data line 18.
O PWM0[3] — Pulse Width Modulator 0, output 3.
I U1_CTS — Clear to Send input for UART1.
P3[19] 161 B14 - - [3] I;
PU
I/O P3[19] — General purpose digital input/output pin.
I/O EMC_D[19] — External memory data line 19.
O PWM0[4] — Pulse Width Modulator 0, output 4.
I U1_DCD — Data Carrier Detect input for UART1.
P3[20] 167 A13 - - [3] I;
PU
I/O P3[20] — General purpose digital input/output pin.
I/O EMC_D[20] — External memory data line 20.
O PWM0[5] — Pulse Width Modulator 0, output 5.
I U1_DSR — Data Set Ready input for UART1.
P3[21] 175 C10 - - [3] I;
PU
I/O P3[21] — General purpose digital input/output pin.
I/O EMC_D[21] — External memory data line 21.
O PWM0[6] — Pulse Width Modulator 0, output 6.
O U1_DTR — Data Terminal Ready output for UART1. Can also
be configured to be an RS-485/EIA-485 output enable signal for
UART1.
P3[22] 195 C6 - - [3] I;
PU
I/O P3[22] — General purpose digital input/output pin.
I/O EMC_D[22] — External memory data line 22.
I PWM0_CAP0 — Capture input for PWM0, channel 0.
I U1_RI — Ring Indicator input for UART1.
P3[23] 65 T6 M4 45 [3] I;
PU
I/O P3[23] — General purpose digital input/output pin.
I/O EMC_D[23] — External memory data line 23.
I PWM1_CAP0 — Capture input for PWM1, channel 0.
I T0_CAP0 — Capture input for Timer 0, channel 0.
P3[24] 58 R5 N3 40 [3] I;
PU
I/O P3[24] — General purpose digital input/output pin.
I/O EMC_D[24] — External memory data line 24.
O PWM1[1] — Pulse Width Modulator 1, output 1.
I T0_CAP1 — Capture input for Timer 0, channel 1.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Reset state[1]
Type[2]
DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 29 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
P3[25] 56 U2 M3 39 [3] I;
PU
I/O P3[25] — General purpose digital input/output pin.
I/O EMC_D[25] — External memory data line 25.
O PWM1[2] — Pulse Width Modulator 1, output 2.
O T0_MAT0 — Match output for Timer 0, channel 0.
P3[26] 55 T3 K7 38 [3] I;
PU
I/O P3[26] — General purpose digital input/output pin.
I/O EMC_D[26] — External memory data line 26.
O PWM1[3] — Pulse Width Modulator 1, output 3.
O T0_MAT1 — Match output for Timer 0, channel 1.
I STCLK — System tick timer clock input. The maximum STCLK
frequency is 1/4 of the ARM processor clock frequency CCLK.
P3[27] 203 A1 - - [3] I;
PU
I/O P3[27] — General purpose digital input/output pin.
I/O EMC_D[27] — External memory data line 27.
O PWM1[4] — Pulse Width Modulator 1, output 4.
I T1_CAP0 — Capture input for Timer 1, channel 0.
P3[28] 5 D2 - - [3] I;
PU
I/O P3[28] — General purpose digital input/output pin.
I/O EMC_D[28] — External memory data line 28.
O PWM1[5] — Pulse Width Modulator 1, output 5.
I T1_CAP1 — Capture input for Timer 1, channel 1.
P3[29] 11 F3 - - [3] I;
PU
I/O P3[29] — General purpose digital input/output pin.
I/O EMC_D[29] — External memory data line 29.
O PWM1[6] — Pulse Width Modulator 1, output 6.
O T1_MAT0 — Match output for Timer 1, channel 0.
P3[30] 19 H3 - - [3] I;
PU
I/O P3[30] — General purpose digital input/output pin.
I/O EMC_D[30] — External memory data line 30.
O U1_RTS — Request to Send output for UART1. Can also be
configured to be an RS-485/EIA-485 output enable signal for
UART1.
O T1_MAT1 — Match output for Timer 1, channel 1.
P3[31] 25 J3 - - [3] I;
PU
I/O P3[31] — General purpose digital input/output pin.
I/O EMC_D[31] — External memory data line 31.
- R — Function reserved.
O T1_MAT2 — Match output for Timer 1, channel 2.
P4[0] to
P4[31]
I/O Port 4: Port 4 is a 32-bit I/O port with individual direction
controls for each bit. The operation of port 4 pins depends upon
the pin function selected via the pin connect block.
P4[0] 75 U9 L6 52 [3] I;
PU
I/O P4[0] — General purpose digital input/output pin.
I/O EMC_A[0] — External memory address line 0.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Reset state[1]
Type[2]
DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 30 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
P4[1] 79 U10 M7 55 [3] I;
PU
I/O P4[1] — General purpose digital input/output pin.
I/O EMC_A[1] — External memory address line 1.
P4[2] 83 T11 M8 58 [3] I;
PU
I/O P4[2] — General purpose digital input/output pin.
I/O EMC_A[2] — External memory address line 2.
P4[3] 97 U16 K9 68 [3] I;
PU
I/O P4[3] — General purpose digital input/output pin.
I/O EMC_A[3] — External memory address line 3.
P4[4] 103 R15 P13 72 [3] I;
PU
I/O P4[4] — General purpose digital input/output pin.
I/O EMC_A[4] — External memory address line 4.
P4[5] 107 R16 H10 74 [3] I;
PU
I/O P4[5] — General purpose digital input/output pin.
I/O EMC_A[5] — External memory address line 5.
P4[6] 113 M14 K10 78 [3] I;
PU
I/O P4[6] — General purpose digital input/output pin.
I/O EMC_A[6] — External memory address line 6.
P4[7] 121 L16 K12 84 [3] I;
PU
I/O P4[7] — General purpose digital input/output pin.
I/O EMC_A[7] — External memory address line 7.
P4[8] 127 J17 J11 88 [3] I;
PU
I/O P4[8] — General purpose digital input/output pin.
I/O EMC_A[8] — External memory address line 8.
P4[9] 131 H17 H12 91 [3] I;
PU
I/O P4[9] — General purpose digital input/output pin.
I/O EMC_A[9] — External memory address line 9.
P4[10] 135 G17 G12 94 [3] I;
PU
I/O P4[10] — General purpose digital input/output pin.
I/O EMC_A[10] — External memory address line 10.
P4[11] 145 F14 F11 101 [3] I;
PU
I/O P4[11] — General purpose digital input/output pin.
I/O EMC_A[11] — External memory address line 11.
P4[12] 149 C16 F10 104 [3] I;
PU
I/O P4[12] — General purpose digital input/output pin.
I/O EMC_A[12] — External memory address line 12.
P4[13] 155 B16 B14 108 [3] I;
PU
I/O P4[13] — General purpose digital input/output pin.
I/O EMC_A[13] — External memory address line 13.
P4[14] 159 B15 E8 110 [3] I;
PU
I/O P4[14] — General purpose digital input/output pin.
I/O EMC_A[14] — External memory address line 14.
P4[15] 173 A11 C10 120 [3] I;
PU
I/O P4[15] — General purpose digital input/output pin.
I/O EMC_A[15] — External memory address line 15.
P4[16] 101 U17 N12 - [3] I;
PU
I/O P4[16] — General purpose digital input/output pin.
I/O EMC_A[16] — External memory address line 16.
P4[17] 104 P14 N13 - [3] I;
PU
I/O P4[17] — General purpose digital input/output pin.
I/O EMC_A[17] — External memory address line 17.
P4[18] 105 P15 P14 - [3] I;
PU
I/O P4[18] — General purpose digital input/output pin.
I/O EMC_A[18] — External memory address line 18.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Reset state[1]
Type[2]
DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 31 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
P4[19] 111 P16 M14 - [3] I;
PU
I/O P4[19] — General purpose digital input/output pin.
I/O EMC_A[19] — External memory address line 19.
P4[20] 109 R17 - - [3] I;
PU
I/O P4[20] — General purpose digital input/output pin.
I/O EMC_A[20] — External memory address line 20.
I/O I2C2_SDA — I
2C2 data input/output (this pin does not use a
specialized I2C pad).
I/O SSP1_SCK — Serial Clock for SSP1.
P4[21] 115 M15 - - [3] I;
PU
I/O P4[21] — General purpose digital input/output pin.
I/O EMC_A[21] — External memory address line 21.
I/O I2C2_SCL — I
2C2 clock input/output (this pin does not use a
specialized I2C pad).
I/O SSP1_SSEL — Slave Select for SSP1.
P4[22] 123 K14 - - [3] I;
PU
I/O P4[22] — General purpose digital input/output pin.
I/O EMC_A[22] — External memory address line 22.
O U2_TXD — Transmitter output for UART2.
I/O SSP1_MISO — Master In Slave Out for SSP1.
P4[23] 129 J15 - - [3] I;
PU
I/O P4[23] — General purpose digital input/output pin.
I/O EMC_A[23] — External memory address line 23.
I U2_RXD — Receiver input for UART2.
I/O SSP1_MOSI — Master Out Slave In for SSP1.
P4[24] 183 B8 C8 127 [3] I;
PU
I/O P4[24] — General purpose digital input/output pin.
O EMC_OE — LOW active Output Enable signal.
P4[25] 179 B9 D9 124 [3] I;
PU
I/O P4[25] — General purpose digital input/output pin.
O EMC_WE — LOW active Write Enable signal.
P4[26] 119 L15 K13 - [3] I;
PU
I/O P4[26] — General purpose digital input/output pin.
O EMC_BLS0 — LOW active Byte Lane select signal 0.
P4[27] 139 G15 F14 - [3] I;
PU
I/O P4[27] — General purpose digital input/output pin.
O EMC_BLS1 — LOW active Byte Lane select signal 1.
P4[28] 170 C11 D10 118 [3] I;
PU
I/O P4[28] — General purpose digital input/output pin.
O EMC_BLS2 — LOW active Byte Lane select signal 2.
O U3_TXD — Transmitter output for UART3.
O T2_MAT0 — Match output for Timer 2, channel 0.
- R — Function reserved.
O LCD_VD[6] — LCD data.
O LCD_VD[10] — LCD data.
O LCD_VD[2] — LCD data.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Reset state[1]
Type[2]
DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 32 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
P4[29] 176 B10 B9 122 [3] I;
PU
I/O P4[29] — General purpose digital input/output pin.
O EMC_BLS3 — LOW active Byte Lane select signal 3.
I U3_RXD — Receiver input for UART3.
O T2_MAT1 — Match output for Timer 2, channel 1.
I/O I2C2_SCL — I
2C2 clock input/output (this pin does not use a
specialized I2C pad).
O LCD_VD[7] — LCD data.
O LCD_VD[11] — LCD data.
O LCD_VD[3] — LCD data.
P4[30] 187 B7 C7 130 [3] I;
PU
I/O P4[30] — General purpose digital input/output pin.
O EMC_CS0 — LOW active Chip Select 0 signal.
P4[31] 193 A4 E7 134 [3] I;
PU
I/O P4[31] — General purpose digital input/output pin.
O EMC_CS1 — LOW active Chip Select 1 signal.
P5[0] to P5[4] I/O Port 5: Port 5 is a 5-bit I/O port with individual direction controls
for each bit. The operation of port 5 pins depends upon the pin
function selected via the pin connect block.
P5[0] 9 F4 E5 6 [3] I;
PU
I/O P5[0] — General purpose digital input/output pin.
I/O EMC_A[24] — External memory address line 24.
I/O SSP2_MOSI — Master Out Slave In for SSP2.
O T2_MAT2 — Match output for Timer 2, channel 2.
P5[1] 30 J4 H1 21 [3] I;
PU
I/O P5[1] — General purpose digital input/output pin.
I/O EMC_A[25] — External memory address line 25.
I/O SSP2_MISO — Master In Slave Out for SSP2.
O T2_MAT3 — Match output for Timer 2, channel 3.
P5[2] 117 L14 L12 81 [11] I I/O P5[2] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
O T3_MAT2 — Match output for Timer 3, channel 2.
- R — Function reserved.
I/O I2C0_SDA — I
2C0 data input/output (this pin uses a specialized
I
2C pad that supports I2C Fast Mode Plus).
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Reset state[1]
Type[2]
DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 33 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
P5[3] 141 G14 G10 98 [11] I I/O P5[3] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
I U4_RXD — Receiver input for USART4.
I/O I2C0_SCL — I
2C0 clock input/output (this pin uses a
specialized I2C pad that supports I2C Fast Mode Plus).
P5[4] 206 C3 C4 143 [3] I;
PU
I/O P5[4] — General purpose digital input/output pin.
O U0_OE — RS-485/EIA-485 output enable signal for UART0.
- R — Function reserved.
O T3_MAT3 — Match output for Timer 3, channel 3.
O U4_TXD — Transmitter output for USART4 (input/output in
smart card mode).
JTAG_TDO
(SWO)
2 D3 B1 1 [3] O O Test Data Out for JTAG interface. Also used as Serial wire trace
output.
JTAG_TDI 4 C2 C3 3 [3] I;
PU
I Test Data In for JTAG interface.
JTAG_TMS
(SWDIO)
6 E3 C2 4 [3] I;
PU
I Test Mode Select for JTAG interface. Also used as Serial wire
debug data input/output.
JTAG_TRST 8 D1 D4 5 [3] I;
PU
I Test Reset for JTAG interface.
JTAG_TCK
(SWDCLK)
10 E2 D2 7 [3] i I Test Clock for JTAG interface. This clock must be slower than
1/6 of the CPU clock (CCLK) for the JTAG interface to operate.
Also used as serial wire clock.
RESET 35 M2 J1 24 [12] I;
PU
I External reset input with 20 ns glitch filter. A LOW-going pulse
as short as 50 ns on this pin resets the device, causing I/O ports
and peripherals to take on their default states, and processor
execution to begin at address 0. This pin also serves as the
debug select input. LOW level selects the JTAG boundary scan.
HIGH level selects the ARM SWD debug mode.
RSTOUT 29 K3 H2 20 [3] OH O Reset status output. A LOW output on this pin indicates that the
device is in the reset state for any reason. This reflects the
RESET input pin and all internal reset sources.
RTC_ALARM 37 N1 H5 26 [13] OL O RTC controlled output. This pin has a low drive strength and is
powered by VBAT. It is driven HIGH when an RTC alarm is
generated.
RTCX1 34 K2 J2 23 [14]
[15]
- I Input to the RTC 32 kHz ultra-low power oscillator circuit.
RTCX2 36 L2 J3 25 [14]
[15]
- O Output from the RTC 32 kHz ultra-low power oscillator circuit.
USB_D2 52 U1 N2 37 [9] - I/O USB port 2 bidirectional D line.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Reset state[1]
Type[2]
DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 34 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
VBAT 38 M3 K1 27 - I RTC power supply: 3.0 V on this pin supplies power to the RTC.
VDD(REG)(3V3) 26,
86,
174
H4,
P11,
D11
G1,
N9,
E9
18,
60,
121
- S 3.3 V regulator supply voltage: This is the power supply for the
on-chip voltage regulator that supplies internal logic.
VDDA 20 G4 F2 14 - S Analog 3.3 V pad supply voltage: This can be connected to the
same supply as VDD(3V3) but should be isolated to minimize
noise and error. This voltage is used to power the ADC and
DAC. Note: This pin should be tied to 3.3 V if the ADC and
DAC are not used.
VDD(3V3) 15,
60,
71,
89,
112,
125,
146,
165,
181,
198
G3,
P6,
P8,
U13,
P17,
K16,
C17,
B13,
C9,
D7
E2,
L4,
K8,
L11,
J14,
E12,
E10,
C5
41,
62,
77,
102,
114,
138
- S 3.3 V supply voltage: This is the power supply voltage for I/O
other than pins in the VBAT domain.
VREFP 24 K1 G2 17 - S ADC positive reference voltage: This should be the same
voltage as VDDA, but should be isolated to minimize noise and
error. The voltage level on this pin is used as a reference for
ADC and DAC. Note: This pin should be tied to 3.3 V if the
ADC and DAC are not used.
VSS 33,
63,
77,
93,
114,
133,
148,
169,
189,
200
L3,
T5,
R9,
P12,
N16,
H14,
E15,
A12,
B6,
A2
H4,
P4,
L9,
L13,
G13,
D13,
C11,
B4
44,
65,
79,
103,
117,
139
- G Ground: 0 V reference for digital IO pins.
VSSREG 32,
84,
172
D12,
K4,
P10
H3,
L8,
A10
22,
59,
119
- G Ground: 0 V reference for internal logic.
VSSA 22 J2 F3 15 - G Analog ground: 0 V power supply and reference for the ADC
and DAC. This should be the same voltage as VSS, but should
be isolated to minimize noise and error.
XTAL1 44 M4 L2 31 [14]
[16]
- I Input to the oscillator circuit and internal clock generator circuits.
XTAL2 46 N4 K4 33 [14]
[16]
- O Output from the oscillator amplifier.
Table 3. Pin description …continued
Not all functions are available on all parts. See Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Table 7 (EMC
pins).
Symbol
Pin LQFP208
Ball TFBGA208
Ball TFBGA180
Pin LQFP144
Reset state[1]
Type[2]
DescriptionLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 35 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
[1] PU = internal pull-up enabled (for VDD(REG)(3V3) = 3.3 V, pulled up to 3.3 V); IA = inactive, no pull-up/down enabled; F = floating; floating
pins, if not used, should be tied to ground or power to minimize power consumption.
[2] I = Input; O = Output; OL = Output driving LOW; G = Ground; S = Supply.
[3] 5 V tolerant pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) providing digital I/O functions with TTL
levels and hysteresis.
[4] 5 V tolerant standard pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) providing digital I/O functions with
TTL levels and hysteresis. This pad can be powered by VBAT.
[5] 5 V tolerant pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present or configured for an analog function, do not exceed 3.6 V)
providing digital I/O functions with TTL levels and hysteresis and analog input. When configured as a ADC input, digital section of the
pad is disabled.
[6] 5 V tolerant fast pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) providing digital I/O functions with TTL
levels and hysteresis.
[7] 5 V tolerant pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present or configured for an analog function, do not exceed 3.6 V)
providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the
pad is disabled.
[8] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. It requires an external pull-up to provide output
functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain
configuration applies to all functions on this pin.
[9] Not 5 V tolerant. Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0
(Full-speed and Low-speed mode only).
[10] 5 V tolerant pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) with 5 ns glitch filter providing digital I/O
functions with TTL levels and hysteresis.
[11] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 1 MHz specification. It requires an external pull-up to provide output
functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain
configuration applies to all functions on this pin.
[12] 5 V tolerant pad (5 V tolerant if VDD(3V3) present; if VDD(3V3) not present, do not exceed 3.6 V) with 20 ns glitch filter providing digital I/O
function with TTL levels and hysteresis.
[13] This pad can be powered from VBAT.
[14] Pad provides special analog functionality. A 32 kHz crystal oscillator must be used with the RTC. An external clock (32 kHz) can’t be
used to drive the RTCX1 pin.
[15] If the RTC is not used, these pins can be left floating.
[16] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding
is preferred to reduce susceptibility to noise). XTAL2 should be left floating.
Table 4. Pin allocation table TFBGA208
Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins).
Ball Symbol Ball Symbol Ball Symbol Ball Symbol
Row A
1 P3[27] 2 VSS 3 P1[0] 4 P4[31]
5 P1[4] 6 P1[9] 7 P1[14] 8 P1[15]
9 P1[17] 10 P1[3] 11 P4[15] 12 VSS
13 P3[20] 14 P1[11] 15 P0[8] 16 P1[12]
17 P1[5] - - -
Row B
1 P3[2] 2 P3[10] 3 P3[1] 4 P3[0]
5 P1[1] 6 VSS 7 P4[30] 8 P4[24]
9 P4[25] 10 P4[29] 11 P1[6] 12 P0[4]
13 VDD(3V3) 14 P3[19] 15 P4[14] 16 P4[13]
17 P2[0] - - -
Row CLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 36 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
1 P3[13] 2 JTAG_TDI 3 P5[4] 4 P0[2]
5 P3[9] 6 P3[22] 7 P1[8] 8 P1[10]
9 VDD(3V3) 10 P3[21] 11 P4[28] 12 P0[5]
13 P0[7] 14 P0[9] 15 P3[18] 16 P4[12]
17 VDD(3V3)- - -
Row D
1 JTAG_TRST 2 P3[28] 3 JTAG_TDO (SWO) 4 P3[12]
5 P3[11] 6 P0[3] 7 VDD(3V3) 8 P3[8]
9 P1[2] 10 P1[16] 11 VDD(REG)(3V3) 12 VSSREG
13 P0[6] 14 P1[7] 15 P2[2] 16 P1[13]
17 P2[4] - - -
Row E
1 P0[26] 2 JTAG_TCK
(SWDCLK)
3 JTAG_TMS (SWDIO) 4 P3[3]
5 - 6- 7 - 8 -
9 - 10 - 11 - 12 -
13 - 14 P2[1] 15 VSS 16 P2[3]
17 P2[6] - - -
Row F
1 P0[25] 2 P3[4] 3 P3[29] 4 P5[0]
5 - 6- 7 - 8 -
9 - 10 - 11 - 12 -
13 - 14 P4[11] 15 P3[17] 16 P2[5]
17 P3[16] - - -
Row G
1 P3[5] 2 P0[24] 3 VDD(3V3) 4 VDDA
5 - 6 - 7 - 8 -
9 - 10 - 11 - 12 -
13 - 14 P5[3] 15 P4[27] 16 P2[7]
17 P4[10] - - -
Row H
1 P0[23] 2 P3[14] 3 P3[30] 4 VDD(REG)(3V3)
5 - 6 - 7 - 8 -
9 - 10 - 11 - 12 -
13 - 14 VSS 15 P2[8] 16 P2[9]
17 P4[9] - - -
Row J
1 P3[6] 2 VSSA 3 P3[31] 4 P5[1]
5 - 6 - 7 - 8 -
9 - 10 - 11 - 12 -
Table 4. Pin allocation table TFBGA208
Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins).
Ball Symbol Ball Symbol Ball Symbol Ball SymbolLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 37 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
13 14 P0[16] 15 P4[23] 16 P0[15]
17 P4[8] - - -
Row K
1 VREFP 2 RTCX1 3 RSTOUT 4 VSSREG
13 - 14 P4[22] 15 P0[18] 16 VDD(3V3)
17 P0[17] - - -
Row L
1 P3[7] 2 RTCX2 3 VSS 4 P2[30]
5 - 6- 7 - 8 -
9 - 10 - 11 - 12 -
13 - 14 P5[2] 15 P4[26] 16 P4[7]
17 P0[19] - - -
Row M
1 P3[15] 2 RESET 3 VBAT 4 XTAL1
5 - 6 - 7 - 8 -
9 - 10 - 11 - 12 -
13 - 14 P4[6] 15 P4[21] 16 P0[21]
17 P0[20] - - -
Row N
1 RTC_ALARM 2 P2[31] 3 P2[29] 4 XTAL2
5 - 6 - 7 - 8 -
9 - 10 - 11 - 12 -
13 - 14 P2[12 15 P2[10] 16 VSS
17 P0[22] - - -
Row P
1 P1[31] 2 P1[30] 3 P2[27] 4 P2[28]
5 P2[24] 6 VDD(3V3) 7 P1[18] 8 VDD(3V3)
9 P1[23] 10 VSSREG 11 VDD(REG)(3V3) 12 VSS
13 P2[15] 14 P4[17] 15 P4[18] 16 P4[19]
17 VDD(3V3) ---
Row R
1 P0[12] 2 P0[13] 3 P0[28] 4 P2[25]
5 P3[24] 6 P0[30] 7 P2[19] 8 P1[21]
9 VSS 10 P1[26] 11 P2[16] 12 P2[14]
13 P2[17] 14 P0[11] 15 P4[4] 16 P4[5]
17 P4[20] - - -
Row T
1 P0[27] 2 P0[31] 3 P3[26] 4 P2[26]
5 VSS 6 P3[23] 7 P0[14] 8 P2[20]
9 P1[24] 10 P1[25] 11 P4[2] 12 P1[27]
Table 4. Pin allocation table TFBGA208
Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins).
Ball Symbol Ball Symbol Ball Symbol Ball SymbolLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 38 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
13 P1[28] 14 P0[1] 15 P0[10] 16 P2[13]
17 P2[11] - - -
Row U
1 USB_D-2 2 P3[25] 3 P2[18] 4 P0[29]
5 P2[23] 6 P1[19] 7 P1[20] 8 P1[22]
9 P4[0] 10 P4[1] 11 P2[21] 12 P2[22]
13 VDD(3V3) 14 P1[29] 15 P0[0] 16 P4[3]
17 P4[16] - - -
Table 4. Pin allocation table TFBGA208
Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins).
Ball Symbol Ball Symbol Ball Symbol Ball Symbol
Table 5. Pin allocation table TFBGA180
Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins).
Ball Symbol Ball Symbol Ball Symbol Ball Symbol
Row A
5 P1[1] 6 P3[8] 7 P1[10] 8 P1[15]
9 P1[3] 10 VSSREG 11 P0[4] 12 P1[11]
13 P0[9] 14 P1[12] - -
Row B
1 JTAG_TDO (SWO) 2 P3[11] 3 P3[10] 4 VSS
5 P1[0] 6 P1[8] 7 P1[2] 8 P1[16]
9 P4[29] 10 P1[6] 11 P0[5] 12 P0[7]
13 P1[5] 14 P4[13] - -
Row C
1 P3[13] 2 JTAG_TMS (SWDIO) 3 JTAG_TDI 4 P5[4]
5 VDD(3V3) 6 P1[4] 7 P4[30] 8 P4[24]
9 P1[17] 10 P4[15] 11 VSS 12 P0[8]
13 P1[7] 14 P2[1] - -
Row D
1 P0[26] 2 JTAG_TCK
(SWDCLK)
3 P3[4] 4 JTAG_TRST
5 P0[2] 6 P3[0] 7 P1[9] 8 P1[14]
9 P4[25] 10 P4[28] 11 P0[6] 12 P2[0]
13 VSS 14 P1[13] - -
Row E
1 P0[24] 2 VDD(3V3) 3 P3[5] 4 P0[25]
5 P5[0] 6 P3[1] 7 P4[31] 8 P4[14]
9 VDD(REG)(3V3) 10 VDD(3V3) 11 P2[2] 12 VDD(3V3)
13 P2[3] 14 P2[4] - -
Row F
1 P3[14] 2 VDDA 3 VSSA 4 P3[6]
5 P0[23] 6 - 7 - 8 -
9 - 10 P4[12] 11 P4[11] 12 P2[5]LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 39 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
13 P2[6] 14 P4[27] - -
Row G
1 VDD(REG)(3V3) 2 VREFP 3 P3[7] 4 P3[15]
5 P3[3] 6 - 7 - 8 -
9 - 10 P5[3] 11 P2[7] 12 P4[10]
13 VSS 14 P2[8] - -
Row H
1 P5[1] 2 RSTOUT 3 VSSREG 4 VSS
5 RTC_ALARM 6 - 7 - 8 -
9 - 10 P4[5] 11 P2[9] 12 P4[9]
13 P0[15] 14 P0[16] - -
Table 5. Pin allocation table TFBGA180
Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins).
Ball Symbol Ball Symbol Ball Symbol Ball SymbolLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 40 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
7. Functional description
7.1 Architectural overview
The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and
the D-code bus. The I-code and D-code core buses are faster than the system bus and
are used similarly to Tightly Coupled Memory (TCM) interfaces: one bus dedicated for
instruction fetch (I-code) and one bus for data access (D-code). The use of two core
buses allows for simultaneous operations if concurrent operations target different devices.
Row J
1 RESET 2 RTCX1 3 RTCX2 4 P0[12]
5 P0[13] 6 - 7 - 8 -
9 - 10 P0[19] 11 P4[8] 12 P0[17]
13 P0[18] 14 VDD(3V3) - -
Row K
1 VBAT 2 P1[31] 3 P1[30] 4 XTAL2
5 P0[29] 6 P1[20] 7 P3[26] 8 VDD(3V3)
9 P4[3] 10 P4[6] 11 P0[21] 12 P4[7]
13 P4[26] 14 P0[20] - -
Row L
1 P2[29] 2 XTAL1 3 P0[27] 4 VDD(3V3)
5 P1[18] 6 P4[0] 7 P1[25] 8 VSSREG
9 VSS 10 P0[10] 11 VDD(3V3) 12 P5[2]
13 VSS 14 P0[22] - -
Row M
1 P0[28] 2 P2[28] 3 P3[25] 4 P3[23]
5 P0[14] 6 P1[22] 7 P4[1] 8 P4[2]
9 P1[27] 10 P0[0] 11 P2[13] 12 P2[11]
13 P2[10] 14 P4[19] - -
Row N
1 P0[31] 2 USB_D-2 3 P3[24] 4 P0[30]
5 P2[19] 6 P1[21] 7 P1[23] 8 P2[21]
9 VDD(REG)(3V3) 10 P1[29] 11 P0[1] 12 P4[16]
13 P4[17] 14 P2[12] - -
Row P
1 P2[24] 2 P2[25] 3 P2[18] 4 VSS
5 P1[19] 6 P2[20] 7 P1[24] 8 P1[26]
9 P2[16] 10 P1[28] 11 P2[17] 12 P0[11]
13 P4[4] 14 P4[18] - -
Table 5. Pin allocation table TFBGA180
Not all functions are available on all parts. See Table 2 and Table 7 (EMC pins).
Ball Symbol Ball Symbol Ball Symbol Ball SymbolLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 41 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
The LPC178x/7x use a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and
other bus masters to peripherals in a flexible manner that optimizes performance by
allowing peripherals that are on different slaves ports of the matrix to be accessed
simultaneously by different bus masters.
7.2 ARM Cortex-M3 processor
The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM Cortex-M3 offers many new
features, including a Thumb-2 instruction set, low interrupt latency, hardware division,
hardware single-cycle multiply, interruptable/continuable multiple load and store
instructions, automatic state save and restore for interrupts, tightly integrated interrupt
controller with wake-up interrupt controller, and multiple core buses capable of
simultaneous accesses.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical
Reference Manual that can be found on official ARM website.
7.3 On-chip flash program memory
The LPC178x/7x contain up to 512 kB of on-chip flash program memory. A new two-port
flash accelerator maximizes performance for use with the two fast AHB-Lite buses.
7.4 EEPROM
The LPC178x/7x contains up to 4032 byte of on-chip byte-erasable and
byte-programmable EEPROM data memory.
7.5 On-chip SRAM
The LPC178x/7x contain a total of up to 96 kB on-chip static RAM data memory. This
includes the main 64 kB SRAM, accessible by the CPU and DMA controller on a
higher-speed bus, and up to two additional 16 kB each SRAM blocks situated on a
separate slave port on the AHB multilayer matrix.
This architecture allows CPU and DMA accesses to be spread over three separate RAMs
that can be accessed simultaneously.
7.6 Memory Protection Unit (MPU)
The LPC178x/7x have a Memory Protection Unit (MPU) which can be used to improve the
reliability of an embedded system by protecting critical data within the user application.
The MPU allows separating processing tasks by disallowing access to each other's data,
disabling access to memory regions, allowing memory regions to be defined as read-only
and detecting unexpected memory accesses that could potentially break the system.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 42 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
The MPU separates the memory into distinct regions and implements protection by
preventing disallowed accesses. The MPU supports up to eight regions each of which can
be divided into eight subregions. Accesses to memory locations that are not defined in the
MPU regions, or not permitted by the region setting, will cause the Memory Management
Fault exception to take place.
7.7 Memory map
The LPC178x/7x incorporate several distinct memory regions, shown in the following
figures. Figure 6 shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB peripheral area is 2 MB in size, and is divided to allow for up to 128 peripherals.
The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals.
Each peripheral of either type is allocated 16 kB of space. This allows simplifying the
address decoding for each peripheral.
Table 6. LPC178x/177x memory usage and details
Address range General Use Address range details and description
0x0000 0000 to
0x1FFF FFFF
On-chip non-volatile
memory
0x0000 0000 - 0x0007 FFFF For devices with 512 kB of flash memory.
0x0000 0000 - 0x0003 FFFF For devices with 256 kB of flash memory.
0x0000 0000 - 0x0001 FFFF For devices with 128 kB of flash memory.
0x0000 0000 - 0x0000 FFFF For devices with 64 kB of flash memory.
On-chip main SRAM 0x1000 0000 - 0x1000 FFFF For devices with 64 kB of main SRAM.
0x1000 0000 - 0x1000 7FFF For devices with 32 kB of main SRAM.
0x1000 0000 - 0x1000 3FFF For devices with 16 kB of main SRAM.
Boot ROM 0x1FFF 0000 - 0x1FFF 1FFF 8 kB Boot ROM with flash services.
0x2000 0000 to
0x3FFF FFFF
On-chip SRAM
(typically used for
peripheral data)
0x2000 0000 - 0x2000 1FFF Peripheral RAM - bank 0 (first 8 kB)
0x2000 2000 - 0x2000 3FFF Peripheral RAM - bank 0 (second 8 kB)
0x2000 4000 - 0x2000 7FFF Peripheral RAM - bank 1 (16 kB)
AHB peripherals 0x2008 0000 - 0x200B FFFF See Figure 6 for details
0x4000 0000 to
0x7FFF FFFF
APB Peripherals 0x4000 0000 - 0x4007 FFFF APB0 Peripherals, up to 32 peripheral blocks of
16 kB each.
0x4008 0000 - 0x400F FFFF APB1 Peripherals, up to 32 peripheral blocks of
16 kB each.
0x8000 0000 to
0xDFFF FFFF
Off-chip Memory via
the External Memory
Controller
Four static memory chip selects:
0x8000 0000 - 0x83FF FFFF Static memory chip select 0 (up to 64 MB)
0x9000 0000 - 0x93FF FFFF Static memory chip select 1 (up to 64 MB)
0x9800 0000 - 0x9BFF FFFF Static memory chip select 2 (up to 64 MB)
0x9C00 0000 - 0x9FFF FFFF Static memory chip select 3 (up to 64 MB)
Four dynamic memory chip selects:
0xA000 0000 - 0xAFFF FFFF Dynamic memory chip select 0 (up to 256MB)
0xB000 0000 - 0xBFFF FFFF Dynamic memory chip select 1 (up to 256MB)
0xC000 0000 - 0xCFFF FFFF Dynamic memory chip select 2 (up to 256MB)
0xD000 0000 - 0xDFFF FFFF Dynamic memory chip select 3 (up to 256MB)
0xE000 0000 to
0xE00F FFFF
Cortex-M3 Private
Peripheral Bus
0xE000 0000 - 0xE00F FFFF Cortex-M3 related functions, includes the NVIC
and System Tick Timer.xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 43 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller (1) Not available on all parts. See Table 2 and Table 6. Fig 6. LPC178x/7x memory map
0x4000 4000
0x4000 8000
0x4000 C000
0x4001 0000
0x4001 8000
0x4002 0000
0x4002 8000
0x4002 C000
0x4003 4000
0x4003 0000
0x4003 8000
0x4003 C000
0x4004 0000
0x4004 4000
0x4004 8000
0x4004 C000
0x4005 C000
0x4006 0000
0x4008 0000
0x4002 4000
0x4001 C000
0x4001 4000
0x4000 0000
APB1 peripherals
0x4008 0000
0x4008 8000
0x4008 C000
0x4009 0000
0x4009 4000
0x4009 8000
0x4009 C000
0x400A 0000
0x400A 4000
0x400A 8000
0x400A C000
0x400B 0000
0x400B 4000
0x400B 8000
0x400B C000
0x400C 0000
0x400F C000
0x4010 0000
SSP0
DAC
timer 2
timer 3
UART2
UART3
USART4(1)
I
2C2
1 - 0 reserved
2
3
4
5
6
7
8
9
10
SSP2
I
2S
11
12
reserved
motor control PWM
reserved
30 - 17 reserved
13
14
15
16
31 system control
reserved
reserved
64 kB main static RAM(1)
EMC 4 x static chip select(1)
EMC 4 x dynamic chip select(1)
reserved
private peripheral bus
0 GB 0x0000 0000
0.5 GB
4 GB
1 GB
0x1000 0000
0x1001 0000
0x1FFF 0000
0x2000 0000
0x2000 8000
0x2008 0000
0x2200 0000
0x200A 0000
0x2400 0000
0x2800 0000
0x4000 0000
0x4008 0000
0x4010 0000
0x4200 0000
0x4400 0000
0x8000 0000
0xA000 0000
0xE000 0000
0xE010 0000
0xFFFF FFFF
reserved
reserved
reserved
reserved
reserved
reserved
APB0 peripherals
0xE004 0000
AHB peripherals
APB1 peripherals
peripheral
SRAM bit-band alias addressing
peripheral bit-band alias addressing
16 kB peripheral SRAM1(1) 0x2000 4000
16 kB peripheral SRAM0(1)
LPC178x/7x
0x0008 0000
512 kB on-chip flash(1)
QEI(1)
SD/MMC(1)
APB0 peripherals
WWDT
timer 0
timer 1
UART0
UART1
reserved
reserved
CAN AF RAM
CAN common
CAN1
CAN2
CAN AF registers
PWM0
I
2C0
RTC/event recorder
+ backup registers
GPIO interrupts
pin connect
SSP1
ADC
22 - 19 reserved
I
2C1
31 - 24 reserved
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
23
PWM1
8 kB boot ROM
0x0000 0000
0x0000 0400
active interrupt vectors
+ 256 words
I-code/D-code
memory space
002aaf574
reserved 0x1FFF 2000
0x2900 0000 reserved
reserved
0x2008 0000
0x2008 4000
0x2008 8000
0x2008 C000
0x200A 0000
0x2009 C000
AHB peripherals
LCD(1)
USB(1)
Ethernet(1)
0 GPDMA controller
1
2
3
0x2009 0000 4 CRC engine
0x2009 4000 5
0x2009 8000 GPIO
EMC registers
6
7LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 44 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
7.8 Nested Vectored Interrupt Controller (NVIC)
The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low
interrupt latency and efficient processing of late arriving interrupts.
7.8.1 Features
• Controls system exceptions and peripheral interrupts.
• On the LPC178x/7x, the NVIC supports 40 vectored interrupts.
• 32 programmable interrupt priority levels, with hardware priority level masking.
• Relocatable vector table.
• Non-Maskable Interrupt (NMI).
• Software interrupt generation.
7.8.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
Any pin on port 0 and port 2 regardless of the selected function can be programmed to
generate an interrupt on a rising edge, a falling edge, or both.
7.9 Pin connect block
The pin connect block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
Most pins can also be configured as open-drain outputs or to have a pull-up, pull-down, or
no resistor enabled.
7.10 External memory controller
Remark: Supported memory size and type and EMC bus width vary for different parts
(see Table 2). The EMC pin configuration for each part is shown in Table 7.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 45 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
Table 7. External memory controller pin configuration
Part Data bus pins Address bus
pins
Control pins
SRAM SDRAM
LPC1788FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0],
EMC_CS[3:0],
EMC_OE, EMC_WE
EMC_RAS, EMC_CAS, EMC_DYCS[3:0],
EMC_CLK[1:0], EMC_CKE[3:0],
EMC_DQM[3:0]
LPC1788FET208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0],
EMC_CS[3:0],
EMC_OE, EMC_WE
EMC_RAS, EMC_CAS, EMC_DYCS[3:0],
EMC_CLK[1:0], EMC_CKE[3:0],
EMC_DQM[3:0]
LPC1788FET180 EMC_D[15:0] EMC_A[19:0] EMC_BLS[1:0],
EMC_CS[1:0],
EMC_OE, EMC_WE
EMC_RAS, EMC_CAS, EMC_DYCS[1:0],
EMC_CLK[1:0], EMC_CKE[1:0],
EMC_DQM[1:0]
LPC1788FBD144 EMC_D[7:0] EMC_A[15:0] EMC_BLS[3:2],
EMC_CS[1:0],
EMC_OE, EMC_WE
not available
LPC1787FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0],
EMC_CS_[3:0],
EMC_OE, EMC_WE
EMC_RAS, EMC_CAS, EMC_DYCS[3:0],
EMC_CLK[1:0], EMC_CKE[3:0],
EMC_DQM[3:0]
LPC1786FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0],
EMC_CS[3:0],
EMC_OE, EMC_WE
EMC_RAS, EMC_CAS, EMC_DYCS[3:0],
EMC_CLK[1:0], EMC_CKE[3:0],
EMC_DQM[3:0]
LPC1785FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0],
EMC_CS[3:0],
EMC_OE, EMC_WE
EMC_RAS, EMC_CAS, EMC_DYCS[3:0],
EMC_CLK[1:0], EMC_CKE[3:0],
EMC_DQM[3:0]
LPC1778FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0],
EMC_CS[3:0],
EMC_OE, EMC_WE
EMC_RAS, EMC_CAS, EMC_DYCS[3:0],
EMC_CLK[1:0], EMC_CKE[3:0],
EMC_DQM[3:0]
LPC1778FET208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0],
EMC_CS[3:0],
EMC_OE, EMC_WE
EMC_RAS, EMC_CAS, EMC_DYCS[3:0],
EMC_CLK[1:0], EMC_CKE[3:0],
EMC_DQM[3:0]
LPC1778FET180 EMC_D[15:0] EMC_A[19:0] EMC_BLS[1:0],
EMC_CS[1:0],
EMC_OE, EMC_WE
EMC_RAS, EMC_CAS, EMC_DYCS[1:0],
EMC_CLK[1:0], EMC_CKE[1:0],
EMC_DQM[1:0]
LPC1778FBD144 EMC_D[7:0] EMC_A[15:0] EMC_CS[1:0],
EMC_OE, EMC_WE
not available
LPC1777FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0],
EMC_CS[3:0],
EMC_OE, EMC_WE
EMC_RAS, EMC_CAS, EMC_DYCS[3:0],
EMC_CLK[1:0], EMC_CKE[3:0],
EMC_DQM[3:0]
LPC1776FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0],
EMC_CS[3:0],
EMC_OE, EMC_WE
EMC_RAS, EMC_CAS, EMC_DYCS[3:0],
EMC_CLK[1:0], EMC_CKE[3:0],
EMC_DQM[3:0]
LPC1776FET180 EMC_D[15:0] EMC_A[19:0] EMC_BLS[3:0],
EMC_CS[3:0],
EMC_OE, EMC_WE
EMC_RAS, EMC_CAS, EMC_DYCS[1:0],
EMC_CLK[1:0], EMC_CKE[1:0],
EMC_DQM[1:0]
LPC1774FBD208 EMC_D[31:0] EMC_A[25:0] EMC_BLS[3:0],
EMC_CS[3:0],
EMC_OE, EMC_WE
EMC_RAS, EMC_CAS, EMC_DYCS[3:0],
EMC_CLK[1:0], EMC_CKE[3:0],
EMC_DQM[3:0]
LPC1774FBD144 EMC_D[7:0] EMC_A[15:0] EMC_CS[1:0],
EMC_OE, EMC_WE
not availableLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 46 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
The LPC178x/7x EMC is an ARM PrimeCell MultiPort Memory Controller peripheral
offering support for asynchronous static memory devices such as RAM, ROM, and flash.
In addition, it can be used as an interface with off-chip memory-mapped devices and
peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant
peripheral.
See Table 6 for EMC memory access.
7.10.1 Features
• Dynamic memory interface support including single data rate SDRAM.
• Asynchronous static memory device support including RAM, ROM, and flash, with or
without asynchronous page mode.
• Low transaction latency.
• Read and write buffers to reduce latency and to improve performance.
• 8/16/32 data and 16/20/26 address lines wide static memory support.
• 16 bit and 32 bit wide chip select SDRAM memory support.
• Static memory features include:
– Asynchronous page mode read.
– Programmable Wait States.
– Bus turnaround delay.
– Output enable and write enable delays.
– Extended wait.
• Four chip selects for synchronous memory and four chip selects for static memory
devices.
• Power-saving modes dynamically control EMC_CKE and EMC_CLK outputs to
SDRAMs.
• Dynamic memory self-refresh mode controlled by software.
• Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row
address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB
parts, with 4, 8, 16, or 32 data bits per device.
• Separate reset domains allow the for auto-refresh through a chip reset if desired.
Note: Synchronous static memory devices (synchronous burst mode) are not supported.
7.11 General purpose DMA controller
The GPDMA is an AMBA AHB compliant peripheral allowing selected peripherals to have
DMA support.
The GPDMA enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. The source and
destination areas can each be either a memory region or a peripheral and can be
accessed through the AHB master. The GPDMA controller allows data transfers between
the various on-chip SRAM areas and supports the SD/MMC card interface, all SSPs, the
I
2S, all UARTs, the A/D Converter, and the D/A Converter peripherals. DMA can also be
triggered by selected timer match conditions. Memory-to-memory transfers and transfers
to or from GPIO are supported. LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 47 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
7.11.1 Features
• Eight DMA channels. Each channel can support an unidirectional transfer.
• 16 DMA request lines.
• Single DMA and burst DMA request signals. Each peripheral connected to the DMA
Controller can assert either a burst DMA request or a single DMA request. The DMA
burst size is set by programming the DMA Controller.
• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral transfers are supported.
• Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.
• Hardware DMA channel priority.
• AHB slave DMA programming interface. The DMA Controller is programmed by
writing to the DMA control registers over the AHB slave interface.
• One AHB bus master for transferring data. The interface transfers data when a DMA
request goes active.
• 32-bit AHB master bus width.
• Incrementing or non-incrementing addressing for source and destination.
• Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data.
• Internal four-word FIFO per channel.
• Supports 8, 16, and 32-bit wide transactions.
• Big-endian and little-endian support. The DMA Controller defaults to little-endian
mode on reset.
• An interrupt to the processor can be generated on a DMA completion or when a DMA
error has occurred.
• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read
prior to masking.
7.12 CRC engine
The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings
supports several CRC standards commonly used. To save system power and bus
bandwidth, the CRC engine supports DMA transfers.
7.12.1 Features
• Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32.
– CRC-CCITT: x16 + x12 + x5 + 1
– CRC-16: x16 + x15 + x2 + 1
– CRC-32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
• Bit order reverse and 1’s complement programmable setting for input data and CRC
sum.
• Programmable seed number setting.
• Supports CPU PIO or DMA back-to-back transfer.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 48 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
• Accept any size of data width per write: 8, 16 or 32-bit.
– 8-bit write: 1-cycle operation.
– 16-bit write: 2-cycle operation (8-bit x 2-cycle).
– 32-bit write: 4-cycle operation (8-bit x 4-cycle).
7.13 LCD controller
Remark: The LCD controller is available on parts LPC1788/87/86/85.
The LCD controller provides all of the necessary control signals to interface directly to a
variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT
panels can be operated. The display resolution is selectable and can be up to 1024 768
pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.
An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the
displayed data) while still supporting a large number of colors.
The LCD interface includes its own DMA controller to allow it to operate independently of
the CPU and other system functions. A built-in FIFO acts as a buffer for display data,
providing flexibility for system timing. Hardware cursor support can further reduce the
amount of CPU time needed to operate the display.
7.13.1 Features
• AHB master interface to access frame buffer.
• Setup and control via a separate AHB slave interface.
• Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.
• Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays
with 4-bit or 8-bit interfaces.
• Supports single and dual-panel color STN displays.
• Supports Thin Film Transistor (TFT) color displays.
• Programmable display resolution including, but not limited to: 320 200, 320 240,
640 200, 640 240, 640 480, 800 600, and 1024 768.
• Hardware cursor support for single-panel displays.
• 15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support.
• 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.
• 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.
• 16 bpp true-color non-palettized, for color STN and TFT.
• 24 bpp true-color non-palettized, for color TFT.
• Programmable timing for different display panels.
• 256 entry, 16-bit palette RAM, arranged as a 128 32-bit RAM.
• Frame, line, and pixel clock signals.
• AC bias signal for STN, data enable signal for TFT panels.
• Supports little and big-endian, and Windows CE data formats.
• LCD panel clock may be generated from the peripheral clock, or from a clock input
pin.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 49 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
7.14 Ethernet
Remark: The Ethernet block is available on parts LPC1788/86 and LPC1778/76.
The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC
designed to provide optimized performance through the use of DMA hardware
acceleration. Features include a generous suite of control registers, half or full duplex
operation, flow control, control frames, hardware acceleration for transmit retry, receive
packet filtering and wake-up on LAN activity. Automatic frame transmission and reception
with scatter-gather DMA off-loads many operations from the CPU.
The Ethernet block and the CPU share the ARM Cortex-M3 D-code and system bus
through the AHB-multilayer matrix to access the various on-chip SRAM blocks for
Ethernet data, control, and status information.
The Ethernet block interfaces between an off-chip Ethernet PHY using the Media
Independent Interface (MII) or Reduced MII (RMII) protocol and the on-chip Media
Independent Interface Management (MIIM) serial bus.
7.14.1 Features
• Ethernet standards support:
– Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX,
100 Base-FX, and 100 Base-T4.
– Fully compliant with IEEE standard 802.3.
– Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back
pressure.
– Flexible transmit and receive frame options.
– Virtual Local Area Network (VLAN) frame support
– .
• Memory management:
– Independent transmit and receive buffers memory mapped to shared SRAM.
– DMA managers with scatter/gather DMA and arrays of frame descriptors.
– Memory traffic optimized by buffering and pre-fetching.
• Enhanced Ethernet features:
– Receive filtering.
– Multicast and broadcast frame support for both transmit and receive.
– Optional automatic Frame Check Sequence (FCS) insertion with Circular
Redundancy Check (CRC) for transmit.
– Selectable automatic transmit frame padding.
– Over-length frame support for both transmit and receive allows any length frames.
– Promiscuous receive mode.
– Automatic collision back-off and frame retransmission.
– Includes power management by clock switching.
– Wake-on-LAN power management support allows system wake-up: using the
receive filters or a magic frame detection filter.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 50 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
• Physical interface:
– Attachment of external PHY chip through standard MII or RMII interface.
– PHY register access is available via the MIIM interface.
7.15 USB interface
Remark: The USB Device/Host/OTG controller is available on parts LPC1788/87/86/85
and LPC1778/77/76. The USB Device-only controller is available on parts LPC1774.
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports hot
plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
Details on typical USB interfacing solutions can be found in Section 14.1.
7.15.1 USB device controller
The device controller enables 12 Mbit/s data exchange with a USB host controller. It
consists of a register interface, serial interface engine, endpoint buffer memory, and a
DMA controller. The serial interface engine decodes the USB data stream and writes data
to the appropriate endpoint buffer. The status of a completed USB transfer or error
condition is indicated via status registers. An interrupt is also generated if enabled. When
enabled, the DMA controller transfers data between the endpoint buffer and the USB
RAM.
7.15.1.1 Features
• Fully compliant with USB 2.0 Specification (full speed).
• Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM.
• Supports Control, Bulk, Interrupt and Isochronous endpoints.
• Scalable realization of endpoints at run time.
• Endpoint Maximum packet size selection (up to USB maximum specification) by
software at run time.
• Supports SoftConnect and GoodLink features.
• While USB is in the Suspend mode, the LPC178x/7x can enter one of the reduced
power modes and wake up on USB activity.
• Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints.
• Allows dynamic switching between CPU-controlled and DMA modes.
• Double buffer implementation for Bulk and Isochronous endpoints.
7.15.2 USB host controller
The host controller enables full- and low-speed data exchange with USB devices attached
to the bus. It consists of register interface, serial interface engine and DMA controller. The
register interface complies with the Open Host Controller Interface (OHCI) specification.
7.15.2.1 Features
• OHCI compliant.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 51 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
• Two downstream ports.
• Supports per-port power switching.
7.15.3 USB OTG controller
USB OTG is a supplement to the USB 2.0 Specification that augments the capability of
existing mobile devices and USB peripherals by adding host functionality for connection to
USB peripherals.
The OTG Controller integrates the host controller, device controller, and a master-only I2C
interface to implement OTG dual-role device functionality. The dedicated I2C interface
controls an external OTG transceiver.
7.15.3.1 Features
• Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision
1.0a.
• Hardware support for Host Negotiation Protocol (HNP).
• Includes a programmable timer required for HNP and Session Request Protocol
(SRP).
• Supports any OTG transceiver compliant with the OTG Transceiver Specification
(CEA-2011), Rev. 1.0.
7.16 SD/MMC card interface
Remark: The SD/MMC card interface is available on parts LPC1788/87/86/85 and parts
LPC1778/77/76.
The Secure Digital and Multimedia Card Interface (MCI) allows access to external SD
memory cards. The SD card interface conforms to the SD Multimedia Card Specification
Version 2.11.
7.16.1 Features
• The MCI provides all functions specific to the SD/MMC memory card. These include
the clock generation unit, power management control, and command and data
transfer.
• Conforms to Multimedia Card Specification v2.11.
• Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96.
• Can be used as a multimedia card bus or a secure digital memory card bus host. The
SD/MMC can be connected to several multimedia cards or a single secure digital
memory card.
• DMA supported through the GPDMA controller.
7.17 Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back as well as the current state of the port pins.
LPC178x/7x use accelerated GPIO functions:LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 52 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
• GPIO registers are accessed through the AHB multilayer bus so that the fastest
possible I/O timing can be achieved.
• Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
• All GPIO registers are byte and half-word addressable.
• Entire port value can be written in one instruction.
• Support for Cortex-M3 bit banding.
• Support for use with the GPDMA controller.
Additionally, any pin on Port 0 and Port 2 providing a digital function can be programmed
to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is
asynchronous, so it may operate when clocks are not present such as during Power-down
mode. Each enabled interrupt can be used to wake up the chip from Power-down mode.
7.17.1 Features
• Bit level set and clear registers allow a single instruction to set or clear any number of
bits in one port.
• Direction control of individual bits.
• All I/O default to inputs after reset.
• Pull-up/pull-down resistor configuration and open-drain configuration can be
programmed through the pin connect block for each GPIO pin.
7.18 12-bit ADC
The LPC178x/7x contain one ADC. It is a single 12-bit successive approximation ADC
with eight channels and DMA support.
7.18.1 Features
• 12-bit successive approximation ADC.
• Input multiplexing among eight pins.
• Power-down mode.
• Measurement range VSS to VREFP.
• 12-bit conversion rate: up to 400 kHz.
• Individual channels can be selected for conversion.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition of input pin or Timer Match signal.
• Individual result registers for each ADC channel to reduce interrupt overhead.
• DMA support.
7.19 10-bit DAC
The LPC178x/7x contain one DAC. The DAC allows to generate a variable analog output.
The maximum output value of the DAC is VREFP.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 53 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
7.19.1 Features
• 10-bit DAC.
• Resistor string architecture.
• Buffered output.
• Power-down mode.
• Selectable output drive.
• Dedicated conversion timer.
• DMA support.
7.20 UARTs
Remark: USART4 is not available on part LPC1774FBD144.
The LPC178x/7x contain five UARTs. In addition to standard transmit and receive data
lines, UART1 also provides a full modem control handshake interface and support for
RS-485/9-bit mode allowing both software address detection and automatic address
detection using 9-bit mode.
The UARTs include a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.20.1 Features
• Maximum UART data bit rate of 7.5 MBit/s.
• 16 B Receive and Transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
• Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• Auto-baud capability.
• Fractional divider for baud rate control, auto baud capabilities and FIFO control
mechanism that enables software flow control implementation.
• Support for RS-485/9-bit/EIA-485 mode and multiprocessor addressing.
• All UARTs have DMA support for both transmit and receive.
• UART1 equipped with standard modem interface signals. This module also provides
full support for hardware flow control (auto-CTS/RTS).
• USART4 includes an IrDA mode to support infrared communication.
• USART4 supports synchronous mode and a smart card mode conforming to
ISO7816-3.
7.21 SSP serial I/O controller
The LPC178x/7x contain three SSP controllers. The SSP controller is capable of
operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and
slaves on the bus. Only a single master and a single slave can communicate on the bus LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 54 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits
to 16 bits of data flowing from the master to the slave and from the slave to the master. In
practice, often only one of these data flows carries meaningful data.
7.21.1 Features
• Maximum SSP speed of 33 Mbit/s (master) or 10 Mbit/s (slave).
• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses.
• Synchronous serial communication.
• Master or slave operation.
• 8-frame FIFOs for both transmit and receive.
• 4-bit to 16-bit frame.
• DMA transfers supported by GPDMA.
7.22 I2C-bus serial I/O controllers
The LPC178x/7x contain three I2C-bus controllers.
The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line
(SCL) and a Serial Data Line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be
controlled by more than one bus master connected to it.
7.22.1 Features
• All I2C-bus controllers can use standard GPIO pins with bit rates of up to 400 kbit/s
(Fast I2C-bus). The I2C0-bus interface uses special open-drain pins with bit rates of
up to 400 kbit/s.
• The I2C-bus interface supports Fast-mode Plus with bit rates up to 1 Mbit/s for I2C0
using pins P5[2] and P5[3].
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus can be used for test and diagnostic purposes.
• Both I2C-bus controllers support multiple address recognition and a bus monitor
mode.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 55 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
7.23 I2S-bus serial I/O controllers
The LPC178x/7x contain one I2S-bus interface. The I2S-bus provides a standard
communication interface for digital audio applications.
The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line,
and one word select signal. The basic I2S connection has one master, which is always the
master, and one slave. The I2S interface on the LPC178x/7x provides a separate transmit
and receive channel, each of which can operate as either a master or a slave.
7.23.1 Features
• The interface has separate input/output channels each of which can operate in master
or slave mode.
• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
• Mono and stereo audio data supported.
• The sampling frequency can range from 16 kHz to 48 kHz (16, 22.05, 32, 44.1,
48) kHz.
• Configurable word select period in master mode (separately for I2S input and output).
• Two 8 word FIFO data buffers are provided, one for transmit and one for receive.
• Generates interrupt requests when buffer levels cross a programmable boundary.
• Two DMA requests, controlled by programmable buffer levels. These are connected
to the GPDMA block.
• Controls include reset, stop and mute options separately for I2S input and I2S output.
7.24 CAN controller and acceptance filters
The LPC178x/7x contain one CAN controller with two channels.
The Controller Area Network (CAN) is a serial communications protocol which efficiently
supports distributed real-time control with a very high level of security. Its domain of
application ranges from high-speed networks to low cost multiplex wiring.
The CAN block is intended to support multiple CAN buses simultaneously, allowing the
device to be used as a gateway, switch, or router between two of CAN buses in industrial
or automotive applications.
Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN
Library block, but the 8-bit registers of those devices have been combined in 32-bit words
to allow simultaneous access in the ARM environment. The main operational difference is
that the recognition of received Identifiers, known in CAN terminology as Acceptance
Filtering, has been removed from the CAN controllers and centralized in a global
Acceptance Filter.
7.24.1 Features
• Two CAN controllers and buses.
• Data rates to 1 Mbit/s on each bus.
• 32-bit register and RAM access.
• Compatible with CAN specification 2.0B, ISO 11898-1.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 56 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
• Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN
buses.
• Acceptance Filter can provide FullCAN-style automatic reception for selected
Standard Identifiers.
• FullCAN messages can generate interrupts.
7.25 General purpose 32-bit timers/external event counters
The LPC178x/7x include four 32-bit timer/counters.
The timer/counter is designed to count cycles of the system derived clock or an
externally-supplied clock. It can optionally generate interrupts, generate timed DMA
requests, or perform other actions at specified timer values, based on four match
registers. Each timer/counter also includes two capture inputs to trap the timer value when
an input signal transitions, optionally generating an interrupt.
7.25.1 Features
• A 32-bit timer/counter with a programmable 32-bit prescaler.
• Counter or timer operation.
• Two 32-bit capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event may also generate an interrupt.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
• Up to two match registers can be used to generate timed DMA requests.
7.26 Pulse Width Modulator (PWM)
The LPC178x/7x contain two standard PWMs.
The PWM is based on the standard Timer block and inherits all of its features, although
only the PWM function is pinned out on the LPC178x/7x. The Timer is designed to count
cycles of the system derived clock and optionally switch pins, generate interrupts or
perform other actions when specified timer values occur, based on seven match registers.
The PWM function is in addition to these features, and is based on match register events.
The ability to separately control rising and falling edge locations allows the PWM to be
used for more applications. For instance, multi-phase motor control typically requires
three non-overlapping PWM outputs with individual control of all three pulse widths and
positions.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 57 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
Two match registers can be used to provide a single edge controlled PWM output. One
match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon
match. The other match register controls the PWM edge position. Additional single edge
controlled PWM outputs require only one match register each, since the repetition rate is
the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a
rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs.
Three match registers can be used to provide a PWM output with both edges controlled.
Again, the PWMMR0 match register controls the PWM cycle rate. The other match
registers control the two PWM edge positions. Additional double edge controlled PWM
outputs require only two match registers each, since the repetition rate is the same for all
PWM outputs.
With double edge controlled PWM outputs, specific match registers control the rising and
falling edge of the output. This allows both positive going PWM pulses (when the rising
edge occurs prior to the falling edge), and negative going PWM pulses (when the falling
edge occurs prior to the rising edge).
7.26.1 Features
• LPC178x/7x has two PWM blocks with Counter or Timer operation (may use the
peripheral clock or one of the capture inputs as the clock source).
• Seven match registers allow up to 6 single edge controlled or 3 double edge
controlled PWM outputs, or a mix of both types. The match registers also allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Supports single edge controlled and/or double edge controlled PWM outputs. Single
edge controlled PWM outputs all go high at the beginning of each cycle unless the
output is a constant low. Double edge controlled PWM outputs can have either edge
occur at any position within a cycle. This allows for both positive going and negative
going pulses.
• Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will
occur at the same repetition rate.
• Double edge controlled PWM outputs can be programmed to be either positive going
or negative going pulses.
• Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must ‘release’ new match values before they can become
effective.
• May be used as a standard 32-bit timer/counter with a programmable 32-bit prescaler
if the PWM mode is not enabled.
7.27 Motor control PWM
The LPC178x/7x contain one motor control PWM.
The motor control PWM is a specialized PWM supporting 3-phase motors and other
combinations. Feedback inputs are provided to automatically sense rotor position and use
that information to ramp speed up or down. An abort input is also provided that causes the LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 58 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
PWM to immediately release all motor drive outputs. At the same time, the motor control
PWM is highly configurable for other generalized timing, counting, capture, and compare
applications.
The maximum PWM speed is determined by the PWM resolution (n) and the operating
frequency f: PWM speed = f/2n (see Table 8).
7.28 Quadrature Encoder Interface (QEI)
Remark: The QEI is available on parts LPC1788/87/86 and LPC1778/77/76
A quadrature encoder, also known as a 2-channel incremental encoder, converts angular
displacement into two pulse signals. By monitoring both the number of pulses and the
relative phase of the two signals, the user can track the position, direction of rotation, and
velocity. In addition, a third channel, or index signal, can be used to reset the position
counter. The quadrature encoder interface decodes the digital pulses from a quadrature
encoder wheel to integrate position over time and determine direction of rotation. In
addition, the QEI can capture the velocity of the encoder wheel.
7.28.1 Features
• Tracks encoder position.
• Increments/decrements depending on direction.
• Programmable for 2 or 4 position counting.
• Velocity capture using built-in timer.
• Velocity compare function with “less than” interrupt.
• Uses 32-bit registers for position and velocity.
• Three position compare registers with interrupts.
• Index counter for revolution counting.
• Index compare register with interrupts.
• Can combine index and position interrupts to produce an interrupt for whole and
partial revolution displacement.
• Digital filter with programmable delays for encoder input signals.
• Can accept decoded signal inputs (clk and direction).
• Connected to APB.
7.29 ARM Cortex-M3 system tick timer
The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a 10 ms interval. In the LPC178x/7x, this timer can be
clocked from the internal AHB clock or from a device pin.
Table 8. PWM speed at operating frequency 120 MHz
PWM resolution PWM speed
6 bit 1.875 MHz
8 bit 0.468 MHz
10 bit 0.117 MHzLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 59 of 122
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32-bit ARM Cortex-M3 microcontroller
7.30 Windowed WatchDog Timer (WWDT)
The purpose of the watchdog is to reset the controller if software fails to periodically
service it within a programmable time window.
7.30.1 Features
• Internally resets chip if not periodically reloaded during the programmable time-out
period.
• Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
• Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
• Incorrect feed sequence causes reset or interrupt if enabled.
• Flag to indicate watchdog reset.
• Programmable 24-bit timer with internal prescaler.
• Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in
multiples of Tcy(WDCLK) 4.
• The Watchdog Clock (WDCLK) source is a dedicated watchdog oscillator, which is
always running if the watchdog timer is enabled.
7.31 RTC and backup registers
The RTC is a set of counters for measuring time when system power is on, and optionally
when it is off. The RTC on the LPC178x/7x is designed to have very low power
consumption. The RTC will typically run from the main chip power supply conserving
battery power while the rest of the device is powered up. When operating from a battery,
the RTC will continue working down to 2.1 V. Battery power can be provided from a
standard 3 V lithium button cell.
An ultra-low power 32 kHz oscillator provides a 1 Hz clock to the time counting portion of
the RTC, moving most of the power consumption out of the time counting function.
The RTC includes a calibration mechanism to allow fine-tuning the count rate in a way
that will provide less than 1 second per day error when operated at a constant voltage and
temperature.
The RTC contains a small set of backup registers (20 bytes) for holding data while the
main part of the LPC178x/7x is powered off.
The RTC includes an alarm function that can wake up the LPC178x/7x from all reduced
power modes with a time resolution of 1 s.
7.31.1 Features
• Measures the passage of time to maintain a calendar and clock.
• Ultra low power design to support battery powered systems.
• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and
Day of Year.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 60 of 122
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32-bit ARM Cortex-M3 microcontroller
• Dedicated power supply pin can be connected to a battery or to the main 3.3 V.
• Periodic interrupts can be generated from increments of any field of the time registers.
• Backup registers (20 bytes) powered by VBAT.
• RTC power supply is isolated from the rest of the chip.
7.32 Event monitor/recorder
The event monitor/recorder allows recording of tampering events in sealed product
enclosures. Sensors report any attempt to open the enclosure, or to tamper with the
device in any other way. The event monitor/recorder stores records of such events when
the device is powered only by the backup battery.
7.32.1 Features
• Supports three digital event inputs in the VBAT power domain.
• An event is defined as a level change at the digital event inputs.
• For each event channel, two timestamps mark the first and the last occurrence of an
event. Each channel also has a dedicated counter tracking the total number of events.
Timestamp values are taken from the RTC.
• Runs in VBAT power domain, independent of system power supply. The
event/recorder/monitor can therefore operate in Deep power-down mode.
• Very low power consumption.
• Interrupt available if system is running.
• A qualified event can be used as a wake-up trigger.
• State of event interrupts accessible by software through GPIO.
7.33 Clocking and power control
7.33.1 Crystal oscillators
The LPC178x/7x include four independent oscillators. These are the main oscillator, the
IRC oscillator, the watchdog oscillator, and the RTC oscillator.
Following reset, the LPC178x/7x will operate from the Internal RC oscillator until switched
by software. This allows systems to operate without any external crystal and the boot
loader code to operate at a known frequency.
See Figure 7 for an overview of the LPC178x/7x clock generation.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 61 of 122
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32-bit ARM Cortex-M3 microcontroller
7.33.1.1 Internal RC oscillator
The IRC may be used as the clock that drives the PLL and subsequently the CPU. The
nominal IRC frequency is 12 MHz. The IRC is trimmed to 1 % accuracy over the entire
voltage and temperature range.
Upon power-up or any chip reset, the LPC178x/7x use the IRC as the clock source.
Software may later switch to one of the other available clock sources.
7.33.1.2 Main oscillator
The main oscillator can be used as the clock source for the CPU, with or without using the
PLL. The main oscillator also provides the clock source for the alternate PLL1.
The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the main
PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock
frequency is referred to as CCLK elsewhere in this document. The frequencies of
PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The
clock frequency for each peripheral can be selected individually and is referred to as
PCLK. Refer to Section 7.33.2 for additional information.
Fig 7. LPC178x/7x clock generation block diagram
MAIN PLL0
IRC oscillator
main oscillator
(osc_clk)
CLKSRCSEL
(system clock select)
sysclk
pll_clk
CCLKSEL
(CPU clock select)
002aaf531
pll_clk
ALT PLL1
CPU CLOCK
DIVIDER
alt_pll_clk
cclk
PERIPHERAL
CLOCK DIVIDER pclk
EMC
CLOCK DIVIDER emc_clk
sysclk
alt_pll_clk
pll_clk
USBCLKSEL
(USB clock select)
USB
CLOCK DIVIDER usb_clk
sysclk
LPC178x/7xLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 62 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
7.33.1.3 RTC oscillator
The RTC oscillator provides a 1 Hz clock to the RTC and a 32 kHz clock output that can
be output on the CLKOUT pin in order to allow trimming the RTC oscillator without
interference from a probe.
7.33.1.4 Watchdog oscillator
The Watchdog Timer has a dedicated watchdog oscillator that provides a 500 kHz clock to
the Watchdog Timer. The watchdog oscillator is always running if the Watchdog Timer is
enabled. The Watchdog oscillator clock can be output on the CLKOUT pin in order to
allow observe its frequency.
In order to allow Watchdog Timer operation with minimum power consumption, which can
be important in reduced power modes, the Watchdog oscillator frequency is not tightly
controlled. The Watchdog oscillator frequency will vary over temperature and power
supply within a particular part, and may vary by processing across different parts. This
variation should be taken into account when determining Watchdog reload values.
Within a particular part, temperature and power supply variations can produce up to a
17 % frequency variation. Frequency variation between devices under the same
operating conditions can be up to 30 %.
7.33.2 Main PLL (PLL0) and Alternate PLL (PLL1)
PLL0 (also called the Main PLL) and PLL1 (also called the Alternate PLL) are functionally
identical but have somewhat different input possibilities and output connections. These
possibilities are shown in Figure 7. The Main PLL can receive its input from either the IRC
or the main oscillator and can potentially be used to provide the clocks to nearly
everything on the device. The Alternate PLL receives its input only from the main oscillator
and is intended to be used as an alternate source of clocking to the USB. The USB has
timing needs that may not always be filled by the Main PLL.
Both PLLs are disabled and powered off on reset. If the Alternate PLL is left disabled, the
USB clock can be supplied by PLL0 if everything is set up to provide 48 MHz to the USB
clock through that route. The source for each clock must be selected via the CLKSEL
registers and can be further reduced by clock dividers as needed.
PLL0 accepts an input clock frequency from either the IRC or the main oscillator. If only
the Main PLL is used, then its output frequency must be an integer multiple of all other
clocks needed in the system. PLL1 takes its input only from the main oscillator, requiring
an external crystal in the range of 10 to 25 MHz. In each PLL, the Current Controlled
Oscillator (CCO) operates in the range of 156 MHz to 320 MHz, so there are additional
dividers to bring the output down to the desired frequencies. The minimum output divider
value is 2, insuring that the output of the PLLs have a 50 % duty cycle.
If the USB is used, the possibilities for the CPU clock and other clocks will be limited by
the requirements that the frequency be precise and very low jitter, and that the PLL0
output must be a multiple of 48 MHz. Even multiples of 48 MHz that are within the
operating range of the PLL are 192 MHz and 288 MHz. Also, only the main oscillator in
conjunction with the PLL can meet the precision and jitter specifications for USB. It is due
to these limitations that the Alternate PLL is provided.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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32-bit ARM Cortex-M3 microcontroller
The alternate PLL accepts an input clock frequency from the main oscillator in the range
of 10 MHz to 25 MHz only. When used as the USB clock, the input frequency is multiplied
up to a multiple of 48 MHz (192 MHz or 288 MHz as described above).
7.33.3 Wake-up timer
The LPC178x/7x begin operation at power-up and when awakened from Power-down
mode by using the 12 MHz IRC oscillator as the clock source. This allows chip operation
to resume quickly. If the main oscillator or the PLL is needed by the application, software
will need to enable these features and wait for them to stabilize before they are used as a
clock source.
When the main oscillator is initially activated, the wake-up timer allows software to ensure
that the main oscillator is fully functional before the processor uses it as a clock source
and starts to execute instructions. This is important at power on, all types of reset, and
whenever any of the aforementioned functions are turned off for any reason. Since the
oscillator and other functions are turned off during Power-down mode, any wake-up of the
processor from Power-down mode makes use of the wake-up Timer.
The wake-up timer monitors the crystal oscillator to check whether it is safe to begin code
execution. When power is applied to the chip, or when some event caused the chip to exit
Power-down mode, some time is required for the oscillator to produce a signal of sufficient
amplitude to drive the clock logic. The amount of time depends on many factors, including
the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its electrical
characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g.,
capacitors), and the characteristics of the oscillator itself under the existing ambient
conditions.
7.33.4 Power control
The LPC178x/7x support a variety of power control features. There are four special
modes of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode,
and Deep power-down mode. The CPU clock rate may also be controlled as needed by
changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider
value. This allows a trade-off of power versus processing speed based on application
requirements. In addition, the peripheral power control allows shutting down the clocks to
individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all
dynamic power use in any peripherals that are not required for the application. Each of the
peripherals has its own clock divider which provides even better power control.
The integrated PMU (Power Management Unit) automatically adjusts internal regulators
to minimize power consumption during Sleep, Deep-sleep, Power-down, and Deep
power-down modes.
The LPC178x/7x also implement a separate power domain to allow turning off power to
the bulk of the device while maintaining operation of the RTC and a small set of registers
for storing data during any of the power-down modes.
7.33.4.1 Sleep mode
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence other than re-enabling the clock to the ARM
core.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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32-bit ARM Cortex-M3 microcontroller
In Sleep mode, execution of instructions is suspended until either a Reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
The DMA controller can continue to work in Sleep mode and has access to the peripheral
RAMs and all peripheral registers. The flash memory and the main SRAM are not
available in Sleep mode, they are disabled in order to save power.
Wake-up from Sleep mode will occur whenever any enabled interrupt occurs.
7.33.4.2 Deep-sleep mode
In Deep-sleep mode, the oscillator is shut down and the chip receives no internal clocks.
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Deep-sleep mode and the logic levels of chip pins remain static.
The output of the IRC is disabled but the IRC is not powered down to allow fast wake-up.
The RTC oscillator is not stopped because the RTC interrupts may be used as the
wake-up source. The PLL is automatically turned off and disconnected. The clock divider
registers are automatically reset to zero.
The Deep-sleep mode can be terminated and normal operation resumed by either a
Reset or certain specific interrupts that are able to function without clocks. Since all
dynamic operation of the chip is suspended, Deep-sleep mode reduces chip power
consumption to a very low value. Power to the flash memory is left on in Deep-sleep
mode, allowing a very quick wake-up.
Wake-up from Deep-sleep mode can initiated by the NMI, External Interrupts EINT0
through EINT3, GPIO interrupts, the Ethernet Wake-on-LAN interrupt, Brownout Detect,
an RTC Alarm interrupt, a USB input pin transition (USB activity interrupt), a CAN input
pin transition, or a Watchdog Timer time-out, when the related interrupt is enabled.
Wake-up will occur whenever any enabled interrupt occurs.
On wake-up from Deep-sleep mode, the code execution and peripherals activities will
resume after four cycles expire if the IRC was used before entering Deep-sleep mode. If
the main external oscillator was used, the code execution will resume when 4096 cycles
expire. PLL and clock dividers need to be reconfigured accordingly.
7.33.4.3 Power-down mode
Power-down mode does everything that Deep-sleep mode does but also turns off the
power to the IRC oscillator and the flash memory. This saves more power but requires
waiting for resumption of flash operation before execution of code or data access in the
flash memory can be accomplished.
When the chip enters Power-down mode, the IRC, the main oscillator, and all clocks are
stopped. The RTC remains running if it has been enabled and RTC interrupts may be
used to wake up the CPU. The flash is forced into Power-down mode. The PLLs are
automatically turned off and the clock selection multiplexers are set to use the system
clock sysclk (the reset state). The clock divider control registers are automatically reset to
zero. If the Watchdog timer is running, it will continue running in Power-down mode.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 65 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
On the wake-up of Power-down mode, if the IRC was used before entering Power-down
mode, it will take IRC 60 s to start-up. After this, four IRC cycles will expire before the
code execution can then be resumed if the code was running from SRAM. In the
meantime, the flash wake-up timer then counts 12 MHz IRC clock cycles to make the
100 s flash start-up time. When it times out, access to the flash will be allowed. Users
need to reconfigure the PLL and clock dividers accordingly.
7.33.4.4 Deep power-down mode
In Deep power-down mode, power is shut off to the entire chip with the exception of the
RTC module and the RESET pin.
To optimize power conservation, the user has the additional option of turning off or
retaining power to the 32 kHz oscillator. It is also possible to use external circuitry to turn
off power to the on-chip regulator via the VDD(REG)(3V3) pins and/or the I/O power via the
VDD(3V3) pins after entering Deep Power-down mode. Power must be restored before
device operation can be restarted.
The LPC178x/7x can wake up from Deep power-down mode via the RESET pin or an
alarm match event of the RTC.
7.33.4.5 Wake-up Interrupt Controller (WIC)
The WIC allows the CPU to automatically wake up from any enabled priority interrupt that
can occur while the clocks are stopped in Deep-sleep, Power-down, and Deep
power-down modes.
The WIC works in connection with the Nested Vectored Interrupt Controller (NVIC). When
the CPU enters Deep-sleep, Power-down, or Deep power-down mode, the NVIC sends a
mask of the current interrupt situation to the WIC.This mask includes all of the interrupts
that are both enabled and of sufficient priority to be serviced immediately. With this
information, the WIC simply notices when one of the interrupts has occurred and then it
wakes up the CPU.
The WIC eliminates the need to periodically wake up the CPU and poll the interrupts
resulting in additional power savings.
7.33.5 Peripheral power control
A power control for peripherals feature allows individual peripherals to be turned off if they
are not needed in the application, resulting in additional power savings.
7.33.6 Power domains
The LPC178x/7x provide two independent power domains that allow the bulk of the
device to have power removed while maintaining operation of the RTC and the backup
registers.
On the LPC178x/7x, I/O pads are powered by VDD(3V3), while VDD(REG)(3V3) powers the
on-chip voltage regulator which in turn provides power to the CPU and most of the
peripherals.
Depending on the LPC178x/7x application, a design can use two power options to
manage power consumption.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 66 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
The first option assumes that power consumption is not a concern and the design ties the
VDD(3V3) and VDD(REG)(3V3) pins together. This approach requires only one 3.3 V power
supply for both pads, the CPU, and peripherals. While this solution is simple, it does not
support powering down the I/O pad ring “on the fly” while keeping the CPU and
peripherals alive.
The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and
a dedicated 3.3 V supply for the CPU (VDD(REG)(3V3)). Having the on-chip voltage regulator
powered independently from the I/O pad ring enables shutting down of the I/O pad power
supply “on the fly” while the CPU and peripherals stay active.
The VBAT pin supplies power only to the RTC domain. The RTC operates at very low
power, which can be supplied by an external battery. The device core power
(VDD(REG)(3V3)) is used to operate the RTC whenever VDD(REG)(3V3) is present. There is no
power drain from the RTC battery when VDD(REG)(3V3) is at nominal levels and
VDD(REG)(3V3) > VBAT.
Fig 8. Power distribution
REAL-TIME CLOCK
BACKUP REGISTERS
REGULATOR
32 kHz
OSCILLATOR
POWER
SELECTOR
ULTRA-LOW
POWER
REGULATOR
RTC POWER DOMAIN
MAIN POWER DOMAIN
002aaf530
RTCX1
VBAT
(typical 3.0 V)
VDD(REG)(3V3)
(typical 3.3 V)
RTCX2
VDD(3V3)
VSS
to memories,
peripherals,
oscillators,
PLLs
to core
to I/O pads
ADC
DAC
ADC POWER DOMAIN
VDDA
VREFP
VSSA
LPC178x/7xLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 67 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
7.34 System control
7.34.1 Reset
Reset has four sources on the LPC178x/7x: the RESET pin, the Watchdog reset,
Power-On Reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a
Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating
voltage attains a usable level, starts the Wake-up timer (see description in
Section 7.33.3), causing reset to remain asserted until the external Reset is de-asserted,
the oscillator is running, a fixed number of clocks have passed, and the flash controller
has completed its initialization.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
7.34.2 Brownout detection
The LPC178x/7x include 2-stage monitoring of the voltage on the VDD(REG)(3V3) pins. If this
voltage falls below 2.2 V (typical), the BOD asserts an interrupt signal to the Vectored
Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable
Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the
signal by reading a dedicated status register.
The second stage of low-voltage detection asserts a reset to inactivate the LPC178x/7x
when the voltage on the VDD(REG)(3V3) pins falls below 1.85 V (typical). This reset prevents
alteration of the flash as operation of the various elements of the chip would otherwise
become unreliable due to low voltage. The BOD circuit maintains this reset down below
1 V, at which point the power-on reset circuitry maintains the overall reset.
Both the 2.2 V and 1.85 V thresholds include some hysteresis. In normal operation, this
hysteresis allows the 2.2 V detection to reliably interrupt, or a regularly executed event
loop to sense the condition.
7.34.3 Code security (Code Read Protection - CRP)
This feature of the LPC178x/7x allows user to enable different levels of security in the
system so that access to the on-chip flash and use of the JTAG and ISP can be restricted.
When needed, CRP is invoked by programming a specific pattern into a dedicated flash
location. IAP commands are not affected by the CRP.
There are three levels of the Code Read Protection.
CRP1 disables access to chip via the JTAG and allows partial flash update (excluding
flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is
required and flash field updates are needed but all sectors can not be erased.
CRP2 disables access to chip via the JTAG and only allows full flash erase and update
using a reduced set of the ISP commands.
Running an application with level CRP3 selected fully disables any access to chip via the
JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too.
It is up to the user’s application to provide (if needed) flash update mechanism using IAP
calls or call reinvoke ISP command to enable flash update via UART0.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 68 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
7.34.4 APB interface
The APB peripherals are split into two separate APB buses in order to distribute the bus
bandwidth and thereby reducing stalls caused by contention between the CPU and the
GPDMA controller.
7.34.5 AHB multilayer matrix
The LPC178x/7x use an AHB multilayer matrix. This matrix connects the instruction
(I-code) and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the
main (64 kB) SRAM, and the Boot ROM. The GPDMA can also access all of these
memories. Additionally, the matrix connects the CPU system bus and all of the DMA
controllers to the various peripheral functions.
7.34.6 External interrupt inputs
The LPC178x/7x include up to 30 edge sensitive interrupt inputs combined with one level
sensitive external interrupt input as selectable pin function. The external interrupt input
can optionally be used to wake up the processor from Power-down mode.
7.34.7 Memory mapping control
The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table
to alternate locations in the memory map. This is controlled via the Vector Table Offset
Register contained in the NVIC.
The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address
space. The vector table must be located on a 128 word (512 byte) boundary because the
NVIC on the LPC178x/7x is configured for 128 total interrupts.
7.35 Debug control
Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and
trace functions are supported in addition to a standard JTAG debug and parallel trace
functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four
watch points.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 69 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
8. Limiting values
[1] The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
[2] Including voltage on outputs in 3-state mode.
[3] Not to exceed 4.6 V.
[4] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined
based on the required shelf lifetime. Please refer to the JEDEC spec for further details.
[5] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
Table 9. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol Parameter Conditions Min Max Unit
VDD(3V3) supply voltage (3.3 V) external rail 2.4 3.6 V
VDD(REG)(3V3) regulator supply voltage (3.3 V) 2.4 3.6 V
VDDA analog 3.3 V pad supply voltage 0.5 +4.6 V
Vi(VBAT) input voltage on pin VBAT for the RTC 0.5 +4.6 V
Vi(VREFP) input voltage on pin VREFP 0.5 +4.6 V
VIA analog input voltage on ADC related
pins
0.5 +5.1 V
VI input voltage 5 V tolerant digital
I/O pins;
VDD(3V3) 2.4V
[2] 0.5 +5.5 V
VDD(3V3) 0 V 0.5 +3.6 V
other I/O pins [2][3] 0.5 VDD(3V3) +
0.5
V
IDD supply current per supply pin - 100 mA
ISS ground current per ground pin - 100 mA
Ilatch I/O latch-up current (0.5VDD(3V3)) < VI
< (1.5VDD(3V3));
Tj
< 125 C
- 100 mA
Tstg storage temperature non-operating [4] 65 +150 C
Ptot(pack) total power dissipation (per package) based on package
heat transfer, not
device power
consumption
- 1.5 W
VESD electrostatic discharge voltage human body
model; all pins
[5] - 4000 VLPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 70 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
9. Thermal characteristics
The average chip junction temperature, Tj (C), can be calculated using the following
equation:
(1)
• Tamb = ambient temperature (C),
• Rth(j-a) = the package junction-to-ambient thermal resistance (C/W)
• PD = sum of internal and I/O power dissipation
Table 10. Thermal characteristics
VDD = 3.0 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified;
Symbol Parameter Min Typ Max Unit
Tj(max) maximum junction
temperature
- - 125 C
Table 11. Thermal resistance (LQFP packages)
Tamb = 40 C to +85 C unless otherwise specified.
Symbol Conditions Thermal resistance in C/W ±15 %
LQFP208 LQFP144
ja JEDEC (4.5 in 4 in)
0 m/s 27.4 31.5
1 m/s 25.7 28.1
2.5 m/s 24.4 26.2
Single-layer (4.5 in 3 in)
0 m/s 35.4 43.2
1 m/s 31.2 35.7
2.5 m/s 29.2 32.8
jc - 8.8 7.8
jb - 15.4 13.8
Table 12. Thermal resistance value (TFBGA packages)
Tamb = 40 C to +85 C unless otherwise specified.
Symbol Conditions Thermal resistance in C/W ±15 %
TFBGA208 TFBGA180
ja JEDEC (4.5 in 4 in)
0 m/s 41 45.5
1 m/s 35 38.3
2.5 m/s 31 33.8
8-layer (4.5 in 3 in)
0 m/s 34.9 38
1 m/s 30.9 33.5
2.5 m/s 28 29.8
jc - 8.3 8.9
jb - 13.6 12
Tj Tamb PD Rth j a – += LPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 71 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
10. Static characteristics
Table 13. Static characteristics
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
Supply pins
VDD(3V3) supply voltage (3.3 V) external rail [2] 2.4 3.3 3.6 V
VDD(REG)(3V3) regulator supply voltage
(3.3 V)
2.4 3.3 3.6 V
VDDA analog 3.3 V pad supply
voltage
[3] 2.7 3.3 3.6 V
Vi(VBAT) input voltage on pin
VBAT
[4] 2.1 3.0 3.6 V
Vi(VREFP) input voltage on pin
VREFP
[3] 2.7 3.3 VDDA V
IDD(REG)(3V3) regulator supply current
(3.3 V)
active mode; code
while(1){}
executed from flash; all
peripherals disabled
PCLK = CCLK/4
CCLK = 12 MHz; PLL
disabled
[5][6] - 7- mA
CCLK = 120 MHz; PLL
enabled
[5][7] - 51- mA
active mode; code
while(1){}
executed from flash; all
peripherals enabled;
PCLK = CCLK/4
CCLK = 12 MHz; PLL
disabled
[5][6] 14
CCLK = 120 MHz; PLL
enabled
[5][7] 100 mA
Sleep mode [5][8] - 5- mA
Deep-sleep mode [5][9] - 550 - A
Power-down mode [5][9] - 280 - A
IBAT battery supply current RTC running;
part powered down;
VDD(REG)(3V3) =0 V;
Vi(VBAT) = 3.0 V;
VDD(3V3) = 0 V.
[10] -
1 - A
part powered;
VDD(REG)(3V3) = 3.3 V;
Vi(VBAT) = 3.0 V
[11] <10 nALPC178X_7X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 5 — 9 September 2014 72 of 122
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
Standard port pins, RESET
IIL LOW-level input current VI = 0 V; on-chip pull-up
resistor disabled
- 0.5 10 nA
IIH HIGH-level input
current
VI = VDD(3V3); on-chip
pull-down resistor
disabled
- 0.5 10 nA
IOZ OFF-state output
current
VO = 0 V; VO = VDD(3V3);
on-chip pull-up/down
resistors disabled
- 0.5 10 nA
VI input voltage pin configured to provide
a digital function
[15][16]
[17]
0- 5.0 V
VO output voltage output active 0 - VDD(3V3) V
VIH HIGH-level input
voltage
0.7VDD(3V3) --V
VIL LOW-level input voltage - - 0.3VDD(3V3) V
Vhys hysteresis voltage 0.4 - - V
VOH HIGH-level output
voltage
IOH = 4 mA VDD(3V3)
0.4
--V
VOL LOW-level output
voltage
IOL = 4 mA --0.4 V
IOH HIGH-level output
current
VOH = VDD(3V3) 0.4 V 4 - - mA
IOL LOW-level output
current
VOL = 0.4 V 4- - mA
IOHS HIGH-level short-circuit
output current
VOH =0V [18] - - 45 mA
IOLS LOW-level short-circuit
output current
VOL = VDD(3V3) [18] --50 mA
Ipd pull-down current VI =5V 10 50 150 A
Ipu pull-up current VI =0V 15 50 85 A
VDD(3V3) < VI <5V 0 0 0 A
I
2C-bus pins (P0[27] and P0[28])
VIH HIGH-level input
voltage
0.7VDD(3V3) --V
VIL LOW-level input voltage - - 0.3VDD(3V3) V
Vhys hysteresis voltage - 0.05
VDD(3V3)
- V
VOL LOW-level output
voltage
IOLS = 3 mA --0.4 V
ILI input leakage current VI = VDD(3V3) [19] - 24 A
VI =5V - 10 22 A
USB pins
IOZ OFF-state output
current
0V>
NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
22. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 5
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 8
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9
7 Functional description . . . . . . . . . . . . . . . . . . 40
7.1 Architectural overview . . . . . . . . . . . . . . . . . . 40
7.2 ARM Cortex-M3 processor . . . . . . . . . . . . . . . 41
7.3 On-chip flash program memory . . . . . . . . . . . 41
7.4 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.5 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 41
7.6 Memory Protection Unit (MPU). . . . . . . . . . . . 41
7.7 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.8 Nested Vectored Interrupt Controller (NVIC) . 44
7.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
7.8.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 44
7.9 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 44
7.10 External memory controller. . . . . . . . . . . . . . . 44
7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.11 General purpose DMA controller . . . . . . . . . . 46
7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.12 CRC engine . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.13 LCD controller. . . . . . . . . . . . . . . . . . . . . . . . . 48
7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.14 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.15 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.15.1 USB device controller . . . . . . . . . . . . . . . . . . . 50
7.15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.15.2 USB host controller. . . . . . . . . . . . . . . . . . . . . 50
7.15.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.15.3 USB OTG controller . . . . . . . . . . . . . . . . . . . . 51
7.15.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.16 SD/MMC card interface . . . . . . . . . . . . . . . . . 51
7.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.17 Fast general purpose parallel I/O . . . . . . . . . . 51
7.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.18 12-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.19 10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.20 UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
7.21 SSP serial I/O controller. . . . . . . . . . . . . . . . . 53
7.21.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
7.22 I2C-bus serial I/O controllers . . . . . . . . . . . . . 54
7.22.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
7.23 I2S-bus serial I/O controllers . . . . . . . . . . . . . 55
7.23.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.24 CAN controller and acceptance filters . . . . . . 55
7.24.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.25 General purpose 32-bit timers/external
event counters . . . . . . . . . . . . . . . . . . . . . . . . 56
7.25.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
7.26 Pulse Width Modulator (PWM). . . . . . . . . . . . 56
7.26.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.27 Motor control PWM . . . . . . . . . . . . . . . . . . . . 57
7.28 Quadrature Encoder Interface (QEI) . . . . . . . 58
7.28.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7.29 ARM Cortex-M3 system tick timer . . . . . . . . . 58
7.30 Windowed WatchDog Timer (WWDT) . . . . . . 59
7.30.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7.31 RTC and backup registers . . . . . . . . . . . . . . . 59
7.31.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7.32 Event monitor/recorder . . . . . . . . . . . . . . . . . 60
7.32.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7.33 Clocking and power control . . . . . . . . . . . . . . 60
7.33.1 Crystal oscillators. . . . . . . . . . . . . . . . . . . . . . 60
7.33.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 61
7.33.1.2 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 61
7.33.1.3 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 62
7.33.1.4 Watchdog oscillator . . . . . . . . . . . . . . . . . . . . 62
7.33.2 Main PLL (PLL0) and Alternate PLL (PLL1) . 62
7.33.3 Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 63
7.33.4 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.33.4.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.33.4.2 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 64
7.33.4.3 Power-down mode . . . . . . . . . . . . . . . . . . . . . 64
7.33.4.4 Deep power-down mode . . . . . . . . . . . . . . . . 65
7.33.4.5 Wake-up Interrupt Controller (WIC) . . . . . . . . 65
7.33.5 Peripheral power control . . . . . . . . . . . . . . . . 65
7.33.6 Power domains . . . . . . . . . . . . . . . . . . . . . . . 65
7.34 System control . . . . . . . . . . . . . . . . . . . . . . . . 67
7.34.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.34.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 67
7.34.3 Code security (Code Read Protection - CRP) 67
7.34.4 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.34.5 AHB multilayer matrix . . . . . . . . . . . . . . . . . . 68
7.34.6 External interrupt inputs . . . . . . . . . . . . . . . . . 68
7.34.7 Memory mapping control . . . . . . . . . . . . . . . . 68
7.35 Debug control. . . . . . . . . . . . . . . . . . . . . . . . . 68NXP Semiconductors LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
© NXP Semiconductors N.V. 2014. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 9 September 2014
Document identifier: LPC178X_7X
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 69
9 Thermal characteristics . . . . . . . . . . . . . . . . . 70
10 Static characteristics. . . . . . . . . . . . . . . . . . . . 71
10.1 Power consumption . . . . . . . . . . . . . . . . . . . . 74
10.2 Peripheral power consumption . . . . . . . . . . . . 76
10.3 Electrical pin characteristics . . . . . . . . . . . . . . 78
11 Dynamic characteristics . . . . . . . . . . . . . . . . . 80
11.1 Flash memory. . . . . . . . . . . . . . . . . . . . . . . . . 80
11.2 External memory interface . . . . . . . . . . . . . . . 81
11.3 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.4 Internal oscillators. . . . . . . . . . . . . . . . . . . . . . 87
11.5 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.6 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.7 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.8 I2S-bus interface. . . . . . . . . . . . . . . . . . . . . . . 91
11.9 LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.10 SD/MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12 ADC electrical characteristics . . . . . . . . . . . . 94
13 DAC electrical characteristics . . . . . . . . . . . . 97
14 Application information. . . . . . . . . . . . . . . . . . 98
14.1 Suggested USB interface solutions . . . . . . . . 98
14.2 Crystal oscillator XTAL input and component
selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
14.3 XTAL Printed-Circuit Board (PCB) layout
guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
14.4 Standard I/O pin configuration . . . . . . . . . . . 104
14.5 Reset pin configuration. . . . . . . . . . . . . . . . . 105
14.6 Reset pin configuration for RTC operation . . 105
15 Package outline . . . . . . . . . . . . . . . . . . . . . . . 107
16 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
17 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . 114
18 References . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
19 Revision history. . . . . . . . . . . . . . . . . . . . . . . 116
20 Legal information. . . . . . . . . . . . . . . . . . . . . . 119
20.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . 119
20.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . 119
20.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 119
20.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . 120
21 Contact information. . . . . . . . . . . . . . . . . . . . 120
22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
1. General description
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embedded
applications which include an ARM Cortex-M0 coprocessor, up to 264 kB of SRAM,
advanced configurable peripherals such as the State Configurable Timer/PWM
(SCTimer/PWM) and the Serial General-Purpose I/O (SGPIO) interface, two High-speed
USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and
analog peripherals. The LPC4350/30/20/10 operate at CPU frequencies of up to 204
MHz.
The ARM Cortex-M4 is a next generation 32-bit core that offers system enhancements
such as low power consumption, enhanced debug features, and a high level of support
block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a
Harvard architecture with separate local instruction and data buses as well as a third bus
for peripherals, and includes an internal prefetch unit that supports speculative branching.
The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD
instructions. A hardware floating-point processor is integrated in the core.
The ARM Cortex-M0 coprocessor is an energy-efficient and easy-to-use 32-bit core which
is code- and tool-compatible with the Cortex-M4 core. The Cortex-M0 coprocessor offers
up to 204 MHz performance with a simple instruction set and reduced code size.
See Section 17 “References” for additional documentation.
2. Features and benefits
Cortex-M4 Processor core
ARM Cortex-M4 processor, running at frequencies of up to 204 MHz.
ARM Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions.
ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
Hardware floating-point unit.
Non-maskable Interrupt (NMI) input.
JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch
points.
Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
System tick timer.
Cortex-M0 Processor core
ARM Cortex-M0 co-processor capable of off-loading the main ARM Cortex-M4
application processor.
Running at frequencies of up to 204 MHz.
JTAG and built-in NVIC.
LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 flashless MCU; up to 264 kB SRAM;
Ethernet; two HS USBs; advanced configurable peripherals
Rev. 4.2 — 18 August 2014 Product data sheetLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 2 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
On-chip memory
Up to 264 kB SRAM for code and data use.
Multiple SRAM blocks with separate bus access. Two SRAM blocks can be
powered down individually.
64 kB ROM containing boot code and on-chip software drivers.
64 bit + 256 bit general-purpose One-Time Programmable (OTP) memory.
Clock generation unit
Crystal oscillator with an operating range of 1 MHz to 25 MHz.
12 MHz Internal RC (IRC) oscillator trimmed to 1.5 % accuracy over temperature
and voltage.
Ultra-low power Real-Time Clock (RTC) crystal oscillator.
Three PLLs allow CPU operation up to the maximum CPU rate without the need for
a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the
third PLL can be used as audio PLL.
Clock output.
Configurable digital peripherals
Serial GPIO (SGPIO) interface.
State Configurable Timer (SCTimer/PWM) subsystem on AHB.
Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and
outputs to event driven peripherals like the timers, SCT, and ADC0/1.
Serial interfaces
Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to
52 MB per second.
10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high
throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time
stamping (IEEE 1588-2008 v2).
One High-speed USB 2.0 Host/Device/OTG interface with DMA support and
on-chip high-speed PHY (USB0).
One High-speed USB 2.0 Host/Device interface with DMA support, on-chip
full-speed PHY and ULPI interface to external high-speed PHY (USB1).
USB interface electrical test software included in ROM USB stack.
Four 550 UARTs with DMA support: one UART with full modem interface; one
UART with IrDA interface; three USARTs support UART synchronous mode and a
smart card interface conforming to ISO7816 specification.
Up to two C_CAN 2.0B controllers with one channel each. Use of C_CAN controller
excludes operation of all other peripherals connected to the same bus bridge. See
Figure 1 and Ref. 2.
Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA
support.
One SPI controller.
One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O
pins conforming to the full I2C-bus specification. Supports data rates of up to
1 Mbit/s.
One standard I2C-bus interface with monitor mode and with standard I/O pins.
Two I2S interfaces, each with DMA support and with one input and one output.LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 3 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
Digital peripherals
External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,
and SDRAM devices.
LCD controller with DMA support and a programmable display resolution of up to
1024 H 768 V. Supports monochrome and color STN panels and TFT color
panels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel
mapping.
Secure Digital Input Output (SD/MMC) card interface.
Eight-channel General-Purpose DMA controller can access all memories on the
AHB and all DMA-capable AHB slaves.
Up to 164 General-Purpose Input/Output (GPIO) pins with configurable
pull-up/pull-down resistors.
GPIO registers are located on the AHB for fast access. GPIO ports have DMA
support.
Up to eight GPIO pins can be selected from all GPIO pins as edge and level
sensitive interrupt sources.
Two GPIO group interrupt modules enable an interrupt based on a programmable
pattern of input states of a group of GPIO pins.
Four general-purpose timer/counters with capture and match capabilities.
One motor control Pulse Width Modulator (PWM) for three-phase motor control.
One Quadrature Encoder Interface (QEI).
Repetitive Interrupt timer (RI timer).
Windowed watchdog timer (WWDT).
Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes
of battery powered backup registers.
Alarm timer; can be battery powered.
Analog peripherals
One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.
Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s.
Up to eight input channels per ADC.
Unique ID for each device.
Power
Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip internal voltage regulator for
the core supply and the RTC power domain.
RTC power domain can be powered separately by a 3 V battery supply.
Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
Processor wake-up from Sleep mode via wake-up interrupts from various
peripherals.
Wake-up from Deep-sleep, Power-down, and Deep power-down modes via
external interrupts and interrupts generated by battery powered blocks in the RTC
power domain.
Brownout detect with four separate thresholds for interrupt and forced reset.
Power-On Reset (POR).
Available as LBGA256, TFBGA180, and TFBGA100 packages and as LQFP144
package.LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 4 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
3. Applications
Motor control Embedded audio applications
Power management Industrial automation
White goods e-metering
RFID readersLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 5 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
4. Ordering information
4.1 Ordering options
Table 1. Ordering information
Type number Package
Name Description Version
LPC4350FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2
LPC4350FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls SOT570-3
LPC4330FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm SOT740-2
LPC4330FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls SOT570-3
LPC4330FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC4330FBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC4320FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC4320FBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
LPC4310FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm SOT926-1
LPC4310FBD144 LQFP144 Plastic low profile quad flat package; 144 leads; body 20 20 1.4 mm SOT486-1
Table 2. Ordering options
Type number Total
SRAM
LCD Ethernet USB0
(Host,
Device,
OTG)
USB1
(Host,
Device)/
ULPI
interface
ADC
channels
PWM QEI GPIO Package
LPC4350FET256 264 kB yes yes yes yes/yes 8 yes yes 164 LBGA256
LPC4350FET180 264 kB yes yes yes yes/yes 8 yes yes 118 TFBGA180
LPC4330FET256 264 kB no yes yes yes/yes 8 yes yes 164 LBGA256
LPC4330FET180 264 kB no yes yes yes/yes 8 yes yes 118 TFBGA180
LPC4330FET100 264 kB no yes yes yes/no 4 no no 49 TFBGA100
LPC4330FBD144 264 kB no yes yes yes/no 8 yes no 83 LQFP144
LPC4320FET100 200 kB no no yes no 4 no no 49 TFBGA100
LPC4320FBD144 200 kB no no yes no 8 yes no 83 LQFP144
LPC4310FET100 168 kB no no no no 4 no no 49 TFBGA100
LPC4310FBD144 168 kB no no no no 8 yes no 83 LQFP144LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 6 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
5. Block diagram
(1) Not available on all parts (see Table 2).
Fig 1. LPC4350/30/20/10 Block diagram
ARM
CORTEX-M4
TEST/DEBUG
INTERFACE I-code bus D-code bus
system bus
DMA LCD(1) SD/
MMC
ETHERNET(1)
10/100
MAC
IEEE 1588
HIGH-SPEED
USB0(1)
HOST/
DEVICE/OTG
HIGH-SPEED
USB1(1)
HOST/DEVICE
EMC
HIGH-SPEED PHY
32 kB AHB SRAM
16 +16 kB AHB SRAM
SPIFI
AES ENCRYPTION/
DECRYPTION(2)
HS GPIO
SPI
SGPIO
SCT
64 kB ROM
I
2C0
I
2S0
I
2S1
C_CAN1
MOTOR
CONTROL
PWM(1)
TIMER3
TIMER2
USART2
USART3
SSP1
RI TIMER
QEI(1)
GIMA
BRIDGE 0 BRIDGE 1 BRIDGE 2 BRIDGE 3 BRIDGE
BRIDGE
AHB MULTILAYER MATRIX
LPC4350/30/20/20/10
128 kB LOCAL SRAM
72 kB LOCAL SRAM
10-bit ADC0
10-bit ADC1
C_CAN0
I
2C1
10-bit DAC
BRIDGE
RGU
CCU2
CGU
CCU1
ALARM TIMER
CONFIGURATION
REGISTERS
OTP MEMORY
EVENT ROUTER
POWER MODE CONTROL
12 MHz IRC
RTC POWER DOMAIN
BACKUP REGISTERS
RTC RTC OSC
002aaf772
slaves
slaves
masters
ARM
CORTEX-M0
TEST/DEBUG
INTERFACE
= connected to GPDMA
GPIO
INTERRUPTS
GPIO GROUP0
INTERRUPT
GPIO GROUP1
INTERRUPT
WWDT
USART0
UART1
SSP0
TIMER0
TIMER1
SCULPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 7 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
6. Pinning information
6.1 Pinning
6.2 Pin description
On the LPC4350/30/20/10, digital pins are grouped into 16 ports, named P0 to P9 and PA
to PF, with up to 20 pins used per port. Each digital pin can support up to eight different
digital functions, including General-Purpose I/O (GPIO), selectable through the System
Configuration Unit (SCU) registers. The pin name is not indicative of the GPIO port
assigned to it.
Fig 2. Pin configuration LBGA256 package Fig 3. Pin configuration TFBGA180 package
002aaf813
LPC4350/30FET256
Transparent top view
T
R
P
N
M
L
J
G
K
H
F
E
D
C
B
A
2 4 6 8 10 12
13
14
15
16
1 3 5 7 9 11
ball A1
index area
002aag374
LPC4350/30FET180
Transparent top view
N
L
P
M
K
J
H
G
F
D
B
E
C
A
2 4 6 8 10 12
13
14
1 3 5 7 9 11
ball A1
index area
Fig 4. Pin configuration TFBGA100 package Fig 5. Pin configuration LQFP144 package
002aag375
LPC4330/20/10FET100
Transparent top view
J
G
K
H
F
E
D
C
B
A
13579 2 4 6 8 10
ball A1
index area
LPC4330/20/10FBD144
72
1
36
108
73
37
109
144
002aag377LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 8 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
Not all functions listed in Table 3 are available on all packages. See Table 2 for availability
of USB0, USB1, Ethernet, and LCD functions.
The parts contain two 10-bit ADCs (ADC0 and ADC1). The input channels of ADC0 and
ADC1 on dedicated pins and multiplexed pins are combined in such a way that all channel
0 inputs (named ADC0_0 and ADC1_0) are tied together and connected to both, channel
0 on ADC0 and channel 0 on ADC1, channel 1 inputs (named ADC0_1 and ADC1_1) are
tied together and connected to channel 1 on ADC0 and ADC1, and so forth. There are
eight ADC channels total for the two ADCs.LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 9 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
Table 3. Pin description
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
Description
Multiplexed digital pins
P0_0 L3 K3 G2 32 [2] N;
PU
I/O GPIO0[0] — General purpose digital input/output pin.
I/O SSP1_MISO — Master In Slave Out for SSP1.
I ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface).
I/O SGPIO0 — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
I/O I2S0_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I
2S-bus specification.
I/O I2S1_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I
2S-bus specification.
P0_1 M2 K2 G1 34 [2] N;
PU
I/O GPIO0[1] — General purpose digital input/output pin.
I/O SSP1_MOSI — Master Out Slave in for SSP1.
I ENET_COL — Ethernet Collision detect (MII interface).
I/O SGPIO1 — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
ENET_TX_EN — Ethernet transmit enable (RMII/MII
interface).
I/O I2S1_TX_SDA — I2S1 transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I
2S-bus specification.
P1_0 P2 L1 H1 38 [2] N;
PU
I/O GPIO0[4] — General purpose digital input/output pin.
I CTIN_3 — SCTimer/PWM input 3. Capture input 1 of timer 1.
I/O EMC_A5 — External memory address line 5.
- R — Function reserved.
- R — Function reserved.
I/O SSP0_SSEL — Slave Select for SSP0.
I/O SGPIO7 — General purpose digital input/output pin.
- R — Function reserved.LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 10 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P1_1 R2 N1 K2 42 [2] N;
PU
I/O GPIO0[8] — General purpose digital input/output pin. Boot pin
(see Table 5).
O CTOUT_7 — SCTimer/PWM output 7. Match output 3 of timer
1.
I/O EMC_A6 — External memory address line 6.
I/O SGPIO8 — General purpose digital input/output pin.
- R — Function reserved.
I/O SSP0_MISO — Master In Slave Out for SSP0.
- R — Function reserved.
- R — Function reserved.
P1_2 R3 N2 K1 43 [2] N;
PU
I/O GPIO0[9] — General purpose digital input/output pin. Boot pin
(see Table 5).
O CTOUT_6 — SCTimer/PWM output 6. Match output 2 of timer
1.
I/O EMC_A7 — External memory address line 7.
I/O SGPIO9 — General purpose digital input/output pin.
- R — Function reserved.
I/O SSP0_MOSI — Master Out Slave in for SSP0.
- R — Function reserved.
- R — Function reserved.
P1_3 P5 M2 J1 44 [2] N;
PU
I/O GPIO0[10] — General purpose digital input/output pin.
O CTOUT_8 — SCTimer/PWM output 8. Match output 0 of timer
2.
I/O SGPIO10 — General purpose digital input/output pin.
O EMC_OE — LOW active Output Enable signal.
O USB0_IND1 — USB0 port indicator LED control
output 1.
I/O SSP1_MISO — Master In Slave Out for SSP1.
- R — Function reserved.
O SD_RST — SD/MMC reset signal for MMC4.4 card.
P1_4 T3 P2 J2 47 [2] N;
PU
I/O GPIO0[11] — General purpose digital input/output pin.
O CTOUT_9 — SCTimer/PWM output 9. Match output 3 of timer
3.
I/O SGPIO11 — General purpose digital input/output pin.
O EMC_BLS0 — LOW active Byte Lane select signal 0.
O USB0_IND0 — USB0 port indicator LED control output 0.
I/O SSP1_MOSI — Master Out Slave in for SSP1.
- R — Function reserved.
O SD_VOLT1 — SD/MMC bus voltage select output 1.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 11 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P1_5 R5 N3 J4 48 [2] N;
PU
I/O GPIO1[8] — General purpose digital input/output pin.
O CTOUT_10 — SCTimer/PWM output 10. Match output 3 of
timer 3.
- R — Function reserved.
O EMC_CS0 — LOW active Chip Select 0 signal.
I USB0_PWR_FAULT — Port power fault signal indicating
overcurrent condition; this signal monitors over-current on the
USB bus (external circuitry required to detect over-current
condition).
I/O SSP1_SSEL — Slave Select for SSP1.
I/O SGPIO15 — General purpose digital input/output pin.
O SD_POW — SD/MMC power monitor output.
P1_6 T4 P3 K4 49 [2] N;
PU
I/O GPIO1[9] — General purpose digital input/output pin.
I CTIN_5 — SCTimer/PWM input 5. Capture input 2 of timer 2.
- R — Function reserved.
O EMC_WE — LOW active Write Enable signal.
- R — Function reserved.
- R — Function reserved.
I/O SGPIO14 — General purpose digital input/output pin.
I/O SD_CMD — SD/MMC command signal.
P1_7 T5 N4 G4 50 [2] N;
PU
I/O GPIO1[0] — General purpose digital input/output pin.
I U1_DSR — Data Set Ready input for UART1.
O CTOUT_13 — SCTimer/PWM output 13. Match output 3 of
timer 3.
I/O EMC_D0 — External memory data line 0.
O USB0_PPWR — VBUS drive signal (towards external charge
pump or power management unit); indicates that VBUS must
be driven (active HIGH).
Add a pull-down resistor to disable the power switch at reset.
This signal has opposite polarity compared to the USB_PPWR
used on other NXP LPC parts.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 12 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P1_8 R7 M5 H5 51 [2] N;
PU
I/O GPIO1[1] — General purpose digital input/output pin.
O U1_DTR — Data Terminal Ready output for UART1.
O CTOUT_12 — SCTimer/PWM output 12. Match output 3 of
timer 3.
I/O EMC_D1 — External memory data line 1.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
O SD_VOLT0 — SD/MMC bus voltage select output 0.
P1_9 T7 N5 J5 52 [2] N;
PU
I/O GPIO1[2] — General purpose digital input/output pin.
O U1_RTS — Request to Send output for UART1.
O CTOUT_11 — SCTimer/PWM output 11. Match output 3 of
timer 2.
I/O EMC_D2 — External memory data line 2.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
I/O SD_DAT0 — SD/MMC data bus line 0.
P1_10 R8 N6 H6 53 [2] N;
PU
I/O GPIO1[3] — General purpose digital input/output pin.
I U1_RI — Ring Indicator input for UART1.
O CTOUT_14 — SCTimer/PWM output 14. Match output 2 of
timer 3.
I/O EMC_D3 — External memory data line 3.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
I/O SD_DAT1 — SD/MMC data bus line 1.
P1_11 T9 P8 J7 55 [2] N;
PU
I/O GPIO1[4] — General purpose digital input/output pin.
I U1_CTS — Clear to Send input for UART1.
O CTOUT_15 — SCTimer/PWM output 15. Match output 3 of
timer 3.
I/O EMC_D4 — External memory data line 4.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
I/O SD_DAT2 — SD/MMC data bus line 2.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 13 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P1_12 R9 P7 K7 56 [2] N;
PU
I/O GPIO1[5] — General purpose digital input/output pin.
I U1_DCD — Data Carrier Detect input for UART1.
- R — Function reserved.
I/O EMC_D5 — External memory data line 5.
I T0_CAP1 — Capture input 1 of timer 0.
- R — Function reserved.
I/O SGPIO8 — General purpose digital input/output pin.
I/O SD_DAT3 — SD/MMC data bus line 3.
P1_13 R10 L8 H8 60 [2] N;
PU
I/O GPIO1[6] — General purpose digital input/output pin.
O U1_TXD — Transmitter output for UART1.
- R — Function reserved.
I/O EMC_D6 — External memory data line 6.
I T0_CAP0 — Capture input 0 of timer 0.
- R — Function reserved.
I/O SGPIO9 — General purpose digital input/output pin.
I SD_CD — SD/MMC card detect input.
P1_14 R11 K7 J8 61 [2] N;
PU
I/O GPIO1[7] — General purpose digital input/output pin.
I U1_RXD — Receiver input for UART1.
- R — Function reserved.
I/O EMC_D7 — External memory data line 7.
O T0_MAT2 — Match output 2 of timer 0.
- R — Function reserved.
I/O SGPIO10 — General purpose digital input/output pin.
- R — Function reserved.
P1_15 T12 P11 K8 62 [2] N;
PU
I/O GPIO0[2] — General purpose digital input/output pin.
O U2_TXD — Transmitter output for USART2.
I/O SGPIO2 — General purpose digital input/output pin.
I ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface).
O T0_MAT1 — Match output 1 of timer 0.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 14 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P1_16 M7 L5 H9 64 [2] N;
PU
I/O GPIO0[3] — General purpose digital input/output pin.
I U2_RXD — Receiver input for USART2.
I/O SGPIO3 — General purpose digital input/output pin.
I ENET_CRS — Ethernet Carrier Sense (MII interface).
O T0_MAT0 — Match output 0 of timer 0.
- R — Function reserved.
- R — Function reserved.
I ENET_RX_DV — Ethernet Receive Data Valid (RMII/MII
interface).
P1_17 M8 L6 H10 66 [3] N;
PU
I/O GPIO0[12] — General purpose digital input/output pin.
I/O U2_UCLK — Serial clock input/output for USART2 in
synchronous mode.
- R — Function reserved.
I/O ENET_MDIO — Ethernet MIIM data input and output.
I T0_CAP3 — Capture input 3 of timer 0.
O CAN1_TD — CAN1 transmitter output.
I/O SGPIO11 — General purpose digital input/output pin.
- R — Function reserved.
P1_18 N12 N10 J10 67 [2] N;
PU
I/O GPIO0[13] — General purpose digital input/output pin.
I/O U2_DIR — RS-485/EIA-485 output enable/direction control for
USART2.
- R — Function reserved.
O ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface).
O T0_MAT3 — Match output 3 of timer 0.
I CAN1_RD — CAN1 receiver input.
I/O SGPIO12 — General purpose digital input/output pin.
- R — Function reserved.
P1_19 M11 N9 K9 68 [2] N;
PU
I ENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit
Clock (MII interface) or Ethernet Reference Clock (RMII
interface).
I/O SSP1_SCK — Serial clock for SSP1.
- R — Function reserved.
- R — Function reserved.
O CLKOUT — Clock output pin.
- R — Function reserved.
O I2S0_RX_MCLK — I2S receive master clock.
I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 15 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P1_20 M10 J10 K10 70 [2] N;
PU
I/O GPIO0[15] — General purpose digital input/output pin.
I/O SSP1_SSEL — Slave Select for SSP1.
- R — Function reserved.
O ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface).
I T0_CAP2 — Capture input 2 of timer 0.
- R — Function reserved.
I/O SGPIO13 — General purpose digital input/output pin.
- R — Function reserved.
P2_0 T16 N14 G10 75 [2] N;
PU
I/O SGPIO4 — General purpose digital input/output pin.
O U0_TXD — Transmitter output for USART0.
I/O EMC_A13 — External memory address line 13.
O USB0_PPWR — VBUS drive signal (towards external charge
pump or power management unit); indicates that VBUS must
be driven (active HIGH).
Add a pull-down resistor to disable the power switch at reset.
This signal has opposite polarity compared to the USB_PPWR
used on other NXP LPC parts.
I/O GPIO5[0] — General purpose digital input/output pin.
- R — Function reserved.
I T3_CAP0 — Capture input 0 of timer 3.
O ENET_MDC — Ethernet MIIM clock.
P2_1 N15 M13 G7 81 [2] N;
PU
I/O SGPIO5 — General purpose digital input/output pin.
I U0_RXD — Receiver input for USART0.
I/O EMC_A12 — External memory address line 12.
I USB0_PWR_FAULT — Port power fault signal indicating
overcurrent condition; this signal monitors over-current on the
USB bus (external circuitry required to detect over-current
condition).
I/O GPIO5[1] — General purpose digital input/output pin.
- R — Function reserved.
I T3_CAP1 — Capture input 1 of timer 3.
- R — Function reserved.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 16 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P2_2 M15 L13 F5 84 [2] N;
PU
I/O SGPIO6 — General purpose digital input/output pin.
I/O U0_UCLK — Serial clock input/output for USART0 in
synchronous mode.
I/O EMC_A11 — External memory address line 11.
O USB0_IND1 — USB0 port indicator LED control output 1.
I/O GPIO5[2] — General purpose digital input/output pin.
I CTIN_6 — SCTimer/PWM input 6. Capture input 1 of timer 3.
I T3_CAP2 — Capture input 2 of timer 3.
- R — Function reserved.
P2_3 J12 G11 D8 87 [3] N;
PU
I/O SGPIO12 — General purpose digital input/output pin.
I/O I2C1_SDA — I
2C1 data input/output (this pin does not use a
specialized I2C pad).
O U3_TXD — Transmitter output for USART3.
I CTIN_1 — SCTimer/PWM input 1. Capture input 1 of timer 0.
Capture input 1 of timer 2.
I/O GPIO5[3] — General purpose digital input/output pin.
- R — Function reserved.
O T3_MAT0 — Match output 0 of timer 3.
O USB0_PPWR — VBUS drive signal (towards external charge
pump or power management unit); indicates that VBUS must
be driven (active HIGH).
Add a pull-down resistor to disable the power switch at reset.
This signal has opposite polarity compared to the USB_PPWR
used on other NXP LPC parts.
P2_4 K11 L9 D9 88 [3] N;
PU
I/O SGPIO13 — General purpose digital input/output pin.
I/O I2C1_SCL — I
2C1 clock input/output (this pin does not use a
specialized I2C pad).
I U3_RXD — Receiver input for USART3.
I CTIN_0 — SCTimer/PWM input 0. Capture input 0 of timer 0,
1, 2, 3.
I/O GPIO5[4] — General purpose digital input/output pin.
- R — Function reserved.
O T3_MAT1 — Match output 1 of timer 3.
I USB0_PWR_FAULT — Port power fault signal indicating
overcurrent condition; this signal monitors over-current on the
USB bus (external circuitry required to detect over-current
condition).
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 17 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P2_5 K14 J12 D10 91 [3] N;
PU
I/O SGPIO14 — General purpose digital input/output pin.
I CTIN_2 — SCTimer/PWM input 2. Capture input 2 of timer 0.
I USB1_VBUS — Monitors the presence of USB1 bus power.
Note: This signal must be HIGH for USB reset to occur.
I ADCTRIG1 — ADC trigger input 1.
I/O GPIO5[5] — General purpose digital input/output pin.
- R — Function reserved.
O T3_MAT2 — Match output 2 of timer 3.
O USB0_IND0 — USB0 port indicator LED control output 0.
P2_6 K16 J14 G9 95 [2] N;
PU
I/O SGPIO7 — General purpose digital input/output pin.
I/O U0_DIR — RS-485/EIA-485 output enable/direction control for
USART0.
I/O EMC_A10 — External memory address line 10.
O USB0_IND0 — USB0 port indicator LED control
output 0.
I/O GPIO5[6] — General purpose digital input/output pin.
I CTIN_7 — SCTimer/PWM input 7.
I T3_CAP3 — Capture input 3 of timer 3.
- R — Function reserved.
P2_7 H14 G12 C10 96 [2] N;
PU
I/O GPIO0[7] — General purpose digital input/output pin. If this pin
is pulled LOW at reset, the part enters ISP mode using
USART0.
O CTOUT_1 — SCTimer/PWM output 1. Match output 3 of timer
3.
I/O U3_UCLK — Serial clock input/output for USART3 in
synchronous mode.
I/O EMC_A9 — External memory address line 9.
- R — Function reserved.
- R — Function reserved.
O T3_MAT3 — Match output 3 of timer 3.
- R — Function reserved.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 18 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P2_8 J16 H14 C6 98 [2] N;
PU
I/O SGPIO15 — General purpose digital input/output pin. Boot pin
(see Table 5).
O CTOUT_0 — SCTimer/PWM output 0. Match output 0 of timer
0.
I/O U3_DIR — RS-485/EIA-485 output enable/direction control for
USART3.
I/O EMC_A8 — External memory address line 8.
I/O GPIO5[7] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
P2_9 H16 G14 B10 102 [2] N;
PU
I/O GPIO1[10] — General purpose digital input/output pin. Boot
pin (see Table 5.
O CTOUT_3 — SCTimer/PWM output 3. Match output 3 of timer
0.
I/O U3_BAUD — Baud pin for USART3.
I/O EMC_A0 — External memory address line 0.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
P2_10 G16 F14 E8 104 [2] N;
PU
I/O GPIO0[14] — General purpose digital input/output pin.
O CTOUT_2 — SCTimer/PWM output 2. Match output 2 of timer
0.
O U2_TXD — Transmitter output for USART2.
I/O EMC_A1 — External memory address line 1.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
P2_11 F16 E13 A9 105 [2] N;
PU
I/O GPIO1[11] — General purpose digital input/output pin.
O CTOUT_5 — SCTimer/PWM output 5. Match output 3 of timer
3.
I U2_RXD — Receiver input for USART2.
I/O EMC_A2 — External memory address line 2.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 19 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P2_12 E15 D13 B9 106 [2] N;
PU
I/O GPIO1[12] — General purpose digital input/output pin.
O CTOUT_4 — SCTimer/PWM output 4. Match output 3 of timer
3.
- R — Function reserved.
I/O EMC_A3 — External memory address line 3.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
I/O U2_UCLK — Serial clock input/output for USART2 in
synchronous mode.
P2_13 C16 E14 A10 108 [2] N;
PU
I/O GPIO1[13] — General purpose digital input/output pin.
I CTIN_4 — SCTimer/PWM input 4. Capture input 2 of timer 1.
- R — Function reserved.
I/O EMC_A4 — External memory address line 4.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
I/O U2_DIR — RS-485/EIA-485 output enable/direction control for
USART2.
P3_0 F13 D12 A8 112 [2] N;
PU
I/O I2S0_RX_SCK — I2S receive clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I
2S-bus specification.
O I2S0_RX_MCLK — I2S receive master clock.
I/O I2S0_TX_SCK — Transmit Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.
O I2S0_TX_MCLK — I2S transmit master clock.
I/O SSP0_SCK — Serial clock for SSP0.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 20 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P3_1 G11 D10 F7 114 [2] N;
PU
I/O I2S0_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I
2S-bus specification.
I/O I2S0_RX_WS — Receive Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I
2S-bus specification.
I CAN0_RD — CAN receiver input.
O USB1_IND1 — USB1 Port indicator LED control output 1.
I/O GPIO5[8] — General purpose digital input/output pin.
- R — Function reserved.
O LCD_VD15 — LCD data.
- R — Function reserved.
P3_2 F11 D9 G6 116 [2] OL;
PU
I/O I2S0_TX_SDA — I2S transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I
2S-bus specification.
I/O I2S0_RX_SDA — I2S Receive data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I
2S-bus specification.
O CAN0_TD — CAN transmitter output.
O USB1_IND0 — USB1 Port indicator LED control output 0.
I/O GPIO5[9] — General purpose digital input/output pin.
- R — Function reserved.
O LCD_VD14 — LCD data.
- R — Function reserved.
P3_3 B14 B13 A7 118 [4] N;
PU
- R — Function reserved.
I/O SPI_SCK — Serial clock for SPI.
I/O SSP0_SCK — Serial clock for SSP0.
O SPIFI_SCK — Serial clock for SPIFI.
O CGU_OUT1 — CGU spare clock output 1.
- R — Function reserved.
O I2S0_TX_MCLK — I2S transmit master clock.
I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 21 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P3_4 A15 C14 B8 119 [2] N;
PU
I/O GPIO1[14] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
I/O SPIFI_SIO3 — I/O lane 3 for SPIFI.
O U1_TXD — Transmitter output for UART 1.
I/O I2S0_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I
2S-bus specification.
I/O I2S1_RX_SDA — I2S1 Receive data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I
2S-bus specification.
O LCD_VD13 — LCD data.
P3_5 C12 C11 B7 121 [2] N;
PU
I/O GPIO1[15] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
I/O SPIFI_SIO2 — I/O lane 2 for SPIFI.
I U1_RXD — Receiver input for UART 1.
I/O I2S0_TX_SDA — I2S transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I
2S-bus specification.
I/O I2S1_RX_WS — Receive Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I
2S-bus specification.
O LCD_VD12 — LCD data.
P3_6 B13 B12 C7 122 [2] N;
PU
I/O GPIO0[6] — General purpose digital input/output pin.
I/O SPI_MISO — Master In Slave Out for SPI.
I/O SSP0_SSEL — Slave Select for SSP0.
I/O SPIFI_MISO — Input 1 in SPIFI quad mode; SPIFI output IO1.
- R — Function reserved.
I/O SSP0_MISO — Master In Slave Out for SSP0.
- R — Function reserved.
- R — Function reserved.
P3_7 C11 C10 D7 123 [2] N;
PU
- R — Function reserved.
I/O SPI_MOSI — Master Out Slave In for SPI.
I/O SSP0_MISO — Master In Slave Out for SSP0.
I/O SPIFI_MOSI — Input I0 in SPIFI quad mode; SPIFI output IO0.
I/O GPIO5[10] — General purpose digital input/output pin.
I/O SSP0_MOSI — Master Out Slave in for SSP0.
- R — Function reserved.
- R — Function reserved.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 22 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P3_8 C10 C9 E7 124 [2] N;
PU
- R — Function reserved.
I SPI_SSEL — Slave Select for SPI. Note that this pin in an
input pin only. The SPI in master mode cannot drive the CS
input on the slave. Any GPIO pin can be used for SPI chip
select in master mode.
I/O SSP0_MOSI — Master Out Slave in for SSP0.
I/O SPIFI_CS — SPIFI serial flash chip select.
I/O GPIO5[11] — General purpose digital input/output pin.
I/O SSP0_SSEL — Slave Select for SSP0.
- R — Function reserved.
- R — Function reserved.
P4_0 D5 D4 - 1 [2] N;
PU
I/O GPIO2[0] — General purpose digital input/output pin.
O MCOA0 — Motor control PWM channel 0, output A.
I NMI — External interrupt input to NMI.
- R — Function reserved.
- R — Function reserved.
O LCD_VD13 — LCD data.
I/O U3_UCLK — Serial clock input/output for USART3 in
synchronous mode.
- R — Function reserved.
P4_1 A1 D3 - 3 [5] N;
PU
I/O GPIO2[1] — General purpose digital input/output pin.
O CTOUT_1 — SCTimer/PWM output 1. Match output 3 of timer
3.
O LCD_VD0 — LCD data.
- R — Function reserved.
- R — Function reserved.
O LCD_VD19 — LCD data.
O U3_TXD — Transmitter output for USART3.
I ENET_COL — Ethernet Collision detect (MII interface).
AI ADC0_1 — ADC0 and ADC1, input channel 1. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 23 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P4_2 D3 A2 - 8 [2] N;
PU
I/O GPIO2[2] — General purpose digital input/output pin.
O CTOUT_0 — SCTimer/PWM output 0. Match output 0 of timer
0.
O LCD_VD3 — LCD data.
- R — Function reserved.
- R — Function reserved.
O LCD_VD12 — LCD data.
I U3_RXD — Receiver input for USART3.
I/O SGPIO8 — General purpose digital input/output pin.
P4_3 C2 B2 - 7 [5] N;
PU
I/O GPIO2[3] — General purpose digital input/output pin.
O CTOUT_3 — SCTimer/PWM output 3. Match output 3 of timer
0.
O LCD_VD2 — LCD data.
- R — Function reserved.
- R — Function reserved.
O LCD_VD21 — LCD data.
I/O U3_BAUD — Baud pin for USART3.
I/O SGPIO9 — General purpose digital input/output pin.
AI ADC0_0 — DAC output; ADC0 and ADC1, input channel 0.
Configure the pin as GPIO input and use the ADC function
select register in the SCU to select the ADC.
P4_4 B1 A1 - 9 [5] N;
PU
I/O GPIO2[4] — General purpose digital input/output pin.
O CTOUT_2 — SCTimer/PWM output 2. Match output 2 of timer
0.
O LCD_VD1 — LCD data.
- R — Function reserved.
- R — Function reserved.
O LCD_VD20 — LCD data.
I/O U3_DIR — RS-485/EIA-485 output enable/direction control for
USART3.
I/O SGPIO10 — General purpose digital input/output pin.
O DAC — DAC output. Shared between 10-bit ADC0/1 and
DAC.. Configure the pin as GPIO input and use the analog
function select register in the SCU to select the DAC.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 24 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P4_5 D2 C2 - 10 [2] N;
PU
I/O GPIO2[5] — General purpose digital input/output pin.
O CTOUT_5 — SCTimer/PWM output 5. Match output 3 of timer
3.
O LCD_FP — Frame pulse (STN). Vertical synchronization pulse
(TFT).
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
I/O SGPIO11 — General purpose digital input/output pin.
P4_6 C1 B1 - 11 [2] N;
PU
I/O GPIO2[6] — General purpose digital input/output pin.
O CTOUT_4 — SCTimer/PWM output 4. Match output 3 of timer
3.
O LCD_ENAB/LCDM — STN AC bias drive or TFT data enable
input.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
I/O SGPIO12 — General purpose digital input/output pin.
P4_7 H4 F4 - 14 [2] O;
PU
O LCD_DCLK — LCD panel clock.
I GP_CLKIN — General-purpose clock input to the CGU.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
I/O I2S1_TX_SCK — Transmit Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.
I/O I2S0_TX_SCK — Transmit Clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I2S-bus specification.
P4_8 E2 D2 - 15 [2] N;
PU
- R — Function reserved.
I CTIN_5 — SCTimer/PWM input 5. Capture input 2 of timer 2.
O LCD_VD9 — LCD data.
- R — Function reserved.
I/O GPIO5[12] — General purpose digital input/output pin.
O LCD_VD22 — LCD data.
O CAN1_TD — CAN1 transmitter output.
I/O SGPIO13 — General purpose digital input/output pin.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 25 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P4_9 L2 J2 - 33 [2] N;
PU
- R — Function reserved.
I CTIN_6 — SCTimer/PWM input 6. Capture input 1 of timer 3.
O LCD_VD11 — LCD data.
- R — Function reserved.
I/O GPIO5[13] — General purpose digital input/output pin.
O LCD_VD15 — LCD data.
I CAN1_RD — CAN1 receiver input.
I/O SGPIO14 — General purpose digital input/output pin.
P4_10 M3 L3 - 35 [2] N;
PU
- R — Function reserved.
I CTIN_2 — SCTimer/PWM input 2. Capture input 2 of timer 0.
O LCD_VD10 — LCD data.
- R — Function reserved.
I/O GPIO5[14] — General purpose digital input/output pin.
O LCD_VD14 — LCD data.
- R — Function reserved.
I/O SGPIO15 — General purpose digital input/output pin.
P5_0 N3 L2 - 37 [2] N;
PU
I/O GPIO2[9] — General purpose digital input/output pin.
O MCOB2 — Motor control PWM channel 2, output B.
I/O EMC_D12 — External memory data line 12.
- R — Function reserved.
I U1_DSR — Data Set Ready input for UART 1.
I T1_CAP0 — Capture input 0 of timer 1.
- R — Function reserved.
- R — Function reserved.
P5_1 P3 M1 - 39 [2] N;
PU
I/O GPIO2[10] — General purpose digital input/output pin.
I MCI2 — Motor control PWM channel 2, input.
I/O EMC_D13 — External memory data line 13.
- R — Function reserved.
O U1_DTR — Data Terminal Ready output for UART 1. Can also
be configured to be an RS-485/EIA-485 output enable signal
for UART 1.
I T1_CAP1 — Capture input 1 of timer 1.
- R — Function reserved.
- R — Function reserved.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 26 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P5_2 R4 M3 - 46 [2] N;
PU
I/O GPIO2[11] — General purpose digital input/output pin.
I MCI1 — Motor control PWM channel 1, input.
I/O EMC_D14 — External memory data line 14.
- R — Function reserved.
O U1_RTS — Request to Send output for UART 1. Can also be
configured to be an RS-485/EIA-485 output enable signal for
UART 1.
I T1_CAP2 — Capture input 2 of timer 1.
- R — Function reserved.
- R — Function reserved.
P5_3 T8 P6 - 54 [2] N;
PU
I/O GPIO2[12] — General purpose digital input/output pin.
I MCI0 — Motor control PWM channel 0, input.
I/O EMC_D15 — External memory data line 15.
- R — Function reserved.
I U1_RI — Ring Indicator input for UART 1.
I T1_CAP3 — Capture input 3 of timer 1.
- R — Function reserved.
- R — Function reserved.
P5_4 P9 N7 - 57 [2] N;
PU
I/O GPIO2[13] — General purpose digital input/output pin.
O MCOB0 — Motor control PWM channel 0, output B.
I/O EMC_D8 — External memory data line 8.
- R — Function reserved.
I U1_CTS — Clear to Send input for UART 1.
O T1_MAT0 — Match output 0 of timer 1.
- R — Function reserved.
- R — Function reserved.
P5_5 P10 N8 - 58 [2] N;
PU
I/O GPIO2[14] — General purpose digital input/output pin.
O MCOA1 — Motor control PWM channel 1, output A.
I/O EMC_D9 — External memory data line 9.
- R — Function reserved.
I U1_DCD — Data Carrier Detect input for UART 1.
O T1_MAT1 — Match output 1 of timer 1.
- R — Function reserved.
- R — Function reserved.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 27 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P5_6 T13 M11 - 63 [2] N;
PU
I/O GPIO2[15] — General purpose digital input/output pin.
O MCOB1 — Motor control PWM channel 1, output B.
I/O EMC_D10 — External memory data line 10.
- R — Function reserved.
O U1_TXD — Transmitter output for UART 1.
O T1_MAT2 — Match output 2 of timer 1.
- R — Function reserved.
- R — Function reserved.
P5_7 R12 N11 - 65 [2] N;
PU
I/O GPIO2[7] — General purpose digital input/output pin.
O MCOA2 — Motor control PWM channel 2, output A.
I/O EMC_D11 — External memory data line 11.
- R — Function reserved.
I U1_RXD — Receiver input for UART 1.
O T1_MAT3 — Match output 3 of timer 1.
- R — Function reserved.
- R — Function reserved.
P6_0 M12 M10 H7 73 [2] N;
PU
- R — Function reserved.
O I2S0_RX_MCLK — I2S receive master clock.
- R — Function reserved.
- R — Function reserved.
I/O I2S0_RX_SCK — Receive Clock. It is driven by the master and
received by the slave. Corresponds to the signal SCK in the
I
2S-bus specification.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
P6_1 R15 P14 G5 74 [2] N;
PU
I/O GPIO3[0] — General purpose digital input/output pin.
O EMC_DYCS1 — SDRAM chip select 1.
I/O U0_UCLK — Serial clock input/output for USART0 in
synchronous mode.
I/O I2S0_RX_WS — Receive Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I
2S-bus specification.
- R — Function reserved.
I T2_CAP0 — Capture input 2 of timer 2.
- R — Function reserved.
- R — Function reserved.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 28 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P6_2 L13 K11 J9 78 [2] N;
PU
I/O GPIO3[1] — General purpose digital input/output pin.
O EMC_CKEOUT1 — SDRAM clock enable 1.
I/O U0_DIR — RS-485/EIA-485 output enable/direction control for
USART0.
I/O I2S0_RX_SDA — I2S Receive data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I
2S-bus specification.
- R — Function reserved.
I T2_CAP1 — Capture input 1 of timer 2.
- R — Function reserved.
- R — Function reserved.
P6_3 P15 N13 - 79 [2] N;
PU
I/O GPIO3[2] — General purpose digital input/output pin.
O USB0_PPWR — VBUS drive signal (towards external charge
pump or power management unit); indicates that the VBUS
signal must be driven (active HIGH).
Add a pull-down resistor to disable the power switch at reset.
This signal has opposite polarity compared to the USB_PPWR
used on other NXP LPC parts.
I/O SGPIO4 — General purpose digital input/output pin.
O EMC_CS1 — LOW active Chip Select 1 signal.
- R — Function reserved.
I T2_CAP2 — Capture input 2 of timer 2.
- R — Function reserved.
- R — Function reserved.
P6_4 R16 M14 F6 80 [2] N;
PU
I/O GPIO3[3] — General purpose digital input/output pin.
I CTIN_6 — SCTimer/PWM input 6. Capture input 1 of timer 3.
O U0_TXD — Transmitter output for USART0.
O EMC_CAS — LOW active SDRAM Column Address Strobe.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 29 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P6_5 P16 L14 F9 82 [2] N;
PU
I/O GPIO3[4] — General purpose digital input/output pin.
O CTOUT_6 — SCTimer/PWM output 6. Match output 2 of timer
1.
I U0_RXD — Receiver input for USART0.
O EMC_RAS — LOW active SDRAM Row Address Strobe.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
P6_6 L14 K12 - 83 [2] N;
PU
I/O GPIO0[5] — General purpose digital input/output pin.
O EMC_BLS1 — LOW active Byte Lane select signal 1.
I/O SGPIO5 — General purpose digital input/output pin.
I USB0_PWR_FAULT — Port power fault signal indicating
overcurrent condition; this signal monitors over-current on the
USB bus (external circuitry required to detect over-current
condition).
- R — Function reserved.
I T2_CAP3 — Capture input 3 of timer 2.
- R — Function reserved.
- R — Function reserved.
P6_7 J13 H11 - 85 [2] N;
PU
- R — Function reserved.
I/O EMC_A15 — External memory address line 15.
I/O SGPIO6 — General purpose digital input/output pin.
O USB0_IND1 — USB0 port indicator LED control output 1.
I/O GPIO5[15] — General purpose digital input/output pin.
O T2_MAT0 — Match output 0 of timer 2.
- R — Function reserved.
- R — Function reserved.
P6_8 H13 F12 - 86 [2] N;
PU
- R — Function reserved.
I/O EMC_A14 — External memory address line 14.
I/O SGPIO7 — General purpose digital input/output pin.
O USB0_IND0 — USB0 port indicator LED control output 0.
I/O GPIO5[16] — General purpose digital input/output pin.
O T2_MAT1 — Match output 1 of timer 2.
- R — Function reserved.
- R — Function reserved.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 30 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P6_9 J15 H13 F8 97 [2] N;
PU
I/O GPIO3[5] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
O EMC_DYCS0 — SDRAM chip select 0.
- R — Function reserved.
O T2_MAT2 — Match output 2 of timer 2.
- R — Function reserved.
- R — Function reserved.
P6_10 H15 G13 - 100 [2] N;
PU
I/O GPIO3[6] — General purpose digital input/output pin.
O MCABORT — Motor control PWM, LOW-active fast abort.
- R — Function reserved.
O EMC_DQMOUT1 — Data mask 1 used with SDRAM and static
devices.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
P6_11 H12 F11 C9 101 [2] N;
PU
I/O GPIO3[7] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
O EMC_CKEOUT0 — SDRAM clock enable 0.
- R — Function reserved.
O T2_MAT3 — Match output 3 of timer 2.
- R — Function reserved.
- R — Function reserved.
P6_12 G15 F13 - 103 [2] N;
PU
I/O GPIO2[8] — General purpose digital input/output pin.
O CTOUT_7 — SCTimer/PWM output 7. Match output 3 of timer
1.
- R — Function reserved.
O EMC_DQMOUT0 — Data mask 0 used with SDRAM and static
devices.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 31 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P7_0 B16 B14 - 110 [2] N;
PU
I/O GPIO3[8] — General purpose digital input/output pin.
O CTOUT_14 — SCTimer/PWM output 14. Match output 2 of
timer 3.
- R — Function reserved.
O LCD_LE — Line end signal.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
I/O SGPIO4 — General purpose digital input/output pin.
P7_1 C14 C13 - 113 [2] N;
PU
I/O GPIO3[9] — General purpose digital input/output pin.
O CTOUT_15 — SCTimer/PWM output 15. Match output 3 of
timer 3.
I/O I2S0_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I
2S-bus specification.
O LCD_VD19 — LCD data.
O LCD_VD7 — LCD data.
- R — Function reserved.
O U2_TXD — Transmitter output for USART2.
I/O SGPIO5 — General purpose digital input/output pin.
P7_2 A16 A14 - 115 [2] N;
PU
I/O GPIO3[10] — General purpose digital input/output pin.
I CTIN_4 — SCTimer/PWM input 4. Capture input 2 of timer 1.
I/O I2S0_TX_SDA — I2S transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I
2S-bus specification.
O LCD_VD18 — LCD data.
O LCD_VD6 — LCD data.
- R — Function reserved.
I U2_RXD — Receiver input for USART2.
I/O SGPIO6 — General purpose digital input/output pin.
P7_3 C13 C12 - 117 [2] N;
PU
I/O GPIO3[11] — General purpose digital input/output pin.
I CTIN_3 — SCTimer/PWM input 3. Capture input 1 of timer 1.
- R — Function reserved.
O LCD_VD17 — LCD data.
O LCD_VD5 — LCD data.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 32 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P7_4 C8 C6 - 132 [5] N;
PU
I/O GPIO3[12] — General purpose digital input/output pin.
O CTOUT_13 — SCTimer/PWM output 13. Match output 3 of
timer 3.
- R — Function reserved.
O LCD_VD16 — LCD data.
O LCD_VD4 — LCD data.
O TRACEDATA[0] — Trace data, bit 0.
- R — Function reserved.
- R — Function reserved.
AI ADC0_4 — ADC0 and ADC1, input channel 4. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.
P7_5 A7 A7 - 133 [5] N;
PU
I/O GPIO3[13] — General purpose digital input/output pin.
O CTOUT_12 — SCTimer/PWM output 12. Match output 3 of
timer 3.
- R — Function reserved.
O LCD_VD8 — LCD data.
O LCD_VD23 — LCD data.
O TRACEDATA[1] — Trace data, bit 1.
- R — Function reserved.
- R — Function reserved.
AI ADC0_3 — ADC0 and ADC1, input channel 3. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.
P7_6 C7 F5 - 134 [2] N;
PU
I/O GPIO3[14] — General purpose digital input/output pin.
O CTOUT_11 — SCTimer/PWM output 1. Match output 3 of
timer 2.
- R — Function reserved.
O LCD_LP — Line synchronization pulse (STN). Horizontal
synchronization pulse (TFT).
- R — Function reserved.
O TRACEDATA[2] — Trace data, bit 2.
- R — Function reserved.
- R — Function reserved.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 33 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P7_7 B6 D5 - 140 [5] N;
PU
I/O GPIO3[15] — General purpose digital input/output pin.
O CTOUT_8 — SCTimer/PWM output 8. Match output 0 of timer
2.
- R — Function reserved.
O LCD_PWR — LCD panel power enable.
- R — Function reserved.
O TRACEDATA[3] — Trace data, bit 3.
O ENET_MDC — Ethernet MIIM clock.
I/O SGPIO7 — General purpose digital input/output pin.
AI ADC1_6 — ADC1 and ADC0, input channel 6. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.
P8_0 E5 E4 - - [3] N;
PU
I/O GPIO4[0] — General purpose digital input/output pin.
I USB0_PWR_FAULT — Port power fault signal indicating
overcurrent condition; this signal monitors over-current on the
USB bus (external circuitry required to detect over-current
condition).
- R — Function reserved.
I MCI2 — Motor control PWM channel 2, input.
I/O SGPIO8 — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
O T0_MAT0 — Match output 0 of timer 0.
P8_1 H5 G4 - - [3] N;
PU
I/O GPIO4[1] — General purpose digital input/output pin.
O USB0_IND1 — USB0 port indicator LED control output 1.
- R — Function reserved.
I MCI1 — Motor control PWM channel 1, input.
I/O SGPIO9 — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
O T0_MAT1 — Match output 1 of timer 0.
P8_2 K4 J4 - - [3] N;
PU
I/O GPIO4[2] — General purpose digital input/output pin.
O USB0_IND0 — USB0 port indicator LED control output 0.
- R — Function reserved.
I MCI0 — Motor control PWM channel 0, input.
I/O SGPIO10 — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
O T0_MAT2 — Match output 2 of timer 0.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 34 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P8_3 J3 H3 - - [2] N;
PU
I/O GPIO4[3] — General purpose digital input/output pin.
I/O USB1_ULPI_D2 — ULPI link bidirectional data line 2.
- R — Function reserved.
O LCD_VD12 — LCD data.
O LCD_VD19 — LCD data.
- R — Function reserved.
- R — Function reserved.
O T0_MAT3 — Match output 3 of timer 0.
P8_4 J2 H2 - - [2] N;
PU
I/O GPIO4[4] — General purpose digital input/output pin.
I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1.
- R — Function reserved.
O LCD_VD7 — LCD data.
O LCD_VD16 — LCD data.
- R — Function reserved.
- R — Function reserved.
I T0_CAP0 — Capture input 0 of timer 0.
P8_5 J1 H1 - - [2] N;
PU
I/O GPIO4[5] — General purpose digital input/output pin.
I/O USB1_ULPI_D0 — ULPI link bidirectional data line 0.
- R — Function reserved.
O LCD_VD6 — LCD data.
O LCD_VD8 — LCD data.
- R — Function reserved.
- R — Function reserved.
I T0_CAP1 — Capture input 1 of timer 0.
P8_6 K3 J3 - - [2] N;
PU
I/O GPIO4[6] — General purpose digital input/output pin.
I USB1_ULPI_NXT — ULPI link NXT signal. Data flow control
signal from the PHY.
- R — Function reserved.
O LCD_VD5 — LCD data.
O LCD_LP — Line synchronization pulse (STN). Horizontal
synchronization pulse (TFT).
- R — Function reserved.
- R — Function reserved.
I T0_CAP2 — Capture input 2 of timer 0.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 35 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P8_7 K1 J1 - - [2] N;
PU
I/O GPIO4[7] — General purpose digital input/output pin.
O USB1_ULPI_STP — ULPI link STP signal. Asserted to end or
interrupt transfers to the PHY.
- R — Function reserved.
O LCD_VD4 — LCD data.
O LCD_PWR — LCD panel power enable.
- R — Function reserved.
- R — Function reserved.
I T0_CAP3 — Capture input 3 of timer 0.
P8_8 L1 K1 - - [2] N;
PU
- R — Function reserved.
I USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock
generated by the PHY.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
O CGU_OUT0 — CGU spare clock output 0.
O I2S1_TX_MCLK — I2S1 transmit master clock.
P9_0 T1 P1 - - [2] N;
PU
I/O GPIO4[12] — General purpose digital input/output pin.
O MCABORT — Motor control PWM, LOW-active fast abort.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
I ENET_CRS — Ethernet Carrier Sense (MII interface).
I/O SGPIO0 — General purpose digital input/output pin.
I/O SSP0_SSEL — Slave Select for SSP0.
P9_1 N6 P4 - - [2] N;
PU
I/O GPIO4[13] — General purpose digital input/output pin.
O MCOA2 — Motor control PWM channel 2, output A.
- R — Function reserved.
- R — Function reserved.
I/O I2S0_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I
2S-bus specification.
I ENET_RX_ER — Ethernet receive error (MII interface).
I/O SGPIO1 — General purpose digital input/output pin.
I/O SSP0_MISO — Master In Slave Out for SSP0.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 36 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P9_2 N8 M6 - - [2] N;
PU
I/O GPIO4[14] — General purpose digital input/output pin.
O MCOB2 — Motor control PWM channel 2, output B.
- R — Function reserved.
- R — Function reserved.
I/O I2S0_TX_SDA — I2S transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I
2S-bus specification.
I ENET_RXD3 — Ethernet receive data 3 (MII interface).
I/O SGPIO2 — General purpose digital input/output pin.
I/O SSP0_MOSI — Master Out Slave in for SSP0.
P9_3 M6 P5 - - [2] N;
PU
I/O GPIO4[15] — General purpose digital input/output pin.
O MCOA0 — Motor control PWM channel 0, output A.
O USB1_IND1 — USB1 Port indicator LED control output 1.
- R — Function reserved.
- R — Function reserved.
I ENET_RXD2 — Ethernet receive data 2 (MII interface).
I/O SGPIO9 — General purpose digital input/output pin.
O U3_TXD — Transmitter output for USART3.
P9_4 N10 M8 - - [2] N;
PU
- R — Function reserved.
O MCOB0 — Motor control PWM channel 0, output B.
O USB1_IND0 — USB1 Port indicator LED control output 0.
- R — Function reserved.
I/O GPIO5[17] — General purpose digital input/output pin.
O ENET_TXD2 — Ethernet transmit data 2 (MII interface).
I/O SGPIO4 — General purpose digital input/output pin.
I U3_RXD — Receiver input for USART3.
P9_5 M9 L7 - 69 [2] N;
PU
- R — Function reserved.
O MCOA1 — Motor control PWM channel 1, output A.
O USB1_PPWR — VBUS drive signal (towards external charge
pump or power management unit); indicates that VBUS must
be driven (active high).
Add a pull-down resistor to disable the power switch at reset.
This signal has opposite polarity compared to the USB_PPWR
used on other NXP LPC parts.
- R — Function reserved.
I/O GPIO5[18] — General purpose digital input/output pin.
O ENET_TXD3 — Ethernet transmit data 3 (MII interface).
I/O SGPIO3 — General purpose digital input/output pin.
O U0_TXD — Transmitter output for USART0.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 37 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
P9_6 L11 M9 - 72 [2] N;
PU
I/O GPIO4[11] — General purpose digital input/output pin.
O MCOB1 — Motor control PWM channel 1, output B.
I USB1_PWR_FAULT — USB1 Port power fault signal
indicating over-current condition; this signal monitors
over-current on the USB1 bus (external circuitry required to
detect over-current condition).
- R — Function reserved.
- R — Function reserved.
I ENET_COL — Ethernet Collision detect (MII interface).
I/O SGPIO8 — General purpose digital input/output pin.
I U0_RXD — Receiver input for USART0.
PA_0 L12 L10 - - [2] N;
PU
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
O I2S1_RX_MCLK — I2S1 receive master clock.
O CGU_OUT1 — CGU spare clock output 1.
- R — Function reserved.
PA_1 J14 H12 - - [3] N;
PU
I/O GPIO4[8] — General purpose digital input/output pin.
I QEI_IDX — Quadrature Encoder Interface INDEX input.
- R — Function reserved.
O U2_TXD — Transmitter output for USART2.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
PA_2 K15 J13 - - [3] N;
PU
I/O GPIO4[9] — General purpose digital input/output pin.
I QEI_PHB — Quadrature Encoder Interface PHB input.
- R — Function reserved.
I U2_RXD — Receiver input for USART2.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 38 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
PA_3 H11 E10 - - [3] N;
PU
I/O GPIO4[10] — General purpose digital input/output pin.
I QEI_PHA — Quadrature Encoder Interface PHA input.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
PA_4 G13 E12 - - [2] N;
PU
- R — Function reserved.
O CTOUT_9 — SCTimer/PWM output 9. Match output 3 of timer
3.
- R — Function reserved.
I/O EMC_A23 — External memory address line 23.
I/O GPIO5[19] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
PB_0 B15 D14 - - [2] N;
PU
- R — Function reserved.
O CTOUT_10 — SCTimer/PWM output 10. Match output 3 of
timer 3.
O LCD_VD23 — LCD data.
- R — Function reserved.
I/O GPIO5[20] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
PB_1 A14 A13 - - [2] N;
PU
- R — Function reserved.
I USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP
data line direction.
O LCD_VD22 — LCD data.
- R — Function reserved.
I/O GPIO5[21] — General purpose digital input/output pin.
O CTOUT_6 — SCTimer/PWM output 6. Match output 2 of timer
1.
- R — Function reserved.
- R — Function reserved.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 39 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
PB_2 B12 B11 - - [2] N;
PU
- R — Function reserved.
I/O USB1_ULPI_D7 — ULPI link bidirectional data line 7.
O LCD_VD21 — LCD data.
- R — Function reserved.
I/O GPIO5[22] — General purpose digital input/output pin.
O CTOUT_7 — SCTimer/PWM output 7. Match output 3 of timer
1.
- R — Function reserved.
- R — Function reserved.
PB_3 A13 A12 - - [2] N;
PU
- R — Function reserved.
I/O USB1_ULPI_D6 — ULPI link bidirectional data line 6.
O LCD_VD20 — LCD data.
- R — Function reserved.
I/O GPIO5[23] — General purpose digital input/output pin.
O CTOUT_8 — SCTimer/PWM output 8. Match output 0 of timer
2.
- R — Function reserved.
- R — Function reserved.
PB_4 B11 B10 - - [2] N;
PU
- R — Function reserved.
I/O USB1_ULPI_D5 — ULPI link bidirectional data line 5.
O LCD_VD15 — LCD data.
- R — Function reserved.
I/O GPIO5[24] — General purpose digital input/output pin.
I CTIN_5 — SCTimer/PWM input 5. Capture input 2 of timer 2.
- R — Function reserved.
- R — Function reserved.
PB_5 A12 A11 - - [2] N;
PU
- R — Function reserved.
I/O USB1_ULPI_D4 — ULPI link bidirectional data line 4.
O LCD_VD14 — LCD data.
- R — Function reserved.
I/O GPIO5[25] — General purpose digital input/output pin.
I CTIN_7 — SCTimer/PWM input 7.
O LCD_PWR — LCD panel power enable.
- R — Function reserved.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 40 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
PB_6 A6 C5 - - [5] N;
PU
- R — Function reserved.
I/O USB1_ULPI_D3 — ULPI link bidirectional data line 3.
O LCD_VD13 — LCD data.
- R — Function reserved.
I/O GPIO5[26] — General purpose digital input/output pin.
I CTIN_6 — SCTimer/PWM input 6. Capture input 1 of timer 3.
O LCD_VD19 — LCD data.
- R — Function reserved.
AI ADC0_6 — ADC0 and ADC1, input channel 6. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.
PC_0 D4 - - - [5] N;
PU
- R — Function reserved.
I USB1_ULPI_CLK — ULPI link CLK signal. 60 MHz clock
generated by the PHY.
- R — Function reserved.
I/O ENET_RX_CLK — Ethernet Receive Clock (MII interface).
O LCD_DCLK — LCD panel clock.
- R — Function reserved.
- R — Function reserved.
I/O SD_CLK — SD/MMC card clock.
AI ADC1_1 — ADC1 and ADC0, input channel 1. Configure the
pin as input (USB_ULPI_CLK) and use the ADC function select
register in the SCU to select the ADC.
PC_1 E4 - - - [2] N;
PU
I/O USB1_ULPI_D7 — ULPI link bidirectional data line 7.
- R — Function reserved.
I U1_RI — Ring Indicator input for UART 1.
O ENET_MDC — Ethernet MIIM clock.
I/O GPIO6[0] — General purpose digital input/output pin.
- R — Function reserved.
I T3_CAP0 — Capture input 0 of timer 3.
O SD_VOLT0 — SD/MMC bus voltage select output 0.
PC_2 F6 - - - [2] N;
PU
I/O USB1_ULPI_D6 — ULPI link bidirectional data line 6.
- R — Function reserved.
I U1_CTS — Clear to Send input for UART 1.
O ENET_TXD2 — Ethernet transmit data 2 (MII interface).
I/O GPIO6[1] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
O SD_RST — SD/MMC reset signal for MMC4.4 card.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 41 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
PC_3 F5 - - - [5] N;
PU
I/O USB1_ULPI_D5 — ULPI link bidirectional data line 5.
- R — Function reserved.
O U1_RTS — Request to Send output for UART 1. Can also be
configured to be an RS-485/EIA-485 output enable signal for
UART 1.
O ENET_TXD3 — Ethernet transmit data 3 (MII interface).
I/O GPIO6[2] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
O SD_VOLT1 — SD/MMC bus voltage select output 1.
AI ADC1_0 — DAC output; ADC1 and ADC0, input channel 0.
Configure the pin as GPIO input and use the ADC function
select register in the SCU to select the ADC.
PC_4 F4 - - - [2] N;
PU
- R — Function reserved.
I/O USB1_ULPI_D4 — ULPI link bidirectional data line 4.
- R — Function reserved.
ENET_TX_EN — Ethernet transmit enable (RMII/MII
interface).
I/O GPIO6[3] — General purpose digital input/output pin.
- R — Function reserved.
I T3_CAP1 — Capture input 1 of timer 3.
I/O SD_DAT0 — SD/MMC data bus line 0.
PC_5 G4 - - - [2] N;
PU
- R — Function reserved.
I/O USB1_ULPI_D3 — ULPI link bidirectional data line 3.
- R — Function reserved.
O ENET_TX_ER — Ethernet Transmit Error (MII interface).
I/O GPIO6[4] — General purpose digital input/output pin.
- R — Function reserved.
I T3_CAP2 — Capture input 2 of timer 3.
I/O SD_DAT1 — SD/MMC data bus line 1.
PC_6 H6 - - - [2] N;
PU
- R — Function reserved.
I/O USB1_ULPI_D2 — ULPI link bidirectional data line 2.
- R — Function reserved.
I ENET_RXD2 — Ethernet receive data 2 (MII interface).
I/O GPIO6[5] — General purpose digital input/output pin.
- R — Function reserved.
I T3_CAP3 — Capture input 3 of timer 3.
I/O SD_DAT2 — SD/MMC data bus line 2.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 42 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
PC_7 G5 - - - [2] N;
PU
- R — Function reserved.
I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1.
- R — Function reserved.
I ENET_RXD3 — Ethernet receive data 3 (MII interface).
I/O GPIO6[6] — General purpose digital input/output pin.
- R — Function reserved.
O T3_MAT0 — Match output 0 of timer 3.
I/O SD_DAT3 — SD/MMC data bus line 3.
PC_8 N4 - - - [2] N;
PU
- R — Function reserved.
I/O USB1_ULPI_D0 — ULPI link bidirectional data line 0.
- R — Function reserved.
I ENET_RX_DV — Ethernet Receive Data Valid (RMII/MII
interface).
I/O GPIO6[7] — General purpose digital input/output pin.
- R — Function reserved.
O T3_MAT1 — Match output 1 of timer 3.
I SD_CD — SD/MMC card detect input.
PC_9 K2 - - - [2] N;
PU
- R — Function reserved.
I USB1_ULPI_NXT — ULPI link NXT signal. Data flow control
signal from the PHY.
- R — Function reserved.
I ENET_RX_ER — Ethernet receive error (MII interface).
I/O GPIO6[8] — General purpose digital input/output pin.
- R — Function reserved.
O T3_MAT2 — Match output 2 of timer 3.
O SD_POW — SD/MMC power monitor output.
PC_10 M5 - - - [2] N;
PU
- R — Function reserved.
O USB1_ULPI_STP — ULPI link STP signal. Asserted to end or
interrupt transfers to the PHY.
I U1_DSR — Data Set Ready input for UART 1.
- R — Function reserved.
I/O GPIO6[9] — General purpose digital input/output pin.
- R — Function reserved.
O T3_MAT3 — Match output 3 of timer 3.
I/O SD_CMD — SD/MMC command signal.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 43 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
PC_11 L5 - - - [2] N;
PU
- R — Function reserved.
I USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULPI
data line direction.
I U1_DCD — Data Carrier Detect input for UART 1.
- R — Function reserved.
I/O GPIO6[10] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
I/O SD_DAT4 — SD/MMC data bus line 4.
PC_12 L6 - - - [2] N;
PU
- R — Function reserved.
- R — Function reserved.
O U1_DTR — Data Terminal Ready output for UART 1. Can also
be configured to be an RS-485/EIA-485 output enable signal
for UART 1.
- R — Function reserved.
I/O GPIO6[11] — General purpose digital input/output pin.
I/O SGPIO11 — General purpose digital input/output pin.
I/O I2S0_TX_SDA — I2S transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I
2S-bus specification.
I/O SD_DAT5 — SD/MMC data bus line 5.
PC_13 M1 - - - [2] N;
PU
- R — Function reserved.
- R — Function reserved.
O U1_TXD — Transmitter output for UART 1.
- R — Function reserved.
I/O GPIO6[12] — General purpose digital input/output pin.
I/O SGPIO12 — General purpose digital input/output pin.
I/O I2S0_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I
2S-bus specification.
I/O SD_DAT6 — SD/MMC data bus line 6.
PC_14 N1 - - - [2] N;
PU
- R — Function reserved.
- R — Function reserved.
I U1_RXD — Receiver input for UART 1.
- R — Function reserved.
I/O GPIO6[13] — General purpose digital input/output pin.
I/O SGPIO13 — General purpose digital input/output pin.
O ENET_TX_ER — Ethernet Transmit Error (MII interface).
I/O SD_DAT7 — SD/MMC data bus line 7.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 44 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
PD_0 N2 - - - [2] N;
PU
- R — Function reserved.
O CTOUT_15 — SCTimer/PWM output 15. Match output 3 of
timer 3.
O EMC_DQMOUT2 — Data mask 2 used with SDRAM and static
devices.
- R — Function reserved.
I/O GPIO6[14] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
I/O SGPIO4 — General purpose digital input/output pin.
PD_1 P1 - - - [2] N;
PU
- R — Function reserved.
- R — Function reserved.
O EMC_CKEOUT2 — SDRAM clock enable 2.
- R — Function reserved.
I/O GPIO6[15] — General purpose digital input/output pin.
O SD_POW — SD/MMC power monitor output.
- R — Function reserved.
I/O SGPIO5 — General purpose digital input/output pin.
PD_2 R1 - - - [2] N;
PU
- R — Function reserved.
O CTOUT_7 — SCTimer/PWM output 7. Match output 3 of timer
1.
I/O EMC_D16 — External memory data line 16.
- R — Function reserved.
I/O GPIO6[16] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
I/O SGPIO6 — General purpose digital input/output pin.
PD_3 P4 - - - [2] N;
PU
- R — Function reserved.
O CTOUT_6 — SCTimer/PWM output 7. Match output 2 of timer
1.
I/O EMC_D17 — External memory data line 17.
- R — Function reserved.
I/O GPIO6[17] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
I/O SGPIO7 — General purpose digital input/output pin.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 45 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
PD_4 T2 - - - [2] N;
PU
- R — Function reserved.
O CTOUT_8 — SCTimer/PWM output 8. Match output 0 of timer
2.
I/O EMC_D18 — External memory data line 18.
- R — Function reserved.
I/O GPIO6[18] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
I/O SGPIO8 — General purpose digital input/output pin.
PD_5 P6 - - - [2] N;
PU
- R — Function reserved.
O CTOUT_9 — SCTimer/PWM output 9. Match output 3 of timer
3.
I/O EMC_D19 — External memory data line 19.
- R — Function reserved.
I/O GPIO6[19] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
I/O SGPIO9 — General purpose digital input/output pin.
PD_6 R6 - - - [2] N;
PU
- R — Function reserved.
O CTOUT_10 — SCTimer/PWM output 10. Match output 3 of
timer 3.
I/O EMC_D20 — External memory data line 20.
- R — Function reserved.
I/O GPIO6[20] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
I/O SGPIO10 — General purpose digital input/output pin.
PD_7 T6 - - - [2] N;
PU
- R — Function reserved.
I CTIN_5 — SCTimer/PWM input 5. Capture input 2 of timer 2.
I/O EMC_D21 — External memory data line 21.
- R — Function reserved.
I/O GPIO6[21] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
I/O SGPIO11 — General purpose digital input/output pin.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 46 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
PD_8 P8 - - - [2] N;
PU
- R — Function reserved.
I CTIN_6 — SCTimer/PWM input 6. Capture input 1 of timer 3.
I/O EMC_D22 — External memory data line 22.
- R — Function reserved.
I/O GPIO6[22] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
I/O SGPIO12 — General purpose digital input/output pin.
PD_9 T11 - - - [2] N;
PU
- R — Function reserved.
O CTOUT_13 — SCTimer/PWM output 13. Match output 3 of
timer 3.
I/O EMC_D23 — External memory data line 23.
- R — Function reserved.
I/O GPIO6[23] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
I/O SGPIO13 — General purpose digital input/output pin.
PD_10 P11 - - - [2] N;
PU
- R — Function reserved.
I CTIN_1 — SCTimer/PWM input 1. Capture input 1 of timer 0.
Capture input 1 of timer 2.
O EMC_BLS3 — LOW active Byte Lane select signal 3.
- R — Function reserved.
I/O GPIO6[24] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
PD_11 N9 M7 - - [2] N;
PU
- R — Function reserved.
- R — Function reserved.
O EMC_CS3 — LOW active Chip Select 3 signal.
- R — Function reserved.
I/O GPIO6[25] — General purpose digital input/output pin.
I/O USB1_ULPI_D0 — ULPI link bidirectional data line 0.
O CTOUT_14 — SCTimer/PWM output 14. Match output 2 of
timer 3.
- R — Function reserved.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 47 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
PD_12 N11 P9 - - [2] N;
PU
- R — Function reserved.
- R — Function reserved.
O EMC_CS2 — LOW active Chip Select 2 signal.
- R — Function reserved.
I/O GPIO6[26] — General purpose digital input/output pin.
- R — Function reserved.
O CTOUT_10 — SCTimer/PWM output 10. Match output 3 of
timer 3.
- R — Function reserved.
PD_13 T14 - - - [2] N;
PU
- R — Function reserved.
I CTIN_0 — SCTimer/PWM input 0. Capture input 0 of timer 0,
1, 2, 3.
O EMC_BLS2 — LOW active Byte Lane select signal 2.
- R — Function reserved.
I/O GPIO6[27] — General purpose digital input/output pin.
- R — Function reserved.
O CTOUT_13 — SCTimer/PWM output 13. Match output 3 of
timer 3.
- R — Function reserved.
PD_14 R13 L11 - - [2] N;
PU
- R — Function reserved.
- R — Function reserved.
O EMC_DYCS2 — SDRAM chip select 2.
- R — Function reserved.
I/O GPIO6[28] — General purpose digital input/output pin.
- R — Function reserved.
O CTOUT_11 — SCTimer/PWM output 11. Match output 3 of
timer 2.
- R — Function reserved.
PD_15 T15 P13 - - [2] N;
PU
- R — Function reserved.
- R — Function reserved.
I/O EMC_A17 — External memory address line 17.
- R — Function reserved.
I/O GPIO6[29] — General purpose digital input/output pin.
I SD_WP — SD/MMC card write protect input.
O CTOUT_8 — SCTimer/PWM output 8. Match output 0 of timer
2.
- R — Function reserved.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 48 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
PD_16 R14 P12 - - [2] N;
PU
- R — Function reserved.
- R — Function reserved.
I/O EMC_A16 — External memory address line 16.
- R — Function reserved.
I/O GPIO6[30] — General purpose digital input/output pin.
O SD_VOLT2 — SD/MMC bus voltage select output 2.
O CTOUT_12 — SCTimer/PWM output 12. Match output 3 of
timer 3.
- R — Function reserved.
PE_0 P14 N12 - - [2] N;
PU
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
I/O EMC_A18 — External memory address line 18.
I/O GPIO7[0] — General purpose digital input/output pin.
O CAN1_TD — CAN1 transmitter output.
- R — Function reserved.
- R — Function reserved.
PE_1 N14 M12 - - [2] N;
PU
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
I/O EMC_A19 — External memory address line 19.
I/O GPIO7[1] — General purpose digital input/output pin.
I CAN1_RD — CAN1 receiver input.
- R — Function reserved.
- R — Function reserved.
PE_2 M14 L12 - - [2] N;
PU
I ADCTRIG0 — ADC trigger input 0.
I CAN0_RD — CAN receiver input.
- R — Function reserved.
I/O EMC_A20 — External memory address line 20.
I/O GPIO7[2] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 49 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
PE_3 K12 K10 - - [2] N;
PU
- R — Function reserved.
O CAN0_TD — CAN transmitter output.
I ADCTRIG1 — ADC trigger input 1.
I/O EMC_A21 — External memory address line 21.
I/O GPIO7[3] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
PE_4 K13 J11 - - [2] N;
PU
- R — Function reserved.
I NMI — External interrupt input to NMI.
- R — Function reserved.
I/O EMC_A22 — External memory address line 22.
I/O GPIO7[4] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
PE_5 N16 - - - [2] N;
PU
- R — Function reserved.
O CTOUT_3 — SCTimer/PWM output 3. Match output 3 of timer
0.
O U1_RTS — Request to Send output for UART 1. Can also be
configured to be an RS-485/EIA-485 output enable signal for
UART 1.
I/O EMC_D24 — External memory data line 24.
I/O GPIO7[5] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
PE_6 M16 - - - [2] N;
PU
- R — Function reserved.
O CTOUT_2 — SCTimer/PWM output 2. Match output 2 of timer
0.
I U1_RI — Ring Indicator input for UART 1.
I/O EMC_D25 — External memory data line 25.
I/O GPIO7[6] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 50 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
PE_7 F15 - - - [2] N;
PU
- R — Function reserved.
O CTOUT_5 — SCTimer/PWM output 5. Match output 3 of timer
3.
I U1_CTS — Clear to Send input for UART1.
I/O EMC_D26 — External memory data line 26.
I/O GPIO7[7] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
PE_8 F14 - - - [2] N;
PU
- R — Function reserved.
O CTOUT_4 — SCTimer/PWM output 4. Match output 3 of timer
3.
I U1_DSR — Data Set Ready input for UART 1.
I/O EMC_D27 — External memory data line 27.
I/O GPIO7[8] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
PE_9 E16 - - - [2] N;
PU
- R — Function reserved.
I CTIN_4 — SCTimer/PWM input 4. Capture input 2 of timer 1.
I U1_DCD — Data Carrier Detect input for UART 1.
I/O EMC_D28 — External memory data line 28.
I/O GPIO7[9] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
PE_10 E14 - - - [2] N;
PU
- R — Function reserved.
I CTIN_3 — SCTimer/PWM input 3. Capture input 1 of timer 1.
O U1_DTR — Data Terminal Ready output for UART 1. Can also
be configured to be an RS-485/EIA-485 output enable signal
for UART 1.
I/O EMC_D29 — External memory data line 29.
I/O GPIO7[10] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 51 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
PE_11 D16 - - - [2] N;
PU
- R — Function reserved.
O CTOUT_12 — SCTimer/PWM output 12. Match output 3 of
timer 3.
O U1_TXD — Transmitter output for UART 1.
I/O EMC_D30 — External memory data line 30.
I/O GPIO7[11] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
PE_12 D15 - - - [2] N;
PU
- R — Function reserved.
O CTOUT_11 — SCTimer/PWM output 11. Match output 3 of
timer 2.
I U1_RXD — Receiver input for UART 1.
I/O EMC_D31 — External memory data line 31.
I/O GPIO7[12] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
PE_13 G14 - - - [2] N;
PU
- R — Function reserved.
O CTOUT_14 — SCTimer/PWM output 14. Match output 2 of
timer 3.
I/O I2C1_SDA — I
2C1 data input/output (this pin does not use a
specialized I2C pad).
O EMC_DQMOUT3 — Data mask 3 used with SDRAM and static
devices.
I/O GPIO7[13] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
PE_14 C15 - - - [2] N;
PU
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
O EMC_DYCS3 — SDRAM chip select 3.
I/O GPIO7[14] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 52 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
PE_15 E13 - - - [2] N;
PU
- R — Function reserved.
O CTOUT_0 — SCTimer/PWM output 0. Match output 0 of timer
0.
I/O I2C1_SCL — I
2C1 clock input/output (this pin does not use a
specialized I2C pad).
O EMC_CKEOUT3 — SDRAM clock enable 3.
I/O GPIO7[15] — General purpose digital input/output pin.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
PF_0 D12 - - - [2] O;
PU
I/O SSP0_SCK — Serial clock for SSP0.
I GP_CLKIN — General-purpose clock input to the CGU.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
O I2S1_TX_MCLK — I2S1 transmit master clock.
PF_1 E11 - - - [2] N;
PU
- R — Function reserved.
- R — Function reserved.
I/O SSP0_SSEL — Slave Select for SSP0.
- R — Function reserved.
I/O GPIO7[16] — General purpose digital input/output pin.
- R — Function reserved.
I/O SGPIO0 — General purpose digital input/output pin.
- R — Function reserved.
PF_2 D11 - - - [2] N;
PU
- R — Function reserved.
O U3_TXD — Transmitter output for USART3.
I/O SSP0_MISO — Master In Slave Out for SSP0.
- R — Function reserved.
I/O GPIO7[17] — General purpose digital input/output pin.
- R — Function reserved.
I/O SGPIO1 — General purpose digital input/output pin.
- R — Function reserved.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 53 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
PF_3 E10 - - - [2] N;
PU
- R — Function reserved.
I U3_RXD — Receiver input for USART3.
I/O SSP0_MOSI — Master Out Slave in for SSP0.
- R — Function reserved.
I/O GPIO7[18] — General purpose digital input/output pin.
- R — Function reserved.
I/O SGPIO2 — General purpose digital input/output pin.
- R — Function reserved.
PF_4 D10 D6 H4 120 [2] O;
PU
I/O SSP1_SCK — Serial clock for SSP1.
I GP_CLKIN — General-purpose clock input to the CGU.
O TRACECLK — Trace clock.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
O I2S0_TX_MCLK — I2S transmit master clock.
I/O I2S0_RX_SCK — I2S receive clock. It is driven by the master
and received by the slave. Corresponds to the signal SCK in
the I
2S-bus specification.
PF_5 E9 - - - [5] N;
PU
- R — Function reserved.
I/O U3_UCLK — Serial clock input/output for USART3 in
synchronous mode.
I/O SSP1_SSEL — Slave Select for SSP1.
O TRACEDATA[0] — Trace data, bit 0.
I/O GPIO7[19] — General purpose digital input/output pin.
- R — Function reserved.
I/O SGPIO4 — General purpose digital input/output pin.
- R — Function reserved.
AI ADC1_4 — ADC1 and ADC0, input channel 4. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 54 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
PF_6 E7 - - - [5] N;
PU
- R — Function reserved.
I/O U3_DIR — RS-485/EIA-485 output enable/direction control for
USART3.
I/O SSP1_MISO — Master In Slave Out for SSP1.
O TRACEDATA[1] — Trace data, bit 1.
I/O GPIO7[20] — General purpose digital input/output pin.
- R — Function reserved.
I/O SGPIO5 — General purpose digital input/output pin.
I/O I2S1_TX_SDA — I2S1 transmit data. It is driven by the
transmitter and read by the receiver. Corresponds to the signal
SD in the I
2S-bus specification.
AI ADC1_3 — ADC1 and ADC0, input channel 3. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.
PF_7 B7 - - - [5] N;
PU
- R — Function reserved.
I/O U3_BAUD — Baud pin for USART3.
I/O SSP1_MOSI — Master Out Slave in for SSP1.
O TRACEDATA[2] — Trace data, bit 2.
I/O GPIO7[21] — General purpose digital input/output pin.
- R — Function reserved.
I/O SGPIO6 — General purpose digital input/output pin.
I/O I2S1_TX_WS — Transmit Word Select. It is driven by the
master and received by the slave. Corresponds to the signal
WS in the I
2S-bus specification.
AI/
O
ADC1_7 — ADC1 and ADC0, input channel 7 or band gap
output. Configure the pin as GPIO input and use the ADC
function select register in the SCU to select the ADC.
PF_8 E6 - - - [5] N;
PU
- R — Function reserved.
I/O U0_UCLK — Serial clock input/output for USART0 in
synchronous mode.
I CTIN_2 — SCTimer/PWM input 2. Capture input 2 of timer 0.
O TRACEDATA[3] — Trace data, bit 3.
I/O GPIO7[22] — General purpose digital input/output pin.
- R — Function reserved.
I/O SGPIO7 — General purpose digital input/output pin.
- R — Function reserved.
AI ADC0_2 — ADC0 and ADC1, input channel 2. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 55 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
PF_9 D6 - - - [5] N;
PU
- R — Function reserved.
I/O U0_DIR — RS-485/EIA-485 output enable/direction control for
USART0.
O CTOUT_1 — SCTimer/PWM output 1. Match output 3 of timer
3.
- R — Function reserved.
I/O GPIO7[23] — General purpose digital input/output pin.
- R — Function reserved.
I/O SGPIO3 — General purpose digital input/output pin.
- R — Function reserved.
AI ADC1_2 — ADC1 and ADC0, input channel 2. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.
PF_10 A3 - - - [5] N;
PU
- R — Function reserved.
O U0_TXD — Transmitter output for USART0.
- R — Function reserved.
- R — Function reserved.
I/O GPIO7[24] — General purpose digital input/output pin.
- R — Function reserved.
I SD_WP — SD/MMC card write protect input.
- R — Function reserved.
AI ADC0_5 — ADC0 and ADC1, input channel 5. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.
PF_11 A2 - - - [5] N;
PU
- R — Function reserved.
I U0_RXD — Receiver input for USART0.
- R — Function reserved.
- R — Function reserved.
I/O GPIO7[25] — General purpose digital input/output pin.
- R — Function reserved.
O SD_VOLT2 — SD/MMC bus voltage select output 2.
- R — Function reserved.
AI ADC1_5 — ADC1 and ADC0, input channel 5. Configure the
pin as GPIO input and use the ADC function select register in
the SCU to select the ADC.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 56 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
Clock pins
CLK0 N5 M4 K3 45 [4] O;
PU
O EMC_CLK0 — SDRAM clock 0.
O CLKOUT — Clock output pin.
- R — Function reserved.
- R — Function reserved.
I/O SD_CLK — SD/MMC card clock.
O EMC_CLK01 — SDRAM clock 0 and clock 1 combined.
I/O SSP1_SCK — Serial clock for SSP1.
I ENET_TX_CLK (ENET_REF_CLK) — Ethernet Transmit
Clock (MII interface) or Ethernet Reference Clock (RMII
interface).
CLK1 T10 - - - [4] O;
PU
O EMC_CLK1 — SDRAM clock 1.
O CLKOUT — Clock output pin.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
O CGU_OUT0 — CGU spare clock output 0.
- R — Function reserved.
O I2S1_TX_MCLK — I2S1 transmit master clock.
CLK2 D14 P10 K6 99 [4] O;
PU
O EMC_CLK3 — SDRAM clock 3.
O CLKOUT — Clock output pin.
- R — Function reserved.
- R — Function reserved.
I/O SD_CLK — SD/MMC card clock.
O EMC_CLK23 — SDRAM clock 2 and clock 3 combined.
O I2S0_TX_MCLK — I2S transmit master clock.
I/O I2S1_RX_SCK — Receive Clock. It is driven by the master and
received by the slave. Corresponds to the signal SCK in the
I
2S-bus specification.
CLK3 P12 - - - [4] O;
PU
O EMC_CLK2 — SDRAM clock 2.
O CLKOUT — Clock output pin.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
O CGU_OUT1 — CGU spare clock output 1.
- R — Function reserved.
I/O I2S1_RX_SCK — Receive Clock. It is driven by the master and
received by the slave. Corresponds to the signal SCK in the
I
2S-bus specification.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 57 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
Debug pins
DBGEN L4 K4 A6 28 [2] I; PU I JTAG interface control signal. Also used for boundary scan. To
use the part in functional mode, connect this pin in one of the
following ways:
• Leave DBGEN open. The DBGEN pin is pulled up
internally by a 50 kΩ resistor.
• Tie DBGEN to VDDIO.
• Pull DBGEN up to VDDIO with an external pull-up resistor.
TCK/SWDCLK J5 G5 H2 27 [2] I; F I Test Clock for JTAG interface (default) or Serial Wire (SW)
clock.
TRST M4 L4 B4 29 [2] I; PU I Test Reset for JTAG interface.
TMS/SWDIO K6 K5 C4 30 [2] I; PU I Test Mode Select for JTAG interface (default) or SW debug
data input/output.
TDO/SWO K5 J5 H3 31 [2] O O Test Data Out for JTAG interface (default) or SW trace output.
TDI J4 H4 G3 26 [2] I; PU I Test Data In for JTAG interface.
USB0 pins
USB0_DP F2 E2 E1 18 [6] - I/O USB0 bidirectional D+ line.
USB0_DM G2 F2 E2 20 [6] - I/O USB0 bidirectional D line.
USB0_VBUS F1 E1 E3 21 [6]
[7]
- I/O VBUS pin (power on USB cable). This pin includes an internal
pull-down resistor of 64 kΩ (typical) 16 kΩ.
USB0_ID H2 G2 F1 22 [8] - I Indicates to the transceiver whether connected as an A-device
(USB0_ID LOW) or B-device (USB0_ID HIGH). For OTG this
pin has an internal pull-up resistor.
USB0_RREF H1 G1 F3 24 [8] - 12.0 kΩ (accuracy 1 %) on-board resistor to ground for current
reference.
USB1 pins
USB1_DP F12 D11 E9 89 [9] - I/O USB1 bidirectional D+ line.
USB1_DM G12 E11 E10 90 [9] - I/O USB1 bidirectional D line.
I
2C-bus pins
I2C0_SCL L15 K13 D6 92 [10] I; F I/O I2C clock input/output. Open-drain output (for I2C-bus
compliance).
I2C0_SDA L16 K14 E6 93 [10] I; F I/O I2C data input/output. Open-drain output (for I2C-bus
compliance).
Reset and wake-up pins
RESET D9 C7 B6 128 [11] I; IA I External reset input: A LOW-going pulse as short as 50 ns on
this pin resets the device, causing I/O ports and peripherals to
take on their default states, and processor execution to begin
at address 0. This pin does not have an internal pull-up.
WAKEUP0 A9 A9 A4 130 [11] I; IA I External wake-up input; can raise an interrupt and can cause
wake-up from any of the low-power modes. A pulse with a
duration > 45 ns wakes up the part. This pin does not have an
internal pull-up.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 58 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
WAKEUP1 A10 C8 - - [11] I; IA I External wake-up input; can raise an interrupt and can cause
wake-up from any of the low-power modes. A pulse with a
duration > 45 ns wakes up the part. This pin does not have an
internal pull-up.
WAKEUP2 C9 E5 - - [11] I; IA I External wake-up input; can raise an interrupt and can cause
wake-up from any of the low-power modes. A pulse with a
duration > 45 ns wakes up the part. This pin does not have an
internal pull-up.
WAKEUP3 D8 - - - [11] I; IA I External wake-up input; can raise an interrupt and can cause
wake-up from any of the low-power modes. A pulse with a
duration > 45 ns wakes up the part. This pin does not have an
internal pull-up.
ADC pins
ADC0_0/
ADC1_0/DAC
E3 B6 A2 6 [8] I; IA I ADC input channel 0. Shared between 10-bit ADC0/1 and
DAC.
ADC0_1/
ADC1_1
C3 C4 A1 2 [8] I; IA I ADC input channel 1. Shared between 10-bit ADC0/1.
ADC0_2/
ADC1_2
A4 B3 B3 143 [8] I; IA I ADC input channel 2. Shared between 10-bit ADC0/1.
ADC0_3/
ADC1_3
B5 B4 A3 139 [8] I; IA I ADC input channel 3. Shared between 10-bit ADC0/1.
ADC0_4/
ADC1_4
C6 A5 - 138 [8] I; IA I ADC input channel 4. Shared between 10-bit ADC0/1.
ADC0_5/
ADC1_5
B3 C3 - 144 [8] I; IA I ADC input channel 5. Shared between 10-bit ADC0/1.
ADC0_6/
ADC1_6
A5 A4 - 142 [8] I; IA I ADC input channel 6. Shared between 10-bit ADC0/1.
ADC0_7/
ADC1_7
C5 B5 - 136 [8] I; IA I ADC input channel 7. Shared between 10-bit ADC0/1.
RTC
RTC_ALARM A11 A10 C3 129 [11] O O RTC controlled output. This pin has an internal pull-up. The
reset state of this pin is LOW after POR. For all other types of
reset, the reset state depends on the state of the RTC alarm
interrupt.
RTCX1 A8 A8 A5 125 [8] - I Input to the RTC 32 kHz ultra-low power oscillator circuit.
RTCX2 B8 B7 B5 126 [8] - O Output from the RTC 32 kHz ultra-low power oscillator circuit.
Crystal oscillator pins
XTAL1 D1 C1 B1 12 [8] - I Input to the oscillator circuit and internal clock generator
circuits.
XTAL2 E1 D1 C1 13 [8] - O Output from the oscillator amplifier.
Power and ground pins
USB0_VDDA
3V3_DRIVER
F3 E3 D1 16 - - Separate analog 3.3 V power supply for driver.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 59 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
USB0
_VDDA3V3
G3 F3 D2 17 - - USB 3.3 V separate power supply voltage.
USB0_VSSA
_TERM
H3 G3 D3 19 - - Dedicated analog ground for clean reference for termination
resistors.
USB0_VSSA
_REF
G1 F1 F2 23 - - Dedicated clean analog ground for generation of reference
currents and voltages.
VDDA B4 A6 B2 137 - - Analog power supply and ADC reference voltage.
VBAT B10 B9 C5 127 - - RTC power supply: 3.3 V on this pin supplies power to the
RTC.
VDDREG F10,
F9,
L8,
L7
D8,
E8
E4,
E5,
F4
94,
131,
59,
25
- Main regulator power supply. Tie the VDDREG and VDDIO
pins to a common power supply to ensure the same ramp-up
time for both supply voltages.
VPP E8 - - - [12] - - OTP programming voltage.
VDDIO D7,
E12,
F7,
F8,
G10,
H10,
J6,
J7,
K7,
L9,
L10,
N7,
N13
H5,
H10,
K8,
G10
F10,
K5
5,
36,
41,
71,
77,
107,
111,
141
[12] - - I/O power supply. Tie the VDDREG and VDDIO pins to a
common power supply to ensure the same ramp-up time for
both supply voltages.
VDD - - - - Power supply for main regulator, I/O, and OTP.
VSS G9,
H7,
J10,
J11,
K8
F10,
D7,
E6,
E7,
E9,
K6,
K9
- - [13]
[14]
- - Ground.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 60 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
[1] N = neutral, input buffer disabled; no extra VDDIO current consumption if the input is driven midway between supplies; set the EZI bit in
the SFS register to enable the input buffer; I = input; OL = output driving LOW; OH = output driving HIGH; AI/O = analog input/output; IA
= inactive; PU = pull-up enabled (weak pull-up resistor pulls up pin to VDDIO; F = floating. Reset state reflects the pin state at reset
without boot code operation.
[2] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides digital I/O
functions with TTL levels and hysteresis; normal drive strength.
[3] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides digital I/O
functions with TTL levels, and hysteresis; high drive strength.
[4] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V); provides high-speed
digital I/O functions with TTL levels and hysteresis.
[5] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input or output (5 V tolerant if VDDIO present;
if VDDIO not present, do not exceed 3.6 V). When configured as an ADC input or DAC output, the pin is not 5 V tolerant and the digital
section of the pad must be disabled by setting the pin to an input function and disabling the pull-up resistor through the pin’s SFSP
register.
[6] 5 V tolerant transparent analog pad.
[7] For maximum load CL = 6.5 μF and maximum pull-down resistance Rpd = 80 kΩ, the VBUS signal takes about 2 s to fall from VBUS =
5 V to VBUS = 0.2 V when it is no longer driven.
[8] Transparent analog pad. Not 5 V tolerant.
[9] Pad provides USB functions 5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V. It is designed in accordance with
the USB specification, revision 2.0 (Full-speed and Low-speed mode only).
[10] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus Fast Mode Plus specification. This pad requires an external pull-up to
provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines.
[11] 5 V tolerant pad with 20 ns glitch filter; provides digital I/O functions with open-drain output and hysteresis.
[12] On the TFBGA100 package, VPP is internally connected to VDDIO.
[13] On the LQFP144 package, VSSIO and VSS are connected to a common ground plane.
[14] On the TFBGA100 package, VSS is internally connected to VSSIO.
VSSIO C4,
D13,
G6,
G7,
G8,
H8,
H9,
J8,
J9,
K9,
K10,
M13,
P7,
P13
- C8,
D4,
D5,
G8,
J3,
J6
4,
40,
76,
109
[13]
[14]
- - Ground.
VSSA B2 A3 C2 135 - - Analog ground.
Not connected
- B9 B8 - - - - n.c.
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256
TFBGA180
TFBGA100
LQFP144
Reset state
[1]
Type
DescriptionLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 61 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
7. Functional description
7.1 Architectural overview
The ARM Cortex-M4 includes three AHB-Lite buses: the system bus, the I-CODE bus,
and the D-code bus. The I-CODE and D-code core buses allow for concurrent code and
data accesses from different slave ports.
The LPC4350/30/20/10 use a multi-layer AHB matrix to connect the ARM Cortex-M4
buses and other bus masters to peripherals in a flexible manner that optimizes
performance by allowing peripherals that are on different slaves ports of the matrix to be
accessed simultaneously by different bus masters.
An ARM Cortex-M0 co-processor is included in the LPC4350/30/20/10, capable of
off-loading the main ARM Cortex-M4 application processor. Most peripheral interrupts are
connected to both processors. The processors communicate with each other via an
interprocessor communication protocol.
7.2 ARM Cortex-M4 processor
The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture
with separate local instruction and data buses as well as a third bus for peripherals, and
includes an internal prefetch unit that supports speculative branching. The ARM
Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A
hardware floating-point processor is integrated in the core. The processor includes an
NVIC with up to 53 interrupts.
7.3 ARM Cortex-M0 co-processor
The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high
performance and very low-power consumption. The ARM Cortex-M0 co-processor uses a
3-stage pipeline von-Neumann architecture and a small but powerful instruction set
providing high-end processing hardware. The co-processor incorporates an NVIC with 32
interrupts.
7.4 Interprocessor communication
The ARM Cortex-M4 and ARM Cortex-M0 interprocessor communication is based on
using shared SRAM as mailbox and one processor raising an interrupt on the other
processor's NVIC, for example after it has delivered a new message in the mailbox. The
receiving processor can reply by raising an interrupt on the sending processor's NVIC to
acknowledge the message.LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 62 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
7.5 AHB multilayer matrix
7.6 Nested Vectored Interrupt Controller (NVIC)
The NVIC is an integral part of the Cortex-M4. The tight coupling to the CPU allows for low
interrupt latency and efficient processing of late arriving interrupts.
The ARM Cortex-M0 co-processor has its own NVIC with 32 vectored interrupts. Most
peripheral interrupts are shared between the Cortex-M0 and Cortex-M4 NVICs.
Fig 6. AHB multilayer matrix master and slave connections
ARM
CORTEX-M4
TEST/DEBUG
INTERFACE
ARM
CORTEX-M0
TEST/DEBUG
INTERFACE
DMA ETHERNET USB0 USB1 LCD SD/
MMC
EXTERNAL
MEMORY
CONTROLLER
APB, RTC
DOMAIN
PERIPHERALS
16 kB + 16 kB
AHB SRAM
64 kB ROM
128 kB LOCAL SRAM
72 kB LOCAL SRAM
System
bus
I-
code
bus
D-
code
bus
masters
slaves
0 1
AHB MULTILAYER MATRIX
= master-slave connection
32 kB AHB SRAM
SPIFI
SGPIO
AHB PERIPHERALS
REGISTER
INTERFACES
002aaf873
HIGH-SPEED PHYLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 63 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
7.6.1 Features
• Controls system exceptions and peripheral interrupts.
• The Cortex-M4 NVIC supports up to 53 vectored interrupts.
• Eight programmable interrupt priority levels with hardware priority level masking.
• Relocatable vector table.
• Non-Maskable Interrupt (NMI).
• Software interrupt generation.
7.6.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags can represent more than one interrupt source.
7.7 System Tick timer (SysTick)
The ARM Cortex-M4 includes a system tick timer (SysTick) that is intended to generate a
dedicated SYSTICK exception at a 10 ms interval.
Remark: The SysTick is not included in the ARM Cortex-M0 core.
7.8 Event router
The event router combines various internal signals, interrupts, and the external interrupt
pins (WAKEUP[3:0]) to create an interrupt in the NVIC, if enabled. In addition, the event
router creates a wake-up signal to the ARM core and the CCU for waking up from Sleep,
Deep-sleep, Power-down, and Deep power-down modes. Individual events can be
configured as edge or level sensitive and can be enabled or disabled in the event router.
The event router can be battery powered.
The following events if enabled in the event router can create a wake-up signal from
sleep, deep-sleep, power-down, and deep power-down modes and/or create an interrupt:
• External pins WAKEUP0/1/2/3 and RESET
• Alarm timer, RTC (32 kHz oscillator running)
The following events if enabled in the event router can create a wake-up signal from sleep
mode only and/or create an interrupt:
• WWDT, BOD interrupts
• C_CAN0/1 and QEI interrupts
• Ethernet, USB0, USB1 signals
• Selected outputs of combined timers (SCTimer/PWM and timer0/1/3)
Remark: Any interrupt can wake up the ARM Cortex-M4 from sleep mode if enabled in
the NVIC.
7.9 Global Input Multiplexer Array (GIMA)
The GIMA routes signals to event-driven peripheral targets like the SCTimer/PWM,
timers, event router, or the ADCs.LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 64 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
7.9.1 Features
• Single selection of a source.
• Signal inversion.
• Can capture a pulse if the input event source is faster than the target clock.
• Synchronization of input event and target clock.
• Single-cycle pulse generation for target.
7.10 On-chip static RAM
The LPC4350/30/20/10 support up to 200 kB local SRAM and an additional 64 kB AHB
SRAM with separate bus master access for higher throughput and individual power
control for low-power operation.
7.11 In-System Programming (ISP)
In-System Programming (ISP) means programming or reprogramming the on-chip SRAM
memory, using the boot loader software and the USART0 serial port. ISP can be
performed when the part resides in the end-user board. ISP loads data into on-chip SRAM
and execute code from on-chip SRAM.
7.12 Boot ROM
The internal ROM memory is used to store the boot code of the LPC4350/30/20/10. After
a reset, the ARM processor will start its code execution from this memory.
The boot ROM memory includes the following features:
• The ROM memory size is 64 kB.
• Supports booting from UART interfaces and external static memory such as NOR
flash, quad SPI flash, and USB0 and USB1.
• Includes API for OTP programming.
• Includes a flexible USB device stack that supports Human Interface Device (HID),
Mass Storage Class (MSC), and Device Firmware Upgrade (DFU) drivers.
Several boot modes are available depending on the values of the OTP bits BOOT_SRC. If
the OTP memory is not programmed or the BOOT_SRC bits are all zero, the boot mode is
determined by the states of the boot pins P2_9, P2_8, P1_2, and P1_1.
Table 4. Boot mode when OTP BOOT_SRC bits are programmed
Boot mode BOOT_SRC
bit 3
BOOT_SRC
bit 2
BOOT_SRC
bit 1
BOOT_SRC
bit 0
Description
Pin state 0 0 0 0 Boot source is defined by the reset state of P1_1,
P1_2, P2_8, and P2_9 pins. See Table 5.
USART0 0 0 0 1 Boot from device connected to USART0 using pins
P2_0 and P2_1.
SPIFI 0 0 1 0 Boot from Quad SPI flash connected to the SPIFI
interface using pins P3_3 to P3_8.
EMC 8-bit 0 0 1 1 Boot from external static memory (such as NOR
flash) using CS0 and an 8-bit data bus.LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 65 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
[1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.
Remark: Pin functions for SPIFI and SSP0 boot are different.
[1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.
Remark: Pin functions for SPIFI and SSP0 boot are different.
7.13 Memory mapping
The memory map shown in Figure 7 and Figure 8 is global to both the Cortex-M4 and the
Cortex-M0 processors and all SRAM is shared between both processors. Each processor
uses its own ARM private bus memory map for the NVIC and other system functions.
EMC 16-bit 0 1 0 0 Boot from external static memory (such as NOR
flash) using CS0 and a 16-bit data bus.
EMC 32-bit 0 1 0 1 Boot from external static memory (such as NOR
flash) using CS0 and a 32-bit data bus.
USB00 1 1 0 Boot from USB0.
USB10 1 1 1 Boot from USB1.
SPI (SSP) 1 0 0 0 Boot from SPI flash connected to the SSP0
interface on P3_3 (function SSP0_SCK), P3_6
(function SSP0_SSEL), P3_7 (function
SSP0_MISO), and P3_8 (function SSP0_MOSI)[1].
USART3 1 0 0 1 Boot from device connected to USART3 using pins
P2_3 and P2_4.
Table 4. Boot mode when OTP BOOT_SRC bits are programmed …continued
Boot mode BOOT_SRC
bit 3
BOOT_SRC
bit 2
BOOT_SRC
bit 1
BOOT_SRC
bit 0
Description
Table 5. Boot mode when OPT BOOT_SRC bits are zero
Boot mode Pins Description
P2_9 P2_8 P1_2 P1_1
USART0 LOW LOW LOW LOW Boot from device connected to USART0 using pins
P2_0 and P2_1.
SPIFI LOW LOW LOW HIGH Boot from Quad SPI flash connected to the SPIFI
interface on P3_3 to P3_8[1].
EMC 8-bit LOW LOW HIGH LOW Boot from external static memory (such as NOR
flash) using CS0 and an 8-bit data bus.
EMC 16-bit LOW LOW HIGH HIGH Boot from external static memory (such as NOR
flash) using CS0 and a 16-bit data bus.
EMC 32-bit LOW HIGH LOW LOW Boot from external static memory (such as NOR
flash) using CS0 and a 32-bit data bus.
USB0 LOW HIGH LOW HIGH Boot from USB0
USB1 LOW HIGH HIGH LOW Boot from USB1.
SPI (SSP) LOW HIGH HIGH HIGH Boot from SPI flash connected to the SSP0
interface on P3_3 (function SSP0_SCK), P3_6
(function SSP0_SSEL), P3_7 (function
SSP0_MISO), and P3_8 (function SSP0_MOSI)[1].
USART3 HIGH LOW LOW LOW Boot from device connected to USART3 using pins
P2_3 and P2_4.LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 66 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
Fig 7. LPC4350/30/20/10 Memory mapping (overview)
reserved
peripheral bit band alias region
reserved
reserved
high-speed GPIO
reserved
0 GB 0x0000 0000
1 GB
4 GB
0x2001 0000
0x2200 0000
0x2400 0000
0x2800 0000
0x1000 0000
0x3000 0000
0x4000 0000
0x4001 2000
0x4004 0000
0x4005 0000
0x4010 0000
0x4400 0000
0x6000 0000
AHB peripherals
APB peripherals #0
APB peripherals #1
reserved
reserved
reserved
RTC domain peripherals
0x4006 0000
0x4008 0000
0x4009 0000
0x400A 0000
0x400B 0000
0x400C 0000
0x400D 0000
0x400E 0000
0x400F 0000
0x400F 1000
0x400F 2000
0x400F 4000
0x400F 8000
clocking/reset peripherals
APB peripherals #2
APB peripherals #3
0x2000 8000
16 kB AHB SRAM (LPC4350/30)
16 kB AHB SRAM (LPC4350/30/20/10)
0x2000 C000
16 kB AHB SRAM (LPC4350/30)
16 kB AHB SRAM (LPC4350/30/20/10)
SGPIO
SPI
0x4010 1000
0x4010 2000
0x4200 0000
reserved
local SRAM/
external static memory banks
0x2000 0000
0x2000 4000
128 MB dynamic external memory DYCS0
256 MB dynamic external memory DYCS1
256 MB dynamic external memory DYCS2
256 MB dynamic external memory DYCS3 0x7000 0000
0x8000 0000
0x8800 0000
0xE000 0000
256 MB shadow area
LPC4350/30/20/10
0x1000 0000
0x1002 0000
0x1008 0000
0x1008 A000
0x1009 2000
0x1040 0000
0x1041 0000
0x1C00 0000
0x1D00 0000
reserved
reserved
32 MB AHB SRAM bit banding
reserved
reserved
reserved
0xE010 0000
0xFFFF FFFF
reserved
SPIFI data
ARM private bus
reserved
0x1001 8000 32 kB local SRAM (LPC4350/30/20)
96 kB local SRAM
(LPC4350/30/20/10)
32 kB + 8 kB local SRAM
(LPC4320/10)
64 kB + 8 kB local SRAM
(LPC4350/30)
reserved
reserved
reserved
reserved
64 kB ROM
0x1400 0000
0x1800 0000
SPIFI data
0x1E00 0000
0x1F00 0000
0x2000 0000
16 MB static external memory CS3
16 MB static external memory CS2
16 MB static external memory CS1
16 MB static external memory CS0
002aaf774xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 67 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller Fig 8. LPC4350/30/20/10 Memory mapping (peripherals)
reserved
peripheral bit band alias region
high-speed GPIO
reserved
reserved
reserved
reserved
0x4000 0000
0x0000 0000
0x4001 2000
0x4004 0000
0x4005 0000
0x4010 0000
0x4400 0000
0x6000 0000
0xFFFF FFFF
AHB peripherals
SRAM memories
external memory banks
APB0 peripherals
APB1 peripherals
reserved
reserved
reserved
RTC domain peripherals
0x4006 0000
0x4008 0000
0x4009 0000
0x400A 0000
0x400B 0000
0x400C 0000
0x400D 0000
0x400E 0000
0x400F 0000
0x400F 1000
0x400F 2000
0x400F 4000
0x400F 8000
clocking/reset peripherals
APB2 peripherals
APB3 peripherals
SGPIO
SPI
0x4010 1000
0x4010 2000
0x4200 0000
reserved
external memories and
ARM private bus
APB2
peripherals
0x400C 1000
0x400C 2000
0x400C 3000
0x400C 4000
0x400C 6000
0x400C 8000
0x400C 7000
0x400C 5000
0x400C 0000 RI timer
USART2
USART3
timer2
timer3
SSP1
QEI
APB1
peripherals
0x400A 1000
0x400A 2000
0x400A 3000
0x400A 4000
0x400A 5000
0x400B 0000
0x400A 0000 motor control PWM
I2C0
I2S0
I2S1
C_CAN1
reserved
AHB
peripherals
0x4000 1000
0x4000 0000 SCT
0x4000 2000
0x4000 3000
0x4000 4000
0x4000 6000
0x4000 8000
0x4001 0000
0x4001 2000
0x4000 9000
0x4000 7000
0x4000 5000
DMA
SD/MMC
EMC
USB1
LCD
USB0
reserved
SPIFI
ethernet
reserved
0x4008 1000
0x4008 0000 WWDT
0x4008 2000
0x4008 3000
0x4008 4000
0x4008 6000
0x4008 A000
0x4008 7000
0x4008 8000
0x4008 9000
0x4008 5000
UART1 w/ modem
SSP0
timer0
timer1
SCU
GPIO interrupts
GPIO GROUP0 interrupt
GPIO GROUP1 interrupt
USART0
RTC domain
peripherals
0x4004 1000
alarm timer 0x4004 0000
0x4004 2000
0x4004 3000
0x4004 4000
0x4004 6000
0x4004 7000
0x4004 5000
power mode control
CREG
event router
OTP controller
reserved
reserved
RTC
backup registers
clocking
reset control
peripherals
0x4005 1000
0x4005 0000 CGU
0x4005 2000
0x4005 3000
0x4005 4000
0x4006 0000
CCU2
RGU
CCU1
LPC4350/30/20/10
002aaf775
reserved
reserved
APB3
peripherals
0x400E 1000
0x400E 2000
0x400E 3000
0x400E 4000
0x400F 0000
0x400E 5000
0x400E 0000 I2C1
DAC
C_CAN0
ADC0
ADC1
reserved
GIMA
APB0
peripheralsLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 68 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
7.14 One-Time Programmable (OTP) memory
The OTP provides 64 bit + 256 bit One-Time Programmable (OTP) memory for
general-purpose use.
7.15 General-Purpose I/O (GPIO)
The LPC4350/30/20/10 provide eight GPIO ports with up to 31 GPIO pins each.
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back as well as the current state of the port pins.
All GPIO pins default to inputs with pull-up resistors enabled and input buffer disabled on
reset. The input buffer must be turned on in the system control block SFS register before
the GPIO input can be read.
7.15.1 Features
• Accelerated GPIO functions:
– GPIO registers are located on the AHB so that the fastest possible I/O timing can
be achieved.
– Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
– All GPIO registers are byte and half-word addressable.
– Entire port value can be written in one instruction.
• Bit-level set and clear registers allow a single instruction set or clear of any number of
bits in one port.
• Direction control of individual bits.
• Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or
level-sensitive GPIO interrupt request (GPIO interrupts).
• Two GPIO group interrupts can be triggered by any pin or pins in each port (GPIO
group0 and group1 interrupts).
7.16 Configurable digital peripherals
7.16.1 State Configurable Timer (SCTimer/PWM) subsystem
The SCTimer/PWM allows a wide variety of timing, counting, output modulation, and input
capture operations. The inputs and outputs of the SCTimer/PWM are shared with the
capture and match inputs/outputs of the 32-bit general-purpose counter/timers.
The SCTimer/PWM can be configured as two 16-bit counters or a unified 32-bit counter. In
the two-counter case, in addition to the counter value the following operational elements
are independent for each half:
• State variable
• Limit, halt, stop, and start conditions
• Values of Match/Capture registers, plus reload or capture control valuesLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 69 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
In the two-counter case, the following operational elements are global to the
SCTimer/PWM, but the last three can use match conditions from either counter:
• Clock selection
• Inputs
• Events
• Outputs
• Interrupts
7.16.1.1 Features
• Two 16-bit counters or one 32-bit counter.
• Counters clocked by bus clock or selected input.
• Counters can be configured as up-counters or up-down counters.
• State variable allows sequencing across multiple counter cycles.
• Event combines input or output condition and/or counter match in a specified state.
• Events control outputs and interrupts.
• Selected events can limit, halt, start, or stop a counter.
• Supports:
– up to 8 inputs
– 16 outputs
– 16 match/capture registers
– 16 events
– 32 states
7.16.2 Serial GPIO (SGPIO)
The Serial GPIOs offer standard GPIO functionality enhanced with features to accelerate
serial stream processing.
7.16.2.1 Features
• Each SGPIO input/output slice can be used to perform a serial to parallel or parallel to
serial data conversion.
• 16 SGPIO input/output slices each with a 32-bit FIFO that can shift the input value
from a pin or an output value to a pin with every cycle of a shift clock.
• Each slice is double-buffered.
• Interrupt is generated on a full FIFO, shift clock, or pattern match.
• Slices can be concatenated to increase buffer size.
• Each slice has a 32-bit pattern match filter.LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 70 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
7.17 AHB peripherals
7.17.1 General-Purpose DMA (GPDMA)
The DMA controller allows peripheral-to memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
example, a bidirectional port requires one stream for transmit and one for receives. The
source and destination areas can each be either a memory region or a peripheral for
master 1, but only memory for master 0.
7.17.1.1 Features
• Eight DMA channels. Each channel can support a unidirectional transfer.
• 16 DMA request lines.
• Single DMA and burst DMA request signals. Each peripheral connected to the DMA
Controller can assert either a burst DMA request or a single DMA request. The DMA
burst size is set by programming the DMA Controller.
• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral transfers are supported.
• Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.
• Hardware DMA channel priority.
• AHB slave DMA programming interface. The DMA Controller is programmed by
writing to the DMA control registers over the AHB slave interface.
• Two AHB bus masters for transferring data. These interfaces transfer data when a
DMA request goes active. Master 1 can access memories and peripherals, master 0
can access memories only.
• 32-bit AHB master bus width.
• Incrementing or non-incrementing addressing for source and destination.
• Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data.
• Internal four-word FIFO per channel.
• Supports 8, 16, and 32-bit wide transactions.
• Big-endian and little-endian support. The DMA Controller defaults to little-endian
mode on reset.
• An interrupt to the processor can be generated on a DMA completion or when a DMA
error has occurred.
• Raw interrupt status. The DMA error and DMA count raw interrupt status can be read
prior to masking.
7.17.2 SPI Flash Interface (SPIFI)
The SPI Flash Interface allows low-cost serial flash memories to be connected to the ARM
Cortex-M4 processor with little performance penalty compared to parallel flash devices
with higher pin count. LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 71 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
After a few commands configure the interface at startup, the entire flash content is
accessible as normal memory using byte, halfword, and word accesses by the processor
and/or DMA channels. Simple sequences of commands handle erasing and
programming.
Many serial flash devices use a half-duplex command-driven SPI protocol for device setup
and initialization and then move to a half-duplex, command-driven 4-bit protocol for
normal operation. Different serial flash vendors and devices accept or require different
commands and command formats. SPIFI provides sufficient flexibility to be compatible
with common flash devices and includes extensions to help insure compatibility with future
devices.
7.17.2.1 Features
• Interfaces to serial flash memory in the main memory map.
• Supports classic and 4-bit bidirectional serial protocols.
• Half-duplex protocol compatible with various vendors and devices.
• Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to
52 MB per second.
• Supports DMA access.
7.17.3 SD/MMC card interface
The SD/MMC card interface supports the following modes to control:
• Secure Digital memory (SD version 3.0)
• Secure Digital I/O (SDIO version 2.0)
• Consumer Electronics Advanced Transport Architecture (CE-ATA version 1.1)
• MultiMedia Cards (MMC version 4.4)
7.17.4 External Memory Controller (EMC)
The LPC4350/30/20/10 EMC is a Memory Controller peripheral offering support for
asynchronous static memory devices such as RAM, ROM, and NOR flash. In addition, it
can be used as an interface with off-chip memory-mapped devices and peripherals.
7.17.4.1 Features
• Dynamic memory interface support including single data rate SDRAM.
• Asynchronous static memory device support including RAM, ROM, and NOR flash,
with or without asynchronous page mode.
• Low transaction latency.
• Read and write buffers to reduce latency and to improve performance.
• 8/16/32 data and 24 address lines-wide static memory support.
• 16 bit and 32 bit wide chip select SDRAM memory support.
• Static memory features include:
– Asynchronous page mode read
– Programmable Wait States
– Bus turnaround delayLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 72 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
– Output enable and write enable delays
– Extended wait
• Four chip selects for synchronous memory and four chip selects for static memory
devices.
• Power-saving modes dynamically control EMC_CKEOUT and EMC_CLK signals to
SDRAMs.
• Dynamic memory self-refresh mode controlled by software.
• Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row
address synchronous memory parts. Those are typically 512 MB, 256 MB, and
128 MB parts, with 4, 8, 16, or 32 data bits per device.
• Separate reset domains allow auto-refresh through a chip reset if desired.
• SDRAM clock can run at full or half the Cortex-M4 core frequency.
Note: Synchronous static memory devices (synchronous burst mode) are not supported.
7.17.5 High-speed USB Host/Device/OTG interface (USB0)
Remark: The USB0 controller is available on parts LPC4350/30/20. See Table 2.
The USB OTG module allows the LPC4350/30/20/10 to connect directly to a USB Host
such as a PC (in device mode) or to a USB Device in host mode.
7.17.5.1 Features
• On-chip UTMI+ compliant high-speed transceiver (PHY).
• Complies with Universal Serial Bus specification 2.0.
• Complies with USB On-The-Go supplement.
• Complies with Enhanced Host Controller Interface Specification.
• Supports auto USB 2.0 mode discovery.
• Supports all high-speed USB-compliant peripherals.
• Supports all full-speed USB-compliant peripherals.
• Supports software Host Negotiation Protocol (HNP) and Session Request Protocol
(SRP) for OTG peripherals.
• Supports interrupts.
• This module has its own, integrated DMA engine.
• USB interface electrical test software included in ROM USB stack.
7.17.6 High-speed USB Host/Device interface with ULPI (USB1)
Remark: The USB1 controller is available on parts LPC4350/30. See Table 2.
The USB1 interface can operate as a full-speed USB Host/Device interface or can
connect to an external ULPI PHY for High-speed operation.
7.17.6.1 Features
• Complies with Universal Serial Bus specification 2.0.
• Complies with Enhanced Host Controller Interface Specification.LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 73 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
• Supports auto USB 2.0 mode discovery.
• Supports all high-speed USB-compliant peripherals if connected to external ULPI
PHY.
• Supports all full-speed USB-compliant peripherals.
• Supports interrupts.
• This module has its own, integrated DMA engine.
• USB interface electrical test software included in ROM USB stack.
7.17.7 LCD controller
Remark: The LCD controller is available on LPC4350 only. See Table 2.
The LCD controller provides all of the necessary control signals to interface directly to
various color and monochrome LCD panels. Both STN (single and dual panel) and TFT
panels can be operated. The display resolution is selectable and can be up to 1024 768
pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.
An on-chip 512 byte color palette allows reducing bus utilization (that is, memory size of
the displayed data) while still supporting many colors.
The LCD interface includes its own DMA controller to allow it to operate independently of
the CPU and other system functions. A built-in FIFO acts as a buffer for display data,
providing flexibility for system timing. Hardware cursor support can further reduce the
amount of CPU time required to operate the display.
7.17.7.1 Features
• AHB master interface to access frame buffer.
• Setup and control via a separate AHB slave interface.
• Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.
• Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays
with 4-bit or 8-bit interfaces.
• Supports single and dual-panel color STN displays.
• Supports Thin Film Transistor (TFT) color displays.
• Programmable display resolution including, but not limited to: 320 200, 320 240,
640 200, 640 240, 640 480, 800 600, and 1024 768.
• Hardware cursor support for single-panel displays.
• 15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support.
• 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.
• 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.
• 16 bpp true-color non-palettized for color STN and TFT.
• 24 bpp true-color non-palettized for color TFT.
• Programmable timing for different display panels.
• 256 entry, 16-bit palette RAM, arranged as a 128 32-bit RAM.
• Frame, line, and pixel clock signals.
• AC bias signal for STN, data enable signal for TFT panels.
• Supports little and big-endian, and Windows CE data formats.LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 74 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
• LCD panel clock may be generated from the peripheral clock, or from a clock input
pin.
7.17.8 Ethernet
Remark: The Ethernet peripheral is available on parts LPC4350/30. See Table 2.
7.17.8.1 Features
• 10/100 Mbit/s
• DMA support
• Power management remote wake-up frame and magic packet detection
• Supports both full-duplex and half-duplex operation
– Supports CSMA/CD Protocol for half-duplex operation.
– Supports IEEE 802.3x flow control for full-duplex operation.
– Optional forwarding of received pause control frames to the user application in
full-duplex operation.
– Back-pressure support for half-duplex operation.
– Automatic transmission of zero-quanta pause frame on deassertion of flow control
input in full-duplex operation.
• Supports IEEE1588 time stamping and IEEE 1588 advanced time stamping (IEEE
1588-2008 v2).
7.18 Digital serial peripherals
7.18.1 UART1
The LPC4350/30/20/10 contain one UART with standard transmit and receive data lines.
UART1 also provides a full modem control handshake interface and support for
RS-485/9-bit mode allowing both software address detection and automatic address
detection using 9-bit mode.
UART1 includes a fractional baud rate generator. Standard baud rates such as 115200 Bd
can be achieved with any crystal frequency above 2 MHz.
7.18.1.1 Features
• Maximum UART data bit rate of 8 MBit/s.
• 16 B Receive and Transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
• Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• Auto baud capabilities and FIFO control mechanism that enables software flow
control implementation.
• Equipped with standard modem interface signals. This module also provides full
support for hardware flow control.
• Support for RS-485/9-bit/EIA-485 mode (UART1).LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 75 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
• DMA support.
7.18.2 USART0/2/3
The LPC4350/30/20/10 contain three USARTs. In addition to standard transmit and
receive data lines, the USARTs support a synchronous mode.
The USARTs include a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.18.2.1 Features
• Maximum UART data bit rate of 8 MBit/s.
• 16 B Receive and Transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
• Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• Auto baud capabilities and FIFO control mechanism that enables software flow
control implementation.
• Support for RS-485/9-bit/EIA-485 mode.
• USART3 includes an IrDA mode to support infrared communication.
• All USARTs have DMA support.
• Support for synchronous mode at a data bit rate of up to 8 Mbit/s.
• Smart card mode conforming to ISO7816 specification
7.18.3 SPI serial I/O controller
The LPC4350/30/20/10 contain one SPI controller. SPI is a full-duplex serial interface
designed to handle multiple masters and slaves connected to a given bus. Only a single
master and a single slave can communicate on the interface during a given data transfer.
During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and
the slave always sends 8 bits to 16 bits of data to the master.
7.18.3.1 Features
• Maximum SPI data bit rate 25 Mbit/s.
• Compliant with SPI specification
• Synchronous, serial, full-duplex communication
• Combined SPI master and slave
• Maximum data bit rate of one eighth of the input clock rate
• 8 bits to 16 bits per transfer
7.18.4 SSP serial I/O controller
Remark: The LPC4350/30/20/10 contain two SSP controllers.
The SSP controller can operate on a SPI, 4-wire SSI, or Microwire bus. It can interact with
multiple masters and slaves on the bus. Only a single master and a single slave can
communicate on the bus during a given data transfer. The SSP supports full-duplex LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 76 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave and
from the slave to the master. In practice, often only one of these data flows carries
meaningful data.
7.18.4.1 Features
• Maximum SSP speed in full-duplex mode of 25 Mbit/s; for transmit only 50 Mbit/s
(master) and 17 Mbit/s (slave).
• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
• Synchronous serial communication
• Master or slave operation
• 8-frame FIFOs for both transmit and receive
• 4-bit to 16-bit frame
• DMA transfers supported by GPDMA
7.18.5 I2C-bus interface
Remark: The LPC4350/30/20/10 contain two I2C-bus interfaces.
The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line
(SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (for example an LCD driver) or a transmitter
with the capability to both receive and send information (such as memory). Transmitters
and/or receivers can operate in either master or slave mode, depending on whether the
chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and
can be controlled by more than one bus master connected to it.
7.18.5.1 Features
• I
2C0 is a standard I2C-compliant bus interface with open-drain pins. I2C0 also
supports Fast mode plus with bit rates up to 1 Mbit/s.
• I
2C1 uses standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus).
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus can be used for test and diagnostic purposes.
• All I2C-bus controllers support multiple address recognition and a bus monitor mode.
7.18.6 I2S interface
Remark: The LPC4350/30/20/10 contain two I2S-bus interfaces.LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 77 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
The I2S-bus provides a standard communication interface for digital audio applications.
The I
2S-bus specification defines a 3-wire serial bus using one data line, one clock line,
and one word select signal. The basic I2S-bus connection has one master, which is
always the master, and one slave. The I2S-bus interface provides a separate transmit and
receive channel, each of which can operate as either a master or a slave.
7.18.6.1 Features
• The I2S interface has separate input/output channels, each of which can operate in
master or slave mode.
• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
• Mono and stereo audio data supported.
• The sampling frequency can range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48,
96, 192) kHz.
• Support for an audio master clock.
• Configurable word select period in master mode (separately for I2S-bus input and
output).
• Two 8-word FIFO data buffers are provided, one for transmit and one for receive.
• Generates interrupt requests when buffer levels cross a programmable boundary.
• Two DMA requests controlled by programmable buffer levels. The DMA requests are
connected to the GPDMA block.
• Controls include reset, stop and mute options separately for I2S-bus input and I2S-bus
output.
7.18.7 C_CAN
Remark: The LPC4350/30/20/10 contain two C_CAN controllers.
Controller Area Network (CAN) is the definition of a high performance communication
protocol for serial data communication. The C_CAN controller is designed to provide a full
implementation of the CAN protocol according to the CAN Specification Version 2.0B. The
C_CAN controller can create powerful local networks with low-cost multiplex wiring by
supporting distributed real-time control with a high level of reliability.
7.18.7.1 Features
• Conforms to protocol version 2.0 parts A and B.
• Supports bit rate of up to 1 Mbit/s.
• Supports 32 Message Objects.
• Each Message Object has its own identifier mask.
• Provides programmable FIFO mode (concatenation of Message Objects).
• Provides maskable interrupts.
• Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN
applications.
• Provides programmable loop-back mode for self-test operation.LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 78 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
7.19 Counter/timers and motor control
7.19.1 General purpose 32-bit timers/external event counters
The LPC4350/30/20/10 include four 32-bit timer/counters. The timer/counter is designed
to count cycles of the system derived clock or an externally-supplied clock. It can
optionally generate interrupts, generate timed DMA requests, or perform other actions at
specified timer values, based on four match registers. Each timer/counter also includes
two capture inputs to trap the timer value when an input signal transitions, optionally
generating an interrupt.
7.19.1.1 Features
• A 32-bit timer/counter with a programmable 32-bit prescaler.
• Counter or timer operation.
• Two 32-bit capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event can also generate an interrupt.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
• Up to two match registers can be used to generate timed DMA requests.
7.19.2 Motor control PWM
The motor control PWM is a specialized PWM supporting 3-phase motors and other
combinations. Feedback inputs are provided to automatically sense rotor position and use
that information to ramp speed up or down. An abort input causes the PWM to release all
motor drive outputs immediately . At the same time, the motor control PWM is highly
configurable for other generalized timing, counting, capture, and compare applications.
7.19.3 Quadrature Encoder Interface (QEI)
A quadrature encoder, also known as a 2-channel incremental encoder, converts angular
displacement into two pulse signals. By monitoring both the number of pulses and the
relative phase of the two signals, the user code can track the position, direction of rotation,
and velocity. In addition, a third channel, or index signal, can be used to reset the position
counter. The quadrature encoder interface decodes the digital pulses from a quadrature
encoder wheel to integrate position over time and determine direction of rotation. In
addition, the QEI can capture the velocity of the encoder wheel.
7.19.3.1 Features
• Tracks encoder position.LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 79 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
• Increments/decrements depending on direction.
• Programmable for 2 or 4 position counting.
• Velocity capture using built-in timer.
• Velocity compare function with “less than” interrupt.
• Uses 32-bit registers for position and velocity.
• Three position-compare registers with interrupts.
• Index counter for revolution counting.
• Index compare register with interrupts.
• Can combine index and position interrupts to produce an interrupt for whole and
partial revolution displacement.
• Digital filter with programmable delays for encoder input signals.
• Can accept decoded signal inputs (clk and direction).
7.19.4 Repetitive Interrupt (RI) timer
The repetitive interrupt timer provides a free-running 32-bit counter which is compared to
a selectable value, generating an interrupt when a match occurs. Any bits of the
timer/compare function can be masked such that they do not contribute to the match
detection. The repetitive interrupt timer can be used to create an interrupt that repeats at
predetermined intervals.
7.19.4.1 Features
• 32-bit counter. Counter can be free-running or be reset by a generated interrupt.
• 32-bit compare value.
• 32-bit compare mask. An interrupt is generated when the counter value equals the
compare value, after masking. This mechanism allows for combinations not possible
with a simple compare.
7.19.5 Windowed WatchDog Timer (WWDT)
The purpose of the watchdog is to reset the controller if software fails to periodically
service it within a programmable time window.
7.19.5.1 Features
• Internally resets chip if not periodically reloaded during the programmable time-out
period.
• Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
• Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
• Incorrect feed sequence causes reset or interrupt if enabled.
• Flag to indicate watchdog reset.
• Programmable 24-bit timer with internal prescaler.LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 80 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
• Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in
multiples of Tcy(WDCLK) 4.
• The Watchdog Clock (WDCLK) uses the IRC as the clock source.
7.20 Analog peripherals
7.20.1 Analog-to-Digital Converter (ADC0/1)
7.20.1.1 Features
• 10-bit successive approximation analog to digital converter.
• Input multiplexing among 8 pins.
• Power-down mode.
• Measurement range 0 to VDDA.
• Sampling frequency up to 400 kSamples/s.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition on ADCTRIG0 or ADCTRIG1 pins, combined timer
outputs 8 or 15, or the PWM output MCOA2.
• Individual result registers for each A/D channel to reduce interrupt overhead.
• DMA support.
7.20.2 Digital-to-Analog Converter (DAC)
7.20.2.1 Features
• 10-bit resolution
• Monotonic by design (resistor string architecture)
• Controllable conversion speed
• Low-power consumption
7.21 Peripherals in the RTC power domain
7.21.1 RTC
The Real-Time Clock (RTC) is a set of counters for measuring time when system power is
on, and optionally when it is off. It uses little power when the CPU does not access its
registers, especially in the reduced power modes. A separate 32 kHz oscillator clocks the
RTC. The oscillator produces a 1 Hz internal time reference and is powered by its own
power supply pin, VBAT.
7.21.1.1 Features
• Measures the passage of time to maintain a calendar and clock. Provides seconds,
minutes, hours, day of month, month, year, day of week, and day of year.
• Ultra-low power design to support battery powered systems. Uses power from the
CPU power supply when it is present.
• Dedicated battery power supply pin.
• RTC power supply is isolated from the rest of the chip.LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 81 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
• Calibration counter allows adjustment to better than 1 sec/day with 1 sec resolution.
• Periodic interrupts can be generated from increments of any field of the time registers.
• Alarm interrupt can be generated for a specific date/time.
7.21.2 Alarm timer
The alarm timer is a 16-bit timer and counts down at 1 kHz from a preset value generating
alarms in intervals of up to 1 min. The counter triggers a status bit when it reaches 0x00
and asserts an interrupt if enabled.
The alarm timer is part of the RTC power domain and can be battery powered.
7.22 System control
7.22.1 Configuration registers (CREG)
The following settings are controlled in the configuration register block:
• BOD trip settings
• Oscillator output
• DMA-to-peripheral muxing
• Ethernet mode
• Memory mapping
• Timer/USART inputs
• Enabling the USB controllers
In addition, the CREG block contains the part identification and part configuration
information.
7.22.2 System Control Unit (SCU)
The system control unit determines the function and electrical mode of the digital pins. By
default function 0 is selected for all pins with pull-up enabled. For pins that support a
digital and analog function, the ADC function select registers in the SCU enable the
analog function.
A separate set of analog I/Os for the ADCs and the DAC as well as most USB pins are
located on separate pads and are not controlled through the SCU.
In addition, the clock delay register for the SDRAM EMC_CLK pins and the registers that
select the pin interrupts are located in the SCU.
7.22.3 Clock Generation Unit (CGU)
The Clock Generator Unit (CGU) generates several base clocks. The base clocks can be
unrelated in frequency and phase and can have different clock sources within the CGU.
One CGU base clock is routed to the CLKOUT pins. The base clock that generates the
CPU clock is referred to as CCLK.
Multiple branch clocks are derived from each base clock. The branch clocks offer flexible
control for power-management purposes. All branch clocks are outputs of one of two
Clock Control Units (CCUs) and can be controlled independently. Branch clocks derived
from the same base clock are synchronous in frequency and phase. LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 82 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
7.22.4 Internal RC oscillator (IRC)
The IRC is used as the clock source for the WWDT and/or as the clock that drives the
PLLs and the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed to 1.5 %
accuracy over the entire voltage and temperature range.
Upon power-up or any chip reset, the LPC4350/30/20/10 use the IRC as the clock source.
The boot loader then configures the PLL1 to provide a 96 MHz clock for the core and the
PLL0USB or PLL0AUDIO as needed if an external boot source is selected.
7.22.5 PLL0USB (for USB0)
PLL0 is a dedicated PLL for the USB0 High-speed controller.
PLL0 accepts an input clock frequency from an external oscillator in the range of 14 kHz
to 25 MHz. The input frequency is multiplied up to a high frequency with a Current
Controlled Oscillator (CCO). The CCO operates in the range of 4.3 MHz to 550 MHz.
7.22.6 PLL0AUDIO (for audio)
The audio PLL PLL0AUDIO is a general-purpose PLL with a small step size. This PLL
accepts an input clock frequency derived from an external oscillator or internal IRC. The
input frequency is multiplied up to a high frequency with a Current Controlled Oscillator
(CCO). A sigma-delta converter modulates the PLL divider ratios to obtain the desired
output frequency. The output frequency can be set as a multiple of the sampling frequency
fs to 32fs, 64fs, 128 fs, 256 fs, 384 fs, 512 fs and the sampling frequency fs can
range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48, 96,192) kHz. Many other
frequencies are possible as well using the integrated fractional divider.
7.22.7 System PLL1
The PLL1 accepts an input clock frequency from an external oscillator in the range of
1 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current
Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO
operates in the range of 156 MHz to 320 MHz. This range is possible through an
additional divider in the loop to keep the CCO within its frequency range while the PLL is
providing the desired output frequency. The output divider can be set to divide by 2, 4, 8,
or 16 to produce the output clock. Since the minimum output divider value is 2, it is
insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed
following a chip reset. After reset, software can enable the PLL. The program must
configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a
clock source. The PLL settling time is 100 s.
7.22.8 Reset Generation Unit (RGU)
The RGU allows generation of independent reset signals for individual blocks and
peripherals on the LPC4350/30/20/10.
7.22.9 Power control
The LPC4350/30/20/10 feature several independent power domains to control power to
the core and the peripherals (see Figure 9). The RTC and its associated peripherals (the
alarm timer, the CREG block, the OTP controller, the back-up registers, and the event
router) are located in the RTC power-domain. The main regulator or a battery supply can
power the RTC. A power selector switch ensures that the RTC block is always powered
on.LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 83 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
7.22.10 Power Management Controller (PMC)
The PMC controls the power to the cores, peripherals, and memories.
The LPC4350/30/20/10 support the following power modes in order from highest to lowest
power consumption:
1. Active mode
2. Sleep mode
3. Power-down modes:
a. Deep-sleep mode
b. Power-down mode
c. Deep power-down mode
Fig 9. Power domains
REAL-TIME CLOCK
BACKUP REGISTERS
RESET/WAKE-UP
CONTROL
REGULATOR
32 kHz
OSCILLATOR
ALWAYS-ON/RTC POWER DOMAIN
MAIN POWER DOMAIN
RTCX1
VBAT
VDDREG
RTCX2
VDDIO
VSS
to memories,
peripherals,
oscillators,
PLLs
to cores
to I/O pads
ADC
DAC
OTP
ADC POWER DOMAIN
OTP POWER DOMAIN
USB0 POWER DOMAIN
VDDA
VSSA
VPP
USB0 USB0_VDDA3V_DRIVER
USB0_VDDA3V3
LPC43xx
ULTRA LOW-POWER
REGULATOR
ALARM
RESET
WAKEUP0/1/2/3
to RTC
domain
peripherals
002aag378
to RTC I/O
pads (Vps)LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 84 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
Active mode and sleep mode apply to the state of the core. In a dual-core system, either
core can be in active or sleep mode independently of the other core.
If the core is in Active mode, it is fully operational and can access peripherals and
memories as configured by software. If the core is in Sleep mode, it receives no clocks,
but peripherals and memories remain running.
Either core can enter sleep mode from active mode independently of the other core and
while the other core remains in active mode or is in sleep mode.
Power-down modes apply to the entire system. In the Power-down modes, both cores and
all peripherals except for peripherals in the always-on power domain are shut down.
Memories can remain powered for retaining memory contents as defined by the individual
power-down mode.
Either core in active mode can put the part into one of the three power down modes if the
core is enabled to do so. If both cores are enabled for putting the system into power-down,
then the system enters power-down only once both cores have received a WFI or WFE
instruction.
Wake-up from sleep mode is caused by an interrupt or event in the core’s NVIC. The
interrupt is captured in the NVIC and an event is captured in the Event router. Both cores
can wake up from sleep mode independently of each other.
Wake-up from the Power-down modes, Deep-sleep, Power-down, and Deep power-down,
is caused by an event on the WAKEUP pins or an event from the RTC or alarm timer.
When waking up from Deep power-down mode, the part resets and attempts to boot.
7.23 Serial Wire Debug/JTAG
Debug and trace functions are integrated into the ARM Cortex-M4. Serial wire debug and
trace functions are supported in addition to a standard JTAG debug and parallel trace
functions. The ARM Cortex-M4 is configured to support up to eight breakpoints and four
watch points.
Remark: Serial Wire Debug is supported for the ARM Cortex-M4 only,
The ARM Cortex-M0 coprocessor supports JTAG debug. A standard ARM
Cortex-compliant debugger can debug the ARM Cortex-M4 and the ARM Cortex-M0
cores separately or both cores simultaneously.
Remark: In order to debug the ARM Cortex-M0, release the M0 reset by software in the
RGU block.LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 85 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
Fig 10. Dual-core debug configuration
002aah448
TCK ARM Cortex-M0 ARM Cortex-M4
DBGEN = HIGH
TMS
TRST
TDI TDO TDO
TDO
DBGEN
RESET RESET = HIGH
TCK
TMS
TRST
TDI
TCK
TMS
TRST
TDI
JTAG ID = 0x0BA0 1477 JTAG ID = 0x4BA0 0477
LPC43xxLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 86 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
8. Limiting values
[1] The following applies to the limiting values:
a) This product includes circuitry designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
[2] Including voltage on outputs in 3-state mode.
[3] The peak current is limited to 25 times the corresponding maximum current.
[4] Dependent on package type.
[5] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol Parameter Conditions Min Max Unit
VDD(REG)(3V3) regulator supply voltage
(3.3 V)
on pin VDDREG 0.5 3.6 V
VDD(IO) input/output supply
voltage
on pin VDDIO 0.5 3.6 V
VDDA(3V3) analog supply voltage
(3.3 V)
on pin VDDA 0.5 3.6 V
VBAT battery supply voltage on pin VBAT 0.5 3.6 V
Vprog(pf) polyfuse programming
voltage
on pin VPP 0.5 3.6 V
VI input voltage only valid when VDD(IO) 2.2 V
5 V tolerant I/O pins
[2]
0.5 5.5 V
ADC/DAC pins and digital I/O
pins configured for an analog
function
0.5 VDDA(3V3) V
USB0 pins USB0_DP;
USB0_DM;USB0_VBUS
0.3 5.25 V
USB0 pins USB0_ID;
USB0_RREF
0.3 3.6 V
USB1 pins USB1_DP and
USB1_DM
0.3 5.25 V
IDD supply current per supply pin [3] - 100 mA
ISS ground current per ground pin [3] - 100 mA
Ilatch I/O latch-up current (0.5VDD(IO)) < VI < (1.5VDD(IO));
Tj
< 125 C
- 100 mA
Tstg storage temperature [4] 65 +150 C
Ptot(pack) total power dissipation
(per package)
based on package heat transfer,
not device power consumption
- 1.5 W
VESD electrostatic discharge
voltage
human body model; all pins [5] 2000 +2000 VLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 87 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
9. Thermal characteristics
The average chip junction temperature, Tj (C), can be calculated using the following
equation:
(1)
• Tamb = ambient temperature (C),
• Rth(j-a) = the package junction-to-ambient thermal resistance (C/W)
• PD = sum of internal and I/O power dissipation
The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of
the I/O pins is often small and many times can be negligible. However it can be significant
in some applications.
Tj Tamb PD Rth j a – +=
Table 7. Thermal characteristics
VDD = 2.2 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified;
Symbol Parameter Conditions Min Typ Max Unit
Tj(max) maximum junction
temperature
- - 125 C
Table 8. Thermal resistance (LQFP packages)
Symbol Parameter Conditions Thermal resistance
in C/W ±15 %
LQFP144
Rth(j-a) thermal resistance from
junction to ambient
JEDEC (4.5 in 4 in); still air 38
Single-layer (4.5 in 3 in);
still air
50
Rth(j-c) thermal resistance from
junction to case
11
Table 9. Thermal resistance value (BGA packages)
Symbol Parameter Conditions Thermal resistance in C/W ±15 %
LBGA256 TFBGA180 TFBGA100
Rth(j-a) thermal resistance from
junction to ambient
JEDEC (4.5 in 4 in); still air 29 38 46
8-layer (4.5 in 3 in); still air 24 30 37
Rth(j-c) thermal resistance from
junction to case
14 11 11LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 88 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
10. Static characteristics
Table 10. Static characteristics
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max Unit
Supply pins
VDD(IO) input/output supply
voltage
2.2 - 3.6 V
VDD(REG)(3V3) regulator supply voltage
(3.3 V)
[2] 2.2 - 3.6 V
VDDA(3V3) analog supply voltage
(3.3 V)
on pin VDDA 2.2 - 3.6 V
on pins
USB0_VDDA3V3_
DRIVER and
USB0_VDDA3V3
3.0 3.3 3.6 V
VBAT battery supply voltage [2] 2.2 - 3.6 V
Vprog(pf) polyfuse programming
voltage
on pin VPP (for OTP) [3] 2.7 - 3.6 V
Iprog(pf) polyfuse programming
current
on pin VPP; OTP
programming time
1.6 ms
- - 30 mA
IDD(REG)(3V3) regulator supply current
(3.3 V)
Active mode; M0-core in
reset; code
while(1){}
executed from RAM; all
peripherals disabled;
PLL1 enabled
CCLK = 12 MHz [4] - 6.6- mA
CCLK = 60 MHz [4] 25.3 - mA
CCLK = 120 MHz [4] - 48.4- mA
CCLK = 180 MHz [4] - 72.0- mA
CCLK = 204 MHz [4] - 81.5- mA
IDD(REG)(3V3) regulator supply current
(3.3 V)
after WFE/WFI instruction
executed from RAM; all
peripherals disabled; M0
core in reset
sleep mode [4][5] - 5.0- mA
deep-sleep mode [4] - 30 - A
power-down mode [4] - 15 - A
deep power-down
mode
[4][6] - 0.03 - A
deep power-down
mode; VBAT floating
[4]-- 2 - A
IBAT battery supply current active mode; VBAT = 3.2 V;
VDD(REG)(3V3) = 3.6 V.
[7] - 0 -nALPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 89 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
IBAT battery supply current VDD(REG)(3V3) = 3.3 V;
VBAT = 3.6 V
deep-sleep mode
[8]
- 2- A
power-down mode [8] - 2- A
deep power-down
mode
[8]
- 2- A
IDD(IO) I/O supply current deep sleep mode - - 1 - A
power-down mode - - 1 - A
deep power-down mode [9] - 0.05 - A
IDDA Analog supply current on pin VDDA;
deep sleep mode
[11] - 0.4 -
A
power-down mode [11] - 0.4 - A
deep power-down
mode
[11] - 0.007 -
A
RESET,RTC_ALARM, WAKEUPn pins
VIH HIGH-level input
voltage
[10] 0.8 (Vps
0.35)
- 5.5 V
VIL LOW-level input voltage [10] 0 - 0.3 (Vps
0.1)
V
Vhys hysteresis voltage [10] 0.05 (Vps
0.35)
--V
Vo output voltage [10] - Vps - 0.2 - V
Standard I/O pins - normal drive strength
CI input capacitance - - 2 pF
ILL LOW-level leakage
current
VI = 0 V; on-chip pull-up
resistor disabled
- 3 - nA
ILH HIGH-level leakage
current
VI = VDD(IO); on-chip
pull-down resistor
disabled
- 3 - nA
VI = 5 V --20 nA
IOZ OFF-state output
current
VO = 0 V to VDD(IO);
on-chip pull-up/down
resistors disabled;
absolute value
- 3- nA
VI input voltage pin configured to provide
a digital function;
VDD(IO) 2.2 V
0 - 5.5 V
VDD(IO) = 0 V 0 - 3.6 V
VO output voltage output active 0 - VDD(IO) V
VIH HIGH-level input
voltage
0.7
VDD(IO)
- 5.5 V
VIL LOW-level input voltage 0 - 0.3
VDD(IO)
V
Vhys hysteresis voltage 0.1
VDD(IO)
--V
Table 10. Static characteristics …continued
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max UnitLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 90 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
VOH HIGH-level output
voltage
IOH = 6 mA VDD(IO)
0.4
--V
VOL LOW-level output
voltage
IOL = 6 mA --0.4 V
IOH HIGH-level output
current
VOH = VDD(IO) 0.4 V 6 - - mA
IOL LOW-level output
current
VOL = 0.4 V 6- - mA
IOHS HIGH-level short-circuit
output current
drive HIGH; connected to
ground
[12] --86.5 mA
IOLS LOW-level short-circuit
output current
drive LOW; connected to
VDD(IO)
[12] --76.5 mA
Ipd pull-down current VI = 5 V [14][15]
[16]
- 93 - A
Ipu pull-up current VI =0V [14][15]
[16]
- 62 - A
VDD(IO) < VI 5 V - 10 - A
Rs series resistance on I/O pins with analog
function; analog function
enabled
200
I/O pins - high drive strength
CI input capacitance - - 5.2 pF
ILL LOW-level leakage
current
VI = 0 V; on-chip pull-up
resistor disabled
- 3 - nA
ILH HIGH-level leakage
current
VI = VDD(IO); on-chip
pull-down resistor
disabled
- 3 - nA
VI = 5 V --20 nA
IOZ OFF-state output
current
VO = 0 V to VDD(IO);
on-chip pull-up/down
resistors disabled;
absolute value
- 3 - nA
VI input voltage pin configured to provide
a digital function;
VDD(IO) 2.2 V 0 - 5.5 V
VDD(IO) = 0 V 0 - 3.6 V
VO output voltage output active 0 - VDD(IO) V
VIH HIGH-level input
voltage
0.7
VDD(IO)
- 5.5 V
VIL LOW-level input voltage 0 - 0.3
VDD(IO)
V
Vhys hysteresis voltage 0.1
VDD(IO)
--V
Ipd pull-down current VI = VDD(IO) [14][15]
[16]
- 62 - A
Table 10. Static characteristics …continued
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max UnitLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 91 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
Ipu pull-up current VI =0V [14][15]
[16]
- 62 - A
VDD(IO) < VI 5 V - 10 - A
I/O pins - high drive strength: standard drive mode
IOH HIGH-level output
current
VOH = VDD(IO) 0.4 V 4 - - mA
IOL LOW-level output
current
VOL = 0.4 V 4- - mA
IOHS HIGH-level short-circuit
output current
drive HIGH; connected to
ground
[12] --32 mA
IOLS LOW-level short-circuit
output current
drive LOW; connected to
VDD(IO)
[12] --32 mA
I/O pins - high drive strength: medium drive mode
IOH HIGH-level output
current
VOH = VDD(IO) 0.4 V 8 - - mA
IOL LOW-level output
current
VOL = 0.4 V 8- - mA
IOHS HIGH-level short-circuit
output current
drive HIGH; connected to
ground
[12] --65 mA
IOLS LOW-level short-circuit
output current
drive LOW; connected to
VDD(IO)
[12] --63 mA
I/O pins - high drive strength: high drive mode
IOH HIGH-level output
current
VOH = VDD(IO) 0.4 V 14 - - mA
IOL LOW-level output
current
VOL = 0.4 V 14- - mA
IOHS HIGH-level short-circuit
output current
drive HIGH; connected to
ground
[12] --113 mA
IOLS LOW-level short-circuit
output current
drive LOW; connected to
VDD(IO)
[12] --110 mA
I/O pins - high drive strength: ultra-high drive mode
IOH HIGH-level output
current
VOH = VDD(IO) 0.4 V 20 - - mA
IOL LOW-level output
current
VOL = 0.4 V 20- - mA
IOHS HIGH-level short-circuit
output current
drive HIGH; connected to
ground
[12] --165 mA
IOLS LOW-level short-circuit
output current
drive LOW; connected to
VDD(IO)
[12] --156 mA
I/O pins - high-speed
CI input capacitance - - 2 pF
ILL LOW-level leakage
current
VI = 0 V; on-chip pull-up
resistor disabled
- 3 - nA
Table 10. Static characteristics …continued
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max UnitLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 92 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
ILH HIGH-level leakage
current
VI = VDD(IO); on-chip
pull-down resistor
disabled
- 3 - nA
VI = 5 V --20 nA
IOZ OFF-state output
current
VO = 0 V to VDD(IO);
on-chip pull-up/down
resistors disabled;
absolute value
- 3 - nA
VI input voltage pin configured to provide
a digital function;
VDD(IO) 2.2 V 0 - 5.5 V
VDD(IO) = 0 V 0 - 3.6 V
VO output voltage output active 0 - VDD(IO) V
VIH HIGH-level input
voltage
0.7
VDD(IO)
- 5.5 V
VIL LOW-level input voltage 0 - 0.3
VDD(IO)
V
Vhys hysteresis voltage 0.1
VDD(IO)
--V
VOH HIGH-level output
voltage
IOH = 8 mA VDD(IO)
0.4
--V
VOL LOW-level output
voltage
IOL = 8 mA --0.4 V
IOH HIGH-level output
current
VOH = VDD(IO) 0.4 V 8 - - mA
IOL LOW-level output
current
VOL = 0.4 V 8- - mA
IOHS HIGH-level short-circuit
output current
drive HIGH; connected to
ground
[12] --86 mA
IOLS LOW-level short-circuit
output current
drive LOW; connected to
VDD(IO)
[12] --76 mA
Ipd pull-down current VI = VDD(IO) [14][15]
[16]
- 62 - A
Ipu pull-up current VI =0V [14][15]
[16]
- 62 - A
VDD(IO) < VI 5V - 0 - A
Open-drain I2C0-bus pins
VIH HIGH-level input
voltage
0.7
VDD(IO)
--V
VIL LOW-level input voltage 0 0.14 0.3
VDD(IO)
V
Vhys hysteresis voltage 0.1
VDD(IO)
--V
VOL LOW-level output
voltage
IOLS = 3 mA --0.4 V
Table 10. Static characteristics …continued
Tamb = 40 C to +85 C, unless otherwise specified.
Symbol Parameter Conditions Min Typ[1] Max UnitLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 93 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
[2] Dynamic characteristics for peripherals are provided for VDD(REG)(3V) 2.7 V.
ILI input leakage current VI = VDD(IO) [13] - 4.5 - A
VI = 5 V --10 A
Oscillator pins
Vi(XTAL1) input voltage on pin
XTAL1
0.5 - 1.2 V
Vo(XTAL2) output voltage on pin
XTAL2
0.5 - 1.2 V
Cio input/output
capacitance
[17] --0.8 pF
USB0 pins[18]
VI input voltage on pins USB0_DP;
USB0_DM; USB0_VBUS
VDD(IO) 2.2 V 0 - 5.25 V
VDD(IO) = 0 V 0 - 3.6 V
Rpd pull-down resistance on pin USB0_VBUS 48 64 80 k
VIC common-mode input
voltage
high-speed mode 50 200 500 mV
full-speed/low-speed
mode
800 - 2500 mV
chirp mode 50 - 600 mV
Vi(dif) differential input voltage 100 400 1100 mV
USB1 pins (USB1_DP/USB1_DM)[18]
IOZ OFF-state output
current
0V 0
EMC_DYCSn,
EMC_RAS,
EMC_CAS,
EMC_WE,
EMC_CKEOUTn,
EMC_A[22:0],
EMC_DQMOUTn
th(Q)
th(Q) - td
th(D) tsu(D)
th(D) tsu(D)
EMC_D[31:0]
write
EMC_D[31:0]
read; delay = 0
EMC_D[31:0]
read; delay > 0
th(x) - td td(xV) - td
td(QV) - td
td(QV)
th(x) td(xV)
EMC_CLKn delay td; programmable CLKn_DELAYLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 123 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
11.15 USB interface
[1] Characterized but not implemented as production test. Guaranteed by design.
Table 28. Dynamic characteristics: USB0 and USB1 pins (full-speed)
CL = 50 pF; Rpu = 1.5 k on D+ to VDD(IO); 3.0 V VDD(IO) 3.6 V.
Symbol Parameter Conditions Min Typ Max Unit
tr rise time 10 % to 90 % 8.5 - 13.8 ns
tf fall time 10 % to 90 % 7.7 - 13.7 ns
tFRFM differential rise and fall time
matching
tr / tf - -109 %
VCRS output signal crossover voltage 1.3 - 2.0 V
tFEOPT source SE0 interval of EOP see Figure 36 160 - 175 ns
tFDEOP source jitter for differential transition
to SE0 transition
see Figure 36 2 - +5 ns
tJR1 receiver jitter to next transition 18.5 - +18.5 ns
tJR2 receiver jitter for paired transitions 10 % to 90 % 9 - +9 ns
tEOPR1 EOP width at receiver must reject as
EOP; see
Figure 36
[1] 40 - - ns
tEOPR2 EOP width at receiver must accept as
EOP; see
Figure 36
[1] 82 - - ns
Fig 36. Differential data-to-EOP transition skew and EOP width
002aab561
TPERIOD
differential
data lines
crossover point
source EOP width: tFEOPT
receiver EOP width: tEOPR1, tEOPR2
crossover point
extended
differential data to
SE0/EOP skew
n × TPERIOD + tFDEOPLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 124 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
[1] Characterized but not implemented as production test.
[2] Total average power consumption.
[3] The driver is active only 20 % of the time.
11.16 Ethernet
Remark: The timing characteristics of the ENET_MDC and ENET_MDIO signals comply
with the IEEE standard 802.3.
Table 29. Static characteristics: USB0 PHY pins[1]
Symbol Parameter Conditions Min Typ Max Unit
High-speed mode
Pcons power consumption [2] - 68 - mW
IDDA(3V3) analog supply current (3.3 V) on pin USB0_VDDA3V3_DRIVER;
total supply current
[3]
- 18 - mA
during transmit - 31 - mA
during receive - 14 - mA
with driver tri-stated - 14 - mA
IDDD digital supply current - 7 - mA
Full-speed/low-speed mode
Pcons power consumption [2] - 15 - mW
IDDA(3V3) analog supply current (3.3 V) on pin USB0_VDDA3V3_DRIVER;
total supply current - 3.5 - mA
during transmit - 5 - mA
during receive - 3 - mA
with driver tri-stated - 3 - mA
IDDD digital supply current - 3 - mA
Suspend mode
IDDA(3V3) analog supply current (3.3 V) - 24 - A
with driver tri-stated - 24 - A
with OTG functionality enabled - 3 - mA
IDDD digital supply current - 30 - A
VBUS detector outputs
Vth threshold voltage for VBUS valid 4.4 - - V
for session end 0.2 - 0.8 V
for A valid 0.8 - 2 V
for B valid 2 - 4 V
Vhys hysteresis voltage for session end - 150 10 mV
A valid - 200 10 mV
B valid - 200 10 mVLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 125 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
[1] Output drivers can drive a load 25 pF accommodating over 12 inch of PCB trace and the input
capacitance of the receiving device.
[2] Timing values are given from the point at which the clock signal waveform crosses 1.4 V to the valid input or
output level.
Table 30. Dynamic characteristics: Ethernet
Tamb = 40 C to 85 C; 2.2 V VDD(REG)(3V3) 3.6 V; 2.7 V VDD(IO) 3.6 V. Values guaranteed by
design.
Symbol Parameter Conditions Min Max Unit
RMII mode
fclk clock frequency for ENET_RX_CLK [1] - 50 MHz
clk clock duty cycle [1] 50 50 %
tsu set-up time for ENET_TXDn, ENET_TX_EN,
ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
[1][2] 4 - ns
th hold time for ENET_TXDn, ENET_TX_EN,
ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
[1][2] 2 - ns
MII mode
fclk clock frequency for ENET_TX_CLK [1] - 25 MHz
clk clock duty cycle [1] 50 50 %
tsu set-up time for ENET_TXDn, ENET_TX_EN,
ENET_TX_ER
[1][2] 4 - ns
th hold time for ENET_TXDn, ENET_TX_EN,
ENET_TX_ER
[1][2] 2 - ns
fclk clock frequency for ENET_RX_CLK [1] - 25 MHz
clk clock duty cycle [1] 50 50 %
tsu set-up time for ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
[1][2] 4 - ns
th hold time for ENET_RXDn, ENET_RX_ER,
ENET_RX_DV
[1][2] 2 - ns
Fig 37. Ethernet timing
002aag210
th tsu
ENET_RX_CLK
ENET_TX_CLK
ENET_RXD[n]
ENET_RX_DV
ENET_RX_ER
ENET_TXD[n]
ENET_TX_EN
ENET_TX_ERLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 126 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
11.17 SD/MMC
11.18 LCD
Table 31. Dynamic characteristics: SD/MMC
Tamb = 40 C to 85 C, 2.2 V VDD(REG)(3V3) 3.6 V; 2.7 V VDD(IO) 3.6 V, CL = 20 pF. Simulated
values. SAMPLE_DELAY = 0x8, DRV_DELAY = 0xF in the SDDELAY register (see the LPC43xx
user manual UM10430).
Symbol Parameter Conditions Min Max Unit
fclk clock frequency on pin SD_CLK; data transfer mode 52 MHz
tr rise time 0.5 2 ns
tf fall time 0.5 2 ns
tsu(D) data input set-up time on pins SD_DATn as inputs 6 - ns
on pins SD_CMD as inputs 7 - ns
th(D) data input hold time on pins SD_DATn as inputs -1 - ns
on pins SD_CMD as inputs 1 ns
td(QV) data output valid delay
time
on pins SD_DATn as outputs - 17 ns
on pins SD_CMD as outputs - 18 ns
th(Q) data output hold time on pins SD_DATn as outputs 4 - ns
on pins SD_CMD as outputs 4 - ns
Fig 38. SD/MMC timing
002aag204
SD_CLK
SD_DATn (O)
SD_DATn (I)
td(QV)
th(D) tsu(D)
Tcy(clk)
th(Q)
SD_CMD (O)
SD_CMD (I)
Table 32. Dynamic characteristics: LCD
Tamb = 40 C to +85 C; 2.2 V VDD(REG)(3V3) 3.6 V; 2.7 V VDD(IO) 3.6 V; CL = 20 pF.
Simulated values.
Symbol Parameter Conditions Min Typ Max Unit
fclk clock frequency on pin LCD_DCLK - 50 - MHz
td(QV) data output valid
delay time
- 17 ns
th(Q) data output hold time 8.5 - nsLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 127 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
11.19 SPIFI
Table 33. Dynamic characteristics: SPIFI
Tamb = 40 C to 85 C; 2.2 V VDD(REG)(3V3) 3.6 V; 2.7 V VDD(IO) 3.6 V. CL = 10 pF. Simulated
values.
Symbol Parameter Min Max Unit
Tcy(clk) clock cycle time 9.6 - ns
tDS data set-up time 3.4 - ns
tDH data hold time 0 - ns
tv(Q) data output valid time - 3.2 ns
th(Q) data output hold time 0.2 - ns
Fig 39. SPIFI timing (Mode 0)
SPIFI_SCK
SPIFI data out
SPIFI data in
Tcy(clk)
tDS tDH
tv(Q)
DATA VALID DATA VALID
th(Q)
DATA VALID DATA VALID
002aah409LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 128 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
12. ADC/DAC electrical characteristics
[1] The ADC is monotonic, there are no missing codes.
[2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 40.
[3] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 40.
[4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 40.
[5] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 40.
[6] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve. See Figure 40.
[7] Tamb = 25 C.
[8] Input resistance Ri
depends on the sampling frequency fs: Ri
= 2 k + 1 / (fs Cia).
Table 34. ADC characteristics
VDDA(3V3) over specified ranges; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VIA analog input voltage 0 - VDDA(3V3) V
Cia analog input
capacitance
- - 2 pF
ED differential linearity error 2.7 V VDDA(3V3) 3.6 V [1][2] - 0.8 - LSB
2.2 V VDDA(3V3) < 2.7 V - 1.0 - LSB
EL(adj) integral non-linearity 2.7 V VDDA(3V3) 3.6 V [3] - 0.8 - LSB
2.2 V VDDA(3V3) < 2.7 V - 1.5 - LSB
EO offset error 2.7 V VDDA(3V3) 3.6 V [4] - 0.15 - LSB
2.2 V VDDA(3V3) < 2.7 V - 0.15 - LSB
EG gain error 2.7 V VDDA(3V3) 3.6 V [5] - 0.3 - %
2.2 V VDDA(3V3) < 2.7 V - 0.35 - %
ET absolute error 2.7 V VDDA(3V3) 3.6 V [6] - 3 - LSB
2.2 V VDDA(3V3) < 2.7 V - 4 - LSB
Rvsi voltage source interface
resistance
see Figure 41 - - 1/(7 fclk(ADC)
Cia)
k
Ri input resistance [7][8] - - 1.2 M
fclk(ADC) ADC clock frequency - - 4.5 MHz
fs sampling frequency 10-bit resolution; 11 clock
cycles
- - 400 kSamples/s
2-bit resolution; 3 clock
cycles
1.5 MSamples/sLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 129 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 40. 10-bit ADC characteristics
002aaf959
1023
1022
1021
1020
1019
(2)
(1)
123456 7 1018 1019 1020 1021 1022 1023 1024
7
6
5
4
3
2
1
0
1018
(5)
(4)
(3)
1 LSB
(ideal)
code
out
VDDA(3V3) − VSSA
1024
offset
error
EO
gain
error
EG
offset error
EO
VIA (LSBideal)
1 LSB =LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 130 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
[1] In the DAC CR register, bit BIAS = 0 (see the LPC43xx user manual).
[2] Settling time is calculated within 1/2 LSB of the final value.
Rs 1/((7 fclk(ADC) Cia) 2 k
Fig 41. ADC interface to pins
LPC43xx
ADC0_n/ADC1_n
Cia = 2 pF
Rvsi
Rs
VSS
VEXT
002aag704
ADC
COMPARATOR
2 kΩ (analog pin)
2.2 kΩ (multiplexed pin)
Table 35. DAC characteristics
VDDA(3V3) over specified ranges; Tamb = 40 C to +85 C; unless otherwise specified
Symbol Parameter Conditions Min Typ Max Unit
ED differential linearity error 2.7 V VDDA(3V3) 3.6 V [1] - 0.8 - LSB
2.2 V VDDA(3V3) < 2.7 V - 1.0 - LSB
EL(adj) integral non-linearity code = 0 to 975
2.7 V VDDA(3V3) 3.6 V
[1] - 1.0 - LSB
2.2 V VDDA(3V3) < 2.7 V - 1.5 - LSB
EO offset error 2.7 V VDDA(3V3) 3.6 V [1] - 0.8 - LSB
2.2 V VDDA(3V3) < 2.7 V - 1.0 - LSB
EG gain error 2.7 V VDDA(3V3) 3.6 V [1] - 0.3 - %
2.2 V VDDA(3V3) < 2.7 V - 1.0 - %
CL load capacitance - - 200 pF
RL load resistance 1 - - k
ts settling time [2] 0.4 LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 131 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
13. Application information
13.1 LCD panel signal usage
Table 36. LCD panel connections for STN single panel mode
External pin 4-bit mono STN single panel 8-bit mono STN single panel Color STN single panel
LPC43xx pin
used
LCD function LPC43xx pin
used
LCD function LPC43xx pin
used
LCD function
LCD_VD[23:8] - - - - - -
LCD_VD7 - - P8_4 UD[7] P8_4 UD[7]
LCD_VD6 - - P8_5 UD[6] P8_5 UD[6]
LCD_VD5 - - P8_6 UD[5] P8_6 UD[5]
LCD_VD4 - - P8_7 UD[4] P8_7 UD[4]
LCD_VD3 P4_2 UD[3] P4_2 UD[3] P4_2 UD[3]
LCD_VD2 P4_3 UD[2] P4_3 UD[2] P4_3 UD[2]
LCD_VD1 P4_4 UD[1] P4_4 UD[1] P4_4 UD[1]
LCD_VD0 P4_1 UD[0] P4_1 UD[0] P4_1 UD[0]
LCD_LP P7_6 LCDLP P7_6 LCDLP P7_6 LCDLP
LCD_ENAB/
LCDM
P4_6 LCDENAB/
LCDM
P4_6 LCDENAB/
LCDM
P4_6 LCDENAB/
LCDM
LCD_FP P4_5 LCDFP P4_5 LCDFP P4_5 LCDFP
LCD_DCLK P4_7 LCDDCLK P4_7 LCDDCLK P4_7 LCDDCLK
LCD_LE P7_0 LCDLE P7_0 LCDLE P7_0 LCDLE
LCD_PWR P7_7 CDPWR P7_7 LCDPWR P7_7 LCDPWR
GP_CLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN
Table 37. LCD panel connections for STN dual panel mode
External pin 4-bit mono STN dual panel 8-bit mono STN dual panel Color STN dual panel
LPC43xx pin
used
LCD function LPC43xx pin
used
LCD function LPC43xx pin
used
LCD function
LCD_VD[23:16] - - - - - -
LCD_VD15 - - PB_4 LD[7] PB_4 LD[7]
LCD_VD14 - - PB_5 LD[6] PB_5 LD[6]
LCD_VD13 - - PB_6 LD[5] PB_6 LD[5]
LCD_VD12 - - P8_3 LD[4] P8_3 LD[4]
LCD_VD11 P4_9 LD[3] P4_9 LD[3] P4_9 LD[3]
LCD_VD10 P4_10 LD[2] P4_10 LD[2] P4_10 LD[2]
LCD_VD9 P4_8 LD[1] P4_8 LD[1] P4_8 LD[1]
LCD_VD8 P7_5 LD[0] P7_5 LD[0] P7_5 LD[0]
LCD_VD7 - - UD[7] P8_4 UD[7]
LCD_VD6 - - P8_5 UD[6] P8_5 UD[6]
LCD_VD5 - - P8_6 UD[5] P8_6 UD[5]
LCD_VD4 - - P8_7 UD[4] P8_7 UD[4]
LCD_VD3 P4_2 UD[3] P4_2 UD[3] P4_2 UD[3]LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 132 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
LCD_VD2 P4_3 UD[2] P4_3 UD[2] P4_3 UD[2]
LCD_VD1 P4_4 UD[1] P4_4 UD[1] P4_4 UD[1]
LCD_VD0 P4_1 UD[0] P4_1 UD[0] P4_1 UD[0]
LCD_LP P7_6 LCDLP P7_6 LCDLP P7_6 LCDLP
LCD_ENAB/
LCDM
P4_6 LCDENAB/
LCDM
P4_6 LCDENAB/
LCDM
P4_6 LCDENAB/
LCDM
LCD_FP P4_5 LCDFP P4_5 LCDFP P4_5 LCDFP
LCD_DCLK P4_7 LCDDCLK P4_7 LCDDCLK P4_7 LCDDCLK
LCD_LE P7_0 LCDLE P7_0 LCDLE P7_0 LCDLE
LCD_PWR P7_7 LCDPWR P7_7 LCDPWR P7_7 LCDPWR
GP_CLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN
Table 37. LCD panel connections for STN dual panel mode …continued
External pin 4-bit mono STN dual panel 8-bit mono STN dual panel Color STN dual panel
LPC43xx pin
used
LCD function LPC43xx pin
used
LCD function LPC43xx pin
used
LCD function
Table 38. LCD panel connections for TFT panels
External
pin
TFT 12 bit (4:4:4
mode)
TFT 16 bit (5:6:5 mode) TFT 16 bit (1:5:5:5 mode) TFT 24 bit
LPC43xx
pin used
LCD
function
LPC43xx
pin used
LCD
function
LPC43xx pin
used
LCD
function
LPC43xx
pin used
LCD
function
LCD_VD23 PB_0 BLUE3 PB_0 BLUE4 PB_0 BLUE4 PB_0 BLUE7
LCD_VD22 PB_1 BLUE2 PB_1 BLUE3 PB_1 BLUE3 PB_1 BLUE6
LCD_VD21 PB_2 BLUE1 PB_2 BLUE2 PB_2 BLUE2 PB_2 BLUE5
LCD_VD20 PB_3 BLUE0 PB_3 BLUE1 PB_3 BLUE1 PB_3 BLUE4
LCD_VD19 - - P7_1 BLUE0 P7_1 BLUE0 P7_1 BLUE3
LCD_VD18 - - - - P7_2 intensity P7_2 BLUE2
LCD_VD17 - - - - - - P7_3 BLUE1
LCD_VD16 - - - - - - P7_4 BLUE0
LCD_VD15 PB_4 GREEN3 PB_4 GREEN5 PB_4 GREEN4 PB_4 GREEN7
LCD_VD14 PB_5 GREEN2 PB_5 GREEN4 PB_5 GREEN3 PB_5 GREEN6
LCD_VD13 PB_6 GREEN1 PB_6 GREEN3 PB_6 GREEN2 PB_6 GREEN5
LCD_VD12 P8_3 GREEN0 P8_3 GREEN2 P8_3 GREEN1 P8_3 GREEN4
LCD_VD11 - - P4_9 GREEN1 P4_9 GREEN0 P4_9 GREEN3
LCD_VD10 - - P4_10 GREEN0 P4_10 intensity P4_10 GREEN2
LCD_VD9 - - - - - - P4_8 GREEN1
LCD_VD8 - - - - - - P7_5 GREEN0
LCD_VD7 P8_4 RED3 P8_4 RED4 P8_4 RED4 P8_4 RED7
LCD_VD6 P8_5 RED2 P8_5 RED3 P8_5 RED3 P8_5 RED6
LCD_VD5 P8_6 RED1 P8_6 RED2 P8_6 RED2 P8_6 RED5
LCD_VD4 P8_7 RED0 P8_7 RED1 P8_7 RED1 P8_7 RED4
LCD_VD3 - - P4_2 RED0 P4_2 RED0 P4_2 RED3
LCD_VD2 - - - - P4_3 intensity P4_3 RED2
LCD_VD1 - - - - - - P4_4 RED1LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 133 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
13.2 Crystal oscillator
The crystal oscillator is controlled by the XTAL_OSC_CTRL register in the CGU (see
LPC43xx user manual).
The crystal oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the PLL.
The oscillator can operate in one of two modes: slave mode and oscillation mode.
• In slave mode, couple the input clock signal with a capacitor of 100 pF (CC in
Figure 42), with an amplitude of at least 200 mV (RMS). The XTAL2 pin in this
configuration can be left unconnected.
• External components and models used in oscillation mode are shown in Figure 43,
and in Table 39 and Table 40. Since the feedback resistance is integrated on chip,
only a crystal and the capacitances CX1 and CX2 need to be connected externally in
case of fundamental mode oscillation L, CL and RS represent the fundamental
frequency). The capacitance CP in Figure 43 represents the parallel package
capacitance and must not be larger than 7 pF. Parameters FC, CL, RS and CP are
supplied by the crystal manufacturer.
LCD_VD0 - - - - - - P4_1 RED0
LCD_LP P7_6 LCDLP P7_6 LCDLP P7_6 LCDLP P7_6 LCDLP
LCD_ENAB
/LCDM
P4_6 LCDENAB/
LCDM
P4_6 LCDENAB/
LCDM
P4_6 LCDENAB/
LCDM
P4_6 LCDENAB/
LCDM
LCD_FP P4_5 LCDFP P4_5 LCDFP P4_5 LCDFP P4_5 LCDFP
LCD_DCLK P4_7 LCDDCLK P4_7 LCDDCLK P4_7 LCDDCLK P4_7 LCDDCLK
LCD_LE P7_0 LCDLE P7_0 LCDLE P7_0 LCDLE P7_0 LCDLE
LCD_PWR P7_7 LCDPWR P7_7 LCDPWR P7_7 LCDPWR P7_7 LCDPWR
GP_CLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN
Table 38. LCD panel connections for TFT panels …continued
External
pin
TFT 12 bit (4:4:4
mode)
TFT 16 bit (5:6:5 mode) TFT 16 bit (1:5:5:5 mode) TFT 24 bit
LPC43xx
pin used
LCD
function
LPC43xx
pin used
LCD
function
LPC43xx pin
used
LCD
function
LPC43xx
pin used
LCD
function
Table 39. Recommended values for CX1/X2 in oscillation mode (crystal and external
components parameters) low frequency mode
Fundamental oscillation
frequency
Maximum crystal series
resistance RS
External load capacitors
CX1, CX2
2 MHz < 200 33 pF, 33 pF
< 200 39 pF, 39 pF
< 200 56 pF, 56 pF
4 MHz < 200 18 pF, 18 pF
< 200 39 pF, 39 pF
< 200 56 pF, 56 pF
8 MHz < 200 18 pF, 18 pF
< 200 39 pF, 39 pFLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 134 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
12 MHz < 160 18 pF, 18 pF
< 160 39 pF, 39 pF
16 MHz < 120 18 pF, 18 pF
< 80 33 pF, 33 pF
20 MHz <100 18 pF, 18 pF
< 80 33 pF, 33 pF
Table 40. Recommended values for CX1/X2 in oscillation mode (crystal and external
components parameters) high frequency mode
Fundamental oscillation
frequency
Maximum crystal series
resistance RS
External load capacitors CX1,
Cx2
15 MHz < 80 18 pF, 18 pF
20 MHz < 80 39 pF, 39 pF
< 100 47 pF, 47 pF
Fig 42. Slave mode operation of the on-chip oscillator
Fig 43. Oscillator modes with external crystal model used for CX1/CX2 evaluation
Table 39. Recommended values for CX1/X2 in oscillation mode (crystal and external
components parameters) low frequency mode …continued
Fundamental oscillation
frequency
Maximum crystal series
resistance RS
External load capacitors
CX1, CX2
LPC43xx
XTAL1
Ci
100 pF
Cg
002aag379
002aag380
LPC43xx
XTAL1 XTAL2
CX1 CX2
XTAL
= CL CP
RS
LLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 135 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
13.3 RTC oscillator
In the RTC oscillator circuit, only the crystal (XTAL) and the capacitances CRTCX1 and
CRTCX2 need to be connected externally. Typical capacitance values for CRTCX1 and
CRTCX2 are CRTCX1/2 = 20 (typical) 4 pF.
An external clock can be connected to RTCX1 if RTCX2 is left open. The recommended
amplitude of the clock signal is Vi(RMS) = 100 mV to 200 mV with a coupling capacitance of
5 pF to 10 pF. Vi(RMS) must be lower than 450 mV. See Figure 42 for a similar slave-mode
set-up that uses the crystal oscillator.
13.4 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines
Connect the crystal on the PCB as close as possible to the oscillator input and output pins
of the chip. Take care that the load capacitors Cx1, Cx2, and Cx3 in case of third overtone
crystal usage have a common ground plane. Also connect the external components to the
ground plain. To keep the noise coupled in via the PCB as small as possible, make loops
and parasitics as small as possible. Choose smaller values of Cx1 and Cx2 if parasitics
increase in the PCB layout.
Ensure that no high-speed or high-drive signals are near the RTCX1/2 signals.
13.5 Standard I/O pin configuration
Figure 45 shows the possible pin modes for standard I/O pins with analog input function:
• Digital output driver enabled/disabled
• Digital input: Pull-up enabled/disabled
• Digital input: Pull-down enabled/disabled
• Digital input: Repeater mode enabled/disabled
• Digital input: Input buffer enabled/disabled
• Analog input
The default configuration for standard I/O pins is input buffer disabled and pull-up
enabled. The weak MOS devices provide a drive capability equivalent to pull-up and
pull-down resistors.
Fig 44. RTC 32 kHz oscillator circuit
002aah148
LPC43xx
RTCX1 RTCX2
CRTCX1 CRTCX2
XTALLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 136 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
13.6 Reset pin configuration
13.7 Suggested USB interface solutions
The USB device can be connected to the USB as self-powered device (see Figure 47) or
bus-powered device (see Figure 48).
The glitch filter rejects pulses of typical 12 ns width.
Fig 45. Standard I/O pin configuration with analog input
slew rate bit EHS
pull-up enable bit EPUN
pull-down enable bit EPD
glitch
filter
analog I/O
ESD
ESD
PIN
VDDIO
VSSIO
input buffer enable bit EZI
filter select bit ZIF
data input to core
data output from core
enable output driver
002aah028
Fig 46. Reset pin configuration
VSS
reset
002aag702
Vps
Vps
Vps
Rpu ESD
ESD
20 ns RC
GLITCH FILTER PINLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 137 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
On the LPC4350/30/20/10, USBn_VBUS pins are 5 V tolerant only when VDDIO is
applied and at operating voltage level. Therefore, if the USBn_VBUS function is
connected to the USB connector and the device is self-powered, the USBn_VBUS pins
must be protected for situations when VDDIO = 0 V.
If VDDIO is always at operating level while VBUS = 5 V, the USBn_VBUS pin can be
connected directly to the VBUS pin on the USB connector.
For systems where VDDIO can be 0 V and VBUS is directly applied to the USBn_VBUS
pins, precautions must be taken to reduce the voltage to below 3.6 V, which is the
maximum allowable voltage on the USBn_VBUS pins in this case.
One method is to use a voltage divider to connect the USBn_VBUS pins to VBUS on the
USB connector. The voltage divider ratio should be such that the USB_VBUS pin will be
greater than 0.7VDDIO to indicate a logic HIGH while below the 3.6 V allowable maximum
voltage.
For the following operating conditions
VBUSmax = 5.25 V
VDDIO = 3.6 V,
the voltage divider should provide a reduction of 3.6 V/5.25 V or ~0.686 V.
For bus-powered devices, a regulator powered by USB can provide 3.3 V to VDDIO
whenever bus power is present and ensure that power to the USBn_VBUS pins is always
present when the 5 V VBUS signal is applied. See Figure 48.
Remark: Applying 5 V to the USBn_VBUS pins for a short time while the regulator ramps
up might compromise the long-term reliability of the part but does not affect its function.
Fig 47. USB interface on a self-powered device where USBn_VBUS = 5 V
LPC43xx
VDDIO
USB-B
connector
USBn_VBUS VBUS
USB
R2
R3
aaa-013458LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 138 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
Remark: If the VBUS function of the USB1 interface is not connected, configure the pin
function for GPIO using the function control bits in the SYSCON block.
Remark: In OTG mode, it is important to be able to detect the VBUS level and to charge
and discharge VBUS. This requires adding active devices that disconnect the link when
VDDIO is not present.
Fig 48. USB interface on a bus-powered device
Fig 49. USB interface for USB operating in OTG mode
REGULATOR
USBn_VBUS VBUS
LPC43xx
VDDIO
USB-B
connector USB
aaa-013459
USBn_VBUS VBUS
LPC43xx
VDDIO
USB-B
connector USB
aaa-013460
R1
R2
R3
T2
T1LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 139 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
14. Package outline
Fig 50. Package outline LBGA256 package
OUTLINE REFERENCES
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC
MO-192
JEITA
SOT740-2 - - - - - -
SOT740-2
05-06-16
05-08-04
UNIT A
max
mm 1.55 0.45
0.35
1.1
0.9
0.55
0.45
17.2
16.8
17.2
16.8
A1
DIMENSIONS (mm are the original dimensions)
LBGA256: plastic low profile ball grid array package; 256 balls; body 17 x 17 x 1 mm
X
A2 b D E e
1
e1
15
e2
15
v
0.25
w
0.1
y
0.12
y1
0.35
1/2 e
1/2 e
A
A2
A1
detail X
D
E
B A
ball A1
index area
y1 C y
C
A B
A
B
C
D
E
F
H
K
G
J
L
M
N
P
R
T
2 4 6 8 10 12 14 16 1 3 5 7 9 11 13 15 ball A1
index area
e
e
e1
b
e2
C
C
∅ v M
∅ w M
0 5 10 mm
scaleLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 140 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
Fig 51. Package outline of the TFBGA180 package
OUTLINE REFERENCES
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT570-3
SOT570-3
08-07-09
10-04-15
UNIT
mm
max
nom
min
1.20
1.06
0.95
0.40
0.35
0.30
0.50
0.45
0.40
12.1
12.0
11.9
12.1
12.0
11.9
0.8 10.4 0.15 0.12
A
DIMENSIONS (mm are the original dimensions)
TFBGA180: thin fine-pitch ball grid array package; 180 balls
0 5 10 mm
scale
A1 A2
0.80
0.71
0.65
b D E e e1
10.4
e2 v w
0.05
y y1
0.1
ball A1
index area
D B A
E
C
y1 C y
X
A
B
C
D
E
F
H
K
G
L
J
M
N
P
2 4 6 8 10 12 14 1 3 5 7 9 11 13
b
e2
e1
e
e
1/2 e
1/2 e ∅ v M AC B
∅ w M C
ball A1
index area
detail X
A
A2
A1LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 141 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
Fig 52. Package outline of the TFBGA100 package
OUTLINE REFERENCES
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT926-1 - - - - - - - - -
SOT926-1
05-12-09
05-12-22
UNIT A
max
mm 1.2 0.4
0.3
0.8
0.65
0.5
0.4
9.1
8.9
9.1
8.9
A1
DIMENSIONS (mm are the original dimensions)
TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm
A2 b D E e2
7.2
e
0.8
e1
7.2
v
0.15
w
0.05
y
0.08
y1
0.1
0 2.5 5 mm
scale
b
e2
e1
e
e
1/2 e
1/2 e
∅ v M AC B
∅ w M C
ball A1
index area
A
B
C
D
E
F
H
K
G
J
13579 2 4 6 8 10
ball A1
index area
B A
E
D
C
y1 C y
X
detail X
A
A1
A2LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 142 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
Fig 53. Package outline for the LQFP144 package
UNIT A1 A2 A3 bp c E(1) e HE L Lp ywv Z θ
OUTLINE REFERENCES
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05
1.45
1.35 0.25 0.27
0.17
0.20
0.09
20.1
19.9 0.5 22.15
21.85
1.4
1.1
7
0
o
1 0.080.2 0.08 o
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.75
0.45
SOT486-1 136E23 MS-026 00-03-14
03-02-20
D(1) (1)(1)
20.1
19.9
HD
22.15
21.85
Z E
1.4
1.1
D
0 5 10 mm
scale
e bp
θ
E
A1
A
Lp
detail X
L
(A ) 3
B
c
bp
EH A2
DH v M B
D
ZD
A
ZE
e
v M A
X
y
w M
w M
A
max.
1.6
LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1
108
109
pin 1 index
73
72
37
1
144
36LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 143 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
15. Soldering
Fig 54. Reflow soldering of the LBGA256 package
DIMENSIONS in mm
P SL SP SR Hx Hy
Hx
Hy
SOT740-2
solder land plus solder paste
occupied area
Footprint information for reflow soldering of LBGA256 package
solder land
solder paste deposit
solder resist
P
P
SL
SP
SR
Generic footprint pattern
Refer to the package outline drawing for actual layout
detail X
see detail X
sot740-2_fr 1.00 0.450 0.450 0.600 17.500 17.500LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 144 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
Fig 55. Reflow soldering of the TFBGA180 package
DIMENSIONS in mm
P SL SP SR Hx Hy
Hx
Hy
SOT570-3
solder land plus solder paste
occupied area
Footprint information for reflow soldering of TFBGA180 package
solder land
solder paste deposit
solder resist
P
P
SL
SP
SR
Generic footprint pattern
Refer to the package outline drawing for actual layout
detail X
see detail X
sot570-3_fr 0.80 0.400 0.400 0.550 12.575 12.575LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 145 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
Fig 56. Reflow soldering of the LQFP144 package
SOT486-1
DIMENSIONS in mm
occupied area
Footprint information for reflow soldering of LQFP144 package
Ax
Bx
Gx
Hy Gy
Hx
AyBy
P2 P1
D2 (8×) D1
(0.125)
P1 P2 Ax Ay Bx By C D1 D2 Gx Gy Hx Hy
sot486-1_fr
solder land
C
Generic footprint pattern
Refer to the package outline drawing for actual layout
0.500 0.560 0.280 23.300 23.300 20.300 20.300 1.500 0.400 20.500 20.500 23.550 23.550LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 146 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
Fig 57. Reflow soldering of the TFBGA100 package
DIMENSIONS in mm
P SL SP SR Hx Hy
Hx
Hy
SOT926-1
solder land plus solder paste
occupied area
Footprint information for reflow soldering of TFBGA100 package
solder land
solder paste deposit
solder resist
P
P
SL
SP
SR
Generic footprint pattern
Refer to the package outline drawing for actual layout
detail X
see detail X
sot926-1_fr 0.80 0.330 0.400 0.480 9.400 9.400LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 147 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
16. Abbreviations
Table 41. Abbreviations
Acronym Description
ADC Analog-to-Digital Converter
AHB Advanced High-performance Bus
APB Advanced Peripheral Bus
API Application Programming Interface
BOD BrownOut Detection
CAN Controller Area Network
CMAC Cipher-based Message Authentication Code
CSMA/CD Carrier Sense Multiple Access with Collision Detection
DAC Digital-to-Analog Converter
DC-DC Direct Current-to-Direct Current
DMA Direct Memory Access
GPIO General-Purpose Input/Output
IRC Internal RC
IrDA Infrared Data Association
JTAG Joint Test Action Group
LCD Liquid Crystal Display
LSB Least Significant Bit
MAC Media Access Control
MCU MicroController Unit
MIIM Media Independent Interface Management
n.c. not connected
OHCI Open Host Controller Interface
OTG On-The-Go
PHY Physical Layer
PLL Phase-Locked Loop
PMC Power Mode Control
PWM Pulse Width Modulator
RIT Repetitive Interrupt Timer
RMII Reduced Media Independent Interface
SDRAM Synchronous Dynamic Random Access Memory
SIMD Single Instruction Multiple Data
SPI Serial Peripheral Interface
SSI Serial Synchronous Interface
SSP Synchronous Serial Port
UART Universal Asynchronous Receiver/Transmitter
ULPI UTMI+ Low Pin Interface
USART Universal Synchronous Asynchronous Receiver/Transmitter
USB Universal Serial Bus
UTMI USB2.0 Transceiver Macrocell InterfaceLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 148 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
17. References
[1] LPC43xx User manual UM10503:
http://www.nxp.com/documents/user_manual/UM10503.pdf
[2] LPC43X0 Errata sheet:
http://www.nxp.com/documents/errata_sheet/ES_LPC43XX.pdfLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 149 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
18. Revision history
Table 42. Revision history
Document ID Release date Data sheet status Change notice Supersedes
LPC4350_30_20_10 v.4.2 20140818 Product data sheet LPC4350_30_20_10 v.4.1
Modifications: • Parameter CI corrected for high-drive pins (changed from 2 pF to 5.2 pF). See
Table 10.
• Table 18 “Dynamic characteristic: I/O pins[1]” added.
• IRC accuracy changed from 1 % to 1.5 % over the full temperature range. See Table
16 “Dynamic characteristic: IRC oscillator”.
• Description of internal pull-up resistor configuration added for RESET, WAKEUPn,
and ALARM pins.See Table 3.
• Description of DEBUG pin updated.
• Input range for PLL1 corrected: 1 MHz to 25 MHz. See Section 7.22.7 “System PLL1”.
• Section 13.7 “Suggested USB interface solutions” added.
• SSP master mode timing diagram updated with SSEL timing parameters. See Figure
30 “SSP master mode timing (SPI mode)”.
• Parameters tlead, tlag, and td added in Table 22 “Dynamic characteristics: SSP pins in
SPI mode”.
• Reset state of the RTC alarm pin RTC_ALARM added. See Table 3.
• SRAM location for parts LPC4320 corrected in Figure 7.
• IEEE standard 802.3 compliance added to Section 11.16. Covers Ethernet dynamic
characteristics of ENET_MDIO and ENET_MDC signals.\
• Signal polarity of EMC_CKEOUT and EMC_DQMOUT corrected. Both signals are
active HIGH.
• SPIFI output timing parameters in Table 33 corrected to apply to Mode 0:
– tv(Q) changed to 3.2 ns.
– th(Q) changed to 0.2 ns,
• Parameter tCSLWEL with condition PB = 1 corrected: (WAITWEN + 1) Tcy(clk) added.
See Table 25 “Dynamic characteristics: Static asynchronous external memory
interface”.
• Parameter tCSLBLSL with condition PB = 0 corrected: (WAITWEN + 1) Tcy(clk) added.
See Table 25 “Dynamic characteristics: Static asynchronous external memory
interface”.
LPC4350_30_20_10 v.4.1 20131211 Product data sheet - LPC4350_30_20_10 v.4
Modifications: • Description of RESET pin updated in Table 3.
• Layout of local SRAM at address 0x1008 0000 clarified in Figure 7
“LPC4350/30/20/10 Memory mapping (overview)”.
• Maximum value for Vi(RMS) added in Section 13.3 “RTC oscillator”.
• VO for RTC_ALARM pin added in Table 10.
• RTC_ALARM and WAKEUPn pins added to Table 10.
• Table note 9 added in Table 10.
• Timing parameters in Table 31 “Dynamic characteristics: SD/MMC” corrected.
• Band gap characteristics removed.
• OTP memory size available for general purpose use corrected.
• Part LPC4350FBD208 removed.
LPC4350_30_20_10 v.4 20130326 Product data sheet - LPC4350_30_20_10 v.3.7LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 150 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
• Parameter ILH (High-level leakage current) for condition VI = 5 V changed to 20 nA
(max). See Table 10.
• Parameter VDDA(3V3) added for pins USB0_VDDA3V3_DRIVER and
USB0_VDDA3V3 in Table 10.
• SPI timing data added. See Table 22.
• SGPIO timing data added. See Table 23.
• SPI and SGPIO peripheral power consumption added in Table 11.
• Data sheet status changed to Product data sheet.
• Corrected max voltage on pins USB0_DP, USB0_DM, USB0_VBUS, USB1_DP, and
USB1_DM in Table 6 and Table 10 to be consistent with USB specifications.
LPC4350_30_20_10 v.3.7 20130131 Preliminary data sheet - LPC4350_30_20_10 v.3.6
Modifications: • SGPIO and SPI location corrected in Figure 1.
• SGPIO-to-DMA connection corrected in Figure 7.
• Power consumption in active mode corrected. See parameter IDD(REG)(3V3) in Table 10
and graphs Figure 12, Figure 13, and Figure 14.
• Parameter name IDD(ADC) changed to IDDA in Table 10.
• Figure 21 “Band gap voltage for different temperatures and process conditions” and
Table 13 “Band gap characteristics” corrected.
• Added note to limit data in Table 24 “Dynamic characteristics: Static asynchronous
external memory interface” to single memory accesses.
• Value of parameter IDD(REG)(3V3) in deep power-down increased to 0.03 μA in
Table 10.
• Value of parameter IDD(IO) in deep power-down increased to 0.05 μA in Table 10.
LPC4350_30_20_10 v.3.6 20121119 Preliminary data sheet - LPC4350_30_20_10 v.3.5
Modifications: • Table 13 “Band gap characteristics” added.
• Power consumption for M0 core added in Table 11 “Peripheral power consumption”.
• Section 7.22.10 “Power Management Controller (PMC)” added.
• Table 10, added Table note 2: “Dynamic characteristics for peripherals are provided
for VDD(REG)(3V3) 2.7 V.”
• Description of ADC pins on digital/analog input pins changed. Each input to the ADC
is connected to ADC0 and ADC1. See Table 3.
• Use of C_CAN peripheral restricted in Section 2.
• ADC channels limited to a total of 8 channels shared between ADC0 and ADC1.
• Minimum value for parameter VIL changed to 0 V in Table 10 “Static characteristics”.
LPC4350_30_20_10 v.3.5 20121011 Preliminary data sheet - LPC4350_30_20_10 v.3.4
Table 42. Revision history …continued
Document ID Release date Data sheet status Change notice SupersedesLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 151 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
Modifications: • Temperature range for simulated timing characteristics corrected to Tamb = 40 C to
+85 C in Section 11 “Dynamic characteristics”.
• SPIFI timing added. See Section 11.15.
• SPIFI maximum data rate changed to 52 MB per second.
• Editorial updates.
• Figure 25 and Figure 26 updated for full temperature range.
• Section 7.23 “Serial Wire Debug/JTAG” updated.
• The following changes were made on the TFBGA180 pinout in Table 3:
– P1_13 moved from ball D6 to L8.
– P7_5 moved from ball C7 to A7.
– PF_4 moved from ball L8 to D6.
– RESET moved from ball B7 to C7.
– RTCX2 moved from ball A7 to B7.
– Ball G10 changed from VSS to VDDIO.
LPC4350_30_20_10 v.3.4 20120904 Preliminary data sheet - LPC4350_30_20_10 v.3.3
Modifications: • SSP0 boot pin functions corrected in Table 5 and Table 4. Pin P3_3 = SSP0_SCK, pin
P3_6 = SSP0_SSEL, pin P3_7 = SSP0_MISO, pin P3_8 = SSP0_MOSI.
• Minimum value for all supply voltages changed to -0.5 V in Table 6.
LPC4350_30_20_10 v.3.3 20120821 Preliminary data sheet - LPC4350_30_20_10 v.3.2
Modifications: • Parameter twake updated in Table 13 for wake-up from deep power-down mode and
reset.
• Dynamic characteristics of the SD/MMC controller updated in Table 28.
• Dynamic characteristics of the LCD controller updated in Table 29.
• Dynamic characteristics of the SSP controller updated in Table 21.
• Minimum value of VI for conditions “USB0 pins USB0_DP; USB0_DM;
USB0_VBUS”,“USB0 pins USB0_ID; USB0_RREF”, and “USB1 pins USB1_DP and
USB1_DM” changed to 0.3 V in Table 6.
• Parameters IIL and IIH renamed to ILL and ILH in Table 10.
• AES removed. AES is available on parts LPC43Sxx only.
• Pin configuration diagrams corrected for LQFP packages (Figure 5 and Figure 6).
• Figure 10 updated.
• All power consumption data updated in Table 10 and Section 10.1 “Power
consumption”.
• BOD levels updated in Table 12.
• SWD debug option removed for Cortex-M0 core.
LPC4350_30_20_10 v.3.2 20120604 Preliminary data sheet - LPC4350_30_20_10 v.3.1
LPC4350_30_20_10 v.3.1 20120105 Objective data sheet - LPC4350_30_20_10 v.3
LPC4350_30_20_10 v.3 20111205 Objective data sheet - LPC4350_30_20_10 v.2.1
LPC4350_30_20_10 v.2.1 20110923 Objective data sheet - LPC4350_30_20_10 v.2
LPC4350_30_20_10 v.2 20110714 Objective data sheet - LPC4350_30_20_10 v.1
LPC4350_30_20_10 v.1 20101029 Objective data sheet - -
Table 42. Revision history …continued
Document ID Release date Data sheet status Change notice SupersedesLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 152 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
19. Legal information
19.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
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Limited warranty and liability — Information in this document is believed to
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In no event shall NXP Semiconductors be liable for any indirect, incidental,
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Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
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Suitability for use — NXP Semiconductors products are not designed,
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Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
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NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification. LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 153 of 155
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
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Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
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whenever customer uses the product for automotive applications beyond
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own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I
2C-bus — logo is a trademark of NXP Semiconductors N.V.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.comLPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 154 of 155
continued >>
NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
21. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 5
4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 5
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 7
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7
7 Functional description . . . . . . . . . . . . . . . . . . 61
7.1 Architectural overview . . . . . . . . . . . . . . . . . . 61
7.2 ARM Cortex-M4 processor . . . . . . . . . . . . . . . 61
7.3 ARM Cortex-M0 co-processor . . . . . . . . . . . . 61
7.4 Interprocessor communication . . . . . . . . . . . . 61
7.5 AHB multilayer matrix . . . . . . . . . . . . . . . . . . . 62
7.6 Nested Vectored Interrupt Controller (NVIC) . 62
7.6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.6.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 63
7.7 System Tick timer (SysTick) . . . . . . . . . . . . . . 63
7.8 Event router . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.9 Global Input Multiplexer Array (GIMA) . . . . . . 63
7.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.10 On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 64
7.11 In-System Programming (ISP) . . . . . . . . . . . . 64
7.12 Boot ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.13 Memory mapping . . . . . . . . . . . . . . . . . . . . . . 65
7.14 One-Time Programmable (OTP) memory . . . 68
7.15 General-Purpose I/O (GPIO) . . . . . . . . . . . . . 68
7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.16 Configurable digital peripherals . . . . . . . . . . . 68
7.16.1 State Configurable Timer (SCTimer/PWM)
subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.16.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
7.16.2 Serial GPIO (SGPIO) . . . . . . . . . . . . . . . . . . . 69
7.16.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
7.17 AHB peripherals . . . . . . . . . . . . . . . . . . . . . . . 70
7.17.1 General-Purpose DMA (GPDMA). . . . . . . . . . 70
7.17.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7.17.2 SPI Flash Interface (SPIFI). . . . . . . . . . . . . . . 70
7.17.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.17.3 SD/MMC card interface . . . . . . . . . . . . . . . . . 71
7.17.4 External Memory Controller (EMC). . . . . . . . . 71
7.17.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.17.5 High-speed USB Host/Device/OTG interface
(USB0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.17.5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.17.6 High-speed USB Host/Device interface with
ULPI (USB1) . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.17.6.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.17.7 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . 73
7.17.7.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.17.8 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.17.8.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.18 Digital serial peripherals. . . . . . . . . . . . . . . . . 74
7.18.1 UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.18.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.18.2 USART0/2/3. . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.18.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.18.3 SPI serial I/O controller . . . . . . . . . . . . . . . . . 75
7.18.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.18.4 SSP serial I/O controller. . . . . . . . . . . . . . . . . 75
7.18.4.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.18.5 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . 76
7.18.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.18.6 I2S interface . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.18.6.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7.18.7 C_CAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7.18.7.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7.19 Counter/timers and motor control . . . . . . . . . 78
7.19.1 General purpose 32-bit timers/external event
counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7.19.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7.19.2 Motor control PWM . . . . . . . . . . . . . . . . . . . . 78
7.19.3 Quadrature Encoder Interface (QEI) . . . . . . . 78
7.19.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
7.19.4 Repetitive Interrupt (RI) timer. . . . . . . . . . . . . 79
7.19.4.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.19.5 Windowed WatchDog Timer (WWDT) . . . . . . 79
7.19.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.20 Analog peripherals . . . . . . . . . . . . . . . . . . . . . 80
7.20.1 Analog-to-Digital Converter (ADC0/1) . . . . . . 80
7.20.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.20.2 Digital-to-Analog Converter (DAC). . . . . . . . . 80
7.20.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.21 Peripherals in the RTC power domain . . . . . . 80
7.21.1 RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.21.1.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.21.2 Alarm timer. . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.22 System control . . . . . . . . . . . . . . . . . . . . . . . . 81
7.22.1 Configuration registers (CREG) . . . . . . . . . . . 81
7.22.2 System Control Unit (SCU) . . . . . . . . . . . . . . 81
7.22.3 Clock Generation Unit (CGU) . . . . . . . . . . . . 81
7.22.4 Internal RC oscillator (IRC) . . . . . . . . . . . . . . 82
7.22.5 PLL0USB (for USB0) . . . . . . . . . . . . . . . . . . . 82NXP Semiconductors LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
© NXP Semiconductors N.V. 2014. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 18 August 2014
Document identifier: LPC4350_30_20_10
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
7.22.6 PLL0AUDIO (for audio) . . . . . . . . . . . . . . . . . 82
7.22.7 System PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.22.8 Reset Generation Unit (RGU). . . . . . . . . . . . . 82
7.22.9 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.22.10 Power Management Controller (PMC) . . . . . . 83
7.23 Serial Wire Debug/JTAG. . . . . . . . . . . . . . . . . 84
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 86
9 Thermal characteristics . . . . . . . . . . . . . . . . . 87
10 Static characteristics. . . . . . . . . . . . . . . . . . . . 88
10.1 Power consumption . . . . . . . . . . . . . . . . . . . . 95
10.2 Peripheral power consumption . . . . . . . . . . . . 99
10.3 BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
10.4 Electrical pin characteristics . . . . . . . . . . . . . 102
11 Dynamic characteristics . . . . . . . . . . . . . . . . 106
11.1 Wake-up times . . . . . . . . . . . . . . . . . . . . . . . 106
11.2 External clock for oscillator in slave mode . . 106
11.3 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 107
11.4 IRC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 107
11.5 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 107
11.6 I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
11.7 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.8 I2S-bus interface. . . . . . . . . . . . . . . . . . . . . . 110
11.9 USART interface. . . . . . . . . . . . . . . . . . . . . . 111
11.10 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . 112
11.11 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . 114
11.12 SSP/SPI timing diagrams . . . . . . . . . . . . . . . 115
11.13 SGPIO timing . . . . . . . . . . . . . . . . . . . . . . . . 116
11.14 External memory interface . . . . . . . . . . . . . . 118
11.15 USB interface . . . . . . . . . . . . . . . . . . . . . . . 123
11.16 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
11.17 SD/MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
11.18 LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
11.19 SPIFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
12 ADC/DAC electrical characteristics . . . . . . . 128
13 Application information. . . . . . . . . . . . . . . . . 131
13.1 LCD panel signal usage . . . . . . . . . . . . . . . . 131
13.2 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . 133
13.3 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 135
13.4 XTAL and RTCX Printed Circuit Board (PCB)
layout guidelines. . . . . . . . . . . . . . . . . . . . . . 135
13.5 Standard I/O pin configuration . . . . . . . . . . . 135
13.6 Reset pin configuration. . . . . . . . . . . . . . . . . 136
13.7 Suggested USB interface solutions . . . . . . . 136
14 Package outline . . . . . . . . . . . . . . . . . . . . . . . 139
15 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
16 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . 147
17 References . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
18 Revision history. . . . . . . . . . . . . . . . . . . . . . . 149
19 Legal information . . . . . . . . . . . . . . . . . . . . . 152
19.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . 152
19.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 152
19.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . 152
19.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 153
20 Contact information . . . . . . . . . . . . . . . . . . . 153
21 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Your Electronic Engineering Resource
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7491181012: Off-line Transformer WE-UNIT
Product Description:
Würth Electronics, Inc. has a broad selection of power transformers
for the latest reference designs from some of the leading IC
manufacturers in the industry. The overall product offering contains
more than 50 transformers built for chipsets from NXP
Semiconductors, Linear Technology, ON Semiconductor, Power
Integrations, STMicroelectronics, and National Semiconductor.
Examples of these devices are a series of offline power transformers
designed for NXP's dimmable LED drivers and a full series of flyback
transformers for Linear Technology's isolated flyback converters.
They are Designed for Tiny Switch ICs from Power Integration and NCP101x or 105x of ON Semiconductor
Key Features:
Nominal input voltage: 125V DC to 375V DC Output power 3W and 9W
Operating temperature: -40°C to +125°C Clearance and creepage distance 6mm min.
Switching frequency: 132kHz Isolation voltage 4kVAC
Applications:
Designed for Tiny Switch ICs from Power
Integration and NCP101x or 105x of ON
Semiconductor
For SMPS with universal input from 85 VAC up to 265
VAC
Ordering Information:
Mfr Part # Farnell# Newark# Description
7491181012 Click Here Click Here Off-line transformer WE-UNIT
1. Introduction
This data sheet describes the functionality of the CLRC632 Integrated Circuit (IC). It
includes the functional and electrical specifications and from a system and hardware
viewpoint gives detailed information on how to design-in the device.
Remark: The CLRC632 supports all variants of the MIFARE Mini, MIFARE 1K,
MIFARE 4K and MIFARE Ultralight RF identification protocols. To aid readability
throughout this data sheet, the MIFARE Mini, MIFARE 1K, MIFARE 4K and
MIFARE Ultralight products and protocols have the generic name MIFARE.
2. General description
The CLRC632 is a highly integrated reader IC for contactless communication at
13.56 MHz. The CLRC632 reader IC provides:
• outstanding modulation and demodulation for passive contactless communication
• a wide range of methods and protocols
• a small, fully integrated package
• pin compatibility with the MFRC500, MFRC530, MFRC531 and SLRC400
All protocol layers of the ISO/IEC 14443 A and ISO/IEC 14443 B communication
standards are supported provided:
• additional components, such as the oscillator, power supply, coil etc. are correctly
applied.
• standardized protocols, such as ISO/IEC 14443-4 and/or ISO/IEC 14443 B
anticollision are correctly implemented
The CLRC632 supports contactless communication using MIFARE higher baud rates (see
Section 9.12 on page 40). The receiver module provides a robust and efficient
demodulation/decoding circuitry implementation for compatible transponder signals (see
Section 9.10 on page 34).
The digital module, manages the complete ISO/IEC 14443 standard framing and error
detection (parity and CRC). In addition, it supports the fast MIFARE security algorithm for
authenticating the MIFARE products (see Section 9.14 on page 42).
All layers of the I-CODE1 and ISO/IEC 15693 protocols are supported by the CLRC632.
The receiver module provides a robust and efficient demodulation/decoding circuitry
implementation for I-CODE1 and ISO/IEC 15693 compatible transponder signals. The
digital module handles I-CODE1 and ISO/IEC 15693 framing and error detection (CRC).
CLRC632
Standard multi-protocol reader solution
Rev. 3.7 — 27 February 2014
073937
Product data sheet
COMPANY PUBLICCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
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073937 2 of 127
NXP Semiconductors CLRC632
Standard multi-protocol reader solution
The internal transmitter module (Section 9.9 on page 31) can directly drive an antenna
designed for a proximity operating distance up to 100 mm without any additional active
circuitry.
A parallel interface can be directly connected to any 8-bit microprocessor to ensure
reader/terminal design flexibility. In addition, Serial Peripheral Interface (SPI) compatibility
is supported (see Section 9.1.4 on page 9).
3. Features and benefits
3.1 General
Highly integrated analog circuitry for demodulating and decoding card/label response
Buffered output drivers enable antenna connection using the minimum of external
components
Proximity operating distance up to 100 mm
Supports both ISO/IEC 14443 A and ISO/IEC 14443 B standards
Supports MIFARE dual-interface card ICs and the MIFARE Mini, MIFARE 1K,
MIFARE 4K protocols
Contactless communication at MIFARE higher baud rates (up to 424 kBd)
Supports both I-CODE1 and ISO/IEC 15693 protocols
Crypto1 and secure non-volatile internal key memory
Pin-compatible with the MFRC500, MFRC530, MFRC531 and the SLRC400
Parallel microprocessor interface with internal address latch and IRQ line
SPI compatibility
Flexible interrupt handling
Automatic detection of parallel microprocessor interface type
64-byte send and receive FIFO buffer
Hard reset with low power function
Software controlled Power-down mode
Programmable timer
Unique serial number
User programmable start-up configuration
Bit-oriented and byte oriented framing
Independent power supply pins for analog, digital and transmitter modules
Internal oscillator buffer optimized for low phase jitter enables 13.56 MHz quartz
connection
Clock frequency filtering
3.3 V to 5 V operation for transmitter in short range and proximity applications
3.3 V or 5 V operation for the digital module
4. Applications
Electronic payment systems
Identification systems
Access control systemsCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
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NXP Semiconductors CLRC632
Standard multi-protocol reader solution
Subscriber services
Banking systems
Digital content systems
5. Quick reference data
6. Ordering information
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
Tamb ambient temperature 40 - +150 C
Tstg storage temperature 40 - +150 C
VDDD digital supply voltage 0.5 5 6 V
VDDA analog supply voltage 0.5 5 6 V
VDD(TVDD) TVDD supply voltage 0.5 5 6 V
Vi
input voltage (absolute
value)
on any digital pin to DVSS 0.5 - VDDD + 0.5 V
on pin RX to AVSS 0.5 - VDDA + 0.5 V
ILI input leakage current 1.0 - 1.0 mA
IDD(TVDD) TVDD supply current continuous wave - - 150 mA
Table 2. Ordering information
Type number Package
Name Description Version
CLRC63201T/0FE SO32 plastic small outline package; 32 leads; body width 7.5 mm SOT287-1CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
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NXP Semiconductors CLRC632
Standard multi-protocol reader solution
7. Block diagram
Fig 1. CLRC632 block diagram
001aaj629
FIFO CONTROL
64-BYTE FIFO
MASTER KEY BUFFER
CRYPTO1 UNIT
CONTROL REGISTER
BANK
NWR NRD NCS ALE A0 A1 A2
10 11 9 21 22 23 24 13 14 15 16 17 18 19 20
AD0 to AD7/D0 to D7
STATE MACHINE
COMMAND REGISTER
PROGRAMMABLE TIMER
INTERRUPT CONTROL
CRC16/CRC8
GENERATION AND CHECK
PARALLEL/SERIAL CONVERTER
BIT COUNTER
PARITY GENERATION AND CHECK
FRAME GENERATION AND CHECK
SERIAL DATA SWITCH
BIT DECODING BIT ENCODING
32 × 16-BYTE
EEPROM
EEPROM
ACCESS
CONTROL
32-BIT PSEUDO
RANDOM GENERATOR
AMPLITUDE
RATING
CLOCK
GENERATION,
FILTERING AND
DISTRIBUTION
OSCILLATOR
LEVEL SHIFTERS
CORRELATION
AND
REFERENCE BIT DECODING
VOLTAGE
Q-CHANNEL
AMPLIFIER
Q-CHANNEL
DEMODULATOR
I-CHANNEL
ANALOG AMPLIFIER
TEST
MULTIPLEXER I-CHANNEL
DEMODULATOR
PARALLEL INTERFACE CONTROL
(INCLUDING AUTOMATIC INTERFACE DETECTION AND SYNCHRONISATION)
VOLTAGE
MONITOR
AND
POWER ON
DETECT
DVDD
RSTPD
Q-CLOCK
GENERATION
TRANSMITTER CONTROL
GND
GND
VMID AUX RX TVSS TX1 TX2 TVDD
30 27 29 8 5 7 6
V
V
POWER ON
DETECT
OSCIN
AVDD
AVSS
OSCOUT
IRQ
MFIN
MFOUT
DVSS
25
31
1
26
28
32
2
3
4
12
RESET
CONTROL
POWER DOWN
CONTROLCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
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NXP Semiconductors CLRC632
Standard multi-protocol reader solution
8. Pinning information
8.1 Pin description
Fig 2. CLRC632 pin configuration
CLRC632
OSCIN OSCOUT
IRQ RSTPD
MFIN VMID
MFOUT RX
TX1 AVSS
TVDD AUX
TX2 AVDD
TVSS DVDD
NCS A2/SCK
NWR/R/NW/nWrite A1
NRD/NDS/nDStrb A0/nWait/MOSI
DVSS ALE/AS/nAStrb/NSS
AD0/D0 D7/AD7
AD1/D1 D6/AD6
AD2/D2 D5/AD5
AD3/D3 D4/AD4
001aaj630
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18
17
20
19
22
21
24
23
26
25
32
31
30
29
28
27
Table 3. Pin description
Pin Symbol Type[1] Description
1 OSCIN I oscillator/clock inputs:
crystal oscillator input to the oscillator’s inverting amplifier
externally generated clock input; fosc = 13.56 MHz
2 IRQ O interrupt request generates an output signaling an interrupt event
3 MFIN I ISO/IEC 14443 A MIFARE serial data interface input
4[2] MFOUT O interface outputs used as follows:
MIFARE: generates serial data ISO/IEC 14443 A
I-CODE: generates serial data based on I-CODE1 and ISO/IEC 15693
5 TX1 O transmitter 1 modulated carrier output; 13.56 MHz
6 TVDD P transmitter power supply for the TX1 and TX2 output stages
7 TX2 O transmitter 2 modulated carrier output; 13.56 MHz
8 TVSS G transmitter ground for the TX1 and TX2 output stages
9 NCS I not chip select input is used to select and activate the CLRC632’s microprocessor
interface
10[3] NWR I not write input generates the strobe signal for writing data to the CLRC632
registers when applied to pins D0 to D7
R/NW I read not write input is used to switch between read or write cycles
nWrite I not write input selects the read or write cycle to be performedCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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NXP Semiconductors CLRC632
Standard multi-protocol reader solution
[1] Pin types: I = Input, O = Output, I/O = Input/Output, P = Power and G = Ground.
[2] The SLRC400 uses pin name SIGOUT for pin MFOUT. The CLRC632 functionality includes test functions for the SLRC400 using pin
MFOUT.
[3] These pins provide different functionality depending on the selected microprocessor interface type (see Section 9.1 on page 7 for
detailed information).
11[3] NRD I not read input generates the strobe signal for reading data from the CLRC632
registers when applied to pins D0 to D7
NDS I not data strobe input generates the strobe signal for the read and write cycles
nDStrb I not data strobe input generates the strobe signal for the read and write cycles
12 DVSS G digital ground
13 D0 O SPI master in, slave out output
13 to 20[3] D0 to D7 I/O 8-bit bidirectional data bus input/output on pins D0 to D7
AD0 to AD7 I/O 8-bit bidirectional address and data bus input/output on pins AD0 to AD7
21[3] ALE I address latch enable input for pins AD0 to AD5; HIGH latches the internal address
AS I address strobe input for pins AD0 to AD5; HIGH latches the internal address
nAStrb I not address strobe input for pins AD0 to AD5; LOW latches the internal address
NSS I not slave select strobe input for SPI communication
22[3] A0 I address line 0 is the address register bit 0 input
nWait O not wait output:
LOW starts an access cycle
HIGH ends an access cycle
MOSI I SPI master out, slave in
23 A1 I address line 1 is the address register bit 1 input
24[3] A2 I address line 2 is the address register bit 2 input
SCK I SPI serial clock input
25 DVDD P digital power supply
26 AVDD P analog power supply for pins OSCIN, OSCOUT, RX, VMID and AUX
27 AUX O auxiliary output is used to generate analog test signals. The output signal is
selected using the TestAnaSelect register’s TestAnaOutSel[4:0] bits
28 AVSS G analog ground
29 RX I receiver input is used as the card response input. The carrier is load modulated at
13.56 MHz, drawn from the antenna circuit
30 VMID P internal reference voltage pin provides the internal reference voltage as a supply
Remark: It must be connected to a 100 nF block capacitor connected between pin
VMID and ground
31 RSTPD I reset and power-down input:
HIGH: the internal current sinks are switched off, the oscillator is inhibited and
the input pads are disconnected
LOW (negative edge): start internal reset phase
32 OSCOUT O crystal oscillator output for the oscillator’s inverting amplifier
Table 3. Pin description …continued
Pin Symbol Type[1] DescriptionCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
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NXP Semiconductors CLRC632
Standard multi-protocol reader solution
9. Functional description
9.1 Digital interface
9.1.1 Overview of supported microprocessor interfaces
The CLRC632 supports direct interfacing to various 8-bit microprocessors. Alternatively,
the CLRC632 can be connected to a PC’s Enhanced Parallel Port (EPP). Table 4 shows
the parallel interface signals supported by the CLRC632.
9.1.2 Automatic microprocessor interface detection
After a Power-On or Hard reset, the CLRC632 resets parallel microprocessor interface
mode and detects the microprocessor interface type.
The CLRC632 identifies the microprocessor interface using the logic levels on the control
pins. This is performed using a combination of fixed pin connections and the dedicated
Initialization routine (see Section 9.7.4 on page 30).
Table 4. Supported microprocessor and EPP interface signals
Bus control signals Bus Separated address
and data bus
Multiplexed address and data bus
Separated read and
write strobes
control NRD, NWR, NCS NRD, NWR, NCS, ALE
address A0, A1, A2 AD0, AD1, AD2, AD3, AD4, AD5
data D0 to D7 AD0 to AD7
Common read and write
strobe
control R/NW, NDS, NCS R/NW, NDS, NCS, AS
address A0, A1, A2 AD0, AD1, AD2, AD3, AD4, AD5
data D0 to D7 AD0 to AD7
Common read and write
strobe with handshake
(EPP)
control - nWrite, nDStrb, nAStrb, nWait
address - AD0, AD1, AD2, AD3, AD4, AD5
data - AD0 to AD7CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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NXP Semiconductors CLRC632
Standard multi-protocol reader solution
9.1.3 Connection to different microprocessor types
The connection to various microprocessor types is shown in Table 5.
9.1.3.1 Separate read and write strobe
Refer to Section 13.4.1 on page 102 for timing specification.
Table 5. Connection scheme for detecting the parallel interface type
CLRC632
pins
Parallel interface type and signals
Separated read/write strobe Common read/write strobe
Dedicated
address bus
Multiplexed
address
bus
Dedicated
address bus
Multiplexed
address bus
Multiplexed
address bus with
handshake
ALE HIGH ALE HIGH AS nAStrb
A2 A2 LOW A2 LOW HIGH
A1 A1 HIGH A1 HIGH HIGH
A0 A0 HIGH A0 LOW nWait
NRD NRD NRD NDS NDS nDStrb
NWR NWR NWR R/NW R/NW nWrite
NCS NCS NCS NCS NCS LOW
D7 to D0 D7 to D0 AD7 to AD0 D7 to D0 AD7 to AD0 AD7 to AD0
Fig 3. Connection to microprocessor: separate read and write strobes
001aak607
address bus (A3 to An)
NCS
A0 to A2
address bus (A0 to A2)
D0 to D7
ALE
data bus (D0 to D7)
HIGH
NRD Read strobe (NRD)
NWR Write strobe (NWR)
DEVICE
ADDRESS
DECODER
non-multiplexed address
NCS
AD0 to AD7
ALE
multiplexed address/data (AD0 to AD7)
address latch enable (ALE)
NRD Read strobe (NRD)
NWR Write strobe (NWR)
A2 LOW
A1 HIGH
A0 HIGH
DEVICE
ADDRESS
DECODERCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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9.1.3.2 Common read and write strobe
Refer to Section 13.4.2 on page 103 for timing specification.
9.1.3.3 Common read and write strobe: EPP with handshake
Refer to Section 13.4.3 on page 104 for timing specification.
Remark: In the EPP standard a chip select signal is not defined. To cover this situation,
the status of the NCS pin can be used to inhibit the nDStrb signal. If this inhibitor is not
used, it is mandatory that pin NCS is connected to pin DVSS.
Remark: After each Power-On or Hard reset, the nWait signal on pin A0 is
high-impedance. nWait is defined as the first negative edge applied to the nAStrb pin after
the reset phase. The CLRC632 does not support Read Address Cycle.
9.1.4 Serial Peripheral Interface
The CLRC632 provides compatibility with the 5-wire Serial Peripheral Interface (SPI)
standard and acts as a slave during the SPI communication. The SPI clock signal SCK
must be generated by the master. Data communication from the master to the slave uses
the MOSI line. The MISO line sends data from the CLRC632 to the master.
Fig 4. Connection to microprocessor: common read and write strobes
001aak608
address bus (A3 to An)
NCS
A0 to A2
address bus (A0 to A2)
D0 to D7
ALE
data bus (D0 to D7)
HIGH
NRD Data strobe (NDS)
NWR Read/Write (R/NW)
DEVICE
ADDRESS
DECODER
non-multiplexed address
NCS
AD0 to AD7
ALE
multiplexed address/data (AD0 to AD7)
Address strobe (AS)
NRD Data strobe (NDS)
NWR Read/Write (R/NW)
A2 LOW
A1 HIGH
A0 LOW
DEVICE
ADDRESS
DECODER
Fig 5. Connection to microprocessor: EPP common read/write strobes and handshake
001aak609
LOW NCS
AD0 to AD7
ALE
multiplexed address/data (AD0 to AD7)
Address strobe (nAStrb)
NRD Data strobe (nDStrb)
NWR Read/Write (nWrite)
A2 HIGH
A1 HIGH
A0 nWait
DEVICECLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
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NXP Semiconductors CLRC632
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Figure 6 shows the microprocessor connection to the CLRC632 using SPI.
Remark: The SPI implementation for CLRC632 conforms to the SPI standard and
ensures that the CLRC632 can only be addressed as a slave.
9.1.4.1 SPI read data
The structure shown in Table 7 must be used to read data using SPI. It is possible to read
up to n-data bytes. The first byte sent defines both, the mode and the address.
The address byte must meet the following criteria:
• the Most Significant Bit (MSB) of the first byte sets the mode. To read data from the
CLRC632 the MSB is set to logic 1
• bits [6:1] define the address
• the Least Significant Bit (LSB) should be set to logic 0.
As shown in Table 8, all the bits of the last byte sent are set to logic 0.
Table 6. SPI compatibility
CLRC632 pins SPI pins
ALE NSS
A2 SCK
A1 LOW
A0 MOSI
NRD HIGH
NWR HIGH
NCS LOW
D7 to D1 do not connect
D0 MISO
Fig 6. Connection to microprocessor: SPI
001aak610
LOW NCS
D0
ALE
A2 SCK
A1 LOW
MOSI
NSS
A0
MISO
DEVICE
Table 7. SPI read data
Pin Byte 0 Byte 1 Byte 2 ... Byte n Byte n + 1
MOSI address 0 address 1 address 2 ... address n 00
MISO XX data 0 data 1 ... data n 1 data nCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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[1] All reserved bits must be set to logic 0.
9.1.4.2 SPI write data
The structure shown in Table 9 must be used to write data using SPI. It is possible to write
up to n-data bytes. The first byte sent defines both the mode and the address.
The address byte must meet the following criteria:
• the MSB of the first byte sets the mode. To write data to the CLRC632, the MSB is set
to logic 0
• bits [6:1] define the address
• the LSB should be set to logic 0.
SPI write mode writes all data to the address defined in byte 0 enabling effective write
cycles to the FIFO buffer.
[1] All reserved bits must be set to logic 0.
Remark: The data bus pins D7 to D0 must be disconnected.
Refer to Section 13.4.4 on page 106 for the timing specification.
Table 8. SPI read address
Address
(MOSI)
Bit 7
(MSB)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
(LSB)
byte 0 1 address address address address address address reserved
byte 1 to byte n reserved address address address address address address reserved
byte n + 1 0 0 0 0 0 0 0 0
Table 9. SPI write data
Byte 0 Byte 1 Byte 2 ... Byte n Byte n + 1
MOSI address data 0 data 1 ... data n 1 data n
MISO XX XX XX ... XX XX
Table 10. SPI write address
Address line
(MOSI)
Bit 7
(MSB)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
(LSB)
byte 0 0 address address address address address address reserved
byte 1 to byte
n+1
data data data data data data data dataCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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9.2 Memory organization of the EEPROM
Table 11. EEPROM memory organization diagram
Block Byte
address
Access Memory content Refer to
Position Address
0 0 00h to 0Fh R product
information field
Section 9.2.1 on page 13
1 1 10h to 1Fh R/W StartUp register
initialization file
Section 9.2.2.1 on page 14
2 2 20h to 2Fh R/W
3 3 30h to 3Fh R/W register
initialization file
user data or
second
initialization
Section 9.2.2.3 “Register
initialization file (read/write)”
on page 16
4 4 40h to 4Fh R/W
5 5 50h to 5Fh R/W
6 6 60h to 6Fh R/W
7 7 70h to 7Fh R/W
8 8 80h to 8Fh W keys for Crypto1 Section 9.2.3 on page 18
9 9 90h to 9Fh W
10 A A0h to AFh W
11 B B0h to BFh W
12 C C0h to CFh W
13 D D0h to DFh W
14 E E0h to EFh W
15 F F0h to FFh W
16 10 100h to 10Fh W
17 11 110h to 11Fh W
18 12 120h to 12Fh W
19 13 130h to 13Fh W
20 14 140h to 14Fh W
21 15 150h to 15Fh W
22 16 160h to 16Fh W
23 17 170h to 17Fh W
24 18 180h to 18Fh W
25 19 190h to 19Fh W
26 1A 1A0h to
1AFh
W
27 1B 1B0h to
1BFh
W
28 1C 1C0h to
1CFh
W
29 1D 1D0h to
1DFh
W
30 1E 1E0h to
1EFh
W
31 1F 1F0h to
1FFh
WCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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9.2.1 Product information field (read only)
[1] Byte 4 contains the current version number.
9.2.2 Register initialization files (read/write)
Register initialization from address 10h to address 2Fh is performed automatically during
the initializing phase (see Section 9.7.3 on page 30) using the StartUp register
initialization file.
In addition, the CLRC632 registers can be initialized using values from the register
initialization file when the LoadConfig command is executed (see Section 11.5.1 on
page 95).
Table 12. Product information field
Byte Symbol Access Value Description
15 CRC R - the content of the product information field
is secured using a CRC byte which is
checked during start-up
14 RsMaxP R - maximum source resistance for the
p-channel driver transistor on pins TX1 and
TX2
The source resistance of the p-channel
driver transistors of pin TX1 and TX2 can be
adjusted using the value GsCfgCW[5:0] in
the CwConductance register (see
Section 9.9.3 on page 32). The mean value
of the maximum adjustable source
resistance for pins TX1 and TX2 is stored
as an integer value in in this byte. Typical
values for RsMaxP are between 60 to
140 . This value is denoted as maximum
adjustable source resistance RS(ref)maxP and
is measured by setting the CwConductance
register’s GsCfgCW[5:0] bits to 01h.
13 to 12 Internal R - two bytes for internal trimming parameters
11 to 8 Product Serial Number R - a unique four byte serial number for the
device
7 to 5 reserved R -
4 to 0 Product Type
Identification
R - the CLRC632 is a member of a new family
of highly integrated reader ICs. Each
member of the product family has a unique
product type identification. The value of the
product type identification is shown in
Table 13.
Table 13. Product type identification definition
Definition Product type identification bytes
Byte 0 1 2 3 4[1]
Value 30h FFh FFh 0Fh XXhCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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Remark: The following points apply to initialization:
• the Page register (addressed using 10h, 18h, 20h, 28h) is skipped and not initialized.
• make sure that all PreSetxx registers are not changed.
• make sure that all register bits that are reserved are set to logic 0.
9.2.2.1 StartUp register initialization file (read/write)
The EEPROM memory block address 1 and 2 contents are used to automatically set the
register subaddresses 10h to 2Fh during the initialization phase. The default values stored
in the EEPROM during production are shown in Section 9.2.2.2 “Factory default StartUp
register initialization file”.
The byte assignment is shown in Table 14.
9.2.2.2 Factory default StartUp register initialization file
During the production tests, the StartUp register initialization file is initialized using the
default values shown in Table 15. During each power-up and initialization phase, these
values are written to the CLRC632’s registers.
Table 14. Byte assignment for register initialization at start-up
EEPROM byte address Register address Remark
10h (block 1, byte 0) 10h skipped
11h 11h copied
… ……
2Fh (block 2, byte 15) 2Fh copiedCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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Remark: The CLRC632 default configuration supports the MIFARE and ISO/IEC 14443 A
communication scheme. Memory addresses 3 to 7 may be used for user-specific
initialization files such as I-CODE1, ISO/IEC 15693 or ISO/IEC 14443 B.
Table 15. Shipment content of StartUp configuration file
EEPROM
byte
address
Register
address
Value Symbol Description
10h 10h 00h Page free for user
11h 11h 58h TxControl transmitter pins TX1 and TX2 are switched off, bridge driver
configuration, modulator driven from internal digital circuitry
12h 12h 3Fh CwConductance source resistance of TX1 and TX2 is set to minimum
13h 13h 3Fh ModConductance defines the output conductance
14h 14h 19h CoderControl ISO/IEC 14443 A coding is set
15h 15h 13h ModWidth pulse width for Miller pulse coding is set to standard configuration
16h 16h 3Fh ModWidthSOF pulse width of Start Of Frame (SOF)
17h 17h 3Bh TypeFraming ISO/IEC 14443 A framing is set
18h 18h 00h Page free for user
19h 19h 73h RxControl1 ISO/IEC 14443 A is set and internal amplifier gain is maximum
1Ah 1Ah 08h DecoderControl bit-collisions always evaluate to HIGH in the data bit stream
1Bh 1Bh ADh BitPhase BitPhase[7:0] is set to standard configuration
1Ch 1Ch FFh RxThreshold MinLevel[3:0] and CollLevel[3:0] are set to maximum
1Dh 1Dh 1Eh BPSKDemControl ISO/IEC 14443 A is set
1Eh 1Eh 41h RxControl2 use Q-clock for the receiver, automatic receiver off is switched on,
decoder is driven from internal analog circuitry
1Fh 1Fh 00h ClockQControl automatic Q-clock calibration is switched on
20h 20h 00h Page free for user
21h 21h 06h RxWait frame guard time is set to six bit-clocks
22h 22h 03h ChannelRedundancy channel redundancy is set using ISO/IEC 14443 A
23h 23h 63h CRCPresetLSB CRC preset value is set using ISO/IEC 14443 A
24h 24h 63h CRCPresetMSB CRC preset value is set using ISO/IEC 14443 A
25h 25h 00h TimeSlotPeriod defines the time for the I-CODE1 time slots
26h 26h 00h MFOUTSelect pin MFOUT is set LOW
27h 27h 00h PreSet27 -
28h 28h 00h Page free for user
29h 29h 08h FIFOLevel WaterLevel[5:0] FIFO buffer warning level is set to standard
configuration
2Ah 2Ah 07h TimerClock TPreScaler[4:0] is set to standard configuration, timer unit restart
function is switched off
2Bh 2Bh 06h TimerControl Timer is started at the end of transmission, stopped at the beginning
of reception
2Ch 2Ch 0Ah TimerReload TReloadValue[7:0]: the timer unit preset value is set to standard
configuration
2Dh 2Dh 02h IRQPinConfig pin IRQ is set to high-impedance
2Eh 2Eh 00h PreSet2E -
2Fh 2Fh 00h PreSet2F -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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9.2.2.3 Register initialization file (read/write)
The EEPROM memory content from block address 3 to 7 can initialize register sub
addresses 10h to 2Fh when the LoadConfig command is executed (see Section 11.5.1 on
page 95). This command requires the EEPROM starting byte address as a two byte
argument for the initialization procedure.
The byte assignment is shown in Table 16.
The register initialization file is large enough to hold values for two initialization sets and
up to one block (16-byte) of user data. The startup configuration could be adapted to the
I-CODE1 StartUp configuration and stored in register block address 3 and 4, providing
additional flexibility.
Remark: The register initialization file can be read/written by users and these bytes can
be used to store other user data.
After each power-up, the default configuration enables the MIFARE and ISO/IEC 14443 A
protocol.
9.2.2.4 Content of I-CODE1 and ISO/IEC 15693 StartUp register values
Table 17 gives an overview of the StartUp values for I-CODE1 and ISO/IEC 15693
communication.
Table 16. Byte assignment for register initialization at startup
EEPROM byte address Register address Remark
EEPROM starting byte address 10h skipped
EEPROM + 1 starting byte address 11h copied
… …
EEPROM + 31 starting byte address 2Fh copiedCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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Table 17. Content of I-CODE1 startup configuration
EEPROM
byte
address
Register
address
Value Symbol Description
30h 10h 00h Page free for user
31h 11h 58h TxControl transmitter pins TX1 and TX2 switched off, bridge driver
configuration, modulator driven from internal digital circuitry
32h 12h 3Fh CwConductance source resistance (RS) of TX1 and TX2 to minimum
33h 13h 05h ModGsCfgh source resistance (RS) of TX1 and TX2 at the time of
modulation, to determine the modulation index
34h 14h 2Ch CoderControl selects the bit coding mode and the framing during
transmission
35h 15h 3Fh ModWidth pulse width for code used (1 out of 256, NRZ or 1 out of 4)
pulse coding is set to standard configuration
36h 16h 3Fh ModWidthSOF pulse width of SOF
37h 17h 00h TypeBFraming -
38h 18h 00h Page free for user
39h 19h 8Bh RxControl1 amplifier gain is maximum
3Ah 1Ah 00h DecoderControl bit-collisions always evaluate to HIGH in the data bit stream
3Bh 1Bh 54h BitPhase BitPhase[7:0] is set to standard configuration
3Ch 1Ch 68h RxThreshold: MinLevel[3:0] and CollLevel[3:0] are set to maximum
3Dh 1Dh 00h BPSKDemControl -
3Eh 1Eh 41h RxControl2 use Q-clock for the receiver, automatic receiver off is
switched on, decoder is driven from internal analog circuitry
3Fh 1Fh 00h ClockQControl automatic Q-clock calibration is switched on
40h 20h 00h Page free for user
41h 21h 08h RxWait frame guard time is set to eight bit-clocks
42h 22h 0Ch ChannelRedundancy channel redundancy is set using I-CODE1
43h 23h FEh CRCPresetLSB CRC preset value is set using I-CODE1
44h 24h FFh CRCPresetMSB CRC preset value is set using I-CODE1
45h 25h 00h TimeSlot Period defines the time for the I-CODE1 time slots
46h 26h 00h MFOUTSelect pin MFOUT is set LOW
47h 27h 00h PreSet27 -
48h 28h 00h Page free for user
49h 29h 3Eh FIFOLevel WaterLevel[5:0] FIFO buffer warning level is set to standard
configuration
4Ah 2Ah 0Bh TimerClock TPreScaler[4:0] is set to standard configuration, timer unit
restart function is switched off
4Bh 2Bh 02h TimerControl Timer is started at the end of transmission, stopped at the
beginning of reception
4Ch 2Ch 00h TimerReload the timer unit preset value is set to standard configuration
4Dh 2Dh 02h IRQPinConfig pin IRQ is set to high-impedance
4Eh 2Eh 00h PreSet2E -
4Fh 2Fh 00h PreSet2F -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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9.2.3 Crypto1 keys (write only)
MIFARE security requires specific cryptographic keys to encrypt data stream
communication on the contactless interface. These keys are called Crypto1 keys.
9.2.3.1 Key format
Keys stored in the EEPROM are written in a specific format. Each key byte must be split
into lower four bits k0 to k3 (lower nibble) and the higher four bits k4 to k7 (higher nibble).
Each nibble is stored twice in one byte and one of the two nibbles is bit-wise inverted. This
format is a precondition for successful execution of the LoadKeyE2 (see Section 11.7.1 on
page 97) and LoadKey commands (see Section 11.7.2 on page 97).
Using this format, 12 bytes of EEPROM memory are needed to store a 6-byte key. This is
shown in Figure 7.
Example: The value for the key must be written to the EEPROM.
• If the key was: A0h A1h A2h A3h A4h A5h then
• 5Ah F0h 5Ah E1h 5Ah D2h 5Ah C3h 5Ah B4h 5Ah A5h would be written.
Remark: It is possible to load data for other key formats into the EEPROM key storage
location. However, it is not possible to validate card authentication with data which will
cause the LoadKeyE2 command (see Section 11.7.1 on page 97) to fail.
9.2.3.2 Storage of keys in the EEPROM
The CLRC632 reserves 384 bytes of memory in the EEPROM for the Crypto1 keys. No
memory segmentation is used to mirror the 12-byte structure of key storage. Thus, every
byte of the dedicated memory area can be the start of a key.
Example: If the key loading cycle starts at the last byte address of an EEPROM block, (for
example, key byte 0 is stored at 12Fh), the next bytes are stored in the next EEPROM
block, for example, key byte 1 is stored at 130h, byte 2 at 131h up to byte 11 at 13Ah.
Based on the 384 bytes of memory and a single key needing 12 bytes, then up to 32
different keys can be stored in the EEPROM.
Remark: It is not possible to load a key exceeding the EEPROM byte location 1FFh.
Fig 7. Key storage format
001aak640
Master key byte 0 (LSB)
Master key bits
EEPROM byte
address
Example
k7 k6 k5 k4 k7 k6 k5 k4
n
5Ah
k3 k2 k1 k0 k3 k2 k1 k0
n + 1
F0h
1
k7 k6 k5 k4 k7 k6 k5 k4
n + 2
5Ah
k3 k2 k1 k0 k3 k2 k1 k0
n + 3
E1h
5 (MSB)
k7 k6 k5 k4 k7 k6 k5 k4
n + 10
5Ah
k3 k2 k1 k0 k3 k2 k1 k0
n + 11
A5hCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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9.3 FIFO buffer
An 8 64 bit FIFO buffer is used in the CLRC632 to act as a parallel-to-parallel converter.
It buffers both the input and output data streams between the microprocessor and the
internal circuitry of the CLRC632. This makes it possible to manage data streams up to 64
bytes long without needing to take timing constraints into account.
9.3.1 Accessing the FIFO buffer
9.3.1.1 Access rules
The FIFO buffer input and output data bus is connected to the FIFOData register. Writing
to this register stores one byte in the FIFO buffer and increments the FIFO buffer write
pointer. Reading from this register shows the FIFO buffer contents stored at the FIFO
buffer read pointer and increments the FIFO buffer read pointer. The distance between the
write and read pointer can be obtained by reading the FIFOLength register.
When the microprocessor starts a command, the CLRC632 can still access the FIFO
buffer while the command is running. Only one FIFO buffer has been implemented which
is used for input and output. Therefore, the microprocessor must ensure that there are no
inadvertent FIFO buffer accesses. Table 18 gives an overview of FIFO buffer access
during command processing.
9.3.2 Controlling the FIFO buffer
In addition to writing to and reading from the FIFO buffer, the FIFO buffer pointers can be
reset using the FlushFIFO bit. This changes the FIFOLength[6:0] value to zero, bit
FIFOOvfl is cleared and the stored bytes are no longer accessible. This enables the FIFO
buffer to be written with another 64 bytes of data.
Table 18. FIFO buffer access
Active
command
FIFO buffer Remark
p Write p Read
StartUp - -
Idle - -
Transmit yes -
Receive - yes
Transceive yes yes the microprocessor has to know the state of the
command (transmitting or receiving)
WriteE2 yes -
ReadE2 yes yes the microprocessor has to prepare the arguments,
afterwards only reading is allowed
LoadKeyE2 yes -
LoadKey yes -
Authent1 yes -
Authent2 - -
LoadConfig yes -
CalcCRC yes -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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9.3.3 FIFO buffer status information
The microprocessor can get the following FIFO buffer status data:
• the number of bytes stored in the FIFO buffer: bits FIFOLength[6:0]
• the FIFO buffer full warning: bit HiAlert
• the FIFO buffer empty warning: bit LoAlert
• the FIFO buffer overflow warning: bit FIFOOvfl.
Remark: Setting the FlushFIFO bit clears the FIFOOvfl bit.
The CLRC632 can generate an interrupt signal when:
• bit LoAlertIRq is set to logic 1 and bit LoAlert = logic 1, pin IRQ is activated.
• bit HiAlertIRq is set to logic 1 and bit HiAlert = logic 1, pin IRQ activated.
The HiAlert flag bit is set to logic 1 only when the WaterLevel[5:0] bits or less can be
stored in the FIFO buffer. The trigger is generated by Equation 1:
(1)
The LoAlert flag bit is set to logic 1 when the FIFOLevel register’s WaterLevel[5:0] bits or
less are stored in the FIFO buffer. The trigger is generated by Equation 2:
(2)
9.3.4 FIFO buffer registers and flags
Table 18 shows the related FIFO buffer flags in alphabetic order.
9.4 Interrupt request system
The CLRC632 indicates interrupt events by setting the PrimaryStatus register bit IRq (see
Section 10.5.1.4 “PrimaryStatus register” on page 51) and activating pin IRQ. The signal
on pin IRQ can be used to interrupt the microprocessor using its interrupt handling
capabilities ensuring efficient microprocessor software.
HiAlert 64 FIFOLength = – WaterLevel
LoAlert FIFOLength WaterLevel =
Table 19. Associated FIFO buffer registers and flags
Flags Register name Bit Register address
FIFOLength[6:0] FIFOLength 6 to 0 04h
FIFOOvfl ErrorFlag 4 0Ah
FlushFIFO Control 0 09h
HiAlert PrimaryStatus 1 03h
HiAlertIEn InterruptEn 1 06h
HiAlertIRq InterruptRq 1 07h
LoAlert PrimaryStatus 0 03h
LoAlertIEn InterruptEn 0 06h
LoAlertIRq InterruptRq 0 07h
WaterLevel[5:0] FIFOLevel 5 to 0 29hCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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9.4.1 Interrupt sources overview
Table 20 shows the integrated interrupt flags, related source and setting condition. The
interrupt TimerIRq flag bit indicates an interrupt set by the timer unit. Bit TimerIRq is set
when the timer decrements from one down to zero (bit TAutoRestart disabled) or from one
to the TReLoadValue[7:0] with bit TAutoRestart enabled.
Bit TxIRq indicates interrupts from different sources and is set as follows:
• the transmitter automatically sets the bit TxIRq interrupt when it is active and its state
changes from sending data to transmitting the end of frame pattern
• the CRC coprocessor sets the bit TxIRq after all data from the FIFO buffer has been
processed indicated by bit CRCReady = logic 1
• when EEPROM programming is finished, the bit TxIRq is set and is indicated by bit
E2Ready = logic 1
The RxIRq flag bit indicates an interrupt when the end of the received data is detected.
The IdleIRq flag bit is set when a command finishes and the content of the Command
register changes to Idle.
When the FIFO buffer reaches the HIGH-level indicated by the WaterLevel[5:0] value (see
Section 9.3.3 on page 20) and bit HiAlert = logic 1, then the HiAlertIRq flag bit is set to
logic 1.
When the FIFO buffer reaches the LOW-level indicated by the WaterLevel[5:0] value (see
Section 9.3.3 on page 20) and bit LoAlert = logic 1, then LoAlertIRq flag bit is set to
logic 1.
9.4.2 Interrupt request handling
9.4.2.1 Controlling interrupts and getting their status
The CLRC632 informs the microprocessor about the interrupt request source by setting
the relevant bit in the InterruptRq register. The relevance of each interrupt request bit as
source for an interrupt can be masked by the InterruptEn register interrupt enable bits.
Table 20. Interrupt sources
Interrupt flag Interrupt source Trigger action
TimerIRq timer unit timer counts from 1 to 0
TxIRq transmitter a data stream, transmitted to the card, ends
CRC coprocessor all data from the FIFO buffer has been processed
EEPROM all data from the FIFO buffer has been
programmed
RxIRq receiver a data stream, received from the card, ends
IdleIRq Command register command execution finishes
HiAlertIRq FIFO buffer FIFO buffer is full
LoAlertIRq FIFO buffer FIFO buffer is empty
Table 21. Interrupt control registers
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
InterruptEn SetIEn reserved TimerIEn TxIEn RxIEn IdleIEn HiAlertIEn LoAlertIEn
InterruptRq SetIRq reserved TimerIRq TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRqCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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If any interrupt request flag is set to logic 1 (showing that an interrupt request is pending)
and the corresponding interrupt enable flag is set, the PrimaryStatus register IRq flag bit is
set to logic 1. Different interrupt sources can activate simultaneously because all interrupt
request bits are OR’ed, coupled to the IRq flag and then forwarded to pin IRQ.
9.4.2.2 Accessing the interrupt registers
The interrupt request bits are automatically set by the CLRC632’s internal state machines.
In addition, the microprocessor can also set or clear the interrupt request bits as required.
A special implementation of the InterruptRq and InterruptEn registers enables changing
an individual bit status without influencing any other bits. If an interrupt register is set to
logic 1, bit SetIxx and the specific bit must both be set to logic 1 at the same time. Vice
versa, if a specific interrupt flag is cleared, zero must be written to the SetIxx and the
interrupt register address must be set to logic 1 at the same time.
If a content bit is not changed during the setting or clearing phase, zero must be written to
the specific bit location.
Example: Writing 3Fh to the InterruptRq register clears all bits. SetIRq is set to logic 0
while all other bits are set to logic 1. Writing 81h to the InterruptRq register sets LoAlertIRq
to logic 1 and leaves all other bits unchanged.
9.4.3 Configuration of pin IRQ
The logic level of the IRq flag bit is visible on pin IRQ. The signal on pin IRQ can also be
controlled using the following IRQPinConfig register bits.
• bit IRQInv: the signal on pin IRQ is equal to the logic level of bit IRq when this bit is set
to logic 0. When set to logic 1, the signal on pin IRQ is inverted with respect to bit IRq.
• bit IRQPushPull: when set to logic 1, pin IRQ has CMOS output characteristics. When
it is set to logic 0, it is an open-drain output which requires an external resistor to
achieve a HIGH-level at pin IRQ.
Remark: During the reset phase (see Section 9.7.2 on page 29) bit IRQInv is set to
logic 1 and bit IRQPushPull is set to logic 0. This results in a high-impedance on pin IRQ.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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9.4.4 Register overview interrupt request system
Table 22 shows the related interrupt request system flags in alphabetic order.
9.5 Timer unit
The timer derives its clock from the 13.56 MHz on-board chip clock. The microprocessor
can use this timer to manage timing-relevant tasks.
The timer unit may be used in one of the following configurations:
• Timeout counter
• WatchDog counter
• Stopwatch
• Programmable one shot
• Periodical trigger
The timer unit can be used to measure the time interval between two events or to indicate
that a specific timed event occurred. The timer is triggered by events but does not
influence any event (e.g. a time-out during data receiving does not automatically influence
the receiving process). Several timer related flags can be set and these flags can be used
to generate an interrupt.
Table 22. Associated Interrupt request system registers and flags
Flags Register name Bit Register address
HiAlertIEn InterruptEn 1 06h
HiAlertIRq InterruptRq 1 07h
IdleIEn InterruptEn 2 06h
IdleIRq InterruptRq 2 07h
IRq PrimaryStatus 3 03h
IRQInv IRQPinConfig 1 07h
IRQPushPull IRQPinConfig 0 07h
LoAlertIEn InterruptEn 0 06h
LoAlertIRq InterruptRq 0 07h
RxIEn InterruptEn 3 06h
RxIRq InterruptRq 3 07h
SetIEn InterruptEn 7 06h
SetIRq InterruptRq 7 07h
TimerIEn InterruptEn 5 06h
TimerIRq InterruptRq 5 07h
TxIEn InterruptEn 4 06h
TxIRq InterruptRq 4 07hCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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9.5.1 Timer unit implementation
9.5.1.1 Timer unit block diagram
Figure 8 shows the block diagram of the timer module.
The timer unit is designed, so that events when combined with enabling flags start or stop
the counter. For example, setting bit TStartTxBegin = logic 1 enables control of received
data with the timer unit. In addition, the first received bit is indicated by the TxBegin event.
This combination starts the counter at the defined TReloadValue[7:0].
The timer stops automatically when the counter value is equal to zero or if a defined stop
event happens.
9.5.1.2 Controlling the timer unit
The main part of the timer unit is a down-counter. As long as the down-counter value is
not zero, it decrements its value with each timer clock cycle.
If the TAutoRestart flag is enabled, the timer does not decrement down to zero. On
reaching value 1, the timer reloads the next clock function with the TReloadValue[7:0].
Fig 8. Timer module block diagram
001aak611
TxEnd Event
TAutoRestart
TRunning
TStartTxEnd
TStartNow
S
RQ
START COUNTER/
PARALLEL LOAD
STOP COUNTER
TPreScaler[4:0]
TimerValue[7:0]
Counter = 0 ?
to interrupt logic: TimerIRq
PARALLEL OUT
PARALLEL IN
TReloadValue[7:0]
CLOCK
DIVIDER
COUNTER MODULE
(x ≤ x − 1)
TStopNow
TxBegin Event
TStartTxBegin
TStopRxEnd
RxEnd Event
TStopRxBegin
13.56 MHz
to parallel interface
RxBegin Event
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The timer is started immediately by loading a value from the TimerReload register into the
counter module.
This is activated by one of the following events:
• transmission of the first bit to the card (TxBegin event) with bit TStartTxBegin = logic 1
• transmission of the last bit to the card (TxEnd event) with bit TStartTxEnd = logic 1
• bit TStartNow is set to logic 1 by the microprocessor
Remark: Every start event reloads the timer from the TimerReload register. Thus, the
timer unit is re-triggered.
The timer can be configured to stop on one of the following events:
• receipt of the first valid bit from the card (RxBegin event) with bit
TStopRxBegin = logic 1
• receipt of the last bit from the card (RxEnd event) with bit TStopRxEnd = logic 1
• the counter module has decremented down to zero and bit TAutoRestart = logic 0
• bit TStopNow is set to logic 1 by the microprocessor.
Loading a new value, e.g. zero, into the TimerReload register or changing the timer unit
while it is counting will not immediately influence the counter. In both cases, this is
because this register only affects the counter content after a start event.
If the counter is stopped when bit TStopNow is set, no TimerIRq is flagged.
9.5.1.3 Timer unit clock and period
The timer unit clock is derived from the 13.56 MHz on-board chip clock using the
programmable divider. Clock selection is made using the TimerClock register
TPreScaler[4:0] bits based on Equation 3:
(3)
The values for the TPreScaler[4:0] bits are between 0 and 21 which results in a minimum
periodic time (TTimerClock) of between 74 ns and 150 ms.
The time period elapsed since the last start event is calculated using Equation 4:
(4)
This results in a minimum time period (tTimer) of between 74 ns and 40 s.
9.5.1.4 Timer unit status
The SecondaryStatus register’s TRunning bit shows the timer’s status. Configured start
events start the timer at the TReloadValue[7:0] and changes the status flag TRunning to
logic 1. Conversely, configured stop events stop the timer and sets the TRunning status
flag to logic 0. As long as status flag TRunning is set to logic 1, the TimerValue register
changes on the next timer unit clock cycle.
The TimerValue[7:0] bits can be read directly from the TimerValue register.
fTimerClock
1
TTimerClock
--------------------------- 2
TPreScaler
13.56 = = -------------------------- MHz
tTimer
TReLoadValue TimerValue –
fTimerClock
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9.5.1.5 TimeSlotPeriod
When sending I-CODE1 Quit frames, it is necessary to generate the exact chronological
relationship to the start of the command frame.
If at the end of command execution TimeSlotPeriod > 0, the TimeSlotPeriod starts. If the
FIFO buffer contains data when the end of TimeSlotPeriod is reached, the data is sent. If
the FIFO buffer is empty nothing happens. As long as the TimeSlotPeriod is > 0, the
TimeSlotPeriod counter automatically starts on reaching the end.
This forms the exact time relationship between the start and finish of the command frame
used to generate and send I-CODE1 Quit frames.
When the TimeSlotPeriod > 0, the next Frame starts with exactly the same interval
TimeSlotPeriod/CoderRate delayed after each previous send frame. CoderRate defines
the clock frequency of the encoder. If TimeSlotPeriod[7:0] = 0, the send function is not
automatically triggered.
The content of the TimeSlotPeriod register can be changed while it is running but the
change is only effective after the next TimeSlotPeriod restart.
Example:
• CoderRate = 0 0.5 (~52.97 kHz)
• The interval should be 8.458 ms for I-CODE1 standard mode
Remark: The TimeSlotPeriodMSB bit is contained in the MFOUTSelect register.
Remark: Set bit TxCRCEn to logic 0 before the Quit frame is sent. If TxCRCEn is not set
to logic 0, the Quit frame is sent with a calculated CRC value. Use the CRC8 algorithm to
calculate the Quit value.
Fig 9. TimeSlotPeriod
Table 23. TimeSlotPeriod
I-CODE1 mode TimeSlotPeriod for TSP1 TimeSlotPeriod for TSP2
standard mode BFh 1BFh
fast mode 5Fh 67h
TimeSlotPeriod CoderRate Interval = = 52.97 kHz 8.458 ms – 1 447 1BFh = =
001aak612
COMMAND
RESPONSE1 RESPONSE2
TSP1 TSP2
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9.5.2 Using the timer unit functions
9.5.2.1 Time-out and WatchDog counters
After starting the timer using TReloadValue[7:0], the timer unit decrements the TimerValue
register beginning with a given start event. If a given stop event occurs, such as a bit
being received from the card, the timer unit stops without generating an interrupt.
If a stop event does not occur, such as the card not answering within the expected time,
the timer unit decrements down to zero and generates a timer interrupt request. This
signals to the microprocessor the expected event has not occurred within the given time
(tTimer).
9.5.2.2 Stopwatch
The time (tTimer) between a start and stop event is measured by the microprocessor using
the timer unit. Setting the TReloadValue register triggers the timer which in turn, starts to
decrement. If the defined stop event occurs, the timer stops. The time between start and
stop is calculated by the microprocessor using Equation 5, when the timer does not
decrement down to zero.
(5)
9.5.2.3 Programmable one shot timer and periodic trigger
Programmable one shot timer: The microprocessor starts the timer unit and waits for
the timer interrupt. The interrupt occurs after the time specified by tTimer.
Periodic trigger: If the microprocessor sets the TAutoRestart bit, it generates an interrupt
request after every tTimer cycle.
9.5.3 Timer unit registers
Table 24 shows the related flags of the timer unit in alphabetical order.
t TReLoadvalue – TimerValue tTimer =
Table 24. Associated timer unit registers and flags
Flags Register name Bit Register address
TAutoRestart TimerClock 5 2Ah
TimerValue[7:0] TimerValue 7 to 0 0Ch
TReloadValue[7:0] TimerReload 7 to 0 2Ch
TPreScaler[4:0] TimerClock 4 to 0 2Ah
TRunning SecondaryStatus 7 05h
TStartNow Control 1 09h
TStartTxBegin TimerControl 0 2Bh
TStartTxEnd TimerControl 1 2Bh
TStopNow Control 2 09h
TStopRxBegin TimerControl 2 2Bh
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9.6 Power reduction modes
9.6.1 Hard power-down
Hard power-down is enabled when pin RSTPD is HIGH. This turns off all internal current
sinks including the oscillator. All digital input buffers are separated from the input pads and
defined internally (except pin RSTPD itself). The output pins are frozen at a given value.
The status of all pins during a hard power-down is shown in Table 25.
9.6.2 Soft power-down mode
Soft power-down mode is entered immediately using the Control register bit PowerDown.
All internal current sinks, including the oscillator buffer, are switched off. The digital input
buffers are not separated from the input pads and keep their functionality. In addition, the
digital output pins do not change their state.
After resetting the Control register bit PowerDown, the bit indicating Soft power-down
mode is only cleared after 512 clock cycles. Resetting it does not immediately clear it. The
PowerDown bit is automatically cleared when the Soft power-down mode is exited.
Remark: When the internal oscillator is used, time (tosc) is required for the oscillator to
become stable. This is because the internal oscillator is supplied by VDDA and any clock
cycles will not be detected by the internal logic until VDDA is stable.
Table 25. Signal on pins during Hard power-down
Symbol Pin Type Description
OSCIN 1 I not separated from input, pulled to AVSS
IRQ 2 O high-impedance
MFIN 3 I separated from input
MFOUT 4 O LOW
TX1 5 O HIGH, if bit TX1RFEn = logic 1
LOW, if bit TX1RFEn = logic 0
TX2 7 O HIGH, only if bit TX2RFEn = logic 1 and bit
TX2Inv = logic 0
otherwise LOW
NCS 9 I separated from input
NWR 10 I separated from input
NRD 11 I separated from input
D0 to D7 13 to 20 I/O separated from input
ALE 21 I separated from input
A0 22 I/O separated from input
A1 23 I separated from input
A2 24 I separated from input
AUX 27 O high-impedance
RX 29 I not changed
VMID 30 A pulled to VDDA
RSTPD 31 I not changed
OSCOUT 32 O HIGHCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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9.6.3 Standby mode
The Standby mode is immediately entered when the Control register StandBy bit is set. All
internal current sinks, including the internal digital clock buffer are switched off. However,
the oscillator buffer is not switched off.
The digital input buffers are not separated by the input pads, keeping their functionality
and the digital output pins do not change their state. In addition, the oscillator does not
need time to wake-up.
After resetting the Control register StandBy bit, it takes four clock cycles on pin OSCIN for
Standby mode to exit. Resetting bit StandBy does not immediately clear it. It is
automatically cleared when the Standby mode is exited.
9.6.4 Automatic receiver power-down
It is a power saving feature to switch off the receiver circuit when it is not needed. Setting
bit RxAutoPD = logic 1, automatically powers down the receiver when it is not in use.
Setting bit RxAutoPD = logic 0, keeps the receiver continuously powered up.
9.7 StartUp phase
The events executed during the StartUp phase are shown in Figure 10.
9.7.1 Hard power-down phase
The hard power-down phase is active during the following cases:
• a Power-On Reset (POR) caused by power-up on pins DVDD or AVDD activated
when VDDD or VDDA is below the digital reset threshold.
• a HIGH-level on pin RSTPD which is active while pin RSTPD is HIGH. The HIGH level
period on pin RSTPD must be at least 100 s (tPD 100 s). Shorter phases will not
necessarily result in the reset phase (treset). The rising or falling edge slew rate on pin
RSTPD is not critical because pin RSTPD is a Schmitt trigger input.
9.7.2 Reset phase
The reset phase automatically follows the Hard power-down. Once the oscillator is
running stably, the reset phase takes 512 clock cycles. During the reset phase, some
register bits are preset by hardware. The respective reset values are given in the
description of each register (see Section 10.5 on page 50).
Remark: When the internal oscillator is used, time (tosc) is required for the oscillator to
become stable. This is because the internal oscillator is supplied by VDDA and any clock
cycles will not be detected by the internal logic until VDDA is stable.
Fig 10. The StartUp procedure
001aak613
StartUp phase
states
tRSTPD treset tinit
Hard powerdown
phase Reset phase Initialising
phase readyCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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9.7.3 Initialization phase
The initialization phase automatically follows the reset phase and takes 128 clock cycles.
During the initializing phase the content of the EEPROM blocks 1 and 2 is copied into the
register subaddresses 10h to 2Fh (see Section 9.2.2 on page 13).
Remark: During the production test, the CLRC632 is initialized with default configuration
values. This reduces the microprocessor’s configuration time to a minimum.
9.7.4 Initializing the parallel interface type
A different initialization sequence is used for each microprocessor. This enables detection
of the correct microprocessor interface type and synchronization of the microprocessor’s
and the CLRC632’s start-up. See Section 9.1.3 on page 8 for detailed information on the
different connections for each microprocessor interface type.
During StartUp phase, the command value is set to 3Fh once the oscillator attains clock
frequency stability at an amplitude of > 90 % of the nominal 13.56 MHz clock frequency. At
the end of the initialization phase, the CLRC632 automatically switches to idle and the
command value changes to 00h.
To ensure correct detection of the microprocessor interface, the following sequence is
executed:
• the Command register is read until the 6-bit register value is 00h. On reading the 00h
value, the internal initialization phase is complete and the CLRC632 is ready to be
controlled
• write 80h to the Page register to initialize the microprocessor interface
• read the Command register. If it returns a value of 00h, the microprocessor interface
was successfully initialized
• write 00h to the Page registers to activate linear addressing mode.
9.8 Oscillator circuit
The clock applied to the CLRC632 acts as a time basis for the synchronous system
encoder and decoder. The stability of the clock frequency is an important factor for correct
operation. To obtain highest performance, clock jitter must be as small as possible. This is
best achieved by using the internal oscillator buffer with the recommended circuitry.
Fig 11. Quartz clock connection
001aak614
13.56 MHz
15 pF 15 pF
OSCOUT OSCIN
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If an external clock source is used, the clock signal must be applied to pin OSCIN. In this
case, be very careful in optimizing clock duty cycle and clock jitter. Ensure the clock
quality has been verified. It must meet the specifications described in Section 13.4.5 on
page 106.
Remark: We do not recommend using an external clock source.
9.9 Transmitter pins TX1 and TX2
The signal on pins TX1 and TX2 is the 13.56 MHz energy carrier modulated by an
envelope signal. It can be used to drive an antenna directly, using minimal passive
components for matching and filtering (see Section 15.1 on page 107). To enable this, the
output circuitry is designed with a very low-impedance source resistance. The TxControl
register is used to control the TX1 and TX2 signals.
9.9.1 Configuring pins TX1 and TX2
TX1 pin configurations are described in Table 26.
TX2 pin configurations are described in Table 27.
Table 26. Pin TX1 configurations
TxControl register configuration Envelope TX1 signal
TX1RFEn FORCE100ASK
0 X X LOW (GND)
1 0 0 13.56 MHz carrier frequency modulated
1 0 1 13.56 MHz carrier frequency
1 1 0 LOW
1 1 1 13.56 MHz energy carrierCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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9.9.2 Antenna operating distance versus power consumption
Using different antenna matching circuits (by varying the supply voltage on the antenna
driver supply pin TVDD), it is possible to find the trade-off between maximum effective
operating distance and power consumption. Different antenna matching circuits are
described in the Application note “MIFARE Design of MFRC500 Matching Circuit and
Antennas”.
9.9.3 Antenna driver output source resistance
The output source conductance of pins TX1 and TX2 can be adjusted between 1 and
100 using the CwConductance register GsCfgCW[5:0] bits.
The output source conductance of pins TX1 and TX2 during the modulation phase can be
adjusted between 1 and 100 using the ModConductance register GsCfgMod[5:0] bits.
The values are relative to the reference resistance (RS(ref)) which is measured during the
production test and stored in the CLRC632 EEPROM. It can be read from the product
information field (see Section 9.2.1 on page 13). The electrical specification can be found
in Section 13.3.3 on page 101.
Table 27. Pin TX2 configurations
TxControl register configuration Envelope TX2 signal
TX2RFEn FORCE100ASK TX2CW TX2Inv
0 X X X X LOW
1 0 0 0 0 13.56 MHz carrier frequency
modulated
1 0 0 0 1 13.56 MHz carrier frequency
1 0 0 1 0 13.56 MHz carrier frequency
modulated, 180 phase-shift
relative to TX1
1 0 0 1 1 13.56 MHz carrier frequency,
180 phase-shift relative to TX1
1 0 1 0 X 13.56 MHz carrier frequency
1 0 1 1 X 13.56 MHz carrier frequency,
180 phase-shift relative to TX1
1 1 0 0 0 LOW
1 1 0 0 1 13.56 MHz carrier frequency
1 1 0 1 0 HIGH
1 1 0 1 1 13.56 MHz carrier frequency,
180 phase-shift relative to TX1
1 1 1 0 X 13.56 MHz carrier frequency
1 1 1 1 X 13.56 MHz carrier frequency,
180 phase-shift relative to TX1CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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9.9.3.1 Source resistance table
Table 28. TX1 and TX2 source resistance of n-channel driver transistor against GsCfgCW or GsCfgMod
MANT = Mantissa; EXP= Exponent.
GsCfgCW,
GsCfgMod
(decimal)
EXPGsCfgCW,
EXPGsCfgMod
(decimal)
MANTGsCfgCW,
MANTGsCfgMod
(decimal)
RS(ref)
()
GsCfgCW,
GsCfgMod
(decimal)
EXPGsCfgCW,
EXPGsCfgMod
(decimal)
MANTGsCfgCW,
MANTGsCfgMod
(decimal)
RS(ref)
()
0 0 0 - 24 1 8 0.0652
16 1 0 - 25 1 9 0.0580
32 2 0 - 37 2 5 0.0541
48 3 0 - 26 1 10 0.0522
1 0 1 1.0000 27 1 11 0.0474
17 1 1 0.5217 51 3 3 0.0467
2 0 2 0.5000 38 2 6 0.0450
3 0 3 0.3333 28 1 12 0.0435
33 2 1 0.2703 29 1 13 0.0401
18 1 2 0.2609 39 2 7 0.0386
4 0 4 0.2500 30 1 14 0.0373
5 0 5 0.2000 52 3 4 0.0350
19 1 3 0.1739 31 1 15 0.0348
6 0 6 0.1667 40 2 8 0.0338
7 0 7 0.1429 41 2 9 0.0300
49 3 1 0.1402 53 3 5 0.0280
34 2 2 0.1351 42 2 10 0.0270
20 1 4 0.1304 43 2 11 0.0246
8 0 8 0.1250 54 3 6 0.0234
9 0 9 0.1111 44 2 12 0.0225
21 1 5 0.1043 45 2 13 0.0208
10 0 10 0.1000 55 3 7 0.0200
11 0 11 0.0909 46 2 14 0.0193
35 2 3 0.0901 47 2 15 0.0180
22 1 6 0.0870 56 3 8 0.0175
12 0 12 0.0833 57 3 9 0.0156
13 0 13 0.0769 58 3 10 0.0140
23 1 7 0.0745 59 3 11 0.0127
14 0 14 0.0714 60 3 12 0.0117
50 3 2 0.0701 61 3 13 0.0108
36 2 4 0.0676 62 3 14 0.0100
15 0 15 0.0667 63 3 15 0.0093CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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9.9.3.2 Calculating the relative source resistance
The reference source resistance RS(ref) can be calculated using Equation 6.
(6)
The reference source resistance (RS(ref)) during the modulation phase can be calculated
using ModConductance register’s GsCfgMod[5:0].
9.9.3.3 Calculating the effective source resistance
Wiring resistance (RS(wire)): Wiring and bonding add a constant offset to the driver
resistance that is relevant when pins TX1 and TX2 are switched to low-impedance. The
additional resistance for pin TX1 (RS(wire)TX1) can be set approximately as shown in
Equation 7.
(7)
Effective resistance (RSx): The source resistances of the driver transistors (RsMaxP
byte) read from the Product Information Field (see Section 9.2.1 on page 13) are
measured during the production test with CwConductance register’s
GsCfgCW[5:0] = 01h.
To calculate the driver resistance for a specific value set in GsCfgMod[5:0], use
Equation 8.
(8)
9.9.4 Pulse width
The envelope carries the data signal information that is transmitted to the card. It is an
encoded data signal based on the Miller code. In addition, each pause of the Miller
encoded signal is again encoded as a pulse of a fixed width. The width of the pulse is
adjusted using the ModWidth register. The pulse width (tw) is calculated using Equation 9
where the frequency constant (fclk) = 13.56 MHz.
(9)
9.10 Receiver circuitry
The CLRC632 uses an integrated quadrature demodulation circuit enabling it to detect an
ISO/IEC 14443 A or ISO/IEC 14443 B compliant subcarrier signal on pin RX.
• ISO/IEC 14443 A subcarrier signal: defined as a Manchester coded ASK modulated
signal
• ISO/IEC 14443 B subcarrier signal: defined as an NRZ-L coded BPSK modulated
ISO/IEC 14443 B subcarrier signal
RS ref
1
MANTGsCfgCW
77
40
----- EXPGsCfgCW
= --------------------------------------------------------------------------------
RS wire TX1 500 m
RSx RS ref maxP RS wire TX1 – RS rel RS wire TX1 = +
tw 2ModWidth 1 +
fc
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The quadrature demodulator uses two different clocks (Q-clock and I-clock) with a
phase-shift of 90 between them. Both resulting subcarrier signals are amplified, filtered
and forwarded to the correlation circuitry. The correlation results are evaluated, digitized
and then passed to the digital circuitry. Various adjustments can be made to obtain
optimum performance for all processing units.
9.10.1 Receiver circuit block diagram
Figure 12 shows the block diagram of the receiver circuit. The receiving process can be
broken down in to several steps. Quadrature demodulation of the 13.56 MHz carrier signal
is performed. To achieve the optimum performance, automatic Q-clock calibration is
recommended (see Section 9.10.2.1 on page 35).
The demodulated signal is amplified by an adjustable amplifier. A correlation circuit
calculates the degree of similarity between the expected and the received signal. The
BitPhase register enables correlation interval position alignment with the received signal’s
bit grid. In the evaluation and digitizer circuitry, the valid bits are detected and the digital
results are sent to the FIFO buffer. Several tuning steps are possible for this circuit.
The signal can be observed on its way through the receiver as shown in Figure 12. One
signal at a time can be routed to pin AUX using the TestAnaSelect register as described in
Section 15.2.2 on page 112.
9.10.2 Receiver operation
In general, the default settings programmed in the StartUp initialization file are suitable for
use with the CLRC632 to MIFARE card data communication. However, in some
environments specific user settings will achieve better performance.
9.10.2.1 Automatic Q-clock calibration
The quadrature demodulation concept of the receiver generates a phase signal (I-clock)
and a 90 phase-shifted quadrature signal (Q-clock). To achieve the optimum
demodulator performance, the Q-clock and the I-clock must be phase-shifted by 90. After
the reset phase, a calibration procedure is automatically performed.
Fig 12. Receiver circuit block diagram
001aak615
ClkQDelay[4:0]
ClkQCalib
ClkQ180Deg
BitPhase[7:0]
CORRELATION
CIRCUITRY
EVALUATION
AND
DIGITIZER
CIRCUITRY
MinLevel[3:0]
CollLevel[3:0]
RxWait[7:0]
RcvClkSell
s_valid
s_data
s_coll
s_clock
Gain[1:0]
to
TestAnaOutSel
clock
I TO Q
CONVERSION
I-clock Q-clock
13.56 MHz
DEMODULATOR RX
VCorrDI
VCorrNI
VCorrDQ
VCorrNQ
VEvalR
VEvalL
VRxFollQ
VRxFollI VRxAmpI
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Automatic calibration can be set-up to execute at the end of each Transceive command if
bit ClkQCalib = logic 0. Setting bit ClkQCalib = logic 1 disables all automatic calibrations
except after the reset sequence. Automatic calibration can also be triggered by the
software when bit ClkQCalib has a logic 0 to logic 1 transition.
Remark: The duration of the automatic Q-clock calibration is 65 oscillator periods or
approximately 4.8 s.
The ClockQControl register’s ClkQDelay[4:0] value is proportional to the phase-shift
between the Q-clock and the I-clock. The ClkQ180Deg status flag bit is set when the
phase-shift between the Q-clock and the I-clock is greater than 180.
Remark:
• The StartUp configuration file enables automatic Q-clock calibration after a reset
• If bit ClkQCalib = logic 1, automatic calibration is not performed. Leaving this bit set to
logic 1 can be used to permanently disable automatic calibration.
• It is possible to write data to the ClkQDelay[4:0] bits using the microprocessor. The
aim could be to disable automatic calibration and set the delay using the software.
Configuring the delay value using the software requires bit ClkQCalib to have been
previously set to logic 1 and a time interval of at least 4.8 s has elapsed. Each delay
value must be written with bit ClkQCalib set to logic 1. If bit ClkQCalib is logic 0, the
configured delay value is overwritten by the next automatic calibration interval.
9.10.2.2 Amplifier
The demodulated signal must be amplified by the variable amplifier to achieve the best
performance. The gain of the amplifiers can be adjusted using the RxControl1 register
Gain[1:0] bits; see Table 29.
Fig 13. Automatic Q-clock calibration
001aak616
calibration impulse
from reset sequence a rising edge initiates
Q-clock calibration
ClkQCalib bit
calibration impulse
from end of
Transceive command
Table 29. Gain factors for the internal amplifier
See Table 86 “RxControl1 register bit descriptions” on page 64 for additional information.
Register setting Gain factor [dB]
(simulation results)
00 20
01 24
10 31
11 35CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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9.10.2.3 Correlation circuitry
The correlation circuitry calculates the degree of matching between the received and an
expected signal. The output is a measure of the amplitude of the expected signal in the
received signal. This is done for both, the Q and I-channels. The correlator provides two
outputs for each of the two input channels, resulting in a total of four output signals.
The correlation circuitry needs the phase information for the incoming card signal for
optimum performance. This information is defined for the microprocessor using the
BitPhase register. This value defines the phase relationship between the transmitter and
receiver clock in multiples of the BitPhase time (tBitPhase) = 1 / 13.56 MHz.
9.10.2.4 Evaluation and digitizer circuitry
The correlation results are evaluated for each bit-half of the Manchester coded signal. The
evaluation and digitizer circuit decides from the signal strengths of both bit-halves, if the
current bit is valid
• If the bit is valid, its value is identified
• If the bit is not valid, it is checked to identify if it contains a bit-collision
Select the following levels for optimal using RxThreshold register bits:
• MinLevel[3:0]: defines the minimum signal strength of the stronger bit-halve’s signal
which is considered valid.
• CollLevel[3:0]: defines the minimum signal strength relative to the amplitude of the
stronger half-bit that has to be exceeded by the weaker half-bit of the Manchester
coded signal to generate a bit-collision. If the signal’s strength is below this value,
logic 1 and logic 0 can be determined unequivocally.
After data transmission, the card is not allowed to send its response before a preset time
period which is called the frame guard time in the ISO/IEC 14443 standard. The length of
this time period is set using the RxWait register’s RxWait[7:0] bits. The RxWait register
defines when the receiver is switched on after data transmission to the card in multiples of
one bit duration.
If bit RcvClkSelI is set to logic 1, the I-clock is used to clock the correlator and evaluation
circuits. If bit RcvClkSelI is set to logic 0, the Q-clock is used.
Remark: It is recommended to use the Q-clock.
9.11 Serial signal switch
The CLRC632 comprises two main blocks:
• digital circuitry: comprising the state machines, encoder and decoder logic etc.
• analog circuitry: comprising the modulator, antenna drivers, receiver and
amplification circuitry
The interface between these two blocks can be configured so that the interface signals
are routed to pins MFIN and MFOUT. This makes it possible to connect the analog part of
one CLRC632 to the digital part of another device.
The serial signal switch can be used to measure MIFARE and ISO/IEC 14443 A as well as
related I-CODE1 and ISO/IEC 15693 signals.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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Remark: Pin MFIN can only be accessed at 106 kBd based on ISO/IEC 14443 A. The
Manchester signal and the Manchester signal with subcarrier can only be accessed on pin
MFOUT at 106 kBd based on ISO/IEC 14443 A.
9.11.1 Serial signal switch block diagram
Figure 14 shows the serial signal switches. Three different switches are implemented in
the serial signal switch enabling the CLRC632 to be used in different configurations.
The serial signal switch can also be used to check the transmitted and received data
during the design-in phase or for test purposes. Section 15.2.1 on page 110 describes the
analog test signals and measurements at the serial signal switch.
Remark: The SLR400 uses pin name SIGOUT for pin MFOUT. The CLRC632
functionality includes the test modes for the SLRC400 using pin MFOUT.
Section 9.11.2, Section 9.11.2.1 and Section 9.11.2.2 describe the relevant registers and
settings used to configure and control the serial signal switch.
9.11.2 Serial signal switch registers
The RxControl2 register DecoderSource[1:0] bits define the input signal for the internal
Manchester decoder and are described in Table 30.
Fig 14. Serial signal switch block diagram
3
MFIN MFOUT 001aak617
MODULATOR DRIVER
(part of)
analog circuitry
SUBCARRIER
DEMODULATOR
TX1
TX2
RX CARRIER
DEMODULATOR
2
MILLER CODER
1 OUT OF 256
NRZ OR
1 OUT OF 4
MANCHESTER
DECODER
SERIAL SIGNAL SWITCH
(part of)
serial data processing
Decoder
Source[1:0]
2
Modulator
Source[1:0]
SUBCARRIER
DEMODULATOR
serial data out
0 0
1 internal
2 Manchester with subcarrier
3
0
1
2
3
4
5
6
0
1
envelope
MFIN
0
1
2
3
Manchester
Manchester out
serial data in
7
0
0 1
1
envelope
transmit NRZ
Manchester with subcarrier
Manchester
reserved
reserved
MFOUTSelect[2:0]
digital test signal
signal to MFOUTCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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The TxControl register ModulatorSource[1:0] bits define the signal used to modulate the
transmitted 13.56 MHz energy carrier. The modulated signal drives pins TX1 and TX2.
The MFOUTSelect register MFOUTSelect[2:0] bits select the output signal which is to be
routed to pin MFOUT.
To use the MFOUTSelect[2:0] bits, the TestDigiSelect register SignalToMFOUT bit must
be logic 0.
9.11.2.1 Active antenna concept
The CLRC632 analog and digital circuitry is accessed using pins MFIN and MFOUT.
Table 33 lists the required settings.
Table 30. DecoderSource[1:0] values
See Table 96 on page 67 for additional information.
Number DecoderSource
[1:0]
Input signal to decoder
0 00 constant 0
1 01 output of the analog part. This is the default configuration
2 10 direct connection to pin MFIN; expects an 847.5 kHz subcarrier
signal modulated by a Manchester encoded signal
3 11 direct connection to pin MFIN; expects a Manchester encoded
signal
Table 31. ModulatorSource[1:0] values
See Table 96 on page 67 for additional information.
Number ModulatorSource
[1:0]
Input signal to modulator
0 00 constant 0 (energy carrier off on pins TX1 and TX2)
1 01 constant 1 (continuous energy carrier on pins TX1 and TX2)
2 10 modulation signal (envelope) from the internal encoder. This is the
default configuration.
3 11 direct connection to MFIN; expects a Miller pulse coded signal
Table 32. MFOUTSelect[2:0] values
See Table 110 on page 70 for additional information.
Number MFOUTSelect
[2:0]
Signal routed to pin MFOUT
0 000 constant LOW
1 001 constant HIGH
2 010 modulation signal (envelope) from the internal encoder
3 011 serial data stream to be transmitted; the same as for
MFOUTSelect[2:0] = 001 but not encoded by the selected pulse
encoder
4 100 output signal of the receiver circuit; card modulation signal
regenerated and delayed
5 101 output signal of the subcarrier demodulator; Manchester coded card
signal
6 110 reserved
7 111 reservedCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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[1] The number column refers to the value in the number column of Table 30, Table 31 and Table 32.
Two CLRC632 devices configured as described in Table 33 can be connected to each
other using pins MFOUT and MFIN.
Remark: The active antenna concept can only be used at 106 kBd based on
ISO/IEC 14443 A.
9.11.2.2 Driving both RF parts
It is possible to connect both passive and active antennas to a single IC. The passive
antenna pins TX1, TX2 and RX are connected using the appropriate filter and matching
circuit. At the same time an active antenna is connected to pins MFOUT and MFIN. In this
configuration, two RF parts can be driven, one after another, by one microprocessor.
9.12 MIFARE higher baud rates
The MIFARE system is specified with a fixed baud rate of 106 kBd for communication on
the RF interface. The current version of ISO/IEC 14443 A also defines 106 kBd for the
initial phase of a communication between Proximity Integrated Circuit Cards (PICC) and
Proximity Coupling Devices (PCD).
To cover requirements of large data transmissions and to speed up terminal to card
communication, the CLRC632 supports communication at MIFARE higher baud rates in
combination with a microcontroller IC such as the MIFARE ProX.
The MIFARE higher baud rates concept is described in the application note: MIFARE
Implementation of Higher Baud rates Ref. 5. This application covers the integration of the
MIFARE higher baud rates communication concept in current applications.
Table 33. Register settings to enable use of the analog circuitry
Register Number[1] Signal CLRC632 pin
Analog circuitry settings
ModulatorSource 3 Miller pulse encoded MFIN
MFOUTSelect 4 Manchester encoded with subcarrier MFOUT
DecoderSource X - -
Digital circuitry settings
ModulatorSource X - -
MFOUTSelect 2 Miller pulse encoded MFOUT
DecoderSource 2 Manchester encoded with subcarrier MFIN
Table 34. MIFARE higher baud rates
Communication direction Baud rates (kBd)
CLRC632 based PCD microcontroller PICC supporting higher baud rates 106, 212, 424
Microcontroller PICC supporting higher baud rates CLRC632 based PCD 106, 212, 424CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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9.13 ISO/IEC 14443 B communication scheme
The international standard ISO/IEC 14443 covers two communication schemes; ISO/IEC
14443 A and ISO/IEC 14443 B. The CLRC632 reader IC fully supports both ISO/IEC
14443 variants.
Table 35 describes the registers and flags covered by the ISO/IEC 14443 B
communication protocol.
As reference documentation, the international standard ISO/IEC 14443 Identification
cards - Contactless integrated circuit(s) cards - Proximity cards, part 1-4 (Ref. 4) can be
used.
Remark: NXP Semiconductors does not offer a basic function library to design-in the
ISO/IEC 14443 B protocol.
Table 35. ISO/IEC 14443 B registers and flags
Flag Register Bit Register address
CharSpacing[2:0] TypeBFraming 4 to 2 17h
CoderRate[2:0] CoderControl 5 to 3 14h
EOFWidth TypeBFraming 5 17h
FilterAmpDet BPSKDemControl 4 1Dh
Force100ASK TxControl 4 11h
GsCfgCW[5:0] CwConductance 5 to 0 12h
GsCfgMod[5:0] ModConductance 5 to 0 13h
MinLevel[3:0] RxThreshold 7 to 4 1Ch
NoTxEOF TypeBFraming 6 17h
NoTxSOF TypeBFraming 7 17h
NoRxEGT BPSKDemControl 6 1Dh
NoRxEOF BPSKDemControl 5 1Dh
NoRxSOF BPSKDemControl 7 1Dh
RxCoding DecoderControl 0 1Ah
RxFraming[1:0] DecoderControl 4 to 3 1Ah
SOFWidth[1:0] TypeBFraming 1 to 0 17h
SubCPulses[2:0] RxControl1 7 to 5 19h
TauB[1:0] BPSKDemControl 1 to 0 1Dh
TauD[1:0] BPSKDemControl 3 to 2 1Dh
TxCoding[2:0] CoderControl 2 to 0 14hCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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9.14 MIFARE authentication and Crypto1
The security algorithm used in the MIFARE products is called Crypto1. It is based on a
proprietary stream cipher with a 48-bit key length. To access data on MIFARE cards,
knowledge of the key format is needed. The correct key must be available in the
CLRC632 to enable successful card authentication and access to the card’s data stored in
the EEPROM.
After a card is selected as defined in ISO/IEC 14443 A standard, the user can continue
with the MIFARE protocol. It is mandatory that card authentication is performed.
Crypto1 authentication is a 3-pass authentication which is automatically performed when
the Authent1 and Authent2 commands are executed (see Section 11.7.3 on page 98 and
Section 11.7.4 on page 98).
During the card authentication procedure, the security algorithm is initialized. After a
successful authentication, communication with the MIFARE card is encrypted.
9.14.1 Crypto1 key handling
On execution of the authentication command, the CLRC632 reads the key from the key
buffer. The key is always read from the key buffer and ensures Crypto1 authentication
commands do not require addressing of a key. The user must ensure the correct key is
prepared in the key buffer before triggering card authentication.
The key buffer can be loaded from:
• the EEPROM using the LoadKeyE2 command (see Section 11.7.1 on page 97)
• the microprocessor’s FIFO buffer using the LoadKey command (see Section 11.7.2
on page 97). This is shown in Figure 15.
Fig 15. Crypto1 key handling block diagram
001aak624
FIFO BUFFER
from the microcontroller
WriteE2
LoadKey
EEPROM
KEYS
KEY BUFFER
LoadKeyE2
during
Authent1
CRYPTO1
MODULE
serial data stream in serial data stream out
(plain) (encrypted)CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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9.14.2 Authentication procedure
The Crypto1 security algorithm enables authentication of MIFARE cards. To obtain valid
authentication, the correct key has to be available in the key buffer of the CLRC632. This
can be ensured as follows:
1. Load the internal key buffer by using the LoadKeyE2 (see Section 11.7.1 on page 97)
or the LoadKey (see Section 11.7.2 on page 97) commands.
2. Start the Authent1 command (see Section 11.7.3 on page 98). When finished, check
the error flags to obtain the command execution status.
3. Start the Authent2 command (see Section 11.7.4 on page 98). When finished, check
the error flags and bit Crypto1On to obtain the command execution status.
10. CLRC632 registers
10.1 Register addressing modes
Three methods can be used to operate the CLRC632:
• initiating functions and controlling data by executing commands
• configuring the functional operation using a set of configuration bits
• monitoring the state of the CLRC632 by reading status flags
The commands, configuration bits and flags are accessed using the microprocessor
interface. The CLRC632 can internally address 64 registers using six address lines.
10.1.1 Page registers
The CLRC632 register set is segmented into eight pages contain eight registers each. A
Page register can always be addressed, irrespective of which page is currently selected.
10.1.2 Dedicated address bus
When using the CLRC632 with the dedicated address bus, the microprocessor defines
three address lines using address pins A0, A1 and A2. This enables addressing within a
page. To switch between registers in different pages a paging mechanism needs to be
used.
Table 36 shows how the register address is assembled.
10.1.3 Multiplexed address bus
The microprocessor may define all six address lines at once using the CLRC632 with a
multiplexed address bus. In this case either the paging mechanism or linear addressing
can be used.
Table 37 shows how the register address is assembled.
Table 36. Dedicated address bus: assembling the register address
Register bit: UsePageSelect Register address
1 PageSelect2 PageSelect1 PageSelect0 A2 A1 A0CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.2 Register bit behavior
Bits and flags for different registers behave differently, depending on their functions. In
principle, bits with same behavior are grouped in common registers. Table 38 describes
the function of the Access column in the register tables.
Table 37. Multiplexed address bus: assembling the register address
Multiplexed
address bus
type
UsePage
Select
Register address
Paging mode 1 PageSelect2 PageSelect1 PageSelect0 AD2 AD1 AD0
Linear
addressing
0 AD5 AD4 AD3 AD2 AD1 AD0
Table 38. Behavior and designation of register bits
Abbreviation Behavior Description
R/W read and write These bits can be read and written by the microprocessor.
Since they are only used for control, their content is not
influenced by internal state machines.
Example: TimerReload register may be read and written by
the microprocessor. It will also be read by internal state
machines but never changed by them.
D dynamic These bits can be read and written by the microprocessor.
Nevertheless, they may also be written automatically by
internal state machines.
Example: the Command register changes its value
automatically after the execution of the command.
R read only These registers hold flags which have a value determined by
internal states only.
Example: the ErrorFlag register cannot be written externally
but shows internal states.
W write only These registers are used for control only. They may be written
by the microprocessor but cannot be read. Reading these
registers returns an undefined value.
Example: The TestAnaSelect register is used to determine the
signal on pin AUX however, it is not possible to read its
content.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.3 Register overview
Table 39. CLRC632 register overview
Sub
address
(Hex)
Register name Function Refer to
Page 0: Command and status
00h Page selects the page register Table 41 on page 50
01h Command starts and stops command execution Table 43 on page 50
02h FIFOData input and output of 64-byte FIFO buffer Table 45 on page 51
03h PrimaryStatus receiver and transmitter and FIFO buffer status flags Table 47 on page 51
04h FIFOLength number of bytes buffered in the FIFO buffer Table 49 on page 52
05h SecondaryStatus secondary status flags Table 51 on page 53
06h InterruptEn enable and disable interrupt request control bits Table 53 on page 53
07h InterruptRq interrupt request flags Table 55 on page 54
Page 1: Control and status
08h Page selects the page register Table 41 on page 50
09h Control control flags for timer unit, power saving etc Table 57 on page 55
0Ah ErrorFlag show the error status of the last command executed Table 59 on page 55
0Bh CollPos bit position of the first bit-collision detected on the RF interface Table 61 on page 56
0Ch TimerValue value of the timer Table 63 on page 57
0Dh CRCResultLSB LSB of the CRC coprocessor register Table 65 on page 57
0Eh CRCResultMSB MSB of the CRC coprocessor register Table 67 on page 57
0Fh BitFraming adjustments for bit oriented frames Table 69 on page 58
Page 2: Transmitter and coder control
10h Page selects the page register Table 41 on page 50
11h TxControl controls the operation of the antenna driver pins TX1 and TX2 Table 71 on page 59
12h CwConductance selects the conductance of the antenna driver pins TX1 and TX2 Table 73 on page 60
13h ModConductance defines the driver output conductance Table 75 on page 60
14h CoderControl sets the clock frequency and the encoding Table 77 on page 61
15h ModWidth selects the modulation pulse width Table 79 on page 62
16h ModWidthSOF selects the SOF pulse-width modulation (I-CODE1 fast mode) Table 81 on page 62
17h TypeBFraming defines the framing for ISO/IEC 14443 B communication Table 83 on page 63
Page 3: Receiver and decoder control
18 Page selects the page register Table 41 on page 50
19 RxControl1 controls receiver behavior Table 85 on page 64
1A DecoderControl controls decoder behavior Table 87 on page 65
1B BitPhase selects the bit-phase between transmitter and receiver clock Table 89 on page 65
1C RxThreshold selects thresholds for the bit decoder Table 91 on page 66
1D BPSKDemControl controls BPSK receiver behavior Table 93 on page 66
1Eh RxControl2 controls decoder and defines the receiver input source Table 95 on page 67
1Fh ClockQControl clock control for the 90 phase-shifted Q-channel clock Table 97 on page 67CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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Page 4: RF Timing and channel redundancy
20h Page selects the page register Table 41 on page 50
21h RxWait selects the interval after transmission before the receiver starts Table 99 on page 68
22h ChannelRedundancy selects the method and mode used to check data integrity on
the RF channel
Table 101 on page 68
23h CRCPresetLSB preset LSB value for the CRC register Table 103 on page 69
24h CRCPresetMSB preset MSB value for the CRC register Table 105 on page 69
25h TimeSlotPeriod selects the time between automatically transmitted frames Table 107 on page 69
26h MFOUTSelect selects internal signal applied to pin MFOUT, includes the MSB
of value TimeSlotPeriod; see Table 107 on page 69
Table 109 on page 70
27h PreSet27 these values are not changed Table 111 on page 70
Page 5: FIFO, timer and IRQ pin configuration
28h Page selects the page register Table 41 on page 50
29h FIFOLevel defines the FIFO buffer overflow and underflow warning levels Table 49 on page 52
2Ah TimerClock selects the timer clock divider Table 114 on page 71
2Bh TimerControl selects the timer start and stop conditions Table 116 on page 72
2Ch TimerReload defines the timer preset value Table 118 on page 72
2Dh IRQPinConfig configures pin IRQ output stage Table 120 on page 73
2Eh PreSet2E these values are not changed Table 122 on page 73
2Fh PreSet2F these values are not changed Table 123 on page 73
Page 6: reserved registers
30h Page selects the page register Table 41 on page 50
31h reserved reserved Table 124 on page 73
32h reserved reserved
33h reserved reserved
34h reserved reserved
35h reserved reserved
36h reserved reserved
37h reserved reserved
Page 7: Test control
38h Page selects the page register Table 41 on page 50
39h reserved reserved Table 125 on page 74
3Ah TestAnaSelect selects analog test mode Table 126 on page 74
3Bh reserved reserved Table 128 on page 75
3Ch reserved reserved Table 129 on page 75
3Dh TestDigiSelect selects digital test mode Table 130 on page 75
3Eh reserved reserved Table 132 on page 76
3Fh reserved reserved
Table 39. CLRC632 register overview …continued
Sub
address
(Hex)
Register name Function Refer toCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.4 CLRC632 register flags overview
Table 40. CLRC632 register flags overview
Flag(s) Register Bit Address
AccessErr ErrorFlag 5 0Ah
BitPhase[7:0] BitPhase 7 to 0 1Bh
CharSpacing[2:0] TypeBFraming 4 to 2 17h,
ClkQ180Deg ClockQControl 7 1Fh
ClkQCalib ClockQControl 6 1Fh
ClkQDelay[4:0] ClockQControl 4 to 0 1Fh
CoderRate[2:0] CoderControl 5 to 3 14h
CollErr ErrorFlag 0 0Ah
CollLevel[3:0] RxThreshold 3 to 0 1Ch
CollPos[7:0] CollPos 7 to 0 0Bh
Command[5:0] Command 5 to 0 01h
CRC3309 ChannelRedundancy 5 22h
CRC8 ChannelRedundancy 4 22h
CRCErr ErrorFlag 3 0Ah
CRCPresetLSB[7:0] CRCPresetLSB 7 to 0 23h
CRCPresetMSB[7:0] CRCPresetMSB 7 to 0 24h
CRCReady SecondaryStatus 5 05h
CRCResultMSB[7:0] CRCResultMSB 7 to 0 0Eh
CRCResultLSB[7:0] CRCResultLSB 7 to 0 0Dh
Crypto1On Control 3 09h
DecoderSource[1:0] RxControl2 1 to 0 1Eh
E2Ready SecondaryStatus 6 05h
EOFWidth TypeBFraming 5 17h
Err PrimaryStatus 2 03h
FIFOData[7:0] FIFOData 7 to 0 02h
FIFOLength[6:0] FIFOLength 6 to 0 04h
FIFOOvfl ErrorFlag 4 0Ah
FilterAmpDet BPSKDemControl 4 1Dh
FlushFIFO Control 0 09h
Force100ASK TxControl 4 11h
FramingErr ErrorFlag 2 0Ah
Gain[1:0] RxControl1 1 to 0 19h
GsCfgCW[5:0] CwConductance 5 to 0 12h
GsCfgMod[5:0] ModConductance 5 to 0 13h
HiAlert PrimaryStatus 1 03h
HiAlertIEn InterruptEn 1 06h
HiAlertIRq InterruptRq 1 07h
IdleIEn InterruptEn 2 06h
IdleIRq InterruptRq 2 07hCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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IFDetectBusy Command 7 01h
IRq PrimaryStatus 3 03h
IRQInv IRQPinConfig 1 2Dh
IRQPushPull IRQPinConfig 0 2Dh
ISO Selection[1:0] RxControl1 4 to 3 19h
KeyErr ErrorFlag 6 0Ah
LoAlert PrimaryStatus 0 03h
LoAlertIEn InterruptEn 0 06h
LoAlertIRq InterruptRq 0 07h
LPOff RxControl1 2 19h
MFOUTSelect[2:0] MFOUTSelect 2 to 0 26h
MinLevel[3:0] RxThreshold 7 to 4 1Ch
ModemState[2:0] PrimaryStatus 6 to 4 03h
ModulatorSource[1:0] TxControl 6 to 5 11h
ModWidth[7:0] ModWidth 7 to 0 15h
NoRxEGT BPSKDemControl 6 1Dh
NoRxEOF BPSKDemControl 5 1Dh
NoRxSOF BPSKDemControl 7 1Dh
NoTxEOF TypeBFraming 6 17h
NoTxSOF TypeBFraming 7 17h
PageSelect[2:0] Page 2 to 0 00h, 08h, 10h, 18h, 20h, 28h, 30h
and 38h
ParityEn ChannelRedundancy 0 22h
ParityErr ErrorFlag 1 0Ah
ParityOdd ChannelRedundancy 1 22h
PowerDown Control 4 09h
RcvClkSelI RxControl2 7 1Eh
RxAlign[2:0] BitFraming 6 to 4 0Fh
RxAutoPD RxControl2 6 1Eh
RxCRCEn ChannelRedundancy 3 22h
RxCoding DecoderControl 0 1Ah
RxFraming[1:0] DecoderControl 4 to 3 1Ah
RxIEn InterruptEn 3 06h
RxIRq InterruptRq 3 07h
RxLastBits[2:0] SecondaryStatus 2 to 0 05h
RxMultiple DecoderControl 6 1Ah
RxWait[7:0] RxWait 7 to 0 21h
SetIEn InterruptEn 7 06h
SetIRq InterruptRq 7 07h
SignalToMFOUT TestDigiSelect 7 3Dh
SOFWidth[1:0] TypeBFraming 1 to 0 17h
Table 40. CLRC632 register flags overview …continued
Flag(s) Register Bit AddressCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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StandBy Control 5 09h
SubCPulses[2:0] RxControl1 7 to 5 19h
TauB[1:0] BPSKDemControl 1 to 0 1Dh
TauD[1:0] BPSKDemControl 3 to 2 1Dh
TAutoRestart TimerClock 5 2Ah
TestAnaOutSel[4:0] TestAnaSelect 3 to 0 3Ah
TestDigiSignalSel[6:0] TestDigiSelect 6 to 0 3Dh
TimerIEn InterruptEn 5 06h
TimerIRq InterruptRq 5 07h
TimerValue[7:0] TimerValue 7 to 0 0Ch
TimeSlotPeriod[7:0] TimeSlotPeriod 7 to 0 25h
TimeSlotPeriodMSB MFOUTSelect 4 26h
TPreScaler[4:0] TimerClock 4 to 0 2Ah
TReloadValue[7:0] TimerReload 7 to 0 2Ch
TRunning SecondaryStatus 7 05h
TStartTxBegin TimerControl 0 2Bh
TStartTxEnd TimerControl 1 2Bh
TStartNow Control 1 09h
TStopRxBegin TimerControl 2 2Bh
TStopRxEnd TimerControl 3 2Bh
TStopNow Control 2 09h
TX1RFEn TxControl 0 11h
TX2Cw TxControl 3 11h
TX2Inv TxControl 3 11h
TX2RFEn TxControl 1 11h
TxCoding[2:0] CoderControl 2 to 0 14h
TxCRCEn ChannelRedundancy 2 22h
TxIEn InterruptEn 4 06h
TxIRq InterruptRq 4 07h
TxLastBits[2:0] BitFraming 2 to 0 0Fh
UsePageSelect Page 7 00h, 08h, 10h, 18h, 20h, 28h, 30h
and 38h
WaterLevel[5:0] FIFOLevel 5 to 0 29h
ZeroAfterColl DecoderControl 7 1Ah, bit 5
Table 40. CLRC632 register flags overview …continued
Flag(s) Register Bit AddressCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.5 Register descriptions
10.5.1 Page 0: Command and status
10.5.1.1 Page register
Selects the page register.
10.5.1.2 Command register
Starts and stops the command execution.
Table 41. Page register (address: 00h, 08h, 10h, 18h, 20h, 28h, 30h, 38h)
reset value: 1000 0000b, 80h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol UsePageSelect 0000 PageSelect[2:0]
Access R/W R/W R/W R/W R/W
Table 42. Page register bit descriptions
Bit Symbol Value Description
7 UsePageSelect 1 the value of PageSelect[2:0] is used as the register address
A5, A4, and A3. The LSBs of the register address are
defined using the address pins or the internal address latch,
respectively.
0 the complete content of the internal address latch defines
the register address. The address pins are used as
described in Table 5 on page 8.
6 to 3 0000 - reserved
2 to 0 PageSelect[2:0] - when UsePageSelect = logic 1, the value of PageSelect is
used to specify the register page (A5, A4 and A3 of the
register address)
Table 43. Command register (address: 01h) reset value: x000 0000b, x0h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol IFDetectBusy 0 Command[5:0]
Access R R D
Table 44. Command register bit descriptions
Bit Symbol Value Description
7 IFDetectBusy - shows the status of interface detection logic
0 interface detection finished successfully
1 interface detection ongoing
6 0 - reserved
5 to 0 Command[5:0] - activates a command based on the Command code.
Reading this register shows which command is being
executed.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.5.1.3 FIFOData register
Input and output of the 64 byte FIFO buffer.
10.5.1.4 PrimaryStatus register
Bits relating to receiver, transmitter and FIFO buffer status flags.
Table 45. FIFOData register (address: 02h) reset value: xxxx xxxxb, 05h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol FIFOData[7:0]
Access D
Table 46. FIFOData register bit descriptions
Bit Symbol Description
7 to 0 FIFOData[7:0] data input and output port for the internal 64-byte FIFO buffer. The FIFO
buffer acts as a parallel in to parallel out converter for all data streams.
Table 47. PrimaryStatus register (address: 03h) reset value: 0000 0101b, 05h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol 0 ModemState[2:0] IRq Err HiAlert LoAlert
Access R R R R R R
Table 48. PrimaryStatus register bit descriptions
Bit Symbol Value Status Description
7 0 - reserved
6 to 4 ModemState[2:0] shows the state of the transmitter and receiver
state machines:
000 Idle neither the transmitter or receiver are operating;
neither of them are started or have input data
001 TxSOF transmit start of frame pattern
010 TxData transmit data from the FIFO buffer (or
redundancy CRC check bits)
011 TxEOF transmit End Of Frame (EOF) pattern
100 GoToRx1 intermediate state 1; receiver starts
GoToRx2 intermediate state 2; receiver finishes
101 PrepareRx waiting until the RxWait register time period
expires
110 AwaitingRx receiver activated; waiting for an input signal on
pin RX
111 Receiving receiving data
3 IRq - shows any interrupt source requesting attention
based on the InterruptEn register flag settingsCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.5.1.5 FIFOLength register
Number of bytes in the FIFO buffer.
2 Err 1 any error flag in the ErrorFlag register is set
1 HiAlert 1 the alert level for the number of bytes in the FIFO
buffer (FIFOLength[6:0]) is:
otherwise value = logic 0
Example:
FIFOLength = 60, WaterLevel = 4 then
HiAlert = logic 1
FIFOLength = 59, WaterLevel = 4 then
HiAlert = logic 0
0 LoAlert 1 the alert level for number of bytes in the FIFO
buffer (FIFOLength[6:0]) is:
otherwise
value = logic 0
Example:
FIFOLength = 4, WaterLevel = 4 then
LoAlert = logic 1
FIFOLength = 5, WaterLevel = 4 then
LoAlert = logic 0
Table 48. PrimaryStatus register bit descriptions …continued
Bit Symbol Value Status Description
HiAlert 64 FIFOLength = – WaterLevel
LoAlert FIFOLe = ngth WaterLevel
Table 49. FIFOLength register (address: 04h) reset value: 0000 0000b, 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol 0 FIFOLength[6:0]
Access R R
Table 50. FIFOLength bit descriptions
Bit Symbol Description
7 0 reserved
6 to 0 FIFOLength[6:0] gives the number of bytes stored in the FIFO buffer. Writing
increments the FIFOLength register value while reading decrements
the FIFOLength register valueCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.5.1.6 SecondaryStatus register
Various secondary status flags.
10.5.1.7 InterruptEn register
Control bits to enable and disable passing of interrupt requests.
[1] This bit can only be set or cleared using bit SetIEn.
Table 51. SecondaryStatus register (address: 05h) reset value: 01100 000b, 60h bit
allocation
Bit 7 6 5 4 3 2 1 0
Symbol TRunning E2Ready CRCReady 00 RxLastBits[2:0]
Access R R R R R
Table 52. SecondaryStatus register bit descriptions
Bit Symbol Value Description
7 TRunning 1 the timer unit is running and the counter decrements the
TimerValue register on the next timer clock cycle
0 the timer unit is not running
6 E2Ready 1 EEPROM programming is finished
0 EEPROM programming is ongoing
5 CRCReady 1 CRC calculation is finished
0 CRC calculation is ongoing
4 to 3 00 - reserved
2 to 0 RxLastBits
[2:0]
- shows the number of valid bits in the last received byte. If zero,
the whole byte is valid
Table 53. InterruptEn register (address: 06h) reset value: 0000 0000b, 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol SetIEn 0 TimerIEn TxIEn RxIEn IdleIEn HiAlertIEn LoAlertIEn
Access W R/W R/W R/W R/W R/W R/W R/W
Table 54. InterruptEn register bit descriptions
Bit Symbol Value Description
7 SetIEn 1 indicates that the marked bits in the InterruptEn register are set
0 clears the marked bits
6 0 - reserved
5 TimerIEn - sends the TimerIRq timer interrupt request to pin IRQ[1]
4 TxIEn - sends the TxIRq transmitter interrupt request to pin IRQ[1]
3 RxIEn - sends the RxIRq receiver interrupt request to pin IRQ[1]
2 IdleIEn - sends the IdleIRq idle interrupt request to pin IRQ[1]
1 HiAlertIEn - sends the HiAlertIRq high alert interrupt request to pin IRQ[1]
0 LoAlertIEn - sends the LoAlertIRq low alert interrupt request to pin IRQ[1]CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.5.1.8 InterruptRq register
Interrupt request flags.
[1] PrimaryStatus register Bit HiAlertIRq stores this event and it can only be reset using bit SetIRq.
Table 55. InterruptRq register (address: 07h) reset value: 0000 0000b, 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol SetIRq 0 TimerIRq TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq
Access W R/W D D D D D D
Table 56. InterruptRq register bit descriptions
Bit Symbol Value Description
7 SetIRq 1 sets the marked bits in the InterruptRq register
0 clears the marked bits in the InterruptRq register
6 0 - reserved
5 TimerIRq 1 timer decrements the TimerValue register to zero
0 timer decrements are still greater than zero
4 TxIRq 1 TxIRq is set to logic 1 if one of the following events occurs:
Transceive command; all data transmitted
Authent1 and Authent2 commands; all data transmitted
WriteE2 command; all data is programmed
CalcCRC command; all data is processed
0 when not acted on by Transceive, Authent1, Authent2, WriteE2 or
CalcCRC commands
3 RxIRq 1 the receiver terminates
0 reception still ongoing
2 IdleIRq 1 command terminates correctly. For example; when the Command
register changes its value from any command to the Idle command.
If an unknown command is started the IdleIRq bit is set.
Microprocessor start-up of the Idle command does not set the
IdleIRq bit.
0 IdleIRq = logic 0 in all other instances
1 HiAlertIRq 1 PrimaryStatus register HiAlert bit is set[1]
0 PrimaryStatus register HiAlert bit is not set
0 LoAlertIRq 1 PrimaryStatus register LoAlert bit is set[1]
0 PrimaryStatus register LoAlert bit is not setCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.5.2 Page 1: Control and status
10.5.2.1 Page register
Selects the page register; see Section 10.5.1.1 “Page register” on page 50.
10.5.2.2 Control register
Various control flags, for timer, power saving, etc.
10.5.2.3 ErrorFlag register
Error flags show the error status of the last executed command.
Table 57. Control register (address: 09h) reset value: 0000 0000b, 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol 00 StandBy PowerDown Crypto1On TStopNow TStartNow FlushFIFO
Access R/W D D D D D D
Table 58. Control register bit descriptions
Bit Symbol Value Description
7 to 6 00 - reserved
5 StandBy 1 activates Standby mode. The current consuming blocks are
switched off but the clock keeps running
4 PowerDown 1 activates Power-down mode. The current consuming blocks
are switched off including the clock
3 Crypto1On 1 Crypto1 unit is switched on and all data communication with
the card is encrypted. This bit can only be set to logic 1 by
successful execution of the Authent2 command
0 Crypto1 unit is switched off. All data communication with the
card is unencrypted (plain)
2 TStopNow 1 immediately stops the timer. Reading this bit always returns
logic 0
1 TStartNow 1 immediately starts the timer. Reading this bit will always
returns logic 0
0 FlushFIFO 1 immediately clears the internal FIFO buffer’s read and write
pointer, the FIFOLength[6:0] bits are set to logic 0 and the
FIFOOvfl flag. Reading this bit always returns logic 0
Table 59. ErrorFlag register (address: 0Ah) reset value: 0100 0000b, 40h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol 0 KeyErr AccessErr FIFOOvfl CRCErr FramingErr ParityErr CollErr
Access R R R R R R R R
Table 60. ErrorFlag register bit descriptions
Bit Symbol Value Description
7 0 - reserved
6 KeyErr 1 set when the LoadKeyE2 or LoadKey command recognize that the
input data is not encoded based on the Key format definition
0 set when the LoadKeyE2 or the LoadKey command startsCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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[1] Only valid for communication using ISO/IEC 14443 A.
10.5.2.4 CollPos register
Bit position of the first bit-collision detected on the RF interface.
Remark: A bit collision is not indicated in the CollPos register when using the
ISO/IEC 14443 B protocol standard.
5 AccessErr 1 set when the access rights to the EEPROM are violated
0 set when an EEPROM related command starts
4 FIFOOvfl 1 set when the microprocessor or CLRC632 internal state machine
(e.g. receiver) tries to write data to the FIFO buffer when it is full
3 CRCErr 1 set when RxCRCEn is set and the CRC fails
0 automatically set during the PrepareRx state in the receiver start
phase
2 FramingErr 1 set when the SOF is incorrect
0 automatically set during the PrepareRx state in the receiver start
phase
1 ParityErr 1 set when the parity check fails
0 automatically set during the PrepareRx state in the receiver start
phase
0 CollErr 1 set when a bit-collision is detected[1]
0 automatically set during the PrepareRx state in the receiver start
phase[1]
Table 60. ErrorFlag register bit descriptions …continued
Bit Symbol Value Description
Table 61. CollPos register (address: 0Bh) reset value: 0000 0000b, 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol CollPos[7:0]
Access R
Table 62. CollPos register bit descriptions
Bit Symbol Description
7 to 0 CollPos[7:0] this register shows the bit position of the first detected collision in a
received frame.
Example:
00h indicates a bit collision in the start bit
01h indicates a bit collision in the 1st bit
...
08h indicates a bit collision in the 8th bitCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.5.2.5 TimerValue register
Value of the timer.
10.5.2.6 CRCResultLSB register
LSB of the CRC coprocessor register.
10.5.2.7 CRCResultMSB register
MSB of the CRC coprocessor register.
Table 63. TimerValue register (address: 0Ch) reset value: xxxx xxxxb, xxh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol TimerValue[7:0]
Access R
Table 64. TimerValue register bit descriptions
Bit Symbol Description
7 to 0 TimerValue[7:0] this register shows the timer counter value
Table 65. CRCResultLSB register (address: 0Dh) reset value: xxxx xxxxb, xxh bit
allocation
Bit 7 6 5 4 3 2 1 0
Symbol CRCResultLSB[7:0]
Access R
Table 66. CRCResultLSB register bit descriptions
Bit Symbol Description
7 to 0 CRCResultLSB[7:0] gives the CRC register’s least significant byte value; only valid if
CRCReady = logic 1
Table 67. CRCResultMSB register (address: 0Eh) reset value: xxxx xxxxb, xxh bit
allocation
Bit 7 6 5 4 3 2 1 0
Symbol CRCResultMSB[7:0]
Access R
Table 68. CRCResultMSB register bit descriptions
Bit Symbol Description
7 to 0 CRCResultMSB[7:0] gives the CRC register’s most significant byte value; only valid if
CRCReady = logic 1.
The register’s value is undefined for 8-bit CRC calculation.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.5.2.8 BitFraming register
Adjustments for bit oriented frames.
Table 69. BitFraming register (address: 0Fh) reset value: 0000 0000b, 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol 0 RxAlign[2:0] 0 TxLastBits[2:0]
Access R/W D R/W D
Table 70. BitFraming register bit descriptions
Bit Symbol Value Description
7 0 - reserved
6 to 4 RxAlign[2:0] defines the bit position for the first bit received to be stored in
the FIFO buffer. Additional received bits are stored in the next
subsequent bit positions. After reception, RxAlign[2:0] is
automatically cleared. For example:
000 the LSB of the received bit is stored in bit position 0 and the
second received bit is stored in bit position 1
001 the LSB of the received bit is stored in bit position 1, the
second received bit is stored in bit position 2
...
111 the LSB of the received bit is stored in bit position 7, the
second received bit is stored in the next byte in bit position 0
3 0 - reserved
2 to 0 TxLastBits[2:0] - defines the number of bits of the last byte that shall be
transmitted. 000 indicates that all bits of the last byte will be
transmitted. TxLastBits[2:0] is automatically cleared after
transmission.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.5.3 Page 2: Transmitter and control
10.5.3.1 Page register
Selects the page register; see Section 10.5.1.1 “Page register” on page 50.
10.5.3.2 TxControl register
Controls the logical behavior of the antenna pin TX1 and TX2.
Table 71. TxControl register (address: 11h) reset value: 0101 1000b, 58h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol 0 ModulatorSource
[1:0]
Force
100ASK
TX2Inv TX2Cw TX2RFEn TX1RFEn
Access R/W R/W R/W R/W R/W R/W R/W
Table 72. TxControl register bit descriptions
Bit Symbol Value Description
7 0 - this value must not be changed
6 to 5 ModulatorSource[1:0] selects the source for the modulator input:
00 modulator input is LOW
01 modulator input is HIGH
10 modulator input is the internal encoder
11 modulator input is pin MFIN
4 Force100ASK - forces a 100 % ASK modulation independent
ModConductance register setting
3 TX2Inv 0 delivers an inverted 13.56 MHz energy carrier output
signal on pin TX2
2 TX2Cw 1 delivers a continuously unmodulated 13.56 MHz
energy carrier output signal on pin TX2
0 enables modulation of the 13.56 MHz energy carrier
1 TX2RFEn 1 the output signal on pin TX2 is the 13.56 MHz energy
carrier modulated by the transmission data
0 TX2 is driven at a constant output level
0 TX1RFEn 1 the output signal on pin TX1 is the 13.56 MHz energy
carrier modulated by the transmission data
0 TX1 is driven at a constant output levelCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.5.3.3 CwConductance register
Selects the conductance of the antenna driver pins TX1 and TX2.
See Section 9.9.3 on page 32 for detailed information about GsCfgCW[5:0].
10.5.3.4 ModConductance register
Defines the driver output conductance.
Remark: When Force100ASK = logic 1, the GsCfgMod[5:0] value has no effect.
See Section 9.9.3 on page 32 for detailed information about GsCfgMod[5:0].
Table 73. CwConductance register (address: 12h) reset value: 0011 1111b, 3Fh bit
allocation
Bit 7 6 5 4 3 2 1 0
Symbol 00 GsCfgCW[5:0]
Access R/W R/W R/W
Table 74. CwConductance register bit descriptions
Bit Symbol Description
7 to 6 00 these values must not be changed
5 to 0 GsCfgCW[5:0] defines the conductance register value for the output driver. This
can be used to regulate the output power/current consumption and
operating distance.
Table 75. ModConductance register (address: 13h) reset value: 0011 1111b, 3Fh bit
allocation
Bit 7 6 5 4 3 2 1 0
Symbol 00 GsCfgMod[5:0]
Access R/W R/W R/W
Table 76. ModConductance register bit descriptions
Bit Symbol Description
7 to 6 00 these values must not be changed
5 to 0 GsCfgMod[5:0] defines the ModConductance register value for the output
driver during modulation. This is used to regulate the
modulation index.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.5.3.5 CoderControl register
Sets the clock rate and the coding mode.
Table 77. CoderControl register (address: 14h) reset value: 0001 1001b, 19h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol SendOnePulse 0 CoderRate[2:0] TxCoding[2:0]
Access R/W R/W R/W R/W
Table 78. CoderControl register bit descriptions
Bit Symbol Value Description
7 SendOnePulse 1 forced ISO/IEC 15693 modulation. This is used to switch to the
next TimeSlot if the Inventory command is used.
0 this bit is not cleared automatically, it must be reset by the user
to logic 0
6 0 - this value must not be changed
5 to 3 CoderRate[2:0] this register defines the clock rate for the encoder circuit
000 MIFARE 848 kBd
001 MIFARE 424 kBd
010 MIFARE 212 kBd
011 MIFARE 106 kBd; ISO/IEC 14443 A
100 ISO/IEC 14443 B
101 I-CODE1 standard mode and ISO/IEC 15693 (~52.97 kHz)
110 I-CODE1 fast mode (~26.48 kHz)
111 reserved
2 to 0 TxCoding[2:0] this register defines the bit coding mode and framing during
transmission
000 NRZ according to ISO/IEC 14443 B
001 MIFARE, ISO/IEC 14443 A, (Miller coded)
010 reserved
011 reserved
100 I-CODE1 standard mode (1 out of 256 coding)
101 I-CODE1 fast mode (NRZ coding)
110 ISO/IEC 15693 standard mode (1 out of 256 coding)
111 ISO/IEC 15693 fast mode (1 out of 4 coding)CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.5.3.6 ModWidth register
Selects the pulse-modulation width.
10.5.3.7 ModWidthSOF register
Table 79. ModWidth register (address: 15h) reset value: 0001 0011b, 13h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol ModWidth[7:0]
Access R/W
Table 80. ModWidth register bit descriptions
Bit Symbol Description
7 to 0 ModWidth[7:0] defines the width of the modulation pulse based on
tmod = 2(ModWidth + 1) / fclk
Table 81. ModWidthSOF register (address: 16h) reset value: 0011 1111b, 3Fh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol ModWidthSOF[7:0]
Access R/W
Table 82. ModWidthSOF register bit descriptions
Bit Symbol Value Description
7 to 0 ModWidthSOF defines the width of the modulation pulse for SOF as
tmod = 2(ModWidth + 1) / fclk the register settings are:
3Fh MIFARE and ISO/IEC 14443; modulation width
SOF = 9.44 s
3Fh I-CODE1 standard mode; modulation width SOF = 9.44 s
73h I-CODE1 fast mode; modulation width SOF = 18.88 s
3Fh ISO/IEC 15693; modulation width SOF = 9.44 sCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.5.3.8 TypeBFraming
Defines the framing for ISO/IEC 14443 B communication.
Table 83. TypeBFraming register (address: 17h) reset value: 0011 1011b, 3Bh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol NoTxSOF NoTxEOF EOFWidth CharSpacing[2:0] SOFWidth[1:0]
Access R/W R/W R/W R/W R/W
Table 84. TypeBFraming register bit descriptions
Bit Symbol Value Description
7 NoTxSOF 1 TxCoder suppresses the SOF
0 TxCoder does not suppress SOF
6 NoTxEOF 1 TxCoder suppresses the EOF
0 TxCoder does not suppress the EOF
5 EOFWidth 1 set the EOF to a length to 11 ETU
0 set the EOF to a length of 10 ETU
4 to 2 CharSpacing[2:0] set the EGT length between 0 and 7 ETU
1 to 0 SOFWidth[1:0] 00 sets the SOF to a length to 10 ETU LOW and 2 ETU HIGH
01 sets the SOF to a length of 10 ETU LOW and 3 ETU HIGH
10 sets the SOF to a length of 11 ETU LOW and 2 ETU HIGH
11 sets the SOF to a length of 11 ETU LOW and 3 ETU HIGHCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.5.4 Page 3: Receiver and decoder control
10.5.4.1 Page register
Selects the page register; see Section 10.5.1.1 “Page register” on page 50.
10.5.4.2 RxControl1 register
Controls receiver operation.
Table 85. RxControl1 register (address: 19h) reset value: 0111 0011b, 73h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol SubCPulses[2:0] ISOSelection[1:0] LPOff Gain[1:0]
Access R/W R/W R/W R/W
Table 86. RxControl1 register bit descriptions
Bit Symbol Value Description
7 to 5 SubCPulses[2:0] defines the number of subcarrier pulses for each bit
000 1 pulse for each bit
001 2 pulses for each bit
010 4 pulses for each bit
011 8 pulses for each bit ISO/IEC 14443 A and
ISO/IEC 14443 B
100 16 pulses for each bit I-CODE1, ISO/IEC 15693
101 reserved
110 reserved
111 reserved
4 to 3 ISOSelection[1:0] used to select the communication protocol
00 reserved
10 ISO/IEC 14443 A and ISO/IEC 14443 B
01 I-CODE1, ISO/IEC 15693
11 reserved
2 LPOff switches off a low-pass filter at the internal amplifier
1 to 0 Gain[1:0] defines the receiver’s signal voltage gain factor
00 20 dB gain factor
01 24 dB gain factor
10 31 dB gain factor
11 35 dB gain factorCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.5.4.3 DecoderControl register
Controls decoder operation.
10.5.4.4 BitPhase register
Selects the bit-phase between transmitter and receiver clock.
Table 87. DecoderControl register (address: 1Ah) reset value: 0000 1000b, 08h bit
allocation
Bit 7 6 5 4 3 2 1 0
Symbol 0 RxMultiple ZeroAfterColl RxFraming[1:0] RxInvert 0 RxCoding
Access R/W R/W R/W R/W R/W R/W R/W
Table 88. DecoderControl register bit descriptions
Bit Symbol Value Description
7 0 - this value must not be changed
6 RxMultiple 0 after receiving one frame, the receiver is deactivated
1 enables reception of more than one frame
5 ZeroAfterColl 1 any bits received after a bit-collision are masked to zero. This
helps to resolve the anti-collision procedure as defined in
ISO/IEC 14443 A
4 to 3 RxFraming[1:0] 00 I-CODE1
01 MIFARE or ISO/IEC 14443 A
10 ISO/IEC 15693
11 ISO/IEC 14443 B
2 RxInvert 0 modulation at the first half-bit results in logic 1 (I-CODE1)
1 modulation at the first half-bit results in logic 0 (ISO/IEC 15693)
1 0 - this value must not be changed
0 RxCoding 0 Manchester encoding
1 BPSK encoding
Table 89. BitPhase register (address: 1Bh) reset value: 1010 1101b, ADh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol BitPhase[7:0]
Access R/W
Table 90. BitPhase register bit descriptions
Bit Symbol Description
7 to 0 BitPhase defines the phase relationship between transmitter and receiver clock
Remark: The correct value of this register is essential for proper
operation.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.5.4.5 RxThreshold register
Selects thresholds for the bit decoder.
10.5.4.6 BPSKDemControl
Controls BPSK demodulation.
Table 91. RxThreshold register (address: 1Ch) reset value: 1111 1111b, FFh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol MinLevel[3:0] CollLevel[3:0]
Access R/W R/W
Table 92. RxThreshold register bit descriptions
Bit Symbol Description
7 to 4 MinLevel[3:0] the minimum signal strength the decoder will accept. If the signal
strength is below this level, it is not evaluated.
3 to 0 CollLevel[3:0] the minimum signal strength the decoder input that must be reached
by the weaker half-bit of the Manchester encoded signal to generate
a bit-collision (relative to the amplitude of the stronger half-bit)
Table 93. BPSKDemControl register (address: 1Dh) reset value: 0001 1110b, 1Eh bit
allocation
Bit 7 6 5 4 3 2 1 0
Symbol NoRxSOF NoRxEGT NoRxEOF FilterAmpDet TauD[1:0] TauB[1:0]
Access R/W R/W R/W R/W R/W R/W
Table 94. BPSKDemControl register bit descriptions
Bit Symbol Value Description
7 NoRxSOF 1 a missing SOF in the received data stream is ignored and no
framing errors are indicated
0 a missing SOF in the received data stream generates framing
errors
6 NoRxEGT 1 an EGT which is too short or too long in the received data stream
is ignored and no framing errors are indicated
0 an EGT which is too short or too long in the received data stream
will cause framing errors
5 NoRxEOF 1 a missing EOF in the received data stream is ignored and no
framing errors indicated
0 a missing EOF in the receiving data stream produces framing
errors
4 FilterAmpDet - switches on a high-pass filter for amplitude detection
3 to 2 TauD[1:0] - changes the time constant of the internal PLL whilst receiving
data
1 to 0 TauB[1:0] - changes the time constant of the internal PLL during data burstsCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.5.4.7 RxControl2 register
Controls decoder behavior and defines the input source for the receiver.
[1] I-clock and Q-clock are 90 phase-shifted from each other.
10.5.4.8 ClockQControl register
Controls clock generation for the 90 phase-shifted Q-clock.
Table 95. RxControl2 register (address: 1Eh) reset value: 0100 0001b, 41h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol RcvClkSelI RxAutoPD 0000 DecoderSource[1:0]
Access R/W R/W R/W R/W
Table 96. RxControl2 register bit descriptions
Bit Symbol Value Description
7 RcvClkSelI 1 I-clock is used as the receiver clock[1]
0 Q-clock is used as the receiver clock[1]
6 RxAutoPD 1 receiver circuit is automatically switched on before
receiving and switched off afterwards. This can be used to
reduce current consumption.
0 receiver is always activated
5 to 2 0000 - these values must not be changed
1 to 0 DecoderSource[1:0] selects the source for the decoder input
00 LOW
01 internal demodulator
10 a subcarrier modulated Manchester encoded signal on
pin MFIN
11 a baseband Manchester encoded signal on pin MFIN
Table 97. ClockQControl register (address: 1Fh) reset value: 000x xxxxb, xxh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol ClkQ180Deg ClkQCalib 0 ClkQDelay[4:0]
Access R R/W R/W D
Table 98. ClockQControl register bit descriptions
Bit Symbol Value Description
7 ClkQ180Deg 1 Q-clock is phase-shifted more than 180 compared to the
I-clock
0 Q-clock is phase-shifted less than 180 compared to the
I-clock
6 ClkQCalib 0 Q-clock is automatically calibrated after the reset phase and
after data reception from the card
1 no calibration is performed automatically
5 0 - this value must not be changed
4 to 0 ClkQDelay[4:0] - this register shows the number of delay elements used to
generate a 90 phase-shift of the I-clock to obtain the
Q-clock. It can be written directly by the microprocessor or
by the automatic calibration cycle.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.5.5 Page 4: RF Timing and channel redundancy
10.5.5.1 Page register
Selects the page register; see Section 10.5.1.1 “Page register” on page 50.
10.5.5.2 RxWait register
Selects the time interval after transmission, before the receiver starts.
10.5.5.3 ChannelRedundancy register
Selects kind and mode of checking the data integrity on the RF channel.
Table 99. RxWait register (address: 21h) reset value: 0000 0101b, 06h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol RxWait[7:0]
Access R/W
Table 100. RxWait register bit descriptions
Bit Symbol Function
7 to 0 RxWait[7:0] after data transmission, the activation of the receiver is delayed
for RxWait bit-clock cycles. During this frame guard time any
signal on pin RX is ignored.
Table 101. ChannelRedundancy register (address: 22h) reset value: 0000 0011b, 03h bit
allocation
Bit 7 6 5 4 3 2 1 0
Symbol 00 CRC3309 CRC8 RxCRCEn TxCRCEn ParityOdd ParityEn
Access R/W R/W R/W R/W R/W R/W R/W R/W
Table 102. ChannelRedundancy bit descriptions
Bit Symbol Value Function
7 to 6 00 - this value must not be changed
5 CRC3309 1 CRC calculation is performed using ISO/IEC 3309
(ISO/IEC 14443 B) and ISO/IEC 15693
0 CRC calculation is performed using ISO/IEC 14443 A and I-CODE1
4 CRC8 1 an 8-bit CRC is calculated
0 a 16-bit CRC is calculated
3 RxCRCEn 1 the last byte(s) of a received frame are interpreted as CRC bytes. If
the CRC is correct, the CRC bytes are not passed to the FIFO. If
the CRC bytes are incorrect, the CRCErr flag is set.
0 no CRC is expected
2 TxCRCEn 1 a CRC is calculated over the transmitted data and the CRC bytes
are appended to the data stream
0 no CRC is transmittedCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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[1] When used with ISO/IEC 14443 A, this bit must be set to logic 1.
10.5.5.4 CRCPresetLSB register
LSB of the preset value for the CRC register.
[1] To use the ISO/IEC 15693 functionality, the CRCPresetLSB register has to be set to FFh.
10.5.5.5 CRCPresetMSB register
MSB of the preset value for the CRC register.
10.5.5.6 TimeSlotPeriod register
Defines the time-slot period for I-CODE1 protocol.
1 ParityOdd 1 odd parity is generated or expected[1]
0 even parity is generated or expected
0 ParityEn 1 a parity bit is inserted in the transmitted data stream after each byte
and expected in the received data stream after each byte (MIFARE,
ISO/IEC 14443 A)
0 no parity bit is inserted or expected (ISO/IEC 14443 B)
Table 102. ChannelRedundancy bit descriptions …continued
Bit Symbol Value Function
Table 103. CRCPresetLSB register (address: 23h) reset value: 0101 0011b, 63h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol CRCPresetLSB[7:0]
Access R/W
Table 104. CRCPresetLSB register bit descriptions
Bit Symbol Description
7 to 0 CRCPresetLSB[7:0] defines the start value for CRC calculation. This value is loaded
into the CRC at the beginning of transmission, reception and
the CalcCRC command (if CRC calculation is enabled)[1].
Table 105. CRCPresetMSB register (address: 24h) reset value: 0101 0011b, 63h bit
allocation
Bit 7 6 5 4 3 2 1 0
Symbol CRCPresetMSB[7:0]
Access R/W
Table 106. CRCPresetMSB bit descriptions
Bit Symbol Description
7 to 0 CRCPresetMSB[7:0] defines the starting value for CRC calculation. This value is
loaded into the CRC at the beginning of transmission, reception
and the CalcCRC command (if the CRC calculation is enabled)
Remark: This register is not relevant if CRC8 is set to logic 1.
Table 107. TimeSlotPeriod register (address: 25h) reset value: 0000 0000b, 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol TimeSlotPeriod[7:0]
Access R/WCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.5.5.7 MFOUTSelect register
Selects the internal signal applied to pin MFOUT.
[1] Only valid for MIFARE and ISO/IEC 14443 A communication at 106 kBd.
10.5.5.8 PreSet27 register
Table 108. TimeSlotPeriod register bit descriptions
Bit Symbol Description
7 to 0 TimeSlotPeriod[7:0] defines the time between automatically transmitted frames. To
send a Quit frame using the I-CODE1 protocol it is necessary to
relate to the beginning of the command frame. The
TimeSlotPeriod starts at the end of the command transmission.
See Section 9.5.1.5 on page 26 for additional information.
Table 109. MFOUTSelect register (address: 26h) reset value: 0000 0000b, 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol 000 TimeSlotPeriodMSB 0 MFOUTSelect[2:0]
Access R/W R/W R/W R/W R/W R/W
Table 110. MFOUTSelect register bit descriptions
Bit Symbol Value Description
7 to 5 000 - these values must not be changed
4 TimeSlotPeriodMSB - MSB of value TimeSlotPeriod; see Table 107 on page 69
for more detailed information
3 0 - this value must not be changed
2 to 0 MFOUTSelect[2:0] defines which signal is routed to pin MFOUT:
000 constant LOW
001 constant HIGH
010 modulation signal (envelope) from the internal
encoder, (Miller coded)
011 serial data stream, not Miller encoded
100 output signal of the energy carrier demodulator (card
modulation signal)[1]
101 output signal of the subcarrier demodulator
(Manchester encoded card signal)[1]
110 reserved
111 reserved
Table 111. PreSet27 (address: 27h) reset value: xxxx xxxxb, xxh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol x x x x x x x x
Access W W W W W W W WCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.5.6 Page 5: FIFO, timer and IRQ pin configuration
10.5.6.1 Page register
Selects the page register; see Section 10.5.1.1 “Page register” on page 50.
10.5.6.2 FIFOLevel register
Defines the levels for FIFO underflow and overflow warning.
10.5.6.3 TimerClock register
Selects the divider for the timer clock.
Table 112. FIFOLevel register (address: 29h) reset value: 0000 1000b, 08h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol 00 WaterLevel[5:0]
Access R/W R/W R/W
Table 113. FIFOLevel register bit descriptions
Bit Symbol Description
7 to 6 00 these values must not be changed
5 to 0 WaterLevel[5:0] defines, the warning level of a FIFO buffer overflow or underflow:
HiAlert is set to logic 1 if the remaining FIFO buffer space is equal to,
or less than, WaterLevel[5:0] bits in the FIFO buffer.
LoAlert is set to logic 1 if equal to, or less than, WaterLevel[5:0] bits in
the FIFO buffer.
Table 114. TimerClock register (address: 2Ah) reset value: 0000 0111b, 07h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol 00 TAutoRestart TPreScaler[4:0]
Access RW RW RW RW
Table 115. TimerClock register bit descriptions
Bit Symbol Value Function
7 to 6 00 - these values must not be changed
5 TAutoRestart 1 the timer automatically restarts its countdown from the
TReloadValue[7:0] instead of counting down to zero
0 the timer decrements to zero and register InterruptIrq
TimerIRq bit is set to logic 1
4 to 0 TPreScaler[4:0] - defines the timer clock frequency (fTimerClock). The
TPreScaler[4:0] can be adjusted from 0 to 21. The following
formula is used to calculate the TimerClock frequency
(fTimerClock):
fTimerClock = 13.56 MHz / 2TPreScaler [MHz]CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.5.6.4 TimerControl register
Selects start and stop conditions for the timer.
10.5.6.5 TimerReload register
Defines the preset value for the timer.
Table 116. TimerControl register (address: 2Bh) reset value: 0000 0110b, 06h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol 0000 TStopRxEnd TStopRxBegin TStartTxEnd TStartTxBegin
Access R/W R/W R/W R/W R/W
Table 117. TimerControl register bit descriptions
Bit Symbol Value Description
7 to 4 0000 - these values must not be changed
3 TStopRxEnd 1 the timer automatically stops when data reception ends
0 the timer is not influenced by this condition
2 TStopRxBegin 1 the timer automatically stops when the first valid bit is received
0 the timer is not influenced by this condition
1 TStartTxEnd 1 the timer automatically starts when data transmission ends. If
the timer is already running, the timer restarts by loading
TReloadValue[7:0] into the timer.
0 the timer is not influenced by this condition
0 TStartTxBegin 1 the timer automatically starts when the first bit is transmitted. If
the timer is already running, the timer restarts by loading
TReloadValue[7:0] into the timer.
0 the timer is not influenced by this condition
Table 118. TimerReload register (address: 2Ch) reset value: 0000 1010b, 0Ah bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol TReloadValue[7:0]
Access R/W
Table 119. TimerReload register bit descriptions
Bit Symbol Description
7 to 0 TReloadValue[7:0] on a start event, the timer loads the TReloadValue[7:0] value.
Changing this register only affects the timer on the next start event. If
TReloadValue[7:0] is set to logic 0 the timer cannot start.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.5.6.6 IRQPinConfig register
Configures the output stage for pin IRQ.
10.5.6.7 PreSet2E register
10.5.6.8 PreSet2F register
10.5.7 Page 6: reserved
10.5.7.1 Page register
Selects the page register; see Section 10.5.1.1 “Page register” on page 50.
10.5.7.2 Reserved registers 31h, 32h, 33h, 34h, 35h, 36h and 37h
Remark: These registers are reserved for future use.
Table 120. IRQPinConfig register (address: 2Dh) reset value: 0000 0010b, 02h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol 000000 IRQInv IRQPushPull
Access R/W R/W R/W
Table 121. IRQPinConfig register bit descriptions
Bit Symbol Value Description
7 to 2 000000 - these values must not be changed
1 IRQInv 1 inverts the signal on pin IRQ with respect to bit IRq
0 the signal on pin IRQ is not inverted and is the same as bit IRq
0 IRQPushPull 1 pin IRQ functions as a standard CMOS output pad
0 pin IRQ functions as an open-drain output pad
Table 122. PreSet2E register (address: 2Eh) reset value: xxxx xxxxb, xxh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol x x x x x x x x
Access W W W W W W W W
Table 123. PreSet2F register (address: 2Fh) reset value: xxxx xxxxb, xxh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol x x x x x x x x
Access W W W W W W W W
Table 124. Reserved registers (address: 31h, 32h, 33h, 34h, 35h, 36h, 37h)
reset value: xxxx xxxxb, xxh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol x x x x x x x x
Access R/W R/W R/W R/W R/W R/W R/W R/WCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.5.8 Page 7: Test control
10.5.8.1 Page register
Selects the page register; see Section 10.5.1.1 “Page register” on page 50.
10.5.8.2 Reserved register 39h
Remark: This register is reserved for future use.
10.5.8.3 TestAnaSelect register
Selects analog test signals.
Table 125. Reserved register (address: 39h) reset value: xxxx xxxxb, xxh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol x x x x x x x x
Access W W W W W W W W
Table 126. TestAnaSelect register (address: 3Ah) reset value: 0000 0000b, 00h bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol 0000 TestAnaOutSel[4:0]
Access W W
Table 127. TestAnaSelect bit descriptions
Bit Symbol Value Description
7 to 4 0000 - these values must not be changed
3 to 0 TestAnaOutSel[4:0] selects the internal analog signal to be routed to pin
AUX. See Section 15.2.2 on page 112 for detailed
information. The settings are as follows:
0 VMID
1 Vbandgap
2 VRxFollI
3 VRxFollQ
4 VRxAmpI
5 VRxAmpQ
6 VCorrNI
7 VCorrNQ
8 VCorrDI
9 VCorrDQ
A VEvalL
B VEvalR
C VTemp
D reserved
E reserved
F reservedCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.5.8.4 Reserved register 3Bh
Remark: This register is reserved for future use.
10.5.8.5 Reserved register 3Ch
Remark: This register is reserved for future use.
10.5.8.6 TestDigiSelect register
Selects digital test mode.
Table 128. Reserved register (address: 3Bh) reset value: xxxx xxxxb, xxh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol x x x x x x x x
Access W W W W W W W W
Table 129. Reserved register (address: 3Ch) reset value: xxxx xxxxb, xxh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol x x x x x x x x
Access W W W W W W W W
Table 130. TestDigiSelect register (address: 3Dh) reset value: xxxx xxxxb, xxh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol SignalToMFOUT TestDigiSignalSel[6:0]
Access W W
Table 131. TestDigiSelect register bit descriptions
Bit Symbol Value Description
7 SignalToMFOUT 1 overrules the MFOUTSelect[2:0] setting and routes the
digital test signal defined with the TestDigiSignalSel[6:0]
bits to pin MFOUT
0 MFOUTSelect[2:0] defines the signal on pin MFOUT
6 to 0 TestDigiSignalSel[6:0] - selects the digital test signal to be routed to pin MFOUT.
Refer to Section 15.2.3 on page 113 for detailed
information. The following lists the signal names for the
TestDigiSignalSel[6:0] addresses:
F4h s_data
E4h s_valid
D4h s_coll
C4h s_clock
B5h rd_sync
A5h wr_sync
96h int_clock
83h BPSK_out
E2h BPSK_sigCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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10.5.8.7 Reserved registers 3Eh, 3Fh
Remark: This register is reserved for future use.
11. CLRC632 command set
CLRC632 operation is determined by an internal state machine capable of performing a
command set. The commands can be started by writing the command code to the
Command register. Arguments and/or data necessary to process a command are mainly
exchanged using the FIFO buffer.
• Each command needing a data stream (or data byte stream) as an input immediately
processes the data in the FIFO buffer
• Each command that requires arguments only starts processing when it has received
the correct number of arguments from the FIFO buffer
• The FIFO buffer is not automatically cleared at the start of a command. It is, therefore,
possible to write command arguments and/or the data bytes into the FIFO buffer
before starting a command.
• Each command (except the StartUp command) can be interrupted by the
microprocessor writing a new command code to the Command register e.g. the Idle
command.
11.1 CLRC632 command overview
Table 132. Reserved register (address: 3Eh, 3Fh) reset value: xxxx xxxxb, xxh bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol x x x x x x x x
Access W W W W W W W W
Table 133. CLRC632 commands overview
Command Value Action FIFO communication
Arguments and data
sent
Data received
StartUp 3Fh runs the reset and initialization phase. See
Section 11.1.2 on page 78.
Remark: This command can only be activated by
Power-On or Hard resets.
- -
Idle 00h no action; cancels execution of the current command.
See Section 11.1.3 on page 78
- -
Transmit 1Ah transmits data from the FIFO buffer to the card. See
Section 11.2.1 on page 79
data stream -
Receive 16h activates receiver circuitry. Before the receiver starts,
the state machine waits until the time defined in the
RxWait register has elapsed. See Section 11.2.2 on
page 82.
Remark: This command may be used for test
purposes only, since there is no timing relationship to
the Transmit command.
- data streamCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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[1] This command is the combination of the Transmit and Receive commands.
[2] Relates to MIFARE Mini/MIFARE 1K/MIFARE 4K security.
Transceive[1] 1Eh transmits data from FIFO buffer to the card and
automatically activates the receiver after
transmission. The receiver waits until the time defined
in the RxWait register has elapsed before starting.
See Section 11.2.3 on page 85.
data stream data stream
WriteE2 01h reads data from the FIFO buffer and writes it to the
EEPROM. See Section 11.4.1 on page 93.
start address LSB -
start address MSB
data byte stream
ReadE2 03h reads data from the EEPROM and sends it to the
FIFO buffer. See Section 11.4.2 on page 95.
Remark: Keys cannot be read back
start address LSB data bytes
start address MSB
number of data bytes
LoadKeyE2 0Bh copies a key from the EEPROM into the key buffer[2]
See Section 11.7.1 on page 97.
start address LSB -
start address MSB
LoadKey 19h reads a key from the FIFO buffer and loads it into the
key buffer[2]. See Section 11.7.2 on page 97.
Remark: The key has to be prepared in a specific
format (refer to Section 9.2.3.1 “Key format” on page
18)
byte 0 LSB -
byte 1
…
byte 10
byte 11 MSB
Authent1 0Ch performs the first part of card authentication using the
Crypto1 algorithm[2]. See Section 11.7.3 on page 98.
card Authent1 command -
card block address
card serial number
LSB
card serial number
byte 1
card serial number
byte 2
card serial number
MSB
Authent2 14h performs the second part of card authentication using
the Crypto1 algorithm[2]. See Section 11.7.4 on
page 98.
- -
LoadConfig 07h reads data from EEPROM and initializes the
CLRC632 registers. See Section 11.5.1 on page 95.
start address LSB -
start address MSB
CalcCRC 12h activates the CRC coprocessor
Remark: The result of the CRC calculation is read
from the CRCResultLSB and CRCResultMSB
registers. See Section 11.5.2 on page 96.
data byte stream -
Table 133. CLRC632 commands overview …continued
Command Value Action FIFO communication
Arguments and data
sent
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11.1.1 Basic states
11.1.2 StartUp command 3Fh
Remark: This command can only be activated by a Power-On or Hard reset.
The StartUp command runs the reset and initialization phases. It does not need or return,
any data. It cannot be activated by the microprocessor but is automatically started after
one of the following events:
• Power-On Reset (POR) caused by power-up on pin DVDD
• POR caused by power-up on pin AVDD
• Negative edge on pin RSTPD
The reset phase comprises an asynchronous reset and configuration of certain register
bits. The initialization phase configures several registers with values stored in the
EEPROM.
When the StartUp command finishes, the Idle command is automatically executed.
Remark:
• The microprocessor must not write to the CLRC632 while it is still executing the
StartUp command. To avoid this, the microprocessor polls for the Idle command to
determine when the initialization phase has finished; see Section 9.7.4 on page 30.
• When the StartUp command is active, it is only possible to read from the Page 0
register.
• The StartUp command cannot be interrupted by the microprocessor.
11.1.3 Idle command 00h
The Idle command switches the CLRC632 to its inactive state where it waits for the next
command. It does not need or return, any data.
The device automatically enters the idle state when a command finishes. When this
happens, the CLRC632 sends an interrupt request by setting bit IdleIRq. When triggered
by the microprocessor, the Idle command can be used to stop execution of all other
commands (except the StartUp command) but this does not generate an interrupt request
(IdleIRq).
Remark: Stopping command execution with the Idle command does not clear the FIFO
buffer.
Table 134. StartUp command 3Fh
Command Value Action Arguments
and data
Returned
data
StartUp 3Fh runs the reset and initialization phase - -
Table 135. Idle command 00h
Command Value Action Arguments
and data
Returned
data
Idle 00h no action; cancels current command
execution
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11.2 Commands for ISO/IEC 14443 A card communication
The CLRC632 is a fully ISO/IEC 14443 A, ISO/IEC 14443 B, ISO/IEC 15693 and
I-CODE1 compliant reader IC. This enables the command set to be more flexible and
generalized when compared to dedicated MIFARE or I-CODE1 reader ICs. Section 11.2.1
to Section 11.2.5 describe the command set for ISO/IEC 14443 A card communication
and related communication protocols.
11.2.1 Transmit command 1Ah
The Transmit command reads data from the FIFO buffer and sends it to the transmitter. It
does not return any data. The Transmit command can only be started by the
microprocessor.
11.2.1.1 Using the Transmit command
To transmit data, one of the following sequences can be used:
1. All data to be transmitted to the card is written to the FIFO buffer while the Idle
command is active. Then the command code for the Transmit command is written to
the Command register.
Remark: This is possible for transmission of a data stream up to 64 bytes.
2. The command code for the Transmit command is stored in the Command register.
Since there is not any data available in the FIFO buffer, the command is only enabled
but transmission is not activated. Data transmission starts when the first data byte is
written to the FIFO buffer. To generate a continuous data stream on the RF interface,
the microprocessor must write the subsequent data bytes into the FIFO buffer in time.
Remark: This allows transmission of any data stream length but it requires data to be
written to the FIFO buffer in time.
3. Part of the data transmitted to the card is written to the FIFO buffer while the Idle
command is active. Then the command code for the Transmit command is written to
the Command register. While the Transmit command is active, the microprocessor
can send further data to the FIFO buffer. This is then appended by the transmitter to
the transmitted data stream.
Remark: This allows transmission of any data stream length but it requires data to be
written to the FIFO buffer in time.
When the transmitter requests the next data byte to ensure the data stream on the RF
interface is continuous and the FIFO buffer is empty, the Transmit command automatically
terminates. This causes the internal state machine to change its state from transmit to
idle.
When the data transmission to the card is finished, the TxIRq flag is set by the CLRC632
to indicate to the microprocessor transmission is complete.
Remark: If the microprocessor overwrites the transmit code in the Command register
with another command, transmission stops immediately on the next clock cycle. This can
produce output signals that are not in accordance with ISO/IEC 14443 A.
Table 136. Transmit command 1Ah
Command Value Action Arguments
and data
Returned
data
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11.2.1.2 RF channel redundancy and framing
Each ISO/IEC 14443 A transmitted frame consists of a Start Of Frame (SOF) pattern,
followed by the data stream and is closed by an End Of Frame (EOF) pattern. These
different phases of the transmission sequence can be monitored using the PrimaryStatus
register ModemState[2:0] bit; see Section 11.2.4 on page 85.
Depending on the setting of the ChannelRedundancy register bit TxCRCEn, the CRC is
calculated and appended to the data stream. The CRC is calculated according to the
settings in the ChannelRedundancy register. Parity generation is handled according to the
ChannelRedundancy register ParityEn and ParityOdd bits settings.
11.2.1.3 Transmission of bit oriented frames
The transmitter can be configured to send an incomplete last byte. To achieve this the
BitFraming register’s TxLastBits[2:0] bits must be set at above zero (for example, 1). This
is shown in Figure 16.
Figure 16 shows the data stream if bit ParityEn is set in the ChannelRedundancy register.
All fully transmitted bytes are followed by a parity check bit but the incomplete byte is not
followed by a parity check bit. After transmission, the TxLastBits[2:0] bits are automatically
cleared.
Remark: If the TxLastBits[2:0] bits are not equal to zero, CRC generation must be
disabled. This is done by clearing the ChannelRedundancy register TxCRCEn bit.
11.2.1.4 Transmission of frames with more than 64 bytes
To generate frames of more than 64 bytes, the microprocessor must write data to the
FIFO buffer while the Transmit command is active. The state machine checks the FIFO
buffer status when it starts transmitting the last bit of the data stream; the check time is
marked in Figure 17 with arrows.
Fig 16. Transmitting bit oriented frames
001aak618
TxLastBits = 0
TxLastBits = 7
TxLastBits = 1
SOF 0 7 P 0 7 P
SOF
SOF
EOF
EOF
EOF
0 7 P 0 6
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As long as the internal accept further data signal is logic 1, further data can be written to
the FIFO buffer. The CLRC632 appends this data to the data stream transmitted using the
RF interface.
If the internal accept further data signal is logic 0, the transmission terminates. All data
written to the FIFO buffer after accept further data signal was set to logic 0 is not
transmitted, however, it remains in the FIFO buffer.
Remark: If parity generation is enabled (ParityEn = logic 1), the parity bit is the last bit
transmitted. This delays the accept further data signal by a duration of one bit.
If the TxLastBits[2:0] bits are not zero, the last byte is not transmitted completely. Only the
number of bits set by TxLastBits[2:0], starting with the least significant bit are transmitted.
This means that the internal state machine has to check the FIFO buffer status at an
earlier point in time; see Figure 18.
Since in this example TxLastBits[2:0] = 4, transmission stops after bit 3 is transmitted and
the frame is completed with an EOF, if configured.
Fig 17. Timing for transmitting byte oriented frames
Fig 18. Timing for transmitting bit oriented frames
001aak619
accept further data
check FIFO empty
TxData
FIFO empty
FIFOLength[6:0] 01h 00h
TxLastBits[2:0] TxLastBits = 0
7 0 7 0 7
001aak620
accept further data
check FIFO empty
TxData
FIFO empty
FIFOLength[6:0] 01h 00h 01h 00h
TxLastBits[2:0] TxLastBits = 4
NWR (FIFO data)
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Figure 18 also shows write access to the FIFOData register just before the FIFO buffer’s
status is checked. This leads to FIFO empty state being held LOW which keeps the
accept further data active. The new byte written to the FIFO buffer is transmitted using the
RF interface.
Accept further data is only changed by the check FIFO empty function. This function
verifies FIFO empty for one bit duration before the last expected bit transmission.
11.2.2 Receive command 16h
The Receive command activates the receiver circuitry. All data received from the RF
interface is written to the FIFO buffer. The Receive command can be started either using
the microprocessor or automatically during execution of the Transceive command.
Remark: This command can only be used for test purposes since there is no timing
relationship to the Transmit command.
11.2.2.1 Using the Receive command
After starting the Receive command, the internal state machine decrements to the RxWait
register value on every bit-clock. The analog receiver circuitry is prepared and activated
from 3 down to 1. When the counter reaches 0, the receiver starts monitoring the incoming
signal at the RF interface.
When the signal strength reaches a level higher than the RxThreshold register
MinLevel[3:0] bits value, it starts decoding. The decoder stops when the signal can longer
be detected on the receiver input pin RX. The decoder sets bit RxIRq indicating receive
termination.
The different phases of the receive sequence are monitored using the PrimaryStatus
register ModemState[2:0] bits; see Section 11.2.4 on page 85.
Remark: Since the counter values from 3 to 0 are needed to initialize the analog receiver
circuitry, the minimum value for RxWait[7:0] is 3.
11.2.2.2 RF channel redundancy and framing
The decoder expects the SOF pattern at the beginning of each data stream. When the
SOF is detected, it activates the serial-to-parallel converter and gathers the incoming data
bits. Every completed byte is forwarded to the FIFO buffer.
Table 137. Transmission of frames of more than 64 bytes
Frame definition Verification at:
8-bit with parity 8th bit
8-bit without parity 7th bit
x-bit without parity (x 1)th bit
Table 138. Receive command 16h
Command Value Action Arguments
and data
Returned
data
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If an EOF pattern is detected or the signal strength falls below the RxThreshold register
MinLevel[3:0] bits setting, both the receiver and the decoder stop. Then the Idle command
is entered and an appropriate response for the microprocessor is generated (interrupt
request activated, status flags set).
When the ChannelRedundancy register bit RxCRCEn is set, a CRC block is expected.
The CRC block can be one byte or two bytes depending on the ChannelRedundancy
register CRC8 bit setting.
Remark: If the CRC block received is correct, it is not sent to the FIFO buffer. This is
realized by shifting the incoming data bytes through an internal buffer of either one or two
bytes (depending on the defined CRC). The CRC block remains in this internal buffer.
Consequently, all data bytes in the FIFO buffer are delayed by one or two bytes. If the
CRC fails, all received bytes are sent to the FIFO buffer including the faulty CRC.
If ParityEn is set in the ChannelRedundancy register, a parity bit is expected after each
byte. If ParityOdd = logic 1, the expected parity is odd, otherwise even parity is expected.
11.2.2.3 Collision detection
If more than one card is within the RF field during the card selection phase, they both
respond simultaneously. The CLRC632 supports the algorithm defined in
ISO/IEC 14443 A to resolve card serial number data collisions by performing the
anti-collision procedure. The basis for this procedure is the ability to detect bit-collisions.
Bit-collision detection is supported by the Manchester coding bit encoding scheme used in
the CLRC632. If in the first and second half-bit of a subcarrier, modulation is detected,
instead of forwarding a 1-bit or 0-bit, a bit-collision is indicated. The CLRC632 uses the
RxThreshold register CollLevel[3:0] bits setting to distinguish between a 1-bit or 0-bit and
a bit-collision. If the amplitude of the half-bit with smaller amplitude is larger than that
defined by the CollLevel[3:0] bits, the CLRC632 flags a bit-collision using the error flag
CollErr. If a bit-collision is detected in a parity bit, the ParityErr flag is set.
On a detected collision, the receiver continues receiving the incoming data stream. In the
case of a bit-collision, the decoder sends logic 1 at the collision position.
Remark: As an exception, if bit ZeroAfterColl is set, all bits received after the first
bit-collision are forced to zero, regardless whether a bit-collision or an unequivocal state
has been detected. This feature makes it easier for the control software to perform the
anti-collision procedure as defined in ISO/IEC 14443 A.
When the first bit collision in a frame is detected, the bit-collision position is stored in the
CollPos register.
Table 139 shows the collision positions.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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Parity bits are not counted in the CollPos register because bit-collisions in parity bit occur
after bit-collisions in the data bits. If a collision is detected in the SOF, a frame error is
flagged and no data is sent to the FIFO buffer. In this case, the receiver continues to
monitor the incoming signal. It generates the correct notifications to the microprocessor
when the end of the faulty input stream is detected. This helps the microprocessor to
determine when it is next allowed to send data to the card.
11.2.2.4 Receiving bit oriented frames
The receiver can manage byte streams with incomplete bytes which result in bit-oriented
frames. To support this, the following values may be used:
• BitFraming register’s RxAlign[2:0] bits select a bit offset for the first incoming byte. For
example, if RxAlign[2:0] = 3, the first 5 bits received are forwarded to the FIFO buffer.
Further bits are packed into bytes and forwarded. After reception, RxAlign[2:0] is
automatically cleared. If RxAlign[2:0] = logic 0, all incoming bits are packed into one
byte.
• RxLastBits[2:0] returns the number of bits valid in the last received byte. For example,
if RxLastBits[2:0] evaluates to 5 bits at the end of the received command, the 5 least
significant bits are valid. If the last byte is complete, RxLastBits[2:0] evaluates to zero.
RxLastBits[2:0] is only valid if a frame error is not indicated by the FramingErr flag. If
RxAlign[2:0] is not zero and ParityEn is active, the first parity bit is ignored and not
checked.
11.2.2.5 Communication errors
The events which can set error flags are shown in Table 140.
Table 139. Return values for bit-collision positions
Collision in bit CollPos register value
(Decimal)
SOF 0
Least Significant Bit (LSB) of the Least Significant Byte (LSByte) 1
… …
Most Significant Bit (MSB) of the LSByte 8
LSB of second byte 9
… …
MSB of second byte 16
LSB of third byte 17
… …
Table 140. Communication error table
Cause Flag bit
Received data did not start with the SOF pattern FramingErr
CRC block is not equal to the expected value CRCErr
Received data is shorter than the CRC block CRCErr
The parity bit is not equal to the expected value (i.e. a bit-collision, not parity) ParityErr
A bit-collision is detected CollErrCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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11.2.3 Transceive command 1Eh
The Transceive command first executes the Transmit command (see Section 11.2.1 on
page 79) and then starts the Receive command (see Section 11.2.2 on page 82). All data
transmitted is sent using the FIFO buffer and all data received is written to the FIFO buffer.
The Transceive command can only be started by the microprocessor.
Remark: To adjust the timing relationship between transmitting and receiving, use the
RxWait register. This register is used to define the time delay between the last bit
transmitted and activation of the receiver. In addition, the BitPhase register determines the
phase-shift between the transmitter and receiver clock.
11.2.4 States of the card communication
The status of the transmitter and receiver state machine can be read from bits
ModemState[2:0] in the PrimaryStatus register.
The assignment of ModemState[2:0] to the internal action is shown in Table 142.
Table 141. Transceive command 1Eh
Command Value Action Arguments
and data
Returned
data
Transceive 1Eh transmits data from FIFO buffer to the card
and then automatically activates the
receiver
data stream data stream
Table 142. Meaning of ModemState
ModemState
[2:0]
State Description
000 Idle transmitter and/or receiver are not operating
001 TxSOF transmitting the SOF pattern
010 TxData transmitting data from the FIFO buffer (or redundancy CRC check
bits)
011 TxEOF transmitting the EOF pattern
100 GoToRx1 intermediate state passed, when receiver starts
GoToRx2 intermediate state passed, when receiver finishes
101 PrepareRx waiting until the RxWait register time period expires
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11.2.5 Card communication state diagram
Fig 19. Card communication state diagram
001aak621
end of receive frame
and
RxMultiple = 0
RxMultiple = 1
EOF transmitted and
command = Transceive
FIFO not empty
and command =
Transmit or Transceive
command = Receive
COMMAND =
TRANSMIT,
RECEIVE OR
TRANSCEIVE
SET
COMMAND REGISTER = IDLE
(000)
Awaiting Rx
(110)
RECEIVING
(111)
GoToRx2
(100)
Prepare Rx
(101)
GoToRx1
(100)
TxEOF
(011)
TxData
(010)
TxSOF
(001)
IDLE
(000)
SOF transmitted next bit clock
data transmitted RxWaitC[7:0] = 0
EOF transmitted and
command = Transmit
signal strength > MinLevel[3:0]
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11.3 I-CODE1 and ISO/IEC 15693 label communication commands
The CLRC632 is a fully ISO/IEC 14443 A, ISO/IEC 14443 B, ISO/IEC 15693 and
I-CODE1 compliant reader IC. This enables the command set to be more flexible and
generalized when compared to dedicated MIFARE or I-CODE1 reader ICs. Section 11.3.1
to Section 11.3.5 give an overview of the command set for I-CODE1 and ISO/IEC 15693
card communication and related communication protocols.
11.3.1 Transmit command 1Ah
The Transmit command reads data from the FIFO buffer and sends it to the transmitter. It
does not return any data. The Transmit command can only be started by the
microprocessor.
11.3.1.1 Using the Transmit command
To transmit data, one of the following sequences can be used:
1. All data to be transmitted to the label is written to the FIFO buffer while the Idle
command is active. Then the command code for the Transmit command is written to
the Command register.
Remark: This is possible for transmission of a data stream up to 64 bytes long.
2. The command code for the Transmit command is stored in the Command register.
Since there is not any data available in the FIFO buffer, the command is only enabled
but transmission is not triggered. Data transmission starts when the first data byte is
written to the FIFO buffer. To generate a continuous data stream on the RF interface,
the microprocessor must write the subsequent data bytes into the FIFO buffer in time.
Remark: This allows transmission of any data stream length but it requires data to be
written to the FIFO buffer in time.
3. Part of the data transmitted to the label is written to the FIFO buffer while the Idle
command is active. Then the command code for the Transmit command is written to
the Command register. While the Transmit command is active, the microprocessor
can send further data to the FIFO buffer. This is then appended by the transmitter to
the transmitted data stream.
Remark: This allows transmission of any data stream length but it requires data to be
written to the FIFO buffer in time.
When the transmitter requests the next data byte, to ensure that the data stream on the
RF interface is continuous and the FIFO buffer is empty, the Transmit command
automatically terminates. This causes the internal state machine to change its state from
transmit to idle. When the data transmission to the label is finished, the TxIRq flag is set
by the CLRC632 to indicate transmission is complete to the microprocessor.
Remark: If the microprocessor overwrites the transmit code in the Command register
with another command, transmission stops immediately on the next clock cycle. This can
produce output signals that do not comply with the ISO/IEC 15693 standard or the
I-CODE1 protocol.
Table 143. Transmit command 1Ah
Command Value Action Arguments
and data
Returned
data
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11.3.1.2 RF channel redundancy and framing
Each transmitted ISO/IEC 15693 frame consists of a Start Of Frame (SOF) pattern,
followed by the data stream and is closed by an End Of Frame (EOF) pattern. All
I-CODE1 command frames consists of a start pulse followed by the data stream. The
I-CODE1 commands have a fixed length and do not need an EOF. The phases of the
transmission sequence are monitored using the PrimaryStatus register’s ModemState[2:0]
bits; see Section 11.2.4 on page 85.
Depending on the ChannelRedundancy register TxCRCEn bit setting, the CRC is
calculated and appended to the data stream. The CRC is calculated using the
ChannelRedundancy register settings.
11.3.1.3 Transmission of frames of more than 64 bytes
To generate frames of more than 64 bytes of data, the microprocessor has to write data to
the FIFO buffer while the Transmit command is active. The state machine checks the
FIFO buffer status when it starts transmitting the last bit of the data stream (the check time
is shown in Figure 20 with arrows).
As long as the internal accept further data signal is logic 1 further data can be written to
the FIFO buffer. The CLRC632 appends this data to the data stream transmitted using the
RF interface.
If the internal accept further data signal is logic 0 the transmission terminates. All data
written to the FIFO buffer after accept further data signal was set to logic 0 is not
transmitted, however, it remains in the FIFO buffer.
11.3.2 Receive command 16h
The Receive command activates the receiver circuitry. All data received from the RF
interface is written to the FIFO buffer. The Receive command can be started either by the
microprocessor or automatically during execution of the Transceive command.
Fig 20. Timing for transmitting byte oriented frames
001aak619
accept further data
check FIFO empty
TxData
FIFO empty
FIFOLength[6:0] 01h 00h
TxLastBits[2:0] TxLastBits = 0
7 0 7 0 7
Table 144. Receive command 16h
Command Value Action Arguments
and data
Returned data
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Remark: This command may be used for test purposes only, since there is no timing
relation to the Transmit command.
11.3.2.1 Using the Receive command
After starting the Receive command the internal state machine decrements the RxWait
register value on every bit-clock. The analog receiver circuitry is prepared and activated
from 3 down to 1. When the counter reaches 0, the receiver starts monitoring the incoming
signal using the RF interface. If the signal strength reaches a level above the value set in
the RxThreshold register’s MinLevel[3:0] bits, the receiver starts decoding. The decoder
stops when the signal cannot be detected on the receiver input pin RX. The decoder sets
the RxIRq flag bit to indicate that the operation has finished.
The receive sequence phases can be monitored using bits ModemStatus[2:0] in the
PrimaryStatus register; see Section 11.2.4 on page 85.
Remark: The minimum value for RxWait[7:0] is 3 because counter values from 3 to 0 are
needed to initialize the analog receiver circuitry.
11.3.2.2 RF channel redundancy and framing
In ISO/IEC 15693 mode, the decoder expects a SOF pattern at the beginning of each data
stream. When a SOF is detected, it activates the serial-to-parallel converter and gathers
the incoming data bits. If an EOF pattern (ISO/IEC 15693) is detected or the signal
strength falls below the MinLevel value, the receiver and the decoder stop, the Idle
command is entered and an appropriate response for the microprocessor is generated
(interrupt request activated, status flags set).
In I-CODE1 mode, the decoder does not expect a SOF pattern at the beginning of each
data stream. It activates the serial-to-parallel converter on the first received bit of the data.
Every full byte is then sent to the FIFO buffer.
If ChannelRedundancy register bit RxCRCEn is set a CRC block is expected. The CRC
block may be one byte or two bytes based on the ChannelRedundancy register’s CRC8
bit.
Remark: If it is correct, the CRC block is not forwarded to the FIFO buffer. The CRC is
realized by shifting the incoming data bytes through an internal buffer of one or two bytes
(depending on the defined CRC). The CRC block remains in this internal buffer.
Consequently, all data bytes in the FIFO buffer are delayed by one or two bytes. If the
CRC fails, all bytes received are forwarded to the FIFO buffer (including the faulty CRC).
11.3.2.3 Collision detection
If more than one label is within the RF field during the label selection phase, they will
respond simultaneously. The CLRC632 supports the algorithm defined in ISO/IEC 15693
as well as the I-CODE1 anti-collision algorithm to resolve label serial number data
collisions using the anti-collision procedure. The basis for this procedure is the ability to
detect bit-collisions.
Bit-collision detection is supported by the Manchester coding bit encoding scheme used. If
in the first and second half-bit of a bit a subcarrier modulation is detected, instead of
forwarding a 1-bit or a 0-bit, a bit-collision is flagged.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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To distinguish between a 1-bit or 0-bit from a bit-collision, the RxThreshold register’s
CollLevel[3:0] value is used. If the amplitude of the half-bit with smaller amplitude is larger
than defined by CollLevel[3:0], a bit-collision is flagged by setting the CollErr error flag.
The receiver continues receiving the incoming data stream independently from the
detected collision. In case of a bit-collision, the decoder forwards logic 1 at the collision
position.
Remark: As an exception, if bit ZeroAfterColl is set, all bits received after the first
bit-collision are forced to zero, regardless of whether a bit-collision or an unequivocal
state has been detected. This feature makes it easier for the software to carry out the
anti-collision procedure as defined in ISO/IEC 15693.
When the first bit-collision in a frame is detected, the bit position of the collision is stored in
the CollPos register.
The collision positions are shown in Table 145.
If a collision is detected in the SOF, a frame error is reported and no data is sent to the
FIFO buffer. In this case the receiver continues to monitor the incoming signal and
generates the correct notifications to the microprocessor when the end of the faulty input
stream is detected. This helps the microprocessor to determine the time when it is next
allowed to send data to the label.
11.3.2.4 Communication errors
Table 146 shows the events that set error flags.
Table 145. Return values for bit-collision positions
Collision in bit CollPos register value
(Decimal)
SOF 0
Least Significant Bit (LSB) of the Least Significant Byte (LSByte) 1
… …
Most Significant Bit (MSB) of the LSByte 8
LSB of second byte 9
… …
MSB of second byte 16
LSB of third byte 17
… …
Table 146. Communication error table
Cause Bit set
Received data did not start with a SOF pattern FramingErr
CRC block is not equal to the expected value CRCErr
Received data is shorter than the CRC block CRCErr
A collision is detected CollErrCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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11.3.3 Transceive command 1Eh
The Transceive command first executes the Transmit command (see Section 11.2.1 on
page 79) and then starts the Receive command (see Section 11.2.2 on page 82). All data
to be transmitted is sent using the FIFO buffer and all received data is written to the FIFO
buffer. The Transceive command can be started only by the microprocessor.
Remark: To adjust the timing relationship between transmitting and receiving, use the
RxWait register. This enables the time delay from the last bit transmitted until the receiver
is activated to be defined. The BitPhase register is used to set-up the phase-shift between
the transmitter and the receiver clock.
11.3.4 Label communication states
The status of the transmitter and receiver state machine can be read from the
PrimaryStatus register ModemState[2:0] bits. The assignment of ModemState[2:0] to the
internal action is shown in Table 148.
Table 147. Transceive command 1Eh
Command Value Action Arguments
and data
Returned
data
Transceive 1Eh transmits data from FIFO buffer to the
label and then activates the receiver
data stream data stream
Table 148. ModemState values
ModemState
[2:0]
Name Description
000 Idle transmitter and/or receiver are not operating
001 TxSOF transmitting the start of frame pattern
010 TxData transmitting data from the FIFO buffer (or CRC check bits)
011 TxEOF transmitting the end of frame pattern
100 GoToRx1 intermediate state passed, when receiver starts
GoToRx2 intermediate state passed, when receiver finishes
101 PrepareRx waiting until the RxWait register wait time has elapsed
110 AwaitingRx receiver activated; awaiting an input signal on pin RX
111 Receiving receiving dataCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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11.3.5 Label communication state diagram
(1) I-CODE1 does not have a SOF and an EOF.
Fig 21. Label communication state diagram
001aak622
end of receive frame
and
RxMultiple = 0
time slot period = 0
RxMultiple = 1
time slot period > 0
time slot trigger and
data FIFO
preparing to send the quit value
EOF transmitted and
command = Transceive
FIFO not empty
and command =
Transmit or Transceive
command = Receive
COMMAND =
TRANSMIT,
RECEIVE OR
TRANSCEIVE
SET
COMMAND REGISTER = IDLE
(000)
Awaiting Rx
(110)
RECEIVING
(111)
GoToRx2
(100)
Prepare Rx
(101)
GoToRx1
(100)
TxEOF
(011)
TxData
(010)
TxSOF
(001)
IDLE
(000)
IDLE
(000)
SOF transmitted next bit clock
data transmitted RxWaitC[7:0] = 0
EOF transmitted and
command = Transmit
signal strength > MinLevel[3:0]
frame received
RxMultiple = 0
time slot period > 0
time slot trigger and
FIFO dataCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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11.4 EEPROM commands
11.4.1 WriteE2 command 01h
The WriteE2 command interprets the first two bytes in the FIFO buffer as the EEPROM
start byte address. Any further bytes are interpreted as data bytes and are programmed
into the EEPROM, starting from the given EEPROM start byte address. This command
does not return any data.
The WriteE2 command can only be started by the microprocessor. It will not stop
automatically but has to be stopped explicitly by the microprocessor by issuing the Idle
command.
11.4.1.1 Programming process
One byte up to 16-byte can be programmed into the EEPROM during a single
programming cycle. The time needed is approximately 5.8 ms.
The state machine copies all the prepared data bytes to the FIFO buffer and then to the
EEPROM input buffer. The internal EEPROM input buffer is 16 bytes long which is equal
to the block size of the EEPROM. A programming cycle is started if the last position of the
EEPROM input buffer is written or if the last byte of the FIFO buffer has been read.
The E2Ready flag remains logic 0 when there are unprocessed bytes in the FIFO buffer or
the EEPROM programming cycle is still in progress. When all the data from the FIFO
buffer are programmed into the EEPROM, the E2Ready flag is set to logic 1. Together
with the rising edge of E2Ready the TxIRq interrupt request flag shows logic 1. This can
be used to generate an interrupt when programming of all data is finished.
Remark: During the E2PROM programming indicated by E2Ready = logic 0, the WriteE2
command cannot be stopped using any other command.
Once E2Ready = logic 1, the WriteE2 command can be stopped by the microprocessor by
sending the Idle command.
Table 149. WriteE2 command 01h
Command Value Action FIFO
Arguments and
data
Returned
data
WriteE2 01h get data from FIFO buffer and write it
to the EEPROM
start address LSB -
start address MSB -
data byte stream -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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11.4.1.2 Timing diagram
Figure 22 shows programming five bytes into the EEPROM.
Assuming that the CLRC632 finds and reads byte 0 before the microprocessor is able to
write byte 1 (tprog,del = 300 ns). This causes the CLRC632 to start the programming cycle
(tprog), which takes approximately 5.8 ms to complete. In the meantime, the
microprocessor stores byte 1 to byte 4 in the FIFO buffer.
If the EEPROM start byte address is 16Ch then byte 0 is stored at that address. The
CLRC632 copies the subsequent data bytes into the EEPROM input buffer. Whilst
copying byte 3, it detects that this data byte has to be programmed at the EEPROM byte
address 16Fh. As this is the end of the memory block, the CLRC632 automatically starts a
programming cycle.
Next, byte 4 is programmed at the EEPROM byte address 170h. As this is the last data
byte, the E2Ready and TxIRq flags are set indicating the end of the EEPROM
programming activity.
Although all data has been programmed into the E2PROM, the CLRC632 stays in the
WriteE2 command. Writing more data to the FIFO buffer would lead to another EEPROM
programming cycle continuing from EEPROM byte address 171h. The command is
stopped using the Idle command.
11.4.1.3 WriteE2 command error flags
Programming is restricted for EEPROM block 0 (EEPROM byte address 00h to 0Fh). If
you program these addresses, the AccessErr flag is set and a programming cycle is not
started.
Addresses above 1FFh are taken modulo 200h; see Section 9.2 on page 12 for the
EEPROM memory organization.
Fig 22. EEPROM programming timing diagram
001aak623
NWR
data
WriteE2
command active
EEPROM
programming
E2Ready
TxIRq
write
E2
addr
LSB
addr
MSB byte 0 byte 1
tprog,del
byte 2 byte 3 byte 4
programming byte 0
tprog
programming
byte 1, byte 2 and byte 3
tprog
programming byte 4
tprog
Idle
commandCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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11.4.2 ReadE2 command 03h
The ReadE2 command interprets the first two bytes stored in the FIFO buffer as the
EEPROM starting byte address. The next byte specifies the number of data bytes
returned.
When all three argument bytes are available in the FIFO buffer, the specified number of
data bytes is copied from the EEPROM into the FIFO buffer, starting from the given
EEPROM starting byte address.
The ReadE2 command can only be triggered by the microprocessor and it automatically
stops when all data has been copied.
11.4.2.1 ReadE2 command error flags
Reading is restricted to EEPROM blocks 8h to 1Fh (key memory area). Reading from
these addresses sets the flag AccessErr = logic 1.
Addresses above 1FFh are taken as modulo 200h; see Section 9.2 on page 12 for the
EEPROM memory organization.
11.5 Diverse commands
11.5.1 LoadConfig command 07h
The LoadConfig command interprets the first two bytes found in the FIFO buffer as the
EEPROM starting byte address. When the two argument bytes are available in the FIFO
buffer, 32 bytes from the EEPROM are copied into the Control and other relevant
registers, starting at the EEPROM starting byte address. The LoadConfig command can
only be started by the microprocessor and it automatically stops when all relevant
registers have been copied.
11.5.1.1 Register assignment
The 32 bytes of EEPROM content are written to the CLRC632 registers 10h to register
2Fh; see Section 9.2 on page 12 for the EEPROM memory organization.
Remark: The procedure for the register assignment is the same as it is for the startup
initialization (see Section 9.7.3 on page 30). The difference is, the EEPROM starting byte
address for the startup initialization is fixed to 10h (block 1, byte 0). However, it can be
chosen with the LoadConfig command.
Table 150. ReadE2 command 03h
Command Value Action Arguments Returned data
ReadE2 03h reads EEPROM data and
stores it in the FIFO buffer
start address LSB data bytes
start address MSB
number of data bytes
Table 151. LoadConfig command 07h
Command Value Action Arguments and
data
Returned data
LoadConfig 07h reads data from EEPROM and
initializes the registers
start address LSB -
start address MSB -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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11.5.1.2 Relevant LoadConfig command error flags
Valid EEPROM starting byte addresses are between 10h and 60h.
Copying from block 8h to 1Fh (keys) is restricted. Reading from these addresses sets the
flag AccessErr = logic 1.
Addresses above 1FFh are taken as modulo 200h; see Section 9.2 on page 12 for the
EEPROM memory organization.
11.5.2 CalcCRC command 12h
The CalcCRC command takes all the data from the FIFO buffer as the input bytes for the
CRC coprocessor. All data stored in the FIFO buffer before the command is started is
processed.
This command does not return any data to the FIFO buffer but the content of the CRC can
be read using the CRCResultLSB and CRCResultMSB registers.
The CalcCRC command can only be started by the microprocessor and it does not
automatically stop. It must be stopped by the microprocessor sending the Idle command.
If the FIFO buffer is empty, the CalcCRC command waits for further input before
proceeding.
11.5.2.1 CRC coprocessor settings
Table 153 shows the parameters that can be configured for the CRC coprocessor.
The CRC polynomial for the 8-bit CRC is fixed to x8 + x4 + x3 + x2 + 1.
The CRC polynomial for the 16-bit CRC is fixed to x16 + x12 + x5 + 1.
11.5.2.2 CRC coprocessor status flags
The CRCReady status flag indicates that the CRC coprocessor has finished processing
all the data bytes in the FIFO buffer. When the CRCReady flag is set to logic 1, an
interrupt is requested which sets the TxIRq flag. This supports interrupt driven use of the
CRC coprocessor.
When CRCReady and TxIRq flags are set to logic 1 the content of the CRCResultLSB
and CRCResultMSB registers and the CRCErr flag are valid. The CRCResultLSB and
CRCResultMSB registers hold the content of the CRC, the CRCErr flag indicates CRC
validity for the processed data.
Table 152. CalcCRC command 12h
Command Value Action Arguments and
data
Returned data
CalcCRC 12h activates the CRC coprocessor data byte stream -
Table 153. CRC coprocessor parameters
Parameter Value Bit Register
CRC register
length
8-bit or 16-bit CRC CRC8 ChannelRedundancy
CRC algorithm ISO/IEC 14443 A or ISO/IEC 3309 CRC3309 ChannelRedundancy
CRC preset value any CRCPresetLSB CRCPresetLSB
CRCPresetMSB CRCPresetMSBCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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11.6 Error handling during command execution
If an error is detected during command execution, the PrimaryStatus register Err flag is
set. The microprocessor can evaluate the status flags in the ErrorFlag register to get
information about the cause of the error.
11.7 MIFARE security commands
11.7.1 LoadKeyE2 command 0Bh
The LoadKeyE2 command interprets the first two bytes found in the FIFO buffer as the
EEPROM starting byte address. The EEPROM bytes starting from the given starting byte
address are interpreted as the key when stored in the correct key format as described in
Section 9.2.3.1 “Key format” on page 18. When both argument bytes are available in the
FIFO buffer, the command executes.
The LoadKeyE2 command can only be started by the microprocessor and it automatically
stops after copying the key from the EEPROM to the key buffer.
11.7.1.1 Relevant LoadKeyE2 command error flags
If the key format is incorrect (see Section 9.2.3.1 “Key format” on page 18) an undefined
value is copied into the key buffer and the KeyErr flag is set.
11.7.2 LoadKey command 19h
Table 154. ErrorFlag register error flags overview
Error flag Related commands
KeyErr LoadKeyE2, LoadKey
AccessErr WriteE2, ReadE2, LoadConfig
FIFOOvlf no specific commands
CRCErr Receive, Transceive, CalcCRC
FramingErr Receive, Transceive
ParityErr Receive, Transceive
CollErr Receive, Transceive
Table 155. LoadKeyE2 command 0Bh
Command Value Action Arguments and
data
Returned
data
LoadKeyE2 0Bh reads a key from the EEPROM and
puts it into the internal key buffer
start address LSB -
start address MSB -
Table 156. LoadKey command 19h
Command Value Action Arguments and
data
Returned
data
LoadKey 19h reads a key from the FIFO buffer and puts it
into the key buffer
byte 0 (LSB) -
byte 1 -
… -
byte 10 -
byte 11 (MSB) -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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The LoadKey command interprets the first twelve bytes it finds in the FIFO buffer as the
key when stored in the correct key format as described in Section 9.2.3.1 “Key format” on
page 18. When the twelve argument bytes are available in the FIFO buffer they are
checked and, if valid, are copied into the key buffer.
The LoadKey command can only be started by the microprocessor and it automatically
stops after copying the key from the FIFO buffer to the key buffer.
11.7.2.1 Relevant LoadKey command error flags
All bytes requested are copied from the FIFO buffer to the key buffer. If the key format is
not correct (see Section 9.2.3.1 “Key format” on page 18) an undefined value is copied
into the key buffer and the KeyErr flag is set.
11.7.3 Authent1 command 0Ch
The Authent1 command is a special Transceive command; it sends six argument bytes to
the card. The card’s response is not sent to the microprocessor, it is used instead to
authenticate the card to the CLRC632 and vice versa.
The Authent1 command can be triggered only by the microprocessor. The sequence of
states for this command are the same as those for the Transceive command; see
Section 11.2.3 on page 85.
11.7.4 Authent2 command 14h
The Authent2 command is a special Transceive command. It does not need any argument
byte, however all the data needed to be sent to the card is assembled by the CLRC632.
The card response is not sent to the microprocessor but is used to authenticate the card
to the CLRC632 and vice versa.
The Authent2 command can only be started by the microprocessor. The sequence of
states for this command are the same as those for the Transceive command; see
Section 11.2.3 on page 85.
Table 157. Authent1 command 0Ch
Command Value Action Arguments and data Returned
data
Authent1 0Ch performs the first part of the Crypto1
card authentication
card Authent1 command -
card block address -
card serial number LSB -
card serial number byte1 -
card serial number byte2 -
card serial number MSB -
Table 158. Authent2 command 14h
Command Value Action Arguments
and data
Returned
data
Authent2 14h performs the second part of the card
authentication using the Crypto1 algorithm
- -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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11.7.4.1 Authent2 command effects
If the Authent2 command is successful, the authenticity of card and the CLRC632 are
proved. This automatically sets the Crypto1On control bit. When bit Crypto1On = logic 1,
all further card communication is encrypted using the Crypto1 security algorithm. If the
Authent2 command fails, bit Crypto1On is cleared (Crypto1On = logic 0).
Remark: The Crypto1On flag can only be set by a successfully executed Authent2
command and not by the microprocessor. The microprocessor can clear bit Crypto1On to
continue with unencrypted (plain) card communication.
Remark: The Authent2 command must be executed immediately after a successful
Authent1 command; see Section 11.7.3 “Authent1 command 0Ch”. In addition, the keys
stored in the key buffer and those on the card must match.
12. Limiting values
13. Characteristics
13.1 Operating condition range
Table 159. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Tamb ambient temperature 40 +150 C
Tstg storage temperature 40 +150 C
VDDD digital supply voltage 0.5 +6 V
VDDA analog supply voltage 0.5 +6 V
VDD(TVDD) TVDD supply voltage 0.5 +6 V
Vi
input voltage (absolute value) on any digital pin to DVSS 0.5 VDDD + 0.5 V
on pin RX to AVSS 0.5 VDDA + 0.5 V
Table 160. Operating condition range
Symbol Parameter Conditions Min Typ Max Unit
Tamb ambient temperature - 25 +25 +85 C
VDDD digital supply voltage DVSS = AVSS = TVSS = 0 V 3.0 3.3 3.6 V
4.5 5.0 5.5 V
VDDA analog supply voltage DVSS = AVSS = TVSS = 0 V 4.5 5.0 5.5 V
VDD(TVDD) TVDD supply voltage DVSS = AVSS = TVSS = 0 V 3.0 5.0 5.5 V
VESD electrostatic discharge voltage Human Body Model (HBM); 1.5 k,
100 pF
- - 1000 V
Machine Model (MM); 0.75 H,
200 pF
- - 100 VCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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13.2 Current consumption
13.3 Pin characteristics
13.3.1 Input pin characteristics
Pins D0 to D7, A0, and A1 have TTL input characteristics and behave as defined in
Table 162.
The digital input pins NCS, NWR, NRD, ALE, A2, and MFIN have Schmitt trigger
characteristics, and behave as defined in Table 163.
Table 161. Current consumption
Symbol Parameter Conditions Min Typ Max Unit
IDDD digital supply current Idle command - 8 11 mA
Standby mode - 3 5 mA
Soft power-down mode - 800 1000 A
Hard power-down mode - 1 10 A
IDDA analog supply current Idle command; receiver on - 25 40 mA
Idle command; receiver off - 12 15 mA
Standby mode - 10 13 mA
Soft power-down mode - 1 10 A
Hard power-down mode - 1 10 A
IDD(TVDD) TVDD supply current continuous wave - - 150 mA
pins TX1 and TX2 unconnected;
TX1RFEn and TX2RFEn = logic 1
- 5.5 7 mA
pins TX1 and TX2 unconnected;
TX1RFEn and TX2RFEn = logic 0
- 65 130 A
Table 162. Standard input pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
ILI input leakage current 1.0 - +1.0 A
Vth threshold voltage CMOS: VDDD < 3.6 V 0.35VDDD - 0.65VDDD V
TTL: 4.5 < VDDD 0.8 - 2.0 V
Table 163. Schmitt trigger input pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
ILI input leakage current 1.0 - +1.0 A
Vth threshold voltage positive-going threshold;
TTL = 4.5 < VDDD
1.4 - 2.0 V
CMOS = VDDD < 3.6 V 0.65VDDD - 0.75VDDD V
negative-going threshold;
TTL = 4.5 < VDDD
0.8 - 1.3 V
CMOS = VDDD < 3.6 V 0.25VDDD - 0.4VDDD VCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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Pin RSTPD has Schmitt trigger CMOS characteristics. In addition, it is internally filtered by
a RC low-pass filter which causes a propagation delay on the reset signal.
The analog input pin RX has the input capacitance and input voltage range shown in
Table 165.
13.3.2 Digital output pin characteristics
Pins D0 to D7, MFOUT and IRQ have CMOS output characteristics and behave as
defined in Table 166.
Remark: Pin IRQ can be configured as open collector which causes the VOH values to be
no longer applicable.
13.3.3 Antenna driver output pin characteristics
The source conductance of the antenna driver pins TX1 and TX2 for driving the
HIGH-level can be configured using the CwConductance register’s GsCfgCW[5:0] bits,
while their source conductance for driving the LOW-level is constant.
The antenna driver default configuration output characteristics are specified in Table 167.
Table 164. RSTPD input pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
ILI input leakage current 1.0 - +1.0 A
Vth threshold voltage positive-going threshold;
CMOS = VDDD < 3.6 V
0.65VDDD - 0.75VDDD V
negative-going threshold;
CMOS = VDDD < 3.6 V
0.25VDDD - 0.4VDDD V
tPD propagation delay - - 20 s
Table 165. RX input capacitance and input voltage range
Symbol Parameter Conditions Min Typ Max Unit
Ci input capacitance - - 15 pF
Vi(dyn) dynamic input voltage VDDA = 5 V; Tamb = 25 C 1.1 - 4.4 V
Table 166. Digital output pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
VOH HIGH-level output
voltage
VDDD = 5 V; IOH = 1 mA 2.4 4.9 - V
VDDD = 5 V; IOH = 10 mA 2.4 4.2 - V
VOL LOW-level output
voltage
VDDD = 5 V; IOL = 1 mA - 25 400 mV
VDDD = 5 V; IOL = 10 mA - 250 400 mV
IO output current source or sink; VDDD = 5 V - - 10 mACLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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13.4 AC electrical characteristics
13.4.1 Separate read/write strobe bus timing
Table 167. Antenna driver output pin characteristics
Symbol Parameter Conditions Min Typ Max Unit
VOH HIGH-level output
voltage
VDD(TVDD) = 5.0 V; IOL = 20 mA - 4.97 - V
VDD(TVDD) = 5.0 V; IOL = 100 mA - 4.85 - V
VOL LOW-level output
voltage
VDD(TVDD) = 5.0 V; IOL = 20 mA - 30 - mV
VDD(TVDD) = 5.0 V; IOL = 100 mA - 150 - mV
IO output current transmitter; continuous wave;
peak-to-peak
- - 200 mA
Table 168. Timing specification for separate read/write strobe
Symbol Parameter Conditions Min Typ Max Unit
tLHLL ALE HIGH time 20 - - ns
tAVLL address valid to ALE LOW time 15 - - ns
tLLAX address hold after ALE LOW
time
8 - - ns
tLLRWL ALE LOW to read/write LOW
time
ALE LOW to NRD or
NWR LOW
15 - - ns
tSLRWL chip select LOW to read/write
LOW time
NCS LOW to NRD or
NWR LOW
0 - - ns
tRWHSH read/write HIGH to chip select
HIGH time
NRD or NWR HIGH to
NCS HIGH
0 - - ns
tRLDV read LOW to data input valid
time
NRD LOW to data valid - - 65 ns
tRHDZ read HIGH to data input high
impedance time
NRD HIGH to data
high-impedance
- - 20 ns
tWLQV write LOW to data output valid
time
NWR LOW to data valid - - 35 ns
tWHDX data output hold after write
HIGH time
data hold time after
NWR HIGH
8 - - ns
tRWLRWH read/write LOW time NRD or NWR 65 - - ns
tAVRWL address valid to read/write
LOW time
NRD or NWR LOW
(set-up time)
30 - - ns
tWHAX address hold after write HIGH
time
NWR HIGH (hold time) 8 - - ns
tRWHRWL read/write HIGH time 150 - - nsCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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Remark: The signal ALE is not relevant for separate address/data bus and the
multiplexed addresses on the data bus do not care. The multiplexed address and data bus
address lines (A0 to A2) must be connected as described in Section 9.1.3 on page 8.
13.4.2 Common read/write strobe bus timing
Fig 23. Separate read/write strobe timing diagram
001aaj638
tSLRWL tRWHSH
tRWHRWL
tWHDX
tRHDZ
tWLQV
tRLDV
tAVRWL tWHAX
tAVLL tLLAX
tRWLRWH
tLLRWL
tRWHRWL
tLHLL
A0 to A2
A0 to A2
D0 to D7 D0 to D7
NWR
NRD
NCS
ALE
A0 to A2
Multiplexed address bus
Separated address bus
Table 169. Common read/write strobe timing specification
Symbol Parameter Conditions Min Typ Max Unit
tLHLL ALE HIGH time 20 - - ns
tAVLL address valid to ALE LOW time 15 - - ns
tLLAX address hold after ALE LOW time 8 - - ns
tLLDSL ALE LOW to data strobe LOW time NWR or NRD
LOW
15 - - ns
tSLDSL chip select LOW to data strobe
LOW time
NCS LOW to
NDS LOW
0 - - ns
tDSHSH data strobe HIGH to chip select
HIGH time
0 - - ns
tDSLDV data strobe LOW to data input valid
time
- - 65 ns
tDSHDZ data strobe HIGH to data input high
impedance time
- - 20 ns
tDSLQV data strobe LOW to data output
valid time
NDS/NCS LOW - - 35 ns
tDSHQX data output hold after data strobe
HIGH time
NDS HIGH (write
cycle hold time)
8 - - ns
tDSHRWX RW hold after data strobe HIGH
time
after NDS HIGH 8 - - ns
tDSLDSH data strobe LOW time NDS/NCS 65 - - nsCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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13.4.3 EPP bus timing
tAVDSL address valid to data strobe LOW
time
30 - - ns
tRHAX address hold after read HIGH time 8 - - ns
tDSHDSL data strobe HIGH time period between
write sequences
150 - - ns
tWLDSL write LOW to data strobe LOW time R/NW valid to
NDS LOW
8 - - ns
Fig 24. Common read/write strobe timing diagram
Table 169. Common read/write strobe timing specification …continued
Symbol Parameter Conditions Min Typ Max Unit
001aaj639
tSLDSL tDSHSH
tDSHDSL
tDSHQX
tDSHDZ
tDSLDV
tDSLQV
tAVDSL tRHAX
tAVLL tLLAX
tDSLDSH
tLLDSL
tDSHDSL
tLHLL
tWLDSL tDSHRWX
A0 to A2
A0 to A2
D0 to D7 D0 to D7
NRD
R/NW
NCS/NDS
ALE
A0 to A2
Multiplexed address bus
Separated address bus
Table 170. Common read/write strobe timing specification for EPP
Symbol Parameter Conditions Min Typ Max Unit
tASLASH address strobe LOW time nAStrb 20 - - ns
tAVASH address valid to address strobe
HIGH time
multiplexed address
bus set-up time
15 - - ns
tASHAV address valid after address strobe
HIGH time
multiplexed address
bus hold time
8 - - ns
tSLDSL chip select LOW to data strobe
LOW time
NCS LOW to nDStrb
LOW
0 - - ns
tDSHSH data strobe HIGH to chip select
HIGH time
nDStrb HIGH to
NCS HIGH
0 - - ns
tDSLDV data strobe LOW to data input valid
time
read cycle - - 65 nsCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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Remark: Figure 25 does not distinguish between the address write cycle and a data write
cycle. The timings for the address write and data write cycle are different. In EPP mode,
the address lines (A0 to A2) must be connected as described in Section 9.1.3 on page 8.
tDSHDZ data strobe HIGH to data input high
impedance time
read cycle - - 20 ns
tDSLQV data strobe LOW to data output
valid time
nDStrb LOW - - 35 ns
tDSHQX data output hold after data strobe
HIGH time
NCS HIGH 8 - - ns
tDSHWX write hold after data strobe HIGH
time
nWrite 8 - - ns
tDSLDSH data strobe LOW time nDStrb 65 - - ns
tWLDSL write LOW to data strobe LOW time nWrite valid to
nDStrb LOW
8 - - ns
tDSL-WAITH data strobe LOW to WAIT HIGH
time
nDStrb LOW to
nWrite HIGH
- - 75 ns
tDSH-WAITL data strobe HIGH to WAIT LOW
time
nDStrb HIGH to
nWrite LOW
- - 75 ns
Fig 25. Timing diagram for common read/write strobe; EPP
Table 170. Common read/write strobe timing specification for EPP …continued
Symbol Parameter Conditions Min Typ Max Unit
001aaj640
nWait
tDSL-WAITH
tDSLDV
tDSLQV
tWLDSL
tSLDSL
tDSHSH
tDSLDSH
D0 to D7
A0 to A7
tDSHQX
tDSHDZ
tDSH-WAITL
tDSHWX
D0 to D7
nDStrb
nAStrb
nWrite
NCSCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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13.4.4 SPI timing
Remark: To send more bytes in one data stream the NSS signal must be LOW during the
send process. To send more than one data stream the NSS signal must be HIGH between
each data stream.
13.4.5 Clock frequency
The clock input is pin OSCIN.
The clock applied to the CLRC632 acts as a time constant for the synchronous system’s
encoder and decoder. The stability of the clock frequency is an important factor for
ensuring proper performance. To obtain highest performance, clock jitter must be as small
as possible. This is best achieved using the internal oscillator buffer and the
recommended circuitry; see Section 9.8 on page 30.
Table 171. SPI timing specification
Symbol Parameter Conditions Min Typ Max Unit
tSCKL SCK LOW time 100 - - ns
tSCKH SCK HIGH time 100 - - ns
tDSHQX data output hold after data strobe
HIGH time
20 - - ns
tDQXCH data input/output changing to clock
HIGH time
20 - - ns
th(SCKL-Q) SCK LOW to data output hold time - - 15 ns
t(SCKL-NSSH) SCK LOW to NSS HIGH time 20 - - ns
Fig 26. Timing diagram for SPI
001aaj64
tNSSH tSCKL tSCKH tSCKL
th(SCKL-Q) tsu(D-SCKH)
th(SCKH-D)
th(SCKL-Q)
t(SCKL-NSSH)
SCK
OSI
ISO
MSB
MSB
LSB
LSB
NSS
Table 172. Clock frequency
Symbol Parameter Conditions Min Typ Max Unit
fclk clock frequency checked by the clock
filter
- 13.56 - MHz
clk clock duty cycle 40 50 60 %
tjit jitter time of clock edges - - 10 psCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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14. EEPROM characteristics
The EEPROM size is 32 16 8 = 4096 bit.
15. Application information
15.1 Typical application
15.1.1 Circuit diagram
Figure 27 shows a typical application where the antenna is directly matched to the
CLRC632:
Table 173. EEPROM characteristics
Symbol Parameter Conditions Min Typ Max Unit
Nendu(W_ER) write or erase endurance erase/write cycles 100.000 - - Hz
tret retention time Tamb 55 C 10 - - year
ter erase time - - 2.9 ms
ta(W) write access time - - 2.9 ms
Fig 27. Application example circuit diagram: directly matched antenna
001aak625
DVDD RSTPD AVDD TVDD
DVDD Reset AVDD TVDD
DVSS
control lines
data bus
IRQ
OSCIN OSCOUT
13.56 MHz
AVSS
VMID
RX
TX2
TVSS
TX1
IRQ
15 pF 15 pF
C0
C0 C2a
C2b
C3
R2
R1
L0
L0 C1
C1
C4
100 nF
MICROPROCESSOR
BUS
MICROPROCESSOR
DEVICECLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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15.1.2 Circuit description
The matching circuit consists of an EMC low-pass filter (L0 and C0), matching circuitry
(C1 and C2), a receiver circuit (R1, R2, C3 and C4) and the antenna itself.
Refer to the following application notes for more detailed information about designing and
tuning an antenna.
• MICORE reader IC family; Directly Matched Antenna Design Ref. 1
• MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas Ref. 2.
15.1.2.1 EMC low-pass filter
The MIFARE system operates at a frequency of 13.56 MHz. This frequency is generated
by a quartz oscillator to clock the CLRC632. It is also the basis for driving the antenna
using the 13.56 MHz energy carrier. This not only causes power emissions at 13.56 MHz,
it also emits power at higher harmonics. International EMC regulations define the
amplitude of the emitted power over a broad frequency range. To meet these regulations,
appropriate filtering of the output signal is required.
A multilayer board is recommended to implement a low-pass filter as shown in Figure 27.
The low-pass filter consists of the components L0 and C0. The recommended values are
given in Application notes MICORE reader IC family; Directly Matched Antenna Design
Ref. 1 and MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas Ref. 2.
Remark: To achieve best performance, all components must be at least equal in quality to
those recommended.
Remark: The layout has a major influence on the overall performance of the filter.
15.1.2.2 Antenna matching
Due to the impedance transformation of the low-pass filter, the antenna coil has to be
matched to a given impedance. The matching elements C1 and C2 can be estimated and
have to be fine tuned depending on the design of the antenna coil.
The correct impedance matching is important to ensure optimum performance. The
overall quality factor has to be considered to guarantee a proper ISO/IEC 14443 A and
ISO/IEC 14443 B communication schemes. Environmental influences have to considered
and common EMC design rules.
Refer to Application notes MICORE reader IC family; Directly Matched Antenna Design
Ref. 1 and MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas Ref. 2 for details.
Remark: Do not exceed the current limits (IDD(TVDD)), otherwise the chip might be
destroyed.
Remark: The overall 13.56 MHz RFID proximity antenna design in combination with the
CLRC632 IC does not require any specialist RF knowledge. However, all relevant
parameters have to be considered to guarantee optimum performance and international
EMC compliance.
15.1.2.3 Receiver circuit
The internal receiver of the CLRC632 makes use of both subcarrier load modulation
side-bands. No external filtering is required.CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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It is recommended to use the internally generated VMID potential as the input potential for
pin RX. This VMID DC voltage level has to be coupled to pin RX using resistor (R2). To
provide a stable DC reference voltage, a capacitor (C4) must be connected between
VMID and ground.
The AC voltage divider of R1 + C3 and R2 has to be designed taking in to account the AC
voltage limits on pin RX. Depending on the antenna coil design and the impedance,
matching the voltage at the antenna coil will differ. Therefore the recommended way to
design the receiver circuit is to use the given values for R1, R2, and C3; refer to
Application note; MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas Ref. 2. The
voltage on pin RX can be altered by varying R1 within the given limits.
Remark: R2 is AC connected to ground using C4.
15.1.2.4 Antenna coil
The precise calculation of the antenna coil’s inductance is not practicable but the
inductance can be estimated using Equation 10. We recommend designing an antenna
that is either circular or rectangular.
(10)
• l1 = length of one turn of the conductor loop
• D1 = diameter of the wire or width of the PCB conductor, respectively
• K = antenna shape factor (K = 1.07 for circular antennas and K = 1.47 for square
antennas)
• N1 = number of turns
• ln = natural logarithm function
The values of the antenna inductance, resistance, and capacitance at 13.56 MHz depend
on various parameters such as:
• antenna construction (type of PCB)
• thickness of conductor
• distance between the windings
• shielding layer
• metal or ferrite in the near environment
Therefore a measurement of these parameters under real life conditions or at least a
rough measurement and a tuning procedure is highly recommended to guarantee a
reasonable performance. Refer to Application notes MICORE reader IC family; Directly
Matched Antenna Design Ref. 1 and MIFARE (14443 A) 13.56 MHz RFID Proximity
Antennas Ref. 2 for details.
L1 nH = 2 I1 cm
I1
D1
ln K ------ – N1
1.8 CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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15.2 Test signals
The CLRC632 allows different kinds of signal measurements. These measurements can
be used to check the internally generated and received signals using the serial signal
switch as described in Section 9.11 on page 37.
In addition, the CLRC632 enables users to select between:
• internal analog signals for measurement on pin AUX
• internal digital signals for observation on pin MFOUT (based on register selections)
These measurements can be helpful during the design-in phase to optimize the receiver’s
behavior, or for test purposes.
15.2.1 Measurements using the serial signal switch
Using the serial signal switch on pin MFOUT, data is observed that is sent to the card or
received from the card. Table 174 gives an overview of the different signals available.
Remark: The routing of the Manchester or the Manchester with subcarrier signal to pin
MFOUT is only possible at 106 kBd based on ISO/IEC 14443 A.
15.2.1.1 TX control
Figure 28 shows as an example of an ISO/IEC 14443 A communication.
The signal is measured on pin MFOUT using the serial signal switch to control the data
sent to the card. Setting the flag MFOUTSelect[2:0] = 3 sends the data to the card coded
as NRZ. Setting MFOUTSelect[2:0] = 2 shows the data as a Miller coded signal.
The RFOut signal is measured directly on the antenna and gives the RF signal pulse
shape. Refer to Application note Directly matched Antenna - Excel calculation (Ref. 3) for
detail information on the RF signal pulse.
Table 174. Signal routed to pin MFOUT
SignalToMFOUT MFOUTSelect Signal routed to pin MFOUT
0 0 LOW
0 1 HIGH
0 2 envelope
0 3 transmit NRZ
0 4 Manchester with subcarrier
0 5 Manchester
0 6 reserved
0 7 reserved
1 X digital test signalCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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15.2.1.2 RX control
Figure 29 shows an example of ISO/IEC 14443 A communication which represents the
beginning of a card’s answer to a request signal.
The RF signal shows the RF voltage measured directly on the antenna so that the card’s
load modulation is visible. Setting MFOUTSelect[2:0] = 4 shows the Manchester decoded
signal with subcarrier. Setting MFOUTSelect[2:0] = 5 shows the Manchester decoded
signal.
(1) MFOUTSelect[2:0] = 3; serial data stream; 2 V per division.
(2) MFOUTSelect[2:0] = 2; serial data stream; 2 V per division.
(3) RFOut; 1 V per division.
Fig 28. TX control signals
001aak626
(1)
(2)
(3)
10 μs per divisionCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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15.2.2 Analog test signals
The analog test signals can be routed to pin AUX by selecting them using the
TestAnaSelect register TestAnaOutSel[4:0] bits.
(1) RFOut; 1 V per division.
(2) MFOUTSelect[2:0] = 4; Manchester with subcarrier; 2 V per division.
(3) MFOUTSelect[2:0] = 5; Manchester; 2 V per division.
Fig 29. RX control signals
001aak627
10 μs per division
(1)
(2)
(3)
Table 175. Analog test signal selection
Value Signal Name Description
0 VMID voltage at internal node VMID
1 Vbandgap internal reference voltage generated by the bandgap
2 VRxFollI output signal from the demodulator using the I-clock
3 VRxFollQ output signal from the demodulator using the Q-clock
4 VRxAmpI I-channel subcarrier signal amplified and filtered
5 VRxAmpQ Q-channel subcarrier signal amplified and filtered
6 VCorrNI output signal of N-channel correlator fed by the I-channel subcarrier
signal
7 VCorrNQ output signal of N-channel correlator fed by the Q-channel subcarrier
signal
8 VCorrDI output signal of D-channel correlator fed by the I-channel subcarrier
signal
9 VCorrDQ output signal of D-channel correlator fed by the Q-channel subcarrier
signal
A VEvalL evaluation signal from the left half-bitCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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15.2.3 Digital test signals
Digital test signals can be routed to pin MFOUT by setting bit SignalToMFOUT = logic 1. A
digital test signal is selected using the TestDigiSelect register TestDigiSignalSel[6:0] bits.
The signals selected by the TestDigiSignalSel[6:0] bits are shown in Table 176.
If test signals are not used, the TestDigiSelect register address value must be 00h.
Remark: All other values for TestDigiSignalSel[6:0] are for production test purposes only.
15.2.4 Examples of ISO/IEC 14443 A analog and digital test signals
Figure 30 shows a MIFARE card’s answer to a request command using the Q-clock
receiving path. RX reference is given to show the Manchester modulated signal on pin
RX.
The signal is demodulated and amplified in the receiver circuitry. Signal VRXAmpQ is the
amplified side-band signal using the Q-clock for demodulation. The signals VCorrDQ and
VCorrNQ were generated in the correlation circuitry. They are processed further in the
evaluation and digitizer circuitry.
B VEvalR evaluation signal from the right half-bit
C VTemp temperature voltage derived from band gap
D reserved reserved for future use
E reserved reserved for future use
F reserved reserved for future use
Table 175. Analog test signal selection …continued
Value Signal Name Description
Table 176. Digital test signal selection
TestDigiSignalSel
[6:0]
Signal name Description
F4h s_data data received from the card
E4h s_valid when logic 1 is returned the s_data and s_coll signals are
valid
D4h s_coll when logic 1 is returned a collision has been detected in the
current bit
C4h s_clock internal serial clock:
during transmission, this is the encoder clock
during reception this is the receiver clock
B5h rd_sync internal synchronized read signal which is derived from the
parallel microprocessor interface
A5h wr_sync internal synchronized write signal which is derived from the
parallel microprocessor interface
96h int_clock internal 13.56 MHz clock
83h BPSK_out BPSK output signal
E2h BPSK_sig BPSK signal’s amplitude detected
00h no test signal output as defined by the MFOUTSelect register
MFOUTSelect[2:0] bits routed to pin MFOUTCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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Signals VEvalR and VEvalL show the evaluation of the signal’s right and left half-bit.
Finally, the digital test signal s_data shows the received data. This is then sent to the
internal digital circuit and s_valid which indicates the received data stream is valid.
15.2.5 Examples of I-CODE1 analog and digital test signals
Figure 31 shows the answer of an I-CODE1 label IC to an unselected read command
using the Q-clock receiving path. RX reference is given to show the Manchester
modulated signal on pin RX.
The signal is demodulated and amplified in the receiver circuitry. Signal VRXAmpQ is the
amplified side-band signal using the Q-clock for demodulation. The signals VCorrDQ and
VCorrNQ generated in the correlation circuitry are processed further in the evaluation and
digitizer circuitry.
Signals VEvalR and VEvalL are the evaluation signal of the right and left half-bit. Finally,
the digital test-signal s_data shows the received data. This is then routed to the internal
digital circuit and s_valid indicates that the received data stream is valid.
Fig 30. ISO/IEC 14443 A receiving path Q-clock
001aak628
RX reference
VRxAmpQ
VCorrDQ
VCorrNQ
VEvalR
VEvalL
s_data
s_valid
50 μs per divisionCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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Fig 31. I-CODE1 receiving path Q-clock
VRxAmpQ
VCorrDQ
VCorrNQ
VEvalR
VEvalL
s_data
s_valid
receiving path Q-Clock
50 μs per division
001aak629
500 μs per divisionCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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16. Package outline
Fig 32. Package outline SOT287-1
UNIT
A
max. A1 A2 A3 bp c D(1) E(1) e HE L Lp Q Z ywv θ
OUTLINE REFERENCES
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
2.65
0.1
0.25
0.01
1.4
0.055
0.3
0.1
2.45
2.25
0.49
0.36
0.27
0.18
20.7
20.3
7.6
7.4 1.27 10.65
10.00
1.2
1.0
0.95
0.55 8
0
o
o
0.25 0.1
0.004
0.25
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.1
0.4
SOT287-1 MO-119
(1)
0.012
0.004
0.096
0.089
0.02
0.01 0.05 0.047
0.039
0.419
0.394
0.30
0.29
0.81
0.80
0.011
0.007
0.037
0.022 0.01 0.01 0.043
0.016
w M bp
D
HE
Z
e
c
v M A
X
A
y
32 17
1 16
θ
A
A1
A2
Lp
Q
detail X
L
(A ) 3
E
pin 1 index
0 5 10 mm
scale
SO32: plastic small outline package; 32 leads; body width 7.5 mm SOT287-1
00-08-17
03-02-19CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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17. Abbreviations
18. References
[1] Application note — MICORE reader IC family; Directly Matched Antenna Design.
[2] Application note — MIFARE (14443 A) 13.56 MHz RFID Proximity Antennas.
[3] Application note — Directly matched Antenna - Excel calculation.
[4] ISO standard — ISO/IEC 14443 Identification cards - Contactless integrated
circuit(s) cards - Proximity cards, part 1-4.
[5] Application note — MIFARE Implementation of Higher Baud rates.
Table 177. Abbreviations and acronyms
Acronym Description
ASK Amplitude-Shift Keying
BPSK Binary Phase-Shift Keying
CMOS Complementary Metal-Oxide Semiconductor
CRC Cyclic Redundancy Check
EOF End Of Frame
EPP Enhanced Parallel Port
ETU Elementary Time Unit
FIFO First In, First Out
HBM Human Body Model
LSB Least Significant Bit
MM Machine Model
MSB Most Significant Bit
NRZ None Return to Zero
POR Power-On Reset
PCD Proximity Coupling Device
PICC Proximity Integrated Circuit Card
SOF Start Of Frame
SPI Serial Peripheral InterfaceCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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19. Revision history
Table 178. Revision history
Document ID Release date Data sheet status Change notice Supersedes
CLRC632 v. 3.7 20140227 Product data sheet - CLRC632 v. 3.6
Modifications: • Section 2 “General description”: 1st paragraph updated
CLRC632 v. 3.6 20140130 Product data sheet - CLRC632_35
Modifications: • Section 2 “General description”: updated
• Change of descriptive title
CLRC632_35 20091110 Product data sheet - CLRC632_34
Modifications: • Data sheet security status changed from COMPANY CONFIDENTIAL to COMPANY PUBLIC
• RATP/Innovatron Technologies license statement added to the legal page
CLRC632_34 20091014 Product data sheet - 073933
Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors
• Legal texts have been adapted to the new company name where appropriate
• The symbols for electrical characteristics and their parameters have been updated to meet the
NXP Semiconductors’ guidelines
• A number of inconsistencies in pin, register and bit names have been eliminated from the data sheet
• All drawings have been updated
• Several symbol changes made to drawings in Figure 23 on page 103 to Figure 26 on page 106
• Section 5 “Quick reference data” on page 3: section added
• Section 6 “Ordering information” on page 3: updated
• Section 15.1.2.4 “Antenna coil” on page 109: added missing formula and updated the last clause
• Section 16 “Package outline” on page 116: updated
• Section 18 “References” on page 117: added section and updated the references in the document
073933 December 2005 Product data sheet 073932
073932 April 2005 Product data sheet 073931
073931 May 2004 Product data sheet 073930
073930 November 2002 Product data sheet 073920
073920 June 2002 Preliminary data sheet 073910
073910 January 2002 internal version -CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
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073937 119 of 127
NXP Semiconductors CLRC632
Standard multi-protocol reader solution
20. Legal information
20.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
20.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification. CLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 27 February 2014
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NXP Semiconductors CLRC632
Standard multi-protocol reader solution
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
20.4 Licenses
20.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
MIFARE — is a trademark of NXP Semiconductors N.V.
ICODE and I-CODE — are trademarks of NXP Semiconductors N.V.
MIFARE Ultralight — is a trademark of NXP Semiconductors N.V.
21. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Purchase of NXP ICs with ISO/IEC 14443 type B functionality
This NXP Semiconductors IC is ISO/IEC 14443 Type B
software enabled and is licensed under Innovatron’s
Contactless Card patents license for ISO/IEC 14443 B.
The license includes the right to use the IC in systems
and/or end-user equipment.
RATP/Innovatron
TechnologyCLRC632 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 27 February 2014
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NXP Semiconductors CLRC632
Standard multi-protocol reader solution
22. Tables
Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .3
Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .3
Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 4. Supported microprocessor and EPP interface
signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 5. Connection scheme for detecting the parallel
interface type . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 6. SPI compatibility . . . . . . . . . . . . . . . . . . . . . . .10
Table 7. SPI read data . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 8. SPI read address . . . . . . . . . . . . . . . . . . . . . . . 11
Table 9. SPI write data . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 10. SPI write address . . . . . . . . . . . . . . . . . . . . . . 11
Table 11. EEPROM memory organization diagram . . . . .12
Table 12. Product information field . . . . . . . . . . . . . . . . .13
Table 13. Product type identification definition . . . . . . . .13
Table 14. Byte assignment for register initialization at
start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 15. Shipment content of StartUp configuration file .15
Table 16. Byte assignment for register initialization at
startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 17. Content of I-CODE1 startup configuration . . . .17
Table 18. FIFO buffer access . . . . . . . . . . . . . . . . . . . . .19
Table 19. Associated FIFO buffer registers and flags . . .20
Table 20. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . .21
Table 21. Interrupt control registers . . . . . . . . . . . . . . . .21
Table 22. Associated Interrupt request system registers
and flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 23. TimeSlotPeriod . . . . . . . . . . . . . . . . . . . . . . . .26
Table 24. Associated timer unit registers and flags . . . . .27
Table 25. Signal on pins during Hard power-down . . . . .28
Table 26. Pin TX1 configurations . . . . . . . . . . . . . . . . . .31
Table 27. Pin TX2 configurations . . . . . . . . . . . . . . . . . .32
Table 28. TX1 and TX2 source resistance of n-channel
driver transistor against GsCfgCW or
GsCfgMod . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 29. Gain factors for the internal amplifier . . . . . . . .36
Table 30. DecoderSource[1:0] values . . . . . . . . . . . . . . .39
Table 31. ModulatorSource[1:0] values . . . . . . . . . . . . . .39
Table 32. MFOUTSelect[2:0] values . . . . . . . . . . . . . . . .39
Table 33. Register settings to enable use of the analog
circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 34. MIFARE higher baud rates . . . . . . . . . . . . . . .40
Table 35. ISO/IEC 14443 B registers and flags . . . . . . . .41
Table 36. Dedicated address bus: assembling the
register address . . . . . . . . . . . . . . . . . . . . . . . .43
Table 37. Multiplexed address bus: assembling the
register address . . . . . . . . . . . . . . . . . . . . . . . .44
Table 38. Behavior and designation of register bits . . . . .44
Table 39. CLRC632 register overview . . . . . . . . . . . . . . .45
Table 40. CLRC632 register flags overview . . . . . . . . . .47
Table 41. Page register (address: 00h, 08h, 10h, 18h,
20h, 28h, 30h, 38h) reset value: 1000 0000b,
80h bit allocation . . . . . . . . . . . . . . . . . . . . . . .50
Table 42. Page register bit descriptions . . . . . . . . . . . . .50
Table 43. Command register (address: 01h) reset
value: x000 0000b, x0h bit allocation . . . . . . .50
Table 44. Command register bit descriptions . . . . . . . . . 50
Table 45. FIFOData register (address: 02h) reset value:
xxxx xxxxb, 05h bit allocation . . . . . . . . . . . . . 51
Table 46. FIFOData register bit descriptions . . . . . . . . . 51
Table 47. PrimaryStatus register (address: 03h) reset
value: 0000 0101b, 05h bit allocation . . . . . . . 51
Table 48. PrimaryStatus register bit descriptions . . . . . . 51
Table 49. FIFOLength register (address: 04h) reset
value: 0000 0000b, 00h bit allocation . . . . . . . 52
Table 50. FIFOLength bit descriptions . . . . . . . . . . . . . . 52
Table 51. SecondaryStatus register (address: 05h)
reset value: 01100 000b, 60h bit allocation . . . 53
Table 52. SecondaryStatus register bit descriptions . . . . 53
Table 53. InterruptEn register (address: 06h) reset
value: 0000 0000b, 00h bit allocation . . . . . . . 53
Table 54. InterruptEn register bit descriptions . . . . . . . . 53
Table 55. InterruptRq register (address: 07h) reset
value: 0000 0000b, 00h bit allocation . . . . . . . 54
Table 56. InterruptRq register bit descriptions . . . . . . . . 54
Table 57. Control register (address: 09h) reset value:
0000 0000b, 00h bit allocation . . . . . . . . . . . . 55
Table 58. Control register bit descriptions . . . . . . . . . . . 55
Table 59. ErrorFlag register (address: 0Ah) reset value:
0100 0000b, 40h bit allocation . . . . . . . . . . . . 55
Table 60. ErrorFlag register bit descriptions . . . . . . . . . . 55
Table 61. CollPos register (address: 0Bh) reset value:
0000 0000b, 00h bit allocation . . . . . . . . . . . . 56
Table 62. CollPos register bit descriptions . . . . . . . . . . . 56
Table 63. TimerValue register (address: 0Ch) reset
value: xxxx xxxxb, xxh bit allocation . . . . . . . . 57
Table 64. TimerValue register bit descriptions . . . . . . . . 57
Table 65. CRCResultLSB register (address: 0Dh) reset
value: xxxx xxxxb, xxh bit allocation . . . . . . . . 57
Table 66. CRCResultLSB register bit descriptions . . . . . 57
Table 67. CRCResult