MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487 - Maxim - Farnell Element 14 - Revenir à l'accueil
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General Description The MAX481, MAX483, MAX485, MAX487–MAX491, and MAX1487 are low-power transceivers for RS-485 and RS- 422 communication. Each part contains one driver and one receiver. The MAX483, MAX487, MAX488, and MAX489 feature reduced slew-rate drivers that minimize EMI and reduce reflections caused by improperly terminated cables, thus allowing error-free data transmission up to 250kbps. The driver slew rates of the MAX481, MAX485, MAX490, MAX491, and MAX1487 are not limited, allowing them to transmit up to 2.5Mbps. These transceivers draw between 120µA and 500µA of supply current when unloaded or fully loaded with disabled drivers. Additionally, the MAX481, MAX483, and MAX487 have a low-current shutdown mode in which they consume only 0.1µA. All parts operate from a single 5V supply. Drivers are short-circuit current limited and are protected against excessive power dissipation by thermal shutdown circuitry that places the driver outputs into a high-impedance state. The receiver input has a fail-safe feature that guarantees a logic-high output if the input is open circuit. The MAX487 and MAX1487 feature quarter-unit-load receiver input impedance, allowing up to 128 MAX487/ MAX1487 transceivers on the bus. Full-duplex communications are obtained using the MAX488–MAX491, while the MAX481, MAX483, MAX485, MAX487, and MAX1487 are designed for half-duplex applications. ________________________Applications Low-Power RS-485 Transceivers Low-Power RS-422 Transceivers Level Translators Transceivers for EMI-Sensitive Applications Industrial-Control Local Area Networks __Next Generation Device Features ♦ For Fault-Tolerant Applications MAX3430: ±80V Fault-Protected, Fail-Safe, 1/4 Unit Load, +3.3V, RS-485 Transceiver MAX3440E–MAX3444E: ±15kV ESD-Protected, ±60V Fault-Protected, 10Mbps, Fail-Safe, RS-485/J1708 Transceivers ♦ For Space-Constrained Applications MAX3460–MAX3464: +5V, Fail-Safe, 20Mbps, Profibus RS-485/RS-422 Transceivers MAX3362: +3.3V, High-Speed, RS-485/RS-422 Transceiver in a SOT23 Package MAX3280E–MAX3284E: ±15kV ESD-Protected, 52Mbps, +3V to +5.5V, SOT23, RS-485/RS-422, True Fail-Safe Receivers MAX3293/MAX3294/MAX3295: 20Mbps, +3.3V, SOT23, RS-485/RS-422 Transmitters ♦ For Multiple Transceiver Applications MAX3030E–MAX3033E: ±15kV ESD-Protected, +3.3V, Quad RS-422 Transmitters ♦ For Fail-Safe Applications MAX3080–MAX3089: Fail-Safe, High-Speed (10Mbps), Slew-Rate-Limited RS-485/RS-422 Transceivers ♦ For Low-Voltage Applications MAX3483E/MAX3485E/MAX3486E/MAX3488E/ MAX3490E/MAX3491E: +3.3V Powered, ±15kV ESD-Protected, 12Mbps, Slew-Rate-Limited, True RS-485/RS-422 Transceivers MAX481/MAX483/MAX485/ MAX487–MAX491/MAX1487 Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com. ______________________________________________________________Selection Table 19-0122; Rev 10; 9/14 PART NUMBER HALF/FULL DUPLEX DATA RATE (Mbps) SLEW-RATE LIMITED LOWPOWER SHUTDOWN RECEIVER/ DRIVER ENABLE QUIESCENT CURRENT (μA) NUMBER OF RECEIVERS ON BUS PIN COUNT MAX481 Half 2.5 No Yes Yes 300 32 8 MAX483 Half 0.25 Yes Yes Yes 120 32 8 MAX485 Half 2.5 No No Yes 300 32 8 MAX487 Half 0.25 Yes Yes Yes 120 128 8 MAX488 Full 0.25 Yes No No 120 32 8 MAX489 Full 0.25 Yes No Yes 120 32 14 MAX490 Full 2.5 No No No 300 32 8 MAX491 Full 2.5 No No Yes 300 32 14 MAX1487 Half 2.5 No No Yes 230 128 8 Ordering Information appears at end of data sheet. Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 2 Maxim Integrated MAX481/MAX483/MAX485/ MAX487–MAX491/MAX1487 ABSOLUTE MAXIMUM RATINGS Supply Voltage (VCC).............................................................12V Control Input Voltage (RE, DE)...................-0.5V to (VCC + 0.5V) Driver Input Voltage (DI).............................-0.5V to (VCC + 0.5V) Driver Output Voltage (A, B)...................................-8V to +12.5V Receiver Input Voltage (A, B).................................-8V to +12.5V Receiver Output Voltage (RO)....................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +70°C) 8-Pin Plastic DIP (derate 9.09mW/°C above +70°C) ....727mW 14-Pin Plastic DIP (derate 10.00mW/°C above +70°C) ..800mW 8-Pin SO (derate 5.88mW/°C above +70°C).................471mW 14-Pin SO (derate 8.33mW/°C above +70°C)...............667mW 8-Pin µMAX (derate 4.1mW/°C above +70°C) ..............830mW 8-Pin CERDIP (derate 8.00mW/°C above +70°C).........640mW 14-Pin CERDIP (derate 9.09mW/°C above +70°C).......727mW Operating Temperature Ranges MAX4_ _C_ _/MAX1487C_ A ...............................0°C to +70°C MAX4_ _E_ _/MAX1487E_ A.............................-40°C to +85°C MAX4_ _M_/MAX1487MJA .............................-55°C to +125°C Storage Temperature Range .............................-65°C to +160°C Lead Temperature (soldering, 10sec) .............................+300°C DC ELECTRICAL CHARACTERISTICS (VCC = 5V ±5%, TA = TMIN to TMAX, unless otherwise noted.) (Notes 1, 2) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. V VIN = -7V VIN = 12V VIN = -7V VIN = 12V Input Current (A, B) IIN2 VTH -7V ≤ VCM ≤ 12V, MAX487/MAX1487 48 kΩ Receiver Input Resistance RIN -7V ≤ VCM ≤ 12V, all devices except MAX487/MAX1487 R = 27Ω (RS-485), Figure 4 0.4V ≤ VO ≤ 2.4V R = 50Ω (RS-422) IO = 4mA, VID = -200mV IO = -4mA, VID = 200mV VCM = 0V -7V ≤ VCM ≤ 12V DE, DI, RE DE, DI, RE MAX487/MAX1487, DE = 0V, VCC = 0V or 5.25V DE, DI, RE R = 27Ω or 50Ω, Figure 4 R = 27Ω or 50Ω, Figure 4 R = 27Ω or 50Ω, Figure 4 DE = 0V; VCC = 0V or 5.25V, all devices except MAX487/MAX1487 CONDITIONS 12 kΩ IOZR ±1 µA Three-State (high impedance) Output Current at Receiver V Receiver Output Low Voltage VOL 0.4 Receiver Output High Voltage VOH 3.5 Receiver Input Hysteresis ΔVTH 70 mV -0.2 0.2 V Receiver Differential Threshold Voltage -0.2 mA 0.25 mA -0.8 1.0 1.5 5 VOD2 Differential Driver Output (with load) V 2 Differential Driver Output (no load) VOD1 5 V Input Current IIN1 ±2 µA Input Low Voltage VIL 0.8 V Input High Voltage VIH 2.0 V ΔVOD 0.2 V Change in Magnitude of Driver Common-Mode Output Voltage for Complementary Output States ΔVOD 0.2 V Change in Magnitude of Driver Differential Output Voltage for Complementary Output States VOC 3 V Driver Common-Mode Output Voltage PARAMETER SYMBOL MIN TYP MAX UNITS Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers Maxim Integrated 3 MAX481/MAX483/MAX485/ MAX487–MAX491/MAX1487 SWITCHING CHARACTERISTICS—MAX481/MAX485, MAX490/MAX491, MAX1487 (VCC = 5V ±5%, TA = TMIN to TMAX, unless otherwise noted.) (Notes 1, 2) DC ELECTRICAL CHARACTERISTICS (continued) (VCC = 5V ±5%, TA = TMIN to TMAX, unless otherwise noted.) (Notes 1, 2) Receiver Short-Circuit Current IOSR 0V ≤ VO ≤ VCC 7 95 mA IOSD2 -7V ≤ VO ≤12V (Note 4) 35 250 mA Driver Short-Circuit Current, VO = Low IOSD1 -7V ≤ VO ≤12V (Note 4) 35 250 mA Driver Short-Circuit Current, VO = High MAX1487, RE = 0V or VCC 250 400 350 650 ns tPHL 10 30 60 Driver Rise or Fall Time Figures 6 and 8, RDIFF = 54Ω, CL1 = CL2 = 100pF ns MAX490M, MAX491M MAX490C/E, MAX491C/E 20 90 150 MAX481, MAX485, MAX1487 MAX490M, MAX491M MAX490C/E, MAX491C/E MAX481, MAX485, MAX1487 Figures 6 and 8, RDIFF = 54Ω, CL1 = CL2 = 100pF MAX481 (Note 5) Figures 5 and 11, CRL = 15pF, S2 closed Figures 5 and 11, CRL = 15pF, S1 closed Figures 5 and 11, CRL = 15pF, S2 closed Figures 5 and 11, CRL = 15pF, S1 closed Figures 6 and 10, RDIFF = 54Ω, CL1 = CL2 = 100pF Figures 6 and 8, RDIFF = 54Ω, CL1 = CL2 = 100pF Figures 6 and 10, RDIFF = 54Ω, CL1 = CL2 = 100pF CONDITIONS ns tSKEW 5 10 Time to Shutdown tSHDN 50 200 600 ns Maximum Data Rate fMAX 2.5 Mbps Receiver Disable Time from High tHZ 20 50 ns ns tPLH 10 30 60 Receiver Disable Time from Low tLZ 20 50 tZH 20 50 ns Driver Input to Output Receiver Enable to Output High Receiver Enable to Output Low tZL 20 50 ns 20 90 200 ns ns 13 tHZ 40 70 tSKD Driver Disable Time from High | tPLH - tPHL | Differential Receiver Skew Driver Disable Time from Low tLZ 40 70 ns ns Driver Enable to Output Low tZL 40 70 3 15 40 ns 5 15 25 ns 3 15 40 tR, tF 20 90 200 Driver Output Skew to Output Receiver Input to Output tPLH, tPHL Driver Enable to Output High tZH 40 70 PARAMETER SYMBOL MIN TYP MAX UNITS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 230 400 300 500 MAX481/MAX485, RE = 0V or VCC 500 900 MAX490/MAX491, DE, DI, RE = 0V or VCC 300 500 MAX488/MAX489, DE, DI, RE = 0V or VCC 120 250 DE = VCC DE = 0V 300 500 DE = VCC DE = 0V Supply Current in Shutdown ISHDN MAX481/483/487, DE = 0V, RE = VCC 0.1 10 µA 120 250 ICC No-Load Supply Current (Note 3) DE = 5V DE = 0V MAX483 MAX487 MAX483/MAX487, RE = 0V or VCC Figures 7 and 9, CL = 100pF, S2 closed Figures 7 and 9, CL = 100pF, S1 closed Figures 7 and 9, CL = 15pF, S1 closed Figures 7 and 9, CL = 15pF, S2 closed µA Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 4 Maxim Integrated MAX481/MAX483/MAX485/ MAX487–MAX491/MAX1487 SWITCHING CHARACTERISTICS—MAX483, MAX487/MAX488/MAX489 (VCC = 5V ±5%, TA = TMIN to TMAX, unless otherwise noted.) (Notes 1, 2) SWITCHING CHARACTERISTICS—MAX481/MAX485, MAX490/MAX491, MAX1487 (continued) (VCC = 5V ±5%, TA = TMIN to TMAX, unless otherwise noted.) (Notes 1, 2) 300 1000 Figures 7 and 9, CL = 100pF, S2 closed Figures 7 and 9, CL = 100pF, S1 closed Figures 5 and 11, CL = 15pF, S2 closed, A - B = 2V CONDITIONS tZH(SHDN) 40 100 ns Driver Enable from Shutdown to Output High (MAX481) ns Figures 5 and 11, CL = 15pF, S1 closed, B - A = 2V tZL(SHDN) Receiver Enable from Shutdown to Output Low (MAX481) tZL(SHDN) 40 100 ns Driver Enable from Shutdown to Output Low (MAX481) tZH(SHDN) 300 1000 ns Receiver Enable from Shutdown to Output High (MAX481) PARAMETER SYMBOL MIN TYP MAX UNITS tPLH tSKEW Figures 6 and 8, RDIFF = 54Ω, CL1 = CL2 = 100pF tPHL Figures 6 and 8, RDIFF = 54Ω, CL1 = CL2 = 100pF Driver Input to Output Driver Output Skew to Output 100 800 ns ns 2000 ns MAX483/MAX487, Figures 7 and 9, CL = 100pF, S2 closed tZH(SHDN) Driver Enable from Shutdown to Output High 250 2000 2500 ns MAX483/MAX487, Figures 5 and 11, CL = 15pF, S1 closed tZL(SHDN) Receiver Enable from Shutdown to Output Low 2500 ns MAX483/MAX487, Figures 5 and 11, CL = 15pF, S2 closed tZH(SHDN) Receiver Enable from Shutdown to Output High 2000 ns MAX483/MAX487, Figures 7 and 9, CL = 100pF, S1 closed tZL(SHDN) Driver Enable from Shutdown to Output Low Time to Shutdown tSHDN MAX483/MAX487 (Note 5) 50 200 600 ns tPHL tPLH, tPHL < 50% of data period Figures 5 and 11, CRL = 15pF, S2 closed Figures 5 and 11, CRL = 15pF, S1 closed Figures 5 and 11, CRL = 15pF, S2 closed Figures 5 and 11, CRL = 15pF, S1 closed Figures 7 and 9, CL = 15pF, S2 closed Figures 6 and 10, RDIFF = 54Ω, CL1 = CL2 = 100pF Figures 7 and 9, CL = 15pF, S1 closed Figures 7 and 9, CL = 100pF, S1 closed Figures 7 and 9, CL = 100pF, S2 closed CONDITIONS fMAX 250 kbps 250 800 2000 Maximum Data Rate Receiver Disable Time from High tHZ 20 50 ns ns 250 800 2000 Receiver Disable Time from Low tLZ 20 50 Receiver Enable to Output High tZH 20 50 ns Receiver Enable to Output Low tZL 20 50 ns ns ns 100 tHZ 300 3000 tSKD Driver Disable Time from High I tPLH - tPHL I Differential Receiver Skew Figures 6 and 10, RDIFF = 54Ω, CL1 = CL2 = 100pF Driver Disable Time from Low tLZ 300 3000 ns Driver Enable to Output Low tZL 250 2000 ns ns Figures 6 and 8, RDIFF = 54Ω, CL1 = CL2 = 100pF tR, tF 250 2000 ns 250 2000 Driver Rise or Fall Time ns tPLH Receiver Input to Output Driver Enable to Output High tZH 250 2000 PARAMETER SYMBOL MIN TYP MAX UNITS MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487 30 0 0 2.5 OUTPUT CURRENT vs. RECEIVER OUTPUT LOW VOLTAGE 5 25 MAX481-01 OUTPUT LOW VOLTAGE (V) OUTPUT CURRENT (mA) 1.5 15 10 0.5 1.0 2.0 20 35 40 45 0.9 0.1 -50 -25 25 75 RECEIVER OUTPUT LOW VOLTAGE vs. TEMPERATURE 0.3 0.7 TEMPERATURE (°C) OUTPUT LOW VOLTAGE (V) 0 50 0.5 0.8 0.2 0.6 0.4 0 100 125 IRO = 8mA MAX481-04 -20 -4 1.5 2.0 3.0 5.0 OUTPUT CURRENT vs. RECEIVER OUTPUT HIGH VOLTAGE -8 -16 MAX481-02 OUTPUT HIGH VOLTAGE (V) OUTPUT CURRENT (mA) 2.5 4.0 -12 -18 -6 -14 -10 -2 0 3.5 4.5 4.8 3.2 -50 -25 25 75 RECEIVER OUTPUT HIGH VOLTAGE vs. TEMPERATURE 3.6 4.4 TEMPERATURE (°C) OUTPUT HIGH VOLTAGE (V) 0 50 4.0 4.6 3.4 4.2 3.8 3.0 100 125 IRO = 8mA MAX481-03 90 0 0 1.0 3.0 4.5 DRIVER OUTPUT CURRENT vs. DIFFERENTIAL OUTPUT VOLTAGE 10 70 MAX481-05 DIFFERENTIAL OUTPUT VOLTAGE (V) OUTPUT CURRENT (mA) 2.0 4.0 50 30 80 60 40 20 0.5 1.5 2.5 3.5 2.3 1.5 -50 -25 25 125 DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs. TEMPERATURE 1.7 2.1 MAX481-06 TEMPERATURE (°C) DIFFERENTIAL OUTPUT VOLTAGE (V) 0 75 1.9 2.2 1.6 2.0 1.8 50 100 2.4 R = 54Ω __________________________________________Typical Operating Characteristics (VCC = 5V, TA = +25°C, unless otherwise noted.) Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers Maxim Integrated 5 MAX481/MAX483/MAX485/ MAX487–MAX491/MAX1487 NOTES FOR ELECTRICAL/SWITCHING CHARACTERISTICS Note 1: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. Note 2: All typical specifications are given for VCC = 5V and TA = +25°C. Note 3: Supply current specification is valid for loaded transmitters when DE = 0V. Note 4: Applies to peak current. See Typical Operating Characteristics. Note 5: The MAX481/MAX483/MAX487 are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 50ns, the parts are guaranteed not to enter shutdown. If the inputs are in this state for at least 600ns, the parts are guaranteed to have entered shutdown. See Low-Power Shutdown Mode (MAX481/MAX483/MAX487) section. MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487 ____________________________Typical Operating Characteristics (continued) (VCC = 5V, TA = +25°C, unless otherwise noted.) 120 0 0 8 OUTPUT CURRENT vs. DRIVER OUTPUT LOW VOLTAGE 20 100 MAX481-07 OUTPUT LOW VOLTAGE (V) OUTPUT CURRENT (mA) 6 60 40 2 4 80 10 12 140 -120 0 -7 -5 -1 5 OUTPUT CURRENT vs. DRIVER OUTPUT HIGH VOLTAGE -20 -80 MAX481-08 OUTPUT HIGH VOLTAGE (V) OUTPUT CURRENT (mA) -3 1 -60 -6 -4 -2 0 2 4 3 -100 -40 100 -60 -20 40 100 120 -40 MAX1487 SUPPLY CURRENT vs. TEMPERATURE 300 MAX481-13 TEMPERATURE (°C) SUPPLY CURRENT (μA) 20 60 80 500 200 600 400 0 0 140 MAX1487; DE = VCC, RE = X MAX1487; DE = 0V, RE = X 100 -50 -25 50 100 MAX481/MAX485/MAX490/MAX491 SUPPLY CURRENT vs. TEMPERATURE 300 MAX481-11 TEMPERATURE (°C) SUPPLY CURRENT (μA) 25 75 500 200 600 400 0 0 125 MAX481/MAX485; DE = VCC, RE = X MAX481; DE = 0, RE = VCC MAX485; DE = 0, RE = X, MAX481; DE = RE = 0 MAX490/MAX491; DE = RE = X 100 -50 -25 50 100 MAX483/MAX487–MAX489 SUPPLY CURRENT vs. TEMPERATURE 300 MAX481-12 TEMPERATURE (°C) SUPPLY CURRENT (μA) 25 75 500 200 600 400 0 0 125 MAX483; DE = VCC, RE = X MAX487; DE = VCC, RE = X MAX483/MAX487; DE = 0, RE = VCC MAX483/MAX487; DE = RE = 0, MAX488/MAX489; DE = RE = X Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 6 Maxim Integrated MAX481/MAX483/MAX485/ MAX487–MAX491/MAX1487 Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers Maxim Integrated 7 MAX481/MAX483/MAX485/ MAX487–MAX491/MAX1487 ______________________________________________________________Pin Description MAX481 MAX483 MAX485 MAX487 MAX1487 TOP VIEW NOTE: PIN LABELS Y AND Z ON TIMING, TEST, AND WAVEFORM DIAGRAMS REFER TO PINS A AND B WHEN DE IS HIGH. TYPICAL OPERATING CIRCUIT SHOWN WITH DIP/SO PACKAGE. 1 2 3 4 8 5 VCC DI GND DE RE RO R D Rt Rt 7 6 D R DE RE DI RO A B 1 2 3 4 8 7 6 5 VCC B A DI GND DE RE RO DIP/SO R D 1 2 3 4 8 7 6 5 VCC A GND RE DE B RO μMAX B A DI MAX481 MAX483 MAX485 MAX487 MAX1487 Figure 1. MAX481/MAX483/MAX485/MAX487/MAX1487 Pin Configuration and Typical Operating Circuit µMAX — — 5 6 7 8 — 2 — 1 3 — µMAX 4 5 6 7 — — 8 — 1 — 2 — DIP/SO DIP/SO 2 3 Receiver Output Enable. RO is enabled when RE is low; RO is high impedance when RE is high. 3 4 Driver Output Enable. The driver outputs, Y and Z, are enabled by bringing DE high. They are high impedance when DE is low. If the driver outputs are enabled, the parts function as line drivers. While they are high impedance, they function as line receivers if RE is low. DIP/SO — 4 5 Driver Input. A low on DI forces output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low. 5 6, 7 Ground — 9 Noninverting Driver Output — 10 Inverting Driver Output — 3 4 6 — Noninverting Receiver Input and Noninverting Driver Output — 12 Noninverting Receiver Input 5 6 — 8 RE DE DI GND Y Z A A 7 — — B Inverting Receiver Input and Inverting Driver Output — 7 11 B Inverting Receiver Input 8 1 14 VCC Positive Supply: 4.75V ≤ VCC ≤ 5.25V — — 1, 8, 13 N.C. No Connect—not internally connected NAME FUNCTION 1 3 4 2 Receiver Output: If A > B by 200mV, RO will be high; If A < B by 200mV, RO will be low. 2 RO PIN NAME FUNCTION MAX481/MAX483/ MAX485/MAX487/ MAX1487 MAX488/ MAX490 MAX489/ MAX491 Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 8 Maxim Integrated MAX481/MAX483/MAX485/ MAX487–MAX491/MAX1487 __________Applications Information The MAX481/MAX483/MAX485/MAX487–MAX491 and MAX1487 are low-power transceivers for RS-485 and RS- 422 communications. The MAX481, MAX485, MAX490, MAX491, and MAX1487 can transmit and receive at data rates up to 2.5Mbps, while the MAX483, MAX487, MAX488, and MAX489 are specified for data rates up to 250kbps. The MAX488–MAX491 are full-duplex transceivers while the MAX481, MAX483, MAX485, MAX487, and MAX1487 are half-duplex. In addition, Driver Enable (DE) and Receiver Enable (RE) pins are included on the MAX481, MAX483, MAX485, MAX487, MAX489, MAX491, and MAX1487. When disabled, the driver and receiver outputs are high impedance. MAX487/MAX1487: 128 Transceivers on the Bus The 48kΩ, 1/ 4-unit-load receiver input impedance of the MAX487 and MAX1487 allows up to 128 transceivers on a bus, compared to the 1-unit load (12kΩ input impedance) of standard RS-485 drivers (32 transceivers maximum). Any combination of MAX487/ MAX1487 and other RS-485 transceivers with a total of 32 unit loads or less can be put on the bus. The MAX481/MAX483/MAX485 and MAX488–MAX491 have standard 12kΩ Receiver Input impedance. MAX488 MAX490 TOP VIEW 1 2 3 4 RO DI GND 8 7 6 5 A B Z Y VCC DIP/SO R D Rt Rt VCC 5 6 7 8 RO DI GND 4 GND DI RO 3 2 A B Y Z VCC D R R D 1 VCC 3 RO 4 A 2 1 6 5 7 8 GND DI Y B Z μMAX MAX488 MAX490 NOTE: TYPICAL OPERATING CIRCUIT SHOWN WITH DIP/SO PACKAGE. MAX489 MAX491 DIP/SO TOP VIEW Rt Rt DE VCC RE GND VCC RE GND DE RO DI 9 10 12 11 B A Z Y 5 RO NC DI 2 1, 8, 13 3 6, 7 4 14 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC N.C. N.C. A B Z Y N.C. RO RE DE DI GND GND R D D R D R Figure 2. MAX488/MAX490 Pin Configuration and Typical Operating Circuit Figure 3. MAX489/MAX491 Pin Configuration and Typical Operating Circuit Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers Maxim Integrated 9 MAX481/MAX483/MAX485/ MAX487–MAX491/MAX1487 MAX483/MAX487/MAX488/MAX489: Reduced EMI and Reflections The MAX483 and MAX487–MAX489 are slew-rate limited, minimizing EMI and reducing reflections caused by improperly terminated cables. Figure 12 shows the driver output waveform and its Fourier analysis of a 150kHz signal transmitted by a MAX481, MAX485, MAX490, MAX491, or MAX1487. High-frequency harmonics with large amplitudes are evident. Figure 13 shows the same information displayed for a MAX483, MAX487, MAX488, or MAX489 transmitting under the same conditions. Figure 13’s high-frequency harmonics have much lower amplitudes, and the potential for EMI is significantly reduced. R R Y Z VOD VOC RECEIVER OUTPUT TEST POINT 1kΩ 1kΩ S1 S2 VCC CRL 15pF DI DE 3V Y Z CL1 CL2 A B RO RE RDIFF VID OUTPUT UNDER TEST 500Ω S1 S2 VCC CL _________________________________________________________________Test Circuits Figure 4. Driver DC Test Load Figure 5. Receiver Timing Test Load Figure 6. Driver/Receiver Timing Test Circuit Figure 7. Driver Timing Test Load Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 10 Maxim Integrated MAX481/MAX483/MAX485/ MAX487–MAX491/MAX1487 _______________________________________________________Switching Waveforms DI 3V 0V Z Y VO 0V -VO VO 1.5V tPLH 1/2 VO 10% tR 90% 90% tPHL 1.5V 1/2 VO 10% tF VDIFF = V (Y) - V (Z) VDIFF tSKEW = | tPLH - tPHL | OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH 3V 0V Y, Z VOL Y, Z 0V 1.5V 1.5V VOL + 0.5V 2.3V VOH - 0.5V 2.3V tZL(SHDN), tZL tLZ tZH(SHDN), tZH tHZ DE VOH VOL VID -VID 1.5V 0V 1.5V OUTPUT INPUT 0V RO A-B tPHL tPLH OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH 3V 0V VCC RO RO 0V 1.5V 1.5V VOL + 0.5V 1.5V VOH - 0.5V 1.5V tZL(SHDN), tZL tLZ tZH(SHDN), tZH tHZ RE _________________Function Tables (MAX481/MAX483/MAX485/MAX487/MAX1487) Figure 8. Driver Propagation Delays Figure 9. Driver Enable and Disable Times (except MAX488 and MAX490) Figure 10. Receiver Propagation Delays Figure 11. Receiver Enable and Disable Times (except MAX488 and MAX490) Table 1. Transmitting Table 2. Receiving INPUTS OUTPUT RE DE A-B RO 0 0 0 1 0 0 0 0 > +0.2V < -0.2V Inputs open X 1 0 1 High-Z* INPUTS OUTPUTS RE DE DI Z Y X X 0 1 1 1 0 0 1 0 X X 0 1 High-Z High-Z* 1 0 High-Z High-Z* X = Don’t care High-Z = High impedance *Shutdown mode for MAX481/MAX483/MAX487 X = Don’t care High-Z = High impedance *Shutdown mode for MAX481/MAX483/MAX487 Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers Maxim Integrated 11 MAX481/MAX483/MAX485/ MAX487–MAX491/MAX1487 Low-Power Shutdown Mode (MAX481/MAX483/MAX487) A low-power shutdown mode is initiated by bringing both RE high and DE low. The devices will not shut down unless both the driver and receiver are disabled. In shutdown, the devices typically draw only 0.1µA of supply current. RE and DE may be driven simultaneously; the parts are guaranteed not to enter shutdown if RE is high and DE is low for less than 50ns. If the inputs are in this state for at least 600ns, the parts are guaranteed to enter shutdown. For the MAX481, MAX483, and MAX487, the tZH and tZL enable times assume the part was not in the lowpower shutdown state (the MAX485/MAX488–MAX491 and MAX1487 can not be shut down). The tZH(SHDN) and tZL(SHDN) enable times assume the parts were shut down (see Electrical Characteristics). It takes the drivers and receivers longer to become enabled from the low-power shutdown state (tZH(SHDN), tZL(SHDN)) than from the operating mode (tZH, tZL). (The parts are in operating mode if the – R —E – , DE inputs equal a logical 0,1 or 1,1 or 0, 0.) Driver Output Protection Excessive output current and power dissipation caused by faults or by bus contention are prevented by two mechanisms. A foldback current limit on the output stage provides immediate protection against short circuits over the whole common-mode voltage range (see Typical Operating Characteristics). In addition, a thermal shutdown circuit forces the driver outputs into a high-impedance state if the die temperature rises excessively. Propagation Delay Many digital encoding schemes depend on the difference between the driver and receiver propagation delay times. Typical propagation delays are shown in Figures 15–18 using Figure 14’s test circuit. The difference in receiver delay times, | tPLH - tPHL |, is typically under 13ns for the MAX481, MAX485, MAX490, MAX491, and MAX1487 and is typically less than 100ns for the MAX483 and MAX487–MAX489. The driver skew times are typically 5ns (10ns max) for the MAX481, MAX485, MAX490, MAX491, and MAX1487, and are typically 100ns (800ns max) for the MAX483 and MAX487–MAX489. 10dB/div 0Hz 5MHz 500kHz/div 10dB/div 0Hz 5MHz 500kHz/div Figure 12. Driver Output Waveform and FFT Plot of MAX481/ MAX485/MAX490/MAX491/MAX1487 Transmitting a 150kHz Signal Figure 13. Driver Output Waveform and FFT Plot of MAX483/ MAX487–MAX489 Transmitting a 150kHz Signal Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 12 Maxim Integrated MAX481/MAX483/MAX485/ MAX487–MAX491/MAX1487 TTL IN tR, tF < 6ns D R 100pF B 100pF A RECEIVER OUT R = 54Ω Z Y 500mV/div 20ns/div A B RO 2V/div VCC = 5V TA = +25°C 500mV/div 20ns/div A B RO 2V/div VCC = 5V TA = +25°C 500mV/div 400ns/div A B RO 2V/div VCC = 5V TA = +25°C 500mV/div 400ns/div A B RO 2V/div VCC = 5V TA = +25°C Figure 14. Receiver Propagation Delay Test Circuit Figure 15. MAX481/MAX485/MAX490/MAX491/MAX1487 Receiver tPHL Figure 16. MAX481/MAX485/MAX490/MAX491/MAX1487 Receiver tPLH Figure 17. MAX483, MAX487–MAX489 Receiver tPHL Figure 18. MAX483, MAX487–MAX489 Receiver tPLH Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers Maxim Integrated 13 MAX481/MAX483/MAX485/ MAX487–MAX491/MAX1487 Line Length vs. Data Rate The RS-485/RS-422 standard covers line lengths up to 4000 feet. For line lengths greater than 4000 feet, see Figure 23. Figures 19 and 20 show the system differential voltage for the parts driving 4000 feet of 26AWG twisted-pair wire at 110kHz into 120Ω loads. Typical Applications The MAX481, MAX483, MAX485, MAX487–MAX491, and MAX1487 transceivers are designed for bidirectional data communications on multipoint bus transmission lines. Figures 21 and 22 show typical network applications circuits. These parts can also be used as line repeaters, with cable lengths longer than 4000 feet, as shown in Figure 23. To minimize reflections, the line should be terminated at both ends in its characteristic impedance, and stub lengths off the main line should be kept as short as possible. The slew-rate-limited MAX483 and MAX487–MAX489 are more tolerant of imperfect termination. DI VY-VZ RO 5V 0V 1V 0V -1V 5V 0V 2μs/div DI VY-VZ RO 5V 0V 1V 0V -1V 5V 0V 2μs/div DI RO DE RE A B RE RE RE RO RO RO DI DI DI DE DE DE D D D R R R B B B A A A 120Ω 120Ω D R MAX481 MAX483 MAX485 MAX487 MAX1487 Figure 19. MAX481/MAX485/MAX490/MAX491/MAX1487 System Differential Voltage at 110kHz Driving 4000ft of Cable Figure 20. MAX483, MAX487–MAX489 System Differential Voltage at 110kHz Driving 4000ft of Cable Figure 21. MAX481/MAX483/MAX485/MAX487/MAX1487 Typical Half-Duplex RS-485 Network Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 14 Maxim Integrated MAX481/MAX483/MAX485/ MAX487–MAX491/MAX1487 Figure 22. MAX488–MAX491 Full-Duplex RS-485 Network 120Ω 120Ω R D RO RE DE DI A B Y 120Ω 120Ω DI DI DI RO RO RO DE DE DE RE RE RE Z Z Z Z Y Y Y A A A B B B D D D R R R MAX488–MAX491 NOTE: RE AND DE ON MAX489/MAX491 ONLY. Figure 23. Line Repeater for MAX488–MAX491 120Ω 120Ω DATA IN DATA OUT R D RO RE DE DI A B Z Y MAX488–MAX491 NOTE: RE AND DE ON MAX489/MAX491 ONLY. Isolated RS-485 For isolated RS-485 applications, see the MAX253 and MAX1480 data sheets. Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers Maxim Integrated 15 MAX481/MAX483/MAX485/ MAX487–MAX491/MAX1487 _______________Ordering Information *Contact factory for dice specifications. MAX489MJD -55°C to +125°C 14 CERDIP MAX489ESD -40°C to +85°C 14 SO MAX489EPD -40°C to +85°C 14 Plastic DIP MAX489C/D 0°C to +70°C Dice* MAX489CSD 0°C to +70°C 14 SO MAX489CPD 0°C to +70°C 14 Plastic DIP MAX488MJA -55°C to +125°C 8 CERDIP MAX488ESA -40°C to +85°C 8 SO MAX488EPA -40°C to +85°C 8 Plastic DIP MAX488C/D 0°C to +70°C Dice* MAX488CSA 0°C to +70°C 8 SO MAX488CPA 0°C to +70°C 8 Plastic DIP MAX487MJA -55°C to +125°C 8 CERDIP MAX487ESA -40°C to +85°C 8 SO MAX487EPA -40°C to +85°C 8 Plastic DIP MAX487C/D 0°C to +70°C Dice* MAX487CSA 0°C to +70°C 8 SO MAX487CPA 0°C to +70°C 8 Plastic DIP MAX485MJA -55°C to +125°C 8 CERDIP MAX485ESA -40°C to +85°C 8 SO MAX485EPA -40°C to +85°C 8 Plastic DIP MAX485C/D 0°C to +70°C Dice* MAX485CSA 0°C to +70°C 8 SO MAX485CPA 0°C to +70°C 8 Plastic DIP MAX483MJA -55°C to +125°C 8 CERDIP MAX483ESA -40°C to +85°C 8 SO MAX483EPA -40°C to +85°C 8 Plastic DIP MAX481MJA -55°C to +125°C 8 CERDIP MAX481CPA 0°C to +70°C 8 Plastic DIP PART TEMP RANGE PIN-PACKAGE MAX491MJD -55°C to +125°C 14 CERDIP MAX491ESD -40°C to +85°C 14 SO MAX491EPD -40°C to +85°C 14 Plastic DIP MAX491C/D 0°C to +70°C Dice* MAX491CSD 0°C to +70°C 14 SO MAX491CPD 0°C to +70°C 14 Plastic DIP MAX490MJA -55°C to +125°C 8 CERDIP MAX490ESA -40°C to +85°C 8 SO MAX490EPA -40°C to +85°C 8 Plastic DIP MAX490C/D 0°C to +70°C Dice* MAX490CPA 0°C to +70°C 8 Plastic DIP PART TEMP RANGE PIN-PACKAGE MAX481ESA -40°C to +85°C 8 SO MAX485CUA 0°C to +70°C 8 µMAX MAX487CUA 0°C to +70°C 8 µMAX MAX488CUA 0°C to +70°C 8 µMAX MAX490CSA 0°C to +70°C 8 SO MAX490CUA 0°C to +70°C 8 µMAX __Ordering Information (continued) MAX1487MJA -55°C to +125°C 8 CERDIP MAX1487ESA -40°C to +85°C 8 SO MAX1487EPA -40°C to +85°C 8 Plastic DIP MAX1487C/D 0°C to +70°C Dice* MAX1487CSA 0°C to +70°C 8 SO MAX1487CPA 0°C to +70°C 8 Plastic DIP MAX1487CUA 0°C to +70°C 8 µMAX MAX483CUA 0°C to +70°C 8 µMAX MAX483C/D 0°C to +70°C Dice* MAX483CSA 0°C to +70°C 8 SO MAX483CPA 0°C to +70°C 8 Plastic DIP MAX481EPA -40°C to +85°C 8 Plastic DIP MAX481C/D 0°C to +70°C Dice* MAX481CUA 0°C to +70°C 8 µMAX MAX481CSA 0°C to +70°C 8 SO MAX491MSD/PR-T -55°C to +125°C 14 CERDIP MAX491MSD/PR -55°C to +125°C 14 CERDIP Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers 16 Maxim Integrated MAX481/MAX483/MAX485/ MAX487–MAX491/MAX1487 Package Information For the latest package outline information and land patterns, go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 8 PDIP P8-1 21-0043 — 8 SO S8-2 21-0041 90-0096 8 MAX U8-1 21-0036 90-0092 8 CERDIP J8-2 21-0045 — 14 PDIP P14-3 21-0043 — 14 SO S14-1 21-0041 90-0112 14 CERDIP J14-3 21-0045 — Low-Power, Slew-Rate-Limited RS-485/RS-422 Transceivers MAX481/MAX483/MAX485/ MAX487–MAX491/MAX1487 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 17 © 2014 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. Revision History REVISION NUMBER REVISION DATE DESCRIPTION PAGES CHANGED 0 1/93 Initial release. — 9 9/09 Changed column name in Selection Table to “Number of Receivers on Bus.” 1 10 9/14 Added MAX491MSD/PR and MAX491MSD/PR-T to data sheet. Updated Absolute Maximum Ratings. 2, 15 MAX3222/MAX3232/ MAX3237/MAX3241* 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1µF External Capacitors EVALUATION KIT AVAILABLE For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com. 19-0273; Rev 7; 1/07 ________________General Description The MAX3222/MAX3232/MAX3237/MAX3241 transceivers have a proprietary low-dropout transmitter output stage enabling true RS-232 performance from a 3.0V to 5.5V supply with a dual charge pump. The devices require only four small 0.1µF external chargepump capacitors. The MAX3222, MAX3232, and MAX3241 are guaranteed to run at data rates of 120kbps while maintaining RS-232 output levels. The MAX3237 is guaranteed to run at data rates of 250kbps in the normal operating mode and 1Mbps in the MegaBaud™ operating mode, while maintaining RS-232 output levels. The MAX3222/MAX3232 have 2 receivers and 2 drivers. The MAX3222 features a 1µA shutdown mode that reduces power consumption and extends battery life in portable systems. Its receivers remain active in shutdown mode, allowing external devices such as modems to be monitored using only 1µA supply current. The MAX3222 and MAX3232 are pin, package, and functionally compatible with the industry-standard MAX242 and MAX232, respectively. The MAX3241 is a complete serial port (3 drivers/ 5 receivers) designed for notebook and subnotebook computers. The MAX3237 (5 drivers/3 receivers) is ideal for fast modem applications. Both these devices feature a shutdown mode in which all receivers can remain active while using only 1µA supply current. Receivers R1 (MAX3237/MAX3241) and R2 (MAX3241) have extra outputs in addition to their standard outputs. These extra outputs are always active, allowing external devices such as a modem to be monitored without forward biasing the protection diodes in circuitry that may have VCC completely removed. The MAX3222, MAX3232, and MAX3241 are available in space-saving TSSOP and SSOP packages. ________________________Applications Notebook, Subnotebook, and Palmtop Computers High-Speed Modems Battery-Powered Equipment Hand-Held Equipment Peripherals Printers __Next Generation Device Features ♦ For Smaller Packaging: MAX3228E/MAX3229E: +2.5V to +5.5V RS-232 Transceivers in UCSP™ ♦ For Integrated ESD Protection: MAX3222E/MAX3232E/MAX3237E/MAX3241E*/ MAX3246E: ±15kV ESD-Protected, Down to 10nA, 3.0V to 5.5V, Up to 1Mbps, True RS-232 Transceivers ♦ For Low-Voltage or Data Cable Applications: MAX3380E/MAX3381E: +2.35V to +5.5V, 1µA, 2Tx/2Rx RS-232 Transceivers with ±15kV ESD-Protected I/O and Logic Pins 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 SHDN VCC GND C1- T1OUT V+ C1+ EN TOP VIEW R1IN R1OUT T1IN T2OUT T2IN V- C2- C2+ R2IN 9 10 R2OUT DIP/SO MAX3222 + _________________Pin Configurations _______________Ordering Information MegaBaud and UCSP are trademarks of Maxim Integrated Products, Inc. *Covered by U.S. Patent numbers 4,636,930; 4,679,134; 4,777,577; 4,797,899; 4,809,152; 4,897,774; 4,999,761; and other patents pending. Typical Operating Circuits appear at end of data sheet. Pin Configurations continued at end of data sheet. Ordering Information continued at end of data sheet. +Denotes lead-free package. PART TEMP RANGE PIN-PACKAGE PKG CODE MAX3222CUP+ 0°C to +70°C 20 TSSOP U20+2 MAX3222CAP+ 0°C to +70°C 20 SSOP A20+1 MAX3222CWN+ 0°C to +70°C 18 SO W18+1 MAX3222CPN+ 0°C to +70°C 18 Plastic Dip P18+5 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1µF External Capacitors 2 Maxim Integrated MAX3222/MAX3232/MAX3237/MAX3241 VCC = 5.0V ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +5.5V, C1–C4 = 0.1µF (Note 2), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 1: V+ and V- can have a maximum magnitude of 7V, but their absolute difference cannot exceed 13V. VCC...........................................................................-0.3V to +6V V+ (Note 1)...............................................................-0.3V to +7V V- (Note 1) ................................................................+0.3V to -7V V+ + V- (Note 1)...................................................................+13V Input Voltages T_IN, SHDN, EN ...................................................-0.3V to +6V MBAUD...................................................-0.3V to (VCC + 0.3V) R_IN .................................................................................±25V Output Voltages T_OUT...........................................................................±13.2V R_OUT....................................................-0.3V to (VCC + 0.3V) Short-Circuit Duration T_OUT ....................................................................Continuous Continuous Power Dissipation (TA = +70°C) 16-Pin TSSOP (derate 6.7mW/°C above +70°C).............533mW 16-Pin Narrow SO (derate 8.70mW/°C above +70°C) ....696mW 16-Pin Wide SO (derate 9.52mW/°C above +70°C)........762mW 16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)...842mW 18-Pin SO (derate 9.52mW/°C above +70°C)..............762mW 18-Pin Plastic DIP (derate 11.11mW/°C above +70°C) ..889mW 20-Pin SSOP (derate 7.00mW/°C above +70°C) .........559mW 20-Pin TSSOP (derate 8.0mW/°C above +70°C).............640mW 28-Pin TSSOP (derate 8.7mW/°C above +70°C).............696mW 28-Pin SSOP (derate 9.52mW/°C above +70°C) .........762mW 28-Pin SO (derate 12.50mW/°C above +70°C).....................1W Operating Temperature Ranges MAX32_ _C_ _.....................................................0°C to +70°C MAX32_ _E_ _ .................................................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C IOUT = -1.0mA IOUT = 1.6mA Receivers disabled T_IN, EN, SHDN, MBAUD T_IN, EN, SHDN, MBAUD CONDITIONS V 0.8 1.5 Input Threshold Low 0.6 1.2 Input Voltage Range -25 25 V 0.5 2.0 VCC Power-Supply Current Output Voltage High VCC - 0.6 VCC - 0.1 V Output Voltage Low 0.4 V Output Leakage Current ±0.05 ±10 µA Input Leakage Current ±0.01 ±1.0 µA 0.8 V Input Logic Threshold Low (Note 3) PARAMETER MIN TYP MAX UNITS TA = +25°C TA = +25°C V 1.8 2.4 Input Threshold High 1.5 2.4 VCC = 3.3V VCC = 5.0V 2.0 V 2.4 Input Logic Threshold High (Note 3) No load, VCC = 3.3V or 5.0V, TA = +25°C mA 0.3 1.0 MAX3222/MAX3232/ MAX3241 MAX3237 Shutdown Supply Current SHDN = GND, TA = +25°C 1.0 10 µA VCC = 3.3V VCC = 5.0V VCC = 3.3V VCC = 5.0V DC CHARACTERISTICS LOGIC INPUTS AND RECEIVER OUTPUTS RECEIVER INPUTS 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1µF External Capacitors Maxim Integrated 3 MAX3222/MAX3232/MAX3237/MAX3241 TIMING CHARACTERISTICS—MAX3222/MAX3232/MAX3241 (VCC = +3.0V to +5.5V, C1–C4 = 0.1µF (Note 2), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +5.5V, C1–C4 = 0.1µF (Note 2), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) T1IN = T2IN = GND, T3IN = VCC, T3OUT loaded with 3kΩ to GND, T1OUT and T2OUT loaded with 2.5mA each CONDITIONS Transmitter Output Voltage ±5.0 V Input Hysteresis 0.3 V PARAMETER MIN TYP MAX UNITS Output Voltage Swing All transmitter outputs loaded with 3kΩ to ground ±5.0 ±5.4 V Output Short-Circuit Current ±35 ±60 mA Output Resistance VCC = V+ = V- = 0V, VOUT = ±2V 300 10M Ω VOUT = ±12V, VCC = 0V or 3V to 5.5V, transmitters disabled Output Leakage Current ±25 µA tPHL RL = 3kΩ, CL = 1000pF, one transmitter switching tPLH | tPHL - tPLH | | tPHL - tPLH | Normal operation Normal operation CONDITIONS 0.3 µs 0.3 Receiver Propagation Delay Maximum Data Rate 120 235 kbps Receiver Skew 300 ns Transmitter Skew 300 ns Receiver Output Disable Time 200 ns Receiver Output Enable Time 200 ns PARAMETER MIN TYP MAX UNITS VCC = 3.3V, RL = 3kΩ to 7kΩ, 6 30 +3V to -3V or -3V to +3V, TA = +25°C, one transmitter switching V/µs 4 30 Transition-Region Slew Rate R_IN to R_OUT, CL = 150pF CL = 150pF to 1000pF CL = 150pF to 2500pF Input Resistance TA = +25°C 357 kΩ MOUSE DRIVEABILITY (MAX3241) TRANSMITTER OUTPUTS 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1µF External Capacitors 4 Maxim Integrated MAX3222/MAX3232/MAX3237/MAX3241 __________________________________________Typical Operating Characteristics (VCC = +3.3V, 235kbps data rate, 0.1µF capacitors, all transmitters loaded with 3kΩ, TA = +25°C, unless otherwise noted.) RL = 3kΩ, CL = 1000pF, one transmitter switching, MBAUD = GND Normal operation CONDITIONS Receiver Output Disable Time Normal operation 200 ns | tPHL - tPLH |, MBAUD = GND 100 ns 0.15 250 µs 0.15 Receiver Propagation Delay Receiver Output Enable Time 200 ns PARAMETER MIN TYP MAX UNITS TIMING CHARACTERISTICS—MAX3237 (VCC = +3.0V to +5.5V, C1–C4 = 0.1µF (Note 2), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) VCC = 3.0V to 4.5V, RL = 3kΩ, CL = 250pF, one transmitter switching, MBAUD = VCC 1000 VCC = 4.5V to 5.5V, RL = 3kΩ, CL = 1000pF, one transmitter switching, MBAUD = VCC kbps 1000 Maximum Data Rate R_IN to R_OUT, CL = 150pF | tPHL - tPLH |, MBAUD = VCC 25 ns Transmitter Skew Receiver Skew | tPHL - tPLH | 50 ns 6 30 V/µs 4 30 tPHL tPLH CL = 150pF to 2500pF, MBAUD = GND CL = 150pF to 1000pF MBAUD = GND VCC = 3.3V, RL = 3Ω to 7kΩ, +3V to -3V or -3V to +3V, TA = +25°C Transition-Region Slew Rate MBAUD = VCC 24 150 Note 2: MAX3222/MAX3232/MAX3241: C1–C4 = 0.1µF tested at 3.3V ±10%; C1 = 0.047µF, C2–C4 = 0.33µF tested at 5.0V ±10%. MAX3237: C1–C4 = 0.1µF tested at 3.3V ±5%; C1–C4 = 0.22µF tested at 3.3V ±10%; C1 = 0.047µF, C2–C4 = 0.33µF tested at 5.0V ±10%. Note 3: Transmitter input hysteresis is typically 250mV. -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 0 MAX3222/MAX3232 TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE MAX3222-01 LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (V) 1000 4000 5000 2000 3000 VOUT+ VOUT- 0 2 4 6 8 10 12 14 16 18 20 22 150 MAX3222/MAX3232 SLEW RATE vs. LOAD CAPACITANCE MAX3222-02 LOAD CAPACITANCE (pF) SLEW RATE (V/μs) 1000 4000 5000 2000 3000 FOR DATA RATES UP TO 235kbps +SLEW -SLEW 0 5 10 15 20 25 30 35 40 0 MAX3222/MAX3232 SUPPLY CURRENT vs. LOAD CAPACITANCE WHEN TRANSMITTING DATA MAX3222-03 LOAD CAPACITANCE (pF) SUPPLY CURRENT (mA) 1000 4000 5000 2000 3000 235kbps 120kbps 20kbps 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1µF External Capacitors Maxim Integrated 5 MAX3222/MAX3232/MAX3237/MAX3241 -7.5 -5.0 -2.5 0 2.5 5.0 7.5 0 MAX3241 TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE MAX3222-04 LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (V) 1000 4000 5000 2000 3000 VOUT+ 1 TRANSMITTER AT 235kbps 2 TRANSMITTERS AT 30kbps VOUT- ALL OUTPUTS LOADED WITH 3kΩ +CL 0.1μF CHARGE-PUMP CAPACITORS FOR ALL DATA RATES UP TO 235kbps 4 6 8 10 12 14 16 18 20 22 24 0 MAX3241 SLEW RATE vs. LOAD CAPACITANCE MAX3222-05 LOAD CAPACITANCE (pF) SLEW RATE (V/μs) 1000 4000 5000 2000 3000 +SLEW -SLEW 0 5 10 15 20 25 30 35 45 40 0 MAX3241 SUPPLY CURRENT vs. LOAD CAPACITANCE WHEN TRANSMITTING DATA MAX3222-06 LOAD CAPACITANCE (pF) SUPPLY CURRENT (mA) 1000 4000 5000 2000 3000 235kbps 120kbps 20kbps -7.5 -5.0 -2.5 0 2.5 5.0 7.5 0 MAX3237 TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE (MBAUD = GND) MAX3222-07 LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (V) 1000 4000 5000 2000 3000 1 TRANSMITTER AT 240kbps 4 TRANSMITTERS AT 15kbps 3kΩ + CL LOADS VCC = 3.3V 0 10 20 30 50 40 60 70 0 MAX3237 SLEW RATE vs. LOAD CAPACITANCE (MBAUD = VCC) MAX3222-10 LOAD CAPACITANCE (pF) SLEW RATE (V/μs) 500 1000 1500 2000 -SLEW, 1Mbps +SLEW, 1Mbps 1 TRANSMITTER AT FULL DATA RATE 4 TRANSMITTERS AT 1/16 DATA RATE 3kΩ + CL LOAD EACH OUTPUT VCC = 3.3V -SLEW, 2Mbps +SLEW, 2Mbps -7.5 -5.0 -2.5 0 2.5 5.0 7.5 0 MAX3237 TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE (MBAUD = VCC) MAX3222-08 LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (V) 500 1000 1500 2000 1 TRANSMITTER AT FULL DATA RATE 4 TRANSMITTERS AT 1/16 DATA RATE 3kΩ + CL LOAD, EACH OUTPUT VCC = 3.3V 2Mbps 1.5Mbps 1Mbps 2Mbps 1Mbps 1.5Mbps 0 10 20 30 40 50 60 0 MAX3237 SUPPLY CURRENT vs. LOAD CAPACITANCE (MBAUD = GND) MAX3222-11 LOAD CAPACITANCE (pF) SUPPLY CURRENT (mA) 1000 4000 5000 2000 3000 240kbps 120kbps 20kbps 1 TRANSMITTER AT FULL DATA RATE 4 TRANSMITTERS AT 1/16 DATA RATE 3kΩ + CL LOADS VCC = 3.3V 0 2 4 6 8 10 12 0 MAX3237 SLEW RATE vs. LOAD CAPACITANCE (MBAUD = GND) MAX3222-09 LOAD CAPACITANCE (pF) SLEW RATE (V/μs) 1000 4000 5000 2000 3000 +SLEW -SLEW 1 TRANSMITTER AT 240kbps 4 TRANSMITTERS AT 15kbps 3kΩ + CL LOADS VCC = 3.3V 0 10 30 20 40 50 60 70 0 MAX3237 SKEW vs. LOAD CAPACITANCE (tPLH - tPHL) MAX3222-12 LOAD CAPACITANCE (pF) 500 2000 2500 1000 1500 MAX MIN AVERAGE; 10 PARTS SKEW (ns)1 TRANSMITTER AT 512kbps 4 TRANSMITTERS AT 32kbps 3kΩ + CL LOADS VCC = 3.3V MBAUD = VCC _____________________________Typical Operating Characteristics (continued) (VCC = +3.3V, 235kbps data rate, 0.1µF capacitors, all transmitters loaded with 3kΩ, TA = +25°C, unless otherwise noted.) 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1µF External Capacitors 6 Maxim Integrated MAX3222/MAX3232/MAX3237/MAX3241 — FUNCTION — MAX3222 Noninverting Complementary Receiver Outputs. Always active. DIP/SO SSOP — 11, 14 1 1 Receiver Enable. Active low. 2 2 Positive Terminal of Voltage-Doubler Charge-Pump Capacitor 6 6 Negative Terminal of Inverting Charge-Pump Capacitor 5 5 Positive Terminal of Inverting Charge-Pump Capacitor 4 4 Negative Terminal of Voltage-Doubler Charge-Pump Capacitor 3 3 +5.5V Generated by the Charge Pump 11, 12 12, 13 TTL/CMOS Transmitter Inputs 10, 13 10, 15 TTL/CMOS Receiver Outputs 9, 14 9, 16 RS-232 Receiver Inputs 8, 15 8, 17 RS-232 Transmitter Outputs 7 7 -5.5V Generated by the Charge Pump 18 20 Shutdown Control. Active low. 17 19 +3.0V to +5.5V Supply Voltage 16 18 Ground No Connection MAX3232 MAX3237 — 16 — 13 1 28 5 3 4 1 3 25 2 27 10, 11 17, 19, 22, 23, 24 9, 12 18, 20, 21 8, 13 8, 9, 11 7, 14 5, 6, 7, 10, 12 6 4 — 14 16 26 15 2 — — NAME EN C1+ C2- C2+ C1- V+ T_IN R_OUT R_IN T_OUT V- SHDN VCC GND R_OUTB N.C. MAX3241 20, 21 23 28 2 1 24 27 12, 13, 14 15–19 4–8 9, 10, 11 3 22 26 25 — PIN — — MegaBaud Control Input. Connect to GND for normal operation; connect to VCC for 1Mbps transmission rates. — 15 — MBAUD ______________________________________________________________Pin Description 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1µF External Capacitors Maxim Integrated 7 MAX3222/MAX3232/MAX3237/MAX3241 _______________Detailed Description Dual Charge-Pump Voltage Converter The MAX3222/MAX3232/MAX3237/MAX3241’s internal power supply consists of a regulated dual charge pump that provides output voltages of +5.5V (doubling charge pump) and -5.5V (inverting charge pump), regardless of the input voltage (VCC) over the 3.0V to 5.5V range. The charge pumps operate in a discontinuous mode; if the output voltages are less than 5.5V, the charge pumps are enabled, and if the output voltages exceed 5.5V, the charge pumps are disabled. Each charge pump requires a flying capacitor (C1, C2) and a reservoir capacitor (C3, C4) to generate the V+ and V- supplies. RS-232 Transmitters The transmitters are inverting level translators that convert CMOS-logic levels to 5.0V EIA/TIA-232 levels. The MAX3222/MAX3232/MAX3241 transmitters guarantee a 120kbps data rate with worst-case loads of 3kΩ in parallel with 1000pF, providing compatibility with PC-toPC communication software (such as LapLink™). Typically, these three devices can operate at data rates of 235kbps. Transmitters can be paralleled to drive multiple receivers or mice. The MAX3222/MAX3237/MAX3241’s output stage is turned off (high impedance) when the device is in shutdown mode. When the power is off, the MAX3222/ MAX3232/MAX3237/MAX3241 permit the outputs to be driven up to ±12V. The transmitter inputs do not have pullup resistors. Connect unused inputs to GND or VCC. MAX3237 MegaBaud Operation In normal operating mode (MBAUD = GND), the MAX3237 transmitters guarantee a 250kbps data rate with worst-case loads of 3kΩ in parallel with 1000pF. This provides compatibility with PC-to-PC communication software, such as LapLink. For higher speed serial communications, the MAX3237 features MegaBaud operation. In MegaBaud operating mode (MBAUD = VCC), the MAX3237 transmitters guarantee a 1Mbps data rate with worst-case loads of 3kΩ in parallel with 250pF for 3.0V < VCC < 4.5V. For 5V ±10% operation, the MAX3237 transmitters guarantee a 1Mbps data rate into worst-case loads of 3kΩ in parallel with 1000pF. MAX3222 MAX3232 MAX3237 MAX3241 5kΩ R_ OUT R_ IN EN* C2- C2+ C1- C1+ V- V+ VCC C4 C1 C3 C2 0.1μF VCC SHDN* T_ IN T_ OUT GND VCC 0V 7kΩ 150pF MAX3222 MAX3232 MAX3237 MAX3241 5kΩ R_ OUT R_ IN EN* C2- C2+ C1- C1+ V- V+ VCC C4 C1 C3 C2 0.1μF VCC SHDN* T_ IN T_ OUT GND VCC 0V 3kΩ 2500pF MINIMUM SLEW-RATE TEST CIRCUIT MAXIMUM SLEW-RATE TEST CIRCUIT *MAX3222/MAX3237/MAX3241 ONLY Figure 1. Slew-Rate Test Circuits LapLink is a trademark of Traveling Software, Inc. 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1µF External Capacitors 8 Maxim Integrated MAX3222/MAX3232/MAX3237/MAX3241 RS-232 Receivers The receivers convert RS-232 signals to CMOS-logic output levels. The MAX3222/MAX3237/MAX3241 receivers have inverting three-state outputs. In shutdown, the receivers can be active or inactive (Table 1). The complementary outputs on the MAX3237 (R1OUTB) and the MAX3241 (R1OUTB, R2OUTB) are always active, regardless of the state of EN or SHDN. This allows for Ring Indicator applications without forward biasing other devices connected to the receiver outputs. This is ideal for systems where VCC is set to 0V in shutdown to accommodate peripherals, such as UARTs (Figure 2). MAX3222/MAX3237/MAX3241 Shutdown Mode Supply current falls to less than 1µA in shutdown mode (SHDN = low). When shut down, the device’s charge pumps are turned off, V+ is pulled down to VCC, V- is pulled to ground, and the transmitter outputs are disabled (high impedance). The time required to exit shutdown is typically 100µs, as shown in Figure 3. Connect SHDN to VCC if the shutdown mode is not used. SHDN has no effect on R_OUT or R_OUTB. MAX3222/MAX3237/MAX3241 Enable Control The inverting receiver outputs (R_OUT) are put into a high-impedance state when EN is high. The complementary outputs R1OUTB and R2OUTB are always active, regardless of the state of EN and SHDN (Table 1). EN has no effect on T_OUT. __________Applications Information Capacitor Selection The capacitor type used for C1–C4 is not critical for proper operation; polarized or nonpolarized capacitors can be used. The charge pump requires 0.1µF capacitors for 3.3V operation. For other supply voltages, refer to Table 2 for required capacitor values. Do not use values lower than those listed in Table 2. Increasing the capacitor values (e.g., by a factor of 2) reduces ripple on the transmitter outputs and slightly reduces power consumption. C2, C3, and C4 can be increased without changing C1’s value. However, do not increase C1 without also increasing the values of C2, C3, and C4, to maintain the proper ratios (C1 to the other capacitors). When using the minimum required capacitor values, make sure the capacitor value does not degrade excessively with temperature. If in doubt, use capacitors with a higher nominal value. The capacitor’s equivalent series resistance (ESR), which usually rises at low temperatures, influences the amount of ripple on V+ and V-. MAX3237 MAX3241 T1OUT R1OUTB Tx UART VCC T1IN LOGIC TRANSITION DETECTOR R1OUT R1IN EN = VCC SHDN = GND VCC TO μP Rx PREVIOUS RS-232 Tx UART PROTECTION DIODE PROTECTION DIODE SHDN = GND VCC VCC GND Rx 5kΩ a) OLDER RS-232: POWERED-DOWN UART DRAWS CURRENT FROM ACTIVE RECEIVER OUTPUT IN SHUTDOWN. b) NEW MAX3237/MAX3241: EN SHUTS DOWN RECEIVER OUTPUTS (EXCEPT FOR B OUTPUTS), SO NO CURRENT FLOWS TO UART IN SHUTDOWN. B OUTPUTS INDICATE RECEIVER ACTIVITY DURING SHUTDOWN WITH EN HIGH. GND 5kΩ Figure 2. Detection of RS-232 Activity when the UART and Interface are Shut Down; Comparison of MAX3237/MAX3241 (b) with Previous Transceivers (a). 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1µF External Capacitors Maxim Integrated 9 MAX3222/MAX3232/MAX3237/MAX3241 Power-Supply Decoupling In most circumstances, a 0.1µF bypass capacitor is adequate. In applications that are sensitive to powersupply noise, decouple VCC to ground with a capacitor of the same value as charge-pump capacitor C1. Connect bypass capacitors as close to the IC as possible. Operation Down to 2.7V Transmitter outputs will meet EIA/TIA-562 levels of ±3.7V with supply voltages as low as 2.7V. Transmitter Outputs when Exiting Shutdown Figure 3 shows two transmitter outputs when exiting shutdown mode. As they become active, the two transmitter outputs are shown going to opposite RS-232 levels (one transmitter input is high, the other is low). Each transmitter is loaded with 3kΩ in parallel with 2500pF. The transmitter outputs display no ringing or undesirable transients as they come out of shutdown. Note that the transmitters are enabled only when the magnitude of V- exceeds approximately 3V. Mouse Driveability The MAX3241 has been specifically designed to power serial mice while operating from low-voltage power supplies. It has been tested with leading mouse brands from manufacturers such as Microsoft and Logitech. The MAX3241 successfully drove all serial mice tested and met their respective current and voltage requirements. Figure 4a shows the transmitter output voltages under increasing load current at 3.0V. Figure 4b shows a typical mouse connection using the MAX3241. Table 1. MAX3222/MAX3237/MAX3241 Shutdown and Enable Control Truth Table Table 2. Required Minimum Capacitor Values 5V/div VCC = 3.3V C1–C4 = 0.1μF 2V/div T2 50μs/div T1 Figure 3. Transmitter Outputs when Exiting Shutdown or Powering Up VCC (V) C1 (µF) 4.5 to 5.5 0.047 3.0 to 5.5 0.1 C2, C3, C4 (µF) MAX3222/MAX3232/MAX3241 0.33 0.47 1 Active 0 1 1 Active SHDN 0 1 High-Z 0 0 High-Z EN T_OUT High-Z Active High-Z Active R_OUT R_OUTB (MAX3237/ MAX3241) Active Active Active Active 3.0 to 3.6 0.22 3.15 to 3.6 0.1 MAX3237 0.22 0.1 4.5 to 5.5 0.047 3.0 to 5.5 0.22 0.33 1.0 3.0 to 3.6 0.1 0.1 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1µF External Capacitors 10 Maxim Integrated MAX3222/MAX3232/MAX3237/MAX3241 MAX3241 23 EN 15 R5OUT 16 R4OUT 17 R3OUT 18 R2OUT 19 R1OUT 20 R2OUTB 21 R1OUTB 5kΩ 5kΩ 5kΩ 5kΩ 5kΩ R5IN 8 R4IN 7 6 R2IN 5 R1IN 4 SHDN 22 GND 25 12 T3IN 13 T2IN 14 T1IN C2- 2 C2+ 1 C1- 24 C1+ 28 T3OUT 11 +V COMPUTER SERIAL PORT MOUSE +V -V GND Tx T2OUT 10 T1OUT 9 V- 3 V+ 27 VCC VCC C4 C1 C3 C2 0.1μF VCC = 3V to 5.5V 26 R3IN Figure 4b. Mouse Driver Test Circuit -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 01234567 MAX3222-04 LOAD CURRENT PER TRANSMITTER (mA) TRANSMITTER OUTPUT VOLTAGE (V) VOUT+ VCC = 3.0V VOUTVOUT+ VCC VOUTT1 T2 T3 Figure 4a. MAX3241 Transmitter Output Voltage vs. Load Current per Transmitter 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1µF External Capacitors Maxim Integrated 11 MAX3222/MAX3232/MAX3237/MAX3241 High Data Rates The MAX3222/MAX3232/MAX3241 maintain the RS-232 ±5.0V minimum transmitter output voltage even at high data rates. Figure 5 shows a transmitter loopback test circuit. Figure 6 shows a loopback test result at 120kbps, and Figure 7 shows the same test at 235kbps. For Figure 6, all transmitters were driven simultaneously at 120kbps into RS-232 loads in parallel with 1000pF. For Figure 7, a single transmitter was driven at 235kbps, and all transmitters were loaded with an RS-232 receiver in parallel with 1000pF. The MAX3237 maintains the RS-232 ±5.0V minimum transmitter output voltage at data rates up to 1Mbps. Figure 8 shows a loopback test result at 1Mbps with MBAUD = VCC. For Figure 8, all transmitters were loaded with an RS-232 receiver in parallel with 250pF. MAX3222 MAX3232 MAX3237 MAX3241 5kΩ R_ OUT R_ IN EN* C2- C2+ C1- C1+ V- V+ VCC C4 C3 C1 C2 0.1μF VCC SHDN* T_ IN T_ OUT GND VCC 0V 1000pF *MAX3222/MAX3237/MAX3241 ONLY T1IN R1OUT VCC = 3.3V T1OUT 5V/div 5V/div 5V/div 5μs/div Figure 5. Loopback Test Circuit Figure 6. MAX3241 Loopback Test Result at 120kbps T1IN R1OUT VCC = 3.3V T1OUT 5V/div 5V/div 2μs/div 5V/div Figure 7. MAX3241 Loopback Test Result at 235kbps +5V 0V +5V 0V -5V +5V 0V T_IN T_OUT = R_IN 5kΩ + 250pF R_OUT 150pF 200ns/div VCC = 3.3V Figure 8. MAX3237 Loopback Test Result at 1000kbps (MBAUD = VCC) 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1µF External Capacitors 12 Maxim Integrated MAX3222/MAX3232/MAX3237/MAX3241 __________________________________________________Typical Operating Circuits MAX3222 10 R2OUT 1 13 R1OUT R2IN 9 18 GND 16 RS-232 OUTPUTS TTL/CMOS INPUTS 11 T2IN 12 T1IN C2- 6 C2+ 5 C1- 4 C1+ 2 R1IN 14 T2OUT 8 T1OUT 15 V- 7 V+ 3 VCC 17 C1 0.1μF C2 0.1μF 0.1μF +3.3V RS-232 INPUTS TTL/CMOS OUTPUTS EN SHDN C3* 0.1μF C4 0.1μF PIN NUMBERS REFER TO DIP/SO PACKAGES. * C3 CAN BE RETURNED TO EITHER VCC OR GROUND. MAX3232 9 R2OUT 12 R1OUT R2IN 8 GND 15 RS-232 OUTPUTS TTL/CMOS INPUTS 10 T2IN 11 T1IN C2- 5 C2+ 4 C1- 3 C1+ 1 R1IN 13 T2OUT 7 T1OUT 14 V- 6 V+ 2 VCC C4 0.1μF 16 0.1μF 0.1μF 0.1μF +3.3V RS-232 INPUTS TTL/CMOS OUTPUTS C3* 0.1μF * C3 CAN BE RETURNED TO EITHER VCC OR GROUND. SEE TABLE 2 FOR CAPACITOR SELECTION 5kΩ 5kΩ 5kΩ 5kΩ Interconnection with 3V and 5V Logic The MAX3222/MAX3232/MAX3237/MAX3241 can directly interface with various 5V logic families, including ACT and HCT CMOS. See Table 3 for more information on possible combinations of interconnections. Table 3. Logic-Family Compatibility with Various Supply Voltages Compatible with ACT and HCT CMOS, and with TTL. Incompatible with AC, HC, and CD4000 CMOS. 5 3.3 SYSTEM POWERSUPPLY VOLTAGE (V) Compatible with all TTL and CMOS-logic families. 5 5 Compatible with all CMOS families. 3.3 3.3 COMPATIBILITY MAX32_ _ VCC SUPPLY VOLTAGE (V) 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1µF External Capacitors Maxim Integrated 13 MAX3222/MAX3232/MAX3237/MAX3241 _____________________________________Typical Operating Circuits (continued) MAX3241 23 EN 15 R5OUT 16 R4OUT 17 R3OUT 18 R2OUT 19 R1OUT 20 R2OUTB 21 R1OUTB TTL/CMOS OUTPUTS 5kΩ 5kΩ 5kΩ 5kΩ 5kΩ R5IN 8 * C3 CAN BE RETURNED TO EITHER VCC OR GROUND. R4IN 7 R3IN 6 R2IN 5 R1IN 4 RS-232 INPUTS SHDN 22 GND 25 RS-232 OUTPUTS TTL/CMOS INPUTS 12 T3IN 13 T2IN T1IN 14 C2- 2 C2+ 1 C1- 24 C1+ 28 T3OUT 11 T2OUT 10 T1OUT 9 V- 3 V+ 27 VCC C4 0.1μF C3* 0.1μF 0.1μF 0.1μF 0.1μF +3.3V 26 MAX3237 13 EN 18 R3OUT 20 R2OUT 21 R1OUT 16 R1OUTB LOGIC OUTPUTS 5kΩ 5kΩ 5kΩ * C3 CAN BE RETURNED TO EITHER VCC OR GROUND. R3IN 11 R2IN 9 R1IN 8 RS-232 INPUTS GND 2 RS-232 OUTPUTS LOGIC INPUTS 22 T3IN 23 T2IN T1IN 24 C2- 3 C2+ 1 C1- 25 C1+ 28 T3OUT 7 T2OUT 6 T1OUT 5 T1 T2 T3 R1 R2 R3 V- 4 V+ 27 VCC 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF 26 MBAUD 15 17 T5IN 19 T4IN T5OUT 12 T4OUT 10 SHDN 14 T4 T5 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1µF External Capacitors 14 Maxim Integrated MAX3222/MAX3232/MAX3237/MAX3241 _____________________________________________Pin Configurations (continued) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VCC GND T1OUT C2+ R1IN C1- V+ C1+ MAX3232 R1OUT T1IN T2IN R2IN R2OUT T2OUT V- C2- DIP/SO/TSSOP + TOP VIEW 20 19 18 17 16 15 14 13 1 2 3 8 12 10 11 4 5 6 7 SHDN VCC GND C1- T1OUT V+ C1+ EN R1IN R1OUT T1IN T2IN T2OUT V- C2- C2+ R2IN 9 R2OUT SSOP/TSSOP + N.C. N.C. MAX3222 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C1+ V+ VCC C1- T1IN T2IN MBAUD T3IN R1OUT R2OUT T4IN R3OUT T5IN R1OUTB SHDN EN T5OUT R3IN T4OUT R2IN R1IN T3OUT T2OUT T1OUT V- C2- GND C2+ SSOP MAX3237 + 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C1+ V+ VCC GND C1- EN R5OUT SHDN R1OUTB R2OUTB R1OUT R2OUT R3OUT R4OUT T1IN T2IN T3IN T3OUT T2OUT T1OUT R5IN R4IN R3IN R2IN R1IN V- C2- C2+ SO/SSOP/TSSOP MAX3241 + 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1µF External Capacitors Maxim Integrated 15 MAX3222/MAX3232/MAX3237/MAX3241 ______3V-Powered EIA/TIA-232 and EIA/TIA-562 Transceivers from Maxim Ordering Information (continued) *Dice are tested at TA = +25°C, DC parameters only. +Denotes lead-free package. 0.1µF capacitors, 1 complementary receiver, MegaBaud operation MAX3237 3.0 to 5.5 5/3 3 250/1000 232 0.1µF capacitors, AutoShutdown, complementary receiver, drives mice MAX3243 3.0 to 5.5 3/5 1 120 232 MAX3232 3.0 to 5.5 2/2 N/A 120 232 0.1µF capacitors MAX3223 3.0 to 5.5 2/2 2 120 232 0.1µF capacitors, AutoShutdown MAX3222 3.0 to 5.5 2/2 2 120 232 0.1µF capacitors 232 562 232 562 232 EIA/ TIA-232 OR 562 2.7 to 3.6 AutoShutdown, complementary receiver, drives mice, transient detection MAX3212 3/5 5 235 MAX563 3.0 to 3.6 2/2 2 230 0.1µF capacitors Operates directly from batteries without a voltage regulator MAX218 1.8 to 4.25 2/2 2 120 No. OF RECEIVERS ACTIVE IN SHUTDOWN POWERSUPPLY VOLTAGE (V) MAX562 2.7 to 5.25 3/5 5 230 Wide supply range MAX212 3.0 to 3.6 3/5 5 120 Drives mice FEATURES GUARANTEED DATA RATE (kbps) No. OF TRANSMITTERS/ RECEIVERS PART 0.1µF capacitors, 2 complementary receivers, drives mice MAX3241 3.0 to 5.5 3/5 5 120 232 PART TEMP RANGE PIN-PACKAGE PKG CODE MAX3222EUP+ -40°C to +85°C 20 TSSOP U20+2 MAX3222EAP+ -40°C to +85°C 20 SSOP A20+1 MAX3222EWN+ -40°C to +85°C 18 SO W18+1 MAX3222EPN+ -40°C to +85°C 18 Plastic Dip P18+5 MAX3222C/D 0°C to +70°C Dice* — MAX3232CUE+ 0°C to +70°C 16 TSSOP U16+1 MAX3232CSE+ 0°C to +70°C 16 Narrow SO S16+1 MAX3232CWE+ 0°C to +70°C 16 Wide SO W16+1 MAX3232CPE+ 0°C to +70°C 16 Plastic DIP P16+1 MAX3232EUE+ -40°C to +85°C 16 TSSOP U16+1 MAX3232ESE+ -40°C to +85°C 16 Narrow SO S16+5 PART TEMP RANGE PIN-PACKAGE PKG CODE MAX3232EWE+ -40°C to +85°C 16 Wide SO W16+1 MAX3232EPE+ -40°C to +85°C 16 Plastic DIP P16+1 MAX3237CAI+ 0°C to +70°C 16 SSOP A28+2 MAX3237EAI+ 0°C to +70°C 28 SSOP A28+1 MAX3241CUI+ 0°C to +70°C 28 TSSOP U28+2 MAX3241CAI+ 0°C to +70°C 28 SSOP A28+1 MAX3241CWI+ 0°C to +70°C 28 SO W28+6 MAX3241EUI+ -40°C to +85°C 28 TSSOP U28+2 MAX3241EAI+ -40°C to +85°C 28 SSOP A28+1 MAX3241EWI+ -40°C to +85°C 28 SO W28+6 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1µF External Capacitors 16 Maxim Integrated MAX3222/MAX3232/MAX3237/MAX3241 ___________________Chip Topography ___________________Chip Information T2IN T1IN 0.127" (3.225mm) 0.087" (2.209mm) T2OUT R2IN R2OUT R1OUT R1IN T1OUT V+ C1+ VCC SHDN EN C1- C2+ C2- V- GND MAX3222 TRANSISTOR COUNT: 339 SUBSTRATE CONNECTED TO GND MAX3222 339 MAX3232 339 MAX3237 1212 MAX3241 894 PART TRANSISTOR COUNT Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 17 © 2007 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. 3.0V to 5.5V, Low-Power, up to 1Mbps, True RS-232 Transceivers Using Four 0.1µF External Capacitors MAX3222/MAX3232/MAX3237/MAX3241 TSSOP4.40mm.EPS Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Revision History Pages changed at Rev 7: 1, 15, 16, 17 MAX3221/MAX3223/MAX3243 +3V to +5.5V RS-232 Transceivers with AutoShutdown General Description The MAX3221/MAX3223/MAX3243 achieve 1µA supply current with Maxim’s revolutionary AutoShutdown™ feature. When the MAX3221/MAX3223/MAX3243 do not sense a valid signal level on their receiver inputs, the on-board power supply and drivers shut down. This occurs if the RS-232 cable is disconnected or if the transmitters of the connected peripheral are turned off. The system turns on again when a valid level is applied to any RS-232 receiver input. The MAX3221/MAX3223/MAX3243 require only 0.1µF capacitors in 3.3V operation, and can operate from input voltages ranging from +3.0V to +5.5V. A proprietary, high-efficiency, dual charge-pump power supply and a low-dropout transmitter combine to deliver true RS-232 performance from a single +3.0V to +5.5V supply. The MAX3221 is a 1-driver/1-receiver 16-pin SSOP version of the 20-pin 2-driver/2-receiver MAX3223. The MAX3243 is a 3-driver/5-receiver with a complementary always-active receiver for external monitoring in a variety of 28 pin packages. Please see order information table for package offerings. Applications • Battery-Powered Equipment • Hand-Held Equipment • Peripherals • Portable Diagnostics Equipment Benefits and Features • Integrated Charge Pump Circuitry Simplifies Power Requirements • Eliminates the Need for a ±12 Supply • Operation From a Single +3.3V or +5V Supply • 1µA Supply Current in Shutdown Mode Saves Power • AutoShutdown Feature is Enabled After No Activity on Receiver Inputs for 30µs • Software Control Option for Shutdown 19-0306; Rev 9; 1/15 PART MAX3221CAE MAX3221EUE† -40°C to +85°C 0°C to +70°C TEMP RANGE PIN-PACKAGE 16 SSOP 16 TSSOP †Future product—contact factory for availability. AutoShutdown and UCSP are trademarks of Maxim Integrated Products, Inc. Pin Configurations appear at end of data sheet. Typical Operating Circuits appear at end of data sheet. MAX3223EPP -40°C to +85°C 20 Plastic DIP MAX3223EAP -40°C to +85°C 20 SSOP MAX3243CWI 0°C to +70°C 28 Wide SO MAX3243CAI 0°C to +70°C 28 SSOP MAX3243EWI -40°C to +85°C 28 Wide SO MAX3243EAI -40°C to +85°C 28 SSOP MAX3223CPP MAX3223CAP 0°C to +70°C 0°C to +70°C 20 Plastic DIP 20 SSOP Ordering Information Selector Guide MAX3221 MAX3223 MAX3243 1 2 3 1 2 3.0 to 5.5 3.0 to 5.5 5 3.0 to 5.5 Yes Yes Yes PART Tx Rx VCC RANGE (V) AutoShutdown MAX3221CUE† 0°C to +70°C 16 TSSOP MAX3221EAE -40°C to +85°C 16 SSOP MAX3223CUP 0°C to +70°C 20 TSSOP MAX3223EUP -40°C to +85°C 20 TSSOP MAX3243CUI 0°C to +70°C 28 TSSOP MAX3243EUI -40°C to +85°C 28 TSSOP www.maximintegrated.com Maxim Integrated | 2 MAX3221/MAX3223/MAX3243 +3V to +5.5V RS-232 Transceivers with AutoShutdown Absolute Maximum Ratings Electrical Characteristics (VCC = +3.0V to +5.5V, C1–C4 = 0.1µF (Note 2), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. VCC...........................................................................-0.3V to +6V V+ (Note 1)...............................................................-0.3V to +7V V- (Note 1) ...............................................................+0.3V to -7V V+ + |V-| (Note 1).................................................................+13V Input Voltages T_IN, FORCEOFF, FORCEON, EN (MAX3223) ......-0.3V to +6V R_IN ...................................................................................±25V Output Voltages T_OUT.............................................................................±13.2V R_OUT, INVALID ......................................-0.3V to (VCC + 0.3V) Short-Circuit Duration T_OUT ......................................................................Continuous Continuous Power Dissipation (TA = +70°C) 16-Pin SSOP (derate 7.14mW/°C above +70°C) ...........571mW 16-Pin TSSOP (derate 6.70mW/°C above +70°C) .........533mW 20-Pin Plastic DIP (derate 11.11mW/°C above +70°C)....889mW 20-Pin SSOP (derate 8.00mW/°C above +70°C) ...........640mW 20-Pin TSSOP DIP (derate 7.00mW/°C above +70°C).....559mW 28-Pin Wide SO (derate 12.50mW/°C above +70°C) ............1W 28-Pin SSOP (derate 9.52mW/°C above +70°C) ...........762mW 28-Pin TSSOP (derate 8.70mW/°C above +70°C) .........696mW Operating Temperature Ranges MAX32_ _C_ _.......................................................0°C to +70°C MAX32_ _E_ _....................................................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Note 1: V+ and V- can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V. IOUT = 1.6mA Receivers disabled T_IN, EN, FORCEON, FORCEOFF T_IN, EN, FORCEON, FORCEOFF T_IN, FORCEON, FORCEOFF, EN (MAX3223) IOUT = -1.0mA CONDITIONS Output Voltage High VCC - 0.6 VCC - 0.1 V Output Voltage Low 0.4 V Output Leakage Current ±0.05 ±10 µA Input Leakage Current ±0.01 ±1.0 µA V 2.4 Input Logic Threshold High 1.0 10 µA Input Logic Threshold Low 0.8 V PARAMETER MIN TYP MAX UNITS VCC = 3.3V VCC = 5.0V 2.0 Supply Current, AutoShutdown Supply Current, Shutdown 1.0 10 µA Supply Current, AutoShutdown Disabled VCC = 3.3V or 5.0V, TA = +25°C 0.3 1.0 mA 2.7 Receiver Positive or Negative Threshold to INVALID High (tINVH) Figure 5 1 µs Receiver Threshold to Transmitters Enabled (tWU) Figure 5 250 µs Receiver Positive or Negative Threshold to INVALID Low (tINVL) Figure 5 30 µs Receiver Input Thresholds to Transmitters Enabled Figure 5 V -2.7 INVALID Output Voltage Low IOUT = 1.6mA 0.4 V Receiver Input Thresholds to Transmitters Disabled 1µA supply current, Figure 5 -0.3 0.3 V Positive threshold Negative threshold INVALID Output Voltage High IOUT = -1.0mA VCC - 0.6 V DC CHARACTERISTICS LOGIC INPUTS AND RECEIVER OUTPUTS AUTOSHUTDOWN (FORCEON = GND, FORCEOFF = VCC) All R_IN open, FORCEON = GND, FORCEOFF = VCC FORCEOFF = GND FORCEON = FORCEOFF = VCC, no load MAX3221/MAX3223/MAX3243 +3V to +5.5V RS-232 Transceivers with AutoShutdown www.maximintegrated.com Maxim Integrated | 3 Electrical Characteristics (continued) (VCC = +3.0V to +5.5V, C1–C4 = 0.1µF (Note 2), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) Note 2: C1–C4 = 0.1µF, tested at 3.3V ±10%. C1 = 0.047µF, C2–C4 = 0.33µF, tested at 5.0V ±10%. 200 Normal operation 200 Receiver Output Enable Time Normal operation ns tPLH Receiver input to receiver output, CL = 150pF 4 8.0 30 Transition-Region Slew Rate V/µs VCC = 3.3V, RL = 3kΩ to 7kΩ, TA = +25°C, measured from +3V to -3V or -3V to +3V Transmitter Skew 200 ⏐ tPHL - tPLH ⏐ ns PARAMETER MIN TYP MAX UNITS ±25 Output Short-Circuit Current ±35 ±60 mA Output Resistance 300 10M Ω Output Leakage Current µA Input Threshold Low 0.6 1.2 V Output Voltage Swing ±5.0 ±5.4 V Maximum Data Rate 120 235 kbps Receiver Propagation Delay 0.3 µs CONDITIONS VCC = V+ = V- = 0V, transmitter output = ±2V VOUT = ±12V, VCC = 0V or 3.0V to 5.5V, transmitters disabled RL = 3kΩ, CL = 1000pF, one transmitter switching All transmitter outputs loaded with 3kΩ to ground Receiver Output Disable Time ns tPHL 0.3 Input Voltage Range -25 25 V Input Hysteresis 0.3 V Input Threshold High V Input Resistance TA = +25°C 35 7 kΩ 0.8 1.5 1.8 2.4 1.5 2.4 TA = +25°C TA = +25°C VCC = 3.3V VCC = 3.3V VCC = 5.0V VCC = 5.0V CL = 200pF to 2500pF CL = 200pF to 1000pF 6 30 Transmitter Output Voltage ±5 V T1IN = T2IN = GND, T3IN = VCC, T3OUT loaded with 3kΩ to GND, T1OUT and T2OUT loaded with 2.5mA each MAX3221/MAX3223 MAX3243 200 1000 Receiver Skew 100 ⏐ tPHL - tPLH ⏐ ns MAX3221/MAX3223 MAX3243 100 500 RECEIVER INPUTS TIMING CHARACTERISTICS TRANSMITTER OUTPUTS MOUSE DRIVEABILITY (MAX3243) www.maximintegrated.com Maxim Integrated | 4 MAX3221/MAX3223/MAX3243 +3V to +5.5V RS-232 Transceivers with AutoShutdown Typical Operating Characteristics (VCC = +3.3V, 235kbps data rate, 0.1µF capacitors, all transmitters loaded with 3kΩ, TA = +25°C, unless otherwise noted.) -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 0 MAX3221/MAX3223 TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE MAX3221/3223-01 LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (V) 1000 4000 5000 2000 3000 VOUT+ VOUT- 0 2 4 6 8 10 12 14 16 18 20 22 150 500 MAX3221/MAX3223 SLEW RATE vs. LOAD CAPACITANCE MAX3221/3223-02 LOAD CAPACITANCE (pF) SLEW RATE (V/μs) 1000 4000 5000 2000 3000 FOR DATA RATES UP TO 235kbps +SLEW -SLEW 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 0 MAX3221/MAX3223 SUPPLY CURRENT vs. LOAD CAPACITANCE WHEN TRANSMITTING DATAMAX3221/3223-03 LOAD CAPACITANCE (pF) 3 3 SU CU ( ) MAX3221 SUPPLY CURRENT (mA) 1000 4000 5000 2000 3000 235kbps 120kbps 20kbps -7.5 -5.0 -2.5 0 2.5 5.0 7.5 0 MAX3243 TRANSMITTER OUTPUT VOLTAGE vs. LOAD CAPACITANCE MAX3221/3223-04 LOAD CAPACITANCE (pF) TRANSMITTER OUTPUT VOLTAGE (V) 1000 4000 5000 2000 3000 VOUT+ 1 TRANSMITTER AT 235kbps 2 TRANSMITTERS AT 30kbps VOUT- ALL OUTPUTS LOADED WITH 3kΩ +CL 0.1μF CHARGE-PUMP CAPACITORS FOR ALL DATA RATES UP TO 235kbps 4 6 8 10 12 14 16 18 20 22 24 0 MAX3243 SLEW RATE vs. LOAD CAPACITANCE MAX3221/3223-05 LOAD CAPACITANCE (pF) SLEW RATE (V/μs) 1000 4000 5000 2000 3000 +SLEW -SLEW 0 5 10 15 20 25 30 35 45 40 0 MAX3243 SUPPLY CURRENT vs. LOAD CAPACITANCE WHEN TRANSMITTING DATA MAX3221/3223-06 LOAD CAPACITANCE (pF) SUPPLY CURRENT (mA) 1000 4000 5000 2000 3000 235kbps 120kbps 20kbps www.maximintegrated.com Maxim Integrated | 5 MAX3221/MAX3223/MAX3243 +3V to +5.5V RS-232 Transceivers with AutoShutdown Pin Description R2OUTB Noninverting Receiver Output—active in shutdown Output of the valid signal detector. Indicates if a valid RS-232 level is present on receiver inputs logic “1”. INVALID Drive low to shut down transmitters and on-board power supply. This overrides all automatic circuitry and FORCEON (Table 1). FORCEOFF Drive high to override automatic circuitry keeping transmitters on (FORCEOFF must be high) (Table 1). FORCEON C1- Negative terminal of the voltage doubler charge-pump capacitor R_IN RS-232 Receiver Inputs T_OUT RS-232 Transmitter Outputs T_IN TTL/CMOS Transmitter Inputs R_OUT TTL/CMOS Receiver Outputs V- -5.5V generated by the charge pump C2- Negative terminal of inverting charge-pump capacitor C2+ Positive terminal of inverting charge-pump capacitor Receiver Enable Control. Drive low for normal operation. Drive high to force the receiver outputs into a high-Z state. EN FUNCTION GND Ground VCC +3.0V to +5.5V Supply Voltage LapLink is a trademark of Traveling Software. Detailed Description Dual Charge-Pump Voltage Converter The MAX3221/MAX3223/MAX3243’s internal power supply consists of a regulated dual charge pump that provides output voltages of +5.5V (doubling charge pump) and -5.5V (inverting charge pump), regardless of the input voltage (VCC) over the +3.0V to +5.5V range. The charge pumps operate in a discontinuous mode: if the output voltages are less than 5.5V, the charge pumps are enabled; if the output voltages exceed 5.5V, the charge pumps are disabled. Each charge pump requires a flying capacitor (C1, C2) and a reservoir capacitor (C3, C4) to generate the V+ and V- supplies. RS-232 Transmitters The transmitters are inverting level translators that convert CMOS-logic levels to 5.0V EIA/TIA-232 levels. They guarantee a 120kbps data rate with worst-case loads of 3kΩ in parallel with 1000pF, providing compatibility with PC-to-PC communication software (such as Laplink™). Typically, the MAX3221/MAX3223/MAX3243 can operate at data rates of 235kbps. Transmitters can be paralleled to drive multiple receivers or mice (MAX3243). Figure 1 shows a complete system connection. When FORCEOFF is driven to ground, or the AutoShutdown circuitry senses invalid voltage levels at all receiver inputs, the transmitters are disabled and the outputs are forced into a high-impedance state. — 10 16 12 4 8 13 11 9 7 6 5 1 14 15 NAME MAX3221 3 V+ +5.5V generated by the charge pump 2 C1+ Positive terminal of the voltage doubler charge-pump capacitor — 11 20 14 4 9, 16 8, 17 12, 13 10, 15 7 6 5 1 18 19 20 21 22 23 24 4–8 9, 10, 11 12, 13, 14 15–19 3 2 1 — 25 26 MAX3223 3 MAX3243 27 2 28 PIN www.maximintegrated.com Maxim Integrated | 6 MAX3221/MAX3223/MAX3243 +3V to +5.5V RS-232 Transceivers with AutoShutdown RS-232 Receivers The MAX3221/MAX3223/MAX3243’s receivers convert RS-232 signals to CMOS-logic output levels. All receivers have one inverting three-state output. In shutdown (FORCEOFF = low) or in AutoShutdown, the MAX3221/MAX3223’s receivers are active (Table 1). Driving EN high places the receiver(s) in a high-impedance state. The MAX3243’s receivers are high impedance when the part is shut down. The MAX3243 has an always-active complementary output (R2OUTB). R2OUTB is an extra output that monitors receiver activity while the other receivers are high impedance. This allows Ring Indicator to be monitored without forward biasing other devices connected to the receiver outputs. This is ideal for systems where VCC is set to 0V in shutdown to accommodate peripherals, such as UARTs (Figure 2). MAX3243 I/O CHIP WITH UART CPU RS-232 POWER MANAGEMENT UNIT OR KEYBOARD CONTROLLER FORCEOFF FORCEON INVALID MAX3243 T1OUT R2OUTB Tx UART 5kΩ VCC T1IN THREE-STATED LOGIC TRANSITION DETECTOR R2IN PROTECTION DIODE R2OUT FORCEOFF = GND VCC TO μP Rx PREVIOUS RS-232 Tx UART SHDN = GND VCC VCC GND Rx 5kΩ (a) OLDER RS-232: POWERED-DOWN UART DRAWS CURRENT FROM ACTIVE RECEIVER OUTPUT IN SHUTDOWN. (b) NEW MAX3243: IN SHUTDOWN, R2OUTB IS USED TO MONITOR EXTERNAL DEVICES AND R2OUT IS THREE STATED, ELIMINATING A CURRENT PATH THROUGH THE UART'S PROTECTION DIODE. GND PROTECTION DIODE I I Figure 1. Interface Under Control of PMU Figure 2. The MAX3243 detects RS-232 activity when the UART and interface are shut down. MAX3221/MAX3223/MAX3243 +3V to +5.5V RS-232 Transceivers with AutoShutdown www.maximintegrated.com Maxim Integrated | 7 AutoShutdown A 1µA supply current is achieved with Maxim’s new AutoShutdown feature, which operates when FORCEON is low and FORCEOFF is high. When the MAX3221/MAX3223/MAX3243 sense no valid signal levels on all receiver inputs for 30µs, the on-board power supply and drivers are shut off, reducing supply current to 1µA. This occurs if the RS-232 cable is disconnected or the connected peripheral transmitters are turned off. The system turns on again when a valid level is applied to any RS-232 receiver input. As a result, the system saves power without changes to the existing BIOS or operating system. When using AutoShutdown, the INVALID output is high when the device is on and low when the device is shut down. Because INVALID indicates the receiver inputs’ condition, it can be used in any mode (Figure 3). Table 2 and Figure 3c summarize the MAX3221/ MAX3223/MAX3243 operating modes. FORCEON and FORCEOFF override the automatic circuitry and force the transceiver into its normal operating state or into its low-power standby state. When neither control is asserted, the IC selects between these states automatically based on receiver input levels. Figures 3a, 3b, and 5a depict valid and invalid RS-232 receiver levels. A mouse or other system with AutoShutdown may need time to wake up. Figure 4 shows a circuit that forces the transmitters on for 100ms, allowing enough time for the other system to realize that the MAX3221/MAX3223/ Table 1a. MAX3221/MAX3223 FORCEOFF and Enable Control Truth Table Table 1b. MAX3243 FORCEOFF Control Truth Table 1 1 Active* 1 0 Active* FORCEOFF 0 1 High-Z 0 0 High-Z EN T_OUT High-Z Active High-Z Active R_OUT +0.3V -0.3V INVALID TO MAX32_ _ POWER SUPPLY AND TRANSMITTERS R_IN * TRANSMITTERS ARE DISABLED, REDUCING SUPPLY CURRENT TO 1μA IF ALL RECEIVER INPUTS ARE BETWEEN +0.3V AND -0.3V FOR AT LEAST 30μs. 30µs COUNTER R 1 Active* 0 High-Z FORCEOFF T_OUT Active* High-Z R_OUT Active Active R2OUTB Figure 3a. MAX32_ _ Entering 1µA Supply Mode via AutoShutdown *Note: If the part is in AutoShutdown mode (FORCEOFF = VCC, FORCEON = GND), it is shut down if no valid RS-232 levels are present on all receiver inputs. FORCEON MASTER SHDN LINE 0.1μF 1MΩ FORCEOFF MAX3221 MAX3223 MAX3243 POWER MANAGEMENT UNIT Figure 4. AutoShutdown with Initial Turn-On to Wake Up a Mouse or Another System +2.7V -2.7V INVALID TO MAX32_ _ POWER SUPPLY R_IN * TRANSMITTERS ARE ENABLED IF: ANY RECEIVER INPUT IS GREATER THAN +2.7V OR LESS THAN -2.7V. ANY RECEIVER INPUT HAS BEEN BETWEEN +0.3V AND -0.3V FOR LESS THAN 30μs. 30µs COUNTER R Figure 3b. MAX32_ _ with Transmitters Enabled Using AutoShutdown FORCEOFF POWER DOWN INVALID FORCEON INVALID IS AN INTERNALLY GENERATED SIGNAL THAT IS USED BY THE AUTOSHUTDOWN LOGIC AND APPEARS AS AN OUTPUT OF THE DEVICE. POWER DOWN IS ONLY AN INTERNAL SIGNAL. IT CONTROLS THE OPERATIONAL STATUS OF THE TRANSMITTERS AND THE POWER SUPPLIES. Figure 3c. AutoShutdown Logic www.maximintegrated.com Maxim Integrated | 8 MAX3221/MAX3223/MAX3243 +3V to +5.5V RS-232 Transceivers with AutoShutdown MAX3243 is awake. If the other system outputs valid RS-232 signals within that time, the RS-232 ports on both systems remain enabled. When shut down, the device’s charge pumps are turned off, V+ decays to VCC, V- decays to ground, and the transmitter outputs are disabled (high impedance). The time required to exit shutdown is typically 100µs (Figure 5b). Software-Controlled Shutdown If direct software control is desired, INVALID can be used to indicate DTR or Ring Indicator signal. Tie FORCEOFF and FORCEON together to bypass AutoShutdown so the line acts like a SHDN input. Applications Information Capacitor Selection The capacitor type used for C1–C4 is not critical for proper operation; either polarized or nonpolarized capacitors may be used. The charge pump requires 0.1µF capacitors for 3.3V operation. For other supply voltages, refer to Table 3 for required capacitor values. Do not use values smaller than those listed in Table 3. Increasing the capacitor values (e.g., by a factor of 2) reduces ripple on the transmitter outputs and slightly reduces power consumption. C2, C3, and C4 can be increased without changing C1’s value. However, do not increase C1 without also increasing the values of C2, C3, and C4 to maintain the proper ratios (C1 to the other capacitors). When using the minimum required capacitor values, make sure the capacitor value does not degrade excessively with temperature. If in doubt, use capacitors with a larger nominal value. The capacitor’s equivalent series resistance (ESR) usually rises at low temperatures and influences the amount of ripple on V+ and V-. Table 2. AutoShutdown Logic RS-232 SIGNAL PRESENT AT RECEIVER INPUT FORCEOFF INPUT FORCEON INPUT INVALID OUTPUT TRANSCEIVER STATUS Yes H X H Normal Operation No H H L Normal Operation (Forced On) No H L L Shutdown (AutoShutdown) Yes L X H Shutdown (Forced Off) No L X L Shutdown (Forced Off) V- VCC 0 V+ 0 VCC tINVL tWU INVALID REGION RECEIVER INPUT VOLTAGE (V) INVALID OUTPUT (V) tINVH TRANSMITTERS ENABLED, INVALID HIGH RECEIVER INPUT LEVELS AUTOSHUTDOWN, TRANSMITTERS DISABLED, 1μA SUPPLY CURRENT, INVALID LOW TRANSMITTERS ENABLED, INVALID HIGH -2.7V -0.3V +2.7V +0.3V 0V INDETERMINATE INDETERMINATE (b) (a) Figure 5. AutoShutdown Trip Levels MAX3221/MAX3223/MAX3243 +3V to +5.5V RS-232 Transceivers with AutoShutdown www.maximintegrated.com Maxim Integrated | 9 Power-Supply Decoupling In most circumstances a 0.1µF bypass capacitor is adequate. In applications that are sensitive to powersupply noise, decouple VCC to ground with a capacitor of the same value as the charge-pump capacitor C1. Connect bypass capacitors as close to the IC as possible. Transmitter Outputs when Exiting Shutdown Figure 6 shows two transmitter outputs when exiting shutdown mode. As they become active, the two transmitter outputs are shown going to opposite RS-232 levels. Each transmitter is loaded with 3kΩ in parallel with 2500pF. The transmitter outputs display no ringing or undesirable transients as they come out of shutdown. Note that the transmitters are enabled only when the magnitude of V- exceeds approximately 3V. Figure 7a shows the MAX3243’s transmitter output voltage vs. current per transmitter. Figure 7b is a mouse driver test circuit. Mouse Driveability (MAX3243) The MAX3243 has been specifically designed to power serial mice while operating from low-voltage power supplies. It has been tested with samples of ten major mouse models from six manufacturers including the leading three: Logitech (5 models), Mouse Systems, and Microsoft. The MAX3243 successfully drove all serial mice and met their respective current and voltage requirements. Figure 7a shows the transmitter outputs under increasing load current. The MAX3243’s switching regulator ensures the transmitters will supply at least ±5V during worst-case conditions. The AutoShutdown feature does not work with a mouse, so FORCEOFF and FORCEON should be connected to VCC. High Data Rates The MAX3221/MAX3223/MAX3243 maintain the RS-232 ±5.0V minimum transmitter output voltage even at high data rates. Figure 8 shows a transmitter loopback test circuit. Figure 9 shows a loopback test result at 120kbps, and Figure 10 shows the same test at 235kbps. For Figure 9, all three transmitters were driven simultaneously at 120kbps into RS-232 loads in parallel with 1000pF. For Figure 10, a single transmitter was driven at 235kbps, but all three transmitters were loaded with an RS-232 receiver in parallel with 1000pF. Interconnection with 3V and 5V Logic The MAX3221/MAX3223/MAX3243 can directly interface with various 5V logic families, including ACT and HCT CMOS. See Table 4 for more information on possible combinations of interconnections. -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 01234567 MAX322 LOAD CURRENT PER TRANSMITTER (mA) TRANSMITTER OUTPUT VOLTAGE (V) VOUT+ VCC = 3.0V VOUTVOUT+ VCC VOUTT1 T2 T3 Figure 7a. MAX3243 Transmitter Output Voltage vs. Load Current per Transmitter 5V/div VCC = +3.3V C1–C4 = 0.1μF 2V/div T2 50μs/div T1 Figure 6. Transmitter Outputs when Exiting Shutdown or Powering Up www.maximintegrated.com Maxim Integrated | 10 MAX3221/MAX3223/MAX3243 +3V to +5.5V RS-232 Transceivers with AutoShutdown +V COMPUTER SERIAL PORT +V -V GND Tx SERIAL MOUSE MAX3243 FORCEOFF 23 15 R5OUT 16 R4OUT 17 R3OUT 18 R2OUT 19 R1OUT 20 R2OUTB LOGIC OUTPUTS 5kΩ 5kΩ 5kΩ 5kΩ 5kΩ R5IN 8 R4IN 7 R3IN 6 R2IN 5 R1IN 4 RS-232 INPUTS GND 25 LOGIC INPUTS 12 T3IN 13 T2IN T1IN 14 C2- 2 C2+ 1 C1- 24 C1+ 28 T3OUT 11 T2OUT 10 T1OUT 9 V- 3 V+ 27 VCC VCC C4 0.1μF C3 0.1μF 0.1μF 26 C1 0.1μF C2 0.1μF FORCEON INVALID 22 21 TO POWER MANAGEMENT UNIT +3.3V Figure 7b. Mouse Driver Test Circuit MAX3221/MAX3223/MAX3243 +3V to +5.5V RS-232 Transceivers with AutoShutdown www.maximintegrated.com Maxim Integrated | 11 Figure 10. Loopback Test Result at 235kbps T1IN R1OUT VCC = +3.3V, 235kbps C1–C4 = 0.1μF T1OUT 5V/div 5V/div 2μs/div 5V/div MAX3221 MAX3223 MAX3243 5kΩ R_ OUT R_ IN EN (MAX3221/3) C2- C2+ C1- C1+ V- V+ VCC C4 C3 C1 C2 0.1μF VCC FORCEOFF T_ IN T_ OUT GND VCC 0V 1000pF Figure 8. Loopback Test Circuit Figure 9. Loopback Test Result at 120kbps T1IN R1OUT VCC = +3.3V, 120kbps C1–C4 = 0.1μF T1OUT 5V/div 5V/div 5V/div 5μs/div Table 4. Logic Family Compatibility with Various Supply Voltages Table 3. Required Capacitor Values VCC SUPPLY VOLTAGE (V) COMPATIBILITY 3.3 3.3 Compatible with all CMOS families. 5 5 Compatible with all TTL and CMOS-logic families. SYSTEM POWERSUPPLY VOLTAGE (V) 5 3.3 Compatible with ACT and HCT CMOS, and with TTL. Incompatible with AC, HC, or CD4000 CMOS. VCC (V) C1 (µF) C2, C3, C4 (µF) 3.0 to 3.6 0.1 0.1 4.5 to 5.5 0.047 0.33 3.0 to 5.5 0.1 0.47 www.maximintegrated.com Maxim Integrated | 12 MAX3221/MAX3223/MAX3243 +3V to +5.5V RS-232 Transceivers with AutoShutdown Typical Operating Circuits MAX3221 FORCEON EN 12 1 9 R1OUT FORCEOFF 16 INVALID 10 GND 14 11 T1IN C2- 6 C2+ 5 C1- 4 C1+ 2 R1IN 8 T1OUT 13 V- 7 V+ 3 VCC VCC C4 0.1μF C3 0.1μF 0.1μF 15 C1 0.1μF C2 0.1μF C5 +3.3V TO POWER MANAGEMENT UNIT 5kΩ MAX3223 FORCEON EN 14 1 10 R2OUT 15 R1OUT FORCEOFF 20 INVALID 11 R2IN 9 GND 18 RS-232 OUTPUTS TTL/CMOS INPUTS 12 T2IN 13 T1IN C2- 6 C2+ 5 C1- 4 C1+ 2 R1IN 16 T2OUT 8 T1OUT 17 V- 7 V+ 3 VCC VCC C4 0.1μF C3 0.1μF 0.1μF 19 C1 0.1μF C2 0.1μF C5 +3.3V RS-232 INPUTS TO POWER MANAGEMENT UNIT TTL/CMOS OUTPUTS 5kΩ 5kΩ MAX3243 FORCEOFF 23 15 R5OUT 16 R4OUT 17 R3OUT 18 R2OUT 19 R1OUT 20 R2OUTB LOGIC OUTPUTS 5kΩ 5kΩ 5kΩ 5kΩ 5kΩ R5IN 8 R4IN 7 R3IN 6 R2IN 5 R1IN 4 RS-232 INPUTS GND 25 RS-232 OUTPUTS LOGIC INPUTS 12 T3IN 13 T2IN T1IN 14 C2- 2 C2+ 1 C1- 24 C1+ 28 T3OUT 11 T2OUT 10 T1OUT 9 V- 3 V+ 27 VCC VCC C4 0.1μF C3 0.1μF 0.1μF 26 C1 0.1μF C2 0.1μF FORCEON INVALID 22 21 TO POWER MANAGEMENT UNIT +3.3V MAX3221/MAX3223/MAX3243 +3V to +5.5V RS-232 Transceivers with AutoShutdown www.maximintegrated.com Maxim Integrated | 13 3V-Powered EIA/TIA-232 and EIA/TIA-562 Transceivers from Maxim MAX3222 3.0 to 5.5 2/2 2 120 232 0.1µF capacitors, MAX242 pinout MAX3223 3.0 to 5.5 2/2 2 120 232 0.1µF capacitors, AutoShutdown 0.1µF capacitors, AutoShutdown complementary receiver, drives mice MAX3243 3.0 to 5.5 3/5 1 120 232 MAX3232 3.0 to 5.5 2/2 N/A 120 232 0.1µF capacitors, MAX232 pinout MAX3221 3.0 to 5.5 1/1 1 120 232 0.1µF capacitors, 16-pin SSOP 232 562 232 562 232 EIA/TIA- 232 OR 562 2.7 to 3.6 AutoShutdown, complementary receiver, drives mice, transient detection MAX3212 3/5 5 235 MAX563 3.0 to 3.6 2/2 2 120 0.1µF capacitors Operates directly from batteries without a voltage regulator MAX218 1.8 to 4.25 2/2 2 120 No. OF RECEIVERS ACTIVE IN SHUTDOWN POWERSUPPLY VOLTAGE (V) MAX562 2.7 to 5.25 3/5 5 230 230kbps guaranteed data rate MAX212 3.0 to 3.6 3/5 5 120 Drives mice FEATURES GUARANTEED DATA RATE (kbps) No. OF TRANSMITTERS/ RECEIVERS PART 0.1µF capacitors, 2 complementary receivers, drives mice MAX3241 3.0 to 5.5 3/5 5 120 232 www.maximintegrated.com Maxim Integrated | 14 MAX3221/MAX3223/MAX3243 +3V to +5.5V RS-232 Transceivers with AutoShutdown Pin Configurations 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 FORCEOFF VCC GND C1- T1OUT V+ C1+ EN R1IN R1OUT FORCEON T2OUT T1IN V- C2- C2+ 12 11 9 10 T2IN R2OUT INVALID R2IN DIP/SSOP/TSSOP MAX3223 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C1+ V+ VCC GND C1- FORCEON FORCEOFF INVALID R2OUTB R1OUT R2OUT R3OUT R4OUT R5OUT C2+ C2- V- R1IN R2IN R3IN R4IN R5IN T1OUT T2OUT T3OUT T3IN T2IN T1IN SO/SSOP/TSSOP MAX3243 TOP VIEW 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 EN C1+ V+ C1- C2+ C2- V- R1IN FORCEOFF VCC GND T1OUT FORCEON T1IN INVALID R1OUT MAX3221 SSOP/TSSOP MAX3221/MAX3223/MAX3243 +3V to +5.5V RS-232 Transceivers with AutoShutdown www.maximintegrated.com Maxim Integrated | 15 SSOP.EPS PACKAGE OUTLINE, SSOP, 5.3 MM 1 1 21-0056 C APPROVAL DOCUMENT CONTROL NO. REV. PROPRIETARY INFORMATION TITLE: NOTES: 1. D&E DO NOT INCLUDE MOLD FLASH. 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006"). 3. CONTROLLING DIMENSION: MILLIMETERS. 4. MEETS JEDEC MO150. 5. LEADS TO BE COPLANAR WITHIN 0.10 MM. H 7.90 L 0∞ 0.301 0.025 8∞ 0.311 0.037 0∞ 7.65 0.63 8∞ 0.95 MAX 5.38 MILLIMETERS B C D E e A1 DIM A SEE VARIATIONS 0.0256 BSC 0.010 0.004 0.205 0.002 0.015 0.008 0.212 0.008 INCHES MIN MAX 0.078 0.65 BSC 0.25 0.09 5.20 0.05 0.38 0.20 0.21 MIN 1.73 1.99 MILLIMETERS 6.07 6.07 10.07 8.07 7.07 INCHES D D D D D 0.239 0.239 0.397 0.317 0.278 MIN 0.249 0.249 0.407 0.328 0.289 MAX MIN 6.33 6.33 10.33 8.33 7.33 14L 16L 28L 24L 20L MAX N A D e A1 L C E H N 2 1 B 0.068 TSSOP4.40mm.EPS Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. www.maximintegrated.com Maxim Integrated | 16 MAX3221/MAX3223/MAX3243 +3V to +5.5V RS-232 Transceivers with AutoShutdown SOICW.EPS PACKAGE OUTLINE, .300" SOIC 1 1 21-0042 B APPROVAL DOCUMENT CONTROL NO. REV. PROPRIETARY INFORMATION TITLE: TOP VIEW FRONT VIEW MAX 0.012 0.104 0.019 0.299 0.013 INCHES 0.291 0.009 E C DIM 0.014 0.004 B A1 MIN A 0.093 0.23 7.40 7.60 0.32 MILLIMETERS 0.10 0.35 2.35 MIN 0.49 0.30 MAX 2.65 L 0.016 0.050 0.40 1.27 D 0.496 0.512 D DIM MIN D INCHES MAX 12.60 13.00 MILLIMETERS MIN MAX 20 AC 0.447 0.463 AB 11.35 18 11.75 0.398 0.413 AA 10.10 16 10.50 N MS013 SIDE VIEW H 0.419 0.394 10.00 10.65 e 0.050 1.27 D 0.614 0.598 15.20 24 15.60 AD D 0.713 0.697 17.70 28 18.10 AE E H N D A1 e B A 0∞-8∞ C L 1 VARIATIONS: PDIPN.EPS Package Information (continued) For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2015 Maxim Integrated Products, Inc. | 17 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com. MAX3221/MAX3223/MAX3243 +3V to +5.5V RS-232 Transceivers with AutoShutdown Revision History REVISION NUMBER REVISION DATE DESCRIPTION PAGES CHANGED 9 1/15 Updated General Description and Benefits and Features sections 1 1 of 8 FEATURES Converts CMOS RAMs into Nonvolatile Memories Unconditionally Write Protects when VCC is Out-of-Tolerance Automatically Switches to Battery when Power-Fail Occurs Space-Saving 8-Pin PDIP or 16-Pin SO Packages Consumes <100nA of Battery Current Tests Battery Condition on Power up Provides for Redundant Batteries Optional 5% or 10% Power-Fail Detection Low Forward Voltage Drop on the VCC Switch Optional Industrial (N) Temperature Range of -40°C to +85°C PIN ASSIGNMENT PIN DESCRIPTION VCCO - RAM Supply VBAT1 - + Battery 1 TOL - Power Supply Tolerance GND - Ground CE - Chip Enable Input CEO - Chip Enable Output VBAT2 - + Battery 2 VCCI - + Supply NC - No Connect DESCRIPTION The DS1210 Nonvolatile Controller Chip is a CMOS circuit which solves the application problem of converting CMOS RAM into nonvolatile memory. Incoming power is monitored for an out-of-tolerance condition. When such a condition is detected, chip enable is inhibited to accomplish write protection and the battery is switched on to supply the RAM with uninterrupted power. Special circuitry uses a lowleakage CMOS process which affords precise voltage detection at extremely low battery consumption. The 8-pin DIP package keeps PC board real estate requirements to a minimum. By combining the DS1210 Nonvolatile Controller Chip with a CMOS memory and batteries, nonvolatile RAM operation can be achieved. DS1210 Nonvolatile Controller Chip VCCO VBAT1 TOL GND 1 2 3 4 VCCI VBAT2 CEO CE 8 7 6 5 DS1210 8-pin PDIP (300 mils) NC VCCO NC VBAT1 NC TOL NC GND NC VCCI NC VBAT2 NC CEO NC CE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 DS1210S 16-pin SO (300 mils) 19-6294; Rev 6/12 DS1210 2 of 8 OPERATION The DS1210 nonvolatile controller performs five circuit functions required to battery back up a RAM. First, a switch is provided to direct power from the battery or the incoming supply (VCCI) depending on which is greater. This switch has a voltage drop of less than 0.3V. The second function which the nonvolatile controller provides is power-fail detection. The DS1210 constantly monitors the incoming supply. When the supply goes out of tolerance, a precision comparator detects power-fail and inhibits chip enable ( CEO ). The third function of write protection is accomplished by holding the CEO output signal to within 0.2 volts of the VCCI or battery supply. If CE input is low at the time power-fail detection occurs, the CEO output is kept in its present state until CE is returned high. The delay of write protection until the current memory cycle is completed prevents the corruption of data. Power-fail detection occurs in the range of 4.75 volts to 4.5 volts with the tolerance (TOL) pin grounded. If TOL in connected to VCCO, then powerfail detection occurs in the range of 4.5 volts to 4.25 volts. During nominal supply conditions CEO will follow CE with a maximum propagation delay of 20ns. The fourth function the DS1210 performs is a battery status warning so that potential data loss is avoided. Each time that the circuit is powered up the battery voltage is checked with a precision comparator. If the battery voltage is less than 2.0 volts, the second memory cycle is inhibited. Battery status can, therefore, be determined by performing a read cycle after power-up to any location in memory, verifying that memory location content. A subsequent write cycle can then be executed to the same memory location altering the data. If the next read cycle fails to verify the written data, then the batteries are less than 2.0V and data is in danger of being corrupted. The fifth function of the nonvolatile controller provides for battery redundancy. In many applications, data integrity is paramount. In these applications it is often desirable to use two batteries to ensure reliability. The DS1210 controller provides an internal isolation switch which allows the connection of two batteries. During battery backup operation the battery with the highest voltage is selected for use. If one battery should fail, the other will take over the load. The switch to a redundant battery is transparent to circuit operation and to the user. A battery status warning will occur when the battery in use falls below 2.0 volts. A grounded VBAT2 pin will not activate a battery-fail warning. In applications where battery redundancy is not required, a single battery should be connected to the BAT1 pin, and the BAT2 battery pin must be grounded. The nonvolatile controller contains circuitry to turn off the battery backup. This is to maintain the battery(s) at its highest capacity until the equipment is powered up and valid data is written to the SRAM. While in the freshness seal mode the CEO and VCCO will be forced to VOL. When the batteries are first attached to one or both of the VBAT pins, VCCO will not provide battery back-up until VCCI exceeds VCCTP, as set by the TOL pin, and then falls below VBAT. Figure 1 shows a typical application incorporating the DS1210 in a microprocessor-based system. Section A shows the connections necessary to write protect the RAM when VCC is less than 4.75 volts and to back up the supply with batteries. Section B shows the use of the DS1210 to halt the processor when VCC is less than 4.75 volts and to delay its restart on power-up to prevent spurious writes. DS1210 3 of 8 SECTION A - BATTERY BACKUP Figure 1 BATTERY BACKUP CURRENT DRAIN EXAMPLE CONSUMPTION DS1210 IBAT 100 nA RAM ICC02 10 µA Total Drain 10.1 µA SECTION B - PROCESSOR RESET DS1210 4 of 8 ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground -0.3V to +7.0V Operating Temperature Range 0°C to +70°C, -40°C to +85°C for N parts Storage Temperature Range -55°C to +125°C Soldering Temperature (reflow, SO) +260°C Lead Temperature (soldering, 10s) +300°C This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) PDIP Junction-to-Ambient Thermal Resistance (θJA).…………………...…………………………...….110°C/W Junction-to-Case Thermal Resistance (θJC)…………………………………………………………40°C/W SO Junction-to-Ambient Thermal Resistance (θJA).…………………………………………………….70°C/W Junction-to-Case Thermal Resistance (θJC)…………………………………………………………23°C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board for the SO. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. RECOMMENDED OPERATING CONDITIONS (Note 10) PARAMETER SYMBOL 4BMIN TYP MAX UNITS 0BNOTES TOL = GND Supply Voltage VCCI 4.75 5.0 5.5 V 2 TOL = VCCO Supply Voltage VCCI 4.5 5.0 5.5 V 2 Logic 1 Input VIH 2.2 VCC+0.3 V 2 Logic 0 Input VIL -0.3 +0.8 V 2 Battery Input VBAT1, VBAT2 2.0 4.0 V 2, 3 DC ELECTRICAL CHARACTERISTICS (Note 10; VCCI = 4.75 to 5.5V, TOL = GND) (VCCI = 4.5 to 5.5V, TOL = VCCO) PARAMETER SYMBOL MIN TYP MAX UNITS 1BNOTES Supply Current ICCI 5 mA 4 Supply Voltage VCCO VCC-0.2 V 2 Supply Current ICCO1 80 mA 5 Input Leakage IIL -1.0 +1.0 µA Output Leakage ILO -1.0 +1.0 µA CEO Output @ 2.4V IOH -1.0 mA 6 CEO Output @ 0.4V IOL 4.0 mA 6 VCC Trip Point (TOL=GND) VCCTP 4.50 4.62 4.74 V 2 VCC Trip Point (TOL=VCCO) VCCTP 4.25 4.37 4.49 V 2 CEO Output VOHL VBAT-0.2 V 8 VBAT1 or VBAT2 Battery Current IBAT 100 nA 3, 4 Battery Backup Current @ VCCO = VBAT – 0.3V ICCO2 50 µA 7, 8 DS1210 5 of 8 CAPACITANCE (TA = +25°C) PARAMETER SYMBOL MIN TYP MAX UNITS 2BNOTES Input Capacitance CIN 5 pF Output Capacitance COUT 7 pF AC ELECTRICAL CHARACTERISTICS (Note 10; VCCI = 4.75V to 5.5V, TOL = GND) (VCCI = 4.5V to 5.5V, TOL = VCCO) PARAMETER SYMBOL MIN TYP MAX UNITS 3BNOTES CE Propagation Delay tPD 5 10 20 ns 6 CE High to Power-Fail tPF 0 ns AC ELECTRICAL CHARACTERISTICS (Note 10; VCCI = 4.75V, TOL = GND) (VCCI < 4.5, TOL = VCCO) Recovery at Power Up tREC 2 80 125 ms VCC Slew Rate Power-Down tF 300 µs VCC Slew Rate Power-Down tFB 10 µs VCC Slew Rate Power-Up tR 0 µs CE Pulse Width tCE 1.5 µs 9 NOTES: 2. All voltages are referenced to ground. 3. Only one battery input is required. Unused battery inputs must be grounded. 4. Measured with VCCO and CEO open. 5. ICC01 is the maximum average load which the DS1210 can supply to the memories. 6. Measured with a load as shown in Figure 2. 7. ICC02 is the maximum average load current which the DS1210 can supply to the memories in the battery backup mode. 8. tCE max must be met to ensure data integrity on power loss. 9. CEO can only sustain leakage current in the battery backup mode. 10. All AC and DC electrical characteristics are valid for the full temperature range. For commercial products, this range is 0 to +70°C. For industrial products (N), this range is -40°C to +85°C. 11. DS1210 is recognized by Underwriters Laboratories (UL) under file E99151. DS1210 6 of 8 TIMING DIAGRAM: POWER-UP TIMING DIAGRAM: POWER-DOWN OUTPUT LOAD Figure 2 DS1210 7 of 8 ORDERING INFORMATION PART TEMP RANGE PINPACKAGE DS1210+ 0°C to +70°C 8 PDIP DS1210N+ -40°C to +85°C 8 PDIP DS1210S+ 0°C to +70°C 16 SO DS1210SN+ -40°C to +85°C 16 SO +Denotes a lead(Pb)-free/RoHS-compliant package. PACKAGE INFORMATION For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 8 PDIP P8+4 21-0043 16 SO W16+2 21-0042 90-0107 DS1210 8 of 8 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, Inc. 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 © 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. REVISION HISTORY REVISION DATE DESCRIPTION PAGES CHANGED 6/12 Added lead temperature and soldering temperature information to the Absolute Maximum Ratings section; changed “Pin 3” to “TOL” in multiple places; added the Package Thermal Characteristics section; added the Ordering Information and Package Information sections 1, 2, 4, 5, 8 1. General description The HEF4052B is a dual 4-channel analog multiplexer/demultiplexer with common channel select logic. Each multiplexer/demultiplexer has four independent inputs/outputs (nY0 to nY3) and a common input/output (nZ). The common channel select logic includes two select inputs (S1 and S2) and an active LOW enable input (E). Both multiplexers/demultiplexers contain four bidirectional analog switches, each with one side connected to an independent input/output (nY0 to nY3) and the other side connected to a common input/output (nZ). With E LOW, one of the four switches is selected (low-impedance ON-state) by S1 and S2. With E HIGH, all switches are in the high-impedance OFF-state, independent of S1 and S2. If break before make is needed, then it is necessary to use the enable input. VDD and VSS are the supply voltage connections for the digital control inputs (S1 and S2, and E). The VDD to VSS range is 3 V to 15 V. The analog inputs/outputs (nY0 to nY3, and nZ) can swing between VDD as a positive limit and VEE as a negative limit. VDD VEE may not exceed 15 V. Unused inputs must be connected to VDD, VSS, or another input. For operation as a digital multiplexer/demultiplexer, VEE is connected to VSS (typically ground). VEE and VSS are the supply voltage connections for the switches. 2. Features and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C and 40 C to +125 C Complies with JEDEC standard JESD 13-B 3. Applications Analog multiplexing and demultiplexing Digital multiplexing and demultiplexing Signal gating HEF4052B Dual 4-channel analog multiplexer/demultiplexer Rev. 9 — 11 September 2014 Product data sheet HEF4052B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 11 September 2014 2 of 22 NXP Semiconductors HEF4052B Dual 4-channel analog multiplexer/demultiplexer 4. Ordering information 5. Functional diagram Table 1. Ordering information All types operate from 40 C to +125 C. Type number Package Name Description Version HEF4052BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 HEF4052BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF4052BTT TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 Fig 1. Functional diagram mnb042 1 - OF - 4 DECODER LOGIC LEVEL CONVERSION 8 7 VSS VEE VDD 12 13 16 3 14 15 11 10 9 6 S1 S2 E 1 5 2 1Y0 1Z 2Z 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 4 HEF4052B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 11 September 2014 3 of 22 NXP Semiconductors HEF4052B Dual 4-channel analog multiplexer/demultiplexer Fig 2. Schematic diagram (one switch) 001aak604 nYn nZ VEE VDD VDD Fig 3. Logic symbol Fig 4. IEC logic symbol 001aak605 4 2 5 1 11 15 14 12 13 3 6 9 1Z S1 S2 E 2Z 2Y3 2Y2 2Y1 2Y0 1Y3 1Y2 1Y1 1Y0 10 mnb041 11 15 14 12 4 2 5 9 1 10 0 6 G4 MDX 0 3 4 × 1 3 2 1 0 13 3 HEF4052B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 11 September 2014 4 of 22 NXP Semiconductors HEF4052B Dual 4-channel analog multiplexer/demultiplexer Fig 5. Logic diagram 001aak634 LEVEL CONVERTER LEVEL CONVERTER LEVEL CONVERTER S1 S2 E 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 2Z 1Z HEF4052B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 11 September 2014 5 of 22 NXP Semiconductors HEF4052B Dual 4-channel analog multiplexer/demultiplexer 6. Pinning information 6.1 Pinning 6.2 Pin description Fig 6. Pin configuration SOT38-4 and SOT109-1 Fig 7. Pin configuration SOT338-1 and SOT403-1 001aag215 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 HEF4052B 2Y0 VDD 2Y2 1Y2 2Z 1Y1 2Y3 1Z 2Y1 1Y0 E 1Y3 VEE S1 VSS S2 HEF4052B 2Y0 VDD 2Y2 1Y2 2Z 1Y1 2Y3 1Z 2Y1 1Y0 E 1Y3 VEE S1 VSS S2 001aak606 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 Table 2. Pin description Symbol Pin Description E 6 enable input (active LOW) VEE 7 supply voltage VSS 8 ground supply voltage S1, S2 10, 9 select input 1Y0, 1Y1, 1Y2, 1Y3, 2Y0, 2Y1, 2Y2, 2Y3 12, 14, 15, 11, 1, 5, 2, 4 independent input or output 1Z, 2Z 13, 3 common output or input VDD 16 supply voltage HEF4052B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 11 September 2014 6 of 22 NXP Semiconductors HEF4052B Dual 4-channel analog multiplexer/demultiplexer 7. Functional description 7.1 Function table [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 8. Limiting values [1] To avoid drawing VDD current out of terminal Z, when switch current flows into terminals Y, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VDD current will flow out of terminals Y, and in this case there is no limit for the voltage drop across the switch, but the voltages at Y and Z may not exceed VDD or VEE. [2] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C. For SO16 package: Ptot derates linearly with 8 mW/K above 70 C. For SSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C. Table 3. Function table[1] Input Channel on E S2 S1 L L L nY0 to nZ L L H nY1 to nZ L H L nY2 to nZ L H H nY3 to nZ H X X switches off Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol Parameter Conditions Min Max Unit VDD supply voltage 0.5 +18 V VEE supply voltage referenced to VDD [1] 18 +0.5 V IIK input clamping current pins Sn and E; VI < 0.5 V or VI > VDD + 0.5 V - 10 mA VI input voltage 0.5 VDD + 0.5 V II/O input/output current - 10 mA IDD supply current - 50 mA Tstg storage temperature 65 +150 C Tamb ambient temperature 40 +125 C Ptot total power dissipation Tamb = 40 C to +125 C [2] DIP16 package - 750 mW SO16 package - 500 mW TSSOP16 package - 500 mW P power dissipation per output - 100 mW HEF4052B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 11 September 2014 7 of 22 NXP Semiconductors HEF4052B Dual 4-channel analog multiplexer/demultiplexer 9. Recommended operating conditions 10. Static characteristics Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VDD supply voltage see Figure 8 3 - 15 V VI input voltage 0 - VDD V Tamb ambient temperature in free air 40 - +125 C t/V input transition rise and fall rate VDD = 5 V - - 3.75 s/V VDD = 10 V - - 0.5 s/V VDD = 15 V - - 0.08 s/V Fig 8. Operating area as a function of the supply voltages VDD − VEE (V) 0 15 5 10 001aac285 10 5 15 VDD − VSS (V) 0 operating area Table 6. Static characteristics VSS = VEE = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter Conditions VDD Tamb = 40 C Tamb = 25 C Tamb = 85 C Tamb = 125 C Unit Min Max Min Max Min Max Min Max VIH HIGH-level input voltage IO < 1 A 5 V 3.5 - 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - 11.0 - V VIL LOW-level input voltage IO < 1 A 5 V - 1.5 - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 - 4.0 V II input leakage current 15 V - 0.1 - 0.1 - 1.0 - 1.0 A HEF4052B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 11 September 2014 8 of 22 NXP Semiconductors HEF4052B Dual 4-channel analog multiplexer/demultiplexer 10.1 Test circuits IS(OFF) OFF-state leakage current Z port; all channels OFF; see Figure 9 15 V - - - 1000 - - - - nA Y port; per channel; see Figure 10 15 V - - - 200 - - - - nA IDD supply current IO = 0 A 5 V - 5 - 5 - 150 - 150 A 10 V - 10 - 10 - 300 - 300 A 15 V - 20 - 20 - 600 - 600 A CI input capacitance Sn, E inputs - - - - 7.5 - - - - pF Table 6. Static characteristics …continued VSS = VEE = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter Conditions VDD Tamb = 40 C Tamb = 25 C Tamb = 85 C Tamb = 125 C Unit Min Max Min Max Min Max Min Max Fig 9. Test circuit for measuring OFF-state leakage current Z port IS 001aak635 VDD VI VSS = VEE S1 and S2 E nZ VDD or VSS VDD nYn VO Fig 10. Test circuit for measuring OFF-state leakage current nYn port IS 001aak636 VSS VO switch VSS = VEE S1 and S2 E nZ nY0 VDD or VSS VDD nYn 1 2 VI HEF4052B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 11 September 2014 9 of 22 NXP Semiconductors HEF4052B Dual 4-channel analog multiplexer/demultiplexer 10.2 On resistance 10.2.1 On resistance waveform and test circuit Table 7. ON resistance Tamb = 25 C; ISW = 200 A; VSS = VEE = 0 V. Symbol Parameter Conditions VDD VEE Typ Max Unit RON(peak) ON resistance (peak) VI = 0 V to VDD VEE; see Figure 11 and Figure 12 5 V 350 2500 10 V 80 245 15 V 60 175 RON(rail) ON resistance (rail) VI = 0 V; see Figure 11 and Figure 12 5 V 115 340 10 V 50 160 15 V 40 115 VI = VDD VEE; see Figure 11 and Figure 12 5 V 120 365 10 V 65 200 15 V 50 155 RON ON resistance mismatch between channels VI = 0 V to VDD VEE; see Figure 11 5 V 25 - 10 V 10 - 15 V 5 - RON = VSW / ISW. Fig 11. Test circuit for measuring RON V 001aak637 VSS VI VSW ISW VSS = VEE S1 and S2 E nZ VDD or VSS VDD nYn HEF4052B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 11 September 2014 10 of 22 NXP Semiconductors HEF4052B Dual 4-channel analog multiplexer/demultiplexer 11. Dynamic characteristics Fig 12. Typical RON as a function of input voltage 9, 9 DDH 521 ȍ 9'' 9 9 9 Table 8. Dynamic characteristics Tamb = 25 C; VSS = VEE = 0 V; for test circuit see Figure 16. Symbol Parameter Conditions VDD Typ Max Unit tPHL HIGH to LOW propagation delay nYn, nZ to nZ, nYn; see Figure 13 5 V 10 20 ns 10 V 5 10 ns 15 V 5 10 ns Sn to nYn, nZ; see Figure 14 5 V 150 305 ns 10 V 65 135 ns 15 V 50 100 ns tPLH LOW to HIGH propagation delay Yn, nZ to nZ, nYn; see Figure 13 5 V 10 20 ns 10 V 5 10 ns 15 V 5 10 ns Sn to nYn, nZ; see Figure 14 5 V 150 300 ns 10 V 75 150 ns 15 V 50 100 ns tPHZ HIGH to OFF-state propagation delay E to nYn, nZ; see Figure 15 5 V 95 190 ns 10 V 90 180 ns 15 V 85 180 ns tPZH OFF-state to HIGH propagation delay E to nYn, nZ; see Figure 15 5 V 130 260 ns 10 V 55 115 ns 15 V 45 85 ns tPLZ LOW to OFF-state propagation delay E to nYn, nZ; see Figure 15 5 V 100 205 ns 10 V 90 180 ns 15 V 90 180 ns HEF4052B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 11 September 2014 11 of 22 NXP Semiconductors HEF4052B Dual 4-channel analog multiplexer/demultiplexer 11.1 Waveforms and test circuit tPZL OFF-state to LOW propagation delay E to nYn, nZ; see Figure 15 5 V 120 240 ns 10 V 50 100 ns 15 V 35 75 ns Table 8. Dynamic characteristics …continued Tamb = 25 C; VSS = VEE = 0 V; for test circuit see Figure 16. Symbol Parameter Conditions VDD Typ Max Unit Measurement points are given in Table 9. Measurement points are given in Table 9. Fig 13. nYn, nZ to nZ, nYn propagation delays Fig 14. Sn to nYn, nZ propagation delays 001aac290 nYn or nZ input nZ or nYn output tPLH tPHL VDD VEE VM VM VO VEE 001aac291 switch ON tPLH tPHL switch OFF VDD VSS VO VEE nYn or nZ output Sn input switch OFF 10 % 90 % VM Measurement points are given in Table 9. Fig 15. Enable and disable times 001aac292 tPLZ tPHZ switch ON switch OFF switch ON nYn or nZ output LOW-to-OFF OFF-to-LOW nYn or nZ output HIGH-to-OFF OFF-to-HIGH E input VO VO VEE VEE VDD VSS VM tPZL tPZH 90 % 90 % 10 % 10 % Table 9. Measurement points Supply voltage Input Output VDD VM VM 5 V to 15 V 0.5VDD 0.5VDD HEF4052B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 11 September 2014 12 of 22 NXP Semiconductors HEF4052B Dual 4-channel analog multiplexer/demultiplexer [1] For nYn to nZ propagation delays use VEE. For Sn to nYn or nZ propagation delays use VDD. Test data is given in Table 10. Definitions: DUT = Device Under Test. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including test jig and probe. RL = Load resistance. Fig 16. Test circuit for measuring switching times 001aaj903 VI VO RT CL RL S1 DUT PULSE GENERATOR tW VM VI VDD VI VDD VSS VEE open 0 V negative pulse VI 0 V positive pulse 10 % 90 % 90 % 10 % VM VM VM tW tf tf tr tr Table 10. Test data Input Load S1 position nYn, nZ Sn and E tr, tf VM CL RL tPHL[1] tPLH tPZH, tPHZ tPZL, tPLZ other VDD or VEE VDD or VSS 20 ns 0.5VDD 50 pF 10 k VDD or VEE VEE VEE VDD VEE HEF4052B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 11 September 2014 13 of 22 NXP Semiconductors HEF4052B Dual 4-channel analog multiplexer/demultiplexer 11.2 Additional dynamic parameters [1] fi is biased at 0.5 VDD; VI = 0.5VDD (p-p). 11.2.1 Test circuits Table 11. Additional dynamic characteristics VSS = VEE = 0 V; Tamb = 25 C. Symbol Parameter Conditions VDD Typ Max Unit THD total harmonic distortion see Figure 17; RL = 10 k; CL = 15 pF; channel ON; VI = 0.5VDD (p-p); fi = 1 kHz 5 V [1] 0.25 - % 10 V [1] 0.04 - % 15 V [1] 0.04 - % f(3dB) 3 dB frequency response see Figure 18; RL = 1 k; CL = 5 pF; channel ON; VI = 0.5VDD (p-p) 5 V [1] 13 - MHz 10 V [1] 40 - MHz 15 V [1] 70 - MHz iso isolation (OFF-state) see Figure 19; fi = 1 MHz; RL = 1 k; CL = 5 pF; channel OFF; VI = 0.5VDD (p-p) 10 V [1] 50 - dB Vct crosstalk voltage digital inputs to switch; see Figure 20; RL = 10 k; CL = 15 pF; E or Sn = VDD (square-wave) 10 V 50 - mV Xtalk crosstalk between switches; see Figure 21; fi = 1 MHz; RL = 1 k; VI = 0.5VDD (p-p) 10 V [1] 50 - dB Table 12. Dynamic power dissipation PD PD can be calculated from the formulas shown; VEE = VSS = 0 V; tr = tf 20 ns; Tamb = 25 C. Symbol Parameter VDD Typical formula for PD (W) where: PD dynamic power dissipation 5V PD = 1300 fi + (fo CL) VDD2 fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VDD = supply voltage in V; (CL fo) = sum of the outputs. 10 V PD = 6100 fi + (fo CL) VDD2 15 V PD = 15600 fi + (fo CL) VDD2 Fig 17. Test circuit for measuring total harmonic distortion Fig 18. Test circuit for measuring frequency response D 001aak638 VSS fi RL CL VSS = VEE S1 and S2 E nZ VDD or VSS VDD nYn dB 001aak639 VSS fi RL CL VSS = VEE S1 and S2 E nZ VDD or VSS VDD nYn HEF4052B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 9 — 11 September 2014 14 of 22 NXP Semiconductors HEF4052B Dual 4-channel analog multiplexer/demultiplexer Fig 19. Test circuit for measuring isolation (OFF-state) dB 001aak657 VSS fi RL CL switch VSS = VEE S1 and S2 E nZ nY0 VDD or VSS VDD nYn 1 2 a. Test circuit b. Input and output pulse definitions Fig 20. Test circuit for measuring crosstalk voltage between digital inputs and switch DDN 9''RU966 9'' VZLWFK 966 9(( 6DQG6 ( Q= Q< 9'' Q
VCC + 0.5 V [1] - 20 mA IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] - 20 mA IO output current 0.5 V < VO < VCC + 0.5 V - 25 mA ICC supply current - 50 mA IGND ground current 50 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation Tamb = 40 C to +125 C DIP20 package [2] - 750 mW SO20, SSOP20, TSSOP20 and DHVQFN20 package [3] - 500 mW 74HC_HCT273 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 4 — 10 June 2013 6 of 21 NXP Semiconductors 74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger 8. Recommended operating conditions 9. Static characteristics Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC273 74HCT273 Unit Min Typ Max Min Typ Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 -VCC V VO output voltage 0 - VCC 0 -VCC V Tamb ambient temperature 40 - +125 40 - +125 C t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HC273 VIH HIGH-level input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VIL LOW-level input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V VOH HIGH-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80 - 160 A 74HC_HCT273 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 4 — 10 June 2013 7 of 21 NXP Semiconductors 74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger 10. Dynamic characteristics CI input capacitance - 3.5 - - - - - pF 74HCT273 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V VOL LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 5.2 mA; VCC = 5.5 V - 0.15 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 5.5 V - - 0.1 - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 8.0 - 80 - 160 A ICC additional supply current per input pin; VI = VCC 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V MR input - 100 360 - 450 - 490 A CP input - 175 630 - 787.5 - 857.5 A Dn input - 15 54 - 67.5 - 73.5 A CI input capacitance - 3.5 - - - - - pF Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max Table 7. Dynamic characteristics GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 10 Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HC273 tpd propagation delay CP to Qn; see Figure 7 [1] VCC = 2.0 V - 41 150 - 185 - 225 ns VCC = 4.5 V - 15 30 - 37 - 45 ns VCC = 5.0 V; CL = 15 pF - 15 - - - - - ns VCC = 6.0 V - 13 26 - 31 - 38 ns 74HC_HCT273 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 4 — 10 June 2013 8 of 21 NXP Semiconductors 74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger tPHL HIGH to LOW propagation delay MR to Qn; see Figure 8 VCC = 2.0 V - 44 150 - 185 - 225 ns VCC = 4.5 V - 16 30 - 37 - 45 ns VCC = 5.0 V; CL = 15 pF - 15 - - - - - ns VCC = 6.0 V - 14 26 - 31 - 38 ns tt transition time Qn output; see Figure 7 [2] VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 15 - 19 ns tW pulse width CP input HIGH or LOW; see Figure 7 VCC = 2.0 V 80 14 - 100 - 120 - ns VCC = 4.5 V 16 5 - 20 - 24 - ns VCC = 6.0 V 14 4 - 17 - 20 - ns MR input LOW; see Figure 8 VCC = 2.0 V 60 17 - 75 - 90 - ns VCC = 4.5 V 12 6 - 15 - 18 - ns VCC = 6.0 V 10 5 - 13 - 15 - ns trec recovery time MR to CP; see Figure 8 VCC = 2.0 V 50 6 - 65 - 75 - ns VCC = 4.5 V 10 2 - 13 - 15 - ns VCC = 6.0 V 9 2 - 11 - 13 - ns tsu set-up time Dn to CP; see Figure 9 VCC = 2.0 V 60 11 - 75 - 90 - ns VCC = 4.5 V 12 4 - 15 - 18 - ns VCC = 6.0 V 10 3 - 13 - 15 - ns th hold time Dn to CP; see Figure 9 VCC = 2.0 V 3 6 - 3 - 3 - ns VCC = 4.5 V 3 2 - 3 - 3 - ns VCC = 6.0 V 3 2 - 3 - 3 - ns fmax maximum frequency CP input; see Figure 7 VCC = 2.0 V 6 20.6 - 4.8 - 4 - MHz VCC = 4.5 V 30 103 - 24 - 20 - MHz VCC = 5.0 V; CL = 15 pF - 66 - - - - - MHz VCC = 6.0 V 35 122 - 28 - 24 - MHz CPD power dissipation capacitance per package; VI = GND to VCC [3] - 20 - - - - - pF Table 7. Dynamic characteristics …continued GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 10 Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HC_HCT273 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 4 — 10 June 2013 9 of 21 NXP Semiconductors 74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger [1] tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; (CL VCC2 fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V. 74HCT273 tpd propagation delay CP to Qn; see Figure 7 [1] VCC = 4.5 V - 16 30 - 38 - 45 ns VCC = 5.0 V; CL = 15 pF - 15 - - - - - ns tPHL HIGH to LOW propagation delay MR to Qn; see Figure 8 VCC = 4.5 V - 23 34 - 43 - 51 ns VCC = 5.0 V; CL = 15 pF - 20 - - - - - ns tt transition time Qn output; see Figure 7 [2] VCC = 4.5 V - 7 15 - 19 - 22 ns tW pulse width CP input; see Figure 7 VCC = 4.5 V 16 9 - 20 - 24 - ns MR input LOW; see Figure 8 VCC = 4.5 V 16 8 - 20 - 24 - ns trec recovery time MR to CP; see Figure 8 VCC = 4.5 V 10 2 - 13 - 15 - ns tsu set-up time Dn to CP; see Figure 9 VCC = 4.5 V 12 5 - 15 - 18 - ns th hold time Dn to CP; see Figure 9 VCC = 4.5 V 3 4 - 3 - 3 - ns fmax maximum frequency CP input; see Figure 7 VCC = 4.5 V 30 56 - 24 - 20 - MHz VCC = 5.0 V; CL = 15 pF - 36 - - - - - MHz CPD power dissipation capacitance per package; VI = GND to VCC 1.5 V [3] - 23 - - - - - pF Table 7. Dynamic characteristics …continued GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 10 Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HC_HCT273 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 4 — 10 June 2013 10 of 21 NXP Semiconductors 74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger 11. Waveforms Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Propagation delay clock input (CP) to output (Qn), clock (CP) pulse width, output transition time and the maximum clock pulse frequency 001aae062 CP input Qn output tPHL tPLH tW tW VM 10% 90% VOH VI GND VOL VM VM 1/fmax tTHL tTLH Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Propagation delay master reset (MR) to output (Qn), pulse width master reset (MR) and recovery time master reset (MR) to clock (CP) mna464 MR input CP input Qn output tPHL tW trec VM VI GND VI VOL GND VM VM VOH 74HC_HCT273 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 4 — 10 June 2013 11 of 21 NXP Semiconductors 74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. Data set-up and hold times data input (Dn) mna767 GND GND th tsu th tsu VM VM VM VI VOH VOL VI Qn output CP input Dn input Table 8. Measurement points Type Input Output VI VM VM 74HC273 VCC 0.5VCC 0.5VCC 74HCT273 3 V 1.3 V 1.3 V 74HC_HCT273 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 4 — 10 June 2013 12 of 21 NXP Semiconductors 74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger Test data is given in Table 9. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch Fig 10. Test circuit for measuring switching times VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf 001aad983 DUT VCC VCC VI VO RT RL S1 CL open G Table 9. Test data Type Input Load S1 position VI tr, tf CL RL tPHL, tPLH 74HC273 VCC 6 ns 15 pF, 50 pF 1 k open 74HCT273 3 V 6 ns 15 pF, 50 pF 1 k open 74HC_HCT273 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 4 — 10 June 2013 13 of 21 NXP Semiconductors 74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger 12. Package outline Fig 11. Package outline SOT146-1 (DIP20) UNIT A max. 1 2 b1 cD E e L MH OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches DIMENSIONS (inch dimensions are derived from the original mm dimensions) SOT146-1 99-12-27 03-02-13 A min. A max. b Z max. e1 ME w 1.73 1.30 0.53 0.38 0.36 0.23 26.92 26.54 6.40 6.22 3.60 3.05 2.54 7.62 0.254 8.25 7.80 10.0 8.3 4.2 0.51 3.2 2 0.068 0.051 0.021 0.015 0.014 0.009 1.060 1.045 0.25 0.24 0.14 0.12 0.1 0.3 0.01 0.32 0.31 0.39 0.33 0.17 0.02 0.13 0.078 MS-001 SC-603 MH c (e ) 1 ME A L seating plane A1 w M b1 e D A2 Z 20 1 11 10 b E pin 1 index 0 5 10 mm scale Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. (1) (1) (1) DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 74HC_HCT273 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 4 — 10 June 2013 14 of 21 NXP Semiconductors 74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger Fig 12. Package outline SOT163-1 (SO20) UNIT A max. A1 A2 A3 bp c D(1) E(1) (1) e HE L Lp Q ywv Z θ OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 SOT163-1 10 20 w M bp detail X Z e 11 1 D y 0.25 075E04 MS-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.51 0.49 0.30 0.29 0.05 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 0 5 10 mm scale X θ A A1 A2 HE Lp Q E c L v M A (A ) 3 A SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 99-12-27 03-02-19 74HC_HCT273 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 4 — 10 June 2013 15 of 21 NXP Semiconductors 74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger Fig 13. Package outline SOT339-1 (SSOP20) UNIT A1 A2 A3 bp c D(1) E(1) e HE L Lp Q (1) Zywv θ OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 7.4 7.0 5.4 5.2 0.65 7.9 7.6 0.9 0.7 0.9 0.5 8 0 o 1.25 0.2 0.1 0.13 o DIMENSIONS (mm are the original dimensions) Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. 1.03 0.63 SOT339-1 MO-150 99-12-27 03-02-19 X w M θ A A1 A2 bp D HE Lp Q detail X E Z e c L v M A (A ) 3 A 1 10 20 11 y 0.25 pin 1 index 0 2.5 5 mm scale SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 A max. 2 74HC_HCT273 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 4 — 10 June 2013 16 of 21 NXP Semiconductors 74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger Fig 14. Package outline SOT360-1 (TSSOP20) UNIT A1 A2 A3 bp c D (1) E (2) (1) e HE L Lp Q Z ywv θ OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.5 0.2 8 0 o 1 0.2 0.13 0.1 o DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT360-1 MO-153 99-12-27 03-02-19 w M bp D Z e 0.25 1 10 20 11 pin 1 index θ A A1 A2 Lp Q detail X L (A ) 3 HE E c v M A X A y 0 2.5 5 mm scale TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 A max. 1.1 74HC_HCT273 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 4 — 10 June 2013 17 of 21 NXP Semiconductors 74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger Fig 15. Package outline SOT764-1 (DHVQFN20) terminal 1 index area 1 0.5 UNIT A1 b Eh e y 0.2 c OUTLINE REFERENCES VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 4.6 4.4 Dh 3.15 2.85 y1 2.6 2.4 1.15 0.85 e1 3.5 0.30 0.18 0.05 0.00 0.05 0.1 DIMENSIONS (mm are the original dimensions) SOT764-1 MO-241 - - - - - - 0.5 0.3 L 0.1 v 0.05 w 0 2.5 5 mm scale SOT764-1 DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm A(1) max. A A1 c detail X y y e 1 C L Eh Dh e e1 b 2 9 19 12 11 1 10 20 X D E C B A terminal 1 index area AC C v M B w M E(1) Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. D(1) 02-10-17 03-01-27 74HC_HCT273 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 4 — 10 June 2013 18 of 21 NXP Semiconductors 74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger 13. Abbreviations 14. Revision history Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT273 v.4 20130610 Product data sheet - 74HC_HCT273 v.3 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. 74HC_HCT273 v.3 20060124 Product data sheet - 74HC_HCT273_CNV v.2 74HC_HCT273_CNV v.2 19970827 Product specification - - 74HC_HCT273 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 4 — 10 June 2013 19 of 21 NXP Semiconductors 74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger 15. Legal information 15.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. 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NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. 74HC_HCT273 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 4 — 10 June 2013 20 of 21 NXP Semiconductors 74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com NXP Semiconductors 74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 10 June 2013 Document identifier: 74HC_HCT273 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Recommended operating conditions. . . . . . . . 6 9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 18 14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 16 Contact information. . . . . . . . . . . . . . . . . . . . . 20 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1. Product profile 1.1 General description High-speed switching diodes, encapsulated in small Surface-Mounted Device (SMD) plastic packages. 1.2 Features and benefits 1.3 Applications High-speed switching General-purpose switching 1.4 Quick reference data [1] When switched from IF = 10 mA to IR = 10 mA; RL = 100 ; measured at IR = 1 mA. BAV756S; BAW56 series High-speed switching diodes Rev. 6 — 18 March 2015 Product data sheet Table 1. Product overview Type number Package Package configuration Configuration NXP JEITA JEDEC BAV756S SOT363 SC-88 - very small quadruple common anode/common cathode BAW56 SOT23 - TO-236AB small dual common anode BAW56M SOT883 SC-101 - leadless ultra small dual common anode BAW56S SOT363 SC-88 - very small quadruple common anode/common anode BAW56T SOT416 SC-75 - ultra small dual common anode BAW56W SOT323 SC-70 - very small dual common anode High switching speed: trr 4 ns Low capacitance: Cd 2 pF Low leakage current Reverse voltage: VR 90 V Small SMD plastic packages AEC-Q101 qualified Table 2. Quick reference data Symbol Parameter Conditions Min Typ Max Unit Per diode IR reverse current VR = 80 V - - 0.5 A VR reverse voltage - - 90 V trr reverse recovery time [1] - - 4 ns BAV756S_BAW56_SER All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 18 March 2015 2 of 16 NXP Semiconductors BAV756S; BAW56 series High-speed switching diodes 2. Pinning information Table 3. Pinning Pin Description Simplified outline Symbol BAV756S 1 anode (diode 1) 2 cathode (diode 2) 3 common anode (diode 2 and diode 3) 4 cathode (diode 3) 5 anode (diode 4) 6 common cathode (diode 1 and diode 4) BAW56; BAW56T; BAW56W 1 cathode (diode 1) 2 cathode (diode 2) 3 common anode BAW56M 1 cathode (diode 1) 2 cathode (diode 2) 3 common anode BAW56S 1 cathode (diode 1) 2 cathode (diode 2) 3 common anode (diode 3 and diode 4) 4 cathode (diode 3) 5 cathode (diode 4) 6 common anode (diode 1 and diode 2) 1 3 2 56 4 006aab103 1 3 6 2 5 4 006aaa144 1 2 3 006aab099 1 2 3 3 1 2 Transparent top view 006aab099 1 2 3 1 3 2 56 4 006aab102 1 3 6 2 5 4 BAV756S_BAW56_SER All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 18 March 2015 3 of 16 NXP Semiconductors BAV756S; BAW56 series High-speed switching diodes 3. Ordering information 4. Marking [1] * = -: made in Hong Kong * = p: made in Hong Kong * = t: made in Malaysia * = W: made in China 5. Limiting values Table 4. Ordering information Type number Package Name Description Version BAV756S SC-88 plastic surface-mounted package; 6 leads SOT363 BAW56 - plastic surface-mounted package; 3 leads SOT23 BAW56M SC-101 leadless ultra small plastic package; 3 solder lands; body 1.0 0.6 0.5 mm SOT883 BAW56S SC-88 plastic surface-mounted package; 6 leads SOT363 BAW56T SC-75 plastic surface-mounted package; 3 leads SOT416 BAW56W SC-70 plastic surface-mounted package; 3 leads SOT323 Table 5. Marking codes Type number Marking code[1] BAV756S A7* BAW56 A1* BAW56M S5 BAW56S A1* BAW56T A1 BAW56W A1* Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Per diode VRRM repetitive peak reverse voltage - 90 V VR reverse voltage - 90 V IF forward current BAV756S Ts = 60 C - 250 mA BAW56 Tamb 25 C - 215 mA BAW56M Tamb 25 C - 150 mA BAW56S Ts = 60 C - 250 mA BAW56T Ts = 90 C - 150 mA BAW56W Tamb 25 C - 150 mA BAV756S_BAW56_SER All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 18 March 2015 4 of 16 NXP Semiconductors BAV756S; BAW56 series High-speed switching diodes [1] Tj = 25 C prior to surge. [2] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint. [3] Reflow soldering is the only recommended soldering method. [4] Single diode loaded. 6. Thermal characteristics IFRM repetitive peak forward current - 500 mA IFSM non-repetitive peak forward current square wave [1] tp = 1 s - 4 A tp = 1 ms - 1 A tp = 1 s - 0.5 A Ptot total power dissipation [2] BAV756S Ts = 60 C - 350 mW BAW56 Tamb 25 C - 250 mW BAW56M Tamb 25 C [3] - 250 mW BAW56S Ts = 60 C - 350 mW BAW56T Ts = 90 C [4] - 170 mW BAW56W Tamb 25 C - 200 mW Per device IF forward current BAV756S Ts = 60 C - 100 mA BAW56 Tamb 25 C - 125 mA BAW56M Tamb 25 C - 75 mA BAW56S Ts = 60 C - 100 mA BAW56T Ts = 90 C - 75 mA BAW56W Tamb 25 C - 130 mA Tj junction temperature - 150 C Tamb ambient temperature 65 +150 C Tstg storage temperature 65 +150 C Table 6. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Table 7. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Per diode Rth(j-a) thermal resistance from junction to ambient in free air [1] BAW56 - - 500 K/W BAW56M [2] - - 500 K/W BAW56W - - 625 K/W BAV756S_BAW56_SER All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 18 March 2015 5 of 16 NXP Semiconductors BAV756S; BAW56 series High-speed switching diodes [1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. [2] Reflow soldering is the only recommended soldering method. 7. Characteristics [1] Pulse test: tp 300 s; 0.02. [2] When switched from IF = 10 mA to IR = 10 mA; RL = 100 ; measured at IR = 1 mA. [3] When switched from IF = 10 mA; tr = 20 ns. Rth(j-sp) thermal resistance from junction to solder point BAV756S - - 255 K/W BAW56 - - 360 K/W BAW56S - - 255 K/W BAW56T - - 350 K/W BAW56W - - 300 K/W Table 7. Thermal characteristics …continued Symbol Parameter Conditions Min Typ Max Unit Table 8. Characteristics Tamb = 25 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Per diode VF forward voltage [1] IF = 1 mA - - 715 mV IF = 10 mA - - 855 mV IF = 50 mA - - 1 V IF = 150 mA - - 1.25 V IR reverse current VR = 25 V - - 30 nA VR = 80 V - - 0.5 A VR = 25 V; Tj = 150 C - - 30 A VR = 80 V; Tj = 150 C - - 150 A Cd diode capacitance VR = 0 V; f = 1 MHz - - 2 pF trr reverse recovery time [2] - - 4 ns VFR forward recovery voltage [3] - - 1.75 V BAV756S_BAW56_SER All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 18 March 2015 6 of 16 NXP Semiconductors BAV756S; BAW56 series High-speed switching diodes (1) Tamb = 150 C (2) Tamb = 85 C (3) Tamb = 25 C (4) Tamb = 40 C Based on square wave currents. Tj = 25 C; prior to surge Fig 1. Forward current as a function of forward voltage; typical values Fig 2. Non-repetitive peak forward current as a function of pulse duration; maximum values (1) Tamb = 150 C (2) Tamb = 85 C (3) Tamb = 25 C (4) Tamb = 40 C f = 1 MHz; Tamb = 25 C Fig 3. Reverse current as a function of reverse voltage; typical values Fig 4. Diode capacitance as a function of reverse voltage; typical values 006aab109 VF (V) 0.2 1.4 0.6 1.0 1 10 102 103 IF (mA) 10−1 (1) (2) (3) (4) mbg704 10 1 102 IFSM (A) 10−1 tp (μs) 1 104 103 10 102 006aab110 10−2 10−4 10−3 10 1 10−1 102 IR (μA) 10−5 VR (V) 0 100 20 40 60 80 (1) (2) (3) (4) 0 25 VR (V) 2.5 0 0.5 mbh191 1.0 1.5 2.0 5 Cd (pF) 10 15 20 BAV756S_BAW56_SER All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 18 March 2015 7 of 16 NXP Semiconductors BAV756S; BAW56 series High-speed switching diodes 8. Test information 8.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is suitable for use in automotive applications. (1) IR = 1 mA Input signal: reverse pulse rise time tr = 0.6 ns; reverse voltage pulse duration tp = 100 ns; duty cycle = 0.05 Oscilloscope: rise time tr = 0.35 ns Fig 5. Reverse recovery time test circuit and waveforms Input signal: forward pulse rise time tr = 20 ns; forward current pulse duration tp 100 ns; duty cycle 0.005 Fig 6. Forward recovery voltage test circuit and waveforms trr (1) + IF t output signal tr tp t 10 % 90 % VR input signal V = VR + IF × RS RS = 50 Ω IF D.U.T. Ri = 50 Ω SAMPLING OSCILLOSCOPE mga881 tr t tp 10 % 90 % I input signal RS = 50 Ω I Ri = 50 Ω OSCILLOSCOPE 1 kΩ 450 Ω D.U.T. mga882 VFR t output signal V BAV756S_BAW56_SER All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 18 March 2015 8 of 16 NXP Semiconductors BAV756S; BAW56 series High-speed switching diodes 9. Package outline Fig 7. Package outline BAW56 (SOT23/TO-236AB) Fig 8. Package outline BAW56M (SOT883/SC-101) Fig 9. Package outline BAV756S and BAW56S (SOT363/SC-88) Fig 10. Package outline BAW56T (SOT416/SC-75) Fig 11. Package outline BAW56W (SOT323/SC-70) Dimensions in mm 04-11-04 0.45 0.15 1.9 1.1 0.9 3.0 2.8 2.5 2.1 1.4 1.2 0.48 0.38 0.15 0.09 1 2 3 Dimensions in mm 03-04-03 0.62 0.55 0.55 0.47 0.50 0.46 0.65 0.20 0.12 3 2 1 0.30 0.22 0.30 0.22 1.02 0.95 0.35 0.25 0.10 0.3 0.2 pin 1 index 1.3 0.65 2.2 2.0 1.35 1.15 2.2 1.8 1.1 0.8 0.45 0.15 1 3 2 6 5 4 Dimensions in mm 14-10-03 Dimensions in mm 04-11-04 0.95 0.60 1.8 1.4 1.75 1.45 0.9 0.7 0.25 0.10 1 0.30 0.15 1 2 3 0.45 0.15 Dimensions in mm 04-11-04 0.45 0.15 1.1 0.8 2.2 1.8 2.2 2.0 1.35 1.15 1.3 0.4 0.3 0.25 0.10 1 2 3 BAV756S_BAW56_SER All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 18 March 2015 9 of 16 NXP Semiconductors BAV756S; BAW56 series High-speed switching diodes 10. Packing information [1] For further information and the availability of packing methods, see Section 14. [2] T1: normal taping [3] T2: reverse taping 11. Soldering Table 9. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.[1] Type number Package Description Packing quantity 3000 10000 BAV756S SOT363 4 mm pitch, 8 mm tape and reel; T1 [2] -115 -135 4 mm pitch, 8 mm tape and reel; T2 [3] -125 -165 BAW56 SOT23 4 mm pitch, 8 mm tape and reel -215 -235 BAW56M SOT883 2 mm pitch, 8 mm tape and reel - -315 BAW56S SOT363 4 mm pitch, 8 mm tape and reel; T1 [2] -115 -135 4 mm pitch, 8 mm tape and reel; T2 [3] -125 -165 BAW56T SOT416 4 mm pitch, 8 mm tape and reel -115 -135 BAW56W SOT323 4 mm pitch, 8 mm tape and reel -115 -135 Fig 12. Reflow soldering footprint BAW56 (SOT23/TO-236AB) solder lands solder resist occupied area solder paste sot023_fr 0.5 (3×) 0.6 (3×) 0.6 (3×) 0.7 (3×) 3 1 3.3 2.9 1.7 1.9 2 Dimensions in mm BAV756S_BAW56_SER All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 18 March 2015 10 of 16 NXP Semiconductors BAV756S; BAW56 series High-speed switching diodes Fig 13. Wave soldering footprint BAW56 (SOT23/TO-236AB) Reflow soldering is the only recommended soldering method. Fig 14. Reflow soldering footprint BAW56M (SOT883/SC-101) solder lands solder resist occupied area preferred transport direction during soldering sot023_fw 2.8 4.5 1.4 4.6 1.4 (2×) 1.2 (2×) 2.2 2.6 Dimensions in mm solder lands solder resist occupied area solder paste sot883_fr 1.3 0.3 0.6 0.7 0.4 0.9 0.3 (2×) 0.4 (2×) 0.25 (2×) 0.7 R0.05 (12×) Dimensions in mm BAV756S_BAW56_SER All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 18 March 2015 11 of 16 NXP Semiconductors BAV756S; BAW56 series High-speed switching diodes Fig 15. Reflow soldering footprint BAV756S and BAW56S (SOT363/SC-88) Fig 16. Wave soldering footprint BAV756S and BAW56S (SOT363/SC-88) solder lands solder resist occupied area solder paste sot363_fr 2.65 2.35 0.4 (2×) 0.6 (2×) 0.5 (4×) 0.5 (4×) 0.6 (4×) 0.6 (4×) 1.5 1.8 Dimensions in mm sot363_fw solder lands solder resist occupied area preferred transport direction during soldering 5.3 1.3 1.3 1.5 0.3 1.5 4.5 2.45 2.5 Dimensions in mm BAV756S_BAW56_SER All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 18 March 2015 12 of 16 NXP Semiconductors BAV756S; BAW56 series High-speed switching diodes Fig 17. Reflow soldering footprint BAW56T (SOT416/SC-75) Fig 18. Reflow soldering footprint BAW56W (SOT323/SC-70) Fig 19. Wave soldering footprint BAW56W (SOT323/SC-70) solder resist occupied area Dimensions in mm solder lands solder paste msa438 2.0 0.6 (3x) 0.7 1.5 1 2 3 1.1 2.2 0.5 (3x) 0.85 0.6 1.9 msa429 0.852.35 0.55 (3×) 0.75 1.325 2.40 2.65 1.30 3 2 1 0.60 (3×) 0.50 (3×) 1.90 solder lands solder resist occupied area solder paste Dimensions in mm msa419 4.00 4.60 2.103.65 1.15 2.70 3 2 1 0.90 (2×) preferred transport direction during soldering solder lands solder resist occupied area Dimensions in mm BAV756S_BAW56_SER All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 18 March 2015 13 of 16 NXP Semiconductors BAV756S; BAW56 series High-speed switching diodes 12. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes BAV756S_BAW56_SER v.6 20150318 Product data sheet - BAV756S_BAW56_SER_ 5 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. BAV756S_BAW56_SER_5 20071126 Product data sheet - BAV756S_2 BAW56_4 BAW56S_2 BAW56T_2 BAW56W_4 BAV756S_2 19971021 Product specification - BAV756S_1 BAW56_4 20030325 Product specification - BAW56_3 BAW56S_2 19971021 Product specification - BAW56S_1 BAW56T_2 19971219 Product specification - - BAW56W_4 19990511 Product specification - BAW56W_3 BAV756S_BAW56_SER All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 18 March 2015 14 of 16 NXP Semiconductors BAV756S; BAW56 series High-speed switching diodes 13. Legal information 13.1 Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 13.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 13.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. BAV756S_BAW56_SER All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 6 — 18 March 2015 15 of 16 NXP Semiconductors BAV756S; BAW56 series High-speed switching diodes No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com NXP Semiconductors BAV756S; BAW56 series High-speed switching diodes © NXP Semiconductors N.V. 2015. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 18 March 2015 Document identifier: BAV756S_BAW56_SER Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 15. Contents 1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 General description . . . . . . . . . . . . . . . . . . . . . 1 1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1 1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . 1 2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 3 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Thermal characteristics . . . . . . . . . . . . . . . . . . 4 7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Test information. . . . . . . . . . . . . . . . . . . . . . . . . 7 8.1 Quality information . . . . . . . . . . . . . . . . . . . . . . 7 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 10 Packing information . . . . . . . . . . . . . . . . . . . . . 9 11 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 13.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 13.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 13.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 13.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 14 Contact information. . . . . . . . . . . . . . . . . . . . . 15 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PWP RHB NT 1FEATURES APPLICATIONS DESCRIPTION Delay x0 12−Bit Grayscale PWM Control DC Register GS Register DC EEPROM Constant Current Driver LED Open Detection Temperature Error Flag (TEF) Max. OUTn Current Delay x1 12−Bit Grayscale PWM Control DC Register GS Register DC EEPROM Constant Current Driver LED Open Detection Delay x15 6−Bit Dot 12−Bit Grayscale PWM Control DC Register GS Register DC EEPROM Constant Current Driver LED Open Detection OUT0 OUT1 OUT15 SOUT SCLK SIN IREF XERR XLAT GSCLK BLANK DCPRG DCPRG DCPRG VPRG VPRG VPRG VCC GND VPRG Input Shift Register Input Shift Register VPRG 0 11 12 23 180 191 90 95 6 11 5 VPRG 0 0 95 96 191 LED Open Detection (LOD) 5 90 95 6 11 DCPRG 0 192 96 1 0 1 0 0 1 1 0 GS Counter CNT CNT CNT CNT 96 96 Status Information: LOD, TED, DC DATA 192 0 191 1 0 0 1 VREF =1.24 V Correction 6−Bit Dot Correction 6−Bit Dot Correction 1 0 Blank TLC5940 SLVS515C–DECEMBER 2004–REVISED OCTOBER 2007 www.ti.com 16 CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL 2• 16 Channels • Monocolor, Multicolor, Full-Color LED Displays • 12 bit (4096 Steps) Grayscale PWM Control • LED Signboards • Dot Correction • Display Backlighting • General, High-Current LED Drive – 6 bit (64 Steps) – Storable in Integrated EEPROM • Drive Capability (Constant-Current Sink) The TLC5940 is a 16-channel, constant-current sink – 0 mA to 60 mA (VCC < 3.6 V) LED driver. Each channel has an individually – 0 mA to 120 mA (VCC > 3.6 V) adjustable 4096-step grayscale PWM brightness • LED Power Supply Voltage up control and a 64-step, constant-current sink (dot to 17 V correction). The dot correction adjusts the brightness • VCC = 3 V to 5.5 V variations between LED channels and other LED • Serial Data Interface drivers. The dot correction data is stored in an • Controlled In-Rush Current integrated EEPROM. Both grayscale control and dot correction are accessible via a serial interface. A • 30MHz Data Transfer Rate single external resistor sets the maximum current • CMOS Level I/O value of all 16 channels. • Error Information The TLC5940 features two error information circuits. – LOD: LED Open Detection The LED open detection (LOD) indicates a broken or – TEF: Thermal Error Flag disconnected LED at an output terminal. The thermal error flag (TEF) indicates an overtemperature condition. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 2004–2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ABSOLUTE MAXIMUM RATINGS. TLC5940 SLVS515C–DECEMBER 2004–REVISED OCTOBER 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA PACKAGE(1) PART NUMBER 28-pin HTSSOP PowerPAD™ TLC5940PWP –40°C to 85°C 32-pin 5mm x 5mm QFN TLC5940RHB 28-pin PDIP TLC5940NT (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. over operating free-air temperature range (unless otherwise noted) (1) UNIT VI Input voltage range(2) VCC –0.3V to 6V IO Output current (dc) 130mA VI Input voltage range V(BLANK), V(DCPRG), V(SCLK), V(XLAT), V(SIN), V(GSCLK), V(IREF) –0.3V to VCC +0.3V V(SOUT), V(XERR) –0.3V to VCC +0.3V VO Output voltage range V(OUT0) to V(OUT15) –0.3V to 18V EEPROM program range V(VPRG) –0.3V to 24V EEPROM write cycles 50 HBM (JEDEC JESD22-A114, Human Body Model) 2kV ESD rating CBM (JEDEC JESD22-C101, Charged Device Model) 500V Tstg Storage temperature range –55°C to 150°C TA Operating ambient temperature range –40°C to 85°C HTSSOP (PWP) (4) 31.58°C/W Package thermal impedance(3) QFN (RHB) 35.9°C/W PDIP (NP) 48°C/W (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal. (3) The package thermal impedance is calculated in accordance with JESD 51-7. (4) With PowerPAD soldered on PCB with 2 oz. (56,7 grams) trace of copper. See SLMA002 for further information. 2 Submit Documentation Feedback Copyright © 2004–2007, Texas Instruments Incorporated Product Folder Link(s): TLC5940 www.ti.com RECOMMENDED OPERATING CONDITIONS DISSIPATION RATINGS TLC5940 SLVS515C–DECEMBER 2004–REVISED OCTOBER 2007 MIN NOM MAX UNIT DC CHARACTERISTICS VCC Supply Voltage 3 5.5 V VO Voltage applied to output (OUT0–OUT15) 17 V VIH High-level input voltage 0.8 VCC VCC V VIL Low-level input voltage GND 0.2 VCC V IOH High-level output current VCC = 5V at SOUT –1 mA IOL Low-level output current VCC = 5V at SOUT, XERR 1 mA OUT0 to OUT15, VCC < 3.6V 60 mA IOLC Constant output current OUT0 to OUT15, VCC > 3.6V 120 mA V(VPRG) EEPROM program voltage 20 22 23 V TA Operating free-air temperature range -40 85 °C AC CHARACTERISTICS VCC = 3 V to 5.5 V, TA = –40°C to 85°C (unless otherwise noted) f (SCLK) Data shift clock frequency SCLK 30 MHz f (GSCLK) Grayscale clock frequency GSCLK 30 MHz twh0/twl0 SCLK pulse duration SCLK = H/L (see Figure 11) 16 ns twh1/twl1 GSCLK pulse duration GSCLK = H/L (see Figure 11) 16 ns twh2 XLAT pulse duration XLAT = H (see Figure 11) 20 ns twh3 BLANK pulse duration BLANK = H (see Figure 11) 20 ns t su0 SIN to SCLK ↑ (1) (see Figure 11) 5 ns t su1 SCLK ↓ to XLAT ↑ (see Figure 11) 10 ns t su2 VPRG ↑ ↓ to SCLK ↑ (see Figure 11) 10 ns t su3 Setup time VPRG ↑ ↓XLAT ↑ (see Figure 11) 10 ns t su4 BLANK ↓ to GSCLK ↑ (see Figure 11) 10 ns t su5 XLAT ↑ to GSCLK ↑ (see Figure 11) 30 ns t su6 VPRG ↑ to DCPRG ↑ (see Figure 16) 1 ms th0 SCLK ↑ to SIN (see Figure 11) 3 ns th1 XLAT ↓ to SCLK ↑ (see Figure 11) 10 ns th2 SCLK ↑ to VPRG ↑ ↓ (see Figure 11) 10 ns Hold Time th3 XLAT ↓ to VPRG ↑ ↓ (see Figure 11) 10 ns th4 GSCLK ↑ to BLANK ↑ (see Figure 11) 10 ns th5 DCPRG ↓ to VPRG ↓ (see Figure 11) 1 ms tprog Programming time for EEPROM (see Figure 16) 20 ms (1) ↑ and ↓ indicates a rising edge, and a falling edge respectively. POWER RATING DERATING FACTOR POWER RATING POWER RATING PACKAGE TA < 25°C ABOVE TA = 25°C TA = 70°C TA = 85°C 28-pin HTSSOP with 3958mW 31.67mW/C 2533mW 2058mW PowerPAD™(1) soldered 28-pin HTSSOP with PowerPAD™ 2026mW 16.21mW/°C 1296mW 1053mW unsoldered 32-pin QFN(1) 3482mW 27.86mW/°C 2228mW 1811mW 28-pin PDIP 2456mW 19.65mW/°C 1572mW 1277mW (1) The PowerPAD is soldered to the PCB with a 2 oz. (56,7 grams) copper trace. See SLMA002 for further information. Copyright © 2004–2007, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): TLC5940 www.ti.com ELECTRICAL CHARACTERISTICS TLC5940 SLVS515C–DECEMBER 2004–REVISED OCTOBER 2007 VCC = 3 V to 5.5 V, TA = –40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage IOH = -1mA, SOUT VCC –0.5 V VOL Low-level output voltage IOL = 1mA, SOUT 0.5 V VI = VCC or GND; BLANK, DCPRG, GSCLK, SCLK, SIN, –1 1 XLAT µA I VI = GND; VPRG –1 1 I Input current VI = VCC; VPRG 50 VI = 22V; VPRG; DCPRG = VCC 4 10 mA No data transfer, all output OFF, 0.9 6 VO = 1V, R(IREF) = 10kΩ No data transfer, all output OFF, 5.2 12 VO = 1V, R(IREF) = 1.3kΩ ICC Supply current mA Data transfer 30MHz, all output ON, 16 25 VO = 1V, R(IREF) = 1.3kΩ Data transfer 30MHz, all output ON, 30 60 VO = 1V, R(IREF) = 640Ω Constant sink current (see IO(LC) All output ON, VO = 1V, R(IREF) = 640Ω 54 61 69 mA Figure 2) All output OFF, VO = 15V, R(IREF) = 640Ω, I lkg Leakage output current 0.1 µA OUT0 to OUT15 All output ON, VO = 1V, R(IREF) = 640Ω, 1 ±4 OUT0 to OUT15, –20°C to 85°C All output ON, VO = 1V, R(IREF) = 640Ω, 1 8 OUT0 to OUT15(1) Constant sink current error ΔIO(LC0) % (see Figure 2) All output ON, VO = 1V, R(IREF) = 320Ω, 1 6 OUT0 to OUT15, –20°C to 85°C All output ON, VO = 1V, R(IREF) = 320Ω, ±1 ±8 VCC = 4.5V to 5.5V, OUT0 to OUT15(1) Constant sink current error Device to device, Averaged current from OUT0 to –2 ΔIO(LC1) 4 % (see Figure 2) OUT15, R(IREF) = 1920Ω (20mA) (2) +0.4 Constant sink current error Device to device, Averaged current from OUT0 to –2.7 ΔIO(LC2) ±4 % (see Figure 2) OUT15, R(IREF) = 480Ω (80mA) (2) +2 All output ON, VO = 1V, R(IREF) = 640Ω 1 ±4 %/V OUT0 to OUT15, VCC = 3V to 5.5V(3) ΔIO(LC3) Line regulation (see Figure 2) All output ON, VO = 1V, R(IREF) = 320Ω , ±1 ±6 %/V OUT0 to OUT15, VCC = 3V to 5.5V(3) All output ON, VO = 1V to 3V, R(IREF) = 640Ω, ±2 ±6 %/V OUT0 to OUT15(4) ΔIO(LC4) Load regulation (see Figure 2) All output ON, VO = 1V to 3V, R(IREF) = 320Ω, 2 8 %/V OUT0 to OUT15(4) T(TEF) Thermal error flag threshold Junction temperature(5) 150 170 C V(LED) LED open detection threshold 0.3 0.4 V Reference voltage V(IREF) R(IREF) = 640Ω 1.20 1.24 1.28 V output (1) The deviation of each output from the average of OUT0-15 constant current. It is calculated by Equation 1 in Table 1. (2) The deviation of average of OUT1-15 constant current from the ideal constant-current value. It is calculated by Equation 2 in Table 1. The ideal current is calculated by Equation 3 in Table 1. (3) The line regulation is calculated by Equation 4 in Table 1. (4) The load regulation is calculated by Equation 5 in Table 1. (5) Not tested. Specified by design 4 Submit Documentation Feedback Copyright © 2004–2007, Texas Instruments Incorporated Product Folder Link(s): TLC5940 www.ti.com 100 I I I (%) OUTavg _ 0 15 OUTn OUTavg _ 0 15 ´ - D = - - (1) 100 I I I (%) OUT(IDEAL) OUTavg OUT(IDEAL) ´ - D = (2) ÷ ÷ ø ö ç ç è æ = ´ IREF OUT(IDEAL) R .1 24V I 31 5. (3) 5.2 100 I( at V 0.3 V) I( at V 5.5 V) I( at V 0.3 V) (% / V) OUTn CC OUTn CC OUTn CC ´ = = - = D = (4) 0.2 100 I( at V 0.1 V) I( at V 0.3 V) I( at V 0.1 V) (%/ V) OUTn OUTn OUTn OUTn OUTn OUTn ´ = = - = D = (5) SWITCHING CHARACTERISTICS TLC5940 SLVS515C–DECEMBER 2004–REVISED OCTOBER 2007 Table 1. Test Parameter Equations VCC = 3V to 5.5V, TA = -40°C to 85°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t r0 SOUT 16 Rise time ns t r1 OUTn, VCC = 5V, TA = 60°C, DCn = 3Fh 10 30 t f0 SOUT 16 Fall time ns t f1 OUTn, VCC = 5V, TA = 60°C, DCn = 3Fh 10 30 tpd0 SCLK to SOUT (see Figure 11) 30 ns tpd1 BLANK to OUT0 60 ns tpd2 OUTn to XERR (see Figure 11 ) 1000 ns Propagation delay time tpd3 GSCLK to OUT0 (see Figure 11 ) 60 ns tpd4 XLAT to IOUT (dot correction) (see Figure 11 ) 60 ns tpd5 DCPRG to OUT0 (see Figure 11) 30 ns td Output delay time OUTn to OUT(n+1) (see Figure 11 ) 20 30 ns ton-err Output on-time error touton– Tgsclk (see Figure 11), GSn = 01h, GSCLK = 11 MHz 10 –50 –90 ns Copyright © 2004–2007, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): TLC5940 www.ti.com DEVICE INFORMATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND BLANK XLAT SCLK SIN VPRG OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 VCC IREF DCPRG GSCLK SOUT XERR OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 PWP PACKAGE (TOP VIEW) Thermal PAD THERMAL PAD GSCLK 24 SOUT 23 XERR 22 OUT15 21 OUT14 20 OUT13 19 OUT12 18 OUT11 17 16 OUT10 15 OUT9 14 OUT8 13 NC 12 NC 11 OUT7 10 OUT6 9 OUT5 OUT4 8 OUT3 7 OUT2 6 OUT1 5 OUT0 4 VPRG 3 SIN 2 SCLK 1 DCPRG 25 IREF 26 VCC 27 NC 28 NC 29 GND 30 BLANK 31 XLAT 32 RHB PACKAGE (TOP VIEW) NC − No internal connection 1 2 3 4 5 6 7 8 9 10 11 12 13 14 18 17 16 15 22 21 20 19 26 25 24 23 28 27 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 GND VCC IREF DCPRG GSCLK SOUT XERR OUT15 SCLK XLAT BLANK OUT0 VPRG SIN NT PACKAGE (TOP VIEW) TLC5940 SLVS515C–DECEMBER 2004–REVISED OCTOBER 2007 6 Submit Documentation Feedback Copyright © 2004–2007, Texas Instruments Incorporated Product Folder Link(s): TLC5940 www.ti.com TLC5940 SLVS515C–DECEMBER 2004–REVISED OCTOBER 2007 TERMINAL FUNCTION TERMINAL NO. I/O DESCRIPTION NAME DIP PWP RHB Blank all outputs. When BLANK = H, all OUTn outputs are forced OFF. GS counter is also BLANK 23 2 31 I reset. When BLANK = L, OUTn are controlled by grayscale PWM control. Switch DC data input. When DCPRG = L, DC is connected to EEPROM. When DCPRG = H, DCPRG 19 26 25 I DC is connected to the DC register. DCPRG also controls EEPROM writing, when VPRG = V(PRG). EEPROM data = 3Fh (default) GND 22 1 30 G Ground GSCLK 18 25 24 I Reference clock for grayscale PWM control IREF 20 27 26 I Reference current terminal 12, 13, NC – – No connection 28, 29 OUT0 28 7 4 O Constant current output OUT1 1 8 5 O Constant current output OUT2 2 9 6 O Constant current output OUT3 3 10 7 O Constant current output OUT4 4 11 8 O Constant current output OUT5 5 12 9 O Constant current output OUT6 6 13 10 O Constant current output OUT7 7 14 11 O Constant current output OUT8 8 15 14 O Constant current output OUT9 9 16 15 O Constant current output OUT10 10 17 16 O Constant current output OUT11 11 18 17 O Constant current output OUT12 12 19 18 O Constant current output OUT13 13 20 19 O Constant current output OUT14 14 21 20 O Constant current output OUT15 15 22 21 O Constant current output SCLK 25 4 1 I Serial data shift clock SIN 26 5 2 I Serial data input SOUT 17 24 23 O Serial data output VCC 21 28 27 I Power supply voltage Multifunction input pin. When VPRG = GND, the device is in GS mode. When VPRG = VCC, the VPRG 27 6 3 I device is in DC mode. When VPRG = V(VPRG), DC register data can programmed into DC EEPROM with DCPRG=HIGH. EEPROM data = 3Fh (default) XERR 16 23 22 O Error output. XERR is an open-drain terminal. XERR goes L when LOD or TEF is detected. Level triggered latch signal. When XLAT = high, the TLC5940 writes data from the input shift XLAT 24 3 32 I register to either GS register (VPRG = low) or DC register (VPRG = high). When XLAT = low, the data in GS or DC register is held constant. Copyright © 2004–2007, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): TLC5940 www.ti.com PARAMETER MEASUREMENT INFORMATION PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC INPUT GND 400 W INPUT EQUIVALENT CIRCUIT (BLANK, XLAT, SCLK, SIN, GSCLK, DCPRG) 23 W 23 SOUT GND OUTPUT EQUIVALENT CIRCUIT (SOUT) _ + Amp 400 W 100 W VCC INPUT GND INPUT EQUIVALENT CIRCUIT (IREF) XERR GND OUTPUT EQUIVALENT CIRCUIT (XERR) 23 W INPUT INPUT GND GND INPUT EQUIVALENT CIRCUIT (VCC) INPUT EQUIVALENT CIRCUIT (VPRG) OUT GND OUTPUT EQUIVALENT CIRCUIT (OUT) VCC W V(IREF) TLC5940 SLVS515C–DECEMBER 2004–REVISED OCTOBER 2007 Resistor values are equivalent resistances, and they are not tested. Figure 1. Input and Output Equivalent Circuits 8 Submit Documentation Feedback Copyright © 2004–2007, Texas Instruments Incorporated Product Folder Link(s): TLC5940 www.ti.com SOUT OUTn t , t , t r0 f0 pd0 t , t , t , t , t , t , t , t r1 f1 pd1 pd2 pd3 pd4 pd5 d VO = 4V Testpoint C = 15pF L Testpoint R = 51 L W C = 15pF L V = 1V O OUTn V = 1V to 3V O OUTn IREF R (IREG) 470kΩ Testpoint V(IREF) VCC XERR tpd3 I , I , I , I , I O(LC) O(LC0) O(LC1) O(LC2) O(LC3) D D D D DIO(LC4) = 640W TLC5940 SLVS515C–DECEMBER 2004–REVISED OCTOBER 2007 PARAMETER MEASUREMENT INFORMATION (continued) Figure 2. Parameter Measurement Circuits Copyright © 2004–2007, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): TLC5940 www.ti.com TYPICAL CHARACTERISTICS 100 1 k 10 k IO − Output Current − mA 0 20 60 100 Reference Resistor, R - (IREF) W 40 80 120 7.68 kΩ 1.92 kΩ 0.96 kΩ 0.64 kΩ 0.38 kΩ 0.32 kΩ 0.48 kΩ 0 1 k 3 k 4 k 2 k TA − Free-Air Temperature − C o -20 0 20 100 Power Dissipation Rate - mW -40 40 60 80 TLC5940PWP PowerPAD Soldered TLC5940PWP PowerPAD Unsoldered TLC5940RHB TLC5940NT 0 20 40 60 80 100 120 140 0 0.5 1 1.5 2 2.5 3 V - Output Voltage - V O I - Output Current - mA O T = 25 C, V = 5 V A CC ° I = 120 mA O I = 100 mA O I = 80 mA O I = 60 mA O I = 40 mA O I = 20 mA O I = 5 mA O 55 56 57 58 59 60 61 62 63 64 65 0 0.5 1 1.5 2 2.5 3 V - Output Voltage - V O I - Output Current - mA O I = 60 mA, V = 5 V O CC T = 85 C A ° T = -40 C A ° T = 25 C A ° TLC5940 SLVS515C–DECEMBER 2004–REVISED OCTOBER 2007 REFERENCE RESISTOR POWER DISSIPATION RATE vs vs OUTPUT CURRENT FREE-AIR TEMPERATURE Figure 3. Figure 4. OUTPUT CURRENT OUTPUT CURRENT vs vs OUTPUT VOLTAGE OUTPUT VOLTAGE Figure 5. Figure 6. 10 Submit Documentation Feedback Copyright © 2004–2007, Texas Instruments Incorporated Product Folder Link(s): TLC5940 www.ti.com -8 -6 -4 -2 0 2 4 6 8 0 20 40 60 80 I - Output Current - mA O Δ I - Constant Output Current - % OLC T = 25 C, V = 5 V A CC ° -8 -6 -4 -2 0 2 4 6 8 -40 -20 0 20 40 60 80 100 T - Ambient Temperature - C A ° Δ I - Constant Output Current - % OLC V = 3.3 V CC V = 5 V CC I = 60 mA O 0 20 40 60 80 100 120 140 0 10 20 30 40 50 60 70 Dot Correction Data - dec I - Output Current - mA O I = 5 mA O I = 60 mA O I = 80 mA O I = 120 mA O I = 30 mA O T = 25 C, V = 5 V A CC ° 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 Dot Correction Data - dec I - Output Current - mA O T = -40 C A ° T = 25 C A ° T = 85 C A ° I = 60 mA, V = 5 V O CC TLC5940 SLVS515C–DECEMBER 2004–REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) CONSTANT OUTPUT CURRENT, ΔIOLC CONSTANT OUTPUT CURRENT, ΔIOLC vs vs AMBIENT TEMPERATURE OUTPUT CURRENT Figure 7. Figure 8. OUTPUT CURRENT OUTPUT CURRENT vs vs DOT CORRECTION LINEARITY (ABS VALUE) DOT CORRECTION LINEARITY (ABS VALUE) Figure 9. Figure 10. Copyright © 2004–2007, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): TLC5940 www.ti.com PRINCIPLES OF OPERATION SERIAL INTERFACE VPRG XLAT SIN SCLK SOUT BLANK GSCLK OUT0 (current) OUT1 (current) OUT15 (current) XERR 1 96 DC MSB DC LSB DC MSB 1 192 193 1 192 193 1 1 4096 t t su4 h4 twh3 1 GS1 MSB GS1 LSB GS1 MSB GS2 MSB GS2 LSB GS2 MSB SID2 MSB SID2 MSB-1 SID1 MSB SID1 MSB-1 SID1 LSB GS3 MSB - - - twh2 t su2 t su1 twh0 twl0 t su0 th0 tpd0 tpd1 t + t pd1 d t + 15 x t pd1 d tpd3 td 15 x td tpd2 t + t pd3 d tpd3 tpd4 twl1 twh1 DC Data Input Mode GS Data Input Mode 1st GS Data Input Cycle 2nd GS Data Input Cycle 1st GS Data Output Cycle 2nd GS Data Output Cycle t su3 th3 th2 th1 t su5 Tgsclk touton SIN(a) SIN SOUT SOUT(b) TLC5940 (a) GSCLK, BLANK, SIN SOUT TLC5940 (b) SCLK, XLAT, VPRG DCPRG, TLC5940 SLVS515C–DECEMBER 2004–REVISED OCTOBER 2007 The TLC5940 has a flexible serial interface, which can be connected to microcontrollers or digital signal processors in various ways. Only 3 pins are needed to input data into the device. The rising edge of SCLK signal shifts the data from the SIN pin to the internal register. After all data is clocked in, a high-level pulse of XLAT signal latches the serial data to the internal registers. The internal registers are level-triggered latches of XLAT signal. All data are clocked in with the MSB first. The length of serial data is 96 bit or 192 bit, depending on the programming mode. Grayscale data and dot correction data can be entered during a grayscale cycle. Although new grayscale data can be clocked in during a grayscale cycle, the XLAT signal should only latch the grayscale data at the end of the grayscale cycle. Latching in new grayscale data immediately overwrites the existing grayscale data. Figure 11 shows the timing chart. More than two TLC5940s can be connected in series by connecting an SOUT pin from one device to the SIN pin of the next device. An example of cascading two TLC5940s is shown in Figure 12 and the timing chart is shown in Figure 13. The SOUT pin can also be connected to the controller to receive status information from TLC5940 as shown in Figure 22. Figure 11. Serial Data Input Timing Chart Figure 12. Cascading Two TLC5940 Devices 12 Submit Documentation Feedback Copyright © 2004–2007, Texas Instruments Incorporated Product Folder Link(s): TLC5940 www.ti.com VPRG XLAT SIN(a) SCLK SOUT(b) BLANK GSCLK OUT0 (current) OUT1 (current) OUT15 (current) XERR 1 192X2 DCb MSB DCa LSB DCb MSB 1 384 385 1 384 385 1 1 4096 1 GSb1 MSB GSa1 LSB GSb1 MSB GSb2 MSB GSa2 LSB GSb2 MSB SIDb2 MSB SIDb2 MSB-1 SIDb1 MSB SIDb1 MSB-1 SIDa1 LSB GSb3 MSB - - - 192 96X2 ERROR INFORMATION OUTPUT TEF: THERMAL ERROR FLAG TLC5940 SLVS515C–DECEMBER 2004–REVISED OCTOBER 2007 Figure 13. Timing Chart for Two Cascaded TLC5940 Devices The open-drain output XERR is used to report both of the TLC5940 error flags, TEF and LOD. During normal operating conditions, the internal transistor connected to the XERR pin is turned off. The voltage on XERR is pulled up to VCC through an external pullup resistor. If TEF or LOD is detected, the internal transistor is turned on, and XERR is pulled to GND. Since XERR is an open-drain output, multiple ICs can be OR'ed together and pulled up to VCC with a single pullup resistor. This reduces the number of signals needed to report a system error (see Figure 22). To differentiate LOD and TEF signal from XERR pin, LOD can be masked out with BLANK = HIGH. Table 2. XERR Truth Table ERROR CONDITION ERROR INFORMATION SIGNALS TEMPERATURE OUTn VOLTAGE TEF LOD BLANK XERR TJ < T(TEF) Don't Care L X H H TJ > T(TEF) Don't Care H X L OUTn > V(LED) L L H TJ < T(TEF) OUTn < V(LED) L H L L OUTn > V(LED) H L L TJ > T(TEF) OUTn < V(LED) H H L The TLC5940 provides a temperature error flag (TEF) circuit to indicate an overtemperature condition of the IC. If the junction temperature exceeds the threshold temperature (160C typical), TEF becomes H and XERR pin goes to low level. When the junction temperature becomes lower than the threshold temperature, TEF becomes L and XERR pin becomes high impedance. TEF status can also be read out from the TLC5940 status register. Copyright © 2004–2007, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Link(s): TLC5940 www.ti.com LOD: LED OPEN DETECTION DELAY BETWEEN OUTPUTS OUTPUT ENABLE SETTING MAXIMUM CHANNEL CURRENT Imax V (IREF) R(IREF) 31.5 (6) TLC5940 SLVS515C–DECEMBER 2004–REVISED OCTOBER 2007 The TLC5940 has an LED-open detector that detects broken or disconnected LEDs. The LED open detector pulls the XERR pin to GND when an open LED is detected. XERR and the corresponding error bit in the Status Information Data is only active under the following open-LED conditions. 1. OUTn is on and the time tpd2 (1 µs typical) has passed. 2. The voltage of OUTn is < 0.3V (typical) The LOD status of each output can be also read out from the SOUT pin. See STATUS INFORMATION OUTPUT section for details. The LOD error bits are latched into the Status Information Data when XLAT returns to a low after a high. Therefore, the XLAT pin must be pulsed high then low while XERR is active in order to latch the LOD error into the Status Information Data for subsequent reading via the serial shift register. The TLC5940 has graduated delay circuits between outputs. These circuits can be found in the constant current driver block of the device (see the functional block diagram). The fixed-delay time is 20ns (typical), OUT0 has no delay, OUT1 has 20ns delay, and OUT2 has 40ns delay, etc. The maximum delay is 300ns from OUT0 to OUT15. The delay works during switch on and switch off of each output channel. These delays prevent large inrush currents which reduces the bypass capacitors when the outputs turn on. All OUTn channels of the TLC5940 can be switched off with one signal. When BLANK is set high, all OUTn channels are disabled, regardless of logic operations of the device. The grayscale counter is also reset. When BLANK is set low, all OUTn channels work under normal conditions. If BLANK goes low and then back high again in less than 300ns, all outputs programmed to turn on still turn on for either the programmed number of grayscale clocks, or the length of time that the BLANK signal was low, which ever is lower. For example, if all outputs are programmed to turn on for 1ms, but the BLANK signal is only low for 200ns, all outputs still turn on for 200ns, even though some outputs are turning on after the BLANK signal has already gone high. Table 3. BLANK Signal Truth Table BLANK OUT0 - OUT15 LOW Normal condition HIGH Disabled The maximum output current per channel is programmed by a single resistor, R(IREF), which is placed between IREF pin and GND pin. The voltage on IREF is set by an internal band gap V(IREF) with a typical value of 1.24V. The maximum channel current is equivalent to the current flowing through R(IREF) multiplied by a factor of 31.5. The maximum output current per channel can be calculated by Equation 6: where: V(IREF) = 1.24 V R(IREF) = User-selected external resistor. Imax must be set between 5 mA and 120 mA. The output current may be unstable if Imax is set lower than 5 mA. Output currents lower than 5 mA can be achieved by setting Imax to 5 mA or higher and then using dot correction. Figure 3 shows the maximum output current IO versus R(IREF). R(IREF) is the value of the resistor between IREF terminal to GND, and IO is the constant output current of OUT0 to OUT15. A variable power supply may be connected to the IREF pin through a resistor to change the maximum output current per channel. The maximum output current per channel is 31.5 times the current flowing out of the IREF pin. 14 Submit Documentation Feedback Copyright © 2004–2007, Texas Instruments Incorporated Product Folder Link(s): TLC5940 www.ti.com POWER DISSIPATION CALCULATION P = V x I + D CC CC V x I OUT MAX x DCn 63 x dPWM x N ( ) ( ) (7) OPERATING MODES SETTING DOT CORRECTION IOUTn Imax DCn 63 (8) TLC5940 SLVS515C–DECEMBER 2004–REVISED OCTOBER 2007 The device power dissipation must be below the power dissipation rating of the device package to ensure correct operation. Equation 7 calculates the power dissipation of device: where: VCC: device supply voltage ICC: device supply current VOUT: TLC5940 OUTn voltage when driving LED current IMAX: LED current adjusted by R(IREF) Resistor DCn: maximum dot correction value for OUTn N: number of OUTn driving LED at the same time dPWM: duty cycle defined by BLANK pin or GS PWM value The TLC5940 has operating modes depending on the signals DCPRG and VPRG. Table 4 shows the available operating modes. The TPS5940 GS operating mode (see Figure 11) and shift register values are not defined after power up. One solution to solve this is to set dot correction data after TLS5940 power-up and switch back to GS PWM mode. The other solution is to overflow the input shift register with 193 bits of dummy data and latch it while TLS540 is in GS PWM mode. The values in the input shift register, DC register and GS register are unknown just after power on. The DC and GS register values should be properly stored through the serial interface before starting the operation. Table 4. TLC5940 Operating Modes Truth Table SIGNAL INPUT SHIFT REGISTER MODE DC VALUE DCPRG VPRG L EEPROM GND 192 bit Grayscale PWM Mode H DC Register L EEPROM VCC 96 bit Dot Correction Data Input Mode H DC Register L EEPROM H V(VPRG) X EEPROM Programming Mode Write dc register value to EEPROM. (Default data: 3Fh) The TLC5940 has the capability to fine adjust the output current of each channel OUT0 to OUT15 independently. This is also called dot correction. This feature is used to adjust the brightness deviations of LEDs connected to the output channels OUT0 to OUT15. Each of the 16 channels can be programmed with a 6-bit word. The channel output can be adjusted in 64 steps from 0% to 100% of the maximum output current Imax. Dot correction for all channels must be entered at the same time. Equation 8 determines the output current for each output n: where: Imax = the maximum programmable output current for each output. DCn = the programmed dot correction value for output n (DCn = 0 to 63). n = 0 to 15 Copyright © 2004–2007, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Link(s): TLC5940 www.ti.com DC 0.0 0 DC 1.0 6 DC 15.0 90 DC 15.5 95 DC 0.5 5 DC 14.5 89 MSB LSB DC OUT15 DC OUT14 − DC OUT2 DC OUT0 tsu1 DC n MSB DC n MSB−1 DC n MSB−2 DC n LSB+1 DC n LSB DC n MSB DC n+1 MSB DC n+1 MSB−1 DC n MSB−1 DC n MSB−2 DC n−1 LSB DC n−1 LSB+1 DC n−1 MSB DC n−1 MSB−1 DC n−1 MSB−2 SCLK 1 2 3 95 96 1 2 SOUT SIN VPRG XLAT DC Mode Data Input Cycle n DC Mode Data Input Cycle n+1 VCC twh0 twl0 DC n−1 LSB twh2 th1 TLC5940 SLVS515C–DECEMBER 2004–REVISED OCTOBER 2007 Figure 14 shows the dot correction data packet format which consists of 6 bits x 16 channel, total 96 bits. The format is Big-Endian format. This means that the MSB is transmitted first, followed by the MSB-1, etc. The DC 15.5 in Figure 14 stands for the 5th most significant bit for output 15. Figure 14. Dot Correction Data Packet Format When VPRG is set to VCC, the TLC5940 enters the dot correction data input mode. The length of input shift register becomes 96 bits. After all serial data are shifted in, the TLC5940 writes the data in the input shift register to DC register when XLAT is high, and holds the data in the DC register when XLAT is low. The DC register is a level triggered latch of XLAT signal. Since XLAT is a level-triggered signal, SCLK and SIN must not be changed while XLAT is high. After XLAT goes low, data in the DC register is latched and does not change. BLANK signal does not need to be high to latch in new data. XLAT has setup time (tsu1) and hold time (th1) to SCLK as shown in Figure 15. Figure 15. Dot Correction Data Input Timing Chart The TLC5940 also has an EEPROM to store dot correction data. To store data from the dot correction register to EEPROM, DCPRG is set to high after applying VPRG to the VPRG pin. Figure 16 shows the EEPROM programming timings. The EEPROM has a default value of all 1s. 16 Submit Documentation Feedback Copyright © 2004–2007, Texas Instruments Incorporated Product Folder Link(s): TLC5940 www.ti.com VPRG DCPRG XLAT SIN SCLK SOUT 1 96 DC MSB - DC MSB DC LSB VCC V(PRG) t su6 tprog th5 DCPRG OUT0 (Current) tpd5 tpd5 OUT15 (Current) SETTING GRAYSCALE Brightness in % GSn 4095 100 (9) GS 0.0 0 GS 1.0 12 GS 15.0 180 GS 15.11 191 GS 0.11 11 GS 14.11 179 MSB LSB GS OUT15 GS OUT14 − GS OUT2 GS OUT0 TLC5940 SLVS515C–DECEMBER 2004–REVISED OCTOBER 2007 Figure 16. EEPROM Programming Timing Chart Figure 17. DCPRG and OUTn Timing Diagram The TLC5940 can adjust the brightness of each channel OUTn using a PWM control scheme. The use of 12 bits per channel results in 4096 different brightness steps, respective 0% to 100% brightness. Equation 9 determines the brightness level for each output n: where: GSn = the programmed grayscale value for output n (GSn = 0 to 4095) n = 0 to 15 Grayscale data for all OUTn Figure 18 shows the grayscale data packet format which consists of 12 bits x 16 channels, totaling 192 bits. The format is Big-Endian format. This means that the MSB is transmitted first, followed by the MSB-1, etc. Figure 18. Grayscale Data Packet Format When VPRG is set to GND, the TLC5940 enters the grayscale data input mode. The device switches the input shift register to 192-bit width. After all data is clocked in, a rising edge of the XLAT signal latches the data into Copyright © 2004–2007, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Link(s): TLC5940 www.ti.com STATUS INFORMATION OUTPUT LOD 15 X DC 15.5 DC 0.0 X X 0 23 LOD Data DC Values Reserved MSB LSB 24 119 120 TEF LOD 0 TEF 16 X 15 191 TLC5940 SLVS515C–DECEMBER 2004–REVISED OCTOBER 2007 the grayscale register (see Figure 11). New grayscale data immediately becomes valid at the rising edge of the XLAT signal; therefore, new grayscale data should be latched at the end of a grayscale cycle when BLANK is high.The first GS data input cycle after dot correction requires an additional SCLK pulse after the XLAT signal to complete the grayscale update cycle. All GS data in the input shift register is replaced with status information data (SID) after updated the grayscale register. The TLC5940 does have a status information register, which can be accessed in grayscale mode (VPRG=GND). After the XLAT signal latches the data into the GS register the input shift register data will be replaced with status information data (SID) of the device (see Figure 18). LOD, TEF, and dot correction EEPROM data (DCPRG=LOW) or dot correction register data (DCPRG=HIGH) can be read out at SOUT pin. The status information data packet is 192 bits wide. Bits 0-15 contain the LOD status of each channel. Bit 16 contains the TEF status. If DCPRG is low, bits 24-119 contain the data of the dot-correction EEPROM. If DCPRG is high, bits 24-119 contain the data of the dot-correction register.The remaining bits are reserved. The complete status information data packet is shown in Figure 19. SOUT outputs the MSB of the SID at the same time the SID are stored in the SID register, as shown Figure 20. The next SCLK pulse, which will be the clock for receiving the SMB of the next grayscale data, transmits MSB-1 of SID. If output voltage is < 0.3 V (typical) when the output sink current turns on, LOD status flage becomes active. The LOD status flag is an internal signal that pulls XERR pin down to low when the LOD status flag becomes active. The delay time, tpd2 (1 µs maximum), is from the time of turning on the output sink current to the time LOD status flage becomes valid. The timing for each channel's LOD status to become valid is shifted by the 30-ns (maximum) channel-to-channel turn-on time. After the first GSCLK goes high, OUT0 LOD status is valid; tpd3 + tpd2 = 60 ns + 1 µs. OUT1 LOD status is valid; tpd3 + td + tpd2 = 60 ns + 30 ns + 1 µs = 1.09 µs. OUT2 LOD status is valid; tpd3 + 2*td + tpd2 = 1.12 µs, and so on. It takes 1.51 µs maximum (tpd3 + 15*td + tpd2) from the first GSCLK rising edge until all LOD become valid; tsuLOD must be > 1.51 µs (see Figure 20) to ensure that all LOD data are valid. Figure 19. Status Information Data Packet Format 18 Submit Documentation Feedback Copyright © 2004–2007, Texas Instruments Incorporated Product Folder Link(s): TLC5940 www.ti.com VPRG XLAT SIN SCLK SOUT BLANK GSCLK OUT0 (current) OUT1 (current) OUT15 (current) XERR 1 192 193 1 192 1 4096 GS1 MSB GS1 LSB GS1 MSB GS2 MSB GS2 LSB GS2 MSB SID1 MSB SID1 MSB-1 SID1 LSB - - t + 15 x t + t pd3 d pd2 tpd3 td 15 x td tpd2 GS Data Input Mode 1st GS Data Input Cycle 2nd GS Data Input Cycle (1st GS Data Output Cycle) t suLOD > tpd4 + 15 x td + tpd3 GRAYSCALE PWM OPERATION TLC5940 SLVS515C–DECEMBER 2004–REVISED OCTOBER 2007 Figure 20. Readout Status Information Data (SID) Timing Chart The grayscale PWM cycle starts with the falling edge of BLANK. The first GSCLK pulse after BLANK goes low increases the grayscale counter by one and switches on all OUTn with grayscale value not zero. Each following rising edge of GSCLK increases the grayscale counter by one. The TLC5940 compares the grayscale value of each output OUTn with the grayscale counter value. All OUTn with grayscale values equal to the counter values are switched off. A BLANK=H signal after 4096 GSCLK pulses resets the grayscale counter to zero and completes the grayscale PWM cycle (see Figure 21). When the counter reaches a count of FFFh, the counter stops counting and all outputs turn off. Pulling BLANK high before the counter reaches FFFh immediately resets the counter to zero. Copyright © 2004–2007, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Link(s): TLC5940 www.ti.com GSCLK BLANK GS PWM Cycle n 1 2 3 1 GS PWM Cycle n+1 OUT0 OUT1 OUT15 XERR n x t d tpd1 tpd1 + td tpd1 + 15 x td tpd2 tpd3 twh1 twl1 twl1 tpd3 4096 th4 twh3 tpd3+ n x td tsu4 (Current) (Current) (Current) SERIAL DATA TRANSFER RATE f (GSCLK) 4096 f (update) f (SCLK) 193 f (update) n (10) TLC5940 SLVS515C–DECEMBER 2004–REVISED OCTOBER 2007 Figure 21. Grayscale PWM Cycle Timing Chart Figure 22 shows a cascading connection of n TLC5940 devices connected to a controller, building a basic module of an LED display system. The maximum number of cascading TLC5940 devices depends on the application system and is in the range of 40 devices. Equation 10 calculates the minimum frequency needed: where: f (GSCLK): minimum frequency needed for GSCLK f (SCLK): minimum frequency needed for SCLK and SIN f (update): update rate of whole cascading system n: number cascaded of TLC5940 device 20 Submit Documentation Feedback Copyright © 2004–2007, Texas Instruments Incorporated Product Folder Link(s): TLC5940 www.ti.com APPLICATION EXAMPLE TLC5940 SIN SOUT OUT0 OUT15 SCLK GSCLK XLAT VPRG BLANK IREF XERR DCPRG TLC5940 SIN SOUT OUT0 OUT15 SCLK GSCLK XLAT VPRG BLANK IREF XERR DCPRG IC 0 IC n 7 SIN SCLK GSCLK XLAT BLANK XERR DCPRG Controller SOUT VPRG_D VPRG_OE W_EEPROM 100 k 50 k 50 k 50 k 50 k 50 k 50 k VPRG 100 nF VCC V(LED) V(LED) V(LED) V(LED) 100 nF V(22V) V(22V) VCC VCC TLC5940 SLVS515C–DECEMBER 2004–REVISED OCTOBER 2007 Figure 22. Cascading Devices Copyright © 2004–2007, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Link(s): TLC5940 PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TLC5940NT ACTIVE PDIP NT 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 TLC5940NT TLC5940NTG4 ACTIVE PDIP NT 28 13 Green (RoHS & no Sb/Br) CU NIPDAU N / A for Pkg Type -40 to 85 TLC5940NT TLC5940PWP ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC5940 TLC5940PWPG4 ACTIVE HTSSOP PWP 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC5940 TLC5940PWPR ACTIVE HTSSOP PWP 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC5940 TLC5940PWPRG4 ACTIVE HTSSOP PWP 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC5940 TLC5940RHBR ACTIVE VQFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC 5940 TLC5940RHBRG4 ACTIVE VQFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC 5940 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2013 Addendum-Page 2 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. 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OTHER QUALIFIED VERSIONS OF TLC5940 : • Enhanced Product: TLC5940-EP NOTE: Qualified Version Definitions: • Enhanced Product - Supports Defense, Aerospace and Medical Applications TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant TLC5940RHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC5940RHBR VQFN RHB 32 3000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated LC Filter Left LC Filter Right 4.5 V-26 V PSU Tuner AM/FM CD/ MP3 Aux in Left Right Audio Processor And control TPA3116D2 AM/FM Avoidance Control FAULTZ SDZ MUTE Capable of synchronizing to other devices Sync GAIN control and Master /Slave setting GAIN/SLV AM2,1,0 Power Limit PLIMIT PBTL Detect Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TPA3116D2, TPA3118D2, TPA3130D2 SLOS708D –APRIL 2012–REVISED JANUARY 2015 TPA3116D2 15-W, 30-W, 50-W Filter-Free Class-D Stereo Amplifier Family With AM Avoidance 1 Features 3 Description The TPA31xxD2 series are stereo efficient, digital 1• Supports Multiple Output Configurations amplifier power stage for driving speakers up to 100 – 2 × 50 W Into a 4-Ω BTL Load at 21 V W / 2 Ω in mono. The high efficiency of the (TPA3116D2) TPA3130D2 allows it to do 2 × 15 W without external – 2 × 30 W Into a 8-Ω BTL Load at 24 V heat sink on a single layer PCB. The TPA3118D2 can (TPA3118D2) even run 2 × 30 W / 8 Ω without heat sink on a dual layer PCB. If even higher power is needed the – 2 × 15 W Into a 8-Ω BTL Load at 15 V TPA3116D2 does 2 × 50 W / 4 Ω with a small heat- (TPA3130D2) sink attached to its top side PowerPAD. All three • Wide Voltage Range: 4.5 V to 26 V devices share the same footprint enabling a single • Efficient Class-D Operation PCB to be used across different power levels. – >90% Power Efficiency Combined With Low The TPA31xxD2 advanced oscillator/PLL circuit Idle Loss Greatly Reduces Heat Sink Size employs a multiple switching frequency option to – Advanced Modulation Schemes avoid AM interferences; this is achieved together with an option of either master or slave option, making it • Multiple Switching Frequencies possible to synchronize multiple devices. – AM Avoidance The TPA31xxD2 devices are fully protected against – Master and Slave Synchronization faults with short-circuit protection and thermal – Up to 1.2-MHz Switching Frequency protection as well as overvoltage, undervoltage, and • Feedback Power-Stage Architecture With High DC protection. Faults are reported back to the PSRR Reduces PSU Requirements processor to prevent devices from being damaged during overload conditions. • Programmable Power Limit • Differential and Single-Ended Inputs Device Information(1) • Stereo and Mono Mode With Single-Filter Mono PART NUMBER PACKAGE BODY SIZE (NOM) Configuration DAD (32) TPA3116D2 11.00 mm × 6.20 mm DAP (32) • Single Power Supply Reduces Component Count TPA3118D2 • Integrated Self-Protection Circuits Including DAP (32) 11.00 mm × 6.20 mm TPA3130D2 Overvoltage, Undervoltage, Overtemperature, DC- (1) For all available packages, see the orderable addendum at Detect, and Short Circuit With Error Reporting the end of the datasheet. • Thermally Enhanced Packages – DAD Simplified Application Circuit (32-Pin HTSSOP Pad Up) – DAP (32-Pin HTSSOP Pad Down) • –40°C to 85°C Ambient Temperature Range 2 Applications • Mini-Micro Component, Speaker Bar, Docks • After-Market Automotive • CRT TV • Consumer Audio Applications 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPA3116D2, TPA3118D2, TPA3130D2 SLOS708D –APRIL 2012–REVISED JANUARY 2015 www.ti.com Table of Contents 1 Features.................................................................. 1 7.3 Feature Description................................................. 13 2 Applications ........................................................... 1 7.4 Device Functional Modes........................................ 24 3 Description ............................................................. 1 8 Applications and Implementation ...................... 25 8.1 Application Information............................................ 25 4 Revision History..................................................... 2 8.2 Typical Application .................................................. 25 5 Pin Configuration and Functions......................... 3 9 Power Supply Recommendations...................... 28 6 Specifications......................................................... 5 10 Layout................................................................... 28 6.1 Absolute Maximum Ratings ...................................... 5 10.1 Layout Guidelines ................................................. 28 6.2 ESD Ratings ............................................................ 5 10.2 Layout Example .................................................... 29 6.3 Recommended Operating Conditions....................... 5 10.3 Heat Sink Used on the EVM ................................. 31 6.4 Thermal Information.................................................. 6 6.5 DC Electrical Characteristics .................................... 6 11 Device and Documentation Support ................. 32 6.6 AC Electrical Characteristics..................................... 6 11.1 Related Links ........................................................ 32 6.7 Typical Characteristics .............................................. 8 11.2 Trademarks ........................................................... 32 11.3 Electrostatic Discharge Caution............................ 32 7 Detailed Description ............................................ 13 11.4 Glossary ................................................................ 32 7.1 Overview ................................................................. 13 7.2 Functional Block Diagram ....................................... 13 12 Mechanical, Packaging, and Orderable Information ........................................................... 32 4 Revision History Changes from Revision C (April 2012) to Revision D Page • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Changes from Revision B (May 2012) to Revision C Page • Changed Notes 2 and 3 of the Thermal Information Table.................................................................................................... 6 • Changed the Gain (BTL) Test Condition values for R1 and R2............................................................................................. 6 • Changed the Gain (SLV) Test Condition values for R1 and R2............................................................................................. 6 • Changed the SYSTEM BLOCK DIAGRAM .......................................................................................................................... 13 2 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 32 31 30 29 19 13 14 15 16 17 18 20 1 2 3 4 5 6 7 8 9 10 11 12 21 22 23 24 28 27 26 25 FAULTZ SDZ SYNC AM0 AM1 MUTE LINN LINP PLIMIT RINN GVDD RINP AVCC OUTPR PVCC BSPL GND OUTPL PVCC OUTNL BSNL PVCC OUTNR BSNR MODSEL BSPR GND GND PVCC GND GAIN/SLV AM2 Thermal PAD 32 31 30 29 19 13 14 15 16 17 18 20 1 2 3 4 5 6 7 8 9 10 11 12 21 22 23 24 28 27 26 25 FAULTZ SDZ SYNC AM0 AM1 MUTE LINN LINP PLIMIT RINN GVDD RINP AVCC OUTPR PVCC BSPL GND OUTPL PVCC OUTNL BSNL PVCC OUTNR BSNR MODSEL BSPR GND GND PVCC GND GAIN/SLV AM2 Thermal PAD TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708D –APRIL 2012–REVISED JANUARY 2015 5 Pin Configuration and Functions DAD Package 32-Pin HTSSOP With PowerPAD Up TPA3116D2 Only, Top View DAP Package 32-Pin HTSSOP With PowerPAD Down Top View Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 SLOS708D –APRIL 2012–REVISED JANUARY 2015 www.ti.com Pin Functions PIN TYPE(1) DESCRIPTION NO. NAME 1 MODSEL I Mode selection logic input (LOW = BD mode, HIGH = 1 SPW mode). TTL logic levels with compliance to AVCC. 2 SDZ I Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with compliance to AVCC. 3 FAULTZ DO General fault reporting including Over-temp, DC Detect. Open drain. FAULTZ = High, normal operation FAULTZ = Low, fault condition 4 RINP I Positive audio input for right channel. Biased at 3 V. 5 RINN I Negative audio input for right channel. Biased at 3 V. 6 PLIMIT I Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. Connect directly to GVDD for no power limit. 7 GVDD PO Internally generated gate voltage supply. Not to be used as a supply or connected to any component other than a 1 µF X7R ceramic decoupling capacitor and the PLIMIT and GAIN/SLV resistor dividers. 8 GAIN/SLV I Selects Gain and selects between Master and Slave mode depending on pin voltage divider. 9 GND G Ground 10 LINP I Positive audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode. 11 LINN I Negative audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode. 12 MUTE I Mute signal for fast disable/enable of outputs (HIGH = outputs Hi-Z, LOW = outputs enabled). TTL logic levels with compliance to AVCC. 13 AM2 I AM Avoidance Frequency Selection 14 AM1 I AM Avoidance Frequency Selection 15 AM0 I AM Avoidance Frequency Selection 16 SYNC DIO Clock input/output for synchronizing multiple class-D devices. Direction determined by GAIN/SLV terminal. 17 AVCC P Analog Supply 18 PVCC P Power supply 19 PVCC P Power supply 20 BSNL BST Boot strap for negative left channel output, connect to 220 nF X5R, or better ceramic cap to OUTPL 21 OUTNL PO Negative left channel output 22 GND G Ground 23 OUTPL PO Positive left channel output 24 BSPL BST Boot strap for positive left channel output, connect to 220 nF X5R, or better ceramic cap to OUTNL 25 GND G Ground 26 BSNR BST Boot strap for negative right channel output, connect to 220 nF X5R, or better ceramic cap to OUTNR 27 OUTNR PO Negative right channel output 28 GND G Ground 29 OUTPR PO Positive right channel output 30 BSPR BST Boot strap for positive right channel output, connect to 220 nF X5R or better ceramic cap to OUTPR 31 PVCC P Power supply 32 PVCC P Power supply 33 PowerPAD G Connect to GND for best system performance. If not connected to GND, leave floating. (1) TYPE: DO = Digital Output, I = Analog Input, G = General Ground, PO = Power Output, BST = Boot Strap. 4 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708D –APRIL 2012–REVISED JANUARY 2015 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage, VCC PVCC, AVCC –0.3 30 V INPL, INNL, INPR, INNR –0.3 6.3 V Input voltage, VI PLIMIT, GAIN / SLV, SYNC –0.3 GVDD+0.3 V AM0, AM1, AM2, MUTE, SDZ, MODSEL –0.3 PVCC+0.3 V Slew rate, maximum(2) AM0, AM1, AM2, MUTE, SDZ, MODSEL 10 V/ms Operating free-air temperature, TA –40 85 °C Operating junction temperature , TJ –40 150 °C Storage temperature, Tstg –40 125 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) 100 kΩ series resistor is needed if maximum slew rate is exceeded. 6.2 ESD Ratings VALUE UNIT Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- ±500 V C101(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. . 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VCC Supply voltage PVCC, AVCC 4.5 26 V High-level input VIH AM0, AM1, AM2, MUTE, SDZ, SYNC, MODSEL 2 V voltage Low-level input VIL AM0, AM1, AM2, MUTE, SDZ, SYNC, MODSEL 0.8 V voltage Low-level output VOL FAULTZ, RPULL-UP = 100 kΩ, PVCC = 26 V 0.8 V voltage High-level input IIH AM0, AM1, AM2, MUTE, SDZ, MODSEL (VI = 2 V, VCC = 18 V) 50 µA current TPA3116D2, TPA3118D2 3.2 4 RL(BTL) Output filter: L = 10 µH, C = 680 nF Minimum load TPA3130D2 5.6 8 Ω Impedance TPA3116D2, TPA3118D2 1.6 RL(PBTL) Output filter: L = 10 µH, C = 1 µF TPA3130D2 3.2 4 Output-filter Lo Minimum output filter inductance under short-circuit condition 1 µH Inductance Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 SLOS708D –APRIL 2012–REVISED JANUARY 2015 www.ti.com 6.4 Thermal Information TPA3130D2 TPA3118D2 TPA3116D2 THERMAL METRIC(1) DAP(2) DAP(3) DAD(4) UNIT 32 PINS 32 PINS 32 PINS RθJA Junction-to-ambient thermal resistance 36 22 14 ψJT Junction-to-top characterization parameter 0.4 0.3 1.2 °C/W ψJB Junction-to-board characterization parameter 5.9 4.7 5.7 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) For the PCB layout please see the TPA3130D2EVM user guide. (3) For the PCB layout please see the TPA3118D2EVM user guide. (4) The heat sink drawing used for the thermal model data are shown in the application section, size: 14mm wide, 50mm long, 25mm high. 6.5 DC Electrical Characteristics TA = 25°C, AVCC = PVCC = 12 V to 24 V, RL = 4 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Class-D output offset voltage (measured | VOS | VI = 0 V, Gain = 36 dB 1.5 15 mV differentially) SDZ = 2 V, No load or filter, PVCC = 12 V 20 35 ICC Quiescent supply current mA SDZ = 2 V, No load or filter, PVCC = 24 V 32 50 Quiescent supply current in shutdown SDZ = 0.8 V, No load or filter, PVCC = 12 V <50 ICC(SD) µA mode SDZ = 0.8 V, No load or filter, PVCC = 24 V 50 400 Drain-source on-state resistance, rDS(on) PVCC = 21 V, Iout = 500 mA, TJ = 25°C 120 mΩ measured pin to pin R1 = 5.6 kΩ, R2 = Open 19 20 21 dB R1 = 20 kΩ, R2 = 100 kΩ 25 26 27 G Gain (BTL) R1 = 39 kΩ, R2 = 100 kΩ 31 32 33 dB R1 = 47 kΩ, R2 = 75 kΩ 35 36 37 R1 = 51 kΩ, R2 = 51 kΩ 19 20 21 dB R1 = 75 kΩ, R2 = 47 kΩ 25 26 27 G Gain (SLV) R1 = 100 kΩ, R2 = 39 kΩ 31 32 33 dB R1 = 100 kΩ, R2 = 16 kΩ 35 36 37 ton Turn-on time SDZ = 2 V 10 ms tOFF Turn-off time SDZ = 0.8 V 2 µs GVDD Gate drive supply IGVDD < 200 µA 6.4 6.9 7.4 V Output voltage maximum under PLIMIT VO V(PLIMIT) = 2 V; VI = 1 Vrms 6.75 7.90 8.75 V control 6.6 AC Electrical Characteristics TA = 25°C, AVCC = PVCC = 12 V to 24 V, RL = 4 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 200 mVPP ripple at 1 kHz, Gain = 20 dB, Inputs AC- KSVR Power supply ripple rejection –70 dB coupled to GND THD+N = 10%, f = 1 kHz, PVCC = 14.4 V 25 PO Continuous output power W THD+N = 10%, f = 1 kHz, PVCC = 21 V 50 THD+N Total harmonic distortion + noise VCC = 21 V, f = 1 kHz, PO = 25 W (half-power) 0.1% 65 µV Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB –80 dBV Crosstalk VO = 1 Vrms, Gain = 20 dB, f = 1 kHz –100 dB Maximum output at THD+N < 1%, f = 1 kHz, Gain = 20 dB, SNR Signal-to-noise ratio 102 dB A-weighted 6 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708D –APRIL 2012–REVISED JANUARY 2015 AC Electrical Characteristics (continued) TA = 25°C, AVCC = PVCC = 12 V to 24 V, RL = 4 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AM2=0, AM1=0, AM0=0 376 400 424 AM2=0, AM1=0, AM0=1 470 500 530 AM2=0, AM1=1, AM0=0 564 600 636 AM2=0, AM1=1, AM0=1 940 1000 1060 fOSC Oscillator frequency kHz AM2=1, AM1=0, AM0=0 1128 1200 1278 AM2=1, AM1=0, AM0=1 AM2=1, AM1=1, AM0=0 Reserved AM2=1, AM1=1, AM0=1 Thermal trip point 150+ °C Thermal hysteresis 15 °C TPA3130D2 4.5 Over current trip point A TPA3118D2, TPA3116D2 7.5 Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 0.001 0.01 0.1 1 10 20 100 1k 10k 20k Frequency (Hz) THD+N (%) PO = 1W PO = 5W PO = 10W Gain = 26dB PVCC = 24V TA = 25°C RL = 8Ω G006 0.001 0.01 0.1 1 10 0.01 0.1 1 10 Output Power (W) THD+N (%) f = 20Hz f = 1kHz f = 6kHz Gain = 26dB PVCC = 6V TA = 25°C RL = 4Ω G008 0.001 0.01 0.1 1 10 20 100 1k 10k 20k Frequency (Hz) THD+N (%) PO = 1W PO = 5W PO = 10W Gain = 26dB PVCC = 24V TA = 25°C RL = 4Ω G004 0.001 0.01 0.1 1 10 20 100 1k 10k 20k Frequency (Hz) THD+N (%) PO = 1W PO = 2.5W PO = 5W Gain = 26dB PVCC = 12V TA = 25°C RL = 8Ω G005 0.001 0.01 0.1 1 10 20 100 1k 10k 20k Frequency (Hz) THD+N (%) PO = 0.5W PO = 1W PO = 2.5W Gain = 26dB PVCC = 6V TA = 25°C RL = 4Ω G002 0.001 0.01 0.1 1 10 20 100 1k 10k 20k Frequency (Hz) THD+N (%) PO = 1W PO = 2.5W PO = 5W Gain = 26dB PVCC = 12V TA = 25°C RL = 4Ω G003 TPA3116D2, TPA3118D2, TPA3130D2 SLOS708D –APRIL 2012–REVISED JANUARY 2015 www.ti.com 6.7 Typical Characteristics fs = 400 kHz, BD Mode (unless otherwise noted) Figure 1. Total Harmonic Distortion + Noise (BTL) vs Figure 2. Total Harmonic Distortion + Noise (BTL) vs Frequency Frequency Figure 3. Total Harmonic Distortion + Noise (BTL) vs Figure 4. Total Harmonic Distortion + Noise (BTL) vs Frequency Frequency Figure 5. Total Harmonic Distortion + Noise (BTL) vs Figure 6. Total Harmonic Distortion + Noise (BTL) vs Output Frequency Power 8 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 0 10 20 30 40 50 0 1 2 3 4 PLIMIT Voltage (V) Output Power (W) Gain = 26dB TA = 25°C PVCC = 24V RL = 4Ω G013 20 100 1k 10k 100k −50 −40 −30 −20 −10 0 10 20 30 −500 −400 −300 −200 −100 0 100 200 300 Frequency (Hz) Gain (dB) Phase (°) Gain Phase Gain = 26dB PVCC = 12V TA = 25°C RL = 4Ω G014 0.001 0.01 0.1 1 10 0.01 0.1 1 10 50 Output Power (W) THD+N (%) f = 20Hz f = 1kHz f = 6kHz Gain = 26dB PVCC = 12V TA = 25°C RL = 8Ω G011 0.001 0.01 0.1 1 10 0.01 0.1 1 10 50 Output Power (W) THD+N (%) f = 20Hz f = 1kHz f = 6kHz Gain = 26dB PVCC = 24V TA = 25°C RL = 8Ω G012 0.001 0.01 0.1 1 10 0.01 0.1 1 10 40 Output Power (W) THD+N (%) f = 20Hz f = 1kHz f = 6kHz Gain = 26dB PVCC = 12V TA = 25°C RL = 4Ω G009 0.001 0.01 0.1 1 10 0.01 0.1 1 10 100 Output Power (W) THD+N (%) f = 20Hz f = 1kHz f = 6kHz Gain = 26dB PVCC = 24V TA = 25°C RL = 4Ω G010 TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708D –APRIL 2012–REVISED JANUARY 2015 Typical Characteristics (continued) fs = 400 kHz, BD Mode (unless otherwise noted) Figure 7. Total Harmonic Distortion + Noise (BTL) vs Output Figure 8. Total Harmonic Distortion + Noise (BTL) vs Output Power Power Figure 9. Total Harmonic Distortion + Noise (BTL) vs Output Figure 10. Total Harmonic Distortion + Noise (BTL) vs Power Output Power Figure 11. Output Power (BTL) vs Plimit Voltage Figure 12. Gain/Phase (BTL) vs Frequency Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 −140 −130 −120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 20 100 1k 10k 20k Frequency (Hz) Crosstalk (dB) Right to Left Left to Right Gain = 26dB PVCC = 24V TA = 25°C RL = 8Ω G021 −140 −130 −120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 20 100 1k 10k 20k Frequency (Hz) Crosstalk (dB) Right to Left Left to Right Gain = 26dB PVCC = 12V TA = 25°C RL = 4Ω G022 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 35 40 45 50 Output Power (W) Power Efficiency (%) PVCC = 6V PVCC =12V PVCC = 24V Gain = 26dB TA = 25°C RL = 8Ω G017 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 35 40 45 50 Output Power (W) Power Efficiency (%) PVCC = 6V PVCC = 12V PVCC = 24V Gain = 26dB TA = 25°C RL = 4Ω G018 0 5 10 15 20 25 30 35 40 45 50 4 6 8 10 12 14 16 18 20 22 24 26 Supply Voltage (V) Maximum Output Power (W) THD+N = 1% THD+N = 10% Gain = 26dB TA = 25°C RL = 8Ω G015 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 4 6 8 10 12 14 16 18 20 22 24 26 Supply Voltage (V) Maximum Output Power (W) THD+N = 1% THD+N = 10% Gain = 26dB TA = 25°C RL = 4Ω G016 TPA3116D2, TPA3118D2, TPA3130D2 SLOS708D –APRIL 2012–REVISED JANUARY 2015 www.ti.com Typical Characteristics (continued) fs = 400 kHz, BD Mode (unless otherwise noted) Figure 13. Maximum Output Power (BTL) vs Supply Voltage Figure 14. Maximum Output Power (BTL) vs Supply Voltage Figure 15. Power Efficiency (BTL) vs Output Power Figure 16. Power Efficiency (BTL) vs Output Power Figure 17. Crosstalk vs Frequency Figure 18. Crosstalk vs Frequency 10 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 Output Power (W) Power Efficiency (%) PVCC = 6V PVCC = 12V PVCC =24V Gain = 26dB TA = 25°C RL = 2Ω G028 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 20 100 1k 10k 20k Frequency (Hz) kSVR (dB) Gain = 26dB PVCC = 12VDC + 200mVP-P TA = 25°C RL = 2Ω G030 0.001 0.01 0.1 1 10 0.01 0.1 1 10 40 Output Power (W) THD+N (%) f = 20Hz f = 1kHz f = 6kHz Gain = 26dB PVCC = 12V TA = 25°C RL = 2Ω G025 0 20 40 60 80 100 120 140 160 180 4 6 8 10 12 14 16 18 20 22 24 26 Supply Voltage (V) Maximum Output Power (W) THD+N = 1% THD+N = 10% Gain = 26dB TA = 25°C RL = 2Ω G027 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 20 100 1k 10k 20k Frequency (Hz) kSVR (dB) Left Channel Right Channel Gain = 26dB PVCC = 12VDC + 200mVP-P TA = 25°C RL = 8Ω G023 0.001 0.01 0.1 1 10 20 100 1k 10k 20k Frequency (Hz) THD+N (%) PO = 1W PO = 5W PO = 10W Gain = 26dB PVCC = 12V TA = 25°C RL = 2Ω G024 TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708D –APRIL 2012–REVISED JANUARY 2015 Typical Characteristics (continued) fs = 400 kHz, BD Mode (unless otherwise noted) Figure 19. Supply Ripple Rejection Ratio (BTL) vs Figure 20. Total Harmonic Distortion + Noise (PBTL) vs Frequency Frequency Figure 21. Total Harmonic Distortion + Noise (PBTL) vs Figure 22. Maximum Output Power (PBTL) vs Supply Output Power Voltage Figure 23. Power Efficiency (PBTL) vs Output Power Figure 24. Supply Ripple Rejection Ratio (PBTL) vs Frequency Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 0.001 0.01 0.1 1 10 0.01 0.1 1 10 100 200 Output Power (W) THD+N (%) f = 20Hz f = 1kHz f = 6kHz Gain = 26dB PVCC = 24V TA = 25°C RL = 3Ω G032 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 4 6 8 10 12 14 16 18 20 22 24 26 Supply Voltage (V) Maximum Output Power (W) THD+N = 1% THD+N = 10% Gain = 26dB TA = 25°C RL = 3Ω G034 TPA3116D2, TPA3118D2, TPA3130D2 SLOS708D –APRIL 2012–REVISED JANUARY 2015 www.ti.com Typical Characteristics (continued) fs = 400 kHz, BD Mode (unless otherwise noted) Figure 25. Total Harmonic Distortion + Noise (PBTL) vs Figure 26. Maximum Output Power (PBTL) vs Supply Output Power Voltage 12 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 + – + – + – + + SDZ MUTE TTL Buffer Gain Control GAIN OUTPR_FB RINP RINN Gain Control OUTPNR_FB FAULTZ SYNC GAIN/SLV AM<2:0> PLIMIT AVCC GVDD LDO Regulator LINP LINN GND Input Sense PBTL Select OUTPL_FB Gain Control OUTNL_FB AVDD GVDD PLIMIT Reference Ramp Generator Biases and References Startup Protection Logic SC Detect DC Detect Thermal Detect UVLO/OVLO PVCC GVDD PVCC Gate Drive OUTNL_ FB PVCC GVDD PVCC Gate Drive PWM Logic Modulation and PBTL Select OUTPL_FB GND OUTPL BSPL GND OUTNL BSNL GND BSNR OUTPR GND OUTNR OUTNR_ FB BSPR OUTPR_FB PVCC GVDD PVCC Gate Drive PVCC GVDD PVCC Gate Drive PWM Logic Modulation and PBTL Select PLIMIT PLIMIT + – + – + – + – + – + – – – Thermal Pad + – PVCC PVCC TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708D –APRIL 2012–REVISED JANUARY 2015 7 Detailed Description 7.1 Overview The TPA31xxD2 device is a highly efficient Class D audio amplifier with integrated 120m Ohms MOSFET that allows output currents up to 7.5 A. The high efficiency allows the amplifier to provide an excellent audio performance without the need for a bulky heat sink. The device can be configured for either master or slave operation by using the SYNC pin. This helps to prevent audible beats noise. 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Gain Setting and Master and Slave The gain of the TPA31xxD2 family is set by the voltage divider connected to the GAIN/SLV control pin. Master or Slave mode is also controlled by the same pin. An internal ADC is used to detect the 8 input states. The first four stages sets the GAIN in Master mode in gains of 20, 26, 32, 36 dB respectively, while the next four stages sets the GAIN in Slave mode in gains of 20, 26, 32, 36 dB respectively. The gain setting is latched during power-up and cannot be changed while device is powered. Table 1 lists the recommended resistor values and the state and gain: Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 i i 1 f 2 Z C p ƒ = 5 6 7 8 9 10 INNR PLIMIT GVDD GAIN/SLV GND 2 1 C5 1 Fµ 2 1 2 1 R1 51 k R2 51 k TPA3116D2, TPA3118D2, TPA3130D2 SLOS708D –APRIL 2012–REVISED JANUARY 2015 www.ti.com Table 1. Gain and Master/Slave MASTER / SLAVE GAIN R1 (to GND)(1) R2 (to GVDD)(1) INPUT IMPEDANCE MODE Master 20 dB 5.6 kΩ OPEN 60 kΩ Master 26 dB 20 kΩ 100 kΩ 30 kΩ Master 32 dB 39 kΩ 100 kΩ 15 kΩ Master 36 dB 47 kΩ 75 kΩ 9 kΩ Slave 20 dB 51 kΩ 51 kΩ 60 kΩ Slave 26 dB 75 kΩ 47 kΩ 30 kΩ Slave 32 dB 100 kΩ 39 kΩ 15 kΩ Slave 36 dB 100 kΩ 16 kΩ 9 kΩ (1) Resistor tolerance should be 5% or better. Figure 27. Gain, Master/Slave In Master mode, SYNC terminal is an output, in Slave mode, SYNC terminal is an input for a clock input. TTL logic levels with compliance to GVDD. 7.3.2 Input Impedance The TPA31xxD2 family input stage is a fully differential input stage and the input impedance changes with the gain setting from 9 kΩ at 36 dB gain to 60 kΩ at 20 dB gain. Table 1 lists the values from min to max gain. The tolerance of the input resistor value is ±20% so the minimum value will be higher than 7.2 kΩ. The inputs need to be AC-coupled to minimize the output dc-offset and ensure correct ramping of the output voltages during powerON and power-OFF. The input ac-coupling capacitor together with the input impedance forms a high-pass filter with the following cut-off frequency: (1) If a flat bass response is required down to 20 Hz the recommended cut-off frequency is a tenth of that, 2 Hz. Table 2 lists the recommended ac-couplings capacitors for each gain step. If a -3 dB is accepted at 20 Hz 10 times lower capacitors can used – for example, a 1 µF can be used. Table 2. Recommended Input AC-Coupling Capacitors GAIN INPUT IMPEDANCE INPUT CAPACITANCE HIGH-PASS FILTER 20 dB 60 kΩ 1.5 µF 1.8 Hz 26 dB 30 kΩ 3.3 µF 1.6 Hz 32 dB 15 kΩ 5.6 µF 2.3 Hz 36 dB 9 kΩ 10 µF 1.8 Hz 14 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 Input Signal Ci IN Zi Zf TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708D –APRIL 2012–REVISED JANUARY 2015 Figure 28. Input Impedance The input capacitors used should be a type with low leakage, like quality electrolytic, tantalum or ceramic. If a polarized type is used the positive connection should face the input pins which are biased to 3 Vdc. 7.3.3 Startup and Shutdown Operation The TPA31xxD2 family employs a shutdown mode of operation designed to reduce supply current (Icc) to the absolute minimum level during periods of nonuse for power conservation. The SDZ input terminal should be held high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling SDZ low will put the outputs to mute and the amplifier to enter a low-current state. It is not recommended to leave SDZ unconnected, because amplifier operation would be unpredictable. For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power supply. The gain setting is selected at the end of the start-up cycle. At the end of the start-up cycle, the gain is selected and cannot be changed until the next power-up. 7.3.4 PLIMIT Operation The TPA31xxD2 family has a built-in voltage limiter that can be used to limit the output voltage level below the supply rail, the amplifier simply operates as if it was powered by a lower supply voltage, and thereby limits the output power. Add a resistor divider from GVDD to ground to set the voltage at the PLIMIT pin. An external reference may also be used if tighter tolerance is required. Add a 1 µF capacitor from pin PLIMIT to ground to ensure stability. It is recommended to connect PLIMIT to GVDD when using 1SPW-modulation mode. Figure 29. Power Limit Example The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle to a fixed maximum value. This limit can be thought of as a "virtual" voltage rail which is lower than the supply connected to PVCC. This "virtual" rail is approximately 4 times the voltage at the PLIMIT pin. This output voltage can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 2 L P L S OUT L R V R + 2 R P = for unclipped power 2 R æ ö æ ö ç ÷ ç ÷´ ´ è ø è ø ´ TPA3116D2, TPA3118D2, TPA3130D2 SLOS708D –APRIL 2012–REVISED JANUARY 2015 www.ti.com where • POUT (10%THD) = 1.25 × POUT (unclipped) • RL is the load resistance. • RS is the total series resistance including RDS(on), and output filter resistance. • VP is the peak amplitude • VP = 4 × PLIMIT voltage if PLIMIT < 4 × VP (2) Table 3. Power Limit Example PVCC (V) PLIMIT VOLTAGE (V)(1) R to GND R to GVDD OUTPUT VOLTAGE (Vrms) 24 V GVDD Short Open 17.9 24 V 3.3 45 kΩ 51 kΩ 12.67 24 V 2.25 24 kΩ 51 kΩ 9 12 V GVDD Short Open 10.33 12 V 2.25 24 kΩ 51 kΩ 9 12 V 1.5 18 kΩ 68 kΩ 6.3 (1) PLIMIT measurements taken with EVM gain set to 26dB and input voltage set to 1Vrms. 7.3.5 GVDD Supply The GVDD Supply is used to power the gates of the output full bridge transistors. It can also be used to supply the PLIMIT and GAIN/SLV voltage dividers. Decouple GVDD with a X5R ceramic 1 µF capacitor to GND. The GVDD supply is not intended to be used for external supply. It is recommended to limit the current consumption by using resistor voltage dividers for GAIN/SLV and PLIMIT of 100 kΩ or more. 7.3.6 BSPx AND BSNx Capacitors The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the high side of each output to turn on correctly. A 220 nF ceramic capacitor of quality X5R or better, rated for at least 16 V, must be connected from each output to its corresponding bootstrap input. (See the application circuit diagram in Figure 37.) The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the highside MOSFETs turned on. 7.3.7 Differential Inputs The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To use the TPA31xxD2 family with a differential source, connect the positive lead of the audio source to the RINP or LINP input and the negative lead from the audio source to the RINN or LINN input. To use the TPA31xxD2 family with a single-ended source, ac ground the negative input through a capacitor equal in value to the input capacitor on positive and apply the audio source to either input. In a single-ended input application, the unused input should be ac grounded at the audio source instead of at the device input for best noise performance. For good transient performance, the impedance seen at each of the two differential inputs should be the same. The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible. This is to allow the input dc blocking capacitors to become completely charged during the 10 ms power-up time. If the input capacitors are not allowed to completely charge, there will be some additional sensitivity to component matching which can result in pop if the input components are not well matched. 7.3.8 Device Protection System The TPA31xxD2 family contains a complete set of protection circuits carefully designed to make system design efficient as well as to protect the device against any kind of permanent failures due to short circuits, overload, over temperature, and under-voltage. The FAULTZ pin will signal if an error is detected according to Table 4: 16 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708D –APRIL 2012–REVISED JANUARY 2015 Table 4. Fault Reporting TRIGGERING CONDITION LATCHED/SELF- FAULT FAULTZ ACTION (typical value) CLEARING Over Current Output short or short to PVCC or GND Low Output high impedance Latched Over Temperature Tj > 150°C Low Output high impedance Latched Too High DC Offset DC output voltage Low Output high impedance Latched Under Voltage on PVCC < 4.5V – Output high impedance Self-clearing PVCC Over Voltage on PVCC > 27V – Output high impedance Self-clearing PVCC 7.3.9 DC Detect Protection The TPA31xxD2 family has circuitry which will protect the speakers from DC current which might occur due to defective capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect fault will be reported on the FAULT pin as a low state. The DC Detect fault will also cause the amplifier to shutdown by changing the state of the outputs to Hi-Z. If automatic recovery from the short circuit protection latch is desired, connect the FAULTZ pin directly to the SDZ pin. This allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the DC Detect protection latch. A DC Detect Fault is issued when the output differential duty-cycle of either channel exceeds 60% for more than 420 msec at the same polarity. Table x below shows some examples of the typical DC Detect Protection threshold for several values of the supply voltage. This feature protects the speaker from large DC currents or AC currents less than 2Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low at powerup until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive and negative inputs to avoid nuisance DC detect faults. Table 5 lists the minimum output offset voltages required to trigger the DC detect. The outputs must remain at or above the voltage listed in the table for more than 420 ms to trigger the DC detect. Table 5. DC Detect Threshold PVCC (V) VOS - OUTPUT OFFSET VOLTAGE (V) 4.5 0.96 6 1.3 12 2.6 18 3.9 7.3.10 Short-Circuit Protection and Automatic Recovery Feature The TPA31xxD2 family has protection from over current conditions caused by a short circuit on the output stage. The short circuit protection fault is reported on the FAULTZ pin as a low state. The amplifier outputs are switched to a high impedance state when the short circuit protection latch is engaged. The latch can be cleared by cycling the SDZ pin through the low state. If automatic recovery from the short circuit protection latch is desired, connect the FAULTZ pin directly to the SDZ pin. This allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the shortcircuit protection latch. In systems where a possibility of a permanent short from the output to PVDD or to a high voltage battery like a car battery can occur, pull the MUTE pin low with the FAULTZ signal with a inverting transistor to ensure a highZ restart, like shown in the figure below: Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 > 1.4sec mP TPA3116D2 SDZ MUTE FAULTZ SDZ MUTE FAULTZ TPA3116D2, TPA3118D2, TPA3130D2 SLOS708D –APRIL 2012–REVISED JANUARY 2015 www.ti.com Figure 30. MUTE Driven by Inverted FAULTZ Figure 31. Timing Requirement for SDZ 7.3.11 Thermal Protection Thermal protection on the TPA31xxD2 family prevents damage to the device when the internal die temperature exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature exceeds the thermal trip point, the device enters into the shutdown state and the outputs are disabled. This is a latched fault. Thermal protection faults are reported on the FAULTZ terminal as a low state. If automatic recovery from the thermal protection latch is desired, connect the FAULTZ pin directly to the SDZ pin. This allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the thermal protection latch. 7.3.12 Device Modulation Scheme The TPA31xxD2 family has the option of running in either BD modulation or 1SPW modulation; this is set by the MODSEL pin. 7.3.12.1 MODSEL = GND: BD-Modulation This is a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is driving an inductive load with short speaker wires. Each output is switching from 0 volts to the supply voltage. The OUTPx and OUTNx are in phase with each other with no input so that there is little or no current in the speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than 50% for positive output voltages. The duty cycle of OUTPx is less than 50% and OUTNx is greater than 50% for negative output voltages. The voltage across the load sits at 0V throughout most of the switching period, reducing the switching current, which reduces any I 2R losses in the load. 18 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 OUTP OUTN OUTP-OUTN Speaker Current OUTP OUTN OUTP-OUTN Speaker Current OUTP OUTN OUTP-OUTN Speaker Current 0V 0V PVCC No Output Positive Output Negative Output 0A 0A 0V -PVCC TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708D –APRIL 2012–REVISED JANUARY 2015 Figure 32. BD Mode Modulation 7.3.12.2 MODSEL = HIGH: 1SPW-modulation The 1SPW mode alters the normal modulation scheme in order to achieve higher efficiency with a slight penalty in THD degradation and more attention required in the output filter selection. In 1SPW mode the outputs operate at ~15% modulation during idle conditions. When an audio signal is applied one output will decrease and one will increase. The decreasing output signal will quickly rail to GND at which point all the audio modulation takes place through the rising output. The result is that only one output is switching during a majority of the audio cycle. Efficiency is improved in this mode due to the reduction of switching losses. The THD penalty in 1SPW mode is minimized by the high performance feedback loop. The resulting audio signal at each half output has a discontinuity each time the output rails to GND. This can cause ringing in the audio reconstruction filter unless care is taken in the selection of the filter components and type of filter used. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 OUTP OUTN OUTP-OUTN Speaker Current OUTP OUTN OUTP-OUTN Speaker Current OUTP OUTN OUTP-OUTN Speaker Current 0 V 0 V PVCC No Output Positive Output Negative Output 0A 0 A 0 V -PVCC TPA3116D2, TPA3118D2, TPA3130D2 SLOS708D –APRIL 2012–REVISED JANUARY 2015 www.ti.com Figure 33. 1SPW Mode Modulation 20 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708D –APRIL 2012–REVISED JANUARY 2015 7.3.13 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme The main reason that the traditional class-D amplifier-based on AD modulation needs an output filter is that the switching waveform results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the time at that voltage. The differential voltage swing is 2 × VCC, and the time at each voltage is half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive, whereas an LC filter is almost purely reactive. The TPA3116D2 modulation scheme has little loss in the load without a filter because the pulses are short and the change in voltage is VCC instead of 2 × VCC. As the output power increases, the pulses widen, making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most applications the filter is not needed. An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow through the filter instead of the load. The filter has less resistance but higher impedance at the switching frequency than the speaker, which results in less power dissipation, therefore increasing efficiency. 7.3.14 Ferrite Bead Filter Considerations Using the Advanced Emissions Suppression Technology in the TPA3116D2 amplifier it is possible to design a high efficiency class-D audio amplifier while minimizing interference to surrounding circuits. It is also possible to accomplish this with only a low-cost ferrite bead filter. In this case it is necessary to carefully select the ferrite bead used in the filter. One important aspect of the ferrite bead selection is the type of material used in the ferrite bead. Not all ferrite material is alike, so it is important to select a material that is effective in the 10 to 100 MHz range which is key to the operation of the class-D amplifier. Many of the specifications regulating consumer electronics have emissions limits as low as 30 MHz. It is important to use the ferrite bead filter to block radiation in the 30 MHz and above range from appearing on the speaker wires and the power supply lines which are good antennas for these signals. The impedance of the ferrite bead can be used along with a small capacitor with a value in the range of 1000 pF to reduce the frequency spectrum of the signal to an acceptable level. For best performance, the resonant frequency of the ferrite bead/ capacitor filter should be less than 10 MHz. Also, it is important that the ferrite bead is large enough to maintain its impedance at the peak currents expected for the amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. In this case it is possible to make sure the ferrite bead maintains an adequate amount of impedance at the peak current the amplifier will see. If these specifications are not available, it is also possible to estimate the bead current handling capability by measuring the resonant frequency of the filter output at low power and at maximum power. A change of resonant frequency of less than fifty percent under this condition is desirable. Examples of ferrite beads which have been tested and work well with the TPA3130D2 can be seen in the TPA3130D2EVM user guide SLOU341. A high quality ceramic capacitor is also needed for the ferrite bead filter. A low ESR capacitor with good temperature and voltage characteristics will work best. Additional EMC improvements may be obtained by adding snubber networks from each of the class-D outputs to ground. Suggested values for a simple RC series snubber network would be 18 Ω in series with a 330 pF capacitor although design of the snubber network is specific to every application and must be designed taking into account the parasitic reactance of the printed circuit board as well as the audio amp. Take care to evaluate the stress on the component in the snubber network especially if the amp is running at high PVCC. Also, make sure the layout of the snubber network is tight and returns directly to the GND pins on the IC. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 SLOS708D –APRIL 2012–REVISED JANUARY 2015 www.ti.com Figure 34. TPA311xD2 Radiated Emissions 7.3.15 When to Use an Output Filter for EMI Suppression The TPA3116D2 has been tested with a simple ferrite bead filter for a variety of applications including long speaker wires up to 125 cm and high power. The TPA3116D2 EVM passes FCC class-B specifications under these conditions using twisted speaker wires. The size and type of ferrite bead can be selected to meet application requirements. Also, the filter capacitor can be increased if necessary with some impact on efficiency. There may be a few circuit instances where it is necessary to add a complete LC reconstruction filter. These circumstances might occur if there are nearby circuits which are sensitive to noise. In these cases a classic second order Butterworth filter similar to those shown in the figures below can be used. Some systems have little power supply decoupling from the AC line but are also subject to line conducted interference (LCI) regulations. These include systems powered by "wall warts" and "power bricks." In these cases, LC reconstruction filters can be the lowest cost means to pass LCI tests. Common mode chokes using low frequency ferrite material can also be effective at preventing line conducted interference. 22 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 OUTP OUTN 10 µH L1 10 µH L2 C2 C3 0.68 µF 0.68 µF OUTP OUTN Ferrite Chip Bead 1 nF 1 nF Ferrite Chip Bead 4 - 8 W W 4 - 8 W W TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708D –APRIL 2012–REVISED JANUARY 2015 Figure 35. TPA31xxD2 Output Filters 7.3.16 AM Avoidance EMI Reduction To reduce interference in the AM radio band, the TPA3116D2 has the ability to change the switching frequency via AM<2:0> pins. The recommended frequencies are listed in Table 6. The fundamental frequency and its second harmonic straddle the AM radio band listed. This eliminates the tones that can be present due to the switching frequency being demodulated by the AM radio. Table 6. AM Frequencies US EUROPEAN SWITCHING FREQUENCY (kHz) AM2 AM1 AM0 AM FREQUENCY (kHz) AM FREQUENCY (kHz) 522-540 540-917 540-914 500 0 0 1 0 1 0 917-1125 914-1122 600 (or 400) 0 0 0 1125-1375 1122-1373 500 0 0 1 0 1 0 1375-1547 1373-1548 600 (or 400) 0 0 0 0 1 0 1547-1700 1548-1701 600 (or 500) 0 0 1 Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2 4.5 V–26 V PSU LC Filter OUTPR OUTNR OUTPL OUTNL Right Left PBTL Detect TPA3116D2, TPA3118D2, TPA3130D2 SLOS708D –APRIL 2012–REVISED JANUARY 2015 www.ti.com 7.4 Device Functional Modes 7.4.1 Mono Mode (PBTL) The TPA31xxD2 family can be connected in MONO mode enabling up to 100W output power. This is done by: • Connect INPL and INNL directly to Ground (without capacitors) this sets the device in Mono mode during power up. • Connect OUTPR and OUTNR together for the positive speaker terminal and OUTNL and OUTPL together for the negative pin. • Analog input signal is applied to INPR and INNR. Figure 36. Mono Mode 24 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708D –APRIL 2012–REVISED JANUARY 2015 8 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information This section describes a 2.1 Master and Slave application. The Master is configured as stereo outputs and the Slave is configured as mono PBTL output. 8.2 Typical Application A 2.1 solution, U1 TPA3116D2 in Master mode 400 kHz, BTL, gain if 20 dB, power limit not implemented. U2 in Slave, PBTL mode gain of 20dB. Inputs are connected for differential inputs. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 Power Pad U1 TPA3116D2 MODSEL 1 SDZ 2 FAULTZ 3 INPR 4 INNR 5 PLIMIT 6 GVDD 7 GAIN/SLV 8 GND 9 INPL 10 INNL 11 MUTE 12 AM2 13 AM1 14 AM0 15 SYNC 16 PVCC 32 PVCC 31 BSPR 30 OUTPR 29 GND 28 OUTNR 27 BSNR 26 GND 25 BSPL 24 OUTPL 23 GND 22 OUTNL 21 BSNL 20 PVCC 19 PVCC 18 AVCC 17 PVCC DECOUPLING C17 220nF 1 2 PVCC DECOUPLING GND C16 220nF 1 2 C13 1uF 2 1 C58 100nF 1 2 C29 680nF 2 1 L7 10uH 1 2 R10 3.3R 1 2 L8 10uH 1 2 C28 680nF 2 1 L9 10uH 1 2 C57 10nF 2 1 R12 20k 1 2 L10 10uH 1 2 C38 10nF 2 1 R14 100k 1 2 C25 220uF 1 2 C26 680nF 2 1 R18 3.3R 1 2 C40 10nF 2 1 R17 3.3R 1 2 GND C41 1nF 2 1 C32 1nF 2 1 C11 1uF 2 1 C22 220uF 1 2 GND C21 100nF 2 1 C20 1nF 2 1 C31 1nF 2 1 R15 3.3R 1 2 C33 1nF 2 1 R16 3.3R 1 2 GND C19 220nF 1 2 C30 1nF 2 1 C27 680nF 2 1 C34 10nF 2 1 C37 10nF 2 1 IN_P_LEFT IN_N_RIGHT IN_N_LEFT IN_P_RIGHT GND PVCC GND GND GND GND GND GND GND GND OUT_ N_LEFT OUT_P_LEFT - + OUT_N_RIGHT OUT_P_RIGHT + PVCC - C14 1uF 2 1 R11 100k 1 2 MUTE_LR OUTPUT LC FILTER R13 100k 1 2 C15 1uF 2 1 EMI C-RC SNUBBER C24 100nF 2 1 GND PVCC C18 220nF 1 2 GND /SD_LR PVCC C23 1nF 2 1 GND C12 1uF 2 1 R73 10k 1 2 C42 220nF 1 2 L15 10uH 1 2 L16 10uH 1 2 R21 75k 1 2 R22 100k 1 2 C50 220uF 1 2 C51 1uF 2 1 GND C35 1uF 2 1 GND C47 220uF 1 2 C46 100nF 2 1 C45 1nF 2 1 C54 1nF 2 1 R23 3.3R 1 2 GND R24 3.3R 1 2 C44 220nF 1 2 C53 1nF 2 1 C52 1uF 2 1 C55 10nF 2 1 C56 10nF 2 1 IN_P_SUB IN_N_SUB GND SYNC GND GND GND - + OUT_P_SUB OUT_N_SUB PVCC MUTE_SUB R20 47k 1 2 OUTPUT LC FILTER R19 100k 1 2 C39 1uF 2 1 C49 100nF 2 1 EMI C-RC SNUBBER PVCC C43 220nF 1 2 PVCC /SD_SUB C48 1nF 2 1 GND C36 1uF 2 1 GND Power Pad U2 TPA3116D2 MODSEL 1 SDZ 2 FAULTZ 3 INPR 4 INNR 5 PLIMIT 6 GVDD 7 GAIN/SLV 8 GND 9 INPL 10 INNL 11 MUTE 12 AM2 13 AM1 14 AM0 15 SYNC 16 PVCC 32 PVCC 31 BSPR 30 OUTPR 29 GND 28 OUTNR 27 BSNR 26 GND 25 BSPL 24 OUTPL 23 GND 22 OUTNL 21 BSNL 20 PVCC 19 PVCC 18 AVCC 17 PVCC DECOUPLING C43 220nF 1 2 PVCC DECOUPLING GND 4R 4R 2R TPA3116D2, TPA3118D2, TPA3130D2 SLOS708D –APRIL 2012–REVISED JANUARY 2015 www.ti.com Typical Application (continued) Figure 37. Schematic 8.2.1 Design Requriements DESIGN PARAMETERS EXAMPLE VALUE Input voltage range PVCC 4.5 V to 26 V PWM output frequencies 400 kHz, 500 kHz, 600 kHz, 1 MHz or 1.2 MHz Maximum output power 50 W 26 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708D –APRIL 2012–REVISED JANUARY 2015 8.2.2 Detailed Design Procedure The TPA31xxD2 family is a very flexible and easy to use Class D amplifier; therefore the design process is straightforward. Before beginning the design, gather the following information regarding the audio system. • PVCC rail planned for the design • Speaker or load impedance • Maximum output power requirement • Desired PWM frequency 8.2.2.1 Select the PWM Frequency Set the PWM frequency by using AM0, AM1 and AM2 pins. 8.2.2.2 Select the Amplifier Gain and Master/Slave Mode In order to select the amplifier gain setting, the designer must determine the maximum power target and the speaker impedance. Once these parameters have been determined, calculate the required output voltage swing which delivers the maximum output power. Choose the lowest analog gain setting that corresponds to produce an output voltage swing greater than the required output swing for maximum power. The analog gain and master/slave mode can be set by selecting the voltage divider resistors (R1 and R2) on the Gain/SLV pin. 8.2.2.3 Select Input Capacitance Select the bulk capacitors at the PVCC inputs for proper voltage margin and adequate capacitance to support the power requirements. In practice, with a well-designed power supply, two 100-μF, 50-V capacitors should be sufficient. One capacitor should be placed near the PVCC inputs at each side of the device. PVCC capacitors should be a low ESR type because they are being used in a high-speed switching application. 8.2.2.4 Select Decoupling Capacitors Good quality decoupling capacitors need to be added at each of the PVCC inputs to provide good reliability, good audio performance, and to meet regulatory requirements. X5R or better ratings should be used in this application. Consider temperature, ripple current, and voltage overshoots when selecting decoupling capacitors. Also, these decoupling capacitors should be located near the PVCC and GND connections to the device in order to minimize series inductances. 8.2.2.5 Select Bootstrap Capacitors Each of the outputs require bootstrap capacitors to provide gate drive for the high-side output FETs. For this design, use 0.22-μF, 25-V capacitors of X5R quality or better. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 0.001 0.01 0.1 1 10 0.01 0.1 1 10 40 Output Power (W) THD+N (%) f = 20Hz f = 1kHz f = 6kHz Gain = 26dB PVCC = 12V TA = 25°C RL = 4Ω G009 0.001 0.01 0.1 1 10 0.01 0.1 1 10 100 Output Power (W) THD+N (%) f = 20Hz f = 1kHz f = 6kHz Gain = 26dB PVCC = 24V TA = 25°C RL = 4Ω G010 TPA3116D2, TPA3118D2, TPA3130D2 SLOS708D –APRIL 2012–REVISED JANUARY 2015 www.ti.com 8.2.3 Application Curves Figure 38. Total Harmonic Distortion + Noise (BTL) vs Figure 39. Total Harmonic Distortion + Noise (BTL) vs Output Power Output Power 9 Power Supply Recommendations The power supply requirements for the TPA3116D2 consist of one higher-voltage supply to power the output stage of the speaker amplifier. Several on-chip regulators are included on the TPA3116D2 to generate the voltages necessary for the internal circuitry of the audio path. It is important to note that the voltage regulators which have been integrated are sized only to provide the current necessary to power the internal circuitry. The external pins are provided only as a connection point for off-chip bypass capacitors to filter the supply. Connecting external circuitry to these regulator outputs may result in reduced performance and damage to the device. The high voltage supply, between 4.5 V and 26 V, supplies the analog circuitry (AVCC) and the power stage (PVCC). The AVCC supply feeds internal LDO including GVDD. This LDO output are connected to external pins for filtering purposes, but should not be connected to external circuits. GVDD LDO output have been sized to provide current necessary for internal functions but not for external loading. 10 Layout 10.1 Layout Guidelines The TPA3116D2 can be used with a small, inexpensive ferrite bead output filter for most applications. However, since the class-D switching edges are fast, it is necessary to take care when planning the layout of the printed circuit board. The following suggestions will help to meet EMC requirements. • Decoupling capacitors — The high-frequency decoupling capacitors should be placed as close to the PVCC and AVCC terminals as possible. Large (100 μF or greater) bulk power supply decoupling capacitors should be placed near the TPA3116D2 on the PVCC supplies. Local, high-frequency bypass capacitors should be placed as close to the PVCC pins as possible. These caps can be connected to the IC GND pad directly for an excellent ground connection. Consider adding a small, good quality low ESR ceramic capacitor between 220 pF and 1 nF and a larger mid-frequency cap of value between 100 nF and 1 µF also of good quality to the PVCC connections at each end of the chip. • Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to GND as small and tight as possible. The size of this current loop determines its effectiveness as an antenna. • Grounding — The PVCC decoupling capacitors should connect to GND. All ground should be connected at the IC GND, which should be used as a central ground connection or star ground for the TPA3116D2. • Output filter — The ferrite EMI filter (see Figure 35) should be placed as close to the output terminals as possible for the best EMI performance. The LC filter should be placed close to the outputs. The capacitors used in both the ferrite and LC filters should be grounded. 28 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708D –APRIL 2012–REVISED JANUARY 2015 Layout Guidelines (continued) For an example layout, see the TPA3116D2 Evaluation Module (TPA3116D2EVM) User Guide (SLOU336). Both the EVM user manual and the thermal pad application reports, SLMA002 and SLMA004, are available on the TI Web site at http://www.ti.com. 10.2 Layout Example Figure 40. Layout Example Top Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 29 Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 SLOS708D –APRIL 2012–REVISED JANUARY 2015 www.ti.com Layout Example (continued) Figure 41. Layout Example Bottom 30 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 MACHINE THESE 3 EDGES AFTER 0.00 ANODIZATION –0.60 +.000 –.024 SINK HEIGHT 25.00 .984 1.00 [.118] 3.00 [.118] 0 [.000] 10.00 [.394] 19.50 [.768] 30.50 [1.201] 40.00 [1.575] 50.00±0.38 [1.969±.015] SINK LENGTH 3.00 [.118] 6.35 [.250] 13.90±0.38 [.547±.015] BASE WIDTH 6.95 [.274] 5.00 [.197] 40.00 [1.575] 2X 4-40 6.5 x TPA3116D2, TPA3118D2, TPA3130D2 www.ti.com SLOS708D –APRIL 2012–REVISED JANUARY 2015 10.3 Heat Sink Used on the EVM The heat sink (part number ATS-TI 10 OP-521-C1-R1) used on the EVM is an 14x25x50 mm extruded aluminum heat sink with three fins (see drawing below). For additional information on the heat sink, go to www.qats.com. Figure 42. EVM Heatsink This size heat sink has shown to be sufficient for continuous output power. The crest factor of music and having airflow will lower the requirement for the heat sink size and smaller types can be used. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 31 Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2, TPA3118D2, TPA3130D2 SLOS708D –APRIL 2012–REVISED JANUARY 2015 www.ti.com 11 Device and Documentation Support 11.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 7. Related Links TECHNICAL TOOLS & SUPPORT & PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY TPA3116D2 Click here Click here Click here Click here Click here TPA3118D2 Click here Click here Click here Click here Click here TPA3130D2 Click here Click here Click here Click here Click here 11.2 Trademarks All trademarks are the property of their respective owners. 11.3 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 32 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: TPA3116D2 TPA3118D2 TPA3130D2 PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TPA3116D2DAD ACTIVE HTSSOP DAD 32 46 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA 3116 D2 TPA3116D2DADR ACTIVE HTSSOP DAD 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA 3116 D2 TPA3118D2DAP ACTIVE HTSSOP DAP 32 46 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA3118 TPA3118D2DAPR ACTIVE HTSSOP DAP 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA3118 TPA3130D2DAP ACTIVE HTSSOP DAP 32 46 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA3130 TPA3130D2DAPR ACTIVE HTSSOP DAP 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TPA3130 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2014 Addendum-Page 2 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant TPA3116D2DADR HTSSOP DAD 32 2000 330.0 24.4 8.6 11.5 1.6 12.0 24.0 Q1 TPA3118D2DAPR HTSSOP DAP 32 2000 330.0 24.4 8.6 11.5 1.6 12.0 24.0 Q1 TPA3130D2DAPR HTSSOP DAP 32 2000 330.0 24.4 8.6 11.5 1.6 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2014 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPA3116D2DADR HTSSOP DAD 32 2000 367.0 367.0 45.0 TPA3118D2DAPR HTSSOP DAP 32 2000 367.0 367.0 45.0 TPA3130D2DAPR HTSSOP DAP 32 2000 367.0 367.0 45.0 PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2014 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2015, Texas Instruments Incorporated SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 15-V Digital or ±7.5-V Peak-to-Peak Switching 125-Ω Typical On-State Resistance for 15-V Operation Switch On-State Resistance Matched to Within 5 Ω Over 15-V Signal-Input Range On-State Resistance Flat Over Full Peak-to-Peak Signal Range High On/Off Output-Voltage Ratio: 80 dB Typical at fis = 10 kHz, RL = 1 kΩ High Degree of Linearity: <0.5% Distortion Typical at fis = 1 kHz, Vis = 5 V p-p, VDD − VSS ≥ 10 V, RL = 10 kΩ Extremely Low Off-State Switch Leakage, Resulting in Very Low Offset Current and High Effective Off-State Resistance: 10 pA Typical at VDD − VSS = 10 V, TA = 25°C Extremely High Control Input Impedance (Control Circuit Isolated From Signal Circuit): 1012 Ω Typical Low Crosstalk Between Switches: −50 dB Typical at fis = 8 MHz, RL = 1 kΩ Matched Control-Input to Signal-Output Capacitance: Reduces Output Signal Transients Frequency Response, Switch On = 40 MHz Typical 100% Tested for Quiescent Current at 20 V 5-V, 10-V, and 15-V Parametric Ratings Meets All Requirements of JEDEC Tentative Standard No. 13-B, Standard Specifications for Description of “B” Series CMOS Devices Applications: − Analog Signal Switching/Multiplexing: Signal Gating, Modulator, Squelch Control, Demodulator, Chopper, Commutating Switch − Digital Signal Switching/Multiplexing − Transmission-Gate Logic Implementation − Analog-to-Digital and Digital-to-Analog Conversion − Digital Control of Frequency, Impedance, Phase, and Analog-Signal Gain description/ordering information The CD4066B is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-for-pin compatible with the CD4016B, but exhibits a much lower on-state resistance. In addition, the on-state resistance is relatively constant over the full signal-input range. The CD4066B consists of four bilateral switches, each with independent controls. Both the p and the n devices in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 1, the well of the n-channel device on each switch is tied to either the input (when the switch is on) or to VSS (when the switch is off). This configuration eliminates the variation of the switch-transistor threshold voltage with input signal and, thus, keeps the on-state resistance low over the full operating-signal range. The advantages over single-channel switches include peak input-signal voltage swings equal to the full supply voltage and more constant on-state impedance over the input-signal range. However, for sample-and-hold applications, the CD4016B is recommended. !" #!$% & "' Copyright 2003, Texas Instruments Incorporated &! #" #" (" " ") !" & & * +' &! # " , &" " " %+ %!&" " , %% # " " ' Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 14 13 12 11 10 9 8 SIG A IN/OUT SIG A OUT/IN SIG B OUT/IN SIG B IN/OUT CONTROL B CONTROL C VSS VDD CONTROL A CONTROL D SIG D IN/OUT SIG D OUT/IN SIG C OUT/IN SIG C IN/OUT E, F, M, NS, OR PW PACKAGE (TOP VIEW) SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING CDIP − F Tube of 25 CD4066BF3A CD4066BF3A PDIP − E Tube of 25 CD4066BE CD4066BE Tube of 50 CD4066BM −55°C to 125°C SOIC − M Reel of 2500 CD4066BM96 CD4066BM −55°C to 125°C SOIC − M Reel of 250 CD4066BMT CD4066BM SOP − NS Reel of 2000 CD4066BNSR CD4066B TSSOP − PW Tube of 90 CD4066BPW CM066B Reel of 2000 CD4066BPWR † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. † All control inputs are protected by the CMOS protection network. NOTES: A. All p substrates are connected to VDD. B. Normal operation control-line biasing: switch on (logic 1), VC = VDD; switch off (logic 0), VC = VSS C. Signal-level range: VSS ≤ Vis ≤ VDD Control VC† VDD VSS VSS n n p Out Vos Control Switch In 92CS-29113 p n Vis Figure 1. Schematic Diagram of One-of-Four Identical Switches and Associated Control Circuitry SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† DC supply-voltage range, VDD (voltages referenced to VSS terminal) −0.5 V to 20 V . . . . . . . . . . . . . . . . . . . . Input voltage range, Vis (all inputs) −0.5 V to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DD + 0.5 V DC input current, IIN (any one input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA Package thermal impedance, θJA (see Note 1): E package 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C/W M package 86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C/W NS package 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C/W PW package 113 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C/W Lead temperature (during soldering): At distance 1/16 ± 1/32 inch (1,59 ± 0,79 mm) from case for 10 s max 265 . . . . . . . . . . . . . . . . . . . . . . . °C Storage temperature range, Tstg −65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . °C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions MIN MAX UNIT VDD Supply voltage 3 18 V TA Operating free-air temperature −55 125 °C SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics LIMITS AT INDICATED TEMPERATURES PARAMETER TEST CONDITIONS VIN VDD −55°C −40°C 85°C 125°C PARAMETER TEST CONDITIONS 25°C UNIT VIN (V) VDD (V) −55°C −40°C 85°C 125°C TYP MAX UNIT 0, 5 5 0.25 0.25 7.5 7.5 0.01 0.25 IDD Quiescent device 0, 10 10 0.5 0.5 15 15 0.01 0.5 IDD A Quiescent device current 0, 15 15 1 1 30 30 0.01 1 µA current 0, 20 20 5 5 150 150 0.02 5 Signal Inputs (Vis) and Outputs (Vos) VC = VDD, RL = 10 kΩ returned 5 800 850 1200 1300 470 1050 ron On-state resistance (max) RL = 10 kΩ returned to , VDD VSS 2 on 10 310 330 500 550 180 400 Ω (max) to , Vis = VSS to VDD 2 15 200 210 300 320 125 240 On-state resistance 5 15 ∆ron On-state resistance difference between any two switches RL = 10 kΩ, VC = VDD ∆ron difference between 10 10 Ω any two switches RL = 10 kΩ, VC = VDD 15 5 Ω THD Total harmonic distortion VC = VDD = 5 V, VSS = −5 V, Vis(p-p) = 5 V (sine wave centered on 0 V), RL = 10 kΩ, fis = 1-kHz sine wave 0.4 % −3-dB cutoff frequency (switch on) VC = VDD = 5 V, VSS = −5 V, Vis(p-p) = 5 V (sine wave centered on 0 V), RL = 1 kΩ 40 MHz −50-dB feedthrough frequency (switch off) VC = VSS = −5 V, Vis(p-p) = 5 V (sine wave centered on 0 V), RL = 1 kΩ 1 MHz Iis Input/output leakage current (switch off) (max) VC = 0 V, Vis = 18 V, Vos = 0 V; and VC = 0 V, Vis = 0 V, Vos = 18 V 18 ±0.1 ±0.1 ±1 ±1 ±10−5 ±0.1 µA −50-dB crosstalk frequency VC(A) = VDD = 5 V, VC(B) = VSS = −5 V, Vis(A) = 5 Vp-p, 50-Ω source, RL = 1 kΩ 8 MHz Propagation delay RL = 200 kΩ, VC = VDD, VSS = GND, CL = 50 pF, 5 20 40 tpd Propagation delay (signal input to signal output) VSS = GND, CL = 50 pF, Vis = 10 V (square wave centered on 5 V), pd (signal input to 10 10 20 ns signal output) is (square wave centered on 5 V), tr, tf = 20 ns 15 7 15 Cis Input capacitance VDD = 5 V, VC = VSS = −5 V 8 pF Cos Output capacitance VDD = 5 V, VC = VSS = −5 V 8 pF Cios Feedthrough VDD = 5 V, VC = VSS = −5 V 0.5 pF SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 electrical characteristics (continued) LIMITS AT INDICATED TEMPERATURES CHARACTERISTIC TEST CONDITIONS VDD −55°C −40°C 85°C 125°C CHARACTERISTIC TEST CONDITIONS 25°C UNIT VDD (V) −55°C −40°C 85°C 125°C TYP MAX UNIT Control (VC) Control input, |Iis| < 10 µA, 5 1 1 1 1 1 VILC Control input, low voltage (max) |Iis| < 10 µA, Vis = VSS, VOS = VDD, and V = V , V = V VILC 10 2 2 2 2 2 V low voltage (max) Vis = VSS, VOS = VDD, and Vis = VDD, VOS = VSS 15 2 2 2 2 2 V Control input, 5 3.5 (MIN) VIHC high voltage VIHC See Figure 6 10 7 (MIN) V high voltage See Figure 6 15 11 (MIN) V IIN Input current (max) Vis ≤ VDD, VDD − VSS = 18 V, VCC ≤ VDD − VSS 18 ±0.1 ±0.1 ±1 ±1 ±10−5 ±0.1 µA Crosstalk (control input to signal output) VC = 10 V (square wave), tr, tf = 20 ns, RL = 10 kΩ 10 50 mV Turn-on and turn-off VIN = VDD, tr, tf = 20 ns, 5 35 70 Turn-on and turn-off propagation delay VIN = VDD, tr, tf = 20 ns, CL = 50 pF, RL = 1 kΩ 10 20 40 ns propagation delay CL = 50 pF, RL = 1 kΩ 15 15 30 ns Vis = VDD, VSS = GND, RL = 1 kΩ to GND, CL = 50 pF, 5 6 Maximum control input repetition rate RL = 1 kΩ to GND, CL = 50 pF, VC = 10 V (square wave centered on 5 V), tr, tf = 20 ns, 10 9 MHz repetition rate C centered on 5 V), tr, tf = 20 ns, Vos = 1/2 Vos at 1 kHz 15 9.5 CI Input capacitance 5 7.5 pF switching characteristics VDD SWITCH INPUT SWITCH VDD OUTPUT, Vos (V) Vis (V) Iis (mA) OUTPUT, Vos (V) (V) Vis (V) −55°C −40°C 25°C 85°C 125°C MIN MAX 5 0 0.64 0.61 0.51 0.42 0.36 0.4 5 5 −0.64 −0.61 −0.51 −0.42 −0.36 4.6 10 0 1.6 1.5 1.3 1.1 0.9 0.5 10 10 −1.6 −1.5 −1.3 −1.1 −0.9 9.5 15 0 4.2 4 3.4 2.8 2.4 1.5 15 15 −4.2 −4 −3.4 −2.8 −2.4 13.5 SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS Vis − Input Signal Voltage − V 600 500 400 300 200 100 0 −4 −3 −2 −1 0 1 2 3 4 TYPICAL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) 92CS-27326RI Figure 2 TA = 125°C +25°C −55°C Supply Voltage (VDD − VSS) = 5 V − Channel On-State Resistance − on Ω r Figure 3 TYPICAL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) 300 250 200 150 100 50 0 −10 −7.5 −5 −2.5 0 2.5 5 7.5 10 Supply Voltage (VDD − VSS) = 10 V TA = 125°C Vis − Input Signal Voltage − V +25°C −55°C 92CS-27327RI − Channel On-State Resistance − on Ω r Vis − Input Signal Voltage − V TYPICAL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) Figure 4 300 250 200 150 100 50 0 −10 −7.5 −5 −2.5 0 2.5 5 7.5 10 Supply Voltage (VDD − VSS) = 15 V TA = 125°C +25°C −55°C 92CS-27329RI − Channel On-State Resistance − on Ω r Vis − Input Signal Voltage − V Figure 5 TYPICAL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) 600 500 400 300 200 100 0 −10 −7.5 −5 −2.5 0 2.5 5 7.5 10 Supply Voltage (VDD − VSS) = 5 V TA = 125°C 10 V −15 V 92CS-27330RI − Channel On-State Resistance − on Ω r SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TYPICAL CHARACTERISTICS CD4066B 1 of 4 Switches Iis Vis Vos 92CS-30966 |Vis − Vos| |Iis| ron = Figure 6. Determination of ron as a Test Condition for Control-Input High-Voltage (VIHC) Specification X-Y Plotter 1-kΩ Range TG On Keithley 160 Digital Multimeter H. P. Moseley 7030A X VSS VDD 10 kΩ 92CS-22716 Y Figure 7. Channel On-State Resistance Measurement Circuit Figure 8 TYPICAL ON CHARACTERISTICS FOR 1 OF 4 CHANNELS 3 2 1 0 −1 −2 −3 −3 −2 −1 0 1 2 3 4 VI − Input Voltage − V 92CS-30919 Output Voltage − V V − VC = VDD VDD Vis Vos RL VSS All unused terminals are connected to VSS CD4066B 1 of 4 Switches O Figure 9 10 102 103 10 101 102 103 104 f − Switching Frequency − kHz POWER DISSIPATION PER PACKAGE vs SWITCHING FREQUENCY TA = 25°C Power Dissipation Per Package − W D µ 6 4 2 6 4 2 6 4 2 6 4 2 2 46 2 46 92C-30920 5 V 10 V VSS VDD 5 6 13 12 7 CD4066B P − 14 Supply Voltage (VDD) = 15 V SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS V VDD = 5 V C = −5 V VSS = −5 V Cios Cis Cos CD4066B 1 of 4 Switches Measured on Boonton capacitance bridge, model 75a (1 MHz); test-fixture capacitance nulled out. 92CS-30921 Figure 10. Typical On Characteristics for One of Four Channels VDD VC = VSS Vos VSS CD4066B 1 of 4 Switches Vis = VDD I 92CS-30922 Figure 11. Off-Switch Input or Output Leakage All unused terminals are connected to VSS. VDD VC = VDD Vos VSS CD4066B 1 of 4 Switches Vis Figure 12. Propagation Delay Time Signal Input (Vis) to Signal Output (Vos) 92CS-30923 200 kΩ 50 pF VDD tr = tf = 20 ns All unused terminals are connected to VSS. VC VDD Vos VSS CD4066B 1 of 4 Switches Vis Figure 13. Crosstalk-Control Input to Signal Output +10 V tr = tf = 20 ns 92CS-30924 1 kΩ 10 kΩ All unused terminals are connected to VSS. SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TYPICAL CHARACTERISTICS VDD VC = VDD Vos VSS CD4066B 1 of 4 Switches VDD 92CS-30925 1 kΩ 50 pF VDD NOTES: A. All unused terminals are connected to VSS. B. Delay is measured at Vos level of +10% from ground (turn-on) or on-state output level (turn-off). tr = tf = 20 ns Figure 14. Propagation Delay, tPLH, tPHL Control-Signal Output VDD = 10 V VC VSS CD4066B 1 of 4 Switches Vis = 10 V 92CS-30925 50 pF 1 kΩ tr = tf = 20 ns VC Vos 90% 10% All unused terminals are connected to VSS. VOS VOS at 1 kHz 2 VOS VOS at 1 kHz 2 Repetition Rate 50% tr tf 10 V 0 V Figure 15. Maximum Allowable Control-Input Repetition Rate SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYPICAL CHARACTERISTICS Inputs VSS Measure inputs sequentially to both VDD and VSS. Connect all unused inputs to either VDD or VSS. Measure control inputs only. I VSS VDD 92CS-27555 Figure 16. Input Leakage-Current Test Circuit VDD Channel 1 Channel 2 Channel 3 Channel 4 Channel 1 Channel 2 Channel 3 Channel 4 1/4 CD4066B CD4066B CD4066B CD4018B CD4018B 1/4 CD4066B CD4001B LPF LPF LPF LPF 1 10 2 3 7 9 12 5 4 14 15 13 1 2 3 5 2 4 1 2 5 6 8 9 12 13 3 4 10 1 8 4 11 11 12 6 5 13 9 10 2 3 10 2 3 7 9 12 14 15 1 5 4 7 9 6 10 13 12 9 8 6 5 2 1 11 10 4 3 12 6 5 11 11 12 5 4 3 8 11 4 1 2 3 9 10 PE J1 J2 J3 J4 J5 Q1 Q2 1/3 CD4049B CD4001B Signal Inputs Clock Reset Package Count 2 - CD4001B 1 - CD4049B 3 - CD4066B 2 - CD4018B 1/3 CD4049B 1/6 CD4049B 10 k Signal Outputs PE J1 J2 J3 J4 J5 Q1 Q2 External Reset Clock Chan 1 Chan 2 Chan 3 Chan 4 VDD 30% (VDD − VSS) Clock Maximum Allowable Signal Level VSS 92CM-30928 Ω 10 kΩ 10 kΩ 10 kΩ 10 kΩ Figure 17. Four-Channel PAM Multiplex System Diagram SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TYPICAL CHARACTERISTICS SWA SWB SWC SWD 92CS-30927 Analog Inputs (±5 V) VDD = 5 V VDD = 5 V 5 V −5 V 5 V CD4066B Analog Outputs (±5 V) VSS = −5 V CD4054B VSS = 0 V VEE = −5 V IN 0 Digital Control Inputs 0 Figure 18. Bidirectional Signal Transmission Via Digital Control Logic SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION In applications that employ separate power sources to drive VDD and the signal inputs, the VDD current capability should exceed VDD/RL (RL = effective external load of the four CD4066B bilateral switches). This provision avoids any permanent current flow or clamp action on the VDD supply when power is applied or removed from the CD4066B. In certain applications, the external load-resistor current can include both VDD and signal-line components. To avoid drawing VDD current when switch current flows into terminals 1, 4, 8, or 11, the voltage drop across the bidirectional switch must not exceed 0.8 V (calculated from ron values shown). No VDD current will flow through RL if the switch current flows into terminals 2, 3, 9, or 10. PACKAGE OPTION ADDENDUM www.ti.com 29-Mar-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CD4066BE ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU | CU SN N / A for Pkg Type -55 to 125 CD4066BE CD4066BEE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD4066BE CD4066BF ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 CD4066BF CD4066BF3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 CD4066BF3A CD4066BF3AS2283 OBSOLETE CDIP J 14 TBD Call TI Call TI CD4066BF3AS2534 OBSOLETE CDIP J 14 TBD Call TI Call TI CD4066BM ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM CD4066BM96 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 CD4066BM CD4066BM96E4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM CD4066BM96G4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM CD4066BME4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM CD4066BMG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM CD4066BMT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066BM CD4066BNSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CD4066B CD4066BPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM066B CD4066BPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM066B CD4066BPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -55 to 125 CM066B CD4066BPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 CM066B PACKAGE OPTION ADDENDUM www.ti.com 29-Mar-2015 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples JM38510/05852BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 05852BCA M38510/05852BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 05852BCA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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PACKAGE OPTION ADDENDUM www.ti.com 29-Mar-2015 Addendum-Page 3 OTHER QUALIFIED VERSIONS OF CD4066B, CD4066B-MIL : • Catalog: CD4066B • Automotive: CD4066B-Q1, CD4066B-Q1 • Military: CD4066B-MIL NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects • Military - QML certified for Military and Defense Applications TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant CD4066BM96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD4066BM96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD4066BM96 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1 CD4066BM96G4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD4066BM96G4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD4066BMT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD4066BNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 CD4066BPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 7-Apr-2014 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD4066BM96 SOIC D 14 2500 333.2 345.9 28.6 CD4066BM96 SOIC D 14 2500 367.0 367.0 38.0 CD4066BM96 SOIC D 14 2500 364.0 364.0 27.0 CD4066BM96G4 SOIC D 14 2500 367.0 367.0 38.0 CD4066BM96G4 SOIC D 14 2500 333.2 345.9 28.6 CD4066BMT SOIC D 14 250 367.0 367.0 38.0 CD4066BNSR SO NS 14 2000 367.0 367.0 38.0 CD4066BPWR TSSOP PW 14 2000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 7-Apr-2014 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2015, Texas Instruments Incorporated TAS5707, TAS5707A www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 20-W STEREO DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC Check for Samples: TAS5707 TAS5707A 1FEATURES 23• Audio Input/Output Night-Mode Listening – 20-W Into an 8-Ω Load From an 18-V Supply – Autobank Switching: Preload Coefficients – Wide PVDD Range, From 8 V to 26 V for Different Sample Rates. No Need to Write New Coefficients to the Part When – Efficient Class-D Operation Eliminates Sample Rate Changes. Need for Heatsinks – Autodetect: Automatically Detects – Requires Only 3.3 V and PVDD Sample-Rate Changes. No Need for – One Serial Audio Input (Two Audio External Microprocessor Intervention Channels) – Supports 8-kHz to 48-kHz Sample Rate APPLICATIONS (LJ/RJ/I2S) • Television • Audio/PWM Processing • iPod™ Dock – Independent Channel Volume Controls With • Sound Bar 24 dB to Mute – Soft Mute (50% Duty Cycle) DESCRIPTION – Programmable Dynamic Range Control The TAS5707 is a 20-W, efficient, digital-audio power – 14 Programmable Biquads for Speaker EQ amplifier for driving stereo bridge-tied speakers. One and Other Audio Processing Features serial data input allows processing of up to two discrete audio channels and seamless integration to – Programmable Coefficients for DRC Filters most digital audio processors and MPEG decoders. – DC Blocking Filters The device accepts a wide range of input data and • General Features data rates. A fully programmable data path routes these channels to the internal speaker drivers. – Serial Control Interface Operational Without MCLK The TAS5707 is a slave-only device receiving all clocks from external sources. The TAS5707 operates – Factory-Trimmed Internal Oscillator for with a PWM carrier between a 384-kHz switching rate Automatic Rate Detection and 352-KHz switching rate, depending on the input – Surface Mount, 48-PIN, 7-mm × 7-mm sample rate. Oversampling combined with a HTQFP Package fourth-order noise shaper provides a flat noise floor – Thermal and Short-Circuit Protection and excellent dynamic range from 20 Hz to 20 kHz.. • Benefits The TAS5707A is identical in function to the HTQFP packaged TAS5707, but has a unique I 2 – EQ: Speaker Equalization Improves Audio C device Performance address. The address of the TAS5707 is 0x36. The address of the TAS5707A is 0x3A. – DRC: Dynamic Range Compression. Can Be Used As Power Limiter. Enables Speaker Protection, Easy Listening, 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2iPod is a trademark of Apple Inc. 3All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2008–2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. SDIN LRCLK SCLK MCLK RESET PDN SDA PLL_FLTM PLL_FLTP AVDD/DVDD PVDD OUT_A OUT_C OUT_B OUT_D BST_A BST_C BST_B BST_D 3.3 V 8 V–26 V SCL Digital Audio Source I C Control 2 Control Inputs LC LC Left Right B0264-11 Loop Filter(1) TAS5707, TAS5707A SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. SIMPLIFIED APPLICATION DIAGRAM (1)See user's guide for loop-filter details. 2 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5707 TAS5707A SDIN MCLK SCLK LRCLK Serial Audio Port 7 BQ L R V O L U M E DRC Protection Logic Click and Pop Control 7 BQ SDA SCL 4 Order th Noise Shaper and PWM S R C mDAP Sample Rate Autodetect and PLL Serial Control Microcontroller Based System Control Terminal Control OUT_A OUT_B 2 HB ´ FET Out OUT_C OUT_D 2 HB ´ FET Out B0262-02 TAS5707, TAS5707A www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 FUNCTIONAL VIEW Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): TAS5707 TAS5707A Temp. Sense VALID FAULT AGND OC_ADJ Power On Reset Undervoltage Protection GND PWM_D OUT_D PGND_CD PVDD_D BST_D Gate Drive PWM Rcv Overcurrent Protection 4 Protection and I/O Logic PWM_C OUT_C PGND_CD PVDD_C BST_C Timing Gate Drive Ctrl PWM Rcv GVDD_CD PWM_B OUT_B PGND_AB PVDD_B BST_B Timing Gate Drive Ctrl PWM Rcv PWM_A OUT_A PGND_AB PVDD_A BST_A Timing Gate Drive Ctrl PWM Rcv GVDD_AB Ctrl Pulldown Resistor Pulldown Resistor Pulldown Resistor Pulldown Resistor 4 GVDD_CD Regulator GVDD_AB Regulator Timing I sense B0034-05 PWM Controller FAULT TAS5707, TAS5707A SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com Figure 1. Power Stage Functional Block Diagram 4 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5707 TAS5707A Vol1 R L 7 BQ EQ ´ ´ ealpha ealpha ´ ´ 7 BQ EQ Input Muxing Vol2 B0341-01 1 Energy MAXMUX Attack Decay DRC1 DRC ON/OFF 50[D7] 30–36 29–2F 3A 3A 3B–3C 46[D0] To PWM Hex numbers refer to I2C subaddresses [Di] = bit "i" of subaddress SSTIMER OC_ADJ PLL_FLTP VR_ANA NC AVSS PLL_FLTM BST_A GVDD_OUT PVDD_A OUT_A RESET PVDD_A STEST PDN VR_DIG OSC_RES DVSSO DVDD FAULT MCLK SCLK SDIN LRCLK AVDD SDA SCL DVSS GND VREG PVDD_B BST_B PVDD_C OUT_C PVDD_D BST_D PGND_AB OUT_B PGND_CD OUT_D AGND PGND_AB PVDD_B PGND_CD PVDD_D BST_C PVDD_C GVDD_OUT P0075-01 PHP Package (Top View) TAS5707 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 TAS5707, TAS5707A www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 DAP Process Structure 48-TERMINAL, HTQFP PACKAGE (TOP VIEW) Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): TAS5707 TAS5707A TAS5707, TAS5707A SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com PIN FUNCTIONS PIN TYPE 5-V TERMINATION (1) DESCRIPTION TOLERANT (2) NAME NO. AGND 30 P Analog ground for power stage AVDD 13 P 3.3-V analog power supply AVSS 9 P Analog 3.3-V supply ground BST_A 4 P High-side bootstrap supply for half-bridge A BST_B 43 P High-side bootstrap supply for half-bridge B BST_C 42 P High-side bootstrap supply for half-bridge C BST_D 33 P High-side bootstrap supply for half-bridge D DVDD 27 P 3.3-V digital power supply DVSSO 17 P Oscillator ground DVSS 28 P Digital ground FAULT 14 DO Backend error indicator. Asserted LOW for over temperature, over current, over voltage, and under voltage error conditions. De-asserted upon recovery from error condition. GND 29 P Analog ground for power stage GVDD_OUT 5, 32 P Gate drive internal regulator output LRCLK 20 DI 5-V Pulldown Input serial audio data left/right clock (sample rate clock) MCLK 15 DI 5-V Pulldown Master clock input NC 8 – No connection OC_ADJ 7 AO Analog overcurrent programming. Requires resistor to ground. OSC_RES 16 AO Oscillator trim resistor. Connect an 18.2-kΩ 1% resistor to DVSSO. OUT_A 1 O Output, half-bridge A OUT_B 46 O Output, half-bridge B OUT_C 39 O Output, half-bridge C OUT_D 36 O Output, half-bridge D PDN 19 DI 5-V Pullup Power down, active-low. PDN prepares the device for loss of power supplies by shutting down the noise shaper and initiating PWM stop sequence. PGND_AB 47, 48 P Power ground for half-bridges A and B PGND_CD 37, 38 P Power ground for half-bridges C and D PLL_FLTM 10 AO PLL negative loop filter terminal PLL_FLTP 11 AO PLL positive loop filter terminal PVDD_A 2, 3 P Power supply input for half-bridge output A PVDD_B 44, 45 P Power supply input for half-bridge output B PVDD_C 40, 41 P Power supply input for half-bridge output C PVDD_D 34, 35 P Power supply input for half-bridge output D RESET 25 DI 5-V Pullup Reset, active-low. A system reset is generated by applying a logic low to this pin. RESET is an asynchronous control signal that restores the DAP to its default conditions, and places the PWM in the hard mute state (tristated). SCL 24 DI 5-V I 2C serial control clock input SCLK 21 DI 5-V Pulldown Serial audio data clock (shift clock). SCLK is the serial audio port input data bit clock. SDA 23 DIO 5-V I 2C serial control data interface input/output SDIN 22 DI 5-V Pulldown Serial audio data input. SDIN supports three discrete (stereo) data formats. (1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output (2) All pullups are weak pullups and all pulldowns are weak pulldowns. The pullups and pulldowns are included to assure proper input logic levels if the pins are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input). 6 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5707 TAS5707A TAS5707, TAS5707A www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 PIN FUNCTIONS (continued) PIN TYPE 5-V TERMINATION (1) DESCRIPTION TOLERANT (2) NAME NO. SSTIMER 6 AI Controls ramp time of OUT_X to minimize pop. Leave this pin floating for BD mode. Requires capacitor of 2.2 nF to GND in AD mode. The capacitor determines the ramp time. STEST 26 DI Factory test pin. Connect directly to DVSS. VR_ANA 12 P Internally regulated 1.8-V analog supply voltage. This pin must not be used to power external devices. VR_DIG 18 P Internally regulated 1.8-V digital supply voltage. This pin must not be used to power external devices. VREG 31 P Digital regulator output. Not to be used for powering external circuitry. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT DVDD, AVDD –0.3 to 3.6 V Supply voltage PVDD_X –0.3 to 30 V OC_ADJ –0.3 to 4.2 V 3.3-V digital input –0.5 to DVDD + 0.5 V Input voltage 5-V tolerant(2) digital input (except MCLK) –0.5 to DVDD + 2.5(3) V 5-V tolerant MCLK input –0.5 to AVDD + 2.5(3) V OUT_x to PGND_X 32(4) V BST_x to PGND_X 43(4) V Input clamp current, IIK ±20 mA Output clamp current, IOK ±20 mA Operating free-air temperature 0 to 85 °C Operating junction temperature range 0 to 150 °C Storage temperature range, Tstg –40 to 125 °C (1) Stresses beyond those listed under absolute ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operation conditions are not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability. (2) 5-V tolerant inputs are PDN, RESET, SCLK, LRCLK, MCLK, SDIN, SDA, and SCL. (3) Maximum pin voltage should not exceed 6.0Vele (4) DC voltage + peak ac waveform measured at the pin should be below the allowed limit for all conditions. DISSIPATION RATINGS(1) DERATING FACTOR TA ≤ 25°C TA = 45°C TA = 70°C PACKAGE ABOVE TA = 25°C POWER RATING POWER RATING POWER RATING 7-mm × 7-mm HTQFP 40 mW/°C 5 W 4.2 W 3.2 W (1) This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SLMA002 for more information about using the HTQFP thermal pad RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Digital/analog supply voltage DVDD, AVDD 3 3.3 3.6 V Half-bridge supply voltage PVDD_X 8 26 V VIH High-level input voltage 5-V tolerant 2 V VIL Low-level input voltage 5-V tolerant 0.8 V TA Operating ambient temperature range 0 85 °C Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): TAS5707 TAS5707A TAS5707, TAS5707A SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com RECOMMENDED OPERATING CONDITIONS (continued) MIN NOM MAX UNIT TJ (1) Operating junction temperature range 0 125 °C RL (BTL) Load impedance Output filter: L = 15 μH, C = 680 nF. 6 8 Ω Minimum output inductance under 10 LO (BTL) Output-filter inductance μH short-circuit condition (1) Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device. PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS PARAMETER TEST CONDITIONS VALUE UNIT 11.025/22.05/44.1-kHz data rate ±2% 352.8 kHz Output sample rate 48/24/12/8/16/32-kHz data rate ±2% 384 8 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5707 TAS5707A TAS5707, TAS5707A www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fMCLKI MCLK Frequency 2.8224 24.576 MHz MCLK duty cycle 40% 50% 60% tr / Rise/fall time for MCLK 5 ns tf(MCLK) LRCLK allowable drift before LRCLK reset 4 MCLKs External PLL filter capacitor C1 SMD 0603 Y5V 47 nF External PLL filter capacitor C2 SMD 0603 Y5V 4.7 nF External PLL filter resistor R SMD 0603, metal film 470 Ω ELECTRICAL CHARACTERISTICS DC Characteristics TA = 25°, PVCC_X = 18V, DVDD = AVDD = 3.3V, RL= 8Ω, BTL AD Mode, FS = 48KHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage FAULTZ and SDA IOH = –4 mA 2.4 V DVDD = AVDD = 3 V VOL Low-level output voltage FAULTZ and SDA IOL = 4 mA 0.5 V DVDD = AVDD = 3 V VI < VIL ; DVDD = AVDD 75 IIL Low-level input current μA = 3.6V VI > VIH ; DVDD = 75 IIH High-level input current μA AVDD = 3.6V Normal Mode 48 83 3.3 V supply voltage (DVDD, IDD 3.3 V supply current Reset (RESET = low, 24 32 mA AVDD) PDN = high) Normal Mode 30 55 IPVDD Half-bridge supply current No load (PVDD_X) Reset (RESET = low, 5 13 mA PDN = high) Drain-to-source resistance, LS TJ = 25°C, includes metallization resistance 180 rDS(on) (1) Drain-to-source resistance, mΩ TJ = 25°C, includes metallization resistance 180 HS I/O Protection Vuvp Undervoltage protection limit PVDD falling 7.2 V Vuvp,hyst Undervoltage protection limit PVDD rising 7.6 V OTE(2) Overtemperature error 150 °C Extra temperature drop OTEHYST (2) 30 °C required to recover from error OTW Overtemperature warning 125 °C Temperature drop required to OTWHYST 25 °C recover from warning OLPC Overload protection counter fPWM = 384 kHz 0.63 ms IOC Overcurrent limit protection Resistor—programmable, max. current, ROCP = 22 kΩ 4.5 A IOCT Overcurrent response time 150 ns OC programming resistor Resistor tolerance = 5% for typical value; the minimum ROCP 20 22 kΩ range resistance should not be less than 20 kΩ. Internal pulldown resistor at Connected when drivers are tristated to provide bootstrap RPD 3 kΩ the output of each half-bridge capacitor charge. (1) This does not include bond-wire or pin resistance. (2) Specified by design Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): TAS5707 TAS5707A TAS5707, TAS5707A SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com AC Characteristics (BTL) PVDD_X = 18 V, BTL AD mode, FS = 48 KHz, RL = 8 Ω, ROCP = 22 KΩ, CBST = 33 nF, audio frequency = 1 kHz, AES17 filter, fPWM = 384 kHz, TA = 25°C (unless otherwise noted). All performance is in accordance with recommended operating conditions, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PVDD = 18 V,10% THD, 1-kHz input signal 20.6 PVDD = 18 V, 7% THD, 1-kHz input signal 19.5 PVDD = 12 V, 10% THD, 1-kHz input 9.4 P signal O Power output per channel W PVDD = 12 V, 7% THD, 1-kHz input signal 8.9 PVDD = 8 V, 10% THD, 1-kHz input signal 4.1 PVDD = 8 V, 7% THD, 1-kHz input signal 3.8 PVDD= 18 V; PO = 1 W 0.06% THD+N Total harmonic distortion + noise PVDD= 12 V; PO = 1 W 0.13% PVDD= 8 V; PO = 1 W 0.2% Vn Output integrated noise (rms) A-weighted 56 μV PO = 0.25 W, f = 1kHz (BD Mode) –82 dB Crosstalk PO = 0.25 W, f = 1kHz (AD Mode) -69 dB A-weighted, f = 1 kHz, maximum power at SNR Signal-to-noise ratio (1) 106 dB THD < 1% (1) SNR is calculated relative to 0-dBFS input level. 10 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5707 TAS5707A th1 t su1 t (edge) t su2 th2 SCLK (Input) LRCLK (Input) SDIN T0026-04 t r t f TAS5707, TAS5707A www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 SERIAL AUDIO PORTS SLAVE MODE over recommended operating conditions (unless otherwise noted) TEST PARAMETER MIN TYP MAX UNIT CONDITIONS fSCLKIN Frequency, SCLK 32 × fS, 48 × fS, 64 × fS CL = 30 pF 1.024 12.288 MHz tsu1 Setup time, LRCLK to SCLK rising edge 10 ns th1 Hold time, LRCLK from SCLK rising edge 10 ns tsu2 Setup time, SDIN to SCLK rising edge 10 ns th2 Hold time, SDIN from SCLK rising edge 10 ns LRCLK frequency 8 48 48 kHz SCLK duty cycle 40% 50% 60% LRCLK duty cycle 40% 50% 60% SCLK SCLK rising edges between LRCLK rising edges 32 64 edges t(edge) SCLK LRCLK clock edge with respect to the falling edge of SCLK –1/4 1/4 period tr / ns Rise/fall time for SCLK/LRCLK 8 tf(SCLK/LRCLK) Figure 2. Slave Mode Serial Data Interface Timing Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): TAS5707 TAS5707A SCL SDA tw(H) tw(L) t r t f t su1 th1 T0027-01 SCL SDA th2 t (buf) t su2 t su3 Start Condition Stop Condition T0028-01 TAS5707, TAS5707A SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com I 2C SERIAL CONTROL PORT OPERATION Timing characteristics for I 2C Interface signals over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT fSCL Frequency, SCL No wait states 400 kHz tw(H) Pulse duration, SCL high 0.6 μs tw(L) Pulse duration, SCL low 1.3 μs tr Rise time, SCL and SDA 300 ns tf Fall time, SCL and SDA 300 ns tsu1 Setup time, SDA to SCL 100 ns th1 Hold time, SCL to SDA 0 ns t(buf) Bus free time between stop and start condition 1.3 μs tsu2 Setup time, SCL to start condition 0.6 μs th2 Hold time, start condition to SCL 0.6 μs tsu3 Setup time, SCL to stop condition 0.6 μs CL Load capacitance for each bus line 400 pF Figure 3. SCL and SDA Timing Figure 4. Start and Stop Conditions Timing 12 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5707 TAS5707A tw(RESET) RESET td(I2C_ready) System Initialization. Enable via I C. 2 T0421-01 I C Active 2 I C Active 2 f − Frequency − Hz 20 PVDD = 18 V RL = 8 Ω 100 1k 10k THD+N − Total Harmonic Distortion + Noise − % 20k G001 P = 1 W P = 5 W 0.001 0.01 10 0.1 1 f − Frequency − Hz 20 PVDD = 12 V RL = 8 Ω 100 1k 10k THD+N − Total Harmonic Distortion + Noise − % 20k G002 P = 2.5 W 0.001 0.01 10 0.1 1 P = 0.5 W TAS5707, TAS5707A www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 RESET TIMING (RESET) Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to Recommended Use Model section on usage of all terminals. PARAMETER MIN TYP MAX UNIT tw(RESET) Pulse duration, RESET active 100 us td(I2C_ready) Time to enable I 2C 13.5 ms NOTE: On power up, it is recommended that the TAS5707 RESET be held LOW for at least 100 μs after DVDD has reached 3.0 V NOTE: If the RESET is asserted LOW while PDN is LOW, then the RESET must continue to be held LOW for at least 100 μs after PDN is deasserted (HIGH). Figure 5. Reset Timing TYPICAL CHARACTERISTICS, BTL CONFIGURATION TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE vs vs FREQUENCY FREQUENCY Figure 6. Figure 7. Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Link(s): TAS5707 TAS5707A f − Frequency − Hz 20 PVDD = 8 V RL = 8 Ω 100 1k 10k THD+N − Total Harmonic Distortion + Noise − % 20k G003 P = 0.5 W P = 1 W 0.001 0.01 10 0.1 1 P = 2.5 W PO − Output Power − W 0.01 PVDD = 18 V RL = 8 Ω 0.1 1 10 THD+N − Total Harmonic Distortion + Noise − % 0.001 0.01 10 40 0.1 G004 1 f = 20 Hz f = 1 kHz f = 10 kHz PO − Output Power − W 0.01 PVDD = 12 V RL = 8 Ω 0.1 1 10 THD+N − Total Harmonic Distortion + Noise − % 0.001 0.01 10 40 0.1 G005 1 f = 20 Hz f = 1 kHz f = 10 kHz PO − Output Power − W 0.01 PVDD = 8 V RL = 8 Ω 0.1 1 10 THD+N − Total Harmonic Distortion + Noise − % 0.001 0.01 10 40 0.1 G006 1 f = 20 Hz f = 1 kHz f = 10 kHz TAS5707, TAS5707A SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued) TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE vs vs FREQUENCY OUTPUT POWER Figure 8. Figure 9. TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE vs vs OUTPUT POWER OUTPUT POWER Figure 10. Figure 11. 14 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5707 TAS5707A PVDD − Supply Voltage − V 2 4 6 8 10 12 14 16 18 20 8 9 10 11 12 13 14 15 16 17 18 PO − Output Power − W G010 RL = 8 Ω THD+N = 1% THD+N = 10% PO − Output Power (Per Channel) − W 0 10 20 30 40 50 60 70 80 90 100 0 4 8 12 16 20 24 28 32 36 40 Efficiency − % G012 PVDD = 12 V PVDD = 18 V RL = 8 Ω PVDD = 8 V −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 f − Frequency − Hz Crosstalk − dB G013 20 100 1k 10k 20k Left to Right Right to Left PO = 0.25 W PVDD = 18 V RL = 8 Ω −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 f − Frequency − Hz Crosstalk − dB G014 20 100 1k 10k 20k Left to Right Right to Left PO = 0.25 W PVDD = 12 V RL = 8 Ω TAS5707, TAS5707A www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued) OUTPUT POWER EFFICIENCY vs vs SUPPLY VOLTAGE OUTPUT POWER Figure 12. Figure 13. CROSSTALK CROSSTALK vs vs FREQUENCY FREQUENCY Figure 14. Figure 15. Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Link(s): TAS5707 TAS5707A −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 f − Frequency − Hz Crosstalk − dB G015 20 100 1k 10k 20k Left to Right Right to Left PO = 0.25 W PVDD = 8 V RL = 8 Ω TAS5707, TAS5707A SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued) CROSSTALK vs FREQUENCY Figure 16. 16 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5707 TAS5707A TAS5707, TAS5707A www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 DETAILED DESCRIPTION POWER SUPPLY To facilitate system design, the TAS5707 needs only a 3.3-V supply in addition to the (typical) 18-V power-stage supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only a few external capacitors. In order to provide good electrical and acoustical characteristics, the PWM signal path for the output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins (BST_X), and power-stage supply pins (PVDD_X). The gate drive voltages (GVDD_AB and GVDD_CD) are derived from the PVDD voltage. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible. In general, inductance between the power-supply pins and decoupling capacitors must be avoided. For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive regulator output pin (GVDD_X) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching frequencies in the range from 352 kHz to 384 kHz, it is recommended to use 33-nF ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of the PWM cycle. Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is decoupled with a 100-nF ceramic capacitor placed as close as possible to each supply pin. The TAS5707 is fully protected against erroneous power-stage turnon due to parasitic gate charging. ERROR REPORTING Any fault resulting in device shutdown is signaled by the FAULT pin going low (see Table 1). A sticky version of this pin is available on D1 of register 0X02. Table 1. FAULT Output States FAULT DESCRIPTION 0 Overcurrent (OC) or undervoltage (UVP) error or overtemperature error (OTE) or over voltage ERROR 1 No faults (normal operation) DEVICE PROTECTION SYSTEM Overcurrent (OC) Protection With Current Limiting The device has independent, fast-reacting current detectors on all high-side and low-side power-stage FETs. The detector outputs are closely monitored by two protection systems. The first protection system controls the power stage in order to prevent the output current further increasing, i.e., it performs a cycle-by-cycle current-limiting function, rather than prematurely shutting down during combinations of high-level music transients and extreme speaker load impedance drops. If the high-current condition situation persists, i.e., the power stage is being overloaded, a second protection system triggers a latching shutdown, resulting in the power stage being set in the high-impedance (Hi-Z) state. The device returns to normal operation once the fault condition (i.e., a short circuit on the output) is removed. Current limiting and overcurrent protection are not independent for half-bridges. That is, if the bridge-tied load between half-bridges A and B causes an overcurrent fault, half-bridges A, B, C, and D are shut down. Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Link(s): TAS5707 TAS5707A TAS5707, TAS5707A SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com Overtemperature Protection The TAS5707 has a two-level temperature-protection system that asserts an active-high warning signal (OTW) when the device junction temperature exceeds 125°C (nominal) and, if the device junction temperature exceeds 150°C (nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z) state and FAULT being asserted low. The TAS5707 recovers from shutdown automatically once the temperature drops approximately 30°C. The overtemperature warning (OTW) is disabled once the temperature drops approximately 25°C. Undervoltage Protection (UVP) and Power-On Reset (POR) The UVP and POR circuits of the TAS5707 fully protect the device in any power-up/down and brownout situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully operational when the PVDD and AVDD supply voltages reach 7.6 V and 2.7 V, respectively. Although PVDD and AVDD are independently monitored, a supply voltage drop below the UVP threshold on AVDD or either PVDD pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and FAULT being asserted low. SSTIMER FUNCTIONALITY The SSTIMER pin uses a capacitor connected between this pin and ground to control the output duty cycle when exiting all-channel shutdown. The capacitor on the SSTIMER pin is slowly charged through an internal current source, and the charge time determines the rate at which the output transitions from a near zero duty cycle to the desired duty cycle. This allows for a smooth transition that minimizes audible pops and clicks. When the part is shutdown the drivers are tristated and transition slowly down through a 3K resistor, similarly minimizing pops and clicks. The shutdown transition time is independent of SSTIMER pin capacitance. Larger capacitors will increase the start-up time, while capacitors smaller than 2.2 nF will decrease the start-up time. The SSTIMER pin should be left floating for BD modulation. CLOCK, AUTO DETECTION, AND PLL The TAS5707 is a slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP) supports all the sample rates and MCLK rates that are defined in the clock control register . The TAS5707 checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a 1 × fS LRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The clock section uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the internal clock (DCLK) running at 512 time the PWM switching frequency. The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock rates as defined in the clock control register. TAS5707 has robust clock error handling that uses the bulit-in trimmed oscillator clock to quickly detect changes/errors. Once the system detects a clock change/error, it will mute the audio (through a single step mute) and then force PLL to limp using the internal oscillator as a reference clock. Once the clocks are stable, the system will auto detect the new rate and revert to normal operation. During this process, the default volume will be restored in a single step (also called hard unmute). The ramp process can be programmed to ramp back slowly (also called soft unmute) as defined in volume register (0X0E). SERIAL DATA INTERFACE Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5707 DAP accepts serial data in 16-, 20-, or 24-bit left-justified, right-justified, and I 2S serial data formats. PWM Section The TAS5707 DAP device uses noise-shaping and sophisticated non-linear correction algorithms to achieve high power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP and outputs two BTL PWM audio output channels. 18 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5707 TAS5707A 23 22 SCLK 32 Clks LRCLK (Note Reversed Phase) Left Channel 24-Bit Mode 1 19 18 20-Bit Mode 16-Bit Mode 15 14 MSB LSB 32 Clks Right Channel 2-Channel I S (Philips Format) Stereo Input 2 T0034-01 9 8 5 4 1 0 0 5 4 1 0 23 22 1 19 18 15 14 MSB LSB 9 8 5 4 1 0 0 5 4 1 0 SCLK TAS5707, TAS5707A www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 The PWM section has individual channel dc blocking filters that can be enabled and disabled. The filter cutoff frequency is less than 1 Hz. Individual channel de-emphasis filters for 44.1- and 48-kHz are included and can be enabled and disabled. Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%. For detailed description of using audio processing features like DRC and EQ, please refer to User's Guide and TAS570X GDE software development tool documentation. Also refer to GDE software development tool for device data path. I 2C COMPATIBLE SERIAL CONTROL INTERFACE The TAS5707 DAP has an I 2C serial control slave interface to receive commands from a system controller. The serial control interface supports both normal-speed (100-kHz) and high-speed (400-kHz) operations without wait states. As an added feature, this interface operates even if MCLK is absent. The serial control interface supports both single-byte and multi-byte read and write operations for status registers and the general control registers associated with the PWM. SERIAL INTERFACE CONTROL AND TIMING I 2S Timing I 2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit clock. The DAP masks unused trailing data bit positions. NOTE: All data presented in 2s-complement form with MSB first. Figure 17. I 2S 64-fS Format Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Link(s): TAS5707 TAS5707A 23 22 SCLK 24 Clks LRCLK Left Channel 24-Bit Mode 1 19 18 20-Bit Mode 16-Bit Mode 15 14 MSB LSB 24 Clks Right Channel 2-Channel I S (Philips Format) Stereo Input/Output (24-Bit Transfer Word Size) 2 T0092-01 17 16 9 8 5 4 3 2 1 0 0 13 12 5 4 9 8 1 0 23 22 SCLK 1 19 18 15 14 MSB LSB 17 16 9 8 5 4 3 2 13 12 5 4 1 0 9 8 1 0 SCLK 16 Clks LRCLK Left Channel 16-Bit Mode 15 14 1 15 14 1 MSB LSB 16 Clks Right Channel 2-Channel I S (Philips Format) Stereo Input 2 T0266-01 13 12 11 10 9 8 5 4 3 2 0 13 12 11 10 9 8 5 4 3 2 SCLK MSB LSB TAS5707, TAS5707A SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com NOTE: All data presented in 2s-complement form with MSB first. Figure 18. I 2S 48-fS Format NOTE: All data presented in 2s-complement form with MSB first. Figure 19. I 2S 32-fS Format 20 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5707 TAS5707A 23 22 SCLK 32 Clks LRCLK Left Channel 24-Bit Mode 1 19 18 20-Bit Mode 16-Bit Mode 15 14 MSB LSB 32 Clks Right Channel 2-Channel Left-Justified Stereo Input T0034-02 9 8 5 4 5 4 1 1 0 0 0 23 22 1 19 18 15 14 MSB LSB 9 8 5 4 5 4 1 1 0 0 0 SCLK TAS5707, TAS5707A www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 Left-Justified Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused trailing data bit positions. NOTE: All data presented in 2s-complement form with MSB first. Figure 20. Left-Justified 64-fS Format Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Link(s): TAS5707 TAS5707A 23 22 SCLK 24 Clks LRCLK Left Channel 24-Bit Mode 1 19 18 20-Bit Mode 16-Bit Mode 15 14 MSB LSB 24 Clks Right Channel 2-Channel Left-Justified Stereo Input (24-Bit Transfer Word Size) T0092-02 17 16 9 8 5 4 13 12 5 4 1 9 8 1 0 0 0 21 17 13 23 22 SCLK 1 19 18 15 14 MSB LSB 17 16 9 8 5 4 13 12 5 4 1 9 8 1 0 0 0 21 17 13 SCLK 16 Clks LRCLK Left Channel 16-Bit Mode 15 14 1 15 14 1 MSB LSB 16 Clks Right Channel 2-Channel Left-Justified Stereo Input T0266-02 13 12 11 10 9 8 5 4 3 2 0 13 12 11 10 9 8 5 4 3 2 0 SCLK MSB LSB TAS5707, TAS5707A SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com NOTE: All data presented in 2s-complement form with MSB first. Figure 21. Left-Justified 48-fS Format NOTE: All data presented in 2s-complement form with MSB first. Figure 22. Left-Justified 32-fS Format 22 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5707 TAS5707A 23 22 SCLK 32 Clks LRCLK Left Channel 24-Bit Mode 1 20-Bit Mode 16-Bit Mode 15 14 MSB LSB SCLK 32 Clks Right Channel 2-Channel Right-Justified (Sony Format) Stereo Input T0034-03 19 18 19 18 1 1 0 0 0 15 14 15 14 23 22 1 15 14 MSB LSB 19 18 19 18 1 1 0 0 0 15 14 15 14 TAS5707, TAS5707A www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 Right-Justified Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for 24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before LRCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock. The DAP masks unused leading data bit positions. Figure 23. Right Justified 64-fS Format Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Link(s): TAS5707 TAS5707A 23 22 SCLK 24 Clks LRCLK Left Channel 24-Bit Mode 1 20-Bit Mode 16-Bit Mode 15 14 MSB LSB SCLK 24 Clks Right Channel MSB 2-Channel Right-Justified Stereo Input (24-Bit Transfer Word Size) T0092-03 19 18 5 19 18 5 1 5 1 0 0 0 2 2 2 6 6 6 15 14 15 14 23 22 1 15 14 19 18 5 19 18 5 1 5 1 0 0 0 2 2 2 6 6 6 15 14 15 14 LSB TAS5707, TAS5707A SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com Figure 24. Right Justified 48-fS Format Figure 25. Right Justified 32-fS Format 24 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5707 TAS5707A 7-Bit Slave Address R/ W A 8-Bit Register Address (N) 8-Bit Register Data For Address (N) Start Stop SDA SCL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 A 8-Bit Register Data For Address (N) A A T0035-01 TAS5707, TAS5707A www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 I 2C SERIAL CONTROL INTERFACE The TAS5707 DAP has a bidirectional I 2C interface that compatible with the I 2C (Inter IC) bus protocol and supports both 100-kHz and 400-kHz data transfer rates for single and multiple byte write and read operations. This is a slave only device that does not support a multimaster bus environment or wait state insertion. The control interface is used to program the registers of the device and to read device status. The DAP supports the standard-mode I 2C bus operation (100 kHz maximum) and the fast I 2C bus operation (400 kHz maximum). The DAP performs all I 2C operations without I 2C wait cycles. General I 2C Operation The I 2C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially one bit at a time. The address and data can be transferred in byte (8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the clock is high to indicate a start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 26. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The TAS5707 holds SDA low during the acknowledge clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for the SDA and SCL signals to set the high level for the bus. Figure 26. Typical I 2C Sequence There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in Figure 26. The 7-bit address for TAS5707 is 0011 011 (0x36). The 7-bit address for the TAS5707A is 0011 101 (0x3A). The TAS5707 address can be changed from 0x36 to 0x38 by writing 0x38 to device slave address register 0xF9. The TAS5707A address can be changed from 0x3A to 0x3C by writing 0x3C to device slave address register 0xF9. Single- and Multiple-Byte Transfers The serial control interface supports both single-byte and multiple-byte read/write operations for subaddresses 0x00 to 0x1F. However, for the subaddresses 0x20 to 0xFF, the serial control interface supports only multiple-byte read/write operations (in multiples of 4 bytes). During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does not contain 32 bits, the unused bits are read as logic 0. Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Link(s): TAS5707 TAS5707A A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK Start Condition Stop Condition Acknowledge Acknowledge Acknowledge I C Device Address and 2 Read/Write Bit Subaddress Data Byte T0036-01 D7 D0 ACK Stop Condition Acknowledge I C Device Address and 2 Read/Write Bit Subaddress Last Data Byte A6 A5 A1 A0 R/W ACK A7 A5 A1 A0 ACK D7 ACK Start Condition Acknowledge Acknowledge Acknowledge First Data Byte A6 A4 A3 Other Data Bytes ACK Acknowledge D0 D7 D0 T0036-02 TAS5707, TAS5707A SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes that are required for each specific subaddress. For example, if a write command is received for a biquad subaddress, the DAP expects to receive five 32-bit words. If fewer than five 32-bit data words have been received when a stop command (or another start command) is received, the data received is discarded. Supplying a subaddress for each subaddress transaction is referred to as random I 2C addressing. The TAS5707 also supports sequential I 2C addressing. For write transactions, if a subaddress is issued followed by data for that subaddress and the 15 subaddresses that follow, a sequential I 2C write transaction has taken place, and the data for all 16 subaddresses is successfully received by the TAS5707. For I 2C sequential write transactions, the subaddress then serves as the start address, and the amount of data subsequently transmitted, before a stop or start is transmitted, determines how many subaddresses are written. As was true for random addressing, sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to the last subaddress, the data for the last subaddress is discarded. However, all other data written is accepted; only the incomplete data is discarded. Single-Byte Write As shown in Figure 27, a single-byte data write transfer begins with the master device transmitting a start condition followed by the I 2C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write data transfer, the read/write bit will be a 0. After receiving the correct I 2C device address and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the address byte or bytes corresponding to the TAS5707 internal memory address being accessed. After receiving the address byte, the TAS5707 again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5707 again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data write transfer. Figure 27. Single-Byte Write Transfer Multiple-Byte Write A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted by the master device to the DAP as shown in Figure 28. After receiving each data byte, the TAS5707 responds with an acknowledge bit. Figure 28. Multiple-Byte Write Transfer 26 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5707 TAS5707A A6 A5 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A0 ACK Start Condition Stop Condition Acknowledge Acknowledge Acknowledge I C Device Address and 2 Read/Write Bit Subaddress Data Byte D7 D6 D1 D0 ACK I C Device Address and Read/Write Bit 2 Not Acknowledge A1 A1 R/W Repeat Start Condition T0036-03 A6 A0 ACK Acknowledge I C Device Address and Read/Write Bit 2 A6 A0 R/W ACK A0 ACK R/W D7 D0 ACK Start Condition Stop Condition Acknowledge Acknowledge Acknowledge Last Data Byte ACK First Data Byte Repeat Start Condition Not Acknowledge I C Device Address and Read/Write Bit 2 Subaddress Other Data Bytes A7 A6 A5 D7 D0 ACK Acknowledge D7 D0 T0036-04 TAS5707, TAS5707A www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 Single-Byte Read As shown in Figure 29, a single-byte data read transfer begins with the master device transmitting a start condition followed by the I 2C device address and the read/write bit. For the data read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5707 address and the read/write bit, TAS5707 responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the TAS5707 address and the read/write bit again. This time the read/write bit becomes a 1, indicating a read transfer. After receiving the address and the read/write bit, the TAS5707 again responds with an acknowledge bit. Next, the TAS5707 transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not acknowledge followed by a stop condition to complete the single byte data read transfer. Figure 29. Single-Byte Read Transfer Multiple-Byte Read A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes are transmitted by the TAS5707 to the master device as shown in Figure 30. Except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte. Figure 30. Multiple Byte Read Transfer Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Link(s): TAS5707 TAS5707A Output Level (dB) Input Level (dB) T O K M0091-02 1:1 Transfer Function Implemented Transfer Function S Z –1 Alpha Filter Structure w a B0265-01 Energy Filter a w, T, K, O a w a , a d d / , a w DRC 0x3A 0x40, 0x41, 0x42 0x3B / 0x3C Compression Control Attack and Decay Filters Audio Input DRC Coefficient NOTE: w a = 1 – TAS5707, TAS5707A SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com Dynamic Range Control (DRC) The DRC scheme has a single threshold, offset, and slope (all programmable). There is one ganged DRC for the left/right channels. The DRC input/output diagram is shown in Figure 31. Professional-quality dynamic range compression automatically adjusts volume to flatten volume level. • One DRC for left/right • The DRC has adjustable threshold, offset, and compression levels • Programmable energy, attack, and decay time constants • Transparent compression: compressors can attack fast enough to avoid apparent clipping before engaging, and decay times can be set slow enough to avoid pumping. Figure 31. Dynamic Range Control Figure 32. DRC Structure 28 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5707 TAS5707A 2 Bit –23 S_xx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx 2 Bit –5 2 Bit –1 2 Bit 0 Sign Bit 2 Bit 1 M0125-01 TAS5707, TAS5707A www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 BANK SWITCHING The TAS5707 uses an approach called bank switching together with automatic sample-rate detection. All processing features that must be changed for different sample rates are stored internally in three banks. The user can program which sample rates map to each bank. By default, bank 1 is used in 32kHz mode, bank 2 is used in 44.1/48 kHz mode, and bank 3 is used for all other rates. Combined with the clock-rate autodetection feature, bank switching allows the TAS5707 to detect automatically a change in the input sample rate and switch to the appropriate bank without any MCU intervention. An external controller configures bankable locations (0x29-0x36 and 0x3A-0x3C) for all three banks during the initialization sequence. If auto bank switching is enabled (register 0x50, bits 2:0) , then the TAS5707 automatically swaps the coefficients for subsequent sample rate changes, avoiding the need for any external controller intervention for a sample rate change. By default, bits 2:0 have the value 000; indicating that bank switching is disabled. In that state, updates to bankable locations take immediate effect. A write to register 0x50 with bits 2:0 being 001, 010, or 011 brings the system into the coefficient-bank-update state update bank1, update bank2, or update bank3, respectively. Any subsequent write to bankable locations updates the coefficient banks stored outside the DAP. After updating all the three banks, the system controller should issue a write to register 0x50 with bits 2:0 being 100; this changes the system state to automatic bank switching mode. In automatic bank switching mode, the TAS5707 automatically swaps banks based on the sample rate. Command sequences for updating DAP coefficients can be summarized as follows: 1. Bank switching disabled (default): DAP coefficient writes take immediate effect and are not influenced by subsequent sample rate changes. OR Bank switching enabled: (a) Update bank-1 mode: Write "001" to bits 2:0 of reg 0x50. Load the 32 kHz coefficients. (b) Update bank-2 mode: Write "010" to bits 2:0 of reg 0x50. Load the 48 kHz coefficients. (c) Update bank-3 mode: Write "011" to bits 2:0 of reg 0x50. Load the other coefficients. (d) Enable automatic bank switching by writing "100" to bits 2:0 of reg 0x50. 26-Bit 3.23 Number Format All mixer gain coefficients are 26-bit coefficients using a 3.23 number format. Numbers formatted as 3.23 numbers means that there are 3 bits to the left of the decimal point and 23 bits to the right of the decimal point. This is shown in Figure 33 . Figure 33. 3.23 Format Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 29 Product Folder Link(s): TAS5707 TAS5707A (1 or 0) 2 + ´ 1 (1 or 0) 2 + (1 or 0) 2 + ....... (1 or 0) 2 + ....... (1 or 0) 2 ´ ´ ´ ´ 0 –1 –4 –23 2 Bit 1 2 Bit 0 2 Bit –1 2 Bit –4 2 Bit –23 M0126-01 u Coefficient Digit 8 u u u u u S x Coefficient Digit 7 x. x x x Coefficient Digit 6 x x x x Coefficient Digit 5 x x x x Coefficient Digit 4 x x x x Coefficient Digit 3 x x x x Coefficient Digit 2 x x x x Coefficient Digit 1 Fraction Digit 5 Fraction Digit 4 Fraction Digit 3 Fraction Digit 2 Fraction Integer Digit 1 Digit 1 Sign Bit Fraction Digit 6 u = unused or don’t care bits Digit = hexadecimal digit M0127-01 0 TAS5707, TAS5707A SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com The decimal value of a 3.23 format number can be found by following the weighting shown in Figure 33. If the most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct number. If the most significant bit is a logic 1, then the number is a negative number. In this case every bit must be inverted, a 1 added to the result, and then the weighting shown in Figure 34 applied to obtain the magnitude of the negative number. Figure 34. Conversion Weighting Factors—3.23 Format to Floating Point Gain coefficients, entered via the I 2C bus, must be entered as 32-bit binary numbers. The format of the 32-bit number (4-byte or 8-digit hexadecimal number) is shown in Figure 35 Figure 35. Alignment of 3.23 Coefficient in 32-Bit I 2C Word Table 2. Sample Calculation for 3.23 Format db Linear Decimal Hex (3.23 Format) 0 1 8388608 00800000 5 1.7782794 14917288 00E39EA8 –5 0.5623413 4717260 0047FACC X L = 10(X/20) D = 8388608 × L H = dec2hex (D, 8) Table 3. Sample Calculation for 9.17 Format db Linear Decimal Hex (9.17 Format) 0 1 131072 20000 5 1.77 231997 38A3D –5 0.56 73400 11EB8 X L = 10(X/20) D = 131072 × L H = dec2hex (D, 8) 30 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5707 TAS5707A Initialization 50 ms 50 ms 2 sm 2 sm 2 sm 2 sm AVDD/DVDD PDN PVDD RESET T0419-01 3 V 3 V 0 ns 0 ns 0 ns 10 sm 100 sμ 13.5 ms 100 sm 6 V 6 V 8 V 8 V 2I S MCLK LRCLK SCLK SDIN 2I C SCL SDA Trim Volume and Mute Commands Clock Changes/Errors OK Stable and Valid Clocks Stable and Valid Clocks Exit SD Enter SD DAP Config Other Config 1 ms + 1.3 tstart(2) 1 ms + 1.3 tstart(2) tPLL(1) tPLL(1) 1 ms + 1.3 tstop(2) 0 ns Normal Operation Shutdown Powerdown (1) t has to be greater than 240 ms + 1.3 t . This constraint only applies to the first trim command following AVDD/DVDD power-up. It does not apply to trim commands following subsequent resets. (2) t /t = PWM start/stop time as defined in register 0X1A PLL start start stop TAS5707, TAS5707A www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 Recommended Use Model Figure 36. Recommended Command Sequence Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 31 Product Folder Link(s): TAS5707 TAS5707A 2 sm 2 sm 2 sm AVDD/DVDD PDN PVDD RESET T0420-01 3 V 8 V 6 V I S2 I C2 2 ms 0 ns 0 ns 0 ns 0 ns TAS5707, TAS5707A SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com Figure 37. Power Loss Sequence Recommended Command Sequences The DAP has two groups of commands. One set is for configuration and is intended for use only during initialization. The other set has built-in click and pop protection and may be used during normal operation while audio is streaming. The following supported command sequences illustrate how to initialize, operate, and shutdown the device. Initialization Sequence Use the following sequence to power-up and initialize the device: 1. Hold all digital inputs low and ramp up AVDD/DVDD to at least 3V. 2. Initialize digital inputs and PVDD supply as follows: • Drive RESETZ=0, PDNZ=1, and other digital inputs to their desired state while ensuring that all are never more than 2.5V above AVDD/DVDD. Provide stable and valid I2S clocks (MCLK, LRCLK, and SCLK). Wait at least 100us, drive RESETZ=1, and wait at least another 13.5ms. • Ramp up PVDD to at least 8V while ensuring that it remains below 6V for at least 100us after AVDD/DVDD reaches 3V. Then wait at least another 10us. 3. Trim oscillator (write 0x00 to register 0x1B) and wait at least 50ms. 4. Configure the DAP via I 2C (see Users's Guide for typical values): Biquads (0x29-36) DRC parameters (0x3A-3C, 0x40-42, and 0x46) Bank select (0x50) 5. Configure remaining registers 6. Exit shutdown (sequence defined below). 32 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5707 TAS5707A TAS5707, TAS5707A www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 Normal Operation The following are the only events supported during normal operation: (a) Writes to master/channel volume registers (b) Writes to soft mute register (c) Enter and exit shutdown (sequence defined below) (d) Clock errors and rate changes Note: Events (c) and (d) are not supported for 240ms+1.3*Tstart after trim following AVDD/DVDD powerup ramp (where Tstart is specified by register 0x1A). Shutdown Sequence Enter: 1. Ensure I2S clocks have been stable and valid for at least 50ms. 2. Write 0x40 to register 0x05. 3. Wait at least 1ms+1.3*Tstop (where Tstop is specified by register 0x1A). 4. Once in shutdown, stable clocks are not required while device remains idle. 5. If desired, reconfigure by ensuring that clocks have been stable and valid for at least 50ms before returning to step 4 of initialization sequence. Exit: 1. Ensure I2S clocks have been stable and valid for at least 50ms. 2. Write 0x00 to register 0x05 (exit shutdown command may not be serviced for as much as 240ms after trim following AVDD/DVDD powerup ramp). 3. Wait at least 1ms+1.3*Tstart (where Tstart is specified by register 0x1A). 4. Proceed with normal operation. Powerdown Sequence Use the following sequence to powerdown the device and its supplies: 1. If time permits, enter shutdown (sequence defined above); else, in case of sudden power loss, assert PDNZ=0 and wait at least 2ms. 2. Assert RESETZ=0. 3. Drive digital inputs low and ramp down PVDD supply as follows: • Drive all digital inputs low after RESETZ has been low for at least 2us. • Ramp down PVDD while ensuring that it remains above 8V until RESETZ has been low for at least 2us. 4. Ramp down AVDD/DVDD while ensuring that it remains above 3V until PVDD is below 6V and that it is never more than 2.5V below the digital inputs. Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 33 Product Folder Link(s): TAS5707 TAS5707A TAS5707, TAS5707A SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com Table 4. Serial Control Interface Register Summary NO. OF INITIALIZATION SUBADDRESS REGISTER NAME CONTENTS BYTES VALUE A u indicates unused bits. 0x00 Clock control register 1 Description shown in subsequent section 0x6C 0x01 Device ID register 1 Description shown in subsequent section 0x70 0x02 Error status register 1 Description shown in subsequent section 0x00 0x03 System control register 1 1 Description shown in subsequent section 0xA0 0x04 Serial data interface 1 Description shown in subsequent section 0x05 register 0x05 System control register 2 1 Description shown in subsequent section 0x40 0x06 Soft mute register 1 Description shown in subsequent section 0x00 0x07 Master volume 1 Description shown in subsequent section 0xFF (mute) 0x08 Channel 1 vol 1 Description shown in subsequent section 0x30 (0 dB) 0x09 Channel 2 vol 1 Description shown in subsequent section 0x30 (0 dB) 0x0A Fine master volume 1 Description shown in subsequent section 0x00 (0 dB) 0x0B–0X0D 1 Reserved(1) 0x0E Volume configuration 1 Description shown in subsequent section 0x91 register 0x0F 1 Reserved(1) 0x10 Modulation limit register 1 Description shown in subsequent section 0x02 0x11 IC delay channel 1 1 Description shown in subsequent section 0xAC 0x12 IC delay channel 2 1 Description shown in subsequent section 0x54 0x13 IC delay channel 3 1 Description shown in subsequent section 0xAC 0x14 IC delay channel 4 1 Description shown in subsequent section 0x54 0x15–0x19 1 Reserved(1) 0x1A Start/stop period register 1 Description shown in subsequent section 0x0F 0x1B Oscillator trim register 1 Description shown in subsequent section 0x82 0x1C BKND_ERR register 1 Description shown in subsequent section 0x02 0x1D–0x1F 1 Reserved(1) 0x20 Input MUX register 4 Description shown in subsequent section 0x0001 7772 0x21-0X24 4 Reserved(1) 0x25 PWM MUX register 4 Description shown in subsequent section 0x0102 1345 0x26–0x28 4 Reserved(1) 0x29 ch1_bq[0] 20 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 0x2A ch1_bq[1] 20 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 0x2B ch1_bq[2] 20 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 (1) Reserved registers should not be accessed. 34 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5707 TAS5707A TAS5707, TAS5707A www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 Table 4. Serial Control Interface Register Summary (continued) NO. OF INITIALIZATION SUBADDRESS REGISTER NAME CONTENTS BYTES VALUE 0x2C ch1_bq[3] 20 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 0x2D ch1_bq[4] 20 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 0x2E ch1_bq[5] 20 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 0x2F ch1_bq[6] 20 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 0x30 ch2_bq[0] 20 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 0x31 ch2_bq[1] 20 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 0x32 ch2_bq[2] 20 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 0x33 ch2_bq[3] 20 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 0x34 ch2_bq[4] 20 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 35 Product Folder Link(s): TAS5707 TAS5707A TAS5707, TAS5707A SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com Table 4. Serial Control Interface Register Summary (continued) NO. OF INITIALIZATION SUBADDRESS REGISTER NAME CONTENTS BYTES VALUE 0x35 ch2_bq[5] 20 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 0x36 ch2_bq[6] 20 u[31:26], b0[25:0] 0x0080 0000 u[31:26], b1[25:0] 0x0000 0000 u[31:26], b2[25:0] 0x0000 0000 u[31:26], a1[25:0] 0x0000 0000 u[31:26], a2[25:0] 0x0000 0000 0x37–0x39 Reserved(2) DRC ae(3) u[31:26], ae[25:0] 0x0080 0000 0x3A 8 DRC (1 – ae) u[31:26], (1 – ae)[25:0] 0x0000 0000 DRC aa u[31:26], aa[25:0] 0x0080 0000 0x3B 8 DRC (1 – aa) u[31:26], (1 – aa)[25:0] 0x0000 0000 DRC ad u[31:26], ad[25:0] 0x0080 0000 0x3C 8 DRC (1 – ad) u[31:26], (1 – ad)[25:0] 0x0000 0000 0x3D–0x3F Reserved(2) 0x40 DRC-T 4 T[31:0] (9.23 format) 0xFDA2 1490 0x41 DRC-K 4 u[31:26], K[25:0] 0x0384 2109 0x42 DRC-O 4 u[31:26], O[25:0] 0x0008 4210 0x43–0x45 Reserved(2) 0x46 DRC control 4 Description shown in subsequent section 0x0000 0000 0x47–0x4F Reserved(2) 0x50 Bank switch control 4 Description shown in subsequent section 0x0F70 8000 0x51–0xC9 Reserved(2) 0xCA 8 Reserved(2) 0xCB–0xF8 Reserved(2) Update device address 4 New Dev Id[7:1], ZERO[0] (New Dev Id = 0x38), 0x00000036 0xF9 register (7:1) defines the new device address 0xFA-0xFF Reserved(2) (2) Reserved registers should not be accessed. (3) "ae" stands for µ of energy filter, "aa" stands for µ of attack filter and "ad" stands for µ of decay filter and 1- µ = ω. All DAP coefficients are 3.23 format unless specified otherwise. 36 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5707 TAS5707A TAS5707, TAS5707A www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 CLOCK CONTROL REGISTER (0x00) The clocks and data rates are automatically determined by the TAS5707. The clock control register contains the auto-detected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency. The device accepts a 64-fS or 32-fS SCLK rate for all MCLK rates, but accepts a 48-fS SCLK rate for MCLK rates of 192 fS and 384 fS only. Table 5. Clock Control Register (0x00) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 0 0 0 – – – – – fS = 32-kHz sample rate 0 0 1 – – – – – Reserved(1) 0 1 0 – – – – – Reserved(1) 0 1 1 – – – – – fS = 44.1/48-kHz sample rate (2) 1 0 0 – – – – – fs = 16-kHz sample rate 1 0 1 – – – – – fs = 22.05/24 -kHz sample rate 1 1 0 – – – – – fs = 8-kHz sample rate 1 1 1 – – – – – fs = 11.025/12 -kHz sample rate – – – 0 0 0 – – MCLK frequency = 64 × fS (3) – – – 0 0 1 – – MCLK frequency = 128 × fS (3) – – – 0 1 0 – – MCLK frequency = 192 × fS (4) – – – 0 1 1 – – MCLK frequency = 256 × fS (2) (5) – – – 1 0 0 – – MCLK frequency = 384 × fS – – – 1 0 1 – – MCLK frequency = 512 × fS – – – 1 1 0 – – Reserved(1) – – – 1 1 1 – – Reserved(1) – – – – – – 0 – Reserved(1) – – – – – – – 0 Reserved(1) (1) Reserved registers should not be accessed. (2) Default values are in bold. (3) Only available for 44.1 kHz and 48 kHz rates. (4) Rate only available for 32/44.1/48 KHz sample rates (5) Not available at 8 kHz DEVICE ID REGISTER (0x01) The device ID register contains the ID code for the firmware revision. Table 6. General Status Register (0x01) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION X – – – – – – – Reserved – 1 1 1 0 0 0 0 Identification code Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 37 Product Folder Link(s): TAS5707 TAS5707A TAS5707, TAS5707A SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com ERROR STATUS REGISTER (0x02) The error bits are sticky and are not cleared by the hardware. This means that the software must clear the register (write zeroes) and then read them to determine if they are persistent errors. Error Definitions: • MCLK Error : MCLK frequency is changing. The number of MCLKs per LRCLK is changing. • SCLK Error: The number of SCLKs per LRCLK is changing. • LRCLK Error: LRCLK frequency is changing. • Frame Slip: LRCLK phase is drifting with respect to internal frame sync. Table 7. Error Status Register (0x02) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 1 - – – – – – – MCLK error – 1 – – – – – – PLL autolock error – – 1 – – – – – SCLK error – – – 1 – – – – LRCLK error – – – – 1 – – – Frame slip – – – – – – 1 – Overcurrent, overtemperature, overvoltage or undervoltage error – – – – – – – 1 Overtemperature warning (sets around 125°) 0 0 0 0 0 0 0 0 No errors (1) (1) Default values are in bold. SYSTEM CONTROL REGISTER 1 (0x03) The system control register 1 has several functions: Bit D7: If 0, the dc-blocking filter for each channel is disabled. If 1, the dc-blocking filter (–3 dB cutoff <1 Hz) for each channel is enabled (default). Bit D5: If 0, use soft unmute on recovery from clock error. This is a slow recovery. Unmute takes same time as volume ramp defined in reg 0X0E. If 1, use hard unmute on recovery from clock error (default). This is a fast recovery, a single step volume ramp Bits D1–D0: Select de-emphasis Table 8. System Control Register 1 (0x03) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 0 – – – – – – – PWM high-pass (dc blocking) disabled 1 – – – – – – – PWM high-pass (dc blocking) enabled (1) – 0 – – – – – – Reserved (1) – – 0 – – – – – Soft unmute on recovery from clock error – – 1 – – – – – Hard unmute on recovery from clock error (1) – – – 0 – – – – Reserved (1) – – – – 0 – – – Reserved (1) – – – – – 0 – – Reserved(1) – – – – – – 0 0 No de-emphasis (1) – – – – – – 0 1 De-emphasis for fS = 32 kHz – – – – – – 1 0 Reserved – – – – – – 1 1 De-emphasis for fS = 48 kHz (1) Default values are in bold. 38 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5707 TAS5707A TAS5707, TAS5707A www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 SERIAL DATA INTERFACE REGISTER (0x04) As shown in Table 9, the TAS5707 supports 9 serial data modes. The default is 24-bit, I 2S mode, Table 9. Serial Data Interface Control Register (0x04) Format RECEIVE SERIAL DATA WORD D7–D4 D3 D2 D1 D0 INTERFACE FORMAT LENGTH Right-justified 16 0000 0 0 0 0 Right-justified 20 0000 0 0 0 1 Right-justified 24 0000 0 0 1 0 I 2S 16 000 0 0 1 1 I 2S 20 0000 0 1 0 0 I 2S (1) 24 0000 0 1 0 1 Left-justified 16 0000 0 1 1 0 Left-justified 20 0000 0 1 1 1 Left-justified 24 0000 1 0 0 0 Reserved 0000 1 0 0 1 Reserved 0000 1 0 1 0 Reserved 0000 1 0 1 1 Reserved 0000 1 1 0 0 Reserved 0000 1 1 0 1 Reserved 0000 1 1 1 0 Reserved 0000 1 1 1 1 (1) Default values are in bold. Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 39 Product Folder Link(s): TAS5707 TAS5707A TAS5707, TAS5707A SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com SYSTEM CONTROL REGISTER 2 (0x05) When bit D6 is set low, the system exits all channel shutdown and starts playing audio; otherwise, the outputs are shut down(hard mute). Table 10. System Control Register 2 (0x05) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 0 – – – – – – – Reserved (1) – 1 – – – – – – Enter all channel shut down (hard mute).(1) – 0 – – – – – – Exit all-channel shutdown (normal operation) – – 0 0 0 0 0 0 Reserved (1) (1) Default values are in bold. SOFT MUTE REGISTER (0x06) Writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle (soft mute). Table 11. Soft Mute Register (0x06) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION – – – – – – – 1 Soft mute channel 1 – – – – – – – 0 Soft unmute channel 1 – – – – – – 1 – Soft mute channel 2 – – – – – – 0 – Soft unmute channel 2 0 0 0 0 0 0 – – Reserved 40 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5707 TAS5707A TAS5707, TAS5707A www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 VOLUME REGISTERS (0x07, 0x08, 0x09) Step size is 0.5 dB. Master volume – 0x07 (default is mute) Channel-1 volume – 0x08 (default is 0 dB) Channel-2 volume – 0x09 (default is 0 dB) Table 12. Volume Registers (0x07, 0x08, 0x09) D D D D D D D D FUNCTION 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 24 dB 0 0 1 1 0 0 0 0 0 dB (default for individual channel volume) (1) 1 1 0 0 1 1 0 1 –78.5 dB 1 1 0 0 1 1 1 0 –79.0 dB 1 1 0 0 1 1 1 1 Values between 0xCF and 0xFE are Reserved 1 1 1 1 1 1 1 1 MUTE (default for master volume) (1) Default values are in bold. Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 41 Product Folder Link(s): TAS5707 TAS5707A TAS5707, TAS5707A SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com MASTER FINE VOLUME REGISTER (0x0A) This register can be used to provide precision tuning of master volume. Table 13. Master Fine Volume Register (0x0A) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION – – – – – – 0 0 0 dB (1) – – – – – – 0 1 0.125 dB – – – – – – 1 0 0.25 dB – – – – – – 1 1 0.375 dB 1 – – – – – – – Write enable bit 0 – – – – – – – Ignore Write to register 0X0A (1) Default values are in bold. VOLUME CONFIGURATION REGISTER (0x0E) Bits Volume slew rate (Used to control volume change and MUTE ramp rates). These bits control the D2–D0: number of steps in a volume ramp.Volume steps occur at a rate that depends on the sample rate of the I2S data as follows Sample Rate (KHz) Approximate Ramp Rate 8/16/32 125 us/step 11.025/22.05/44.1 90.7 us/step 12/24/48 83.3 us/step Table 14. Volume Control Register (0x0E) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 1 0 0 1 0 – – – Reserved (1) – – – – – 0 0 0 Volume slew 512 steps (43 ms volume ramp time at 48kHz) – – – – – 0 0 1 Volume slew 1024 steps (85 ms volume ramp time at 48kHz) (1) – – – – – 0 1 0 Volume slew 2048 steps (171 ms volume ramp time at 48kHz) – – – – – 0 1 1 Volume slew 256 steps (21ms volume ramp time at 48kHz) – – – – – 1 X X Reserved (1) Default values are in bold. 42 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5707 TAS5707A TAS5707, TAS5707A www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 MODULATION LIMIT REGISTER (0x10) The modulation limit is the maximum duty cycle of the PWM output waveform. Table 15. Modulation Limit Register (0x10) D7 D6 D5 D4 D3 D2 D1 D0 MODULATION LIMIT – – – – – 0 0 0 99.2% – – – – – 0 0 1 98.4% – – – – – 0 1 0 97.7% – – – – – 0 1 1 96.9% – – – – – 1 0 0 96.1% – – – – – 1 0 1 95.3% – – – – – 1 1 0 94.5% – – – – – 1 1 1 93.8% 0 0 0 0 0 – – – RESERVED INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, and 0x14) Internal PWM channels 1, 2, 1, and 2 are mapped into registers 0x11, 0x12, 0x13, and 0x14. Table 16. Channel Interchannel Delay Register Format BITS DEFINITION D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 0 0 0 0 0 0 – – Minimum absolute delay, 0 DCLK cycles 0 1 1 1 1 1 – – Maximum positive delay, 31 × 4 DCLK cycles 1 0 0 0 0 0 – – Maximum negative delay, –32 × 4 DCLK cycles 0 0 RESERVED SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 Delay = (value) × 4 DCLKs 0x11 1 0 1 0 1 1 – – Default value for channel 1 (1) 0x12 0 1 0 1 0 1 – – Default value for channel 2 (1) 0x13 1 0 1 0 1 1 – – Default value for channel 1 (1) 0x14 0 1 0 1 0 1 – – Default value for channel 2 (1) (1) Default values are in bold. ICD settings have high impact on audio performance (e.g., dynamic range, THD, crosstalk etc.) Therefore, appropriate ICD settings must be used. By default, the device has ICD settings for AD mode. If used in BD mode, then update these registers before coming out of all-channel shutdown. REGISTER AD MODE BD MODE 0x11 0xAC 0xB8 0x12 0x54 0x60 0x13 0xAC 0xA0 0x14 0x54 0x48 Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 43 Product Folder Link(s): TAS5707 TAS5707A TAS5707, TAS5707A SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com START/STOP PERIOD REGISTER (0x1A) This register is used to control the soft-start and soft-stop period following an enter/exit all channel shut down command or change in the PDN state. This helps reduce pops and clicks at start-up and shutdown.The times are only approximate and vary depending on device activity level and I2S clock stability. Table 17. Start/Stop Period Register (0x1A) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 0 0 0 – – – – – Reserved – – – 0 0 – – – No 50% duty cycle start/stop period – – – 0 1 0 0 0 16.5-ms 50% duty cycle start/stop period – – – 0 1 0 0 1 23.9-ms 50% duty cycle start/stop period – – – 0 1 0 1 0 31.4-ms 50% duty cycle start/stop period – – – 0 1 0 1 1 40.4-ms 50% duty cycle start/stop period – – – 0 1 1 0 0 53.9-ms 50% duty cycle start/stop period – – – 0 1 1 0 1 70.3-ms 50% duty cycle start/stop period – – – 0 1 1 1 0 94.2-ms 50% duty cycle start/stop period – – – 0 1 1 1 1 125.7-ms 50% duty cycle start/stop period(1) – – – 1 0 0 0 0 164.6-ms 50% duty cycle start/stop period – – – 1 0 0 0 1 239.4-ms 50% duty cycle start/stop period – – – 1 0 0 1 0 314.2-ms 50% duty cycle start/stop period – – – 1 0 0 1 1 403.9-ms 50% duty cycle start/stop period – – – 1 0 1 0 0 538.6-ms 50% duty cycle start/stop period – – – 1 0 1 0 1 703.1-ms 50% duty cycle start/stop period – – – 1 0 1 1 0 942.5-ms 50% duty cycle start/stop period – – – 1 0 1 1 1 1256.6-ms 50% duty cycle start/stop period – – – 1 1 0 0 0 1728.1-ms 50% duty cycle start/stop period – – – 1 1 0 0 1 2513.6-ms 50% duty cycle start/stop period – – – 1 1 0 1 0 3299.1-ms 50% duty cycle start/stop period – – – 1 1 0 1 1 4241.7-ms 50% duty cycle start/stop period – – – 1 1 1 0 0 5655.6-ms 50% duty cycle start/stop period – – – 1 1 1 0 1 7383.7-ms 50% duty cycle start/stop period – – – 1 1 1 1 0 9897.3-ms 50% duty cycle start/stop period – – – 1 1 1 1 1 13,196.4-ms 50% duty cycle start/stop period (1) Default values are in bold. 44 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5707 TAS5707A TAS5707, TAS5707A www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 OSCILLATOR TRIM REGISTER (0x1B) The TAS5707 PWM processor contains an internal oscillator to support autodetect of I2S clock rates. This reduces system cost because an external reference is not required. Currently, TI recommends a reference resistor value of 18.2 kΩ (1%). This should be connected between OSC_RES and DVSSO. Writing 0X00 to reg 0X1B enables the trim that was programmed at the factory. Note that trim must always be run following reset of the device. Table 18. Oscillator Trim Register (0x1B) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 1 – – – – – – – Reserved (1) – 0 – – – – – – Oscillator trim not done (read-only) (1) – 1 – – – – – – Oscillator trim done (read only) – – 0 0 0 0 – – Reserved (1) – – – – – – 0 – Select factory trim (Write a 0 to select factory trim; default is 1.) – – – – – – 1 – Factory trim disabled (1) – – – – – – – 0 Reserved (1) (1) Default values are in bold. BKND_ERR REGISTER (0x1C) When a back-end error signal is received from the internal power stage, the power stage is reset stopping all PWM activity. Subsequently, the modulator waits approximately for the time listed in Table 19 before attempting to re-start the power stage. Table 19. BKND_ERR Register (0x1C)(1) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 0 0 0 0 0 0 0 X Reserved – – – – 0 0 1 0 Set back-end reset period to 299 ms (2) – – – – 0 0 1 1 Set back-end reset period to 449 ms – – – – 0 1 0 0 Set back-end reset period to 598 ms – – – – 0 1 0 1 Set back-end reset period to 748 ms – – – – 0 1 1 0 Set back-end reset period to 898 ms – – – – 0 1 1 1 Set back-end reset period to 1047 ms – – – – 1 0 0 0 Set back-end reset period to 1197 ms – – – – 1 0 0 1 Set back-end reset period to 1346 ms – – – – 1 0 1 X Set back-end reset period to 1496 ms – – – – 1 1 X X Set back-end reset period to 1496 ms (1) This register can be written only with a "non-Reserved" value. Also this register can be written once after the reset. (2) Default values are in bold. Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 45 Product Folder Link(s): TAS5707 TAS5707A TAS5707, TAS5707A SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com INPUT MULTIPLEXER REGISTER (0x20) This register controls the modulation scheme (AD or BD mode) as well as the routing of I2S audio to the internal channels. Table 20. Input Multiplexer Register (0x20) D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION 0 0 0 0 0 0 0 0 Reserved (1) D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION 0 – – – – – – – Channel-1 AD mode 1 – – – – – – – Channel-1 BD mode – 0 0 0 – – – – SDIN-L to channel 1 (1) – 0 0 1 – – – – SDIN-R to channel 1 – 0 1 0 – – – – Reserved – 0 1 1 – – – – Reserved – 1 0 0 – – – – Reserved – 1 0 1 – – – – Reserved – 1 1 0 – – – – Ground (0) to channel 1 – 1 1 1 – – – – Reserved – – – – 0 – – – Channel 2 AD mode – – – – 1 – – – Channel 2 BD mode – – – – – 0 0 0 SDIN-L to channel 2 – – – – – 0 0 1 SDIN-R to channel 2 (1) – – – – – 0 1 0 Reserved – – – – – 0 1 1 Reserved – – – – – 1 0 0 Reserved – – – – – 1 0 1 Reserved – – – – – 1 1 0 Ground (0) to channel 2 – – – – – 1 1 1 Reserved D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION 0 1 1 1 0 1 1 1 Reserved (1) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 0 1 1 1 0 0 1 0 Reserved (1) (1) Default values are in bold. PWM OUTPUT MUX REGISTER (0x25) This DAP output mux selects which internal PWM channel is output to the external pins. Any channel can be output to any external output pin. Bits D21–D20: Selects which PWM channel is output to OUT_A Bits D17–D16: Selects which PWM channel is output to OUT_B Bits D13–D12: Selects which PWM channel is output to OUT_C Bits D09–D08: Selects which PWM channel is output to OUT_D Note that channels are enclosed so that channel 1 = 0x00, channel 2 = 0x01, channet 1 = 0x02, and channel 2 = 0x03. 46 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5707 TAS5707A TAS5707, TAS5707A www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 Table 21. PWM Output Mux Register (0x25) D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION 0 0 0 0 0 0 0 1 Reserved(1) D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION 0 0 – – – – – – Reserved(1) – – 0 0 – – – – Multiplex channel 1 to OUT_A (1) – – 0 1 – – – – Multiplex channel 2 to OUT_A – – 1 0 – – – – Multiplex channel 1 to OUT_A – – 1 1 – – – – Multiplex channel 2 to OUT_A – – – – 0 0 – – Reserved (1) – – – – – – 0 0 Multiplex channel 1 to OUT_B – – – – – – 0 1 Multiplex channel 2 to OUT_B – – – – – – 1 0 Multiplex channel 1 to OUT_B (1) – – – – – – 1 1 Multiplex channel 2 to OUT_B D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION 0 0 – – – – – – Reserved (1) – – 0 0 – – – – Multiplex channel 1 to OUT_C – – 0 1 – – – – Multiplex channel 2 to OUT_C(1) – – 1 0 – – – – Multiplex channel 1 to OUT_C – – 1 1 – – – – Multiplex channel 2 to OUT_C – – – – 0 0 – – Reserved (1) – – – – – – 0 0 Multiplex channel 1 to OUT_D – – – – – – 0 1 Multiplex channel 2 to OUT_D – – – – – – 1 0 Multiplex channel 1 to OUT_D – – – – – – 1 1 Multiplex channel 2 to OUT_D (1) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 0 1 0 0 0 1 0 1 RESERVED (1) Default values are in bold. DRC CONTROL (0x46) Each DRC can be enabled independently using the DRC control register. The DRCs are disabled by default. Table 22. DRC Control Register (0x46) D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION 0 0 0 0 0 0 0 0 Reserved (1) D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION 0 0 0 0 0 0 0 0 Reserved (1) D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION 0 0 0 0 0 0 0 0 Reserved (1) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION – – – – – – – 0 DRC turned OFF (1) – – – – – – – 1 DRC turned ON 0 0 0 0 0 0 0 – Reserved (1) (1) Default values are in bold. Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 47 Product Folder Link(s): TAS5707 TAS5707A TAS5707, TAS5707A SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com BANK SWITCH AND EQ CONTROL (0x50) Table 23. Bank Switching Command D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION 0 – – – – – – – 32 kHz, does not use bank 3 (1) 1 – – – – – – – 32 kHz, uses bank 3 – 0 – – – – – – Reserved(1) – – 0 – – – – – Reserved(1) – – – 0 – – – – 44.1/48 kHz, does not use bank 3 (1) – – – 1 – – – – 44.1/48 kHz, uses bank 3 – – – – 0 – – – 16 kHz, does not use bank 3 – – – – 1 – – – 16 kHz, uses bank 3 (1) – – – – – 0 – – 22.025/24 kHz, does not use bank 3 – – – – – 1 – – 22.025/24 kHz, uses bank 3 (1) – – – – – – 0 – 8 kHz, does not use bank 3 – – – – – – 1 – 8 kHz, uses bank 3 (1) – – – – – – – 0 11.025 kHz/12, does not use bank 3 – – – – – – – 1 11.025/12 kHz, uses bank 3 (1) D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION 0 – – – – – – – 32 kHz, does not use bank 2 (1) 1 – – – – – – – 32 kHz, uses bank 2 – 1 – – – – – – Reserved (1) – – 1 – – – – – Reserved (1) – – – 0 – – – – 44.1/48 kHz, does not use bank 2 – – – 1 – – – – 44.1/48 kHz, uses bank 2 (1) – – – – 0 – – – 16 kHz, does not use bank 2 (1) – – – – 1 – – – 16 kHz, uses bank 2 – – – – – 0 – – 22.025/24 kHz, does not use bank 2 (1) – – – – – 1 – – 22.025/24 kHz, uses bank 2 – – – – – – 0 – 8 kHz, does not use bank 2 (1) – – – – – – 1 – 8 kHz, uses bank 2 – – – – – – – 0 11.025/12 kHz, does not use bank 2 (1) – – – – – – – 1 11.025/12 kHz, uses bank 2 D15 D14 D13 D12 D11 D10 D9 D8 FUNCTION 0 – – – – – – – 32 kHz, does not use bank 1 1 – – – – – – – 32 kHz, uses bank 1 (1) – 0 – – – – – – Reserved(1) – – 0 – – – – – Reserved(1) – – – 0 – – – – 44.1/48 kHz, does not use bank 1 (1) – – – 1 – – – – 44.1/48 kHz, uses bank 1 – – – – 0 – – – 16 kHz, does not use bank 1 (1) – – – – 1 – – – 16 kHz, uses bank 1 – – – – – 0 – – 22.025/24 kHz, does not use bank 1 (1) – – – – – 1 – – 22.025/24 kHz, uses bank 1 – – – – – – 0 – 8 kHz, does not use bank 1 (1) – – – – – – 1 – 8 kHz, uses bank 1 – – – – – – – 0 11.025/12 kHz, does not use bank 1 (1) – – – – – – – 1 11.025/12 kHz, uses bank 1 (1) Default values are in bold. 48 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5707 TAS5707A TAS5707, TAS5707A www.ti.com SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 Table 23. Bank Switching Command (continued) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 0 EQ ON 1 – – – – – – – EQ OFF (bypass BQ 0-6 of channels 1 and 2) – 0 – – – – – – Reserved (2) – – 0 – – – – – Ignore bank-mapping in bits D31–D8.Use default mapping. (2) 1 Use bank-mapping in bits D31–D8. – – – 0 – – – – L and R can be written independently. (2) L and R are ganged for EQ biquads; a write to Left channel BQ is – – – 1 – – – – also written to Right channel BQ. (0X29-2F is ganged to 0X30-0X36). – – – – 0 – – – Reserved (2) – – – – – 0 0 0 No bank switching. All updates to DAP (2) – – – – – 0 0 1 Configure bank 1 (32 kHz by default) – – – – – 0 1 0 Configure bank 2 (44.1/48 kHz by default) – – – – – 0 1 1 Configure bank 3 (other sample rates by default) – – – – – 1 0 0 Automatic bank selection – – – – – 1 0 1 Reserved – – – – – 1 1 X Reserved (2) Default values are in bold. Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 49 Product Folder Link(s): TAS5707 TAS5707A TAS5707, TAS5707A SLOS556B –NOVEMBER 2008–REVISED NOVEMBER 2009 www.ti.com Changes from Revision A (November 2008) to Revision B Page • Added TAS5707A device to data sheet ................................................................................................................................ 1 • Changed PVDD maximum voltage to 26 V in Features ....................................................................................................... 1 • Added Applications section ................................................................................................................................................... 1 • Inserted paragraph on TAS5707A into Description section .................................................................................................. 1 • Changed PVDD maximum voltage to 26 V in simplified application diagram ...................................................................... 2 • Changed PVDD maximum voltage to 26 V in recommended operating conditions ............................................................. 7 • Added AVDD to output voltage test conditions ..................................................................................................................... 9 • Added rows to Electrical Characteristics fro OTW and OTW ............................................................................................... 9 • Changed OLPC typical value to 0.63 ms. ............................................................................................................................. 9 • Replaced text of Overtemperature Protection section ........................................................................................................ 18 • Added address information for the TAS5707A ................................................................................................................... 25 • Revised Sample Calculation for 3.23 Format table ............................................................................................................ 30 • Added 0xCA row to Register Summary table ..................................................................................................................... 36 • Revised 0xF9 row of Register Summary table ................................................................................................................... 36 • Corrected temperature from 145°C to 125°C ..................................................................................................................... 38 • Changed de-emphasis settings in register 0x03 table ........................................................................................................ 38 • Added text to Modulationi Limit Register section ................................................................................................................ 43 • Added text to the DRC Control section ............................................................................................................................... 47 50 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): TAS5707 TAS5707A PACKAGE OPTION ADDENDUM www.ti.com 9-Sep-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples TAS5707APHP ACTIVE HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 85 TAS5707A TAS5707APHPR ACTIVE HTQFP PHP 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 85 TAS5707A TAS5707PHP ACTIVE HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 85 TAS5707 TAS5707PHPR ACTIVE HTQFP PHP 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 85 TAS5707 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant TAS5707APHPR HTQFP PHP 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 TAS5707APHPR HTQFP PHP 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 TAS5707PHPR HTQFP PHP 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Jun-2014 Pack Materials-Page 1 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5707APHPR HTQFP PHP 48 1000 367.0 367.0 38.0 TAS5707APHPR HTQFP PHP 48 1000 336.6 336.6 31.8 TAS5707PHPR HTQFP PHP 48 1000 336.6 336.6 31.8 PACKAGE MATERIALS INFORMATION www.ti.com 4-Jun-2014 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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B2 1 www.fairchildsemi.com FDS6679AZ P-Channel PowerTrench® MOSFET -30V, -13A, 9mΩ General Description This P-Channel MOSFET is producted using Fairchild Semiconductor’s advanced PowerTrench process that has been especially tailored to minimize the on-state resistance. This device is well suited for Power Management and load switching applications common in Notebook Computers and Portable Battery Packs. Features Max rDS(on) = 9.3mΩ at VGS = -10V, ID = -13A Max rDS(on) = 14.8mΩ at VGS = -4.5V, ID = -11A Extended VGS range (-25V) for battery applications HBM ESD protection level of 6kV typical (note 3) High performance trench technology for extremely low rDS(on) High power and current handing capability RoHS Compliant S D S S SO-8 D D D G 1 7 5 2 8 4 6 3 MOSFET Maximum Ratings TA = 25°C unless otherwise noted Thermal Characteristics Package Marking and Ordering Information Symbol Parameter Ratings Units VDS Drain to Source Voltage -30 V VGS Gate to Source Voltage ±25 V ID Drain Current -Continuous (Note 1a) -13 A -Pulsed -65 PD Power Dissipation for Single Operation (Note 1a) 2.5 (Note 1b) 1.2 W (Note 1c) 1.0 TJ, TSTG Operating and Storage Temperature -55 to +150 °C RθJA Thermal Resistance , Junction to Ambient (Note 1a) 50 °C/W RθJC Thermal Resistance , Junction to Case (Note 1) 25 °C/W Device Marking Device Reel Size Tape Width Quantity FDS6679AZ FDS6679AZ 13’’ 12mm 2500 units FDS6679AZ P-Channel PowerTrench® MOSFET ©2009 Fairchild Semiconductor Corporation 2 www.fairchildsemi.com FDS6679AZ Rev. B2 Electrical Characteristics T J = 25°C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage I D = -250 µA, VGS = 0V -30 V ∆ BVDSS ∆ T J Breakdown Voltage Temperature Coefficient I D = -250 µA, referenced to 25 ° C -20 mV/°C IDSS Zero Gate Voltage Drain Current VDS = -24V, VGS=0V -1 µ A IGSS Gate to Source Leakage Current VGS = ±25V, VDS=0V ±10 µ A On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, I D = -250 µ A -1 -1.9 -3 V ∆ VGS(th) ∆ T J Gate to Source Threshold Voltage Temperature Coefficient I D = -250 µA, referenced to 25°C 6.5 mV/°C rDS(on) Drain to Source On Resistance VGS = -10V, I D = -13A 7.7 9.3 m Ω VGS = -4.5V, I D = -11A 11.8 14.8 VGS = -10V, I D = -13A, T J = 125 ° C 10.7 13.4 gFS Forward Transconductance VDS = -5V, I D = -13A 55 S (Note 2) Dynamic Characteristics Ciss Input Capacitance VDS = -15V, VGS = 0V, f = 1MHz 2890 3845 pF Coss Output Capacitance 500 665 pF Crss Reverse Transfer Capacitance 495 745 pF Switching Characteristics (Note 2) td(on) Turn-On Delay Time VDD = -15V, I D = -1A VGS = -10V, RGS = 6 Ω 13 24 ns t r Rise Time 15 27 ns td(off) Turn-Off Delay Time 210 336 ns tf Fall Time 92 148 ns Qg Total Gate Charge VDS = -15V, VGS = -10V, ID = -13A 68 96 nC Qg Total Gate Charge VDS = -15V, VGS = -5V, ID = -13A 38 54 nC Qgs Gate to Source Gate Charge 10 nC Qgd Gate to Drain Charge 17 nC Drain-Source Diode Characteristic VSD Source to Drain Diode Forward Voltage VGS = 0V, I S = -2.1A -0.7 -1.2 V trr Reverse Recovery Time I F = -13A, di/dt = 100A/ µ s 40 ns Qrr Reverse Recovery Charge I F = -13A, di/dt = 100A/ µ s -31 nC Notes: 1: R θJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R θJC is guaranteed by design while R θCA is determined by the user’s board design. Scale 1 : 1 on letter size paper 2: Pulse Test:Pulse Width <300 µs, Duty Cycle <2.0% 3: The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied. a) 50 °C/W when mounted on a 1 in 2 pad of 2 oz copper b)105 °C/W when mounted on a .04 in 2 pad of 2 oz copper minimun pad c) 125 °C/W when mounted on a FDS6679AZ P-Channel PowerTrench® MOSFET ©2009 Fairchild Semiconductor Corporation 3 www.fairchildsemi.com FDS6679AZ Rev. B2 Typical Characteristics T J = 25°C unless otherwise noted Figure 1. On Region Characteristics 01234 0 10 20 30 40 50 60 70 PULSE DURATION = 80 µ s DUTY CYCLE = 0.5%MAX VGS = -5V VGS = -4V VGS = -3V VGS = -3.5V VGS = -4.5V VGS = -10V -ID, DRAIN CURRENT (A) -VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 2. Normalized 0 10 20 30 40 50 60 70 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 PULSE DURATION = 80 µ s DUTY CYCLE = 0.5%MAX NORMALIZED DRAIN TO SOURCE ON-RESISTANCE -I D, DRAIN CURRENT(A) VGS = -10V VGS = -5V VGS = -4.5V VGS = -4V VGS = -3.5V On-Resistance vs Drain Current and Gate Voltage Figure 3. -80 -40 0 40 80 120 160 0.6 0.8 1.0 1.2 1.4 1.6 I D = -13A VGS = -10V NORMALIZED DRAIN TO SOURCE ON-RESISTANCE T J, JUNCTION TEMPERATURE ( o C ) Normalized On Resistance vs Junction Temperature Figure 4. 3.0 4.5 6.0 7.5 9.0 0 10 20 30 PULSE DURATION = 80 µ s DUTY CYCLE = 0.5%MAX TJ = 150oC TJ = 25oC ID = -13A rDS(on), DRAIN TO SOURCE ON-RESISTANCE (mΩ) -VGS, GATE TO SOURCE VOLTAGE (V) 10 On-Resistance vs Gate to Source Voltage Figure 5. Transfer Characteristics 2.0 2.5 3.0 3.5 4.0 4.5 0 10 20 30 40 50 60 70 PULSE DURATION = 80 µ s DUTY CYCLE = 0.5%MAX T J = -55 o C T J = 25 o C TJ = 150 o C -ID, DRAIN CURRENT (A) -VGS, GATE TO SOURCE VOLTAGE (V) Figure 6. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1E-3 0.01 0.11 10 100 T J = -55 o C T J = 25 o C TJ = 150 o C VGS = 0V -IS, REVERSE DRAIN CURRENT (A) -VSD, BODY DIODE FORWARD VOLTAGE (V) Source to Drain Diode Forward Voltage vs Source Current FDS6679AZ P-Channel PowerTrench® MOSFET ©2009 Fairchild Semiconductor Corporation 4 www.fairchildsemi.com FDS6679AZ Rev. B2 Figure 7. 0 15 30 45 60 75 02468 10 VDD = -20V VDD = -10V -VGS, GATE TO SOURCE VOLTAGE(V) Q g, GATE CHARGE(nC) VDD = -15V Gate Charge Characteristics Figure 8. 0.1 1 10 100 1000 10000 f = 1MHz VGS = 0V CAPACITANCE (pF) -VDS, DRAIN TO SOURCE VOLTAGE (V) Crss Coss Ciss 30 Capacitance vs Drain to Source Voltage Figure 9. I g vs VGS 0 5 10 15 20 25 30 35 1E-4 1E-3 0.01 0.11 10 100 1000 TJ = 150 o CT J = 25 o C -Ig(uA) -VGS(V) Figure 10. 10-2 10-1 10 0 10 1 10 2 1 10 TJ = 25 o C TJ = 125 o C -IAS, AVALANCHE CURRENT(A) 20 t AV, TIME IN AVALANCHE(ms) Unclamped Inductive Switching Capability Figure 11. 25 50 75 100 125 150 02468 10 12 14 16 VGS = -10V VGS = -4.5V -ID, DRAIN CURRENT (A) TA, AMBIENT TEMPERATURE ( o C ) Maximum Continuous Drain Current vs Ambient Temperature Figure 12. Forward Bias Safe Operating Area 0.01 0.1 1 10 100 0.01 0.11 10 100 100 us 1 s 10 s DC 100 ms 10 ms 1 ms ID, DRAIN CURRENT (A) VDS, DRAIN to SOURCE VOLTAGE (V) THIS AREA IS LIMITED BY rDS(on) SINGLE PULSE TJ = MAX RATED RθJA = 125 o C/W TA = 25 o C 200 Typical Characteristics T J = 25°C unless otherwise noted FDS6679AZ P-Channel PowerTrench® MOSFET ©2009 Fairchild Semiconductor Corporation 5 www.fairchildsemi.com FDS6679AZ Rev. B2 Figure 13. 10-4 10-3 10-2 10-1 1 10 10 2 10 3 0.51 10 10 2 10 3 10 4 SINGLE PULSE RθJA = 125 o C/W TA = 25 o C VGS = -10 V P(PK), PEAK TRANSIENT POWER (W) t, PULSE WIDTH (sec) Single Pulse Maximum Power Dissipation Figure 14. 10-4 10-3 10-2 10-1 1 10 10 2 10 3 10-4 10-3 10-2 10-11 SINGLE PULSE RθJA = 125 o C/W DUTY CYCLE-DESCENDING ORDER NORMALIZED THERMAL IMPEDANCE, ZθJA t, RECTANGULAR PULSE DURATION (sec) D = 0.5 0.2 0.1 0.05 0.02 0.01 2 PDM t 1 t 2 NOTES: DUTY FACTOR: D = t 1/t 2 PEAK T J = PDM x Z θJA x R θJA + TA Junction-to-Ambient Transient Thermal Response Curve Typical Characteristics T J = 25°C unless otherwise noted 6 www.fairchildsemi.com FDS6679AZ P-Channel PowerTrench ® MOSFET ©2009 Fairchild Semiconductor Corporation FDS6679AZ Rev. B2 Rev. I39 TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Build it Now™ CorePLUS™ CorePOWER™ CROSSVOLT™ CTL™ Current Transfer Logic™ EcoSPARK® EfficentMax™ EZSWITCH™ * ™ Fairchild® Fairchild Semiconductor® FACT Quiet Series™ FACT® FAST® FastvCore™ FlashWriter® * FPS™ F-PFS™ FRFET® Global Power ResourceSM Green FPS™ Green FPS™ e-Series™ GTO™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MillerDrive™ MotionMax™ Motion-SPM™ OPTOLOGIC® OPTOPLANAR® ® PDP SPM™ Power-SPM™ PowerTrench® PowerXS™ Programmable Active Droop™ QFET® QS™ Quiet Series™ RapidConfigure™ ™ Saving our world, 1mW /W /kW at a time™ SmartMax™ SMART START™ SPM® STEALTH™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SupreMOS™ SyncFET™ ® The Power Franchise® TinyBoost™ TinyBuck™ TinyLogic® TINYOPTO™ TinyPower™ TinyPWM™ TinyWire™ TriFault Detect™ TRUECURRENT™* µSerDes™ UHC® Ultra FRFET™ UniFET™ VCX™ VisualMax™ XS™ tm ® tm tm Datasheet Identification Product Status Definition Advance Information Formative / In Design Datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. ANTI-COUNTERFEITING POLICY Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website, www.Fairchildsemi.com, under Sales Support. Counterfeiting of semiconductor parts is a growing problem in the industry. All manufactures of semiconductor products are experiencing counterfeiting of their parts. Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed application, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild Distributors who are listed by country on our web page cited above. Products customers buy either from fairchild directly or from Authorized Fairchild Distributors are genuine parts, have full traceability, meet Fairchild’s quality standards for handing and storage and provide access to Fairchild’s full range of up-to-date technical and product information. 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Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail. － FC32 － Plastic Film Capacitors Metallized Polyester Film Capacitor Type:ECQE(F) Non-inductive construction using metallized Polyester film with flame retardant epoxy resin coating ■Features •Self-healing property •Excellent electrical characteristics •Flame retardant epoxy resin coating •RoHS directive compliant ■Recommended Applications •General purpose usage ❈Please contact us when applications are CD , ignitor etc. ■Explanation of Part Numbers 1 2 3 4 5 6 7 8 9 10 11 12 E C Q E Product code Dielectric & construction Rated volt. Capacitance F Cap. Tol. Suffix Suffix 1 2 4 6 100 VDC 250 VDC 400 VDC 630 VDC 10 12 1A 2A 1000 VDC 1250 VDC 125 VAC 250 VAC J K ±5 % ±10 % E C Q E Product code Dielectric & construction Rated volt. Capacitance R F Suffix Cap. Tol. Suffix ■Specifications ●Explanation of Part Number for Odd Size Taping Category temp. range (Including temperature-rise on unit surface) Rated voltage Capacitance range Capacitance tolerance Dissipation factor (tan ) Withstand voltage Insulation resistance (IR) 100 VDC, 250 VDC,400 VDC, 630 VDC, 1000 VDC, 1250 VDC, 125 VAC, 250 VAC –40 ˚C to +105 ˚C –40 ˚C to +105 ˚C 100 VDC, 250 VDC, 400 VDC, 630 VDC, 1000 VDC, 1250 VDC, (Derating of rated voltage by 1.25 %/˚C at more than 85 ˚C) 125 VAC, 250 VAC 0.0010 µF to 10 µF (E12) ±5 %(J), ±10 %(K) tan <=1.0 % (20 ˚C, 1 kHz) •Rated volt. 100 V to 630 VDC Between terminals : Rated volt.(VDC)✕150 % 60 s •Rated volt. 1000 VDC, 1250 VDC Between terminals : Rated volt. (VDC)✕175 % 2 s to 5 s or 1000 VAC 60 s Between terminals to enclosure : 1500 VAC 60 s •Rated volt. 125 VAC, 250 VAC Between terminals : Rated volt.(VAC)✕230 % 60 s Between terminals to enclosure : 1500 VAC 60 s 100 V to 630 VDC: C <= 0.33 µF : IR>=9000 MΩ (20 ˚C, 100 VDC, 60 s) C > 0.33 µF : IR>=3000 MΩ . µF 1000 VDC, 1250 VDC: IR>=10000 MΩ (20 ˚C, 100 VDC, 60 s) IR>=2000 MΩ (20 ˚C, 500 VDC, 60 s) 125 VAC, 250 VAC: C <= 0.47 µF : IR>=2000 MΩ (20 ˚C, 500 VDC, 60 s) C > 0.47 µF : IR>=3000 MΩ . µF (20 ˚C, 100 VDC, 60 s) ❈ In case of applying voltage in alternating current (50 Hz or 60 Hz sine wave) to a capacitor with DC rated voltage, please refer to the page of “Permissible voltage (R.M.S) in alternating current corresponding to DC rated voltage”. ❈ Voltage to be applied to ECQE1A (F) & ECQE2A (F) is only sine wave (50 Hz or 60 Hz). Suffix Blank B Z 3 6 Lead Form Straight Crimped lead Cut lead Crimped taping (Ammo) Crimped taping (Ammo) p Œ ¯ ¶ ‚ /P33-52 12.11.14 19:29 y [ W 32 Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use. Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail. － FC33 － Plastic Film Capacitors ■Dimensions in mm (not to scale) Cut lead ■Packaging Specifications for Bulk Package Packing quantity:100 pcs./bag ■Taping Specifications for Automatic Insertion ●Taping style ❈Refer to the page of taping specifications. 100 VDC 250 VDC 400 VDC 630 VDC 1000 VDC 1250 VDC 125 VAC 250 VAC ECQE (F) AD AS AB BCD E 0.56 to 0.68 ○ Ammo ( ) F3 0.82 to 1.0 ○ Ammo ( ) F3 1.2 to 3.3 ○ Ammo ( ) F3 1.2 to 3.3 ○ Ammo R( ) F 0.010 to 0.27 ○ Ammo ( ) F3 0.33 ○ Ammo ( ) F3 0.39 to 1.5 ○ Ammo ( ) F3 0.010 to 0.33 ○ Ammo R( ) F 0.39 to 1.5 ○ Ammo R( ) F 0.010 to 0.10 ○ Ammo ( ) F3 0.12 to 0.47 ○ Ammo ( ) F3 0.010 to 0.10 ○ Ammo R( ) F 0.12 to 0.47 ○ Ammo R( ) F 0.0010 to 0.033 ○ Ammo ( ) F3 0.039 to 0.047 ○ Ammo ( ) F3 0.056 to 0.22 ○ Ammo ( ) F3 0.0010 to 0.047 ○ Ammo R( ) F 0.056 to 0.22 ○ Ammo R( ) F 0.010 to 0.10 ○ Ammo R( ) F 0.0010 to 0.022 ○ Ammo R( ) F 0.010 to 0.068 ○ Ammo ( ) F6 0.010 to 0.068 ○ Ammo R( ) F 0.010 to 0.033 ○ Ammo ( ) F6 0.010 to 0.047 ○ Ammo R( ) F 0.056 to 0.22 ○ Ammo R( ) F ●Packaging Specifications Cap. range (µF) Taping style Type Rated volt. Packing suffix Style AD AB B C D E Lead Spacing 5.0 mm 5.0 mm 5.0 mm 5.0 mm 7.5 mm 7.5 mm ❈See the column “Rating, Dimensions & Quantity Box” for packing quantity. ●Lead Spacing Metallized Film p Œ ¯ ¶ ‚ /P33-52 12.11.14 19:29 y [ W 33 Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use. Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail. － FC34 － Plastic Film Capacitors ■Rating, Dimensions & Quantity/Ammo Box ●Rated voltage : 250 VDC, Capacitance tolerance : ±5 %(J), ±10 %(K) Style D: 0.010 µF to 0.33 µF Style B: 0.39 µF to 10.0 µF Suffix for lead crimped or taped type Cap. tol. code ▲ ▲ Suffix for lead crimped or taped type Cap. tol. code ▲ ▲ ■Rating, Dimensions & Quantity/Ammo Box ●Rated voltage : 100 VDC, Capacitance tolerance : ± 5 %(J), ±10 %(K) 0.56 12.0 5.5 10.9 15.9 10.0 10.0 1.0 0.60 0.68 12.0 6.0 11.9 16.9 10.0 10.0 1.0 0.60 0.82 12.0 6.0 13.5 18.5 10.0 10.0 1.0 0.60 1.0 12.0 6.7 14.0 19.0 10.0 10.0 1.0 0.60 1.2 18.5 5.5 12.8 17.8 15.0 10.0 1.0 0.60 1.5 18.5 6.0 13.4 18.4 15.0 10.0 1.0 0.80 1.8 18.5 6.5 14.4 19.4 15.0 10.0 1.0 0.80 2.2 18.5 7.0 15.0 20.0 15.0 10.0 1.0 0.80 2.7 18.5 8.0 15.8 20.8 15.0 10.0 1.0 0.80 3.3 18.5 8.5 16.5 21.5 15.0 10.0 1.0 0.80 3.9 26.0 7.0 16.4 21.4 22.5 15.0 1.0 0.80 4.7 26.0 7.5 17.0 22.0 22.5 15.0 1.0 0.80 5.6 26.0 8.3 17.5 22.5 22.5 15.0 1.0 0.80 6.8 26.0 9.0 18.5 23.5 22.5 15.0 1.0 0.80 8.2 26.0 10.0 20.0 25.0 22.5 15.0 1.5 0.80 10.0 26.0 11.5 21.0 26.0 22.5 15.0 1.5 0.80 Part No. Cap. (µF) Min. order Q'ty Taping 500 － － － － Dimensions (mm) L max. T max. Standard 5 mm Odd size 5 mm Odd size 7.5 mm ø d ECQE1564□F( ) ECQE1684□F( ) ECQE1824□F( ) ECQE1105□F( ) ECQE1125□F( ) ECQE1155□F( ) ECQE1185□F( ) ECQE1225□F( ) ECQE1275□F( ) ECQE1335□F( ) ECQE1395□F( ) ECQE1475□F( ) ECQE1565□F( ) ECQE1685□F( ) ECQE1825□F( ) ECQE1106□F( ) 500 1,000 400 400 500 600 － H max. Straight Crimped lead Straight F Crimped lead S Straight G max. Bulk 500 style D: 0.056 µF to 1.0 µF style B: 1.2 µF to 10.0 µF Part No. Cap. (µF) Dimensions (mm) L max. T max. ø d ECQE2103□F( ) 0.010 10.3 4.3 7.4 12.4 7.5 7.5 1.0 0.60 ECQE2123□F( ) 0.012 10.3 4.4 7.5 12.5 7.5 7.5 1.0 0.60 ECQE2153□F( ) 0.015 10.3 4.4 7.5 12.5 7.5 7.5 1.0 0.60 ECQE2183□F( ) 0.018 10.3 4.4 7.5 12.5 7.5 7.5 1.0 0.60 ECQE2223□F( ) 0.022 10.3 4.4 7.5 12.5 7.5 7.5 1.0 0.60 ECQE2273□F( ) 0.027 10.3 4.4 7.5 12.5 7.5 7.5 1.0 0.60 ECQE2333□F( ) 0.033 10.3 4.5 7.5 12.5 7.5 7.5 1.0 0.60 ECQE2393□F( ) 0.039 10.3 4.5 7.5 12.5 7.5 7.5 1.0 0.60 ECQE2473□F( ) 0.047 10.3 4.5 7.5 12.5 7.5 7.5 1.0 0.60 ECQE2563□F( ) 0.056 10.3 4.8 7.9 12.9 7.5 7.5 1.0 0.60 ECQE2683□F( ) 0.068 10.3 4.5 7.5 12.5 7.5 7.5 1.0 0.60 ECQE2823□F( ) 0.082 10.3 4.9 8.0 13.0 7.5 7.5 1.0 0.60 ECQE2104□F( ) 0.10 10.3 5.8 8.4 13.4 7.5 7.5 1.0 0.60 ECQE2124□F( ) 0.12 10.3 6.0 9.0 14.0 7.5 7.5 1.0 0.60 ECQE2154□F( ) 0.15 10.3 6.0 10.8 15.8 7.5 7.5 1.0 0.60 ECQE2184□F( ) 0.18 12.0 5.0 10.3 15.3 10.0 10.0 1.0 0.60 ECQE2224□F( ) 0.22 12.0 5.5 10.5 15.5 10.0 10.0 1.0 0.60 ECQE2274□F( ) 0.27 12.0 6.0 11.5 16.5 10.0 10.0 1.0 0.60 ECQE2334□F( ) 0.33 12.0 6.5 12.0 17.0 10.0 10.0 1.0 0.60 ECQE2394□F( ) 0.39 18.5 4.9 12.0 17.0 15.0 10.0 1.0 0.60 ECQE2474□F( ) 0.47 18.5 5.3 12.5 17.5 15.0 10.0 1.0 0.60 ECQE2564□F( ) 0.56 18.5 5.5 13.0 18.0 15.0 10.0 1.0 0.60 ECQE2684□F( ) 0.68 18.5 6.0 13.5 18.5 15.0 10.0 1.0 0.80 ECQE2824□F( ) 0.82 18.5 6.5 14.5 19.5 15.0 10.0 1.0 0.80 ECQE2105□F( ) 1.0 18.5 7.4 15.0 20.0 15.0 10.0 1.0 0.80 ECQE2125□F( ) 1.2 18.5 8.0 15.9 20.9 15.0 10.0 1.0 0.80 ECQE2155□F( ) 1.5 18.5 9.0 16.8 21.8 15.0 10.0 1.0 0.80 ECQE2185□F( ) 1.8 26.0 7.5 15.5 20.5 22.5 15.0 1.0 0.80 ECQE2225□F( ) 2.2 26.0 8.5 16.3 21.3 22.5 15.0 1.0 0.80 ECQE2275□F( ) 2.7 26.0 9.4 17.0 22.0 22.5 15.0 1.0 0.80 ECQE2335□F( ) 3.3 26.0 10.3 18.0 23.0 22.5 15.0 1.5 0.80 ECQE2395□F( ) 3.9 26.0 11.0 20.5 25.5 22.5 15.0 1.5 0.80 ECQE2475□F( ) 4.7 26.0 12.0 21.5 26.5 22.5 15.0 1.5 0.80 ECQE2565□F( ) 5.6 31.0 11.8 21.0 26.0 27.5 22.5 1.5 0.80 ECQE2685□F( ) 6.8 31.0 13.0 22.4 27.4 27.5 22.5 1.5 0.80 ECQE2825□F( ) 8.2 31.0 14.3 23.5 28.5 27.5 22.5 1.5 0.80 ECQE2106□F( )10.0 31.0 15.9 25.8 30.8 27.5 22.5 1.5 0.80 1000 － － 1000 500 500 1000 400 500 400 300 － － H max. Straight Crimped lead Straight F Crimped lead S Straight G max. 500 Min. order Q'ty Taping Standard 5 mm Odd size 5 mm Odd size 7.5 mm Bulk p Œ ¯ ¶ ‚ /P33-52 12.11.14 19:29 y [ W 34 Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use. Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail. － FC35 － Plastic Film Capacitors ■Rating, Dimensions & Quantity/Ammo Box ●Rated voltage : 400 VDC, Capacitance tolerance : ±5 %(J), ±10 %(K) style D:0.010 µF to 0.10 µF style B:0.12 µF to 2.2 µF Suffix for lead crimped or taped type Cap. tol. code ▲ ▲ Part No. 0.010 10.3 4.3 7.4 12.4 7.5 7.5 1.0 0.60 0.012 10.3 4.4 7.5 12.5 7.5 7.5 1.0 0.60 0.015 10.3 4.4 7.5 12.5 7.5 7.5 1.0 0.60 0.018 10.3 4.4 7.5 12.5 7.5 7.5 1.0 0.60 0.022 10.3 4.8 7.9 12.9 7.5 7.5 1.0 0.60 0.027 10.3 5.5 8.0 13.0 7.5 7.5 1.0 0.60 0.033 10.3 6.0 9.0 14.0 7.5 7.5 1.0 0.60 0.039 12.0 4.9 8.0 13.0 10.0 10.0 1.0 0.60 0.047 12.0 5.0 8.3 13.3 10.0 10.0 1.0 0.60 0.056 12.0 5.0 10.0 15.0 10.0 10.0 1.0 0.60 0.068 12.0 5.4 10.5 15.5 10.0 10.0 1.0 0.60 0.082 12.0 5.8 11.0 16.0 10.0 10.0 1.0 0.60 0.10 12.0 6.3 12.0 17.0 10.0 10.0 1.0 0.60 0.12 18.5 5.0 10.0 15.0 15.0 10.0 1.0 0.60 0.15 18.5 5.0 12.4 17.4 15.0 10.0 1.0 0.60 0.18 18.5 5.4 12.5 17.5 15.0 10.0 1.0 0.60 0.22 18.5 5.9 13.0 18.0 15.0 10.0 1.0 0.60 0.27 18.5 6.5 14.3 19.3 15.0 10.0 1.0 0.80 0.33 18.5 7.0 14.9 19.9 15.0 10.0 1.0 0.80 0.39 18.5 7.5 15.4 20.4 15.0 10.0 1.0 0.80 0.47 18.5 7.8 17.0 22.0 15.0 10.0 1.0 0.80 0.56 26.0 6.5 16.0 21.0 22.5 15.0 1.0 0.80 0.68 26.0 7.0 16.5 21.5 22.5 15.0 1.0 0.80 0.82 26.0 7.9 17.3 22.3 22.5 15.0 1.0 0.80 1.0 26.0 8.5 18.0 23.0 22.5 15.0 1.0 0.80 1.2 26.0 9.5 18.9 23.9 22.5 15.0 1.0 0.80 1.5 31.0 9.5 19.0 24.0 27.5 22.5 1.0 0.80 1.8 31.0 11.0 20.5 25.5 27.5 22.5 1.5 0.80 2.2 31.0 11.0 22.0 27.0 27.5 22.5 1.5 0.80 ECQE4103□F( ) ECQE4123□F( ) ECQE4153□F( ) ECQE4183□F( ) ECQE4223□F( ) ECQE4273□F( ) ECQE4333□F( ) ECQE4393□F( ) ECQE4473□F( ) ECQE4563□F( ) ECQE4683□F( ) ECQE4823□F( ) ECQE4104□F( ) ECQE4124□F( ) ECQE4154□F( ) ECQE4184□F( ) ECQE4224□F( ) ECQE4274□F( ) ECQE4334□F( ) ECQE4394□F( ) ECQE4474□F( ) ECQE4564□F( ) ECQE4684□F( ) ECQE4824□F( ) ECQE4105□F( ) ECQE4125□F( ) ECQE4155□F( ) ECQE4185□F( ) ECQE4225□F( ) Cap. (µF) 1000 500 － － 500 500 400 － － 1000 Dimensions (mm) L max. T max. φd H max. Straight Crimped lead Straight F Crimped lead S Straight G max. 500 Min. order Q'ty Taping Standard 5 mm Odd size 5 mm Odd size 7.5 mm Bulk Metallized Film p Œ ¯ ¶ ‚ /P33-52 12.11.14 19:29 y [ W 35 Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use. Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail. － FC36 － Plastic Film Capacitors ●Rated voltage : 630 VDC, Capacitance tolerance : ±5 %(J), ±10 %(K) Suffix for lead crimped or taped type. Cap. tol. code ▲ ▲ style D:0.010 µF to 0.047 µF style B:0.0010 µF to 0.0082 µF, 0.056 µF to 2.2 µF Part No. 0.0010 10.0 4.5 9.5 14.5 7.5 5.0 1.0 0.60 0.0012 10.0 4.5 10.0 15.0 7.5 5.0 1.0 0.60 0.0015 10.0 4.5 10.0 15.0 7.5 5.0 1.0 0.60 0.0018 10.0 4.5 10.0 15.0 7.5 5.0 1.0 0.60 0.0022 10.0 4.5 10.0 15.0 7.5 5.0 1.0 0.60 0.0027 10.0 4.5 10.0 15.0 7.5 5.0 1.0 0.60 0.0033 10.0 4.5 10.0 15.0 7.5 5.0 1.0 0.60 0.0039 10.0 4.5 10.0 15.0 7.5 5.0 1.0 0.60 0.0047 12.0 4.5 10.0 15.0 10.0 7.5 1.0 0.60 0.0056 12.0 4.5 10.0 15.0 10.0 7.5 1.0 0.60 0.0068 12.0 4.9 10.0 15.0 10.0 7.5 1.0 0.60 0.0082 12.0 4.5 10.0 15.0 10.0 7.5 1.0 0.60 0.010 12.0 4.5 7.5 12.5 10.0 10.0 1.0 0.60 0.012 12.0 4.5 7.8 12.8 10.0 10.0 1.0 0.60 0.015 12.0 5.0 8.2 13.2 10.0 10.0 1.0 0.60 0.018 12.0 4.9 10.0 15.0 10.0 10.0 1.0 0.60 0.022 12.0 5.3 10.5 15.5 10.0 10.0 1.0 0.60 0.027 12.0 5.5 10.9 15.9 10.0 10.0 1.0 0.60 0.033 12.0 6.0 11.9 16.9 10.0 10.0 1.0 0.60 0.039 12.0 6.0 13.4 18.4 10.0 10.0 1.0 0.60 0.047 12.0 6.5 13.5 18.5 10.0 10.0 1.0 0.60 0.056 18.5 5.4 10.5 15.5 15.0 10.0 1.0 0.60 0.068 18.5 5.8 11.0 16.0 15.0 10.0 1.0 0.60 0.082 18.5 6.5 12.0 17.0 15.0 10.0 1.0 0.60 0.10 18.5 6.3 14.0 19.0 15.0 10.0 1.0 0.60 0.12 18.5 6.3 14.5 19.5 15.0 10.0 1.0 0.80 0.15 18.5 7.5 15.4 20.4 15.0 10.0 1.0 0.80 0.18 18.5 8.0 16.0 21.0 15.0 10.0 1.0 0.80 0.22 18.5 9.0 16.5 21.5 15.0 10.0 1.0 0.80 0.27 26.0 7.0 16.5 21.5 22.5 15.0 1.0 0.80 0.33 26.0 7.8 17.0 22.0 22.5 15.0 1.0 0.80 0.39 26.0 8.5 17.9 22.9 22.5 15.0 1.0 0.80 0.47 26.0 9.3 18.5 23.5 22.5 15.0 1.0 0.80 0.56 26.0 10.0 20.0 25.0 22.5 15.0 1.5 0.80 0.68 26.0 11.5 21.0 26.0 22.5 15.0 1.5 0.80 0.82 31.0 11.3 20.5 25.5 27.5 22.5 1.5 0.80 1.0 31.0 12.5 21.9 26.9 27.5 22.5 1.5 0.80 1.2 31.0 13.5 23.0 28.0 27.5 22.5 1.5 0.80 1.5 31.0 15.3 24.7 29.7 27.5 22.5 1.5 0.80 1.8 31.0 16.8 27.0 32.0 27.5 22.5 1.5 0.80 2.2 31.0 19.5 29.0 34.0 27.5 22.5 1.5 0.80 ECQE6102□F( ) ECQE6122□F( ) ECQE6152□F( ) ECQE6182□F( ) ECQE6222□F( ) ECQE6272□F( ) ECQE6332□F( ) ECQE6392□F( ) ECQE6472□F( ) ECQE6562□F( ) ECQE6682□F( ) ECQE6822□F( ) ECQE6103□F( ) ECQE6123□F( ) ECQE6153□F( ) ECQE6183□F( ) ECQE6223□F( ) ECQE6273□F( ) ECQE6333□F( ) ECQE6393□F( ) ECQE6473□F( ) ECQE6563□F( ) ECQE6683□F( ) ECQE6823□F( ) ECQE6104□F( ) ECQE6124□F( ) ECQE6154□F( ) ECQE6184□F( ) ECQE6224□F( ) ECQE6274□F( ) ECQE6334□F( ) ECQE6394□F( ) ECQE6474□F( ) ECQE6564□F( ) ECQE6684□F( ) ECQE6824□F( ) ECQE6105□F( ) ECQE6125□F( ) ECQE6155□F( ) ECQE6185□F( ) ECQE6225□F( ) Cap. (µF) 1000 － 1000 500 400 300 1000 500 400 － － 500 － Dimensions (mm) L max. T max. φd H max. Straight Crimped lead Straight F Crimped lead S Straight G max. 500 Min. order Q'ty Taping Standard 5 mm Odd size 5 mm Odd size 7.5 mm Bulk p Œ ¯ ¶ ‚ /P33-52 12.11.14 19:29 y [ W 36 Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use. Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail. － FC37 － Plastic Film Capacitors ■Rating, Dimensions & Quantity/Ammo Box ●Rated voltage : 1000 VDC, Note) 125 VAC, Capacitance tolerance : ±5 %(J), ±10 %(K) Note) This type has two rated voltage, one is DC rated voltage another is AC rated voltage.. DC rated voltage is 1000 V, AC rated voltage is 125 V. Making for rated voltage is「1000 V, 125 V 」 When capacitors use in secondary side of power source, and in case of applying voltage in altering current (50 Hz or 60 Hz sine wave) to a capacitor, please refer to the page of ''Permissible voltage (R.M.S) in altering current corresponding to DC rated voltage''. When capacitors use in primary side of power source, the rated voltage is shown 125 VAC. Voltage to be applied to capacitors in only sine wave (50 Hz or 60 Hz). AC rated capacitors complying with clause 1 of ''Electrical Appliance and Material Safety Law''. And not complying with clause 2 of ''Electrical Appliance and Material Safety Law'', in this case please use ECQUL type or ECQUG type Part No. 0.010 15.5 6.0 11.0 16.0 12.5 12.5 1.0 0.60 0.012 15.5 6.0 12.0 17.0 12.5 12.5 1.0 0.60 0.015 15.5 7.0 12.5 17.5 12.5 12.5 1.0 0.60 0.018 15.5 7.5 13.0 20.0 12.5 12.5 1.0 0.80 0.022 15.5 7.5 15.5 22.5 12.5 12.5 1.0 0.80 0.027 21.0 6.0 13.0 18.0 17.5 12.5 1.0 0.80 0.033 21.0 6.5 14.0 19.0 17.5 12.5 1.0 0.80 0.039 21.0 7.0 14.5 19.5 17.5 12.5 1.0 0.80 0.047 21.0 7.5 15.5 20.5 17.5 12.5 1.0 0.80 0.056 21.0 7.5 17.0 22.0 17.5 12.5 1.0 0.80 0.068 21.0 8.5 18.0 23.0 17.5 12.5 1.0 0.80 0.082 21.0 9.0 18.5 23.5 17.5 12.5 1.0 0.80 0.10 21.0 10.0 20.0 25.0 17.5 12.5 1.0 0.80 0.12 26.0 9.0 18.5 23.5 22.5 17.5 1.0 0.80 0.15 26.0 10.0 20.0 25.0 22.5 17.5 1.5 0.80 0.18 26.0 10.5 22.0 27.0 22.5 17.5 1.5 0.80 0.22 26.0 12.0 23.0 28.0 22.5 17.5 1.5 0.80 ECQE10103□F( ) ECQE10123□F( ) ECQE10153□F( ) ECQE10183□F( ) ECQE10223□F( ) ECQE10273□F( ) ECQE10333□F( ) ECQE10393□F( ) ECQE10473□F( ) ECQE10563□F( ) ECQE10683□F( ) ECQE10823□F( ) ECQE10104□F( ) ECQE10124□F( ) ECQE10154□F( ) ECQE10184□F( ) ECQE10224□F( ) Cap. (µF) Min. order Q'ty 500 400 500 400 300 － Dimensions (mm) L max. T max. ø d 7.5 mm H max. Straight Crimped lead Straight F Crimped lead S Straight G max. 500 Bulk Taping Style D: 0.010 µF to 0.022 µF Style B: 0.027 µF to 0.22 µF Suffix for lead crimped or taped type. Cap. tol. code ▲ ▲ Metallized Film p Œ ¯ ¶ ‚ /P33-52 12.11.14 19:29 y [ W 37 Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use. Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail. － FC38 － Plastic Film Capacitors ■Rating, Dimensions & Quantity/Ammo Box ●Rated voltage : 1250 VDC, Note) 125 VAC, Capacitance tolerance : ±5 %(J), ±10 %(K) Note) This type has two rated voltage, one is DC rated voltage another is AC rated voltage.. DC rated voltage is 1250 V, AC rated voltage is 125 V. Making for rated voltage is「1250 V, 125 V 」 When capacitors use in secondary side of power source, and in case of applying voltage in altering current (50 Hz or 60 Hz sine wave) to a capacitor, please refer to the page of ''Permissible voltage (R.M.S) in altering current corresponding to DC rated voltage''. When capacitors use in primary side of power source, the rated voltage is shown 125 VAC. Voltage to be applied to capacitors in only sine wave (50 Hz or 60 Hz). AC rated capacitors complying with clause 1 of ''Electrical Appliance and Material Safety Law''. And not complying with clause 2 of ''Electrical Appliance and Material Safety Law'', in this case please use ECQUL type or ECQUG type Style D: 0.0010 µF to 0.0068 µF Style B: 0.0082 µF to 0.22 µF Part No. 0.0010 15.5 6.0 11.0 16.0 12.5 10.0 1.0 0.60 0.0012 15.5 6.0 11.0 16.0 12.5 10.0 1.0 0.60 0.0015 15.5 6.0 11.0 16.0 12.5 10.0 1.0 0.60 0.0018 15.5 6.0 11.0 16.0 12.5 10.0 1.0 0.60 0.0022 15.5 6.0 11.5 16.5 12.5 10.0 1.0 0.60 0.0027 15.5 6.5 12.0 17.0 12.5 10.0 1.0 0.60 0.0033 15.5 6.0 11.5 16.5 12.5 10.0 1.0 0.60 0.0039 15.5 6.5 12.0 17.0 12.5 10.0 1.0 0.60 0.0047 15.5 7.0 12.5 17.5 12.5 10.0 1.0 0.60 0.0056 15.5 7.5 13.0 18.0 12.5 10.0 1.0 0.60 0.0068 15.5 7.5 15.0 20.0 12.5 10.0 1.0 0.60 0.0082 21.0 5.0 12.0 17.0 17.5 12.5 1.0 0.60 0.010 21.0 5.0 12.5 17.5 17.5 12.5 1.0 0.60 0.012 21.0 5.5 13.0 18.0 17.5 12.5 1.0 0.60 0.015 21.0 6.0 13.5 18.5 17.5 12.5 1.0 0.60 0.018 21.0 6.5 14.5 19.5 17.5 12.5 1.0 0.80 0.022 21.0 7.0 15.0 20.0 17.5 12.5 1.0 0.80 0.027 26.0 6.0 15.5 20.5 22.5 17.5 1.0 0.80 0.033 26.0 6.5 16.0 21.0 22.5 17.5 1.0 0.80 0.039 26.0 7.0 16.5 21.5 22.5 17.5 1.0 0.80 0.047 26.0 8.0 17.0 22.0 22.5 17.5 1.0 0.80 0.056 31.0 7.5 17.0 22.0 27.5 22.5 1.0 0.80 0.068 31.0 8.0 17.5 22.5 27.5 22.5 1.0 0.80 0.082 31.0 9.0 18.5 23.5 27.5 22.5 1.0 0.80 0.10 31.0 10.0 19.5 24.5 27.5 22.5 1.0 0.80 0.12 31.0 11.5 20.5 25.5 27.5 22.5 1.5 0.80 0.15 31.0 12.0 23.0 28.0 27.5 22.5 1.5 0.80 0.18 31.0 13.0 24.5 29.5 27.5 22.5 1.5 0.80 0.22 31.0 14.5 26.5 31.5 27.5 22.5 1.5 0.80 ECQE12102□F( ) ECQE12122□F( ) ECQE12152□F( ) ECQE12182□F( ) ECQE12222□F( ) ECQE12272□F( ) ECQE12332□F( ) ECQE12392□F( ) ECQE12472□F( ) ECQE12562□F( ) ECQE12682□F( ) ECQE12822□F( ) ECQE12103□F( ) ECQE12123□F( ) ECQE12153□F( ) ECQE12183□F( ) ECQE12223□F( ) ECQE12273□F( ) ECQE12333□F( ) ECQE12393□F( ) ECQE12473□F( ) ECQE12563□F( ) ECQE12683□F( ) ECQE12823□F( ) ECQE12104□F( ) ECQE12124□F( ) ECQE12154□F( ) ECQE12184□F( ) ECQE12224□F( ) Cap. (µF) Min. order Q'ty 500 400 500 Dimensions (mm) L max. T max. ø d 7.5 mm H max. Straight Crimped lead Straight F Crimped lead S Straight G max. Bulk Taping 500 Suffix for lead crimped or taped type. Cap. tol. code ▲ ▲ p Œ ¯ ¶ ‚ /P33-52 12.11.14 19:29 y [ W 38 Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use. Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail. － FC39 － Plastic Film Capacitors ■Rating, Dimensions & Quantity/Ammo Box ●Rated voltage : 125 VAC, Capacitance tolerance : ±5 %(J), ±10 %(K) ●Noise suppression Capacitors (Across-the-line) style D:0.010 µF to 0.068 µF Suffix for lead crimped or taped type. Cap. tol. code MF( ) Table 1 Notice for AC rated AC rated capacitors complying with clause 1 of ''Electrical Appliance and Material Safety Law''. As for clause 2 of ''Electrical Appliance and Material Safety Law'', please use ECQUL type or ECQUG type. When using these capacitors as a across-the-line capacitor, it shall be required to follow either item 1. or item 2. condition. 1. Capacitor shall be connected in parallel with varistor (Specified varistor voltage in table 1.) 2. Voltage applied for capacitor shall not exceed other than specified in table 1, when using these capacitors. Cap. Rated Voltage 125 VAC Varistor voltage 250 V Pulse voltage 250 V0–P Part No. 0.010 10.5 4.5 7.5 12.5 7.5 7.5 1.0 0.60 0.012 10.5 4.4 7.5 12.5 7.5 7.5 1.0 0.60 0.015 10.5 4.4 7.5 12.5 7.5 7.5 1.0 0.60 0.018 10.5 4.4 7.5 12.5 7.5 7.5 1.0 0.60 0.022 10.5 4.4 7.5 12.5 7.5 7.5 1.0 0.60 0.027 10.5 4.4 7.5 12.5 7.5 7.5 1.0 0.60 0.033 10.5 4.5 7.8 12.8 7.5 7.5 1.0 0.60 0.039 10.5 4.5 7.8 12.8 7.5 7.5 1.0 0.60 0.047 10.5 5.5 8.0 13.0 7.5 7.5 1.0 0.60 0.056 10.5 5.9 8.5 13.5 7.5 7.5 1.0 0.60 0.068 10.5 6.3 9.4 14.4 7.5 7.5 1.0 0.60 ECQE1A103□F( ) ECQE1A123□F( ) ECQE1A153□F( ) ECQE1A183□F( ) ECQE1A223□F( ) ECQE1A273□F( ) ECQE1A333□F( ) ECQE1A393□F( ) ECQE1A473□F( ) ECQE1A563□F( ) ECQE1A683□F( ) Cap. (µF) 1000 － 1000 500 Dimensions (mm) L max. T max. φd H max. Straight Crimped lead Straight F Crimped lead S Straight G max. 500 Min. order Q'ty Taping Standard 5 mm Odd size 5 mm Odd size 7.5 mm Bulk Metallized Film p Œ ¯ ¶ ‚ /P33-52 12.11.14 19:29 y [ W 39 Design, Specifications are subject to change without notice. Ask factory for technical specifications before purchase and/or use. Whenever a doubt about safety arises from this product, please inform us immediately for technical consultation without fail. － FC40 － Plastic Film Capacitors ●Rated voltage : 250 VAC, Capacitance tolerance : ±5 %(J), ±10 %(K) Noise suppression Capacitors (Across-the-line) Style D:0.010 µF to 0.047 µF Style B:0.056 µF to 0.47 µF Table 1 ❈Please consult us about Crimed lead type of 0.56 µF to 2.2 µF. Notice for AC rated AC rated capacitors complying with clause 1 of ''Electrical Appliance and Material Safety Law''. As for clause 2 of ''Electrical Appliance and Material Safety Law'', please use ECQUL type or ECQUG type. When using these capacitors as a across-the-line capacitor, it shall be required to follow either item 1. or item 2. condition. 1. Capacitor shall be connected in parallel with varistor (Specified varistor voltage in table 1.) 2. Voltage applied for capacitor shall not exceed other than specified in table 1, when using these capacitors. Cap. Rated Voltage 250 VAC Varistor voltage 470 V Pulse voltage 630 V0–P Suffix for lead crimped or taped type. Cap. tol. code MF( ) Part No. 0.010 12.5 5.5 10.8 15.8 10.0 10.0 1.0 0.60 0.012 12.5 6.0 11.5 16.5 10.0 10.0 1.0 0.60 0.015 12.5 6.3 9.9 14.9 10.0 10.0 1.0 0.60 0.018 12.5 6.0 11.9 16.9 10.0 10.0 1.0 0.60 0.022 12.5 6.0 11.5 16.5 10.0 10.0 1.0 0.60 0.027 12.5 5.5 10.9 15.9 10.0 10.0 1.0 0.60 0.033 12.5 6.0 11.9 16.9 10.0 10.0 1.0 0.60 0.039 12.5 6.0 13.4 18.4 10.0 10.0 1.0 0.60 0.047 12.5 6.5 14.4 19.4 10.0 10.0 1.0 0.60 0.056 18.5 5.4 10.5 15.5 15.0 10.0 1.0 0.60 0.068 18.5 5.8 11.0 16.0 15.0 10.0 1.0 0.60 0.082 18.5 6.3 12.0 17.0 15.0 10.0 1.0 0.60 0.10 18.5 6.3 14.0 19.0 15.0 10.0 1.0 0.60 0.12 18.5 6.8 14.5 19.5 15.0 10.0 1.0 0.80 0.15 18.5 7.5 15.4 20.4 15.0 10.0 1.0 0.80 0.18 18.5 8.0 16.0 21.0 15.0 10.0 1.0 0.80 0.22 18.5 9.0 16.9 21.9 15.0 10.0 1.0 0.80 0.27 26.0 7.0 16.5 21.5 22.5 15.0 1.0 0.80 0.33 26.0 7.8 17.0 22.0 22.5 15.0 1.0 0.80 0.39 26.0 8.5 17.9 22.9 22.5 15.0 1.0 0.80 0.47 26.0 9.3 18.5 23.5 22.5 15.0 1.0 0.80 0.56 26.0 10.0 20.0 ─ 22.5 ─ 1.0 0.80 0.68 26.0 11.5 21.0 ─ 22.5 ─ 1.0 0.80 0.82 26.0 13.0 22.5 ─ 22.5 ─ 1.0 0.80 1.0 31.0 12.5 21.9 ─ 27.5 ─ 1.5 0.80 1.2 31.0 13.5 23.0 ─ 27.5 ─ 1.5 0.80 1.5 31.0 15.3 24.7 ─ 27.5 ─ 1.5 0.80 1.8 31.0 16.8 27.0 ─ 27.5 ─ 1.5 0.80 2.2 31.0 19.5 29.0 ─ 27.5 ─ 1.5 0.80 ECQE2A103□F( ) ECQE2A123□F( ) ECQE2A153□F( ) ECQE2A183□F( ) ECQE2A223□F( ) ECQE2A273□F( ) ECQE2A333□F( ) ECQE2A393□F( ) ECQE2A473□F( ) ECQE2A563□F( ) ECQE2A683□F( ) ECQE2A823□F( ) ECQE2A104□F( ) ECQE2A124□F( ) ECQE2A154□F( ) ECQE2A184□F( ) ECQE2A224□F( ) ECQE2A274□F( ) ECQE2A334□F( ) ECQE2A394□F( ) ECQE2A474□F( ) ECQE2A564P( )( ) ECQE2A684P( )( ) ECQE2A824P( )( ) ECQE2A105P( )( ) ECQE2A125P( )( ) ECQE2A155P( )( ) ECQE2A185P( )( ) ECQE2A225P( )( ) Cap. (µF) 500 1000 500 400 300 － － Dimensions (mm) L max. T max. φd H max. Straight Crimped lead Straight F Crimped lead S Straight G max. 500 Min. order Q'ty Taping Standard 5 mm Odd size 7.5 mm Bulk p Œ ¯ ¶ ‚ /P33-52 12.11.14 19:29 y [ W 40 Temperature Characteristics Frequency Characteristics 0.01 0.1 1 10 100 1000 10000 1 10 100 1000 10000 0 2 4 6 8 10 1 10 100 1000 10000 -10 -5 0 5 10 1 10 100 1000 10000 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11 1.E+12 -60 -40 -20 0 20 40 60 80 100 0 2 4 6 8 10 -60 -40 -20 0 20 40 60 80 100 -10 -5 0 5 10 -60 -40 -20 0 20 40 60 80 100 ECQE(F) Type 100VDC Series (Metallized Polyester Film) Erectrical Characteristicsat 1kHz Temperature (Degree C) Capacitance change (%) Dissipation factor (%) Temperature (Degree C) at 1kHz at DC100V Temperature (Degree C) Insuration resistance (ohm) Capacitance change (%) Frequency (kHz) Frequency (kHz) Dissipation factor (%) Frequency (kHz) Impedance (ohm) 10uF 4.7uF 1.0uF 10uF 4.7uF 1.0uF 10uF 4.7uF 1.0uF 10uF 4.7uF 1.0uF 1.0uF 4.7uF 10uF 1.0uF 4.7uF 10uF Rating Voltage Capacitance Value(uF) Code dV/dt(V/us) Current(o-p) (A) 0.56 564 12.32 0.68 684 15.0 0.82 824 18.0 1.00 105 22.0 1.20 125 13.2 1.50 155 17.1 1.80 185 19.8 2.20 225 24.2 2.70 275 29.7 3.30 335 36.3 3.90 395 23.4 4.70 475 28.2 5.60 565 33.6 6.80 685 40.8 8.20 825 49.2 10.00 106 60.0 Pulse Handling Capability (dV/dt) (Max 10000cycles) Voltage Derating by Temperature Permissible Current Permissible Voltage 6 22 100VDC 11 0 20 40 60 80 100 120 -60 -40 -20 0 20 40 60 80 100 120 0.1 1 10 100 10 100 1000 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 10 100 1000 * Please consult Panasonic if your condition exceeds the above spec. ECQE(F) Type 100VDC Series (Metallized Polyester Film) Applicable Specifications Frequency (kHz) Permissible Current (Arms) Permissible Voltage (Vrms) (at sinewave) Frequency (kHz) Rated Voltage (VDC) Surface Temperature of Capacitor(Degree C) 1.0uF 2.2uF 4.7uF 10uF 1.0uF 2.2uF 4.7uF 10uF From 0.56uF to 10uF Temperature Characteristics Frequency Characteristics 0.01 0.1 1 10 100 1000 10000 1 10 100 1000 10000 100000 0 2 4 6 8 10 1 10 100 1000 10000 -10 -5 0 5 10 1 10 100 1000 10000 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11 1.E+12 -60 -40 -20 0 20 40 60 80 100 0 2 4 6 8 10 -60 -40 -20 0 20 40 60 80 100 -10 -5 0 5 10 -60 -40 -20 0 20 40 60 80 100 ECQE(F) Type 250VDC Series (Metallized Polyester Film) Erectrical Characteristics at 1kHz Temperature (Degree C) Capacitance change (%) Dissipation factor (%) Temperature (Degree C) at 1kHz at DC100V Temperature (Degree C) Insuration resistance (ohm) Capacitance change (%) Frequency (kHz) Frequency (kHz) Dissipation factor (%) Frequency (kHz) Impedance (ohm) 10uF 1.0uF 0.1uF 10uF 1.0uF 0.1uF 10uF 1.0uF 0.01uF 10uF 1.0uF 0.1uF 0.1uF 1.0uF 10uF 0.1uF 1.0uF 10uF 0.01uF 0.01uF 0.1uF 0.01uF 0.01uF 0.01uF Rating Voltage Capacitance Value(uF) Code dV/dt(V/us) Current(o-p) (A) 0.010 103 0.48 0.015 153 0.72 0.022 223 1.06 0.033 333 1.58 0.047 473 2.26 0.068 683 3.26 0.100 104 4.80 0.150 154 7.20 0.220 224 7.26 0.330 334 10.89 0.470 474 8.46 0.680 684 12.24 1.000 105 18.00 1.500 155 27.00 2.200 225 22.00 3.300 335 33.00 4.700 475 47.00 6.800 685 54.40 10.000 106 80.00 250VDC Pulse Handling Capability (dV/dt) Voltage Derating by Temperature (Max 10000cycles) 48 8 10 18 33 Permissible Current Permissible Voltage 0 50 100 150 200 250 300 -60 -40 -20 0 20 40 60 80 100 120 1 10 100 10 100 1000 0 1 2 3 4 5 10 100 1000 * Please consult Panasonic if your condition exceeds the above spec. ECQE(F) Type 250VDC Series (Metallized Polyester Film) Applicable Specifications Frequency (kHz) Permissible Current (Arms) Permissible Voltage (Vrms) (at sinewave) Frequency (kHz) Rated Voltage (VDC) Surface Temperature of Capacitor(Degree C) 1.0uF 2.2uF 4.7uF 10uF From 0.01uF to 10uF 0.47uF 0.22uF 0.10uF 0.047u 0.022u 0.01uF 0.01uF 0.022uF 0.047uF 0.10uF 0.22uF 0.47uF 1.0uF 2.2uF 4.7uF 10uF Temperature Characteristics Frequency Characteristics 0.01 0.1 1 10 100 1000 10000 1 10 100 1000 10000 100000 0 2 4 6 8 10 1 10 100 1000 10000 -10 -5 0 5 10 -60 -40 -20 0 20 40 60 80 100 -10 -5 0 5 10 1 10 100 1000 10000 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11 1.E+12 1.E+13 -60 -40 -20 0 20 40 60 80 100 0 2 4 6 8 10 -60 -40 -20 0 20 40 60 80 100 ECQE(F) Type 400VDC Series (Metallized Polyester Film) Erectrical Characteristics at 1kHz Temperature (Degree C) Capacitance change (%) Dissipation factor (%) Temperature (Degree C) at 1kHz at DC100V Temperature (Degree C) Insuration resistance (ohm) Capacitance change (%) Frequency (kHz) Frequency (kHz) Dissipation factor (%) Frequency (kHz) Impedance (ohm) 2.2uF 1.0uF 0.1uF 2.2uF 1.0uF 0.1uF 2.2uF 1.0uF 0.1uF 0.01uF 0.01uF 0.01uF 0.01uF 0.1uF 1.0uF 2.2uF 0.01uF 0.1uF 1.0uF 2.2uF 2.2uF 1.0uF 0.1uF 0.01uF Rating Voltage Capacitance Value(uF) Code dV/dt(V/us) Current(o-p) (A) 0.010 103 1.31 0.015 153 1.97 0.022 223 2.88 0.033 333 4.32 0.047 473 3.67 0.068 683 5.30 0.100 104 7.80 0.150 154 5.55 0.220 224 8.14 0.330 334 12.21 0.470 474 17.39 0.680 684 14.96 1.000 105 22.00 1.200 155 27.00 2.200 225 39.60 Permissible Voltage Voltage Derating by Temperature 131 Permissible Current Pulse Handling Capability (dV/dt) (Max 10000cycles) 400VDC 78 37 22 18 0 100 200 300 400 500 -60 -40 -20 0 20 40 60 80 100 120 0 0.5 1 1.5 2 2.5 3 10 100 1000 1 10 100 10 100 1000 * Please consult Panasonic if your condition exceeds the above spec. ECQE(F) Type 400VDC Series (Metallized Polyester Film) Applicable Specifications Frequency (kHz) Permissible Current (Arms) Permissible Voltage (Vrms) (at sinewave) Frequency (kHz) Rated Voltage (VDC) Surface Temperature of Capacitor(Degree C) From 0.01uF to 2.2uF 2.2uF 1.0uF 0.47uF 0.22uF 0.1uF 0.047uF 0.022uF 0.01uF 0.01uF 0.022uF 0.047uF 0.1uF 0.22uF 0.47uF 1.0uF 2.2uF Temperature Characteristics Frequency Characteristics 0.01 0.1 1 10 100 1000 10000 1 10 100 1000 10000 100000 0 2 4 6 8 10 1 10 100 1000 10000 -10 -5 0 5 10 1 10 100 1000 10000 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11 1.E+12 1.E+13 -60 -40 -20 0 20 40 60 80 100 0 2 4 6 8 10 -60 -40 -20 0 20 40 60 80 100 -10 -5 0 5 10 -60 -40 -20 0 20 40 60 80 100 ECQE(F) Type 630VDC Series (Metallized Polyester Film) Erectrical Characteristics at 1kHz Temperature (Degree C) Capacitance change (%) Dissipation factor (%) Temperature (Degree C) at 1kHz at DC100V Temperature (Degree C) Insuration resistance (ohm) Capacitance change (%) Frequency (kHz) Frequency (kHz) Dissipation factor (%) Frequency (kHz) Impedance (ohm) 2.2uF 1.0uF 0.1uF 2.2uF 1.0uF 0.1uF 1.0uF 0.1uF 0.01uF 0.01uF 0.01uF 0.01uF 0.1uF 1.0uF 2.2uF 0.01uF 0.1uF 1.0uF 2.2uF 2.2uF 1.0uF 0.1uF 0.01uF 2.2uF Rating Voltage Capacitance Value(uF) Code dV/dt(V/us) Current(o-p) (A) 0.010 103 2.73 0.015 153 4.10 0.022 223 6.01 0.033 333 9.01 0.047 473 12.83 0.068 683 7.89 0.100 104 11.60 0.150 154 17.40 0.220 224 25.52 0.330 334 20.79 0.470 474 29.61 0.680 684 42.84 1.000 105 48.00 1.500 155 72.00 2.200 225 105.60 (Max 10000cycles) 273 Voltage Derating by Temperature 630VDC Permissible Current Permissible Voltage 116 63 48 Pulse Handling Capability (dV/dt) 0 100 200 300 400 500 600 700 800 -60 -40 -20 0 20 40 60 80 100 120 1 10 100 10 100 1000 0 1 2 3 4 5 10 100 1000 * Please consult Panasonic if your condition exceeds the above spec. ECQE(F) Type 630VDC Series (Metallized Polyester Film) Applicable Specifications Frequency (kHz) Permissible Current (Arms) Permissible Voltage (Vrms) (at sinewave) Frequency (kHz) Rated Voltage (VDC) Surface Temperature of Capacitor(Degree C) From 0.01uF to 2.2uF 2.2uF 1.0uF 0.47uF 0.22uF 0.1uF 0.047uF 0.022uF 0.01uF 0.01uF 0.022uF 0.047uF 0.1uF 0.22uF 0.47uF 1.0uF 2.2uF Temperature Characteristics Frequency Characteristics 0.01 0.1 1 10 100 1000 10000 1 10 100 1000 10000 100000 0 2 4 6 8 10 1 10 100 1000 10000 -10 -5 0 5 10 1 10 100 1000 10000 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11 1.E+12 1.E+13 -60 -40 -20 0 20 40 60 80 100 0 2 4 6 8 10 -10 -5 0 5 10 -60 -40 -20 0 20 40 60 80 100 ECQE(F) Type 125VAC Series (Metallized Polyester Film) Erectrical Characteristics at 1kHz Temperature (Degree C) Capacitance change (%) Dissipation factor (%) Temperature (Degree C) at 1kHz at DC100V Temperature (Degree C) Insuration resistance (ohm) Capacitance change (%) Frequency (kHz) Frequency (kHz) Dissipation factor (%) Frequency (kHz) Impedance (ohm) 0.47uF 0.1uF 0.047uF 0.47uF 0.1uF 0.047uF 0.47uF 0.1uF 0.01uF 0.47uF 0.1uF 0.047uF 0.047uF 0.1uF 0.47uF 0.047uF 0.1uF 0.47uF 0.01uF 0.01uF 0.047uF 0.01uF 0.01uF 0.01uF Temperature Characteristics Frequency Characteristics 0.01 0.1 1 10 100 1000 10000 1 10 100 1000 10000 100000 0 2 4 6 8 10 1 10 100 1000 10000 -10 -5 0 5 10 1 10 100 1000 10000 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11 1.E+12 1.E+13 -60 -40 -20 0 20 40 60 80 100 0 2 4 6 8 10 -60 -40 -20 0 20 40 60 80 100 -10 -5 0 5 10 -60 -40 -20 0 20 40 60 80 100 ECQE(F) Type 250VAC Series (Metallized Polyester Film) Erectrical Characteristics at 1kHz Temperature (Degree C) Capacitance change (%) Dissipation factor (%) Temperature (Degree C) at 1kHz at DC100V Temperature (Degree C) Insuration resistance (ohm) Capacitance change (%) Frequency (kHz) Frequency (kHz) Dissipation factor (%) Frequency (kHz) Impedance (ohm) 0.47uF 0.1uF 0.047uF 0.47uF 0.1uF 0.047uF 0.47uF 0.1uF 0.01uF 0.47uF 0.1uF 0.047uF 0.047uF 0.1uF 0.47uF 0.047uF 0.1uF 0.47uF 0.01uF 0.01uF 0.047uF 0.01uF 0.01uF 0.01uF Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ FR – EEE-82 – 010 Sleeve L 14 min. 3 min. = = L 16 : L±1.5 L 20 : L±2.0 Pressure relief 06.3 + – 08 0D±0.5 F±0.5 0D±0.5 fd±0.05 ■ Country of origin Malaysia Radial Lead Type Series: FR Type: A ■ Specifi cations Category Temp. Range –40 °C to +105 °C Rated W.V. Range 6.3 V.DC to 100 V.DC Nominal Cap. Range 4.7 μF to 8200 μF Capacitance Tolerance ±20 % (120 Hz/+20 °C) DC Leakage Cur rent I < 0.01 CV (μA) After 2 minutes tan d W.V. 6.3 10 16 25 35 50 63 100 (120 Hz/+20 °C) tan d 0.22 0.19 0.16 0.14 0.12 0.10 0.09 0.08 Add 0.02 per 1000 μF for products of 1000 μF or more. Endurance After following life test with DC voltage and +105 °C±2 °C ripple current value applied. (The sum of DC and ripple peak voltage shall not exceed the rated working voltage) when the capacitors are restored to 20 °C, the capacitors shall meet the limits specifi ed below. Duration 05×11/ 06.3×11.2 : 5000 hours 08×11.5/ 010×12.5 : 6000 hours (✽ Only EEUFR1V331U (010×12.5) 5000 hours) 08×15/ 010×16 : 8000 hours, 08×20 : 9000 hours 010×20 to 010×25/ 012.5×20 to 012.5×35/ 016×20 to 016×25 : 10000 hours Capacitance change ±25 % of initial measured value (6.3 V to 10 V : ±30 %) tan d < 200 % of initial specifi ed value DC leakage current < initial specifi ed value Shelf Life After storage for 1000 hours at +105 °C±2 °C with no voltage applied and then being stabilized at +20 °C, capacitors shall meet the limits specifi ed in Endurance. (With voltage treatment) ■ Di men sions in mm (not to scale) W.V.(V.DC) Cap (μF) Frequency (Hz) 60 120 1 k 10 k 100 k 6.3 to 100 4.7 to 33 0.45 0.55 0.75 0.90 1.00 47 to 330 0.60 0.70 0.85 0.95 1.00 390 to 1000 0.65 0.75 0.90 0.98 1.00 1200 to 8200 0.75 0.80 0.95 1.00 1.00 ■ Frequency correction factor for ripple current Body Dia. 0D 5 6.3 8 10 12.5 16 Body Length L — — — — 12.5 to 25 30 to 35 — Lead Dia. 0d 0.5 0.5 0.6 0.6 0.6 0.8 0.8 Lead space F 2.0 2.5 3.5 5.0 5.0 7.5 ■ Features ● Low ESR (Same as FM Series) ● Endurance : 5000 h to 10000 h at +105 °C ● RoHS directive compliant ■ Attention Not applicable for automotive (Unit : mm) 06 Nov. 2014 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ FR – EEE-83 – ■ Case size/Impedance/Ripple current W.V.(V.DC) 6.3 V to 35 V 50 V Case size (0D×L) Imped ance (Ω/100 kHz) Ripple Current (mA r.m.s./100 kHz) Imped ance (Ω/100 kHz) Ripple Current (mA r.m.s./100 kHz) +20 °C –10 °C +105 °C +20 °C –10 °C +105 °C 5 × 11 0.300 1.000 280 0.340 1.130 250 6.3 × 11.2 0.130 0.430 455 0.140 0.460 405 8 × 11.5 0.056 0.168 950 0.061 0.183 870 8 × 15 0.041 0.123 1240 0.045 0.135 1140 8 × 20 0.030 0.090 1560 0.033 0.099 1430 10 × 12.5 0.043 0.114 1290 0.042 0.126 1170 10 × 16 0.028 0.078 1790 0.030 0.090 1650 10 × 20 0.020 0.057 2180 0.023 0.069 1890 10 × 25 0.018 0.054 2470 0.022 0.066 2150 12.5 × 20 0.018 0.045 2600 0.022 0.055 2260 12.5 × 25 0.015 0.038 3190 0.018 0.045 2660 12.5 × 30 0.013 0.033 3630 0.016 0.040 3160 12.5 × 35 0.012 0.030 3750 0.014 0.035 3270 16 × 20 0.017 0.043 3300 0.019 0.048 2870 16 × 25 0.014 0.035 3820 0.016 0.040 3320 W.V.(V.DC) 63 V Case size (0D×L) Imped ance (Ω/100 kHz) Ripple Current (mA r.m.s./100 kHz) +20 °C –10 °C +105 °C 5 × 11 0.510 2.040 175 6.3 × 11.2 0.210 0.840 284 8 × 11.5 0.092 0.368 566 8 × 15 0.068 0.272 741 8 × 20 0.050 0.200 930 10 × 12.5 0.063 0.252 761 10 × 16 0.045 0.180 1073 10 × 20 0.035 0.140 1229 10 × 25 0.033 0.132 1500 12.5 × 20 0.033 0.125 1582 12.5 × 25 0.027 0.092 1995 12.5 × 30 0.024 0.082 2528 12.5 × 35 0.021 0.071 2780 16 × 20 0.029 0.093 2153 16 × 25 0.024 0.074 2988 W.V.(V.DC) 100 V Case size (0D×L) Imped ance (Ω/100 kHz) Ripple Current (mA r.m.s./100 kHz) +20 °C –10 °C +105 °C 10 × 20 0.084 0.336 1500 06 Nov. 2014 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ FR – EEE-84 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (100 kHz) (+105 °C) Impedance (100 kHz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽H (V) (μF) (mm) (mm) (mA r.m.s.) (Ω) (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 6.3 150 5 11 280 0.300 5000 0.5 2.0 5.0 2.5 EEUFR0J151( ) 200 2000 220 6.3 11.2 455 0.130 5000 0.5 2.5 5.0 2.5 EEUFR0J221( ) 200 2000 330 6.3 11.2 455 0.130 5000 0.5 2.5 5.0 2.5 EEUFR0J331( ) 200 2000 470 6.3 11.2 455 0.130 5000 0.5 2.5 5.0 2.5 EEUFR0J471( ) 200 2000 820 8 11.5 950 0.056 6000 0.6 3.5 5.0 EEUFR0J821( ) 200 1000 1000 8 11.5 950 0.056 6000 0.6 3.5 5.0 EEUFR0J102( ) 200 1000 1200 8 15 1240 0.041 8000 0.6 3.5 5.0 EEUFR0J122L( ) 200 1000 10 12.5 1290 0.043 6000 0.6 5.0 5.0 EEUFR0J122( ) 200 500 1500 8 20 1560 0.030 9000 0.6 3.5 5.0 EEUFR0J152L( ) 200 1000 1800 10 16 1790 0.028 8000 0.6 5.0 5.0 EEUFR0J182( ) 200 500 2200 10 20 2180 0.020 10000 0.6 5.0 5.0 EEUFR0J222( ) 200 500 2700 10 25 2470 0.018 10000 0.6 5.0 5.0 EEUFR0J272L( ) 200 500 3300 10 25 2470 0.018 10000 0.6 5.0 5.0 EEUFR0J332L( ) 200 500 3900 12.5 20 2600 0.018 10000 0.6 5.0 5.0 EEUFR0J392( ) 200 500 4700 12.5 25 3190 0.015 10000 0.6 5.0 5.0 EEUFR0J472( ) 200 500 5600 12.5 30 3630 0.013 10000 0.8 5.0 EEUFR0J562L 100 6800 12.5 35 3750 0.012 10000 0.8 5.0 EEUFR0J682L 100 16 20 3300 0.017 10000 0.8 7.5 7.5 EEUFR0J682S( ) 100 250 8200 16 25 3820 0.014 10000 0.8 7.5 7.5 EEUFR0J822( ) 100 250 10 100 5 11 280 0.300 5000 0.5 2.0 5.0 2.5 EEUFR1A101( ) 200 2000 150 5 11 280 0.300 5000 0.5 2.0 5.0 2.5 EEUFR1A151( ) 200 2000 220 6.3 11.2 455 0.130 5000 0.5 2.5 5.0 2.5 EEUFR1A221( ) 200 2000 270 6.3 11.2 455 0.130 5000 0.5 2.5 5.0 2.5 EEUFR1A271( ) 200 2000 470 8 11.5 950 0.056 6000 0.6 3.5 5.0 EEUFR1A471( ) 200 1000 680 8 11.5 950 0.056 6000 0.6 3.5 5.0 EEUFR1A681( ) 200 1000 820 10 12.5 1290 0.043 6000 0.6 5.0 5.0 EEUFR1A821( ) 200 500 1000 10 16 1790 0.028 8000 0.6 5.0 5.0 EEUFR1A102( ) 200 500 8 15 1240 0.041 8000 0.6 3.5 5.0 EEUFR1A102L( ) 200 1000 1500 8 20 1560 0.030 9000 0.6 3.5 5.0 EEUFR1A152L( ) 200 1000 10 16 1790 0.028 8000 0.6 5.0 5.0 EEUFR1A152( ) 200 500 1800 10 20 2180 0.020 10000 0.6 5.0 5.0 EEUFR1A182( ) 200 500 2200 10 25 2470 0.018 10000 0.6 5.0 5.0 EEUFR1A222L( ) 200 500 3300 12.5 20 2600 0.018 10000 0.6 5.0 5.0 EEUFR1A332( ) 200 500 3900 12.5 25 3190 0.015 10000 0.6 5.0 5.0 EEUFR1A392( ) 200 500 4700 12.5 30 3630 0.013 10000 0.8 5.0 EEUFR1A472L 100 16 20 3300 0.017 10000 0.8 7.5 7.5 EEUFR1A472S( ) 100 250 5600 12.5 35 3750 0.012 10000 0.8 5.0 EEUFR1A562L 100 6800 12.5 35 3750 0.012 10000 0.8 5.0 EEUFR1A682L 100 16 25 3820 0.014 10000 0.8 7.5 7.5 EEUFR1A682( ) 100 250 · When requesting taped product, please put the letter "B" or "H" be tween the "( )". Lead wire pitch ✽B=5 mm, 7.5 mm, H=2.5 mm. · Please refer to the page of “Taping Dimensions”. 06 Nov. 2014 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ FR – EEE-85 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (100 kHz) (+105 °C) Impedance (100 kHz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽H (V) (μF) (mm) (mm) (mA r.m.s.) (Ω) (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 16 68 5 11 280 0.300 5000 0.5 2.0 5.0 2.5 EEUFR1C680( ) 200 2000 100 5 11 280 0.300 5000 0.5 2.0 5.0 2.5 EEUFR1C101( ) 200 2000 120 6.3 11.2 455 0.130 5000 0.5 2.5 5.0 2.5 EEUFR1C121( ) 200 2000 220 6.3 11.2 455 0.130 5000 0.5 2.5 5.0 2.5 EEUFR1C221( ) 200 2000 470 8 11.5 950 0.056 6000 0.6 3.5 5.0 EEUFR1C471( ) 200 1000 680 8 15 1240 0.041 8000 0.6 3.5 5.0 EEUFR1C681L( ) 200 1000 10 12.5 1290 0.043 6000 0.6 5.0 5.0 EEUFR1C681( ) 200 500 1000 8 20 1560 0.030 9000 0.6 3.5 5.0 EEUFR1C102L( ) 200 1000 10 16 1790 0.028 8000 0.6 5.0 5.0 EEUFR1C102( ) 200 500 1500 10 20 2180 0.020 10000 0.6 5.0 5.0 EEUFR1C152( ) 200 500 10 25 2470 0.018 10000 0.6 5.0 5.0 EEUFR1C152L( ) 200 500 1800 10 25 2470 0.018 10000 0.6 5.0 5.0 EEUFR1C182L( ) 200 500 2200 12.5 20 2600 0.018 10000 0.6 5.0 5.0 EEUFR1C222( ) 200 500 2700 12.5 25 3190 0.015 10000 0.6 5.0 5.0 EEUFR1C272( ) 200 500 3300 12.5 30 3630 0.013 10000 0.8 5.0 EEUFR1C332L 100 16 20 3300 0.017 10000 0.8 7.5 7.5 EEUFR1C332S( ) 100 250 3900 12.5 35 3750 0.012 10000 0.8 5.0 EEUFR1C392L 100 16 20 3300 0.017 10000 0.8 7.5 7.5 EEUFR1C392S( ) 100 250 4700 12.5 35 3750 0.012 10000 0.8 5.0 EEUFR1C472L 100 16 25 3820 0.014 10000 0.8 7.5 7.5 EEUFR1C472( ) 100 250 5600 16 25 3820 0.014 10000 0.8 7.5 7.5 EEUFR1C562( ) 100 250 25 47 5 11 280 0.300 5000 0.5 2.0 5.0 2.5 EEUFR1E470( ) 200 2000 68 5 11 280 0.300 5000 0.5 2.0 5.0 2.5 EEUFR1E680( ) 200 2000 100 6.3 11.2 455 0.130 5000 0.5 2.5 5.0 2.5 EEUFR1E101( ) 200 2000 150 6.3 11.2 455 0.130 5000 0.5 2.5 5.0 2.5 EEUFR1E151( ) 200 2000 220 8 11.5 950 0.056 6000 0.6 3.5 5.0 EEUFR1E221( ) 200 1000 330 8 11.5 950 0.056 6000 0.6 3.5 5.0 EEUFR1E331( ) 200 1000 390 8 15 1240 0.041 8000 0.6 3.5 5.0 EEUFR1E391L( ) 200 1000 470 8 15 1240 0.041 8000 0.6 3.5 5.0 EEUFR1E471Y( ) 200 1000 8 20 1560 0.030 9000 0.6 3.5 5.0 EEUFR1E471L( ) 200 1000 10 12.5 1290 0.043 6000 0.6 5.0 5.0 EEUFR1E471( ) 200 500 560 8 20 1560 0.030 9000 0.6 3.5 5.0 EEUFR1E561L( ) 200 1000 680 8 20 1560 0.030 9000 0.6 3.5 5.0 EEUFR1E681L( ) 200 1000 10 16 1790 0.028 8000 0.6 5.0 5.0 EEUFR1E681( ) 200 500 820 10 20 2180 0.020 10000 0.6 5.0 5.0 EEUFR1E821( ) 200 500 1000 10 20 2180 0.020 10000 0.6 5.0 5.0 EEUFR1E102( ) 200 500 10 25 2470 0.018 10000 0.6 5.0 5.0 EEUFR1E102L( ) 200 500 1200 10 25 2470 0.018 10000 0.6 5.0 5.0 EEUFR1E122L( ) 200 500 1500 12.5 20 2600 0.018 10000 0.6 5.0 5.0 EEUFR1E152( ) 200 500 1800 12.5 25 3190 0.015 10000 0.6 5.0 5.0 EEUFR1E182( ) 200 500 16 20 3300 0.017 10000 0.8 7.5 7.5 EEUFR1E182S( ) 100 250 2200 12.5 30 3630 0.013 10000 0.8 5.0 EEUFR1E222L 100 16 20 3300 0.017 10000 0.8 7.5 7.5 EEUFR1E222S( ) 100 250 2700 12.5 35 3750 0.012 10000 0.8 5.0 EEUFR1E272L 100 16 20 3300 0.017 10000 0.8 7.5 7.5 EEUFR1E272S( ) 100 250 3300 16 25 3820 0.014 10000 0.8 7.5 7.5 EEUFR1E332( ) 100 250 · When requesting taped product, please put the letter "B" or "H" be tween the "( )". Lead wire pitch ✽B=5 mm, 7.5 mm, H=2.5 mm. · Please refer to the page of “Taping Dimensions”. 06 Nov. 2014 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ FR – EEE-86 – ■ Standard Prod ucts W.V. Cap. (±20 %) Case size Specifi cation Lead Length Part No. Min. Packaging Q'ty Dia. Length Ripple Current (100 kHz) (+105 °C) Impedance (100 kHz) (+20 °C) Endurance Lead Dia. Lead Space Straight Leads Taping Straight Taping ✽B Taping ✽H (V) (μF) (mm) (mm) (mA r.m.s.) (Ω) (hours) (mm) (mm) (mm) (mm) (pcs) (pcs) 35 33 5 11 280 0.300 5000 0.5 2.0 5.0 2.5 EEUFR1V330( ) 200 2000 68 6.3 11.2 455 0.130 5000 0.5 2.5 5.0 2.5 EEUFR1V680( ) 200 2000 100 8 11.5 950 0.056 6000 0.6 3.5 5.0 EEUFR1V101( ) 200 1000 180 8 11.5 950 0.056 6000 0.6 3.5 5.0 EEUFR1V181( ) 200 1000 220 8 11.5 950 0.056 6000 0.6 3.5 5.0 EEUFR1V221( ) 200 1000 270 8 15 1240 0.041 8000 0.6 3.5 5.0 EEUFR1V271L( ) 200 1000 10 12.5 1290 0.043 6000 0.6 5.0 5.0 EEUFR1V271( ) 200 500 330 10 12.5 1330 0.043 5000 0.6 5.0 5.0 EEUFR1V331U( ) 200 500 390 8 20 1560 0.030 9000 0.6 3.5 5.0 EEUFR1V391L( ) 200 1000 470 8 20 1560 0.030 9000 0.6 3.5 5.0 EEUFR1V471L( ) 200 1000 10 16 1790 0.028 8000 0.6 5.0 5.0 EEUFR1V471( ) 200 500 560 10 20 2180 0.020 10000 0.6 5.0 5.0 EEUFR1V561( ) 200 500 680 10 20 2180 0.020 10000 0.6 5.0 5.0 EEUFR1V681( ) 200 500 10 25 2470 0.018 10000 0.6 5.0 5.0 EEUFR1V681L( ) 200 500 820 10 25 2470 0.018 10000 0.6 5.0 5.0 EEUFR1V821L( ) 200 500 1000 12.5 20 2600 0.018 10000 0.6 5.0 5.0 EEUFR1V102( ) 200 500 1200 12.5 25 3190 0.015 10000 0.6 5.0 5.0 EEUFR1V122( ) 200 500 1500 12.5 30 3630 0.013 10000 0.8 5.0 EEUFR1V152L 100 16 20 3300 0.017 10000 0.8 7.5 7.5 EEUFR1V152S( ) 100 250 1800 12.5 35 3750 0.012 10000 0.8 5.0 EEUFR1V182L 100 16 25 3820 0.014 10000 0.8 7.5 7.5 EEUFR1V182( ) 100 250 2200 12.5 35 3750 0.012 10000 0.8 5.0 EEUFR1V222L 100 16 25 3820 0.014 10000 0.8 7.5 7.5 EEUFR1V222( ) 100 250 50 4.7 5 11 185 0.620 5000 0.5 2.0 5.0 2.5 EEUFR1H4R7( ) 200 2000 10 5 11 250 0.340 5000 0.5 2.0 5.0 2.5 EEUFR1H100( ) 200 2000 22 5 11 250 0.340 5000 0.5 2.0 5.0 2.5 EEUFR1H220( ) 200 2000 47 6.3 11.2 405 0.140 5000 0.5 2.5 5.0 EEUFR1H470( ) 200 2000 56 6.3 11.2 405 0.140 5000 0.5 2.5 5.0 2.5 EEUFR1H560( ) 200 2000 100 8 11.5 870 0.061 6000 0.6 3.5 5.0 EEUFR1H101( ) 200 1000 120 8 15 1140 0.045 8000 0.6 3.5 5.0 EEUFR1H121L( ) 200 1000 150 10 12.5 1170 0.042 6000 0.6 5.0 5.0 EEUFR1H151( ) 200 500 180 8 20 1430 0.033 9000 0.6 3.5 5.0 EEUFR1H181L( ) 200 1000 220 10 16 1650 0.030 8000 0.6 5.0 5.0 EEUFR1H221( ) 200 500 270 10 20 1890 0.023 10000 0.6 5.0 5.0 EEUFR1H271( ) 200 500 330 10 25 2150 0.022 10000 0.6 5.0 5.0 EEUFR1H331L( ) 200 500 470 12.5 20 2260 0.022 10000 0.6 5.0 5.0 EEUFR1H471( ) 200 500 560 12.5 25 2660 0.018 10000 0.6 5.0 5.0 EEUFR1H561( ) 200 500 680 12.5 30 3160 0.016 10000 0.8 5.0 EEUFR1H681L 100 820 12.5 35 3270 0.014 10000 0.8 5.0 EEUFR1H821L 100 16 20 2870 0.019 10000 0.8 7.5 7.5 EEUFR1H821S( ) 100 250 1000 16 25 3320 0.016 10000 0.8 7.5 7.5 EEUFR1H102( ) 100 250 63 18 5 11 175 0.510 5000 0.5 2.0 5.0 2.5 EEUFR1J180( ) 200 2000 47 6.3 11.2 284 0.210 5000 0.5 2.5 5.0 2.5 EEUFR1J470( ) 200 2000 82 8 11.5 566 0.092 6000 0.6 3.5 5.0 EEUFR1J820( ) 200 1000 100 8 15 741 0.068 8000 0.6 3.5 5.0 EEUFR1J101L( ) 200 1000 10 12.5 761 0.063 6000 0.6 5.0 5.0 EEUFR1J101( ) 200 500 120 8 20 930 0.050 9000 0.6 3.5 5.0 EEUFR1J121L( ) 200 1000 10 16 1073 0.045 8000 0.6 5.0 5.0 EEUFR1J121( ) 200 500 150 8 20 930 0.050 9000 0.6 3.5 5.0 EEUFR1J151L( ) 200 1000 10 16 1073 0.045 8000 0.6 5.0 5.0 EEUFR1J151( ) 200 500 180 10 20 1229 0.035 10000 0.6 5.0 5.0 EEUFR1J181( ) 200 500 220 10 25 1500 0.033 10000 0.6 5.0 5.0 EEUFR1J221L( ) 200 500 270 10 20 1229 0.035 10000 0.6 5.0 5.0 EEUFR1J271U( ) 200 500 10 25 1500 0.033 10000 0.6 5.0 5.0 EEUFR1J271L( ) 200 500 12.5 20 1582 0.033 10000 0.6 5.0 5.0 EEUFR1J271( ) 200 500 330 12.5 20 1582 0.033 10000 0.6 5.0 5.0 EEUFR1J331( ) 200 500 390 12.5 25 1995 0.027 10000 0.6 5.0 5.0 EEUFR1J391( ) 200 500 470 12.5 25 1995 0.027 10000 0.6 5.0 5.0 EEUFR1J471( ) 200 500 560 12.5 30 2528 0.024 10000 0.8 5.0 EEUFR1J561L 100 16 20 2153 0.029 10000 0.8 7.5 7.5 EEUFR1J561S( ) 100 250 680 12.5 35 2780 0.021 10000 0.8 5.0 EEUFR1J681L 100 820 16 25 2988 0.024 10000 0.8 7.5 7.5 EEUFR1J821( ) 100 250 100 100 10 20 1500 0.084 10000 0.6 5.0 5.0 EEUFR2A101( ) 200 500 · When requesting taped product, please put the letter "B" or "H" be tween the "( )". Lead wire pitch ✽B=5 mm, 7.5 mm, H=2.5 mm. · Please refer to the page of “Taping Dimensions”. 06 Nov. 2014 Design and specifi cations are each subject to change without notice. Ask factory for the current technical specifi cations before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. Aluminum Electrolytic Capacitors/ M – EEE-111 – 010 Sleeve L 14 min. 3 min. = 06.3 =L 16 : L±1.0 L 20 : L±2.0 Pressure relief + – 08 0D+0.5 F±0.5 0D+0.5 fd±0.05 ■ Features ● Endurance : 85 °C 2000 h ● Smaller than series SU ● RoHS directive compliant Radial Lead Type Series: M Type: A ■ Specifi cations Category Temp. Range –40 °C to + 85 °C –25 °C to +85 °C Rated W.V. Range 6.3 V.DC to 100 V.DC 160 V.DC to 450 V.DC Nominal Cap. Range 2.2 μF to 22000 μF 1 μF to 470 μF Capacitance Tolerance ±20 % (120 Hz/+20 °C) DC Leakage Cur rent I < 0.01 CV or 3 (μA) After 2 minutes (Whichever is greater) I < 0.06 CV +10 (μA) After 2 minutes tan d Please see the attached standard products list Endurance After applying rated working voltage for 2000 hours at +85°C±2 °C, when the capacitors are restored to 20 °C, capacitors shall meet the following limits. Capacitance change ±20 % of initial measured value tan d <150 % of initial specifi ed value DC leakage current > NXP Semiconductors LPC2468 Single-chip 16-bit/32-bit micro 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information. . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 Functional description . . . . . . . . . . . . . . . . . . 24 7.1 Architectural overview . . . . . . . . . . . . . . . . . . 24 7.2 On-chip flash programming memory . . . . . . . 25 7.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 25 7.4 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.5 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 27 7.5.1 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 28 7.6 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 28 7.7 External memory controller. . . . . . . . . . . . . . . 28 7.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.8 General purpose DMA controller . . . . . . . . . . 29 7.8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.9 Fast general purpose parallel I/O . . . . . . . . . . 30 7.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.10 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.11 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.11.1 USB device controller . . . . . . . . . . . . . . . . . . . 32 7.11.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.11.2 USB host controller. . . . . . . . . . . . . . . . . . . . . 32 7.11.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.11.3 USB OTG controller . . . . . . . . . . . . . . . . . . . . 33 7.11.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.12 CAN controller and acceptance filters . . . . . . 33 7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.13 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.14 10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.15 UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.16 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 35 7.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.17 SSP serial I/O controller . . . . . . . . . . . . . . . . . 35 7.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.18 SD/MMC card interface . . . . . . . . . . . . . . . . . 35 7.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.19 I2C-bus serial I/O controller . . . . . . . . . . . . . . 36 7.19.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.20 I2S-bus serial I/O controllers . . . . . . . . . . . . . 36 7.20.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.21 General purpose 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.21.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.22 Pulse width modulator . . . . . . . . . . . . . . . . . . 38 7.22.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.23 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 39 7.23.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.24 RTC and battery RAM . . . . . . . . . . . . . . . . . . 39 7.24.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.25 Clocking and power control . . . . . . . . . . . . . . 40 7.25.1 Crystal oscillators. . . . . . . . . . . . . . . . . . . . . . 40 7.25.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 40 7.25.1.2 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 40 7.25.1.3 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 41 7.25.2 PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.25.3 Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 41 7.25.4 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.25.4.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.25.4.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.25.4.3 Power-down mode . . . . . . . . . . . . . . . . . . . . . 42 7.25.4.4 Deep power-down mode . . . . . . . . . . . . . . . . 43 7.25.4.5 Power domains . . . . . . . . . . . . . . . . . . . . . . . 43 7.26 System control . . . . . . . . . . . . . . . . . . . . . . . . 44 7.26.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.26.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 44 7.26.3 Code security (Code Read Protection - CRP) 44 7.26.4 AHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.26.5 External interrupt inputs . . . . . . . . . . . . . . . . . 45 7.26.6 Memory mapping control . . . . . . . . . . . . . . . . 45 7.27 Emulation and debugging . . . . . . . . . . . . . . . 45 7.27.1 EmbeddedICE . . . . . . . . . . . . . . . . . . . . . . . . 45 7.27.2 Embedded trace. . . . . . . . . . . . . . . . . . . . . . . 46 7.27.3 RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 47 9 Thermal characteristics . . . . . . . . . . . . . . . . . 48 10 Static characteristics . . . . . . . . . . . . . . . . . . . 49 10.1 Power-down mode . . . . . . . . . . . . . . . . . . . . . 52 10.2 Deep power-down mode . . . . . . . . . . . . . . . . 53 10.3 Electrical pin characteristics. . . . . . . . . . . . . . 55 11 Dynamic characteristics. . . . . . . . . . . . . . . . . 56 11.1 Internal oscillators . . . . . . . . . . . . . . . . . . . . . 57 11.2 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.3 USB interface. . . . . . . . . . . . . . . . . . . . . . . . . 57 11.4 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 58 NXP Semiconductors LPC2468 Single-chip 16-bit/32-bit micro © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 January 2013 Document identifier: LPC2468 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 11.5 Static external memory interface . . . . . . . . . . 59 11.6 Dynamic external memory interface . . . . . . . . 61 11.7 Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12 ADC electrical characteristics . . . . . . . . . . . . 65 13 DAC electrical characteristics . . . . . . . . . . . . 68 14 Application information. . . . . . . . . . . . . . . . . . 69 14.1 Suggested USB interface solutions . . . . . . . . 69 14.2 Crystal oscillator XTAL input and component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 14.3 RTC 32 kHz oscillator component selection. . 75 14.4 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines. . . . . . . . . . . . . . . . . . . . . . . 76 14.5 Standard I/O pin configuration . . . . . . . . . . . . 76 14.6 Reset pin configuration. . . . . . . . . . . . . . . . . . 77 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 78 16 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 80 17 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 81 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 82 18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 82 18.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 18.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 18.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 83 19 Contact information. . . . . . . . . . . . . . . . . . . . . 83 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 1. General description The LPC2141/42/44/46/48 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, that combine the microcontroller with embedded high-speed flash memory ranging from 32 kB to 512 kB. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty. Due to their tiny size and low power consumption, LPC2141/42/44/46/48 are ideal for applications where miniaturization is a key requirement, such as access control and point-of-sale. Serial communications interfaces ranging from a USB 2.0 Full-speed device, multiple UARTs, SPI, SSP to I2C-bus and on-chip SRAM of 8 kB up to 40 kB, make these devices very well suited for communication gateways and protocol converters, soft modems, voice recognition and low end imaging, providing both large buffer size and high processing power. Various 32-bit timers, single or dual 10-bit ADC(s), 10-bit DAC, PWM channels and 45 fast GPIO lines with up to nine edge or level sensitive external interrupt pins make these microcontrollers suitable for industrial control and medical systems. 2. Features and benefits 2.1 Key features 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package. 8 kB to 40 kB of on-chip static RAM and 32 kB to 512 kB of on-chip flash memory. 128-bit wide interface/accelerator enables high-speed 60 MHz operation. In-System Programming/In-Application Programming (ISP/IAP) via on-chip boot loader software. Single flash sector or full chip erase in 400 ms and programming of 256 B in 1 ms. EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging with the on-chip RealMonitor software and high-speed tracing of instruction execution. USB 2.0 Full-speed compliant device controller with 2 kB of endpoint RAM. In addition, the LPC2146/48 provides 8 kB of on-chip RAM accessible to USB by DMA. One or two (LPC2141/42 vs. LPC2144/46/48) 10-bit ADCs provide a total of 6/14 analog inputs, with conversion times as low as 2.44 s per channel. Single 10-bit DAC provides variable analog output (LPC2142/44/46/48 only). Two 32-bit timers/external event counters (with four capture and four compare channels each), PWM unit (six outputs) and watchdog. Low power Real-Time Clock (RTC) with independent power and 32 kHz clock input. LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, USB 2.0 full-speed device, 10-bit ADC and DAC Rev. 5 — 12 August 2011 Product data sheet LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 2 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400 kbit/s), SPI and SSP with buffering and variable data length capabilities. Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses. Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package. Up to 21 external interrupt pins available. 60 MHz maximum CPU clock available from programmable on-chip PLL with settling time of 100 s. On-chip integrated oscillator operates with an external crystal from 1 MHz to 25 MHz. Power saving modes include Idle and Power-down. Individual enable/disable of peripheral functions as well as peripheral clock scaling for additional power optimization. Processor wake-up from Power-down mode via external interrupt or BOD. Single power supply chip with POR and BOD circuits: CPU operating voltage range of 3.0 V to 3.6 V (3.3 V 10 %) with 5 V tolerant I/O pads. 3. Ordering information 3.1 Ordering options [1] While the USB DMA is the primary user of the additional 8 kB RAM, this RAM is also accessible at any time by the CPU as a general purpose RAM for data and code storage. Table 1. Ordering information Type number Package Name Description Version LPC2141FBD64 LQFP64 plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2 LPC2142FBD64 LPC2144FBD64 LPC2146FBD64 LPC2148FBD64 Table 2. Ordering options Type number Flash memory RAM Endpoint USB RAM ADC (channels overall) DAC Temperature range LPC2141FBD64 32 kB 8 kB 2 kB 1 (6 channels) - 40 C to +85 C LPC2142FBD64 64 kB 16 kB 2 kB 1 (6 channels) 1 40 C to +85 C LPC2144FBD64 128 kB 16 kB 2 kB 2 (14 channels) 1 40 C to +85 C LPC2146FBD64 256 kB 32 kB + 8 kB shared with USB DMA[1] 2 kB 2 (14 channels) 1 40 C to +85 C LPC2148FBD64 512 kB 32 kB + 8 kB shared with USB DMA[1] 2 kB 2 (14 channels) 1 40 C to +85 C LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 3 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers 4. Block diagram (1) Pins shared with GPIO. (2) LPC2144/46/48 only. (3) USB DMA controller with 8 kB of RAM accessible as general purpose RAM and/or DMA is available in LPC2146/48 only. (4) LPC2142/44/46/48 only. Fig 1. Block diagram 002aab560 system clock TRST(1) TMS(1) TCK(1) TDI(1) TDO(1) XTAL2 XTAL1 AMBA AHB (Advanced High-performance Bus) INTERNAL FLASH CONTROLLER AHB BRIDGE EMULATION TRACE MODULE TEST/DEBUG INTERFACE AHB AHB TO APB DECODER BRIDGE APB DIVIDER VECTORED INTERRUPT CONTROLLER SYSTEM FUNCTIONS PLL0 USB clock PLL1 SYSTEM CONTROL 32 kB/64 kB/128 kB/ 256 kB/512 kB FLASH ARM7TDMI-S LPC2141/42/44/46/48 INTERNAL SRAM CONTROLLER 8 kB/16 kB/ 32 kB SRAM ARM7 local bus SCL0, SCL1 SDA0, SDA1 4 × CAP0 4 × CAP1 8 × MAT0 8 × MAT1 I 2C-BUS SERIAL INTERFACES 0 AND 1 CAPTURE/COMPARE (W/EXTERNAL CLOCK) TIMER 0/TIMER 1 EINT3 to EINT0 EXTERNAL INTERRUPTS D+ D− UP_LED CONNECT VBUS USB 2.0 FULL-SPEED DEVICE CONTROLLER WITH DMA(3) SCK0, SCK1 MOSI0, MOSI1 MISO0, MISO1 AD0[7:6] and AD0[4:1] AD1[7:0](2) SSEL0, SSEL1 SPI AND SSP SERIAL INTERFACES A/D CONVERTERS 0 AND 1(2) TXD0, TXD1 RXD0, RXD1 DSR1(2),CTS1(2), RTS1(2), DTR1(2) DCD1(2),RI1(2) AOUT(4) D/A CONVERTER UART0/UART1 P0[31:28] and P0[25:0] P1[31:16] RTXC2 RTXC1 VBAT REAL-TIME CLOCK GENERAL PURPOSE I/O PWM6 to PWM0 WATCHDOG TIMER PWM0 P0[31:28] and P0[25:0] P1[31:16] FAST GENERAL PURPOSE I/O 8 kB RAM SHARED WITH USB DMA(3) RST LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 4 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers 5. Pinning information 5.1 Pinning Fig 2. LPC2141 pinning LPC2141 P0.21/PWM5/CAP1.3 P1.20/TRACESYNC P0.22/CAP0.0/MAT0.0 P0.17/CAP1.2/SCK1/MAT1.2 RTCX1 P0.16/EINT0/MAT0.2/CAP0.2 P1.19/TRACEPKT3 P0.15/EINT2 RTCX2 P1.21/PIPESTAT0 VSS VDD VDDA VSS P1.18/TRACEPKT2 P0.14/EINT1/SDA1 P0.25/AD0.4 P1.22/PIPESTAT1 D+ P0.13/MAT1.1 D− P0.12/MAT1.0 P1.17/TRACEPKT1 P0.11/CAP1.1/SCL1 P0.28/AD0.1/CAP0.2/MAT0.2 P1.23/PIPESTAT2 P0.29/AD0.2/CAP0.3/MAT0.3 P0.10/CAP1.0 P0.30/AD0.3/EINT3/CAP0.0 P0.9/RXD1/PWM6/EINT3 P1.16/TRACEPKT0 P0.8/TXD1/PWM4 P0.31/UP_LED/CONNECT P1.27/TDO VSS VREF P0.0/TXD0/PWM1 XTAL1 P1.31/TRST XTAL2 P0.1/RXD0/PWM3/EINT0 P1.28/TDI P0.2/SCL0/CAP0.0 VSSA VDD P0.23/VBUS P1.26/RTCK RESET VSS P1.29/TCK P0.3/SDA0/MAT0.0/EINT1 P0.20/MAT1.3/SSEL1/EINT3 P0.4/SCK0/CAP0.1/AD0.6 P0.19/MAT1.2/MOSI1/CAP1.2 P1.25/EXTIN0 P0.18/CAP1.3/MISO1/MAT1.3 P0.5/MISO0/MAT0.1/AD0.7 P1.30/TMS P0.6/MOSI0/CAP0.2 VDD P0.7/SSEL0/PWM2/EINT2 VSS P1.24/TRACECLK VBAT 002aab733 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 5 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers Fig 3. LPC2142 pinning LPC2142 P0.21/PWM5/CAP1.3 P1.20/TRACESYNC P0.22/CAP0.0/MAT0.0 P0.17/CAP1.2/SCK1/MAT1.2 RTCX1 P0.16/EINT0/MAT0.2/CAP0.2 P1.19/TRACEPKT3 P0.15/EINT2 RTCX2 P1.21/PIPESTAT0 VSS VDD VDDA VSS P1.18/TRACEPKT2 P0.14/EINT1/SDA1 P0.25/AD0.4/AOUT P1.22/PIPESTAT1 D+ P0.13/MAT1.1 D− P0.12/MAT1.0 P1.17/TRACEPKT1 P0.11/CAP1.1/SCL1 P0.28/AD0.1/CAP0.2/MAT0.2 P1.23/PIPESTAT2 P0.29/AD0.2/CAP0.3/MAT0.3 P0.10/CAP1.0 P0.30/AD0.3/EINT3/CAP0.0 P0.9/RXD1/PWM6/EINT3 P1.16/TRACEPKT0 P0.8/TXD1/PWM4 P0.31/UP_LED/CONNECT P1.27/TDO VSS VREF P0.0/TXD0/PWM1 XTAL1 P1.31/TRST XTAL2 P0.1/RXD0/PWM3/EINT0 P1.28/TDI P0.2/SCL0/CAP0.0 VSSA VDD P0.23/VBUS P1.26/RTCK RESET VSS P1.29/TCK P0.3/SDA0/MAT0.0/EINT1 P0.20/MAT1.3/SSEL1/EINT3 P0.4/SCK0/CAP0.1/AD0.6 P0.19/MAT1.2/MOSI1/CAP1.2 P1.25/EXTIN0 P0.18/CAP1.3/MISO1/MAT1.3 P0.5/MISO0/MAT0.1/AD0.7 P1.30/TMS P0.6/MOSI0/CAP0.2 VDD P0.7/SSEL0/PWM2/EINT2 VSS P1.24/TRACECLK VBAT 002aab734 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 6 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers Fig 4. LPC2144/46/48 pinning LPC2144/2146/2148 P0.21/PWM5/AD1.6/CAP1.3 P1.20/TRACESYNC P0.22/AD1.7/CAP0.0/MAT0.0 P0.17/CAP1.2/SCK1/MAT1.2 RTCX1 P0.16/EINT0/MAT0.2/CAP0.2 P1.19/TRACEPKT3 P0.15/RI1/EINT2/AD1.5 RTCX2 P1.21/PIPESTAT0 VSS VDD VDDA VSS P1.18/TRACEPKT2 P0.14/DCD1/EINT1/SDA1 P0.25/AD0.4/AOUT P1.22/PIPESTAT1 D+ P0.13/DTR1/MAT1.1/AD1.4 D− P0.12/DSR1/MAT1.0/AD1.3 P1.17/TRACEPKT1 P0.11/CTS1/CAP1.1/SCL1 P0.28/AD0.1/CAP0.2/MAT0.2 P1.23/PIPESTAT2 P0.29/AD0.2/CAP0.3/MAT0.3 P0.10/RTS1/CAP1.0/AD1.2 P0.30/AD0.3/EINT3/CAP0.0 P0.9/RXD1/PWM6/EINT3 P1.16/TRACEPKT0 P0.8/TXD1/PWM4/AD1.1 P0.31/UP_LED/CONNECT P1.27/TDO VSS VREF P0.0/TXD0/PWM1 XTAL1 P1.31/TRST XTAL2 P0.1/RXD0/PWM3/EINT0 P1.28/TDI P0.2/SCL0/CAP0.0 VSSA VDD P0.23/VBUS P1.26/RTCK RESET VSS P1.29/TCK P0.3/SDA0/MAT0.0/EINT1 P0.20/MAT1.3/SSEL1/EINT3 P0.4/SCK0/CAP0.1/AD0.6 P0.19/MAT1.2/MOSI1/CAP1.2 P1.25/EXTIN0 P0.18/CAP1.3/MISO1/MAT1.3 P0.5/MISO0/MAT0.1/AD0.7 P1.30/TMS P0.6/MOSI0/CAP0.2/AD1.0 VDD P0.7/SSEL0/PWM2/EINT2 VSS P1.24/TRACECLK VBAT 002aab735 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 7 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers 5.2 Pin description Table 3. Pin description Symbol Pin Type Description P0.0 to P0.31 I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. Total of 31 pins of the Port 0 can be used as a general purpose bidirectional digital I/Os while P0.31 is output only pin. The operation of port 0 pins depends upon the pin function selected via the pin connect block. Pins P0.24, P0.26 and P0.27 are not available. P0.0/TXD0/ PWM1 19[1] I/O P0.0 — General purpose input/output digital pin (GPIO). O TXD0 — Transmitter output for UART0. O PWM1 — Pulse Width Modulator output 1. P0.1/RXD0/ PWM3/EINT0 21[2] I/O P0.1 — General purpose input/output digital pin (GPIO). I RXD0 — Receiver input for UART0. O PWM3 — Pulse Width Modulator output 3. I EINT0 — External interrupt 0 input. P0.2/SCL0/ CAP0.0 22[3] I/O P0.2 — General purpose input/output digital pin (GPIO). I/O SCL0 — I 2C0 clock input/output. Open-drain output (for I2C-bus compliance). I CAP0.0 — Capture input for Timer 0, channel 0. P0.3/SDA0/ MAT0.0/EINT1 26[3] I/O P0.3 — General purpose input/output digital pin (GPIO). I/O SDA0 — I 2C0 data input/output. Open-drain output (for I2C-bus compliance). O MAT0.0 — Match output for Timer 0, channel 0. I EINT1 — External interrupt 1 input. P0.4/SCK0/ CAP0.1/AD0.6 27[4] I/O P0.4 — General purpose input/output digital pin (GPIO). I/O SCK0 — Serial clock for SPI0. SPI clock output from master or input to slave. I CAP0.1 — Capture input for Timer 0, channel 1. I AD0.6 — ADC 0, input 6. P0.5/MISO0/ MAT0.1/AD0.7 29[4] I/O P0.5 — General purpose input/output digital pin (GPIO). I/O MISO0 — Master In Slave Out for SPI0. Data input to SPI master or data output from SPI slave. O MAT0.1 — Match output for Timer 0, channel 1. I AD0.7 — ADC 0, input 7. P0.6/MOSI0/ CAP0.2/AD1.0 30[4] I/O P0.6 — General purpose input/output digital pin (GPIO). I/O MOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data input to SPI slave. I CAP0.2 — Capture input for Timer 0, channel 2. I AD1.0 — ADC 1, input 0. Available in LPC2144/46/48 only. P0.7/SSEL0/ PWM2/EINT2 31[2] I/O P0.7 — General purpose input/output digital pin (GPIO). I SSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave. O PWM2 — Pulse Width Modulator output 2. I EINT2 — External interrupt 2 input. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 8 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers P0.8/TXD1/ PWM4/AD1.1 33[4] I/O P0.8 — General purpose input/output digital pin (GPIO). O TXD1 — Transmitter output for UART1. O PWM4 — Pulse Width Modulator output 4. I AD1.1 — ADC 1, input 1. Available in LPC2144/46/48 only. P0.9/RXD1/ PWM6/EINT3 34[2] I/O P0.9 — General purpose input/output digital pin (GPIO). I RXD1 — Receiver input for UART1. O PWM6 — Pulse Width Modulator output 6. I EINT3 — External interrupt 3 input. P0.10/RTS1/ CAP1.0/AD1.2 35[4] I/O P0.10 — General purpose input/output digital pin (GPIO). O RTS1 — Request to Send output for UART1. LPC2144/46/48 only. I CAP1.0 — Capture input for Timer 1, channel 0. I AD1.2 — ADC 1, input 2. Available in LPC2144/46/48 only. P0.11/CTS1/ CAP1.1/SCL1 37[3] I/O P0.11 — General purpose input/output digital pin (GPIO). I CTS1 — Clear to Send input for UART1. Available in LPC2144/46/48 only. I CAP1.1 — Capture input for Timer 1, channel 1. I/O SCL1 — I 2C1 clock input/output. Open-drain output (for I2C-bus compliance) P0.12/DSR1/ MAT1.0/AD1.3 38[4] I/O P0.12 — General purpose input/output digital pin (GPIO). I DSR1 — Data Set Ready input for UART1. Available in LPC2144/46/48 only. O MAT1.0 — Match output for Timer 1, channel 0. I AD1.3 — ADC 1 input 3. Available in LPC2144/46/48 only. P0.13/DTR1/ MAT1.1/AD1.4 39[4] I/O P0.13 — General purpose input/output digital pin (GPIO). O DTR1 — Data Terminal Ready output for UART1. LPC2144/46/48 only. O MAT1.1 — Match output for Timer 1, channel 1. I AD1.4 — ADC 1 input 4. Available in LPC2144/46/48 only. P0.14/DCD1/ EINT1/SDA1 41[3] I/O P0.14 — General purpose input/output digital pin (GPIO). I DCD1 — Data Carrier Detect input for UART1. LPC2144/46/48 only. I EINT1 — External interrupt 1 input. I/O SDA1 — I 2C1 data input/output. Open-drain output (for I2C-bus compliance). Note: LOW on this pin while RESET is LOW forces on-chip boot loader to take over control of the part after reset. P0.15/RI1/ EINT2/AD1.5 45[4] I/O P0.15 — General purpose input/output digital pin (GPIO). I RI1 — Ring Indicator input for UART1. Available in LPC2144/46/48 only. I EINT2 — External interrupt 2 input. I AD1.5 — ADC 1, input 5. Available in LPC2144/46/48 only. Table 3. Pin description …continued Symbol Pin Type Description LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 9 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers P0.16/EINT0/ MAT0.2/CAP0.2 46[2] I/O P0.16 — General purpose input/output digital pin (GPIO). I EINT0 — External interrupt 0 input. O MAT0.2 — Match output for Timer 0, channel 2. I CAP0.2 — Capture input for Timer 0, channel 2. P0.17/CAP1.2/ SCK1/MAT1.2 47[1] I/O P0.17 — General purpose input/output digital pin (GPIO). I CAP1.2 — Capture input for Timer 1, channel 2. I/O SCK1 — Serial Clock for SSP. Clock output from master or input to slave. O MAT1.2 — Match output for Timer 1, channel 2. P0.18/CAP1.3/ MISO1/MAT1.3 53[1] I/O P0.18 — General purpose input/output digital pin (GPIO). I CAP1.3 — Capture input for Timer 1, channel 3. I/O MISO1 — Master In Slave Out for SSP. Data input to SPI master or data output from SSP slave. O MAT1.3 — Match output for Timer 1, channel 3. P0.19/MAT1.2/ MOSI1/CAP1.2 54[1] I/O P0.19 — General purpose input/output digital pin (GPIO). O MAT1.2 — Match output for Timer 1, channel 2. I/O MOSI1 — Master Out Slave In for SSP. Data output from SSP master or data input to SSP slave. I CAP1.2 — Capture input for Timer 1, channel 2. P0.20/MAT1.3/ SSEL1/EINT3 55[2] I/O P0.20 — General purpose input/output digital pin (GPIO). O MAT1.3 — Match output for Timer 1, channel 3. I SSEL1 — Slave Select for SSP. Selects the SSP interface as a slave. I EINT3 — External interrupt 3 input. P0.21/PWM5/ AD1.6/CAP1.3 1[4] I/O P0.21 — General purpose input/output digital pin (GPIO). O PWM5 — Pulse Width Modulator output 5. I AD1.6 — ADC 1, input 6. Available in LPC2144/46/48 only. I CAP1.3 — Capture input for Timer 1, channel 3. P0.22/AD1.7/ CAP0.0/MAT0.0 2[4] I/O P0.22 — General purpose input/output digital pin (GPIO). I AD1.7 — ADC 1, input 7. Available in LPC2144/46/48 only. I CAP0.0 — Capture input for Timer 0, channel 0. O MAT0.0 — Match output for Timer 0, channel 0. P0.23/VBUS 58[1] I/O P0.23 — General purpose input/output digital pin (GPIO). I VBUS — Indicates the presence of USB bus power. Note: This signal must be HIGH for USB reset to occur. P0.25/AD0.4/ AOUT 9[5] I/O P0.25 — General purpose input/output digital pin (GPIO). I AD0.4 — ADC 0, input 4. O AOUT — DAC output. Available in LPC2142/44/46/48 only. P0.28/AD0.1/ CAP0.2/MAT0.2 13[4] I/O P0.28 — General purpose input/output digital pin (GPIO). I AD0.1 — ADC 0, input 1. I CAP0.2 — Capture input for Timer 0, channel 2. O MAT0.2 — Match output for Timer 0, channel 2. Table 3. Pin description …continued Symbol Pin Type Description LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 10 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers P0.29/AD0.2/ CAP0.3/MAT0.3 14[4] I/O P0.29 — General purpose input/output digital pin (GPIO). I AD0.2 — ADC 0, input 2. I CAP0.3 — Capture input for Timer 0, channel 3. O MAT0.3 — Match output for Timer 0, channel 3. P0.30/AD0.3/ EINT3/CAP0.0 15[4] I/O P0.30 — General purpose input/output digital pin (GPIO). I AD0.3 — ADC 0, input 3. I EINT3 — External interrupt 3 input. I CAP0.0 — Capture input for Timer 0, channel 0. P0.31/UP_LED/ CONNECT 17[6] O P0.31 — General purpose output only digital pin (GPO). O UP_LED — USB GoodLink LED indicator. It is LOW when device is configured (non-control endpoints enabled). It is HIGH when the device is not configured or during global suspend. O CONNECT — Signal used to switch an external 1.5 k resistor under the software control. Used with the SoftConnect USB feature. Important: This is an digital output only pin. This pin MUST NOT be externally pulled LOW when RESET pin is LOW or the JTAG port will be disabled. P1.0 to P1.31 I/O Port 1: Port 1 is a 32-bit bidirectional I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block. Pins 0 through 15 of port 1 are not available. P1.16/ TRACEPKT0 16[6] I/O P1.16 — General purpose input/output digital pin (GPIO). Standard I/O port with internal pull-up. O TRACEPKT0 — Trace Packet, bit 0. P1.17/ TRACEPKT1 12[6] I/O P1.17 — General purpose input/output digital pin (GPIO). Standard I/O port with internal pull-up. O TRACEPKT1 — Trace Packet, bit 1. P1.18/ TRACEPKT2 8[6] I/O P1.18 — General purpose input/output digital pin (GPIO). Standard I/O port with internal pull-up. O TRACEPKT2 — Trace Packet, bit 2. P1.19/ TRACEPKT3 4[6] I/O P1.19 — General purpose input/output digital pin (GPIO). Standard I/O port with internal pull-up. O TRACEPKT3 — Trace Packet, bit 3. P1.20/ TRACESYNC 48[6] I/O P1.20 — General purpose input/output digital pin (GPIO). Standard I/O port with internal pull-up. O TRACESYNC — Trace Synchronization. Note: LOW on this pin while RESET is LOW enables pins P1.25:16 to operate as Trace port after reset. P1.21/ PIPESTAT0 44[6] I/O P1.21 — General purpose input/output digital pin (GPIO). Standard I/O port with internal pull-up. O PIPESTAT0 — Pipeline Status, bit 0. P1.22/ PIPESTAT1 40[6] I/O P1.22 — General purpose input/output digital pin (GPIO). Standard I/O port with internal pull-up. O PIPESTAT1 — Pipeline Status, bit 1. Table 3. Pin description …continued Symbol Pin Type Description LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 11 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers P1.23/ PIPESTAT2 36[6] I/O P1.23 — General purpose input/output digital pin (GPIO). Standard I/O port with internal pull-up. O PIPESTAT2 — Pipeline Status, bit 2. P1.24/ TRACECLK 32[6] I/O P1.24 — General purpose input/output digital pin (GPIO). Standard I/O port with internal pull-up. O TRACECLK — Trace Clock. P1.25/EXTIN0 28[6] I/O P1.25 — General purpose input/output digital pin (GPIO). Standard I/O port with internal pull-up. I EXTIN0 — External Trigger Input. P1.26/RTCK 24[6] I/O P1.26 — General purpose input/output digital pin (GPIO). I/O RTCK — Returned Test Clock output. Extra signal added to the JTAG port. Assists debugger synchronization when processor frequency varies. Bidirectional pin with internal pull-up. Note: LOW on RTCK while RESET is LOW enables pins P1[31:26] to operate as Debug port after reset. P1.27/TDO 64[6] I/O P1.27 — General purpose input/output digital pin (GPIO). O TDO — Test Data out for JTAG interface. P1.28/TDI 60[6] I/O P1.28 — General purpose input/output digital pin (GPIO). I TDI — Test Data in for JTAG interface. P1.29/TCK 56[6] I/O P1.29 — General purpose input/output digital pin (GPIO). I TCK — Test Clock for JTAG interface. This clock must be slower than 16 of the CPU clock (CCLK) for the JTAG interface to operate. P1.30/TMS 52[6] I/O P1.30 — General purpose input/output digital pin (GPIO). I TMS — Test Mode Select for JTAG interface. P1.31/TRST 20[6] I/O P1.31 — General purpose input/output digital pin (GPIO). I TRST — Test Reset for JTAG interface. D+ 10[7] I/O USB bidirectional D+ line. D 11[7] I/O USB bidirectional D line. RESET 57[8] I External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant. XTAL1 62[9] I Input to the oscillator circuit and internal clock generator circuits. XTAL2 61[9] O Output from the oscillator amplifier. RTCX1 3[9][10] I Input to the RTC oscillator circuit. RTCX2 5[9][10] O Output from the RTC oscillator circuit. VSS 6, 18, 25, 42, 50 I Ground: 0 V reference. VSSA 59 I Analog ground: 0 V reference. This should nominally be the same voltage as VSS, but should be isolated to minimize noise and error. VDD 23, 43, 51 I 3.3 V power supply: This is the power supply voltage for the core and I/O ports. Table 3. Pin description …continued Symbol Pin Type Description LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 12 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers [1] 5 V tolerant pad (no built-in pull-up resistor) providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. [2] 5 V tolerant pad (no built-in pull-up resistor) providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. If configured for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. [3] Open-drain 5 V tolerant digital I/O I2C-bus 400 kHz specification compatible pad. It requires external pull-up to provide an output functionality. [4] 5 V tolerant pad (no built-in pull-up resistor) providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog input function. If configured for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. When configured as an ADC input, digital section of the pad is disabled. [5] 5 V tolerant pad (no built-in pull-up resistor) providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog output function. When configured as the DAC output, digital section of the pad is disabled. [6] 5 V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. The pull-up resistor’s value typically ranges from 60 k to 300 k. [7] Pad is designed in accordance with the Universal Serial Bus (USB) specification, revision 2.0 (Full-speed and Low-speed mode only). [8] 5 V tolerant pad providing digital input (with TTL levels and hysteresis) function only. [9] Pad provides special analog functionality. [10] When unused, the RTCX1 pin can be grounded or left floating. For lowest power leave it floating. The other RTC pin, RTCX2, should be left floating. VDDA 7 I Analog 3.3 V power supply: This should be nominally the same voltage as VDD but should be isolated to minimize noise and error. This voltage is only used to power the on-chip ADC(s) and DAC. VREF 63 I ADC reference voltage: This should be nominally less than or equal to the VDD voltage but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC(s) and DAC. VBAT 49 I RTC power supply voltage: 3.3 V on this pin supplies the power to the RTC. Table 3. Pin description …continued Symbol Pin Type Description LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 13 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers 6. Functional description 6.1 Architectural overview The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers (CISC). This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets: • The standard 32-bit ARM set. • A 16-bit Thumb set. The Thumb set’s 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because Thumb code operates on the same 32-bit register set as ARM code. Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the performance of an equivalent ARM processor connected to a 16-bit memory system. The particular flash implementation in the LPC2141/42/44/46/48 allows for full speed execution also in ARM mode. It is recommended to program performance critical and short code sections (such as interrupt service routines and DSP algorithms) in ARM mode. The impact on the overall code size will be minimal but the speed can be increased by 30 % over Thumb mode. 6.2 On-chip flash program memory The LPC2141/42/44/46/48 incorporate a 32 kB, 64 kB, 128 kB, 256 kB and 512 kB flash memory system respectively. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the serial port. The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc. Due to the architectural solution chosen for an on-chip boot loader, flash memory available for user’s code on LPC2141/42/44/46/48 is 32 kB, 64 kB, 128 kB, 256 kB and 500 kB respectively. The LPC2141/42/44/46/48 flash memory provides a minimum of 100000 erase/write cycles and 20 years of data-retention. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 14 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers 6.3 On-chip static RAM On-chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8-bit, 16-bit, and 32-bit. The LPC2141, LPC2142/44 and LPC2146/48 provide 8 kB, 16 kB and 32 kB of static RAM respectively. In case of LPC2146/48 only, an 8 kB SRAM block intended to be utilized mainly by the USB can also be used as a general purpose RAM for data storage and code storage and execution. 6.4 Memory map The LPC2141/42/44/46/48 memory map incorporates several distinct regions, as shown in Figure 5. In addition, the CPU interrupt vectors may be remapped to allow them to reside in either flash memory (the default) or on-chip static RAM. This is described in Section 6.19 “System control”. Fig 5. LPC2141/42/44/46/48 memory map AHB PERIPHERALS VPB PERIPHERALS RESERVED ADDRESS SPACE BOOT BLOCK (12 kB REMAPPED FROM ON-CHIP FLASH MEMORY RESERVED ADDRESS SPACE 0xFFFF FFFF 0xF000 0000 0xE000 0000 0xC000 0000 0x8000 0000 0x7FFF FFFF 0x7FD0 2000 TOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY (LPC2148) 0x0004 0000 0x0007 FFFF TOTAL OF 256 kB ON-CHIP NON-VOLATILE MEMORY (LPC2146) 0x0002 0000 0x0003 FFFF TOTAL OF 128 kB ON-CHIP NON-VOLATILE MEMORY (LPC2144) 0x0001 0000 0x0001 FFFF TOTAL OF 64 kB ON-CHIP NON-VOLATILE MEMORY (LPC2142) 0x0000 8000 0x0000 FFFF TOTAL OF 32 kB ON-CHIP NON-VOLATILE MEMORY (LPC2141) 0x0000 0000 0x0000 7FFF RESERVED ADDRESS SPACE 0x0008 0000 0x3FFF FFFF 8 kB ON-CHIP STATIC RAM (LPC2141) 0x4000 0000 0x4000 1FFF 16 kB ON-CHIP STATIC RAM (LPC2142/2144) 0x4000 2000 0x4000 3FFF 32 kB ON-CHIP STATIC RAM (LPC2146/2148) 0x4000 4000 0x4000 7FFF RESERVED ADDRESS SPACE 0x4000 8000 0x7FCF FFFF 8 kB ON-CHIP USB DMA RAM (LPC2146/2148) 0x7FD0 0000 0x7FD0 1FFF 0x7FFF D000 0x7FFF CFFF 4.0 GB 3.75 GB 3.5 GB 3.0 GB 2.0 GB 1.0 GB 0.0 GB 002aab558 LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 15 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers 6.5 Interrupt controller The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and categorizes them as Fast Interrupt reQuest (FIQ), vectored Interrupt ReQuest (IRQ), and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine does not need to branch into the interrupt service routine but can run from the interrupt vector location. If more than one request is assigned to the FIQ class, the FIQ service routine will read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt. Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned to this category. Any of the interrupt requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest. Non-vectored IRQs have the lowest priority. The VIC combines the requests from all the vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are pending, the VIC provides the address of the highest-priority requesting IRQs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored IRQs. The default routine can read another VIC register to see what IRQs are active. 6.5.1 Interrupt sources Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller, but may have several internal interrupt flags. Individual interrupt flags may also represent more than one interrupt source. 6.6 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. The Pin Control Module with its pin select registers defines the functionality of the microcontroller in a given hardware environment. After reset all pins of Port 0 and Port 1 are configured as input with the following exceptions: If debug is enabled, the JTAG pins will assume their JTAG functionality; if trace is enabled, the Trace pins will assume their trace functionality. The pins associated with the I2C0 and I2C1 interface are open drain. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 16 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers 6.7 Fast general purpose parallel I/O (GPIO) Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back, as well as the current state of the port pins. LPC2141/42/44/46/48 introduce accelerated GPIO functions over prior LPC2000 devices: • GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing. • Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. • All GPIO registers are byte addressable. • Entire port value can be written in one instruction. 6.7.1 Features • Bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. • Direction control of individual bits. • Separate control of output set and clear. • All I/O default to inputs after reset. 6.8 10-bit ADC The LPC2141/42 contain one and the LPC2144/46/48 contain two analog to digital converters. These converters are single 10-bit successive approximation analog to digital converters. While ADC0 has six channels, ADC1 has eight channels. Therefore, total number of available ADC inputs for LPC2141/42 is 6 and for LPC2144/46/48 is 14. 6.8.1 Features • 10 bit successive approximation analog to digital converter. • Measurement range of 0 V to VREF (2.5 V VREF VDDA). • Each converter capable of performing more than 400000 10-bit samples per second. • Every analog input has a dedicated result register to reduce interrupt overhead. • Burst conversion mode for single or multiple inputs. • Optional conversion on transition on input pin or timer match signal. • Global Start command for both converters (LPC2142/44/46/48 only). 6.9 10-bit DAC The DAC enables the LPC2141/42/44/46/48 to generate a variable analog output. The maximum DAC output voltage is the VREF voltage. 6.9.1 Features • 10-bit DAC. • Buffered output. • Power-down mode available. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 17 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers • Selectable speed versus power. 6.10 USB 2.0 device controller The USB is a 4-wire serial bus that supports communication between a host and a number (127 max) of peripherals. The host controller allocates the USB bandwidth to attached devices through a token based protocol. The bus supports hot plugging, unplugging, and dynamic configuration of the devices. All transactions are initiated by the host controller. The LPC2141/42/44/46/48 is equipped with a USB device controller that enables 12 Mbit/s data exchange with a USB host controller. It consists of a register interface, serial interface engine, endpoint buffer memory and DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate end point buffer memory. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. A DMA controller (available in LPC2146/48 only) can transfer data between an endpoint buffer and the USB RAM. 6.10.1 Features • Fully compliant with USB 2.0 Full-speed specification. • Supports 32 physical (16 logical) endpoints. • Supports control, bulk, interrupt and isochronous endpoints. • Scalable realization of endpoints at run time. • Endpoint maximum packet size selection (up to USB maximum specification) by software at run time. • RAM message buffer size based on endpoint realization and maximum packet size. • Supports SoftConnect and GoodLink LED indicator. These two functions are sharing one pin. • Supports bus-powered capability with low suspend current. • Supports DMA transfer on all non-control endpoints (LPC2146/48 only). • One duplex DMA channel serves all endpoints (LPC2146/48 only). • Allows dynamic switching between CPU controlled and DMA modes (only in LPC2146/48). • Double buffer implementation for bulk and isochronous endpoints. 6.11 UARTs The LPC2141/42/44/46/48 each contain two UARTs. In addition to standard transmit and receive data lines, the LPC2144/46/48 UART1 also provides a full modem control handshake interface. Compared to previous LPC2000 microcontrollers, UARTs in LPC2141/42/44/46/48 introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers to achieve standard baud rates such as 115200 with any crystal frequency above 2 MHz. In addition, auto-CTS/RTS flow-control functions are fully implemented in hardware (UART1 in LPC2144/46/48 only). LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 18 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers 6.11.1 Features • 16 B Receive and Transmit FIFOs. • Register locations conform to 16C550 industry standard. • Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B • Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • Transmission FIFO control enables implementation of software (XON/XOFF) flow control on both UARTs. • LPC2144/46/48 UART1 equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). 6.12 I2C-bus serial I/O controller The LPC2141/42/44/46/48 each contain two I2C-bus controllers. The I2C-bus is bidirectional, for inter-IC control using only two wires: a Serial Clock Line (SCL), and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the capability to both receive and send information (such as memory)). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus, it can be controlled by more than one bus master connected to it. The I2C-bus implemented in LPC2141/42/44/46/48 supports bit rates up to 400 kbit/s (Fast I2C-bus). 6.12.1 Features • Compliant with standard I2C-bus interface. • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • The I2C-bus can be used for test and diagnostic purposes. 6.13 SPI serial I/O controller The LPC2141/42/44/46/48 each contain one SPI controller. The SPI is a full duplex serial interface, designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 19 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers 6.13.1 Features • Compliant with SPI specification. • Synchronous, Serial, Full Duplex, Communication. • Combined SPI master and slave. • Maximum data bit rate of one eighth of the input clock rate. 6.14 SSP serial I/O controller The LPC2141/42/44/46/48 each contain one Serial Synchronous Port controller (SSP). The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. However, only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with data frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. Often only one of these data flows carries meaningful data. 6.14.1 Features • Compatible with Motorola’s SPI, TI’s 4-wire SSI and National Semiconductor’s Microwire buses. • Synchronous serial communication. • Master or slave operation. • 8-frame FIFOs for both transmit and receive. • Four bits to 16 bits per frame. 6.15 General purpose timers/external event counters The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally supplied clock and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. Multiple pins can be selected to perform a single capture or match function, providing an application with ‘or’ and ‘and’, as well as ‘broadcast’ functions among them. The LPC2141/42/44/46/48 can count external events on one of the capture inputs if the minimum external pulse is equal or longer than a period of the PCLK. In this configuration, unused capture lines can be selected as regular timer capture inputs, or used as external interrupts. 6.15.1 Features • A 32-bit timer/counter with a programmable 32-bit prescaler. • External event counter or timer operation. • Four 32-bit capture channels per timer/counter that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt. • Four 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 20 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Four external outputs per timer/counter corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. 6.16 Watchdog timer The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined amount of time. 6.16.1 Features • Internally resets chip if not periodically reloaded. • Debug mode. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 32-bit timer with internal pre-scaler. • Selectable time period from (Tcy(PCLK) 256 4) to (Tcy(PCLK) 232 4) in multiples of Tcy(PCLK) 4. 6.17 Real-time clock The RTC is designed to provide a set of counters to measure time when normal or idle operating mode is selected. The RTC has been designed to use little power, making it suitable for battery powered systems where the CPU is not running continuously (Idle mode). 6.17.1 Features • Measures the passage of time to maintain a calendar and clock. • Ultra-low power design to support battery powered systems. • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. • Can use either the RTC dedicated 32 kHz oscillator input or clock derived from the external crystal/oscillator input at XTAL1. Programmable reference clock divider allows fine adjustment of the RTC. • Dedicated power supply pin can be connected to a battery or the main 3.3 V. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 21 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers 6.18 Pulse width modulator The PWM is based on the standard timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2141/42/44/46/48. The timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is also based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. One match register (MR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an MR0 match occurs. Three match registers can be used to provide a PWM output with both edges controlled. Again, the MR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge). 6.18.1 Features • Seven match registers allow up to six single edge controlled or three double edge controlled PWM outputs, or a mix of both types. • The match registers also allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the output is a constant LOW. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses. • Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. • Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 22 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers • Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must ‘release’ new match values before they can become effective. • May be used as a standard timer if the PWM mode is not enabled. • A 32-bit Timer/Counter with a programmable 32-bit Prescaler. 6.19 System control 6.19.1 Crystal oscillator On-chip integrated oscillator operates with external crystal in range of 1 MHz to 25 MHz. The oscillator output frequency is called fosc and the ARM processor clock frequency is referred to as CCLK for purposes of rate equations, etc. fosc and CCLK are the same value unless the PLL is running and connected. Refer to Section 6.19.2 “PLL” for additional information. 6.19.2 PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The PLL settling time is 100 s. 6.19.3 Reset and wake-up timer Reset has two sources on the LPC2141/42/44/46/48: the RESET pin and watchdog reset. The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip reset by any source starts the Wake-up Timer (see Wake-up Timer description below), causing the internal chip reset to remain asserted until the external reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the on-chip flash controller has completed its initialization. When the internal reset is removed, the processor begins executing at address 0, which is the reset vector. At that point, all of the processor and peripheral registers have been initialized to predetermined values. The Wake-up Timer ensures that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions. This is important at power on, all types of reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the Wake-up Timer. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 23 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers The Wake-up Timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. 6.19.4 Brownout detector The LPC2141/42/44/46/48 include 2-stage monitoring of the voltage on the VDD pins. If this voltage falls below 2.9 V, the BOD asserts an interrupt signal to the VIC. This signal can be enabled for interrupt; if not, software can monitor the signal by reading dedicated register. The second stage of low voltage detection asserts reset to inactivate the LPC2141/42/44/46/48 when the voltage on the VDD pins falls below 2.6 V. This reset prevents alteration of the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the POR circuitry maintains the overall reset. Both the 2.9 V and 2.6 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.9 V detection to reliably interrupt, or a regularly-executed event loop to sense the condition. 6.19.5 Code security This feature of the LPC2141/42/44/46/48 allow an application to control whether it can be debugged or protected from observation. If after reset on-chip boot loader detects a valid checksum in flash and reads 0x8765 4321 from address 0x1FC in flash, debugging will be disabled and thus the code in flash will be protected from observation. Once debugging is disabled, it can be enabled only by performing a full chip erase using the ISP. 6.19.6 External interrupt inputs The LPC2141/42/44/46/48 include up to nine edge or level sensitive External Interrupt Inputs as selectable pin functions. When the pins are combined, external events can be processed as four independent interrupt signals. The External Interrupt Inputs can optionally be used to wake-up the processor from Power-down mode. Additionally capture input pins can also be used as external interrupts without the option to wake the device up from Power-down mode. 6.19.7 Memory mapping control The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip flash memory, or to the on-chip static RAM. This allows code running in different memory spaces to have control of the interrupts. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 24 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers 6.19.8 Power control The LPC2141/42/44/46/48 supports two reduced power modes: Idle mode and Power-down mode. In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses. In Power-down mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Power-down mode and the logic levels of chip output pins remain static. The Power-down mode can be terminated and normal operation resumed by either a reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Power-down mode reduces chip power consumption to nearly zero. Selecting an external 32 kHz clock instead of the PCLK as a clock-source for the on-chip RTC will enable the microcontroller to have the RTC active during Power-down mode. Power-down current is increased with RTC active. However, it is significantly lower than in Idle mode. A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings during active and Idle mode. 6.19.9 APB bus The APB divider determines the relationship between the processor clock (CCLK) and the clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first is to provide peripherals with the desired PCLK via APB bus so that they can operate at the speed chosen for the ARM processor. In order to achieve this, the APB bus may be slowed down to 12 to 14 of the processor clock rate. Because the APB bus must work properly at power-up (and its timing cannot be altered if it does not work since the APB divider control registers reside on the APB bus), the default condition at reset is for the APB bus to run at 14 of the processor clock rate. The second purpose of the APB divider is to allow power savings when an application does not require any peripherals to run at the full processor rate. Because the APB divider is connected to the PLL output, the PLL remains active (if it was running) during Idle mode. 6.20 Emulation and debugging The LPC2141/42/44/46/48 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Debugging and trace functions are multiplexed only with GPIOs on Port 1. This means that all communication, timer and interface peripherals residing on Port 0 are available during the development and debugging phase as they are when the application is run in the embedded system itself. 6.20.1 EmbeddedICE Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the remote debug protocol commands to the JTAG data needed to access the ARM core. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 25 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers The ARM core has a Debug Communication Channel (DCC) function built-in. The DCC allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state. The DCC is accessed as a co-processor 14 by the program running on the ARM7TDMI-S core. The DCC allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The DCC data and control registers are mapped in to addresses in the EmbeddedICE logic. This clock must be slower than 16 of the CPU clock (CCLK) for the JTAG interface to operate. 6.20.2 Embedded trace Since the LPC2141/42/44/46/48 have significant amounts of on-chip memory, it is not possible to determine how the processor core is operating simply by observing the external pins. The Embedded Trace Macrocell (ETM) provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to the trace port. The ETM is connected directly to the ARM core and not to the main AMBA system bus. It compresses the trace information and exports it through a narrow trace port. An external trace port analyzer must capture the trace information under software debugger control. Instruction trace (or PC trace) shows the flow of execution of the processor and provides a list of all the instructions that were executed. Instruction trace is significantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. Trace information generation can be controlled by selecting the trigger resource. Trigger resources include address comparators, counters and sequencers. Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code can not be traced because of this restriction. 6.20.3 RealMonitor RealMonitor is a configurable software module, developed by ARM Inc., which enables real-time debug. It is a lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC, which is present in the EmbeddedICE logic. The LPC2141/42/44/46/48 contain a specific configuration of RealMonitor software programmed into the on-chip flash memory. LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 26 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers 7. Limiting values [1] The following applies to the Limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. [2] Including voltage on outputs in 3-state mode. [3] Not to exceed 4.6 V. [4] The peak current is limited to 25 times the corresponding maximum current. [5] Dependent on package type. [6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VDD supply voltage (core and external rail) 0.5 +3.6 V VDDA analog 3.3 V pad supply voltage 0.5 +4.6 V Vi(VBAT) input voltage on pin VBAT for the RTC 0.5 +4.6 V Vi(VREF) input voltage on pin VREF 0.5 +4.6 V VIA analog input voltage on ADC related pins 0.5 +5.1 V VI input voltage 5 V tolerant I/O pins; only valid when the VDD supply voltage is present [2] 0.5 +6.0 V other I/O pins [2][3] 0.5 VDD + 0.5 V IDD supply current per supply pin [4] - 100 mA ISS ground current per ground pin [4] - 100 mA Isink sink current for I2C-bus; DC; T = 85 C - 20 mA Tstg storage temperature [5] 65 +150 C Ptot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 W Vesd electrostatic discharge voltage human body model [6] all pins 4000 +4000 V LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 27 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers 8. Static characteristics Table 5. Static characteristics Tamb = 40 C to +85 C for commercial applications, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VDD supply voltage [2] 3.0 3.3 3.6 V VDDA analog supply voltage 3.3 V pad 3.0 3.3 3.6 V Vi(VBAT) input voltage on pin VBAT [3] 2.0 3.3 3.6 V Vi(VREF) input voltage on pin VREF 2.5 3.3 VDDA V Standard port pins, RESET, P1.26/RTCK IIL LOW-level input current VI = 0 V; no pull-up - - 3 A IIH HIGH-level input current VI = VDD; no pull-down - - 3 A IOZ OFF-state output current VO = 0 V; VO = VDD; no pull-up/down --3 A Ilatch I/O latch-up current (0.5VDD) < VI < (1.5VDD); Tj < 125 C - - 100 mA VI input voltage pin configured to provide a digital function [4][5][6] [7] 0- 5.5 V VO output voltage output active 0 - VDD V VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V Vhys hysteresis voltage 0.4 - - V VOH HIGH-level output voltage IOH = 4 mA [8] VDD 0.4 - - V VOL LOW-level output voltage IOL = 4 mA [8] --0.4 V IOH HIGH-level output current VOH = VDD 0.4 V [8] 4 - - mA IOL LOW-level output current VOL = 0.4 V [8] 4- - mA IOHS HIGH-level short-circuit output current VOH =0V [9] - - 45 mA IOLS LOW-level short-circuit output current VOL = VDDA [9] --50 mA Ipd pull-down current VI =5V [10] 10 50 150 A Ipu pull-up current VI =0V [11] 15 50 85 A VDD < VI <5V [10] 000 A LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 28 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers IDD(act) active mode supply current VDD = 3.3 V; Tamb = 25 C; code while(1){} executed from flash, no active peripherals CCLK = 10 MHz - 15 50 mA CCLK = 60 MHz - 40 70 mA VDD = 3.3 V; Tamb = 25 C; code executed from flash; USB enabled and active; all other peripherals disabled CCLK = 12 MHz - 27 70 mA CCLK = 60 MHz - 57 90 mA IDD(pd) Power-down mode supply current VDD = 3.3 V; Tamb = 25 C - 40 100 A VDD = 3.3 V; Tamb = 85 C -250 500 A IBATpd Power-down mode battery supply current RTC clock = 32 kHz (from RTCXn pins); Tamb = 25 C VDD = 3.0 V; Vi(VBAT) = 2.5 V [12] - 15 30 A VDD = 3.0 V; Vi(VBAT) = 3.0 V - 20 40 A IBATact active mode battery supply current CCLK = 60 MHz; PCLK = 15 MHz; PCLK enabled to RTCK; RTC clock = 32 kHz (from RTCXn pins); Tamb = 25 C VDD = 3.0 V; Vi(VBAT) = 3.0 V [12] - 78 - A IBATact(opt) optimized active mode battery supply current PCLK disabled to RTCK in the PCONP register; RTC clock = 32 kHz (from RTCXn pins); Tamb = 25 C; Vi(VBAT) = 3.3 V CCLK = 25 MHz [12][13] - 23 - A CCLK = 60 MHz - 30 - A I 2C-bus pins VIH HIGH-level input voltage 0.7VDD --V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage - 0.05VDD - V VOL LOW-level output voltage IOLS = 3 mA [8] --0.4 V ILI input leakage current VI = VDD [14] - 24 A VI = 5 V - 10 22 A Oscillator pins Vi(XTAL1) input voltage on pin XTAL1 0.5 1.8 1.95 V Table 5. Static characteristics …continued Tamb = 40 C to +85 C for commercial applications, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 12 August 2011 29 of 45 NXP Semiconductors LPC2141/42/44/46/48 Single-chip 16-bit/32-bit microcontrollers [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [2] Core and external rail. [3] The RTC typically fails when Vi(VBAT) drops below 1.6 V. [4] Including voltage on outputs in 3-state mode. [5] VDD supply voltages must be present. [6] 3-state outputs go into 3-state mode when VDD is grounded. [7] Please also see the errata note mentioned in errata sheet. [8] Accounts for 100 mV voltage drop in all supply lines. [9] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [10] Minimum condition for VI = 4.5 V, maximum condition for VI = 5.5 V. [11] Applies to P1.16 to P1.31. [12] On pin VBAT. [13] Optimized for low battery consumption. [14] To VSS. [15] Includes external resistors of 33 ± 1 % on D+ and D. Vo(XTAL2) output voltage on pin XTAL2 0.5 1.8 1.95 V Vi(RTCX1) input voltage on pin RTCX1 0.5 1.8 1.95 V Vo(RTCX2) output voltage on pin RTCX2 0.5 1.8 1.95 V USB pins IOZ OFF-state output current 0V