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Farnell PDF
PN512 - NXP Semiconductors - Farnell Element 14
PN512 - NXP Semiconductors - Farnell Element 14
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Farnell Element 14 :
See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…
Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.
Puce électronique / Microchip :
Sans fil - Wireless :
Texas instrument :
Ordinateurs :
Logiciels :
Tutoriels :
Autres documentations :
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1. Introduction
This document describes the functionality and electrical specifications of the
transceiver IC PN512.
The PN512 is a highly integrated transceiver IC for contactless communication at
13.56 MHz. This transceiver IC utilizes an outstanding modulation and demodulation
concept completely integrated for different kinds of contactless communication methods
and protocols at 13.56 MHz.
1.1 Different available versions
The PN512 is available in three versions:
• PN5120A0HN1/C2 (HVQFN32), PN5120A0HN/C2 (HVQFN40) and PN5120A0ET/C2
(TFBGA64), hereafter named as version 2.0
• PN512AA0HN1/C2 (HVQFN32) and PN512AA0HN1/C2BI (HVQFN32 with Burn In),
hereafter named as industrial version, fulfilling the automotive qualification stated in
AEC-Q100 grade 3 from the Automotive Electronics Council, defining the critical
stress test qualification for automotive integrated circuits (ICs).
• PN5120A0HN1/C1(HVQFN32) and PN5120A0HN/C1 (HVQFN40), hereafter named
as version 1.0
The data sheet describes the functionality for the industrial version and version 2.0. The
differences of the version 1.0 to the version 2.0 are summarized in Section 21. The
industrial version has only differences within the outlined characteristics and limitations.
2. General description
The PN512 transceiver ICs support 4 different operating modes
• Reader/Writer mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme
• Reader/Writer mode supporting ISO/IEC 14443B
• Card Operation mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme
• NFCIP-1 mode
Enabled in Reader/Writer mode for ISO/IEC 14443A/MIFARE, the PN512’s internal
transmitter part is able to drive a reader/writer antenna designed to communicate with
ISO/IEC 14443A/ MIFARE cards and transponders without additional active circuitry. The
receiver part provides a robust and efficient implementation of a demodulation and
PN512
Full NFC Forum compliant solution
Rev. 4.5 — 17 December 2013
111345
Product data sheet
COMPANY PUBLICPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 4.5 — 17 December 2013
111345 2 of 136
NXP Semiconductors PN512
Full NFC Forum compliant solution
decoding circuitry for signals from ISO/IEC 14443A/MIFARE compatible cards and
transponders. The digital part handles the complete ISO/IEC 14443A framing and error
detection (Parity & CRC).
The PN512 supports MIFARE 1K or MIFARE 4K emulation products. The PN512 supports
contactless communication using MIFARE higher transfer speeds up to 424 kbit/s in both
directions.
Enabled in Reader/Writer mode for FeliCa, the PN512 transceiver IC supports the FeliCa
communication scheme. The receiver part provides a robust and efficient implementation
of the demodulation and decoding circuitry for FeliCa coded signals. The digital part
handles the FeliCa framing and error detection like CRC. The PN512 supports contactless
communication using FeliCa Higher transfer speeds up to 424 kbit/s in both directions.
The PN512 supports all layers of the ISO/IEC 14443B reader/writer communication
scheme, given correct implementation of additional components, like oscillator, power
supply, coil etc. and provided that standardized protocols, e.g. like ISO/IEC 14443-4
and/or ISO/IEC 14443B anticollision are correctly implemented.
In Card Operation mode, the PN512 transceiver IC is able to answer to a reader/writer
command either according to the FeliCa or ISO/IEC 14443A/MIFARE card interface
scheme. The PN512 generates the digital load modulated signals and in addition with an
external circuit the answer can be sent back to the reader/writer. A complete card
functionality is only possible in combination with a secure IC using the S2C interface.
Additionally, the PN512 transceiver IC offers the possibility to communicate directly to an
NFCIP-1 device in the NFCIP-1 mode. The NFCIP-1 mode offers different communication
mode and transfer speeds up to 424 kbit/s according to the Ecma 340 and ISO/IEC 18092
NFCIP-1 Standard. The digital part handles the complete NFCIP-1 framing and error
detection.
Various host controller interfaces are implemented:
• 8-bit parallel interface1
• SPI interface
• serial UART (similar to RS232 with voltage levels according pad voltage supply)
• I
2C interface.
A purchaser of this NXP IC has to take care for appropriate third party patent licenses.
1. 8-bit parallel Interface only available in HVQFN40 package.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 4.5 — 17 December 2013
111345 3 of 136
NXP Semiconductors PN512
Full NFC Forum compliant solution
3. Features and benefits
Highly integrated analog circuitry to demodulate and decode responses
Buffered output drivers for connecting an antenna with the minimum number of
external components
Integrated RF Level detector
Integrated data mode detector
Supports ISO/IEC 14443 A/MIFARE
Supports ISO/IEC 14443 B Read/Write modes
Typical operating distance in Read/Write mode up to 50 mm depending on the
antenna size and tuning
Typical operating distance in NFCIP-1 mode up to 50 mm depending on the antenna
size and tuning and power supply
Typical operating distance in ISO/IEC 14443A/MIFARE card or FeliCa Card Operation
mode of about 100 mm depending on the antenna size and tuning and the external
field strength
Supports MIFARE 1K or MIFARE 4K emulation encryption in Reader/Writer mode
ISO/IEC 14443A higher transfer speed communication at 212 kbit/s and 424 kbit/s
Contactless communication according to the FeliCa scheme at 212 kbit/s and
424 kbit/s
Integrated RF interface for NFCIP-1 up to 424 kbit/s
S2C interface
Additional power supply to directly supply the smart card IC connected via S2C
Supported host interfaces
SPI up to 10 Mbit/s
I
2C-bus interface up to 400 kBd in Fast mode, up to 3400 kBd in High-speed mode
RS232 Serial UART up to 1228.8 kBd, with voltage levels dependant on pin
voltage supply
8-bit parallel interface with and without Address Latch Enable
FIFO buffer handles 64 byte send and receive
Flexible interrupt modes
Hard reset with low power function
Power-down mode per software
Programmable timer
Internal oscillator for connection to 27.12 MHz quartz crystal
2.5 V to 3.6 V power supply
CRC coprocessor
Programmable I/O pins
Internal self-testPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 4.5 — 17 December 2013
111345 4 of 136
NXP Semiconductors PN512
Full NFC Forum compliant solution
4. Quick reference data
[1] Supply voltages below 3 V reduce the performance in, for example, the achievable operating distance.
[2] VDDA, VDDD and VDD(TVDD) must always be the same voltage.
[3] VDD(PVDD) must always be the same or lower voltage than VDDD.
[4] Ipd is the total current for all supplies.
[5] IDD(PVDD) depends on the overall load at the digital pins.
[6] IDD(TVDD) depends on VDD(TVDD) and the external circuit connected to pins TX1 and TX2.
[7] During typical circuit operation, the overall current is below 100 mA.
[8] Typical value using a complementary driver configuration and an antenna matched to 40 between pins TX1 and TX2 at 13.56 MHz.
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
VDDA analog supply voltage VDD(PVDD) VDDA = VDDD = VDD(TVDD);
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) =0V
[1][2] 2.5 - 3.6 V
VDDD digital supply voltage
VDD(TVDD) TVDD supply voltage
VDD(PVDD) PVDD supply voltage [3] 1.6 - 3.6 V
VDD(SVDD) SVDD supply voltage VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V 1.6 - 3.6 V
Ipd power-down current VDDA = VDDD = VDD(TVDD) =VDD(PVDD) =3V
hard power-down; pin NRSTPD set LOW [4] --5 A
soft power-down; RF level detector on [4] - - 10 A
IDDD digital supply current pin DVDD; VDDD =3V - 6.5 9 mA
IDDA analog supply current pin AVDD; VDDA = 3 V, CommandReg register’s
RcvOff bit = 0
- 7 10 mA
pin AVDD; receiver switched off; VDDA = 3 V,
CommandReg register’s RcvOff bit = 1
- 3 5 mA
IDD(PVDD) PVDD supply current pin PVDD [5] - - 40 mA
IDD(TVDD) TVDD supply current pin TVDD; continuous wave [6][7][8] - 60 100 mA
Tamb ambient temperature HVQFN32, HVQFN40, TFBGA64 30 +85 C
lndustrial version:
Ipd power-down current VDDA = VDDD = VDD(TVDD) =VDD(PVDD) =3V
hard power-down; pin NRSTPD set LOW [4] - - 15 A
soft power-down; RF level detector on [4] - - 30 A
Tamb ambient temperature HVQFN32 40 - +90 CPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 4.5 — 17 December 2013
111345 5 of 136
NXP Semiconductors PN512
Full NFC Forum compliant solution
5. Ordering information
Table 2. Ordering information
Type number Package
Name Description Version
PN5120A0HN1/C2 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;
32 terminal; body 5 5 0.85 mm
SOT617-1
PN5120A0HN/C2 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6 6 0.85 mm
SOT618-1
PN512AA0HN1/C2 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;
32 terminal; body 5 5 0.85 mm
SOT617-1
PN512AA0HN1/C2BI HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;
32 terminal; body 5 5 0.85 mm
SOT617-1
PN5120A0HN1/C1 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;
32 terminal; body 5 5 0.85 mm
SOT617-1
PN5120A0HN/C1 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6 6 0.85 mm
SOT618-1
PN5120A0ET/C2 TFBGA64 plastic thin fine-pitch ball grid array package; 64 balls SOT1336-1PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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6. Block diagram
The analog interface handles the modulation and demodulation of the analog signals
according to the Card Receiving mode, Reader/Writer mode and NFCIP-1 mode
communication scheme.
The RF level detector detects the presence of an external RF-field delivered by the
antenna to the RX pin.
The Data mode detector detects a MIFARE, FeliCa or NFCIP-1 mode in order to prepare
the internal receiver to demodulate signals, which are sent to the PN512.
The communication (S2C) interface provides digital signals to support communication for
transfer speeds above 424 kbit/s and digital signals to communicate to a secure IC.
The contactless UART manages the protocol requirements for the communication
protocols in cooperation with the host. The FIFO buffer ensures fast and convenient data
transfer to and from the host and the contactless UART and vice versa.
Various host interfaces are implemented to meet different customer requirements.
Fig 1. Simplified block diagram of the PN512
001aaj627
HOST
ANTENNA FIFO
BUFFER
ANALOG
INTERFACE
CONTACTLESS
UART SERIAL UART
SPI
I
2C-BUS
REGISTER BANKPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Fig 2. Detailed block diagram of the PN512
001aak602
DVDD
NRSTPD
IRQ
MFIN
MFOUT
SVDD
OSCIN
OSCOUT
VMID AUX1 AUX2 RX TVSS TX1 TX2 TVDD
16 19 20 17 10, 14 11 13 12
DVSS
AVDD
SDA/NSS/RX EA I2C PVDD PVSS
24 32 1 52
D1/ADR_5
25
D2/ADR_4
26
D3/ADR_3
27
D4/ADR_2
28
D5/ADR_1/
SCK/DTRQ
29
D6/ADR_0/
MOSI/MX
30
D7/SCL/
MISO/TX
31
AVSS
3
6
23
7
8
9
21
22
4
15
18
FIFO CONTROL
MIFARE CLASSIC UNIT
STATE MACHINE
COMMAND REGISTER
PROGRAMABLE TIMER
INTERRUPT CONTROL
CRC16
GENERATION AND CHECK
PARALLEL/SERIAL
CONVERTER
SERIAL DATA SWITCH
TRANSMITTER CONTROL
BIT COUNTER
PARITY GENERATION AND CHECK
FRAME GENERATION AND CHECK
BIT DECODING BIT ENCODING
RANDOM NUMBER
GENERATOR
ANALOG TO DIGITAL
CONVERTER
I-CHANNEL
AMPLIFIER
ANALOG TEST
MULTIPLEXOR
AND
DIGITAL TO
ANALOG
CONVERTER
I-CHANNEL
DEMODULATOR
Q-CHANNEL
AMPLIFIER
CLOCK
GENERATION,
FILTERING AND
DISTRIBUTION
Q-CLOCK
GENERATION
OSCILLATOR
TEMPERATURE
SENSOR
Q-CHANNEL
DEMODULATOR
AMPLITUDE
RATING
REFERENCE
VOLTAGE
64-BYTE FIFO
BUFFER
CONTROL REGISTER
BANK
SPI, UART, I2C-BUS INTERFACE CONTROL
VOLTAGE
MONITOR
AND
POWER ON
DETECT
RESET
CONTROL
POWER-DOWN
CONTROLPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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7. Pinning information
7.1 Pinning
Fig 3. Pinning configuration HVQFN32 (SOT617-1)
Fig 4. Pinning configuration HVQFN40 (SOT618-1)
001aan212
PN512
Transparent top view
RX
SIGIN
SIGOUT
AVSS
NRSTPD AUX1
PVSS AUX2
DVSS OSCIN
DVDD OSCOUT
PVDD IRQ
A1 ALE SVDD TVSS TX1 TVDD TX2 TVSS AVDD VMID A0D7 D6 D5 D4 D3 D2 D1
8 17
7 18
6 19
5 20
4 21
3 22
2 23
1 24
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
terminal 1
index area
001aan213
PN512
AVSS
NRSTPD
SIGIN
AUX1
PVSS AUX2
DVSS OSCIN
DVDD OSCOUT
PVDD IRQ
A5 NWR
A4 NRD
A3 ALE
A2 NCS SIGOUT SVDD TVSS TX1 TVDD TX2 TVSS AVDD VMIDRX A1A0D7 D6 D5 D4 D3 D2 D1 D0
10 21
9 22
8 23
7 24
6 25
5 26
4 27
3 28
2 29
1 30 11121314151617181920 40393837363534333231
terminal 1
index area
Transparent top viewPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Fig 5. Pin configuration TFBGA64 (SOT1336-1)
aaa-005873
TFBGA64
Transparent top view
ball A1
index area
H
G
F
E
D
C
B
A
1 3 5 78 246PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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7.2 Pin description
Table 3. Pin description HVQFN32
Pin Symbol Type Description
1 A1 I Address Line
2 PVDD PWR Pad power supply
3 DVDD PWR Digital Power Supply
4 DVSS PWR Digital Ground
5 PVSS PWR Pad power supply ground
6 NRSTPD I Not Reset and Power Down: When LOW, internal current sinks are switched off, the
oscillator is inhibited, and the input pads are disconnected from the outside world. With
a positive edge on this pin the internal reset phase starts.
7 SIGIN I Communication Interface Input: accepts a digital, serial data stream
8 SIGOUT O Communication Interface Output: delivers a serial data stream
9 SVDD PWR S2C Pad Power Supply: provides power to the S2C pads
10 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2
11 TX1 O Transmitter 1: delivers the modulated 13.56 MHz energy carrier
12 TVDD PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2
13 TX2 O Transmitter 2: delivers the modulated 13.56 MHz energy carrier
14 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2
15 AVDD PWR Analog Power Supply
16 VMID PWR Internal Reference Voltage: This pin delivers the internal reference voltage.
17 RX I Receiver Input
18 AVSS PWR Analog Ground
19 AUX1 O Auxiliary Outputs: These pins are used for testing.
20 AUX2 O
21 OSCIN I Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is
also the input for an externally generated clock (fosc = 27.12 MHz).
22 OSCOUT O Crystal Oscillator Output: Output of the inverting amplifier of the oscillator.
23 IRQ O Interrupt Request: output to signal an interrupt event
24 ALE I Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch
when HIGH.
25 to 31 D1 to D7 I/O 8-bit Bi-directional Data Bus.
Remark: An 8-bit parallel interface is not available.
Remark: If the host controller selects I2C as digital host controller interface, these pins
can be used to define the I2C address.
Remark: For serial interfaces this pins can be used for test signals or I/Os.
32 A0 I Address LinePN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Table 4. Pin description HVQFN40
Pin Symbol Type Description
1 to 4 A2 to A5 I Address Line
5 PVDD PWR Pad power supply
6 DVDD PWR Digital Power Supply
7 DVSS PWR Digital Ground
8 PVSS PWR Pad power supply ground
9 NRSTPD I Not Reset and Power Down: When LOW, internal current sinks are switched off, the
oscillator is inhibited, and the input pads are disconnected from the outside world. With
a positive edge on this pin the internal reset phase starts.
10 SIGIN I Communication Interface Input: accepts a digital, serial data stream
11 SIGOUT O Communication Interface Output: delivers a serial data stream
12 SVDD PWR S2C Pad Power Supply: provides power to the S2C pads
13 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2
14 TX1 O Transmitter 1: delivers the modulated 13.56 MHz energy carrier
15 TVDD PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2
16 TX2 O Transmitter 2: delivers the modulated 13.56 MHz energy carrier
17 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2
18 AVDD PWR Analog Power Supply
19 VMID PWR Internal Reference Voltage: This pin delivers the internal reference voltage.
20 RX I Receiver Input
21 AVSS PWR Analog Ground
22 AUX1 O Auxiliary Outputs: These pins are used for testing.
23 AUX2 O
24 OSCIN I Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is
also the input for an externally generated clock (fosc = 27.12 MHz).
25 OSCOUT O Crystal Oscillator Output: Output of the inverting amplifier of the oscillator.
26 IRQ O Interrupt Request: output to signal an interrupt event
27 NWR I Not Write: strobe to write data (applied on D0 to D7) into the PN512 register
28 NRD I Not Read: strobe to read data from the PN512 register (applied on D0 to D7)
29 ALE I Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch
when HIGH.
30 NCS I Not Chip Select: selects and activates the host controller interface of the PN512
31 to 38 D0 to D7 I/O 8-bit Bi-directional Data Bus.
Remark: For serial interfaces this pins can be used for test signals or I/Os.
Remark: If the host controller selects I2C as digital host controller interface, these pins
can be used to define the I2C address.
39 to 40 A0 to A1 I Address LinePN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Table 5. Pin description TFBGA64
Pin Symbol Type Description
A1 to A5, A8,
B3, B4, B8, E1
PVSS PWR Pad power supply ground
A6 D4 I/O 8-bit Bi-directional Data Bus.
Remark: For serial interfaces this pins can be used for test signals or I/Os.
Remark: If the host controller selects I2C as digital host controller interface, these
pins can be used to define the I2C address.
A7 D2 I/O
B1 PVDD PWR Pad power supply
B2 A0 I Address Line
B5 D5 I/O 8-bit Bi-directional Data Bus.
Remark: For serial interfaces this pins can be used for test signals or I/Os.
Remark: If the host controller selects I2C as digital host controller interface, these
pins can be used to define the I2C address.
B6 D3 I/O
B7 D1 I/O
C1 DVDD PWR Digital Power Supply
C2 A1 I Address Line
C3 D7 I/O 8-bit Bi-directional Data Bus.
Remark: For serial interfaces this pins can be used for test signals or I/Os.
Remark: If the host controller selects I2C as digital host controller interface, these
pins can be used to define the I2C address.
C4 D6 I/O
C5 IRQ O Interrupt Request: output to signal an interrupt event
C6 ALE I Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch
when HIGH.
C7, C8, D6, D8,
E6, E8, F7, G8,
H8
AVSS PWR Analog Ground
D1 DVSS PWR Digital Ground
D2 NRSTPD I Not Reset and Power Down: When LOW, internal current sinks are switched off,
the oscillator is inhibited, and the input pads are disconnected from the outside
world. With a positive edge on this pin the internal reset phase starts.
D3 to D5, E3 to
E5, F3, F4,
G1 to G6,
H1, H2, H6
TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2
D7 OSCOUT O Crystal Oscillator Output: Output of the inverting amplifier of the oscillator.
E2 SIGIN I Communication Interface Input: accepts a digital, serial data stream
E7 OSCIN I Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin
is also the input for an externally generated clock (fosc = 27.12 MHz).
F1 SVDD PWR S2C Pad Power Supply: provides power to the S2C pads
F2 SIGOUT O Communication Interface Output: delivers a serial data stream
F5 AUX1 O Auxiliary Outputs: These pins are used for testing.
F6 AUX2 O
F8 RX I Receiver Input
G7 VMID PWR Internal Reference Voltage: This pin delivers the internal reference voltage.
H3 TX1 O Transmitter 1: delivers the modulated 13.56 MHz energy carrierPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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H4 TVDD PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2
H5 TX2 O Transmitter 2: delivers the modulated 13.56 MHz energy carrier
H7 AVDD PWR Analog Power Supply
Table 5. Pin description TFBGA64
Pin Symbol Type DescriptionPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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8. Functional description
The PN512 transmission module supports the Read/Write mode for
ISO/IEC 14443 A/MIFARE and ISO/IEC 14443 B using various transfer speeds and
modulation protocols.
PN512 transceiver IC supports the following operating modes:
• Reader/Writer mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme
• Card Operation mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme
• NFCIP-1 mode
The modes support different transfer speeds and modulation schemes. The following
chapters will explain the different modes in detail.
Note: All indicated modulation indices and modes in this chapter are system parameters.
This means that beside the IC settings a suitable antenna tuning is required to achieve the
optimum performance.
8.1 ISO/IEC 14443 A/MIFARE functionality
The physical level communication is shown in Figure 7.
The physical parameters are described in Table 4.
Fig 6. PN512 Read/Write mode
001aan218
BATTERY
reader/writer
contactless card
MICROCONTROLLER
PN512 ISO/IEC 14443 A CARD
Fig 7. ISO/IEC 14443 A/MIFARE Read/Write mode communication diagram
Table 6. Communication overview for ISO/IEC 14443 A/MIFARE reader/writer
Communication
direction
Signal type Transfer speed
106 kBd 212 kBd 424 kBd
Reader to card (send
data from the PN512
to a card)
reader side
modulation
100 % ASK 100 % ASK 100 % ASK
bit encoding modified Miller
encoding
modified Miller
encoding
modified Miller
encoding
bit length 128 (13.56 s) 64 (13.56 s) 32 (13.56 s)
(1)
(2)
001aan219
PN512
ISO/IEC 14443 A CARD
ISO/IEC 14443 A
READERPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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The PN512’s contactless UART and dedicated external host must manage the complete
ISO/IEC 14443 A/MIFARE protocol. Figure 8 shows the data coding and framing
according to ISO/IEC 14443 A/MIFARE.
The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 A
part 3 and handles parity generation internally according to the transfer speed. Automatic
parity generation can be switched off using the ManualRCVReg register’s ParityDisable
bit.
8.2 ISO/IEC 14443 B functionality
The PN512 reader IC fully supports international standard ISO 14443 which includes
communication schemes ISO 14443 A and ISO 14443 B.
Refer to the ISO 14443 reference documents Identification cards - Contactless integrated
circuit cards - Proximity cards (parts 1 to 4).
Remark: NXP Semiconductors does not offer a software library to enable design-in of the
ISO 14443 B protocol.
Card to reader
(PN512 receives data
from a card)
card side
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier
frequency
13.56 MHz/16 13.56 MHz/16 13.56 MHz/16
bit encoding Manchester
encoding
BPSK BPSK
Table 6. Communication overview for ISO/IEC 14443 A/MIFARE reader/writer …continued
Communication
direction
Signal type Transfer speed
106 kBd 212 kBd 424 kBd
Fig 8. Data coding and framing according to ISO/IEC 14443 A
001aak585
ISO/IEC 14443 A framing at 106 kBd
8-bit data 8-bit data 8-bit data
odd
parity
odd
parity
start
odd
start bit is 1 parity
ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd
8-bit data 8-bit data 8-bit data
odd
parity
odd
parity
start
even
parity
start bit is 0
burst of 32
subcarrier clocks
even parity at the
end of the framePN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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8.3 FeliCa reader/writer functionality
The FeliCa mode is the general reader/writer to card communication scheme according to
the FeliCa specification. The following diagram describes the communication on a
physical level, the communication overview describes the physical parameters.
The contactless UART of PN512 and a dedicated external host controller are required to
handle the complete FeliCa protocol.
8.3.1 FeliCa framing and coding
To enable the FeliCa communication a 6 byte preamble (00h, 00h, 00h, 00h, 00h, 00h)
and 2 bytes Sync bytes (B2h, 4Dh) are sent to synchronize the receiver.
The following Len byte indicates the length of the sent data bytes plus the LEN byte itself.
The CRC calculation is done according to the FeliCa definitions with the MSB first.
To transmit data on the RF interface, the host controller has to send the Len- and databytes
to the PN512's FIFO-buffer. The preamble and the sync bytes are generated by the
PN512 automatically and must not be written to the FIFO by the host controller. The
PN512 performs internally the CRC calculation and adds the result to the data frame.
Example for FeliCa CRC Calculation:
Fig 9. FeliCa reader/writer communication diagram
Table 7. Communication overview for FeliCa reader/writer
Communication
direction
FeliCa FeliCa Higher
transfer speeds
Transfer speed 212 kbit/s 424 kbit/s
PN512 card Modulation on reader side 8-30 % ASK 8-30 % ASK
bit coding Manchester Coding Manchester Coding
Bitlength (64/13.56) s (32/13.56) s
card PN512 Loadmodulation on card side > 12 % ASK > 12 % ASK
bit coding Manchester coding Manchester coding
2. PICC to PCD, > 12 % ASK loadmodulation
Manchester coded, baudrate 212 to 424 kbaud
1. PCD to PICC, 8-30 % ASK
Manchester coded, baudrate 212 to 424 kbaud
001aan214
PN512
FeliCa CARD
(PICC)
Felica READER
(PCD)
Table 8. FeliCa framing and coding
Preamble Sync Len n-Data CRC
00h 00h 00h 00h 00h 00h B2h 4Dh
Table 9. Start value for the CRC Polynomial: (00h), (00h)
Preamble Sync Len 2 Data Bytes CRC
00h 00h 00h 00h 00h 00h B2h 4Dh 03h ABh CDh 90h 35hPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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8.4 NFCIP-1 mode
The NFCIP-1 communication differentiates between an active and a Passive
Communication mode.
• Active Communication mode means both the initiator and the target are using their
own RF field to transmit data.
• Passive Communication mode means that the target answers to an initiator command
in a load modulation scheme. The initiator is active in terms of generating the RF field.
• Initiator: generates RF field at 13.56 MHz and starts the NFCIP-1 communication
• Target: responds to initiator command either in a load modulation scheme in Passive
Communication mode or using a self generated and self modulated RF field for Active
Communication mode.
In order to fully support the NFCIP-1 standard the PN512 supports the Active and Passive
Communication mode at the transfer speeds 106 kbit/s, 212 kbit/s and 424 kbit/s as
defined in the NFCIP-1 standard.
Fig 10. NFCIP-1 mode
001aan215
BATTERY
initiator: active target:
passive or active
MICROCONTROLLER
PN512
BATTERY
MICROCONTROLLER
PN512PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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8.4.1 Active communication mode
Active communication mode means both the initiator and the target are using their own
RF field to transmit data.
The contactless UART of PN512 and a dedicated host controller are required to handle
the NFCIP-1 protocol.
Note: Transfer Speeds above 424 kbit/s are not defined in the NFCIP-1 standard. The
PN512 supports these transfer speeds only with dedicated external circuits.
Fig 11. Active communication mode
Table 10. Communication overview for Active communication mode
Communication
direction
106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s 1.69 Mbit/s,
3.39 Mbit/s
Initiator Target According to
ISO/IEC 14443A
100 % ASK,
Modified
Miller Coded
According to FeliCa, 8-30 %
ASK Manchester Coded
digital capability to handle
this communication Target Initiator
host NFC INITIATOR
powered to
generate RF field
1. initiator starts communication at
selected transfer speed
Initial command
response
2. target answers at
the same transfer speed
host NFC INITIATOR
powered for digital
processing
host
host
NFC TARGET
NFC TARGET
powered for
digital processing
powered to
generate RF field
001aan216PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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8.4.2 Passive communication mode
Passive Communication mode means that the target answers to an initiator command in a
load modulation scheme. The initiator is active meaning generating the RF field.
The contactless UART of PN512 and a dedicated host controller are required to handle
the NFCIP-1 protocol.
Note: Transfer Speeds above 424 kbit/s are not defined in the NFCIP-1 standard. The
PN512 supports these transfer speeds only with dedicated external circuits.
Fig 12. Passive communication mode
Table 11. Communication overview for Passive communication mode
Communication
direction
106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s 1.69 Mbit/s,
3.39 Mbit/s
Initiator Target According to
ISO/IEC 14443A
100 % ASK,
Modified
Miller Coded
According to FeliCa, 8-30
% ASK Manchester Coded
digital capability to handle
this communication
Target Initiator According to
ISO/IEC 14443A
subcarrier load
modulation,
Manchester Coded
According to FeliCa, > 12 %
ASK Manchester Coded
host NFC INITIATOR
powered to
generate RF field
1. initiator starts communication
at selected transfer speed
2. targets answers using
load modulated data
at the same transfer speed
host NFC TARGET
powered for
digital processing
001aan217PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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8.4.3 NFCIP-1 framing and coding
The NFCIP-1 framing and coding in Active and Passive Communication mode is defined
in the NFCIP-1 standard.
8.4.4 NFCIP-1 protocol support
The NFCIP-1 protocol is not completely described in this document. For detailed
explanation of the protocol refer to the NFCIP-1 standard. However the datalink layer is
according to the following policy:
• Speed shall not be changed while continuum data exchange in a transaction.
• Transaction includes initialization and anticollision methods and data exchange (in
continuous way, meaning no interruption by another transaction).
In order not to disturb current infrastructure based on 13.56 MHz general rules to start
NFCIP-1 communication are defined in the following way.
1. Per default NFCIP-1 device is in Target mode meaning its RF field is switched off.
2. The RF level detector is active.
3. Only if application requires the NFCIP-1 device shall switch to Initiator mode.
4. Initiator shall only switch on its RF field if no external RF field is detected by RF Level
detector during a time of TIDT.
5. The initiator performs initialization according to the selected mode.
8.4.5 MIFARE Card operation mode
Table 12. Framing and coding overview
Transfer speed Framing and Coding
106 kbit/s According to the ISO/IEC 14443A/MIFARE scheme
212 kbit/s According to the FeliCa scheme
424 kbit/s According to the FeliCa scheme
Table 13. MIFARE Card operation mode
Communication
direction
ISO/IEC 14443A/
MIFARE
MIFARE Higher transfer speeds
transfer speed 106 kbit/s 212 kbit/s 424 kbit/s
reader/writer
PN512
Modulation on
reader side
100 % ASK 100 % ASK 100 % ASK
bit coding Modified Miller Modified Miller Modified Miller
Bitlength (128/13.56) s (64/13.56) s (32/13.56) s
PN512 reader/
writer
Modulation on
PN512 side
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier
frequency
13.56 MHz/16 13.56 MHz/16 13.56 MHz/16
bit coding Manchester coding BPSK BPSKPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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8.4.6 FeliCa Card operation mode
9. PN512 register SET
9.1 PN512 registers overview
Table 14. FeliCa Card operation mode
Communication
direction
FeliCa FeliCa Higher
transfer speeds
Transfer speed 212 kbit/s 424 kbit/s
reader/writer
PN512
Modulation on reader side 8-30 % ASK 8-30 % ASK
bit coding Manchester Coding Manchester Coding
Bitlength (64/13.56) s (32/13.56) s
PN512 reader/
writer
Load modulation on PN512
side
> 12 % ASK load
modulation
> 12 % ASK load
modulation
bit coding Manchester coding Manchester coding
Table 15. PN512 registers overview
Addr
(hex)
Register Name Function
Page 0: Command and Status
0 PageReg Selects the register page
1 CommandReg Starts and stops command execution
2 ComlEnReg Controls bits to enable and disable the passing of Interrupt Requests
3 DivlEnReg Controls bits to enable and disable the passing of Interrupt Requests
4 ComIrqReg Contains Interrupt Request bits
5 DivIrqReg Contains Interrupt Request bits
6 ErrorReg Error bits showing the error status of the last command executed
7 Status1Reg Contains status bits for communication
8 Status2Reg Contains status bits of the receiver and transmitter
9 FIFODataReg In- and output of 64 byte FIFO-buffer
A FIFOLevelReg Indicates the number of bytes stored in the FIFO
B WaterLevelReg Defines the level for FIFO under- and overflow warning
C ControlReg Contains miscellaneous Control Registers
D BitFramingReg Adjustments for bit oriented frames
E CollReg Bit position of the first bit collision detected on the RF-interface
F RFU Reserved for future use
Page 1: Command
0 PageReg Selects the register page
1 ModeReg Defines general modes for transmitting and receiving
2 TxModeReg Defines the data rate and framing during transmission
3 RxModeReg Defines the data rate and framing during receiving
4 TxControlReg Controls the logical behavior of the antenna driver pins TX1 and TX2
5 TxAutoReg Controls the setting of the antenna driversPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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6 TxSelReg Selects the internal sources for the antenna driver
7 RxSelReg Selects internal receiver settings
8 RxThresholdReg Selects thresholds for the bit decoder
9 DemodReg Defines demodulator settings
A FelNFC1Reg Defines the length of the valid range for the receive package
B FelNFC2Reg Defines the length of the valid range for the receive package
C MifNFCReg Controls the communication in ISO/IEC 14443/MIFARE and NFC
target mode at 106 kbit
D ManualRCVReg Allows manual fine tuning of the internal receiver
E TypeBReg Configure the ISO/IEC 14443 type B
F SerialSpeedReg Selects the speed of the serial UART interface
Page 2: CFG
0 PageReg Selects the register page
1 CRCResultReg Shows the actual MSB and LSB values of the CRC calculation
2
3 GsNOffReg Selects the conductance of the antenna driver pins TX1 and TX2 for
modulation, when the driver is switched off
4 ModWidthReg Controls the setting of the ModWidth
5 TxBitPhaseReg Adjust the TX bit phase at 106 kbit
6 RFCfgReg Configures the receiver gain and RF level
7 GsNOnReg Selects the conductance of the antenna driver pins TX1 and TX2 for
modulation when the drivers are switched on
8 CWGsPReg Selects the conductance of the antenna driver pins TX1 and TX2 for
modulation during times of no modulation
9 ModGsPReg Selects the conductance of the antenna driver pins TX1 and TX2 for
modulation during modulation
A TModeReg
TPrescalerReg
Defines settings for the internal timer
B
C TReloadReg Describes the 16-bit timer reload value
D
E TCounterValReg Shows the 16-bit actual timer value
F
Page 3: TestRegister
0 PageReg selects the register page
1 TestSel1Reg General test signal configuration
2 TestSel2Reg General test signal configuration and PRBS control
3 TestPinEnReg Enables pin output driver on 8-bit parallel bus (Note: For serial
interfaces only)
4 TestPin
ValueReg
Defines the values for the 8-bit parallel bus when it is used as I/O bus
5 TestBusReg Shows the status of the internal testbus
6 AutoTestReg Controls the digital selftest
Table 15. PN512 registers overview …continued
Addr
(hex)
Register Name FunctionPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.1.1 Register bit behavior
Depending on the functionality of a register, the access conditions to the register can vary.
In principle bits with same behavior are grouped in common registers. In Table 16 the
access conditions are described.
7 VersionReg Shows the version
8 AnalogTestReg Controls the pins AUX1 and AUX2
9 TestDAC1Reg Defines the test value for the TestDAC1
A TestDAC2Reg Defines the test value for the TestDAC2
B TestADCReg Shows the actual value of ADC I and Q
C-F RFT Reserved for production tests
Table 15. PN512 registers overview …continued
Addr
(hex)
Register Name Function
Table 16. Behavior of register bits and its designation
Abbreviation Behavior Description
r/w read and write These bits can be written and read by the -Controller. Since they
are used only for control means, there content is not influenced by
internal state machines, e.g. the PageSelect-Register may be
written and read by the -Controller. It will also be read by internal
state machines, but never changed by them.
dy dynamic These bits can be written and read by the -Controller.
Nevertheless, they may also be written automatically by internal
state machines, e.g. the Command-Register changes its value
automatically after the execution of the actual command.
r read only These registers hold bits, which value is determined by internal
states only, e.g. the CRCReady bit can not be written from
external but shows internal states.
w write only Reading these registers returns always ZERO.
RFU - These registers are reserved for future use.
In case of a PN512 Version version 2.0 (VersionReg = 82h) a
read access to these registers returns always the value “0”.
Nevertheless this is not guaranteed for future chips versions
where the value is undefined. In case of a write access, it is
recommended to write always the value “0”.
RFT - These registers are reserved for production tests and shall not be
changed.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2 Register description
9.2.1 Page 0: Command and status
9.2.1.1 PageReg
Selects the register page.
9.2.1.2 CommandReg
Starts and stops command execution.
Table 17. PageReg register (address 00h); reset value: 00h, 0000000b
7 6 5 4 3 2 1 0
UsePage Select 0 0 0 0 0 PageSelect
Access
Rights
r/w RFU RFU RFU RFU RFU r/w r/w
Table 18. Description of PageReg bits
Bit Symbol Description
7 UsePageSelect Set to logic 1, the value of PageSelect is used as register address A5
and A4. The LSB-bits of the register address are defined by the
address pins or the internal address latch, respectively.
Set to logic 0, the whole content of the internal address latch defines
the register address. The address pins are used as described in
Section 10.1 “Automatic microcontroller interface detection”.
6 to 2 - Reserved for future use.
1 to 0 PageSelect The value of PageSelect is used only if UsePageSelect is set to
logic 1. In this case it specifies the register page (which is A5 and A4
of the register address).
Table 19. CommandReg register (address 01h); reset value: 20h, 00100000b
7 6 5 4 3 2 1 0
0 0 RcvOff Power Down Command
Access
Rights
RFU RFU r/w dy dy dy dy dy
Table 20. Description of CommandReg bits
Bit Symbol Description
7 to 6 - Reserved for future use.
5 RcvOff Set to logic 1, the analog part of the receiver is switched off.
4 PowerDown Set to logic 1, Soft Power-down mode is entered.
Set to logic 0, the PN512 starts the wake up procedure. During this
procedure this bit still shows a 1. A 0 indicates that the PN512 is ready
for operations; see Section 16.2 “Soft power-down mode”.
Note: The bit Power Down cannot be set, when the command
SoftReset has been activated.
3 to 0 Command Activates a command according to the Command Code. Reading this
register shows, which command is actually executed (see Section 19.3
“PN512 command overview”).PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.1.3 CommIEnReg
Control bits to enable and disable the passing of interrupt requests.
Table 21. CommIEnReg register (address 02h); reset value: 80h, 10000000b
7 6 5 4 3 2 1 0
IRqInv TxIEn RxIEn IdleIEn HiAlertIEn LoAlertIEn ErrIEn TimerIEn
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 22. Description of CommIEnReg bits
Bit Symbol Description
7 IRqInv Set to logic 1, the signal on pin IRQ is inverted with respect to bit IRq in the
register Status1Reg. Set to logic 0, the signal on pin IRQ is equal to bit IRq.
In combination with bit IRqPushPull in register DivIEnReg, the default value
of 1 ensures, that the output level on pin IRQ is 3-state.
6 TxIEn Allows the transmitter interrupt request (indicated by bit TxIRq) to be
propagated to pin IRQ.
5 RxIEn Allows the receiver interrupt request (indicated by bit RxIRq) to be
propagated to pin IRQ.
4 IdleIEn Allows the idle interrupt request (indicated by bit IdleIRq) to be propagated to
pin IRQ.
3 HiAlertIEn Allows the high alert interrupt request (indicated by bit HiAlertIRq) to be
propagated to pin IRQ.
2 LoAlertIEn Allows the low alert interrupt request (indicated by bit LoAlertIRq) to be
propagated to pin IRQ.
1 ErrIEn Allows the error interrupt request (indicated by bit ErrIRq) to be propagated
to pin IRQ.
0 TimerIEn Allows the timer interrupt request (indicated by bit TimerIRq) to be
propagated to pin IRQ. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.1.4 DivIEnReg
Control bits to enable and disable the passing of interrupt requests.
Table 23. DivIEnReg register (address 03h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
IRQPushPull 0 0 SiginActIEn ModeIEn CRCIEn RFOnIEn RFOffIEn
Access
Rights
r/w RFU RFU r/w r/w r/w r/w r/w
Table 24. Description of DivIEnReg bits
Bit Symbol Description
7 IRQPushPull Set to logic 1, the pin IRQ works as standard CMOS output pad.
Set to logic 0, the pin IRQ works as open drain output pad.
6 to 5 - Reserved for future use.
4 SiginActIEn Allows the SIGIN active interrupt request to be propagated to pin IRQ.
3 ModeIEn Allows the mode interrupt request (indicated by bit ModeIRq) to be
propagated to pin IRQ.
2 CRCIEn Allows the CRC interrupt request (indicated by bit CRCIRq) to be
propagated to pin IRQ.
1 RfOnIEn Allows the RF field on interrupt request (indicated by bit RfOnIRq) to
be propagated to pin IRQ.
0 RfOffIEn Allows the RF field off interrupt request (indicated by bit RfOffIRq) to
be propagated to pin IRQ.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.1.5 CommIRqReg
Contains Interrupt Request bits.
Table 25. CommIRqReg register (address 04h); reset value: 14h, 00010100b
7 6 5 4 3 2 1 0
Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq
Access
Rights
w dy dy dy dy dy dy dy
Table 26. Description of CommIRqReg bits
All bits in the register CommIRqReg shall be cleared by software.
Bit Symbol Description
7 Set1 Set to logic 1, Set1 defines that the marked bits in the register CommIRqReg
are set.
Set to logic 0, Set1 defines, that the marked bits in the register CommIRqReg
are cleared.
6 TxIRq Set to logic 1 immediately after the last bit of the transmitted data was sent out.
5 RxIRq Set to logic 1 when the receiver detects the end of a valid datastream.
If the bit RxNoErr in register RxModeReg is set to logic 1, bit RxIRq is only set
to logic 1 when data bytes are available in the FIFO.
4 IdleIRq Set to logic 1, when a command terminates by itself e.g. when the
CommandReg changes its value from any command to the Idle Command.
If an unknown command is started, the CommandReg changes its content to
the idle state and the bit IdleIRq is set. Starting the Idle Command by the
-Controller does not set bit IdleIRq.
3 HiAlertIRq Set to logic 1, when bit HiAlert in register Status1Reg is set. In opposition to
HiAlert, HiAlertIRq stores this event and can only be reset as indicated by bit
Set1.
2 LoAlertIRq Set to logic 1, when bit LoAlert in register Status1Reg is set. In opposition to
LoAlert, LoAlertIRq stores this event and can only be reset as indicated by bit
Set1.
1 ErrIRq Set to logic 1 if any error bit in the Error Register is set.
0 TimerIRq Set to logic 1 when the timer decrements the TimerValue Register to zero.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.1.6 DivIRqReg
Contains Interrupt Request bits
Table 27. DivIRqReg register (address 05h); reset value: XXh, 000X00XXb
7 6 5 4 3 2 1 0
Set2 0 0 SiginActIRq ModeIRq CRCIRq RFOnIRq RFOffIRq
Access
Rights
w RFU RFU dy dy dy dy dy
Table 28. Description of DivIRqReg bits
All bits in the register DivIRqReg shall be cleared by software.
Bit Symbol Description
7 Set2 Set to logic 1, Set2 defines that the marked bits in the register
DivIRqReg are set.
Set to logic 0, Set2 defines, that the marked bits in the register
DivIRqReg are cleared
6 to 5 - Reserved for future use.
4 SiginActIRq Set to logic 1, when SIGIN is active. See Section 12.6 “S2C interface
support”. This interrupt is set when either a rising or falling signal edge
is detected.
3 ModeIRq Set to logic 1, when the mode has been detected by the Data mode
detector.
Note: The Data mode detector can only be activated by the AutoColl
command and is terminated automatically having detected the
Communication mode.
Note: The Data mode detector is automatically restarted after each RF
Reset.
2 CRCIRq Set to logic 1, when the CRC command is active and all data are
processed.
1 RFOnIRq Set to logic 1, when an external RF field is detected.
0 RFOffIRq Set to logic 1, when a present external RF field is switched off.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.1.7 ErrorReg
Error bit register showing the error status of the last command executed.
[1] Command execution will clear all error bits except for bit TempErr. A setting by software is impossible.
Table 29. ErrorReg register (address 06h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
WrErr TempErr RFErr BufferOvfl CollErr CRCErr ParityErr ProtocolErr
Access
Rights
r rr r r r r r
Table 30. Description of ErrorReg bits
Bit Symbol Description
7 WrErr Set to logic 1, when data is written into FIFO by the host controller
during the AutoColl command or MFAuthent command or if data is
written into FIFO by the host controller during the time between
sending the last bit on the RF interface and receiving the last bit on the
RF interface.
6 TempErr[1] Set to logic 1, if the internal temperature sensor detects overheating.
In this case, the antenna drivers are switched off automatically.
5 RFErr Set to logic 1, if in Active Communication mode the counterpart does
not switch on the RF field in time as defined in NFCIP-1 standard.
Note: RFErr is only used in Active Communication mode. The bits
RxFraming or the bits TxFraming has to be set to 01 to enable this
functionality.
4 BufferOvfl Set to logic 1, if the host controller or a PN512’s internal state machine
(e.g. receiver) tries to write data into the FIFO-bufferFIFO-buffer
although the FIFO-buffer is already full.
3 CollErr Set to logic 1, if a bit-collision is detected. It is cleared automatically at
receiver start-up phase. This bit is only valid during the bitwise
anticollision at 106 kbit. During communication schemes at 212 and
424 kbit this bit is always set to logic 1.
2 CRCErr Set to logic 1, if bit RxCRCEn in register RxModeReg is set and the
CRC calculation fails. It is cleared to 0 automatically at receiver
start-up phase.
1 ParityErr Set to logic 1, if the parity check has failed. It is cleared automatically
at receiver start-up phase. Only valid for ISO/IEC 14443A/MIFARE or
NFCIP-1 communication at 106 kbit.
0 ProtocolErr Set to logic 1, if one out of the following cases occur:
• Set to logic 1 if the SOF is incorrect. It is cleared automatically at
receiver start-up phase. The bit is only valid for 106 kbit in Active
and Passive Communication mode.
• If bit DetectSync in register ModeReg is set to logic 1 during
FeliCa communication or active communication with transfer
speeds higher than 106 kbit, the bit ProtocolErr is set to logic 1 in
case of a byte length violation.
• During the AutoColl command, bit ProtocolErr is set to logic 1, if
the bit Initiator in register ControlReg is set to logic 1.
• During the MFAuthent Command, bit ProtocolErr is set to logic 1,
if the number of bytes received in one data stream is incorrect.
• Set to logic 1, if the Miller Decoder detects 2 pulses below the
minimum time according to the ISO/IEC 14443A definitions.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.1.8 Status1Reg
Contains status bits of the CRC, Interrupt and FIFO-buffer.
Table 31. Status1Reg register (address 07h); reset value: XXh, X100X01Xb
7 6 5 4 3 2 1 0
RFFreqOK CRCOk CRCReady IRq TRunning RFOn HiAlert LoAlert
Access
Rights
r r r r r rr r
Table 32. Description of Status1Reg bits
Bit Symbol Description
7 RFFreqOK Indicates if the frequency detected at the RX pin is in the range of
13.56 MHz.
Set to logic 1, if the frequency at the RX pin is in the range
12 MHz < RX pin frequency < 15 MHz.
Note: The value of RFFreqOK is not defined if the external RF
frequency is in the range from 9 to 12 MHz or in the range from
15 to 19 MHz.
6 CRCOk Set to logic 1, if the CRC Result is zero. For data transmission and
reception the bit CRCOk is undefined (use CRCErr in register
ErrorReg). CRCOk indicates the status of the CRC co-processor,
during calculation the value changes to ZERO, when the calculation is
done correctly, the value changes to ONE.
5 CRCReady Set to logic 1, when the CRC calculation has finished. This bit is only
valid for the CRC co-processor calculation using the command
CalcCRC.
4 IRq This bit shows, if any interrupt source requests attention (with respect
to the setting of the interrupt enable bits, see register CommIEnReg
and DivIEnReg).
3 TRunning Set to logic 1, if the PN512’s timer unit is running, e.g. the timer will
decrement the TCounterValReg with the next timer clock.
Note: In the gated mode the bit TRunning is set to logic 1, when the
timer is enabled by the register bits. This bit is not influenced by the
gated signal.
2 RFOn Set to logic 1, if an external RF field is detected. This bit does not store
the state of the RF field.
1 HiAlert Set to logic 1, when the number of bytes stored in the FIFO-buffer
fulfills the following equation:
Example:
FIFOLength = 60, WaterLevel = 4 HiAlert = 1
FIFOLength = 59, WaterLevel = 4 HiAlert = 0
0 LoAlert Set to logic 1, when the number of bytes stored in the FIFO-buffer
fulfills the following equation:
Example:
FIFOLength = 4, WaterLevel = 4 LoAlert = 1
FIFOLength = 5, WaterLevel = 4 LoAlert = 0
HiAlert 64 FIFOLength = – WaterLevel
LoAlert FIFOLength WaterLevel = PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.1.9 Status2Reg
Contains status bits of the Receiver, Transmitter and Data mode detector.
Table 33. Status2Reg register (address 08h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
TempSensClear I2CForceHS 0 TargetActivated MFCrypto1On Modem State
Access
Rights
r/w r/w RFU dy dy r r r
Table 34. Description of Status2Reg bits
Bit Symbol Description
7 TempSensClear Set to logic 1, this bit clears the temperature error, if the temperature
is below the alarm limit of 125 C.
6 I2CForceHS I2C input filter settings. Set to logic 1, the I2C input filter is set to the
High-speed mode independent of the I2C protocol. Set to logic 0, the
I
2C input filter is set to the used I2C protocol.
5 - Reserved for future use.
4 TargetActivated Set to logic 1 if the Select command or if the Polling command was
answered. Note: This bit can only be set during the AutoColl
command in Passive Communication mode.
Note: This bit is cleared automatically by switching off the external
RF field.
3 MFCrypto1On This bit indicates that the MIFARE Crypto1 unit is switched on and
therefore all data communication with the card is encrypted.
This bit can only be set to logic 1 by a successful execution of the
MFAuthent Command. This bit is only valid in Reader/Writer mode
for MIFARE cards. This bit shall be cleared by software.
2 to 0 Modem State ModemState shows the state of the transmitter and receiver state
machines.
Value Description
000 IDLE
001 Wait for StartSend in register BitFramingReg
010 TxWait: Wait until RF field is present, if the bit TxWaitRF is
set to logic 1. The minimum time for TxWait is defined by the
TxWaitReg register.
011 Sending
100 RxWait: Wait until RF field is present, if the bit RxWaitRF is
set to logic 1. The minimum time for RxWait is defined by the
RxWaitReg register.
101 Wait for data
110 ReceivingPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.1.10 FIFODataReg
In- and output of 64 byte FIFO-buffer.
9.2.1.11 FIFOLevelReg
Indicates the number of bytes stored in the FIFO.
Table 35. FIFODataReg register (address 09h); reset value: XXh, XXXXXXXXb
7 6 5 4 3 2 1 0
FIFOData
Access
Rights
dy dy dy dy dy dy dy dy
Table 36. Description of FIFODataReg bits
Bit Symbol Description
7 to 0 FIFOData Data input and output port for the internal 64 byte FIFO-buffer. The
FIFO-buffer acts as parallel in/parallel out converter for all serial data
stream in- and outputs.
Table 37. FIFOLevelReg register (address 0Ah); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
FlushBuffer FIFOLevel
Access
Rights
w rrrrrrr
Table 38. Description of FIFOLevelReg bits
Bit Symbol Description
7 FlushBuffer Set to logic 1, this bit clears the internal FIFO-buffer’s read- and
write-pointer and the bit BufferOvfl in the register ErrReg immediately.
Reading this bit will always return 0.
6 to 0 FIFOLevel Indicates the number of bytes stored in the FIFO-buffer. Writing to the
FIFODataReg increments, reading decrements the FIFOLevel.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.1.12 WaterLevelReg
Defines the level for FIFO under- and overflow warning.
9.2.1.13 ControlReg
Miscellaneous control bits.
Table 39. WaterLevelReg register (address 0Bh); reset value: 08h, 00001000b
7 6 5 4 3 2 1 0
0 0 WaterLevel
Access
Rights
RFU RFU r/w r/w r/w r/w r/w r/w
Table 40. Description of WaterLevelReg bits
Bit Symbol Description
7 to 6 - Reserved for future use.
5 to 0 WaterLevel This register defines a warning level to indicate a FIFO-buffer over- or
underflow:
The bit HiAlert in Status1Reg is set to logic 1, if the remaining number
of bytes in the FIFO-buffer space is equal or less than the defined
number of WaterLevel bytes.
The bit LoAlert in Status1Reg is set to logic 1, if equal or less than
WaterLevel bytes are in the FIFO.
Note: For the calculation of HiAlert and LoAlert see Table 31
Table 41. ControlReg register (address 0Ch); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
TStopNow TStartNow WrNFCIDtoFIFO Initiator 0 RxLastBits
Access
Rights
w w dy r/w RFU r r r
Table 42. Description of ControlReg bits
Bit Symbol Description
7 TStopNow Set to logic 1, the timer stops immediately.
Reading this bit will always return 0.
6 TStartNow Set to logic 1 starts the timer immediately.
Reading this bit will always return 0.
5 WrNFCIDtoFIFO Set to logic 1, the internal stored NFCID (10 bytes) is copied into the
FIFO.
Afterwards the bit is cleared automatically
4 Initiator Set to logic 1, the PN512 acts as initiator, otherwise it acts as target
3 - Reserved for future use.
2 to 0 RxLastBits Shows the number of valid bits in the last received byte. If zero, the
whole byte is valid.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.1.14 BitFramingReg
Adjustments for bit oriented frames.
Table 43. BitFramingReg register (address 0Dh); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
StartSend RxAlign 0 TxLastBits
Access
Rights
w r/w r/w r/w RFU r/w r/w r/w
Table 44. Description of BitFramingReg bits
Bit Symbol Description
7 StartSend Set to logic 1, the transmission of data starts.
This bit is only valid in combination with the Transceive command.
6 to 4 RxAlign Used for reception of bit oriented frames: RxAlign defines the bit position
for the first bit received to be stored in the FIFO. Further received bits are
stored at the following bit positions.
Example:
RxAlign = 0: the LSB of the received bit is stored at bit 0, the second
received bit is stored at bit position 1.
RxAlign = 1: the LSB of the received bit is stored at bit 1, the second
received bit is stored at bit position 2.
RxAlign = 7: the LSB of the received bit is stored at bit 7, the second
received bit is stored in the following byte at bit position 0.
This bit shall only be used for bitwise anticollision at 106 kbit/s in Passive
Communication mode. In all other modes it shall be set to logic 0.
3 - Reserved for future use.
2 to 0 TxLastBits Used for transmission of bit oriented frames: TxLastBits defines the
number of bits of the last byte that shall be transmitted. A 000 indicates
that all bits of the last byte shall be transmitted.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.1.15 CollReg
Defines the first bit collision detected on the RF interface.
Table 45. CollReg register (address 0Eh); reset value: XXh, 101XXXXXb
7 6 5 4 3 2 1 0
Values
AfterColl
0 CollPos
NotValid
CollPos
Access
Rights
r/w RFU r r r r r r
Table 46. Description of CollReg bits
Bit Symbol Description
7 ValuesAfterColl If this bit is set to logic 0, all receiving bits will be cleared after a
collision. This bit shall only be used during bitwise anticollision at
106 kbit, otherwise it shall be set to logic 1.
6 - Reserved for future use.
5 CollPosNotValid Set to logic 1, if no Collision is detected or the Position of the
Collision is out of the range of bits CollPos. This bit shall only be
interpreted in Passive Communication mode at 106 kbit or
ISO/IEC 14443A/MIFARE Reader/Writer mode.
4 to 0 CollPos These bits show the bit position of the first detected collision in a
received frame, only data bits are interpreted.
Example:
00h indicates a bit collision in the 32th bit
01h indicates a bit collision in the 1st bit
08h indicates a bit collision in the 8th bit
These bits shall only be interpreted in Passive Communication mode
at 106 kbit or ISO/IEC 14443A/MIFARE Reader/Writer mode if bit
CollPosNotValid is set to logic 0.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2 Page 1: Communication
9.2.2.1 PageReg
Selects the register page.
Table 47. PageReg register (address 10h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
UsePage Select 0 0 0 0 0 PageSelect
Access
Rights
r/w RFU RFU RFU RFU RFU r/w r/w
Table 48. Description of PageReg bits
Bit Symbol Description
7 UsePage Select Set to logic 1, the value of PageSelect is used as register address A5
and A4. The LSB-bits of the register address are defined by the
address pins or the internal address latch, respectively.
Set to logic 0, the whole content of the internal address latch defines
the register address. The address pins are used as described in
Section 10.1 “Automatic microcontroller interface detection”.
6 to 2 - Reserved for future use.
1 to 0 PageSelect The value of PageSelect is used only, if UsePageSelect is set to
logic 1. In this case it specifies the register page (which is A5 and A4
of the register address).PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2.2 ModeReg
Defines general mode settings for transmitting and receiving.
Table 49. ModeReg register (address 11h); reset value: 3Bh, 00111011b
7 6 5 4 3 2 1 0
MSBFirst Detect Sync TxWaitRF RxWaitRF PolSigin ModeDetOff CRCPreset
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 50. Description of ModeReg bits
Bit Symbol Description
7 MSBFirst Set to logic 1, the CRC co-processor calculates the CRC with MSB
first and the CRCResultMSB and the CRCResultLSB in the
CRCResultReg register are bit reversed.
Note: During RF communication this bit is ignored.
6 Detect Sync If set to logic 1, the contactless UART waits for the value F0h before
the receiver is activated and F0h is added as a Sync-byte for
transmission.
This bit is only valid for 106 kbit during NFCIP-1 data exchange
protocol.
In all other modes it shall be set to logic 0.
5 TxWaitRF Set to logic 1 the transmitter in reader/writer or initiator mode for
NFCIP-1 can only be started, if an RF field is generated.
4 RxWaitRF Set to logic 1, the counter for RxWait starts only if an external RF field
is detected in Target mode for NFCIP-1 or in Card Communication
mode.
3 PolSigin PolSigin defines the polarity of the SIGIN pin. Set to logic 1, the
polarity of SIGIN pin is active high. Set to logic 0 the polarity of SIGIN
pin is active low.
Note: The internal envelope signal is coded active low.
Note: Changing this bit will generate a SiginActIRq event.
2 ModeDetOff Set to logic 1, the internal mode detector is switched off.
Note: The mode detector is only active during the AutoColl command.
1 to 0 CRCPreset Defines the preset value for the CRC co-processor for the command
CalCRC.
Note: During any communication, the preset values is selected
automatically according to the definition in the bits RxMode and
TxMode.
Value Description
00 0000
01 6363
10 A671
11 FFFFPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2.3 TxModeReg
Defines the data rate and framing during transmission.
Table 51. TxModeReg register (address 12h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
TxCRCEn TxSpeed InvMod TxMix TxFraming
Access
Rights
r/w dy dy dy r/w r/w dy dy
Table 52. Description of TxModeReg bits
Bit Symbol Description
7 TxCRCEn Set to logic 1, this bit enables the CRC generation during data
transmission.
Note: This bit shall only be set to logic 0 at 106 kbit.
6 to 4 TxSpeed Defines the bit rate while data transmission.
Value Description
000 106 kbit
001 212 kbit
010 424 kbit
011 848 kbit
100 1696 kbit
101 3392 kbit
110 Reserved
111 Reserved
Note: The bit coding for transfer speeds above 424 kbit is equivalent to
the bit coding of Active Communication mode 424 kbit (Ecma 340).
3 InvMod Set to logic 1, the modulation for transmitting data is inverted.
2 TxMix Set to logic 1, the signal at pin SIGIN is mixed with the internal coder
(see Section 12.6 “S2C interface support”).
1 to 0 TxFraming Defines the framing used for data transmission.
Value Description
00 ISO/IEC 14443A/MIFARE and Passive Communication mode
106 kbit
01 Active Communication mode
10 FeliCa and Passive communication mode 212 and 424 kbit
11 ISO/IEC 14443BPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2.4 RxModeReg
Defines the data rate and framing during reception.
Table 53. RxModeReg register (address 13h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
RxCRCEn RxSpeed RxNoErr RxMultiple RxFraming
Access
Rights
r/w dy dy dy r/w r/w dy dy
Table 54. Description of RxModeReg bits
Bit Symbol Description
7 RxCRCEn Set to logic 1, this bit enables the CRC calculation during reception.
Note: This bit shall only be set to logic 0 at 106 kbit.
6 to 4 RxSpeed Defines the bit rate while data transmission.
The PN512’s analog part handles only transfer speeds up to 424 kbit
internally, the digital UART handles the higher transfer speeds as well.
Value Description
000 106 kbit
001 212 kbit
010 424 kbit
011 848 kbit
100 1696 kbit
101 3392 kbit
110 Reserved
111 Reserved
Note: The bit coding for transfer speeds above 424 kbit is equivalent to
the bit coding of Active Communication mode 424 kbit (Ecma 340).
3 RxNoErr If set to logic 1 a not valid received data stream (less than 4 bits
received) will be ignored. The receiver will remain active.
For ISO/IEC14443B also RxSOFReq logic 1 is required to ignore a non
valid datastream.
2 RxMultiple Set to logic 0, the receiver is deactivated after receiving a data frame.
Set to logic 1, it is possible to receive more than one data frame. Having
set this bit, the receive and transceive commands will not terminate
automatically. In this case the multiple receiving can only be deactivated
by writing any command (except the Receive command) to the
CommandReg register or by clearing the bit by the host controller.
At the end of a received data stream an error byte is added to the FIFO.
The error byte is a copy of the ErrorReg register.
The behaviour for version 1.0 is described in Section 21 “Errata sheet”
on page 109.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2.5 TxControlReg
Controls the logical behavior of the antenna driver pins Tx1 and Tx2.
1 to 0 RxFraming Defines the expected framing for data reception.
Value Description
00 ISO/IEC 14443A/MIFARE and Passive Communication
mode 106 kbit
01 Active Communication mode
10 FeliCa and Passive Communication mode 212 and 424 kbit
11 ISO/IEC 14443B
Table 54. Description of RxModeReg bits
Bit Symbol Description
Table 55. TxControlReg register (address 14h); reset value: 80h, 10000000b
7 6 5 4 3 2 1 0
InvTx2RF
On
InvTx1RF
On
InvTx2RF
Off
InvTx1RF
Off
Tx2CW CheckRF Tx2RF
En
Tx1RF
En
Access
Rights
r/w r/w r/w r/w r/w w r/w r/w
Table 56. Description of TxControlReg bits
Bit Symbol Description
7 InvTx2RFOn Set to logic 1, the output signal at pin TX2 will be inverted, if driver TX2
is enabled.
6 InvTx1RFOn Set to logic 1, the output signal at pin TX1 will be inverted, if driver TX1
is enabled.
5 InvTx2RFOff Set to logic 1, the output signal at pin TX2 will be inverted, if driver TX2
is disabled.
4 InvTx1RFOff Set to logic 1, the output signal at pin TX1 will be inverted, if driver TX1
is disabled.
3 Tx2CW Set to logic 1, the output signal on pin TX2 will deliver continuously the
un-modulated 13.56 MHz energy carrier.
Set to logic 0, Tx2CW is enabled to modulate the 13.56 MHz energy
carrier.
2 CheckRF Set to logic 1, Tx2RFEn and Tx1RFEn can not be set if an external RF
field is detected. Only valid when using in combination with bit
Tx2RFEn or Tx1RFEn
1 Tx2RFEn Set to logic 1, the output signal on pin TX2 will deliver the 13.56 MHz
energy carrier modulated by the transmission data.
0 Tx1RFEn Set to logic 1, the output signal on pin TX1 will deliver the 13.56 MHz
energy carrier modulated by the transmission data.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2.6 TxAutoReg
Controls the settings of the antenna driver.
Table 57. TxAutoReg register (address 15h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
AutoRF
OFF
Force100
ASK
Auto
WakeUp
0 CAOn InitialRF
On
Tx2RFAut
oEn
Tx1RFAuto
En
Access
Rights
r/w r/w r/w RFU r/w r/w r/w r/w
Table 58. Description of TxAutoReg bits
Bit Symbol Description
7 AutoRFOFF Set to logic 1, all active antenna drivers are switched off after the last
data bit has been transmitted as defined in the NFCIP-1.
6 Force100ASK Set to logic 1, Force100ASK forces a 100% ASK modulation
independent of the setting in register ModGsPReg.
5 AutoWakeUp Set to logic 1, the PN512 in soft Power-down mode will be started by
the RF level detector.
4 - Reserved for future use.
3 CAOn Set to logic 1, the collision avoidance is activated and internally the
value n is set in accordance to the NFCIP-1 Standard.
2 InitialRFOn Set to logic 1, the initial RF collision avoidance is performed and the bit
InitialRFOn is cleared automatically, if the RF is switched on.
Note: The driver, which should be switched on, has to be enabled by
bit Tx2RFAutoEn or bit Tx1RFAutoEn.
1 Tx2RFAutoEn Set to logic 1, the driver Tx2 is switched on after the external RF field
is switched off according to the time TADT. If the bits InitialRFOn and
Tx2RFAutoEn are set to logic 1, Tx2 is switched on if no external RF
field is detected during the time TIDT.
Note: The times TADT and TIDT are defined in the NFC IP-1 standard
(ISO/IEC 18092).
0 Tx1RFAutoEn Set to logic 1, the driver Tx1 is switched on after the external RF field
is switched off according to the time TADT. If the bit InitialRFOn and
Tx1RFAutoEn are set to logic 1, Tx1 is switched on if no external RF
field is detected during the time TIDT.
Note: The times TADT and TIDT are defined in the NFC IP-1 standard
(ISO/IEC 18092).PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2.7 TxSelReg
Selects the sources for the analog part.
Table 59. TxSelReg register (address 16h); reset value: 10h, 00010000b
7 6 5 4 3 2 1 0
0 0 DriverSel SigOutSel
Access
Rights
RFU RFU r/w r/w r/w r/w r/w r/w
Table 60. Description of TxSelReg bits
Bit Symbol Description
7 to 6 - Reserved for future use.
5 to 4 DriverSel Selects the input of driver Tx1 and Tx2.
Value Description
00 Tristate
Note: In soft power down the drivers are only in Tristate mode
if DriverSel is set to Tristate mode.
01 Modulation signal (envelope) from the internal coder
10 Modulation signal (envelope) from SIGIN
11 HIGH
Note: The HIGH level depends on the setting of InvTx1RFOn/
InvTx1RFOff and InvTx2RFOn/InvTx2RFOff.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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3 to 0 SigOutSel Selects the input for the SIGOUT Pin.
Value Description
0000 Tristate
0001 Low
0010 High
0011 TestBus signal as defined by bit TestBusBitSel in register
TestSel1Reg.
0100 Modulation signal (envelope) from the internal coder
0101 Serial data stream to be transmitted
0110 Output signal of the receiver circuit (card modulation signal
regenerated and delayed). This signal is used as data output
signal for SAM interface connection using 3 lines.
Note: To have a valid signal the PN512 has to be set to the
receiving mode by either the Transceive or Receive
command. The bit RxMultiple can be used to keep the PN512
in receiving mode.
Note: Do not use this setting in MIFARE mode. Manchester
coding as data collisions will not be transmitted on the
SIGOUT line.
0111 Serial data stream received.
Note: Do not use this setting in MIFARE mode. Miller coding
parameters as the bit length can vary.
1000-1011 FeliCa Sam modulation
1000 RX*
1001 TX
1010 Demodulator comparator output
1011 RFU
Note: * To have a valid signal the PN512 has to be set to the
receiving mode by either the Transceive or Receive
command. The bit RxMultiple can be used to keep the PN512
in receiving mode.
1100-1111 MIFARE Sam modulation
1100 RX* with RF carrier
1101 TX with RF carrier
1110 RX with RF carrier un-filtered
1111 RX envelope un-filtered
Note: *To have a valid signal the PN512 has to be set to the
receiving mode by either the Transceive or Receive
command. The bit RxMultiple can be used to keep the PN512
in receiving mode.
Table 60. Description of TxSelReg bits …continued
Bit Symbol DescriptionPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2.8 RxSelReg
Selects internal receiver settings.
9.2.2.9 RxThresholdReg
Selects thresholds for the bit decoder.
Table 61. RxSelReg register (address 17h); reset value: 84h, 10000100b
7 6 5 4 3 2 1 0
UartSel RxWait
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 62. Description of RxSelReg bits
Bit Symbol Description
7 to 6 UartSel Selects the input of the contactless UART
Value Description
00 Constant Low
01 Envelope signal at SIGIN
10 Modulation signal from the internal analog part
11 Modulation signal from SIGIN pin. Only valid for transfer
speeds above 424 kbit
5 to 0 RxWait After data transmission, the activation of the receiver is delayed for
RxWait bit-clocks. During this ‘frame guard time’ any signal at pin RX
is ignored. This parameter is ignored by the Receive command. All
other commands (e.g. Transceive, Autocoll, MFAuthent) use this
parameter. Depending on the mode of the PN512, the counter starts
different. In Passive Communication mode the counter starts with the
last modulation pulse of the transmitted data stream. In Active
Communication mode the counter starts immediately after the external
RF field is switched on.
Table 63. RxThresholdReg register (address 18h); reset value: 84h, 10000100b
7 6 5 4 3 2 1 0
MinLevel 0 CollLevel
Access
Rights
r/w r/w r/w r/w RFU r/w r/w r/w
Table 64. Description of RxThresholdReg bits
Bit Symbol Description
7 to 4 MinLevel Defines the minimum signal strength at the decoder input that shall be
accepted. If the signal strength is below this level, it is not evaluated.
3 - Reserved for future use.
2 to 0 CollLevel Defines the minimum signal strength at the decoder input that has to be
reached by the weaker half-bit of the Manchester-coded signal to
generate a bit-collision relatively to the amplitude of the stronger half-bit.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2.10 DemodReg
Defines demodulator settings.
Table 65. DemodReg register (address 19h); reset value: 4Dh, 01001101b
7 6 5 4 3 2 1 0
AddIQ FixIQ TPrescal
Even
TauRcv TauSync
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 66. Description of DemodReg bits
Bit Symbol Description
7 to 6 AddIQ Defines the use of I and Q channel during reception
Note: FixIQ has to be set to logic 0 to
enable the following settings.
Value Description
00 Select the stronger channel
01 Select the stronger and freeze the selected during communication
10 combines the I and Q channel
11 Reserved
5 FixIQ If set to logic 1 and the bits of AddIQ are set to X0, the reception is fixed to
I channel.
If set to logic 1 and the bits of AddIQ are set to X1, the reception is fixed to
Q channel.
NOTE: If SIGIN/SIGOUT is used as S2C interface FixIQ set to 1 and AddIQ
set to X0 is rewired.
4 TPrescalE
ven
If set to logic 0 the following formula is used to calculate fTimer of the
prescaler:
fTimer = 13.56 MHz / (2 * TPreScaler + 1).
If set to logic 1 the following formula is used to calculate fTimer of the
prescaler:
fTimer = 13.56 MHz / (2 * TPreScaler + 2).
(Default TPrescalEven is logic 0)
The behaviour for the version 1.0 is described in Section 21 “Errata
sheet” on page 109.
3 to 2 TauRcv Changes the time constant of the internal during data reception.
Note: If set to 00, the PLL is frozen during data reception.
1 to 0 TauSync Changes the time constant of the internal PLL during burst.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2.11 FelNFC1Reg
Defines the length of the FeliCa Sync bytes and the minimum length of the received
packet.
Table 67. FelNFC1Reg register (address 1Ah); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
FelSyncLen DataLenMin
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 68. Description of FelNFC1Reg bits
Bit Symbol Description
7 to 6 FelSyncLen Defines the length of the Sync bytes.
Value Sync- bytes in hex
00 B2 4D
01 00 B2 4D
10 00 00 B2 4D
11 00 00 00 B2 4D
5 to 0 DataLenMin These bits define the minimum length of the accepted packet length:
DataLenMin * 4 data packet length
This parameter is ignored at 106 kbit if the bit DetectSync in register
ModeReg is set to logic 0. If a received data packet is shorter than the
defined DataLenMin value, the data packet will be ignored.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2.12 FelNFC2Reg
Defines the maximum length of the received packet.
Table 69. FelNFC2Reg register (address1Bh); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
WaitForSelected ShortTimeSlot DataLenMax
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 70. Description of FelNFC2Reg bits
Bit Symbol Description
7 WaitForSelected Set to logic 1, the AutoColl command is only terminated
automatically when:
1. A valid command has been received after performing a valid
Select procedure according ISO/IEC 14443A.
2. A valid command has been received after performing a valid
Polling procedure according to the FeliCa specification.
Note: If this bit is set, no active communication is possible.
Note: Setting this bit reduces the host controller interaction in case
of a communication to another device in the same RF field during
Passive Communication mode.
6 ShortTimeSlot Defines the time slot length for Passive Communication mode at
424 kbit. Set to logic 1 a short time slot is used (half of the timeslot
at 212 kbit). Set to logic 0 a long timeslot is used (equal to the
timeslot for 212 kbit).
5 to 0 DataLenMax These bits define the maximum length of the accepted packet
length: DataLenMax * 4 data packet length
Note: If set to logic 0 the maximum data length is 256 bytes.
This parameter is ignored at 106 kbit if the bit DetectSync in
register ModeReg is set to logic 0. If a received packet is larger
than the defined DataLenMax value, the packet will be ignored.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2.13 MifNFCReg
Defines ISO/IEC 14443A/MIFARE/NFC specific settings in target or Card Operating
mode.
Table 71. MifNFCReg register (address 1Ch); reset value: 62h, 01100010b
7 6 5 4 3 2 1 0
SensMiller TauMiller MFHalted TxWait
Access
Rights
r/w r/w r/w r/w r/w r/w r/w r/w
Table 72. Description of MifNFCReg bits
Bit Symbol Description
7 to 5 SensMiller These bits define the sensitivity of the Miller decoder.
4 to 3 TauMiller These bits define the time constant of the Miller decoder.
2 MFHalted Set to logic 1, this bit indicates that the PN512 is set to HALT mode in
Card Operation mode at 106 kbit. This bit is either set by the host
controller or by the internal state machine and indicates that only the
code 52h is accepted as a request command. This bit is cleared
automatically by a RF reset.
1 to 0 TxWait These bits define the minimum response time between receive and
transmit in number of data bits + 7 data bits.
The shortest possible minimum response time is 7 data bits.
(TxWait=0). The minimum response time can be increased by the
number of bits defined in TxWait. The longest minimum response time
is 10 data bits (TxWait = 3).
If a transmission of a frame is started before the minimum response
time is over, the PN512 waits before transmitting the data until the
minimum response time is over.
If a transmission of a frame is started after the minimum response time
is over, the frame is started immediately if the data bit synchronization
is correct. (adjustable with TxBitPhase).PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2.14 ManualRCVReg
Allows manual fine tuning of the internal receiver.
Remark: For standard applications it is not recommended to change this register settings.
Table 73. ManualRCVReg register (address 1Dh); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
0 FastFilt
MF_SO
Delay
MF_SO
Parity
Disable
LargeBW
PLL
Manual
HPCF
HPFC
Access
Rights
RFU r/w r/w r/w r/w r/w r/w r/w
Table 74. Description of ManualRCVReg bits
Bit Symbol Description
7 - Reserved for future use.
6 FastFilt
MF_SO
If this bit is set to logic 1, the internal filter for the Miller-Delay Circuit is
set to Fast mode.
Note: This bit should only set to logic 1, if Millerpulses of less than
400 ns Pulse length are expected. At 106 kBaud the typical value is
3 us.
5 Delay MF_SO If this bit is set to logic 1, the Signal at SIGOUT-pin is delayed, so that
in SAM mode the Signal at SIGIN must be 128/fc faster compared to
the ISO/IEC 14443A, to reach the ISO/IEC 14443A restrictions on the
RF-Field.
Note: This delay shall only be activated for setting bits SigOutSel to
(1110b) or (1111b) in register TxSelReg.
4 Parity Disable If this bit is set to logic 1, the generation of the Parity bit for
transmission and the Parity-Check for receiving is switched off. The
received Parity bit is handled like a data bit.
3 LargeBWPLL Set to logic 1, the bandwidth of the internal PLL used for clock
recovery is extended.
2 ManualHPCF Set to logic 0, the HPCF bits are ignored and the HPCF settings are
adapted automatically to the receiving mode. Set to logic 1, values of
HPCF are valid.
1 to 0 HPFC Selects the High Pass Corner Frequency (HPCF) of the filter in the
internal receiver chain
00 For signals with frequency spectrum down to 106 kHz.
01 For signals with frequency spectrum down to 212 kHz.
10 For signals with frequency spectrum down to 424 kHz.
11 For signals with frequency spectrum down to 848 kHzPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.2.15 TypeBReg
9.2.2.16 SerialSpeedReg
Selects the speed of the serial UART interface.
Table 75. TypeBReg register (address 1Eh); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
RxSOF
Req
RxEOF
Req
0 EOFSO
FWidth
NoTxSOF NoTxEOF TxEGT
Access
Rights
r/w r/w RFU r/w r/w r/w r/w r/w
Table 76. Description of TypeBReg bits
Bit Symbol Description
7 RxSOFReq If this bit is set to logic 1, the SOF is required. A datastream starting
without SOF is ignored.
If this bit is cleared, a datastream with and without SOF is accepted.
The SOF will be removed and not written into the FIFO.
6 RxEOFReq If this bit is set to logic 1, the EOF is required. A datastream ending
without EOF will generate a Protocol-Error. If this bit is cleared, a
datastream with and without EOF is accepted. The EOF will be
removed and not written into the FIFO.
For the behaviour in version 1.0, see Section 21 “Errata sheet” on
page 109.
5 - Reserved for future use.
4 EOFSOFWidth If this bit is set to logic 1 and EOFSOFAdjust bit is logic 0, the SOF
and EOF will have the maximum length defined in ISO/IEC 14443B.
If this bit is cleared and EOFSOFAdjust bit is logic 0, the SOF and
EOF will have the minimum length defined in ISO/IEC 14443B.
If this bit is set to 1 and the EOFSOFadjust bit is logic 1 will result in
SOF low = (11etu 8 cycles)/fc
SOF high = (2 etu + 8 cycles)/fc
EOF low = (11 etu 8 cycles)/fc
If this bit is set to 0 and the EOFSOFAdjust bit is logic 1 will result in
an incorrect system behavior in respect to ISO specification.
For the behaviour in version 1.0, see Section 21 “Errata sheet” on
page 109.
3 NoTxSOF If this bit is set to logic 1, the generation of the SOF is suppressed.
2 NoTxEOF If this bit is set to logic 1, the generation of the EOF is suppressed.
1 to 0 TxEGT These bits define the length of the EGT.
Value Description
00 0 bit
01 1 bit
10 2 bits
11 3 bitsPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Table 77. SerialSpeedReg register (address 1Fh); reset value: EBh, 11101011b
7 6 5 4 3 2 1 0
BR_T0 BR_T1
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Table 78. Description of SerialSpeedReg bits
Bit Symbol Description
7 to 5 BR_T0 Factor BR_T0 to adjust the transfer speed, for description see Section
10.3.2 “Selectable UART transfer speeds”.
3 to 0 BR_T1 Factor BR_T1 to adjust the transfer speed, for description see Section
10.3.2 “Selectable UART transfer speeds”.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.3 Page 2: Configuration
9.2.3.1 PageReg
Selects the register page.
9.2.3.2 CRCResultReg
Shows the actual MSB and LSB values of the CRC calculation.
Note: The CRC is split into two 8-bit register.
Note: Setting the bit MSBFirst in ModeReg register reverses the bit order, the byte order is
not changed.
Table 79. PageReg register (address 20h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
UsePageSelect 0 0 0 0 0 PageSelect
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Table 80. Description of PageReg bits
Bit Symbol Description
7 UsePageSelect Set to logic 1, the value of PageSelect is used as register address A5
and A4. The LSB-bits of the register address are defined by the
address pins or the internal address latch, respectively.
Set to logic 0, the whole content of the internal address latch defines
the register address. The address pins are used as described in
Section 10.1 “Automatic microcontroller interface detection”.
6 to 2 - Reserved for future use.
1 to 0 PageSelect The value of PageSelect is used only if UsePageSelect is set to
logic 1. In this case, it specifies the register page (which is A5 and
A4of the register address).
Table 81. CRCResultReg register (address 21h); reset value: FFh, 11111111b
7 6 5 4 3 2 1 0
CRCResultMSB
Access Rights r r r r r r r r
Table 82. Description of CRCResultReg bits
Bit Symbol Description
7 to 0 CRCResultMSB This register shows the actual value of the most significant byte of
the CRCResultReg register. It is valid only if bit CRCReady in
register Status1Reg is set to logic 1.
Table 83. CRCResultReg register (address 22h); reset value: FFh, 11111111b
7 6 5 4 3 2 1 0
CRCResultLSB
Access Rights r r r r r r r r
Table 84. Description of CRCResultReg bits
Bit Symbol Description
7 to 0 CRCResultLSB This register shows the actual value of the least significant byte of
the CRCResult register. It is valid only if bit CRCReady in register
Status1Reg is set to logic 1.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.3.3 GsNOffReg
Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the
driver is switched off.
Table 85. GsNOffReg register (address 23h); reset value: 88h, 10001000b
7 6 5 4 3 2 1 0
CWGsNOff ModGsNOff
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Table 86. Description of GsNOffReg bits
Bit Symbol Description
7 to 4 CWGsNOff The value of this register defines the conductance of the output
N-driver during times of no modulation.
Note: The conductance value is binary weighted.
Note: During soft Power-down mode the highest bit is forced to 1.
Note: The value of the register is only used if the driver is switched
off. Otherwise the bit value CWGsNOn of register GsNOnReg is
used.
Note: This value is used for LoadModulation.
3 to 0 ModGsNOff The value of this register defines the conductance of the output
N-driver for the time of modulation. This may be used to regulate the
modulation index.
Note: The conductance value is binary weighted.
Note: During soft Power-down mode the highest bit is forced to 1.
Note: The value of the register is only used if the driver is switched
off. Otherwise the bit value ModGsNOn of register GsNOnReg is
used
Note: This value is used for LoadModulation.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.3.4 ModWidthReg
Controls the modulation width settings.
9.2.3.5 TxBitPhaseReg
Adjust the bitphase at 106 kbit during transmission.
Table 87. ModWidthReg register (address 24h); reset value: 26h, 00100110b
7 6 5 4 3 2 1 0
ModWidth
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Table 88. Description of ModWidthReg bits
Bit Symbol Description
7 to 0 ModWidth These bits define the width of the Miller modulation as initiator in Active
and Passive Communication mode as multiples of the carrier
frequency (ModWidth + 1/fc). The maximum value is half the bit
period.
Acting as a target in Passive Communication mode at 106 kbit or in
Card Operating mode for ISO/IEC 14443A/MIFARE these bits are
used to change the duty cycle of the subcarrier frequency.
The resulting number of carrier periods are calculated according to the
following formulas:
LOW value: #clocksLOW = (ModWidth modulo 8) + 1.
HIGH value: #clocksHIGH = 16-#clocksLOW.
Table 89. TxBitPhaseReg register (address 25h); reset value: 87h, 10000111b
7 6 5 4 3 2 1 0
RcvClkChange TxBitPhase
Access
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Table 90. Description of TxBitPhaseReg bits
Bit Symbol Description
7 RcvClkChange Set to logic 1, the demodulator’s clock is derived by the external RF
field.
6 to 0 TxBitPhase These bits are representing the number of carrier frequency clock
cycles, which are added to the waiting period before transmitting
data in all communication modes. TXBitPhase is used to adjust the
TX bit synchronization during passive NFCIP-1 communication mode
at 106 kbit and in ISO/IEC 14443A/MIFARE card mode.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.3.6 RFCfgReg
Configures the receiver gain and RF level detector sensitivity.
Table 91. RFCfgReg register (address 26h); reset value: 48h, 01001000b
7 6 5 4 3 2 1 0
RFLevelAmp RxGain RFLevel
Access
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Table 92. Description of RFCfgReg bits
Bit Symbol Description
7 RFLevelAmp Set to logic 1, this bit activates the RF level detectors’ amplifier.
6 to 4 RxGain This register defines the receivers signal voltage gain factor:
Value Description
000 18 dB
001 23 dB
010 18 dB
011 23 dB
100 33 dB
101 38 dB
110 43 dB
111 48 dB
3 to 0 RFLevel Defines the sensitivity of the RF level detector, for description see
Section 12.3 “RF level detector”.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.3.7 GsNOnReg
Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the
driver is switched on.
9.2.3.8 CWGsPReg
Defines the conductance of the P-driver during times of no modulation
Table 93. GsNOnReg register (address 27h); reset value: 88h, 10001000b
7 6 5 4 3 2 1 0
CWGsNOn ModGsNOn
Access
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Table 94. Description of GsNOnReg bits
Bit Symbol Description
7 to 4 CWGsNOn The value of this register defines the conductance of the output
N-driver during times of no modulation. This may be used to regulate
the output power and subsequently current consumption and
operating distance.
Note: The conductance value is binary weighted.
Note: During soft Power-down mode the highest bit is forced to 1.
Note: This value is only used if the driver TX1 or TX2 are switched on.
Otherwise the value of the bits CWGsNOff of register GsNOffReg is
used.
3 to 0 ModGsNOn The value of this register defines the conductance of the output
N-driver for the time of modulation. This may be used to regulate the
modulation index.
Note: The conductance value is binary weighted.
Note: During soft Power-down mode the highest bit is forced to 1.
Note: This value is only used if the driver TX1 or Tx2 are switched on.
Otherwise the value of the bits ModsNOff of register GsNOffReg is
used.
Table 95. CWGsPReg register (address 28h); reset value: 20h, 00100000b
7 6 5 4 3 2 1 0
0 0 CWGsP
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Table 96. Description of CWGsPReg bits
Bit Symbol Description
7 to 6 - Reserved for future use.
5 to 0 CWGsP The value of this register defines the conductance of the output
P-driver. This may be used to regulate the output power and
subsequently current consumption and operating distance.
Note: The conductance value is binary weighted.
Note: During soft Power-down mode the highest bit is forced to 1.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.3.9 ModGsPReg
Defines the driver P-output conductance during modulation.
[1] If Force100ASK is set to logic 1, the value of ModGsP has no effect.
9.2.3.10 TMode Register, TPrescaler Register
Defines settings for the timer.
Note: The Prescaler value is split into two 8-bit registers
Table 97. ModGsPReg register (address 29h); reset value: 20h, 00100000b
7 6 5 4 3 2 1 0
0 0 ModGsP
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Table 98. Description of ModGsPReg bits
Bit Symbol Description
7 to 6 - Reserved for future use.
5 to 0 ModGsP[1] The value of this register defines the conductance of the output
P-driver for the time of modulation. This may be used to regulate the
modulation index.
Note: The conductance value is binary weighted.
Note: During soft Power-down mode the highest bit is forced to 1.
Table 99. TModeReg register (address 2Ah); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
TAuto TGated TAutoRestart TPrescaler_Hi
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Table 100. Description of TModeReg bits
Bit Symbol Description
7 TAuto Set to logic 1, the timer starts automatically at the end of the transmission
in all communication modes at all speeds or when bit InitialRFOn is set to
logic 1 and the RF field is switched on.
In mode MIFARE and ISO14443-B 106kbit/s the timer stops after the 5th
bit (1 startbit, 4 databits) if the bit RxMultiple in the register RxModeReg is
not set. In all other modes, the timer stops after the 4th bit if the bit
RxMultiple the register RxModeReg is not set.
If RxMultiple is set to logic 1, the timer never stops. In this case the timer
can be stopped by setting the bit TStopNow in register ControlReg to 1.
Set to logic 0 indicates, that the timer is not influenced by the protocol.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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6 to 5 TGated The internal timer is running in gated mode.
Note: In the gated mode, the bit TRunning is 1 when the timer is enabled
by the register bits. This bit does not influence the gating signal.
Value Description
00 Non gated mode
01 Gated by SIGIN
10 Gated by AUX1
11 Gated by A3
4 TAutoRestart Set to logic 1, the timer automatically restart its count-down from
TReloadValue, instead of counting down to zero.
Set to logic 0 the timer decrements to ZERO and the bit TimerIRq is set
to logic 1.
3 to 0 TPrescaler_Hi Defines higher 4 bits for TPrescaler.
The following formula is used to calculate fTimer if TPrescalEven bit in
Demot Reg is set to logic 0:
fTimer = 13.56 MHz/(2*TPreScaler+1).
Where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] (TPrescaler value
on 12 bits) (Default TPrescalEven is logic 0)
The following formula is used to calculate fTimer if TPrescalEven bit in
Demot Reg is set to logic 1:
fTimer = 13.56 MHz/(2*TPreScaler+2).
For detailed description see Section 15 “Timer unit”. For the behaviour
within version 1.0, see Section 21 “Errata sheet” on page 109.
Table 101. TPrescalerReg register (address 2Bh); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
TPrescaler_Lo
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Table 102. Description of TPrescalerReg bits
Bit Symbol Description
7 to 0 TPrescaler_Lo Defines lower 8 bits for TPrescaler.
The following formula is used to calculate fTimer if TPrescalEven bit in
Demot Reg is set to logic 0:
fTimer = 13.56 MHz/(2*TPreScaler+1).
Where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] (TPrescaler value
on 12 bits)
The following formula is used to calculate fTimer if TPrescalEven bit in
Demot Reg is set to logic 1:
fTimer = 13.56 MHz/(2*TPreScaler+2).
Where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] (TPrescaler value
on 12 bits)
For detailed description see Section 15 “Timer unit”.
Table 100. Description of TModeReg bits …continued
Bit Symbol DescriptionPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.3.11 TReloadReg
Describes the 16-bit long timer reload value.
Note: The Reload value is split into two 8-bit registers.
Table 103. TReloadReg (Higher bits) register (address 2Ch); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
TReloadVal_Hi
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Table 104. Description of the higher TReloadReg bits
Bit Symbol Description
7 to 0 TReloadVal_Hi Defines the higher 8 bits for the TReloadReg.
With a start event the timer loads the TReloadVal. Changing this
register affects the timer only at the next start event.
Table 105. TReloadReg (Lower bits) register (address 2Dh); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
TReloadVal_Lo
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Table 106. Description of lower TReloadReg bits
Bit Symbol Description
7 to 0 TReloadVal_Lo Defines the lower 8 bits for the TReloadReg.
With a start event the timer loads the TReloadVal. Changing this
register affects the timer only at the next start event. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.3.12 TCounterValReg
Contains the current value of the timer.
Note: The Counter value is split into two 8-bit register.
9.2.4 Page 3: Test
9.2.4.1 PageReg
Selects the register page.
Table 107. TCounterValReg (Higher bits) register (address 2Eh); reset value: XXh,
XXXXXXXXb
7 6 5 4 3 2 1 0
TCounterVal_Hi
Access
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rrrrrrrr
Table 108. Description of the higher TCounterValReg bits
Bit Symbol Description
7 to 0 TCounterVal_Hi Current value of the timer, higher 8 bits.
Table 109. TCounterValReg (Lower bits) register (address 2Fh); reset value: XXh,
XXXXXXXXb
7 6 5 4 3 2 1 0
TCounterVal_Lo
Access
Rights
rrrrrrrr
Table 110. Description of lower TCounterValReg bits
Bit Symbol Description
7 to 0 TCounterVal_Lo Current value of the timer, lower 8 bits.
Table 111. PageReg register (address 30h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
UsePageSelect 0 0 0 0 0 PageSelect
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Table 112. Description of PageReg bits
Bit Symbol Description
7 UsePageSelect Set to logic 1, the value of PageSelect is used as register address
A5 and A4. The LSB-bits of the register address are defined by the
address pins or the internal address latch, respectively.
Set to logic 0, the whole content of the internal address latch defines
the register address. The address pins are used as described in
Section 10.1 “Automatic microcontroller interface detection”.
6 to 2 - Reserved for future use.
1 to 0 PageSelect The value of PageSelect is used only if UsePageSelect is set to
logic 1. In this case, it specifies the register page (which is A5 and
A4 of the register address).PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.4.2 TestSel1Reg
General test signal configuration.
9.2.4.3 TestSel2Reg
General test signal configuration and PRBS control
Table 113. TestSel1Reg register (address 31h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
- - SAMClockSel SAMClkD1 TstBusBitSel
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Table 114. Description of TestSel1Reg bits
Bit Symbol Description
7 to 6 - Reserved for future use.
5 to 4 SAMClockSel Defines the source for the 13.56 MHz SAM clock
Value Description
00 GND- Sam Clock switched off
01 clock derived by the internal oscillator
10 internal UART clock
11 clock derived by the RF field
3 SAMClkD1 Set to logic 1, the SAM clock is delivered to D1.
Note: Only possible if the 8bit parallel interface is not used.
2 to 0 TstBusBitSel Select the TestBus bit from the testbus to be propagated to SIGOUT.
Table 115. TestSel2Reg register (address 32h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
TstBusFlip PRBS9 PRBS15 TestBusSel
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Table 116. Description of TestSel2Reg bits
Bit Symbol Description
7 TstBusFlip If set to logic 1, the testbus is mapped to the parallel port by the
following order:
D4, D3, D2, D6, D5, D0, D1. See Section 20 “Testsignals”.
6 PRBS9 Starts and enables the PRBS9 sequence according ITU-TO150.
Note: All relevant registers to transmit data have to be configured
before entering PRBS9 mode.
Note: The data transmission of the defined sequence is started by the
send command.
5 PRBS15 Starts and enables the PRBS15 sequence according ITU-TO150.
Note: All relevant registers to transmit data have to be configured
before entering PRBS15 mode.
Note: The data transmission of the defined sequence is started by the
send command.
4 to 0 TestBusSel Selects the testbus. See Section 20 “Testsignals”PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.4.4 TestPinEnReg
Enables the pin output driver on the 8-bit parallel bus.
9.2.4.5 TestPinValueReg
Defines the values for the 7-bit parallel port when it is used as I/O.
Table 117. TestPinEnReg register (address 33h); reset value: 80h, 10000000b
7 6 5 4 3 2 1 0
RS232LineEn TestPinEn
Access
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Table 118. Description of TestPinEnReg bits
Bit Symbol Description
7 RS232LineEn Set to logic 0, the lines MX and DTRQ for the serial UART are
disabled.
6 to 0 TestPinEn Enables the pin output driver on the 8-bit parallel interface.
Example:
Setting bit 0 to 1 enables D0
Setting bit 5 to 1 enables D5
Note: Only valid if one of serial interfaces is used.
If the SPI interface is used only D0 to D4 can be used. If the serial
UART interface is used and RS232LineEn is set to logic 1 only D0 to
D4 can be used.
Table 119. TestPinValueReg register (address 34h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
UseIO TestPinValue
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Table 120. Description of TestPinValueReg bits
Bit Symbol Description
7 UseIO Set to logic 1, this bit enables the I/O functionality for the 7-bit parallel
port in case one of the serial interfaces is used. The input/output
behavior is defined by TestPinEn in register TestPinEnReg. The value
for the output behavior is defined in the bits TestPinVal.
Note: If SAMClkD1 is set to logic 1, D1 can not be used as I/O.
6 to 0 TestPinValue Defines the value of the 7-bit parallel port, when it is used as I/O. Each
output has to be enabled by the TestPinEn bits in register
TestPinEnReg.
Note: Reading the register indicates the actual status of the pins D6 -
D0 if UseIO is set to logic 1. If UseIO is set to logic 0, the value of the
register TestPinValueReg is read back. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.4.6 TestBusReg
Shows the status of the internal testbus.
9.2.4.7 AutoTestReg
Controls the digital selftest.
9.2.4.8 VersionReg
Shows the version.
Table 121. TestBusReg register (address 35h); reset value: XXh, XXXXXXXXb
7 6 5 4 3 2 1 0
TestBus
Access Rights r r r r r r r r
Table 122. Description of TestBusReg bits
Bit Symbol Description
7 to 0 TestBus Shows the status of the internal testbus. The testbus is selected by the
register TestSel2Reg. See Section 20 “Testsignals”.
Table 123. AutoTestReg register (address 36h); reset value: 40h, 01000000b
7 6 5 4 3 2 1 0
0 AmpRcv EOFSO
FAdjust
- SelfTest
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Table 124. Description of bits
Bit Symbol Description
7 - Reserved for production tests.
6 AmpRcv If set to logic 1, the internal signal processing in the receiver chain is
performed non-linear. This increases the operating distance in
communication modes at 106 kbit.
Note: Due to the non linearity the effect of the bits MinLevel and
CollLevel in the register RxThreshholdReg are as well non linear.
5 EOFSOFAdjust If set to logic 0 and the EOFSOFwidth is set to 1 will result in the
Maximum length of SOF and EOF according to ISO/IEC14443B
If set to logic 0 and the EOFSOFwidth is set to 0 will result in the
Minimum length of SOF and EOF according to ISO/IEC14443B
If this bit is set to 1 and the EOFSOFwidth bit is logic 1 will result in
SOF low = (11 etu 8 cycles)/fc
SOF high = (2 etu + 8 cycles)/fc
EOF low = (11 etu 8 cycles)/fc
For the behaviour in version 1.0, see Section 21 “Errata sheet” on
page 109.
4 - Reserved for future use.
3 to 0 SelfTest Enables the digital self test. The selftest can be started by the selftest
command in the command register. The selftest is enabled by 1001.
Note: For default operation the selftest has to be disabled by 0000.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Table 125. VersionReg register (address 37h); reset value: XXh, XXXXXXXXb
7 6 5 4 3 2 1 0
Version
Access Rights r r r r r r r r
Table 126. Description of VersionReg bits
Bit Symbol Description
7 to 0 Version 80h indicates PN512 version 1.0, differences to version 2.0 are
described within Section 21 “Errata sheet” on page 109.
82h indicates PN512 version 2.0, which covers also the industrial
version.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.4.9 AnalogTestReg
Controls the pins AUX1 and AUX2
Table 127. AnalogTestReg register (address 38h); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
AnalogSelAux1 AnalogSelAux2
Access Rights r/w r/w r/w r/w r/w r/w r/w r/w
Table 128. Description of AnalogTestReg bits
Bit Symbol Description
7 to 4
3 to 0
AnalogSelAux1
AnalogSelAux2
Controls the AUX pin.
Note: All test signals are described in Section 20 “Testsignals”.
Value Description
0000 Tristate
0001 Output of TestDAC1 (AUX1), output of TESTDAC2 (AUX2)
Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.
0010 Testsignal Corr1
Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.
0011 Testsignal Corr2
Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.
0100 Testsignal MinLevel
Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.
0101 Testsignal ADC channel I
Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.
0110 Testsignal ADC channel Q
Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.
0111 Testsignal ADC channel I combined with Q
Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.
1000 Testsignal for production test
Note: Current output. The use of 1 k pull-down resistor on AUX is recommended.
1001 SAM clock (13.56 MHz)
1010 HIGH
1011 LOW
1100 TxActive
At 106 kbit: HIGH during Startbit, Data bit, Parity and CRC. At 212 and 424 kbit: High
during Preamble, Sync, Data and CRC.
1101 RxActive
At 106 kbit: High during databit, Parity and CRC.
At 212 and 424 kbit: High during data and CRC.
1110 Subcarrier detected
106 kbit: not applicable
212 and 424 kbit: High during last part of Preamble, Sync data and CRC
1111 TestBus-Bit as defined by the TstBusBitSel in register TestSel1Reg.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.4.10 TestDAC1Reg
Defines the testvalues for TestDAC1.
9.2.4.11 TestDAC2Reg
Defines the testvalue for TestDAC2.
9.2.4.12 TestADCReg
Shows the actual value of ADC I and Q channel.
Table 129. TestDAC1Reg register (address 39h); reset value: XXh, 00XXXXXXb
7 6 5 4 3 2 1 0
0 0 TestDAC1
Access
Rights
RFT RFU r/w r/w r/w r/w r/w r/w
Table 130. Description of TestDAC1Reg bits
Bit Symbol Description
7 - Reserved for production tests.
6 - Reserved for future use.
5 to 0 TestDAC1 Defines the testvalue for TestDAC1. The output of the DAC1 can be
switched to AUX1 by setting AnalogSelAux1 to 0001 in register
AnalogTestReg.
Table 131. TestDAC2Reg register (address 3Ah); reset value: XXh, 00XXXXXXb
7 6 5 4 3 2 1 0
0 0 TestDAC2
Access
Rights
RFU RFU r/w r/w r/w r/w r/w r/w
Table 132. Description ofTestDAC2Reg bits
Bit Symbol Description
7 to 6 - Reserved for future use.
5 to 0 TestDAC2 Defines the testvalue for TestDAC2. The output of the DAC2 can be
switched to AUX2 by setting AnalogSelAux2 to 0001 in register
AnalogTestReg.
Table 133. TestADCReg register (address 3Bh); reset value: XXh, XXXXXXXXb
7 6 5 4 3 2 1 0
ADC_I ADC_Q
Access
Rights
Table 134. Description of TestADCReg bits
Bit Symbol Description
7 to 4 ADC_I Shows the actual value of ADC I channel.
3 to 0 ADC_Q Shows the actual value of ADC Q channel. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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9.2.4.13 RFTReg
10. Digital interfaces
10.1 Automatic microcontroller interface detection
The PN512 supports direct interfacing of hosts using SPI, I2C-bus or serial UART
interfaces. The PN512 resets its interface and checks the current host interface type
automatically after performing a power-on or hard reset. The PN512 identifies the host
interface by sensing the logic levels on the control pins after the reset phase. This is done
using a combination of fixed pin connections. Table 141 shows the different connection
configurations.
Table 135. RFTReg register (address 3Ch); reset value: FFh, 11111111b
7 6 5 4 3 2 1 0
11111111
Access
Rights
RFT RFT RFT RFT RFT RFT RFT RFT
Table 136. Description of RFTReg bits
Bit Symbol Description
7 to 0 - Reserved for production tests.
Table 137. RFTReg register (address 3Dh, 3Fh); reset value: 00h, 00000000b
7 6 5 4 3 2 1 0
00000000
Access
Rights
RFT RFT RFT RFT RFT RFT RFT RFT
Table 138. Description of RFTReg bits
Bit Symbol Description
7 to 0 - Reserved for production tests.
Table 139. RFTReg register (address 3Eh); reset value: 03h, 00000011b
7 6 5 4 3 2 1 0
00000011
Access
Rights
RFT RFT RFT RFT RFT RFT RFT RFT
Table 140. Description of RFTReg bits
Bit Symbol Description
7 to 0 - Reserved for production tests.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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[1] only available in HVQFN 40.
Table 141. Connection protocol for detecting different interface types
Pin Interface type
UART (input) SPI (output) I
2C-bus (I/O)
SDA RX NSS SDA
I
2C0 0 1
EA 0 1 EA
D7 TX MISO SCL
D6 MX MOSI ADR_0
D5 DTRQ SCK ADR_1
D4 - - ADR_2
D3 - - ADR_3
D2 - - ADR_4
D1 - - ADR_5
Table 142. Connection scheme for detecting the different interface types
PN512 Parallel Interface Type Serial Interface Types
Separated Read/Write Strobe Common Read/Write Strobe
Pin Dedicated
Address Bus
Multiplexed
Address Bus
Dedicated
Address Bus
Multiplexed
Address Bus
UART SPI I
2C
ALE 1 ALE 1 AS RX NSS SDA
A5[1] A5 0 A5 0 0 0 0
A4[1] A4 0 A4 0 0 0 0
A3[1] A3 0 A3 0 0 0 0
A2[1] A2 1 A2 1 0 0 0
A1 A1 1 A1 1 0 0 1
A0 A0 1 A0 0 0 1 EA
NRD[1] NRD NRD NDS NDS 1 1 1
NWR[1] NWR NWR RD/NWR RD/NWR 1 1 1
NCS[1] NCS NCS NCS NCS NCS NCS NCS
D7 D7 D7 D7 D7 TX MISO SCL
D6 D6 D6 D6 D6 MX MOSI ADR_0
D5 D5 AD5 D5 AD5 DTRQ SCK ADR_1
D4 D4 AD4 D4 AD4 - - ADR_2
D3 D3 AD3 D3 AD3 - - ADR_3
D2 D2 AD2 D2 AD2 - - ADR_4
D1 D1 AD1 D1 AD1 - - ADR_5
D0 D0 AD0 D0 AD0 - - ADR_6
Remark: Overview on the pin behavior
Pin behavior Input Output In/OutPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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10.2 Serial Peripheral Interface
A serial peripheral interface (SPI compatible) is supported to enable high-speed
communication to the host. The interface can handle data speeds up to 10 Mbit/s. When
communicating with a host, the PN512 acts as a slave, receiving data from the external
host for register settings, sending and receiving data relevant for RF interface
communication.
An interface compatible with SPI enables high-speed serial communication between the
PN512 and a microcontroller. The implemented interface is in accordance with the SPI
standard.
The timing specification is given in Section 26.1 on page 117.
The PN512 acts as a slave during SPI communication. The SPI clock signal SCK must be
generated by the master. Data communication from the master to the slave uses the
MOSI line. The MISO line is used to send data from the PN512 to the master.
Data bytes on both MOSI and MISO lines are sent with the MSB first. Data on both MOSI
and MISO lines must be stable on the rising edge of the clock and can be changed on the
falling edge. Data is provided by the PN512 on the falling clock edge and is stable during
the rising clock edge.
10.2.1 SPI read data
Reading data using SPI requires the byte order shown in Table 143 to be used. It is
possible to read out up to n-data bytes.
The first byte sent defines both the mode and the address.
[1] X = Do not care.
Remark: The MSB must be sent first.
10.2.2 SPI write data
To write data to the PN512 using SPI requires the byte order shown in Table 144. It is
possible to write up to n data bytes by only sending one address byte.
Fig 13. SPI connection to host
001aan220
PN512
SCK SCK
MOSI MOSI
MISO MISO
NSS NSS
Table 143. MOSI and MISO byte order
Line Byte 0 Byte 1 Byte 2 To Byte n Byte n + 1
MOSI address 0 address 1 address 2 ... address n 00
MISO X[1] data 0 data 1 ... data n 1 data nPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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The first send byte defines both the mode and the address byte.
[1] X = Do not care.
Remark: The MSB must be sent first.
10.2.3 SPI address byte
The address byte has to meet the following format.
The MSB of the first byte defines the mode used. To read data from the PN512 the MSB is
set to logic 1. To write data to the PN512 the MSB must be set to logic 0. Bits 6 to 1 define
the address and the LSB is set to logic 0.
10.3 UART interface
10.3.1 Connection to a host
Remark: Signals DTRQ and MX can be disabled by clearing TestPinEnReg register’s
RS232LineEn bit.
10.3.2 Selectable UART transfer speeds
The internal UART interface is compatible with an RS232 serial interface.
The default transfer speed is 9.6 kBd. To change the transfer speed, the host controller
must write a value for the new transfer speed to the SerialSpeedReg register. Bits
BR_T0[2:0] and BR_T1[4:0] define the factors for setting the transfer speed in the
SerialSpeedReg register.
The BR_T0[2:0] and BR_T1[4:0] settings are described in Table 10. Examples of different
transfer speeds and the relevant register settings are given in Table 11.
Table 144. MOSI and MISO byte order
Line Byte 0 Byte 1 Byte 2 To Byte n Byte n + 1
MOSI address 0 data 0 data 1 ... data n 1 data n
MISO X[1] X[1] X[1] ... X[1] X[1]
Table 145. Address byte 0 register; address MOSI
7 (MSB) 6 5 4 3 2 1 0 (LSB)
1 = read
0 = write
address 0
Fig 14. UART connection to microcontrollers
001aan221
PN512
RX RX
TX TX
DTRQ DTRQ
MX MXPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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[1] The resulting transfer speed error is less than 1.5 % for all described transfer speeds.
The selectable transfer speeds shown in Table 11 are calculated according to the
following equations:
If BR_T0[2:0] = 0:
(1)
If BR_T0[2:0] > 0:
(2)
Remark: Transfer speeds above 1228.8 kBd are not supported.
10.3.3 UART framing
Table 146. BR_T0 and BR_T1 settings
BR_Tn Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
BR_T0 factor 1 1 2 4 8 16 32 64
BR_T1 range 1 to 32 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64
Table 147. Selectable UART transfer speeds
Transfer speed (kBd) SerialSpeedReg value Transfer speed accuracy (%)[1]
Decimal Hexadecimal
7.2 250 FAh 0.25
9.6 235 EBh 0.32
14.4 218 DAh 0.25
19.2 203 CBh 0.32
38.4 171 ABh 0.32
57.6 154 9Ah 0.25
115.2 122 7Ah 0.25
128 116 74h 0.06
230.4 90 5Ah 0.25
460.8 58 3Ah 0.25
921.6 28 1Ch 1.45
1228.8 21 15h 0.32
transfer speed 27.12 106
BR_T0 1 + = --------------------------------
transfer speed 27.12 106
BR_T1 33 +
2
BR_T0 1 – -----------------------------------
-----------------------------------
=
Table 148. UART framing
Bit Length Value
Start 1-bit 0
Data 8 bits data
Stop 1-bit 1PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Remark: The LSB for data and address bytes must be sent first. No parity bit is used
during transmission.
Read data: To read data using the UART interface, the flow shown in Table 149 must be
used. The first byte sent defines both the mode and the address.
Write data: To write data to the PN512 using the UART interface, the structure shown in
Table 150 must be used.
The first byte sent defines both the mode and the address.
Table 149. Read data byte order
Pin Byte 0 Byte 1
RX (pin 24) address -
TX (pin 31) - data 0
(1) Reserved.
Fig 15. UART read data timing diagram
001aak588
SA
ADDRESS
RX
TX
MX
DTRQ
A0 A1 A2 A3 A4 A5 (1) SO
SA D0 D1 D2 D3 D4 D5 D6 D7 SO
DATA
R/W
Table 150. Write data byte order
Pin Byte 0 Byte 1
RX (pin 24) address 0 data 0
TX (pin 31) - address 0xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Remark: The data byte can be sent directly after the address byte on pin RX.
Address byte: The address byte has to meet the following format:
(1) Reserved.
Fig 16. UART write data timing diagram
001aak589
SA
ADDRESS
RX
TX
MX
DTRQ
A0 A1 A2 A3 A4 A5 (1) SO SA D0 D1 D2 D3 D4 D5 D6 D7 SO
SA A0 A1 A2 A3 A4 A5 (1) SO
DATA
ADDRESS
R/W
R/WPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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The MSB of the first byte sets the mode used. To read data from the PN512, the MSB is
set to logic 1. To write data to the PN512 the MSB is set to logic 0. Bit 6 is reserved for
future use, and bits 5 to 0 define the address; see Table 151.
10.4 I2C Bus Interface
An I2C-bus (Inter-IC) interface is supported to enable a low-cost, low pin count serial bus
interface to the host. The I2C-bus interface is implemented according to
NXP Semiconductors’ I
2C-bus interface specification, rev. 2.1, January 2000. The
interface can only act in Slave mode. Therefore the PN512 does not implement clock
generation or access arbitration.
The PN512 can act either as a slave receiver or slave transmitter in Standard mode, Fast
mode and High-speed mode.
SDA is a bidirectional line connected to a positive supply voltage using a current source or
a pull-up resistor. Both SDA and SCL lines are set HIGH when data is not transmitted. The
PN512 has a 3-state output stage to perform the wired-AND function. Data on the I2C-bus
can be transferred at data rates of up to 100 kBd in Standard mode, up to 400 kBd in Fast
mode or up to 3.4 Mbit/s in High-speed mode.
If the I2C-bus interface is selected, spike suppression is activated on lines SCL and SDA
as defined in the I2C-bus interface specification.
See Table 171 on page 117 for timing requirements.
Table 151. Address byte 0 register; address MOSI
7 (MSB) 6 5 4 3 2 1 0 (LSB)
1 = read
0 = write
reserved address
Fig 17. I2C-bus interface
001aan222
PN512
SDA
SCL
I2C
EA
ADR_[5:0]
PULL-UP
NETWORK
CONFIGURATION
WIRING
PULL-UP
NETWORK
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10.4.1 Data validity
Data on the SDA line must be stable during the HIGH clock period. The HIGH or LOW
state of the data line must only change when the clock signal on SCL is LOW.
10.4.2 START and STOP conditions
To manage the data transfer on the I2C-bus, unique START (S) and STOP (P) conditions
are defined.
• A START condition is defined with a HIGH-to-LOW transition on the SDA line while
SCL is HIGH.
• A STOP condition is defined with a LOW-to-HIGH transition on the SDA line while
SCL is HIGH.
The I2C-bus master always generates the START and STOP conditions. The bus is busy
after the START condition. The bus is free again a certain time after the STOP condition.
The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition.
The START (S) and repeated START (Sr) conditions are functionally identical. Therefore,
S is used as a generic term to represent both the START (S) and repeated START (Sr)
conditions.
10.4.3 Byte format
Each byte must be followed by an acknowledge bit. Data is transferred with the MSB first;
see Figure 22. The number of transmitted bytes during one data transfer is unrestricted
but must meet the read/write cycle format.
Fig 18. Bit transfer on the I2C-bus
mbc621
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 19. START and STOP conditions
mbc622
SDA
SCL
P
STOP condition
SDA
SCL
S
START conditionPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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10.4.4 Acknowledge
An acknowledge must be sent at the end of one data byte. The acknowledge-related clock
pulse is generated by the master. The transmitter of data, either master or slave, releases
the SDA line (HIGH) during the acknowledge clock pulse. The receiver pulls down the
SDA line during the acknowledge clock pulse so that it remains stable LOW during the
HIGH period of this clock pulse.
The master can then generate either a STOP (P) condition to stop the transfer or a
repeated START (Sr) condition to start a new transfer.
A master-receiver indicates the end of data to the slave-transmitter by not generating an
acknowledge on the last byte that was clocked out by the slave. The slave-transmitter
releases the data line to allow the master to generate a STOP (P) or repeated START (Sr)
condition.
Fig 20. Acknowledge on the I2C-bus
mbc602
S
START
condition
1 2 8 9
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from
master
Fig 21. Data transfer on the I2C-bus
msc608
Sr
or
P
SDA
Sr
P
SCL
STOP or
repeated START
condition
S
or
Sr
START or
repeated START
condition
1 2 3 - 8 9
ACK
9
ACK
1 2 7 8
MSB acknowledgement
signal from slave
byte complete,
interrupt within slave
clock line held LOW while
interrupts are serviced
acknowledgement
signal from receiverPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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10.4.5 7-Bit addressing
During the I2C-bus address procedure, the first byte after the START condition is used to
determine which slave will be selected by the master.
Several address numbers are reserved. During device configuration, the designer must
ensure that collisions with these reserved addresses cannot occur. Check the I
2C-bus
specification for a complete list of reserved addresses.
The I2C-bus address specification is dependent on the definition of pin EA. Immediately
after releasing pin NRSTPD or after a power-on reset, the device defines the I2C-bus
address according to pin EA.
If pin EA is set LOW, the upper 4 bits of the device bus address are reserved by
NXP Semiconductors and set to 0101b for all PN512 devices. The remaining 3 bits
(ADR_0, ADR_1, ADR_2) of the slave address can be freely configured by the customer
to prevent collisions with other I2C-bus devices.
If pin EA is set HIGH, ADR_0 to ADR_5 can be completely specified at the external pins
according to Table 141 on page 69. ADR_6 is always set to logic 0.
In both modes, the external address coding is latched immediately after releasing the
reset condition. Further changes at the used pins are not taken into consideration.
Depending on the external wiring, the I2C-bus address pins can be used for test signal
outputs.
10.4.6 Register write access
To write data from the host controller using the I2C-bus to a specific register in the PN512
the following frame format must be used.
• The first byte of a frame indicates the device address according to the I2C-bus rules.
• The second byte indicates the register address followed by up to n-data bytes.
In one frame all data bytes are written to the same register address. This enables fast
FIFO buffer access. The Read/Write (R/W) bit is set to logic 0.
Fig 22. First byte following the START procedure
slave address 001aak591
bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W
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10.4.7 Register read access
To read out data from a specific register address in the PN512, the host controller must
use the following procedure:
• Firstly, a write access to the specific register address must be performed as indicated
in the frame that follows
• The first byte of a frame indicates the device address according to the I2C-bus rules
• The second byte indicates the register address. No data bytes are added
• The Read/Write bit is 0
After the write access, read access can start. The host sends the device address of the
PN512. In response, the PN512 sends the content of the read access register. In one
frame all data bytes can be read from the same register address. This enables fast FIFO
buffer access or register polling.
The Read/Write (R/W) bit is set to logic 1.
Fig 23. Register read and write access
001aak592
S A 0 0
I
2C-BUS
SLAVE ADDRESS
[A7:A0]
JOINER REGISTER
ADDRESS [A5:A0]
write cycle
0
(W) A DATA
[7:0] [0:n]
[0:n]
[0:n]
A
P
S A 0 0
I
2C-BUS
SLAVE ADDRESS
[A7:A0]
JOINER REGISTER
ADDRESS [A5:A0]
read cycle
optional, if the previous access was on the same register address
0
(W) A P
P
S
S start condition
P stop condition
A acknowledge
A not acknowledge
W write cycle
R read cycle
A
I
2C-BUS
SLAVE ADDRESS
[A7:A0]
sent by master
sent by slave
DATA
[7:0]
1
(R) A
DATA
[7:0]
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10.4.8 High-speed mode
In High-speed mode (HS mode), the device can transfer information at data rates of up to
3.4 Mbit/s, while remaining fully downward-compatible with Fast or Standard mode
(F/S mode) for bidirectional communication in a mixed-speed bus system.
10.4.9 High-speed transfer
To achieve data rates of up to 3.4 Mbit/s the following improvements have been made to
I
2C-bus operation.
• The inputs of the device in HS mode incorporate spike suppression, a Schmitt trigger
on the SDA and SCL inputs and different timing constants when compared to
F/S mode
• The output buffers of the device in HS mode incorporate slope control of the falling
edges of the SDA and SCL signals with different fall times compared to F/S mode
10.4.10 Serial data transfer format in HS mode
The HS mode serial data transfer format meets the Standard mode I2C-bus specification.
HS mode can only start after all of the following conditions (all of which are in F/S mode):
1. START condition (S)
2. 8-bit master code (00001XXXb)
3. Not-acknowledge bit (A)
When HS mode starts, the active master sends a repeated START condition (Sr) followed
by a 7-bit slave address with a R/W bit address and receives an acknowledge bit (A) from
the selected PN512.
Data transfer continues in HS mode after the next repeated START (Sr), only switching
back to F/S mode after a STOP condition (P). To reduce the overhead of the master code,
a master links a number of HS mode transfers, separated by repeated START conditions
(Sr).
Fig 24. I2C-bus HS mode protocol switch
F/S mode HS mode (current-source for SCL HIGH enabled) F/S mode
001aak749
A A/A A DATA
(n-bytes + A)
S MASTER CODE Sr SLAVE ADDRESS R/W
HS mode continues
Sr SLAVE ADDRESS
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Fig 25. I2C-bus HS mode protocol frame
msc618
8-bit master code 0000 1xxx A
tH
t1
S
F/S mode
HS mode
If P then
F/S mode
If Sr (dotted lines)
then HS mode
1 6789 6789 1
1 2 to 5
2 to 5 2 to 5
67 89
SDA high
SCL high
SDA high
SCL high
tH tFS
Sr Sr P 7-bit SLA R/W A n + (8-bit data + A/A)
= Master current source pull-up
= Resistor pull-upPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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10.4.11 Switching between F/S mode and HS mode
After reset and initialization, the PN512 is in Fast mode (which is in effect F/S mode as
Fast mode is downward-compatible with Standard mode). The connected PN512
recognizes the “S 00001XXX A” sequence and switches its internal circuitry from the Fast
mode setting to the HS mode setting.
The following actions are taken:
1. Adapt the SDA and SCL input filters according to the spike suppression requirement
in HS mode.
2. Adapt the slope control of the SDA output stages.
It is possible for system configurations that do not have other I2C-bus devices involved in
the communication to switch to HS mode permanently. This is implemented by setting
Status2Reg register’s I2CForceHS bit to logic 1. In permanent HS mode, the master code
is not required to be sent. This is not defined in the specification and must only be used
when no other devices are connected on the bus. In addition, spikes on the I2C-bus lines
must be avoided because of the reduced spike suppression.
10.4.12 PN512 at lower speed modes
PN512 is fully downward-compatible and can be connected to an F/S mode I2C-bus
system. The device stays in F/S mode and communicates at F/S mode speeds because a
master code is not transmitted in this configuration.
11. 8-bit parallel interface
The PN512 supports two different types of 8-bit parallel interfaces, Intel and Motorola
compatible modes.
11.1 Overview of supported host controller interfaces
The PN512 supports direct interfacing to various -Controllers. The following table shows
the parallel interface types supported by the PN512.
Table 152. Supported interface types
Supported interface types Bus Separated Address and
Data Bus
Multiplexed Address
and Data Bus
Separated Read and Write
Strobes (INTEL compatible)
control NRD, NWR, NCS NRD, NWR, NCS, ALE
address A0 … A3 [..A5*] AD0 … AD7
data D0 … D7 AD0 … AD7
Multiplexed Read and Write
Strobe (Motorola compatible)
control R/NW, NDS, NCS R/NW, NDS, NCS, AS
address A0 … A3 [..A5*] AD0 … AD7
data D0 … D7 AD0 … AD7PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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11.2 Separated Read/Write strobe
For timing requirements refer to Section 26.2 “8-bit parallel interface timing”.
11.3 Common Read/Write strobe
For timing requirements refer to Section 26.2 “8-bit parallel interface timing”
Fig 26. Connection to host controller with separated Read/Write strobes
001aan223
PN512
NCS
A0...A3[A5*]
D0...D7
A0
A1
A2
A3
A4*
A5*
address bus (A0...A3[A5*])
ALE
NRD
NWR
ADDRESS
DECODER
data bus (D0...D7)
high
not data strobe (NRD)
not write (NWR)
address bus
remark: *depending on the package type.
multiplexed address/data AD0...AD7)
PN512
NCS
D0...D7
ALE
NRD
NWR
ADDRESS
DECODER
low
low
high
high
high
low
address latch enable (ALE)
not read strobe (NRD)
not write (NWR)
non multiplexed
address
Fig 27. Connection to host controller with common Read/Write strobes
001aan224
PN512
NCS
A0...A3[A5*]
D0...D7
A0
A1
A2
A3
A4*
A5*
address bus (A0...A3[A5*])
ALE
NRD
NWR
ADDRESS
DECODER
Data bus (D0...D7)
high
not data strobe (NDS)
read not write (RD/NWR)
address bus
remark: *depending on the package type.
multiplexed address/data AD0...AD7)
PN512
NCS
D0...D7
ALE
NRD
NWR
ADDRESS
DECODER
low
low
high
high
low
low
address strobe (AS)
not data strobe (NDS)
read not write (RD/NWR)
non multiplexed
addressPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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12. Analog interface and contactless UART
12.1 General
The integrated contactless UART supports the external host online with framing and error
checking of the protocol requirements up to 848 kBd. An external circuit can be connected
to the communication interface pins MFIN and MFOUT to modulate and demodulate the
data.
The contactless UART handles the protocol requirements for the communication
protocols in cooperation with the host. Protocol handling generates bit and byte-oriented
framing. In addition, it handles error detection such as parity and CRC, based on the
various supported contactless communication protocols.
Remark: The size and tuning of the antenna and the power supply voltage have an
important impact on the achievable operating distance.
12.2 TX driver
The signal on pins TX1 and TX2 is the 13.56 MHz energy carrier modulated by an
envelope signal. It can be used to drive an antenna directly using a few passive
components for matching and filtering; see Section 15 on page 96. The signal on pins TX1
and TX2 can be configured using the TxControlReg register; see Section 9.2.2.5 on
page 40.
The modulation index can be set by adjusting the impedance of the drivers. The
impedance of the p-driver can be configured using registers CWGsPReg and
ModGsPReg. The impedance of the n-driver can be configured using the GsNReg
register. The modulation index also depends on the antenna design and tuning.
The TxModeReg and TxSelReg registers control the data rate and framing during
transmission and the antenna driver setting to support the different requirements at the
different modes and transfer speeds.
[1] X = Do not care.
Table 153. Register and bit settings controlling the signal on pin TX1
Bit
Tx1RFEn
Bit
Force
100ASK
Bit
InvTx1RFOn
Bit
InvTx1RFOff
Envelope Pin
TX1
GSPMos GSNMos Remarks
0 X[1] X[1] X[1] X[1] X[1] CWGsNOff CWGsNOff not specified if RF is
switched off
1 00 X[1] 0 RF pMod nMod 100 % ASK: pin TX1
pulled to logic 0,
independent of the
InvTx1RFOff bit
1 RF pCW nCW
01 X[1] 0 RF pMod nMod
1 RF pCW nCW
11 X[1] 0 0 pMod nMod
1 RF_n pCW nCWPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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[1] X = Do not care.
The following abbreviations have been used in Table 153 and Table 154:
• RF: 13.56 MHz clock derived from 27.12 MHz quartz crystal oscillator divided by 2
• RF_n: inverted 13.56 MHz clock
• GSPMos: conductance, configuration of the PMOS array
• GSNMos: conductance, configuration of the NMOS array
• pCW: PMOS conductance value for continuous wave defined by the CWGsPReg
register
• pMod: PMOS conductance value for modulation defined by the ModGsPReg register
• nCW: NMOS conductance value for continuous wave defined by the GsNReg
register’s CWGsN[3:0] bits
• nMod: NMOS conductance value for modulation defined by the GsNReg register’s
ModGsN[3:0] bits
• X = do not care.
Remark: If only one driver is switched on, the values for CWGsPReg, ModGsPReg and
GsNReg registers are used for both drivers.
12.3 RF level detector
The RF level detector is integrated to fulfill NFCIP1 protocol requirements (e.g. RF
collision avoidance). Furthermore the RF level detector can be used to wake up the
PN512 and to generate an interrupt.
Table 154. Register and bit settings controlling the signal on pin TX2
Bit
Tx1RFEn
Bit
Force
100ASK
Bit
Tx2CW
Bit
InvTx2RFOn
Bit
InvTx2RFOff
Envelope
Pin
TX2
GSPMos GSNMos Remarks
0 X[1] X[1] X[1] X[1] X[1] X[1] CWGsNOff CWGsNOff not specified if
RF is switched
off
1 0 00 X[1] 0 RF pMod nMod -
1 RF pCW nCW
1 X[1] 0 RF_n pMod nMod
1 RF_n pCW nCW
10 X[1] X[1] RF pCW nCW conductance
always CW for
the Tx2CW bit
1 X[1] X[1] RF_n pCW nCW
1 00 X[1] 0 0 pMod nMod 100 % ASK: pin
TX2 pulled
to logic 0
(independent of
the
InvTx2RFOn/In
vTx2RFOff bits)
1 RF pCW nCW
1 X[1] 0 0 pMod nMod
1 RF_n pCW nCW
10 X[1] X[1] RF pCW nCW
1 X[1] X[1] RF_n pCW nCWPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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The sensitivity of the RF level detector is adjustable in a 4-bit range using the bits RFLevel
in register RFCfgReg. The sensitivity itself depends on the antenna configuration and
tuning.
Possible sensitivity levels at the RX pin are listed in the Table 154.
To increase the sensitivity of the RF level detector an amplifier can be activated by setting
the bit RFLevelAmp in register RFCfgReg to 1.
Remark: During soft Power-down mode the RF level detector amplifier is automatically
switched off to ensure that the power consumption is less than 10 A at 3 V.
Remark: With typical antennas lower sensitivity levels can provoke misleading results
because of intrinsic noise in the environment.
Note: It is recommended to use the bit RFLevelAmp only with higher RF level settings.
12.4 Data mode detector
The Data mode detector gives the possibility to detect received signals according to the
ISO/IEC 14443A/MIFARE, FeliCa or NFCIP-1 schemes at the standard transfer speeds
for 106 kbit, 212 kbit and 424 kbit in order to prepare the internal receiver in a fast and
convenient way for further data processing.
The Data mode detector can only be activated by the AutoColl command. The mode
detector resets, when no external RF field is detected by the RF level detector. The Data
mode detector could be switched off during the AutoColl command by setting bit
ModeDetOff in register ModeReg to 1.
Table 155. Setting of the bits RFlevel in register RFCfgReg (RFLevel amplifier deactivated)
V~Rx [Vpp] RFLevel
~2 1111
~1.4 1110
~0.99 1101
~0.69 1100
~0.49 1011
~0.35 1010
~0.24 1001
~0.17 1000
~0.12 0111
~0.083 0110
~0.058 0101
~0.041 0100
~0.029 0011
~0.020 0010
~0.014 0001
~0.010 0000PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Fig 28. Data mode detector
001aan225
HOST INTERFACES
RECEIVER
I/Q DEMODULATOR
REGISTERS
REGISTERSETTING
FOR THE
DETECTED MODE
DATA MODE DETECTOR
PN512 RX
NFC @ 106 kbit/s
NFC @ 212 kbit/s
NFC @ 424 kbit/sPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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12.5 Serial data switch
Two main blocks are implemented in the PN512. The digital block comprises the state
machines, encoder/decoder logic. The analog block comprises the modulator and
antenna drivers, the receiver and amplifiers. The interface between these two blocks can
be configured in the way, that the interfacing signals may be routed to the pins SIGIN and
SIGOUT. SIGIN is capable of processing digital NFC signals on transfer speeds above
424 kbit. The SIGOUT pin can provide a digital signal that can be used with an additional
external circuit to generate transfer speeds above 424 kbit (including 106, 212 and
424 kbit). Furthermore SIGOUT and SIGIN can be used to enable the S2C interface in the
card SAM mode to emulate a card functionality with the PN512 and a secure IC. A secure
IC can be the SmartMX smart card controller IC.
This topology allows the analog block of the PN512 to be connected to the digital block of
another device.
The serial signal switch is controlled by the TxSelReg and RxSelReg registers.
Figure 29 shows the serial data switch for TX1 and TX2.
12.6 S2C interface support
The S2C provides the possibility to directly connect a secure IC to the PN512 in order act
as a contactless smart card IC via the PN512. The interfacing signals can be routed to the
pins SIGIN and SIGOUT. SIGIN can receive either a digital FeliCa or digitized
ISO/IEC 14443A signal sent by the secure IC. The SIGOUT pin can provide a digital
signal and a clock to communicate to the secure IC. A secure IC can be the smart card IC
provided by NXP Semiconductors.
The PN512 has an extra supply pin (SVDD and PVSS as Ground line) for the SIGIN and
SIGOUT pads.
Figure 31 outlines possible ways of communications via the PN512 to the secure IC.
Fig 29. Serial data switch for TX1 and TX2
001aak593
INTERNAL
CODER
INVERT IF
InvMod = 1
DriverSel[1:0]
00
01
10
11
3-state
to driver TX1 and TX2
0 = impedance = modulated
1 = impedance = CW 1
INVERT IF
PolMFin = 0 MFIN
envelopePN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Configured in the Secure Access Mode the host controller can directly communicate to
the Secure IC via SIGIN/SIGOUT. In this mode the PN512 generates the RF clock and
performs the communication on the SIGOUT line. To enable the Secure Access module
mode the clock has to be derived by the internal oscillator of the PN512, see bits
SAMClockSel in register TestSel1Reg.
Configured in Contactless Card mode the secure IC can act as contactless smart card IC
via the PN512. In this mode the signal on the SIGOUT line is provided by the external RF
field of the external reader/writer. To enable the Contactless Card mode the clock derived
by the external RF field has to be used.
The configuration of the S2C interface differs for the FeliCa and MIFARE scheme as
outlined in the following chapters.
Fig 30. Communication flows using the S2C interface
001aan226
CONTACTLESS UART
SERIAL SIGNAL SWITCH
FIFO AND STATE MACHINE
SPI, I2C, SERIAL UART
HOST CONTROLLER
PN512
SECURE CORE IC
SIGOUT
SIGIN
2. contactless
card mode
1. secure access
module (SAM) mode PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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12.6.1 Signal shape for Felica S2C interface support
The FeliCa secure IC is connected to the PN512 via the pins SIGOUT and SIGIN.
The signal at SIGOUT contains the information of the 13.56 MHz clock and the digitized
demodulated signal. The clock and the demodulated signal is combined by using the
logical function exclusive or.
To ensure that this signal is free of spikes, the demodulated signal is digitally filtered first.
The time delay for that digital filtering is in the range of one bit length. The demodulated
signal changes only at a positive edge of the clock.
The register TxSelReg controls the setting at SIGOUT.
The answer of the FeliCa SAM is transferred from SIGIN directly to the antenna driver.
The modulation is done according to the register settings of the antenna drivers.
The clock is switched to AUX1 or AUX2 (see AnalogSelAux).
Note: A HIGH signal on AUX1 and AUX2 has the same level as AVDD. A HIGH signal at
SIGOUT has the same level as SVDD. Alternatively it is possible to use pin D0 as clock
output if a serial interface is used. The HIGH level at D0 is the same as PVDD.
Note: The signal on the antenna is shown in principle only. In reality the waveform is
sinusoidal.
Fig 31. Signal shape for SIGOUT in FeliCa card SAM mode
Fig 32. Signal shape for SIGIN in SAM mode
001aan227
clock
signal on
SIGIN
signal on
antenna
001aan228
clock
demodulated
signal
signal on
SIGOUTPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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12.6.2 Waveform shape for ISO/IEC 14443A and MIFARE S2C support
The secure IC, e.g. the SmartMX is connected to the PN512 via the pins SIGOUT and
SIGIN.
The waveform shape at SIGOUT is a digital 13.56 MHz Miller coded signal with levels
between PVSS and PVDD derived out of the external 13.56 MHz carrier signal in case of
the Contactless Card mode or internally generated in terms of Secure Access mode.
The register TxSelReg controls the setting at SIGOUT.
Note: The clock settings for the Secure Access mode and the Contactless Card mode
differ, refer to the description of the bits SAMClockSel in register TestSel1Reg.
The signal at SIGIN is a digital Manchester coded signal according to the requirements of
the ISO/IEC 14443A with the subcarrier frequency of 847.5 kHz generated by the secure
IC.
Fig 33. Signal shape for SIGOUT in MIFARE Card SAM mode
Fig 34. Signal shape for SIGIN in MIFARE Card SAM mode
001aan229
1
0
bit
value RF
signal on
antenna
signal on
SIGOUT
01001
001aan230
0
1
0
1 1 0 0
bit
value
signal on
antenna
signal on
SIGINPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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12.7 Hardware support for FeliCa and NFC polling
12.7.1 Polling sequence functionality for initiator
1. Timer: The PN512 has a timer, which can be programmed in a way that it generates
an interrupt at the end of each timeslot, or if required an interrupt is generated at the
end of the last timeslot.
2. The receiver can be configured in a way to receive continuously. In this mode it can
receive any number of packets. The receiver is ready to receive the next packet
directly after the last packet has been received. This mode is active by setting the bit
RxMultiple in register RxModeReg to 1 and has to be stopped by software.
3. The internal UART adds one byte to the end of every received packet, before it is
transferred into the FIFO-buffer. This byte indicates if the received byte packet is
correct (see register ErrReg). The first byte of each packet contains the length byte of
the packet.
4. The length of one packet is 18 or 20 bytes (+ 1 byte Error-Info). The FIFO has a
length of 64 bytes. This means three packets can be stored in the FIFO at the same
time. If more than three packets are expected, the host controller has to empty the
FIFO, before the FIFO is filled completely. In case of a FIFO-overflow data is lost (See
bit BufferOvfl in register ErrorReg).
12.7.2 Polling sequence functionality for target
1. The host controller has to configure the PN512 with the correct polling response
parameters for the polling command.
2. To activate the automatic polling in Target mode, the AutoColl Command has to be
activated.
3. The PN512 receives the polling command send out by an initiator and answers with
the polling response. The timeslot is selected automatically (The timeslot itself is
randomly generated, but in the range 0 to TSN, which is defined by the Polling
command). The PN512 compares the system code, stored in byte 17 and 18 of the
Config Command with the system code received by the polling command of an
initiator. If the system code is equal, the PN512 answers according to the configured
polling response. The system code FF (hex) acts as a wildcard for the system code
bytes, i.e. a target of a system code 1234 (hex) answers to the polling command with
one of the following system codes 1234 (hex), 12FF (hex), FF34 (hex) or FFFF (hex).
If the system code does not match no answer is sent back by the PN512.
If a valid command is received by the PN512, which is not a Polling command, no
answer is sent back and the command AutoColl is stopped. The received packet is
stored in the FIFO.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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12.7.3 Additional hardware support for FeliCa and NFC
Additionally to the polling sequence support for the Felica mode, the PN512 supports the
check of the Len-byte.
The received Len-byte in accordance to the registers FelNFC1Reg and FelNFC2Reg:
DataLenMin in register FelNFC1Reg defines the minimum length of the accepted packet
length. This register is six bit long. Each bit represents a length of four bytes.
DataLenMax in register FelNFC2Reg defines the maximum length of the accepted
package. This register is six bit long. Each bit represents a length of four bytes. If set to
logic 1 this limit is ignored. If the length is not in the supposed range, the packet is not
transferred to the FIFO and receiving is kept active.
Example 1:
• DataLenMin = 4
– The length shall be greater or equal 16.
• DataLenMax = 5
– The length shall be smaller than 20. Valid area: 16, 17, 18, 19
Example 2:
• DataLenMin = 9
– The length shall be greater or equal 36.
• DataLenMax = 0
– The length shall be smaller than 256. Valid area: 36 to 255
12.7.4 CRC coprocessor
The following CRC coprocessor parameters can be configured:
• The CRC preset value can be either 0000h, 6363h, A671h or FFFFh depending on
the ModeReg register’s CRCPreset[1:0] bits setting
• The CRC polynomial for the 16-bit CRC is fixed to x16 + x12 + x5 + 1
• The CRCResultReg register indicates the result of the CRC calculation. This register
is split into two 8-bit registers representing the higher and lower bytes.
• The ModeReg register’s MSBFirst bit indicates that data will be loaded with the MSB
first.
Table 156. CRC coprocessor parameters
Parameter Value
CRC register length 16-bit CRC
CRC algorithm algorithm according to ISO/IEC 14443 A and ITU-T
CRC preset value 0000h, 6363h, A671h or FFFFh depending on the setting of the
ModeReg register’s CRCPreset[1:0] bitsPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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13. FIFO buffer
An 8 64 bit FIFO buffer is used in the PN512. It buffers the input and output data stream
between the host and the PN512’s internal state machine. This makes it possible to
manage data streams up to 64 bytes long without the need to take timing constraints into
account.
13.1 Accessing the FIFO buffer
The FIFO buffer input and output data bus is connected to the FIFODataReg register.
Writing to this register stores one byte in the FIFO buffer and increments the internal FIFO
buffer write pointer. Reading from this register shows the FIFO buffer contents stored in
the FIFO buffer read pointer and decrements the FIFO buffer read pointer. The distance
between the write and read pointer can be obtained by reading the FIFOLevelReg
register.
When the microcontroller starts a command, the PN512 can, while the command is in
progress, access the FIFO buffer according to that command. Only one FIFO buffer has
been implemented which can be used for input and output. The microcontroller must
ensure that there are not any unintentional FIFO buffer accesses.
13.2 Controlling the FIFO buffer
The FIFO buffer pointers can be reset by setting FIFOLevelReg register’s FlushBuffer bit
to logic 1. Consequently, the FIFOLevel[6:0] bits are all set to logic 0 and the ErrorReg
register’s BufferOvfl bit is cleared. The bytes stored in the FIFO buffer are no longer
accessible allowing the FIFO buffer to be filled with another 64 bytes.
13.3 FIFO buffer status information
The host can get the following FIFO buffer status information:
• Number of bytes stored in the FIFO buffer: FIFOLevelReg register’s FIFOLevel[6:0]
• FIFO buffer almost full warning: Status1Reg register’s HiAlert bit
• FIFO buffer almost empty warning: Status1Reg register’s LoAlert bit
• FIFO buffer overflow warning: ErrorReg register’s BufferOvfl bit. The BufferOvfl bit
can only be cleared by setting the FIFOLevelReg register’s FlushBuffer bit.
The PN512 can generate an interrupt signal when:
• ComIEnReg register’s LoAlertIEn bit is set to logic 1. It activates pin IRQ when
Status1Reg register’s LoAlert bit changes to logic 1.
• ComIEnReg register’s HiAlertIEn bit is set to logic 1. It activates pin IRQ when
Status1Reg register’s HiAlert bit changes to logic 1.
If the maximum number of WaterLevel bytes (as set in the WaterLevelReg register) or less
are stored in the FIFO buffer, the HiAlert bit is set to logic 1. It is generated according to
Equation 3:
HiAlert 64 FIFOLength = – WaterLevel (3)PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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If the number of WaterLevel bytes (as set in the WaterLevelReg register) or less are
stored in the FIFO buffer, the LoAlert bit is set to logic 1. It is generated according to
Equation 4:
(4)
14. Interrupt request system
The PN512 indicates certain events by setting the Status1Reg register’s IRq bit and, if
activated, by pin IRQ. The signal on pin IRQ can be used to interrupt the host using its
interrupt handling capabilities. This allows the implementation of efficient host software.
14.1 Interrupt sources overview
Table 157 shows the available interrupt bits, the corresponding source and the condition
for its activation. The ComIrqReg register’s TimerIRq interrupt bit indicates an interrupt set
by the timer unit which is set when the timer decrements from 1 to 0.
The ComIrqReg register’s TxIRq bit indicates that the transmitter has finished. If the state
changes from sending data to transmitting the end of the frame pattern, the transmitter
unit automatically sets the interrupt bit. The CRC coprocessor sets the DivIrqReg
register’s CRCIRq bit after processing all the FIFO buffer data which is indicated by
CRCReady bit = 1.
The ComIrqReg register’s RxIRq bit indicates an interrupt when the end of the received
data is detected. The ComIrqReg register’s IdleIRq bit is set if a command finishes and
the Command[3:0] value in the CommandReg register changes to idle (see Table 158 on
page 101).
The ComIrqReg register’s HiAlertIRq bit is set to logic 1 when the Status1Reg register’s
HiAlert bit is set to logic 1 which means that the FIFO buffer has reached the level
indicated by the WaterLevel[5:0] bits.
The ComIrqReg register’s LoAlertIRq bit is set to logic 1 when the Status1Reg register’s
LoAlert bit is set to logic 1 which means that the FIFO buffer has reached the level
indicated by the WaterLevel[5:0] bits.
The ComIrqReg register’s ErrIRq bit indicates an error detected by the contactless UART
during send or receive. This is indicated when any bit is set to logic 1 in register ErrorReg.
LoAlert FIFOLength WaterLevel =
Table 157. Interrupt sources
Interrupt flag Interrupt source Trigger action
TimerIRq timer unit the timer counts from 1 to 0
TxIRq transmitter a transmitted data stream ends
CRCIRq CRC coprocessor all data from the FIFO buffer has been processed
RxIRq receiver a received data stream ends
IdleIRq ComIrqReg register command execution finishes
HiAlertIRq FIFO buffer the FIFO buffer is almost full
LoAlertIRq FIFO buffer the FIFO buffer is almost empty
ErrIRq contactless UART an error is detectedPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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15. Timer unit
A timer unit is implemented in the PN512. The external host controller may use this timer
to manage timing relevant tasks. The timer unit may be used in one of the following
configurations:
• Time-out counter
• Watch-dog counter
• Stop watch
• Programmable one-shot
• Periodical trigger
The timer unit can be used to measure the time interval between two events or to indicate
that a specific event occurred after a specific time. The timer can be triggered by events
which will be explained in the following, but the timer itself does not influence any internal
event (e.g. A time-out during data reception does not influence the reception process
automatically). Furthermore, several timer related bits are set and these bits can be used
to generate an interrupt.
Timer
The timer has an input clock of 13.56 MHz (derived from the 27.12 MHz quartz). The timer
consists of two stages: 1 prescaler and 1 counter.
The prescaler is a 12-bit counter. The reload value for TPrescaler can be defined between
0 and 4095 in register TModeReg and TPrescalerReg.
The reload value for the counter is defined by 16 bits in a range of 0 to 65535 in the
register TReloadReg.
The current value of the timer is indicated by the register TCounterValReg.
If the counter reaches 0 an interrupt will be generated automatically indicated by setting
the TimerIRq bit in the register CommonIRqReg. If enabled, this event can be indicated on
the IRQ line. The bit TimerIRq can be set and reset by the host controller. Depending on
the configuration the timer will stop at 0 or restart with the value from register
TReloadReg.
The status of the timer is indicated by bit TRunning in register Status1Reg.
The timer can be manually started by TStartNow in register ControlReg or manually
stopped by TStopNow in register ControlReg.
Furthermore the timer can be activated automatically by setting the bit TAuto in the
register TModeReg to fulfill dedicated protocol requirements automatically.
The time delay of a timer stage is the reload value +1.
The definition of total time is: t = ((TPrescaler*2+1)*TReload+1)/13.56MHz or if
TPrescaleEven bit is set: t = ((TPrescaler*2+2)*TReload+1)/13.56MHz
Maximum time: TPrescaler = 4095,TReloadVal = 65535
=> (2*4095 +2)*65536/13.56 MHz = 39.59 s
Example:PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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To indicate 25 us it is required to count 339 clock cycles. This means the value for
TPrescaler has to be set to TPrescaler = 169.The timer has now an input clock of 25 us.
The timer can count up to 65535 timeslots of each 25 s. For the behaviour in version
1.0, see Section 21 “Errata sheet” on page 109.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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16. Power reduction modes
16.1 Hard power-down
Hard power-down is enabled when pin NRSTPD is LOW. This turns off all internal current
sinks including the oscillator. All digital input buffers are separated from the input pins and
clamped internally (except pin NRSTPD). The output pins are frozen at either a HIGH or
LOW level.
16.2 Soft power-down mode
Soft Power-down mode is entered immediately after the CommandReg register’s
PowerDown bit is set to logic 1. All internal current sinks are switched off, including the
oscillator buffer. However, the digital input buffers are not separated from the input pins
and keep their functionality. The digital output pins do not change their state.
During soft power-down, all register values, the FIFO buffer content and the configuration
keep their current contents.
After setting the PowerDown bit to logic 0, it takes 1024 clocks until the Soft power-down
mode is exited indicated by the PowerDown bit. Setting it to logic 0 does not immediately
clear it. It is cleared automatically by the PN512 when Soft power-down mode is exited.
Remark: If the internal oscillator is used, you must take into account that it is supplied by
pin AVDD and it will take a certain time (tosc) until the oscillator is stable and the clock
cycles can be detected by the internal logic. It is recommended for the serial UART, to first
send the value 55h to the PN512. The oscillator must be stable for further access to the
registers. To ensure this, perform a read access to address 0 until the PN512 answers to
the last read command with the register content of address 0. This indicates that the
PN512 is ready.
16.3 Transmitter power-down mode
The Transmitter Power-down mode switches off the internal antenna drivers thereby,
turning off the RF field. Transmitter power-down mode is entered by setting either the
TxControlReg register’s Tx1RFEn bit or Tx2RFEn bit to logic 0.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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17. Oscillator circuitry
The clock applied to the PN512 provides a time basis for the synchronous system’s
encoder and decoder. The stability of the clock frequency, therefore, is an important factor
for correct operation. To obtain optimum performance, clock jitter must be reduced as
much as possible. This is best achieved using the internal oscillator buffer with the
recommended circuitry.
If an external clock source is used, the clock signal must be applied to pin OSCIN. In this
case, special care must be taken with the clock duty cycle and clock jitter and the clock
quality must be verified.
18. Reset and oscillator start-up time
18.1 Reset timing requirements
The reset signal is filtered by a hysteresis circuit and a spike filter before it enters the
digital circuit. The spike filter rejects signals shorter than 10 ns. In order to perform a reset,
the signal must be LOW for at least 100 ns.
18.2 Oscillator start-up time
If the PN512 has been set to a Power-down mode or is powered by a VDDX supply, the
start-up time for the PN512 depends on the oscillator used and is shown in Figure 36.
The time (tstartup) is the start-up time of the crystal oscillator circuit. The crystal oscillator
start-up time is defined by the crystal.
The time (td) is the internal delay time of the PN512 when the clock signal is stable before
the PN512 can be addressed.
The delay time is calculated by:
(5)
The time (tosc) is the sum of td and tstartup.
Fig 35. Quartz crystal connection
001aan231
PN512
27.12 MHz
OSCOUT OSCIN
td
1024
27 s = = -------------- 37.74 sPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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19. PN512 command set
The PN512 operation is determined by a state machine capable of performing a set of
commands. A command is executed by writing a command code (see Table 158) to the
CommandReg register.
Arguments and/or data necessary to process a command are exchanged via the FIFO
buffer.
19.1 General description
The PN512 operation is determined by a state machine capable of performing a set of
commands. A command is executed by writing a command code (see Table 158) to the
CommandReg register.
Arguments and/or data necessary to process a command are exchanged via the FIFO
buffer.
19.2 General behavior
• Each command that needs a data bit stream (or data byte stream) as an input
immediately processes any data in the FIFO buffer. An exception to this rule is the
Transceive command. Using this command, transmission is started with the
BitFramingReg register’s StartSend bit.
• Each command that needs a certain number of arguments, starts processing only
when it has received the correct number of arguments from the FIFO buffer.
• The FIFO buffer is not automatically cleared when commands start. This makes it
possible to write command arguments and/or the data bytes to the FIFO buffer and
then start the command.
• Each command can be interrupted by the host writing a new command code to the
CommandReg register, for example, the Idle command.
Fig 36. Oscillator start-up time
001aak596
tstartup td
tosc
t
device activation
oscillator
clock stable
clock readyPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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19.3 PN512 command overview
19.3.1 PN512 command descriptions
19.3.1.1 Idle
Places the PN512 in Idle mode. The Idle command also terminates itself.
19.3.1.2 Config command
To use the automatic MIFARE Anticollision, FeliCa Polling and NFCID3 the data used for
these transactions has to be stored internally. All the following data have to be written to
the FIFO in this order:
SENS_RES (2 bytes); in order byte 0, byte 1
NFCID1 (3 Bytes); in order byte 0, byte 1, byte 2; the first NFCID1 byte is fixed to 08h and
the check byte is calculated automatically.
SEL_RES (1 Byte)
polling response (2 bytes (shall be 01h, FEh) + 6 bytes NFCID2 + 8 bytes Pad + 2 bytes
system code)
NFCID3 (1 byte)
In total 25 bytes are transferred into an internal buffer.
The complete NFCID3 is 10 bytes long and consists of the 3 NFCID1 bytes, the 6 NFCID2
bytes and the one NFCID3 byte which are listed above.
To read out this configuration the command Config with an empty FIFO-buffer has to be
started. In this case the 25 bytes are transferred from the internal buffer to the FIFO.
Table 158. Command overview
Command Command
code
Action
Idle 0000 no action, cancels current command execution
Configure 0001 Configures the PN512 for FeliCa, MIFARE and NFCIP-1
communication
Generate RandomID 0010 generates a 10-byte random ID number
CalcCRC 0011 activates the CRC coprocessor or performs a self test
Transmit 0100 transmits data from the FIFO buffer
NoCmdChange 0111 no command change, can be used to modify the
CommandReg register bits without affecting the command,
for example, the PowerDown bit
Receive 1000 activates the receiver circuits
Transceive 1100 transmits data from FIFO buffer to antenna and automatically
activates the receiver after transmission
AutoColl 1101 Handles FeliCa polling (Card Operation mode only) and
MIFARE anticollision (Card Operation mode only)
MFAuthent 1110 performs the MIFARE standard authentication as a reader
SoftReset 1111 resets the PN512PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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The PN512 has to be configured after each power up, before using the automatic
Anticollision/Polling function (AutoColl command). During a hard power down (reset pin)
this configuration remains unchanged.
This command terminates automatically when finished and the active command is idle.
19.3.1.3 Generate RandomID
This command generates a 10-byte random number which is initially stored in the internal
buffer. This then overwrites the 10 bytes in the internal 25-byte buffer. This command
automatically terminates when finished and the PN512 returns to Idle mode.
19.3.1.4 CalcCRC
The FIFO buffer content is transferred to the CRC coprocessor and the CRC calculation is
started. The calculation result is stored in the CRCResultReg register. The CRC
calculation is not limited to a dedicated number of bytes. The calculation is not stopped
when the FIFO buffer is empty during the data stream. The next byte written to the FIFO
buffer is added to the calculation.
The CRC preset value is controlled by the ModeReg register’s CRCPreset[1:0] bits. The
value is loaded in to the CRC coprocessor when the command starts.
This command must be terminated by writing a command to the CommandReg register,
such as, the Idle command.
If the AutoTestReg register’s SelfTest[3:0] bits are set correctly, the PN512 enters Self
Test mode. Starting the CalcCRC command initiates a digital self test. The result of the
self test is written to the FIFO buffer.
19.3.1.5 Transmit
The FIFO buffer content is immediately transmitted after starting this command. Before
transmitting the FIFO buffer content, all relevant registers must be set for data
transmission.
This command automatically terminates when the FIFO buffer is empty. It can be
terminated by another command written to the CommandReg register.
19.3.1.6 NoCmdChange
This command does not influence any running command in the CommandReg register. It
can be used to manipulate any bit except the CommandReg register Command[3:0] bits,
for example, the RcvOff bit or the PowerDown bit.
19.3.1.7 Receive
The PN512 activates the receiver path and waits for a data stream to be received. The
correct settings must be chosen before starting this command.
This command automatically terminates when the data stream ends. This is indicated
either by the end of frame pattern or by the length byte depending on the selected frame
type and speed.
Remark: If the RxModeReg register’s RxMultiple bit is set to logic 1, the Receive
command will not automatically terminate. It must be terminated by starting another
command in the CommandReg register.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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19.3.1.8 Transceive
This command continuously repeats the transmission of data from the FIFO buffer and the
reception of data from the RF field. The first action is transmit and after transmission the
command is changed to receive a data stream.
Each transmit process must be started by setting the BitFramingReg register’s StartSend
bit to logic 1. This command must be cleared by writing any command to the
CommandReg register.
Remark: If the RxModeReg register’s RxMultiple bit is set to logic 1, the Transceive
command never leaves the receive state because this state cannot be cancelled
automatically.
19.3.1.9 AutoColl
This command automatically handles the MIFARE activation and the FeliCa polling in the
Card Operation mode. The bit Initiator in the register ControlReg has to be set to logic 0
for correct operation. During this command also the mode detector is active if not
deactivated by setting the bit ModeDetOff in the ModeReg register. After the mode
detector detects a mode, all the mode dependent registers are set according to the
received data. In case of no external RF field the command resets the internal state
machine and returns to the initial state but it will not be terminated. When the command
terminates the transceive command gets active.
During protocol processing the IRQ bits are not supported. Only the last received frame
will serve the IRQ’s. The treatment of the TxCRCEn and RxCRCEn bits is different to the
protocol. During ISO/IEC 14443A activation the enable bits are defined by the command
AutoColl. The changes cannot be observed at the register TXModeReg and RXModeReg.
After the Transceive command is active, the value of the register bit is relevant.
The FIFO will also receive the two CRC check bytes of the last command even if they
already checked and correct, if the state machine (Anticollision and Select routine) has to
not been executed and 106 kbit is detected.
During Felica activation the register bit is always relevant and is not overruled by the
command settings. This command can be cleared by software by writing any other
command to the CommandReg register, e.g. the idle command. Writing the same content
again to the CommandReg register resets the state machine.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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NFCIP-1 106 kbps Passive Communication mode:
The MIFARE anticollision is finished and the command has automatically changed to
Transceive. The FIFO contains the ATR_REQ frame including the start byte F0h. The bit
TargetActivated in the Status2Reg register is set to logic 1.
NFCIP-1 212/424 kbps Passive Communication mode:
The FeliCa polling command is finished and the command has automatically changed to
Transceive. The FIFO contains the ATR_REQ. The bit TargetActivated in the Status2Reg
register is set to logic 1.
NFCIP-1 106/212/424 kbps Active Communication mode:
This command is changing the automatically to the command Transceive. The FIFO
contains the ATR REQ The bit TargetActivated in the Status2Reg register is set to logic 0.
For 106 kbps only, the first byte in the FIFO indicates the start byte F0h and the CRC is
added to the FIFO.
Fig 37. Autocoll Command
NFCIP-1 106 kB aud
ISO14443-3
NPCIP-1 > 106 kB aud
FELICA
IDLE MODEO
MODE
detection
RXF
raming
MFHalted = 1
HALT
AC
nAC
SELECT
nSELECT
HLTA
AC
polling,
polling response
next frame
received
next frame
received
REQA, WUPA
READY
ACTIVE
WUPA
SELECT SELECT
READY*
ACTIVE*
TRANSCEIVE
wait for
transmit
next frame
received
J N
HLTA
REQA,
WUPA,
AC,
nAC,
SELECT,
nSELECT,
error
REQA,
AC,
nAC,
SELECT,
nSELECT,
HLTA
REQA,
WUPA,
nAC,
nSELECT,
HLTA,
error
REQA,
WUPA,
nAC,
nSELECT,
HLTA,
error
REQA,
WUPA,
AC,
SELECT,
nSELECT,
error
00 10
AC
aaa-001826PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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MIFARE (Card Operation mode):
The MIFARE anticollision is finished and the command has automatically changed to
transceive. The FIFO contains the first command after the Select. The bit TargetActivated
in the Status2Reg register is set to logic 1.
Felica (Card Operation mode):
The FeliCa polling command is finished and the command has automatically changed to
transceive. The FIFO contains the first command followed after the Poling by the FeliCa
protocol. The bit TargetActivated in the Status2Reg register is set to logic 1.
19.3.1.10 MFAuthent
This command manages MIFARE authentication to enable a secure communication to
any MIFARE Mini, MIFARE 1K and MIFARE 4K card. The following data is written to the
FIFO buffer before the command can be activated:
• Authentication command code (60h, 61h)
• Block address
• Sector key byte 0
• Sector key byte 1
• Sector key byte 2
• Sector key byte 3
• Sector key byte 4
• Sector key byte 5
• Card serial number byte 0
• Card serial number byte 1
• Card serial number byte 2
• Card serial number byte 3
In total 12 bytes are written to the FIFO.
Remark: When the MFAuthent command is active all access to the FIFO buffer is
blocked. However, if there is access to the FIFO buffer, the ErrorReg register’s WrErr bit is
set.
This command automatically terminates when the MIFARE card is authenticated and the
Status2Reg register’s MFCrypto1On bit is set to logic 1.
This command does not terminate automatically if the card does not answer, so the timer
must be initialized to automatic mode. In this case, in addition to the IdleIRq bit, the
TimerIRq bit can be used as the termination criteria. During authentication processing, the
RxIRq bit and TxIRq bit are blocked. The Crypto1On bit is only valid after termination of
the MFAuthent command, either after processing the protocol or writing Idle to the
CommandReg register.
If an error occurs during authentication, the ErrorReg register’s ProtocolErr bit is set to
logic 1 and the Status2Reg register’s Crypto1On bit is set to logic 0.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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19.3.1.11 SoftReset
This command performs a reset of the device. The configuration data of the internal buffer
remains unchanged. All registers are set to the reset values. This command automatically
terminates when finished.
Remark: The SerialSpeedReg register is reset and therefore the serial data rate is set to
9.6 kBd.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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20. Testsignals
20.1 Selftest
The PN512 has the capability to perform a digital selftest. To start the selftest the following
procedure has to be performed:
1. Perform a soft reset.
2. Clear the internal buffer by writing 25 bytes of 00h and perform the Config Command.
3. Enable the Selftest by writing the value 09h to the register AutoTestReg.
4. Write 00h to the FIFO.
5. Start the Selftest with the CalcCRC Command.
6. The Selftest will be performed.
7. When the Selftest is finished, the FIFO contains the following bytes:
Version 1.0 has a different Selftest answer, explained in Section 21.
Correct answer for VersionReg equal to 82h:
00h, EBh, 66h, BAh, 57h, BFh, 23h, 95h, D0h, E3h, 0Dh, 3Dh, 27h, 89h, 5Ch, DEh,
9Dh, 3Bh, A7h, 00h, 21h, 5Bh, 89h, 82h, 51h, 3Ah, EBh, 02h, 0Ch, A5h, 00h,
49h, 7Ch, 84h, 4Dh, B3h, CCh, D2h, 1Bh, 81h, 5Dh, 48h, 76h, D5h, 71h, 61h,
21h, A9h, 86h, 96h, 83h, 38h, CFh, 9Dh, 5Bh, 6Dh, DCh, 15h, BAh, 3Eh, 7Dh,
95h, 3Bh, 2Fh
20.2 Testbus
The testbus is implemented for production test purposes. The following configuration can
be used to improve the design of a system using the PN512. The testbus allows to route
internal signals to the digital interface. The testbus signals are selected by accessing
TestBusSel in register TestSel2Reg.
Table 159. Testsignal routing (TestSel2Reg = 07h)
Pins D6 D5 D4 D3 D2 D1 D0
Testsignal sdata scoll svalid sover RCV_reset RFon,
filtered
Envelope
Table 160. Description of Testsignals
Pins Testsignal Description
D6 sdata shows the actual received data stream.
D5 scoll shows if in the actual bit a collision has been detected (106 kbit only)
D4 svalid shows if sdata and scoll are valid
D3 sover shows that the receiver has detected a stop condition
(ISO/IEC 14443A/ MIFARE mode only).
D2 RCV_reset shows if the receiver is reset
D1 RFon, filtered shows the value of the internal RF level detector
D0 Envelope shows the output of the internal coderPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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20.3 Testsignals at pin AUX
Table 161. Testsignal routing (TestSel2Reg = 0Dh)
Pins D6 D5 D4 D3 D2 D1 D0
Testsignal clkstable clk27/8 clk27rf/8 clkrf13rf/4 clk27 clk27rf clk13rf
Table 162. Description of Testsignals
Pins Testsignal Description
D6 clkstable shows if the oscillator delivers a stable signal.
D5 clk27/8 shows the output signal of the oscillator divided by 8
D4 clk27rf/8 shows the clk27rf signal divided by 8
D3 clkrf13/4 shows the clk13rf divided by 4.
D2 clk27 shows the output signal of the oscillator
D1 clk27rf shows the RF clock multiplied by 2.
D0 clk13rf shows the RF clock of 13.56 MHz
Table 163. Testsignal routing (TestSel2Reg = 19h)
Pins D6 D5 D4 D3 D2 D1 D0
Testsignal - TRunning - - - - -
Table 164. Description of Testsignals
Pins Testsignal Description
D6 - -
D5 TRunning TRunning stops 1 clockcycle after TimerIRQ is raised
D4 - -
D3 - -
D2 - -
D1 - -
D0 - -
Table 165. Testsignals description
SelAux Description for Aux1 / Aux2
0000 Tristate
0001 DAC: register TestDAC 1/2
0010 DAC: testsignal corr1
0011 DAC: testsignal corr2
0100 DAC: testsignal MinLevel
0101 DAC: ADC_I
0110 DAC: ADC_Q
0111 DAC: testsignal ADC_I combined with ADC_Q
1000 Testsignal for production test
1001 SAM clock
1010 High
1011 low
1100 TxActivePN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Each signal can be switched to pin AUX1 or AUX2 by setting SelAux1 or SelAux2 in the
register AnalogTestReg.
Note: The DAC has a current output, it is recommended to use a 1 k pull-down
resistance at pins AUX1/AUX2.
20.4 PRBS
Enables the PRBS9 or PRBS15 sequence according to ITU-TO150. To start the
transmission of the defined datastream the command send has to be activated. The
preamble/Sync byte/start bit/parity bit are generated automatically depending on the
selected mode.
Note: All relevant register to transmit data have to be configured before entering PRBS
mode according ITU-TO150.
21. Errata sheet
This data sheet is describing the functionality for version 2.0 and the industrial version.
This chapter lists all differences from version 1.0 to version 2.0:
The value of the version in Section 9.2.4.8 is set to80h.
The behaviour ‘RFU’ for the register is undefined.
The answer to the Selftest (see Section 20.1) for version 1.0 (VersionReg equal to 80h):
00h, AAh, E3h, 29h, 0Ch, 10h, 29zhh, 6Bh,
76h, 8Dh, AFh, 4Bh, A2h, DAh, 76h, 99h
C7h, 5Eh, 24h, 69h, D2h, BAh, FAh, BCh
3Eh, DAh, 96h, B5h, F5h, 94h, B0h, 3Ah
4Eh, C3h, 9Dh, 94h, 76h, 4Ch, EAh, 5Eh
38h, 10h, 8Fh, 2Dh, 21h, 4Bh, 52h, BFh
4Eh, C3h, 9Dh, 94h, 76h, 4Ch, EAh, 5Eh
38h, 10h, 8Fh, 2Dh, 21h, 4Bh, 52h, BFh
FBh, F4h, 19h, 94h, 82h, 5Ah, 72h, 9Dh
BAh, 0Dh, 1Fh, 17h, 56h, 22h, B9h, 08h
Only the default setting for the prescaler (see Section 15 “Timer unit” on page 96): t =
((TPreScaler*2+1)*TReload+1)/13,56 MHz is supported. As such only the formula fTimer =
13,56 MHz/(2*PreScaler+1) is applicable for the TPrescalerHigh in Table 100 “Description
of TModeReg bits” on page 57 and TPrescalerLo in Table 101 “TPrescalerReg register
(address 2Bh); reset value: 00h, 00000000b” on page 58. As there is no option for the
prescaler available, also the TPrescalEven is not available Section 9.2.2.10 on page 45.
This bit is set to ‘RFU’.
1101 RxActive
1110 Subcarrier detected
1111 TstBusBit
Table 165. Testsignals description
SelAux Description for Aux1 / Aux2PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Especially when using time slot protocols, it is needed that the error flag is copied into the
status information of the frame. When using the RxMultiple feature (see Section 9.2.2.4
on page 39) within version 1.0 the protocol error flag is not included in the status
information for the frame. In addition the CRCOk is copied instead of the CRCErr. This
can be a problem in frames without length information e.g. ISO/IEC 14443-B.
The version 1.0 does not accept a Type B EOF if there is no 1 bit after the series of 0 bits,
as such the configuration within Section 9.2.2.15 “TypeBReg” on page 50 bit 4 for
RxEOFReq does not exist. In addition the IC only has the possibility to select the
minimum or maximum timings for SOF/EOF generation defined in ISO/IEC14443B. As
such the configuration possible in version 2.0 through the EOFSOFAdjust bit (see Section
9.2.4.7 “AutoTestReg” on page 64) does not exist and the configuration is limited to only
setting minimum and maximum length according ISO/IEC 14443-B, see Section 9.2.2.15
“TypeBReg” on page 50, bit 4.
22. Application design-in information
The figure below shows a typical circuit diagram, using a complementary antenna
connection to the PN512.
The antenna tuning and RF part matching is described in the application note “NFC
Transmission Module Antenna and RF Design Guide”.
Fig 38. Typical circuit diagram
AVDD TVDD
RX
VMID
supply
TX1
TVSS
TX2
DVSS
DVDD
DVDD
PVDD
SVDD
AVSS
IRQ
NRSTPD
R1
R2
L0
C0
C0
C2
C1
CRX
RQ
C1 RQ
C2
L0
Cvmid
001aan232
27.12 MHz
OSCIN OSCOUT
HOST
CONTROLLER
interface
PN512
antenna
LantPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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23. Limiting values
24. Recommended operating conditions
Table 166. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDDA analog supply voltage 0.5 +4.0 V
VDDD digital supply voltage 0.5 +4.0 V
VDD(PVDD) PVDD supply voltage 0.5 +4.0 V
VDD(TVDD) TVDD supply voltage 0.5 +4.0 V
VDD(SVDD) SVDD supply voltage 0.5 +4.0 V
VI input voltage all input pins except pins SIGIN and
RX
VSS(PVSS) 0.5 VDD(PVDD) + 0.5 V
pin MFIN VSS(PVSS) 0.5 VDD(SVDD) + 0.5 V
Ptot total power dissipation per package; and VDDD in shortcut
mode
- 200 mW
Tj junction temperature - 125 C
VESD electrostatic discharge
voltage
HBM; 1500 , 100 pF;
JESD22-A114-B
- 2000 V
MM; 0.75 H, 200 pF;
JESD22-A114-A
- 200 V
Charged device model;
JESD22-C101-A
on all pins - 200 V
on all pins except SVDD in
TFBGA64 package
- 500 V
Industrial version:
VESD electrostatic discharge
voltage
HBM; 1500 , 100 pF;
JESD22-A114-B
- 2000 V
MM; 0.75 H, 200 pF;
JESD22-A114-A
- 200 V
Charged device model;
AEC-Q100-011
on all pins - 200 V
on all pins except SVDD - 500 V
Table 167. Operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VDDA analog supply voltage VDD(PVDD) VDDA = VDDD = VDD(TVDD);
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) =0V
[1][2] 2.5 - 3.6 V
VDDD digital supply voltage VDD(PVDD) VDDA = VDDD = VDD(TVDD);
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) =0V
[1][2] 2.5 - 3.6 V
VDD(TVDD) TVDD supply voltage VDD(PVDD) VDDA = VDDD = VDD(TVDD);
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) =0V
[1][2] 2.5 - 3.6 VPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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[1] Supply voltages below 3 V reduce the performance (the achievable operating distance).
[2] VDDA, VDDD and VDD(TVDD) must always be the same voltage.
[3] VDD(PVDD) must always be the same or lower voltage than VDDD.
25. Thermal characteristics
26. Characteristics
VDD(PVDD) PVDD supply voltage VDD(PVDD) VDDA = VDDD = VDD(TVDD);
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) =0V
[3] 1.6 - 3.6 V
VDD(SVDD) SVDD supply voltage VSSA = VSSD = VSS(PVSS) = VSS(TVSS) =0V 1.6 - 3.6 V
Tamb ambient temperature HVQFN32, HVQFN40, TFBGA64 30 - +85 C
Industrial version:
Tamb ambient temperature HVQFN32 40 - +90 C
Table 167. Operating conditions …continued
Symbol Parameter Conditions Min Typ Max Unit
Table 168. Thermal characteristics
Symbol Parameter Conditions Package Typ Unit
Rthj-a Thermal resistance from
junction to ambient
In still air with exposed pad
soldered on a 4 layer Jedec PCB
In still air
HVQFN32 40 K/W
HVQFN40 35 K/W
TFBGA64 K/W
Table 169. Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Input characteristics
Pins A0, A1 and NRSTPD
ILI input leakage current 1 - +1 A
VIH HIGH-level input voltage 0.7VDD(PVDD) -- V
VIL LOW-level input voltage - - 0.3VDD(PVDD) V
Pin SIGIN
ILI input leakage current 1 - +1 A
VIH HIGH-level input voltage 0.7VDD(SVDD) -- V
VIL LOW-level input voltage - - 0.3VDD(SVDD) V
Pin ALE
ILI input leakage current 1 - +1 A
VIH HIGH-level input voltage 0.7VDD(PVDD) -- V
VIL LOW-level input voltage - - 0.3VDD(PVDD) V
Pin RX[1]
Vi input voltage 1 -VDDA +1 V
Ci input capacitance VDDA = 3 V; receiver active;
VRX(p-p) = 1 V; 1.5 V (DC)
offset
- 10- pFPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Ri input resistance VDDA = 3 V; receiver active;
VRX(p-p) = 1 V; 1.5 V (DC)
offset
- 350 -
Input voltage range; see Figure 39
Vi(p-p)(min) minimum peak-to-peak input
voltage
Manchester encoded;
VDDA =3V
- 100 - mV
Vi(p-p)(max) maximum peak-to-peak input
voltage
Manchester encoded;
VDDA =3V
- 4- V
Input sensitivity; see Figure 39
Vmod modulation voltage minimum Manchester
encoded; VDDA = 3 V;
RxGain[2:0] = 111b (48 dB)
- 5 - mV
Pin OSCIN
ILI input leakage current 1 - +1 A
VIH HIGH-level input voltage 0.7VDDA -- V
VIL LOW-level input voltage - - 0.3VDDA V
Ci input capacitance VDDA = 2.8 V; DC = 0.65 V;
AC = 1 V (p-p)
- 2 - pF
Input/output characteristics
pins D1, D2, D3, D4, D5, D6 and D7
ILI input leakage current 1 - +1 A
VIH HIGH-level input voltage 0.7VDD(PVDD) -- V
VIL LOW-level input voltage - - 0.3VDD(PVDD) V
VOH HIGH-level output voltage VDD(PVDD) = 3 V; IO = 4 mA VDD(PVDD)
0.4
- VDD(PVDD) V
VOL LOW-level output voltage VDD(PVDD) = 3 V; IO = 4 mA VSS(PVSS) - VSS(PVSS) +
0.4
V
IOH HIGH-level output current VDD(PVDD) =3V - - 4 mA
IOL LOW-level output current VDD(PVDD) =3V - - 4 mA
Output characteristics
Pin SIGOUT
VOH HIGH-level output voltage VDD(SVDD) = 3 V; IO = 4 mA VDD(SVDD)
0.4
- VDD(SVDD) V
VOL LOW-level output voltage VDD(SVDD) = 3 V; IO = 4 mA VSS(PVSS) - VSS(PVSS) +
0.4
V
IOL LOW-level output current VDD(SVDD) =3V - - 4 mA
IOH HIGH-level output current VDD(SVDD) =3V - - 4 mA
Pin IRQ
VOH HIGH-level output voltage VDD(PVDD) = 3 V; IO = 4 mA VDD(PVDD)
0.4
- VDD(PVDD) V
VOL LOW-level output voltage VDD(PVDD) = 3 V; IO = 4 mA VSS(PVSS) - VSS(PVSS) +
0.4
V
IOL LOW-level output current VDD(PVDD) =3V - - 4 mA
IOH HIGH-level output current VDD(PVDD) =3V - - 4 mA
Table 169. Characteristics …continued
Symbol Parameter Conditions Min Typ Max UnitPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Pins AUX1 and AUX2
VOH HIGH-level output voltage VDDD = 3 V; IO = 4 mA VDDD 0.4 - VDDD V
VOL LOW-level output voltage VDDD = 3 V; IO = 4 mA VSS(PVSS) - VSS(PVSS) +
0.4
V
IOL LOW-level output current VDDD =3V - - 4 mA
IOH HIGH-level output current VDDD =3V - - 4 mA
Pins TX1 and TX2
VOL LOW-level output voltage VDD(TVDD) = 3 V;
IDD(TVDD) = 32 mA;
CWGsP[5:0] = 0Fh
- - 0.15 V
VDD(TVDD) = 3 V;
IDD(TVDD) = 80 mA;
CWGsP[5:0] = 0Fh
- - 0.4 V
VDD(TVDD) = 2.5 V;
IDD(TVDD) = 32 mA;
CWGsP[5:0] = 0Fh
- - 0.24 V
VDD(TVDD) = 2.5 V;
IDD(TVDD) = 80 mA;
CWGsP[5:0] = 0Fh
- - 0.64 V
VOH HIGH-level output voltage VDD(TVDD) = 3 V;
IDD(TVDD) = 32 mA;
CWGsP[5:0] = 3Fh
VDD(TVDD)
0.15
-- V
VDD(TVDD) = 3 V;
IDD(TVDD) = 80 mA;
CWGsP[5:0] = 3Fh
VDD(TVDD)
0.4
-- V
VDD(TVDD) = 2.5 V;
IDD(TVDD) = 32 mA;
CWGsP[5:0] = 3Fh
VDD(TVDD)
0.24
-- V
VDD(TVDD) = 2.5 V;
IDD(TVDD) = 80 mA;
CWGsP[5:0] = 3Fh
VDD(TVDD)
0.64
-- V
Industrial version:
VOL LOW-level output voltage VDD(TVDD) = 2.5 V;
IDD(TVDD) = 32 mA;
CWGsP[5:0] = 3Fh
- - 0.18 V
VDD(TVDD) = 2.5 V;
IDD(TVDD) = 80 mA;
CWGsP[5:0] = 3Fh
- -0.44 V
VOH HIGH-level output voltage VDD(TVDD) = 3 V;
IDD(TVDD) = 32 mA;
CWGsP[5:0] = 3Fh
VDD(TVDD)
0.18
-- V
VDD(TVDD) = 3 V;
IDD(TVDD) = 80 mA;
CWGsP[5:0] = 3Fh
VDD(TVDD)
0.44
-- V
Output resistance for TX1/TX2,
Industrial Version:
ROP,01H High level output resistance TVDD = 3 V, VTX = TVDD -
100 mV, CWGsP = 01h
123 180 261
Table 169. Characteristics …continued
Symbol Parameter Conditions Min Typ Max UnitPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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ROP,02H High level output resistance TVDD = 3 V, VTX = TVDD -
100 mV, CWGsP = 02h
61 90 131
ROP,04H High level output resistance TVDD = 3 V, VTX = TVDD -
100 mV, CWGsP = 04h
30 46 68
ROP,08H High level output resistance TVDD = 3 V, VTX = TVDD -
100 mV, CWGsP = 08h
15 23 35
ROP,10H High level output resistance TVDD = 3 V, VTX = TVDD -
100 mV, CWGsP = 10h
7.5 12 19
ROP,20H High level output resistance TVDD = 3 V, VTX = TVDD -
100 mV, CWGsP = 20h
4.2 6 9
ROP,3FH High level output resistance TVDD = 3 V, VTX = TVDD -
100 mV, CWGsP = 3Fh
2 35
RON,10H Low level output resistance TVDD = 3 V, VTX = TVDD -
100 mV, CWGsN = 10h
30 46 68
RON,20H Low level output resistance TVDD = 3 V, VTX = TVDD -
100 mV, CWGsN = 20h
15 23 35
RON,40H Low level output resistance TVDD = 3 V, VTX = TVDD -
100 mV, CWGsN = 40h
7.5 12 19
RON,80H Low level output resistance TVDD = 3 V, VTX = TVDD -
100 mV, CWGsN = 80h
4.2 6 9
RON,F0H Low level output resistance TVDD = 3 V, VTX = TVDD -
100 mV, CWGsN = F0h
2 35
Current consumption
Ipd power-down current VDDA = VDDD = VDD(TVDD) =
VDD(PVDD) =3V
hard power-down; pin
NRSTPD set LOW
[2] - -5 A
soft power-down; RF
level detector on
[2] - -10 A
IDD(PVDD) PVDD supply current pin PVDD [3] - -40 mA
IDD(TVDD) TVDD supply current pin TVDD; continuous wave [4][5][6] - 60 100 mA
IDD(SVDD) SVDD supply current pin SVDD [7] - -4 mA
IDDD digital supply current pin DVDD; VDDD =3V - 6.5 9 mA
IDDA analog supply current pin AVDD; VDDA = 3 V,
CommandReg register’s
RcvOff bit = 0
- 7 10 mA
pin AVDD; receiver
switched off; VDDA = 3 V,
CommandReg register’s
RcvOff bit = 1
- 3 5 mA
Industrial version:
IDDD digital supply current pin DVDD; VDDD =3V - 6.5 9,5 mA
Table 169. Characteristics …continued
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[1] The voltage on pin RX is clamped by internal diodes to pins AVSS and AVDD.
[2] Ipd is the total current for all supplies.
[3] IDD(PVDD) depends on the overall load at the digital pins.
[4] IDD(TVDD) depends on VDD(TVDD) and the external circuit connected to pins TX1 and TX2.
[5] During typical circuit operation, the overall current is below 100 mA.
[6] Typical value using a complementary driver configuration and an antenna matched to 40 between pins TX1 and TX2 at 13.56 MHz.
[7] IDD(SVDD) depends on the load at pin MFOUT.
Ipd power-down current VDDA = VDDD = VDD(TVDD) =
VDD(PVDD) =3V
hard power-down; pin
NRSTPD set LOW
[2] - -15 A
soft power-down; RF
level detector on
[2] - -30 A
Clock frequency
fclk clock frequency - 27.12 - MHz
clk clock duty cycle 40 50 60 %
tjit jitter time RMS - - 10 ps
Crystal oscillator
VOH HIGH-level output voltage pin OSCOUT - 1.1 - V
VOL LOW-level output voltage pin OSCOUT - 0.2 - V
Ci input capacitance pin OSCOUT - 2 - pF
pin OSCIN - 2 - pF
Typical input requirements
fxtal crystal frequency - 27.12 - MHz
ESR equivalent series resistance - - 100
CL load capacitance - 10 - pF
Pxtal crystal power dissipation - 50 100 W
Table 169. Characteristics …continued
Symbol Parameter Conditions Min Typ Max UnitPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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26.1 Timing characteristics
Fig 39. Pin RX input voltage range
001aak012
VMID
0 V
Vmod
Vi(p-p)(max) Vi(p-p)(min)
13.56 MHz
carrier
Table 170. SPI timing characteristics
Symbol Parameter Conditions Min Typ Max Unit
tWL pulse width LOW line SCK 50 - - ns
tWH pulse width HIGH line SCK 50 - - ns
th(SCKH-D) SCK HIGH to data input
hold time
SCK to changing
MOSI
25 - - ns
tsu(D-SCKH) data input to SCK HIGH
set-up time
changing MOSI to
SCK
25 - - ns
th(SCKL-Q) SCK LOW to data output
hold time
SCK to changing
MISO
- - 25 ns
t(SCKL-NSSH) SCK LOW to NSS HIGH
time
0 - - ns
Table 171. I2C-bus timing in Fast mode
Symbol Parameter Conditions Fast mode High-speed
mode
Unit
Min Max Min Max
fSCL SCL clock frequency 0 400 0 3400 kHz
tHD;STA hold time (repeated) START
condition
after this period,
the first clock pulse
is generated
600 - 160 - ns
tSU;STA set-up time for a repeated
START condition
600 - 160 - ns
tSU;STO set-up time for STOP condition 600 - 160 - ns
tLOW LOW period of the SCL clock 1300 - 160 - ns
tHIGH HIGH period of the SCL clock 600 - 60 - ns
tHD;DAT data hold time 0 900 0 70 nsPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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tSU;DAT data set-up time 100 - 10 - ns
tr rise time SCL signal 20 300 10 40 ns
tf fall time SCL signal 20 300 10 40 ns
tr rise time SDA and SCL
signals
20 300 10 80 ns
tf fall time SDA and SCL
signals
20 300 10 80 ns
tBUF bus free time between a STOP
and START condition
1.3 - 1.3 - s
Remark: The signal NSS must be LOW to be able to send several bytes in one data stream.
To send more than one data stream NSS must be set HIGH between the data streams.
Fig 40. Timing diagram for SPI
Fig 41. Timing for Fast and Standard mode devices on the I2C-bus
Table 171. I2C-bus timing in Fast mode …continued
Symbol Parameter Conditions Fast mode High-speed
mode
Unit
Min Max Min Max
001aaj634
tSCKL tSCKH tSCKL
tDXSH tSHDX tDXSH
tSLDX
tSLNH
MOSI
SCK
MISO
MSB
MSB
LSB
LSB
NSS
001aaj635
SDA
tf
SCL
tLOW tf
tSP tr
tHD;STA
tHD;DAT
tHD;STA
tr tHIGH
tSU;DAT
S Sr P S
tSU;STA
tSU;STO
tBUFPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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26.2 8-bit parallel interface timing
26.2.1 AC symbols
Each timing symbol has five characters. The first character is always 't' for time. The other
characters indicate the name of a signal or the logic state of that signal (depending on
position):
Example: tAVLL = time for address valid to ALE low
26.2.2 AC operating specification
26.2.2.1 Bus timing for separated Read/Write strobe
Table 172. AC symbols
Designation Signal Designation Logic Level
A address H HIGH
D data L LOW
W NWR or nWait Z high impedance
R NRD or R/NW or nWrite X any level or data
L ALE or AS V any valid signal or data
C NCS N NSS
S NDS or nDStrb and nAStrb, SCK
Table 173. Timing specification for separated Read/Write strobe
Symbol Parameter Min Max Unit
tLHLL ALE pulse width 10 - ns
tAVLL Multiplexed Address Bus valid to ALE low (Address Set Up Time) 5 - ns
tLLAX Multiplexed Address Bus valid after ALE low (Address Hold Time) 5 - ns
tLLWL ALE low to NWR, NRD low 10 - ns
tCLWL NCS low to NRD, NWR low 0 - ns
tWHCH NRD, NWR high to NCS high 0 - ns
tRLDV NRD low to DATA valid - 35 ns
tRHDZ NRD high to DATA high impedance - 10 ns
tDVWH DATA valid to NWR high 5 - ns
tWHDX DATA hold after NWR high (Data Hold Time) 5 - ns
tWLWH NRD, NWR pulse width 40 - ns
tAVWL Separated Address Bus valid to NRD, NWR low (Set Up Time) 30 - ns
tWHAX Separated Address Bus valid after NWR high (Hold Time) 5 - ns
tWHWL period between sequenced read/write accesses 40 - nsPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Remark: For separated address and data bus the signal ALE is not relevant and the
multiplexed addresses on the data bus don’t care.
For the multiplexed address and data bus the address lines A0 to A3 have to be
connected as described in chapter Automatic host controller Interface Type Detection.
26.2.2.2 Bus timing for common Read/Write strobe
Fig 42. Timing diagram for separated Read/Write strobe
001aan233
tLHLL
tCLWL
tLLWL
tWHWL tWLWH tWHWL
tWHDX
tRHDZ
tWLDV
tRLDV
tWHCH
tWHAX
tAVLL tLLAX
tAVWL
ALE
NCS
NWR
NRD
D0...D7 D0...D7
A0...A3
multiplexed
addressbus
A0...A3
SEPARATED ADDRESSBUS A0...A3
Table 174. Timing specification for common Read/Write strobe
Symbol Parameter Min Max Unit
tLHLL AS pulse width 10 - ns
tAVLL Multiplexed Address Bus valid to AS low (Address Set Up Time) 5 - ns
tLLAX Multiplexed Address Bus valid after AS low (Address Hold Time) 5 - ns
tLLSL AS low to NDS low 10 - ns
tCLSL NCS low to NDS low 0 - ns
tSHCH NDS high to NCS high 0 - ns
tSLDV,R NDS low to DATA valid (for read cycle) - 35 ns
tSHDZ NDS low to DATA high impedance (read cycle) - 10 ns
tDVSH DATA valid to NDS high (for write cycle) 5 - ns
tSHDX DATA hold after NDS high (write cycle, Hold Time) 5 - ns
tSHRX R/NW hold after NDS high 5 - ns
tSLSH NDS pulse width 40 - ns
tAVSL Separated Address Bus valid to NDS low (Hold Time) 30 - ns
tSHAX Separated Address Bus valid after NDS high (Set Up Time) 5 - nsPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Remark: For separated address and data bus the signal ALE is not relevant and the
multiplexed addresses on the data bus don’t care. For the multiplexed address and data
bus the address lines A0 to A3 have to be connected as described in Automatic
-Controller Interface Type Detection.
Fig 43. Timing diagram for common Read/Write strobe
SEPARATED ADDRESSBUS A0...A3
multiplexed
addressbus
A0...A3
ALE
tLHLL
tCLSL
R/NW
NDS
D0...D7 D0...D7
A0...A3
NCS
tSHCH
tSHRX tRVSL
tLLSL
tSLSH tSHSL
tAVLL
tLLAX
tSLDV, R
tSLDV, W tSHDX
tSHDZ
tSHAX tAVSL
tSHSL
001aan234PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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27. Package information
The PN512 can be delivered in 3 different packages.
Table 175. Package information
Package Remarks
HVQFN32 8-bit parallel interface not supported
HVQFN40 Supports the 8-bit parallel interface
TFBGA64 Ball grid array facilitating development of an PCI compliant devicePN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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28. Package outline
Fig 44. Package outline package version (HVQFN32)
1 0.5
UNIT A1 b Eh e y
0.2
c
OUTLINE REFERENCES
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 5.1
4.9
Dh
3.25
2.95
y1
5.1
4.9
3.25
2.95
e1
3.5
e2
3.5 0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT617-1 MO-220 - - - - - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT617-1
HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm
A(1)
max.
A
A1
c
detail X
y y e 1 C
L
Eh
Dh
e
e1
b
9 16
32 25
24
17
8
1
X
D
E
C
B A
e2
terminal 1
index area
terminal 1
index area
01-08-08
02-10-18
1/2 e
1/2 e AC
C
v M B
w M
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet
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Fig 45. Package outline package version (HVQFN40)
Outline References
version
European
projection Issue date
IEC JEDEC JEITA
SOT618-1 MO-220
sot618-1_po
02-10-22
13-11-05
Unit
mm
max
nom
min
1.00 0.05 0.2 6.1 4.25 6.1
0.4
A(1)
Dimensions (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
HVQFN40: plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6 x 6 x 0.85 mm SOT618-1
A1 b
0.30
c D(1) Dh E(1) Eh
4.10
e e1 e2 Lvw
0.05
y
0.05
y1
0.1
0.85 0.02 6.0 4.10 6.0 0.21
0.80 0.00 0.18 5.9 3.95 5.9 3.95 0.3
4.25 0.5 4.5 0.5 4.5 0.1
e
e
1/2 e
1/2 e
y
terminal 1
index area
A A1
c
L
Eh
Dh
b
11 20
40 31
30
21 10
1
D
E
terminal 1
index area
0 2.5 5 mm
scale
e1
AC
C
v B
w y1 C
C
e2
X
detail X
B APN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Fig 46. Package outline package version (TFBGA64)
Outline References
version
European
projection Issue date
IEC JEDEC JEITA
SOT1336-1 - - -
sot1336-1_po
12-06-19
12-08-28
Unit
mm
max
nom
min
1.15 0.35 0.45 5.6 5.6
4.55 0.15 0.1
A
Dimensions (mm are the original dimensions)
TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls
A1 A2
0.80
1.00 0.30 0.40 5.5 5.5 0.65 0.70
b DE ee1
4.55
0.90 0.25 0.35 5.4 5.4 0.65
e2 v w
0.08
y y1
0.1
SOT1336-1
C
y1 C y
0 5 mm
scale
X
A
A2
A1
detail X
ball A1
index area
ball A1
index area
A
E
D B
e2
e
A
B
C
D
E
F
G
H
1 3 5 78 246
e1
e Ø v AC B
Ø w C b
1/2 e
1/2 ePN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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29. Abbreviations
30. Glossary
Modulation index — Defined as the voltage ratio (Vmax Vmin) / (Vmax + Vmin).
Load modulation index — Defined as the voltage ratio for the card
(Vmax Vmin) / (Vmax + Vmin) measured at the card’s coil.
Initiator — Generates RF field at 13.56 MHz and starts the NFCIP-1 communication.
Target — Responds to command either using load modulation scheme (RF field
generated by Initiator) or using modulation of self generated RF field (no RF field
generated by initiator).
31. References
[1] Application note — NFC Transmission Module Antenna and RF Design Guide
Table 176. Abbreviations
Acronym Description
ADC Analog-to-Digital Converter
ASK Amplitude Shift keying
BPSK Binary Phase Shift Keying
CRC Cyclic Redundancy Check
CW Continuous Wave
DAC Digital-to-Analog Converter
EOF End of frame
HBM Human Body Model
I
2C Inter-integrated Circuit
LSB Least Significant Bit
MISO Master In Slave Out
MM Machine Model
MOSI Master Out Slave In
MSB Most Significant Bit
NSS Not Slave Select
PCB Printed-Circuit Board
PLL Phase-Locked Loop
PRBS Pseudo-Random Bit Sequence
RX Receiver
SOF Start Of Frame
SPI Serial Peripheral Interface
TX Transmitter
UART Universal Asynchronous Receiver TransmitterPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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32. Revision history
Table 177. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PN512 v.4.5 20131217 Product data sheet - PN512 v.4.4
Modifications: • Typo corrected
PN512 v.4.4 20130730 Product data sheet - PN512 v.4.3
Modifications: • Value added in Table 166 “Limiting values”
• Change of descriptive title
PN512 v.4.3 20130507 Product data sheet - PN512 v.4.2
Modifications: • New type PN5120A0ET/C2 added
• Table 72 “Description of MifNFCReg bits”: description of TxWait updated
• Table 153 “Register and bit settings controlling the signal on pin TX1” and Table 153 “Register
and bit settings controlling the signal on pin TX1”: updated
• Table 166 “Limiting values”: VESD values added
PN512 v.4.2 20120828 Product data sheet - PN512 v.4.1
Modifications: • Table 123 “AutoTestReg register (address 36h); reset value: 40h, 01000000b”: description of
bits 4 and 5 corrected
PN512 v.4.1 20120821 Product data sheet - PN512 v.4.0
Modifications: • Table 124 “Description of bits”: description of bits 4 and 5 corrected
PN512 v.4.0 20120712 Product data sheet - PN512 v.3.9
Modifications: • Section 33.4 “Licenses”: updated
PN512 v.3.9 20120201 Product data sheet - PN512 v.3.8
Modifications: • Adding information on the different version in General description.
• Adding Section 21 “Errata sheet” on page 109 for explanation of differences between 1.0 and
2.0.
• Adding ordering information for version 1.0 and industrial version in Table 2 “Ordering
information” on page 5
• Adding the limitations and characteristics for the industrial version, see Table 1 “Quick
reference data” on page 4, Table 166 “Limiting values” on page 111, Table 1 “Quick reference
data” on page 4
• Referring to the Section 21 “Errata sheet” on page 109 within the following sections: Section
9.2.2.4 “RxModeReg” on page 39, Section 9.2.2.10 “DemodReg” on page 45, Section 9.2.2.15
“TypeBReg” on page 50, Section 9.2.3.10 “TMode Register, TPrescaler Register” on page 57,
Section 9.2.4.7 “AutoTestReg” on page 64, Section 9.2.4.8 “VersionReg” on page 64, Section
9.1.1 “Register bit behavior” on page 23, Section 15 “Timer unit” on page 96, Section 20
“Testsignals” on page 107;
• Update of command ‘Mem’ to ‘Configure’ and ‘RFU’ to ‘Autocoll’ in Table 158 “Command
overview” on page 101.
• Change of ‘Mem’ to ‘Configure’ in ‘Mem’ in Section 19.3.1.2 “Config command” on page 101
• Adding Autocoll in Section 19.3.1.9 “AutoColl” on page 103
PN512 v.3.8 20111025 Product data sheet - PN512 v.3.7
Modifications: • Table 168 “Characteristics”: unit of Pxtal corrected
111310 June 2005 Objective data sheet -
Modifications: • Initial versionPN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet
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33. Legal information
33.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
33.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
33.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification. PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
33.4 Licenses
33.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I
2C-bus — logo is a trademark of NXP B.V.
MIFARE — is a trademark of NXP B.V.
34. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Purchase of NXP ICs with ISO/IEC 14443 type B functionality
This NXP Semiconductors IC is ISO/IEC 14443 Type B
software enabled and is licensed under Innovatron’s
Contactless Card patents license for ISO/IEC 14443 B.
The license includes the right to use the IC in systems
and/or end-user equipment.
RATP/Innovatron
Technology
Purchase of NXP ICs with NFC technology
Purchase of an NXP Semiconductors IC that complies with one of the Near
Field Communication (NFC) standards ISO/IEC 18092 and ISO/IEC 21481
does not convey an implied license under any patent right infringed by
implementation of any of those standards.PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
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Full NFC Forum compliant solution
35. Tables
Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .4
Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .5
Table 3. Pin description HVQFN32 . . . . . . . . . . . . . . . .10
Table 4. Pin description HVQFN40 . . . . . . . . . . . . . . . . 11
Table 5. Pin description TFBGA64 . . . . . . . . . . . . . . . . .12
Table 6. Communication overview for
ISO/IEC 14443 A/MIFARE reader/writer . . . . .14
Table 7. Communication overview for FeliCa
reader/writer . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 8. FeliCa framing and coding . . . . . . . . . . . . . . . .16
Table 9. Start value for the CRC Polynomial: (00h),
(00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 10. Communication overview for Active
communication mode . . . . . . . . . . . . . . . . . . . .18
Table 11. Communication overview for Passive
communication mode . . . . . . . . . . . . . . . . . . . .19
Table 12. Framing and coding overview. . . . . . . . . . . . . .20
Table 13. MIFARE Card operation mode . . . . . . . . . . . . .20
Table 14. FeliCa Card operation mode . . . . . . . . . . . . . .21
Table 15. PN512 registers overview . . . . . . . . . . . . . . . .21
Table 16. Behavior of register bits and its designation. . .23
Table 17. PageReg register (address 00h); reset value:
00h, 0000000b . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 18. Description of PageReg bits . . . . . . . . . . . . . . .24
Table 19. CommandReg register (address 01h); reset
value: 20h, 00100000b . . . . . . . . . . . . . . . . . . .24
Table 20. Description of CommandReg bits. . . . . . . . . . .24
Table 21. CommIEnReg register (address 02h); reset
value: 80h, 10000000b . . . . . . . . . . . . . . . . . . .25
Table 22. Description of CommIEnReg bits . . . . . . . . . . .25
Table 23. DivIEnReg register (address 03h); reset value:
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .26
Table 24. Description of DivIEnReg bits. . . . . . . . . . . . . .26
Table 25. CommIRqReg register (address 04h); reset
value: 14h, 00010100b . . . . . . . . . . . . . . . . . . .27
Table 26. Description of CommIRqReg bits . . . . . . . . . . .27
Table 27. DivIRqReg register (address 05h); reset
value: XXh, 000X00XXb . . . . . . . . . . . . . . . . . .28
Table 28. Description of DivIRqReg bits . . . . . . . . . . . . .28
Table 29. ErrorReg register (address 06h); reset value:
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .29
Table 30. Description of ErrorReg bits . . . . . . . . . . . . . . .29
Table 31. Status1Reg register (address 07h); reset
value: XXh, X100X01Xb . . . . . . . . . . . . . . . . . .30
Table 32. Description of Status1Reg bits . . . . . . . . . . . . .30
Table 33. Status2Reg register (address 08h); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .31
Table 34. Description of Status2Reg bits . . . . . . . . . . . . .31
Table 35. FIFODataReg register (address 09h); reset
value: XXh, XXXXXXXXb . . . . . . . . . . . . . . . . .32
Table 36. Description of FIFODataReg bits . . . . . . . . . . .32
Table 37. FIFOLevelReg register (address 0Ah); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .32
Table 38. Description of FIFOLevelReg bits. . . . . . . . . . .32
Table 39. WaterLevelReg register (address 0Bh); reset
value: 08h, 00001000b . . . . . . . . . . . . . . . . . . .33
Table 40. Description of WaterLevelReg bits. . . . . . . . . . 33
Table 41. ControlReg register (address 0Ch); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 33
Table 42. Description of ControlReg bits . . . . . . . . . . . . 33
Table 43. BitFramingReg register (address 0Dh); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 34
Table 44. Description of BitFramingReg bits . . . . . . . . . . 34
Table 45. CollReg register (address 0Eh); reset
value: XXh, 101XXXXXb . . . . . . . . . . . . . . . . . 35
Table 46. Description of CollReg bits. . . . . . . . . . . . . . . . 35
Table 47. PageReg register (address 10h); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 36
Table 48. Description of PageReg bits . . . . . . . . . . . . . . 36
Table 49. ModeReg register (address 11h); reset value:
3Bh, 00111011b . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 50. Description of ModeReg bits . . . . . . . . . . . . . . 37
Table 51. TxModeReg register (address 12h); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 38
Table 52. Description of TxModeReg bits . . . . . . . . . . . . 38
Table 53. RxModeReg register (address 13h); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 39
Table 54. Description of RxModeReg bits . . . . . . . . . . . . 39
Table 55. TxControlReg register (address 14h); reset
value: 80h, 10000000b . . . . . . . . . . . . . . . . . . 40
Table 56. Description of TxControlReg bits . . . . . . . . . . . 40
Table 57. TxAutoReg register (address 15h); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 41
Table 58. Description of TxAutoReg bits . . . . . . . . . . . . . 41
Table 59. TxSelReg register (address 16h); reset value:
10h, 00010000b. . . . . . . . . . . . . . . . . . . . . . . . 42
Table 60. Description of TxSelReg bits . . . . . . . . . . . . . . 42
Table 61. RxSelReg register (address 17h); reset value:
84h, 10000100b. . . . . . . . . . . . . . . . . . . . . . . . 44
Table 62. Description of RxSelReg bits . . . . . . . . . . . . . . 44
Table 63. RxThresholdReg register (address 18h);
reset value: 84h, 10000100b . . . . . . . . . . . . . . 44
Table 64. Description of RxThresholdReg bits . . . . . . . . 44
Table 65. DemodReg register (address 19h); reset
value: 4Dh, 01001101b . . . . . . . . . . . . . . . . . . 45
Table 66. Description of DemodReg bits . . . . . . . . . . . . . 45
Table 67. FelNFC1Reg register (address 1Ah); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 46
Table 68. Description of FelNFC1Reg bits . . . . . . . . . . . 46
Table 69. FelNFC2Reg register (address1Bh); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 47
Table 70. Description of FelNFC2Reg bits . . . . . . . . . . . 47
Table 71. MifNFCReg register (address 1Ch); reset
value: 62h, 01100010b. . . . . . . . . . . . . . . . . . . 48
Table 72. Description of MifNFCReg bits. . . . . . . . . . . . . 48
Table 73. ManualRCVReg register (address 1Dh);
reset value: 00h, 00000000b . . . . . . . . . . . . . . 49
Table 74. Description of ManualRCVReg bits . . . . . . . . . 49
Table 75. TypeBReg register (address 1Eh); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 50
Table 76. Description of TypeBReg bits. . . . . . . . . . . . . . 50
Table 77. SerialSpeedReg register (address 1Fh); PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet
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Full NFC Forum compliant solution
reset value: EBh, 11101011b . . . . . . . . . . . . . .51
Table 78. Description of SerialSpeedReg bits . . . . . . . . .51
Table 79. PageReg register (address 20h); reset value:
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .52
Table 80. Description of PageReg bits . . . . . . . . . . . . . . .52
Table 81. CRCResultReg register (address 21h); reset
value: FFh, 11111111b. . . . . . . . . . . . . . . . . . . .52
Table 82. Description of CRCResultReg bits . . . . . . . . . .52
Table 83. CRCResultReg register (address 22h); reset
value: FFh, 11111111b. . . . . . . . . . . . . . . . . . . .52
Table 84. Description of CRCResultReg bits . . . . . . . . . .52
Table 85. GsNOffReg register (address 23h); reset
value: 88h, 10001000b . . . . . . . . . . . . . . . . . . .53
Table 86. Description of GsNOffReg bits . . . . . . . . . . . . .53
Table 87. ModWidthReg register (address 24h); reset
value: 26h, 00100110b . . . . . . . . . . . . . . . . . . .54
Table 88. Description of ModWidthReg bits . . . . . . . . . . .54
Table 89. TxBitPhaseReg register (address 25h); reset
value: 87h, 10000111b . . . . . . . . . . . . . . . . . . .54
Table 90. Description of TxBitPhaseReg bits . . . . . . . . . .54
Table 91. RFCfgReg register (address 26h); reset
value: 48h, 01001000b . . . . . . . . . . . . . . . . . . .55
Table 92. Description of RFCfgReg bits . . . . . . . . . . . . .55
Table 93. GsNOnReg register (address 27h); reset
value: 88h, 10001000b . . . . . . . . . . . . . . . . . . .56
Table 94. Description of GsNOnReg bits . . . . . . . . . . . . .56
Table 95. CWGsPReg register (address 28h); reset
value: 20h, 00100000b . . . . . . . . . . . . . . . . . . .56
Table 96. Description of CWGsPReg bits. . . . . . . . . . . . .56
Table 97. ModGsPReg register (address 29h); reset
value: 20h, 00100000b . . . . . . . . . . . . . . . . . . .57
Table 98. Description of ModGsPReg bits . . . . . . . . . . . .57
Table 99. TModeReg register (address 2Ah); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .57
Table 100. Description of TModeReg bits . . . . . . . . . . . . .57
Table 101. TPrescalerReg register (address 2Bh); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .58
Table 102. Description of TPrescalerReg bits . . . . . . . . . .58
Table 103. TReloadReg (Higher bits) register (address
2Ch); reset value: 00h, 00000000b . . . . . . . . .59
Table 104. Description of the higher TReloadReg bits . . .59
Table 105. TReloadReg (Lower bits) register (address
2Dh); reset value: 00h, 00000000b . . . . . . . . .59
Table 106. Description of lower TReloadReg bits . . . . . . .59
Table 107. TCounterValReg (Higher bits) register (address
2Eh); reset value: XXh, XXXXXXXXb . . . . . . .60
Table 108. Description of the higher TCounterValReg bits 60
Table 109. TCounterValReg (Lower bits) register (address
2Fh); reset value: XXh, XXXXXXXXb. . . . . . . .60
Table 110. Description of lower TCounterValReg bits . . . .60
Table 111. PageReg register (address 30h); reset value:
00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . .60
Table 112. Description of PageReg bits. . . . . . . . . . . . . . .61
Table 113. TestSel1Reg register (address 31h); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .62
Table 114. Description of TestSel1Reg bits . . . . . . . . . . . .62
Table 115. TestSel2Reg register (address 32h); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . .62
Table 116. Description of TestSel2Reg bits. . . . . . . . . . . . 62
Table 117. TestPinEnReg register (address 33h); reset
value: 80h, 10000000b . . . . . . . . . . . . . . . . . . 63
Table 118. Description of TestPinEnReg bits . . . . . . . . . . 63
Table 119. TestPinValueReg register (address 34h); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 63
Table 120. Description of TestPinValueReg bits . . . . . . . . 63
Table 121. TestBusReg register (address 35h); reset
value: XXh, XXXXXXXXb . . . . . . . . . . . . . . . . 64
Table 122. Description of TestBusReg bits . . . . . . . . . . . . 64
Table 123. AutoTestReg register (address 36h); reset
value: 40h, 01000000b . . . . . . . . . . . . . . . . . . 64
Table 124. Description of bits . . . . . . . . . . . . . . . . . . . . . . 64
Table 125. VersionReg register (address 37h); reset
value: XXh, XXXXXXXXb . . . . . . . . . . . . . . . . 65
Table 126. Description of VersionReg bits . . . . . . . . . . . . 65
Table 127. AnalogTestReg register (address 38h); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 66
Table 128. Description of AnalogTestReg bits . . . . . . . . . 66
Table 129. TestDAC1Reg register (address 39h); reset
value: XXh, 00XXXXXXb . . . . . . . . . . . . . . . . . 67
Table 130. Description of TestDAC1Reg bits . . . . . . . . . . 67
Table 131. TestDAC2Reg register (address 3Ah); reset
value: XXh, 00XXXXXXb . . . . . . . . . . . . . . . . . 67
Table 132. Description ofTestDAC2Reg bits. . . . . . . . . . . 67
Table 133. TestADCReg register (address 3Bh); reset
value: XXh, XXXXXXXXb . . . . . . . . . . . . . . . . 67
Table 134. Description of TestADCReg bits . . . . . . . . . . . 67
Table 135. RFTReg register (address 3Ch); reset value:
FFh, 11111111b . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 136. Description of RFTReg bits . . . . . . . . . . . . . . . 68
Table 137. RFTReg register (address 3Dh, 3Fh); reset
value: 00h, 00000000b . . . . . . . . . . . . . . . . . . 68
Table 138. Description of RFTReg bits . . . . . . . . . . . . . . . 68
Table 139. RFTReg register (address 3Eh); reset value:
03h, 00000011b . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 140. Description of RFTReg bits . . . . . . . . . . . . . . . 68
Table 141. Connection protocol for detecting different
interface types . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 142. Connection scheme for detecting the different
interface types . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 143. MOSI and MISO byte order . . . . . . . . . . . . . . 70
Table 144. MOSI and MISO byte order . . . . . . . . . . . . . . 71
Table 145. Address byte 0 register; address MOSI . . . . . 71
Table 146. BR_T0 and BR_T1 settings . . . . . . . . . . . . . . 72
Table 147. Selectable UART transfer speeds . . . . . . . . . 72
Table 148. UART framing . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 149. Read data byte order . . . . . . . . . . . . . . . . . . . 73
Table 150. Write data byte order . . . . . . . . . . . . . . . . . . . 73
Table 151. Address byte 0 register; address MOSI . . . . . 75
Table 152. Supported interface types . . . . . . . . . . . . . . . . 82
Table 153. Register and bit settings controlling the
signal on pin TX1 . . . . . . . . . . . . . . . . . . . . . . 84
Table 154. Register and bit settings controlling the
signal on pin TX2 . . . . . . . . . . . . . . . . . . . . . . 85
Table 155. Setting of the bits RFlevel in register
RFCfgReg (RFLevel amplifier deactivated) . . . 86
Table 156. CRC coprocessor parameters . . . . . . . . . . . . 93PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet
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NXP Semiconductors PN512
Full NFC Forum compliant solution
Table 157. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . .95
Table 158. Command overview . . . . . . . . . . . . . . . . . . .101
Table 159. Testsignal routing (TestSel2Reg = 07h) . . . . .107
Table 160. Description of Testsignals . . . . . . . . . . . . . . .107
Table 161. Testsignal routing (TestSel2Reg = 0Dh) . . . .108
Table 162. Description of Testsignals . . . . . . . . . . . . . . .108
Table 163. Testsignal routing (TestSel2Reg = 19h) . . . . .108
Table 164. Description of Testsignals . . . . . . . . . . . . . . .108
Table 165. Testsignals description. . . . . . . . . . . . . . . . . .108
Table 166. Limiting values . . . . . . . . . . . . . . . . . . . . . . . 111
Table 167. Operating conditions . . . . . . . . . . . . . . . . . . . 111
Table 168. Thermal characteristics . . . . . . . . . . . . . . . . . 112
Table 169. Characteristics . . . . . . . . . . . . . . . . . . . . . . . 112
Table 170. SPI timing characteristics . . . . . . . . . . . . . . . 117
Table 171. I2C-bus timing in Fast mode . . . . . . . . . . . . . 117
Table 172. AC symbols . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 173. Timing specification for separated
Read/Write strobe. . . . . . . . . . . . . . . . . . . . . . 119
Table 174. Timing specification for common
Read/Write strobe. . . . . . . . . . . . . . . . . . . . . .120
Table 175. Package information . . . . . . . . . . . . . . . . . . .122
Table 176. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . .126
Table 177. Revision history . . . . . . . . . . . . . . . . . . . . . . .127PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet
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Rev. 4.5 — 17 December 2013
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NXP Semiconductors PN512
Full NFC Forum compliant solution
36. Figures
Fig 1. Simplified block diagram of the PN512 . . . . . . . . .6
Fig 2. Detailed block diagram of the PN512 . . . . . . . . . .7
Fig 3. Pinning configuration HVQFN32 (SOT617-1) . . . .8
Fig 4. Pinning configuration HVQFN40 (SOT618-1) . . . .8
Fig 5. Pin configuration TFBGA64 (SOT1336-1) . . . . . . .9
Fig 6. PN512 Read/Write mode. . . . . . . . . . . . . . . . . . .14
Fig 7. ISO/IEC 14443 A/MIFARE Read/Write mode
communication diagram. . . . . . . . . . . . . . . . . . . .14
Fig 8. Data coding and framing according to
ISO/IEC 14443 A . . . . . . . . . . . . . . . . . . . . . . . . .15
Fig 9. FeliCa reader/writer communication diagram . . .16
Fig 10. NFCIP-1 mode. . . . . . . . . . . . . . . . . . . . . . . . . . .17
Fig 11. Active communication mode . . . . . . . . . . . . . . . .18
Fig 12. Passive communication mode . . . . . . . . . . . . . . .19
Fig 13. SPI connection to host. . . . . . . . . . . . . . . . . . . . .70
Fig 14. UART connection to microcontrollers . . . . . . . . .71
Fig 15. UART read data timing diagram . . . . . . . . . . . . .73
Fig 16. UART write data timing diagram . . . . . . . . . . . . .74
Fig 17. I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . . .75
Fig 18. Bit transfer on the I2C-bus . . . . . . . . . . . . . . . . . .76
Fig 19. START and STOP conditions . . . . . . . . . . . . . . .76
Fig 20. Acknowledge on the I2C-bus . . . . . . . . . . . . . . . .77
Fig 21. Data transfer on the I2C-bus . . . . . . . . . . . . . . . .77
Fig 22. First byte following the START procedure . . . . . .78
Fig 23. Register read and write access . . . . . . . . . . . . . .79
Fig 24. I2C-bus HS mode protocol switch . . . . . . . . . . . .80
Fig 25. I2C-bus HS mode protocol frame. . . . . . . . . . . . .81
Fig 26. Connection to host controller with separated
Read/Write strobes . . . . . . . . . . . . . . . . . . . . . . .83
Fig 27. Connection to host controller with common
Read/Write strobes . . . . . . . . . . . . . . . . . . . . . . .83
Fig 28. Data mode detector . . . . . . . . . . . . . . . . . . . . . . .87
Fig 29. Serial data switch for TX1 and TX2 . . . . . . . . . . .88
Fig 30. Communication flows using the S2C interface. . .89
Fig 31. Signal shape for SIGOUT in FeliCa card SAM
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Fig 32. Signal shape for SIGIN in SAM mode . . . . . . . . .90
Fig 33. Signal shape for SIGOUT in MIFARE Card SAM
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Fig 34. Signal shape for SIGIN in MIFARE Card SAM
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Fig 35. Quartz crystal connection . . . . . . . . . . . . . . . . . .99
Fig 36. Oscillator start-up time. . . . . . . . . . . . . . . . . . . .100
Fig 37. Autocoll Command . . . . . . . . . . . . . . . . . . . . . .104
Fig 38. Typical circuit diagram . . . . . . . . . . . . . . . . . . . . 110
Fig 39. Pin RX input voltage range . . . . . . . . . . . . . . . . 116
Fig 40. Timing diagram for SPI . . . . . . . . . . . . . . . . . . . 118
Fig 41. Timing for Fast and Standard mode devices
on the I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Fig 42. Timing diagram for separated Read/Write
strobe. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
Fig 43. Timing diagram for common Read/Write strobe 121
Fig 44. Package outline package version (HVQFN32) .123
Fig 45. Package outline package version (HVQFN40) .124
Fig 46. Package outline package version (TFBGA64). .125PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 4.5 — 17 December 2013
111345 134 of 136
continued >>
NXP Semiconductors PN512
Full NFC Forum compliant solution
37. Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Different available versions. . . . . . . . . . . . . . . . 1
2 General description . . . . . . . . . . . . . . . . . . . . . . 1
3 Features and benefits . . . . . . . . . . . . . . . . . . . . 3
4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 4
5 Ordering information. . . . . . . . . . . . . . . . . . . . . 5
6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6
7 Pinning information. . . . . . . . . . . . . . . . . . . . . . 8
7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10
8 Functional description . . . . . . . . . . . . . . . . . . 14
8.1 ISO/IEC 14443 A/MIFARE functionality . . . . . 14
8.2 ISO/IEC 14443 B functionality . . . . . . . . . . . . 15
8.3 FeliCa reader/writer functionality . . . . . . . . . . 16
8.3.1 FeliCa framing and coding . . . . . . . . . . . . . . . 16
8.4 NFCIP-1 mode . . . . . . . . . . . . . . . . . . . . . . . . 17
8.4.1 Active communication mode . . . . . . . . . . . . . 18
8.4.2 Passive communication mode . . . . . . . . . . . . 19
8.4.3 NFCIP-1 framing and coding . . . . . . . . . . . . . 20
8.4.4 NFCIP-1 protocol support. . . . . . . . . . . . . . . . 20
8.4.5 MIFARE Card operation mode . . . . . . . . . . . . 20
8.4.6 FeliCa Card operation mode . . . . . . . . . . . . . 21
9 PN512 register SET . . . . . . . . . . . . . . . . . . . . . 21
9.1 PN512 registers overview. . . . . . . . . . . . . . . . 21
9.1.1 Register bit behavior. . . . . . . . . . . . . . . . . . . . 23
9.2 Register description . . . . . . . . . . . . . . . . . . . . 24
9.2.1 Page 0: Command and status . . . . . . . . . . . . 24
9.2.1.1 PageReg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.2.1.2 CommandReg . . . . . . . . . . . . . . . . . . . . . . . . 24
9.2.1.3 CommIEnReg . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.2.1.4 DivIEnReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9.2.1.5 CommIRqReg. . . . . . . . . . . . . . . . . . . . . . . . . 27
9.2.1.6 DivIRqReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.2.1.7 ErrorReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9.2.1.8 Status1Reg . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.2.1.9 Status2Reg . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.2.1.10 FIFODataReg . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.2.1.11 FIFOLevelReg . . . . . . . . . . . . . . . . . . . . . . . . 32
9.2.1.12 WaterLevelReg. . . . . . . . . . . . . . . . . . . . . . . . 33
9.2.1.13 ControlReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.2.1.14 BitFramingReg . . . . . . . . . . . . . . . . . . . . . . . . 34
9.2.1.15 CollReg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.2.2 Page 1: Communication . . . . . . . . . . . . . . . . . 36
9.2.2.1 PageReg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.2.2.2 ModeReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.2.2.3 TxModeReg . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.2.2.4 RxModeReg . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.2.2.5 TxControlReg. . . . . . . . . . . . . . . . . . . . . . . . . 40
9.2.2.6 TxAutoReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.2.2.7 TxSelReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
9.2.2.8 RxSelReg. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.2.2.9 RxThresholdReg . . . . . . . . . . . . . . . . . . . . . . 44
9.2.2.10 DemodReg. . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.2.2.11 FelNFC1Reg . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.2.2.12 FelNFC2Reg . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.2.2.13 MifNFCReg . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.2.2.14 ManualRCVReg . . . . . . . . . . . . . . . . . . . . . . . 49
9.2.2.15 TypeBReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.2.2.16 SerialSpeedReg. . . . . . . . . . . . . . . . . . . . . . . 50
9.2.3 Page 2: Configuration . . . . . . . . . . . . . . . . . . 52
9.2.3.1 PageReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.2.3.2 CRCResultReg . . . . . . . . . . . . . . . . . . . . . . . 52
9.2.3.3 GsNOffReg . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.2.3.4 ModWidthReg . . . . . . . . . . . . . . . . . . . . . . . . 54
9.2.3.5 TxBitPhaseReg . . . . . . . . . . . . . . . . . . . . . . . 54
9.2.3.6 RFCfgReg . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.2.3.7 GsNOnReg . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.2.3.8 CWGsPReg . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.2.3.9 ModGsPReg . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.2.3.10 TMode Register, TPrescaler Register . . . . . . 57
9.2.3.11 TReloadReg. . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.2.3.12 TCounterValReg . . . . . . . . . . . . . . . . . . . . . . 60
9.2.4 Page 3: Test . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.2.4.1 PageReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.2.4.2 TestSel1Reg. . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.2.4.3 TestSel2Reg. . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.2.4.4 TestPinEnReg . . . . . . . . . . . . . . . . . . . . . . . . 63
9.2.4.5 TestPinValueReg . . . . . . . . . . . . . . . . . . . . . . 63
9.2.4.6 TestBusReg . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.2.4.7 AutoTestReg . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.2.4.8 VersionReg . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.2.4.9 AnalogTestReg. . . . . . . . . . . . . . . . . . . . . . . . 66
9.2.4.10 TestDAC1Reg . . . . . . . . . . . . . . . . . . . . . . . . 67
9.2.4.11 TestDAC2Reg . . . . . . . . . . . . . . . . . . . . . . . . 67
9.2.4.12 TestADCReg . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.2.4.13 RFTReg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
10 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . 68
10.1 Automatic microcontroller interface detection 68
10.2 Serial Peripheral Interface . . . . . . . . . . . . . . . 70
10.2.1 SPI read data . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.2.2 SPI write data. . . . . . . . . . . . . . . . . . . . . . . . . 70
10.2.3 SPI address byte . . . . . . . . . . . . . . . . . . . . . . 71
10.3 UART interface . . . . . . . . . . . . . . . . . . . . . . . 71
10.3.1 Connection to a host . . . . . . . . . . . . . . . . . . . 71PN512 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 4.5 — 17 December 2013
111345 135 of 136
continued >>
NXP Semiconductors PN512
Full NFC Forum compliant solution
10.3.2 Selectable UART transfer speeds . . . . . . . . . 71
10.3.3 UART framing. . . . . . . . . . . . . . . . . . . . . . . . . 72
10.4 I2C Bus Interface . . . . . . . . . . . . . . . . . . . . . . 75
10.4.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10.4.2 START and STOP conditions . . . . . . . . . . . . . 76
10.4.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10.4.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 77
10.4.5 7-Bit addressing . . . . . . . . . . . . . . . . . . . . . . . 78
10.4.6 Register write access . . . . . . . . . . . . . . . . . . . 78
10.4.7 Register read access . . . . . . . . . . . . . . . . . . . 79
10.4.8 High-speed mode . . . . . . . . . . . . . . . . . . . . . . 80
10.4.9 High-speed transfer . . . . . . . . . . . . . . . . . . . . 80
10.4.10 Serial data transfer format in HS mode . . . . . 80
10.4.11 Switching between F/S mode and HS mode . 82
10.4.12 PN512 at lower speed modes . . . . . . . . . . . . 82
11 8-bit parallel interface . . . . . . . . . . . . . . . . . . . 82
11.1 Overview of supported host controller
interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.2 Separated Read/Write strobe . . . . . . . . . . . . . 83
11.3 Common Read/Write strobe . . . . . . . . . . . . . . 83
12 Analog interface and contactless UART . . . . 84
12.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
12.2 TX driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
12.3 RF level detector . . . . . . . . . . . . . . . . . . . . . . 85
12.4 Data mode detector . . . . . . . . . . . . . . . . . . . . 86
12.5 Serial data switch . . . . . . . . . . . . . . . . . . . . . . 88
12.6 S2C interface support . . . . . . . . . . . . . . . . . . . 88
12.6.1 Signal shape for Felica S2C interface support 90
12.6.2 Waveform shape for ISO/IEC 14443A and
MIFARE S2C support . . . . . . . . . . . . . . . . . . . 91
12.7 Hardware support for FeliCa and NFC polling 92
12.7.1 Polling sequence functionality for initiator. . . . 92
12.7.2 Polling sequence functionality for target. . . . . 92
12.7.3 Additional hardware support for FeliCa and
NFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.7.4 CRC coprocessor . . . . . . . . . . . . . . . . . . . . . . 93
13 FIFO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
13.1 Accessing the FIFO buffer . . . . . . . . . . . . . . . 94
13.2 Controlling the FIFO buffer . . . . . . . . . . . . . . . 94
13.3 FIFO buffer status information . . . . . . . . . . . . 94
14 Interrupt request system. . . . . . . . . . . . . . . . . 95
14.1 Interrupt sources overview . . . . . . . . . . . . . . . 95
15 Timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
16 Power reduction modes . . . . . . . . . . . . . . . . . 98
16.1 Hard power-down . . . . . . . . . . . . . . . . . . . . . . 98
16.2 Soft power-down mode. . . . . . . . . . . . . . . . . . 98
16.3 Transmitter power-down mode . . . . . . . . . . . . 98
17 Oscillator circuitry . . . . . . . . . . . . . . . . . . . . . . 99
18 Reset and oscillator start-up time . . . . . . . . . 99
18.1 Reset timing requirements . . . . . . . . . . . . . . . 99
18.2 Oscillator start-up time . . . . . . . . . . . . . . . . . . 99
19 PN512 command set . . . . . . . . . . . . . . . . . . . 100
19.1 General description . . . . . . . . . . . . . . . . . . . 100
19.2 General behavior . . . . . . . . . . . . . . . . . . . . . 100
19.3 PN512 command overview . . . . . . . . . . . . . 101
19.3.1 PN512 command descriptions . . . . . . . . . . . 101
19.3.1.1 Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
19.3.1.2 Config command . . . . . . . . . . . . . . . . . . . . . 101
19.3.1.3 Generate RandomID . . . . . . . . . . . . . . . . . . 102
19.3.1.4 CalcCRC . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
19.3.1.5 Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
19.3.1.6 NoCmdChange . . . . . . . . . . . . . . . . . . . . . . 102
19.3.1.7 Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
19.3.1.8 Transceive . . . . . . . . . . . . . . . . . . . . . . . . . . 103
19.3.1.9 AutoColl . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
19.3.1.10 MFAuthent . . . . . . . . . . . . . . . . . . . . . . . . . . 105
19.3.1.11 SoftReset . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
20 Testsignals. . . . . . . . . . . . . . . . . . . . . . . . . . . 107
20.1 Selftest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
20.2 Testbus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
20.3 Testsignals at pin AUX . . . . . . . . . . . . . . . . . 108
20.4 PRBS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
21 Errata sheet . . . . . . . . . . . . . . . . . . . . . . . . . . 109
22 Application design-in information. . . . . . . . . 110
23 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 111
24 Recommended operating conditions . . . . . . 111
25 Thermal characteristics . . . . . . . . . . . . . . . . . 112
26 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 112
26.1 Timing characteristics . . . . . . . . . . . . . . . . . . 117
26.2 8-bit parallel interface timing . . . . . . . . . . . . . 119
26.2.1 AC symbols . . . . . . . . . . . . . . . . . . . . . . . . . . 119
26.2.2 AC operating specification . . . . . . . . . . . . . . . 119
26.2.2.1 Bus timing for separated Read/Write strobe . 119
26.2.2.2 Bus timing for common Read/Write strobe . 120
27 Package information. . . . . . . . . . . . . . . . . . . 122
28 Package outline. . . . . . . . . . . . . . . . . . . . . . . 123
29 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 126
30 Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
31 References. . . . . . . . . . . . . . . . . . . . . . . . . . . 126
32 Revision history . . . . . . . . . . . . . . . . . . . . . . 127
33 Legal information . . . . . . . . . . . . . . . . . . . . . 128
33.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . 128
33.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 128
33.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . 128
33.4 Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
33.5 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 129NXP Semiconductors PN512
Full NFC Forum compliant solution
© NXP B.V. 2013. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 17 December 2013
111345
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
34 Contact information. . . . . . . . . . . . . . . . . . . . 129
35 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
36 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
37 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
1. Product profile
1.1 General description
Unidirectional double ElectroStatic Discharge (ESD) protection diodes in a common
cathode configuration, encapsulated in a SOT23 (TO-236AB) small Surface-Mounted
Device (SMD) plastic package. The devices are designed for ESD and transient
overvoltage protection of up to two signal lines.
[1] All types available as /DG halogen-free version.
1.2 Features
1.3 Applications
MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage
suppression
Rev. 01 — 3 September 2008 Product data sheet
Table 1. Product overview
Type number[1] Package Configuration
NXP JEDEC
MMBZ12VDL SOT23 TO-236AB dual common cathode
MMBZ15VDL
MMBZ18VCL
MMBZ20VCL
MMBZ27VCL
MMBZ33VCL
■ Unidirectional ESD protection of
two lines
■ ESD protection up to 30 kV (contact
discharge)
■ Bidirectional ESD protection of one line ■ IEC 61000-4-2; level 4 (ESD)
■ Low diode capacitance: Cd ≤ 140 pF ■ IEC 61643-321
■ Rated peak pulse power: PPPM ≤ 40 W ■ AEC-Q101 qualified
■ Ultra low leakage current: IRM ≤ 5 nA
■ Computers and peripherals ■ Automotive electronic control units
■ Audio and video equipment ■ Portable electronics
■ Cellular handsets and accessoriesMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 3 September 2008 2 of 15
NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
1.4 Quick reference data
2. Pinning information
Table 2. Quick reference data
Tamb = 25 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Per diode
VRWM reverse standoff voltage
MMBZ12VDL
MMBZ12VDL/DG
- - 8.5 V
MMBZ15VDL
MMBZ15VDL/DG
- - 12.8 V
MMBZ18VCL
MMBZ18VCL/DG
- - 14.5 V
MMBZ20VCL
MMBZ20VCL/DG
- - 17 V
MMBZ27VCL
MMBZ27VCL/DG
- - 22 V
MMBZ33VCL
MMBZ33VCL/DG
- - 26 V
Cd diode capacitance f = 1 MHz; VR =0V
MMBZ12VDL
MMBZ12VDL/DG
- 110 140 pF
MMBZ15VDL
MMBZ15VDL/DG
- 85 105 pF
MMBZ18VCL
MMBZ18VCL/DG
- 70 90 pF
MMBZ20VCL
MMBZ20VCL/DG
- 65 80 pF
MMBZ27VCL
MMBZ27VCL/DG
- 48 60 pF
MMBZ33VCL
MMBZ33VCL/DG
- 45 55 pF
Table 3. Pinning
Pin Description Simplified outline Graphic symbol
1 anode (diode 1)
2 anode (diode 2)
3 common cathode
1 2
3
006aaa150
1 2
3MMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 3 September 2008 3 of 15
NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
3. Ordering information
4. Marking
[1] * = -: made in Hong Kong
* = p: made in Hong Kong
* = t: made in Malaysia
* = W: made in China
Table 4. Ordering information
Type number Package
Name Description Version
MMBZ12VDL - plastic surface-mounted package; 3 leads SOT23
MMBZ15VDL
MMBZ18VCL
MMBZ20VCL
MMBZ27VCL
MMBZ33VCL
MMBZ12VDL/DG - plastic surface-mounted package; 3 leads SOT23
MMBZ15VDL/DG
MMBZ18VCL/DG
MMBZ20VCL/DG
MMBZ27VCL/DG
MMBZ33VCL/DG
Table 5. Marking codes
Type number Marking code[1] Type number Marking code[1]
MMBZ12VDL *MA MMBZ12VDL/DG TJ*
MMBZ15VDL *MB MMBZ15VDL/DG TL*
MMBZ18VCL *MC MMBZ18VCL/DG TN*
MMBZ20VCL *MD MMBZ20VCL/DG TQ*
MMBZ27VCL *ME MMBZ27VCL/DG TS*
MMBZ33VCL *MF MMBZ33VCL/DG TU*MMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 3 September 2008 4 of 15
NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
5. Limiting values
[1] In accordance with IEC 61643-321 (10/1000 µs current waveform).
[2] Measured from pin 1 or 2 to pin 3.
[3] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard
footprint.
[4] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for cathode 1 cm2.
[1] Device stressed with ten non-repetitive ESD pulses.
[2] Measured from pin 1 or 2 to pin 3.
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Per diode
PPPM rated peak pulse power tp = 10/1000 µs [1][2] - 40 W
IPPM rated peak pulse current tp = 10/1000 µs [1][2]
MMBZ12VDL
MMBZ12VDL/DG
- 2.35 A
MMBZ15VDL
MMBZ15VDL/DG
- 1.9 A
MMBZ18VCL
MMBZ18VCL/DG
- 1.6 A
MMBZ20VCL
MMBZ20VCL/DG
- 1.4 A
MMBZ27VCL
MMBZ27VCL/DG
- 1A
MMBZ33VCL
MMBZ33VCL/DG
- 0.87 A
Per device
Ptot total power dissipation Tamb ≤ 25 °C [3] - 350 mW
[4] - 440 mW
Tj junction temperature - 150 °C
Tamb ambient temperature −55 +150 °C
Tstg storage temperature −65 +150 °C
Table 7. ESD maximum ratings
Tamb = 25 °C unless otherwise specified.
Symbol Parameter Conditions Min Max Unit
Per diode
VESD electrostatic discharge voltage [1][2]
IEC 61000-4-2
(contact discharge)
- 30 kV
machine model - 2 kVMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 3 September 2008 5 of 15
NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
6. Thermal characteristics
[1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[2] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for cathode 1 cm2.
[3] Soldering point at pin 3.
Table 8. ESD standards compliance
Standard Conditions
Per diode
IEC 61000-4-2; level 4 (ESD) > 15 kV (air); > 8 kV (contact)
MIL-STD-883; class 3 (human body model) > 8 kV
Fig 1. 10/1000 µs pulse waveform according to
IEC 61643-321
Fig 2. ESD pulse waveform according to
IEC 61000-4-2
tp (ms)
0 4.0 1.0 2.0 3.0
006aab319
50
100
150
IPP
(%)
0
50 % IPP; 1000 µs
100 % IPP; 10 µs
001aaa631
IPP
100 %
90 %
t
30 ns
60 ns
10 %
tr = 0.7 ns to 1 ns
Table 9. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Per device
Rth(j-a) thermal resistance from junction
to ambient
in free air [1] - - 350 K/W
[2] - - 280 K/W
Rth(j-sp) thermal resistance from junction
to solder point
[3] - - 60 K/WMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 3 September 2008 6 of 15
NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
7. Characteristics
Table 10. Characteristics
Tamb = 25 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Per diode
VF forward voltage
MMBZ12VDL
MMBZ12VDL/DG
IF = 10 mA - - 0.9 V
MMBZ15VDL
MMBZ15VDL/DG
IF = 10 mA - - 0.9 V
MMBZ18VCL
MMBZ18VCL/DG
IF = 10 mA - - 0.9 V
MMBZ20VCL
MMBZ20VCL/DG
IF = 10 mA - - 0.9 V
MMBZ27VCL
MMBZ27VCL/DG
IF = 200 mA - - 1.1 V
MMBZ33VCL
MMBZ33VCL/DG
IF = 10 mA - - 0.9 V
VRWM reverse standoff
voltage
MMBZ12VDL
MMBZ12VDL/DG
- - 8.5 V
MMBZ15VDL
MMBZ15VDL/DG
- - 12.8 V
MMBZ18VCL
MMBZ18VCL/DG
- - 14.5 V
MMBZ20VCL
MMBZ20VCL/DG
- - 17 V
MMBZ27VCL
MMBZ27VCL/DG
- - 22 V
MMBZ33VCL
MMBZ33VCL/DG
- - 26 V
IRM reverse leakage current
MMBZ12VDL
MMBZ12VDL/DG
VRWM = 8.5 V - 0.1 5 nA
MMBZ15VDL
MMBZ15VDL/DG
VRWM = 12.8 V - 0.1 5 nA
MMBZ18VCL
MMBZ18VCL/DG
VRWM = 14.5 V - 0.1 5 nA
MMBZ20VCL
MMBZ20VCL/DG
VRWM = 17 V - 0.1 5 nA
MMBZ27VCL
MMBZ27VCL/DG
VRWM = 22 V - 0.1 5 nA
MMBZ33VCL
MMBZ33VCL/DG
VRWM = 26 V - 0.1 5 nAMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 3 September 2008 7 of 15
NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
VBR breakdown voltage IR = 1 mA
MMBZ12VDL
MMBZ12VDL/DG
11.4 12 12.6 V
MMBZ15VDL
MMBZ15VDL/DG
14.3 15 15.8 V
MMBZ18VCL
MMBZ18VCL/DG
17.1 18 18.9 V
MMBZ20VCL
MMBZ20VCL/DG
19 20 21 V
MMBZ27VCL
MMBZ27VCL/DG
25.65 27 28.35 V
MMBZ33VCL
MMBZ33VCL/DG
31.35 33 34.65 V
Cd diode capacitance f = 1 MHz; VR =0V
MMBZ12VDL
MMBZ12VDL/DG
- 110 140 pF
MMBZ15VDL
MMBZ15VDL/DG
- 85 105 pF
MMBZ18VCL
MMBZ18VCL/DG
- 70 90 pF
MMBZ20VCL
MMBZ20VCL/DG
- 65 80 pF
MMBZ27VCL
MMBZ27VCL/DG
- 48 60 pF
MMBZ33VCL
MMBZ33VCL/DG
- 45 55 pF
VCL clamping voltage [1][2]
MMBZ12VDL
MMBZ12VDL/DG
IPPM = 2.35 A - - 17 V
MMBZ15VDL
MMBZ15VDL/DG
IPPM = 1.9 A - - 21.2 V
MMBZ18VCL
MMBZ18VCL/DG
IPPM = 1.6 A - - 25 V
MMBZ20VCL
MMBZ20VCL/DG
IPPM = 1.4 A - - 28 V
MMBZ27VCL
MMBZ27VCL/DG
IPPM = 1 A - - 38 V
MMBZ33VCL
MMBZ33VCL/DG
IPPM = 0.87 A - - 46 V
Table 10. Characteristics …continued
Tamb = 25 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max UnitMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 3 September 2008 8 of 15
NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
[1] In accordance with IEC 61643-321 (10/1000 µs current waveform).
[2] Measured from pin 1 or 2 to pin 3.
SZ temperature coefficient IZ = 1 mA
MMBZ12VDL
MMBZ12VDL/DG
- 8.1 - mV/K
MMBZ15VDL
MMBZ15VDL/DG
- 11 - mV/K
MMBZ18VCL
MMBZ18VCL/DG
- 14 - mV/K
MMBZ20VCL
MMBZ20VCL/DG
- 15.8 - mV/K
MMBZ27VCL
MMBZ27VCL/DG
- 23 - mV/K
MMBZ33VCL
MMBZ33VCL/DG
- 29.4 - mV/K
Table 10. Characteristics …continued
Tamb = 25 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
MMBZ27VCL: unidirectional and bidirectional
Tamb = 25 °C
Fig 3. Rated peak pulse power as a function of
exponential pulse duration (rectangular
waveform); typical values
Fig 4. Relative variation of rated peak pulse power as
a function of junction temperature; typical
values
006aab327
102
10
103
PPPM
(W)
1
tp (ms)
10−2 103 102 10−1 1 10
Tj
(°C)
0 200 50 100 150
006aab321
0.4
0.8
1.2
PPPM
0
PPPM(25°C)MMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 3 September 2008 9 of 15
NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
f = 1 MHz; Tamb = 25 °C
(1) MMBZ15VDL: unidirectional
(2) MMBZ15VDL: bidirectional
(3) MMBZ27VCL: unidirectional
(4) MMBZ27VCL: bidirectional
MMBZ27VCL: VRWM = 22 V
Fig 5. Diode capacitance as a function of reverse
voltage; typical values
Fig 6. Reverse leakage current as a function of
junction temperature; typical values
Fig 7. V-I characteristics for a unidirectional
ESD protection diode
Fig 8. V-I characteristics for a bidirectional
ESD protection diode
VR (V)
0 25 5 10 15 20
006aab328
40
60
20
80
100
Cd
(pF)
0
(1)
(2)
(3)
(4)
006aab329
10−1
10−2
10
1
102
IRM
(nA)
10−3
Tamb (°C)
−75 175 −25 25 75 125
006aab324
−VCL −VBR −VRWM
−IRM
−IR
−IPP
V
I
P-N
− +
−IPPM 006aab325
−VCL −VBR −VRWM
−IRM VRWM VBR VCL
IRM
−IR
IR
−IPP
IPP
− +
IPPM
−IPPMMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 3 September 2008 10 of 15
NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
8. Application information
The MMBZxVCL series and the MMBZxVDL series are designed for the protection of up
to two unidirectional data or signal lines from the damage caused by ESD and surge
pulses. The devices may be used on lines where the signal polarities are either positive or
negative with respect to ground. The devices provide a surge capability of 40 W per line
for a 10/1000 µs waveform.
Circuit board layout and protection device placement
Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT)
and surge transients. The following guidelines are recommended:
1. Place the devices as close to the input terminal or connector as possible.
2. The path length between the device and the protected line should be minimized.
3. Keep parallel signal paths to a minimum.
4. Avoid running protected conductors in parallel with unprotected conductors.
5. Minimize all Printed-Circuit Board (PCB) conductive loops including power and
ground loops.
6. Minimize the length of the transient return path to ground.
7. Avoid using shared transient return paths to a common ground point.
8. Ground planes should be used whenever possible. For multilayer PCBs, use ground
vias.
9. Test information
9.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is
suitable for use in automotive applications.
Fig 9. Typical application: ESD and transient voltage protection of data lines
006aab330
MMBZxVCL/VDL
line 1 to be protected
unidirectional protection of two lines bidirectional protection of one line
line 2 to be protected
GND
MMBZxVCL/VDL
line 1 to be protected
GNDMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 3 September 2008 11 of 15
NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
10. Package outline
11. Packing information
[1] For further information and the availability of packing methods, see Section 15.
Fig 10. Package outline SOT23 (TO-236AB)
Dimensions in mm 04-11-04
0.45
0.15
1.9
1.1
0.9
3.0
2.8
2.5
2.1
1.4
1.2
0.48
0.38
0.15
0.09
1 2
3
Table 11. Packing methods
The indicated -xxx are the last three digits of the 12NC ordering code.[1]
Type number Package Description Packing quantity
3000 10000
MMBZ12VDL SOT23 4 mm pitch, 8 mm tape and reel -215 -235
MMBZ15VDL
MMBZ18VCL
MMBZ20VCL
MMBZ27VCL
MMBZ33VCL
MMBZ12VDL/DG SOT23 4 mm pitch, 8 mm tape and reel -215 -235
MMBZ15VDL/DG
MMBZ18VCL/DG
MMBZ20VCL/DG
MMBZ27VCL/DG
MMBZ33VCL/DGMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 3 September 2008 12 of 15
NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
12. Soldering
Fig 11. Reflow soldering footprint SOT23 (TO-236AB)
Fig 12. Wave soldering footprint SOT23 (TO-236AB)
solder lands
solder resist
occupied area
solder paste
sot023_fr
0.5
(3×)
0.6
(3×)
0.6
(3×)
0.7
(3×)
3
1
3.3
2.9
1.7
1.9
2
Dimensions in mm
solder lands
solder resist
occupied area
preferred transport direction during soldering
sot023_fw
2.8
4.5
1.4
4.6
1.4
(2×)
1.2
(2×)
2.2
2.6
Dimensions in mmMMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 3 September 2008 13 of 15
NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
13. Revision history
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
MMBZXVCL_MMBZXVDL_SER_1 20080903 Product data sheet - -MMBZXVCL_MMBZXVDL_SER_1 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 01 — 3 September 2008 14 of 15
NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
14. Legal information
14.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
14.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
ESD protection devices — These products are only intended for protection
against ElectroStatic Discharge (ESD) pulses and are not intended for any
other usage including, without limitation, voltage regulation applications. NXP
Semiconductors accepts no liability for use in such applications and therefore
such use is at the customer’s own risk.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.NXP Semiconductors MMBZxVCL; MMBZxVDL series
Double ESD protection diodes for transient overvoltage suppression
© NXP B.V. 2008. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 3 September 2008
Document identifier: MMBZXVCL_MMBZXVDL_SER_1
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
16. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description. . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 2
2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3
4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Thermal characteristics. . . . . . . . . . . . . . . . . . . 5
7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 Application information. . . . . . . . . . . . . . . . . . 10
9 Test information . . . . . . . . . . . . . . . . . . . . . . . . 10
9.1 Quality information . . . . . . . . . . . . . . . . . . . . . 10
10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
11 Packing information. . . . . . . . . . . . . . . . . . . . . 11
12 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
13 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
14.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
14.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
14.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15 Contact information. . . . . . . . . . . . . . . . . . . . . 14
16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1. Product profile
1.1 General description
The devices are 4-, 6- and 8-channel RC low-pass filter arrays which are designed to
provide filtering of undesired RF signals on the I/O ports of portable communication or
computing devices. In addition, the devices incorporate diodes to provide protection to
downstream components from ElectroStatic Discharge (ESD) voltages as high as ±30 kV.
The devices are fabricated using monolithic silicon technology and integrate up to eight
resistors and sixteen diodes in a 0.4 mm pitch 8-, 12- or 16-pin ultra-thin leadless Quad
Flat No-leads (QFN) plastic package with a height of 0.55 mm only.
1.2 Features and benefits
Pb-free, Restriction of Hazardous Substances (RoHS) compliant and free of halogen
and antimony (Dark Green compliant)
4-, 6- and 8-channel integrated π-type RC filter network
ESD protection to ±30 kV contact discharge according to IEC 61000-4-2 far exceeding
level 4
QFN plastic package with 0.4 mm pitch and 0.55 mm height
1.3 Applications
General-purpose ElectroMagnetic Interference (EMI) and Radio-Frequency
Interference (RFI) filtering and downstream ESD protection for:
Cellular phone and Personal Communication System (PCS) mobile handsets
Cordless telephones
Wireless data (WAN/LAN) systems
Mobile Internet Devices (MID)
Portable Media Players (PMP)
IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
with ESD protection
Rev. 2 — 5 May 2011 Product data sheetIP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 2 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
1.4 Quick reference data
[1] For the total channel.
2. Pinning information
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
IP4251CZ8-4-TTL; IP4251CZ12-6-TTL; IP4251CZ16-8-TTL
Cch channel capacitance f = 100 kHz;
Vbias(DC) = 2.5 V
[1] - 10 - pF
Rs(ch) channel series resistance 80 100 120 Ω
IP4252CZ8-4-TTL; IP4252CZ12-6-TTL; IP4252CZ16-8-TTL
Cch channel capacitance f = 100 kHz;
Vbias(DC) = 2.5 V
[1] - 12 - pF
Rs(ch) channel series resistance 32 40 48 Ω
IP4253CZ8-4-TTL; IP4253CZ12-6-TTL; IP4253CZ16-8-TTL
Cch channel capacitance f = 100 kHz;
Vbias(DC) = 2.5 V
[1] - 30 - pF
Rs(ch) channel series resistance 160 200 240 Ω
IP4254CZ8-4-TTL; IP4254CZ12-6-TTL; IP4254CZ16-8-TTL
Cch channel capacitance f = 100 kHz;
Vbias(DC) = 2.5 V
[1] - 30 - pF
Rs(ch) channel series resistance 80 100 120 Ω
Table 2. Pinning
Pin Description Simplified outline Graphic symbol
IP4251CZ8-4-TTL; IP4252CZ8-4-TTL; IP4253CZ8-4-TTL; IP4254CZ8-4-TTL (SOT1166-1)
1 and 8 filter channel 1
2 and 7 filter channel 2
3 and 6 filter channel 3
4 and 5 filter channel 4
ground pad ground
IP4251CZ12-6-TTL; IP4252CZ12-6-TTL; IP4253CZ12-6-TTL; IP4254CZ12-6-TTL (SOT1167-1)
1 and 12 filter channel 1
2 and 11 filter channel 2
3 and 10 filter channel 3
4 and 9 filter channel 4
5 and 8 filter channel 5
6 and 7 filter channel 6
ground pad ground
Transparent
top view
8
1
5
4
018aaa071
Rs(ch)
Cch
1 to 4 5 to 8
GND
2
Cch
2
Transparent
top view
12
1
7
6
018aaa072
Rs(ch)
1 to 6 7 to 12
GND
Cch
2
Cch
2IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 3 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
3. Ordering information
IP4251CZ16-8-TTL; IP4252CZ16-8-TTL; IP4253CZ16-8-TTL; IP4254CZ16-8-TTL (SOT1168-1)
1 and 16 filter channel 1
2 and 15 filter channel 2
3 and 14 filter channel 3
4 and 13 filter channel 4
5 and 12 filter channel 5
6 and 11 filter channel 6
7 and 10 filter channel 7
8 and 9 filter channel 8
ground pad ground
Table 2. Pinning …continued
Pin Description Simplified outline Graphic symbol
Transparent
top view
16
1
9
8
018aaa073
Rs(ch)
1 to 8 9 to 16
GND
Cch
2
Cch
2
Table 3. Ordering information
Type number Package
Name Description Version
IP4251CZ8-4-TTL HUSON8 plastic, thermal enhanced ultra thin small outline package; no leads;
8 terminals; body 1.35 × 1.7 × 0.55 mm
SOT1166-1
IP4251CZ12-6-TTL HUSON12 plastic, thermal enhanced ultra thin small outline package; no leads;
12 terminals; body 1.35 × 2.5 × 0.55 mm
SOT1167-1
IP4251CZ16-8-TTL HUSON16 plastic, thermal enhanced ultra thin small outline package; no leads;
16 terminals; body 1.35 × 3.3 × 0.55 mm
SOT1168-1
IP4252CZ8-4-TTL HUSON8 plastic, thermal enhanced ultra thin small outline package; no leads;
8 terminals; body 1.35 × 1.7 × 0.55 mm
SOT1166-1
IP4252CZ12-6-TTL HUSON12 plastic, thermal enhanced ultra thin small outline package; no leads;
12 terminals; body 1.35 × 2.5 × 0.55 mm
SOT1167-1
IP4252CZ16-8-TTL HUSON16 plastic, thermal enhanced ultra thin small outline package; no leads;
16 terminals; body 1.35 × 3.3 × 0.55 mm
SOT1168-1
IP4253CZ8-4-TTL HUSON8 plastic, thermal enhanced ultra thin small outline package; no leads;
8 terminals; body 1.35 × 1.7 × 0.55 mm
SOT1166-1
IP4253CZ12-6-TTL HUSON12 plastic, thermal enhanced ultra thin small outline package; no leads;
12 terminals; body 1.35 × 2.5 × 0.55 mm
SOT1167-1
IP4253CZ16-8-TTL HUSON16 plastic, thermal enhanced ultra thin small outline package; no leads;
16 terminals; body 1.35 × 3.3 × 0.55 mm
SOT1168-1
IP4254CZ8-4-TTL HUSON8 plastic, thermal enhanced ultra thin small outline package; no leads;
8 terminals; body 1.35 × 1.7 × 0.55 mm
SOT1166-1
IP4254CZ12-6-TTL HUSON12 plastic, thermal enhanced ultra thin small outline package; no leads;
12 terminals; body 1.35 × 2.5 × 0.55 mm
SOT1167-1
IP4254CZ16-8-TTL HUSON16 plastic, thermal enhanced ultra thin small outline package; no leads;
16 terminals; body 1.35 × 3.3 × 0.55 mm
SOT1168-1IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 4 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
4. Limiting values
[1] Device tested with 1000 pulses of ±15 kV contact discharges, according to the IEC 61000-4-2 model,
far exceeding IEC 61000-4-2 level 4 (8 kV contact discharge).
[2] Device tested with 1000 pulses of ±30 kV contact discharges, according to the IEC 61000-4-2 model,
far exceeding IEC 61000-4-2 level 4 (8 kV contact discharge).
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
IP4251CZ8-4-TTL; IP4251CZ12-6-TTL; IP4251CZ16-8-TTL
VESD electrostatic discharge
voltage
all pins to ground;
contact discharge
[1] - ±15 kV
IP4252CZ8-4-TTL; IP4252CZ12-6-TTL; IP4252CZ16-8-TTL
VESD electrostatic discharge
voltage
all pins to ground;
contact discharge
[1] - ±15 kV
IP4253CZ8-4-TTL; IP4253CZ12-6-TTL; IP4253CZ16-8-TTL
VESD electrostatic discharge
voltage
all pins to ground [2]
contact discharge - ±30 kV
air discharge - ±30 kV
IP4254CZ8-4-TTL; IP4254CZ12-6-TTL; IP4254CZ16-8-TTL
VESD electrostatic discharge
voltage
all pins to ground [2]
contact discharge - ±30 kV
air discharge - ±30 kV
Per device
VESD electrostatic discharge
voltage
IEC 61000-4-2, level 4;
all pins to ground
contact discharge - ±8 kV
air discharge - ±15 kV
VCC supply voltage −0.5 +5.6 V
Pch channel power dissipation Tamb = 85 °C - 60 mW
Ptot total power dissipation Tamb = 85 °C - 200 mW
Tstg storage temperature −55 +150 °C
Tamb ambient temperature −40 +85 °CIP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 5 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
5. Characteristics
[1] For the total channel.
[2] Guaranteed by design.
Table 5. Channel characteristics
Tamb = 25 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
IP4251CZ8-4-TTL; IP4251CZ12-6-TTL; IP4251CZ16-8-TTL
Cch channel capacitance f = 100 kHz [1]
Vbias(DC) = 2.5 V - 10 - pF
Vbias(DC) =0V [2] - 15 - pF
Rs(ch) channel series resistance 80 100 120 Ω
IP4252CZ8-4-TTL; IP4252CZ12-6-TTL; IP4252CZ16-8-TTL
Cch channel capacitance f = 100 kHz [1]
Vbias(DC) = 2.5 V - 12 - pF
Vbias(DC) =0V [2] - 18 - pF
Rs(ch) channel series resistance 32 40 48 Ω
IP4253CZ8-4-TTL; IP4253CZ12-6-TTL; IP4253CZ16-8-TTL
Cch channel capacitance f = 100 kHz [1]
Vbias(DC) = 2.5 V - 30 - pF
Vbias(DC) =0V [2] - 45 - pF
Rs(ch) channel series resistance 160 200 240 Ω
IP4254CZ8-4-TTL; IP4254CZ12-6-TTL; IP4254CZ16-8-TTL
Cch channel capacitance f = 100 kHz [1]
Vbias(DC) = 2.5 V - 30 - pF
Vbias(DC) =0V [2] - 45 - pF
Rs(ch) channel series resistance 80 100 120 Ω
Per device
ILR reverse leakage current per channel; VI = 3.5 V - - 0.1 μA
VBR breakdown voltage positive clamp; II = 1 mA 5.8 - 9 V
VF forward voltage negative clamp; IF = 1 mA 0.4 - 1.5 VIP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 6 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
Table 6. Frequency characteristics
Tamb = 25 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
IP4251CZ8-4-TTL; IP4251CZ12-6-TTL; IP4251CZ16-8-TTL
αil insertion loss Rsource = 50 Ω; RL = 50 Ω
800 MHz < f < 3 GHz - 16 - dB
f = 1 GHz - 20 - dB
αct crosstalk attenuation Rsource = 50 Ω; RL = 50 Ω;
800 MHz < f < 3 GHz
- 30 - dB
IP4252CZ8-4-TTL; IP4252CZ12-6-TTL; IP4252CZ16-8-TTL
αil insertion loss Rsource = 50 Ω; RL = 50 Ω
800 MHz < f < 3 GHz - 12 - dB
f = 1 GHz - 14 - dB
αct crosstalk attenuation Rsource = 50 Ω; RL = 50 Ω;
800 MHz < f < 3 GHz
- 40 - dB
IP4253CZ8-4-TTL; IP4253CZ12-6-TTL; IP4253CZ16-8-TTL
αil insertion loss Rsource = 50 Ω; RL = 50 Ω
800 MHz < f < 3 GHz - 33 - dB
f = 1 GHz 35 - - dB
αct crosstalk attenuation Rsource = 50 Ω; RL = 50 Ω;
800 MHz < f < 3 GHz
- 30 - dB
IP4254CZ8-4-TTL; IP4254CZ12-6-TTL; IP4254CZ16-8-TTL
αil insertion loss Rsource = 50 Ω; RL = 50 Ω
800 MHz < f < 3 GHz - 28 - dB
f = 1 GHz 30 - - dB
αct crosstalk attenuation Rsource = 50 Ω; RL = 50 Ω;
800 MHz < f < 3 GHz
- 30 - dBIP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 7 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
6. Application information
6.1 Insertion loss
The devices are designed as EMI/RFI filters for multichannel interfaces.
The block schematic for measuring insertion loss in a 50 Ω system is shown in Figure 1.
Typical measurements results are shown in Figure 2 to Figure 6 for the different devices.
(1) IP4252CZ16-8-TTL - channel 1 to channel 16
(2) IP4251CZ16-8-TTL - channel 1 to channel 16
(3) IP4254CZ16-8-TTL - channel 1 to channel 16
(4) IP4253CZ16-8-TTL - channel 1 to channel 16
Fig 1. Frequency response setup Fig 2. Frequency response curves overview
018aaa074
50 Ω
Vgen
50 Ω
DUT
IN OUT
001aaj308
−30
−20
−40
−10
0
S21
(dB)
−50
f (MHz)
10−1 104 103 1 102 10
(1)
(2)
(3)
(4)IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 8 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
Due to the optimized silicon dice and package design, all channels in a single package
show a very good matching performance as the insertion loss for a channel at the
package side (e.g. channel 1 to channel 16) is nearly identical with the center channels
(e.g. channel 4 to channel 13).
(1) Channel 1 to channel 16
(2) Channel 4 to channel 13
(1) Channel 1 to channel 16
(2) Channel 4 to channel 13
Fig 3. IP4251CZ16-8-TTL: frequency response
curves
Fig 4. IP4252CZ16-8-TTL: frequency response
curves
(1) Channel 1 to channel 16
(2) Channel 4 to channel 13
(1) Channel 4 to channel 13
(2) Channel 1 to channel 16
Fig 5. IP4253CZ16-8-TTL: frequency response
curves
Fig 6. IP4254CZ16-8-TTL: frequency response
curves
001aaj608
−30
−20
−40
−10
0
S21
(dB)
−50
f (MHz)
10−1 104 103 1 102 10
(1)
(2)
001aaj609
−30
−20
−40
−10
0
S21
(dB)
−50
f (MHz)
10−1 104 103 1 102 10
(1)
(2)
001aaj610
−30
−20
−40
−10
0
S21
(dB)
−50
f (MHz)
10−1 104 103 1 102 10
(1)
(2)
001aaj611
−30
−20
−40
−10
0
S21
(dB)
−50
f (MHz)
10−1 104 103 1 102 10
(1)
(2)IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 9 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
6.2 Selection
The selection of one of the filter devices has to be performed depending on the maximum
clock frequency, driver strength, capacitive load of the sink, and also the maximum
applicable rise and fall times.
6.2.1 SDHC and MMC memory interface
The Secure Digital High Capacity (SDHC) memory card interface standard specification
and the Multi Media Card (MMC) (JESD 84A43) standard specification recommend a rise
and fall time of 25 % to 62.5 % (62.5 % to 25 % respectively) of 3 ns or less for the input
signal of the receiving interface side.
Assuming a typical capacitance of about 20 pF for the SDHC memory card itself, and
approximately 4 pF to 7 pF for the Printed-Circuit Board (PCB) and the card holder,
IP4252CZ12-6-TTL (6 channels, Rs(ch) = 40 Ω, Cch = 12 pF at Vbias(DC) = 2.5 V) is a
matching selection to filter and protect all relevant interface pins such as CLK, CMD, and
DAT0 to DAT3/CD. Please refer to Figure 7 for a general example of the implementation
of the device in an SDHC card interface.
In case additional channels such as write-protect or a mechanical card-detection switch
are used, the IP4252CZ16-8-TTL (8 channels, Rs(ch) = 40 Ω, Cch = 12 pF at
Vbias(DC) = 2.5 V) offers two additional channels.IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 10 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
The capacitance values specified for the signal channels of the MMC interface differ from
the SDHC specification. The MMC card-side interface is specified to have an intrinsic
capacitance of 12 pF to 18 pF and the total channel is limited according to the
specification to 30 pF only. Therefore, any filter device capacitance is limited to a
maximum of up to 18 pF, including the card holder and PCB traces.
Please refer to Figure 8 for a general example of the implementation of the IP4252 in an
MMC interface application.
Fig 7. Example of IP4252 in an SDHC card interface
018aaa075
IP4252CZ12-6-TTL
(IP4252CZ16-8-TTL)
DAT1
pull-up resistors
10 kΩ − 100 kΩ
10 kΩ − 90 kΩ
DAT3/CD pull-up
10 kΩ − 100 kΩ
DAT3/CD pull-up
>270 kΩ
exact value
depends on
required
logic levels
DAT1 SD MEMORY
CARD
SET_CLR_
CARD_DETECT
(ACMD42)
to HOST
INTERFACE
DAT0
GND
CLK
VCC(VSD)
VCC(VSD)
DAT3/CD
CMD
DAT2
optional:
2-additional channels
of IP4252CZ16-8-TTL
optional:
write protect switch
optional:
electrical card detect
WP
DAT0
CLK
CMD
DAT3/CD
DAT2
CD
WP
optional:
card detect switch
CDIP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 11 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
To generate SDHC and MMC-compliant digital signals, the driver strength should not
significantly undercut 8 mA.
6.2.2 LCD interfaces, medium-speed interfaces
For digital interfaces such as LCD interfaces running at clock speeds between 10 MHz
and 25 MHz or more, IP4251, IP4252 or IP4254 can be used depending on the sink load,
clock speed, driver strength and rise and fall time requirements. Also the minimum
EMI filter requirements may be a decision-making factor.
6.2.3 Keypad, low-speed interfaces
Especially for lower-speed interfaces such as keypads, low-speed serial interfaces
(e.g. Recommended Standard (RS) 232) and low-speed control signals,
IP4253 (Rs(ch) = 200 Ω, Cch = 30 pF at Vbias(DC) = 2.5 V) offers a very robust
ESD protection and strong suppression of unwanted frequencies (EMI filtering).
Fig 8. Example of IP4252 in an MMC interface
018aaa076
IP4252CZ12-6-TTL
IP4252CZ8-4-TTL
DAT1
pull-up resistors
50 kΩ - 100 kΩ
CMD pull-up
4.7 kΩ - 100 kΩ
DAT1 C8
e.g.
RSMMC
HOST
INTERFACE
DAT0 C7
DAT7 C13
VSS2 C6
DAT6 C12
CLK C5
VCC(VMMC)
VCC(VMMC)
C4
VSS1 C3
DAT5 C11
CMD C2
DAT4 C10
DAT3 C1
DAT2
CMD
DAT4
DAT3
DAT2 C9
DAT0
DAT7
DAT6
CLK
DAT5IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 12 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
7. Package outline
Fig 9. Package outline SOT1166-1 (HUSON8)
Outline References
version
European
projection Issue date
IEC JEDEC JEITA
SOT1166-1 - - - - - - - - -
sot1166-1_po
10-03-18
10-03-22
Unit(1)
mm
max
nom
min
0.55 0.05
0.00
0.25
0.20
0.15
1.8
1.7
1.6
1.3
1.2
1.1
1.45
1.35
1.25
0.4 1.2
0.30
0.25
0.20
0.05
A
Dimensions
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
HUSON8: plastic, thermal enhanced ultra thin small outline package; no leads;
8 terminals; body 1.35 x 1.7 x 0.55 mm SOT1166-1
A1 c
0.127
b DDh E Eh
0.45
0.40
0.35
e e1 k
0.2
L v
0.1
w
0.05
y
0.05
y1
0 1 2 mm
scale
X
C
y1 C y
tiebars are indicated on
arbitrary location and size
detail X
A
A1
c
terminal 1
index area
D B A
E
b
terminal 1
index area
e1
e v C A B
w C
L
k
Eh
Dh
1
8
4
5IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 13 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
Fig 10. Package outline SOT1167-1 (HUSON12)
Outline References
version
European
projection Issue date
IEC JEDEC JEITA
SOT1167-1 - - - - - - - - -
sot1167-1_po
10-03-18
10-03-22
Unit(1)
mm
max
nom
min
0.55 0.05
0.00
0.25
0.20
0.15
2.6
2.5
2.4
2.1
2.0
1.9
1.45
1.35
1.25
0.4 2.0
0.30
0.25
0.20
0.05
A
Dimensions
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
HUSON12: plastic, thermal enhanced ultra thin small outline package; no leads;
12 terminals; body 1.35 x 2.5 x 0.55 mm SOT1167-1
A1 c
0.127
b DDh E Eh
0.45
0.40
0.35
e e1 k
0.2
L v
0.1
w
0.05
y
0.05
y1
0 1 2 mm
scale
X
C
y1 C y
tiebars are indicated on
arbitrary location and size
detail X
A
A1
c
terminal 1
index area
D B A
E
b
terminal 1
index area
e1
e v C A B
w C
L
k
Eh
Dh
1
12
6
7IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 14 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
Fig 11. Package outline SOT1168-1 (HUSON16)
Outline References
version
European
projection Issue date
IEC JEDEC JEITA
SOT1168-1 - - - - - - - - -
sot1168-1_po
10-03-18
10-03-22
Unit(1)
mm
max
nom
min
0.55 0.05
0.00
0.25
0.20
0.15
3.4
3.3
3.2
2.9
2.8
2.7
1.45
1.35
1.25
0.4 2.8
0.30
0.25
0.20
0.05
A
Dimensions
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
HUSON16: plastic, thermal enhanced ultra thin small outline package; no leads;
16 terminals; body 1.35 x 3.3 x 0.55 mm SOT1168-1
A1 c
0.127
b DDh E Eh
0.45
0.40
0.35
e e1 k
0.2
L v
0.1
w
0.05
y
0.05
y1
0 1 2 mm
scale
X
C
y1 C y
tiebars are indicated on
arbitrary location and size
detail X
A
A1
c
terminal 1
index area
D B A
E
b
terminal 1
index area
e1
e v C A B
w C
L
k
Eh
Dh
1
16
8
9IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 15 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
8. Revision history
Table 7. Revision history
Document ID Release date Data sheet status Change notice Supersedes
IP4251_52_53_54-TTL v.2 20110505 Product data sheet - IP4251_52_53_54-TTL v.1
Modifications: • Section 1 “Product profile”: updated.
• Table 2 “Pinning”: updated.
• Deleted section “Thermal characteristics”.
IP4251_52_53_54-TTL v.1 20110131 Objective data sheet - -IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 16 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
9. Legal information
9.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
9.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
9.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification. IP4251_52_53_54-TTL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 5 May 2011 17 of 18
NXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
9.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
10. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.comNXP Semiconductors IP4251/52/53/54-TTL
Integrated 4-, 6- and 8-channel passive filter network
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 5 May 2011
Document identifier: IP4251_52_53_54-TTL
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
11. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . 2
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 3
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
5 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
6 Application information. . . . . . . . . . . . . . . . . . . 7
6.1 Insertion loss . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.2 Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6.2.1 SDHC and MMC memory interface . . . . . . . . . 9
6.2.2 LCD interfaces, medium-speed interfaces . . . 11
6.2.3 Keypad, low-speed interfaces. . . . . . . . . . . . . 11
7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10 Contact information. . . . . . . . . . . . . . . . . . . . . 17
11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DATA SHEET
Product data sheet
Supersedes data of 2003 Nov 27
2004 Nov 04
DISCRETE SEMICONDUCTORS
PBSS5320X
20 V, 3 A
PNP low VCEsat (BISS) transistor
dbook, halfpage
M3D1092004 Nov 04 2
NXP Semiconductors Product data sheet
20 V, 3 A
PNP low VCEsat (BISS) transistor PBSS5320X
FEATURES
• SOT89 (SC-62) package
• Low collector-emitter saturation voltage VCEsat
• High collector current capability: IC and ICM
• Higher efficiency leading to less heat generation
• Reduced printed-circuit board requirements.
APPLICATIONS
• Power management
– DC/DC converters
– Supply line switching
– Battery charger
– LCD backlighting.
• Peripheral drivers
– Driver in low supply voltage applications (e.g. lamps
and LEDs)
– Inductive load driver (e.g. relays,
buzzers and motors).
DESCRIPTION
PNP low VCEsat transistor in a SOT89 plastic package.
NPN complement: PBSS4320X.
MARKING
TYPE NUMBER MARKING CODE
PBSS5320X S45
PINNING
PIN DESCRIPTION
1 emitter
2 collector
3 base
321 sym079
1
2
3
Fig.1 Simplified outline (SOT89) and symbol.
QUICK REFERENCE DATA
SYMBOL PARAMETER MAX. UNIT
VCEO collector-emitter voltage −20 V
IC collector current (DC) −3 A
ICM peak collector current −5 A
RCEsat equivalent on-resistance 105 mΩ
ORDERING INFORMATION
TYPE NUMBER
PACKAGE
NAME DESCRIPTION VERSION
PBSS5320X SC-62 plastic surface mounted package; collector pad for good heat
transfer; 3 leads
SOT892004 Nov 04 3
NXP Semiconductors Product data sheet
20 V, 3 A
PNP low VCEsat (BISS) transistor PBSS5320X
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
Notes
1. Device mounted on a FR4 printed-circuit board; single-sided copper; tin-plated; standard footprint.
2. Device mounted on a FR4 printed-circuit board; single-sided copper; tin-plated; mounting pad for collector 1 cm2.
3. Device mounted on a FR4 printed-circuit board; single-sided copper; tin-plated; mounting pad for collector 6 cm2.
4. Device mounted on a ceramic printed-circuit board 7 cm2, single-sided copper, tin-plated.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCBO collector-base voltage open emitter − −20 V
VCEO collector-emitter voltage open base − −20 V
VEBO emitter-base voltage open collector − −5 V
IC collector current (DC) note 4 − −3 A
ICM peak collector current limited by Tj(max) − −5 A
IB base current (DC) − −0.5 A
Ptot total power dissipation Tamb ≤ 25 °C
note 1 − 550 mW
note 2 − 1 W
note 3 − 1.4 W
note 4 − 1.6 W
Tstg storage temperature −65 +150 °C
Tj junction temperature − 150 °C
Tamb ambient temperature −65 +150 °C2004 Nov 04 4
NXP Semiconductors Product data sheet
20 V, 3 A
PNP low VCEsat (BISS) transistor PBSS5320X
handbook, halfpage
0 40 80 160
Ptot
(W) (1)
(2)
(3)
2
0
1.6
120
1.2
0.8
0.4
MLE372
Tamb (°C)
(4)
Fig.2 Power derating curves.
(1) Ceramic PCB; 7 cm2
mounting pad for collector.
(2) FR4 PCB; 6 cm2 copper
mounting pad for collector.
(3) FR4 PCB; 1 cm2 copper
mounting pad for collector.
(4) Standard footprint.2004 Nov 04 5
NXP Semiconductors Product data sheet
20 V, 3 A
PNP low VCEsat (BISS) transistor PBSS5320X
THERMAL CHARACTERISTICS
Notes
1. Device mounted on a FR4 printed-circuit board; single-sided copper; tin-plated; standard footprint.
2. Device mounted on a FR4 printed-circuit board; single-sided copper; tin-plated; mounting pad for collector 1 cm2.
3. Device mounted on a FR4 printed-circuit board; single-sided copper; tin-plated; mounting pad for collector 6 cm2.
4. Device mounted on a ceramic printed-circuit board 7 cm2, single-sided copper, tin-plated.
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth(j-a) thermal resistance from junction to ambient in free air
note 1 225 K/W
note 2 125 K/W
note 3 90 K/W
note 4 80 K/W
Rth(j-s) thermal resistance from junction to soldering point 16 K/W
006aaa243
10
1
102
103
Zth(j-a)
(K/W)
10−1
10−5 10 10 −2 10−4 102 10−1
tp (s)
10−3 103 1
duty cycle =
1.00
0.75
0.50
0.33
0.20
0.10
0.05
0.02
0.01
0
Fig.3 Transient thermal impedance as a function of pulse time; typical values.
Mounted on FR4 printed-circuit board; standard footprint.2004 Nov 04 6
NXP Semiconductors Product data sheet
20 V, 3 A
PNP low VCEsat (BISS) transistor PBSS5320X
006aaa244
10
1
102
103
Zth(j-a)
(K/W)
10−1
10−5 10 10 −2 10−4 102 10−1
tp (s)
10−3 103 1
duty cycle =
1.00
0.75
0.50
0.20
0.05
0.02
0.01
0
0.33
0.10
Fig.4 Transient thermal impedance as a function of pulse time; typical values.
Mounted on FR4 printed-circuit board; mounting pad for collector 1 cm2.
006aaa245
10
1
102
103
Zth(j-a)
(K/W)
10−1
10−5 10 10 −2 10−4 102 10−1
tp (s)
10−3 103 1
duty cycle =
1.00
0.75
0.50
0.20
0.05
0.02
0.01
0
0.33
0.10
Fig.5 Transient thermal impedance as a function of pulse time; typical values.
Mounted on FR4 printed-circuit board; mounting pad for collector 6 cm2.2004 Nov 04 7
NXP Semiconductors Product data sheet
20 V, 3 A
PNP low VCEsat (BISS) transistor PBSS5320X
CHARACTERISTICS
Tamb = 25 °C unless otherwise specified.
Note
1. Pulse test: tp ≤ 300 μs; δ ≤ 0.02.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
ICBO collector-base cut-off current VCB = −20 V; IE = 0 A − − −100 nA
VCB = −20 V; IE = 0 A; Tj = 150 °C − − −50 μA
ICES collector-emitter cut-off current VCE = −20 V; VBE = 0 V − − −100 nA
IEBO emitter-base cut-off current VEB = −5 V; IC = 0 A − − −100 nA
hFE DC current gain VCE = −2 V
IC = −0.1 A 220 − −
IC = −0.5 A 220 − −
IC = −1 A; note 1 200 − −
IC = −2 A; note 1 150 − −
IC = −3 A; note 1 100 − −
VCEsat collector-emitter saturation
voltage
IC = −0.5 A; IB = −50 mA − − −70 mV
IC = −1 A; IB = −50 mA − − −130 mV
IC = −2 A; IB = −100 mA − − −230 mV
IC = −3 A; IB = −300 mA; note 1 − − −300 mV
RCEsat equivalent on-resistance IC = −3 A; IB = −300 mA; note 1 − 90 105 mΩ
VBEsat base-emitter saturation voltage IC = −2 A; IB = −100 mA − −1.1 − V
IC = −3 A; IB = −300 mA; note 1 − − −1.2 V
VBEon base-emitter turn-on voltage VCE = −2 V; IC = −1 A −1.1 − − V
fT transition frequency IC = −100 mA; VCE = −5 V;
f = 100 MHz
100 − − MHz
Cc collector capacitance VCB = −10 V; IE = ie = 0 A; f = 1 MHz − − 50 pF2004 Nov 04 8
NXP Semiconductors Product data sheet
20 V, 3 A
PNP low VCEsat (BISS) transistor PBSS5320X
0
800
200
400
600
MLE374
−10−1 −1
I
C (mA)
hFE
−10 −102 −103 −104
(2)
(3)
(1)
Fig.6 DC current gain as a function of collector
current; typical values.
VCE = −2 V.
(1) Tamb = 100 °C.
(2) Tamb = 25 °C.
(3) Tamb = −55 °C.
handbook, halfpage
MLE368
0
−1.2
−0.4
−0.8
−10−1 −1 −10
I
C (mA)
VBE
(V)
−102 −103 −104
(1)
(3)
(2)
Fig.7 Base-emitter voltage as a function of
collector current; typical values.
VCE = −2 V.
(1) Tamb = −55 °C.
(2) Tamb = 25 °C.
(3) Tamb = 100 °C.
handbook, halfpage
MLE370
−1
−10−1
−10−2
−10−3
−10−1 −1 −10
I
C (mA)
VCEsat
(V)
−102 −103 −104
(1)
(3)
(2)
Fig.8 Collector-emitter saturation voltage as a
function of collector current; typical values.
IC/IB = 20.
(1) Tamb = 100 °C.
(2) Tamb = 25 °C.
(3) Tamb = −55 °C.
handbook, halfpage
MLE371
−1
−10−1
−10−2
−10−3
−10−1 −1 −10
I
C (mA)
VCEsat
(V)
−102 −103 −104
(3)
(1)
(2)
Fig.9 Collector-emitter saturation voltage as a
function of collector current; typical values.
Tamb = 25 °C.
(1) IC/IB = 100.
(2) IC/IB = 50.
(3) IC/IB = 10.2004 Nov 04 9
NXP Semiconductors Product data sheet
20 V, 3 A
PNP low VCEsat (BISS) transistor PBSS5320X
handbook, halfpage −10
−1
−10−1 −1 −10 −102 −103 −104 −10−1
MLE369
I
C (mA)
VBEsat
(V)
(2)
(3)
(1)
Fig.10 Base-emitter saturation voltage as a
function of collector current; typical values.
IC/IB = 20.
(1) Tamb = −55 °C.
(2) Tamb = 25 °C.
(3) Tamb = 100 °C.
handbook, halfpage
103
102
10
1
10−2
10−1
MLE376
−10−1 −1 −10
I
C (mA)
RCEsat
(Ω)
−103 −102 −104
(1)
(3) (2)
Fig.11 Equivalent on-resistance as a function of
collector current; typical values.
Tamb = 25 °C.
(1) IC/IB = 100. (2) IC/IB = 50. (3) IC/IB = 10.
handbook, halfpage
MLE367
102
10
10−1
10−2
1
−10−1 −1
RCEsat
(Ω)
I
C (mA) −10 −102 −103 −104
(2)
(3)
(1)
Fig.12 Equivalent on-resistance as a function of
collector current; typical values.
IC/IB = 20.
(1) Tamb = 100 °C. (2) Tamb = 25 °C. (3) Tamb = −55 °C.
handbook, halfpage
0 −2
−5
0
−1
−2
−3
−4
−0.4
VCE (V)
I
C
(A)
−0.8 −1.2 −1.6
MLE375
(8)
(5)
(1)
(2)
(3)
(4)
(10)
(7)
(6)
(9)
Fig.13 Collector current as a function of
collector-emitter voltage; typical values.
(1) IB = −25 mA.
(2) IB = −22.5 mA.
(3) IB = −20 mA.
(4) IB = −17.5 mA.
(5) IB = −15 mA.
(6) IB = −12.5 mA.
(7) IB = −10 mA.
(8) IB = −7.5 mA.
(9) IB = −5 mA.
(10) IB = −2.5 mA.
Tamb = 25 °C.2004 Nov 04 10
NXP Semiconductors Product data sheet
20 V, 3 A
PNP low VCEsat (BISS) transistor PBSS5320X
PACKAGE OUTLINE
REFERENCES OUTLINE
VERSION
EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
DIMENSIONS (mm are the original dimensions)
SOT89 TO-243 SC-62 04-08-03
06-03-16
w M
e1
e
E
HE
B
0 2 4 mm
scale
bp3
bp2
bp1
c
D
Lp
A
Plastic surface-mounted package; collector pad for good heat transfer; 3 leads SOT89
1 23
UNIT A
mm 1.6
1.4
0.48
0.35
c
0.44
0.23
D
4.6
4.4
E
2.6
2.4
HE Lp
4.25
3.75
e
3.0
w
0.13
e1
1.5 1.2
0.8
bp1 bp2
0.53
0.40
bp3
1.8
1.42004 Nov 04 11
NXP Semiconductors Product data sheet
20 V, 3 A
PNP low VCEsat (BISS) transistor PBSS5320X
DATA SHEET STATUS
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
DOCUMENT
STATUS(1)
PRODUCT
STATUS(2) DEFINITION
Objective data sheet Development This document contains data from the objective specification for product
development.
Preliminary data sheet Qualification This document contains data from the preliminary specification.
Product data sheet Production This document contains the product specification.
DISCLAIMERS
General ⎯ Information in this document is believed to be
accurate and reliable. However, NXP Semiconductors
does not give any representations or warranties,
expressed or implied, as to the accuracy or completeness
of such information and shall have no liability for the
consequences of use of such information.
Right to make changes ⎯ NXP Semiconductors
reserves the right to make changes to information
published in this document, including without limitation
specifications and product descriptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
Suitability for use ⎯ NXP Semiconductors products are
not designed, authorized or warranted to be suitable for
use in medical, military, aircraft, space or life support
equipment, nor in applications where failure or malfunction
of an NXP Semiconductors product can reasonably be
expected to result in personal injury, death or severe
property or environmental damage. NXP Semiconductors
accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at
the customer’s own risk.
Applications ⎯ Applications that are described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values ⎯ Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) may cause permanent damage to
the device. Limiting values are stress ratings only and
operation of the device at these or any other conditions
above those given in the Characteristics sections of this
document is not implied. Exposure to limiting values for
extended periods may affect device reliability.
Terms and conditions of sale ⎯ NXP Semiconductors
products are sold subject to the general terms and
conditions of commercial sale, as published at
http://www.nxp.com/profile/terms, including those
pertaining to warranty, intellectual property rights
infringement and limitation of liability, unless explicitly
otherwise agreed to in writing by NXP Semiconductors. In
case of any inconsistency or conflict between information
in this document and such terms and conditions, the latter
will prevail.
No offer to sell or license ⎯ Nothing in this document
may be interpreted or construed as an offer to sell products
that is open for acceptance or the grant, conveyance or
implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control ⎯ This document as well as the item(s)
described herein may be subject to export control
regulations. Export might require a prior authorization from
national authorities.
Quick reference data ⎯ The Quick reference data is an
extract of the product data given in the Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaustive or legally binding. NXP Semiconductors
Contact information
For additional information please visit: http://www.nxp.com
For sales offices addresses send e-mail to: salesaddresses@nxp.com
© NXP B.V. 2009
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.
Printed in The Netherlands R75/03/pp12 Date of release: 2004 Nov 04 Document order number: 9397 750 13887
Features
• Utilizes the AVR® RISC Architecture
• AVR – High-performance and Low-power RISC Architecture
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
• Data and Non-volatile Program and Data Memories
– 2K Bytes of In-System Self Programmable Flash
Endurance 10,000 Write/Erase Cycles
– 128 Bytes In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– 128 Bytes Internal SRAM
– Programming Lock for Flash Program and EEPROM Data Security
• Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes
– Four PWM Channels
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– USI – Universal Serial Interface
– Full Duplex USART
• Special Microcontroller Features
– debugWIRE On-chip Debugging
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low-power Idle, Power-down, and Standby Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
• I/O and Packages
– 18 Programmable I/O Lines
– 20-pin PDIP, 20-pin SOIC, 20-pad QFN/MLF
• Operating Voltages
– 1.8 – 5.5V (ATtiny2313V)
– 2.7 – 5.5V (ATtiny2313)
• Speed Grades
– ATtiny2313V: 0 – 4 MHz @ 1.8 - 5.5V, 0 – 10 MHz @ 2.7 – 5.5V
– ATtiny2313: 0 – 10 MHz @ 2.7 - 5.5V, 0 – 20 MHz @ 4.5 – 5.5V
• Typical Power Consumption
– Active Mode
1 MHz, 1.8V: 230 µA
32 kHz, 1.8V: 20 µA (including oscillator)
– Power-down Mode
< 0.1 µA at 1.8V
8-bit
Microcontroller
with 2K Bytes
In-System
Programmable
Flash
ATtiny2313/V
Preliminary
Rev. 2543L–AVR–08/102
2543L–AVR–08/10
ATtiny2313
Pin
Configurations
Figure 1. Pinout ATtiny2313
Overview The ATtiny2313 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATtiny2313 achieves
throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption
versus processing speed.
(RESET/dW) PA2
(RXD) PD0
(TXD) PD1
(XTAL2) PA1
(XTAL1) PA0
(CKOUT/XCK/INT0) PD2
(INT1) PD3
(T0) PD4
(OC0B/T1) PD5
GND
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
VCC
PB7 (UCSK/SCL/PCINT7)
PB6 (MISO/DO/PCINT6)
PB5 (MOSI/DI/SDA/PCINT5)
PB4 (OC1B/PCINT4)
PB3 (OC1A/PCINT3)
PB2 (OC0A/PCINT2)
PB1 (AIN1/PCINT1)
PB0 (AIN0/PCINT0)
PD6 (ICP)
PDIP/SOIC
1
2
3
4
5
MLF
15
14
13
12
11
20
19
18
17
16
6
7
8
9
10
(TXD) PD1
XTAL2) PA1
(XTAL1) PA0
(CKOUT/XCK/INT0) PD2
(INT1) PD3
(T0) PD4
(OC0B/T1) PD5
GND
(ICP) PD6
(AIN0/PCINT0) PB0
PB5 (MOSI/DI/SDA/PCINT5)
PB4 (OC1B/PCINT4)
PB3 (OC1A/PCINT3)
PB2 (OC0A/PCINT2)
PB1 (AIN1/PCINT1)
PD0 (RXD)
PA2 (RESET/dW)
VCC
PB7 (UCSK/SCK/PCINT7)
PB6 (MISO/DO/PCINT6)
NOTE: Bottom pad should be soldered to ground.3
2543L–AVR–08/10
ATtiny2313
Block Diagram
Figure 2. Block Diagram
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
GND
VCC
INSTRUCTION
DECODER
CONTROL
LINES
STACK
POINTER
SRAM
GENERAL
PURPOSE
REGISTER
ALU
STATUS
REGISTER
PROGRAMMING
LOGIC SPI
8-BIT DATA BUS
XTAL1 XTAL2
RESET
INTERNAL
OSCILLATOR
OSCILLATOR
WATCHDOG
TIMER
TIMING AND
CONTROL
MCU CONTROL
REGISTER
MCU STATUS
REGISTER
TIMER/
COUNTERS
INTERRUPT
UNIT
EEPROM
USI
USART
ANALOG
COMPARATOR
DATA REGISTER
PORTB
DATA DIR.
REG. PORTB
DATA REGISTER
PORTA
DATA DIR.
REG. PORTA
PORTB DRIVERS
PB0 - PB7
PORTA DRIVERS
PA0 - PA2
DATA REGISTER
PORTD
DATA DIR.
REG. PORTD
PORTD DRIVERS
PD0 - PD6
ON-CHIP
DEBUGGER
INTERNAL
CALIBRATED
OSCILLATOR4
2543L–AVR–08/10
ATtiny2313
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than conventional
CISC microcontrollers.
The ATtiny2313 provides the following features: 2K bytes of In-System Programmable Flash,
128 bytes EEPROM, 128 bytes SRAM, 18 general purpose I/O lines, 32 general purpose working
registers, a single-wire Interface for On-chip Debugging, two flexible Timer/Counters with
compare modes, internal and external interrupts, a serial programmable USART, Universal
Serial Interface with Start Condition Detector, a programmable Watchdog Timer with internal
Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU
while allowing the SRAM, Timer/Counters, and interrupt system to continue functioning. The
Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip
functions until the next interrupt or hardware reset. In Standby mode, the crystal/resonator Oscillator
is running while the rest of the device is sleeping. This allows very fast start-up combined
with low-power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI
serial interface, or by a conventional non-volatile memory programmer. By combining an 8-bit
RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATtiny2313
is a powerful microcontroller that provides a highly flexible and cost effective solution to many
embedded control applications.
The ATtiny2313 AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators,
and Evaluation kits.5
2543L–AVR–08/10
ATtiny2313
Pin Descriptions
VCC Digital supply voltage.
GND Ground.
Port A (PA2..PA0) Port A is a 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port A also serves the functions of various special features of the ATtiny2313 as listed on page
53.
Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny2313 as listed on page
53.
Port D (PD6..PD0) Port D is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATtiny2313 as listed on page
56.
RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page
34. Shorter pulses are not guaranteed to generate a reset. The Reset Input is an alternate function
for PA2 and dW.
XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. XTAL1
is an alternate function for PA0.
XTAL2 Output from the inverting Oscillator amplifier. XTAL2 is an alternate function for PA1.6
2543L–AVR–08/10
ATtiny2313
General
Information
Resources A comprehensive set of development tools, application notes and datasheets are available for
downloadon http://www.atmel.com/avr.
Code Examples This documentation contains simple code examples that briefly show how to use various parts of
the device. These code examples assume that the part specific header file is included before
compilation. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation
for more details.
Disclaimer Typical values contained in this data sheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max values
will be available after the device is characterized.7
2543L–AVR–08/10
ATtiny2313
AVR CPU Core
Introduction This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
Architectural
Overview
Figure 3. Block Diagram of the AVR Architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruction
is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical
ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle.
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
Direct Addressing
Indirect Addressing
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
I/O Module 2
I/O Module1
I/O Module n8
2543L–AVR–08/10
ATtiny2313
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointers
can also be used as an address pointer for look up tables in Flash program memory. These
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single register operations can also be executed in the ALU. After an arithmetic operation,
the Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most AVR instructions have a single 16-bit word format.
Every program memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack
Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position.
The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers,
and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space
locations following those of the Register File, 0x20 - 0x5F.
ALU – Arithmetic
Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general purpose
registers or between a register and an immediate are executed. The ALU operations are divided
into three main categories – arithmetic, logical, and bit-functions. Some implementations of the
architecture also provide a powerful multiplier supporting both signed/unsigned multiplication
and fractional format. See the “Instruction Set” section for a detailed description.
Status Register The Status Register contains information about the result of the most recently executed arithmetic
instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the Instruction Set Reference. This will in many cases remove the need for using the
dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored
when returning from an interrupt. This must be handled by software.9
2543L–AVR–08/10
ATtiny2313
The AVR Status Register – SREG – is defined as:
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt
enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination
for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful
in BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the negative flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
General Purpose
Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve
the required performance and flexibility, the following input/output schemes are supported by the
Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 4 shows the structure of the 32 general purpose working registers in the CPU.
Bit 7 6 5 4 3 2 1 0
I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 010
2543L–AVR–08/10
ATtiny2313
Figure 4. AVR CPU General Purpose Working Registers
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 4, each register is also assigned a data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically implemented
as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
The X-register, Yregister,
and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers
are 16-bit address pointers for indirect addressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in Figure 5.
Figure 5. The X-, Y-, and Z-registers
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
7 0 Addr.
R0 0x00
R1 0x01
R2 0x02
…
R13 0x0D
General R14 0x0E
Purpose R15 0x0F
Working R16 0x10
Registers R17 0x11
…
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte
15 XH XL 0
X-register 7 0 7 0
R27 (0x1B) R26 (0x1A)
15 YH YL 0
Y-register 7 0 7 0
R29 (0x1D) R28 (0x1C)
15 ZH ZL 0
Z-register 7 0 7 0
R31 (0x1F) R30 (0x1E)11
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ATtiny2313
Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations
to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack
with the PUSH instruction, and it is decremented by two when the return address is pushed onto
the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is incremented by two when data is
popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementations
of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
Instruction
Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the
chip. No internal clock division is used.
Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Harvard
architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 6. The Parallel Instruction Fetches and Instruction Executions
Figure 7 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destination
register.
Bit 15 14 13 12 11 10 9 8
– – – – – – – – SPH
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R R R R R R R R
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU12
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ATtiny2313
Figure 7. Single Cycle ALU Operation
Reset and
Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt.
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 44. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. Refer to “Interrupts” on page 44 for more information.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled.
The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
interrupt flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector
in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt
flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be
cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared,
the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared
by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable
bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global
Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clkCPU13
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ATtiny2313
CLI instruction. The following example shows how this can be used to avoid interrupts during the
timed EEPROM write sequence..
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed
before any pending interrupts, as shown in this example.
Interrupt Response
Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum.
After four clock cycles the program vector address for the actual interrupt handling routine
is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack.
The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If
an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed
before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt
execution response time is increased by four clock cycles. This increase comes in addition to the
start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock
cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is
incremented by two, and the I-bit in SREG is set.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
__disable_interrupt();
EECR |= (1< xxx
... ... ... ... 46
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ATtiny2313
I/O-Ports
Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.
This means that the direction of one port pin can be changed without unintentionally changing
the direction of any other pin with the SBI and CBI instructions. The same applies when changing
drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as
input). Each output buffer has symmetrical drive characteristics with both high sink and source
capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually
selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have
protection diodes to both VCC and Ground as indicated in Figure 21. Refer to “Electrical Characteristics”
on page 177 for a complete list of parameters.
Figure 21. I/O Pin Equivalent Schematic
All registers and bit references in this section are written in general form. A lower case “x” represents
the numbering letter for the port, and a lower case “n” represents the bit number. However,
when using the register or bit defines in a program, the precise form must be used. For example,
PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Registers
and bit locations are listed in “Register Description for I/O-Ports” on page 58.
Three I/O memory address locations are allocated for each port, one each for the Data Register
– PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins
I/O location is read only, while the Data Register and the Data Direction Register are read/write.
However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding
bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the
pull-up function for all pins in all ports when set.
Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page
47. Most port pins are multiplexed with alternate functions for the peripheral features on the
device. How each alternate function interferes with the port pin is described in “Alternate Port
Functions” on page 51. Refer to the individual module sections for a full description of the alternate
functions.
Note that enabling the alternate function of some of the port pins does not affect the use of the
other pins in the port as general digital I/O.
Cpin
Logic
Rpu
See Figure
"General Digital I/O" for
Details
Pxn47
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ATtiny2313
Ports as General
Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 22 shows a functional
description of one I/O-port pin, here generically called Pxn.
Figure 22. General Digital I/O(1)
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,
SLEEP, and PUD are common to all ports.
Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register
Description for I/O-Ports” on page 58, the DDxn bits are accessed at the DDRx I/O address, the
PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to
be configured as an output pin. The port pins are tri-stated when reset condition becomes active,
even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven
high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port
pin is driven low (zero).
Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
Note that the SBI instruction can be used to toggle one single bit in a port.
clk
RPx
RRx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
PUD: PULLUP DISABLE
clkI/O: I/O CLOCK
RDx: READ DDRx
D
L
Q
Q
RESET
RESET
Q
D Q
Q
Q D
CLR
PORTxn
Q
Q D
CLR
DDxn
PINxn
DATA BUS
SLEEP
SLEEP: SLEEP CONTROL
Pxn
I/O
WPx
0
1
WRx
WPx: WRITE PINx REGISTER48
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ATtiny2313
Switching Between
Input and Output
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}
= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output
low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable,
as a high-impedant environment will not notice the difference between a strong high driver
and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all
pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}
= 0b11) as an intermediate step.
Table 22 summarizes the control signals for the pin value.
Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in Figure 22, the PINxn Register bit and the preceding latch constitute
a synchronizer. This is needed to avoid metastability if the physical pin changes value near
the edge of the internal clock, but it also introduces a delay. Figure 23 shows a timing diagram of
the synchronization when reading an externally applied pin value. The maximum and minimum
propagation delays are denoted tpd,max and tpd,min respectively.
Figure 23. Synchronization when Reading an Externally Applied Pin value
Table 22. Port Pin Configurations
DDxn PORTxn
PUD
(in MCUCR) I/O Pull-up Comment
0 0 X Input No Tri-state (Hi-Z)
0 1 0 Input Yes
Pxn will source current if ext. pulled
low.
0 1 1 Input No Tri-state (Hi-Z)
1 0 X Output No Output Low (Sink)
1 1 X Output No Output High (Source)
XXX in r17, PINx
0x00 0xFF
INSTRUCTIONS
SYNC LATCH
PINxn
r17
XXX
SYSTEM CLK
tpd, max
tpd, min49
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ATtiny2313
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated
by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed
between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indicated
in Figure 24. The out instruction sets the “SYNC LATCH” signal at the positive edge of the
clock. In this case, the delay tpd through the synchronizer is 1 system clock period.
Figure 24. Synchronization when Reading a Software Assigned Pin Value
out PORTx, r16 nop in r17, PINx
0xFF
0x00 0xFF
SYSTEM CLK
r16
INSTRUCTIONS
SYNC LATCH
PINxn
r17
t pd50
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ATtiny2313
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define
the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin
values are read back again, but as previously discussed, a nop instruction is included to be able
to read back the value recently assigned to some of the pins.
Note: 1. For the assembly program, two temporary registers are used to minimize the time from pullups
are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3
as low and redefining bits 0 and 1 as strong high drivers.
Digital Input Enable
and Sleep Modes
As shown in Figure 22, the digital input signal can be clamped to ground at the input of the
Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in
Power-down mode, and Standby mode to avoid high power consumption if some input signals
are left floating, or have an analog signal level close to VCC/2.
SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt
request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various
other alternate functions as described in “Alternate Port Functions” on page 51.
If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as
“Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt
is not enabled, the corresponding External Interrupt Flag will be set when resuming from the
above mentioned Sleep mode, as the clamping in these sleep mode produces the requested
logic change.
Assembly Code Example(1)
...
; Define pull-ups and set outputs high
; Define directions for port pins
ldi r16,(1< CSn2:0 > 1). The number of system clock
cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system
clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution.
However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is
connected to.
External Clock Source An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock
(clkT1/clkT0). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization
logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 38
shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector
logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch
is transparent in the high period of the internal system clock.
The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or negative
(CSn2:0 = 6) edge it detects.
Figure 38. T1/T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the T1/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the system
clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses
sampling, the maximum frequency of an external clock it can detect is half the sampling freTn_sync
(To Clock
Select Logic)
Synchronization Edge Detector
D Q D Q
LE
Tn D Q
clkI/O81
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ATtiny2313
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5.
An external clock source can not be prescaled.
Figure 39. Prescaler for Timer/Counter0 and Timer/Counter1(1)
Note: 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 38.
General Timer/Counter
Control Register –
GTCCR
• Bits 7..1 – Res: Reserved Bits
These bits are reserved bits in the ATtiny2313 and will always read as zero.
• Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally
cleared immediately by hardware. Note that Timer/Counter1 and Timer/Counter0 share
the same prescaler and a reset of this prescaler will affect both timers.
PSR10
Clear
clkT1 clkT0
T1
T0
clkI/O
Synchronization
Synchronization
Bit 7 6 5 4 3 2 1 0
— – – – – – — PSR10 GTCCR
Read/Write R R R R R R R R/W
Initial Value 0 0 0 0 0 0 0 082
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16-bit
Timer/Counter1
The 16-bit Timer/Counter unit allows accurate program execution timing (event management),
wave generation, and signal timing measurement. The main features are:
• True 16-bit Design (i.e., Allows 16-bit PWM)
• Two independent Output Compare Units
• Double Buffered Output Compare Registers
• One Input Capture Unit
• Input Capture Noise Canceler
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, Phase Correct Pulse Width Modulator (PWM)
• Variable PWM Period
• Frequency Generator
• External Event Counter
• Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
Overview Most register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit
channel. However, when using the register or bit defines in a program, the precise form must be
used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 40. For the actual
placement of I/O pins, refer to “Pinout ATtiny2313” on page 2. CPU accessible I/O Registers,
including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations
are listed in the “16-bit Timer/Counter Register Description” on page 104.
Figure 40. 16-bit Timer/Counter Block Diagram(1)
Note: 1. Refer to Figure 1 on page 2 for Timer/Counter1 pin placement and description.
Clock Select
Timer/Counter
DATA BUS
OCRnA
OCRnB
ICRn
=
=
TCNTn
Waveform
Generation
Waveform
Generation
OCnA
OCnB
Noise
Canceler
ICPn
=
Fixed
TOP
Values
Edge
Detector
Control Logic
= 0
TOP BOTTOM
Count
Clear
Direction
TOVn
(Int.Req.)
OCnA
(Int.Req.)
OCnB
(Int.Req.)
ICFn (Int.Req.)
TCCRnA TCCRnB
( From Analog
Comparator Ouput )
Tn Edge
Detector
( From Prescaler )
clkTn83
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ATtiny2313
Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register
(ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16-
bit registers. These procedures are described in the section “Accessing 16-bit Registers” on
page 84. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers and have no CPU
access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible
in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer
Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T1 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clkT1).
The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter
value at all time. The result of the compare can be used by the Waveform Generator to
generate a PWM or variable frequency output on the Output Compare pin (OC1A/B). See “Output
Compare Units” on page 90.. The compare match event will also set the Compare Match
Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request.
The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered)
event on either the Input Capture pin (ICP1) or on the Analog Comparator pins (See
“Analog Comparator” on page 149.) The Input Capture unit includes a digital filtering unit (Noise
Canceler) for reducing the chance of capturing noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined
by either the OCR1A Register, the ICR1 Register, or by a set of fixed values. When using
OCR1A as TOP value in a PWM mode, the OCR1A Register can not be used for generating a
PWM output. However, the TOP value will in this case be double buffered allowing the TOP
value to be changed in run time. If a fixed TOP value is required, the ICR1 Register can be used
as an alternative, freeing the OCR1A to be used as PWM output.
Definitions The following definitions are used extensively throughout the section:
Compatibility The 16-bit Timer/Counter has been updated and improved from previous versions of the 16-bit
AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier version
regarding:
• All 16-bit Timer/Counter related I/O Register address locations, including Timer Interrupt
Registers.
• Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers.
• Interrupt Vectors.
The following control bits have changed name, but have same functionality and register location:
• PWM10 is changed to WGM10.
• PWM11 is changed to WGM11.
• CTC1 is changed to WGM12.
Table 42. Definitions
BOTTOM The counter reaches the BOTTOM when it becomes 0x0000.
MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).
TOP
The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be one of the fixed values:
0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCR1A or ICR1 Register.
The assignment is dependent of the mode of operation.84
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ATtiny2313
The following bits are added to the 16-bit Timer/Counter Control Registers:
• FOC1A and FOC1B are added to TCCR1A.
• WGM13 is added to TCCR1B.
The 16-bit Timer/Counter has improvements that will affect the compatibility in some special
cases.
Accessing 16-bit
Registers
The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via
the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations.
Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit
access. The same temporary register is shared between all 16-bit registers within each 16-bit
timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a
16-bit register is written by the CPU, the high byte stored in the temporary register, and the low
byte written are both copied into the 16-bit register in the same clock cycle. When the low byte of
a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the temporary
register in the same clock cycle as the low byte is read.
Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR1A/B 16-
bit registers does not involve using the temporary register.
To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low
byte must be read before the high byte.
The following code examples show how to access the 16-bit timer registers assuming that no
interrupts updates the temporary register. The same principle can be used directly for accessing
the OCR1A/B and ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit
access.85
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ATtiny2313
Note: 1. The example code assumes that the part specific header file is included.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
The assembly code example returns the TCNT1 value in the r17:r16 register pair.
It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt
occurs between the two instructions accessing the 16-bit register, and the interrupt code
updates the temporary register by accessing the same or any other of the 16-bit timer registers,
then the result of the access outside the interrupt will be corrupted. Therefore, when both the
main code and the interrupt code update the temporary register, the main code must disable the
interrupts during the 16-bit access.
Assembly Code Examples(1)
...
; Set TCNT1 to 0x01FF
ldi r17,0x01
ldi r16,0xFF
out TCNT1H,r17
out TCNT1L,r16
; Read TCNT1 into r17:r16
in r16,TCNT1L
in r17,TCNT1H
...
C Code Examples(1)
unsigned int i;
...
/* Set TCNT1 to 0x01FF */
TCNT1 = 0x1FF;
/* Read TCNT1 into i */
i = TCNT1;
...86
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The following code examples show how to do an atomic read of the TCNT1 Register contents.
Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
Note: 1. The example code assumes that the part specific header file is included.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
The assembly code example returns the TCNT1 value in the r17:r16 register pair.
Assembly Code Example(1)
TIM16_ReadTCNT1:
; Save global interrupt flag
in r18,SREG
; Disable interrupts
cli
; Read TCNT1 into r17:r16
in r16,TCNT1L
in r17,TCNT1H
; Restore global interrupt flag
out SREG,r18
ret
C Code Example(1)
unsigned int TIM16_ReadTCNT1( void )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
__disable_interrupt();
/* Read TCNT1 into i */
i = TCNT1;
/* Restore global interrupt flag */
SREG = sreg;
return i;
}87
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The following code examples show how to do an atomic write of the TCNT1 Register contents.
Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
Note: 1. The example code assumes that the part specific header file is included.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
The assembly code example requires that the r17:r16 register pair contains the value to be written
to TCNT1.
Reusing the
Temporary High Byte
Register
If writing to more than one 16-bit register where the high byte is the same for all registers written,
then the high byte only needs to be written once. However, note that the same rule of atomic
operation described previously also applies in this case.
Assembly Code Example(1)
TIM16_WriteTCNT1:
; Save global interrupt flag
in r18,SREG
; Disable interrupts
cli
; Set TCNT1 to r17:r16
out TCNT1H,r17
out TCNT1L,r16
; Restore global interrupt flag
out SREG,r18
ret
C Code Example(1)
void TIM16_WriteTCNT1( unsigned int i )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
__disable_interrupt();
/* Set TCNT1 to i */
TCNT1 = i;
/* Restore global interrupt flag */
SREG = sreg;
}88
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Timer/Counter
Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits
located in the Timer/Counter control Register B (TCCR1B). For details on clock sources and
prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 80.
Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.
Figure 41 shows a block diagram of the counter and its surroundings.
Figure 41. Counter Unit Block Diagram
Signal description (internal signals):
Count Increment or decrement TCNT1 by 1.
Direction Select between increment and decrement.
Clear Clear TCNT1 (set all bits to zero).
clkT1 Timer/Counter clock.
TOP Signalize that TCNT1 has reached maximum value.
BOTTOM Signalize that TCNT1 has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) containing
the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight
bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU does an
access to the TCNT1H I/O location, the CPU accesses the high byte temporary register (TEMP).
The temporary register is updated with the TCNT1H value when the TCNT1L is read, and
TCNT1H is updated with the temporary register value when TCNT1L is written. This allows the
CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.
It is important to notice that there are special cases of writing to the TCNT1 Register when the
counter is counting that will give unpredictable results. The special cases are described in the
sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clkT1). The clkT1 can be generated from an external or internal clock source,
selected by the Clock Select bits (CS12:0). When no clock source is selected (CS12:0 = 0) the
timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of
whether clkT1 is present or not. A CPU write overrides (has priority over) all counter clear or
count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits
(WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B).
There are close connections between how the counter behaves (counts) and how waveforms
are generated on the Output Compare outputs OC1x. For more details about advanced counting
sequences and waveform generation, see “Modes of Operation” on page 94.
TEMP (8-bit)
DATA BUS (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit) Control Logic
Count
Clear
Direction
TOVn
(Int.Req.)
Clock Select
TOP BOTTOM
Tn Edge
Detector
( From Prescaler )
clkTn89
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The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by
the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt.
Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give
them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple
events, can be applied via the ICP1 pin or alternatively, via the analog-comparator unit. The
time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal
applied. Alternatively the time-stamps can be used for creating a log of the events.
The Input Capture unit is illustrated by the block diagram shown in Figure 42. The elements of
the block diagram that are not directly a part of the Input Capture unit are gray shaded. The
small “n” in register and bit names indicates the Timer/Counter number.
Figure 42. Input Capture Unit Block Diagram
When a change of the logic level (an event) occurs on the Input Capture pin (ICP1), alternatively
on the Analog Comparator output (ACO), and this change confirms to the setting of the edge
detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter
(TCNT1) is written to the Input Capture Register (ICR1). The Input Capture Flag (ICF1) is set at
the same system clock as the TCNT1 value is copied into ICR1 Register. If enabled (ICIE1 = 1),
the Input Capture Flag generates an Input Capture interrupt. The ICF1 flag is automatically
cleared when the interrupt is executed. Alternatively the ICF1 flag can be cleared by software by
writing a logical one to its I/O bit location.
Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the low
byte (ICR1L) and then the high byte (ICR1H). When the low byte is read the high byte is copied
into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will
access the TEMP Register.
The ICR1 Register can only be written when using a Waveform Generation mode that utilizes
the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Generation
mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1
Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location
before the low byte is written to ICR1L.
ICFn (Int.Req.)
Analog
Comparator
WRITE ICRn (16-bit Register)
ICRnH (8-bit)
Noise
Canceler
ICPn
Edge
Detector
TEMP (8-bit)
DATA BUS (8-bit)
ICRnL (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit)
ACO* ACIC* ICNC ICES90
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For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers”
on page 84.
Input Capture Trigger
Source
The main trigger source for the Input Capture unit is the Input Capture pin (ICP1).
Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the
Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog
Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register
(ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag
must therefore be cleared after the change.
Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled
using the same technique as for the T1 pin (Figure 38 on page 80). The edge detector is also
identical. However, when the noise canceler is enabled, additional logic is inserted before the
edge detector, which increases the delay by four system clock cycles. Note that the input of the
noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform
Generation mode that uses ICR1 to define TOP.
An Input Capture can be triggered by software by controlling the port of the ICP1 pin.
Noise Canceler The noise canceler improves noise immunity by using a simple digital filtering scheme. The
noise canceler input is monitored over four samples, and all four must be equal for changing the
output that in turn is used by the edge detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in
Timer/Counter Control Register B (TCCR1B). When enabled the noise canceler introduces additional
four system clock cycles of delay from a change applied to the input, to the update of the
ICR1 Register. The noise canceler uses the system clock and is therefore not affected by the
prescaler.
Using the Input
Capture Unit
The main challenge when using the Input Capture unit is to assign enough processor capacity
for handling the incoming events. The time between two events is critical. If the processor has
not read the captured value in the ICR1 Register before the next event occurs, the ICR1 will be
overwritten with a new value. In this case the result of the capture will be incorrect.
When using the Input Capture interrupt, the ICR1 Register should be read as early in the interrupt
handler routine as possible. Even though the Input Capture interrupt has relatively high
priority, the maximum interrupt response time is dependent on the maximum number of clock
cycles it takes to handle any of the other interrupt requests.
Using the Input Capture unit in any mode of operation when the TOP value (resolution) is
actively changed during operation, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after
each capture. Changing the edge sensing must be done as early as possible after the ICR1
Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be
cleared by software (writing a logical one to the I/O bit location). For measuring frequency only,
the clearing of the ICF1 flag is not required (if an interrupt handler is used).
Output Compare
Units
The 16-bit comparator continuously compares TCNT1 with the Output Compare Register
(OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output
Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Compare
Flag generates an Output Compare interrupt. The OCF1x flag is automatically cleared
when the interrupt is executed. Alternatively the OCF1x flag can be cleared by software by writing
a logical one to its I/O bit location. The Waveform Generator uses the match signal to
generate an output according to operating mode set by the Waveform Generation mode
(WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP and BOTTOM signals91
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are used by the Waveform Generator for handling the special cases of the extreme values in
some modes of operation (See “Modes of Operation” on page 94.)
A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e.,
counter resolution). In addition to the counter resolution, the TOP value defines the period time
for waveforms generated by the Waveform Generator.
Figure 43 shows a block diagram of the Output Compare unit. The small “n” in the register and
bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output
Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output
Compare unit are gray shaded.
Figure 43. Output Compare Unit, Block Diagram
The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation
(PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the
double buffering is disabled. The double buffering synchronizes the update of the OCR1x Compare
Register to either TOP or BOTTOM of the counting sequence. The synchronization
prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output
glitch-free.
The OCR1x Register access may seem complex, but this is not case. When the double buffering
is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled
the CPU will access the OCR1x directly. The content of the OCR1x (Buffer or Compare)
Register is only changed by a write operation (the Timer/Counter does not update this register
automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the high byte
temporary register (TEMP). However, it is a good practice to read the low byte first as when
accessing other 16-bit registers. Writing the OCR1x Registers must be done via the TEMP Register
since the compare of all 16 bits is done continuously. The high byte (OCR1xH) has to be
written first. When the high byte I/O location is written by the CPU, the TEMP Register will be
updated by the value written. Then when the low byte (OCR1xL) is written to the lower eight bits,
the high byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare
Register in the same system clock cycle.
OCFnx (Int.Req.)
= (16-bit Comparator )
OCRnx Buffer (16-bit Register)
OCRnxH Buf. (8-bit)
OCnx
TEMP (8-bit)
DATA BUS (8-bit)
OCRnxL Buf. (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit) TCNTnL (8-bit)
WGMn3:0 COMnx1:0
OCRnx (16-bit Register)
OCRnxH (8-bit) OCRnxL (8-bit)
Waveform Generator
TOP
BOTTOM92
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For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers”
on page 84.
Force Output
Compare
In non-PWM Waveform Generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOC1x) bit. Forcing compare match will not set the
OCF1x flag or reload/clear the timer, but the OC1x pin will be updated as if a real compare
match had occurred (the COM11:0 bits settings define whether the OC1x pin is set, cleared or
toggled).
Compare Match
Blocking by TCNT1
Write
All CPU writes to the TCNT1 Register will block any compare match that occurs in the next timer
clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the
same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled.
Using the Output
Compare Unit
Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNT1 when using any of the Output Compare
channels, independent of whether the Timer/Counter is running or not. If the value written to
TCNT1 equals the OCR1x value, the compare match will be missed, resulting in incorrect waveform
generation. Do not write the TCNT1 equal to TOP in PWM modes with variable TOP
values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF.
Similarly, do not write the TCNT1 value equal to BOTTOM when the counter is downcounting.
The setup of the OC1x should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OC1x value is to use the Force Output Compare
(FOC1x) strobe bits in Normal mode. The OC1x Register keeps its value even when
changing between Waveform Generation modes.
Be aware that the COM1x1:0 bits are not double buffered together with the compare value.
Changing the COM1x1:0 bits will take effect immediately.93
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Compare Match
Output Unit
The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses
the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match.
Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 44 shows a simplified
schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O
pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR
and PORT) that are affected by the COM1x1:0 bits are shown. When referring to the OC1x
state, the reference is for the internal OC1x Register, not the OC1x pin. If a system reset occur,
the OC1x Register is reset to “0”.
Figure 44. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform
Generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or output)
is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x value is visible
on the pin. The port override function is generally independent of the Waveform Generation
mode, but there are some exceptions. Refer to Table 43, Table 44 and Table 45 for details.
The design of the Output Compare pin logic allows initialization of the OC1x state before the output
is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of
operation. See “16-bit Timer/Counter Register Description” on page 104.
The COM1x1:0 bits have no effect on the Input Capture unit.
PORT
DDR
D Q
D Q
OCnx
OCnx Pin
D Q Waveform
Generator
COMnx1
COMnx0
0
1
DATA BUS
FOCnx
clkI/O94
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Compare Output Mode
and Waveform
Generation
The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes.
For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no action on the
OC1x Register is to be performed on the next compare match. For compare output actions in the
non-PWM modes refer to Table 43 on page 104. For fast PWM mode refer to Table 44 on page
104, and for phase correct and phase and frequency correct PWM refer to Table 45 on page
105.
A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOC1x strobe bits.
Modes of
Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is
defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Output
mode (COM1x1:0) bits. The Compare Output mode bits do not affect the counting sequence,
while the Waveform Generation mode bits do. The COM1x1:0 bits control whether the PWM output
generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes
the COM1x1:0 bits control whether the output should be set, cleared or toggle at a compare
match (See “Compare Match Output Unit” on page 93.)
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 102.
Normal Mode The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the
BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOV1) will be set in
the same timer clock cycle as the TCNT1 becomes zero. The TOV1 flag in this case behaves
like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow
interrupt that automatically clears the TOV1 flag, the timer resolution can be increased by software.
There are no special cases to consider in the Normal mode, a new counter value can be
written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maximum
interval between the external events must not exceed the resolution of the counter. If the interval
between events are too long, the timer overflow interrupt or the prescaler must be used to
extend the resolution for the capture unit.
The Output Compare units can be used to generate interrupts at some given time. Using the
Output Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
Clear Timer on
Compare Match (CTC)
Mode
In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Register
are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when
the counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 =
12). The OCR1A or ICR1 define the top value for the counter, hence also its resolution. This
mode allows greater control of the compare match output frequency. It also simplifies the operation
of counting external events.
The timing diagram for the CTC mode is shown in Figure 45 on page 95. The counter value
(TCNT1) increases until a compare match occurs with either OCR1A or ICR1, and then counter
(TCNT1) is cleared.95
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Figure 45. CTC Mode, Timing Diagram
An interrupt can be generated at each time the counter value reaches the TOP value by either
using the OCF1A or ICF1 flag according to the register used to define the TOP value. If the interrupt
is enabled, the interrupt handler routine can be used for updating the TOP value. However,
changing the TOP to a value close to BOTTOM when the counter is running with none or a low
prescaler value must be done with care since the CTC mode does not have the double buffering
feature. If the new value written to OCR1A or ICR1 is lower than the current value of TCNT1, the
counter will miss the compare match. The counter will then have to count to its maximum value
(0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In many
cases this feature is not desirable. An alternative will then be to use the fast PWM mode using
OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double buffered.
For generating a waveform output in CTC mode, the OCFA output can be set to toggle its logical
level on each compare match by setting the Compare Output mode bits to toggle mode
(COM1A1:0 = 1). The OCF1A value will not be visible on the port pin unless the data direction
for the pin is set to output (DDR_OCF1A = 1). The waveform generated will have a maximum
frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). The waveform frequency is
defined by the following equation:
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV1 flag is set in the same timer clock cycle that the
counter counts from MAX to 0x0000.
TCNTn
OCnA
(Toggle)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
Period 1 2 3 4
(COMnA1:0 = 1)
f
OCnA
f
clk_I/O
2 ⋅ ⋅ N ( ) 1 + OCRnA = --------------------------------------------------96
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Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a
high frequency PWM waveform generation option. The fast PWM differs from the other PWM
options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts
from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is set on
the compare match between TCNT1 and OCR1x, and cleared at TOP. In inverting Compare
Output mode output is cleared on compare match and set at TOP. Due to the single-slope operation,
the operating frequency of the fast PWM mode can be twice as high as the phase correct
and phase and frequency correct PWM modes that use dual-slope operation. This high frequency
makes the fast PWM mode well suited for power regulation, rectification, and DAC
applications. High frequency allows physically small sized external components (coils, capacitors),
hence reduces total system cost.
The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or
OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum
resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be
calculated by using the following equation:
In fast PWM mode the counter is incremented until the counter value matches either one of the
fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 =
14), or the value in OCR1A (WGM13:0 = 15). The counter is then cleared at the following timer
clock cycle. The timing diagram for the fast PWM mode is shown in Figure 46. The figure shows
fast PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing
diagram shown as a histogram for illustrating the single-slope operation. The diagram includes
non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes
represent compare matches between OCR1x and TCNT1. The OC1x interrupt flag will be set
when a compare match occurs.
Figure 46. Fast PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition
the OCF1A or ICF1 flag is set at the same timer clock cycle as TOV1 is set when either OCR1A
or ICR1 is used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler
routine can be used for updating the TOP and compare values.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x.
RFPWM
log( ) TOP + 1
log( ) 2 = -----------------------------------
TCNTn
OCRnx/TOP Update and
TOVn Interrupt Flag Set and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
Period 1 2 3 4 5 6 7 8
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)97
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Note that when using fixed TOP values the unused bits are masked to zero when any of the
OCR1x Registers are written.
The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP
value. The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low
value when the counter is running with none or a low prescaler value, there is a risk that the new
ICR1 value written is lower than the current value of TCNT1. The result will then be that the
counter will miss the compare match at the TOP value. The counter will then have to count to the
MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur.
The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location
to be written anytime. When the OCR1A I/O location is written the value written will be put into
the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value
in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done
at the same timer clock cycle as the TCNT1 is cleared and the TOV1 flag is set.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using
ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However,
if the base PWM frequency is actively changed (by changing the TOP value), using the OCR1A
as TOP is clearly a better choice due to its double buffer feature.
In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins.
Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output
can be generated by setting the COM1x1:0 to three (see Table 43 on page 104). The actual
OC1x value will only be visible on the port pin if the data direction for the port pin is set as output
(DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at
the compare match between OCR1x and TCNT1, and clearing (or setting) the OC1x Register at
the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR1x is set equal to BOTTOM (0x0000) the output
will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR1x equal to TOP
will result in a constant high or low output (depending on the polarity of the output set by the
COM1x1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting
OCF1A to toggle its logical level on each compare match (COM1A1:0 = 1). The waveform
generated will have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero
(0x0000). This feature is similar to the OCF1A toggle in CTC mode, except the double buffer
feature of the Output Compare unit is enabled in the fast PWM mode.
f
OCnxPWM
f
clk_I/O
N ⋅ ( ) 1 + TOP = -----------------------------------98
2543L–AVR–08/10
ATtiny2313
Phase Correct PWM
Mode
The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3,
10, or 11) provides a high resolution phase correct PWM waveform generation option. The
phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dualslope
operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from
TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is
cleared on the compare match between TCNT1 and OCR1x while upcounting, and set on the
compare match while downcounting. In inverting Output Compare mode, the operation is
inverted. The dual-slope operation has lower maximum operation frequency than single slope
operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes
are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined
by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to
0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution
in bits can be calculated by using the following equation:
In phase correct PWM mode the counter is incremented until the counter value matches either
one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1
(WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then reached the
TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock
cycle. The timing diagram for the phase correct PWM mode is shown on Figure 47. The figure
shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1
value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The
diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on
the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x interrupt
flag will be set when a compare match occurs.
Figure 47. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When
either OCR1A or ICR1 is used for defining the TOP value, the OCF1A or ICF1 flag is set accordingly
at the same timer clock cycle as the OCR1x Registers are updated with the double buffer
RPCPWM
log( ) TOP + 1
log( ) 2 = -----------------------------------
OCRnx/TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1 2 3 4
TOVn Interrupt Flag Set
(Interrupt on Bottom)
TCNTn
Period
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)99
2543L–AVR–08/10
ATtiny2313
value (at TOP). The interrupt flags can be used to generate an interrupt each time the counter
reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x.
Note that when using fixed TOP values, the unused bits are masked to zero when any of the
OCR1x Registers are written. As the third period shown in Figure 47 illustrates, changing the
TOP actively while the Timer/Counter is running in the phase correct mode can result in an
unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Register.
Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This
implies that the length of the falling slope is determined by the previous TOP value, while the
length of the rising slope is determined by the new TOP value. When these two values differ the
two slopes of the period will differ in length. The difference in length gives the unsymmetrical
result on the output.
It is recommended to use the phase and frequency correct mode instead of the phase correct
mode when changing the TOP value while the Timer/Counter is running. When using a static
TOP value there are practically no differences between the two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the
OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted
PWM output can be generated by setting the COM1x1:0 to three (See Table 44 on page 104).
The actual OC1x value will only be visible on the port pin if the data direction for the port pin is
set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x
Register at the compare match between OCR1x and TCNT1 when the counter increments, and
clearing (or setting) the OC1x Register at compare match between OCR1x and TCNT1 when
the counter decrements. The PWM frequency for the output when using phase correct PWM can
be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
f
OCnxPCPWM
f
clk_I/O
2 ⋅ ⋅ N TOP = ----------------------------100
2543L–AVR–08/10
ATtiny2313
Phase and Frequency
Correct PWM Mode
The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM
mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency correct PWM waveform
generation option. The phase and frequency correct PWM mode is, like the phase correct
PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM
(0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the
Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x while
upcounting, and set on the compare match while downcounting. In inverting Compare Output
mode, the operation is inverted. The dual-slope operation gives a lower maximum operation frequency
compared to the single-slope operation. However, due to the symmetric feature of the
dual-slope PWM modes, these modes are preferred for motor control applications.
The main difference between the phase correct, and the phase and frequency correct PWM
mode is the time the OCR1x Register is updated by the OCR1x Buffer Register, (see Figure 47
and Figure 48).
The PWM resolution for the phase and frequency correct PWM mode can be defined by either
ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and
the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can
be calculated using the following equation:
In phase and frequency correct PWM mode the counter is incremented until the counter value
matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The
counter has then reached the TOP and changes the count direction. The TCNT1 value will be
equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency
correct PWM mode is shown on Figure 48. The figure shows phase and frequency correct PWM
mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram
shown as a histogram for illustrating the dual-slope operation. The diagram includes noninverted
and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent
compare matches between OCR1x and TCNT1. The OC1x interrupt flag will be set when a
compare match occurs.
Figure 48. Phase and Frequency Correct PWM Mode, Timing Diagram
RPFCPWM
log( ) TOP + 1
log( ) 2 = -----------------------------------
OCRnx/TOP Updateand
TOVn Interrupt Flag Set
(Interrupt on Bottom)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1 2 3 4
TCNTn
Period
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)101
2543L–AVR–08/10
ATtiny2313
The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x
Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1
is used for defining the TOP value, the OCF1A or ICF1 flag set when TCNT1 has reached TOP.
The interrupt flags can then be used to generate an interrupt each time the counter reaches the
TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x.
As Figure 48 shows the output generated is, in contrast to the phase correct mode, symmetrical
in all periods. Since the OCR1x Registers are updated at BOTTOM, the length of the rising and
the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency
correct.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using
ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However,
if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as
TOP is clearly a better choice due to its double buffer feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms
on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and
an inverted PWM output can be generated by setting the COM1x1:0 to three (See Table 45 on
page 105). The actual OC1Fx value will only be visible on the port pin if the data direction for the
port pin is set as output (DDR_OCF1x). The PWM waveform is generated by setting (or clearing)
the OCF1x Register at the compare match between OCR1x and TCNT1 when the counter increments,
and clearing (or setting) the OCF1x Register at compare match between OCR1x and
TCNT1 when the counter decrements. The PWM frequency for the output when using phase
and frequency correct PWM can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be set to high for noninverted
PWM mode. For inverted PWM the output will have the opposite logic values.
f
OCnxPFCPWM
f
clk_I/O
2 ⋅ ⋅ N TOP = ----------------------------102
2543L–AVR–08/10
ATtiny2313
Timer/Counter
Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a
clock enable signal in the following figures. The figures include information on when interrupt
flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for
modes utilizing double buffering). Figure 49 shows a timing diagram for the setting of OCF1x.
Figure 49. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
Figure 50 shows the same timing data, but with the prescaler enabled.
Figure 50. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8)
Figure 51 shows the count sequence close to TOP in various modes. When using phase and
frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams
will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
The same renaming applies for modes that set the TOV1 flag at BOTTOM.
clkTn
(clkI/O/1)
OCFnx
clkI/O
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clkI/O
clkTn
(clkI/O/8)103
2543L–AVR–08/10
ATtiny2313
Figure 51. Timer/Counter Timing Diagram, no Prescaling
Figure 52 shows the same timing data, but with the prescaler enabled.
Figure 52. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2
Old OCRnx Value New OCRnx Value
TOP - 1 TOP BOTTOM BOTTOM + 1
clkTn
(clkI/O/1)
clkI/O
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOP - 1 TOP TOP - 1 TOP - 2
Old OCRnx Value New OCRnx Value
TOP - 1 TOP BOTTOM BOTTOM + 1
clkI/O
clkTn
(clkI/O/8)104
2543L–AVR–08/10
ATtiny2313
16-bit
Timer/Counter
Register
Description
Timer/Counter1
Control Register A –
TCCR1A
• Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A
• Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B
The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respectively)
behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output
overrides the normal port functionality of the I/O pin it is connected to. If one or both of the
COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding
to the OC1A or OC1B pin must be set in order to enable the output driver.
When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is dependent
of the WGM13:0 bits setting. Table 43 shows the COM1x1:0 bit functionality when the
WGM13:0 bits are set to a Normal or a CTC mode (non-PWM).
Table 44 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM
mode.
Bit 7 6 5 4 3 2 1 0
COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 TCCR1A
Read/Write R/W R/W R/W R/W R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 43. Compare Output Mode, non-PWM
COM1A1/COM1B1 COM1A0/COM1B0 Description
0 0 Normal port operation, OC1A/OC1B
disconnected.
0 1 Toggle OC1A/OC1B on Compare Match.
1 0 Clear OC1A/OC1B on Compare Match (Set
output to low level).
1 1 Set OC1A/OC1B on Compare Match (Set output
to high level).
Table 44. Compare Output Mode, Fast PWM(1)
COM1A1/COM1B1 COM1A0/COM1B0 Description
0 0 Normal port operation, OC1A/OC1B
disconnected.
0 1 WGM13=0: Normal port operation, OC1A/OC1B
disconnected.
WGM13=1: Toggle OC1A on Compare Match,
OC1B reserved.
1 0 Clear OC1A/OC1B on Compare Match, set
OC1A/OC1B at TOP
1 1 Set OC1A/OC1B on Compare Match, clear
OC1A/OC1B at TOP105
2543L–AVR–08/10
ATtiny2313
Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In
this case the compare match is ignored, but the set or clear is done at TOP. See “Fast PWM
Mode” on page 96. for more details.
Table 45 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct
or the phase and frequency correct, PWM mode.
Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See
“Phase Correct PWM Mode” on page 98. for more details.
• Bit 1:0 – WGM11:0: Waveform Generation Mode
Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform
generation to be used, see Table 46. Modes of operation supported by the Timer/Counter
unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types
of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 94.).
Table 45. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1)
COM1A1/COM1B1 COM1A0/COM1B0 Description
0 0 Normal port operation, OC1A/OC1B
disconnected.
0 1 WGM13=0: Normal port operation, OC1A/OC1B
disconnected.
WGM13=1: Toggle OC1A on Compare Match,
OC1B reserved.
1 0 Clear OC1A/OC1B on Compare Match when upcounting.
Set OC1A/OC1B on Compare Match
when downcounting.
1 1 Set OC1A/OC1B on Compare Match when upcounting.
Clear OC1A/OC1B on Compare Match
when downcounting.106
2543L–AVR–08/10
ATtiny2313
Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and
location of these bits are compatible with previous versions of the timer.
Table 46. Waveform Generation Mode Bit Description(1)
Mode WGM13
WGM12
(CTC1)
WGM11
(PWM11)
WGM10
(PWM10)
Timer/Counter Mode of
Operation TOP
Update of
OCR1x at
TOV1 Flag
Set on
0 0 0 0 0 Normal 0xFFFF Immediate MAX
1 0 0 0 1 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM
2 0 0 1 0 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM
3 0 0 1 1 PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM
4 0 1 0 0 CTC OCR1A Immediate MAX
5 0 1 0 1 Fast PWM, 8-bit 0x00FF TOP TOP
6 0 1 1 0 Fast PWM, 9-bit 0x01FF TOP TOP
7 0 1 1 1 Fast PWM, 10-bit 0x03FF TOP TOP
8 1 0 0 0 PWM, Phase and Frequency
Correct
ICR1 BOTTOM BOTTOM
9 1 0 0 1 PWM, Phase and Frequency
Correct
OCR1A BOTTOM BOTTOM
10 1 0 1 0 PWM, Phase Correct ICR1 TOP BOTTOM
11 1 0 1 1 PWM, Phase Correct OCR1A TOP BOTTOM
12 1 1 0 0 CTC ICR1 Immediate MAX
13 1 1 0 1 (Reserved) – – –
14 1 1 1 0 Fast PWM ICR1 TOP TOP
15 1 1 1 1 Fast PWM OCR1A TOP TOP107
2543L–AVR–08/10
ATtiny2313
Timer/Counter1
Control Register B –
TCCR1B
• Bit 7 – ICNC1: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is
activated, the input from the Input Capture pin (ICP1) is filtered. The filter function requires four
successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is
therefore delayed by four Oscillator cycles when the noise canceler is enabled.
• Bit 6 – ICES1: Input Capture Edge Select
This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture
event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICES1 setting, the counter value is copied into the
Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this
can be used to cause an Input Capture Interrupt, if this interrupt is enabled.
When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the
TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture
function is disabled.
• Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be
written to zero when TCCR1B is written.
• Bit 4:3 – WGM13:2: Waveform Generation Mode
See TCCR1A Register description.
• Bit 2:0 – CS12:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure
49 and Figure 50.
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
Bit 7 6 5 4 3 2 1 0
ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 47. Clock Select Bit Description
CS12 CS11 CS10 Description
0 0 0 No clock source (Timer/Counter stopped).
0 0 1 clkI/O/1 (No prescaling)
0 1 0 clkI/O/8 (From prescaler)
0 1 1 clkI/O/64 (From prescaler)
1 0 0 clkI/O/256 (From prescaler)
1 0 1 clkI/O/1024 (From prescaler)
1 1 0 External clock source on T1 pin. Clock on falling edge.
1 1 1 External clock source on T1 pin. Clock on rising edge.108
2543L–AVR–08/10
ATtiny2313
Timer/Counter1
Control Register C –
TCCR1C
• Bit 7 – FOC1A: Force Output Compare for Channel A
• Bit 6 – FOC1B: Force Output Compare for Channel B
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode.
However, for ensuring compatibility with future devices, these bits must be set to zero when
TCCR1A is written when operating in a PWM mode. When writing a logical one to the
FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit.
The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the
FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the
COM1x1:0 bits that determine the effect of the forced compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer
on Compare match (CTC) mode using OCR1A as TOP.
The FOC1A/FOC1B bits are always read as zero.
Timer/Counter1 –
TCNT1H and TCNT1L
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary high byte register
(TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit
Registers” on page 84.
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a compare
match between TCNT1 and one of the OCR1x Registers.
Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock
for all compare units.
Output Compare
Register 1 A –
OCR1AH and OCR1AL
Bit 7 6 5 4 3 2 1 0
FOC1A FOC1B – – – – – – TCCR1C
Read/Write W W R R R R R R
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
TCNT1[15:8] TCNT1H
TCNT1[7:0] TCNT1L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OCR1A[15:8] OCR1AH
OCR1A[7:0] OCR1AL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0109
2543L–AVR–08/10
ATtiny2313
Output Compare
Register 1 B -
OCR1BH and OCR1BL
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC1x pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-
bit registers. See “Accessing 16-bit Registers” on page 84.
Input Capture Register
1 – ICR1H and ICR1L
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit
registers. See “Accessing 16-bit Registers” on page 84.
Timer/Counter
Interrupt Mask
Register – TIMSK
• Bit 7 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector
(See “Interrupts” on page 44.) is executed when the TOV1 flag, located in TIFR, is set.
• Bit 6 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (See “Interrupts” on page 44.) is executed when the OCF1A flag, located in
TIFR, is set.
• Bit 5 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (See “Interrupts” on page 44.) is executed when the OCF1B flag, located in
TIFR, is set.
• Bit 3 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
Bit 7 6 5 4 3 2 1 0
OCR1B[15:8] OCR1BH
OCR1B[7:0] OCR1BL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ICR1[15:8] ICR1H
ICR1[7:0] ICR1L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
TOIE1 OCIE1A OCIE1B – ICIE1 OCIE0B TOIE0 OCIE0A TIMSK
Read/Write R/W R/W R/W R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0110
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ATtiny2313
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector (See “Interrupts” on page 44.) is executed when the ICF1 flag, located in TIFR, is set.
Timer/Counter
Interrupt Flag Register
– TIFR
• Bit 7 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WGM13:0 bits setting. In Normal and CTC modes,
the TOV1 flag is set when the timer overflows. Refer to Table 46 on page 106 for the TOV1 flag
behavior when using another WGM13:0 bit setting.
TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed.
Alternatively, TOV1 can be cleared by writing a logic one to its bit location.
• Bit 6 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register A (OCR1A).
Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A flag.
OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed.
Alternatively, OCF1A can be cleared by writing a logic one to its bit location.
• Bit 5 – OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register B (OCR1B).
Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B flag.
OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed.
Alternatively, OCF1B can be cleared by writing a logic one to its bit location.
• Bit 3 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register
(ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 flag is set when the counter
reaches the TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,
ICF1 can be cleared by writing a logic one to its bit location.
Bit 7 6 5 4 3 2 1 0
TOV1 OCF1A OCF1B – ICF1 OCF0B TOV0 OCF0A TIFR
Read/Write R/W R/W R/W R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0111
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ATtiny2313
USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication device. The main features are:
• Full Duplex Operation (Independent Serial Receive and Transmit Registers)
• Asynchronous or Synchronous Operation
• Master or Slave Clocked Synchronous Operation
• High Resolution Baud Rate Generator
• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
• Odd or Even Parity Generation and Parity Check Supported by Hardware
• Data OverRun Detection
• Framing Error Detection
• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
• Multi-processor Communication Mode
• Double Speed Asynchronous Communication Mode
Overview A simplified block diagram of the USART Transmitter is shown in Figure 53. CPU accessible I/O
Registers and I/O pins are shown in bold.
Figure 53. USART Block Diagram(1)
Note: 1. Refer to Figure 1 on page 2, Table 29 on page 57, and Table 26 on page 55 for USART pin
placement.
PARITY
GENERATOR
UBRR[H:L]
UDR (Transmit)
UCSRA UCSRB UCSRC
BAUD RATE GENERATOR
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER RxD
TxD PIN
CONTROL
UDR (Receive)
PIN
CONTROL
XCK
DATA
RECOVERY
CLOCK
RECOVERY
PIN
CONTROL
TX
CONTROL
RX
CONTROL
PARITY
CHECKER
DATA BUS
OSC
SYNC LOGIC
Clock Generator
Transmitter
Receiver112
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ATtiny2313
The dashed boxes in the block diagram separate the three main parts of the USART (listed from
the top): Clock Generator, Transmitter and Receiver. Control registers are shared by all units.
The Clock Generation logic consists of synchronization logic for external clock input used by
synchronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only
used by synchronous transfer mode. The Transmitter consists of a single write buffer, a serial
Shift Register, Parity Generator and Control logic for handling different serial frame formats. The
write buffer allows a continuous transfer of data without any delay between frames. The
Receiver is the most complex part of the USART module due to its clock and data recovery
units. The recovery units are used for asynchronous data reception. In addition to the recovery
units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level
receive buffer (UDR). The Receiver supports the same frame formats as the Transmitter, and
can detect Frame Error, Data OverRun and Parity Errors.
AVR USART vs. AVR
UART – Compatibility
The USART is fully compatible with the AVR UART regarding:
• Bit locations inside all USART Registers.
• Baud Rate Generation.
• Transmitter Operation.
• Transmit Buffer Functionality.
• Receiver Operation.
However, the receive buffering has two improvements that will affect the compatibility in some
special cases:
• A second Buffer Register has been added. The two Buffer Registers operate as a circular
FIFO buffer. Therefore the UDR must only be read once for each incoming data! More
important is the fact that the error flags (FE and DOR) and the ninth data bit (RXB8) are
buffered with the data in the receive buffer. Therefore the status bits must always be read
before the UDR Register is read. Otherwise the error status will be lost since the buffer state
is lost.
• The Receiver Shift Register can now act as a third buffer level. This is done by allowing the
received data to remain in the serial Shift Register (see Figure 53) if the Buffer Registers are
full, until a new start bit is detected. The USART is therefore more resistant to Data OverRun
(DOR) error conditions.
The following control bits have changed name, but have same functionality and register location:
• CHR9 is changed to UCSZ2.
• OR is changed to DOR.
Clock Generation The Clock Generation logic generates the base clock for the Transmitter and Receiver. The
USART supports four modes of clock operation: Normal asynchronous, Double Speed asynchronous,
Master synchronous and Slave synchronous mode. The UMSEL bit in USART
Control and Status Register C (UCSRC) selects between asynchronous and synchronous operation.
Double Speed (asynchronous mode only) is controlled by the U2X found in the UCSRA
Register. When using synchronous mode (UMSEL = 1), the Data Direction Register for the XCK
pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave
mode). The XCK pin is only active when using synchronous mode.
Figure 54 shows a block diagram of the clock generation logic.113
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ATtiny2313
Figure 54. Clock Generation Logic, Block Diagram
Signal description:
txclk Transmitter clock (Internal Signal).
rxclk Receiver base clock (Internal Signal).
xcki Input from XCK pin (internal Signal). Used for synchronous slave operation.
xcko Clock output to XCK pin (Internal Signal). Used for synchronous master
operation.
fosc XTAL pin frequency (System Clock).
Internal Clock
Generation – The
Baud Rate Generator
Internal clock generation is used for the asynchronous and the synchronous master modes of
operation. The description in this section refers to Figure 54.
The USART Baud Rate Register (UBRR) and the down-counter connected to it function as a
programmable prescaler or baud rate generator. The down-counter, running at system clock
(fosc), is loaded with the UBRR value each time the counter has counted down to zero or when
the UBRRL Register is written. A clock is generated each time the counter reaches zero. This
clock is the baud rate generator clock output (= fosc/(UBRR+1)). The Transmitter divides the
baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator output
is used directly by the Receiver’s clock and data recovery units. However, the recovery units
use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the
UMSEL, U2X and DDR_XCK bits.
Table 48 contains equations for calculating the baud rate (in bits per second) and for calculating
the UBRR value for each mode of operation using an internally generated clock source.
Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps)
Prescaling
Down-Counter /2
UBRR
/4 /2
fosc
UBRR+1
Sync
Register
OSC
XCK
Pin
txclk
U2X
UMSEL
DDR_XCK
0
1
0
1
xcki
xcko
DDR_XCK rxclk 0
1
1
0
Edge
Detector
UCPOL
Table 48. Equations for Calculating Baud Rate Register Setting
Operating Mode
Equation for Calculating
Baud Rate(1)
Equation for Calculating
UBRR Value
Asynchronous Normal
mode (U2X = 0)
Asynchronous Double
Speed mode (U2X = 1)
Synchronous Master
mode
BAUD f
OSC
16( ) UBRR + 1 = -------------------------------------- UBRR f
OSC
16BAUD = ------------------------ – 1
BAUD f
OSC
8( ) UBRR + 1 = ----------------------------------- UBRR f
OSC
8BAUD = -------------------- – 1
BAUD f
OSC
2( ) UBRR + 1 = ----------------------------------- UBRR f
OSC
2BAUD = -------------------- – 1114
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ATtiny2313
BAUD Baud rate (in bits per second, bps)
fOSC System Oscillator clock frequency
UBRR Contents of the UBRRH and UBRRL Registers, (0-4095)
Some examples of UBRR values for some system clock frequencies are found in Table 56 (see
page 134).
Double Speed
Operation (U2X)
The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only has effect
for the asynchronous operation. Set this bit to zero when using synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling
the transfer rate for asynchronous communication. Note however that the Receiver will in this
case only use half the number of samples (reduced from 16 to 8) for data sampling and clock
recovery, and therefore a more accurate baud rate setting and system clock are required when
this mode is used. For the Transmitter, there are no downsides.
External Clock External clocking is used by the synchronous slave modes of operation. The description in this
section refers to Figure 54 for details.
External clock input from the XCK pin is sampled by a synchronization register to minimize the
chance of meta-stability. The output from the synchronization register must then pass through
an edge detector before it can be used by the Transmitter and Receiver. This process introduces
a two CPU clock period delay and therefore the maximum external XCK clock frequency
is limited by the following equation:
Note that fosc depends on the stability of the system clock source. It is therefore recommended to
add some margin to avoid possible loss of data due to frequency variations.
Synchronous Clock
Operation
When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input
(Slave) or clock output (Master). The dependency between the clock edges and data sampling
or data change is the same. The basic principle is that data input (on RxD) is sampled at the
opposite XCK clock edge of the edge the data output (TxD) is changed.
Figure 55. Synchronous Mode XCK Timing.
The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is
used for data change. As Figure 55 shows, when UCPOL is zero the data will be changed at risf
XCK
f
OSC
4 < -----------
RxD / TxD
XCK
RxD / TxD
UCPOL = 0 XCK
UCPOL = 1
Sample
Sample115
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ATtiny2313
ing XCK edge and sampled at falling XCK edge. If UCPOL is set, the data will be changed at
falling XCK edge and sampled at rising XCK edge.
Frame Formats A serial frame is defined to be one character of data bits with synchronization bits (start and stop
bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of
the following as valid frame formats:
• 1 start bit
• 5, 6, 7, 8, or 9 data bits
• no, even or odd parity bit
• 1 or 2 stop bits
A frame starts with the start bit followed by the least significant data bit. Then the next data bits,
up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit
is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can
be directly followed by a new frame, or the communication line can be set to an idle (high) state.
Figure 56 illustrates the possible combinations of the frame formats. Bits inside brackets are
optional.
Figure 56. Frame Formats
St Start bit, always low.
(n) Data bits (0 to 8).
P Parity bit. Can be odd or even.
Sp Stop bit, always high.
IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be
high.
The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in UCSRB
and UCSRC. The Receiver and Transmitter use the same setting. Note that changing the setting
of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter.
The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame. The
USART Parity mode (UPM1:0) bits enable and set the type of parity bit. The selection between
one or two stop bits is done by the USART Stop Bit Select (USBS) bit. The Receiver ignores the
second stop bit. An FE (Frame Error) will therefore only be detected in the cases where the first
stop bit is zero.
Parity Bit Calculation The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the
result of the exclusive or is inverted. The relation between the parity bit and data bits is as
follows:
Peven Parity bit using even parity
Podd Parity bit using odd parity
(IDLE) St Sp1 [Sp2] 0 2 3 4 [5] [6] [7] [8] [P] 1 (St / IDLE)
FRAME
Peven dn – 1 … d3 d2 d1 d0 0
Podd
⊕⊕⊕⊕⊕⊕
dn – 1 … d3 d2 d1 d0 ⊕⊕⊕⊕⊕⊕ 1
=
=116
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dn Data bit n of the character
If used, the parity bit is located between the last data bit and first stop bit of a serial frame.
USART
Initialization
The USART has to be initialized before any communication can take place. The initialization process
normally consists of setting the baud rate, setting frame format and enabling the
Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the
Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the
initialization.
Before doing a re-initialization with changed baud rate or frame format, be sure that there are no
ongoing transmissions during the period the registers are changed. The TXC flag can be used to
check that the Transmitter has completed all transfers, and the RXC flag can be used to check
that there are no unread data in the receive buffer. Note that the TXC flag must be cleared
before each transmission (before UDR is written) if it is used for this purpose.
The following simple USART initialization code examples show one assembly and one C function
that are equal in functionality. The examples assume asynchronous operation using polling
(no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter.
For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16
Registers.
Note: 1. The example code assumes that the part specific header file is included.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
Assembly Code Example(1)
USART_Init:
; Set baud rate
out UBRRH, r17
out UBRRL, r16
; Enable receiver and transmitter
ldi r16, (1<>8);
UBRRL = (unsigned char)baud;
/* Enable receiver and transmitter */
UCSRB = (1<> 1) & 0x01;
return ((resh << 8) | resl);
}123
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Note: 1. The example code assumes that the part specific header file is included.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
The receive function example reads all the I/O Registers into the Register File before any computation
is done. This gives an optimal receive buffer utilization since the buffer location read will
be free to accept new data as early as possible.
Receive Compete Flag
and Interrupt
The USART Receiver has one flag that indicates the Receiver state.
The Receive Complete (RXC) flag indicates if there are unread data present in the receive buffer.
This flag is one when unread data exist in the receive buffer, and zero when the receive
buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXEN = 0),
the receive buffer will be flushed and consequently the RXC bit will become zero.
When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART Receive
Complete interrupt will be executed as long as the RXC flag is set (provided that global interrupts
are enabled). When interrupt-driven data reception is used, the receive complete routine
must read the received data from UDR in order to clear the RXC flag, otherwise a new interrupt
will occur once the interrupt routine terminates.
Receiver Error Flags The USART Receiver has three error flags: Frame Error (FE), Data OverRun (DOR) and Parity
Error (UPE). All can be accessed by reading UCSRA. Common for the error flags is that they are
located in the receive buffer together with the frame for which they indicate the error status. Due
to the buffering of the error flags, the UCSRA must be read before the receive buffer (UDR),
since reading the UDR I/O location changes the buffer read location. Another equality for the
error flags is that they can not be altered by software doing a write to the flag location. However,
all flags must be set to zero when the UCSRA is written for upward compatibility of future
USART implementations. None of the error flags can generate interrupts.
The Frame Error (FE) flag indicates the state of the first stop bit of the next readable frame
stored in the receive buffer. The FE flag is zero when the stop bit was correctly read (as one),
and the FE flag will be one when the stop bit was incorrect (zero). This flag can be used for
detecting out-of-sync conditions, detecting break conditions and protocol handling. The FE flag
is not affected by the setting of the USBS bit in UCSRC since the Receiver ignores all, except for
the first, stop bits. For compatibility with future devices, always set this bit to zero when writing to
UCSRA.
The Data OverRun (DOR) flag indicates data loss due to a receiver buffer full condition. A Data
OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in
the Receive Shift Register, and a new start bit is detected. If the DOR flag is set there was one
or more serial frame lost between the frame last read from UDR, and the next frame read from
UDR. For compatibility with future devices, always write this bit to zero when writing to UCSRA.
The DOR flag is cleared when the frame received was successfully moved from the Shift Register
to the receive buffer.
The Parity Error (UPE) Flag indicates that the next frame in the receive buffer had a Parity Error
when received. If Parity Check is not enabled the UPE bit will always be read zero. For compatibility
with future devices, always set this bit to zero when writing to UCSRA. For more details see
“Parity Bit Calculation” on page 115 and “Parity Checker” on page 124.124
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ATtiny2313
Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of Parity
Check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the Parity
Checker calculates the parity of the data bits in incoming frames and compares the result with
the parity bit from the serial frame. The result of the check is stored in the receive buffer together
with the received data and stop bits. The Parity Error (UPE) flag can then be read by software to
check if the frame had a Parity Error.
The UPE bit is set if the next character that can be read from the receive buffer had a Parity
Error when received and the Parity Checking was enabled at that point (UPM1 = 1). This bit is
valid until the receive buffer (UDR) is read.
Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing
receptions will therefore be lost. When disabled (i.e., the RXEN is set to zero) the Receiver will
no longer override the normal function of the RxD port pin. The Receiver buffer FIFO will be
flushed when the Receiver is disabled. Remaining data in the buffer will be lost
Flushing the Receive
Buffer
The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be
emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal
operation, due to for instance an error condition, read the UDR I/O location until the RXC flag is
cleared. The following code example shows how to flush the receive buffer.
Note: 1. The example code assumes that the part specific header file is included.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
Asynchronous
Data Reception
The USART includes a clock recovery and a data recovery unit for handling asynchronous data
reception. The clock recovery logic is used for synchronizing the internally generated baud rate
clock to the incoming asynchronous serial frames at the RxD pin. The data recovery logic samples
and low pass filters each incoming bit, thereby improving the noise immunity of the
Receiver. The asynchronous reception operational range depends on the accuracy of the internal
baud rate clock, the rate of the incoming frames, and the frame size in number of bits.
Assembly Code Example(1)
USART_Flush:
sbis UCSRA, RXC
ret
in r16, UDR
rjmp USART_Flush
C Code Example(1)
void USART_Flush( void )
{
unsigned char dummy;
while ( UCSRA & (1< 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
t
BVDV BS1 Valid to DATA valid 0 250 ns
tOLDV OE Low to DATA Valid 250 ns
tOHDZ OE High to DATA Tri-stated 250 ns
Table 76. Parallel Programming Characteristics, VCC = 5V ± 10% (Continued)
Symbol Parameter Min Typ Max Units
VCC
GND
XTAL1
SCK
MISO
MOSI
RESET
+1.8 - 5.5V173
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ATtiny2313
Serial Programming
Algorithm
When writing serial data to the ATtiny2313, data is clocked on the rising edge of SCK.
When reading data from the ATtiny2313, data is clocked on the falling edge of SCK. See Figure
79, Figure 80 and Table 79 for timing details.
To program and verify the ATtiny2313 in the serial programming mode, the following sequence
is recommended (See four byte instruction formats in Table 78 on page 174):
1. Power-up sequence:
Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems,
the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
2. Wait for at least 20 ms and enable serial programming by sending the Programming
Enable serial instruction to pin MOSI.
3. The serial programming instructions will not work if the communication is out of synchronization.
When in sync. the second byte (0x53), will echo back when issuing the third
byte of the Programming Enable instruction. Whether the echo is correct or not, all four
bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a
positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The memory page is loaded one byte at a
time by supplying the 4 LSB of the address and data together with the Load Program
Memory Page instruction. To ensure correct loading of the page, the data low byte must
be loaded before data high byte is applied for a given address. The Program Memory
Page is stored by loading the Write Program Memory Page instruction with the 6 MSB of
the address. If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH before
issuing the next page. (See Table 77 on page 174.) Accessing the serial programming
interface before the Flash write operation completes can result in incorrect programming.
5. A: The EEPROM array is programmed one byte at a time by supplying the address and
data together with the appropriate Write instruction. An EEPROM memory location is first
automatically erased before new data is written. If polling (RDY/BSY) is not used, the user
must wait at least tWD_EEPROM before issuing the next byte. (See Table 77 on page 174.)
In a chip erased device, no 0xFFs in the data file(s) need to be programmed.
B: The EEPROM array is programmed one page at a time. The Memory page is loaded
one byte at a time by supplying the 2 LSB of the address and data together with the Load
EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading
the Write EEPROM Memory Page Instruction with the 5 MSB of the address. When using
EEPROM page access only byte locations loaded with the Load EEPROM Memory Page
instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is
not used, the used must wait at least tWD_EEPROM before issuing the next page (See Table
77 on page 174). In a chip erased device, no 0xFF in the data file(s) need to be
programmed.
6. Any memory location can be verified by using the Read instruction which returns the content
at the selected address at serial output MISO.
7. At the end of the programming session, RESET can be set high to commence normal
operation.
8. Power-off sequence (if needed):
Set RESET to “1”.
Turn VCC power off.174
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Figure 79. Serial Programming Waveforms
Table 77. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
Symbol Minimum Wait Delay
tWD_FLASH 4.5 ms
tWD_EEPROM 4.0 ms
tWD_ERASE 9.0 ms
tWD_FUSE 4.5 ms
MSB
MSB
LSB
LSB
SERIAL CLOCK INPUT
(SCK)
SERIAL DATA INPUT
(MOSI)
(MISO)
SAMPLE
SERIAL DATA OUTPUT
Table 78. Serial Programming Instruction Set
Instruction
Instruction Format
Byte 1 Byte 2 Byte 3 Byte4 Operation
Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after
RESET goes low.
Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash.
Read Program Memory 0010 H000 0000 00aa bbbb bbbb oooo oooo Read H (high or low) data o from
Program memory at word address a:b.
Load Program Memory Page 0100 H000 000x xxxx xxxx bbbb iiii iiii Write H (high or low) data i to Program
Memory page at word address b. Data
low byte must be loaded before Data
high byte is applied within the same
address.
Write Program Memory Page 0100 1100 0000 00aa bbbb xxxx xxxx xxxx Write Program Memory Page at
address a:b.
Read EEPROM Memory 1010 0000 000x xxxx xbbb bbbb oooo oooo Read data o from EEPROM memory at
address b.
Write EEPROM Memory 1100 0000 000x xxxx xbbb bbbb iiii iiii Write data i to EEPROM memory at
address b.
Load EEPROM Memory
Page (page access)
1100 0001 0000 0000 0000 00bb iiii iiii Load data i to EEPROM memory page
buffer. After data is loaded, program
EEPROM page.
Write EEPROM Memory
Page (page access)
1100 0010 00xx xxxx xbbb bb00 xxxx xxxx
Write EEPROM page at address b.175
2543L–AVR–08/10
ATtiny2313
Note: a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care
Read Lock bits 0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock bits. “0” = programmed, “1”
= unprogrammed. See Table 64 on
page 158 for details.
Write Lock bits 1010 1100 111x xxxx xxxx xxxx 11ii iiii Write Lock bits. Set bits = “0” to
program Lock bits. See Table 64 on
page 158 for details.
Read Signature Byte 0011 0000 000x xxxx xxxx xxbb oooo oooo Read Signature Byte o at address b.
Write Fuse bits 1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to
unprogram.
Write Fuse High bits 1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to
unprogram.
Write Extended Fuse Bits 1010 1100 1010 0100 xxxx xxxx xxxx xxxi Set bits = “0” to program, “1” to
unprogram.
Read Fuse bits 0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fuse bits. “0” = programmed, “1”
= unprogrammed.
Read Fuse High bits 0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fuse High bits. “0” = programmed,
“1” = unprogrammed.
Read Extended Fuse Bits 0101 0000 0000 1000 xxxx xxxx oooo oooo Read Extended Fuse bits. “0” = programmed,
“1” = unprogrammed.
Read Calibration Byte 0011 1000 000x xxxx 0000 000b oooo oooo Read Calibration Byte at address b.
Poll RDY/BSY 1111 0000 0000 0000 xxxx xxxx xxxx xxxo If o = “1”, a programming operation is
still busy. Wait until this bit returns to
“0” before applying another command.
Table 78. Serial Programming Instruction Set
Instruction
Instruction Format
Byte 1 Byte 2 Byte 3 Byte4 Operation176
2543L–AVR–08/10
ATtiny2313
Serial Programming
Characteristics
Figure 80. Serial Programming Timing
Note: 1. 2 tCLCL for fck < 12 MHz, 3 tCLCL for fck >= 12 MHz
Table 79. Serial Programming Characteristics, TA = -40°C to +85°C, VCC = 2.7V - 5.5V (Unless
Otherwise Noted)
Symbol Parameter Min Typ Max Units
1/tCLCL Oscillator Frequency (ATtiny2313L) 0 10 MHz
tCLCL Oscillator Period (ATtiny2313L) 125 ns
1/tCLCL
Oscillator Frequency (ATtiny2313, VCC = 4.5V -
5.5V) 0 20 MHz
tCLCL
Oscillator Period (ATtiny2313, VCC = 4.5V -
5.5V) 67 ns
tSHSL SCK Pulse Width High 2 tCLCL* ns
tSLSH SCK Pulse Width Low 2 tCLCL* ns
tOVSH MOSI Setup to SCK High tCLCL ns
tSHOX MOSI Hold after SCK High 2 tCLCL ns
tSLIV SCK Low to MISO Valid 100 ns
MOSI
MISO
SCK
t
OVSH
t
SHSL
t t
SHOX SLSH
t
SLIV177
2543L–AVR–08/10
ATtiny2313
Electrical Characteristics
Absolute Maximum Ratings*
DC Characteristics
Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature ..................................... -65°C to +150°C
Voltage on any Pin except RESET
with respect to Ground ................................-0.5V to VCC+0.5V
Voltage on RESET with respect to Ground......-0.5V to +13.0V
Maximum Operating Voltage ............................................ 6.0V
DC Current per I/O Pin ............................................... 40.0 mA
DC Current VCC and GND Pins ................................ 200.0 mA
TA = -40°C to +85°C, VCC = 1.8V to 5.5V (unless otherwise noted)(1)
Symbol Parameter Condition Min. Typ.(2) Max. Units
VIL
Input Low Voltage except
XTAL1 and RESET pin
VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V -0.5 0.2VCC(3)
0.3VCC(3) V
VIH
Input High-voltage except
XTAL1 and RESET pins
VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V
0.7VCC(4)
0.6VCC(4) VCC +0.5 V
VIL1
Input Low Voltage
XTAL1 pin
VCC = 1.8V - 5.5V -0.5 0.1VCC(3) V
VIH1
Input High-voltage
XTAL1 pin
VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V
0.8VCC(4)
0.7VCC(4) VCC +0.5 V
VIL2
Input Low Voltage
RESET pin VCC = 1.8V - 5.5V -0.5 0.2VCC(3) V
VIH2
Input High-voltage
RESET pin VCC = 1.8V - 5.5V 0.9VCC(4) VCC +0.5 V
VIL3
Input Low Voltage
RESET pin as I/O
VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V -0.5 0.2VCC(3)
0.3VCC(3) V
VIH3
Input High-voltage
RESET pin as I/O
VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V
0.7VCC(4)
0.6VCC(4) VCC +0.5 V
VOL
Output Low Voltage(5)
(Port A, Port B, Port D)
I
OL = 20 mA, VCC = 5V
IOL = 10 mA, VCC = 3V
0.7
0.5
V
V
VOH
Output High-voltage(6)
(Port A, Port B, Port D)
I
OH = -20 mA, VCC = 5V
IOH = -10 mA, VCC = 3V
4.2
2.5
V
V
IIL
Input Leakage
Current I/O Pin
VCC = 5.5V, pin low
(absolute value) 1 µA
IIH
Input Leakage
Current I/O Pin
VCC = 5.5V, pin high
(absolute value) 1 µA
RRST Reset Pull-up Resistor 30 60 kΩ
Rpu I/O Pin Pull-up Resistor 20 50 kΩ178
2543L–AVR–08/10
ATtiny2313
Notes: 1. All DC Characteristics contained in this data sheet are based on simulation and characterization of other AVR microcontrollers
manufactured in the same process technology. These values are preliminary values representing design targets, and
will be updated after characterization of actual silicon.
2. Typical values at +25°C.
3. “Max” means the highest value where the pin is guaranteed to be read as low.
4. “Min” means the lowest value where the pin is guaranteed to be read as high.
5. Although each I/O port can sink more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state
conditions (non-transient), the following must be observed:
1] The sum of all IOL, for all ports, should not exceed 60 mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test condition.
6. Although each I/O port can source more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state
conditions (non-transient), the following must be observed:
1] The sum of all IOH, for all ports, should not exceed 60 mA.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current
greater than the listed test condition.
ICC
Power Supply Current
Active 1MHz, VCC = 2V 0.35 mA
Active 4MHz, VCC = 3V 2 mA
Active 8MHz, VCC = 5V 6 mA
Idle 1MHz, VCC = 2V 0.08 0.2 mA
Idle 4MHz, VCC = 3V 0.41 1 mA
Idle 8MHz, VCC = 5V 1.6 3 mA
Power-down mode
WDT enabled, VCC = 3V < 3 6 µA
WDT disabled, VCC = 3V < 0.5 2 µA
VACIO
Analog Comparator
Input Offset Voltage
VCC = 5V
Vin = VCC/2 < 10 40 mV
IACLK
Analog Comparator
Input Leakage Current
VCC = 5V
Vin = VCC/2 -50 50 nA
t
ACPD
Analog Comparator
Propagation Delay
VCC = 2.7V
VCC = 5.0V
750
500 ns
TA = -40°C to +85°C, VCC = 1.8V to 5.5V (unless otherwise noted)(1) (Continued)
Symbol Parameter Condition Min. Typ.(2) Max. Units179
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ATtiny2313
External Clock
Drive Waveforms
Figure 81. External Clock Drive Waveforms
External Clock
Drive
VIL1
VIH1
Table 80. External Clock Drive (Estimated Values)
Symbol Parameter
VCC = 1.8 - 5.5V VCC = 2.7 - 5.5V VCC = 4.5 - 5.5V
Min. Max. Min. Max. Min. Max. Units
1/tCLCL
Oscillator
Frequency 0 4 0 10 0 20 MHz
tCLCL Clock Period 250 100 50 ns
tCHCX High Time 100 40 20 ns
tCLCX Low Time 100 40 20 ns
tCLCH Rise Time 2.0 1.6 0.5 μs
tCHCL Fall Time 2.0 1.6 0.5 μs
ΔtCLCL
Change in
period from one
clock cycle to
the next
2 2 2%180
2543L–AVR–08/10
ATtiny2313
Maximum Speed
vs. VCC
Maximum frequency is dependent on VCC. As shown in Figure 82 and Figure 83, the Maximum
Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V and between 2.7V < VCC < 4.5V.
Figure 82. Maximum Frequency vs. VCC, ATtiny2313V
Figure 83. Maximum Frequency vs. VCC, ATtiny2313
10 MHz
4 MHz
1.8V 2.7V 5.5V
Safe Operating Area
20 MHz
10 MHz
2.7V 4.5V 5.5V
Safe Operating Area181
2543L–AVR–08/10
ATtiny2313
ATtiny2313
Typical
Characteristics
The following charts show typical behavior. These figures are not tested during manufacturing.
All current consumption measurements are performed with all I/O pins configured as inputs and
with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock
source.
The power consumption in Power-down mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage, operating
frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature.
The dominating factors are operating voltage and frequency.
The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where
CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to
function properly at frequencies higher than the ordering code indicates.
The difference between current consumption in Power-down mode with Watchdog Timer
enabled and Power-down mode with Watchdog Timer disabled represents the differential current
drawn by the Watchdog Timer.
Active Supply Current Figure 84. Active Supply Current vs. Frequency (0.1 - 1.0 MHz)
ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY
0.1 - 1.0 MHz
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0
0.2
0.4
0.6
0.8
1
1.2
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)
ICC (mA)182
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ATtiny2313
Figure 85. Active Supply Current vs. Frequency (1 - 20 MHz)
Figure 86. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY
1 - 20 MHz
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0
2
4
6
8
10
12
14
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)
ICC (mA)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 8 MHz
85 ˚C
25 ˚C
-40 ˚C
0
1
2
3
4
5
6
7
8
9
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (mA)183
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ATtiny2313
Figure 87. Active Supply Current vs. VCC (Internal RC Oscillator, 4 MHz)
Figure 88. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)
ACTIVE SUPPLY CURRENT vs. Vcc
INTERNAL RC OSCILLATOR, 4 MHz
85 °C
25 °C
-40 °C
0
1
2
3
4
5
6
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Vcc (V)
Icc (mA)
ACTIVE SUPPLY CURRENT vs. Vcc
INTERNAL RC OSCILLATOR, 1 MHz
85 °C
25 °C
-40 °C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Vcc (V)
Icc (mA)184
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ATtiny2313
Figure 89. Active Supply Current vs. VCC (Internal RC Oscillator, 0.5 MHz)
Figure 90. Active Supply Current vs. VCC (Internal RC Oscillator, 128 KHz)
ACTIVE SUPPLY CURRENT vs. Vcc
INTERNAL RC OSCILLATOR, 0.5 MHz
85 °C
25 °C
-40 °C
0
0.2
0.4
0.6
0.8
1
1.2
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Vcc (V)
Icc (mA)
ACTIVE SUPPLY CURRENT vs. Vcc
INTERNAL RC OSCILLATOR, 128 KHz
85 °C
25 °C
-40 °C
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
Vcc (V)
Icc (mA)185
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ATtiny2313
Idle Supply Current Figure 91. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz)
Figure 92. Idle Supply Current vs. Frequency (1 - 20 MHz)
IDLE SUPPLY CURRENT vs. FREQUENCY
0.1 - 1.0 MHz
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0
0.05
0.1
0.15
0.2
0.25
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)
Icc (m A)
IDLE SUPPLY CURRENT vs. FREQUENCY
1 - 20 MHz
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)
Icc (mA)186
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ATtiny2313
Figure 93. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)
Figure 94. Idle Supply Current vs. VCC (Internal RC Oscillator, 4 MHz)
IDLE SUPPLY CURRENT vs. Vcc
INTERNAL RC OSCILLATOR, 8 MHz
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
3
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Vcc (V)
Icc (mA)
IDLE SUPPLY CURRENT vs. Vcc
INTERNAL RC OSCILLATOR, 4 MHz
85 °C
25 °C
-40 °C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Vcc (V)
Icc (mA)187
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ATtiny2313
Figure 95. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)
Figure 96. Idle Supply Current vs. VCC (Internal RC Oscillator, 0.5 MHz)
IDLE SUPPLY CURRENT vs. Vcc
INTERNAL RC OSCILLATOR, 1 MHz
85 °C
25 °C
-40 °C
0
0.1
0.2
0.3
0.4
0.5
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Vcc (V)
Icc (mA)
IDLE SUPPLY CURRENT vs. Vcc
INTERNAL RC OSCILLATOR, 0.5 MHz
85 °C
25 °C
-40 °C
0
0.05
0.1
0.15
0.2
0.25
0.3
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Vcc (V)
Icc (mA)188
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ATtiny2313
Figure 97. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 KHz)
Power-down Supply
Current
Figure 98. Power-down Supply Current vs. VCC (Watchdog Timer Disabled)
IDLE SUPPLY CURRENT vs. Vcc
INTERNAL RC OSCILLATOR, 128 KHz
85 °C
25 °C
-40 °C
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Vcc (V)
Icc (m A)
POWER-DOWN SUPPLY CURRENT vs. Vcc
WATCHDOG TIMER DISABLED
85 °C
25 °C
-40 °C
0
0.25
0.5
0.75
1
1.25
1.5
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Vcc (V)
Icc (uA)189
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ATtiny2313
Figure 99. Power-down Supply Current vs. VCC (Watchdog Timer Enabled)
Standby Supply
Current
Figure 100. Standby Supply Current vs. VCC
POWER-DOWN SUPPLY CURRENT vs. Vcc
WATCHDOG TIMER ENABLED
85 °C
25 °C
-40 °C
0
2
4
6
8
10
12
14
16
18
20
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Vcc (V)
Icc (uA)
STANDBY SUPPLY CURRENT vs. Vcc
455KHz Res
2MHz Xtal
2MHz Res
1MHz Res
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Vcc (V)
Icc (m A)190
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ATtiny2313
Pin Pull-up Figure 101. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)
Figure 102. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 5V
85 °C 25 °C
-40 °C
0
20
40
60
80
100
120
140
160
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VOP (V)
IOP (uA )
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 2.7V
85 °C 25 °C
-40 °C
0
10
20
30
40
50
60
70
80
0 0.5 1 1.5 2 2.5 3
VOP (V)
IOP (uA)191
2543L–AVR–08/10
ATtiny2313
Figure 103. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
Figure 104. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
Vcc = 5V
85 °C
25 °C
-40 °C
0
20
40
60
80
100
120
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VRESET (V)
IRESET (uA)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
Vcc = 2.7V
85 °C
-40 °C 25 °C
0
10
20
30
40
50
60
0 0.5 1 1.5 2 2.5 3
VRESET (V)
IRESET (uA)192
2543L–AVR–08/10
ATtiny2313
Pin Driver Strength Figure 105. I/O Pin Source Current vs. Output Voltage (VCC = 5V)
Figure 106. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
Vcc = 5V
85 °C
25 °C
-40 °C
0
10
20
30
40
50
60
70
80
90
3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5
VOH (V)
IOH (mA)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
Vcc = 2.7V
85 °C
25 °C
-40 °C
0
5
10
15
20
25
30
35
0.5 1 1.5 2 2.5 3
VOH (V)
IOH (mA)193
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ATtiny2313
Figure 107. I/O Pin Source Current vs. Output Voltage (VCC = 1.8V)
Figure 108. I/O Pin Sink Current vs. Output Voltage (VCC = 5V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
Vcc = 1.8V
85 °C
25 °C
-40 °C
0
1
2
3
4
5
6
7
8
9
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VOH (V)
IOH (mA)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
Vcc = 5V
85 °C
25 °C
-40 °C
0
10
20
30
40
50
60
70
80
90
100
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VOL (V)
IOL (mA)194
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ATtiny2313
Figure 109. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V)
Figure 110. I/O Pin Sink Current vs. Output Voltage (VCC = 1.8V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
Vcc = 2.7V
85 °C
25 °C
-40 °C
0
5
10
15
20
25
30
35
40
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VOL (V)
IOL (mA)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
Vcc = 1.8V
85 °C
25 °C
-40 °C
0
2
4
6
8
10
12
14
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VOL (V)
IOL (mA)195
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ATtiny2313
Figure 111. Reset I/O Pin Source Current vs. Output Voltage (VCC = 5V)
Figure 112. Reset I/O Pin Source Current vs. Output Voltage (VCC = 2.7V)
RESET I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
Vcc = 5V
85 °C
25 °C
-40 °C
0
2
4
6
8
10
12
14
16
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VOH (V)
Current (mA)
RESET I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
Vcc = 2.7V
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0 0.5 1 1.5 2 2.5 3
VOH (V)
Current (m A)196
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ATtiny2313
Figure 113. Reset I/O Pin Source Current vs. Output Voltage (VCC = 1.8V)
Figure 114. Reset I/O Pin Sink Current vs. Output Voltage (VCC = 5V)
RESET I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
Vcc = 1.8V
85 °C
25 °C
-40 °C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VOH (V)
Current (mA)
RESET I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
Vcc = 5V
85 °C
25 °C
-40 °C
0
2
4
6
8
10
12
14
16
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VOL (V)
Current (mA)197
2543L–AVR–08/10
ATtiny2313
Figure 115. Reset I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V)
Figure 116. Reset I/O Pin Sink Current vs. Output Voltage (VCC = 1.8V)
RESET I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
Vcc = 2.7V
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VOL (V)
Current (mA)
RESET I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
Vcc = 1.8V
85 °C
25 °C
-40 °C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VOL (V)
Current (mA)198
2543L–AVR–08/10
ATtiny2313
Pin Thresholds and
Hysteresis
Figure 117. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”)
Figure 118. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”)
I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc
VIH, IO PIN READ AS '1'
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
3
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Threshold (V)
I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc
VIL, IO PIN READ AS '0'
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
3
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Threshold (V)199
2543L–AVR–08/10
ATtiny2313
Figure 119. Reset I/O Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”)
Figure 120. Reset I/O Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”)
RESET I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc
VIH, IO PIN READ AS '1'
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
3
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Vcc (V)
Threshold (V)
RESET I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc
VIL, IO PIN READ AS '0'
85°C
25°C
-40°C
0
0.5
1
1.5
2
2.5
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Vcc (V)
Threshold (V)200
2543L–AVR–08/10
ATtiny2313
Figure 121. Reset I/O Input Pin Hysteresis vs. VCC
Figure 122. Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”)
RESET I/O INPUT PIN HYSTERESIS vs. Vcc
85 °C
25 °C
-40 °C
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Input Hysteresis (V)
RESET INPUT THRESHOLD VOLTAGE vs. Vcc
VIH, IO PIN READ AS '1'
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Threshold (V)201
2543L–AVR–08/10
ATtiny2313
Figure 123. Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”)
Figure 124. Reset Input Pin Hysteresis vs. VCC
RESET INPUT THRESHOLD VOLTAGE vs. Vcc
VIL, IO PIN READ AS '0'
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Vcc (V)
Threshold (V)
RESET INPUT PIN HYSTERESIS vs. Vcc
85 °C
25 °C
-40 °C
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Vcc (V)
Input Hysteresis (V)202
2543L–AVR–08/10
ATtiny2313
BOD Thresholds and
Analog Comparator
Offset
Figure 125. BOD Thresholds vs. Temperature (BOD Level is 4.3V)
Figure 126. BOD Thresholds vs. Temperature (BOD Level is 2.7V)
BOD THRESHOLDS vs. TEMPERATURE
BODLEVEL IS 4.3V
4.25
4.3
4.35
4.4
4.45
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature (C)
Thres hol d (V )
Rising Vcc
Falling Vcc
BOD THRESHOLDS vs. TEMPERATURE
BODLEVEL IS 2.7V
2.65
2.7
2.75
2.8
2.85
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature (C)
Threshold (V)
Rising Vcc
Falling Vcc203
2543L–AVR–08/10
ATtiny2313
Figure 127. BOD Thresholds vs. Temperature (BOD Level is 1.8V)
Internal Oscillator
Speed
Figure 128. Watchdog Oscillator Frequency vs. VCC
BOD THRESHOLDS vs. TEMPERATURE
BODLEVEL IS 1.8V
Rising Vcc
Falling Vcc
1.78
1.8
1.82
1.84
1.86
1.88
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature (C)
Threshold (V)
WATCHDOG OSCILLATOR FREQUENCY vs. VCC
85 °C
25 °C
-40 °C
0.095
0.096
0.097
0.098
0.099
0.1
0.101
0.102
0.103
0.104
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
FRC (M Hz)204
2543L–AVR–08/10
ATtiny2313
Figure 129. Watchdog Oscillator Frequency vs. Temperature
Figure 130. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature
WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0.096
0.097
0.098
0.099
0.1
0.101
0.102
0.103
0.104
0.105
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature (°C)
FRC (MHz)
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
7.7
7.8
7.9
8
8.1
8.2
8.3
8.4
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature (°C)
FRC (MHz )205
2543L–AVR–08/10
ATtiny2313
Figure 131. Calibrated 8 MHz RC Oscillator Frequency vs. VCC
Figure 132. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. Vcc
85 °C
25 °C
-40 °C
7.7
7.8
7.9
8
8.1
8.2
8.3
8.4
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
FRC (MHz)
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
25 °C
0
2
4
6
8
10
12
14
0 16 32 48 64 80 96 112 128
OSCCAL VALUE
FRC (MHz)206
2543L–AVR–08/10
ATtiny2313
Figure 133. Calibrated 4 MHz RC Oscillator Frequency vs. Temperature
Figure 134. Calibrated 4 MHz RC Oscillator Frequency vs. VCC
CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
5.5 V
5.0 V
3.3 V
1.8 V
3.9
3.95
4
4.05
4.1
4.15
4.2
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature (°C)
FRC (MHz)
CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. Vcc
85 °C
25 °C
-40 °C
3.9
3.95
4
4.05
4.1
4.15
4.2
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
FRC (MHz)207
2543L–AVR–08/10
ATtiny2313
Figure 135. Calibrated 4 MHz RC Oscillator Frequency vs. Osccal Value
Current Consumption
of Peripheral Units
Figure 136. Brownout Detector Current vs. VCC
CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
25 °C
0
1
2
3
4
5
6
7
0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128
OSCCAL VALUE
FRC (MHz )
BROWNOUT DETECTOR CURRENT vs. Vcc
85 °C
25 °C
-40 °C
0
5
10
15
20
25
30
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Vcc (V)
Icc (uA)208
2543L–AVR–08/10
ATtiny2313
Figure 137. Analog Comparator Current vs. VCC
Figure 138. Programming Current vs. VCC
ANALOG COMPARATOR CURRENT vs. Vcc
85 °C
25 °C
-40 °C
0
10
20
30
40
50
60
70
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Vcc (V)
Icc (uA)
PROGRAMMING CURRENT vs. Vcc
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Vcc (V)
Icc (mA)209
2543L–AVR–08/10
ATtiny2313
Current Consumption
in Reset and Reset
Pulsewidth
Figure 139. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current Through The
Reset Pull-up)
Figure 140. Reset Supply Current vs. VCC (1 - 20 MHz, Excluding Current Through The Reset
Pull-up)
RESET SUPPLY CURRENT vs. Vcc
0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)
Icc (mA)
RESET SUPPLY CURRENT vs. Vcc
1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
0
0.5
1
1.5
2
2.5
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)
Icc (mA)210
2543L–AVR–08/10
ATtiny2313
Figure 141. Minimum Reset Pulse Width vs. VCC
MINIMUM RESET PULSE WIDTH vs. Vcc
85 °C
25 °C
-40 °C
0
500
1000
1500
2000
2500
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Vcc (V)
Pulsewidth (ns)211
2543L–AVR–08/10
ATtiny2313
Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
0x3F (0x5F) SREG I T H S V N Z C 8
0x3E (0x5E) Reserved – – – – – – – –
0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 11
0x3C (0x5C) OCR0B Timer/Counter0 – Compare Register B 77
0x3B (0x5B) GIMSK INT1 INT0 PCIE – – – – – 60
0x3A (0x5A) EIFR INTF1 INTF0 PCIF – – – – – 61
0x39 (0x59) TIMSK TOIE1 OCIE1A OCIE1B – ICIE1 OCIE0B TOIE0 OCIE0A 78, 109
0x38 (0x58) TIFR TOV1 OCF1A OCF1B – ICF1 OCF0B TOV0 OCF0A 78
0x37 (0x57) SPMCSR – – – CTPB RFLB PGWRT PGERS SELFPRGEN 155
0x36 (0x56) OCR0A Timer/Counter0 – Compare Register A 77
0x35 (0x55) MCUCR PUD SM1 SE SM0 ISC11 ISC10 ISC01 ISC00 53
0x34 (0x54) MCUSR – – – – WDRF BORF EXTRF PORF 37
0x33 (0x53) TCCR0B FOC0A FOC0B – – WGM02 CS02 CS01 CS00 76
0x32 (0x52) TCNT0 Timer/Counter0 (8-bit) 77
0x31 (0x51) OSCCAL – CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 26
0x30 (0x50) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 73
0x2F (0x4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1BO – – WGM11 WGM10 104
0x2E (0x4E) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 107
0x2D (0x4D) TCNT1H Timer/Counter1 – Counter Register High Byte 108
0x2C (0x4C) TCNT1L Timer/Counter1 – Counter Register Low Byte 108
0x2B (0x4B) OCR1AH Timer/Counter1 – Compare Register A High Byte 108
0x2A (0x4A) OCR1AL Timer/Counter1 – Compare Register A Low Byte 108
0x29 (0x49) OCR1BH Timer/Counter1 – Compare Register B High Byte 109
0x28 (0x48) OCR1BL Timer/Counter1 – Compare Register B Low Byte 109
0x27 (0x47) Reserved – – – – – – – –
0x26 (0x46) CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 28
0x25 (0x45) ICR1H Timer/Counter1 - Input Capture Register High Byte 109
0x24 (0x44) ICR1L Timer/Counter1 - Input Capture Register Low Byte 109
0x23 (0x43) GTCCR – – – – – – – PSR10 81
0x22 (ox42) TCCR1C FOC1A FOC1B – – – – – – 108
0x21 (0x41) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 42
0x20 (0x40) PCMSK PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 61
0x1F (0x3F) Reserved – – – – – – – –
0x1E (0x3E) EEAR – EEPROM Address Register 16
0x1D (0x3D) EEDR EEPROM Data Register 17
0x1C (0x3C) EECR – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE 17
0x1B (0x3B) PORTA – – – – – PORTA2 PORTA1 PORTA0 58
0x1A (0x3A) DDRA – – – – – DDA2 DDA1 DDA0 58
0x19 (0x39) PINA – – – – – PINA2 PINA1 PINA0 58
0x18 (0x38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 58
0x17 (0x37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 58
0x16 (0x36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 58
0x15 (0x35) GPIOR2 General Purpose I/O Register 2 21
0x14 (0x34) GPIOR1 General Purpose I/O Register 1 21
0x13 (0x33) GPIOR0 General Purpose I/O Register 0 21
0x12 (0x32) PORTD – PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 58
0x11 (0x31) DDRD – DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 58
0x10 (0x30) PIND – PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 58
0x0F (0x2F) USIDR USI Data Register 144
0x0E (0x2E) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 145
0x0D (0x2D) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC 145
0x0C (0x2C) UDR UART Data Register (8-bit) 129
0x0B (0x2B) UCSRA RXC TXC UDRE FE DOR UPE U2X MPCM 129
0x0A (0x2A) UCSRB RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 131
0x09 (0x29) UBRRL UBRRH[7:0] 133
0x08 (0x28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 149
0x07 (0x27) Reserved – – – – – – – –
0x06 (0x26) Reserved – – – – – – – –
0x05 (0x25) Reserved – – – – – – – –
0x04 (0x24) Reserved – – – – – – – –
0x03 (0x23) UCSRC – UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL 132
0x02 (0x22) UBRRH – – – – UBRRH[11:8] 133
0x01 (0x21) DIDR – – – – – – AIN1D AIN0D 150
0x00 (0x20) Reserved – – – – – – – –212
2543L–AVR–08/10
ATtiny2313
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. 213
2543L–AVR–08/10
ATtiny2313
Instruction Set Summary
Mnemonics Operands Description Operation Flags #Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1
ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1
ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2
SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1
SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1
SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1
SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1
SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1
ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1
OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1
ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1
EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1
COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1
NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1
SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1
CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1
INC Rd Increment Rd ← Rd + 1 Z,N,V 1
DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1
TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1
CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1
SER Rd Set Register Rd ← 0xFF None 1
BRANCH INSTRUCTIONS
RJMP k Relative Jump PC ← PC + k + 1 None 2
IJMP Indirect Jump to (Z) PC ← Z None 2
RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3
ICALL Indirect Call to (Z) PC ← Z None 3
RET Subroutine Return PC ← STACK None 4
RETI Interrupt Return PC ← STACK I 4
CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3
CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1
CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1
CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3
SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3
SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3
SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2
BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2
BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2
BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2
BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2
BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2
BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2
BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2
BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2
BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2
BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2
BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2
BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2
BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2
BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2
BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2
CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2
LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1
LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1
ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1214
2543L–AVR–08/10
ATtiny2313
ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1
ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1
BSET s Flag Set SREG(s) ← 1 SREG(s) 1
BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1
BST Rr, b Bit Store from Register to T T ← Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) ← T None 1
SEC Set Carry C ← 1 C1
CLC Clear Carry C ← 0 C 1
SEN Set Negative Flag N ← 1 N1
CLN Clear Negative Flag N ← 0 N 1
SEZ Set Zero Flag Z ← 1 Z1
CLZ Clear Zero Flag Z ← 0 Z 1
SEI Global Interrupt Enable I ← 1 I1
CLI Global Interrupt Disable I ← 0 I 1
SES Set Signed Test Flag S ← 1 S1
CLS Clear Signed Test Flag S ← 0 S 1
SEV Set Twos Complement Overflow. V ← 1 V1
CLV Clear Twos Complement Overflow V ← 0 V 1
SET Set T in SREG T ← 1 T1
CLT Clear T in SREG T ← 0 T 1
SEH Set Half Carry Flag in SREG H ← 1 H1
CLH Clear Half Carry Flag in SREG H ← 0 H 1
DATA TRANSFER INSTRUCTIONS
MOV Rd, Rr Move Between Registers Rd ← Rr None 1
MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1
LDI Rd, K Load Immediate Rd ← K None 1
LD Rd, X Load Indirect Rd ← (X) None 2
LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2
LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2
LD Rd, Y Load Indirect Rd ← (Y) None 2
LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2
LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2
LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2
LD Rd, Z Load Indirect Rd ← (Z) None 2
LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2
LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2
LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2
LDS Rd, k Load Direct from SRAM Rd ← (k) None 2
ST X, Rr Store Indirect (X) ← Rr None 2
ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2
ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2
ST Y, Rr Store Indirect (Y) ← Rr None 2
ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2
ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2
STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2
ST Z, Rr Store Indirect (Z) ← Rr None 2
ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2
ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2
STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2
STS k, Rr Store Direct to SRAM (k) ← Rr None 2
LPM Load Program Memory R0 ← (Z) None 3
LPM Rd, Z Load Program Memory Rd ← (Z) None 3
LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3
SPM Store Program Memory (Z) ← R1:R0 None -
IN Rd, P In Port Rd ← P None 1
OUT P, Rr Out Port P ← Rr None 1
PUSH Rr Push Register on Stack STACK ← Rr None 2
POP Rd Pop Register from Stack Rd ← STACK None 2
MCU CONTROL INSTRUCTIONS
NOP No Operation None 1
SLEEP Sleep (see specific descr. for Sleep function) None 1
WDR Watchdog Reset (see specific descr. for WDR/timer) None 1
BREAK Break For On-chip Debug Only None N/A
Mnemonics Operands Description Operation Flags #Clocks215
2543L–AVR–08/10
ATtiny2313
Ordering Information
Notes: 1. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).
Also Halide free and fully Green.
3. For Speed vs. VCC, see Figure 82 on page 180 and Figure 83 on page 180.
4. Code Indicators:
– U: matte tin
– R: tape & reel
Speed (MHz)(3) Power Supply (V) Ordering Code(4) Package(2) Operation Range
10 1.8 - 5.5
ATtiny2313V-10PU
ATtiny2313V-10SU
ATtiny2313V-10SUR
ATtiny2313V-10MU
ATtiny2313V-10MUR
20P3
20S
20S
20M1
20M1
Industrial
(-40°C to +85°C)(1)
20 2.7 - 5.5
ATtiny2313-20PU
ATtiny2313-20SU
ATtiny2313-20SUR
ATtiny2313-20MU
ATtiny2313-20MUR
20P3
20S
20S
20M1
20M1
Industrial
(-40°C to +85°C)(1)
Package Type
20P3 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
20S 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC)
20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (MLF)216
2543L–AVR–08/10
ATtiny2313
Packaging Information
20P3
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual
Inline Package (PDIP) 20P3 C
1/12/04
PIN
1
E1
A1
B
E
B1
C
L
SEATING PLANE
A
D
e
eB
eC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A – – 5.334
A1 0.381 – –
D 25.493 – 25.984 Note 2
E 7.620 – 8.255
E1 6.096 – 7.112 Note 2
B 0.356 – 0.559
B1 1.270 – 1.551
L 2.921 – 3.810
C 0.203 – 0.356
eB – – 10.922
eC 0.000 – 1.524
e 2.540 TYP
Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 217
2543L–AVR–08/10
ATtiny2313
20S218
2543L–AVR–08/10
ATtiny2313
20M1
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, 20M1 A
10/27/04
2.6 mm Exposed Pad, Micro Lead Frame Package (MLF)
A 0.70 0.75 0.80
A1 – 0.01 0.05
A2 0.20 REF
b 0.18 0.23 0.30
D 4.00 BSC
D2 2.45 2.60 2.75
E 4.00 BSC
E2 2.45 2.60 2.75
e 0.50 BSC
L 0.35 0.40 0.55
SIDE VIEW
Pin 1 ID
Pin #1
Notch
(0.20 R)
BOTTOM VIEW
TOP VIEW
Note: Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5.
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D
E
e
A2
A1
A
D2
E2
0.08 C
L
1
2
3
b
1
2
3219
2543L–AVR–08/10
ATtiny2313
Errata The revision in this section refers to the revision of the ATtiny2313 device.
ATtiny2313 Rev C No known errata
ATtiny2313 Rev B • Wrong values read after Erase Only operation
• Parallel Programming does not work
• Watchdog Timer Interrupt disabled
• EEPROM can not be written below 1.9 volts
1. Wrong values read after Erase Only operation
At supply voltages below 2.7 V, an EEPROM location that is erased by the Erase Only operation
may read as programmed (0x00).
Problem Fix/Workaround
If it is necessary to read an EEPROM location after Erase Only, use an Atomic Write operation
with 0xFF as data in order to erase a location. In any case, the Write Only operation can
be used as intended. Thus no special considerations are needed as long as the erased location
is not read before it is programmed.
2. Parallel Programming does not work
Parallel Programming is not functioning correctly. Because of this, reprogramming of the
device is impossible if one of the following modes are selected:
– In-System Programming disabled (SPIEN unprogrammed)
– Reset Disabled (RSTDISBL programmed)
Problem Fix/Workaround
Serial Programming is still working correctly. By avoiding the two modes above, the device
can be reprogrammed serially.
3. Watchdog Timer Interrupt disabled
If the watchdog timer interrupt flag is not cleared before a new timeout occurs, the watchdog
will be disabled, and the interrupt flag will automatically be cleared. This is only applicable in
interrupt only mode. If the Watchdog is configured to reset the device in the watchdog timeout
following an interrupt, the device works correctly.
Problem fix / Workaround
Make sure there is enough time to always service the first timeout event before a new
watchdog timeout occurs. This is done by selecting a long enough time-out period.
4. EEPROM can not be written below 1.9 volts
Writing the EEPROM at VCC below 1.9 volts might fail.
Problem fix / Workaround
Do not write the EEPROM when VCC is below 1.9 volts.
ATtiny2313 Rev A Revision A has not been sampled.220
2543L–AVR–08/10
ATtiny2313
Datasheet
Revision
History
Please note that the referring page numbers in this section refer to the complete document.
Rev. 2543L - 8/10 Added tape and reel part numbers in “Ordering Information” on page 215. Removed text
“Not recommended for new design” from cover page. Fixed literature number mismatch
in Datasheet Revision History.
Rev. 2543K - 03/10
Rev. 2543J - 11/09
Changes from Rev.
2543H-02/05 to
Rev. 2543I-04/06
Changes from Rev.
2543G-10/04 to
Rev. 2543H-02/05
1. Added device Rev C “No known errata” in “Errata” on page 219.
1. Updated template
2. Changed device status to “Not recommended for new designs.”
3. Updated “Stack Pointer” on page 11.
4. Updated Table “Sleep Mode Select” on page 30.
5. Updated “Calibration Byte” on page 160 (to one byte of calibration data)
1. Updated typos.
2. Updated Figure 1 on page 2.
3 Added “Resources” on page 6.
4. Updated “Default Clock Source” on page 23.
5. Updated “128 kHz Internal Oscillator” on page 28.
6. Updated “Power Management and Sleep Modes” on page 30
7. Updated Table 3 on page 23,Table 13 on page 30, Table 14 on page 31,
Table 19 on page 42, Table 31 on page 60, Table 79 on page 176.
8. Updated “External Interrupts” on page 59.
9. Updated “Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0” on page
61.
10. Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page
149.
11. Updated “Calibration Byte” on page 160.
12. Updated “DC Characteristics” on page 177.
13. Updated “Register Summary” on page 211.
14. Updated “Ordering Information” on page 215.
15. Changed occurences of OCnA to OCFnA, OCnB to OCFnB and OC1x to
OCF1x.
1. Updated Table 6 on page 25, Table 15 on page 34, Table 68 on page 160
and Table 80 on page 179.
2. Changed CKSEL default value in “Default Clock Source” on page 23 to
8 MHz.221
2543L–AVR–08/10
ATtiny2313
Changes from Rev.
2543F-08/04 to
Rev. 2543G-10/04
Changes from Rev.
2543E-04/04 to
Rev. 2543F-08/04
Changes from Rev.
2543D-03/04 to
Rev. 2543E-04/04
Changes from Rev.
2543C-12/03 to
Rev. 2543D-03/04
3. Updated “Programming the Flash” on page 165, “Programming the
EEPROM” on page 167 and “Enter Programming Mode” on page 163.
4. Updated “DC Characteristics” on page 177.
5. MLF option updated to “Quad Flat No-Lead/Micro Lead Frame
(QFN/MLF)”
1. Updated “Features” on page 1.
2. Updated “Pinout ATtiny2313” on page 2.
3. Updated “Ordering Information” on page 215.
4. Updated “Packaging Information” on page 216.
5. Updated “Errata” on page 219.
1. Updated “Features” on page 1.
2. Updated “Alternate Functions of Port B” on page 53.
3. Updated “Calibration Byte” on page 160.
4. Moved Table 69 on page 160 and Table 70 on page 160 to “Page Size”
on page 160.
5. Updated “Enter Programming Mode” on page 163.
6. Updated “Serial Programming Algorithm” on page 173.
7. Updated Table 78 on page 174.
8. Updated “DC Characteristics” on page 177.
9. Updated “ATtiny2313 Typical Characteristics” on page 181.
10. Changed occurences of PCINT15 to PCINT7, EEMWE to EEMPE and
EEWE to EEPE in the document.
1. Speed Grades changed
- 12MHz to 10MHz
- 24MHz to 20MHz
2. Updated Figure 1 on page 2.
3. Updated “Ordering Information” on page 215.
4. Updated “Maximum Speed vs. VCC” on page 180.
5. Updated “ATtiny2313 Typical Characteristics” on page 181.
1. Updated Table 2 on page 23.
2. Replaced “Watchdog Timer” on page 39.
3. Added “Maximum Speed vs. VCC” on page 180.
4. “Serial Programming Algorithm” on page 173 updated.
5. Changed mA to µA in preliminary Figure 136 on page 207.
6. “Ordering Information” on page 215 updated.
MLF package option removed222
2543L–AVR–08/10
ATtiny2313
Changes from Rev.
2543B-09/03 to
Rev. 2543C-12/03
Changes from Rev.
2543A-09/03 to
Rev. 2543B-09/03
7. Package drawing “20P3” on page 216 updated.
8. Updated C-code examples.
9. Renamed instances of SPMEN to SELFPRGEN, Self Programming
Enable.
1. Updated “Calibrated Internal RC Oscillator” on page 25.
1. Fixed typo from UART to USART and updated Speed Grades and Power
Consumption Estimates in “Features” on page 1.
2. Updated “Pin Configurations” on page 2.
3. Updated Table 15 on page 34 and Table 80 on page 179.
4. Updated item 5 in “Serial Programming Algorithm” on page 173.
5. Updated “Electrical Characteristics” on page 177.
6. Updated Figure 82 on page 180 and added Figure 83 on page 180.
7. Changed SFIOR to GTCCR in “Register Summary” on page 211.
8. Updated “Ordering Information” on page 215.
9. Added new errata in “Errata” on page 219.i
2543L–AVR–08/10
ATtiny2313
Table of Contents
Features 1
Pin Configurations 2
General Information 6
Resources 6
Code Examples 6
Disclaimer 6
AVR CPU Core 7
Introduction 7
Architectural Overview 7
ALU – Arithmetic Logic Unit 8
Status Register 8
General Purpose Register File 9
Instruction Execution Timing 11
Reset and Interrupt Handling 12
AVR ATtiny2313 Memories 14
In-System Reprogrammable Flash Program Memory 14
EEPROM Data Memory 16
I/O Memory 20
System Clock and Clock Options 22
Clock Systems and their Distribution 22
Clock Sources 23
Default Clock Source 23
Crystal Oscillator 23
Calibrated Internal RC Oscillator 25
System Clock Prescalar 28
Power Management and Sleep Modes 30
Idle Mode 30
Power-down Mode 31
Standby Mode 31
Minimizing Power Consumption 31
System Control and Reset 33
Interrupts 44
Interrupt Vectors in ATtiny2313 44
I/O-Ports 46
Introduction 46ii
2543L–AVR–08/10
ATtiny2313
Ports as General Digital I/O 47
Alternate Port Functions 51
External Interrupts 59
Pin Change Interrupt Timing 59
8-bit Timer/Counter0 with PWM 62
Overview 62
Timer/Counter Clock Sources 63
Counter Unit 63
Output Compare Unit 64
Compare Match Output Unit 65
Modes of Operation 66
Timer/Counter Timing Diagrams 71
Timer/Counter0 and Timer/Counter1 Prescalers 80
16-bit Timer/Counter1 82
Overview 82
Accessing 16-bit Registers 84
Counter Unit 88
Input Capture Unit 89
Output Compare Units 90
Modes of Operation 94
USART 111
Overview 111
Clock Generation 112
Frame Formats 115
USART Initialization 116
Asynchronous Data Reception 124
Universal Serial Interface – USI 138
Overview 138
Functional Descriptions 139
Alternative USI Usage 144
USI Register Descriptions 144
Analog Comparator 149
debugWIRE On-chip Debug System 151
Features 151
Overview 151
Physical Interface 151
Software Break Points 152
Limitations of debugWIRE 152iii
2543L–AVR–08/10
ATtiny2313
debugWIRE Related Register in I/O Memory 152
Self-Programming the Flash 153
Memory Programming 158
Program And Data Memory Lock Bits 158
Signature Bytes 160
Calibration Byte 160
Page Size 160
Parallel Programming Parameters, Pin Mapping, and Commands 161
Serial Programming Pin Mapping 163
Parallel Programming 163
Serial Downloading 172
External Clock Drive 179
ATtiny2313 Typical Characteristics 181
Errata 219
ATtiny2313 Rev C 219
ATtiny2313 Rev B 219
ATtiny2313 Rev A 219
Datasheet Revision History 220
Rev. 2543L - 8/10 220
Rev. 2543K - 03/10 220
Rev. 2543J - 11/09 220
Changes from Rev. 2543H-02/05 to Rev. 2543I-04/06 220
Changes from Rev. 2543G-10/04 to Rev. 2543H-02/05 220
Changes from Rev. 2543F-08/04 to Rev. 2543G-10/04 221
Changes from Rev. 2543E-04/04 to Rev. 2543F-08/04 221
Changes from Rev. 2543D-03/04 to Rev. 2543E-04/04 221
Changes from Rev. 2543C-12/03 to Rev. 2543D-03/04 221
Changes from Rev. 2543B-09/03 to Rev. 2543C-12/03 222
Changes from Rev. 2543A-09/03 to Rev. 2543B-09/03 2222543L–AVR–08/10
Headquarters International
Atmel Corporation
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Tel: 1(408) 441-0311
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Technical Support
avr@atmel.com
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www.atmel.com/contacts
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intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS
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as components in applications intended to support or sustain life.
© 2010 Atmel Corporation. All rights reserved. Atmel®, Atmel logo and combinations thereof, AVR® and others are registered trademarks or
trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
AVR172: Sensorless Commutation of Brushless
DC Motor (BLDC) using ATmega32M1 and
ATAVRMC320
Features
• Robust sensorless commutation control
• Ramp-up sequence
References
[1] ATmega32M1 Data sheet
[2] AVR194: Brushless DC Motor Control using ATmega32M1
[3] AVR430: MC300 Hardware User Guide
[4] AVR470: MC310 User Guide
[5] AVR471: MC320 Getting Started Guide
[6] AVR928: Sensorless methods to drive BLDC motors
1 Introduction
This application note describes how to implement a sensorless commutation of
BLDC motors with the ATAVRMC320 development kit.
The ATmega32M1 is equipped with integrated peripherals that reduce the number
of external components required in a BLDC application. The ATmega32M1 is
suitable for sensorless commutation and for commutation with Hall sensors as well,
but this application note focuses on the sensorless commutation.
The AVR928 Application Note describes the theory of the sensorless control
method and must be carefully read first.
8-bit Microcontrollers
Application Note
Rev. 8306B-AVR-05/10 2 AVR172
8306B-AVR-05/10
2 Hardware
The hardware includes the ATAVRMC310 and ATAVRMC300 boards which are the
two parts of the ATAVRMC320 Starter kit.
Please refer to the ATAVRMC300 and ATAVRMC310 user guides :
- AVR430: MC300 Hardware User Guide
- AVR470: MC310 Hardware User Guide
2.1 MC310 jumpers setting
The AVR172 firmware has been developed with the following jumper settings:
Table 2-1.ATAVRMC310 jumpers setting for sensorless control
Designator Setting Function
J5 Vm connect PB4 to Vm’ (motor voltage measurement if necessary)
J6 PFC OC Connect to overcurrent signal
J7 none used by CAN applications
J8 ShCo connect PC5 to ShCo for current measurement
J9 GNDm connect PC4 to GNDm for current measurement
J12 TxD connect PD3 to the RS232 driver
MOSI A Connect PD3 to ISP connector (for ISP use)
RxDUSB Connect PD3 to RxD1 (for USB interface use)
J13 RxD connect PD4 to the RS232 driver
SCK Connect PD3 to ISP connector (for ISP use)
TxDUSB Connect PD3 to RxD1 (for USB interface use)
J15 none used by CAN application to add a termination resistor
J21 Cmp- connect ACMP0- to V+W bemf conditioning
J22 Cmp+ connect ACMP0+ to U bemf conditioning
J23 Cmp- connect ACMP1- to U+W bemf conditioning
J24 Cmp+ connect ACMP1+ to V bemf conditioning
J25 Cmp- connect ACMP2- to U+V bemf conditioning
J26 Cmp+ connect ACMP2+ to W bemf conditioning
J28 VCC supply the on board USB dongle from the board power supply
See also following picture of MC310 Jumpers configurations : AVR172
3
8306B-AVR-05/10
Figure 1. MC310 Jumpers configuration
2.2 MC300 jumper settings
Table 2-1. ATAVRMC300 jumpers setting for sensorless control
Designator Setting Function
J2 none provide +5V to supply the ATAVRMC310 board
On ATAVRMC300, Vm and Vin connectors can be supplied from the same +12V/7A
power supply. Nevertheless a separate +12V/1A can also be used to supply the Vin
(processor supply voltage).
2.3 Power-supply
This firmware example has been configured according to a power-supply Vm=12V.
This power-supply must be able to provide up to 4A output current.
2.4 Motor
The BLDC motor provided inside MC320 and MC300 Motor Control Kit has the
following characteristics:
Manufacturer : TECMOTION
Number of phases : 3
Number of poles : 8 (4 pairs)
Rated voltage : 24V
Rated speed : 4000 rpm
Rated torque : 62.5 Nm
Torque constant : 35 Nm/A = k_tau4 AVR172
8306B-AVR-05/10
Line to Line Resistance : 1.8 ohm = R
Back EMF : 3.66 V/Krpm = k_e
Peak current : 5.4A
As Vm=12V, the rated speed will be 2000 rpm.
2.5 ATmega32M1 Configuration
ATmega32M1 must be programmed to run at 16MHz using PLL (set corresponding
Fuse bits).
The CKDIV8 fuse must be disabled.
Extended/High/Low Fuses configurations are : FF/DF/F3
2.6 Technical Advices
2.6.1 Disconnecting the BLDC Motor
The BLDC motor must not be disconnected while it is running or while its coils carry
current. It is allowed to disconnect a BLDC motor if the PWM duty cycle is 0% and the
rotor is at rest so that no current is driven through the coils. Be careful, when stopping
the power supply or PWM, a BLDC motor with a high moment of inertia is able to run
for a relatively long time.
2.6.2 Ground and Power Wirings
One design its own board has to take care of the ground wiring and power wiring. The
power supply of the processor and additional signal conditioning components (e.g.
additional fast comparators, operational amplifiers, …) has to be decoupled from the
motor power supply. The ground connection has to be of low resistance and low
inductance to prevent against voltage drop and noise due to high currents. A ground
plane within a multi layer PCB is recommended for proper operation.
3 Firmware
The example firmware is based on the Sensorless method described in AVR928
Application Note.
It is operating in sensorless mode using the ATmega32M1 internal comparators. Hall
sensor wires of the BLDC motor of the kit can remain unconnected.
The source file directory embeds an html documentation which can be opened
through the readme.html file.
The theory of the different tasks has been detailed in AVR928. The application to
ATmega32M1 is detailed in following sections.
3.1 Main Flow chart
The firmware main flowchart is described below : AVR172
5
8306B-AVR-05/10
Figure 2. Main flow chart
The tasks are scheduled thanks to the g_tick produced each 1.024ms with Timer0. 6 AVR172
8306B-AVR-05/10
3.2 MS_ALIGN phase
The ALIGN phase forces the motor at a specific position. The time of this phase is
controlled with ALIGN_TIME constant which is the ru_period_counter initial value
(200 for MC310 motor).
3.3 RAMP_UP phase
The ramp-up charateristics (duty-cycles and times) are stored in two tables:
• ramp_up_duty_table[] : which provides the duty_cycle of the step
• ramp_up_time_table[] : which provides the length of the step (ru_step_length)
These two tables are specific to the motor and the application.
The scanning of the step sequences and the monitoring of the step length are
achieved thanks to three independant counters :
- ru_step_length_cntr : which counts the commutation time (up to ru_step_length
variable)
- ru_period_counter : which counts the step length (up to RAMP_UP_PERIOD
constant)
- ramp_up_index : which counts the step numbers (up to
RAMP_UP_INDEX_MAX constant)
The figure below provides a waveform of steps timing :
Figure 3. Steps timing AVR172
7
8306B-AVR-05/10
3.3.1 Time of steps
The step time is RAMP_UP_PERIOD = 50ms.
3.3.2 Number of steps
The parameter : RAMP_UP_INDEX_MAX = 9, defines 10 steps ramp up.
3.3.3 Parameters tables
In firmware example, the tables have been defined according to the characteristics of
the motor provided in the kit (see parameters in 2.4 Motor section) :
ramp_up_time_table[] = {26,23,20,17,14,11,8,5,3,2,2};
ramp_up_duty_table[] = {122,124,126,129,131,133,135,137,140,143,145};
3.3.4 Sp1/pwm1
The usual parameters described in AVR928 Application Note are:
• Pwm1 = 50%
• Sp1 = Sp_max/60
The parameters defined with MC310 Tecmotion motor are:
• Pwm1 = 48% (= 122/256)
• Sp1 :
Sp1 is defined thanks to the initialization value of ru_step_length :
ru_step_length = RAMP_UP_STEP_MAX = 40
This variable determines one commutation each 40ms.
So an electrical rotation time is 120ms. As the motor has 4 pairs of poles, the
mechanical rotation time is 480ms. So the rotation speed is 60/0.48 = 125 rpm.
So Sp1 = Sp_max/32.
The second value of ru_step_length is 26 in the time table. It defines the following
commutation time.
3.3.5 Sp2/pwm2
The theorical parameters described in AVR928 Application Note are:
• Pwm2 = 60%
• Sp2 = Sp_max/6 = Sp1 / 10
The parameters defined with Tecmotion motor are:
• Pwm2 = 57% (= 145/256)
• Sp2 :
Sp2 is defined thanks to the last value of ru_step_length : 2
This variable determines one commutation each 4ms.
So an electrical rotation time is 12ms. As the motor has 4 pairs of poles, the
mechanical rotation time is 48ms. So the rotation speed is 60/0.048 = 1250 rpm.
So Sp2 = Sp_max/3.2. 8 AVR172
8306B-AVR-05/10
This confirms also the usual ratio = 10 between Sp1 and Sp2 which is defined in
AVR498 Application Note.
3.4 LAST_RAMP_UP phase
To avoid a shorten last step, this phase monitors the last ramp-up step to guarantee it
is ended properly before running in closed loop.
3.5 RUNNING Phase
3.5.1 Closed-loop block diagram
The Running phase is a sensorless closed loop which block diagram is following :
Figure 4. Closed-loop block diagram AVR172
9
8306B-AVR-05/10
3.5.2 Running flowchart
The flowchart is following :
Figure 5. Closed-loop flowchart
•
Motor_state is kept equal to MS_RUNNING
mci_set_ref_speed() function updates the speed setpoint according to the
potentiometer adjustment or the speed command received on serial transmission.
In mc_regulation_loop() function, duty_cycle_reference is the duty_cycle variable
which controls the PWM generator. This variable is the result of following functions :
• In OPEN_LOOP:
mci_set_ref_speed() function
• In SPEED_LOOP: 10 AVR172
8306B-AVR-05/10
mc_control_speed(2*mci_get_ref_speed())
duty-cycle_reference is calculated from ref_speed and from
monitored mci_get_measured_speed()
measured_speed = (KSPEED * 4) / mci_measured_period
with mci_measured_period calculated in the Interrupt vector of
Analog Comparator 1. This interrupt uses Timer 0 to compute the
period.
• In CURRENT_LOOP :
mc_control_current(mc_get_potentiometer_value()
3.5.3 Sensorless Detection and Commutation Management
The analog comparators 0, 1 and 2 are used to detect the zero crossing of the U, V
and W phases.
The timer 1 is used to monitor the time between two consecutive zero crossings. This
time corresponds to one sector of the electrical rotation of the motor. It equals 60° of
the entire electrical period of the motor.
When a zero crossing event occurs, the timer 1 value is stored. Then this value is
divided by 2 (providing the 30° time) and loaded into the Compare A register of timer
1. Then this value is added to the half of itself to provide the 45° time and loaded into
the Compare B register of timer 1.
The timer 1 compare A event occurs 30° after the zero crossing. It activates the next
commutation state and masks the zero crossing to avoid the discharge of the
inductance (demagnetization) pulse generated at the end of a step when the active
switches are released.
Due to the inductance of the motor coils, a voltage equals to -Ldi/dt is generated, the
demagnetization is done through the diodes of the power bridge.
The timer 1 compare B event releases the zero crossing mask : enables the
comparator n interrupt according to the motor_step variable. This Timer1 interrupt
provides the demagnetization mask delay. AVR172
11
8306B-AVR-05/10
4 RS232 Communication with firmware
4.1 Connecting ATAVRMC310 to use the RS232 interface
Connect PC com port to the ATAVRMC310 RS232 connector through a direct cable.
The serial configuration is:
• 38400 bauds,
• 8 bit data bit,
• 1 stop bit,
• no handshake,
4.2 PC applications
User can communicate with firmware through RS232 with usual PC serial
communication applications (i.e. Hyperterminal) or the Atmel “Motor Control Center”
application which can be downloaded from Atmel web at url : http://www.atmel.com
4.2.1 PC Terminal : RS232 Messages and Commands
At power up the following welcome message is received on terminal :
“ATMEL Motor Control Interface”.
The following commands can be sent to the firmware:
Table 2-1. List of commands
Command Action
ru Run motor
st Stop Motor
help Gives help
fw Set direction to Forward
bw Set direction to Backward
ss Set Speed (followed with speed value)
gi Get ID
g0 Get Status 0
g1 Get Status 1
4.2.2 Motor Control Center
The User Guide is available in Install directory at URL :
C:\Program Files\Atmel\Motor Control Center\help\Overview.htm
The AVR172 Target must be selected first to get the right configuration :
To select a target, execute the File > Select Target command or click the
button in the toolbar. The following dialog pops up: 12 AVR172
8306B-AVR-05/10
Figure 6. Motor Control Center Interface
5 USB communication
Communication can be achieved from PC to USB connector of MC310 board.
The AVR470, MC310 Hardware User Guide details the configuration to be achieved.
Communication port becomes a Virtual Com port. Same tools as described in section
4 (RS232 Communication with firmware), can be used through this Virtual Com port. 8306B-AVR-05/10
Disclaimer
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1. Product profile
1.1 General description
NPN/NPN general-purpose transistor pair in a small SOT457 (SC-74) Surface-Mounted
Device (SMD) plastic package.
1.2 Features
■ Low collector capacitance
■ Low collector-emitter saturation voltage
■ Closely matched current gain
■ Reduces number of components and board space
■ No mutual interference between the transistors
■ AEC-Q101 qualified
1.3 Applications
■ General-purpose switching and amplification
1.4 Quick reference data
BC846DS
65 V, 100 mA NPN/NPN general-purpose transistor
Rev. 01 — 17 July 2009 Product data sheet
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
Per transistor
VCEO collector-emitter voltage open base - - 65 V
IC collector current - - 100 mA
hFE DC current gain VCE = 5 V; IC = 2 mA 200 300 450BC846DS_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 17 July 2009 2 of 12
NXP Semiconductors BC846DS
65 V, 100 mA NPN/NPN general-purpose transistor
2. Pinning information
3. Ordering information
4. Marking
5. Limiting values
Table 2. Pinning
Pin Description Simplified outline Graphic symbol
1 emitter TR1
2 base TR1
3 collector TR2
4 emitter TR2
5 base TR2
6 collector TR1
1 3 2
6 5 4
sym020
1 2 3
6 5
TR1
TR2
4
Table 3. Ordering information
Type number Package
Name Description Version
BC846DS SC-74 plastic surface-mounted package (TSOP6); 6 leads SOT457
Table 4. Marking codes
Type number Marking code
BC846DS ZK
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Per transistor
VCBO collector-base voltage open emitter - 80 V
VCEO collector-emitter voltage open base - 65 V
VEBO emitter-base voltage open collector - 6 V
IC collector current - 100 mA
ICM peak collector current single pulse;
tp ≤ 1 ms
- 200 mA
IBM peak base current single pulse;
tp ≤ 1 ms
- 200 mA
Ptot total power dissipation Tamb ≤ 25 °C [1] - 250 mW
Per device
Ptot total power dissipation Tamb ≤ 25 °C [1] - 380 mWBC846DS_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 17 July 2009 3 of 12
NXP Semiconductors BC846DS
65 V, 100 mA NPN/NPN general-purpose transistor
[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard
footprint.
6. Thermal characteristics
[1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
Tj junction temperature - 150 °C
Tamb ambient temperature −55 +150 °C
Tstg storage temperature −65 +150 °C
FR4 PCB, standard footprint
Fig 1. Per device: Power derating curve SOT457 (SC-74)
Table 5. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Tamb (°C)
−75 175 −25 25 75 125
006aab621
200
300
100
400
500
Ptot
(mW)
0
Table 6. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Per transistor
Rth(j-a) thermal resistance from
junction to ambient
in free air [1] - - 500 K/W
Rth(j-sp) thermal resistance from
junction to solder point
- - 250 K/W
Per device
Rth(j-a) thermal resistance from
junction to ambient
in free air [1] - - 328 K/WBC846DS_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 17 July 2009 4 of 12
NXP Semiconductors BC846DS
65 V, 100 mA NPN/NPN general-purpose transistor
7. Characteristics
FR4 PCB, standard footprint
Fig 2. Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
006aab622
10−5 10 10 −2 10−4 102 10−1
tp (s)
10−3 103 1
102
10
103
Zth(j-a)
(K/W)
1
δ = 1
0.75
0.50
0.33
0.10
0.05
0.02
0.01
0
0.20
Table 7. Characteristics
Tamb = 25 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Per transistor
ICBO collector-base cut-off
current
VCB = 50 V; IE = 0 A - - 15 nA
VCB = 30 V; IE = 0 A;
Tj = 150 °C
--5 µA
IEBO emitter-base cut-off
current
VEB = 6 V; IC = 0 A - - 100 nA
hFE DC current gain VCE =5V
IC = 10 µA - 280 -
IC = 2 mA 200 300 450
VCEsat collector-emitter
saturation voltage
IC = 10 mA; IB = 0.5 mA - 55 100 mV
IC = 100 mA; IB = 5 mA - 200 300 mV
VBEsat base-emitter
saturation voltage
IC = 10 mA; IB = 0.5 mA - 755 850 mV
IC = 100 mA; IB = 5 mA - 1000 - mV
VBE base-emitter voltage VCE =5V
IC = 2 mA 580 650 700 mV
IC = 10 mA - - 770 mVBC846DS_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 17 July 2009 5 of 12
NXP Semiconductors BC846DS
65 V, 100 mA NPN/NPN general-purpose transistor
Cc collector capacitance VCB = 10 V; IE = ie = 0 A;
f = 1 MHz
- 1.9 - pF
Ce emitter capacitance VEB = 0.5 V; IC = ic = 0 A;
f = 1 MHz
- 11 - pF
fT transition frequency VCE = 5 V; IC = 10 mA;
f = 100 MHz
100 - - MHz
NF noise figure VCE = 5 V; IC = 0.2 mA;
RS =2kΩ;
f = 10 Hz to 15.7 kHz
- 1.9 - dB
VCE = 5 V; IC = 0.2 mA;
RS =2kΩ; f = 1 kHz;
B = 200 Hz
- 3.1 - dB
Table 7. Characteristics …continued
Tamb = 25 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VCE =5V
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −55 °C
Tamb = 25 °C
Fig 3. Per transistor: DC current gain as a function of
collector current; typical values
Fig 4. Per transistor: Collector current as a function
of collector-emitter voltage; typical values
006aaa533
200
400
600
hFE
0
IC (mA)
10−2 103 102 10−1 1 10
(3)
(1)
(2)
006aaa532
VCE (V)
0 10 2 4 6 8
0.08
0.12
0.04
0.16
0.20
IC
(A)
0
IB (mA) = 4.50
2.70
3.15
4.05
3.60
0.45
0.90
1.35
1.80
2.25BC846DS_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 17 July 2009 6 of 12
NXP Semiconductors BC846DS
65 V, 100 mA NPN/NPN general-purpose transistor
VCE = 5 V; Tamb = 25 °C IC/IB = 20
(1) Tamb = −55 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
Fig 5. Per transistor: Base-emitter voltage as a
function of collector current; typical values
Fig 6. Per transistor: Base-emitter saturation voltage
as a function of collector current; typical
values
IC/IB = 20
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = −55 °C
VCE = 5 V; Tamb = 25 °C
Fig 7. Per transistor: Collector-emitter saturation
voltage as a function of collector current;
typical values
Fig 8. Per transistor: Transition frequency as a
function of collector current; typical values
006aaa536
0.6
0.8
1
VBE
(V)
0.4
IC (mA)
10−1 103 102 1 10
006aaa534
IC (mA)
10−1 103 102 1 10
0.5
0.9
1.3
0.3
0.7
1.1
VBEsat
(V)
0.1
(1)
(2)
(3)
006aaa535
1
10−1
10
VCEsat
(V)
10−2
IC (mA)
10−1 103 102 1 10
(1)
(2)
(3)
006aaa537
IC (mA)
1 102 10
102
103
fT
(MHz)
10BC846DS_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 17 July 2009 7 of 12
NXP Semiconductors BC846DS
65 V, 100 mA NPN/NPN general-purpose transistor
f = 1 MHz; Tamb = 25 °C f = 1 MHz; Tamb = 25 °C
Fig 9. Per transistor: Collector capacitance as a
function of collector-base voltage; typical
values
Fig 10. Per transistor: Emitter capacitance as a
function of emitter-base voltage; typical values
VCB (V)
0 10 2 4 6 8
006aab620
2
4
6
Cc
(pF)
0
006aaa539
VEB (V)
0 6 2 4
9
11
7
13
15
Ce
(pF)
5BC846DS_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 17 July 2009 8 of 12
NXP Semiconductors BC846DS
65 V, 100 mA NPN/NPN general-purpose transistor
8. Test information
8.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is
suitable for use in automotive applications.
9. Package outline
10. Packing information
[1] For further information and the availability of packing methods, see Section 14.
[2] T1: normal taping
[3] T2: reverse taping
Fig 11. Package outline SOT457 (SC-74)
Dimensions in mm 04-11-08
3.0
2.5
1.7
1.3
3.1
2.7
pin 1 index
1.9
0.26
0.10
0.40
0.25 0.95
1.1
0.9
0.6
0.2
1 3 2
6 5 4
Table 8. Packing methods
The indicated -xxx are the last three digits of the 12NC ordering code.[1]
Type number Package Description Packing quantity
3000 10000
BC846DS SOT457 4 mm pitch, 8 mm tape and reel; T1 [2] -115 -135
4 mm pitch, 8 mm tape and reel; T2 [3] -125 -165BC846DS_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 17 July 2009 9 of 12
NXP Semiconductors BC846DS
65 V, 100 mA NPN/NPN general-purpose transistor
11. Soldering
Fig 12. Reflow soldering footprint SOT457 (SC-74)
Fig 13. Wave soldering footprint SOT457 (SC-74)
solder lands
solder resist
occupied area
solder paste
sot457_fr
3.45
1.95
3.3 2.825
0.45
(6×)
0.55
(6×)
0.7
(6×)
0.8
(6×)
2.4
0.95
0.95
Dimensions in mm
sot457_fw
5.3
5.05
1.45
(6×)
0.45
(2×)
1.5
(4×)
2.85
1.475
1.475
solder lands
solder resist
occupied area
preferred transport
direction during soldering
Dimensions in mmBC846DS_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 17 July 2009 10 of 12
NXP Semiconductors BC846DS
65 V, 100 mA NPN/NPN general-purpose transistor
12. Revision history
Table 9. Revision history
Document ID Release date Data sheet status Change notice Supersedes
BC846DS_1 20090717 Product data sheet - -BC846DS_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 17 July 2009 11 of 12
NXP Semiconductors BC846DS
65 V, 100 mA NPN/NPN general-purpose transistor
13. Legal information
13.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
13.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
13.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
13.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
14. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.NXP Semiconductors BC846DS
65 V, 100 mA NPN/NPN general-purpose transistor
© NXP B.V. 2009. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 17 July 2009
Document identifier: BC846DS_1
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
15. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description. . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
6 Thermal characteristics. . . . . . . . . . . . . . . . . . . 3
7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Test information . . . . . . . . . . . . . . . . . . . . . . . . . 8
8.1 Quality information . . . . . . . . . . . . . . . . . . . . . . 8
9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
10 Packing information. . . . . . . . . . . . . . . . . . . . . . 8
11 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
12 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
13.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
13.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
13.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
13.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
14 Contact information. . . . . . . . . . . . . . . . . . . . . 11
15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1. Product profile
1.1 General description
Planar Maximum Efficiency General Application (MEGA) Schottky barrier rectifier with an
integrated guard ring for stress protection, encapsulated in a SOD128 small and flat lead
Surface-Mounted Device (SMD) plastic package.
1.2 Features
■ Average forward current: IF(AV) ≤ 1 A
■ Reverse voltage: VR ≤ 30 V
■ Low forward voltage
■ High power capability due to clip-bond technology
■ AEC-Q101 qualified
■ Small and flat lead SMD plastic package
1.3 Applications
■ Low voltage rectification
■ High efficiency DC-to-DC conversion
■ Switch Mode Power Supply (SMPS)
■ Reverse polarity protection
■ Low power consumption applications
1.4 Quick reference data
[1] Device mounted on a ceramic Printed-Circuit Board (PCB), Al2O3, standard footprint.
PMEG3010EP
1 A low VF MEGA Schottky barrier rectifier
Rev. 01 — 30 December 2008 Product data sheet
Table 1. Quick reference data
Tj = 25 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
IF(AV) average forward current square wave;
δ = 0.5;
f = 20 kHz
Tamb ≤ 130 °C [1] - - 1A
Tsp ≤ 145 °C - - 1A
VR reverse voltage - - 30 V
VF forward voltage IF = 1 A - 320 360 mV
IR reverse current VR = 30 V - 0.6 1.5 mAPMEG3010EP_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 30 December 2008 2 of 13
NXP Semiconductors PMEG3010EP
1 A low VF MEGA Schottky barrier rectifier
2. Pinning information
[1] The marking bar indicates the cathode.
3. Ordering information
4. Marking
5. Limiting values
Table 2. Pinning
Pin Description Simplified outline Graphic symbol
1 cathode [1]
2 anode 1 2
sym001
1 2
Table 3. Ordering information
Type number Package
Name Description Version
PMEG3010EP - plastic surface-mounted package; 2 leads SOD128
Table 4. Marking codes
Type number Marking code
PMEG3010EP A1
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VR reverse voltage Tj = 25 °C - 30 V
IF(AV) average forward current square wave;
δ = 0.5;
f = 20 kHz
Tamb ≤ 130 °C [1] - 1A
Tsp ≤ 145 °C - 1A
IFSM non-repetitive peak
forward current
square wave;
tp = 8 ms
[2] - 50 A
Ptot total power dissipation Tamb ≤ 25 °C [3][4] - 625 mW
[3][5] - 1050 mW
[3][1] - 2100 mWPMEG3010EP_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 30 December 2008 3 of 13
NXP Semiconductors PMEG3010EP
1 A low VF MEGA Schottky barrier rectifier
[1] Device mounted on a ceramic PCB, Al2O3, standard footprint.
[2] Tj = 25 °C prior to surge.
[3] Reflow soldering is the only recommended soldering method.
[4] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[5] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for cathode 1 cm2.
6. Thermal characteristics
[1] For Schottky barrier diodes thermal runaway has to be considered, as in some applications the reverse
power losses PR are a significant part of the total power losses.
[2] Reflow soldering is the only recommended soldering method.
[3] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[4] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for cathode 1 cm2.
[5] Device mounted on a ceramic PCB, Al2O3, standard footprint.
[6] Soldering point of cathode tab.
Tj junction temperature - 150 °C
Tamb ambient temperature −55 +150 °C
Tstg storage temperature −65 +150 °C
Table 5. Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Table 6. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Rth(j-a) thermal resistance from
junction to ambient
in free air [1][2]
[3] - - 200 K/W
[4] - - 120 K/W
[5] - - 60 K/W
Rth(j-sp) thermal resistance from
junction to solder point
[6] - - 12 K/WPMEG3010EP_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 30 December 2008 4 of 13
NXP Semiconductors PMEG3010EP
1 A low VF MEGA Schottky barrier rectifier
FR4 PCB, standard footprint
Fig 1. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
FR4 PCB, mounting pad for cathode 1 cm2
Fig 2. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
006aab296
10
1
102
103
Zth(j-a)
(K/W)
10−1
tp (s)
10−3 102 103 10 1 10 −2 10−1
duty cycle =
1
0.75
0.5
0.33
0.25 0.2
0.1
0.05
0.02 0.01
0
006aab297
10
1
102
103
Zth(j-a)
(K/W)
10−1
tp (s)
10−3 102 103 10 1 10 −2 10−1
duty cycle =
1
0.75
0.5
0.33 0.25
0.2
0.1
0.05
0.02 0.01
0PMEG3010EP_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 30 December 2008 5 of 13
NXP Semiconductors PMEG3010EP
1 A low VF MEGA Schottky barrier rectifier
7. Characteristics
Ceramic PCB, Al2O3, standard footprint
Fig 3. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values
006aab298
10
1
102
103
Zth(j-a)
(K/W)
10−1
tp (s)
10−3 102 103 10 1 10 −2 10−1
duty cycle =
1
0.75
0.5 0.33
0.25 0.2
0.1
0.05
0.02 0.01
0
Table 7. Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VF forward voltage IF = 0.1 A - 230 260 mV
IF = 0.5 A - 280 310 mV
IF = 1 A - 320 360 mV
IR reverse current VR = 5 V - 55 - µA
VR = 30 V - 0.6 1.5 mA
Cd diode capacitance f = 1 MHz
VR = 1 V - 170 - pF
VR = 10 V - 60 - pFPMEG3010EP_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 30 December 2008 6 of 13
NXP Semiconductors PMEG3010EP
1 A low VF MEGA Schottky barrier rectifier
(1) Tj = 150 °C
(2) Tj = 125 °C
(3) Tj = 85 °C
(4) Tj = 25 °C
(5) Tj = −40 °C
(1) Tj = 125 °C
(2) Tj = 85 °C
(3) Tj = 25 °C
(4) Tj = −40 °C
Fig 4. Forward current as a function of forward
voltage; typical values
Fig 5. Reverse current as a function of reverse
voltage; typical values
f = 1 MHz; Tamb = 25 °C
Fig 6. Diode capacitance as a function of reverse voltage; typical values
006aab299
10−2
10−3
1
10−1
10
IF
(A)
10−4
VF (V)
0 0.8 0.2 0.4 0.6
(1)
(2)
(3) (4) (5)
006aab300
VR (V)
0 30 10 20
1
10−1
10−2
10−3
10−4
10−5
10−6
IR
(A)
10−7
(1)
(2)
(3)
(4)
VR (V)
0 30 10 20
006aab301
100
200
300
Cd
(pF)
0PMEG3010EP_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 30 December 2008 7 of 13
NXP Semiconductors PMEG3010EP
1 A low VF MEGA Schottky barrier rectifier
Tj = 150 °C
(1) δ = 0.1
(2) δ = 0.2
(3) δ = 0.5
(4) δ = 1
Tj = 125 °C
(1) δ = 1
(2) δ = 0.9
(3) δ = 0.8
(4) δ = 0.5
Fig 7. Average forward power dissipation as a
function of average forward current; typical
values
Fig 8. Average reverse power dissipation as a
function of reverse voltage; typical values
FR4 PCB, standard footprint
Tj = 150 °C
(1) δ = 1; DC
(2) δ = 0.5; f = 20 kHz
(3) δ = 0.2; f = 20 kHz
(4) δ = 0.1; f = 20 kHz
FR4 PCB, mounting pad for cathode 1 cm2
Tj = 150 °C
(1) δ = 1; DC
(2) δ = 0.5; f = 20 kHz
(3) δ = 0.2; f = 20 kHz
(4) δ = 0.1; f = 20 kHz
Fig 9. Average forward current as a function of
ambient temperature; typical values
Fig 10. Average forward current as a function of
ambient temperature; typical values
006aab302
IF(AV) (A)
0 1.5 0.5 1
0.2
0.1
0.3
0.4
PF(AV)
(W)
0
(1) (2)
(3)
(4)
VR (V)
0 30 10 20
006aab303 3.5
PR(AV)
(W)
0
0.5
1
1.5
2
2.5
3
(1)
(2)
(3)
(4)
Tamb (°C)
0 75 25 150 50 100 125 175
006aab304
0.8
0.4
1.2
1.6
IF(AV)
(A)
0
(1)
(2)
(3)
(4)
Tamb (°C)
0 75 25 150 50 100 125 175
006aab305
0.8
0.4
1.2
1.6
IF(AV)
(A)
0
(1)
(2)
(3)
(4)PMEG3010EP_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 30 December 2008 8 of 13
NXP Semiconductors PMEG3010EP
1 A low VF MEGA Schottky barrier rectifier
Ceramic PCB, Al2O3, standard footprint
Tj = 150 °C
(1) δ = 1; DC
(2) δ = 0.5; f = 20 kHz
(3) δ = 0.2; f = 20 kHz
(4) δ = 0.1; f = 20 kHz
Tj = 150 °C
(1) δ = 1; DC
(2) δ = 0.5; f = 20 kHz
(3) δ = 0.2; f = 20 kHz
(4) δ = 0.1; f = 20 kHz
Fig 11. Average forward current as a function of
ambient temperature; typical values
Fig 12. Average forward current as a function of
solder point temperature; typical values
Tamb (°C)
0 75 25 150 50 100 125 175
006aab306
0.8
0.4
1.2
1.6
IF(AV)
(A)
0
(1)
(2)
(3)
(4)
Tsp (°C)
0 75 25 150 50 100 125 175
006aab307
0.8
0.4
1.2
1.6
IF(AV)
(A)
0
(1)
(2)
(3)
(4)PMEG3010EP_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 30 December 2008 9 of 13
NXP Semiconductors PMEG3010EP
1 A low VF MEGA Schottky barrier rectifier
8. Test information
The current ratings for the typical waveforms as shown in Figure 9, 10, 11 and 12 are
calculated according to the equations: with IM defined as peak current,
at DC, and with IRMS defined as RMS current.
8.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is
suitable for use in automotive applications.
9. Package outline
Fig 13. Duty cycle definition
t1
t2
P
t
006aaa812
duty cycle δ =
t1
t2
IF AV ( ) = IM × δ
IRMS IF AV ( ) = IRMS = IM × δ
Fig 14. Package outline SOD128
Dimensions in mm 07-09-12
1.1
0.9
0.22
0.10
0.6
0.3
5.0
4.4
4.0
3.6
1.9
1.6
2.7
2.3
1
2PMEG3010EP_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 30 December 2008 10 of 13
NXP Semiconductors PMEG3010EP
1 A low VF MEGA Schottky barrier rectifier
10. Packing information
[1] For further information and the availability of packing methods, see Section 14.
11. Soldering
Table 8. Packing methods
The indicated -xxx are the last three digits of the 12NC ordering code.[1]
Type number Package Description Packing quantity
3000
PMEG3010EP SOD128 4 mm pitch, 12 mm tape and reel -115
Reflow soldering is the only recommended soldering method.
Fig 15. Reflow soldering footprint SOD128
solder lands
solder resist
occupied area
solder paste
3.4 2.5 2.1
(2×)
1.9
(2×)
4.4
4.2
6.2
1.2
(2×)
1.4
(2×) sod128_fr
Dimensions in mmPMEG3010EP_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 30 December 2008 11 of 13
NXP Semiconductors PMEG3010EP
1 A low VF MEGA Schottky barrier rectifier
12. Revision history
Table 9. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PMEG3010EP_1 20081230 Product data sheet - -PMEG3010EP_1 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 — 30 December 2008 12 of 13
NXP Semiconductors PMEG3010EP
1 A low VF MEGA Schottky barrier rectifier
13. Legal information
13.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
13.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
13.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
13.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
14. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.NXP Semiconductors PMEG3010EP
1 A low VF MEGA Schottky barrier rectifier
© NXP B.V. 2009. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 30 December 2008
Document identifier: PMEG3010EP_1
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
15. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description. . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
6 Thermal characteristics. . . . . . . . . . . . . . . . . . . 3
7 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Test information . . . . . . . . . . . . . . . . . . . . . . . . . 9
8.1 Quality information . . . . . . . . . . . . . . . . . . . . . . 9
9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
10 Packing information. . . . . . . . . . . . . . . . . . . . . 10
11 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
12 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
13.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
13.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
13.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
13.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
14 Contact information. . . . . . . . . . . . . . . . . . . . . 12
15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1. Product profile
1.1 General description
Planar Schottky barrier single diode with an integrated guard ring for stress protection,
encapsulated in a SOD323F (SC-90) very small and flat lead Surface-Mounted Device
(SMD) plastic package.
1.2 Features
■ Low forward voltage
■ Very small and flat lead SMD plastic package
■ Low capacitance
■ Flat leads: excellent coplanarity and improved thermal behavior
1.3 Applications
■ Voltage clamping
■ Line termination
■ Reverse polarity protection
1.4 Quick reference data
[1] Pulse test: tp ≤ 300 µs; δ ≤ 0.02.
BAT54J
Schottky barrier single diode
Rev. 01 — 8 March 2007 Product data sheet
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
IF forward current - - 200 mA
VR reverse voltage - - 30 V
VF forward voltage IF = 1 mA [1] - - 320 mVBAT54J_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 8 March 2007 2 of 8
NXP Semiconductors BAT54J
Schottky barrier single diode
2. Pinning information
[1] The marking bar indicates the cathode.
3. Ordering information
4. Marking
5. Limiting values
[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated, mounting pad for
cathode 1 cm2.
Table 2. Pinning
Pin Description Simplified outline Symbol
1 cathode [1]
2 anode 1 2
sym001
1 2
Table 3. Ordering information
Type number Package
Name Description Version
BAT54J SC-90 plastic surface-mounted package; 2 leads SOD323F
Table 4. Marking codes
Type number Marking code
BAT54J AP
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VR reverse voltage - 30 V
IF forward current - 200 mA
IFRM repetitive peak forward
current
tp ≤ 1 s; δ ≤ 0.5 - 300 mA
IFSM non-repetitive peak forward
current
square wave;
tp < 10 ms
- 600 mA
Ptot total power dissipation Tamb ≤ 25 °C [1] - 550 mW
Tj junction temperature - 150 °C
Tamb ambient temperature −65 +150 °C
Tstg storage temperature −65 +150 °CBAT54J_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 8 March 2007 3 of 8
NXP Semiconductors BAT54J
Schottky barrier single diode
6. Thermal characteristics
[1] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for cathode 1 cm2.
[2] Reflow soldering is the only recommended soldering method.
[3] Soldering point of cathode tab.
7. Characteristics
[1] Pulse test: tp ≤ 300 µs; δ ≤ 0.02.
Table 6. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Rth(j-a) thermal resistance from
junction to ambient
in free air [1][2] - - 230 K/W
Rth(j-sp) thermal resistance from
junction to solder point
[3] - - 55 K/W
Table 7. Characteristics
Tamb = 25 °C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VF forward voltage [1]
IF = 0.1 mA - - 240 mV
IF = 1 mA - - 320 mV
IF = 10 mA - - 400 mV
IF = 30 mA - - 500 mV
IF = 100 mA - - 800 mV
IR reverse current VR = 25 V - - 2 µA
Cd diode capacitance VR = 1 V; f = 1 MHz - - 10 pFBAT54J_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 8 March 2007 4 of 8
NXP Semiconductors BAT54J
Schottky barrier single diode
(1) Tamb = 125 °C
(2) Tamb = 85 °C
(3) Tamb = 25 °C
(1) Tamb = 125 °C
(2) Tamb = 85 °C
(3) Tamb = 25 °C
Fig 1. Forward current as a function of forward
voltage; typical values
Fig 2. Reverse current as a function of reverse
voltage; typical values
Tamb = 25 °C; f = 1 MHz
Fig 3. Diode capacitance as a function of reverse voltage; typical values
103
102
10−1
IF
(mA)
VF (V)
10
1
0 0.4 0.8 1.2
msa892
(1) (2) (3)
(1) (2) (3)
0 10 20 30 VR (V)
103
102
10−1
IR
(µA)
10
1
(1)
(2)
(3)
msa893
0 10 20 30
0
5
10
15
VR (V)
Cd
(pF)
msa891BAT54J_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 8 March 2007 5 of 8
NXP Semiconductors BAT54J
Schottky barrier single diode
8. Package outline
9. Packing information
[1] For further information and the availability of packing methods, see Section 13.
10. Soldering
Fig 4. Package outline SOD323F (SC-90)
Dimensions in mm 04-09-13
0.80
0.65
0.25
0.10
0.5
0.3
2.7
2.3
1.8
1.6
0.40
0.25
1.35
1.15
1
2
Table 8. Packing methods
The indicated -xxx are the last three digits of the 12NC ordering code.[1]
Type number Package Description Packing quantity
3000 10000
BAT54J SOD323F 4 mm pitch, 8 mm tape and reel -115 -135
Reflow soldering is the only recommended soldering method.
Dimensions in mm
Fig 5. Reflow soldering footprint SOD323F (SC-90)
001aab169
1.65
0.50
(2×)
2.10
1.60
2.80
0.60
3.05
0.95 0.50
solder lands
solder resist
occupied area
solder pasteBAT54J_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 8 March 2007 6 of 8
NXP Semiconductors BAT54J
Schottky barrier single diode
11. Revision history
Table 9. Revision history
Document ID Release date Data sheet status Change notice Supersedes
BAT54J_1 20070308 Product data sheet - -BAT54J_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 8 March 2007 7 of 8
NXP Semiconductors BAT54J
Schottky barrier single diode
12. Legal information
12.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
12.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
12.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied,