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Farnell PDF
Guide pratique de mise à jour du firmware d'un SSD - Crucial
Guide pratique de mise à jour du firmware d'un SSD - Crucial
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Farnell Element 14 :
See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…
Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.
Puce électronique / Microchip :
Sans fil - Wireless :
Texas instrument :
Ordinateurs :
Logiciels :
Tutoriels :
Autres documentations :
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Introduction
Ce document détaille la procédure de mise à jour du firmware
du SSD Crucial m4 via notre utilitaire de mise à jour Windows.
L’utilitaire consiste en un seul fichier exécutable qui contient tous
les codes nécessaires pour procéder à la mise à jour. La création
d’un support de démarrage distinct est inutile.
Ce programme est destiné à la mise à jour du firmware depuis les
révisions 0001, 0002, 0009, 0309, 000F et 010G vers la révision
040H.
REMARQUE : Cette mise à jour du firmware ne s’applique pas
à tous les SSD Micron acquis seuls ou en tant que matériel de
première monte d’un ordinateur. Les mises à jour de firmware de
ces disques là seront, le cas échéant, fournies par le fabricant de
l’ordinateur ou seront disponibles sur www.micron.com. Cette
mise à jour du firmware ne concerne pas n’importe quel disque
Micron RealSSD C300. De même, elle ne doit pas être utilisée
pour un SED (Self Encrypting Drive) Micron RealSSD C400. Cette
mise à jour s’applique uniquement aux disques m4 2,5” et ne
doit pas être utilisée pour mettre à jour des disques m4 mSATA.
AVERTISSEMENT : Comme pour toutes mises à jour, il est
fortement recommandé de sauvegarder ou de copier tous vos
fichiers importants auparavant. Cette procédure de mise à jour
du firmware s’effectue sous votre seule responsabilité. Si elle
est exécutée correctement, il n’y aura aucune perte de données
système ou utilisateur présentes sur le disque. Toutefois, une
interruption de la mise à jour, quelle qu’en soit l’origine, peut
entraîner le dysfonctionnement de votre SSD. Si cette mise à
jour est appliquée sur un ordinateur portable, il est fortement
recommandé de le brancher en secteur pendant la procédure.
Instructions générales
Procédez aux opérations suivantes avant de démarrer la
procédure de mise à jour du firmware :
1. Sauvegarde du contenu du SSD
Il est fortement recommandé de procéder à une sauvegarde
complète du système avant de démarrer cette mise à jour
du firmware. Si la procédure de mise à jour est interrompue
(coupure d’alimentation ou défaillance matérielle de
toute nature), il est possible que le SSD ne fonctionne pas
correctement.
2. Utiliser une alimentation CA
Veillez à ce que votre ordinateur portable ou de bureau soit
relié à une alimentation CA pendant la mise à jour. Il est
déconseillé de n’utiliser que la batterie pendant la procédure.
Ne débranchez l’alimentation à aucun moment de la procédure
de mise à jour du firmware car cela pourrait aboutir à un
déroulement incomplet de celle-ci et donc, rendre le SSD
inutilisable.
3. Désactiver/supprimer les mots de passe associés au disque
La protection par mots de passe, comme le cryptage du disque
contenant le SE ou les mots de passe du BIOS, peut bloquer
les mises à jour du firmware. Le cryptage du disque peut être
désactivé via le SE ou le logiciel de cryptage. Pour désactiver
un mot de passe de BIOS, vous devez éditer les paramètres
de votre BIOS. Veuillez consulter le manuel utilisateur de votre
ordinateur pour savoir comment procéder. Entrez dans le BIOS
(généralement en appuyant sur les touches « Suppr », « F2 »
ou « F12 » au démarrage de l’ordinateur) et désactivez tous les
mots de passe éventuellement associés au SSD.
4. Mettre à jour Microsoft .NET Framework
Pour être compatible avec Windows 7 et 8, cet utilitaire de
mise à jour du firmware a été conçu avec Microsoft .NET
Framework 4. Il se peut que certains utilisateurs de Windows
7 doivent mettre à jour leur version de .NET Framework pour
exécuter cet utilitaire. Si le message d’erreur suivant apparaît
à l’exécution de l’utilitaire de mise à jour, veuillez mettre à jour
.NET Framework via Windows Update.
Guide pratique de mise à jour du firmware d’un SSD
Guide de mise à jour du firmware du SSD Crucial®
m4 2,5” vers la révision 040H - Windows 7 et 8
(mise à jour depuis les versions 0001, 0002, 0009, 0309, 000F, 010G vers la version 040H)Guide pratique de mise à jour du firmware d’un SSD
Guide de mise à jour du firmware du SSD Crucial®
m4 2,5” vers la révision 040H - Windows 7 et 8
(mise à jour depuis les versions 0001, 0002, 0009, 0309, 000F, 010G vers la version 040H)
Téléchargez la mise à jour du firmware
1. Avant de commencer le téléchargement du firmware,
fermez tous les autres programmes, sauf votre navigateur
internet.
2. Recherchez l’utilitaire Windows de mise à jour du firmware
associé à votre SSD Crucial m4 à l’adresse : http://www.
crucial.com/support/ firmware.aspx
3. Cliquez sur le lien correspondant et sélectionnez
Enregistrer pour télécharger le fichier *.ZIP contenant
l’utilitaire de mise à jour pour votre système.
4. Double-cliquez sur le fichier *.ZIP pour extraire son
contenu. Enregistrez les fichiers extraits sur votre bureau.
Lancez la mise à jour du firmware
1. Si ce n’est pas déjà fait, copiez l’utilitaire de mise à jour sur
votre bureau.
2. Double-cliquez sur l’icône pour lancer l’utilitaire de mise à jour.
3. Une fenêtre de contrôle des comptes d’utilisateurs s’affichera :
Assurez-vous que l’éditeur soit bien Micron Technology, Inc. Si
ce n’est pas le cas, sélectionnez No (Non) pour interrompre cette
opération. Cliquez sur Yes (Oui) pour continuer si la signature du
fichier est exacte.
4. Vous devez accepter le Contrat de Licence pour poursuivre.
Lorsque la fenêtre suivante apparaît, cliquez sur le bouton «
Licence ».
5. Parcourez et lisez le Contrat de Licence du logiciel. Pour
continuer, cliquez sur le bouton Accept (Accepter).
6. L’utilitaire est prêt à démarrer la procédure de mise à jour.
Avant de cliquer sur Continue (Continuer), assurez-vous que
toutes les autres tâches ont été sauvegardées et toutes les
applications ouvertes ont été fermées. Un clic sur Continue
(Continuer) déclenchera la procédure. Windows sera arrêté
et l’ordinateur redémarré.
7. Votre ordinateur redémarrera sur l’utilitaire de mise à jour.
L’écran affichera ceci :
8. Après le chargement complet de l’utilitaire de mise à jour, ces
éléments apparaîtront à l’écran :
La mise à jour est possible depuis les révisions 0001, 0002, 0009,
0309, 000F ou 010G du firmware ; c’est pourquoi l’une d’entre
elles peut apparaître sur l’écran ci-dessus (juste en dessous du
numéro de série de votre disque). Si votre disque m4 est absent
de la liste affichée sur l’écran ci-dessus, veuillez vous reporter
au paragraphe « Astuces de dépannage » à la page suivante.
9. L’utilitaire mettra à jour votre firmware immédiatement en
affichant cette mention :
10.Sur la plupart des systèmes, cette procédure durera entre 30
et 60 secondes. Dans certains cas, cela peut être plus long.
11. À la fin de la procédure, le message suivant apparaîtra :
12.Après quelques secondes, le système redémarrera à nouveau,
relançant Windows.
13.Lorsque Windows a correctement redémarré, la mise à jour
du firmware est terminée.Astuces de dépannage
• Bien que tout ait été mis enœuvre pourtesterla compatibilité
de ce logiciel avec différentes configurations de systèmes
et de jeux de composants, il est impossible de procéder à
des essais sur tous les systèmes existants. Par conséquent,
certains systèmes (anciens par exemple) peuvent se heurter
des problèmes de compatibilité.
• Si vous rencontrez des difficultés après le redémarrage de
l’utilitaire, vérifiez que vous avez désactivé tous les mots de
passe du BIOS.
• Si votre disque m4 n’est pas reconnu lors de l’étape 8 du
paragraphe « Lancez la mise à jour du firmware », il peut
s’avérer nécessaire d’exécuter cette mise à jour en mode
IDE et non AHCI, sur certains systèmes anciens. Si un
basculement du mode IDE ou AHCI est nécessaire, il peut
falloir redémarrer le système au moyen d’un support externe
tel qu’un CD-ROM amorçable. Des instructions d’exécution
de la mise à jour 040H à partir d’un support amorçable sont
disponibles sur la page d’assistance consacrée aux SSD
http://www.crucial.com/support/firmware.aspx
• Certains systèmes empêchent les mises à jour de firmware
en mode RAID. Dans ce cas, le basculement en mode AHCI
ou IDE peut aider à terminer la mise à jour. Toutes les
configurations RAID devraient être conservées après la mise
à jour, lorsque le système rebascule en mode RAID mais
vérifiez ceci dans le manuel utilisateur de votre système
avant de démarrer la procédure.
• Les cartes RAID périphériques ne transmettront pas les
commandes nécessaires aux mises à jour du firmware. Il
se peut que vous deviez déplacer le disque cible sur un
adaptateur de bus hôte SATA ou un connecteur SATA de la
carte mère qui facilite ces commandes.
• Cet utilitaire de mise à jour du firmware peut ne pas
fonctionner sur des ordinateurs fixes, portables ou des
tablettes disposant d’une interface UEFI. Nous mettrons
à disposition un outil de mise à jour séparé qui prendra
en charge les mises à jour du firmware sous UEFI (Unified
Extensible Firmware Interface).
Vérification de la version actuelle du
firmware
Dans Windows 7, l’utilisateur peut vérifier la version actuelle
du firmware du disque en suivant la procédure suivante :
• Cliquez sur le bouton “Démarrer” de Windows, puis sur
“Ordinateur”.
• Faites un clic droit sur l’icône correspondant à votre disque
et sélectionnez “Propriétés”.
• Dans la fenêtre qui s’affiche, sélectionnez l’onglet “Matériel”.
• Dans la liste Tous les lecteurs de disque, sélectionnez votre
disque m4 et cliquez sur “Propriétés”.
• Dans la fenêtre suivante, sélectionnez l’onglet “Détails”.
• Dans le menu déroulant Propriété, sélectionnez “Numéros
d’identification du matériel” et les mentions suivantes
apparaîtront :
• La version actuelle du firmware est entourée en rouge sur
la capture d’écran ci-dessus. Si la révision du firmware est
la 040H, aucune autre action n’est nécessaire.©2012 Micron Technology, Inc. Tous droits réservés. Ces informations peuvent être modifiées sans avis préalable.
Crucial et le logo Crucial sont des marques commerciales ou marques de service de Micron Technology, Inc.
Toutes les autres marques commerciales et marques de service sont la propriété de leurs détenteurs respectifs. REVISION: 04/12/12 FW040H
Notes de version du firmware
Le firmware du SSD m4 a été mis à jour de la version 010G
à 040H.
Le firmware 040H est recommandé pour tous les disques
disposant de la version 010G, ou précédentes. Il comporte
des améliorations et corrections cumulatives par rapport à
ces versions, susceptibles d’améliorer l’expérience utilisateur
globale.
Comme le firmware 010G, la version 040H contient des
améliorations par rapport à la version 000F et aux révisions
précédentes, notamment pour les systèmes sous Windows
8 et les nouveaux UltraBook, même si des améliorations
peuvent également être constatées sur les systèmes sous
Windows 7 et autres systèmes d’exploitation. Toute version
du firmware du m4 fonctionnera normalement sous Windows
8, même sans ces améliorations de fonctionnement.
Voici un résumé des différences entre la version 010G et
040H, quel que soit le système d’exploitation :
• Amélioration de la fiabilité en cas de coupure d’alimentation
inattendue.* Réduction significative des effets de durées de
redémarrage prolongées après une coupure d’alimentation
inattendue.
• Correction d’un problème concernant le statut du lecteur
lors de l’exécution du test SMART Drive Self Test (n’affecte
pas les données d’attribut SMART).
• Amélioration du processus de mise à jour pour Windows 8.
• Amélioration des algorithmes de gestion de l’usure du SSD
afin de réduire leur influence sur les débits.
* Une « coupure d’alimentation inattendue » lorsqu’une
coupure d’alimentation n’est pas précédée d’une commande
ATA de VEILLE IMMÉDIATE ou autre commande identique. La
VEILLE IMMÉDIATE est une commande système qui avertit
le dispositif de stockage d’une coupure d’alimentation
imminente ou d’un passage en modes basse consommation
tels que la VEILLE ou VEILLE PROLONGÉE. Généralement, la
VEILLE IMMÉDIATE ne se déclenche pas quand la coupure
d’alimentation est due à une coupure de connexion électrique,
une batterie épuisée ou au maintien du bouton Power pendant
au moins 4 secondes. Bien que le nouveau firmware réduise
significativement le risque, ce type de coupures d’alimentation
inattendues peuvent entraîner un temps de redémarrage plus
long à la mise sous tension suivante. D’un autre côté, un
arrêt normal sur un système Windows ou Mac déclenchera la
commande VEILLE IMMÉDIATE auparavant, permettant ainsi
un démarrage sans encombre lors de sa remise sous tension.
Versions précédentes
Rév. A………………………………………………………… 4 Décembre 2012
• Version initiale
Introduction
Ce document décrit le processus de mise à jour du
microprogramme sur l’unité Crucial m4 SSD en utilisant votre
fonction de mise à jour Windows. La fonction est un seul fichier
exécutable qui contient tous les codes nécessaires pour faire
une mise à jour. La création d’une unité amorçable séparée n’est
pas nécessaire.
Ce programme peut être utilisé pour la mise à jour du
Microprogramme de Révisions 0001, 0002, 0009, 0309 ou 000F
vers Révision 010G.
ATTENTION : Cette mise à jour pour microprogramme
ne s’applique pas à toute unité Micron SSD qui a été achetée
séparément ou comme équipement d’origine dans le système
informatique. Toute mise à jour pour microprogramme pour
une telle unité sera mise à disposition, si besoin, par le fabricant
de l’ordinateur ou sur www.micron.com. Cette mise à jour pour
microprogramme ne s’applique pas aux unités Micron RealSSD
C300. La mise à jour ne devrait pas être utilisée non plus pour
toute unité Micron RealSSD C400 Self Encrypting Drive (SED)
[Unité Auto-Encryptage]. Cette mise à jour est uniquement
destinée aux unités 2.5’’ m4 et ne devrait pas être utilisée pour
mettre à jour des unités mSATA m4.
AVERTISSEMENT : Comme pour toute mise à jour pour
microprogramme, il est fortement recommandé de faire
une sauvegarde ou des copies des fichiers importants avant
d’exécuter cette mise à jour. L’exécution de la mise à jour pour
microprogramme est entièrement à votre risque. Si exécutée
correctement, le système ou les données sur l’unité ne seront
pas perdus. Cependant, si le processus est interrompu, votre
unité SSD peut ne pas fonctionner correctement. Si cette mise
à jour est effectuée sur un ordinateur notebook, il est fortement
recommandé d’utiliser un adaptateur courant alternatif pour
alimenter l’ordinateur en électricité.
Instructions Générales
Complétez les étapes suivantes avant de démarrer le
processus de mise à jour pour microprogramme :
1. Faire une sauvegarde de l’unité SSD
Il est fortement recommandé de faire une sauvegarde
complète avant de démarrer cette procédure de mise à jour.
Si la mise à jour est interrompue (coupure de courant ou panne
d’équipement…), il est possible que l’unité SSD ne fonctionne
pas correctement.
2. Utiliser du courant alternatif
Assurez-vous que votre ordinateur portable ou PC est
alimenté avec du courant alternatif pendant le processus de
mise à jour. Il n’est pas recommandé d’utiliser uniquement
la batterie pendant la mise à jour. Ne coupez pas le courant
pendant le processus de mise à jour pour microprogramme
car ceci pourrait donner un résultat incomplet et rendre votre
unité SSD inutilisable.
3. Désactiver/Supprimer les Mots de passe sur l’Unité
La protection par mot de passe, comme l’encryptage sur unité
OS ou des mots de passe au niveau BIOS, peuvent bloquer les
mises à jour du microprogramme. L’encryptage de l’unité peut
être désactivé dans l’OS ou l’outil de logiciel que vous utilisez
pour l’encryptage. Pour désactiver un mot de passe BIOS, il faut
régler les paramètres BIOS sur votre ordinateur. Consultez le
mode d’emploi de votre ordinateur pour les détails concernant
le réglage de ces paramètres. Rentrez le BIOS (normalement
en appuyant sur « Supprimer », « F2 » ou « F12 » pendant le
démarrage de l’écran) et désactivez tout mot de passe que
vous avez pu programmer sur l’unité SSD.
4. Mise à jour Microsoft.NET Framework
Afin de pouvoir être compatible avec Windows 7 et Windows
8, cet outil de mise à jour pour microprogramme est construit
sous Microsoft.NET Framework 4. Certains utilisateurs Windows
7 doivent mettre à jour leur version .NET Framework afin de
pouvoir activer cet outil. Si le message d’erreur suivant s’affiche
quand vous utilisez la mise à jour pour microprogramme,
utilisez la fonction Windows Update [mise à jour Windows]
pour mettre à jour .NET Framework.
Guide pour la Mise à Jour du Microprogramme SSD
Guide pour la mise à jour du microprogramme Crucial®
m4 2.5’’ Révision 000F pour Windows 7
+ Windows 8 (Mise à jour du Rév 0001,0002, 0009, 0309, 000F vers Rév 010G)Guide pour la Mise à Jour du Microprogramme SSD
Guide pour la mise à jour du microprogramme Crucial®
m4 2.5’’ Révision 000F pour Windows 7
+ Windows 8 (Mise à jour du Rév 0001,0002, 0009, 0309, 000F vers Rév 010G)
Télécharger la Mise à jour pour
Microprogramme
1. Avant de commencer le processus de mise à jour pour
microprogramme, fermez tous les programmes sauf votre
navigateur Internet.
2. Trouvez la Fonction Mise à jour Microprogramme Windows
associé avec votre unité Crucial m4 SSD sur http://www.
crucial.com/support/firmware.aspx
3. Cliquez sur le lien pour la Fonction Mise à jour
Microprogramme Windows et sélectionnez Save pour
télécharger le fichier ZIP qui contient l’outil mise à jour
microprogramme, sur votre système.
4. Double-cliquez sur le fichier ZIP pour extraire les fichiers.
Sauvegardez-les sur votre PC.
Exécuter la Mise à jour pour
Microprogramme
1. Si vous ne l’avez pas encore fait, copiez le fichier fonction
mise à jour sur votre PC.
2. Double-cliquez sur l’icône pour démarrer la fonction de mise
à jour.
3. Un cadre Gestion du Compte Utilisateur apparait :
Assurez-vous que l’Editeur Vérifié est bien « Micron Technology,
Inc. ». Si ce n’est pas le cas, sélectionnez « No » pour arrêter
cette opération. Cliquez « Yes » pour continuer si le fichier est
correctement signé.
4. Vous devez accepter l’Accord de Licence afin de pouvoir
continuer. Quand vous voyez la fenêtre suivante, cliquez sur
la touche « License ».
5. Lisez l’Accord de License pour le Logiciel. Si vous souhaitez
continuer, cliquez sur la touche « Accept ».
6. La fonction est prête à démarrer le processus de mise à jour.
Avant de cliquer sur « Continue », assurez-vous que tout
votre travail est sauvegardé et que les applications ouvertes
sont fermées. En cliquant sur « Continue », le processus
commencera, Windows sera fermé et votre ordinateur sera
redémarré.
7. Votre ordinateur redémarre et va vers l’outil de mise à jour.
Vous voyez le message suivant sur votre écran :
8. Une fois l’outil de mise à jour complètement chargé, vous
voyez le suivant :
Il est acceptable de faire une mise à jour du microprogramme de
la révision 0001, 0002, 0009, 0309 ou 010G donc vous voyez
peut-être une de ces révisions sur l’écran (juste en dessous le
numéro de série de votre unité). Si votre unité m4 n’est pas listée
sur l’écran, vérifiez la section « Astuces Dépannage » en dessous.
9. La fonction exécutera immédiatement la mise à jour de votre
unité, indiquant le message suivant :
10.Sur la plupart des systèmes, ce processus prend entre 30
et 60 secondes. Certains systèmes peuvent prendre plus
longtemps.
11. Une fois ce processus complété, le message suivant
s’affiche :
12.Après quelques secondes, le système sera réinitialisé
à nouveau, Windows redémarre.
13.Quand Windows redémarre normalement, le processus de
mise à jour pour microprogramme est complété.Astuces Dépannage
• Malgré des efforts faits pour tester la compatibilité de ce
logiciel avec des configurations de différents systèmes
et de jeux de composants, il n’est pas possible de tester
tout système disponible. Certains systèmes (par ex. des
systèmes plus anciens) peuvent donc avoir des problèmes
de compatibilité.
• Si vous avez des problèmes après la réinitialisation de l’outil,
vérifiez que vous avez bien désactivé les mots de passe
BIOS sur l’unité.
• Si votre unité RealSSD m4 n’est pas reconnue pendant
l’étape 8 de la section « Exécuter la Mise à jour pour
Microprogramme » ci-dessus, il peut être nécessaire
d’exécuter cette mise à jour sur certains systèmes plus
anciens en mode IDE au lieu du mode AHCI. Quand vous
devez changer le système en mode IDE ou AHCI, il peut être
nécessaire de réinitialiser le système en utilisant un média
externe comme un CD-ROM amorçable. Des instructions
pour exécuter la mise à jour 010G à partir des médias
amorçables sont disponibles sur la page SSD Support sur
http://www.crucial.com/support/firmware.aspx
• Certains systèmes bloquent une mise à jour pour
microprogramme quand en mode RAID. Dans ce cas,
changer en mode AHCI ou IDE peut aider à compléter le
processus de mise à jour. Toute configuration RAID doit
être préservée après la mise à jour pour quand le système
est à nouveau mis en mode RAID, mais vérifiez le mode
d’emploi pour votre système avant de continuer.
• Des cartes périphériques RAID ne font pas passer les
commandes nécessaires pour exécuter des mises à jour
pour microprogramme. Vous devez peut-être déplacer
l’unité cible vers un adaptateur de bus hôte SATA ou
un connecteur SATA sur la carte-mère qui accepte ces
commandes.
• Cetoutil demise à jour pourmicroprogramme ne fonctionne
peut-être pas correctement sur des PCs, notebooks ou
tablettes avec BIOS-UEFI. Nous proposerons un outil de
mise à jour séparément qui accepte les mises à jour pour
microprogramme avec UEFI [interface micrologicielle
extensible unifiée].
Validation de la Révision Actuelle
du Microprogramme
Windows 7 permet à l’utilisateur de vérifier la révision
actuelle du microprogramme pour l’unité en suivant les
étapes suivantes :
• Cliquez sur Windows « Start » et sélectionnez « Computer
».
• Sur l’icône du disque, représentant votre unité, faites
un clic-droit et sélectionnez « Properties ».
• Dans la fenêtre qui s’ouvre par la suite, vous sélectionnez
l’onglet « Hardware ».
• Dans la liste All Disk Drives, vous sélectionnez votre unité
C400 et vous cliquez sur « Properties ».
• Dans la fenêtre suivante qui s’ouvre, sélectionnez la page
« Details ».
• Dans le menu déroulant Property, sélectionnez « Hardware
Ids « , ensuite vous voyez le suivant :
• La révision actuelle du microprogramme est entourée
en rouge. Si la révision du microprogramme indique
« 010G », aucune action supplémentaire est nécessaire.REVISION : 11/5/12 FW010G
©2012 Micron Technology, Inc Tous droits réservés. L’information peut être modifiée sans notification.
Crucial et le logo Crucial sont des marques commerciales de Micron Technology, Inc. Toute autre marque
commerciale et marque de service est la propriété des propriétaires respectifs.
Notes de Publication pour
Microprogramme
Le microprogramme pour l’unité SSD m4 est mis à jour de la
version 000F vers la version 010G.
Microprogramme 010G est une option pour toute personne
qui utilise actuellement la version 000F comme la nouvelle
version comprend des améliorations incrémentales mais est
recommandé si l’utilisateur a eu des problèmes avec la version
actuelle.
La version 010G comprend des améliorations spécifiques
pour Windows 8 et des nouveaux systèmes UltraBook, même
si Windows 7 et d’autres systèmes et des plates-formes
informatiques peuvent également voir des améliorations.
Toute version m4 pour microprogramme fonctionnera
normalement dans Windows 8. Cependant, les améliorations
suivantes ont été ajoutées pour répondre aux nouvelles
exigences de certification pour ce système d’exploitation :
Améliorations pour Windows 8
• Meilleur Time-to-ready (« TTR ») après un cycle
de détente. TTR est maintenant moins de 850
millisecondes pour tous les points de capacité. Un «
cycle de détente » est une séquence OFF-ON suite à
une commande STANDBY IMMEDIATE envoyée par
l’hôte et acceptée par l’unité SSD. STANDBY IMMEDIATE
est typiquement envoyée durant une mise à l’arrêt du
système d’exploitation.
• Ce changement améliore également le temps resumefrom-sleep
afin de répondre aux nouvelles exigences
Windows 8.
• Le temps de réponse a été réduit de 50ms à 20ms
(typique).
Consommation d’électricité améliorée pour certains
ordinateurs notebook
• HIPM (Host Initiated Power Management) n’est plus
accepté. Dans certains ordinateurs notebook, HIPM
peut interférer avec la capacité de SSD de rentrer et
de rester dans des modes basse consommation en
utilisant DIPM (Device Initiated Power Management).
Utiliser DIPM seul est la méthode la plus efficace pour
conserver la puissance SSD.
• SATA pin 11 (Device Activity Signal) est électroniquement
isolé de l’hôte quand l’unité SSD est en mode basse
consommation. Ceci élimine une voie de fuite
potentielle qui peut consommer de l’électricité pendant
que l’unité SSD soit en veille. Ceci n’affecte pas la
plupart des systèmes informatiques.
Historique des Révisions
Rév. A…………………………...............………….25 septembre 2012
• Publication Initiale
Summary
This white paper addresses the energy consumption of DRAM in computing applications and the
opportunities to maximize energy savings by targeting more efficient products for data center servers.
Micron estimates module power savings at 24 percent; this has the potential to achieve energy savings
of 5.5 billion kilowatt hours (kWh) on a global basis annually. At typical industrial power costs1 ($0.06
per kWh), the savings are more than $300 million per year.
Michael Sporer
Regional Sales Manager, Micron Memory Products Group
©2008 Micron Technology, Inc. All rights reserved 1
The power demands of data centers require memory innovationsThe power demands of data centers require memory innovations
Introduction
The U.S. EPA Energy Star program is conducting a study to assess opportunities for energy efficiency
improvements to computer servers and data centers2. This is in response to Public Law 109-431, which
was passed and signed into law December 20, 20063. This legislation requires an investigation down to
the microchip level. As a manufacturer of semiconductor memory products used in server systems, Micron
intends to proactively address these opportunities.
Justification
A recent study conducted by Dr. Jonathan Koomey4 with the Lawrence Berkeley National Laboratory (LBL)
and funded by Advanced Micro Devices (AMD), illustrated the significant and growing energy use by
data centers. Data centers are rooms, floors or sometimes entire buildings that house computer, storage,
and networking equipment. Data centers can serve up Web pages, stream media, enable Internet access,
and run simulations of any kind of research. They can also provide computing power for traditional and
private uses like banking or other financial transactions.
The computers in data centers, called servers, are similar to PCs in that they have the same basic
microchips—the CPU and memory. Unlike PCs, servers in data centers are packed together as densely
as possible and use substantial amounts of electricity, the majority of which ends up in the form of heat,
which then must be removed from the servers. The power delivery to the systems is provided through
uninterruptible power supplies (UPS) that are not 100 percent efficient and also produce copious amounts
of heat as well. The heat must be carefully and continuously managed to keep the systems running within
their specified operating temperature and humidity ranges. Regardless of the type and efficiency of the
cooling system, the heat must be removed from the data center in one way or another. To do so requires
additional energy be used to operate the cooling infrastructure.
©2008 Micron Technology, Inc. All rights reserved 2
The data centers’ incremental
overhead power consumption
due to inefficiencies and
cooling is estimated to be
equal to the amount that is
consumed by servers, storage,
and networkingIntroduction
The data centers’ incremental overhead power consumption due to inefficiencies and cooling is estimated
to be equal to the amount that is consumed by servers, storage, and networking. The user of a single PC,
workstation, or laptop doesn’t see system heat generation ias a concern, but for data centers, managing
the overhead is as important as the servers themselves. If system power is reduced, then the available
overhead can handle a greater IT load and perform more useful work in the same power envelope.
The Role Memory Plays in the Challenges of Servers and Energy Use
The memory content in servers has been growing at a rapid pace and is expected to continue to do so
for a variety of reasons. In general, software with more functionality requires both greater computational
ability as well as a larger memory footprint. However, some factors are more applicable to servers than
PCs.
First is the proliferation of multi-core CPUs executing single-threaded applications. Each thread requires
its own memory space, therefore doubling the number of CPU cores requires doubling the memory. A
recent seminar5 on server design cited this rule of thumb:
1GB per (1 GHz × # cores)
This equation reinforces the idea that each CPU core mandates an increase in memory space. Another
factor driving memory content growth and server power consumption is the adoption of virtualization
technologies. A server running a virtualized environment is able to achieve a higher utilization which, in
turn, increases the total power consumption of the server. Once again, the importance of energy efficient
component selection increases. By analogy, a car will burn very little fuel if it isn’t driven. Virtualization, or
anything that increases server operation, is like adding a new driver to the mix. Now the car gets driven
more and energy efficiency becomes a greater concern.
Traditionally, the CPU has been the component that consumes the most power in the system. Improvements
in CPU power consumption now place a greater scrutiny on the other components. Where memory once
played a distant second to CPUs in the ranking of system power consumption, now, in some cases, it
exceeds the power consumption of the CPU.
The power demands of data centers require memory innovations
©2008 Micron Technology, Inc. All rights reserved 3
The memory content in servers
has been growing at a rapid
pace and is expected to
continue to do so for a variety
of reasonsThe power demands of data centers require memory innovations
Energy Efficient Memory Advantages
Micron’s new energy efficient Aspen Memory® product line includes several new products that have a
lower power consumption compared to legacy standard products. These technologies are intended for
use in both client machines—PCs, laptops, workstations—as well as in servers.
The new products are 1Gb-based, DDR2 reduced chip count (RCC) modules; and 1.5V DDR2 FBDIMMs.
The 1.5V DDR2 SDRAM operates at 1.5V instead of 1.8V. The 1Gb-based, DDR2 RCC modules provide the
same memory capacity and performance as a DIMM built using legacy (currently 512Mb) devices, but
use half as many higher density (1Gb) DRAM devices (see Appendix A for product details). The combined
savings of these two technologies is estimated to be 24 percent of the memory DIMM power consumption.
For reasons previously cited, extrapolating the savings to the system level is difficult; instead, we have
directly measured power savings at the power supply input of the server under test.
Under minimum and maximum loading conditions and using commercially available systems, Micron
has measured between 1.5 to 1.8 watts per 2GB DIMM improvement in power consumption when
comparing standard legacy products to 1Gb-based, DDR2 reduced chip count DIMMs.
Measurements made in a lab environment using modified commercial hardware with the adaptations
required to support 1.5V DDR2 on FBDIMMs show power reductions in the 1.5 to 2.0 watts per 4GB 1.5V
DIMM attributed only to the DRAM. Additional power savings could be possible using a low-voltage
advanced memory buffer (AMB) chip, which is also on the FBDIMM.
For the purpose of the analyses that follow, it is necessary to convert these savings into a percentage
basis. We will assume a conservative 24 percent DIMM-level savings for the 1Gb-based, DDR2 RCC
DIMM and 1.5V DDR2 SDRAM.
©2008 Micron Technology, Inc. All rights reserved 4
The combined savings of these
two technologies—1Gbbased,
DDR2 reduced chip
count modules and 1.5V
DDR2 SDRAM devices—is
estimated to be 24 percent
of the memory DIMM power
consumptionThe power demands of data centers require memory innovations
Data Centers and Energy Use
According to Dr. Koomey’s report, data center servers consumed 616 billion kWh worldwide in 2005. The
historical growth rate of this figure has been 15 percent annually from the year 2000 to 2005.
Estimating the power consumption attributed to memory is a difficult challenge. A computer system has
multiple memory sockets that can be fully or partially populated with memory modules, and the memory
module density can also vary. In addition to these physical variations, the portion of power attributed to
memory also depends on the type of workload and memory utilization. Certainly, further study is needed
in this area. For the purpose of this paper we are going to assume memory accounts for 20 percent7 of
the total system power budget in a server. The reader can adjust this assumption
as needed.
Micron has come up with an alternative method for estimating DRAM power consumption (summarized
here; details in Appendix C). This method incorporates analysts’ data to estimate the total DRAM
production in a given year and the DRAM consumption by market segment. This method also makes
assumptions regarding hours of operation as well as system utilization to estimate power consumption
and potential savings. (Figure 2 provides the estimate for calendar year 2008.)
The production of DRAM is quantified in terms of 512Mb equivalent units. For example, a single 1Gb
DRAM is equivalent to two 512Mb devices. First, we divide the market into three categories: server, client,
and other. The client-machine category includes desktops, laptops, and workstations. The other category
is a catch-all for non-computing markets and is not considered in this analysis. Given these market
segments, it’s apparent that the client market consumes four times as many DRAM equivalent units as
the server market.
Next, we consider the hours of operation and system utilization on an annual basis. Servers operate 24
hours a day, 7 days a week; client machines operate approximately 8 hours a day, 5 days a week. Server
utilization is assumed to be 15 percent; client, 5 percent. By applying the usage model to each DRAM
market, we conclude that despite the four-to-one difference in shipments, the DRAM in servers consumes
more power than all DRAM in the client machines.
©2008 Micron Technology, Inc. All rights reserved 5
Estimation of Memory Power
Consumption and Potential Savings
Illustrates the potential savings. For a detailed description, see Appendix B.
2005
61 billion kWh servers
12 billion kWh servers
20%
24%
2.9 billion kWh potential
savings in 2005
34 billion kWh
non-memoryThe power demands of data centers require memory innovations
Next, we consider the total available 1Gb DRAM which could be used to build the 1Gb-based, DDR2 RCC
DIMMs (see Appendix A for RCC details). For 2008, all 1Gb DRAM production is estimated to be enough
to provide for 98 percent of the total demand for servers or 24 percent of the total demand for client
machines. Finally, we look at the potential power savings for all the 1Gb-based, DDR2 RCC DIMMs if they
were installed into either client machines or servers.
When we analyze this power-savings comparison, we see that although the DIMM power requirements
and potential savings are identical in either application, the cumulative energy savings is substantial for
the server market due the longer hours of operation and higher utilization factors of server platforms. In
this example, 462 million kWh energy savings would be achieved for energy efficient DRAM devices sold
this year. This approach would conserve 2.3 billion kWh over a five-year product lifecycle.
©2008 Micron Technology, Inc. All rights reserved 6
Savings in servers are much
greater because, unlike client
machines, servers are always
running
Estimation of power conusmption based on annual
DRAM manufacturing and market usage
13,849 million 512Mb EQ
DRAM produced
1,870 million in servers 7,478 million in
client machines
66MW
potential savings
13MW
potential savings
53MW could be saved by steering all available
1Gb DRAM to servers instead of client machines in 2008
463 million kWh per year
2,314 million kWh potential savings in 2008
9,348 million in servers and
client machines
135MW total power
for all DRAM in servers
109MW total power
for all DRAM
in client machines
67.5%
High use Low use
If all 1Gb went into
servers as RCC
If all 1Gb went into
client machines as RCC
Straight conversion to
kWh annually
Assume 5-year lifecycle; extrapolate
to the entire installed base
20%
Other marketsThe power demands of data centers require memory innovations
Comparing the Two Methods
Let’s attempt to correlate the two estimation methods. First we need to look at the differences so we
can compensate accordingly. The first method is based on data from 2005 and assumes both 1Gb-based,
DDR2 RCC DIMMs and 1.5V devices are placed into the installed base. The second method is based on
data for 2008 and assumes only 1Gb-based, DDR2 RCC DIMMs are used (see figure below).
To extrapolate from 2005 to 2008, we will assume a 15 percent annual growth rate consistent with the
previous five years. As a first approximation we will assume that the savings from 1.5V DDR2 devices
and 1Gb-based, DDR2 RCC modules are equal. As shown below, both methods demonstrate 4.5 billion
kWh annual potential savings for DRAM in servers. The aggregate data center energy savings would
be doubled when considering the incremental overhead and cooling energy costs. Alternately, instead
of reducing power consumption, these savings could be used to support more IT equipment within the
existing infrastructure, resulting in better asset utilization and deferring the need for new data center
construction.
©2008 Micron Technology, Inc. All rights reserved 7
Comparing the Two Methods for Estimating Energy Savings
4.4 billion kWh in 2008 -4.6 billion kWh from both
RCC and 1.5V devices
4.5 billion kWh from both
RCC and 1.5V devices
Savings from overhead roughly equal to IT load;
therefore, 4.5 billion x 2 = -9 billion kWh savings
2.9 billion kWh in 2005
potential saving from RCC and 1.5V devices
2.3 billion kWh in 2008
potential saving from RCC only
Data Center
Use Calculation
DRAM Production
Calculation
Extrapolate to 2008 based on 15%
annual growth historical trend
Reasonable
agreementThe power demands of data centers require memory innovations
Conclusion
This paper brings together three important findings for memory with respect to energy consumption in
computing applications. First, we highlight the growing memory content per server due to the increasing
deployment of multi-core CPUs. We also discuss the relative importance of memory as CPUs and other
sub-assemblies are being optimized for lower energy consumption. Second, we demonstrate two methods
for estimating the energy consumption and potential savings of DRAM in both the general computing
market and data centers. This also reinforces the idea that the greatest opportunity for power savings is
in data center applications due to servers’ high utilization. Finally, we show how a significant reductions
in power consumption can be achieved by adopting high-density 1Gb-based, DDR2 reduced chip count
modules with 1.5V DDR2 SDRAM devices.
©2008 Micron Technology, Inc. All rights reserved 8
The greatest opportunity for
power savings is in data center
applications due to servers’
high utilizationThe power demands of data centers require memory innovations
Appendix A: Product Availability
Micron has introduced a product line which features products that are optimized for low power
consumption and have superior performance compared to standard products.
1.5V DDR2 Devices
The 1.5V DDR2, DIMMs, and motherboards that can use this technology are currently under development.
Please contact Micron for the latest status.
1Gb-based, DDR2 Reduced Chip Count DIMMs
Currently, 1Gb-based, DDR2 reduced chip count modules are available for a wide range of computer
applications. These 1Gb-based, DDR2 RCC modules provide the same memory capacity and performance
as a DIMM built using legacy (currently 512Mb) devices while using half as many higher density (1Gb)
DRAM chips.
For existing systems that can address 1Gb DRAM technology, the 1Gb-based, DDR2 RCC modules should
easily work. Systems that use registered DIMMs or fully buffered DIMMs (FBDIMMs) and can support a
4GB density should be able to use 2GB reduced chip count DIMMs, which are built using the same 1Gb
DRAM technology.
Some systems require DIMMs to be installed in matched pairs. For these systems, pairing a reduced chip
count DIMM with a standard DIMM could reduce system performance or possibly cause the system to
stop functioning. Oftentimes, a memory upgrade or a firmware or BIOS update will solve the problem.
Refer to your system manufacturer for compatibility questions.
©2008 Micron Technology, Inc. All rights reserved 9
Micron’s Aspen Memory®
product line features modules
that are optimized for low
power consumptionThe power demands of data centers require memory innovations
For some of the more common system questions, check the Micron® motherboard compatibility page
from www.micron.com. For additional compatibility questions, refer to your system manufacturer.
TABLE 1: Quick Reference for Reduced Chip Count DIMMs
Note: Even numbers are for standard DIMMs; odd numbers are for ECC (error correction code) DIMMs.
Appendix B:
Derivation from LBL/AMD8
White Paper
Calculating energy use and potential energy savings has not yet become a standard practice for data
centers. Because of this, many calculations for determining actual energy use can be inaccurate. This
situation is further complicated by the fact that power equipment efficiency is commonly calculated as
the difference between power out and power in.
Power consumed by memory in servers varies significantly depending on many factors. The two primary
factors are the memory capacity of the server relative to the power consumed by the rest of the system
and the second factor is the actual amount of memory installed. We assume 20 percent of the power is
consumed by memory.
61 billion × 0.2 = 12 billion kWh
By implementing 1.5V chips in reduced chip count server modules, data centers could reduce system
memory power consumption by approximately 24 percent, which would be a reduction of 2.9 billion
kWh.
12 billion × 0.24 = 2.9 billion kWh
©2008 Micron Technology, Inc. All rights reserved 10
4 or 5
8 or 9
16 or 18
512MB
1GB
2GB
8 or 9
16 or 18
32 or 36
DIMM Density Number of Chips on a DIMM
Standard Reduced Chip CountThe power demands of data centers require memory innovations
Assuming a power cost of $0.06 per kWh a 24 percent drop in power consumption translates into an
average annual savings of $0.174 billion ($174 million)9.
2.9 billion × 0.06 = $174 million > ~$150 million
Including the savings in overhead power raises this to 5.8 billion kWh and more than ~$300 million,
respectively.
Appendix C:
DRAM Energy Consumption Based on Manufacturing and Market
Another method for determining total energy consumption focuses on cumulative DRAM production and
the applications into which DRAM is placed. According to market analysts although 13.5 percent of total
DRAM gets placed into servers; the majority—54 percent—goes into workstations, PCs, and laptops
(client machines). (The remainder goes into market segments not covered in this paper.)
A typical client machine is operated approximately eight hours a day, five days a week. Utilization of
clients is typically cited at 5 percent. Many government regulatory agencies have instituted energy
efficiency requirements, with EnergyStar in the United States as one such example. Given these factors,
the total energy consumed by DRAM in client machines is reasonably low, even when the power switch is
on throughout the day. Compare that to a typical server in a data center that is powered on twenty-four
hours a day, seven days a week. Utilization of servers is typically cited at about 15 percent. Table 2 shows
the difference in total DRAM power consumption between client and server machines.
©2008 Micron Technology, Inc. All rights reserved 11The power demands of data centers require memory innovations
TABLE 2: Use Percentages of Client Machines and Servers
Note: Client machines limited to desktop, laptop, and workstations.
In Table 2, total power equals the sum of :
Percent of DRAM market × [Power-on hours
× [%Utilization × DIMM Power (Utilized)
+ (1-%Utilization) × DIMM Power (Idle)]]
Table 2 shows that, although client machines have four times more DRAM than servers, the total
DRAM power consumed by servers is nearly equal, if not slightly higher, than power consumed by client
machines. Initially, the implications might not be apparent. Of course, putting more energy efficient
DRAM in either application will save power. The problem, however, is that advanced, energy efficient
DRAM technology is not widely available. Given the limited availability, the question is what is the best
use of what little is available?
To determine what is available, we need to examine the total worldwide production of advanced DRAM
products. Market analyst data in Table 3 shows the distribution of forecasted DRAM production and use
for 2007 and 2008.
©2008 Micron Technology, Inc. All rights reserved 12
54
24
5
6
2
0
0.29
45
%
%
%
Watts per DIMM
Watts per DIMM
Watts per DIMM
%
13.5
100
15
6
2
0
0.35
55
Clients Servers Units
Percent of DRAM market
Annual power-on hours
Utilization
DIMM Power
Utilized
Idle
Sleep
Total Power:
Percent of totalThe power demands of data centers require memory innovations
TABLE 3: Projected Distribution of DRAM Production
Notes:
1. Average of Gartner, iSupply, and IDC.
2. iSupply 4Q06 report.
3. 6W/DIMM typical for system in use; 2W for system idle; 0W for client in E-star or off.
www.sun.com/servers/coolthreads/t2000/calc/
www.sun.com/servers/x64/x2200/calc/
4. Calculated.
5. Maximum savings assumes all 1Gb DRAM goes into this market segment.
The key will be the availability of 1Gb DRAM within the 2007-2008 time frame. A 1Gb DRAM built on
advanced process technology will have power consumption on par with a 512Mb device built on older
processes. The 1Gb DRAM enables a 2GB DIMM to be built using 18 chips rather than the 36 chips
required with 512Mb DRAM.
Table 3 projects that in 2007, 1Gb DRAM shipments will only be 4 percent of total production, but will
increase in 2008 to 13 percent. Since the server market is roughly one-fourth the size of the client market,
it is possible to achieve a much higher market penetration in the server market. In 2008 the available 1Gb
DRAM will be large enough to service 98 percent of the projected demand for servers.
The client machines’ low power-on hours and low utilization shown in Table 2, combined with the market
size estimates in Table 3, indicate a baseline power consumption 109MW in 2008. However, since the
available 1Gb DRAM could only serve 24 percent of the total client machine market, the potential savings
would be 13.28MW.
©2008 Micron Technology, Inc. All rights reserved 13
512Mb
EQ
%
%
%
MW
MW
%
%
MW
MW
MW
million
kWh
million
kWh
TOTAL production
1Gb as % total
Client
Server
DRAM in Client: Power
DRAM in Server: Power
1Gb supply/demand client
1Gb supply/demand server
Max Client savings
Max Server Savings
Annual delta from
putting 1Gb in servers
Annual delta Power
5 year lifecycle savings
1
1
2
2
3
3
4
4
4, 5
4, 5
4
4
4
9,203
4%
54%
13.5%
72
90
8%
31%
2.80
13.93
11.13
97.5
488
13,849
13%
54%
13.5%
109
135
24%
98%
13.28
66.11
52.83
462.8
2,314
Units 2007 2008 NotesBy comparison, the available 1Gb DRAM could serve 98 percent of the total server market. Applying
the same mathematical computation as before produces a power savings of 66.1MW—a difference of
52MW. Significant power savings is achieved simply by channeling a scarce DRAM resource into a market
segment where utilization is the highest.
These results represent a reduction of 0.463B kWh for equipment installed during 2008. If we assume
this represents only one-fifth of data center servers, and if we extrapolate that to the entire installed
base, we find the estimated savings would be 2.3B kWh. This estimate only assumes reduced chip count
technology; adding in 1.5V DDR2 FBDIMMs would add another 2.3B KWh, which brings the total annual
IT load savings to 4.6B kWh.
Finally, when the overhead power consumption is added into the mix, an equal amount of overhead
energy can be saved with regard to reduced cooling, supply inefficiencies, etc. In other words, another
4.6B kWh could be saved, bringing the total potential savings to more than 9B kWh annually.
Currently, the effective service life of servers is five years or longer due to the depreciation schedule
imposed by Internal Revenue Service. Dr. Koomey’s report indicates a server life of three to five years.
Micron’s investigation revealed on a limited dataset that if a server was no longer capable of meeting
customer requirements inside the 5 year schedule, it would be repurposed for a less intensive workload.
Thus, most servers can be expected to run for a minimum of five years, with many running much longer.
In contrast, client machines are typically expensed or depreciated on a shorter service life schedule.
The power demands of data centers require memory innovations
©2008 Micron Technology, Inc. All rights reserved 14The power demands of data centers require memory innovations
Footnotes:
1. Energy Information Administration: Official energy statistics from the U.S. Government:
www.eia.doe.gov/cneaf/electricity/epm/table5_3.html
2. Enterprise Server and Data Center Energy Efficiency Initiatives:
www.energystar.gov/index.cfm?c=products.pr_servers_datacenters
3. http://clerk.house.gov/evs/2006/roll369.xml
4. http://enterprise.amd.com/Downloads/svrpwrusecompletefinal.pdf
5. University of Washington Television Webcast:
www.uwtv.org/programs/displayevent.aspx?rID=2879 : Urs Holzle presenting.
6. http://enterprise.amd.com/Downloads/svrpwrusecompletefinal.pdf
7. Ibid.
8. Memory power consumption in a fully loaded server is estimated in the range of 25% to 66%.
This analysis assumes 20% on the basis that we do not have a clear understanding of memory
content per system; www.energystar.gov/index.cfm?c=products.pr_esads_conf_media The presenter
is Gregg Papadopoulos, CTO of Sun Microsystems.
9. http://enterprise.amd.com/Downloads/svrpwrusecompletefinal.pdf. Note (7) of this document states
that total electricity consumption (including cooling and auxiliary equipment) is twice that of the
direct server power consumption, based on typical industry practice
©2008 Micron Technology, Inc. All rights reserved 15About Micron
Micron Technology, Inc., one of the world’s most efficient and innovative semiconductor companies,
manufactures and markets a full line of DRAM components and modules, NAND Flash memory, CMOS
image sensors, and other semiconductors. Our broad product line includes both legacy and leading-edge
solutions, offered in multiple generations, densities, configurations, and packages to meet the diverse
needs of our customers. With operations in 18 countries, customers can count on us to deliver the expert
design, manufacturing, sales, and technical support—and ultimately, the high-performance, advanced
semiconductor solutions—that go into successful product designs.
Products and specifications discussed herein are subject to change by Micron without notice. Products are warranted only to meet
Micron’s production data sheet specifications. All information discussed herein is provided “AS IS” and without warranties of any kind.
Micron, the Micron logo, Crucial, and the Crucial logo are trademarks of Micron Technology, Inc. All other trademarks are the property
of their respective owners.
The power demands of data centers require memory innovations
©2008 Micron Technology, Inc. All rights reserved 16
EZ Gig IV
User’s Guide
Cloning Software with
Data SelectTABLE OF CONTENTS
EZ Gig - Getting Started 4
Cloning as Easy as 1-2-3 4
Compatibility 4
System Requirements 5
Connecting Your Hard Drive 6
EZ Gig Start Up Options 6
Creating a Bootable EZ Gig CD 7
Cloning your hard drive with EZ Gig 8
Selecting the Source Drive 9
Selecting the Destination Drive 10
Speed Test 10
Drive Verification 11
Data Select 12
Using the Data Select feature 13
Analyzing files 14
Selecting Folders to Omit 15
Advanced Options 16
Verify Copy 16
Copy Free Areas 16
SmartCopy 16
Media Direct (Dell) 16
More Advanced Options 17
FastCopy 17
SafeRescue 17
CachedMemory 17
SharedMemory 17
Animation 17
HotCopy / LiveImage 18
Avoid exclusive read access 18
Partitions 19
Resizing your partitions manually 20Start Clone 21
Interupting the Cloning Process 22
Aborting the Cloning Process 22
Interupting the Verification process 22
Congratulations your Clone is Complete 23
FAQs 24
Load errors 24
Error #5002 and ‘Disk error’ 24
Keyboard and mouse 24
General problems 25
Slowed down system 25
Read, write and verification errors 25
IDE/ATA/SATA 25
Hard disk not recognized 25
IDE controller not found 26
Source & Destination Size Differences 26
Equal Size 26
Small to large 26
Large to small 26
Automatic troubleshooting 27
Intensive reading/writing 27
Read errors 27
Write errors 27
Verification errors 27
Contacting Technical Support 29
RMA Policy 29
Warranty Conditions 304 www.apricorn.com
Cloning as Easy as 1-2-3
Upgrading your notebook hard drive is one
the easiest ways to increase performance
and capacity. EZ Gig makes this process
simple by copying all of your data, OS,
email and settings to your new drive in just
three simple steps.
EZ Gig - Getting Started
Compatibility
EZ Gig is compatible with the latest Apricorn Upgrade products, including
DriveWire, SATA Wire, Velocity Solo and EZ Upgrade. Before commencing,
please ensure that your new hard drive is connected to your computer using
one of the below products.
NOTE: Before starting the cloning process EZ Gig automatically
verifies which Apricorn upgrade product is being used. If used without
one of the products below, EZ Gig will not work.
EZ Upgrade DriveWire SATA Wire
SATA Wire 3.0 Velocity Solowww.apricorn.com 5
System Requirements
Hardware: 1 GHz Intel® Pentium® or Atom™ processor
or equivalent
256MB RAM
Available USB port
CD ROM or CD-RW drive
Keyboard: standard, PS/2 or USB
Mouse: serial, PS/2 or USB (optionally, can be
operated with keyboard only)
Operating systems:
Microsoft: Windows® 7, XP or Vista™
NOTE: When used with Windows 2000 you must boot
to the EZ Gig III CD to clone your drive
Supported Media: IDE/ATA hard disks, CompactFlash via IDE
SATA hard disks (internal & external)
SCSI hard disks (internal & external)
USB hard disks (internal & external)
Hub Devices - USB devices may also be connected
via a USB Hub, however for achieving the highest
possible data transfer rate it is recommended that
you connect them directly to your computer
Supported controllers:
PCI IDE controller
Bus master IDE controller
SATA controller with IDE interface
SATA-II controller with AHCI interface
USB UHCI & OHCI controller (USB 1.1)
USB EHCI controller (USB 2.0)
USB 3.0 x HCI (USB 3.0)6 www.apricorn.com
Connecting Your Hard Drive
Before starting the EZ Gig software,
please ensure that your new hard drive
is connected to your notebook’s USB
port via one of Apricorn’s Upgrade
products listed on the previous page.
EZ Gig
Start Up Options
Depending on how you received EZ Gig, you have two options.
1. If you have EZ Gig on a CD, please choose the Start option (proceed
to page 7 of this manual to continue).
2. If you downloaded EZ Gig from Apricorn’s website, you can either
choose the Start option (go to page 7) or create a bootable EZ Gig CD
to use in the future (go to page 8 for instructions).www.apricorn.com 7
Creating a Bootable EZ Gig CD
If you downloaded EZ Gig from Apricorn’s website, you have the option
of creating a bootable EZ Gig CD, floppy disk or thumb drive to use in
the future.
To create a bootable media disk follow the appropriate directions below:
• If you want to create a bootable floppy disk, choose the desired
drive at ‘Floppy drive’ and click “Create floppy”.
• To create a bootable CD/DVD, choose the desired drive at ‘CD/
DVD writer’ and click “Create CD/DVD”.
• To create a bootable USB key, choose the desired drive at ‘USB
medium’ and click “Make bootable”.
Follow the instructions and wait until the installation program reports
successful creation of the bootable medium.
Once you have created you bootable media device, click “Exit” and then
choose “Start EZ Gig”.8 www.apricorn.com
Cloning your hard drive with EZ Gig
1. Click the “Let’s Get Started” button to proceed.
2. EZ Gig will then scan for connected drives. This may take a few
moments.www.apricorn.com 9
Selecting the Source Drive
Once EZ Gig has scanned for connected drives, you will be asked to select
your Source Drive. This is the drive you would like to copy from and in
most cases is the internal drive in your notebook.
NOTE: Your computer’s internal drive will usually be denoted by the
prefix AHCI or IDE.
Select the appropriate drive from the menu and click “Next” to continue. 10 www.apricorn.com
Selecting the Destination Drive
Once you have selected your Source Drive, EZ Gig will ask you to select
your Destination Drive. This is the drive you would like to copy to and in
most cases is the external drive connected to your notebook’s USB port.
NOTE: Your external drive will be denoted by the prefix USB
Select the appropriate drive from the menu and click “Next” to continue.
Click the Speed Test icon
on either the Source or
Destination drive for an
estimate of the drive’s read
speed.
From this estimate, a rough
estimate of the clone time
may be gauged
Speed Testwww.apricorn.com 11
Drive Verification
You are almost ready to start your clone, but before you do, EZ Gig asks
that you verify that the choosen drives are correct.
If they are you have one of two options. Either click “Next” to
continue (go to page 21) or to deselect files from the cloning process,
press the “Data Select” button (go to page 12).
If you need to change your drive selection, click the “Back” button
At this point you can also modify the default options for your clone using
the “Advanced Options” button. Only select this option if you would like
to change your options from the default (go to page 16 for more info on
Advanced Options).12 www.apricorn.com
Data Select
EZ Gig’s Data Select feature provides a simple method to deselect data
folders from the cloning process which is helpful when migrating from a
large HDD to a smaller SSD and perfect for creating a Boot Disk. This
gives you the option to run your OS and applications from a fast, smaller
SSD boot drive, while keeping your documents and media files on your
original hard drive.
There are two ways to get to the Data Select feature:
1. If the Destination drive is smaller than the Source drive, EZ Gig
will direct you to the below screen. To deselect files from the
clone click the “Data Select” button, this will open the Data Select
feature.
2. On the “You are almost ready to Clone” screen, you may press
the “Data Select” button to open the Data Select feature.www.apricorn.com 13
Using the Data Select feature
The Data Select feature shows the capacity of the:
• Destination Drive
• Source Drive
• Available Capacity
If the Source drive is smaller than the Destination drive, the available
capacity will be highlighted in orange and shown as a negative value.
EZ Gig will only proceed with a clone if the available capacity is positive
(i.e. the Destination capacity is larger than the Source capacity.)
In order to decrease the size of the clone (i.e. the Source image), EZ Gig
enables you to deselect files from the cloning process to save space.
The files you may deselect from the cloning process are from the folders:
1. Documents
2. My Videos
3. My Music
4. My Pictures14 www.apricorn.com
Analyzing files
To analyze the amount of space used by each of the folders, select the
checkbox to the left, under the “Select Folders to Analyze” column. EZ Gig
will then analyze the space used in the ajoining “Space Used” column.
To analyze the
amount of space
used by each
folder, select
the appropriate
checkbox.
EZ Gig will then
display the space
used in the ajoining
columnwww.apricorn.com 15
Selecting Folders to Omit
To select folders to omit, select the checkboxes to the right, under the “Select Folders
to Omit” column. Any selection from this column will automatically be reflected in an
updated amount for the “Available Capacity” value. Once the “Available Capacity”
value is positive, you will have the option to “Apply” the changes.
Once you hit the “Apply” button, you will be directed to the “You are almost
ready to Clone” screen. The Data Select button will have a check mark to the
left, indicating that you have choosen to omit files from the clone.
To continue with the clone, click the “Next” button (go to page 21).16 www.apricorn.com
Advanced Options
Compares the data of source and target after copying. If verify copy is
chosen, the free areas between partitions will also be copied. This option
has no influence on the copying performance itself, but offers the possibility
to synchronize the data of the source and target after the copying process.
However, the whole process of copying and verifying then normally takes
approximately the double amount of time. Choose this option according to
your needs of copying and your time available.
Verify Copy
SmartCopy enables you to clone your file systems in a fraction of time
usually required - this option is chosen by default
SmartCopy
This option is off when doing a default clone, but when selected allows
you to copy free space between partitions from your internal drive to your
external drive.
Copy Free Areas
Used to deactivate MediaDirect software on the Destination drive. Check
your Dell notebook specs to see if you have Media Direct on your system.
Media Direct (Dell)www.apricorn.com 17
To access additional advanced options, click on the Apricorn logo in the
bottom right corner of the “Advanced Options” window
More Advanced Options
FastCopy
Special copy algorithm. Can increase the regular copy speed up to double.
SafeRescue
Special algorithm for data recovery. Tries to recover as large areas on the drive
as possible. Can also stay turned on for normal copies.
CachedMemory
Use fast intermediate memory.
SharedMemory
Use fast data transfers.
Animation
Switch off copy animation, may lead to a slight speed increase.18 www.apricorn.com
HotCopy / LiveImage
Allows or denies EZ Gig access to the Windows shadow copy mechanism.
If this option is deselected, EZ Gig is not able to create copies or file
images of the system volume or of volumes, which are used by other
programs at the same time.
Avoid exclusive read access
Usually, EZ Gig when running on Windows, at first tries to reserve the
source drive for exclusive access. This is the most reliable way for creating
an identical copy, but it may interfere with other programs running at the
same time. If this option is selected, EZ Gig tries to create a HotCopy or a
LiveImage at first.www.apricorn.com 19
Partitions
When used in the Default mode, EZ Gig will automatically resize your
partitions according to the new hard drive space.
However, EZ Gig also gives the option of keeping your partition sizes the
same or allows you to resize your partition sizes manually.20 www.apricorn.com
Resizing your partitions manually
To resize your partition manually:
1. Choose the “Manually” radio button on the “Advanced Options”
window.
2. Once this radio button is selected, click the “Apply Changes” button.
The “Adjust Partitions” window (shown left) will pop up.
Positions and sizes of the partitions to be copied to the Destination
drive are displayed graphically in a bar. The original size of the
partition is displayed in dark green, while the additionally assigned
space is displayed in light green. The size of partitions displayed in
black cannot be altered. Free space not yet assigned to any partition
is displayed in white.
3. To resize, click the desired partition’s extended space (light green
portion) and drag with your mouse. You can also use the [+] and [-]
cursor keys to the same effect.
4. Once you have resized the partitions to the desired size, choose “Apply
Adjustment” which will then close the window.
5. Once the “Adjust Partition” window is closed, close the “Advanced
Options” window by clicking the “Close Window” button.www.apricorn.com 21
Start Clone
Now you’re ready!
Press the “Start Clone” button to start the cloning process.
EZ Gig will keep you up-to-date with the status of the clone throughout the
entire process with a progress bar and percentage completed. Depending
on your system size a clone can take anywhere from several minutes to a
couple of hours.22 www.apricorn.com
Aborting the Cloning Process
Interupting the Verification process
If you chose the “Verify Copy” option before starting the clone, EZ Gig will
automatically compare the information on the “Source” and “Destination”
drives once the clone is complete. If this process is interupted or stopped
at anytime, the aborted verification run will have no influence on the copied
data. The copy itself is already finished at that point of time.
When the final report is read, EZ Gig will report that the clone is only
partially verified.
Interupting the Cloning Process
If the cloning process aborted, a new clone must be commenced.
The cloning process can be stopped at anytime using the “Stop” button.
Continue cloning by clicking “Continue copying”. To stop the clone
completely, select “Abort copying.”www.apricorn.com 23
Congratulations your Clone is Complete
Once your clone is complete, EZ Gig will let you know with a pop up
window. To get a report of the cloning process, click the “Details” button.
The final report will outline
the number of sector
copied, read errors, write
errors and if verified, will
also report verification
errors.
Once you have finished
your clone, click “Quit
EZ Gig”. You will then
be prompted to turn
your computer off and
disconnect the attached
hard drive.24 www.apricorn.com
FAQs
Load errors
During the start of the program, before EZ Gig is loaded itself, a message
and a progress bar will appear on the boot screen. In case of an error, one
of the following error codes will be indicated here.
Error #5002 and ‘Disk error’
This error will be displayed if the boot medium is not readable when
booting the program. The error is reported by the BIOS of the computer
and points to a defective data carrier or a problem with the used boot
drive. In many cases, in particular when booting from a floppy disk, an
incompatibility between drive and data carrier is the cause. Principally
this problem can be fixed. Please try the following steps, at best in the
indicated order:
• Try again to boot the program, perhaps with/without cold start.
• Create once again a bootable disk (page 7).
• Floppy disk: format the floppy disk (no quick format) before
creating a new one.
• Floppy disk: use another floppy disk.
• Use (if possible) another boot drive.
NOTE: If you didn’t receive EZ Gig as an installation package but on a
bootable disk and if a disk shows this problems also after multiple trials on
different devices, please contact Support.
Keyboard and mouse
EZ Gig supports keyboards and mice with PS/2 standard or USB
connector. This also includes many wireless mice, given they are
connected as a true USB device. Input devices connected with Bluetooth
are currently not supported. In this case, please connect a separate USB
device. If keyboard or mouse (or both) do not function with EZ Gig, this is
usually due to a wrong legacy emulation setting in BIOS setup. On most
computers, you can fix this problem by changing (activating or deactivating,
depending on the current setting) the emulation for PS/2 devices in BIOS
setup. Please consult your computer manual on how to change this setting
since it may be named differently according to the respective BIOS. In
most of the cases, you can find it under the name USB Legacy Support or
USB Keyboard Support (often under Integrated Peripherals or Advanced
Options).www.apricorn.com 25
NOTE: In some of the cases, problems with the PS/2 keyboard and/or
mouse occurred with an activated emulation for PS/2 devices. If you do not
use any USB input de-vices, please switch off the PS/2 emulation in the
BIOS setup.
General problems
Slowed down system
If you think the speed of the total system or the copying speed – also with
IDE and SCSI devices – is too slow, a USB controller can be the cause,
even if it is not used.
Read, write and verification errors
If EZ Gig reports errors, these are usually defective areas on the
respective medium. However, general problems with the hardware
can possibly also cause (putative) read and write errors. This is mostly
noticeable by a very high number of displayed errors. First of all, try
to fix the problem via the help instructions for the respective hardware
types (IDE, SCSI, USB) because the causes are usually found there. If
the problems cannot be fixed this way either, deactivate step by step the
following options, at best in the indicated order:
• CachedMemory
• Read cache and write cache
• FastCopy
• DMA
• SharedMemory
If the problem does not occur any more after having deactivated a certain
option, the previously deactivated options can be reactivated as a test.
IDE/ATA/SATA
Hard disk not recognized
If EZ Gig does not recognize a hard disk, there can be several reasons.
Perhaps the controller which the disk is connected to has not been found
(See next section: IDE controller not found). A further possible reason can
be a non-standardly connected hard disk. This is for example the case if
a hard disk is configured as slave and if a CD/DVD drive or no drive at all
is connected at the same IDE channel as master. Normally, EZ Gig can
handle that, too.26 www.apricorn.com
NOTE: If an SATA hard disk is not recognized, this can also be due to the
used SATA controller.
IDE controller not found
There are the following three reasons why EZ Gig has not automatically
recognized an IDE controller:
• The IDE controller/channel is deactivated, e.g. on an onboard IDE
controller. Activate the IDE controller/channel via the BIOS setup.
• Standard IDE controllers (ISA) are not taken into account if PCI
IDE controllers are available. Connect the respective hard disk to a
PCI IDE controller in this case or deactivate the PCI IDE controller
or controllers.
• The used controller does not correspond to the PCI IDE standard.
Although most controllers support this standardized programming
interface, there are some controllers which have only a proprietary
programming interface. Connect the corresponding drives to
another controller (PCI IDE controller).
Source & Destination Size Differences
Equal Size
If source and target are of the same size, EZ Gig creates an absolutely
identical copy(clone). On this clone, all sectors on source and target, from
the first to the last sector, are 100% identical, provided that the process
was error-free.
Small to large
If the source is smaller than the target, EZ Gig copies only the data that
is available on the source. This data is copied from the beginning of the
source onto the beginning of the target medium. The area at the end of
the target medium, which is larger than the source, remains unaffected.
Apart from that the unaffected area remains possibly unused during a later
usage, such a copy is usually comparable to a real clone as far as the
capacity of use is concerned because the target contains entirely all data of
the source
Large to small
If the source is bigger than the target, EZ Gig will direct you to the Data
Select feature. EZ Gig’s Data Select provides a simple method to deselect
data folders from the cloning process. EZ Gig will only allow to proceed
with the clone, once the available capacity on the target drive is a positive
value.www.apricorn.com 27
Automatic troubleshooting
In case of occurring errors, EZ Gig tries to troubleshoot them the
best possible. If this is not possible, the errors will be mentioned in a
corresponding error statistic in the detailed report after the clone is
complete.
Intensive reading/writing
In case of read or write errors, EZ Gig uses different strategies in order
to still be able to read or write this data, if possible. The time used for
defective areas depends to a large extent on the respective medium.
According to the medium and its state, several seconds up to minutes can
be needed for the recovery trials. Therefore, it is recommended to always
activate the option SafeRescue because then handling defective sectors
takes place after the copying of all intact areas has been finished. The
process can then be aborted if it takes too long without losing the data of
the intact areas.
Read errors
During the copying process, read errors can only occur on the source
medium. EZ Gig then tries to read the defective areas immediately after
the termination of the copying process (with the option SafeRescue) with
the help of special data recovery strategies within a single troubleshooting
run. During the troubleshooting run, the number of the indicated read errors
can reduce according to the areas on the source medium, which could be
recovered.
NOTE: Read errors, that occur during the verification run, are not counted
as read errors but as verification errors.
Write errors
Write errors can only occur during the copying process and only on the
target medium. EZ Gig then tries to read the defective areas immediately
after the termination of the copying process (with the option SafeRescue)
with the help of special data recovery strategies within a proper
troubleshooting run. During the troubleshooting run, the number of the
indicated write errors can decrease according to the areas on the target
medium, which could be recovered.
Verification errors
When the option Verifying is activated, EZ Gig executes a verification run
after the copying process. A verification error is counted if the data of two
sectors on source and target do not correspond. Furthermore, read errors, 28 www.apricorn.com
which occur during the verification run in one or both of the areas to be
compared, are also counted as verification errors. Therefore, the number
of verification errors gives you absolute information on how exactly source
and target correspond to each other after the copying process. In case of
an error-free copying process, EZ Gig should not report any verification
errors and signalize a 100% conformity of source and target.30 www.apricorn.com
Warranty Conditions
Warranty:
Apricorn offers a 1 to 3 year warranty on its upgrade products against defects
in materials and workmanship under normal use. The warranty period
is effective from the date of purchase (validated by your original receipt)
either directly from Apricorn or an authorized reseller.
Disclaimer and terms of the warranties:
The warranty becomes effective on the date of purchase and must be verified
with your sales receipt or invoice displaying the date of product purchase.
Apricorn will, at no additional charge, repair or replace defective parts with
new parts or serviceable used parts that are equivalent to new in performance.
All exchanged parts and products replaced under this warranty will become
the property of Apricorn.
This warranty does not extend to any product not purchased directly from
Apricorn or an authorize reseller or to any product that has been damaged or
rendered defective: 1. As a result of accident, misuse, Neglect, abuse or failure
and/or inability to follow the written instructions provided in this instruction
guide: 2. By the use of parts not manufactured or sold by Apricorn; 3. By
modification of the product; or 4. As a result of service, alternation or repair
by anyone other than Apricorn and shall be void. This warranty does not cover
normal wear and tear.
No other warranty, either express or implied, including any warranty or merchantability
and fitness for a particular purpose, has been or will be made by
or on behalf of Apricorn or by operation of law with respect to the product
or its installation, use, operation, replacement or repair.
Apricorn shall not be liable by virtue of this warranty, or otherwise, for any
incidental, special or consequential damage including any loss of data resulting
from the use or operation of the product, whether or not Apricorn was
apprised of the possibility of such damages.
Copyright © Apricorn, Inc. 2011. All rights reserved.
Windows is a registered trademark of Microsoft Corporation. All other trademarks and copyrights
referred to are the property of their respective owners. Distribution of substantively modified
versions of this document is prohibited without the explicit permission of the copyright holder.
Distribution of the work or derivative work in any standard (paper) book form for commercial
purposes is prohibited unless prior permission is obtained from the copyright holder.
DOCUMENTATION IS PROVIDED AS IS AND ALL EXPRESS OR IMPLIED CONDITIONS,
REPRESENTATIONS AND WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT,
ARE DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD TO
BE LEGALLY INVALID.12191 Kirkham Road
Poway, CA, U.S.A. 92064
1-858-513-2000
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revision: 10/22/12 1
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• Limited lifetime warrantyCrucial Ballistix Elite
Part Number Density Speed Latency Voltage Bandwidth UPC
BLE2G3D1608DE1TX0 2GB DDR3-1600 CL8 (8-8-8-24) 1.5V PC3-12800 (12.8 GB/s) 649528755575
BLE2G3D1869DE1TX0 2GB DDR3-1866 CL9 (9-9-9-27) 1.5V PC3-14900 (14.9 GB/s) 649528755681
BLE2G3D1608CE1TX0 2GB DDR3-1600 CL8 (8-8-8-24) 1.65V PC3-12800 (12.8 GB/s) 649528754790
BLE2G3D1869CE1TX0 2GB DDR3-1866 CL9 (9-9-9-24) 1.65V PC3-14900 (14.9 GB/s) 649528755322
BLE2G3D2139CE1TX0 2GB DDR3-2133 CL9 (9-10-9-24) 1.65V PC3-17000 (17.0 GB/s) 649528754936
BLE4G3D1608DE1TX0 4GB DDR3-1600 CL8 (8-8-8-24) 1.5V PC3-12800 (12.8 GB/s) 649528755636
BLE4G3D1869DE1TX0 4GB DDR3-1866 CL9 (9-9-9-27) 1.5V PC3-14900 (14.9 GB/s) 649528755537
BLE8G3D1869DE1TX0 8GB DDR3-1866 CL9 (9-9-9-27) 1.5V PC3-14900 (14.9 GB/s) 649528757821
Crucial Ballistix Elite Dual Channel Kits
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BLE2KIT2G3D1608DE1TX0 4GB Kit (2x2GB) DDR3-1600 CL8 (8-8-8-24) 1.5V PC3-12800 (12.8 GB/s) 649528755582
BLE2KIT2G3D1869DE1TX0 4GB Kit (2x2GB) DDR3-1866 CL9 (9-9-9-27) 1.5V PC3-14900 (14.9 GB/s) 649528755698
BLE2KIT4G3D1608DE1TX0 8GB Kit (2x4GB) DDR3-1600 CL8 (8-8-8-24) 1.5V PC3-12800 (12.8 GB/s) 649528755643
BLE2KIT4G3D1869DE1TX0 8GB Kit (2x4GB) DDR3-1866 CL9 (9-9-9-27) 1.5V PC3-14900 (14.9 GB/s) 649528755544
BLE2KIT8G3D1869DE1TX0 16GB Kit (2x8GB) DDR3-1866 CL9 (9-9-9-27) 1.5V PC3-14900 (14.9 GB/s) 649528757838
Crucial Ballistix Elite Three Channel Kits
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BLE3KIT2G3D1608DE1TX0 6GB Kit (3x2GB) DDR3-1600 CL8 (8-8-8-24) 1.5V PC3-12800 (12.8 GB/s) 649528755599
BLE3KIT4G3D1608DE1TX0 12GB Kit (3x4GB) DDR3-1600 CL8 (8-8-8-24) 1.5V PC3-12800 (12.8 GB/s) 649528755650
revision: 10/22/12 2
©2012 Micron Technology, Inc. All rights reserved. Information is subject to change without notice. All trademarks and service marks are property of their respective owners.
Performance DRAM
Guide!pratique!de!mise!à!jour!du!firmware!d'un!SSD
Guide!de!mise!à!jour!du!firmware!du!SSD!Crucial®!m4!2,5"!vers!la!version!070H!@ à!partir!d'un!CD/d'une!clé!USB
(mise à!jour!depuis!les!versions!0001,!0002,!0009,!0309,!000F,!010G,!040H!vers!la!version!070H)
Introduction
Ce! document! détaille! la! procédure! de! mise! à! jour! du! firmware du! SSD!
Crucial! m4! via! une! clé! USB! ou! un! CD! et! une! image! ISO! de! démarrage.!
L'image! ISO! contient! la! mise! à! jour! 070H! du! firmware! et! un! code! de!
démarrage!DOS.
Cette! procédure! est! destinée! à! la! mise! à! jour! du! firmware! depuis! les!
versions!0001,!0002,!0009,!0309,!000F,!010G!et!040H!vers!la!version!070H.
REMARQUE : Cette!mise!à!jour!du! firmware!ne!s'applique!pas à! tous!les!
SSD!Micron!acquis!seuls!ou!en!tant!que!matériel!de!première!monte!d'un!
ordinateur.! Les!mises!à!jour! de! firmware! de! ces! disques@là! seront,!le! cas!
échéant,!fournies!par!le!fabricant!de!l'ordinateur!ou!seront!disponibles!sur!
www.micron.com.! Cette! mise! à! jour! du! firmware! ne! concerne! pas!
n'importe! quel! disque!Micron! RealSSD! C300.! De! même,! elle! ne! doit! pas!
être! utilisée! pour! un! SED! (Self! Encrypting! Drive) Micron! RealSSD! C400.!
Cette!mise!à!jour! s'applique! uniquement!aux! disques!m4! 2,5"!et! ne! doit!
pas!être!utilisée!pour!mettre!à!jour!des!disques!m4 mSATA.
AVERTISSEMENT : Comme! pour! toutes! mises! à! jour,! il! est! fortement!
recommandé! de! sauvegarder! ou! de! copier! tous! vos! fichiers! importants!
auparavant.! Cette! procédure! de!mise! à! jour! du! firmware! s'effectue! sous!
votre! seule! responsabilité.! Si! elle! est! exécutée! correctement,! il! n'y! aura!
aucune!perte!de!données! système!ou!utilisateur!présentes! sur!le!disque.!
Toutefois,! une! interruption! de! la! mise! à! jour,! quelle! qu'en! soit! l'origine,!
peut!entraîner!le!dysfonctionnement!de!votre!SSD.!Si!cette!mise!à!jour!est!
appliquée!sur!un!ordinateur!portable,!il!est!fortement!recommandé!de!le!
brancher!en!secteur!pendant!la!procédure.
Instructions!générales
Procédez!aux!opérations!suivantes!avant!de!démarrer!la!procédure!de!
mise!à!jour!du!firmware :
1.!Sauvegarde!du!contenu!du!SSD
Il!est! fortement!recommandé!de!procéder!à!une!sauvegarde!complète!
du! système! avant! de! démarrer! cette! mise! à! jour! du! firmware.! Si! la!
procédure! de!mise!à!jour!est!interrompue! (coupure! d'alimentation!ou!
défaillance! matérielle! de! toute! nature),! il! est! possible que! le! SSD! ne!
fonctionne!pas!correctement.
2.!Utiliser!une!alimentation!CA
Veillez!à!ce!que!votre!ordinateur!portable!ou!de!bureau!soit!relié!à!une!
alimentation! CA! pendant! la!mise!à!jour.!Il!est! déconseillé! de! n'utiliser!
que! la! batterie! pendant! la! procédure.! Ne! débranchez! l'alimentation! à!
aucun! moment! de! la! procédure! de! mise! à! jour! du! firmware! car! cela!
pourrait!aboutir!à!un!déroulement!incomplet!de!celle@ci!et!donc,!rendre!
le!SSD!inutilisable.
3.!Éditer!les!paramètres!du!BIOS
Pour! exécuter! les! opérations! suivantes,! vous! devrez! peut@être!
éditer! les! paramètres! de! BIOS! de! votre! ordinateur.! Veuillez!
consulter! le! manuel! utilisateur! de! votre! ordinateur! pour! savoir!
comment!procéder.
a)!Désactivez/supprimez!les!mots!de!passe!associés!au!disque
Entrez! dans! le! BIOS! (généralement! en! appuyant! sur! les! touches!
« Suppr »,! « F2 »! ou! « F12 »! au! démarrage! de! l'ordinateur)! et!
désactivez!tous!les!mots!de!passe!éventuellement!associés!au!SSD.!
Une!protection!par!mots!de!passe!peut!bloquer!les!mises!à!jour!du!
firmware.
b)!Vérifiez!l'ordre!de!démarrage
Si!votre!système!ne!démarre!pas!à!partir!du!CD!ou!de!la!clé!USB,!
vous!devrez!accéder!aux!paramètres!de!votre!BIOS.!Dans!l'éditeur!
du!BIOS,!vérifiez!l'ordre!de!démarrage.!Par!défaut,!la!plupart!des!
systèmes!démarre!à!partir!du!lecteur!de!CD@ROM!avant!le!lecteur!
système.! D'un! fabricant! de! BIOS! à! l'autre,! vous! trouverez! une!
option! dénommée! « Priorités! de! démarrage! des! périphériques »!
(Boot$Device$ Priority),! « Priorités! de! chargement! au! démarrage »!
(Boot$ Load$ Order)! ou! « Caractéristiques! avancées! du! BIOS »!
(Advanced$BIOS$Features).!Veillez!à!ce!que!le!système!démarre!sur!
le!CD!ou!la!clé!USB!de!démarrage!avant!le!disque!contenant!le!SE.
Téléchargez!la!mise!à!jour!du!firmware
1. Avant! de! commencer! le! téléchargement! du! firmware,! fermez!
tous!les!autres!programmes,!sauf!votre!navigateur!internet.
2. Recherchez! l'utilitaire! Windows! de! mise! à! jour! vers! le!
firmware 070H! associé! à! votre! SSD! Crucial! à! l'adresse :
http://www.crucial.com/support/firmware.aspx
3. Cliquez! sur! le! lien! correspondant! et! vous! serez! invité! à! Ouvrir,!
Enregistrer! ou!Annuler.!Cliquez! sur!Enregistrer! pour! télécharger!
l'image!ISO!et!la!sauvegarder!dans!votre!système.!
4. Copiez! ce! fichier! sur! le! bureau! ou! dans! un! autre! dossier!
facilement! accessible! ultérieurement! et! fermez! le! fenêtre! de!
téléchargement!à!la!fin!de!celui@ci.
Créer!un!support!de!démarrage!avec!fichier!ISO
Option!1 :!Graver!un!CD!de!démarrage
Remarque : Windows 7!dispose!d'un!logiciel!de!gravure!optique!de!
disques.
1. Utilisez! le! logiciel! de! gravure! de! votre! choix! pour! graver!
l'image!ISO!du!firmware!sur!un!CD.Option!2 :!Créer!une!clé!USB!de!démarrage
Remarque : pour!utiliser!cette!option,!votre!système!doit!prendre!
en!charge!le!démarrage!à!partir!d'une!clé!USB.
1. Munissez@vous! d'une! clé! USB! préalablement! formatée! (256 Mo,!
ou!plus).
2.!!Ouvrez!un!installeur!USB.!Si!vous!n'en!disposez!pas,!vous!pouvez,!
par!exemple,! télécharger!gratuitement!l'installeur!USB!universel!
(disponible! sur! www.pendrivelinux.com/universal@usb@installer@
easy@as@1@2@3/).
3. Une! fenêtre! de! sécurité!et/ou!le! contrat! de!licence!apparaîtront!
peut@être.
4.!!Si!vous!utilisez!l'installeur!USB!universel :
• À!l'étape 1,!atteignez!le!bas!de!la!liste!déroulante!et!sélectionnez!
la!dernière!option :!Try$Unlisted$Linux$ISO.
• Passez! à! l'étape 2! et! recherchez! l'ISO! du! firmware! téléchargée!
précédemment.
• À! l'étape! 3,! sélectionnez! la! clé! USB! sur! laquelle! vous! souhaitez!
installer!l'ISO.!
• Cliquez! sur! le! bouton! Create (Créer)! et! sur! Format$ E:\Drive
(Formater,! efface! le! contenu).! Répondez! Yes (Oui)! à!
l'avertissement!indiquant!la!réécriture!de!votre!clé!USB.!
• Après! l'apparition/la! disparition! d'une! série! d'écrans,! la! clé!USB!
est!chargée.
Lancez!la!mise!à!jour!du!firmware!
1. Insérez!le!CD!ou!la!clé!USB!de!démarrage!contenant!l'image!ISO!
dans!votre!ordinateur.
2. Démarrez! l'ordinateur! à! partir! du! support! de! démarrage.! Cela!
lance!automatiquement!la!mise!à!jour!du!firmware.!
3. Après! le! chargement! complet! de! l'utilitaire! de! mise! à! jour,! ces!
éléments!apparaîtront!à!l'écran :
La! mise! à! jour! étant! possible! depuis! n'importe! quelle! version!
précédente,! 0001,! 0002,! 0009,! 0309,! 000F,! 010G!ou! 040H,!l'une!ou!
l'autre!de!ces!révisions!peut!donc!apparaître!sur!l'écran!ci@dessus.!Si!
votre!disque!m4!est!absent!de!la!liste!affichée!sur!l'écran!ci@dessus,!
veuillez!vous!reporter!au!paragraphe!« Astuces!de!dépannage »!à!la!
page!suivante.
4. Avant!la!demande!de!mise!à!jour!du! firmware,!il!se!peut!que!la!
mention! Waiting! for! DRQ! s'affiche.! Ce! type! de! message! est!
normal.!Tapez!yes!(oui)!en!minuscules!lorsqu'il!vous!est!demandé!
si! vous! souhaitez! mettre! à! jour! le! firmware.! L'écran! suivant!
apparaîtra :
5. Sur!la!plupart!des!systèmes,!cette!procédure!durera!entre!30!et!
60!secondes.!Dans!certains!cas,!cela!peut!être!plus!long.
6. À!la!fin!de!la!procédure,!le!message!suivant!apparaîtra :
7. IMPORTANT !! Le! numéro! de! version! sera! indiqué.! Si! la! version!
s'affichant! n'est! PAS! la! 070H,! recommencez! la! procédure! à!
l'étape 1! du! paragraphe! précédent! « Lancez! la! mise! à! jour! du!
firmware ».! Vous! pouvez! reprendre! la! procédure! en! tapant!
« AUTOEXEC.BAT »!à!l'invite!de!commande!A:\>.
8. Si! vous! doutez! de! la! version! de! votre! firmware! ou! si! vous!
souhaitez!en!avoir!la!confirmation,!vous!pouvez!taper :
dosmcli!``verbose!`d!
à!l'invite!de!commande!A:\>.!La!version!du!firmware!est!indiquée!
sur! la! dernière! ligne.! Si la! version! s'affichant! n'est! PAS! la!070H,!
recommencez!la!procédure!à!l'étape 1!du!paragraphe!précédent!
« Lancez! la! mise! à! jour! du! firmware ».! REMARQUE :! Cette!
commande!fera!apparaître!sous!forme!de!liste,!non!seulement!le!
SSD!Crucial,!mais!plus!généralement,!tous!les!disques!ATA.
9. Retirez! le! support! de! démarrage!et! arrêtez! votre! ordinateur!en!
appuyant!longuement!sur!le!bouton!Power.!
10. Rallumez!l'ordinateur.!Au!redémarrage,!vous!pouvez!rétablir!les!
réglages! d'origine! de! tout! paramètre! du! BIOS! éventuellement!
modifié.
11. La!procédure!est!terminée.
Astuces!de!dépannage
• Bien! que! tout!ait!été!mis!en!œuvre! pour! tester!la!compatibilité!
de! ce!logiciel!avec! différentes! configurations! de! systèmes!et! de!
jeux! de! composants,! il! est! impossible! de! procéder! à! des! essais!
sur! tous! les! systèmes! existants.! Par! conséquent,! certains!
systèmes! (anciens! par! exemple)! peuvent! se! heurter! des!
problèmes!de!compatibilité.
• Si! votre! disque! m4! n'est! pas! reconnu! lors! de! l'étape! 3! du!
paragraphe!« Lancez!la!mise!à!jour!du!firmware », il!peut!s'avérer!
nécessaire!d'exécuter!cette!mise!à!jour!en!mode!IDE!et!non!AHCI,!
sur!certains!systèmes!anciens.!Pour!cela,!procédez!ainsi :
• Sur!un! ordinateur! de! bureau,! assurez@vous! que! votre! disque!
connecté! à! l'un! des! 4! ports! présents! sur! le! bus! SATA! et!
habituellement! numérotés! de! 0! à! 3.! Certaines! cartes! mères!
ne! prenant! pas! en! charge! la! connexion! à! chaud! de!
périphériques!SATA,!il!est! recommandé! d'arrêter l'ordinateur!
avant!de!changer!les!branchements!aux!ports.
• Dans!le!BIOS,!passez!du!mode!SATA!au!mode!IDE,!hérité!(Legacy)!
ou!compatibilité!(compatibility).!Recherchez!le!paramètre!« SATA!
Configuration »! (configuration$ SATA)! ou! « Integrated!
Peripherals »!(Périphériques$intégrés).
• Sauvegardez!vos!réglages!et!sortez!du!BIOS.
• Exécutez! les! instructions à! partir! de! l'étape 1! du! paragraphe!
précédent!« Lancez!la!mise!à!jour!du!firmware ».• La!plupart!des!systèmes!empêchent!les!mises!à!jour!de!firmware!
en!mode!RAID.!Dans!ce!cas,!le!basculement!en!mode!AHCI!ou!IDE!
peut! aider! à! terminer! la! mise! à! jour.! Toutes! les! configurations!
RAID! devraient!être! conservées! après! la!mise! à! jour,! lorsque! le!
système! rebascule! en! mode! RAID! mais! vérifiez! ceci! dans! le!
manuel! utilisateur! de! votre! système! avant! de! démarrer! la!
procédure.
• Les! cartes! RAID! périphériques! ne! transmettront! pas! les!
commandes!nécessaires!aux!mises!à!jour!du!firmware. Il!se!peut!
que! vous! deviez! déplacer! le! disque! cible! sur! un! adaptateur! de!
bus! hôte! SATA! ou! un! connecteur! SATA! de! la! carte! mère! qui!
facilite!ces!commandes.
• Cet!utilitaire!de!mise!à!jour!du!firmware!peut!ne!pas!fonctionner!
sur! des! ordinateurs! fixes,! portables! ou! des! tablettes! disposant!
d'une! interface! UEFI.! Nous! mettrons! à! disposition! un! outil! de!
mise! à! jour! séparé! qui! prendra! en! charge! les! mises! à! jour! du!
firmware!sous!UEFI!(Unified$Extensible$Firmware$Interface).
Notes!de!version!du!firmware
Le!firmware!du!SSD!m4!a!été!mis!à!jour!de!la!version!040H!à!070H.
Le! firmware 070H!est! recommandé!pour! tous!les!disques!disposant!
de!la!version! 040H,! ou! précédentes. Il! comporte! des!améliorations!
et! corrections! cumulatives! par! rapport! à! ces! versions,! susceptibles!
d'améliorer!l'expérience!utilisateur!globale.
À!l'instar!des!récentes!versions!du!firmware,!la!version!070H!contient!
des!améliorations!par!rapport!à!la!version!000F,!notamment!pour!les!
systèmes! sous!Windows 8! et! les! nouveaux!UltraBook,!même! si! des!
améliorations! peuvent! également! être! constatées! sur! les! systèmes!
sous!Windows 7!et!autres!systèmes!d'exploitation. Toute!version!du!
firmware!du!m4!fonctionnera!normalement!sous!Windows 8,!même!
sans!ces!améliorations!de!fonctionnement.
Voici!un!résumé!des!différences!entre!la!version!040H!et!070H,!
quel!que!soit!le!système!d'exploitation :
• Résolution! d'un! problème! de! synchronisation! à! la! mise! sous!
tension,!susceptible!d'entraîner!un!blocage!du!disque!et!de!ce!fait,!
une! impossibilité! de! communiquer! avec! l'ordinateur! hôte. En!
général,! le! blocage! se! produit! à! la!mise! sous! tension! ou bien! au!
retour!du!mode!Veille!ou!Veille!prolongée. La!plupart!du! temps,!
un! redémarrage! élimine! le! blocage! et! le! fonctionnement! normal!
peut! reprendre.! Cette! défaillance! n'a!été! observée! que! lors! d'un!
essai!en!usine!et!nous!pensons!que!ce!processus!de!défaillance!ne!
s'est!pas!déroulé!en!dehors!de!l'usine.!! Par!mesure!de!précaution,!
cette! correction! est! désormais! intégrée! à! toutes! les! nouvelles!
versions,!quel!que!soit!le!format. Les!utilisateurs!qui!le!souhaitent!
peuvent! appliquer! la! correction! pour! éviter que! cet! échec! se!
produise! à! la!mise! sous! tension. À! ce! jour,! ce! problème! n'a! pas!
été!identifié!comme!étant!à!l'origine!de!retours!de!produits. Une!
réinitialisation! du! système! devrait! normalement! résoudre! une!
défaillance!de!cette!nature.
Versions!précédentes
Rév.!A…………………….....................……………………………………!2!avril!2013
•!Version!initiale
©2013!Micron!Technology,!Inc.!Tous!droits!réservés.!Ces!informations!peuvent!être!modifiées!sans!avis!préalable.!Crucial!et!le!logo!Crucial!sont!des marques!commerciales!et!marques!de!service!de!Micron!
Technology,!Inc.!Toutes!les!autres!marques!commerciales!et!marques!de!service sont!la!propriété!de!leurs!détenteurs!respectifs.!Révision!02/04/13!070H
Crucial®
DDR4 Memory Technology
2002 2004 2007 2014
20%
DECREASE
from DDR3
300%
INCREASE
from DDR3
100%
INCREASE
from DDR3
16.6%
DECREASE
from DDR2
300%
INCREASE
from DDR2
166.5%
INCREASE
from DDR2
28%
DECREASE
from DDR
100%
INCREASE
from DDR
50.3%
INCREASE
from DDR
Technological advancements
by the numbers,
starting with DDR
Next-gen memory. Next-gen performance.
MORE DENSITY
2x Density
©2013 Micron Technology, Inc. All rights reserved. Information is subject to change without notice. Crucial and the Crucial logo are trademarks of Micron Technology, Inc. All other trademarks and service
marks are property of their respective owners.
NOTE: This infographic contains forward-looking statements regarding the production of DDR4. Actual events or results may di er materially from those contained in the forward-looking statements. Please
refer to the documents Micron files on a consolidated basis from time to time with the Securities and Exchange Commission, specifically Micron's most recent Form 10-K and Form 10-Q. These documents
contain and identify important factors that could cause the actual results for Micron on a consolidated basis to di er materially from those contained in our forward-looking statements (see Certain Factors).
Although we believe that the expectations reflected in the forward-looking statements are reasonable, we cannot guarantee future results, levels of activity, performance or achievements.
MORE SPEED
2x Faster
Why Speed
Matters
Faster application load times.
Increased responsiveness.
Increased ability to handle
the data-intensive
programs of tomorrow.
Speeds to
power the
systems of
tomorrow.
MORE EFFICIENT
Up to 20%
less power
Energy E cient
Reduced System Temps
Less heat generated
per module makes it easy
to keep your system cool.
DDR3 (1.5V)
DDR4 (1.2V)
Lower Energy Costs
Less voltage means big
savings for data centers and
large-scale applications.
$$$
Longer Battery Life
Less voltage allows for
longer battery life.
Smaller dies allow more
gigabits per component.
Gigabit
Why Density
Matters
DDR4 allows you to get
more out of a single
memory module.
More capacity per
component allows for
higher density modules.
8Gb DDR4 Component
4Gb DDR3 Component
Higher density modules
allow for greater
RAM capacity, which
will pave the way for
next-gen performance.
Up to 16GB
DDR4 UDIMMs
2.5 VOLTS
SPEED 266 MT/s
DENSITY 128Mb
1.8 VOLTS
SPEED 400 MT/s
DENSITY 256Mb
1.5 VOLTS
SPEED 1066 MT/s
DENSITY 1Gb
1.2 VOLTS
SPEED 2133 MT/s
DENSITY 4Gb
2133+
MT/s
DDR4
DDR3 1066 MT/s
DDR2 400 MT/s
DDR 266 MT/s
DDR4 2133 MT/s
Technologie de mémoire DDR4 Crucial®
2002 2004 2007 2014
20%
DE BAISSE
par rapport à DDR3
300%
D’AUGMENTATION
par rapport à DDR3
100%
D’AUGMENTATION
par rapport à DDR3
16.6%
DE BAISSE
par rapport à DDR2
300%
D’AUGMENTATION
par rapport à DDR2
166.5%
D’AUGMENTATION
par rapport à DDR2
28%
DE BAISSE
par rapport à DDR
100%
D’AUGMENTATION
par rapport à DDR
50.3%
D’AUGMENTATION
par rapport à DDR
Avancées technologiques
en fonction des chi res,
en commençant par DDR
Mémoire nouvelle génération. Performance nouvelle génération.
DENSITÉ SUPÉRIEURE
2x plus dense
©2013 Micron Technology, Inc. Tous droits réservés. Informations pouvant être modifiées sans préavis. Crucial et le logo Crucial sont des marques de commerce de Micron Technology, Inc. Toutes les autres
marques de commerce et de service sont la propriété de leurs propriétaires respectifs.
NOTA : cet infographique contient des déclarations prospectives concernant la production du DDR4. Les événements ou résultats réels peuvent être substantiellement di érents de ceux qui sont contenus
dans les déclarations prospectives. Veuillez vous référer aux fichiers de documents de Micron déposés sur une base consolidée à intervalles réguliers auprès de la Securities and Exchange Commission, plus
précisément le Formulaire 10-K et le Formulaire 10-Q les plus récents de Micron. Ces documents contiennent et identifient les facteurs importants qui pourraient causer des di érences substantielles entre les
résultats réels de Micron sur une base consolidée et ceux qui sont indiqués dans nos déclarations prospectives (voir Certains facteurs). Bien que nous pensions que les attentes reflétées dans les déclarations
prospectives soient raisonnables, nous ne pouvons pas garantir des résultats, des niveaux d’activité, des performances ou des accomplissements futurs.
PLUS RAPIDE
2x plus rapide
Pourquoi la vitesse
compte
Chargement plus rapide
des applications.
Réactivité améliorée.
Capacité accrue de traiter
les programmes à grand
volume de données de l’aveznir.
Des vitesses
capables
d'alimenter
les systèmes
du futur.
PLUS EFFICACE
Jusqu’à 20 % en moins
en consommation
Haut rendement
énergétique
Moins de surchau e
Moins de chaleur par module
= votre système a moins
tendance à surchau er.
DDR3 (1,5 V)
DDR4 (1,2 V)
Coût énergétique inférieur
Moins de consommation =
économies importantes
pour les centres de données
et les applications
de grande envergure.
$$$
Durée de vie de la
batterie plus longue
Moins de consommation
pour une durée de vie
de la batterie plus accrue.
La taille inférieure des puces
permet plus de gigabits
par composant.
Gigabit
Pourquoi la densité
compte
La DDR4 vous permet de
bénéficier de bien plus qu'un
simple module de mémoire.
La capacité supérieure
par composant permet
des modules de densité
plus élevée.
Composant DDR4 de 8 Gbit
Composant DDR3 de 4 Gbit
Les modules de densité
plus élevée permettent une
capacité de RAM supérieure,
ce qui ouvrira la voie pour
une performance
nouvelle génération.
Des DDR4 UDIMM
de jusqu’à 16 Go
2,5 VOLTS
VITESSE 266 MT/s
1,2 VOLTS
VITESSE 2133 MT/s
DENSITÉ 4 Gbit
DENSITÉ 1 Gbit
DENSITÉ 128 Mbit
1,8 VOLTS
VITESSE 400 MT/s
DENSITÉ 256 Mbit
1,5 VOLTS
VITESSE 1066 MT/s
2133+
MT/s
DDR4
DDR3 1066 MT/s
DDR2 400 MT/s
DDR 266 MT/s
DDR4 2133 MT/s
Ti400, Ti300 and Ti200 Thermal
Imagers with LaserSharp® Auto Focus
Get accurate readings and
consistently in-focus images
Fluke Thermal Imagers
Experience. Performance. Confidence.
Quickly capture an in-focus image with the pull of a trigger and
wirelessly share measurements with your team anytime, anywhere
with the Fluke ConnectTM ShareLiveTM video call.
• Quickly get accurate readings and in-focus images with
LaserSharp® Auto Focus
• Save Reporting Time. Make better decisions faster than before.
Organize your measurements by asset in one location with
EquipmentLogTM history.
• Brilliantly detailed quality images. Pixel for pixel the best spatial
resolution available.
• Precisely blended visual and infrared images with crucial details
to assist in identifying potential problems—IR-Fusion® technology
with AutoBlendTM mode
• Standard and radiometric video recording and video streaming*
• Text and voice recording/annotation allows you to save additional
details to image files
• Extensive memory options—Removable micro SD memory card,
on-board flash memory, save-to-USB capability, direct download
via USB-to-PC connection
* Firmware updates for these features are not available yet in all countries. Users notified via SmartView
Technical Data
Three-phase Full Visible Three-phase Full Infrared Three-phase AutoBlend Mode
Superior Image Quality
Spatial Resolution
Ti400
1.31 mRad
Ti300
1.75 mRad
Ti200
2.09 mRad
Resolution
Ti400
320x240 (76,800 pixels)
Ti300
240X180 (43,200 pixels)
Ti200
200X150 (30,000 pixels)
Field of View
Ti400, Ti300, Ti200
24 °H x 17 °V
Built with
Now compatible with Fluke
Connect™ Mobile App
IR-Fusion® Technology with
AutoBlendTM Mode
Precisely blended visual and infrared images with crucial details to
assist in identifying potential problems.2 Fluke Corporation Ti400, Ti300 and Ti200 Thermal Imagers with LaserSharp® Auto Focus
Detailed specifications
Ti400 Ti300 Ti200
Key features
IFOV with standard lens (spatial resolution) 1.31 mRad 1.75 mRad 2.09 mRad
Resolution 320x240 (76,800 pixels) 240X180 (43,200 pixels) 200X150 (30,000 pixels)
Field of view 24 °H x 17 °V
Minimum focus distance 15 cm (approx. 6 in)
IFOV with optional telephoto lens 0.65 mRad 0.87 mRad 1.05 mRad
Field of view 12 °H x 9 °V
Minimum focus distance 45 cm (approx. 18 in)
IFOV with optional wide-angle lens 2.62 mRad 3.49 mRad 4.19 mRad
Field of view 46 °H x 34 °V
Minimum focus distance 15 cm (approx. 6 in)
LaserSharp® Auto Focus Yes, for consistently in-focus images. Every. Single. Time.
Advanced manual focus Yes
Wireless connectivity Yes, to PC, iPhone® and iPad® (iOS 4s and later), Android™ 4.3 and up, and WiFi to LAN*
Fluke ConnectTM App compatible* Yes* (where available)
CNXTM Wireless System* Yes* (where available)
IR-Fusion® technology Yes
AutoBlendTM mode Yes
Picture-In-Picture (PIP) Yes
Ruggedized touchscreen display (Capacitive) 8.9 cm (3.5 in) diagonal landscape color VGA (640 x 480) LCD with backlight
Rugged, ergonomic design for one-handed use Yes
Thermal sensitivity (NETD) ≤ 0.05 °C at 30 °C target temp (50 mK) ≤ 0.075 °C at 30 °C target temp
(75 mK)
Temperature measurement range (not calibrated below -10 °C) -20 °C to +1200 °C
(-4 °F to +2192 °F)
-20 °C to +650 °C (-4 °F to +1202 °F)
Level and span Smooth auto and manual scaling
Fast auto toggle between manual and auto modes Yes
Fast auto-rescale in manual mode Yes
Minimum span (in manual mode) 2.0 °C (3.6 °F)
Minimum span (in auto mode) 3.0 °C (5.4 °F)
Built-in digital camera (visible light) 5 megapixel industrial performance
Frame rate 9 Hz
Laser pointer Yes
Torch Yes
Data storage and image capture
Extensive memory options Removable micro SD memory card, on-board flash memory, save-to-USB capability,
direct download via USB-to-PC connection
Image capture, review, save mechanism One-handed image capture, review, and save capability
File formats Non-radiometric (.bmp) or (.jpeg) or fully-radiometric (.is2); No analysis software required for
non-radiometric (.bmp, .jpg and .avi*) files
Memory review Thumbnail view navigation and review selection
Software SmartView® software, Fluke ConnectTM, and SmartView® Mobile App—full analysis and reporting software
Export file formats with SmartView® software BMP, DIB, GIF, JPE, JFIF, JPEG, JPG, PNG, TIF, and TIFF
Voice annotation 60 seconds maximum recording time per image; reviewable playback on camera
IR-PhotoNotesTM Yes
Text annotation* Yes
Video recording* Standard and Radiometric
Streaming video Via USB to PC and HDMI to HDMI compatible screen
File formats video* Non-radiometric (MPEG - encoded .AVI) and fully-radiometric (.IS3)*
Auto capture (temperature and interval)* Yes*3 Fluke Corporation Ti400, Ti300 and Ti200 Thermal Imagers with LaserSharp® Auto Focus
Detailed specifications
Remote control and operation (for special and advanced applications) Yes —
Ti400 Ti300 Ti200
Battery
Batteries (field-replaceable, rechargeable) Two lithium ion smart battery packs with five-segment LED display to show charge level
Battery life Four+ hours continuous use per battery pack (assumes 50 % brightness of LCD and average usage)
Battery charge time 2.5 hours to full charge
AC battery charging system Two-bay AC battery charger (110 V AC to 220 V AC, 50/60 Hz) (included), or in-imager charging.
AC mains adapters included in 9 Hz versions. Optional 12 V automotive charging adapter.
AC operation AC operation with included power supply (110 V AC to 220 V AC, 50/60 Hz). AC mains adapters included.
Power saving User selectable sleep and power off modes
Temperature measurement
Accuracy ± 2 °C or 2 % (at 25 °C nominal, whichever is greater)
On-screen emissivity correction Yes (both number and table)
On-screen reflected background temperature compensation Yes
On-screen transmission correction Yes
Color Palettes
Standard Palettes 8: Ironbow, Blue-Red, High Contrast, Amber, Amber Inverted, Hot Metal, Grayscale, Grayscale Inverted
Ultra ContrastTM Palettes 8: Ironbow Ultra, Blue-Red Ultra, High Contrast Ultra, Amber Ultra, Amber Inverted Ultra,
Hot Metal Ultra, Grayscale Ultra, Grayscale Inverted Ultra
General specifications
Color alarms (temperature alarms) High-temperature , low-temperature, and isotherm
Infrared spectral band 7.5 μm to 14 μm (long wave)
Operating temperature -10 °C to +50 °C (14 °F to 122 °F)
Storage temperature -20 °C to +50 °C (-4 °F to 122 °F) without batteries
Relative humidity 10 % to 95 % non-condensing
Center-point temperature measurement Yes
Spot markers User selectable hot spot and cold spot markers, 3 user definable spot markers on camera
and in Smartview®
Center box (MIN-MAX-AVG) Expandable-contractable measurement box with MIN-MAX-AVG temp
Safety standards UL 61010-1:2012 CAN/CSA-C22.2 No.61010-1-12 IEC 61010-1 3rd Edition (2010)
Electromagnetic compatibility EN 61326-1:2006 IEC 61326-1:2005
C Tick IEC/EN 61326-1
US FCC CFR 47, Part 15 Subpart B Class B
Vibration 0.03 g2/Hz (3.8 grms), 2.5g IEC 68-2-6
Shock 25 g, IEC 68-2-29
Drop Engineered to withstand 2 meter (6.5 feet) drop with standard lens
Size (H x W x L) 27.7 cm x 12.2 cm x 16.7 cm (10.9 in x 4.8 in x 6.5 in)
Weight (battery included) 1.04 Kg (2.3 lb)
Enclosure rating IP54 (protected against dust, limited ingress; protection against water spray from all directions)
Warranty Two-years (standard), extended warranties are available.
Recommended calibration cycle Two-years (assumes normal operation and normal aging)
Supported languages Czech, Dutch, English, Finnish, French, German, Hungarian, Italian, Japanese, Korean, Polish, Portuguese,
Russian, Simplified Chinese, Spanish, Swedish, Traditional Chinese, and Turkish
* Firmware updates for these features are not available yet in all countries. Users notified via SmartView® software when available.
4 Fluke Corporation Ti400, Ti300 and Ti200 Thermal Imagers with LaserSharp® Auto Focus
Ordering information
FLK-Ti400 9Hz Thermal Imager, 9 Hz
FLK-Ti300 9Hz Thermal Imager, 9 Hz
FLK-Ti200 9Hz Thermal Imager, 9 Hz
Included
Thermal imager with standard infrared lens; ac power
supply and battery pack charger (including main adapters);
two, rugged lithium ion smart battery packs; USB cable;
HDMI video cable; SmartView® software available via free
download; rugged, hard carrying case; soft transport bag;
adjustable hand strap; warranty registration card.
Optional accessories
FLK-LENS/TELE2 Infrared Telephoto Lens (2X
magnification)
FLK-LENS/WIDE2 Infrared Wide Angle Lens
TI-CAR-CHARGER Car Charger
FLK-TI-VISOR3 Sun Visor
BOOK-ITP Introduction to Thermography Principles Book
TI-TRIPOD3 Tripod Mounting Accessory
FLK-Ti-SBP3 Additional Smart Battery
FLK-TI-SBC3 Additional Smart Battery Charger
Visit the Fluke website to get complete details on these
products or ask your local Fluke sales representative.
RF connection time (binding time) may take up to 1 minute.
Built with
Fluke Connect with ShareLiveTM is the only wireless measurement
system that lets you stay in contact with your entire team without
leaving the field. The Fluke Connect mobile app is available
for AndroidTM (4.3 and up) and iOS (4s and later) and works with
over 20 different Fluke products—the largest system of connected
test tools in the world. And more are on the way. Go to the Fluke
website to find out more.
See it. Save it. Share it.
All the facts, right in the field.
Smart phone not included with purchase.
All trademarks are the property of their respective owners. Smart phone, wireless service, and data plan
not included with purchase. The first 5GB of storage is free. Compatible with Android™ (4.3 and up) and
iOS (4s and later). Apple and the Apple logo are trademarks of Apple Inc., registered in the U.S. and other
countries. App Store is a service mark of Apple Inc. Google Play is a trademark of Google Inc.
Fluke Europe B.V.
P.O. Box 1186
5602 BD Eindhoven
The Netherlands
Web: www.fluke.co.uk
For more information call:
In Europe/M-East/Africa
+31 (0)40 267 5100 or
Fax +31 (0)40 267 5222
Fluke. Keeping your world
up and running.®
Fluke (UK) Ltd.
52 Hurricane Way
Norwich, Norfolk
NR6 6JB
United Kingdom
Tel.: +44 (0) 20 7942 0700
Fax: +44 (0) 20 7942 0701
E-mail: industrial@uk.fluke.nl
Web: www.fluke.co.uk
©2014 Fluke Corporation.
Specifications subject to change without notice.
5/2014 Pub_ID: 13036-eng
Modification of this document is not permitted without
written permission from Fluke Corporation.
Download the app at:
Crucial Ballistix Sport XT Memory
Performance memory for gamers and enthusiasts
XMP profile for advanced speeds and timings
Tall, aggressive heat spreader
Premium-quality DRAM
Easy to install
Limited lifetime warranty
Get ready to play.
Engineered to deliver fast and reliable performance memory for enthusiasts and mainstream users alike, the Crucial
Ballistix Sport series is a great place to start. Touting all the usual benefits of a memory upgrade — faster load times,
better system responsiveness, and increased ability to handle data-intensive games — Ballistix Sport modules also
feature an array of additional features. With an eye-catching design, premium-quality DRAM, and a stylish integrated heat
spreader for thermal performance, Ballistix Sport makes it easy to take your game to the next level. Since Ballistix Sport
performance memory is budget-friendly and compatible with nearly every type of system, you’ll be hard pressed to find a
better win.
Ballistix Sport XT modules: aggressive performance.
Ballistix Sport XT memory offers faster and more aggressive performance. Designed for gamers who are comfortable
changing BIOS settings to unleash their memory’s full potential, Sport XT modules offer blazing-fast DDR3 speeds and
are available in higher densities. With an expanded heat spreader that offers more surface area for heat dissipation,
Sport XT modules enable better thermal performance. Coupled with an aggressive design and XMP profiles for easy
configuration in Intel®-supported systems, Sport XT modules deliver no-hassle performance so you can own your
opponents.
1/231
PRELIMINARY DATA
January 2005
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
uPSD33xx
Turbo Series
Fast 8032 MCU with Programmable Logic
FEATURES SUMMARY
■ FAST 8-BIT TURBO 8032 MCU, 40MHz
– Advanced core, 4-clocks per instruction
– 10 MIPs peak performance at 40MHz (5V)
– JTAG Debug and In-System
Programming
– Branch Cache & 6 instruction Prefetch
Queue
– Dual XDATA pointers with auto incr & decr
– Compatible with 3rd party 8051 tools
■ DUAL FLASH MEMORIES WITH MEMORY
MANAGEMENT
– Place either memory into 8032 program
address space or data address space
– READ-while-WRITE operation for InApplication
Programming and EEPROM
emulation
– Single voltage program and erase
– 100K guaranteed erase cycles, 15-year
retention
■ CLOCK, RESET, AND SUPPLY
MANAGEMENT
– SRAM is Battery Backup capable
– Flexible 8-level CPU clock divider register
– Normal, Idle, and Power Down Modes
– Power-on and Low Voltage reset
supervisor
– Programmable Watchdog Timer
■ PROGRAMMABLE LOGIC, GENERAL
PURPOSE
– 16 macrocells
– Create shifters, state machines, chipselects,
glue-logic to keypads, panels,
LCDs, others
■ COMMUNICATION INTERFACES
– I2C Master/Slave controller, 833KHz
– SPI Master controller, 10MHz
– Two UARTs with independent baud rate
– IrDA protocol support up to 115K baud
– Up to 46 I/O, 5V tolerant on 3.3V
uPSD33xxV
Figure 1. Packages
■ A/D CONVERTER
– Eight Channels, 10-bit resolution, 6µs
■ TIMERS AND INTERRUPTS
– Three 8032 standard 16-bit timers
– Programmable Counter Array (PCA), six
16-bit modules for PWM, CAPCOM, and
timers
– 8/10/16-bit PWM operation
– 11 Interrupt sources with two external
interrupt pins
■ OPERATING VOLTAGE SOURCE (±10%)
– 5V devices use both 5.0V and 3.3V
sources
– 3.3V devices use only 3.3V sourceuPSD33xx
2/231
Table 1. Device Summary
Part Number
1st
Flash
(bytes)
2nd
Flash
(bytes)
SRAM
(bytes) GPIO 8032
Bus VCC VDD Pkg. Temp.
uPSD3312D-40T6 64K 16K 2K 37 No 3.3V 5.0V TQFP52 –40°C to 85°C
uPSD3312DV-40T6 64K 16K 2K 37 No 3.3V 3.3V TQFP52 –40°C to 85°C
uPSD3333D-40T6 128K 32K 8K 37 No 3.3V 5.0V TQFP52 –40°C to 85°C
uPSD3333DV-40T6 128K 32K 8K 37 No 3.3V 3.3V TQFP52 –40°C to 85°C
uPSD3333D-40U6 128K 32K 8K 46 Yes 3.3V 5.0V TQFP80 –40°C to 85°C
uPSD3333DV-40U6 128K 32K 8K 46 Yes 3.3V 3.3V TQFP80 –40°C to 85°C
uPSD3334D-40U6 256K 32K 8K 46 Yes 3.3V 5.0V TQFP80 –40°C to 85°C
uPSD3334DV-40U6 256K 32K 8K 46 Yes 3.3V 3.3V TQFP80 –40°C to 85°C
uPSD3354D-40T6 256K 32K 32K 37 No 3.3V 5.0V TQFP52 –40°C to 85°C
uPSD3354DV-40T6 256K 32K 32K 37 No 3.3V 3.3V TQFP52 –40°C to 85°C
uPSD3354D-40U6 256K 32K 32K 46 Yes 3.3V 5.0V TQFP80 –40°C to 85°C
uPSD3354DV-40U6 256K 32K 32K 46 Yes 3.3V 3.3V TQFP80 –40°C to 85°C3/231
uPSD33xx
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
uPSD33xx HARDWARE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Internal Memory (MCU Module, Standard 8032 Memory: DATA, IDATA, SFR) . . . . . . . . . . . . 16
External Memory (PSD Module: Program memory, Data memory). . . . . . . . . . . . . . . . . . . . . . 16
8032 MCU CORE PERFORMANCE ENHANCEMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Pre-Fetch Queue (PFQ) and Branch Cache (BC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PFQ Example, Multi-cycle Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Aggregate Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
MCU MODULE DISCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8032 MCU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Data Pointer (DPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Program Counter (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Accumulator (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
B Register (B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
General Purpose Registers (R0 - R7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Program Status Word (PSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SPECIAL FUNCTION REGISTERS (SFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8032 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Register Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
External Direct Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
External Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Indexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Relative Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Absolute Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Long Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Bit Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
uPSD33xx INSTRUCTION SET SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32uPSD33xx
4/231
DUAL DATA POINTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Data Pointer Control Register, DPTC (85h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Data Pointer Mode Register, DPTM (86h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DEBUG UNIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
INTERRUPT SYSTEM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Individual Interrupt Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
MCU CLOCK GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
MCU_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
PERIPH_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Power-down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Reduced Frequency Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
OSCILLATOR AND EXTERNAL COMPONENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
I/O PORTS of MCU MODULE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
MCU Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
MCU BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Bus Read Cycles (PSEN or RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Bus Write Cycles (WR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Controlling the PFQ and BC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
SUPERVISORY FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
External Reset Input Pin, RESET_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Low VCC Voltage Detect, LVD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Power-up Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
JTAG Debug Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Watchdog Timer, WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
STANDARD 8032 TIMER/COUNTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Standard Timer SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SFR, TCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SFR, TMOD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Timer 0 and Timer 1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
SERIAL UART INTERFACES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
UART Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815/231
uPSD33xx
Serial Port Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
UART Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
More About UART Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
More About UART Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
More About UART Modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
IrDA INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Pulse Width Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
I
2C INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
I2C Interface Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Communication Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
General Call Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Serial I/O Engine (SIOE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
I
2C Interface Control Register (S1CON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
I
2C Interface Status Register (S1STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
I2C Data Shift Register (S1DAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
I
2C Address Register (S1ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
I
2C START Sample Setting (S1SETUP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
I
2C Operating Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
SPI (SYNCHRONOUS PERIPHERAL INTERFACE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
SPI Bus Features and Communication Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Bus-Level Activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
SPI SFR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Dynamic Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
ANALOG-TO-DIGITAL CONVERTOR (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Port 1 ADC Channel Selects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
PROGRAMMABLE COUNTER ARRAY (PCA) WITH PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
PCA Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
PCA Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Operation of TCM Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Capture Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Toggle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
PWM Mode - (X8), Fixed Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
PWM Mode - (X8), Programmable Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
PWM Mode - Fixed Frequency, 16-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129uPSD33xx
6/231
PWM Mode - Fixed Frequency, 10-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Writing to Capture/Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Control Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
TCM Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
PSD MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
PSD Module Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Runtime Control Register Definitions (csiop). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
PSD Module Detailed Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
PSD Module Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2307/231
uPSD33xx
SUMMARY DESCRIPTION
The Turbo uPSD33xx Series combines a powerful
8051-based microcontroller with a flexible memory
structure, programmable logic, and a rich peripheral
mix to form an ideal embedded controller. At
its core is a fast 4-cycle 8032 MCU with a 6-byte
instruction prefetch queue (PFQ) and a 4-entry fully
associative branching cache (BC) to maximize
MCU performance, enabling loops of code in
smaller localities to execute extremely fast.
Code development is easily managed without a
hardware In-Circuit Emulator by using the serial
JTAG debug interface. JTAG is also used for InSystem
Programming (ISP) in as little as 10 seconds,
perfect for manufacturing and lab development.
The 8032 core is coupled to Programmable
System Device (PSD) architecture to optimize the
8032 memory structure, offering two independent
banks of Flash memory that can be placed at virtually
any address within 8032 program or data address
space, and easily paged beyond 64K bytes
using on-chip programmable decode logic. Dual
Flash memory banks provide a robust solution for
remote product updates in the field through In-Application
Programming (IAP). Dual Flash banks
also support EEPROM emulation, eliminating the
need for external EEPROM chips. General purpose
programmable logic (PLD) is included to
build an endless variety of glue-logic, saving external
logic devices. The PLD is configured using the
software development tool, PSDsoft Express,
available from the web at www.st.com/psm, at no
charge. The uPSD33xx also includes supervisor
functions such as a programmable watchdog timer
and low-voltage reset.
Figure 2. Block Diagram
PA0:7
PB0:7
PD1:2
PC0:7
MCU
Bus
P4.0:7
P1.0:7
P3.0:7
uPSD33xx SYSTEM BUS
Dedicated
Pins
Supervisor:
Watchdog and Low-Voltage Reset
1st Flash Memory:
64K, 128K,
or 256K Bytes
2nd Flash Memory:
16K or 32K Bytes
SRAM:
2K, 8K, or 32K Bytes
Programmable
Decode and
Page Logic
General
Purpose
Programmable
Logic,
16 Macrocells
(8) GPIO, Port A
(80-pin only)
(8) GPIO, Port B
(4) GPIO, Port C
(2) GPIO, Port D
JTAG ICE and ISP
8032 Address/Data/Control Bus
(80-pin device only)
VCC, VDD, GND, Reset, Crystal In
Turbo
8032
Core
PFQ
&
BC
(3) 16-bit
Timer/
Counters
(2)
External
Interrupts
I
2
C
SPI
(8) 10-bit ADC
UART0
(8) GPIO, Port 1
(8) GPIO, Port 3
(8) GPIO, Port 4
UART1 Optional IrDA
Encoder/Decoder
16-bit PCA
(6) PWM, CAPCOM, TIMER
AI08875uPSD33xx
8/231
PIN DESCRIPTIONS
Figure 3. TQFP52 Connections
Note: 1. For 5V applications, VDD must be connected to a 5.0V source. For 3.3V applications, VDD must be connected to a 3.3V source.
2. These signals can be used on one of two different ports (Port 1 or Port 4) for flexibility. Default is Port1.
3. VREF and 3.3V AVCC are shared in the 52-pin package only. ADC channels must use AVCC as VREF for the 52-pin package.
39 P1.5/SPIRXD(2)/ADC5
38 P1.4/SPICLK(2)/ADC4
37 P1.3/TXD1(IrDA)(2)/ADC3
36 P1.2/RXD1(IrDA)(2)/ADC2
35 P1.1/T2X(2)/ADC1
34 P1.0/T2(2)/ADC0
33 VDD(1)
32 XTAL2
31 XTAL1
30 P3.7/SCL
29 P3.6/SDA
28 P3.5/C1
27 P3.4/C0
PD1/CLKIN
PC7
JTAG TDO
JTAG TDI
DEBUG
3.3V VCC
PC4/TERR
VDD(1)
GND
PC3/TSTAT
PC2/VSTBY
JTAG TCK
JTAG TMS
1
2
3
4
5
6
7
8
9
10
11
12
13
52
51
50
49
48
47
46
45
44
43
42
41
40
PB0
PB1
PB2
PB3
PB4
AVCC/VREF(3)
PB5
GND
RESET_IN
PB6
PB7
P1.7/SPISEL(2)/ADC7
P1.6/SPITXD(2)/ADC6
14
15
16
17
18
19
20
21
22
23
24
25
26
SPISEL(2)/PCACLK1/P4.7
SPITXD(2)/TCM5/P4.6
SPIRXD(2)/TCM4/P4.5
SPICLK(2)/TCM3/P4.4
TXD1(IrDA)(2)/PCACLK0/P4.3
GND
RXD1(IrDA)(2)/TCM2/P4.2
T2X(2)/TCM1/P4.1
T2(2)/TCM0/P4.0
RXD0/P3.0
TXD0/P3.1
EXTINT0/TG0/P3.2
EXTINT1/TG1/P3.3
AI078229/231
uPSD33xx
Figure 4. TQFP80 Connections
Note: NC = Not Connected
Note: 1. For 5V applications, VDD must be connected to a 5.0V source. For 3.3V applications, VDD must be connected to a 3.3V source.
2. These signals can be used on one of two different ports (Port 1 or Port 4) for flexibility. Default is Port1.
60 P1.5/SPIRXD(2)/ADC5
59 P1.4/SPICLK(2)/ADC4
58 P1.3/TXD1(IrDA)(2)/ADC3
57 MCU A11
56 P1.2/RXD1(IrDA)(2)/ADC2
55 MCU A10
54 P1.1/T2X(2)/ADC1
53 MCU A9
52 P1.0/T2(2)/ADC0
51 MCU A8
50 VDD(1)
49 XTAL2
48 XTAL1
47 MCU AD7
46 P3.7/SCL
45 MCU AD6
44 P3.6/SDA
43 MCU AD5
42 P3.5/C1
41 MCU AD4
PD2/CSI
P3.3/TG1/EXINT1
PD1/CLKIN
ALE
PC7
JTAG TDO
JTAG TDI
DEBUG
PC4/TERR
3.3V VCC
NC
VDD(1)
GND
PC3/TSTAT
PC2/VSTBY
JTAG TCK
NC
SPISEL(2)/PCACLK1/P4.7
SPITXD(2)/TCM5/P4.6
JTAG TMS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PB0
P3.2/EXINT0/TG0
PB1
P3.1/TXD0
PB2
P3.0/RXD0
PB3
PB4
AVCC
PB5
VREF
GND
RESET_IN
PB6
PB7
RD
P1.7/SPISEL(2)/ADC7
PSEN
WR
P1.6/SPITXD(2)/ADC6
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PA7
PA6
SPIRXD(2)/TCM4/P4.5
PA5
SPICLK(2)/TCM3/P4.4
PA4
TXD1(IrDA)(2)/PCACLK0/P4.3
PA3
GND
RXD1(IrDA)(2)/TCM2/P4.2
T2X(2)/TCM1/P4.1
PA2
T2(2)/TCM0/P4.0
PA1
PA0
MCU AD0
MCU AD1
MCU AD2
MCU AD3
P3.4/C0
AI07823uPSD33xx
10/231
Table 2. Pin Definitions
Port Pin Signal
Name
80-Pin
No.
52-Pin
No.(1) In/Out
Function
Basic Alternate 1 Alternate 2
MCUAD0 AD0 36 N/A I/O
External Bus
Multiplexed Address/
Data bus A0/D0
MCUAD1 AD1 37 N/A I/O Multiplexed Address/
Data bus A1/D1
MCUAD2 AD2 38 N/A I/O Multiplexed Address/
Data bus A2/D2
MCUAD3 AD3 39 N/A I/O Multiplexed Address/
Data bus A3/D3
MCUAD4 AD4 41 N/A I/O Multiplexed Address/
Data bus A4/D4
MCUAD5 AD5 43 N/A I/O Multiplexed Address/
Data bus A5/D5
MCUAD6 AD6 45 N/A I/O Multiplexed Address/
Data bus A6/D6
MCUAD7 AD7 47 N/A I/O Multiplexed Address/
Data bus A7/D7
MCUA8 A8 51 N/A O External Bus, Addr
A8
MCUA9 A9 53 N/A O External Bus, Addr
A9
MCUA10 A10 55 N/A O External Bus, Addr
A10
MCUA11 A11 57 N/A O External Bus, Addr
A11
P1.0 T2
ADC0 52 34 I/O General I/O port pin Timer 2 Count input
(T2)
ADC Channel 0
input (ADC0)
P1.1 T2X
ADC1 54 35 I/O General I/O port pin Timer 2 Trigger input
(T2X)
ADC Channel 1
input (ADC1)
P1.2 RxD1
ADC2 56 36 I/O General I/O port pin UART1 or IrDA
Receive (RxD1)
ADC Channel 2
input (ADC2)
P1.3 TXD1
ADC3 58 37 I/O General I/O port pin UART or IrDA
Transmit (TxD1)
ADC Channel 3
input (ADC3)
P1.4 SPICLK
ADC4 59 38 I/O General I/O port pin SPI Clock Out
(SPICLK)
ADC Channel 4
input (ADC4)
P1.5 SPIRxD
ADC6 60 39 I/O General I/O port pin SPI Receive
(SPIRxD)
ADC Channel 5
input (ADC5)
P1.6 SPITXD
ADC6 61 40 I/O General I/O port pin SPI Transmit
(SPITxD)
ADC Channel 6
input (ADC6)
P1.7 SPISEL
ADC7 64 41 I/O General I/O port pin SPI Slave Select
(SPISEL)
ADC Channel 7
input (ADC7)
P3.0 RxD0 75 23 I/O General I/O port pin UART0 Receive
(RxD0)
P3.1 TXD0 77 24 I/O General I/O port pin UART0 Transmit
(TxD0)
P3.2 EXINT0
TGO 79 25 I/O General I/O port pin
Interrupt 0 input
(EXTINT0)/Timer 0
gate control (TG0)
P3.3 INT1 2 26 I/O General I/O port pin
Interrupt 1 input
(EXTINT1)/Timer 1
gate control (TG1)
P3.4 C0 40 27 I/O General I/O port pin Counter 0 input (C0)11/231
uPSD33xx
P3.5 C1 42 28 I/O General I/O port pin Counter 1 input (C1)
P3.6 SDA 44 29 I/O General I/O port pin I
2C Bus serial data
(I2CSDA)
P3.7 SCL 46 30 I/O General I/O port pin I
2C Bus clock
(I2CSCL)
P4.0 T2
TCM0 33 22 I/O General I/O port pin Program Counter
Array0 PCA0-TCM0
Timer 2 Count input
(T2)
P4.1 T2X
TCM1 31 21 I/O General I/O port pin PCA0-TCM1 Timer 2 Trigger input
(T2X)
P4.2 RXD1
TCM2 30 20 I/O General I/O port pin PCA0-TCM2 UART1 or IrDA
Receive (RxD1)
P4.3 TXD1
PCACLK0 27 18 I/O General I/O port pin PCACLK0 UART1 or IrDA
Transmit (TxD1)
P4.4 SPICLK
TCM3 25 17 I/O General I/O port pin Program Counter
Array1 PCA1-TCM3
SPI Clock Out
(SPICLK)
P4.5 SPIRXD
TCM4 23 16 I/O General I/O port pin PCA1-TCM4 SPI Receive
(SPIRxD)
P4.6 SPITXD 19 15 I/O General I/O port pin PCA1-TCM5 SPI Transmit
(SPITxD)
P4.7 SPISEL
PCACLK1 18 14 I/O General I/O port pin PCACLK1 SPI Slave Select
(SPISEL)
VREF 70 N/A I Reference Voltage
input for ADC
RD 65 N/A O READ Signal,
external bus
WR 62 N/A O WRITE Signal,
external bus
PSEN 63 N/A O PSEN Signal,
external bus
ALE 4 N/A O Address Latch
signal, external bus
RESET_IN 68 44 I Active low reset
input
XTAL1 48 31 I Oscillator input pin
for system clock
XTAL2 49 32 O Oscillator output pin
for system clock
DEBUG 8 5 I/O I/O to the MCU
Debug Unit
PA0 35 N/A I/O General I/O port pin All Port A pins
support:
1. PLD Macro-cell
outputs, or
2. PLD inputs, or
3. Latched
Address Out
(A0-A7), or
4. Peripheral I/O
Mode
PA1 34 N/A I/O General I/O port pin
PA2 32 N/A I/O General I/O port pin
PA3 28 N/A I/O General I/O port pin
PA4 26 N/A I/O General I/O port pin
PA5 24 N/A I/O General I/O port pin
PA6 22 N/A I/O General I/O port pin
PA7 21 N/A I/O General I/O port pin
Port Pin Signal
Name
80-Pin
No.
52-Pin
No.(1) In/Out
Function
Basic Alternate 1 Alternate 2uPSD33xx
12/231
Note: 1. N/A = Signal Not Available on 52-pin package.
PB0 80 52 I/O General I/O port pin
All Port B pins
support:
1. PLD Macro-cell
outputs, or
2. PLD inputs, or
3. Latched
Address Out
(A0-A7)
PB1 78 51 I/O General I/O port pin
PB2 76 50 I/O General I/O port pin
PB3 74 49 I/O General I/O port pin
PB4 73 48 I/O General I/O port pin
PB5 71 46 I/O General I/O port pin
PB6 67 43 I/O General I/O port pin
PB7 66 42 I/O General I/O port pin
JTAGTMS TMS 20 13 I JTAG pin (TMS)
JTAGTCK TCK 16 12 I JTAG pin (TCK)
PC2 VSTBY 15 11 I/O General I/O port pin
SRAM Standby
voltage input
(VSTBY)
PLD Macrocell
output, or PLD input
PC3 TSTAT 14 10 I/O General I/O port pin Optional JTAG
Status (TSTAT)
PLD, Macrocell
output, or PLD input
PC4 TERR 9 7 I/O General I/O port pin Optional JTAG
Status (TERR)
PLD, Macrocell
output, or PLD input
JTAGTDI TDI 7 4 I JTAG pin (TDI)
JTAGTDO TDO 6 3 O JTAG pin (TDO)
PC7 5 2 I/O General I/O port pin PLD, Macrocell
output, or PLD input
PD1 CLKIN 3 1 I/O General I/O port pin
1. PLD I/O
2. Clock input to
PLD and APD
PD2 CSI 1 N/A I/O General I/O port pin
1. PLD I/O
2. Chip select ot
PSD Module
3.3V-VCC 10 6 VCC - MCU Module
AVCC 72 47 Analog VCC Input
VDD
3.3V or 5V 12 8
VDD - PSD Module
VDD - 3.3V for 3V
VDD - 5V for 5V
VDD
3.3V or 5V 50 33
VDD - PSD Module
VDD - 3.3V for 3V
VDD - 5V for 5V
GND 13 9
GND 29 19
GND 69 45
NC 11 N/A
NC 17 N/A
Port Pin Signal
Name
80-Pin
No.
52-Pin
No.(1) In/Out
Function
Basic Alternate 1 Alternate 213/231
uPSD33xx
uPSD33xx HARDWARE DESCRIPTION
The uPSD33xx has a modular architecture built
from a stacked die process. There are two die, one
is designated “MCU Module” in this document, and
the other is designated “PSD Module” (see Figure
5., page 14). In all cases, the MCU Module die operates
at 3.3V with 5V tolerant I/O. The PSD Module
is either a 3.3V die or a 5V die, depending on
the uPSD33xx device as described below.
The MCU Module consists of a fast 8032 core, that
operates with 4 clocks per instruction cycle, and
has many peripheral and system supervisor functions.
The PSD Module provides the 8032 with
multiple memories (two Flash and one SRAM) for
program and data, programmable logic for address
decoding and for general-purpose logic, and
additional I/O. The MCU Module communicates
with the PSD Module through internal address and
data busses (A8 – A15, AD0 – AD7) and control
signals (RD, WR, PSEN, ALE, RESET).
There are slightly different I/O characteristics for
each module. I/Os for the MCU module are designated
as Ports 1, 3, and 4. I/Os for the PSD Module
are designated as Ports A, B, C, and D.
For all 5V uPSD33xx devices, a 3.3V MCU Module
is stacked with a 5V PSD Module. In this case, a
5V uPSD33xx device must be supplied with
3.3VCC for the MCU Module and 5.0VDD for the
PSD Module. Ports 3 and 4 of the MCU Module
are 3.3V ports with tolerance to 5V devices (they
can be directly driven by external 5V devices and
they can directly drive external 5V devices while
producing a VOH of 2.4V min and VCC max). Ports
A, B, C, and D of the PSD Module are true 5V
ports.
For all 3.3V uPSD33xxV devices, a 3.3V MCU
Module is stacked with a 3.3V PSD Module. In this
case, a 3.3V uPSD33xx device needs to be supplied
with a single 3.3V voltage source at both VCC
and VDD. I/O pins on Ports 3 and 4 are 5V tolerant
and can be connected to external 5V peripherals
devices if desired. Ports A, B, C, and D of the PSD
Module are 3.3V ports, which are not tolerant to
external 5V devices.
Refer to Table 3 for port type and voltage source
requirements.
80-pin uPSD33xx devices provide access to 8032
address, data, and control signals on external pins
to connect external peripheral and memory devices.
52-pin uPSD33xx devices do not provide access
to the 8032 system bus.
All non-volatile memory and configuration portions
of the uPSD33xx device are programmed through
the JTAG interface and no special programming
voltage is needed. This same JTAG port is also
used for debugging of the 8032 core at runtime
providing breakpoint, single-step, display, and
trace features. A non-volatile security bit may be
programmed to block all access via JTAG interface
for security. The security bit is defeated only
by erasing the entire device, leaving the device
blank and ready to use again.
Table 3. Port Type and Voltage Source Combinations
Device Type VCC for MCU
Module
VDD for PSD
Module
Ports 3 and 4 on
MCU Module
Ports A, B, C, and D on
PSD Module
5V:
uPSD33xx 3.3V 5.0V 3.3V but 5V tolerant 5V
3.3V:
uPSD33xxV 3.3V 3.3V 3.3V but 5V tolerant 3.3V. NOT 5V tolerantuPSD33xx
14/231
Figure 5. uPSD33xx Functional Modules
10-bit
ADC
Dedicated Memory
Interface Prefetch,
Branch Cache
Enhanced MCU Interface
Decode PLD
PSD Page Register SRAM
JTAG ISP CPLD - 16 MACROCELLS
Reset Logic
WDT
Internal
Reset
Port 3 Port 1
Dual
UARTs
Interrupt
3 Timer /
Counters
256 Byte SRAM
Turbo 8032 Core
PSD Internal Bus
8032 Internal Bus
PSD
Reset
LVD
I
2
C
Unit
Port D
GPIO
Port C
JTAG and
GPIO
Secondary
Flash
Reset Input
uPSD33XX
JTAG
DEBUG
8-Bit Die-to-Die Bus
Main Flash
PCA
PWM
Counters
Reset
Pin
Ext.
Bus
SPI
VCC Pins
3.3V
VDD Pins
3.3V or 5V
MCU Module
PSD Module
Port 3 - UART0,
Intr, Timers Port 1 - Timer, ADC, SPI Port 4 - PCA,
PWM, UART1
Port 3
I
2
C
XTAL
Clock Unit
Port A,B,C PLD
I/O and GPIO
AI0784215/231
uPSD33xx
MEMORY ORGANIZATION
The 8032 MCU core views memory on the MCU
module as “internal” memory and it views memory
on the PSD module as “external” memory, see
Figure 6.
Internal memory on the MCU Module consists of
DATA, IDATA, and SFRs. These standard 8032
memories reside in 384 bytes of SRAM located at
a fixed address space starting at address 0x0000.
External memory on the PSD Module consists of
four types: main Flash (64K, 128K, or 256K bytes),
a smaller secondary Flash (16K, or 32K), SRAM
(2K, 8K, or 32K bytes), and a block of PSD Module
control registers called CSIOP (256 bytes). These
external memories reside at programmable address
ranges, specified using the software tool
PSDsoft Express. See the PSD Module section of
this document for more details on these memories.
External memory is accessed by the 8032 in two
separate 64K byte address spaces. One address
space is for program memory and the other address
space is for data memory. Program memory
is accessed using the 8032 signal, PSEN. Data
memory is accessed using the 8032 signals, RD
and WR. If the 8032 needs to access more than
64K bytes of external program or data memory, it
must use paging (or banking) techniques provided
by the Page Register in the PSD Module.
Note: When referencing program and data memory
spaces, it has nothing to do with 8032 internal
SRAM areas of DATA, IDATA, and SFR on the
MCU Module. Program and data memory spaces
only relate to the external memories on the PSD
Module.
External memory on the PSD Module can overlap
the internal SRAM memory on the MCU Module in
the same physical address range (starting at
0x0000) without interference because the 8032
core does not assert the RD or WR signals when
accessing internal SRAM.
Figure 6. uPSD33xx Memories
• External memories may be placed at virtually
any address using software tool PSDsoft Express.
• The SRAM and Flash memories may be placed
in 8032 Program Space or Data Space using
PSDsoft Express.
• Any memory in 8032 Data Space is XDATA.
64KB,
128KB,
or
256KB
16KB
or
32KB
Main
Flash
Internal SRAM on
MCU Module
External Memory on
PSD Module
IDATA SFR
DATA
Secondary
Flash
2KB,
8KB,
or
32KB
SRAM
256 Bytes
CSIOP
384 Bytes SRAM
Direct or Indirect Addressing
FF
80
7F
128 Bytes
128 Bytes
128 Bytes
0
Indirect
Addressing
Fixed
Addresses
Direct
Addressing
AI07843uPSD33xx
16/231
Internal Memory (MCU Module, Standard 8032
Memory: DATA, IDATA, SFR)
DATA Memory. The first 128 bytes of internal
SRAM ranging from address 0x0000 to 0x007F
are called DATA, which can be accessed using
8032 direct or indirect addressing schemes and
are typically used to store variables and stack.
Four register banks, each with 8 registers (R0 –
R7), occupy addresses 0x0000 to 0x001F. Only
one of these four banks may be enabled at a time.
The next 16 locations at 0x0020 to 0x002F contain
128 directly addressable bit locations that can be
used as software flags. SRAM locations 0x0030
and above may be used for variables and stack.
IDATA Memory. The next 128 bytes of internal
SRAM are named IDATA and range from address
0x0080 to 0x00FF. IDATA can be accessed only
through 8032 indirect addressing and is typically
used to hold the MCU stack as well as data variables.
The stack can reside in both DATA and
IDATA memories and reach a size limited only by
the available space in the combined 256 bytes of
these two memories (since stack accesses are always
done using indirect addressing, the boundary
between DATA and IDATA does not exist with
regard to the stack).
SFR Memory. Special Function Registers (Table
5., page 24) occupy a separate physical memory,
but they logically overlap the same 128 bytes as
IDATA, ranging from address 0x0080 to 0x00FF.
SFRs are accessed only using direct addressing.
There 86 active registers used for many functions:
changing the operating mode of the 8032 MCU
core, controlling 8032 peripherals, controlling I/O,
and managing interrupt functions. The remaining
unused SFRs are reserved and should not be accessed.
16 of the SFRs are both byte- and bit-addressable.
Bit-addressable SFRs are those whose address
ends in “0” or “8” hex.
External Memory (PSD Module: Program
memory, Data memory)
The PSD Module has four memories: main Flash,
secondary Flash, SRAM, and CSIOP. See the
PSD MODULE section for more detailed information
on these memories.
Memory mapping in the PSD Module is implemented
with the Decode PLD (DPLD) and optionally
the Page Register. The user specifies decode
equations for individual segments of each of the
memories using the software tool PSDsoft Express.
This is a very easy point-and-click process
allowing total flexibility in mapping memories. Additionally,
each of the memories may be placed in
various combinations of 8032 program address
space or 8032 data address space by using the
software tool PSDsoft Express.
Program Memory. External program memory is
addressed by the 8032 using its 16-bit Program
Counter (PC) and is accessed with the 8032 signal,
PSEN. Program memory can be present at
any address in program space between 0x0000
and 0xFFFF.
After a power-up or reset, the 8032 begins program
execution from location 0x0000 where the
reset vector is stored, causing a jump to an initialization
routine in firmware. At address 0x0003, just
following the reset vector are the interrupt service
locations. Each interrupt is assigned a fixed interrupt
service location in program memory. An interrupt
causes the 8032 to jump to that service
location, where it commences execution of the
service routine. External Interrupt 0 (EXINT0), for
example, is assigned to service location 0x0003. If
EXINT0 is going to be used, its service routine
must begin at location 0x0003. Interrupt service locations
are spaced at 8-byte intervals: 0x0003 for
EXINT0, 0x000B for Timer 0, 0x0013 for EXINT1,
and so forth. If an interrupt service routine is short
enough, it can reside entirely within the 8-byte interval.
Longer service routines can use a jump instruction
to somewhere else in program memory.
Data Memory. External data is referred to as
XDATA and is addressed by the 8032 using Indirect
Addressing via its 16-bit Data Pointer Register
(DPTR) and is accessed by the 8032 signals, RD
and WR. XDATA can be present at any address in
data space between 0x0000 and 0xFFFF.
Note: the uPSD33xx has dual data pointers
(source and destination) making XDATA transfers
much more efficient.
Memory Placement. PSD Module architecture
allows the placement of its external memories into
different combinations of program memory and
data memory spaces. This means the main Flash,
the secondary Flash, and the SRAM can be
viewed by the 8032 MCU in various combinations
of program memory or data memory as defined by
PSDsoft Express.
As an example of this flexibility, for applications
that require a great deal of Flash memory in data
space (large lookup tables or extended data recording),
the larger main Flash memory can be
placed in data space and the smaller secondary
Flash memory can be placed in program space.
The opposite can be realized for a different application
if more Flash memory is needed for code
and less Flash memory for data.17/231
uPSD33xx
By default, the SRAM and CSIOP memories on
the PSD Module must always reside in data memory
space and they are treated by the 8032 as
XDATA. However, the SRAM may optionally reside
in program space in addition to data space if
it is desired to execute code from SRAM. The main
Flash and secondary Flash memories may reside
in program space, data space, or both.
These memory placement choices specified by
PSDsoft Express are programmed into non-volatile
sections of the uPSD33xx, and are active at
power-up and after reset. It is possible to override
these initial settings during runtime for In-Application
Programming (IAP).
Standard 8032 MCU architecture cannot write to
its own program memory space to prevent accidental
corruption of firmware. However, this becomes
an obstacle in typical 8032 systems when
a remote update to firmware in Flash memory is
required using IAP. The PSD module provides a
solution for remote updates by allowing 8032 firmware
to temporarily “reclassify” Flash memory to
reside in data space during a remote update, then
returning Flash memory back to program space
when finished. See the VM Register (Table
78., page 143) in the PSD Module section of this
document for more details.
8032 MCU CORE PERFORMANCE ENHANCEMENTS
Before describing performance features of the
uPSD33xx, let us first look at standard 8032 architecture.
The clock source for the 8032 MCU creates
a basic unit of timing called a machine-cycle,
which is a period of 12 clocks for standard 8032
MCUs. The instruction set for traditional 8032
MCUs consists of 1, 2, and 3 byte instructions that
execute in different combinations of 1, 2, or 4 machine-cycles.
For example, there are one-byte instructions
that execute in one machine-cycle (12
clocks), one-byte instructions that execute in four
machine-cycles (48 clocks), two-byte, two-cycle
instructions (24 clocks), and so on. In addition,
standard 8032 architecture will fetch two bytes
from program memory on almost every machinecycle,
regardless if it needs them or not (dummy
fetch). This means for one-byte, one-cycle instructions,
the second byte is ignored. These one-byte,
one-cycle instructions account for half of the
8032's instructions (126 out of 255 opcodes).
There are inefficiencies due to wasted bus cycles
and idle bus times that can be eliminated.
The uPSD33xx 8032 MCU core offers increased
performance in a number of ways, while keeping
the exact same instruction set as the standard
8032 (all opcodes, the number of bytes per instruction,
and the native number a machine-cycles
per instruction are identical to the original 8032).
The first way performance is boosted is by reducing
the machine-cycle period to just 4 MCU clocks
as compared to 12 MCU clocks in a standard
8032. This shortened machine-cycle improves the
instruction rate for one-byte, one-cycle instructions
by a factor of three (Figure 7., page 18) compared
to standard 8051 architectures, and
significantly improves performance of multiple-cycle
instruction types.
The example in Figure 7 shows a continuous execution
stream of one-byte, one-cycle instructions.
The 5V uPSD33xx will yield 10 MIPS peak performance
in this case while operating at 40MHz clock
rate. In a typical application however, the effective
performance will be lower since programs do not
use only one-cycle instructions, but special techniques
are implemented in the uPSD33xx to keep
the effective MIPS rate as close as possible to the
peak MIPS rate at all times. This is accomplished
with an instruction Pre-Fetch Queue (PFQ) and a
Branch Cache (BC) as shown in Figure
8., page 18.uPSD33xx
18/231
Figure 7. Comparison of uPSD33xx with Standard 8032 Performance
Figure 8. Instruction Pre-Fetch Queue and Branch Cache
MCU Clock
Standard 8032 Fetch Byte for Instruction A Execute Instruction A
and Fetch a Second Dummy Byte
Turbo uPSD33XX Execute Instruction and
Pre-Fetch Next Instruction
4 clocks (one machine cycle)
12 clocks (one machine cycle)
1-byte, 1-Cycle Instructions
Dummy Byte is Ignored (wasted bus access)
Execute Instruction and
Pre-Fetch Next Instruction
Execute Instruction and
Pre-Fetch Next Instruction
Instruction A Instruction B Instruction C
Instruction A
Turbo uPSD33XX executes instructions A, B, and C in the same
amount of time that a standard 8032 executes only instruction A.
one machine cycle one machine cycle
AI08808
Branch 4
Code
Branch 4
Code
Branch 4
Code
Branch 4
Code
Branch 4
Code
Branch 4
Code
Previous
Branch 4
8032
Program MCU
Memory on
PSD Module
Instruction Pre-Fetch Queue (PFQ)
6 Bytes of Instruction
Instruction
Byte
Wait Stall
8
Instruction
Byte
8
Current
Branch
Address
Compare Branch
Cache
(BC)
16
AI08809
Address
16
Address
Load on Branch Address Match
Branch 3
Code
Branch 3
Code
Branch 3
Code
Branch 3
Code
Branch 3
Code
Branch 3
Code
Previous
Branch 3
Branch 2
Code
Branch 2
Code
Branch 2
Code
Branch 2
Code
Branch 2
Code
Branch 2
Code
Previous
Branch 2
Branch 1
Code
Branch 1
Code
Branch 1
Code
Branch 1
Code
Branch 1
Code
Branch 1
Code
Previous
Branch 1
Address19/231
uPSD33xx
Pre-Fetch Queue (PFQ) and Branch Cache
(BC)
The PFQ is always working to minimize the idle
bus time inherent to 8032 MCU architecture, to
eliminate wasted memory fetches, and to maximize
memory bandwidth to the MCU. The PFQ
does this by running asynchronously in relation to
the MCU, looking ahead to pre-fetch code from
program memory during any idle bus periods. Only
necessary bytes will be fetched (no dummy fetches
like standard 8032). The PFQ will queue up to
six code bytes in advance of execution, which significantly
optimizes sequential program performance.
However, when program execution
becomes non-sequential (program branch), a typical
pre-fetch queue will empty itself and reload
new code, causing the MCU to stall. The Turbo
uPSD33xx diminishes this problem by using a
Branch Cache with the PFQ. The BC is a four-way,
fully associative cache, meaning that when a program
branch occurs, it's branch destination address
is compared simultaneously with four recent
previous branch destinations stored in the BC.
Each of the four cache entries contain up to six
bytes of code related to a branch. If there is a hit
(a match), then all six code bytes of the matching
program branch are transferred immediately and
simultaneously from the BC to the PFQ, and execution
on that branch continues with minimal delay.
This greatly reduces the chance that the MCU
will stall from an empty PFQ, and improves performance
in embedded control systems where it is
quite common to branch and loop in relatively
small code localities.
By default, the PFQ and BC are enabled after
power-up or reset. The 8032 can disable the PFQ
and BC at runtime if desired by writing to a specific
SFR (BUSCON).
The memory in the PSD module operates with
variable wait states depending on the value specified
in the SFR named BUSCON. For example, a
5V uPSD33xx device operating at a 40MHz crystal
frequency requires four memory wait states (equal
to four MCU clocks). In this example, once the
PFQ has one or more bytes of code, the wait
states become transparent and a full 10 MIPS is
achieved when the program stream consists of sequential
one-byte, one machine-cycle instructions
as shown in Figure 7., page 18 (transparent because
a machine-cycle is four MCU clocks which
equals the memory pre-fetch wait time that is also
four MCU clocks). But it is also important to understand
PFQ operation on multi-cycle instructions.
PFQ Example, Multi-cycle Instructions
Let us look at a string of two-byte, two-cycle instructions
in Figure 9., page 20. There are three
instructions executed sequentially in this example,
instructions A, B, and C. Each of the time divisions
in the figure is one machine-cycle of four clocks,
and there are six phases to reference in this discussion.
Each instruction is pre-fetched into the
PFQ in advance of execution by the MCU. Prior to
Phase 1, the PFQ has pre-fetched the two instruction
bytes (A1 and A2) of instruction A. During
Phase one, both bytes are loaded into the MCU
execution unit. Also in Phase 1, the PFQ is prefetching
the first byte (B1) of instruction B from
program memory. In Phase 2, the MCU is processing
Instruction A internally while the PFQ is
pre-fetching the second byte (B2) of Instruction B.
In Phase 3, both bytes of instruction B are loaded
into the MCU execution unit and the PFQ begins
to pre-fetch bytes for the third instruction C. In
Phase 4 Instruction B is processed and the prefetching
continues, eliminating idle bus cycles and
feeding a continuous flow of operands and opcodes
to the MCU execution unit.
The uPSD33xx MCU instructions are an exact 1/3
scale of all standard 8032 instructions with regard
to number of cycles per instruction. Figure
10., page 20 shows the equivalent instruction sequence
from the example above on a standard
8032 for comparison.
Aggregate Performance
The stream of two-byte, two-cycle instructions in
Figure 9., page 20, running on a 40MHz, 5V,
uPSD33xx will yield 5 MIPs. And we saw the
stream of one-byte, one-cycle instructions in Figure
7., page 18, on the same MCU yield 10 MIPs.
Effective performance will depend on a number of
things: the MCU clock frequency; the mixture of instructions
types (bytes and cycles) in the application;
the amount of time an empty PFQ stalls the
MCU (mix of instruction types and misses on
Branch Cache); and the operating voltage. A 5V
uPSD33xx device operates with four memory wait
states, but a 3.3V device operates with five memory
wait states yielding 8 MIPS peak compared to
10 MIPs peak for 5V device. The same number of
wait states will apply to both program fetches and
to data READ/WRITEs unless otherwise specified
in the SFR named BUSCON.
In general, a 3X aggregate performance increase
is expected over any standard 8032 application
running at the same clock frequency.uPSD33xx
20/231
Figure 9. PFQ Operation on Multi-cycle Instructions
Figure 10. uPSD33xx Multi-cycle Instructions Compared to Standard 8032
Inst A, Byte 1
Three 2-byte, 2-cycle Instructions on uPSD33XX
PFQ
MCU
Execution
Inst A, Byte 2 Inst B, Byte 1 Inst B, Byte 2 Inst C, Byte 1 Inst C, Byte 2
Previous Instruction A1 A2 Process A B1 B2 Process B C1 C2
AI08810
Process C
Continue to Pre-Fetch
Next Inst
4-clock
Macine Cycle
Instruction A Instruction B Instruction C
Pre-Fetch Inst A Pre-Fetch Inst B Pre-Fetch Inst C
Phase 1 Phase 2 Phase 3 Phase 4 Phase 6 Phase 5
A1 A2 Inst A B1 B2 Inst B C1 C2 Inst C
Three 2-byte, 2-cycle Instructions, uPSD33XX vs. Standard 8032
uPSD33XX
Std 8032
72 Clocks (12 clocks per cycle)
24 Clocks Total (4 clocks per cycle)
Byte 1 Byte 2 Process Inst A Byte 1 Byte 2 Process Inst B Byte 1 Byte 2 Process Inst C
AI08811
1 Cycle
1 Cycle21/231
uPSD33xx
MCU MODULE DISCRIPTION
This section provides a detail description of the
MCU Module system functions and peripherals, including:
■ 8032 MCU Registers
■ Special Function Registers
■ 8032 Addressing Modes
■ uPSD33xx Instruction Set Summary
■ Dual Data Pointers
■ Debug Unit
■ Interrupt System
■ MCU Clock Generation
■ Power Saving Modes
■ Oscillator and External Components
■ I/O Ports
■ MCU Bus Interface
■ Supervisory Functions
■ Standard 8032 Timer/Counters
■ Serial UART Interfaces
■ IrDA Interface
■ I
2C Interface
■ SPI Interface
■ Analog to Digital Converter
■ Programmable Counter Array (PCA)
Note: A full description of the 8032 instruction set
may be found in the uPSD33xx Programmers
Guide.
8032 MCU REGISTERS
The uPSD33xx has the following 8032 MCU core
registers, also shown in Figure 11.
Figure 11. 8032 MCU Registers
Stack Pointer (SP)
The SP is an 8-bit register which holds the current
location of the top of the stack. It is incremented
before a value is pushed onto the stack, and decremented
after a value is popped off the stack. The
SP is initialized to 07h after reset. This causes the
stack to begin at location 08h (top of stack). To
avoid overlapping conflicts, the user must initialize
the top of the stack to 20h if all four banks of registers
R0 - R7 are used, and the user must initialize
the top of stack to 30h if all of the 8032 bit memory
locations are used.
Data Pointer (DPTR)
DPTR is a 16-bit register consisting of two 8-bit
registers, DPL and DPH. The DPTR Register is
used as a base register to create an address for indirect
jumps, table look-up operations, and for external
data transfers (XDATA). When not used for
addressing, the DPTR Register can be used as a
general purpose 16-bit data register.
Very frequently, the DPTR Register is used to access
XDATA using the External Direct addressing
mode. The uPSD33xx has a special set of SFR
registers (DPTC, DPTM) to control a secondary
DPTR Register to speed memory-to-memory
XDATA transfers. Having dual DPTR Registers allows
rapid switching between source and destination
addresses (see details in DUAL DATA
POINTERS, page 37).
Program Counter (PC)
The PC is a 16-bit register consisting of two 8-bit
registers, PCL and PCH. This counter indicates
the address of the next instruction in program
memory to be fetched and executed. A reset forces
the PC to location 0000h, which is where the reset
jump vector is stored.
Accumulator (ACC)
This is an 8-bit general purpose register which
holds a source operand and receives the result of
arithmetic operations. The ACC Register can also
be the source or destination of logic and data
movement operations. For MUL and DIV instructions,
ACC is combined with the B Register to hold
16-bit operands. The ACC is referred to as “A” in
the MCU instruction set.
B Register (B)
The B Register is a general purpose 8-bit register
for temporary data storage and also used as a 16-
bit register when concatenated with the ACC Register
for use with MUL and DIV instructions.
AI06636
Accumulator
B Register
Stack Pointer
Program Counter
Program Status Word
General Purpose
Register (Bank0-3)
Data Pointer Register
PCH
DPTR(DPH)
A
B
SP
PCL
PSW
R0-R7
DPTR(DPL)uPSD33xx
22/231
General Purpose Registers (R0 - R7)
There are four banks of eight general purpose 8-
bit registers (R0 - R7), but only one bank of eight
registers is active at any given time depending on
the setting in the PSW word (described next). R0 -
R7 are generally used to assist in manipulating
values and moving data from one memory location
to another. These register banks physically reside
in the first 32 locations of 8032 internal DATA23/231
uPSD33xx
SPECIAL FUNCTION REGISTERS (SFR)
A group of registers designated as Special Function
Register (SFR) is shown in Table 5., page 24.
SFRs control the operating modes of the MCU
core and also control the peripheral interfaces and
I/O pins on the MCU Module. The SFRs can be accessed
only by using the Direct Addressing method
within the address range from 80h to FFh of
internal 8032 SRAM. Sixteen addresses in SFR
address space are both byte- and bit-addressable.
The bit-addressable SFRs are noted in Table 5.
86 of a possible 128 SFR addresses are occupied.
The remaining unoccupied SFR addresses (designated
as “RESERVED” in Table 5) should not be
written. Reading unoccupied locations will return
an undefined value.
Note: There is a separate set of control registers
for the PSD Module, designated as csiop, and they
are described in the PSD MODULE, page 133.
The I/O pins, PLD, and other functions on the PSD
Module are NOT controlled by SFRs.
SFRs are categorized as follows:
■ MCU core registers:
IP, A, B, PSW, SP, DPTL, DPTH, DPTC,
DPTM
■ MCU Module I/O Port registers:
P1, P3, P4, P1SFS0, P1SFS1, P3SFS,
P4SFS0, P4SFS1
■ Standard 8032 Timer registers
TCON, TMOD, T2CON, TH0, TH1, TH2, TL0,
TL1, TL2, RCAP2L, RCAP2H
■ Standard Serial Interfaces (UART)
SCON0, SBUF0, SCON1, SBUF1
■ Power, clock, and bus timing registers
PCON, CCON0, BUSCON
■ Hardware watchdog timer registers
WDKEY, WDRST
■ Interrupt system registers
IP, IPA, IE, IEA
■ Prog. Counter Array (PCA) control
registers
PCACL0, PCACH0, PCACON0, PCASTA,
PCACL1, PCACH1, PCACON1, CCON2,
CCON3
■ PCA capture/compare and PWM registers
CAPCOML0, CAPCOMH0, TCMMODE0,
CAPCOML1, CAPCOMH1, TCMMODE2,
CAPCOML2, CAPCOMH2, TCMMODE2,
CAPCOML3, CAPCOMH3, TCMMODE3,
CAPCOML4, CAPCOMH4, TCMMODE4,
CAPCOML5, CAPCOMH5, TCMMODE5,
PWMF0, PMWF1
■ SPI interface registers
SPICLKD, SPISTAT, SPITDR, SPIRDR,
SPICON0, SPICON1
■ I
2C interface registers
S1SETUP, S1CON, S1STA, S1DAT, S1ADR
■ Analog to Digital Converter registers
ACON, ADCPS, ADAT0, ADAT1
■ IrDA interface register
IRDACONuPSD33xx
24/231
Table 5. SFR Memory Map with Direct Address and Reset Value
SFR
Addr
(hex)
SFR
Name
Bit Name and Reset
Value
(hex)
Reg.
Descr.
7 6 5 4 3 2 10 with Link
80 RESERVED
81 SP SP[7:0] 07
Stack
Pointer
(SP), page
21
82 DPL DPL[7:0] 00 Data
Pointer
(DPTR), p
age 21
83 DPH DPH[7:0] 00
84 RESERVED
85 DPTC – AT – – – DPSEL[2:0] 00
Table
13., page
37
86 DPTM – – – – MD1[1:0] MD0[1:0] 00
Table
14., page
38
87 PCON SMOD0 SMOD1 – POR RCLK1 TCLK1 PD IDLE 00
Table
24., page
50
88(1) TCON TF1
<8Fh>
TR1
<8Eh>
TF0
<8Dh>
TR0
<8Ch>
IE1
<8Bh>
IT1
<8Ah>
IE0
<89h>
IT0
<88h> 00
Table
39., page
70
89 TMOD GATE C/T M1 M0 GATE C/T M1 M0 00
Table
40., page
72
8A TL0 TL0[7:0] 00
Standard
Timer
SFRs, pag
e 69
8B TL1 TL1[7:0] 00
8C TH0 TH0[7:0] 00
8D TH1 TH1[7:0] 00
8E P1SFS0 P1SFS0[7:0] 00
Table
29., page
60
8F P1SFS1 P1SFS1[7:0] 00
Table
30., page
60
90(1) P1 P1.7
<97h>
P1.6
<96h>
P1.5
<95h>
P1.4
<94h>
P1.3
<93h>
P1.2
<92h>
P1.1
<91h>
P1.0
<90h> FF
Table
25., page
57
91 P3SFS P3SFS[7:0] 00
Table
28., page
60
92 P4SFS0 P4SFS0[7:0] 00
Table
32., page
61
93 P4SFS1 P4SFS1[7:0] 00
Table
33., page
6125/231
uPSD33xx
94 ADCPS – – – – ADCCE ADCPS[2:0] 00
Table
64., page
122
95 ADAT0 ADATA[7:0] 00
Table
65., page
122
96 ADAT1 – – – – – – ADATA[9:8] 00
Table
66., page
122
97 ACON AINTF AINTEN ADEN ADS[2:0] ADST ADSF 00
Table
63., page
121
98(1) SCON0 SM0
<9Fh>
SM1
<9Eh>
SM2
<9Dh>
REN
<9Ch>
TB8
<9Bh>
RB8
<9Ah>
TI
<99h>
RI
<9h8> 00
Table
45., page
82
99 SBUF0 SBUF0[7:0] 00
Figure
25., page
79
9A RESERVED
9B RESERVED
9C RESERVED
9D BUSCON EPFQ EBC WRW1 WRW0 RDW1 RDW0 CW1 CW0 EB
Table
35., page
63
9E RESERVED
9F RESERVED
A0 RESERVED
A1 RESERVED
A2 PCACL0 PCACL0[7:0] 00
Table
67., page
124
A3 PCACH0 PCACH0[7:0] 00
Table
67., page
124
A4 PCACON0 EN_ALL EN_PCA EOVF1 PCA_IDL – – CLK_SEL[1:0] 00
Table
70., page
129
A5 PCASTA OVF1 INTF5 INTF4 INTF3 OVF0 INTF2 INTF1 INTF0 00
Table
72., page
131
A6 WDTRST WDTRST[7:0] 00
Table
38., page
68
A7 IEA EADC ESPI EPCA ES1 – – EI2C – 00
Table
18., page
44
SFR
Addr
(hex)
SFR
Name
Bit Name and Reset
Value
(hex)
Reg.
Descr.
7 6 5 4 3 2 10 with LinkuPSD33xx
26/231
A8(1) IE EA
– ET2
ES0
ET1
EX1
ET0
EX0
00
Table
17., page
43
A9 TCMMODE
0 EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM[1:0] 00
Table
73., page
132
AA TCMMODE
1 EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM[1:0] 00
AB TCMMODE
2 EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM[1:0] 00
AC CAPCOML
0 CAPCOML0[7:0] 00 Table
67., page
124 AD CAPCOMH
0 CAPCOMH0[7:0] 00
AE WDTKEY WDTKEY[7:0] 55
Table
37., page
68
AF CAPCOML
1 CAPCOML1[7:0] 00
Table
67., page
124
B0(1) P3 P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
FF
Table
26., page
58
B1 CAPCOMH
1 CAPCOMH1[7:0] 00
Table
67., page
124
B2 CAPCOML
2 CAPCOML2[7:0] 00
B3 CAPCOMH
2 CAPCOMH2[7:0] 00
B4 PWMF0 PWMF0[7:0] 00
B5 RESERVED
B6 RESERVED
B7 IPA PADC PSPI PPCA PS1 – – PI2C – 00
Table
20., page
45
B8(1) IP – – PT2
PS0
PT1
PX1
PT0
PX0
00
Table
19., page
44
B9 RESERVED
BA PCACL1 PCACL1[7:0] 00 Table
67., page BB PCACH1 PCACH1[7:0] 00 124
BC
Table
2671 page
12027/231
uPSD33xx
BD TCMMODE
3 EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM[1:0] 00
Table
73., page
132
BE TCMMODE
4 EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM[1:0] 00
BF TCMMODE
5 EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM[1:0] 00
C0(1) P4 P4.7
P4.6
P4.5
P4.4
P4.3
P4.2
P4.1
P4.0
FF
Table
27., page
58
C1 CAPCOML
3 CAPCOML3[7:0] 00
Table
67., page
124
C2 CAPCOMH
3 CAPCOMH3[7:0] 00
C3 CAPCOML
4 CAPCOML4[7:0] 00
C4 CAPCOMH
4 CAPCOMH4[7:0] 00
C5 CAPCOML
5 CAPCOML5[7:0] 00
C6 CAPCOMH
5 CAPCOMH5[7:0] 00
C7 PWMF1 PWMF1[7:0] 00
C8(1) T2CON TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/
RL2
00
Table
41., page
75
C9 RESERVED
CA RCAP2L RCAP2L[7:0] 00
Standard
Timer
SFRs, pag
e 69
CB RCAP2H RCAP2H[7:0] 00
CC TL2 TL2[7:0] 00
CD TH2 TH2[7:0] 00
CE IRDACON – IRDA_EN BIT_PULS CDIV4 CDIV3 CDIV2 CDIV1 CDIV0 0F
Table
48., page
93
D0(1) PSW CY
AC
F0
RS[1:0]
OV
– P
00
Program
Status
Word
(PSW), pa
ge 22
D1 RESERVED
D2 SPICLKD SPICLKD[5:0] – – 04
Table
61., page
118
D3 SPISTAT – – – BUSY TEISF RORISF TISF RISF 02
Table
62., page
119
SFR
Addr
(hex)
SFR
Name
Bit Name and Reset
Value
(hex)
Reg.
Descr.
7 6 5 4 3 2 10 with LinkuPSD33xx
28/231
D4 SPITDR SPITDR[7:0] 00 Table
62., page
D5 SPIRDR SPIRDR[7:0] 00 119
D6 SPICON0 – TE RE SPIEN SSEL FLSB SPO – 00
Table
59., page
117
D7 SPICON1 – – – – TEIE RORIE TIE RIE 00
Table
60., page
118
D8(1) SCON1 SM0
SM2
REN
TB8
RB8
TI
RI
00
Table
46., page
83
D9 SBUF1 SBUF1[7:0] 00
Figure
25., page
79
DA RESERVED
DB S1SETUP SS_EN SMPL_SET[6:0] 00
Table
55., page
105
DC S1CON CR2 EN1 STA STO ADDR AA CR1 CR0 00
Table
50., page
100
DD S1STA GC STOP INTR TX_MD B_BUSY B_LOST ACK_R SLV 00
Table
52., page
103
DE S1DAT S1DAT[7:0] 00
Table
53., page
104
DF S1ADR S1ADR[7:0] 00
Table
54., page
104
E0(1) A A[7:0]
00
Accumulat
or
(ACC), pa
ge 21
E1
to
EF
RESERVED
F0(1) B B[7:0]
00
B Register
(B), page
21
F1 RESERVED
F2 RESERVED
F3 RESERVED
F4 RESERVED
F5 RESERVED
F6 RESERVED
SFR
Addr
(hex)
SFR
Name
Bit Name and Reset
Value
(hex)
Reg.
Descr.
7 6 5 4 3 2 10 with Link29/231
uPSD33xx
Note: 1. This SFR can be addressed by individual bits (Bit Address mode) or addressed by the entire byte (Direct Address mode).
F7 RESERVED
F8 RESERVED
F9 CCON0 – – – DBGCE CPU_AR CPUPS[2:0] 10
Table
21., page
47
FA RESERVED
FB CCON2 – – – PCA0CE PCA0PS[3:0] 10
Table
68., page
125
FC CCON3 – – – PCA1CE PCA1PS[3:0] 10
Table
69., page
125
FD RESERVED
FE RESERVED
FF RESERVED
SFR
Addr
(hex)
SFR
Name
Bit Name and Reset
Value
(hex)
Reg.
Descr.
7 6 5 4 3 2 10 with LinkuPSD33xx
30/231
8032 ADDRESSING MODES
The 8032 MCU uses 11 different addressing
modes listed below:
■ Register
■ Direct
■ Register Indirect
■ Immediate
■ External Direct
■ External Indirect
■ Indexed
■ Relative
■ Absolute
■ Long
■ Bit
Register Addressing
This mode uses the contents of one of the registers
R0 - R7 (selected by the last three bits in the
instruction opcode) as the operand source or destination.
This mode is very efficient since an additional
instruction byte is not needed to identify the
operand. For example:
Direct Addressing
This mode uses an 8-bit address, which is contained
in the second byte of the instruction, to directly
address an operand which resides in either
8032 DATA SRAM (internal address range 00h-
07Fh) or resides in 8032 SFR (internal address
range 80h-FFh). This mode is quite fast since the
range limit is 256 bytes of internal 8032 SRAM.
For example:
Register Indirect Addressing
This mode uses an 8-bit address contained in either
Register R0 or R1 to indirectly address an operand
which resides in 8032 IDATA SRAM
(internal address range 80h-FFh). Although 8032
SFR registers also occupy the same physical address
range as IDATA, SFRs will not be accessed
by Register Indirect mode. SFRs may only be accesses
using Direct address mode. For example:
Immediate Addressing
This mode uses 8-bits of data (a constant) contained
in the second byte of the instruction, and
stores it into the memory location or register indicated
by the first byte of the instruction. Thus, the
data is immediately available within the instruction.
This mode is commonly used to initialize registers
and SFRs or to perform mask operations.
There is also a 16-bit version of this mode for loading
the DPTR Register. In this case, the two bytes
following the instruction byte contain the 16-bit value.
For example:
External Direct Addressing
This mode will access external memory (XDATA)
by using the 16-bit address stored in the DPTR
Register. There are only two instructions using this
mode and both use the accumulator to either receive
a byte from external memory addressed by
DPTR or to send a byte from the accumulator to
the address in DPTR. The uPSD33xx has a special
feature to alternate the contents (source and
destination) of DPTR rapidly to implement very efficient
memory-to-memory transfers. For example:
Note: See details in DUAL DATA
POINTERS, page 37.
External Indirect Addressing
This mode will access external memory (XDATA)
by using the 8-bit address stored in either Register
R0 or R1. This is the fastest way to access XDATA
(least bus cycles), but because only 8-bits are
available for address, this mode limits XDATA to a
size of only 256 bytes (the traditional Port 2 of the
8032 MCU is not available in the uPSD33xx, so it
is not possible to write the upper address byte).
This mode is not supported by uPSD33xx.
For example:
MOV A, R7 ; Move contents of R7 to accumulator
MOV A, 40h ; Move contents of DATA SRAM
; at location 40h into the accumulator
MOV A, @R0 ; Move into the accumulator the
; contents of IDATA SRAM that is
; pointed to by the address
; contained in R0.
MOV A, 40# ; Move the constant, 40h, into
; the accumulator
MOV DPTR, 1234# ; Move the constant, 1234h, into
; DPTR
MOVX A, @DPTR ; Move contents of accumulator to
; XDATA at address contained in
; DPTR
MOVX @DPTR, A ; Move XDATA to accumulator
MOVX @R0,A ; Move into the accumulator the
; XDATA that is pointed to by
; the address contained in R0.31/231
uPSD33xx
Indexed Addressing
This mode is used for the MOVC instruction which
allows the 8032 to read a constant from program
memory (not data memory). MOVC is often used
to read look-up tables that are embedded in program
memory. The final address produced by this
mode is the result of adding either the 16-bit PC or
DPTR value to the contents of the accumulator.
The value in the accumulator is referred to as an
index. The data fetched from the final location in
program memory is stored into the accumulator,
overwriting the index value that was previously
stored there. For example:
Relative Addressing
This mode will add the two’s-compliment number
stored in the second byte of the instruction to the
program counter for short jumps within +128 or –
127 addresses relative to the program counter.
This is commonly used for looping and is very efficient
since no additional bus cycle is needed to
fetch the jump destination address. For example:
Absolute Addressing
This mode will append the 5 high-order bits of the
address of the next instruction to the 11 low-order
bits of an ACALL or AJUMP instruction to produce
a 16-bit jump address. The jump will be within the
same 2K byte page of program memory as the first
byte of the following instruction. For example:
Long Addressing
This mode will use the 16-bits contained in the two
bytes following the instruction byte as a jump destination
address for LCALL and LJMP instructions.
For example:
Bit Addressing
This mode allows setting or clearing an individual
bit without disturbing the other bits within an 8-bit
value of internal SRAM. Bit Addressing is only
available for certain locations in 8032 DATA and
SFR memory. Valid locations are DATA addresses
20h - 2Fh and for SFR addresses whose base
address ends with 0h or 8h. (Example: The SFR,
IE, has a base address of A8h, so each of the eight
bits in IE can be addressed individually at address
A8h, A9h, ...up to AFh.) For example:
MOVC A, @A+DPTR; Move code byte relative to
; DPTR into accumulator
MOVC A, @A+PC ; Move code byte relative to PC
; into accumulator
SJMP 34h ; Jump 34h bytes ahead (in program
; memory) of the address at which
; the SJMP instruction is stored. If
; SJMP is at 1000h, program
; execution jumps to 1034h.
AJMP 0500h ; If next instruction is located at
; address 4000h, the resulting jump
; will be made to 4500h.
LJMP 0500h ; Unconditionally jump to address
; 0500h in program memory
SETB AFh ; Set the individual EA bit (Enable All
; Interrupts) inside the SFR Register,
; IE. uPSD33xx
32/231
uPSD33xx INSTRUCTION SET SUMMARY
Tables 6 through 11 list all of the instructions supported
by the uPSD33xx, including the number of
bytes and number of machine cycles required to
implement each instruction. This is the standard
8051 instruction set.
The meaning of “machine cycles” is how many
8032 MCU core machine cycles are required to
execute the instruction. The “native” duration of all
machine cycles is set by the memory wait state
settings in the SFR, BUSCON, and the MCU clock
divider selections in the SFR, CCON0 (i.e. a machine
cycle is typically set to 4 MCU clocks for a 5V
uPSD33xx). However, an individual machine cycle
may grow in duration when either of two things
happen:
1. a stall is imposed while loading the 8032 PreFetch
Queue (PFQ); or
2. the occurrence of a cache miss in the Branch
Cache (BC) during a branch in program
execution flow.
See 8032 MCU CORE PERFORMANCE
ENHANCEMENTS, page 17 or more details.
But generally speaking, during typical program execution,
the PFQ is not empty and the BC has no
misses, producing very good performance without
extending the duration of any machine cycles.
The uPSD33xx Programmers Guide describes
each instruction operation in detail.
Table 6. Arithmetic Instruction Set
Note: 1. All mnemonics copyrighted ©Intel Corporation 1980.
Mnemonic(1)
and Use Description Length/Cycles
ADD A, Rn Add register to ACC 1 byte/1 cycle
ADD A, Direct Add direct byte to ACC 2 byte/1 cycle
ADD A, @Ri Add indirect SRAM to ACC 1 byte/1 cycle
ADD A, #data Add immediate data to ACC 2 byte/1 cycle
ADDC A, Rn Add register to ACC with carry 1 byte/1 cycle
ADDC A, direct Add direct byte to ACC with carry 2 byte/1 cycle
ADDC A, @Ri Add indirect SRAM to ACC with carry 1 byte/1 cycle
ADDC A, #data Add immediate data to ACC with carry 2 byte/1 cycle
SUBB A, Rn Subtract register from ACC with borrow 1 byte/1 cycle
SUBB A, direct Subtract direct byte from ACC with borrow 2 byte/1 cycle
SUBB A, @Ri Subtract indirect SRAM from ACC with borrow 1 byte/1 cycle
SUBB A, #data Subtract immediate data from ACC with borrow 2 byte/1 cycle
INC A Increment A 1 byte/1 cycle
INC Rn Increment register 1 byte/1 cycle
INC direct Increment direct byte 2 byte/1 cycle
INC @Ri Increment indirect SRAM 1 byte/1 cycle
DEC A Decrement ACC 1 byte/1 cycle
DEC Rn Decrement register 1 byte/1 cycle
DEC direct Decrement direct byte 2 byte/1 cycle
DEC @Ri Decrement indirect SRAM 1 byte/1 cycle
INC DPTR Increment Data Pointer 1 byte/2 cycle
MUL AB Multiply ACC and B 1 byte/4 cycle
DIV AB Divide ACC by B 1 byte/4 cycle
DA A Decimal adjust ACC 1 byte/1 cycle33/231
uPSD33xx
Table 7. Logical Instruction Set
Note: 1. All mnemonics copyrighted ©Intel Corporation 1980.
Mnemonic(1)
and Use Description Length/Cycles
ANL A, Rn AND register to ACC 1 byte/1 cycle
ANL A, direct AND direct byte to ACC 2 byte/1 cycle
ANL A, @Ri AND indirect SRAM to ACC 1 byte/1 cycle
ANL A, #data AND immediate data to ACC 2 byte/1 cycle
ANL direct, A AND ACC to direct byte 2 byte/1 cycle
ANL direct, #data AND immediate data to direct byte 3 byte/2 cycle
ORL A, Rn OR register to ACC 1 byte/1 cycle
ORL A, direct OR direct byte to ACC 2 byte/1 cycle
ORL A, @Ri OR indirect SRAM to ACC 1 byte/1 cycle
ORL A, #data OR immediate data to ACC 2 byte/1 cycle
ORL direct, A OR ACC to direct byte 2 byte/1 cycle
ORL direct, #data OR immediate data to direct byte 3 byte/2 cycle
SWAP A Swap nibbles within the ACC 1 byte/1 cycle
XRL A, Rn Exclusive-OR register to ACC 1 byte/1 cycle
XRL A, direct Exclusive-OR direct byte to ACC 2 byte/1 cycle
XRL A, @Ri Exclusive-OR indirect SRAM to ACC 1 byte/1 cycle
XRL A, #data Exclusive-OR immediate data to ACC 2 byte/1 cycle
XRL direct, A Exclusive-OR ACC to direct byte 2 byte/1 cycle
XRL direct, #data Exclusive-OR immediate data to direct byte 3 byte/2 cycle
CLR A Clear ACC 1 byte/1 cycle
CPL A Compliment ACC 1 byte/1 cycle
RL A Rotate ACC left 1 byte/1 cycle
RLC A Rotate ACC left through the carry 1 byte/1 cycle
RR A Rotate ACC right 1 byte/1 cycle
RRC A Rotate ACC right through the carry 1 byte/1 cycleuPSD33xx
34/231
Table 8. Data Transfer Instruction Set
Note: 1. All mnemonics copyrighted ©Intel Corporation 1980.
Mnemonic(1)
and Use Description Length/Cycles
MOV A, Rn Move register to ACC 1 byte/1 cycle
MOV A, direct Move direct byte to ACC 2 byte/1 cycle
MOV A, @Ri Move indirect SRAM to ACC 1 byte/1 cycle
MOV A, #data Move immediate data to ACC 2 byte/1 cycle
MOV Rn, A Move ACC to register 1 byte/1 cycle
MOV Rn, direct Move direct byte to register 2 byte/2 cycle
MOV Rn, #data Move immediate data to register 2 byte/1 cycle
MOV direct, A Move ACC to direct byte 2 byte/1 cycle
MOV direct, Rn Move register to direct byte 2 byte/2 cycle
MOV direct, direct Move direct byte to direct 3 byte/2 cycle
MOV direct, @Ri Move indirect SRAM to direct byte 2 byte/2 cycle
MOV direct, #data Move immediate data to direct byte 3 byte/2 cycle
MOV @Ri, A Move ACC to indirect SRAM 1 byte/1 cycle
MOV @Ri, direct Move direct byte to indirect SRAM 2 byte/2 cycle
MOV @Ri, #data Move immediate data to indirect SRAM 2 byte/1 cycle
MOV DPTR, #data16 Load Data Pointer with 16-bit constant 3 byte/2 cycle
MOVC A, @A+DPTR Move code byte relative to DPTR to ACC 1 byte/2 cycle
MOVC A, @A+PC Move code byte relative to PC to ACC 1 byte/2 cycle
MOVX A, @Ri Move XDATA (8-bit addr) to ACC 1 byte/2 cycle
MOVX A, @DPTR Move XDATA (16-bit addr) to ACC 1 byte/2 cycle
MOVX @Ri, A Move ACC to XDATA (8-bit addr) 1 byte/2 cycle
MOVX @DPTR, A Move ACC to XDATA (16-bit addr) 1 byte/2 cycle
PUSH direct Push direct byte onto stack 2 byte/2 cycle
POP direct Pop direct byte from stack 2 byte/2 cycle
XCH A, Rn Exchange register with ACC 1 byte/1 cycle
XCH A, direct Exchange direct byte with ACC 2 byte/1 cycle
XCH A, @Ri Exchange indirect SRAM with ACC 1 byte/1 cycle
XCHD A, @Ri Exchange low-order digit indirect SRAM with ACC 1 byte/1 cycle35/231
uPSD33xx
Table 9. Boolean Variable Manipulation Instruction Set
Note: 1. All mnemonics copyrighted ©Intel Corporation 1980.
Mnemonic(1)
and Use Description Length/Cycles
CLR C Clear carry 1 byte/1 cycle
CLR bit Clear direct bit 2 byte/1 cycle
SETB C Set carry 1 byte/1 cycle
SETB bit Set direct bit 2 byte/1 cycle
CPL C Compliment carry 1 byte/1 cycle
CPL bit Compliment direct bit 2 byte/1 cycle
ANL C, bit AND direct bit to carry 2 byte/2 cycle
ANL C, /bit AND compliment of direct bit to carry 2 byte/2 cycle
ORL C, bit OR direct bit to carry 2 byte/2 cycle
ORL C, /bit OR compliment of direct bit to carry 2 byte/2 cycle
MOV C, bit Move direct bit to carry 2 byte/1 cycle
MOV bit, C Move carry to direct bit 2 byte/2 cycle
JC rel Jump if carry is set 2 byte/2 cycle
JNC rel Jump if carry is not set 2 byte/2 cycle
JB rel Jump if direct bit is set 3 byte/2 cycle
JNB rel Jump if direct bit is not set 3 byte/2 cycle
JBC bit, rel Jump if direct bit is set and clear bit 3 byte/2 cycleuPSD33xx
36/231
Table 10. Program Branching Instruction Set
Note: 1. All mnemonics copyrighted ©Intel Corporation 1980.
Table 11. Miscellaneous Instruction Set
Note: 1. All mnemonics copyrighted ©Intel Corporation 1980.
Table 12. Notes on Instruction Set and Addressing Modes
Mnemonic(1)
and Use Description Length/Cycles
ACALL addr11 Absolute subroutine call 2 byte/2 cycle
LCALL addr16 Long subroutine call 3 byte/2 cycle
RET Return from subroutine 1 byte/2 cycle
RETI Return from interrupt 1 byte/2 cycle
AJMP addr11 Absolute jump 2 byte/2 cycle
LJMP addr16 Long jump 3 byte/2 cycle
SJMP rel Short jump (relative addr) 2 byte/2 cycle
JMP @A+DPTR Jump indirect relative to the DPTR 1 byte/2 cycle
JZ rel Jump if ACC is zero 2 byte/2 cycle
JNZ rel Jump if ACC is not zero 2 byte/2 cycle
CJNE A, direct, rel Compare direct byte to ACC, jump if not equal 3 byte/2 cycle
CJNE A, #data, rel Compare immediate to ACC, jump if not equal 3 byte/2 cycle
CJNE Rn, #data, rel Compare immediate to register, jump if not equal 3 byte/2 cycle
CJNE @Ri, #data, rel Compare immediate to indirect, jump if not equal 3 byte/2 cycle
DJNZ Rn, rel Decrement register and jump if not zero 2 byte/2 cycle
DJNZ direct, rel Decrement direct byte and jump if not zero 3 byte/2 cycle
Mnemonic(1)
and Use Description Length/Cycles
NOP No Operation 1 byte/1 cycle
Rn Register R0 - R7 of the currently selected register bank.
direct 8-bit address for internal 8032 DATA SRAM (locations 00h - 7Fh) or SFR registers (locations 80h - FFh).
@Ri 8-bit internal 8032 SRAM (locations 00h - FFh) addressed indirectly through contents of R0 or R1.
#data 8-bit constant included within the instruction.
#data16 16-bit constant included within the instruction.
addr16 16-bit destination address used by LCALL and LJMP.
addr11 11-bit destination address used by ACALL and AJMP.
rel Signed (two-s compliment) 8-bit offset byte.
bit Direct addressed bit in internal 8032 DATA SRAM (locations 20h to 2Fh) or in SFR registers (88h, 90h,
98h, A8h, B0, B8h, C0h, C8h, D0h, D8h, E0h, F0h).37/231
uPSD33xx
DUAL DATA POINTERS
XDATA is accessed by the External Direct addressing
mode, which uses a 16-bit address
stored in the DPTR Register. Traditional 8032 architecture
has only one DPTR Register. This is a
burden when transferring data between two XDATA
locations because it requires heavy use of the
working registers to manipulate the source and
destination pointers.
However, the uPSD33xx has two data pointers,
one for storing a source address and the other for
storing a destination address. These pointers can
be configured to automatically increment or decrement
after each data transfer, further reducing the
burden on the 8032 and making this kind of data
movement very efficient.
Data Pointer Control Register, DPTC (85h)
By default, the DPTR Register of the uPSD33xx
will behave no different than in a standard 8032
MCU. The DPSEL0 Bit of SFR register DPTC
shown in Table 13, selects which one of the two
“background” data pointer registers (DPTR0 or
DPTR1) will function as the traditional DPTR Register
at any given time. After reset, the DPSEL0 Bit
is cleared, enabling DPTR0 to function as the DPTR,
and firmware may access DPTR0 by reading
or writing the traditional DPTR Register at SFR addresses
82h and 83h. When the DPSEL0 bit is set,
then the DPTR1 Register functions as DPTR, and
firmware may now access DPTR1 through SFR
registers at 82h and 83h. The pointer which is not
selected by the DPSEL0 bit remains in the background
and is not accessible by the 8032. If the
DPSEL0 bit is never set, then the uPSD33xx will
behave like a traditional 8032 having only one
DPTR Register.
To further speed XDATA to XDATA transfers, the
SFR bit, AT, may be set to automatically toggle the
two data pointers, DPTR0 and DPTR1, each time
the standard DPTR Register is accessed by a
MOVX instruction. This eliminates the need for
firmware to manually manipulate the DPSEL0 bit
between each data transfer.
Detailed description for the SFR register DPTC is
shown in Table 13.
Table 13. DPTC: Data Pointer Control Register (SFR 85h, reset value 00h)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
– AT – – – – – DPSEL0
Details
Bit Symbol R/W Definition
7 – – Reserved
6 AT R,W 0 = Manually Select Data Pointer
1 = Auto Toggle between DPTR0 and DPTR1
5-1 – – Reserved
0 DPSE0 R,W 0 = DPTR0 Selected for use as DPTR
1 = DPTR1 Selected for use as DPTRuPSD33xx
38/231
Data Pointer Mode Register, DPTM (86h)
The two “background” data pointers, DPTR0 and
DPTR1, can be configured to automatically increment,
decrement, or stay the same after a MOVX
instruction accesses the DPTR Register. Only the
currently selected pointer will be affected by the increment
or decrement. This feature is controlled
by the DPTM Register defined in Table 14.
The automatic increment or decrement function is
effective only for the MOVX instruction, and not
MOVC or any other instruction that uses the DTPR
Register.
Firmware Example. The 8051 assembly code illustrated
in Table 15 shows how to transfer a block
of data bytes from one XDATA address region to
another XDATA address region. Auto-address incrementing
and auto-pointer toggling will be used.
Table 14. DPTM: Data Pointer Mode Register (SFR 86h, reset value 00h)
Table 15. 8051 Assembly Code Example
Note: 1. The code loop where the data transfer takes place is only 3 lines of code.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
– – – – MD11 MD10 MD01 MD00
Details
Bit Symbol R/W Definition
7-4 – – Reserved
3-2 MD[11:10] R,W
DPTR1 Mode Bits
00: DPTR1 No Change
01: Reserved
10: Auto Increment
11: Auto Decrement
1-0 MD[01:00] R,W
DPTR0 Mode Bits
00: DPTR0 No Change
01: Reserved
10: Auto Increment
11: Auto Decrement
MOV R7, #COUNT ; initialize size of data block to transfer
MOV DPTR, #SOURCE_ADDR ; load XDATA source address base into DPTR0
MOV 85h, #01h ; load DPTC to access DPTR1 pointer
MOV DPTR, #DEST_ADDR ; load XDATA destination address base into DPTR1
MOV 85h, #40h ; load DPTC to access DPTR0 pointer and auto toggle
MOV 86h, #0Ah ; load DPTM to auto-increment both pointers
LOOP: MOVX(1) A, @DPTR ; load XDATA byte from source into ACC.
; after load completes, DPTR0 increments and DPTR
; switches DPTR1
MOVX(1) @DPTR, A ; store XDATA byte from ACC to destination.
; after store completes, DPTR1 increments and DPTR
; switches to DPTR0
DJNZ(1) R7, LOOP ; continue until done
MOV 86h, #00 ; disable auto-increment
MOV 85h, #00 ; disable auto-toggle, now back to single DPTR mode39/231
uPSD33xx
DEBUG UNIT
The 8032 MCU Module supports run-time debugging
through the JTAG interface. This same JTAG
interface is also used for In-System Programming
(ISP) and the physical connections are described
in the PSD Module section, JTAG ISP and JTAG
Debug, page 195.
Debugging with a serial interface such as JTAG is
a non-intrusive way to gain access to the internal
state of the 8032 MCU core and various memories.
A traditional external hardware emulator cannot
be completely effective on the uPSD33xx
because of the Pre-Fetch Queue and Branch
Cache. The nature of the PFQ and BC hide the
visibility of actual program flow through traditional
external bus connections, thus requiring on-chip
serial debugging instead.
Debugging is supported by Windows PC based
software tools used for 8051 code development
from 3rd party vendors listed at www.st.com/psm.
Debug capabilities include:
■ Halt or Start MCU execution
■ Reset the MCU
■ Single Step
■ 3 Match Breakpoints
■ 1 Range Breakpoint (inside or outside range)
■ Program Tracing
■ Read or Modify MCU core registers, DATA,
IDATA, SFR, XDATA, and Code
■ External Debug Event Pin, Input or Output
Some key points regarding use of the JTAG Debugger.
– The JTAG Debugger can access MCU
registers, data memory, and code memory
while the MCU is executing at full speed by
cycle-stealing. This means “watch windows”
may be displayed and periodically updated on
the PC during full speed operation. Registers
and data content may also be modified during
full speed operation.
– There is no on-chip storage for Program Trace
data, but instead this data is scanned from the
uPSD33xx through the JTAG channel at runtime
to the PC host for proccessing. As such,
full speed program tracing is possible only
when the 8032 MCU is operating below
approximately one MIPS of performance.
Above one MIPS, the program will not run
real-time while tracing. One MIPS
performance is determined by the
combination of choice for MCU clock
frequency, and the bit settings in SFR
registers BUSCON and CCON0.
– Breakpoints can optionally halt the MCU, and/
or assert the external Debug Event pin.
– Breakpoint definitions may be qualified with
read or write operations, and may also be
qualified with an address of code, SFR, DATA,
IDATA, or XDATA memories.
– Three breakpoints will compare an address,
but the fourth breakpoint can compare an
address and also data content. Additionally,
the fouth breakpoint can be logically combined
(AND/OR) with any of the other three
breakpoints.
– The Debug Event pin can be configured by the
PC host to generate an output pulse for
external triggering when a break condition is
met. The pin can also be configured as an
event input to the breakpoint logic, causing a
break on the falling-edge of an external event
signal. If not used, the Debug Event pin should
be pulled up to VCC as described in the
section, Debugging the 8032 MCU
Module., page 201.
– The duration of a pulse, generated when the
Event pin configured as an output, is one MCU
clock cycle. This is an active-low signal, so the
first edge when an event occurs is high-to-low.
– The clock to the Watchdog Timer, ADC, and
I
2C interface are not stopped by a breakpoint
halt.
– The Watchdog Timer should be disabled while
debugging with JTAG, else a reset will be
generated upon a watchdog time-out.uPSD33xx
40/231
INTERRUPT SYSTEM
The uPSD33xx has an 11-source, two priority level
interrupt structure summarized in Table 16.
Firmware may assign each interrupt source either
high or low priority by writing to bits in the SFRs
named, IP and IPA, shown in Table 16. An interrupt
will be serviced as long as an interrupt of
equal or higher priority is not already being serviced.
If an interrupt of equal or higher priority is
being serviced, the new interrupt will wait until it is
finished before being serviced. If a lower priority
interrupt is being serviced, it will be stopped and
the new interrupt is serviced. When the new interrupt
is finished, the lower priority interrupt that was
stopped will be completed. If new interrupt requests
are of the same priority level and are received
simultaneously, an internal polling
sequence determines which request is selected
for service. Thus, within each of the two priority
levels, there is a second priority structure determined
by the polling sequence.
Firmware may individually enable or disable interrupt
sources by writing to bits in the SFRs named,
IE and IEA, shown in Table 16., page 41. The SFR
named IE contains a global disable bit (EA), which
can be cleared to disable all 11 interrupts at once,
as shown in Table 17., page 43. Figure
13., page 42 illustrates the interrupt priority, polling,
and enabling process.
Each interrupt source has at least one interrupt
flag that indicates whether or not an interrupt is
pending. These flags reside in bits of various
SFRs shown in Table 16., page 41.
All of the interrupt flags are latched into the interrupt
control system at the beginning of each MCU
machine cycle, and they are polled at the beginning
of the following machine cycle. If polling determines
one of the flags was set, the interrupt
control system automatically generates an LCALL
to the user’s Interrupt Service Routine (ISR) firmware
stored in program memory at the appropriate
vector address.
The specific vector address for each of the interrupt
sources are listed in Table 16., page 41. However,
this LCALL jump may be blocked by any of
the following conditions:
– An interrupt of equal or higher priority is
already in progress
– The current machine cycle is not the final cycle
in the execution of the instruction in progress
– The current instruction involves a write to any
of the SFRs: IE, IEA, IP, or IPA
– The current instruction is an RETI
Note: Interrupt flags are polled based on a sample
taken in the previous MCU machine cycle. If an interrupt
flag is active in one cycle but is denied serviced
due to the conditions above, and then later it
is not active when the conditions above are finally
satisfied, the previously denied interrupt will not be
serviced. This means that active interrupts are not
remembered. Every poling cycle is new.
Assuming all of the listed conditions are satisfied,
the MCU executes the hardware generated
LCALL to the appropriate ISR. This LCALL pushes
the contents of the PC onto the stack (but it does
not save the PSW) and loads the PC with the appropriate
interrupt vector address. Program execution
then jumps to the ISR at the vector address.
Execution precedes in the ISR. It may be necessary
for the ISR firmware to clear the pending interrupt
flag for some interrupt sources, because
not all interrupt flags are automatically cleared by
hardware when the ISR is called, as shown in Table
16., page 41. If an interrupt flag is not cleared
after servicing the interrupt, an unwanted interrupt
will occur upon exiting the ISR.
After the interrupt is serviced, the last instruction
executed by the ISR is RETI. The RETI informs
the MCU that the ISR is no longer in progress and
the MCU pops the top two bytes from the stack
and loads them into the PC. Execution of the interrupted
program continues where it left off.
Note: An ISR must end with a RETI instruction,
not a RET. An RET will not inform the interrupt
control system that the ISR is complete, leaving
the MCU to think the ISR is still in progress, making
future interrupts impossible.41/231
uPSD33xx
Table 16. Interrupt Summary
Interrupt
Source
Polling
Priority
Vector
Addr
Flag Bit Name
(SFR.bit position)
1 = Intr Pending
0 = No Interrupt
Flag Bit AutoCleared
by Hardware?
Enable Bit Name
(SFR.bit position)
1 = Intr Enabled
0 = Intr Disabled
Priority Bit Name
(SFR.bit position)
1= High Priority
0 = Low Priority
Reserved 0 (high) 0063h – – – –
External
Interrupt INT0 1 0003h IE0 (TCON.1) Edge - Yes
Level - No EX0 (IE.0) PX0 (IP.0)
Timer 0
Overflow 2 000Bh TF0 (TCON.5) Yes ET0 (IE.1) PT0 (IP.1)
External
Interrupt INT1 3 0013h IE1 (TCON.3 Edge - Yes
Level - No EX1 (IE.2) PX1 (IP.2)
Timer 1
Overflow 4 001Bh TF1 (TCON.7) Yes ET1 (IE.3) PT1 (IP.3)
UART0 5 0023h RI (SCON0.0)
TI (SCON0.1) No ES0 (IE.4) PS0 (IP.4)
Timer 2
Overflow
or TX2 Pin
6 002Bh TF2 (T2CON.7)
EXF2 (T2CON.6) No ET2 (IE.5) PT2 (IP.5)
SPI 7 0053h
TEISF, RORISF,
TISF, RISF
(SPISTAT[3:0])
Yes ESPI (IEA.6) PSPI (IPA.6)
Reserved 8 0033h – – – –
I
2C 9 0043h INTR (S1STA.5) Yes EI2C (IEA.1) PI2C (IPA.1)
ADC 10 003Bh AINTF (ACON.7) No EADC (IEA.7) PADC (IPA.7)
PCA 11 005Bh OFVx, INTFx
(PCASTA[0:7]) No EPCA (IEA.5) PPCA (IPA.5)
UART1 12 (low) 004Bh RI (SCON1.0)
TI (SCON1.1) No ES1 (IEA.4) PS1 (IPA.4)uPSD33xx
42/231
Figure 13. Enabling and Polling Interrupts
Reserved
Ext
INT0
Ext
INT1
Timer 0
UART0
Timer 1
SPI
USB
Timer 2
High
LowInterrupt Polling Sequence
Interrupt
Sources IE/IEA IP/IPA
Priority
Global
Enable
ADC
PCA
I
2
C
UART1
AI0784443/231
uPSD33xx
Individual Interrupt Sources
External Interrupts Int0 and Int1. External interrupt
inputs on pins EXTINT0 and EXTINT1
(pins 3.2 and 3.3) are either edge-triggered or level-triggered,
depending on bits IT0 and IT1 in the
SFR named TCON.
When an external interrupt is generated from an
edge-triggered (falling-edge) source, the appropriate
flag bit (IE0 or IE1) is automatically cleared by
hardware upon entering the ISR.
When an external interrupt is generated from a
level-triggered (low-level) source, the appropriate
flag bit (IE0 or IE1) is NOT automatically cleared
by hardware.
Timer 0 and 1 Overflow Interrupt. Timer 0 and
Timer 1 interrupts are generated by the flag bits
TF0 and TF1 when there is an overflow condition
in the respective Timer/Counter register (except
for Timer 0 in Mode 3).
Timer 2 Overflow Interrupt. This interrupt is
generated to the MCU by a logical OR of flag bits,
TF2 and EXE2. The ISR must read the flag bits to
determine the cause of the interrupt.
– TF2 is set by an overflow of Timer 2.
– EXE2 is generated by the falling edge of a
signal on the external pin, T2X (pin P1.1).
UART0 and UART1 Interrupt. Each of the
UARTs have identical interrupt structure. For each
UART, a single interrupt is generated to the MCU
by the logical OR of the flag bits, RI (byte received)
and TI (byte transmitted).
The ISR must read flag bits in the SFR named
SCON0 for UART0, or SCON1 for UART1 to determine
the cause of the interrupt.
SPI Interrupt. The SPI interrupt has four interrupt
sources, which are logically ORed together when
interrupting the MCU. The ISR must read the flag
bits to determine the cause of the interrupt.
A flag bit is set for: end of data transmit (TEISF);
data receive overrun (RORISF); transmit buffer
empty (TISF); or receive buffer full (RISF).
I
2C Interrupt. The flag bit INTR is set by a variety
of conditions occurring on the I2C interface: received
own slave address (ADDR flag); received
general call address (GC flag); received STOP
condition (STOP flag); or successful transmission
or reception of a data byte.The ISR must read the
flag bits to determine the cause of the interrupt.
ADC Interrupt. The flag bit AINTF is set when an
A-to-D conversion has completed.
PCA Interrupt. The PCA has eight interrupt
sources, which are logically ORed together when
interrupting the MCU.The ISR must read the flag
bits to determine the cause of the interrupt.
– Each of the six TCMs can generate a "match
or capture" interrupt on flag bits OFV5..0
respectively.
– Each of the two 16-bit counters can generate
an overflow interrupt on flag bits INTF1 and
INTF0 respectively.
Tables 17 through Table 20., page 45 have detailed
bit definitions of the interrupt system SFRs.
Table 17. IE: Interrupt Enable Register (SFR A8h, reset value 00h)
Note: 1. 1 = Enable Interrupt, 0 = Disable Interrupt
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
EA – ET2 ES0 ET1 EX1 ET0 EX0
Details
Bit Symbol R/W Function
7 EA R,W
Global disable bit. 0 = All interrupts are disabled. 1 = Each interrupt
source can be individually enabled or disabled by setting or clearing its
enable bit.
6 – R,W
Do not modify this bit. It is used by the JTAG debugger for instruction
tracing. Always read the bit and write back the same bit value when
writing this SFR.
5(1) ET2 R,W Enable Timer 2 Interrupt
4(1) ES0 R,W Enable UART0 Interrupt
3(1) ET1 R,W Enable Timer 1 Interrupt
2(1) EX1 R,W Enable External Interrupt INT1
1(1) ET0 R,W Enable Timer 0 Interrupt
0(1) EX0 R,W Enable External Interrupt INT0uPSD33xx
44/231
Table 18. IEA: Interrupt Enable Addition Register (SFR A7h, reset value 00h)
Note: 1. 1 = Enable Interrupt, 0 = Disable Interrupt
Table 19. IP: Interrupt Priority Register (SFR B8h, reset value 00h)
Note: 1. 1 = Assigns high priority level, 0 = Assigns low priority level
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
EADC ESPI EPCA ES1 – – EI2C –
Details
Bit Symbol R/W Function
7(1) EADC R,W Enable ADC Interrupt
6(1) ESPI R,W Enable SPI Interrupt
5(1) EPCA R,W Enable Programmable Counter Array Interrupt
4(1) ES1 R,W Enable UART1 Interrupt
3 – – Reserved, do not set to logic '1.'
2 – – Reserved, do not set to logic '1.'
1(1) EI2C R,W Enable I2C Interrupt
0 – – Reserved, do not set to logic '1.'
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
– – PT2 PS0 PT1 PX1 PT0 PX0
Details
Bit Symbol R/W Function
7 – – Reserved
6 – – Reserved
5(1) PT2 R,W Timer 2 Interrupt priority level
4(1) PS0 R,W UART0 Interrupt priority level
3(1) PT1 R,W Timer 1 Interrupt priority level
2(1) PX1 R,W External Interrupt INT1 priority level
1(1) PT0 R,W Timer 0 Interrupt priority level
0(1) PX0 R,W External Interrupt INT0 priority level45/231
uPSD33xx
Table 20. IPA: Interrupt Priority Addition register (SFR B7h, reset value 00h)
Note: 1. 1 = Assigns high priority level, 0 = Assigns low priority level
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PADC PSPI PPCA PS1 – – PI2C –
Details
Bit Symbol R/W Function
7(1) PADC R,W ADC Interrupt priority level
6(1) PSPI R,W SPI Interrupt priority level
5(1) PPCA R,W PCA Interrupt level
4(1) PS1 R,W UART1 Interrupt priority level
3 – – Reserved
2 – – Reserved
1(1) PI2C R,W I
2C Interrupt priority level
0 – – ReserveduPSD33xx
46/231
MCU CLOCK GENERATION
Internal system clocks generated by the clock generation
unit are derived from the signal, XTAL1,
shown in Figure 14. XTAL1 has a frequency fOSC,
which comes directly from the external crystal or
oscillator device. The SFR named CCON0 (Table
21., page 47) controls the clock generation unit.
There are two clock signals produced by the clock
generation unit:
■ MCU_CLK
■ PERIPH_CLK
MCU_CLK
This clock drives the 8032 MCU core and the
Watchdog Timer (WDT). The frequency of
MCU_CLK is equal to fOSC by default, but it can be
divided by as much as 2048, shown in Figure 14.
The bits CPUPS[2:0] select one of eight different
divisors, ranging from 2 to 2048. The new frequency
is available immediately after the CPUPS[2:0]
bits are written. The final frequency of MCU_CLK
is fMCU.
MCU_CLK is blocked by either bit, PD or IDL, in
the SFR named PCON during MCU Power-down
Mode or Idle Mode respectively.
MCU_CLK clock can be further divided as required
for use in the WDT. See details of the WDT
in SUPERVISORY FUNCTIONS, page 65.
PERIPH_CLK
This clock drives all the uPSD33xx peripherals except
the WDT. The Frequency of PERIPH_CLK is
always fOSC. Each of the peripherals can independently
divide PERIPH_CLK to scale it appropriately
for use.
PERIPH_CLK runs at all times except when
blocked by the PD bit in the SFR named PCON
during MCU Power-down Mode.
JTAG Interface Clock. The JTAG interface for
ISP and for Debugging uses the externally supplied
JTAG clock, coming in on pin TCK. This
means the JTAG ISP interface is always available,
and the JTAG Debug interface is available when
enabled, even during MCU Idle mode and Powerdown
Mode.
However, since the MCU participates in the JTAG
debug process, and MCU_CLK is halted during
Idle and Power-down Modes, the majority of debug
functions are not available during these low
power modes. But the JTAG debug interface is capable
of executing a reset command while in these
low power modes, which will exit back to normal
operating mode where all debug commands are
available again.
The CCON0 SFR contains a bit, DBGCE, which
enables the breakpoint comparators inside the
JTAG Debug Unit when set. DBGCE is set by default
after reset, and firmware may clear this bit at
run-time. Disabling these comparators will reduce
current consumption on the MCU Module, and it’s
recommended to do so if the Debug Unit will not
be used (such as in the production version of an
end-product).
Figure 14. Clock Generation Logic
XTAL1 /2
XTAL1 /4
XTAL1 /2048
Q
Q
Q
M
U
X
XTAL1 (default)
XTAL1 /8
XTAL1 /16
Q
Q
XTAL1 /32
XTAL1 /1024
Q
Q
0
1
2
3
4
5
6
7
XTAL1
(fOSC)
PCON[1]: PD,
Power-Down Mode
PCON[2:0]: CPUPS[2:0],
Clock Pre-Scaler Select
PCON[0]: IDL,
Idle Mode
Clock Divider
MCU_CLK (fMCU)
(to: 8032, WDT)
PERIPH_CLK (fOSC)
(to: TIMER0/1/2, UART0/1, PCA0/1, SPI, I2C, ADC)
3
AI0919747/231
uPSD33xx
Table 21. CCON0: Clock Control Register (SFR F9h, reset value 10h)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
– – – DBGCE CPUAR CPUPS[2:0]
Details
Bit Symbol R/W Definition
7 – – Reserved
6 – – Reserved
5 – – Reserved
4 DBGCE R,W
Debug Unit Breakpoint Comparator Enable
0 = JTAG Debug Unit comparators are disabled
1 = JTAG Debug Unit comparators are enabled (Default condition after
reset)
3 CPUAR R,W
Automatic MCU Clock Recovery
0 = There is no change of CPUPS[2:0] when an interrupt occurs.
1 = Contents of CPUPS[2:0] automatically become 000b whenever any
interrupt occurs.
2:0 CPUPS R,W
MCUCLK Pre-Scaler
000b: fMCU = fOSC (Default after reset)
001b: fMCU = fOSC/2
010b: fMCU = fOSC/4
011b: fMCU = fOSC/8
100b: fMCU = fOSC/16
101b: fMCU = fOSC/32
110b: fMCU = fOSC/1024
111b: fMCU = fOSC/2048uPSD33xx
48/231
POWER SAVING MODES
The uPSD33xx is a combination of two die, or
modules, each module having it’s own current
consumption characteristics. This section describes
reduced power modes for the MCU Module.
See the section, Power
Management, page 137 for reduced power modes
of the PSD Module. Total current consumption for
the combined modules is determined in the DC
specifications at the end of this document.
The MCU Module has three software-selectable
modes of reduced power operation.
■ Idle Mode
■ Power-down Mode
■ Reduced Frequency Mode
Idle Mode
Idle Mode will halt the 8032 MCU core while leaving
the MCU peripherals active (Idle Mode blocks
MCU_CLK only). For lowest current consumption
in this mode, it is recommended to disable all unused
peripherals, before entering Idle mode (such
as the ADC and the Debug Unit breakpoint comparators).
The following functions remain fully active
during Idle Mode (except if disabled by SFR
settings).
■ External Interrupts INT0 and INT1
■ Timer 0, Timer 1 and Timer 2
■ Supervisor reset from: LVD, JTAG Debug,
External RESET_IN_, but not the WTD
■ ADC
■ I
2C Interface
■ UART0 and UART1 Interfaces
■ SPI Interface
■ Programmable Counter Array
An interrupt generated by any of these peripherals,
or a reset generated from the supervisor, will
cause Idle Mode to exit and the 8032 MCU will resume
normal operation.
The output state on I/O pins of MCU ports 1, 3, and
4 remain unchanged during Idle Mode.
To enter Idle Mode, the 8032 MCU executes an instruction
to set the IDL bit in the SFR named
PCON, shown in Table 24., page 50. This is the
last instruction executed in normal operating mode
before Idle Mode is activated. Once in Idle Mode,
the MCU status is entirely preserved, and there
are no changes to: SP, PSW, PC, ACC, SFRs,
DATA, IDATA, or XDATA.
The following are factors related to Idle Mode exit:
– Activation of any enabled interrupt will cause
the IDL bit to be cleared by hardware,
terminating Idle Mode. The interrupt is
serviced, and following the Return from
Interrupt instruction (RETI), the next
instruction to be executed will be the one
which follows the instruction that set the IDL
bit in the PCON SFR.
– After a reset from the supervisor, the IDL bit is
cleared, Idle Mode is terminated, and the MCU
restarts after three MCU machine cycles.
Power-down Mode
Power-down Mode will halt the 8032 core and all
MCU peripherals (Power-down Mode blocks
MCU_CLK and PERIPH_CLK). This is the lowest
power state for the MCU Module. When the PSD
Module is also placed in Power-down mode, the
lowest total current consumption for the combined
die is achieved for the uPSD33xx. See Power
Management, page 137 in the PSD Module section
for details on how to also place the PSD Module
in Power-down mode. The sequence of 8032
instructions is important when placing both modules
into Power-down Mode.
The instruction that sets the PD Bit in the SFR
named PCON (Table 24., page 50) is the last instruction
executed prior to the MCU Module going
into Power-down Mode. Once in Power-down
Mode, the on-chip oscillator circuitry and all clocks
are stopped. The SFRs, DATA, IDATA,
and XDATA are preserved.
Power-down Mode is terminated only by a reset
from the supervisor, originating from the
RESET_IN_ pin, the Low-Voltage Detect circuit
(LVD), or a JTAG Debug reset command. Since
the clock to the WTD is not active during Powerdown
mode, it is not possible for the supervisor to
generate a WDT reset.
Table 22., page 49 summarizes the status of I/O
pins and peripherals during Idle and Power-down
Modes on the MCU Module. Table 23., page 49
shows the state of 8032 MCU address, data, and
control signals during these modes.
Reduced Frequency Mode
The 8032 MCU consumes less current when operating
at a lower clock frequency. The MCU can reduce
it’s own clock frequency at run-time by
writing to three bits, CPUPS[2:0], in the SFR
named CCON0 described in Table 21., page 47.
These bits effectively divide the clock frequency
(fOSC) coming in from the external crystal or oscillator
device. The clock division range is from 1/2 to
1/2048, and the resulting frequency is fMCU.
This MCU clock division does not affect any of the
peripherals, except for the WTD. The clock driving
the WTD is the same clock driving the 8032 MCU
core as shown in Figure 14., page 46.49/231
uPSD33xx
MCU firmware may reduce the MCU clock frequency
at run-time to consume less current when
performing tasks that are not time critical, and then
restore full clock frequency as required to perform
urgent tasks.
Returning to full clock frequency is done automatically
upon an MCU interrupt, if the CPUAR Bit in
the SFR named CCON0 is set (the interrupt will
force CPUPS[2:0] = 000). This is an excellent way
to conserve power using a low frequency clock until
an event occurs that requires full performance.
See Table 21., page 47 for details on CPUAR.
See the DC Specifications at the end of this document
to estimate current consumption based on
the MCU clock frequency.
Note: Some of the bits in the PCON SFR shown in
Table 24., page 50 are not related to power control.
Table 22. MCU Module Port and Peripheral Status during Reduced Power Modes
Note: 1. The Watchdog Timer is not active during Idle Mode. Other supervisor functions are active: LVD, external reset, JTAG Debug reset
Table 23. State of 8032 MCU Bus Signals during Power-down and Idle Modes
Mode Ports 1, 3, 4 PCA SPI I
2C ADC SUPERVISOR
UART0,
UART1
TIMER
0,1,2
EXT
INT0, 1
Idle Maintain Data Active Active Active Active Active(1) Active Active Active
Power-down Maintain Data Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled
Mode ALE PSEN_ RD_ WR_ AD0-7 A8-15
Idle 0 1 1 1 FFh FFh
Power-down 0 1 1 1 FFh FFhuPSD33xx
50/231
Table 24. PCON: Power Control Register (SFR 87h, reset value 00h)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SMOD0 SMOD1 – POR RCLK1 TCLK1 PD IDL
Details
Bit Symbol R/W Function
7 SMOD0 R,W
Baud Rate Double Bit (UART0)
0 = No Doubling
1 = Doubling
(See UART Baud Rates, page 84 for details.)
6 SMOD1 R,W
Baud Rate Double Bit for 2nd UART (UART1)
0 = No Doubling
1 = Doubling
(See UART Baud Rates, page 84 for details.)
5 – – Reserved
4 POR R,W
Only a power-on reset sets this bit (cold reset). Warm reset will not set
this bit.
'0,' Cleared to zero with firmware
'1,' Is set only by a power-on reset generated by Supervisory circuit (see
Power-up Reset, page 66 for details).
3 RCLK1 R,W Received Clock Flag (UART1)
(See Table 41., page 75 for flag description.)
2 TCLK1 R,W Transmit Clock Flag (UART1)
(See Table 41., page 75 for flag description)
1 PD R,W
Activate Power-down Mode
0 = Not in Power-down Mode
1 = Enter Power-down Mode
0 IDL R,W
Activate Idle Mode
0 = Not in Idle Mode
1 = Enter Idle Mode51/231
uPSD33xx
OSCILLATOR AND EXTERNAL COMPONENTS
The oscillator circuit of uPSD33xx devices is a single
stage, inverting amplifier in a Pierce oscillator
configuration. The internal circuitry between pins
XTAL1 and XTAL2 is basically an inverter biased
to the transfer point. Either an external quartz crystal
or ceramic resonator can be used as the feedback
element to complete the oscillator circuit.
Both are operated in parallel resonance. Ceramic
resonators are lower cost, but typically have a wider
frequency tolerance than quartz crystals. Alternatively,
an external clock source from an
oscillator or other active device may drive the
uPSD33xx oscillator circuit input directly, instead
of using a crystal or resonator.
The minimum frequency of the quartz crystal, ceramic
resonator, or external clock source is 1MHz
if the I2C interface is not used. The minimum is
8MHz if I2C is used. The maximum is 40MHz in all
cases. This frequency is fOSC, which can be divided
internally as described in MCU CLOCK
GENERATION, page 46.
The pin XTAL1 is the high gain amplifier input, and
XTAL2 is the output. To drive the uPSD33xx device
externally from an oscillator or other active
device, XTAL1 is driven and XTAL2 is left opencircuit.
This external source should drive a logic
low at the voltage level of 0.3 VCC or below, and
logic high at 0.7V VCC or above, up to 5.5V VCC.
The XTAL1 input is 5V tolerant.
Most of the quartz crystals in the range of 25MHz
to 40MHz operate in the third overtone frequency
mode. An external LC tank circuit at the XTAL2
output of the oscillator circuit is needed to achieve
the third overtone frequency, as shown in Figure
15., page 52. Without this LC circuit, the crystal
will oscillate at a fundamental frequency mode that
is about 1/3 of the desired overtone frequency.
Note: In Figure 15., page 52 crystals which are
specified to operate in fundamental mode (not
overtone mode) do not need the LC circuit components.
Since quartz crystals and ceramic resonators
have their own characteristics based on their
manufacturer, it is wise to also consult the manufacturer’s
recommended values for external components.uPSD33xx
52/231
Figure 15. Oscillator and Clock Connections
Crystal or Resonator
Usage
Direct Drive
XTAL1
(in)
XTAL1
(in)
XTAL2
(out)
XTAL2
(out)
C1 C2 XTAL
(fOSC)
L1
C3
External Ocsillator or No Connect
Active Clock Source
XTAL (fOSC) C1 = C2 C3 L1
Ceramic Resonator 40 - 50pF None
Crystal, fundamental mode (3-40MHz) 15-33pF None
None
None
Crystal, overtone mode (25-40MHz) 20pF 10nF 2.2µH
AI0919853/231
uPSD33xx
I/O PORTS OF MCU MODULE
The MCU Module has three 8-bit I/O ports: Port 1,
Port 3, and Port 4. The PSD Module has four other
I/O ports: Port A, B, C, and D. This section describes
only the I/O ports on the MCU Module.
I/O ports will function as bi-directional General
Purpose I/O (GPIO), but the port pins can have alternate
functions assigned at run-time by writing to
specific SFRs. The default operating mode (during
and after reset) for all three ports is GPIO input
mode. Port pins that have no external connection
will not float because each pin has an internal
weak pull-up (~150K ohms) to VCC.
I/O ports 3 and 4 are 5V tolerant, meaning they
can be driven/pulled externally up to 5.5V without
damage. The pins on Port 4 have a higher current
capability than the pins on Ports 1 and 3.
Three additional MCU ports (only on 80-pin
uPSD33xx devices) are dedicated to bring out the
8032 MCU address, data, and control signals to
external pins. One port, named MCUA[11:8], contains
four MCU address signal outputs. Another
port, named MCUAD[7:0], has eight multiplexed
address/data bidirectional signals. The third port
has MCU bus control outputs: read, write, program
fetch, and address latch. These ports are typically
used to connect external parallel peripherals and
memory devices, but they may NOT be used as
GPIO. Notice that only four of the eight upper address
signals come out to pins on the port MCUA[11:8].
If additional high-order address signals
are required on external pins (MCU addresses
A[15:12]), then these address signals can be
brought out as needed to PLD output pins or to the
Address Out mode pins on PSD Module ports.
See PSD Module section, “Latched Address Output
Mode, page 177 for details.
Figure 16., page 55 represents the flexibility of pin
function routing controlled by the SFRs. Each of
the 24 pins on three ports, P1, P3, and P4, may be
individually routed on a pin-by-pin basis to a desired
function.
MCU Port Operating Modes
MCU port pins can operate as GPIO or as alternate
functions (see Figure 17., page 56 through
Figure 19., page 57).
Depending on the selected pin function, a particular
pin operating mode will automatically be used:
■ GPIO - Quasi-bidirectional mode
■ UART0, UART1 - Quasi-bidirectional mode
■ SPI - Quasi-bidirectional mode
■ I2C - Open drain mode
■ ADC - Analog input mode
■ PCA output - Push-Pull mode
■ PCA input - Input only (Quasi-bidirectional)
■ Timer 0,1,2 - Input only (Quasi-bidirectional)
GPIO Function. Ports in GPIO mode operate as
quasi-bidirectional pins, consistent with standard
8051 architecture. GPIO pins are individually controlled
by three SFRs:
■ SFR, P1 (Table 25., page 57)
■ SFR, P3 (Table 26., page 58)
■ SFR, P4 (Table 27., page 58)
These SFRs can be accessed using the Bit Addressing
mode, an efficient way to control individual
port pins.
GPIO Output. Simply stated, when a logic '0' is
written to a bit in any of these port SFRs while in
GPIO mode, the corresponding port pin will enable
a low-side driver, which pulls the pin to ground,
and at the same time releases the high-side driver
and pull-ups, resulting in a logic'0' output. When a
logic '1' is written to the SFR, the low-side driver is
released, the high-side driver is enabled for just
one MCU_CLK period to rapidly make the 0-to1
transition on the pin, while weak active pull-ups
(total ~150K ohms) to VCC are enabled. This structure
is consistent with standard 8051 architecture.
The high side driver is momentarily enabled only
for 0-to-1 transitions, which is implemented with
the delay function at the latch output as pictured in
Figure 17., page 56 through Figure 19., page 57.
After the high-side driver is disabled, the two weak
pull-ups remain enabled resulting in a logic '1' output
at the pin, sourcing IOH uA to an external device.
Optionally, an external pull-up resistor can be
added if additional source current is needed while
outputting a logic '1.'uPSD33xx
54/231
GPIO Input. To use a GPIO port pin as an input,
the low-side driver to ground must be disabled, or
else the true logic level being driven on the pin by
an external device will be masked (always reads
logic '0'). So to make a port pin “input ready”, the
corresponding bit in the SFR must have been set
to a logic '1' prior to reading that SFR bit as an input.
A reset condition forces SFRs P1, P3, and P4
to FFh, thus all three ports are input ready after reset.
When a pin is used as an input, the stronger pullup
“A” maintains a solid logic '1' until an external
device drives the input pin low. At this time, pull-up
“A” is automatically disabled, and only pull-up “B”
will source the external device IIH uA, consistent
with standard 8051 architecture.
GPIO Bi-Directional. It is possible to operate individual
port pins in bi-directional mode. For an output,
firmware would simply write the
corresponding SFR bit to logic '1' or '0' as needed.
But before using the pin as an input, firmware must
first ensure that a logic '1' was the last value written
to the corresponding SFR bit prior to reading
that SFR bit as an input.
GPIO Current Capability. A GPIO pin on Port 4
can sink twice as much current than a pin on either
Port 1 or Port 3 when the low-side driver is outputting
a logic '0' (IOL). See the DC specifications at
the end of this document for full details.
Reading Port Pin vs. Reading Port Latch. When
firmware reads the GPIO ports, sometimes the actual
port pin is sampled in hardware, and sometimes
the port SFR latch is read and not the actual
pin, depending on the type of MCU instruction
used. These two data paths are shown in Figure
17., page 56 through Figure 19., page 57. SFR
latches are read (and not the pins) only when the
read is part of a read-modify-write instruction and
the write destination is a bit or bits in a port SFR.
These instructions are: ANL, ORL, XRL, JBC,
CPL, INC, DEC, DJNZ, MOV, CLR, and SETB. All
other types of reads to port SFRs will read the actual
pin logic level and not the port latch. This is
consistent with 8051 architecture.55/231
uPSD33xx
Figure 16. MCU Module Port Pin Function Routing
8 P3
P1
P4
M
C
U
A
D
M
C
U
A
GPIO (8)
UART0 (2)
TIMER0/1 (4)
I
2C (2)
GPIO (8)
GPIO (8)
TIMER2 (2)
UART1 (2)
SPI (4)
ADC (8)
PCA (8)
8032 MCU
CORE
Low Addr & Data[7:0] 8
Available on PSD Hi Address [15:12] Hi Address [11:8] 4
Module Pins
MCU Module
4
On 80-pin
Devices
Only
Ports
C
N
T
L
RD, WR, PSEN, ALE 4
SFR
8
8
SFR
SFR
SFR
SFR
SFR
AI09199uPSD33xx
56/231
Figure 17. MCU I/O Cell Block Diagram for Port 1
Figure 18. MCU I/O Cell Block Diagram for Port 3
P1.X Pin
Analog_Alt_Func_En
Analog_Pin_In
D Q
PRE
SFR
P1.X
Latch
8032 Data Bus Bit
GPIO P1.X SFR
Write Latch
MCU_Reset
P1.X SFR Read Latch
(for R-M-W instructions)
P1.X SFR Read Pin
Select_Alternate_Func
Digital_Pin_Data_In
IN 1
IN 0
MUX Y
VCC VCC VCC
SEL
WEAK
PULL-UP, B
STONGER
PULL-UP, A
LOW
SIDE
HIGH
SIDE
DELAY,
1 MCU_CLK
DELAY,
1 MCU_CLK
Q
Digital_Alt_Func_Data_Out
AI09600
P3.X Pin
Digital_Pin_Data_In
D Q
PRE
SFR
P3.X
Latch
8032 Data Bus Bit
GPIO P3.X SFR
Write Latch
MCU_Reset
P3.X SFR Read Latch
(for R-M-W instructions)
P3.X SFR Read Pin
Select_Alternate_Func
Disables High-Side Driver
IN 1
IN 0
MUX Y
VCC VCC VCC
SEL
Enable_I2C
WEAK
PULL-UP, B
STONGER
PULL-UP, A
LOW
SIDE
HIGH
SIDE
DELAY,
1 MCU_CLK
DELAY,
1 MCU_CLK
Q
Digital_Alt_Func_Data_Out
AI0960157/231
uPSD33xx
Figure 19. MCU I/O Cell Block Diagram for Port 4
Table 25. P1: I/O Port 1 Register (SFR 90h, reset value FFh)
Note: 1. Write '1' or '0' for pin output. Read for pin input, but prior to READ, this bit must have been set to '1' by firmware or by a reset event.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0
Details
Bit Symbol R/W Function(1)
7 P1.7 R,W Port pin 1.7
6 P1.6 R,W Port pin 1.6
5 P1.5 R,W Port pin 1.5
4 P1.4 R,W Port pin 1.4
3 P1.3 R,W Port pin 1.3
2 P1.2 R,W Port pin 1.2
1 P1.1 R,W Port pin 1.1
0 P1.0 R,W Port pin 1.0
P4.X Pin
Digital_Pin_Data_In
D Q
PRE
SFR
P4.X
Latch
8032 Data Bus Bit
GPIO P4.X SFR
Write Latch
MCU_Reset
P4.X SFR Read Latch
(for R-M-W instructions)
P4.X SFR Read Pin
Select_Alternate_Func
For PCA Alternate Function
IN 1
IN 0
MUX Y
VCC VCC VCC
SEL
Enable_Push_Pull
WEAK
PULL-UP, B
STONGER
PULL-UP, A
LOW
SIDE
HIGH
SIDE
DELAY,
1 MCU_CLK
DELAY,
1 MCU_CLK
Q
Digital_Alt_Func_Data_Out
AI09602uPSD33xx
58/231
Table 26. P3: I/O Port 3 Register (SFR B0h, reset value FFh)
Note: 1. Write '1' or '0' for pin output. Read for pin input, but prior to READ, this bit must have been set to '1' by firmware or by a reset event.
Table 27. P4: I/O Port 4 Register (SFR C0h, reset value FFh)
Note: 1. Write '1' or '0' for pin output. Read for pin input, but prior to READ, this bit must have been set to '1' by firmware or by a reset event.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
Details
Bit Symbol R/W Function(1)
7 P3.7 R,W Port pin 3.7
6 P3.6 R,W Port pin 3.6
5 P3.5 R,W Port pin 3.5
4 P3.4 R,W Port pin 3.4
3 P3.3 R,W Port pin 3.3
2 P3.2 R,W Port pin 3.2
1 P3.1 R,W Port pin 3.1
0 P3.0 R,W Port pin 3.0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0
Details
Bit Symbol R/W Function(1)
7 P4.7 R,W Port pin 4.7
6 P4.6 R,W Port pin 4.6
5 P4.5 R,W Port pin 4.5
4 P4.4 R,W Port pin 4.4
3 P4.3 R,W Port pin 4.3
2 P4.2 R,W Port pin 4.2
1 P4.1 R,W Port pin 4.1
0 P4.0 R,W Port pin 4.059/231
uPSD33xx
Alternate Functions. There are five SFRs used
to control the mapping of alternate functions onto
MCU port pins, and these SFRs are depicted as
switches in Figure 16., page 55.
■ Port 3 uses the SFR, P3SFS (Table
28., page 60).
■ Port 1 uses SFRs, P1SFS0 (Table
29., page 60) and P1SFS1 (Table
30., page 60).
■ Port 4 uses SFRs, P4SFS0 (Table
32., page 61) and P4SFS1 (Table
33., page 61).
Since these SFRs are cleared by a reset, then by
default all port pins function as GPIO (not the alternate
function) until firmware initializes these SFRs.
Each pin on each of the three ports can be independently
assigned a different function on a pinby-pin
basis.
The peripheral functions Timer 2, UART1, and I2C
may be split independently between Port 1 and
Port 4 for additional flexibility by giving a wider
choice of peripheral usage on a limited number of
device pins.
When the selected alternate function is UART0,
UART1, or SPI, then the related pins are in quasibidirectional
mode, including the use of the highside
driver for rapid 0-to-1 output transitions. The
high-side driver is enabled for just one MCU_CLK
period on 0-to-1 transitions by the delay function at
the “digital_alt_func_data_out” signal pictured in
Figure 17., page 56 through Figure 19., page 57.
If the alternate function is Timer 0, Timer 1, Timer
2, or PCA input, then the related pins are in quasibidirectional
mode, but input only.
If the alternate function is ADC, then for each pin
the pull-ups, the high-side driver, and the low-side
driver are disabled. The analog input is routed directly
to the ADC unit. Only Port 1 supports analog
functions (Figure 17., page 56). Port 1 is not 5V
tolerant.
If the alternate function is I2C, the related pins will
be in open drain mode, which is just like quasi-bidirectional
mode but the high-side driver is not enabled
for one cycle when outputting a 0-to-1
transition. Only the low-side driver and the internal
weak pull-ups are used. Only Port 3 supports
open-drain mode (Figure 18., page 56). I2C requires
the use of an external pull-up resistor on
each bus signal, typically 4.7KΩ to VCC.
If the alternate function is PCA output, then the related
pins are in push-pull mode, meaning the pins
are actively driven and held to logic '1' by the highside
driver, or actively driven and held to logic '0'
by the low-side driver. Only Port 4 supports pushpull
mode (Figure 19., page 57). Port 4 push-pull
pins can source IOH current when driving logic '1,'
and sink IOL current when driving logic '0.' This
current is significantly more than the capability of
pins on Port 1 or Port 3 (see Table
129., page 207).
For example, to assign these port functions:
■ Port 1: UART1, ADC[1:0], P1[7:4] are GPIO
■ Port 3: UART0, I2C, P3[5:2] are GPIO
■ Port 4: TCM0, SPI, P4[3:1] are GPIO
The following values need to be written to the
SFRs:
P1SFS0 = 00001111b, or 0Fh
P1SFS1 = 00000011b , or 03h
P3SFS = 11000011b, or C3h
P4SFS0 = 11110001b, or F1h
P4SFS1 = 11110000b, or F0huPSD33xx
60/231
Table 28. P3SFS: Port 3 Special Function Select Register (SFR 91h, reset value 00h)
Table 29. P1SFS0: Port 1 Special Function Select 0 Register (SFR 8Eh, reset value 00h)
Table 30. P1SFS1: Port 1 Special Function Select 1 Register (SFR 8Fh, reset value 00h)
Table 31. P1SFS0 and P1SFS1 Details
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P3SFS7 P3SFS6 P3SFS5 P3SFS4 P3SFS3 P3SFS2 P3SFS1 P3SFS0
Details
Port 3 Pin R/W
Default Port Function Alternate Port Function
P3SFS[i] - 0; Port 3 Pin, i = 0..7 P3SFS[i] - 1; Port 3 Pin, i = 0..7
0 R,W GPIO UART0 Receive, RXD0
1 R,W GPIO UART0 Transmit, TXD0
2 R,W GPIO Ext Intr 0/Timer 0 Gate, EXT0INT/TG0
3 R,W GPIO Ext Intr 1/Timer 1 Gate, EXT1INT/TG1
4 R,W GPIO Counter 0 Input, C0
5 R,W GPIO Counter 0 Input, C1
6 R,W GPIO I
2C Data, I2CSDA
7 R,W GPIO I
2C Clock, I2CCL
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P1SF07 P1SF06 P1SF05 P1SF04 P1SF03 P1SF02 P1SF01 P1SF00
Details
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P1SF17 P1SF16 P1SF15 P1SF14 P1SF13 P1SF12 P1SF11 P1SF10
Port 1 Pin R/W
Default Port Function Alternate 1 Port Function Alternate 2 Port Function
P1SFS0[i] = 0
P1SFS1[i] = x
P1SFS0[i] = 1
P1SFS1[i] = 0
P1SFS0[i] = 1
P1SFS1[i] = 1
Port 1 Pin, i = 0.. 7 Port 1 Pin, i = 0.. 7 Port 1 Pin, i = 0.. 7
0 R,W GPIO Timer 2 Count Input, T2 ADC Chn 0 Input, ADC0
1 R,W GPIO Timer 2 Trigger Input, TX2 ADC Chn 1 Input, ADC1
2 R,W GPIO UART1 Receive, RXD1 ADC Chn 2 Input, ADC2
3 R,W GPIO UART1 Transmit, TXD1 ADC Chn 3 Input, ADC3
4 R,W GPIO SPI Clock, SPICLK ADC Chn 4 Input, ADC4
5 R,W GPIO SPI Receive, SPIRXD ADC Chn 5 Input, ADC5
6 R,W GPIO SPI Transmit, SPITXD ADC Chn 6 Input, ADC6
7 R,W GPIO SPI Select, SPISEL_ ADC Chn 7 Input, ADC761/231
uPSD33xx
Table 32. P4SFS0: Port 4 Special Function Select 0 Register (SFR 92h, reset value 00h)
Table 33. P4SFS1: Port 4 Special Function Select 1 Register (SFR 93h, reset value 00h)
Table 34. P4SFS0 and P4SFS1 Details
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P4SF07 P4SF06 P4SF05 P4SF04 P4SF03 P4SF02 P4SF01 P4SF00
Details
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P4SF17 P4SF16 P4SF15 P4SF14 P4SF13 P4SF12 P4SF11 P4SF10
Port 4 Pin R/W
Default Port Function Alternate 1 Port Function Alternate 2 Port Function
P4SFS0[i] = 0
P4SFS1[i] = x
P4SFS0[i] = 1
P4SFS1[i] = 0
P4SFS0[i] = 1
P4SFS1[i] = 1
Port 4 Pin, i = 0.. 7 Port 4 Pin, i = 0.. 7 Port 4 Pin, i = 0.. 7
0 R,W GPIO PCA0 Module 0, TCM0 Timer 2 Count Input, T2
1 R,W GPIO PCA0 Module 1, TCM1 Timer 2 Trigger Input, TX2
2 R,W GPIO PCA0 Module 2, TCM2 UART1 Receive, RXD1
3 R,W GPIO PCA0 Ext Clock, PCACLK0 UART1 Transmit, TXD1
4 R,W GPIO PCA1 Module 3, TCM3 SPI Clock, SPICLK
5 R,W GPIO PCA1 Module 4, TCM4 SPI Receive, SPIRXD
6 R,W GPIO PCA1 Module 5, TCM5 SPI Transmit, SPITXD
7 R,W GPIO PCA1 Ext Clock, PCACLK1 SPI Select, SPISEL_uPSD33xx
62/231
MCU BUS INTERFACE
The MCU Module has a programmable bus interface.
It is based on a standard 8032 bus, with eight
data signals multiplexed with eight low-order address
signals (AD[7:0]). It also has eight high-order
non-multiplexed address signals (A[15:8]).
Time multiplexing is controlled by the address
latch signal, ALE.
This bus connects the MCU Module to the PSD
Module, and also connects to external pins only on
80-pin devices. See the AC specifications section
at the end of this document for external bus timing
on 80-pin devices.
Four types of data transfers are supported, each
transfer is to/from a memory location external to
the MCU Module:
– Code Fetch cycle using the PSEN signal: fetch
a code byte for execution
– Code Read cycle using PSEN: read a code
byte using the MOVC (Move Constant)
instruction
– XDATA Read cycle using the RD signal: read
a data byte using the MOVX (Move eXternal)
instruction
– XDATA Write cycle using the WR signal: write
a data byte using the MOVX instruction
The number of MCU_CLK periods for these transfer
types can be specified at runtime by firmware
writing to the SFR register named BUSCON (Table
35., page 63). Here, the number of MCU_CLK
clock pulses per bus cycle are specified to maximize
performance.
Important: By default, the BUSCON Register is
loaded with long bus cycle times (6 MCU_CLK periods)
after a reset condition. It is important that the
post-reset initialization firmware sets the bus cycle
times appropriately to get the most performance,
according to Table 36., page 64. Keep in mind that
the PSD Module has a faster Turbo Mode (default)
and a slower but less power consuming Non-Turbo
Mode. The bus cycle times must be programmed
in BUSCON to optimize for each mode
as shown in Table 36., page 64. See PLD NonTurbo
Mode, page 192 for more details.
Bus Read Cycles (PSEN or RD)
When the PSEN signal is used to fetch a byte of
code, the byte is read from the PSD Module or external
device and it enters the MCU Pre-Fetch
Queue (PFQ). When PSEN is used during a
MOVC instruction, or when the RD signal is used
to read a byte of data, the byte is routed directly to
the MCU, bypassing the PFQ.
Bits in the BUSCON Register determine the number
of MCU_CLK periods per bus cycle for each of
these kinds of transfers to all address ranges.
It is not possible to specify in the BUSCON Register
a different number of MCU_CLK periods for
various address ranges. For example, the user
cannot specify 4 MCU_CLK periods for RD read
cycles to one address range on the PSD Module,
and 5 MCU_CLK periods for RD read cycles to a
different address range on an external device.
However, the user can specify one number of
clock periods for PSEN read cycles and a different
number of clock periods for RD read cycles.
Note 1: A PSEN bus cycle in progress may be
aborted before completion if the PFQ and Branch
Cache (BC) determines the current code fetch cycle
is not needed.
Note 2: Whenever the same number of MCU_CLK
periods is specified in BUSCON for both PSEN
and RD cycles, the bus cycle timing is typically
identical for each of these types of bus cycles. In
this case, the only time PSEN read cycles are
longer than RD read cycles is when the PFQ issues
a stall while reloading. PFQ stalls do not affect
RD read cycles. By comparison, in many
traditional 8051 architectures, RD bus cycles are
always longer than PSEN bus cycles.
Bus Write Cycles (WR)
When the WR signal is used, a byte of data is written
directly to the PSD Module or external device,
no PFQ or caching is involved. Bits in the BUSCON
Register determine the number of
MCU_CLK periods for bus write cycles to all addresses.
It is not possible to specify in BUSCON a
different number of MCU_CLK periods for writes to
various address ranges.
Controlling the PFQ and BC
The BUSCON Register allows firmware to enable
and disable the PFQ and BC at run-time. Sometimes
it may be desired to disable the PFQ and BC
to ensure deterministic execution. The dynamic
action of the PFQ and BC may cause varying program
execution times depending on the events
that happen prior to a particular section of code of
interest. For this reason, it is not recommended to
implement timing loops in firmware, but instead
use one of the many hardware timers in the
uPSD33xx.
By default, the PFQ and BC are enabled after a reset
condition.
Important: Disabling the PFQ or BC will seriously
reduce MCU performance.63/231
uPSD33xx
Table 35. BUSCON: Bus Control Register (SFR 9Dh, reset value EBh)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
EPFQ EBC WRW[1:0] RDW[1:0] CW[1:0]
Details
Bit Symbol R/W Definition
7 EPFQ R,W
Enable Pre-Fetch Queue
0 = PFQ is disabled
1 = PFQ is enabled (default)
6 EBC R,W
Enable Branch Cache
0 = BC is disabled
1 = BC is enabled (default)
5:4 WRW[1:0] R,W
WR Wait, number of MCU_CLK periods for WR write bus cycle during
any MOVX instruction
00b: 4 clock periods
01b: 5 clock periods
10b: 6 clock periods (default)
11b: 7 clock periods
3:2 RDW[1:0] R,W
RD Wait, number of MCU_CLK periods for RD read bus cycle during any
MOVX instruction
00b: 4 clock periods
01b: 5 clock periods
10b: 6 clock periods (default)
11b: 7 clock periods
1:0 CW[1:0] R,W
Code Wait, number of MCU_CLK periods for PSEN read bus cycle
during any code byte fetch or during any MOVC code byte read
instruction. Periods will increase with PFQ stall
00b: 3 clock periods - exception, for MOVC instructions this setting
results 4 clock periods
01b: 4 clock periods
10b: 5 clock periods
11b: 6 clock periods (default)uPSD33xx
64/231
Table 36. Number of MCU_CLK Periods Required to Optimize Bus Transfer Rate
Note: 1. VDD of the PSD Module
2. “Turbo mode PSD” means that the PSD Module is in the faster, Turbo mode (default condition). A PSD Module in Non-Turbo mode
is slower, but consumes less current. See PSD Module section, titled “PLD Non-Turbo Mode” for details.
MCU Clock Frequency,
MCU_CLK (fMCU)
CW[1:0] Clk Periods RDW[1:0] Clk
Periods
WRW[1:0] Clk
Periods
3.3V(1) 5V(1) 3.3V(1) 5V(1) 3.3V(1) 5V(1)
40MHz, Turbo mode PSD(2) 545454
40MHz, Non-Turbo mode PSD 6 5 6 5 6 5
36MHz, Turbo mode PSD 545454
36MHz, Non-Turbo mode PSD 6 4 6 4 6 4
32MHz, Turbo mode PSD 545454
32MHz, Non-Turbo mode PSD 5 4 5 4 5 4
28MHz, Turbo mode PSD 434444
28MHz, Non-Turbo mode PSD 5 4 5 4 5 4
24MHz, Turbo mode PSD 434444
24MHz, Non-Turbo mode PSD 4 3 4 4 4 4
20MHz and below, Turbo mode PSD 334444
20MHz and below, Non-Turbo mode PSD 3 3 4 4 4 465/231
uPSD33xx
SUPERVISORY FUNCTIONS
Supervisory circuitry on the MCU Module will issue
an internal reset signal to the MCU Module and simultaneously
to the PSD Module as a result of any
of the following four events:
– The external RESET_IN pin is asserted
– The Low Voltage Detect (LVD) circuitry has
detected a voltage on VCC below a specific
threshold (power-on or voltage sags)
– The JTAG Debug interface has issued a reset
command
– The Watch Dog Timer (WDT) has timed out
The resulting internal reset signal, MCU_RESET,
will force the 8032 into a known reset state while
asserted, and then 8032 program execution will
jump to the reset vector at program address 0000h
just after MCU_RESET is deasserted. The MCU
Module will also assert an active low internal reset
signal, RESET, to the PSD Module. If needed, the
signal RESET can be driven out to external system
components through any PLD output pin on
the PSD Module. When driving this
“RESET_OUT” signal from a PLD output, the user
can choose to make it either active-high or activelow
logic, depending on the PLD equation.
External Reset Input Pin, RESET_IN
The RESET_IN pin can be connected directly to a
mechanical reset switch or other device which
pulls the signal to ground to invoke a reset.
RESET_IN is pulled up internally and enters a
Schmitt trigger input buffer with a voltage hysteresis
of VRST_HYS for immunity to the effects of slow
signal rise and fall times, as shown in Figure 20.
RESET_IN is also filtered to reject a voltage spike
less than a duration of tRST_FIL. The RESET_IN
signal must be maintained at a logic '0' for at least
a duration of tRST_LO_IN while the oscillator is running.
The resulting MCU_RESET signal will last
only as long as the RESET_IN signal is active (it is
not stretched). Refer to the Supervisor AC specifications
in Table 150., page 221 at the end of this
document for these parameter values.
Figure 20. Supervisor Reset Generation
S Q
MCU
Clock
Sync
Noise Filter
VCC
PIN
PULL-UP
DELAY,
tRST_ACTV
R
AI09603
RESET_IN
RESET
to PSD Module
MCU_RESET
to MCU and
Peripherals
LVD
JTAG Debug
WDTuPSD33xx
66/231
Low VCC Voltage Detect, LVD
An internal reset is generated by the LVD circuit
when VCC drops below the reset threshold,
VLV_THRESH. After VCC returns to the reset threshold,
the MCU_RESET signal will remain asserted
for tRST_ACTV before it is released. The LVD circuit
is always enabled (cannot be disabled by SFR),
even in Idle Mode and Power-down Mode. The
LVD input has a voltage hysteresis of VRST_HYS
and will reject voltage spikes less than a duration
of tRST_FIL.
Important: The LVD voltage threshold is
VLV_THRESH, suitable for monitoring both the 3.3V
VCC supply on the MCU Module and the 3.3V VDD
supply on the PSD Module for 3.3V uPSD33xxV
devices, since these supplies are one in the same
on the circuit board.
However, for 5V uPSD33xx devices, VLV_THRESH
is not suitable for monitoring the 5V VDD voltage
supply (VLV_THRESH is too low), but good for monitoring
the 3.3V VCC supply. In the case of 5V
uPSD33xx devices, an external means is required
to monitor the separate 5V VDD supply, if desired.
Power-up Reset
At power up, the internal reset generated by the
LVD circuit is latched as a logic '1' in the POR bit
of the SFR named PCON (Table 24., page 50).
Software can read this bit to determine whether
the last MCU reset was the result of a power up
(cold reset) or a reset from some other condition
(warm reset). This bit must be cleared with software.
JTAG Debug Reset
The JTAG Debug Unit can generate a reset for debugging
purposes. This reset source is also available
when the MCU is in Idle Mode and PowerDown
Mode (the JTAG debugger can be used to
exit these modes).
Watchdog Timer, WDT
When enabled, the WDT will generate a reset
whenever it overflows. Firmware that is behaving
correctly will periodically clear the WDT before it
overflows. Run-away firmware will not be able to
clear the WDT, and a reset will be generated.
By default, the WDT is disabled after each reset.
Note: The WDT is not active during Idle mode or
Power-down Mode.
There are two SFRs that control the WDT, they are
WDKEY (Table 37., page 68) and WDRST (Table
38., page 68).
If WDKEY contains 55h, the WDT is disabled. Any
value other than 55h in WDKEY will enable the
WDT. By default, after any reset condition, WDKEY
is automatically loaded with 55h, disabling
the WDT. It is the responsibility of initialization
firmware to write some value other than 55h to
WDKEY after each reset if the WDT is to be used.
The WDT consists of a 24-bit up-counter (Figure
21), whose initial count is 000000h by default after
every reset. The most significant byte of this
counter is controlled by the SFR, WDRST. After
being enabled by WDKEY, the 24-bit count is increased
by 1 for each MCU machine cycle. When
the count overflows beyond FFFFFh (224 MCU
machine cycles), a reset is issued and the WDT is
automatically disabled (WDKEY = 55h again).
To prevent the WDT from timing out and generating
a reset, firmware must repeatedly write some
value to WDRST before the count reaches
FFFFFh. Whenever WDRST is written, the upper
8 bits of the 24-bit counter are loaded with the written
value, and the lower 16 bits of the counter are
cleared to 0000h.
The WDT time-out period can be adjusted by writing
a value other that 00h to WDRST. For example,
if WDRST is written with 04h, then the WDT
will start counting 040000h, 040001h, 040002h,
and so on for each MCU machine cycle. In this example,
the WDT time-out period is shorter than if
WDRST was written with 00h, because the WDT
is an up-counter. A value for WDRST should never
be written that results in a WDT time-out period
shorter than the time required to complete the
longest code task in the application, else unwanted
WDT overflows will occur.
Figure 21. Watchdog Counter
23 15 7 0
8-bits 8-bits 8-bits
SFR, WDRST AI0960467/231
uPSD33xx
The formula to determine WDT time-out period is:
WDTPERIOD = tMACH_CYC x NOVERFLOW
NOVERFLOW is the number of WDT up-counts required
to reach FFFFFFh. This is determined by
the value written to the SFR, WDRST.
tMACH_CYC is the average duration of one MCU
machine cycle. By default, an MCU machine cycle
is always 4 MCU_CLK periods for uPSD33xx, but
the following factors can sometimes add more
MCU_CLK periods per machine cycle:
– The number of MCU_CLK periods assigned to
MCU memory bus cycles as determined in the
SFR, BUSCON. If this setting is greater than
4, then machine cycles have additional
MCU_CLK periods during memory transfers.
– Whether or not the PFQ/BC circuitry issues a
stall during a particular MCU machine cycle. A
stall adds more MCU_CLK periods to a
machine cycle until the stall is removed.
tMACH_CYC is also affected by the absolute time of
a single MCU_CLK period. This number is fixed by
the following factors:
– Frequency of the external crystal, resonator,
or oscillator: (fOSC)
– Bit settings in the SFR CCON0, which can
divide fOSC and change MCU_CLK
As an example, assume the following:
1. fOSC is 40MHz, thus its period is 25ns.
2. CCON0 is 10h, meaning no clock division, so
the period of MCU_CLK is also 25ns.
3. BUSCON is C1h, meaning the PFQ and BC
are enabled, and each MCU memory bus
cycle is 4 MCU_CLK periods, adding no
additional MCU_CLK periods to MCU
machine cycles during memory transfers.
4. Assume there are no stalls from the PFQ/BC.
In reality, there are occational stalls but their
occurance has minimal impact on WDT
timeout period.
5. WDRST contains 00h, meaning a full 224 upcounts
are required to reach FFFFFh and
generate a reset.
In this example,
tMACH_CYC = 100ns (4 MCU_CLK periods x 25ns)
NOVERFLOW = 224 = 16777216 up-counts
WDTPERIOD = 100ns X 16777216 = 1.67 seconds
The actual value will be slightly longer due to PFQ/
BC.
Firmware Example: The following 8051 assembly
code illustrates how to operate the WDT. A
simple statement in the reset initialization firmware
enables the WDT, and then a periodic write to
clear the WDT in the main firmware is required to
keep the WDT from overflowing. This firmware is
based on the example above (40MHz fOSC,
CCON0 = 10h, BUSCON = C1h).
For example, in the reset initialization firmware
(the function that executes after a jump to the reset
vector):
Somewhere in the flow of the main program, this
statement will execute periodically to reset the
WDT before it’s time-out period of 1.67 seconds.
For example:
MOV AE, #AA ; enable WDT by writing value to
; WDKEY other than 55h
MOV A6, #00 ; reset WDT, loading 000000h.
; Counting will automatically
; resume as long as 55h in not in
; WDKEYuPSD33xx
68/231
Table 37. WDKEY: Watchdog Timer Key Register (SFR AEh, reset value 55h)
Table 38. WDRST: Watchdog Timer Reset Counter Register (SFR A6h, reset value 00h)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WDKEY[7:0]
Details
Bit Symbol R/W Definition
[7:0] WDKEY W
55h disables the WDT from counting. 55h is automatically loaded in this
SFR after any reset condition, leaving the WDT disabled by default.
Any value other than 55h written to this SFR will enable the WDT, and
counting begins.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WDRST[7:0]
Details
Bit Symbol R/W Definition
[7:0] WDRST W
This SFR is the upper byte of the 24-bit WDT up-counter. Writing this
SFR sets the upper byte of the counter to the written value, and clears
the lower two bytes of the counter to 0000h.
Counting begins when WDKEY does not contain 55h.69/231
uPSD33xx
STANDARD 8032 TIMER/COUNTERS
There are three 8032-style 16-bit Timer/Counter
registers (Timer 0, Timer 1, Timer 2) that can be
configured to operate as timers or event counters.
There are two additional 16-bit Timer/Counters in
the Programmable Counter Array (PCA), seePCA
Block, page 123 for details.
Standard Timer SFRs
Timer 0 and Timer 1 have very similar functions,
and they share two SFRs for control:
■ TCON (Table 39., page 70)
■ TMOD (Table 40., page 72).
Timer 0 has two SFRs that form the 16-bit counter,
or that can hold reload values, or that can scale
the clock depending on the timer/counter mode:
■ TH0 is the high byte, address 8Ch
■ TL0 is the low byte, address 8Ah
Timer 1 has two similar SFRs:
■ TH1 is the high byte, address 8Dh
■ TL1 is the low byte, address 8Bh
Timer 2 has one control SFR:
■ T2CON (Table 41., page 75)
Timer 2 has two SFRs that form the 16-bit counter,
and perform other functions:
■ TH2 is the high byte, address CDh
■ TL2 is the low byte, address CCh
Timer 2 has two SFRs for capture and reload:
■ RCAP2H is the high byte, address CBh
■ RCAP2L is the low byte, address CAh
Clock Sources
When enabled in the “Timer” function, the Registers
THx and TLx are incremented every 1/12 of
the oscillator frequency (fOSC). This timer clock
source is not effected by MCU clock dividers in the
CCON0, stalls from PFQ/BC, or bus transfer cycles.
Timers are always clocked at 1/12 of fOSC.
When enabled in the “Counter” function, the Registers
THx and TLx are incremented in response to
a 1-to-0 transition sampled at their corresponding
external input pin: pin C0 for Timer 0; pin C1 for
Timer 1; or pin T2 for Timer 2. In this function, the
external clock input pin is sampled by the counter
at a rate of 1/12 of fOSC. When a logic '1' is determined
in one sample, and a logic '0' in the next
sample period, the count is incremented at the
very next sample period (period1: sample=1,
period2: sample=0, period3: increment count
while continuing to sample). This means the maximum
count rate is 1/24 of the fOSC. There are no
restrictions on the duty cycle of the external input
signal, but to ensure that a given level is sampled
at least once before it changes, it should be active
for at least one full sample period (12 / fOSC, seconds).
However, if MCU_CLK is divided by the
SFR CCON0, then the sample period must be calculated
based on the resultant, longer, MCU_CLK
frequency. In this case, an external clock signal on
pins C0, C1, or T2 should have a duration longer
than one MCU machine cycle, tMACH_CYC. The
section, Watchdog Timer, WDT, page 66 explains
how to estimate tMACH_CYC.uPSD33xx
70/231
Table 39. TCON: Timer Control Register (SFR 88h, reset value 00h)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Details
Bit Symbol R/W Definition
7 TF1 R
Timer 1 overflow interrupt flag. Set by hardware upon overflow.
Automatically cleared by hardware after firmware services the interrupt
for Timer 1.
6 TR1 R,W Timer 1 run control. 1 = Timer/Counter 1 is on, 0 = Timer/Counter 1 is off.
5 TF0 R
Timer 0 overflow interrupt flag. Set by hardware upon overflow.
Automatically cleared by hardware after firmware services the interrupt
for Timer 0.
4 TR0 R,W Timer 0 run control. 1 = Timer/Counter 0 is on, 0 = Timer/Counter 0 is off.
3 IE1 R
Interrupt flag for external interrupt pin, EXTINT1. Set by hardware when
edge is detected on pin. Automatically cleared by hardware after
firmware services EXTINT1 interrupt.
2 IT1 R,W Trigger type for external interrupt pin EXTINT1. 1 = falling edge, 0 = lowlevel
1 IE0 R
Interrupt flag for external interrupt pin, EXTINT0. Set by hardware when
edge is detected on pin. Automatically cleared by hardware after
firmware services EXTINT0 interrupt.
0 IT0 R,W Trigger type for external interrupt pin EXTINT0. 1 = falling edge, 0 = lowlevel71/231
uPSD33xx
SFR, TCON
Timer 0 and Timer 1 share the SFR, TCON, that
controls these timers and provides information
about them. See Table 39., page 70.
Bits IE0 and IE1 are not related to Timer/Counter
functions, but they are set by hardware when a
signal is active on one of the two external interrupt
pins, EXTINT0 and EXTINT1. For system information
on all of these interrupts, see Table
16., page 41, Interrupt Summary.
Bits IT0 and IT1 are not related to Timer/Counter
functions, but they control whether or not the two
external interrupt input pins, EXTINT0 and
EXTINT1 are edge or level triggered.
SFR, TMOD
Timer 0 and Timer 1 have four modes of operation
controlled by the SFR named TMOD (Table 40).
Timer 0 and Timer 1 Operating Modes
The “Timer” or “Counter” function is selected by
the C/T control bits in TMOD. The four operating
modes are selected by bit-pairs M[1:0] in TMOD.
Modes 0, 1, and 2 are the same for both Timer/
Counters. Mode 3 is different.
Mode 0. Putting either Timer/Counter into Mode 0
makes it an 8-bit Counter with a divide-by-32 prescaler.
Figure 22 shows Mode 0 operation as it applies
to Timer 1 (same applies to Timer 0).
In this mode, the Timer Register is configured as a
13-bit register. As the count rolls over from all '1s'
to all '0s,' it sets the Timer Interrupt flag TF1. The
counted input is enabled to the Timer when
TR1 = 1 and either GATE = 0 or EXTINT1 = 1.
(Setting GATE = 1 allows the Timer to be controlled
by external input pin, EXTINT1, to facilitate
pulse width measurements). TR1 is a control bit in
the SFR, TCON. GATE is a bit in the SFR, TMOD.
The 13-bit register consists of all 8 bits of TH1 and
the lower 5 bits of TL1. The upper 3 bits of TL1 are
indeterminate and should be ignored. Setting the
run flag, TR1, does not clear the registers.
Mode 0 operation is the same for the Timer 0 as
for Timer 1. Substitute TR0, TF0, C0, TL0, TH0,
and EXTINT0 for the corresponding Timer 1 signals
in Figure 22. There are two different GATE
Bits, one for Timer 1 and one for Timer 0.
Mode 1. Mode 1 is the same as Mode 0, except
that the Timer Register is being run with all 16 bits.
Mode 2. Mode 2 configures the Timer Register as
an 8-bit Counter (TL1) with automatic reload, as
shown in Figure 23., page 73. Overflow from TL1
not only sets TF1, but also reloads TL1 with the
contents of TH1, which is preset with firmware.
The reload leaves TH1 unchanged. Mode 2 operation
is the same for Timer/Counter 0.
Mode 3. Timer 1 in Mode 3 simply holds its count.
The effect is the same as setting TR1 = 0.
Timer 0 in Mode 3 establishes TL0 and TH0 as two
separate counters. The logic for Mode 3 on Timer
0 is shown in Figure 24., page 73. TL0 uses the
Timer 0 control Bits: C/T, GATE, TR0, and TF0, as
well as the pin EXTINT0. TH0 is locked into a timer
function (counting at a rate of 1/12 fOSC) and takes
over the use of TR1 and TF1 from Timer 1. Thus,
TH0 now controls the “Timer 1“ interrupt flag.
Mode 3 is provided for applications requiring an
extra 8-bit timer on the counter (see Figure
24., page 73). With Timer 0 in Mode 3, a
uPSD33xx device can look like it has three Timer/
Counters (not including the PCA). When Timer 0 is
in Mode 3, Timer 1 can be turned on and off by
switching it out of and into its own Mode 3, or can
still be used by the serial port as a baud rate generator,
or in fact, in any application not requiring an
interrupt.uPSD33xx
72/231
Table 40. TMOD: Timer Mode Register (SFR 89h, reset value 00h)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GATE C/T M[1:0] GATE C/T M[1:0]
Details
Bit Symbol R/W Timer Definition (T/C is abbreviation for Timer/Counter)
7 GATE R,W
Timer 1
Gate control.
When GATE = 1, T/C is enabled only while pin EXTINT1
is '1' and the flag TR1 is '1.' When GATE = 0, T/C is
enabled whenever the flag TR1 is '1.'
6 C/T R,W
Counter or Timer function select.
When C/T = 0, function is timer, clocked by internal clock.
C/T = 1, function is counter, clocked by signal sampled on
external pin, C1.
[5:4] M[1:0] R,W
Mode Select.
00b = 13-bit T/C. 8 bits in TH1 with TL1 as 5-bit prescaler.
01b = 16-bit T/C. TH1 and TL1 are cascaded. No prescaler.
10b = 8-bit auto-reload T/C. TH1 holds a constant and
loads into TL1 upon overflow.
11b = Timer Counter 1 is stopped.
3 GATE R,W
Timer 0
Gate control.
When GATE = 1, T/C is enabled only while pin EXTINT0
is '1' and the flag TR0 is '1.' When GATE = 0, T/C is
enabled whenever the flag TR0 is '1.'
2 C/T R,W
Counter or Timer function select.
When C/T = 0, function is timer, clocked by internal clock.
C/T = 1, function is counter, clocked by signal sampled on
external pin, C0.
[1:0] M[1:0] R,W
Mode Select.
00b = 13-bit T/C. 8 bits in TH0 with TL0 as 5-bit prescaler.
01b = 16-bit T/C. TH0 and TL0 are cascaded. No prescaler.
10b = 8-bit auto-reload T/C. TH0 holds a constant and
loads into TL0 upon overflow.
11b = TL0 is 8-bit T/C controlled by standard Timer 0
control bits. TH0 is a separate 8-bit timer that uses Timer
1 control bits.73/231
uPSD33xx
Figure 22. Timer/Counter Mode 0: 13-bit Counter
Figure 23. Timer/Counter Mode 2: 8-bit Auto-reload
Figure 24. Timer/Counter Mode 3: Two 8-bit Counters
AI06622
f
OSC
TF1 Interrupt
Gate
TR1
EXTINT1 pin
C1 pin Control
TL1
(5 bits)
TH1
(8 bits)
C/T = 0
C/T = 1
÷ 12
AI06623
f
OSC
TF1 Interrupt
Gate
TR1
EXTINT1 pin
C1 pin Control
TL1
(8 bits)
TH1
(8 bits)
C/T = 0
C/T = 1
÷ 12
AI06624
f
OSC
TF0 Interrupt
Gate
TR0
EXTINT0 pin
C0 pin Control
TL0
(8 bits)
C/T = 0
C/T = 1
÷ 12
f
OSC TF1 Interrupt
Control
TH0
(8 bits) ÷ 12
TR1uPSD33xx
74/231
Timer 2
Timer 2 can operate as either an event timer or as
an event counter. This is selected by the bit C/T2
in the SFR named, T2CON (Table 41., page 75).
Timer 2 has three operating modes selected by
bits in T2CON, according to Table 42., page 76.
The three modes are:
■ Capture mode
■ Auto re-load mode
■ Baud rate generator mode
Capture Mode. In Capture Mode there are two
options which are selected by the bit EXEN2 in
T2CON. Figure 25., page 79 illustrates Capture
mode.
If EXEN2 = 0, then Timer 2 is a 16-bit timer if C/T2
= 0, or it’s a 16-bit counter if C/T2 = 1, either of
which sets the interrupt flag bit TF2 upon overflow.
If EXEN2 = 1, then Timer 2 still does the above,
but with the added feature that a 1-to-0 transition
at external input pin T2X causes the current value
in the Timer 2 registers, TL2 and TH2, to be captured
into Registers RCAP2L and RCAP2H, respectively.
In addition, the transition at T2X
causes interrupt flag bit EXF2 in T2CON to be set.
Either flag TF2 or EXF2 will generate an interrupt
and the MCU must read both flags to determine
the cause. Flags TF2 and EXF2 are not automatically
cleared by hardware, so the firmware servicing
the interrupt must clear the flag(s) upon exit of
the interrupt service routine.
Auto-reload Mode. In the Auto-reload Mode,
there are again two options, which are selected by
the bit EXEN2 in T2CON. Figure 26., page 79
shows Auto-reload mode.
If EXEN2 = 0, then when Timer 2 counts up and
rolls over from FFFFh it not only sets the interrupt
flag TF2, but also causes the Timer 2 registers to
be reloaded with the 16-bit value contained in
Registers RCAP2L and RCAP2H, which are preset
with firmware.
If EXEN2 = 1, then Timer 2 still does the above,
but with the added feature that a 1-to-0 transition
at external input T2X will also trigger the 16-bit reload
and set the interrupt flag EXF2. Again, firmware
servicing the interrupt must read both TF2
and EXF2 to determine the cause, and clear the
flag(s) upon exit.
Note: The uPSD33xx does not support selectable
up/down counting in Auto-reload mode (this feature
was an extension to the original 8032 architecture).75/231
uPSD33xx
Table 41. T2CON: Timer 2 Control Register (SFR C8h, reset value 00h)
Note: 1. The RCLK1 and TCLK1 Bits in the SFR named PCON control UART1, and have the exact same function as RCLK and TCLK.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
Details
Bit Symbol R/W Definition
7 TF2 R,W
Timer 2 flag, causes interrupt if enabled.
TF2 is set by hardware upon overflow. Must be cleared by firmware. TF2
will not be set when either RCLK or TCLK =1.
6 EXF2 R,W
Timer 2 flag, causes interrupt if enabled.
EXF2 is set when a capture or reload is caused by a negative transition
on T2X pin and EXEN2 = 1. EXF2 must be cleared by firmware.
5 RCLK(1) R,W
UART0 Receive Clock control.
When RCLK = 1, UART0 uses Timer 2 overflow pulses for its receive
clock in Modes 1 and 3. RCLK=0, Timer 1 overflow is used for its receive
clock
4 TCLK(1) R,W
UART0 Transmit Clock control.
When TCLK = 1, UART0 uses Timer 2 overflow pulses for its transmit
clock in Modes 1 and 3. TCLK=0, Timer 1 overflow is used for transmit
clock
3 EXEN2 R,W
Timer 2 External Enable.
When EXEN2 = 1, capture or reload results when negative edge on pin
T2X occurs. EXEN2 = 0 causes Timer 2 to ignore events at pin T2X.
2 TR2 R,W
Timer 2 run control.
1 = Timer/Counter 2 is on, 0 = Timer Counter 2 is off.
1 C/T2 R,W
Counter or Timer function select.
When C/T2 = 0, function is timer, clocked by internal clock. When C/T2 =
1, function is counter, clocked by signal sampled on external pin, T2.
0 CP/RL2 R,W
Capture/Reload.
When CP/RL2 = 1, capture occurs on negative transition at pin T2X if
EXEN2 = 1. When CP/RL2 = 0, auto-reload occurs when Timer 2
overflows, or on negative transition at pin T2X when EXEN2=1. When
RCLK = 1 or TCLK = 1, CP/RL2 is ignored, and Timer 2 is forced to autoreload
upon Timer 2 overflowuPSD33xx
76/231
Table 42. Timer/Counter 2 Operating Modes
Note: ↓ = falling edge
Mode
Bits in T2CON SFR
Pin
T2X Remarks
Input Clock
RCLK
or
TCLK
CP/
RL2 TR2 EXEN2 Timer,
Internal
Counter,
External
(Pin T2,
P1.0)
16-bit
Autoreload
001 0 x reload [RCAP2H, RCAP2L] to [TH2,
TL2] upon overflow (up counting) fOSC/12 MAX
fOSC/24
001 1 ↓ reload [RCAP2H, RCAP2L] to [TH2,
TL2] at falling edge on pin T2X
16-bit
Capture
0 1 1 0 x 16-bit Timer/Counter (up counting)
fOSC/12 MAX
fOSC/24 011 1 ↓
Capture [TH2, TL2] and store to
[RCAP2H, RCAP2L] at falling edge on
pin T2X
Baud Rate
Generator
1 x 1 0 x No overflow interrupt request (TF2)
fOSC/2 – 1x1 1 ↓ Extra Interrupt on pin T2X, sets TF2
Off x x 0 x x Timer 2 stops – –77/231
uPSD33xx
Baud Rate Generator Mode. The RCLK and/or
TCLK Bits in the SFR T2CON allow the transmit
and receive baud rates on serial port UART0 to be
derived from either Timer 1 or Timer 2. Figure
27., page 80 illustrates Baud Rate Generator
Mode.
When TCLK = 0, Timer 1 is used as UART0’s
transmit baud generator. When TCLK = 1, Timer 2
will be the transmit baud generator. RCLK has the
same effect for UART0’s receive baud rate. With
these two bits, UART0 can have different receive
and transmit baud rates - one generated by Timer
1, the other by Timer 2.
Note: Bits RCLK1 and TCLK1 in the SFR named
PCON (see PCON: Power Control Register (SFR
87h, reset value 00h), page 50) have identical
functions as RCLK and TCLK but they apply to
UART1 instead. For simplicity in the following discussions
about baud rate generation, no suffix will
be used when referring to SFR registers and bits
related to UART0 or UART1, since each UART interface
has identical operation. Example, TCLK or
TCLK1 will be referred to as just TCLK.
The Baud Rate Generator Mode is similar to the
Auto-reload Mode, in that a roll over in TH2 causes
the Timer 2 registers, TH2 and TL2, to be reloaded
with the 16-bit value in Registers RCAP2H and
RCAP2L, which are preset with firmware.
The baud rates in UART Modes 1 and 3 are determined
by Timer 2’s overflow rate as follows:
UART Mode 1,3 Baud Rate =
Timer 2 Overflow Rate / 16
The timer can be configured for either “timer” or
“counter” operation. In the most typical applications,
it is configured for “timer” operation (C/T2 =
0). “Timer” operation is a little different for Timer 2
when it's being used as a baud rate generator. In
this case, the baud rate is given by the formula:
UART Mode 1,3 Baud Rate =
fOSC/(32 x [65536 – [RCAP2H, RCAP2L]))
where [RCAP2H, RCAP2L] is the content of the
SFRs RCAP2H and RCAP2L taken as a 16-bit unsigned
integer.
A roll-over in TH2 does not set TF2, and will not
generate an interrupt. Therefore, the Timer Interrupt
does not have to be disabled when Timer 2 is
in the Baud Rate Generator Mode.
If EXEN2 is set, a 1-to-0 transition on pin T2X will
set the Timer 2 interrupt flag EXF2, but will not
cause a reload from RCAP2H and RCAP2L to
TH2 and TL2. Thus when Timer 2 is in use as a
baud rate generator, the pin T2X can be used as
an extra external interrupt, if desired.
When Timer 2 is running (TR2 = 1) in a “timer”
function in the Baud Rate Generator Mode, firmware
should not read or write TH2 or TL2. Under
these conditions the results of a read or write may
not be accurate. However, SFRs RCAP2H and
RCAP2L may be read, but should not be written,
because a write might overlap a reload and cause
write and/or reload errors. Timer 2 should be
turned off (clear TR2) before accessing Timer 2 or
Registers RCAP2H and RCAP2L, in this case.
Table 43., page 78 shows commonly used baud
rates and how they can be obtained from Timer 2,
with T2CON = 34h.uPSD33xx
78/231
Table 43. Commonly Used Baud Rates Generated from Timer2 (T2CON = 34h)
fOSC MHz Desired
Baud Rate
Timer 2 SFRs Resulting
Baud Rate
Baud Rate
Deviation RCAP2H (hex) RCAP2L(hex)
40.0 115200 FF F5 113636 -1.36%
40.0 57600 FF EA 56818 -1.36%
40.0 28800 FF D5 29070 0.94%
40.0 19200 FF BF 19231 0.16%
40.0 9600 FF 7E 9615 0.16%
36.864 115200 FF F6 115200 0
36.864 57600 FF EC 57600 0
36.864 28800 FF D8 28800 0
36.864 19200 FF C4 19200 0
36.864 9600 FF 88 9600 0
36.0 28800 FF D9 28846 0.16%
36.0 19200 FF C5 19067 -0.69%
36.0 9600 FF 8B 9615 0.16%
24.0 57600 FF F3 57692 0.16%
24.0 28800 FF E6 28846 0.16%
24.0 19200 FF D9 19231 0.16%
24.0 9600 FF B2 9615 0.16%
12.0 28800 FF F3 28846 0.16%
12.0 9600 FF D9 9615 0.16%
11.0592 115200 FF FD 115200 0
11.0592 57600 FF FA 57600 0
11.0592 28800 FF F4 28800 0
11.0592 19200 FF EE 19200 0
11.0592 9600 FF DC 9600 0
3.6864 115200 FF FF 115200 0
3.6864 57600 FF FE 57600 0
3.6864 28800 FF FC 28800 0
3.6864 19200 FF FA 19200 0
3.6864 9600 FF F4 9600 0
1.8432 19200 FF FD 19200 0
1.8432 9600 FF FA 9600 079/231
uPSD33xx
Figure 25. Timer 2 in Capture Mode
Figure 26. Timer 2 in Auto-Reload Mode
AI06625
f
OSC
TF2
Capture
TR2
T2 pin Control
TL2
(8 bits)
TH2
(8 bits)
C/T2 = 0
C/T2 = 1
÷ 12
EXP2
Control
EXEN2
RCAP2L RCAP2H
T2X pin
Timer 2
Interrupt
Transition
Detector
AI06626
f
OSC
TF2
Reload
TR2
T2 pin Control
TL2
(8 bits)
TH2
(8 bits)
C/T2 = 0
C/T2 = 1
÷ 12
EXP2
Control
EXEN2
RCAP2L RCAP2H
T2X pin
Timer 2
Interrupt
Transition
DetectoruPSD33xx
80/231
Figure 27. Timer 2 in Baud Rate Generator Mode
AI09605
f
OSC
Reload
TR2
T2 pin Control
Note: Oscillator frequency is divided by 2,
not 12 like in other timer modes.
Note: Availability of additional external interrupt.
TL2
(8 bits)
TH2
(8 bits)
C/T2 = 0
C/T2 = 1
÷ 12
÷ 2
÷ 16
÷ 16
EXF2
Control
EXEN2
RCAP2L RCAP2H
T2X pin Timer 2 Interrupt
TX CLK
RX CLK
Timer 1 Overflow
SMOD
RCLK
'1' '0'
'0' '1'
'1' '0'
TCLK
Transition
Detector81/231
uPSD33xx
SERIAL UART INTERFACES
uPSD33xx devices provide two standard 8032
UART serial ports.
– The first port, UART0, is connected to pins
RxD0 (P3.0) and TxD0 (P3.1)
– The second port, UART1 is connected to pins
RxD1 (P1.2) and TxD1 (P1.3). UART1 can
optionally be routed to pins P4.2 and P4.3 as
described in Alternate Functions, page 59.
The operation of the two serial ports are the same
and are controlled by two SFRs:
■ SCON0 (Table 45., page 82) for UART0
■ SCON1 (Table 46., page 83) for UART1
Each UART has its own data buffer accessed
through an SFR listed below:
■ SBUF0 for UART0, address 99h
■ SBUF1 for UART1, address D9h
When writing SBU0 or SBUF1, the data automatically
loads into the associated UART transmit data
register. When reading this SFR, data comes from
a different physical register, which is the receive
register of the associated UART.
Note: For simplicity in the remaining UART discussions,
the suffix “0” or “1” will be dropped when
referring to SFR registers and bits related to
UART0 or UART1, since each UART interface has
identical operation. Example, SBUF0 and SBUF1
will be referred to as just SBUF.
Each UART serial port can be full-duplex, meaning
it can transmit and receive simultaneously. Each
UART is also receive-buffered, meaning it can
commence reception of a second byte before a
previously received byte has been read from the
SBUF Register. However, if the first byte still has
not been read by the time reception of the second
byte is complete, one of the bytes will be lost.
UART Operation Modes
Each UART can operate in one of four modes, one
mode is synchronous, and the others are asynchronous
as shown in Table 44.
Mode 0. Mode 0 provides asynchronous, half-duplex
operation. Serial data is both transmitted, and
received on the RxD pin. The TxD pin outputs a
shift clock for both transmit and receive directions,
thus the MCU must be the master. Eight bits are
transmitted/received LSB first. The baud rate is
fixed at 1/12 of fOSC.
Mode 1. Mode 1 provides standard asynchronous,
full-duplex communication using a total of 10
bits per data byte. Data is transmitted through TxD
and received through RxD with: a Start Bit (logic
'0'), eight data bits (LSB first), and a Stop Bit (logic
'1'). Upon receive, the eight data bits go into the
SFR SBUF, and the Stop Bit goes into bit RB8 of
the SFR SCON. The baud rate is variable and derived
from overflows of Timer 1 or Timer 2.
Mode 2. Mode 2 provides asynchronous, full-duplex
communication using a total of 11 bits per
data byte. Data is transmitted through TxD and received
through RxD with: a Start Bit (logic '0');
eight data bits (LSB first); a programmable 9th
data bit; and a Stop Bit (logic '1'). Upon Transmit,
the 9th data bit (from bit TB8 in SCON) can be assigned
the value of '0' or '1.' Or, for example, the
Parity Bit (P, in the PSW) could be moved into
TB8. Upon receive, the 9th data bit goes into RB8
in SCON, while the Stop Bit is ignored. The baud
rate is programmable to either 1/32 or 1/64 of
fOSC.
Mode 3. Mode 3 is the same as Mode 2 in all respects
except the baud rate is variable like it is in
Mode 1.
In all four modes, transmission is initiated by any
instruction that uses SBUF as a destination register.
Reception is initiated in Mode 0 by the condition
RI = 0 and REN = 1. Reception is initiated in
the other modes by the incoming Start Bit if
REN = 1.
Table 44. UART Operating Modes
Mode Synchronization
Bits of SFR,
SCON Baud Clock Data
Bits Start/Stop Bits See Figure
SM0 SM1
0 Synchronous 0 0 fOSC/12 8 None Figure
28., page 86
1 Asynchronous 0 1 Timer 1 or Timer 2 Overflow 8 1 Start, 1 Stop Figure
30., page 88
2 Asynchronous 1 0 fOSC/32 or fOSC/64 9 1 Start, 1 Stop Figure
32., page 90
3 Asynchronous 1 1 Timer 1 or Timer 2 Overflow 9 1 Start, 1 Stop Figure
34., page 91uPSD33xx
82/231
Multiprocessor Communications. Modes 2 and
3 have a special provision for multiprocessor communications.
In these modes, 9 data bits are received.
The 9th one goes into bit RB8, then comes
a stop bit. The port can be programmed such that
when the stop bit is received, the UART interrupt
will be activated only if bit RB8 = 1. This feature is
enabled by setting bit SM2 in SCON. A way to use
this feature in multi-processor systems is as follows:
When the master processor wants to transmit
a block of data to one of several slaves, it first
sends out an address byte which identifies the target
slave. An address byte differs from a data byte
in that the 9th bit is 1 in an address byte and 0 in a
data byte. With SM2 = 1, no slave will be interrupted
by a data byte. An address byte, however, will
interrupt all slaves, so that each slave can examine
the received byte and see if it is being addressed.
The addressed slave will clear its SM2 bit
and prepare to receive the data bytes that will be
coming. The slaves that were not being addressed
leave their SM2 bits set and go on about their business,
ignoring the coming data bytes.
SM2 has no effect in Mode 0, and in Mode 1, SM2
can be used to check the validity of the stop bit. In
a Mode 1 reception, if SM2 = 1, the receive interrupt
will not be activated unless a valid stop bit is
received.
Serial Port Control Registers
The SFR SCON0 controls UART0, and SCON1
controls UART1, shown in Table 45 and Table 46.
These registers contain not only the mode selection
bits, but also the 9th data bit for transmit and
receive (bits TB8 and RB8), and the UART Interrupt
flags, TI and RI.
Table 45. SCON0: Serial Port UART0 Control Register (SFR 98h, reset value 00h)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SM0 SM1 SM2 REN TB8 RB8 TI RI
Details
Bit Symbol R/W Definition
7 SM0 R,W Serial Mode Select, See Table 44., page 81. Important, notice bit order
of SM0 and SM1.
[SM0:SM1] = 00b, Mode 0
[SM0:SM1] = 01b, Mode 1
[SM0:SM1] = 10b, Mode 2
[SM0:SM1] = 11b, Mode 3
6 SM1 R,W
5 SM2 R,W
Serial Multiprocessor Communication Enable.
Mode 0: SM2 has no effect but should remain 0.
Mode 1: If SM2 = 0 then stop bit ignored. SM2 =1 then RI active if stop
bit = 1.
Mode 2 and 3: Multiprocessor Comm Enable. If SM2=0, 9th bit is
ignored. If SM2=1, RI active when 9th bit = 1.
4 REN R,W
Receive Enable.
If REN=0, UART reception disabled. If REN=1, reception is enabled
3 TB8 R,W TB8 is assigned to the 9th transmission bit in Mode 2 and 3. Not used in
Mode 0 and 1.
2 RB8 R,W
Mode 0: RB8 is not used.
Mode 1: If SM2 = 0, the RB8 is the level of the received stop bit.
Mode 2 and 3: RB8 is the 9th data bit that was received in Mode 2 and
3.
1 TI R,W
Transmit Interrupt flag.
Causes interrupt at end of 8th bit time when transmitting in Mode 0, or at
beginning of stop bit transmission in other modes. Must clear flag with
firmware.
0 RI R,W
Receive Interrupt flag.
Causes interrupt at end of 8th bit time when receiving in Mode 0, or
halfway through stop bit reception in other modes (see SM2 for
exception). Must clear this flag with firmware.83/231
uPSD33xx
Table 46. SCON1: Serial Port UART1 Control Register (SFR D8h, reset value 00h)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SM0 SM1 SM2 REN TB8 RB8 TI RI
Details
Bit Symbol R/W Definition
7 SM0 R,W Serial Mode Select, See Table 44., page 81. Important, notice bit order
of SM0 and SM1.
[SM0:SM1] = 00b, Mode 0
[SM0:SM1] = 01b, Mode 1
[SM0:SM1] = 10b, Mode 2
[SM0:SM1] = 11b, Mode 3
6 SM1 R,W
5 SM2 R,W
Serial Multiprocessor Communication Enable.
Mode 0: SM2 has no effect but should remain 0.
Mode 1: If SM2 = 0 then stop bit ignored. SM2 =1 then RI active if stop
bit = 1.
Mode 2 and 3: Multiprocessor Comm Enable. If SM2=0, 9th bit is
ignored. If SM2=1, RI active when 9th bit = 1.
4 REN R,W
Receive Enable.
If REN=0, UART reception disabled. If REN=1, reception is enabled
3 TB8 R,W TB8 is assigned to the 9th transmission bit in Mode 2 and 3. Not used in
Mode 0 and 1.
2 RB8 R,W
Mode 0: RB8 is not used.
Mode 1: If SM2 = 0, the RB8 is the level of the received stop bit.
Mode 2 and 3: RB8 is the 9th data bit that was received in Mode 2 and
3.
1 TI R,W
Transmit Interrupt flag.
Causes interrupt at end of 8th bit time when transmitting in Mode 0, or at
beginning of stop bit transmission in other modes. Must clear flag with
firmware.
0 RI R,W
Receive Interrupt flag.
Causes interrupt at end of 8th bit time when receiving in Mode 0, or
halfway through stop bit reception in other modes (see SM2 for
exception). Must clear this flag with firmware.uPSD33xx
84/231
UART Baud Rates
The baud rate in Mode 0 is fixed:
Mode 0 Baud Rate = fOSC / 12
The baud rate in Mode 2 depends on the value of
the bit SMOD in the SFR named PCON. If SMOD
= 0 (default value), the baud rate is 1/64 the oscillator
frequency, fOSC. If SMOD = 1, the baud rate
is 1/32 the oscillator frequency.
Mode 2 Baud Rate = (2SMOD / 64) x fOSC
Baud rates in Modes 1 and 3 are determined by
the Timer 1 or Timer 2 overflow rate.
Using Timer 1 to Generate Baud Rates. When
Timer 1 is used as the baud rate generator (bits
RCLK = 0, TCLK = 0), the baud rates in Modes 1
and 3 are determined by the Timer 1 overflow rate
and the value of SMOD as follows:
Mode 1,3 Baud Rate =
(2SMOD / 32) x (Timer 1 overflow rate)
The Timer 1 Interrupt should be disabled in this
application. The Timer itself can be configured for
either “timer” or “counter” operation, and in any of
its 3 running modes. In the most typical applications,
it is configured for “timer” operation, in the
Auto-reload Mode (high nibble of the SFR TMOD
= 0010B). In that case the baud rate is given by the
formula:
Mode 1,3 Baud Rate =
(2SMOD / 32) x (fOSC / (12 x [256 – (TH1)]))
Table 47 lists various commonly used baud rates
and how they can be obtained from Timer 1.
Using Timer/Counter 2 to Generate Baud
Rates. See Baud Rate Generator
Mode, page 77.
Table 47. Commonly Used Baud Rates Generated from Timer 1
UART Mode fOSC MHz Desired
Baud Rate
Resultant
Baud Rate
Baud Rate
Deviation
SMOD
bit in
PCON
Timer 1
C/T Bit
in TMOD
Timer
Mode in
TMOD
TH1
Reload
value (hex)
Mode 0 Max 40.0 3.33MHz 3.33MHz 0 X X X X
Mode 2 Max 40.0 1250 k 1250 k 0 1 X X X
Mode 2 Max 40.0 625 k 625 k 0 0 X X X
Modes 1 or 3 40.0 19200 18939 -1.36% 1 0 2 F5
Modes 1 or 3 40.0 9600 9470 -1.36% 1 0 2 EA
Modes 1 or 3 36.0 19200 18570 -2.34% 1 0 2 F6
Modes 1 or 3 33.333 57600 57870 0.47% 1 0 2 FD
Modes 1 or 3 33.333 28800 28934 0.47% 1 0 2 FA
Modes 1 or 3 33.333 19200 19290 0.47% 1 0 2 F7
Modes 1 or 3 33.333 9600 9645 0.47% 1 0 2 EE
Modes 1 or 3 24.0 9600 9615 0.16% 1 0 2 F3
Modes 1 or 3 12.0 4800 4808 0.16% 1 0 2 F3
Modes 1 or 3 11.0592 57600 57600 0 1 0 2 FF
Modes 1 or 3 11.0592 28800 28800 0 1 0 2 FE
Modes 1 or 3 11.0592 19200 19200 0 1 0 2 FD
Modes 1 or 3 11.0592 9600 9600 0 1 0 2 FA
Modes 1 or 3 3.6864 19200 19200 0 1 0 2 FF
Modes 1 or 3 3.6864 9600 9600 0 1 0 2 FE
Modes 1 or 3 1.8432 9600 9600 0 1 0 2 FF
Modes 1 or 3 1.8432 4800 4800 0 1 0 2 FE85/231
uPSD33xx
More About UART Mode 0
Refer to the block diagram in Figure 28., page 86,
and timing diagram in Figure 29., page 86.
Transmission is initiated by any instruction which
writes to the SFR named SBUF. At the end of a
write operation to SBUF, a 1 is loaded into the 9th
position of the transmit shift register and tells the
TX Control unit to begin a transmission. Transmission
begins on the following MCU machine cycle,
when the “SEND” signal is active in Figure 29.
SEND enables the output of the shift register to the
alternate function on the port containing pin RxD,
and also enables the SHIFT CLOCK signal to the
alternate function on the port containing the pin,
TxD. At the end of each SHIFT CLOCK in which
SEND is active, the contents of the transmit shift
register are shifted to the right one position.
As data bits shift out to the right, zeros come in
from the left. When the MSB of the data byte is at
the output position of the shift register, then the '1'
that was initially loaded into the 9th position, is just
to the left of the MSB, and all positions to the left
of that contain zeros. This condition flags the TX
Control unit to do one last shift, then deactivate
SEND, and then set the interrupt flag TI. Both of
these actions occur at S1P1.
Reception is initiated by the condition REN = 1 and
RI = 0. At the end of the next MCU machine cycle,
the RX Control unit writes the bits 11111110 to the
receive shift register, and in the next clock phase
activates RECEIVE. RECEIVE enables the SHIFT
CLOCK signal to the alternate function on the port
containing the pin, TxD. Each pulse of SHIFT
CLOCK moves the contents of the receive shift
register one position to the left while RECEIVE is
active. The value that comes in from the right is the
value that was sampled at the RxD pin. As data
bits come in from the right, 1s shift out to the left.
When the 0 that was initially loaded into the rightmost
position arrives at the left-most position in the
shift register, it flags the RX Control unit to do one
last shift, and then it loads SBUF. After this, RECEIVE
is cleared, and the receive interrupt flag RI
is set.uPSD33xx
86/231
Figure 28. UART Mode 0, Block Diagram
Figure 29. UART Mode 0, Timing Diagram
AI06824
Zero Detector
Internal Bus
Tx Control
Rx Control
Internal Bus
SBUF
Write
to
SBUF
Read
SBUF
Load
SBUF
SBUF
Input Shift Register
Shift
Shift
Clock
Serial
Port
Interrupt
f
OSC/12
REN
R1
Rx Clock
Start
Tx Clock
Start Shift
Shift
Send
Receive
T
R
CL
D S Q
7 6 5 4 3 2 1 0
RxD
P3.0 Alt
Input
Function
RxD
Pin
TxD
Pin
AI06825
Write to SBUF
Send
Shift
RxD (Data Out)
TxD (Shift Clock)
TI
Write to SCON
RI
Receive
Shift
RxD (Data In)
TxD (Shift Clock)
Clear RI
Receive
Transmit D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D787/231
uPSD33xx
More About UART Mode 1
Refer to the block diagram in Figure 30., page 88,
and timing diagram in Figure 31., page 88.
Transmission is initiated by any instruction which
writes to SBUF. At the end of a write operation to
SBUF, a '1' is loaded into the 9th position of the
transmit shift register and flags the TX Control unit
that a transmission is requested. Transmission actually
starts at the end of the MCU the machine cycle
following the next rollover in the divide-by-16
counter. Thus, the bit times are synchronized to
the divide-by-16 counter, not to the writing of
SBUF. Transmission begins with activation of
SEND which puts the start bit at pin TxD. One bit
time later, DATA is activated, which enables the
output bit of the transmit shift register to pin TxD.
The first shift pulse occurs one bit time after that.
As data bits shift out to the right, zeros are clocked
in from the left. When the MSB of the data byte is
at the output position of the shift register, then the
1 that was initially loaded into the 9th position is
just to the left of the MSB, and all positions to the
left of that contain zeros. This condition flags the
TX Control unit to do one last shift and then deactivates
SEND, and sets the interrupt flag, TI. This
occurs at the 10th divide-by-16 rollover after a
write to SBUF.
Reception is initiated by a detected 1-to-0 transition
at the pin RxD. For this purpose RxD is sampled
at a rate of 16 times whatever baud rate has
been established. When a transition is detected,
the divide-by-16 counter is immediately reset, and
1FFH is written into the input shift register. Resetting
the divide-by-16 counter aligns its rollovers
with the boundaries of the incoming bit times. The
16 states of the counter divide each bit time into
16ths. At the 7th, 8th, and 9th counter states of
each bit time, the bit detector samples the value of
RxD. The value accepted is the value that was
seen in at least 2 of the 3 samples. This is done for
noise rejection. If the value accepted during the
first bit time is not '0,' the receive circuits are reset
and the unit goes back to looking for another '1'-to-
'0' transition. This is to provide rejection of false
start bits. If the start bit proves valid, it is shifted
into the input shift register, and reception of the reset
of the rest of the frame will proceed. As data
bits come in from the right, '1s' shift out to the left.
When the start bit arrives at the left-most position
in the shift register (which in mode 1 is a 9-bit register),
it flags the RX Control unit to do one last
shift, load SBUF and RB8, and set the receive interrupt
flag RI. The signal to load SBUF and RB8,
and to set RI, will be generated if, and only if, the
following conditions are met at the time the final
shift pulse is generated:
1. RI = 0, and
2. Either SM2 = 0, or the received stop bit = 1.
If either of these two conditions are not met, the received
frame is irretrievably lost. If both conditions
are met, the stop bit goes into RB8, the 8 data bits
go into SBUF, and RI is activated. At this time,
whether the above conditions are met or not, the
unit goes back to looking for a '1'-to-'0' transition
on pin RxD.uPSD33xx
88/231
Figure 30. UART Mode 1, Block Diagram
Figure 31. UART Mode 1, Timing Diagram
AI06826
Zero Detector
Internal Bus
Tx Control
Rx Control
Internal Bus
SBUF
Write
to
SBUF
Read
SBUF
Load
SBUF
SBUF
Input Shift Register
Shift
Serial
Port
Interrupt
Rx Clock
Start
Tx Clock
Start Shift
Shift
Send
Load SBUF
TI
RI
CL
D S Q
1FFh
TxD
Pin
Data
Rx Detector
RxD
Pin
1-to-0
Transition
Detector
÷16
Sample
÷16
÷2
TB8
Timer1
Overflow
Timer2
Overflow
0
0 1
1
0 1
TCLK
RCLK
SMOD
AI06843
Write to SBUF
Data
Shift
TxD
TI
Rx Clock
RxD
Bit Detector
Sample Times
Shift
RI
Receive
Transmit
D0 D1 D2 D3 D4 D5 D6 D7
Send
Tx Clock
Start Bit
Stop Bit
D0 D1 D2 D3 D4 D5 D6 D7
Start Bit
Stop Bit89/231
uPSD33xx
More About UART Modes 2 and 3
For Mode 2, refer to the block diagram in Figure
32., page 90, and timing diagram in Figure
33., page 90. For Mode 3, refer to the block diagram
in Figure 34., page 91, and timing diagram in
Figure 35., page 91.
Keep in mind that the baud rate is programmable
to either 1/32 or 1/64 of fOSC in Mode 2, but Mode
3 uses a variable baud rate generated from Timer
1 or Timer 2 rollovers.
The receive portion is exactly the same as in Mode
1. The transmit portion differs from Mode 1 only in
the 9th bit of the transmit shift register.
Transmission is initiated by any instruction which
writes to SBUF. At the end of a write operation to
SBUF, the TB8 Bit is loaded into the 9th position of
the transmit shift register and flags the TX Control
unit that a transmission is requested. Transmission
actually starts at the end of the MCU the machine
cycle following the next rollover in the divideby-16
counter. Thus, the bit times are synchronized
to the divide-by-16 counter, not to the writing
of SBUF. Transmission begins with activation of
SEND which puts the start bit at pin TxD. One bit
time later, DATA is activated, which enables the
output bit of the transmit shift register to pin TxD.
The first shift pulse occurs one bit time after that.
The first shift clocks a '1' (the stop bit) into the 9th
bit position of the shift register. There-after, only
zeros are clocked in. Thus, as data bits shift out to
the right, zeros are clocked in from the left. When
bit TB8 is at the output position of the shift register,
then the stop bit is just to the left of TB8, and all positions
to the left of that contain zeros. This condition
flags the TX Control unit to do one last shift
and then deactivate SEND, and set the interrupt
flag, TI. This occurs at the 11th divide-by 16 rollover
after writing to SBUF.
Reception is initiated by a detected 1-to-0 transition
at pin RxD. For this purpose RxD is sampled
at a rate of 16 times whatever baud rate has been
established. When a transition is detected, the divide-by-16
counter is immediately reset, and 1FFH
is written to the input shift register. At the 7th, 8th,
and 9th counter states of each bit time, the bit detector
samples the value of RxD. The value accepted
is the value that was seen in at least 2 of
the 3 samples. If the value accepted during the
first bit time is not '0,' the receive circuits are reset
and the unit goes back to looking for another '1'-to-
'0' transition. If the start bit proves valid, it is shifted
into the input shift register, and reception of the
rest of the frame will proceed. As data bits come in
from the right, '1s' shift out to the left. When the
start bit arrives at the left-most position in the shift
register (which in Modes 2 and 3 is a 9-bit register),
it flags the RX Control unit to do one last shift,
load SBUF and RB8, and set the interrupt flag RI.
The signal to load SBUF and RB8, and to set RI,
will be generated if, and only if, the following conditions
are met at the time the final shift pulse is
generated:
1. RI = 0, and
2. Either SM2 = 0, or the received 9th data bit = 1.
If either of these conditions is not met, the received
frame is irretrievably lost, and RI is not set. If both
conditions are met, the received 9th data bit goes
into RB8, and the first 8 data bits go into SBUF.
One bit time later, whether the above conditions
were met or not, the unit goes back to looking for
a '1'-to-'0' transition on pin RxD.uPSD33xx
90/231
Figure 32. UART Mode 2, Block Diagram
Figure 33. UART Mode 2, Timing Diagram
AI06844
Zero Detector
Internal Bus
Tx Control
Rx Control
Internal Bus
SBUF
Write
to
SBUF
Read
SBUF
Load
SBUF
SBUF
Input Shift Register
Shift
Serial
Port
Interrupt
Rx Clock
Start
Tx Clock
Start Shift
Shift
Send
Load SBUF
TI
RI
CL
D S Q
1FFh
TxD
Pin
Data
Rx Detector
RxD
Pin
1-to-0
Transition
Detector
÷16
Sample
÷16
÷2
TB8
f
OSC/32
0 1
SMOD
AI06845
Write to SBUF
Data
Shift
TxD
TI
Rx Clock
RxD
Bit Detector
Sample Times
Shift
RI
Receive
Transmit
D0 D1 D2 D3 D4 D5 D6 D7
Send
Tx Clock
Start Bit TB8 Stop Bit
D0 D1 D2 D3 D4 D5 D6 D7
Start Bit
RB8 Stop Bit
Stop Bit Generator91/231
uPSD33xx
Figure 34. UART Mode 3, Block Diagram
Figure 35. UART Mode 3, Timing Diagram
AI06846
Zero Detector
Internal Bus
Tx Control
Rx Control
Internal Bus
SBUF
Write
to
SBUF
Read
SBUF
Load
SBUF
SBUF
Input Shift Register
Shift
Serial
Port
Interrupt
Rx Clock
Start
Tx Clock
Start Shift
Shift
Send
Load SBUF
TI
RI
CL
D S Q
1FFh
TxD
Pin
Data
Rx Detector
RxD
Pin
1-to-0
Transition
Detector
÷16
Sample
÷16
÷2
TB8
Timer1
Overflow
Timer2
Overflow
0
0 1
1
0 1
TCLK
RCLK
SMOD
AI06847
Write to SBUF
Data
Shift
TxD
TI
Rx Clock
RxD
Bit Detector
Sample Times
Shift
RI
Receive
Transmit
D0 D1 D2 D3 D4 D5 D6 D7
Send
Tx Clock
Start Bit TB8 Stop Bit
D0 D1 D2 D3 D4 D5 D6 D7
Start Bit
RB8 Stop Bit
Stop Bit GeneratoruPSD33xx
92/231
IrDA INTERFACE
uPSD33xx devices provide an internal IrDA interface
that will allow the connection of the UART1
serial interface directly to an external infrared
transceiver device. The IrDA interface does this by
automatically shortening the pulses transmitted on
UART1’s TxD1 pin, and stretching the incoming
pulses received on the RxD1 pin. Reference Figures
36 and 37.
When the IrDA interface is enabled, the output signal
from UART1’s transmitter logic on pin TxD1 is
compliant with the IrDA Physical Layer Link Specification
v1.4 (www.irda.org) operating from 1.2k
bps up to 115.2k bps. The pulses received on the
RxD1 pin are stretched by the IrDA interface to be
recognized by UART1’s receiver logic, also adhering
to the IrDA specification up to 115.2k bps.
Note: In Figure 37 a logic '0' in the serial data
stream of a UART Frame corresponds to a logic
high pulse in an IR Frame. A logic '1' in a UART
Frame corresponds to no pulse in an IR Frame.
Figure 36. IrDA Interface
Figure 37. Pulse Shaping by the IrDA Interface
UART1 IrDA
Interface
TxD
RxD
uPSD33XX
IrDA
Transceiver
TxD1-IrDA
RxD1-IrDA
SIRClk
AI07851
Start
Bit
0101 11 1 00 0
Stop
Bit
UART Frame
Data Bits
Bit Time Pulse Width = 3/16 Bit Time
Start
Bit
0101 11 1 00 0
Stop
Bit
UART Frame
IR Frame
IR Frame
Data Bits
AI0962493/231
uPSD33xx
The UART1 serial channel can operate in one of
four different modes as shown in Table
44., page 81 in the section, SERIAL UART
INTERFACES, page 81. However, when UART1
is used for IrDA communication, UART1 must operate
in Mode 1 only, to be compatible with IrDA
protocol up to 115.2k bps. The IrDA interface will
support baud rates generated from Timer 1 or Timer
2, just like standard UART serial communication,
but with one restriction. The transmit baud
rate and receive baud rate must be the same (cannot
be different rates as is allowed by standard
UART communications).
The IrDA Interface is disabled after a reset and is
enabled by setting the IRDAEN Bit in the SFR
named IRDACON (Table 48., page 93). When
IrDA is disabled, the UART1's RxD and TxD signals
will bypass the internal IrDA logic and instead
they are routed directly to the pins RxD1 and TxD1
respectively. When IrDA is enabled, the IrDA pulse
shaping logic is active and resides between
UART1 and the pins RxD1 and TxD1 as shown in
Figure 36., page 92.
Table 48. IRDACON Register Bit Definition (SFR CEh, Reset Value 0Fh)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
– IRDAEN PULSE CDIV4 CDIV3 CDIV2 CDIV1 CDIV0
Details
Bit Symbol R/W Definition
7 – – Reserved
6 IRDAEN RW
IrDA Enable
0 = IrDA Interface is disabled
1 = IrDA is enabled, UART1 outputs are disconnected from Port 1 (or
Port 4)
5 PULSE RW
IrDA Pulse Modulation Select
0 = 1.627µs
1 = 3/16 bit time pulses
4-0 CDIV[4:0] RW Specify Clock Divider (see Table 49., page 94)uPSD33xx
94/231
Pulse Width Selection
The IrDA interface has two ways to modulate the
standard UART1 serial stream:
1. An IrDA data pulse will have a constant pulse
width for any bit time, regardless of the
selected baud rate.
2. An IrDA data pulse will have a pulse width that
is proportional to the the bit time of the
selected baud rate. In this case, an IrDA data
pulse width is 3/16 of its bit time, as shown in
Figure 37., page 92.
The PULSE bit in the SFR named IRDACON determines
which method above will be used.
According to the IrDA physical layer specification,
for all baud rates at 115.2k bps and below, the
minimum data pulse width is 1.41µs. For a baud
rate of 115.2k bps, the maximum pulse width
2.23µs. If a constant pulse width is to be used for
all baud rates (PULSE bit = 0), the ideal general
pulse width is 1.63µs, derived from the bit time of
the fastest baud rate (8.68µs bit time for 115.2k
bps rate), multiplied by the proportion, 3/16.
To produce this fixed data pulse width when the
PULSE bit = 0, a prescaler is needed to generate
an internal reference clock, SIRClk, shown in Figure
36., page 92. SIRClk is derived by dividing the
oscillator clock frequency, fOSC, using the five bits
CDIV[4:0] in the SFR named IRDACON. A divisor
must be chosen to produce a frequency for SIRClk
that lies between 1.34 MHz and 2.13 MHz, but it is
best to choose a divisor value that produces SIRClk
frequency as close to 1.83MHz as possible,
because SIRClk at 1.83MHz will produce an fixed
IrDA data pulse width of 1.63µs. Table 49 provides
recommended values for CDIV[4:0] based on several
different values of fOSC.
For reference, SIRClk of 2.13MHz will generate a
fixed IrDA data pulse width of 1.41µs, and SIRClk
of 1.34MHz will generate a fixed data pulse width
of 2.23µs.
Table 49. Recommended CDIV[4:0] Values to Generate SIRClk (default CDIV[4:0] = 0Fh, 15 decimal)
Note: 1. When PULSE bit = 0 (fixed data pulse width), this is minimum recommended fOSC because CDIV[4:0] must be 4 or greater.
fOSC (MHz) Value in CDIV[4:0] Resulting fSIRCLK (MHz)
40.00 16h, 22 decimal 1.82
36.864, or 36.00 14h, 20 decimal 1.84, or 1.80
24.00 0Dh, 13 decimal 1.84
11.059, or 12.00 06h, 6 decimal 1.84, or 2.00
7.3728(1) 04h, 4 decimal 1.8495/231
uPSD33xx
I
2C INTERFACE
uPSD33xx devices support one serial I2C interface.
This is a two-wire communication channel,
having a bi-directional data signal (SDA, pin P3.6)
and a clock signal (SCL, pin P3.7) based on opendrain
line drivers, requiring external pull-up resistors,
RP, each with a typical value of 4.7kΩ (see
Figure 38).
I
2C Interface Main Features
Byte-wide data is transferred, MSB first, between
a Master device and a Slave device on two wires.
More than one bus Master is allowed, but only one
Master may control the bus at any given time. Data
is not lost when another Master requests the use
of a busy bus because I2C supports collision detection
and arbitration. The bus Master initiates all
data movement and generates the clock that permits
the transfer. Once a transfer is initiated by the
Master, any device addressed is considered a
Slave. Automatic clock synchronization allows I2C
devices with different bit rates to communicate on
the same physical bus. A single device can play
the role of Master or Slave, or a single device can
be a Slave only. Each Slave device on the bus has
a unique address, and a general broadcast address
is also available. A Master or Slave device
has the ability to suspend data transfers if the device
needs more time to transmit or receive data.
This I2C interface has the following features:
– Serial I/O Engine (SIOE): serial/parallel
conversion; bus arbitration; clock generation
and synchronization; and handshaking are all
performed in hardware
– Interrupt or Polled operation
– Multi-master capability
– 7-bit Addressing
– Supports standard speed I2C (SCL up to
100kHz), fast mode I2C (101KHz to 400kHz),
and high-speed mode I2C (401KHz to
833kHz)
Figure 38. Typical I2C Bus Configuration
Note: 1. For 3.3V system, connect RP to 3.3V VCC. For 5.0V system, connect RP to 5.0V VDD.
I
2C BUS
SDA
SCL
RP RP
VCC or VDD(1)
Device with I2C
Interface
Device with I2C
Interface
SDA/P3.6 SCL/P3.7
uPSD33XX(V)
Device with I2C
Interface
AI09623uPSD33xx
96/231
Communication Flow
I
2C data flow control is based on the fact that all
I
2C compatible devices will drive the bus lines with
open-drain (or open-collector) line drivers pulled
up with external resistors, creating a wired-AND
situation. This means that either bus line (SDA or
SCL) will be at a logic '1' level only when no I2C device
is actively driving the line to logic '0.' The logic
for handshaking, arbitration, synchronization, and
collision detection is implemented by each I2C device
having:
1. The ability to hold a line low against the will of
the other devices who are trying to assert the
line high.
2. The ability of a device to detect that another
device is driving the line low against its will.
Assert high means the driver releases the line and
external pull-ups passively raise the signal to logic
'1.' Holding low means the open-drain driver is
actively pulling the signal to ground for a logic '0.'
For example, if a Slave device cannot transmit or
receive a byte because it is distracted by and interrupt
or it has to wait for some process to complete,
it can hold the SCL clock line low. Even though the
Master device is generating the SCL clock, the
Master will sense that the Slave is holding the SCL
line low against the will of the Master, indicating
that the Master must wait until the Slave releases
SCL before proceeding with the transfer.
Another example is when two Master devices try
to put information on the bus simultaneously, the
first one to release the SDA data line looses arbitration
while the winner continues to hold SDA low.
Two types of data transfers are possible with I2C
depending on the R/W bit, see Figure
39., page 97.
1. Data transfer from Master Transmitter to
Slave Receiver (R/W = 0). In this case, the
Master generates a START condition on the
bus and it generates a clock signal on the SCL
line. Then the Master transmits the first byte
on the SDA line containing the 7-bit Slave
address plus the R/W bit. The Slave who owns
that address will respond with an acknowledge
bit on SDA, and all other Slave devices will not
respond. Next, the Master will transmit a data
byte (or bytes) that the addressed Slave must
receive. The Slave will return an acknowledge
bit after each data byte it successfully
receives. After the final byte is transmitted by
the Master, the Master will generate a STOP
condition on the bus, or it will generate a RESTART
conditon and begin the next transfer.
There is no limit to the number of bytes that
can be transmitted during a transfer session.
2. Data transfer from Slave Transmitter to
Master Receiver (R/W = 1). In this case, the
Master generates a START condition on the
bus and it generates a clock signal on the SCL
line. Then the Master transmits the first byte
on the SDA line containing the 7-bit Slave
address plus the R/W bit. The Slave who owns
that address will respond with an acknowledge
bit on SDA, and all other Slave devices will not
respond. Next, the addressed Slave will
transmit a data byte (or bytes) to the Master.
The Master will return an acknowledge bit
after each data byte it successfully receives,
unless it is the last byte the Master desires. If
so, the Master will not acknowledge the last
byte and from this, the Slave knows to stop
transmitting data bytes to the Master. The
Master will then generate a STOP condition on
the bus, or it will generate a RE-START
conditon and begin the next transfer. There is
no limit to the number of bytes that can be
transmitted during a transfer session.
A few things to know related to these transfers:
– Either the Master or Slave device can hold the
SCL clock line low to indicate it needs more
time to handle a byte transfer. An indefinite
holding period is possible.
– A START condition is generated by a Master
and recognized by a Slave when SDA has a 1-
to-0 transition while SCL is high (Figure
39., page 97).
– A STOP condition is generated by a Master
and recognized by a Slave when SDA has a 0-
to1 transition while SCL is high (Figure
39., page 97).
– A RE-START (repeated START) condition
generated by a Master can have the same
function as a STOP condition when starting
another data transfer immediately following
the previous data transfer (Figure
39., page 97).
– When transferring data, the logic level on the
SDA line must remain stable while SCL is
high, and SDA can change only while SCL is
low. However, when not transferring data,
SDA may change state while SCL is high,
which creates the START and STOP bus
conditions.97/231
uPSD33xx
– An Acknowlegde bit is generated from a
Master or a Slave by driving SDA low during
the “ninth” bit time, just following each 8-bit
byte that is transfered on the bus (Figure
39., page 97). A Non-Acknowledge occurs
when SDA is asserted high during the ninth bit
time. All byte transfers on the I2C bus include
a 9th bit time reserved for an Acknowlege
(ACK) or Non-Acknowledge (NACK).
– An additional Master device that desires to
control the bus should wait until the bus is not
busy before generating a START condition so
that a possible Slave operation is not
interrupted.
– If two Master devices both try to generate a
START condition simultaneously, the Master
who looses arbitration will switch immediately
to Slave mode so it can recoginize it’s own
Slave address should it appear on the bus.
Figure 39. Data Transfer on an I2C Bus
MSB
7-bit Slave
Address
READ/WRITE
Indicator Acknowledge
bits from
receiver
Start
Condition Clock can be held low
to stall transfer.
Repeated if more
data bytes are
transferred.
Repeated
Start
Condition
Stop
Condition
12 789 3-6 1 2 9 3-8
ACK MSB
ACK
NACK
R/W
AI09625uPSD33xx
98/231
Operating Modes
The I2C interface supports four operating modes:
■ Master-Transmitter
■ Master-Receiver
■ Slave-Transmitter
■ Slave-Receiver
The interface may operate as either a Master or a
Slave within a given application, controlled by firmware
writing to SFRs.
By default after a reset, the I2C interface is in Master
Receiver mode, and the SDA/P3.6 and SCL/
P3.7 pins default to GPIO input mode, high impedance,
so there is no I2C bus interference. Before
using the I2C interface, it must be initialized by
firmware, and the pins must be configured. This is
discussed in I
2C Operating Sequences, page 108.
Bus Arbitration
A Master device always samples the I2C bus to
ensure a bus line is high whenever that Master is
asserting a logic 1. If the line is low at that time, the
Master recognizes another device is overriding it’s
own transmission.
A Master may start a transfer only if the I2C bus is
not busy. However, it’s possible that two or more
Masters may generate a START condition simultaneously.
In this case, arbitration takes place on the
SDA line each time SCL is high. The Master that
first senses that its bus sample does not correspond
to what it is driving (SDA line is low while it’s
asserting a high) will immediately change from
Master-Transmitter to Slave-Receiver mode. The
arbitration process can carry on for many bit times
if both Masters are addressing the same Slave device,
and will continue into the data bits if both
Masters are trying to be Master-Transmitter. It is
also possible for arbitration to carry on into the acknowledge
bits if both Masters are trying to be
Master-Receiver. Because address and data information
on the bus is determined by the winning
Master, no information is lost during the arbitration
process.
Clock Synchronization
Clock synchronization is used to synchronize arbitrating
Masters, or used as a handshake by a devices
to slow down the data transfer.
Clock Sync During Arbitration. During bus arbitration
between competing Masters, Master_X,
with the longest low period on SCL, will force
Master_Y to wait until Master_X finishes its low
period before Master_Y proceeds to assert its high
period on SCL. At this point, both Masters begin
asserting their high period on SCL simultaneously,
and the Master with the shortest high period will be
the first to drive SCL for the next low period. In this
scheme, the Master with the longest low SCL period
paces low times, and the Master with the
shortest high SCL period paces the high times,
making synchronized arbitration possible.
Clock Sync During Handshaking. This allows
receivers in different devices to handle various
transfer rates, either at the byte-level, or bit-level.
At the byte-level, a device may pause the transfer
between bytes by holding SCL low to have time to
store the latest received byte or fetch the next byte
to transmit.
At the bit-level, a Slave device may extend the low
period of SCL by holding it low. Thus the speed of
any Master device will adapt to the internal operation
of the Slave.
General Call Address
A General Call (GC) occurs when a Master-Transmitter
initiates a transfer containing a Slave address
of 0000000b, and the R/W bit is logic 0. All
Slave devices capable of responding to this broadcast
message will acknowledge the GC simultaneously
and then behave as a Slave-Receiver.
The next byte transmitted by the Master will be accepted
and acknowledged by all Slaves capable of
handling the special data bytes. A Slave that cannot
handle one of these data bytes must ignore it
by not acknowledging it. The I2C specification lists
the possible meanings of the special bytes that follow
the first GC address byte, and the actions to
be taken by the Slave device(s) upon receiving
them. A common use of the GC by a Master is to
dynamically assign device addresses to Slave devices
on the bus capable of a programmable device
address.
The uPSD33xx can generate a GC as a MasterTransmitter,
and it can receive a GC as a Slave.
When receiving a GC address (00h), an interrupt
will be generated so firmware may respond to the
special GC data bytes if desired.99/231
uPSD33xx
Serial I/O Engine (SIOE)
At the heart of the I2C interface is the hardware
SIOE, shown in Figure 40. The SIOE automatically
handles low-level I2C bus protocol (data shifting,
handshaking, arbitration, clock generation and
synchronization) and it is controlled and monitored
by five SFRs.
The five SFRs shown in Figure 40 are:
■ S1CON - Interface Control (Table
50., page 100)
■ S1STA - Interface Status (Table
52., page 103)
■ S1DAT - Data Shift Register (Table
53., page 104)
■ S1ADR - Device Address (Table
54., page 104)
■ S1SETUP - Sampling Rate (Table
55., page 105)
Figure 40. I2C Interface SIOE Block Diagram
OpenDrain
Output
Input
OpenDrain
Output
Input
Comparator
S1SETUP - Sample Rate
Control (START Condition)
S1STA - Interface Status
S1CON - Interface Control
ACK
Bit
SCL / P3.7
Timing and
Control
Clock
Generation
Arbitration
and Sync Periph
Clock
(fOSC)
SDA / P3.6
8032 MCU Bus
INTR to 8032
S1DAT - Shift Register
Serial DATA IN
Serial DATA OUT
Shift Direction
8
8
8
8
8
7
7
b7 b0
S1ADR - Device Address
b7 b0
AI09626uPSD33xx
100/231
I
2C Interface Control Register (S1CON)
Table 50. Serial Control Register S1CON (SFR DCh, Reset Value 00h)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CR2 ENI1 STA STO ADDR AA CR[1:0]
Details
Bit Symbol R/W Function
7 CR2 R,W
This bit, along with bits CR1 and CR0, determine the SCL clock
frequency (fSCL) when SIOE is in Master mode. These bits create a clock
divisor for fOSC. See Table 51.
6 ENI1 R,W
I
2C Interface Enable
0 = SIOE disabled, 1 = SIOE enabled. When disabled, both SDA and
SCL signals are in high impedance state.
5 STA R,W
START flag.
When set, Master mode is entered and SIOE generates a START
condition only if the I2C bus is not busy. When a START condition is
detected on the bus, the STA flag is cleared by hardware. When the STA
bit is set during an interrupt service, the START condition will be
generated after the interrupt service.
4 STO R,W
STOP flag
When STO is set in Master mode, the SIOE generates a STOP condition.
When a STOP condition is detected, the STO flag is cleared by
hardware. When the STO bit is set during an interrupt service, the STOP
condition will be generated after the interrupt service.
3 ADDR R,W
This bit is set when an address byte received in Slave mode matches the
device address programmed into the S1ADR register. The ADDR bit
must be cleared with firmware.
2 AA R,W
Assert Acknowledge enable
If AA = 1, an acknowledge signal (low on SDA) is automatically returned
during the acknowledge bit-time on the SCL line when any of the
following three events occur:
1. SIOE in Slave mode receives an address that matches contents of
S1ADR register
2. A data byte has been received while SIOE is in Master Receiver
mode
3. A data byte has been received while SIOE is a selected Slave
Receiver
When AA = 0, no acknowledge is returned (high on SDA during acknowledge
bit-time).
1, 0 CR1, CR0 R,W
These bits, along with bit CR2, determine the SCL clock frequency (fSCL)
when SIOE is in Master mode. These bits create a clock divisor for fOSC.
See Table 51 for values.101/231
uPSD33xx
Table 51. Selection of the SCL Frequency in Master Mode based on fOSC Examples
Note: 1. These values are beyond the bit rate supported by uPSD33xx.
CR2 CR1 CR0 fOSC
Divided by:
Bit Rate (kHz) @ fOSC
12MHz fOSC 24MHz fOSC 36MHz fOSC 40MHz fOSC
0 0 0 32 375 750 X(1) X(1)
0 0 1 48 250 500 750 833
0 1 0 60 200 400 600 666
0 1 1 120 100 200 300 333
1 0 0 240 50 100 150 166
1 0 1 480 25 50 75 83
1 1 0 960 12.5 25 37.5 41
1 1 1 1920 6.25 12.5 18.75 20uPSD33xx
102/231
I
2C Interface Status Register (S1STA)
The S1STA register provides status regarding immediate
activity and the current state of operation
on the I2C bus. All bits in this register are read-only
except bit 5, INTR, which is the interrupt flag.
Interrupt Conditions. If the I2C interrupt is enabled
(EI2C = 1 in SFR named IEA, and EA =1 in
SFR named IE), and the SIOE is initialized, then
an interrupt is automatically generated when any
one of the following five events occur:
– When the SIOE receives an address that
matches the contents of the SFR, S1ADR.
Requirements: SIOE is in Slave Mode, and bit
AA = 1 in the SFR S1CON.
– When the SIOE receives General Call
address. Requirments: SIOE is in Slave Mode,
bit AA = 1 in the SFR S1CON
– When a complete data byte has been received
or transmitted by the SIOE while in Master
mode. The interrupt will occur even if the
Master looses arbitration.
– When a complete data byte has been received
or transmitted by the SIOE while in selected
Slave mode.
– A STOP condition on the bus has been
recognized by the SIOE while in selected
Slave mode.
Selected Slave mode means the device address
sent by the Master device at the beginning of the
current data transfer matched the address stored
in the S1ADR register.
If the I2C interrupt is not enabled, the MCU may
poll the INTR flag in S1STA.103/231
uPSD33xx
Table 52. S1STA: I2C Interface Status Register (SFR DDh, reset value 00h)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
GC STOP INTR TX_MODE BBUSY BLOST ACK_RESP SLV
Details
Bit Symbol R/W Function
7 GC R
General Call flag
GC = 1 if the General Call address of 00h was received when SIOE is in
Slave mode, and GC is cleared by a START or STOP condition on the
bus. If the SIOE is in Master mode when GC = 1, the Bus Lost condition
exists, and BLOST = 1.
6 STOP R
STOP flag
STOP = 1 while SIOE detects a STOP condition on the bus when in
Master or Slave mode.
5 INTR R,W
Interrupt flag
INTR is set to 1 by any of the five I2C interrupt conditions listed above.
INTR must be cleared by firmware.
4 TX_MODE R
Transmission Mode flag
TX_MODE = 1 whenever the SIOE is in Master-Transmitter or SlaveTransmitter
mode. TX_MODE = 0 when SIOE is in any receiver mode.
3 BBUSY R
Bus Busy flag
BBUSY = 1 when the I2C bus is in use. BBUSY is set by the SIOE when
a START condition exists on the bus and BBUSY is cleared by a STOP
condition.
2 BLOST R
Bus Lost flag
BLOST is set when the SIOE is in Master mode and it looses the
arbitration process to another Master device on the bus.
1 ACK_RESP R
Not Acknowledge Response flag
While SIOE is in Transmitter mode:
– After SIOE sends a byte, ACK_RESP = 1 whenever the external I2C
device receives the byte, but that device does NOT assert an
ackowledge signal (external device asserted a high on SDA during
the acknowledge bit-time).
– After SIOE sends a byte, ACK_RESP = 0 whenever the external I2C
device receives the byte, and that device DOES assert an
ackowledge signal (external device drove a low on SDA during the
acknowledge bit-time)
Note: If SIOE is in Master-Transmitter mode, and ACK_RESP = 1 due to
a Slave-Transmitter not sending an Acknowledge, a STOP condition will
not automatically be generated by the SIOE. The STOP condition must
be generated with S1CON.STO = 1.
0 SLV R
Slave Mode flag
SLV = 1 when the SIOE is in Slave mode. SLV = 0 when the SIOE is in
Master mode (default).uPSD33xx
104/231
I
2C Data Shift Register (S1DAT)
The S1ADR register (Table 53) holds a byte of serial
data to be transmitted or it holds a serial byte
that has just been received. The MCU may access
S1DAT while the SIOE is not in the process of
shifting a byte (the INTR flag indicates shifting is
complete).
While transmitting, bytes are shifted out MSB first,
and when receiving, bytes are shifted in MSB first,
through the Acknowledge Bit register as shown in
Figure 40., page 99.
Bus Wait Condition. After the SIOE finishes receiving
a byte in Receive mode, or transmitting a
byte in Transmit mode, the INTR flag (in S1STA)
is set and automatically a wait condition is imposed
on the I2C bus (SCL held low by SIOE). In
Transmit mode, this wait condition is released as
soon as the MCU writes any byte to S1DAT. In Receive
mode, the wait condition is released as soon
as the MCU reads the S1DAT register.
This method allows the user to handle transmit
and receive operations within an interrupt service
routine. The SIOE will automatically stall the I2C
bus at the appropriate time, giving the MCU time
to get the next byte ready to transmit or time to
read the byte that was just received.
Table 53. S1DAT: I2C Data Shift register (SFR DEh, reset value 00h)
I
2C Address Register (S1ADR)
The S1ADR register (Table 54) holds the 7-bit device
address used when the SIOE is operating as
a Slave. When the SIOE receives an address from
a Master, it will compare this address to the contents
of S1ADR, as shown in Figure 40., page 99.
If the 7 bits match, the INTR Interrupt flag (in
S1STA) is set, and the ADDR Bit (in S1CON) is
set. The SIOE cannot modify the contents S1ADR,
and S1ADR is not used during Master mode.
Table 54. S1ADR: I2C Address register (SFR DFh, reset value 00h)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
S1DAT[7:0]
Details
Bit Symbol R/W Function
7:0 S1DAT[7:0] R/W Holds the data byte to be transmitted in Transmit mode, or it holds the
data byte received in Receiver mode.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SLA6 SLA5 SLA4 SLA3 SLA2 SLA1 SLA0 –
Details
Bit Symbol R/W Function
7:1 SLA[6:0] R/W Stores desired 7-bit device address, used when SIOE is in Slave mode.
0 – – Not used105/231
uPSD33xx
I
2C START Sample Setting (S1SETUP)
The S1SETUP register (Table 55) determines how
many times an I2C bus START condition will be
sampled before the SIOE validates the START
condition, giving the SIOE the ability to reject noise
or illegal transmissions.
Because the minimum duration of an START condition
varies with I2C bus speed (fSCL), and also
because the uPSD33xx may be operated with a
wide variety of frequencies (fOSC), it is necessary
to scale the number of samples per START condition
based on fOSC and fSCL.
In Slave mode, the SIOE recognizes the beginning
of a START condition when it detects a '1'-to-'0'
transition on the SDA bus line while the SCL line is
high (see Figure 39., page 97). The SIOE must
then validate the START condition by sampling the
bus lines to ensure SDA remains low and SCL remains
high for a minimum amount of hold time,
tHLDSTA. Once validated, the SIOE begins receiving
the address byte that follows the START condition.
If the EN_SS Bit (in the S1SETUP Register) is not
set, then the SIOE will sample only once after detecting
the '1'-to-'0' transition on SDA. This single
sample is taken 1/fOSC seconds after the initial 1-
to-0 transition was detected. However, more samples
should be taken to ensure there is a valid
START condition.
To take more samples, the SIOE should be initialized
such that the EN_SS Bit is set, and a value is
written to the SMPL_SET[6:0] field of the
S1SETUP Register to specify how many samples
to take. The goal is to take a good number of samples
during the minimum START condition hold
time, tHLDSTA, but no so many samples that the
bus will be sampled after tHLDSTA expires.
Table 56., page 106 describes the relationship between
the contents of S1SETUP and the resulting
number of I2C bus samples that SIOE will take after
detecting the 1-to-0 transition on SDA of a
START condition.
Important: Keep in mind that the time between
samples is always 1/fOSC.
The minimum START condition hold time, tHLDSTA,
is different for the three common I2C speed
categories per Table 57., page 106.
Table 55. S1SETUP: I2C START Condition Sample Setup register (SFR DBh, reset value 00h)
Note: 1. Sampling SCL and SDA lines begins after '1'-to-'0' transition on SDA occurred while SCL is high. Time between samples is 1/fOSC.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
EN_SS SMPL_SET[6:0]
Details
Bit Symbol R/W Function
7 EN_SS R/W
Enable Sample Setup
EN_SS = 1 will force the SIOE to sample(1) a START condition on the bus
the number of times specified in SMPL_SET[6:0].
EN_SS = 0 means the SIOE will sample(1) a START condition only one
time, regardless of the contents of SMPL_SET[6:0].
6:0 SMPL_SET
[6:0] –
Sample Setting
Specifies the number of bus samples(1) taken during a START condition.
See Table 56 for values.uPSD33xx
106/231
Table 56. Number of I2C Bus Samples Taken after 1-to-0 Transition on SDA (START Condition)
Table 57. Start Condition Hold Time
Note: 1. 833KHz is maximum for uPSD33xx devices.
Contents of S1SETUP
Resulting value for S1SETUP Resulting Number of Samples
Taken After 1-to-0 on SDA Line SS_EN bit SMPL_SET[6:0]
0 XXXXXXXb 00h (default) 1
1 0000000b 80h 1
1 0000001b 81h 2
1 0000010b 82h 3
... ... ... ...
1 0001011b 8Bh 12
1 0010111b 97h 24
... ... ... ...
1 1111111b FFh 128
I
2C Bus Speed Range of I2C Clock Speed (fSCL)
Minimum START Condition Hold
Time (tHLDSTA)
Standard Up to 100KHz 4000ns
Fast 101KHz to
400KHz 600ns
High 401KHz to 833KHz(1) 160ns107/231
uPSD33xx
Table 58 provides recommended settings for
S1SETUP based on various combinations of fOSC
and fSCL. Note that the “Total Sample Period”
times in Table 57., page 106 are typically slightly
less than the minimum START condition hold time,
tHLDSTA for a given I2C bus speed.
Important: The SCL bit rate fSCL must first be determined
by bits CR[2:0] in the SFR S1CON before
a value is chosen for SMPL_SET[6:0] in the
SFR S1SETUP.
Table 58. S1SETUP Examples for Various I2C Bus Speeds and Oscillator Frequencies
Note: 1. Not compatible with High Speed I2C.
I
2C Bus
Speed,
fSCL
Parameter
Oscillator Frequency, fOSC
6 MHz 12 MHz 24 MHz 33 MHz 40 MHz
Standard
Recommended
S1SETUP Value 93h A7h CFh EEh FFh
Number of Samples 20 40 80 111 128
Time Between Samples 166.6ns 83.3ns 41.6ns 30ns 25ns
Total Sampled Period 3332ns 3332ns 3332ns 3333ns 3200ns
Fast
Recommended
S1SETUP Value 82h 85h 8Bh 90h 93h
Number of Samples 3 6 12 17 20
Time Between Samples 166.6ns 83.3ns 41.6ns 30ns 25ns
Total Sampled Period 500ns 500ns 500ns 510ns 500ns
High
Recommended
S1SETUP Value (Note 1) 80 82 83 84
Number of Samples - 1 3 4 5
Time Between Samples - 83.3ns 41.6ns 30ns 25ns
Total Sampled Period - 83.3 125ns 120ns 125nsuPSD33xx
108/231
I
2C Operating Sequences
The following pseudo-code explains hardware
control for these I2C functions on the uPSD33xx:
– Initialize the Interface
– Function as Master-Transmitter
– Function as Master-Receiver
– Function as Slave-Transmitter
– Function as Slave-Receiver
– Interrupt Service Routine
Full C code drivers for the uPSD33xx I2C interface,
and other interfaces are available from the
web at www.st.com\psm.
Initialization after a uPSD33xx reset
Ensure pins P3.6 and P3.7 are GPIO inputs
– SFR P3.7 = 1 and SFR P3.6 = 1
Configure pins P3.6 and P3.7 as I2C
– SFR P3SFS.6 = 1 and P3SFS.7 = 1
Set I2C clock prescaler to determine
fSCL
– SFR S1CON.CR[2:0] = desired SCL
freq.
Set bus START condition sampling
– SFR S1SETUP[7:0] = number of samples
Enable individual I2C interrupt and
set priority
– SFR IEA.I2C = 1
– SFR IPA.I2C = 1 if high priority is
desired
Set the Device address for Slave mode
– SFR S1ADR = XXh, desired address
Enable SIOE (as Slave) to return an
ACK signal
– SFR S1CON.AA = 1
Master-Transmitter
Disable all interrupts
– SFR IE.EA = 0
Set pointer to global data xmit buffer,
set count
– *xmit_buf = *pointer to data
– buf_length = number of bytes to
xmit
Set global variables to indicate Master-Xmitter
– I2C_master = 1, I2C_xmitter = 1
Disable Master from returning an ACK
– SFR S1CON.AA = 0
Enable I2C SIOE
– SFR S1CON.INI1 = 1
Transmit Address and R/W bit = 0 to
Slave
– Is bus not busy? (SFR S1STA.BBUSY
= 0?)
– SFR S1DAT[7:0] = Load Slave Address
& FEh
– SFR S1CON.STA = 1, send START on
bus
Enable All Interrupts and go do something
else
– SFR IE.EA = 1
Master-Receiver
Disable all interrupts
– SFR IE.EA = 0
Set pointer to global data recv buffer,
set count
– *recv_buf = *pointer to data
– buf_length = number of bytes to
recv
Set global variables to indicate Master-Xmitter
– I2C_master = 1, I2C_xmitter = 0
Disable Master from returning an ACK
– SFR S1CON.AA = 0
Enable I2C SIOE
– SFR S1CON.INI1 = 1
Transmit Address and R/W bit = 1 to
Slave
– Is bus not busy? (SFR S1STA.BBUSY
= 0?)
– SFR S1DAT[7:0] = Load Slave Address
# 01h
– SFR S1CON.STA = 1, send START on
bus
Enable All Interrupts and go do something
else
– SFR IE.EA = 1109/231
uPSD33xx
Slave-Transmitter
Disable all interrupts
– SFR IE.EA = 0
Set pointer to global data xmit buffer,
set count
– *xmit_buf = *pointer to data
– buf_length = number of bytes to
xmit
Set global variables to indicate Master-Xmitter
– I2C_master = 0, I2C_xmitter = 1
Enable SIOE
– SFR S1CON.INI1 = 1
Prepare to Xmit first data byte
– SFR S1DAT[7:0] = xmit_buf[0]
Enable All Interrupts and go do something
else
– SFR IE.EA = 1
Slave-Receiver
Disable all interrupts
– SFR IE.EA = 0
Set pointer to global data recv buffer,
set count
– *recv_buf = *pointer to data
– buf_length = number of bytes to
recv
Set global variables to indicate Master-Xmitter
– I2C_master = 0, I2C_xmitter = 0
Enable SIOE
– SFR S1CON.INI1 = 1
Enable All Interrupts and go do something
else
– SFR IE.EA = 1
Interrupt Service Routine (ISR). A typical I2C
interrupt service routine would handle a interrupt
for any of the four combinations of Master/Slave
and Transmitter/Receiver. In the example routines
above, the firmware sets global variables,
I2C_master and I2C_xmitter, before enabling interrupts.
These flags tell the ISR which one of the
four cases to process. Following is pseudo-code
for high-level steps in the I2C ISR:
Begin I2C ISR :
Clear I2C interrupt flag:
– S1STA.INTR = 0
Read status of SIOE, put in to variable,
status
– status = S1STA
Read global variables that determine
the mode
– mode <= (I2C_master, I2C_slave)
If mode is Master-Transmitter
Bus Arbitration lost? (status.BLOST=1?)
If Yes, Arbitration was lost:
– S1DAT = dummy, write to release bus
– Exit ISR, SIOE will switch to Slave
Recv mode
If No, Arbitration was not
lost, continue:
ACK recvd from Slave? (status.ACK_RESP=0?)
If No, an ACK was not received:
– S1CON.STO = 1, set STOP bus condition
–
– S1DAT = dummy, write to release bus
– Exit ISR
If Yes, ACK was received, then
continue:
– S1DAT = xmit_buf[buffer_index],
transmit byte
Was that the last byte of data to
transmit?
If No, it was not the last byte,
then:
– Exit ISR, transmit next byte on
next interrupt
If Yes, it was the last byte,
then:
– S1CON.STO = 1, set STOP bus condition
– S1DAT = dummy, write to release bus
– Exit ISRuPSD33xx
110/231
Else If mode is Master-Receiver:
Bus Arbitration lost? (status.BLOST=1?)
If Yes, Arbitration was lost:
– S1DAT = dummy, write to release bus
– Exit ISR, SIOE will switch to Slave
Recv mode
If No, Aribitration was not
lost, continue:
Is this Interrupt from sending an address
to Slave, or is it from receiving
a data byte from Slave?
If its from sending Slave address,
goto A:
If its from receiving Slave data,
goto B:
A: (Interrupt is from Master sending
addr to Slave)
ACK recvd from Slave? (status.ACK_RESP=0?)
If No, an ACK was not received:
– S1CON.STO = 1, set STOP condition
– dummy = S1DAT, read to release bus
– Exit ISR
If Yes, ACK was received, then
continue:
– dummy = S1DAT, read to release bus
Does Master want to receive just one
data byte?
If Yes, do not allow Master to
ACK on next interrupt:
– Exit ISR, now ready to recv one
byte from Slv
If No, Master can ACK next byte
from Slv
– S1CON.AA = 1, allow Master to send
ACK
– Exit ISR, now ready to recv data
from Slave
B: (Interrupt is from Master recving
data from Slv)
– recv_buf[buffer_index] = S1DAT,
read byte
Is this the last data byte to receive
from Slave?
If Yes, tell Slave to stop
transmitting:
– S1CON.STO = 1, set STOP bus condition
– Exit ISR, finished receiving data
from Slave
If No, continue:
Is this the next to last byte to receive
from Slave?
If this is the next to last
byte, do not allow Master to ACK
on next interrupt.
– S1CON.AA = 0, don’t let Master return
ACK
– Exit ISR, now ready to recv last
byte from Slv
If this is not next to last
byte, let Master send ACK to
Slave
– Exit ISR, ready to recv more bytes
from Slave
Else If mode is Slave-Transmitter:
Is this Intr from SIOE detecting a
STOP on bus?
If Yes, a STOP was detected:
– S1DAT = dummy, write to release bus
– Exit ISR, Master needs no more data
bytes
If No, a STOP was not detected,
continue:
ACK recvd from Master? (status.ACK_RESP=0?)
If No, an ACK was not received:
– S1DAT = dummy, write to release bus
– Exit ISR, Master needs no more data
bytes
If Yes, ACK was received, then
continue:
– S1DAT = xmit_buf[buffer_index],
transmit byte
– Exit ISR, transmit next byte on
next interrupt111/231
uPSD33xx
Else If mode is Slave-Receiver:
Is this Intr from SIOE detecting a
STOP on bus?
If Yes, a STOP was detected:
– recv_buf[buffer_index] = S1DAT,
get last byte
– Exit ISR, Master has sent last byte
If No, a STOP was not detected,
continue:
Determine if this Interrupt is from
receiving an address or a data byte
from a Master.
Is (S1CON.ADDR = 1 and S1CON.AA =1)?
If No, intr is from receiving
data, goto C:
If Yes, intr is from an address,
continue:
– slave_is_adressed = 1, local variable
set true
– S1CON.ADDR = 0, clear address
match flag
Determine if R/W bit indicates transmit
or receive.
Does status.TX_MODE = 1?
If Yes, Master wants transmit
mode
– Exit ISR, indicate Master wants
Slv-Xmit mode
If No, Master wants Slave-Recv
mode
– dummy = S1DAT, read taran se bueuPSD33xx
112/231
SPI (SYNCHRONOUS PERIPHERAL INTERFACE)
uPSD33xx devices support one serial SPI interface
in Master Mode only. This is a three- or fourwire
synchronous communication channel, capable
of full-duplex operation on 8-bit serial data
transfers. The four SPI bus signals are:
■ SPIRxD
Pin P1.5 or P4.5 receives data from the Slave
SPI device to the uPSD33xx
■ SPITxD
Pin P1.6 or P4.6 transmits data from the
uPSD33xx to the Slave SPI device
■ SPICLK
Pin P1.4 or P4.4 clock is generated from the
uPSD33xx to the SPI Slave device
■ SPISEL
Pin P1.7 or P4.7 selects the signal from the
uPSD33xx to an individual Slave SPI device
This SPI interface supports single-Master/multiple-Slave
connections. Multiple-Master connections
are not directly supported by the uPSD33xx
(no internal logic for collision detection).
If more than one Slave device is required, the
SPISEL signal may be generated from uPSD33xx
GPIO outputs (one for each Slave) or from the
PLD outputs of the PSD Module. Figure 41. illustrates
three examples of SPI device connections
using the uPSD33xx:
■ Single-Master/Single-Slave with SPISEL
■ Single-Master/Single-Slave without SPISEL
■ Single-Master/Multiple-Slave without SPISEL
Figure 41. SPI Device Connection Examples
SPI Bus SPI Bus
SPI Bus
SPITxD
SPIRxD
uPSD33xx
SPI Master
SPI Slave
SPICLK Device
SPISEL
AI07853b
MOSI
MISO
SCLK
Single-Master/Single-Slave, with SPISEL Single-Master/Single-Slave, without SPISEL
Single-Master/Multiple-Slave, without SPISEL
SS
SPI Slave
Device
MOSI
MISO
SCLK
SS
SPI Slave
Device
MOSI
MISO
SCLK
SS
SS
SPITxD
SPIRxD
uPSD33xx
SPI Master
SPI Slave
SPICLK Device
SPITxD
SPIRxD
uPSD33xx
SPI Master
SPICLK
GPIO or PLD
GPIO or PLD
MOSI
MISO
SCLK113/231
uPSD33xx
SPI Bus Features and Communication Flow
The SPICLK signal is a gated clock generated
from the uPSD33xx (Master) and regulates the
flow of data bits. The Master may transmit at a variety
of baud rates, and the SPICLK signal will
clock one period for each bit of transmitted data.
Data is shifted on one edge of SPICLK and sampled
on the opposite edge.
The SPITxD signal is generated by the Master and
received by the Slave device. The SPIRxD signal
is generated by the Slave device and received by
the Master. There may be no more than one Slave
device transmitting data on SPIRxD at any given
time in a multi-Slave configuration. Slave selection
is accomplished when a Slave’s “Slave Select”
(SS) input is permanently grounded or asserted
active-low by a Master device. Slave devices that
are not selected do not interfere with SPI activities.
Slave devices ignore SPICLK and keep their
MISO output pins in high-impedance state when
not selected.
The SPI specification allows a selection of clock
polarity and clock phase with respect to data. The
uPSD33xx supports the choice of clock polarity,
but it does not support the choice of clock phase
(phase is fixed at what is typically known as
CPHA = 1). See Figure 43. and Figure
44., page 114 for SPI data and clock relationships.
Referring to these figures (43 and 44), when the
phase mode is defined as such (fixed at
CPHA =1), in a new SPI data frame, the Master
device begins driving the first data bit on SPITxD
at the very first edge of the first clock period of SPICLK.
The Slave device will use this first clock edge as a
transmission start indicator, and therefore the
Slave’s Slave Select input signal may remain
grounded in a single-Master/single-Slave configuration
(which means the user does not have to use
the SPISEL signal from uPSD33xx in this case).
The SPI specification does not specify high-level
protocol for data exchange, only low-level bit-serial
transfers are defined.
Full-Duplex Operation
When an SPI transfer occurs, 8 bits of data are
shifted out on one pin while a different 8 bits of
data are simultaneously shifted in on a second pin.
Another way to view this transfer is that an 8-bit
shift register in the Master and another 8-bit shift
register in the Slave are connected as a circular
16-bit shift register. When a transfer occurs, this
distributed shift register is shifted 8 bit positions;
thus, the data in the Master and Slave devices are
effectively exchanged (see Figure 42.).
Bus-Level Activity
Figure 43. details an SPI receive operation (with
respect to bus Master) and Figure 44. details an
SPI transmit operation. Also shown are internal
flags available to firmware to manage data flow.
These flags are accessed through a number of
SFRs.
Note: The uPSD33xx SPI interface SFRs allow
the choice of transmitting the most significant bit
(MSB) of a byte first, or the least significant bit
(LSB) first. The same bit-order applies to data reception.
Figures 43 and 44 illustrate shifting the
LSB first.
Figure 42. SPI Full-Duplex Data Exchange
SPI Bus Master Device Slave Device
AI10485
SS
SPITxD
SPIRxD
Baud Rate
Generator
8-Bit Shift
Register 8-Bit Shift
Register
SPICLK
MOSI
MISO
SCLKuPSD33xx
114/231
Figure 43. SPI Receive Operation Example
Figure 44. SPI Transmit Operation Example
Bit7
SPICLK
(SPO=0)
SPICLK
(SPO=1)
SPIRXD Bit0 Bit1 Bit7 Bit0 Bit1 Bit7
1 frame
RISF
RORIS
BUSY
SPIINTR
SPIRDR Full
interrupt requested
Interrupt handler
read data in SPIRDR
SPIRDR Full
interrupt requested
Transmit End
interrupt requested
AI07855
Bit0
SPICLK
(SPO=0)
SPICLK
(SPO=1)
SPITXD Bit1 Bit7 Bit0 Bit1 Bit7
1 frame
TISF
TEISF
BUSY
SPIINTR
SPITDR Empty
interrupt requested
Interrupt handler
write data in TDR
SPITDR Empty
interrupt requested
Transmit End
interrupt requested
SPISEL
AI07854115/231
uPSD33xx
SPI SFR Registers
Six SFR registers control the SPI interface:
■ SPICON0 (Table 59., page 117) for interface
control
■ SPICON1 (Table 60., page 118) for interrupt
control
■ SPITDR (SFR D4h, Write only) holds byte to
transmit
■ SPIRDR (SFR D5h, Read only) holds byte
received
■ SPICLKD (Table 61., page 118) for clock
divider
■ SPISTAT (Table 62., page 119) holds
interface status
The SPI interface functional block diagram (Figure
45.) shows these six SFRs. Both the transmit and
receive data paths are double-buffered, meaning
that continuous transmitting or receiving (back-toback
transfer) is possible by reading from SPIRDR
or writing data to SPITDR while shifting is taking
place. There are a number of flags in the SPISTAT
register that indicate when it is full or empty to assist
the 8032 MCU in data flow management.
When enabled, these status flags will cause an interrupt
to the MCU.
Figure 45. SPI Interface, Master Mode Only
SPITDR - TRANSMIT REGISTER
SPITxD / P1.6 or P4.6
TIMING AND CONTROL
(fOSC)
INTR
to
8032
SPIRDR - RECEIVE REGISTER
8-bit SHIFT REGISTER
8
8
8
8
SPIRxD /
P1.5 or P4.5
SPICON0, SPICON1
- CONTROL REGISTERS
8
SPISTAT - STATUS REGISTER
8
8032 MCU DATA BUS
CLOCK
GENERATE
SPISEL / P1.7 or P4.7
CLOCK SPICLK / P1.4 or P4.4
DIVIDE
÷1
÷4
÷8
÷16
÷32
÷64
÷128
SPICLKD - DIVIDE SELECT
8
PERIPH_CLK
AI10486uPSD33xx
116/231
SPI Configuration
The SPI interface is reset by the MCU reset, and
firmware needs to initialize the SFRs SPICON0,
SPICON1, and SPICLKD to define several operation
parameters.
The SPO Bit in SPICON0 determines the clock polarity.
When SPO is set to '0,' a data bit is transmitted
on SPITxD from one rising edge of SPICLK to
the next and is guaranteed to be valid during the
falling edge of SPICLK. When SPO is set to '1,' a
data bit is transmitted on SPITxD from one falling
edge of SPICLK to the next and is guaranteed to
be valid during the rising edge of SPICLK. The
uPSD33xx will sample received data on the appropriate
edge of SPICLK as determined by SPO.
The effect of the SPO Bit can be seen in Figure 43.
and Figure 44., page 114.
The FLSB Bit in SPICON0 determines the bit order
while transmitting and receiving the 8-bit data.
When FLSB is '0,' the 8-bit data is transferred in order
from MSB (first) to LSB (last). When FLSB Bit
is set to '1,' the data is transferred in order from
LSB (first) to MSB (last).
The clock signal generated on SPICLK is derived
from the internal PERIPH_CLK signal.
PERIPH_CLK always operates at the frequency,
fOSC, and runs constantly except when stopped in
MCU Power Down mode. SPICLK is a result of dividing
PERIPH_CLK by a sum of different divisors
selected by the value contained in the SPICLKD
register. The default value in SPICLKD after a reset
divides PERIPH_CLK by a factor of 4. The bits
in SPICLKD can be set to provide resulting divisor
values in of sums of multiples of 4, such as 4, 8,
12, 16, 20, all the way up to 252. For example, if
SPICLKD contains 0x24, SPICLK has the frequency
of PERIH_CLK divided by 36 decimal.
The SPICLK frequency must be set low enough to
allow the MCU time to read received data bytes
without loosing data. This is dependent upon
many things, including the crystal frequency of the
MCU and the efficiency of the SPI firmware.
Dynamic Control
At runtime, bits in registers SPICON0, SPICON1,
and SPISTAT are managed by firmware for dynamic
control over the SPI interface. The bits
Transmitter Enable (TE) and Receiver Enable
(RE) when set will allow transmitting and receiving
respectively. If TE is disabled, both transmitting
and receiving are disabled because SPICLK is
driven to constant output logic ‘0’ (when SPO = 0)
or logic '1' (when SPO = 1).
When the SSEL Bit is set, the SPISEL pin will drive
to logic '0' (active) to select a connected slave device
at the appropriate time before the first data bit
of a byte is transmitted, and SPISEL will automatically
return to logic '1' (inactive) after transmitting
the eight bit of data, as shown in Figure
44., page 114. SPISEL will continue to automatically
toggle this way for each byte data transmission
while the SSEL bit is set by firmware. When
the SSEL Bit is cleared, the SPISEL pin will drive
to constant logic '1' and stay that way (after a
transmission in progress completes).
The Interrupt Enable Bits (TEIE, RORIE,TIE, and
RIE) when set, will allow an SPI interrupt to be
generated to the MCU upon the occurrence of the
condition enabled by these bits. Firmware must
read the four corresponding flags in the SPISTAT
register to determine the specific cause of interrupt.
These flags are automatically cleared when
firmware reads the SPISTAT register.117/231
uPSD33xx
Table 59. SPICON0: Control Register 0 (SFR D6h, Reset Value 00h)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
– TE RE SPIEN SSEL FLSB SBO –
Details
Bit Symbol R/W Definition
7 – – Reserved
6 TE RW
Transmitter Enable
0 = Transmitter is disabled
1 = Transmitter is enabled
5 RE RW
Receiver Enable
0 = Receiver is disabled
1 = Receiver is enabled
4 SPIEN RW
SPI Enable
0 = Entire SPI Interface is disabled
1 = Entire SPI Interface is enabled
3 SSEL RW
Slave Selection
0 = SPISEL output pin is constant logic '1' (slave device not selected)
1 = SPISEL output pin is logic '0' (slave device is selected) during data
transfers
2 FLSB RW
First LSB
0 = Transfer the most significant bit (MSB) first
1 = Transfer the least significant bit (LSB) first
1 SPO –
Sampling Polarity
0 = Sample transfer data at the falling edge of clock (SPICLK is '0' when
idle)
1 = Sample transfer data at the rising edge of clock (SPICLK is '1' when
idle)
0 – – ReserveduPSD33xx
118/231
Table 60. SPICON1: SPI Interface Control Register 1 (SFR D7h, Reset Value 00h)
Table 61. SPICLKD: SPI Prescaler (Clock Divider) Register (SFR D2h, Reset Value 04h)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
– – – – TEIE RORIE TIE RIE
Details
Bit Symbol R/W Definition
7-4 – – Reserved
3 TEIE RW
Transmission End Interrupt Enable
0 = Disable Interrupt for Transmission End
1 = Enable Interrupt for Transmission End
2 RORIE RW
Receive Overrun Interrupt Enable
0 = Disable Interrupt for Receive Overrun
1 = Enable Interrupt for Receive Overrun
1 TIE RW
Transmission Interrupt Enable
0 = Disable Interrupt for SPITDR empty
1 = Enable Interrupt for SPITDR empty
0 RIE RW
Reception Interrupt Enable
0 = Disable Interrupt for SPIRDR full
1 = Enable Interrupt for SPIRDR full
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DIV128 DIV64 DIV32 DIV16 DIV8 DIV4 – –
Details
Bit Symbol R/W Definition
7 DIV128 RW 0 = No division
1 = Divide fOSC clock by 128
6 DIV64 RW 0 = No division
1 = Divide fOSC clock by 64
5 DIV32 RW 0 = No division
1 = Divide fOSC clock by 32
4 DIV16 RW 0 = No division
1 = Divide fOSC clock by 16
3 DIV8 RW 0 = No division
1 = Divide fOSC clock by 8
2 DIV4 RW 0 = No division
1 = Divide fOSC clock by 4
1-0 Not Used –119/231
uPSD33xx
Table 62. SPISTAT: SPI Interface Status Register (SFR D3h, Reset Value 02h)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
– – – BUSY TEISF RORISF TISF RISF
Details
Bit Symbol R/W Definition
7-5 – – Reserved
4 BUSY R
SPI Busy
0 = Transmit or Receive is completed
1 = Transmit or Receive is in process
3 TEISF R
Transmission End Interrupt Source flag
0 = Automatically resets to '0' when firmware reads this register
1 = Automatically sets to '1' when transmission end occurs
2 RORISF R
Receive Overrun Interrupt Source flag
0 = Automatically resets to '0' when firmware reads this register
1 = Automatically sets to '1' when receive overrun occurs
1 TISF R
Transfer Interrupt Source flag
0 = Automatically resets to '0' when SPITDR is full (just after the SPITDR
is written)
1 = Automatically sets to '1' when SPITDR is empty (just after byte loads
from SPITDR into SPI shift register)
0 RISF R
Receive Interrupt Source flag
0 = Automatically resets to '0' when SPIRDR is empty (after the SPIRDR
is read)
1 = Automatically sets to '1' when SPIRDR is fulluPSD33xx
120/231
ANALOG-TO-DIGITAL CONVERTOR (ADC)
The ADC unit in the uPSD33xx is a SAR type ADC
with an SAR register, an auto-zero comparator
and three internal DACs. The unit has 8 input
channels with 10-bit resolution. The A/D converter
has its own VREF input (80-pin package only),
which specifies the voltage reference for the A/D
operations. The analog to digital converter (A/D)
allows conversion of an analog input to a corresponding
10-bit digital value. The A/D module has
eight analog inputs (P1.0 through P1.7) to an 8x1
multiplexor. One ADC channel is selected by the
bits in the configuration register. The converter
generates a 10-bits result via successive approximation.
The analog supply voltage is connected to
the VREF input, which powers the resistance ladder
in the A/D module.
The A/D module has 3 registers, the control register
ACON, the A/D result register ADAT0, and the
second A/D result register ADAT1. The ADAT0
Register stores Bits 0.. 7 of the converter output,
Bits 8.. 9 are stored in Bits 0..1 of the ADAT1 Register.
The ACON Register controls the operation of
the A/D converter module. Three of the bits in the
ACON Register select the analog channel inputs,
and the remaining bits control the converter operation.
ADC channel pin input is enabled by setting the
corresponding bit in the P1SFS0 and P1SFS1
Registers to '1' and the channel select bits in the
ACON Register.
The ADC reference clock (ADCCLK) is generated
from fOSC divided by the divider in the ADCPS
Register. The ADC operates within a range of 2 to
16MHz, with typical ADCCLK frequency at 8MHz.
The conversion time is 4µs typical at 8MHz.
The processing of conversion starts when the
Start Bit ADST is set to '1.' After one cycle, it is
cleared by hardware. The ADC is monotonic with
no missing codes. Measurement is by continuous
conversion of the analog input. The ADAT Register
contains the results of the A/D conversion.
When conversion is complete, the result is loaded
into the ADAT. The A/D Conversion Status Bit
ADSF is set to '1.' The block diagram of the A/D
module is shown in Figure 46. The A/D status bit
ADSF is set automatically when A/D conversion is
completed and cleared when A/D conversion is in
process.
In addition, the ADC unit sets the interrupt flag in
the ACON Register after a conversion is complete
(if AINTEN is set to '1'). The ADC interrupts the
CPU when the enable bit AINTEN is set.
Port 1 ADC Channel Selects
The P1SFS0 and P1SFS1 Registers control the
selection of the Port 1 pin functions. When the
P1SFS0 Bit is '0,' the pin functions as a GPIO.
When bits are set to '1,' the pins are configured as
alternate functions. A new P1SFS1 Register selects
which of the alternate functions is enabled.
The ADC channel is enabled when the bit in
P1SFS1 is set to '1.'
Note: In the 52-pin package, there is no individual
VREF pin because VREF is combined with AVCC
pin.
Figure 46. 10-Bit ADC
ANALOG
MUX
SELECT
ADC OUT - 10 BITS
ACON REG ADAT 0 REG
CONTROL
10-BIT SAR ADC
ADAT1
REG
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
AVREF
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
AVREF
AI07856121/231
uPSD33xx
Table 63. ACON Register (SFR 97h, Reset Value 00h)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
AINTF AINTEN ADEN ADS2 ADS1 ADS0 ADST ADSF
Details
Bit Symbol Function
7 AINTF
ADC Interrupt flag. This bit must be cleared with software.
0 = No interrupt request
1 = The AINTF flag is set when ADSF goes from '0' to '1.' Interrupts CPU when both
AINTF and AINTEN are set to '1.'
6 AINTEN
ADC Interrupt Enable
0 = ADC interrupt is disabled
1 = ADC interrupt is enabled
5 ADEN
ADC Enable Bit
0 = ADC shut off and consumes no operating current
1 = Enable ADC. After ADC is enabled, 16ms of calibration is needed before ADST Bit is
set.
4.. 2 ADS2.. 0
Analog channel Select
000 Select channel 0 (P1.0)
001 Select channel 0 (P1.1)
010 Select channel 0 (P1.2)
011 Select channel 0 (P1.3)
101 Select channel 0 (P1.5)
110 Select channel 0 (P1.6)
111 Select channel 0 (P1.7)
1 ADST
ADC Start Bit
0 = Force to zero
1 = Start ADC, then after one cycle, the bit is cleared to '0.'
0 ADSF
ADC Status Bit
0 = ADC conversion is not completed
1 = ADC conversion is completed. The bit can also be cleared with software.uPSD33xx
122/231
Table 64. ADCPS Register Details (SFR 94h, Reset Value 00h)
Table 65. ADAT0 Register (SFR 95H, Reset Value 00h)
Table 66. ADAT1 Register (SFR 96h, Reset Value 00h)
Bit Symbol Function
7:4 – Reserved
3 ADCCE
ADC Conversion Reference Clock Enable
0 = ADC reference clock is disabled (default)
1 = ADC reference clock is enabled
2:0 ADCPS[2:0]
ADC Reference Clock PreScaler
Only three Prescaler values are allowed:
ADCPS[2:0] = 0, for fOSC frequency 16MHz or less. Resulting ADC clock is fOSC.
ADCPS[2:0] = 1, for fOSC frequency 32MHz or less. Resulting ADC clock is fOSC/2.
ADCPS[2:0] = 2, for fOSC frequency 32MHz > 40MHz. Resulting ADC clock is fOSC/4.
Bit Symbol Function
7:0 – Store ADC output, Bit 7 - 0
Bit Symbol Function
7:2 – Reserved
1.. 0 – Store ADC output, Bit 9, 8123/231
uPSD33xx
PROGRAMMABLE COUNTER ARRAY (PCA) WITH PWM
There are two Programmable Counter Array
blocks (PCA0 and PCA1) in the uPSD33xx. A PCA
block consists of a 16-bit up-counter, which is
shared by three TCM (Timer Counter Module). A
TCM can be programmed to perform one of the
following four functions:
1. Capture Mode: capture counter values by
external input signals
2. Timer Mode
3. Toggle Output Mode
4. PWM Mode: fixed frequency (8-bit or 16-bit),
programmable frequency (8-bit only)
PCA Block
The 16-bit Up-Counter in the PCA block is a freerunning
counter (except in PWM Mode with programmable
frequency). The Counter has a choice
of clock input: from an external pin, Timer 0 Overflow,
or PCA Clock.
A PCA block has 3 Timer Counter Modules (TCM)
which share the 16-bit Counter output. The TCM
can be configured to capture or compare counter
value, generate a toggling output, or PWM functions.
Except for the PWM function, the other TCM
functions can generate an interrupt when an event
occurs.
Every TCM is connected to a port pin in Port 4; the
TCM pin can be configured as an event input, a
PWMs, a Toggle Output, or as External Clock Input.
The pins are general I/O pins when not assigned
to the TCM.
The TCM operation is configured by Control registers
and Capture/Compare registers. Table
67., page 124 lists the SFR registers in the PCA
blocks.
Figure 47. PCA0 Block Diagram
TIMER0
OVERFLOW
P4.3/ECI
PCACH0
8-bit
PCACL0
8-bit
CLKSEL1
IDLE MODE
(From CPU)
OVF0 INT
EOVFI
TCM0
TCM1
TCM2
PWM FREQ
COMPARE
P4.0/CEX0
P4.1/CEX1
P4.2/CEX2
16-bit up Timer/Counter
CLKSEL0
PCAIDLE
PCA0CLK
CLEAR COUNTER
EN_PCA
EN_ALL
AI07857uPSD33xx
124/231
Table 67. PCA0 and PCA1 Registers
SFR Address Register Name
RW Register Function
PCA0 PCA1 PCA0 PCA1
A2 BA PCACL0 PCACL1 RW The low 8 bits of PCA 16-bit counter.
A3 BB PCACH0 PCACH1 RW The high 8 bits of PCA 16-bit counter.
A4 BC PCACON0 PCACON1 RW
Control Register
– Enable PCA, Timer Overflow flag ,
PCA Idle Mode, and Select clock
source.
A5 A5 PCASTA N/A RW Status Register, Interrupt Status flags
– Common for both PCA Block 0 and 1.
A9,
AA,
AB
BD,
BE,
BF
TCMMODE0
TCMMODE1
TCMMODE2
TCMMODE3
TCMMODE4
TCMMODE5
RW
TCM Mode
– Capture, Compare, and Toggle
Enable Interrupts
– PWM Mode Select.
AC
AD
C1
C2
CAPCOML0
CAPCOMH0
CAPCOML3
CAPCOMH3 RW Capture/Compare registers of TCM0
AF
B1
C3
C4
CAPCOML1
CAPCOMH1
CAPCOML4
CAPCOMH4 RW Capture/Compare registers of TCM1
B2
B3
C5
C6
CAPCOML2
CAPCOMH2
CAPCOML5
CAPCOMH5 RW Capture/Compare registers of TCM2
B4 C7 PWMF0 PWMF1 RW
The 8-bit register to program the PWM
frequency. This register is used for
programmable, 8-bit PWM Mode only.
FB FC CCON2 CCON3 RW Specify the pre-scaler value of PCA0 or
PCA1 clock input125/231
uPSD33xx
PCA Clock Selection
The clock input to the 16-bit up counter in the PCA
block is user-programmable. The three clock
sources are:
– PCA Prescaler Clock (PCA0CLK, PCA1CLK)
– Timer 0 Overflow
– External Clock, Pin P4.3 or P4.7
The clock source is selected in the configuration
register PCACON. The Prescaler output clock
PCACLK is the fOSC divided by the divisor which is
specified in the CCON2 or CCON3 Register.
When External Clock is selected, the maximum
clock frequency should not exceed fOSC/4.
Table 68. CCON2 Register Bit Definition (SFR 0FBh, Reset Value 10h)
Table 69. CCON3 Register Bit Definition (SFR 0FCh, Reset Value 10h)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
– – – PCA0CE PCA0PS3 PCA0PS2 PCA0PS1 PCA0PS0
Details
Bit Symbol R/W Definition
4 PCA0CE R/W
PCA0 Clock Enable
0 = PCA0CLK is disabled
1 = PCA0CLK is enabled (default)
3:0 PCA0PS
[3:0] R/W
PCA0 Prescaler
fPCA0CLK = fOSC / (2 ^ PCA0PS[3:0])
Divisor range: 1, 2, 4, 8, 16... 16384, 32768
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
– – – PCA1CE PCA1PS3 PCA1PS2 PCA1PS1 PCA1PS0
Details
Bit Symbol R/W Definition
4 PCA1CE R/W
PCA1 Clock Enable
0 = PCA1CLK is disabled
1 = PCA1CLK is enabled (default)
3:0 PCA1PS
[3:0] R/W
PCA1 Prescaler
fPCA1CLK = fOSC / (2 ^ PCA1PS[3:0])
Divisor range: 1, 2, 4, 8, 16... 16384, 32768uPSD33xx
126/231
Operation of TCM Modes
Each of the TCM in a PCA block supports four
modes of operation. However, an exception is
when the TCM is configured in PWM Mode with
programmable frequency. In this mode, all TCM in
a PCA block must be configured in the same mode
or left to be not used.
Capture Mode
The CAPCOM registers in the TCM are loaded
with the counter values when an external pin input
changes state. The user can configure the counter
value to be loaded by positive edge, negative edge
or any transition of the input signal. At loading, the
TCM can generate an interrupt if it is enabled.
Timer Mode
The TCM modules can be configured as software
timers by enable the comparator. The user writes
a value to the CAPCOM registers, which is then
compared with the 16-bit counter. If there is a
match, an interrupt can be generated to CPU.
Toggle Mode
In this mode, the user writes a value to the TCM's
CAPCOM registers and enables the comparator.
When there is a match with the Counter output, the
output of the TCM pin toggles. This mode is a simple
extension of the Timer Mode.
PWM Mode - (X8), Fixed Frequency
In this mode, one or all the TCM's can be configured
to have a fixed frequency PWM output on the
port pins. The PWM frequency depends on when
the low byte of the Counter overflows (modulo
256). The duty cycle of each TCM module can be
specified in the CAPCOMHn Register. When the
PCA_Counter_L value is equal to or greater than
the value in CAPCOMHn, the PWM output is
switched to a high state. When the
PCA_Counter_L Register overflows, the content
in CAPCOMHn is loaded to CAPCOMLn and a
new PWM pulse starts.
Figure 48. Timer Mode
Note: m = 0: n = 0, 1, or 2
m = 1: n = 3, 4, or 5
MATCH_TIMER
INTR
0 0 0
TCMMODEn
ENABLE
8
8
MATCH
PCASTA
CAPCOMLn
PCACHm PCACLm
16-bit COMPARATOR
CAPCOMHn INTFn
0 0
16-bit up Timer/Counter
8
8
EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM1 PWM0
RESET
WRITE to
CAPCOMHn
WRITE to
CAPCOMLn
1
0 EN_FLAG
C D
AI07858127/231
uPSD33xx
Figure 49. PWM Mode - (X8), Fixed Frequency
Note: m = 0: n = 0, 1, or 2
m = 1: n = 3, 4, or 5
CAPCOMHn
OVERFLOW
ENABLE
8
PCACLm
8
CAPCOMLn
8-bit COMPARATORn CEXn MATCH S
R
Q
Q
SET
CLR
0 0
TCMMODEn
0 0 0
EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM1 PWM0
AI07859uPSD33xx
128/231
PWM Mode - (X8), Programmable Frequency
In this mode, the PWM frequency is not determined
by the overflow of the low byte of the
Counter. Instead, the frequency is determined by
the PWMFm Register. The user can load a value
in the PWMFm Register, which is then compared
to the low byte of the Counter. If there is a match,
the Counter is cleared and the Load registers
(PWMFm, CAPCOMHn) are re-loaded for the next
PWM pulse. There is only one PWMFm Register
which serves all 3 TCM in a PCA block.
If one of the TCM modules is operating in this
mode, the other modules in the PCA must be configured
to the same mode or left not to be used.
The duty cycle of the PWM can be specified in the
CAPCOMHn Register as in the PWM with fixed
frequency mode. Different TCM modules can have
their own duty cycle.
Note: The value in the Frequency Register (PWMFm)
must be larger than the duty cycle register
(CAPCOM).
Figure 50. PWM Mode - (X8) Programmable Frequency
Note: m = 0: n = 0, 1, or 2
m = 1: n = 3, 4, or 5
CLR
PCACHm
PWM FREQ COMPARE
PWMFm = PCACLm
PCACLm
CAPCOMHn
ENABLE ENABLE CEXn
8
8
PWMFm
8-bit COMPARATORm 8-bit COMPARATORn
CAPCOMLn
MATCH
S
R
Q
Q
SET
CLR
8
0 0
TCMMODEn
0 0 0
EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM1 PWM0
AI07860129/231
uPSD33xx
PWM Mode - Fixed Frequency, 16-bit
The operation of the 16-bit PWM is the same as
the 8-bit PWM with fixed frequency. In this mode,
one or all the TCM can be configured to have a
fixed frequency PWM output on the port pins. The
PWM frequency is depending on the clock input
frequency to the 16-bit Counter. The duty cycle of
each TCM module can be specified in the CAPCOMHn
and CAPCOMLn Registers. When the 16-
bit PCA_Counter is equal or greater than the values
in registers CAPCOMHn and CAPCOMLn, the
PWM output is switched to a high state. When the
PCA_Counter overflows, CEXn is asserted low.
PWM Mode - Fixed Frequency, 10-bit
The 10-bit PWM logic requires that all 3 TCMs in
PCA0 or PCA1 operate in the same 10-bit PWM
mode. The 10-bit PWM operates in a similar manner
as the 16-bit PWM, except the PCACHm and
PCACLm counters are reconfigured as 10-bit
counters. The CAPCOMHn and CAPCOMLn Registers
become 10-bit registers.
PWM duty cycle of each TCM module can be
specified in the 10-bit CAPCOMHn and CAPCOMLn
Registers. When the 10-bit PCA counter
is equal or greater than the values in the 10-bit
registers CAPCOMHn and CAPCOMLn, the PWM
output switches to a high state. When the 10-bit
PCA counter overflows, the PWM pin is switched
to a logic low and starts the next PWM pulse.
The most-significant 6 bits in the PCACHm
counter and CAPCOMH Register are “Don’t cares”
and have no effect on the PWM generation.
Writing to Capture/Compare Registers
When writing a 16-bit value to the PCA Capture/
Compare registers, the low byte should always be
written first. Writing to CAPCOMLn clears the
E_COMP Bit to '0'; writing to CAPCOMHn sets
E_COMP to '1' the largest duty cycle is 100%
(CAPCOMHn CAPCOMLn = 0x0000), and the
smallest duty cycle is 0.0015% (CAPCOMHn
CAPCOMLn = 0xFFFF). A 0% duty cycle may be
generated by clearing the E_COMP Bit to ‘0’.
Control Register Bit Definition
Each PCA has its own PCA_CONFIGn, and each
module within the PCA block has its own
TCM_Mode Register which defines the operation
of that module (see Table 70., page 129 through
Table 71., page 130). There is one PCA_STATUS
Register that covers both PCA0 and PCA1 (see
Table 72., page 131).
Table 70. PCA0 Control Register PCACON0 (SFR 0A4h, Reset Value 00h)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
EN-ALL EN_PCA EOVFI PCAIDLE – – CLK_SEL[1:0]
Details
Bit Symbol Function
7 EN-ALL
0 = No impact on TCM modules
1 = Enable both PCA counters simultaneously (override the EN_PCA Bits)
This bit is to start the two 16-bit counters in the PCA. For customers who want 5 PWM,
for example, this bit can start all of the PWM outputs.
6 EN_PCA
0 = PCA counter is disabled
1 = PCA counter is enabled
EN_PCA Counter Run Control Bit. Set with software to turn the PCA counter on. Must
be cleared with software to turn the PCA counter off.
5 EOVFI 1 = Enable Counter Overflow Interrupt if overflow flag (OVF) is set
4 PCAIDLE 0 = PCA operates when CPU is in Idle Mode
1 = PCA stops running when CPU is in Idle Mode
3 – Reserved
2 10B_PWM 0 = Select 16-bit PWM
1 = Select 10-bit PWM
1-0 CLK_SEL
[1:0]
00 Select Prescaler clock as Counter clock
01 Select Timer 0 Overflow
10 Select External Clock pin (P4.3 for PCA0) (MAX clock rate = fOSC/4)uPSD33xx
130/231
Table 71. PCA1 Control Register PCACON1 (SFR 0BCh, Reset Value 00h)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
– EN_PCA EOVFI PCAIDLE – – CLK_SEL[1:0]
Details
Bit Symbol Function
6 EN_PCA
0 = PCA counter is disabled
1 = PCA counter is enabled
EN_PCA Counter Run Control Bit. Set with software to turn the PCA counter on. Must
be cleared with software to turn the PCA counter off.
5 EOVFI 1 = Enable Counter Overflow Interrupt if overflow flag (OVF) is set
4 PCAIDLE 0 = PCA operates when CPU is in Idle Mode
1 = PCA stops running when CPU is in Idle Mode
3 – Reserved
2 10B_PWM 0 = Select 16-bit PWM
1 = Select 10-bit PWM
1-0 CLK_SEL
[1:0]
00 Select Prescaler clock as Counter clock
01 Select Timer 0 Overflow
10 Select External Clock pin (P4.7 for PCA1) (MAX clock rate = fOSC/4)131/231
uPSD33xx
Table 72. PCA Status Register PCASTA (SFR 0A5h, Reset Value 00h)uPSD33xx
132/231
TCM Interrupts
There are 8 TCM interrupts: 6 match or capture interrupts
and two counter overflow interrupts. The 8
interrupts are “ORed” as one PCA interrupt to the
CPU.
By the nature of PCA application, it is unlikely that
many of the interrupts occur simultaneously. If
they do, the CPU has to read the interrupt flags
and determine which one to serve. The software
has to clear the interrupt flag in the Status Register
after serving the interrupt.
Table 73. TCMMODE0 - TCMMODE5 (6 Registers, Reset Value 00h)
Table 74. TCMMODE Register Configurations
Note: 1. 10-bit PWM mode requires the 10B_PWM Bit in the PCACON Register set to '1.'
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM[1:0]
Details
Bit Symbol Function
7 EINTF 1 - Enable the interrupt flags (INTF) in the Status Register to generate an interrupt.
6 E_COMP 1 - Enable the comparator when set
5 CAP_PE 1 - Enable Capture Mode, a positive edge on the CEXn pin.
4 CAP_NE 1 - Enable Capture Mode, a negative edge on the CEXn pin.
3 MATCH 1 - A match from the comparator sets the INTF bits in the Status Register.
2 TOGGLE 1 - A match on the comparator results in a toggling output on CEXn pin.
1-0 PWM[1:0]
01 Enable PWM Mode (x8), fixed frequency. Enable the CEXn pin as a PWM output.
10 Enable PWM Mode (x8) with programmable frequency. Enable the CEXn pin as a
PWM output.
11 Enable PWM Mode (x10 or x16), fixed frequency. Enable the CEXn pin as a PWM
output.
EINTF E_COMP CAP_PE CAP_NE MATCH TOGGLE PWM1 PWM0 TCM FUNCTION
0 0 0 0 0 0 0 0 No operation (reset value)
0 1 0 0 0 0 0 1 8-bit PWM, fixed frequency
0 1 0 0 0 0 10 8-bit PWM, programmable
frequency
0 1 0 0 0 0 11 10-bit or 16-bit PMW, fixed
frequency(1)
X 1 0 0 1 1 0 0 16-bit toggle
X 1 0 0 1 0 0 0 16-bit Software Timer
X X 0 1 0 0 0 0 16-bit capture, negative trigger
X X 1 0 0 0 0 0 16-bit capture, positive trigger
X X 1 1 0 0 0 0 16-bit capture, transition trigger133/231
uPSD33xx
PSD MODULE
The PSD Module is stacked with the MCU Module
to form the uPSD33xx, see uPSD33xx HARDWARE
DESCRIPTION, page 13. Details of the
PSD Module are shown in Figure 51. The two separate
modules interface with each other at the
8032 Address, Data, and Control interface blocks
in Figure 51.
Figure 51. PSD Module Block Diagram PD1 PD2 PORT D PA0 PA1 PA2
PA3
PA4
PA5
PA6
PA7
PORT B
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
GENERAL PLD
20 INPUT
MACROCELLS
A
B
16 OUTPUT MACROCELLS
A
B
A
B
A
B
A
B
A
B
A
B
A
B
B
C
B
C
B
C
B
C
B
C
B
C
B
C
B
C
SECURITY
LOCK
PLD INPUT BUS
PIN FEEDBACK
NODE FEEDBACK
PSD Module: uPSD33XX
DECODE
PLD
AND-OR
ARRAY
FS0-7
AAAAAAAA
BBBBBBBB
C
C
C
C
TO PLD
INPUT
BUS
PORT C
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7 JTAG-ISP TO ALL
AREAS OF PSD
MODULE
ADDR, DATA, CONTROL BUS LINKED TO 8032 MCU
RUNTIME CONTROL, 256 REGs
GPIO, VM, PAGE
POWER MNGMT
CSIOP
PLD
CSBOOT0-3
EXTERNAL
CHIPSELECTS
MAIN FLASH MEMORY
Up to 8 SEGMENTS
FS0
Up to 256 KBytes TOTAL
FS7
2nd FLASH MEMORY
Up to 4 SEGMENTS
Up to 32 KBytes TOTAL
CSBOOT0
CSBOOT3
DATA
ADDRESS
LATCH
LOW
ADDR
HIGH
ADDR
8032 MUX
ADDR/DATA
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
8032 HI
ADDR
A8
A9
A10
A11
A12
A13
A14
A15
8032 CNTL
RD
WR
PSEN
ALE
RST
8032 MCU Module
PORT A
(80-pin
only)
TO JTAG DEBUG ON MCU
GPIO
PLD
GPIO
GPIO
GPIO
8 PIN INPUTS
MCU READ or WRITE
MCU READ
PLD OUT
PLD OUT
PLD OUT
PLD OUT
PLD OUT
JTAG
CNTL 8 PIN INPUTS
4 PIN INPUTS
MCU
READ or
WRITE
RS0
Up to 32 KBytes
SRAM
PAGE REG
JTAG
OMC
ALLOCATOR
AND-OR
ARRAY
69 INPUTS
69 INPUTS
AI07872B
PLD INPUT BUSuPSD33xx
134/231
PSD Module Functional Description
Major functional blocks are shown in Figure
51., page 133. The next sections describe each
major block.
8032 Address/Data/Control Interface. These
signals attach directly to the MCU Module to implement
a typical multiplexed 8051-style bus between
the two stacked die. The MCU instruction
prefetch and branch cache logic resides on the
MCU Module, leaving a standard 8051-style memory
interface on the PSD Module.
The active-low reset signal originating from the
MCU Module goes to the PSD Module reset input
(RST). This reset signal can then be routed as an
external output from the uPSD33xx to the system
PC board, if needed, through any one of the PLD
output pins as active-high or active-low logic by
specifying logic equations in PSDsoft Express.
The 8032 address and data busses are routed
throughout the PSD Module as shown in Figure 51
connecting many elements on the PSD Module to
the 8032 MCU. The 8032 bus is not only connected
to the memories, but also to the General PLD,
making it possible for the 8032 to directly read and
write individual logic macrocells inside the General
PLD.
Dual Flash Memories and IAP. uPSD33xx devices
contain two independent Flash memory arrays.
This means that the 8032 can read
instructions from one Flash memory array while
erasing or writing the other Flash memory array.
Concurrent operation like this enables robust remote
updates of firmware, also known as In-Application
Programming (IAP). IAP can occur using
any uPSD33xx interface (e.g., UART, I2C, SPI).
Concurrent memory operation also enables the
designer to emulate EEPROM memory within either
of the two Flash memory arrays for small data
sets that have frequent updates.
The 8032 can erase Flash memories by individual
sectors or it can erase an entire Flash memory array
at one time. Each sector in either Flash memory
may be individually write protected, blocking
any WRITEs from the 8032 (good for boot and
start-up code protection). The Flash memories automatically
go to standby between 8032 READ or
WRITE accesses to conserve power. Minimum
erase cycles is 100K and minimum data retention
is 15 years. Flash memory, as well as the entire
PSD Module may be programmed with the JTAG
In-System Programming (ISP) interface with no
8032 involvement, good for manufacturing and lab
development.
Main Flash Memory. The Main Flash memory is
divided into equal sized sectors that are individually
selectable by the Decode PLD output signals,
named FSx, one signal for each Main Flash memory
sector. Each Flash sector can be located at
any address within 8032 program address space
(accessed with PSEN) or data address space,
also known as 8032 XDATA space (accessed with
RD or WR), as defined with the software development
tool, PSDsoft Express. The user only has to
specify an address range for each segment and
specify if Main Flash memory will reside in 8032
data or program address space, and then PSEN,
RD, or WR are automatically activated for the
specified range. 8032 firmware is easily programmed
into Main Flash memory using PSDsoft
Express or other software tools. See Table
75., page 135 for Main Flash sector sizes on the
various uPSD33xx devices.
Secondary Flash Memory. The smaller Secondary
Flash memory is also divided into equal sized
sectors that are individually selectable by the Decode
PLD signals, named CSBOOTx, one signal
for each Secondary Flash memory sector. Each
sector can be located at any address within 8032
program address space (accessed with PSEN) or
XDATA space (accessed with RD or WR) as defined
with PSDsoft Express. The user only has to
specify an address range for each segment, and
specify if Secondary Flash memory will reside in
8032 data or program address space, and then
PSEN, RD, or WR are automatically activated for
the specified range. 8032 firmware is easily programmed
into Secondary Flash memory using PSDsoft
Express and others. See Table
75., page 135 for Secondary Flash sector sizes.
SRAM. The SRAM is selected by a single signal,
named RS0, from the Decode PLD. SRAM may be
located at any address within 8032 XDATA space
(accessed with RD or WR), or optionally within
8032 program address space (accessed with
PSEN) to execute code from SRAM. The default
setting places SRAM in XDATA space only. These
choices are specified using PSDSoft Express,
where the user specifies an SRAM address range.
The user would also specify (at run-time) if SRAM
will additionally reside in 8032 program address
space, and then PSEN, RD, or WR are automatically
activated for the specified range. See Table
75., page 135 for SRAM sizes.
The SRAM may optionally be backed up by an external
battery (or other DC source) to make its contents
non-volatile (see SRAM Standby Mode
(battery backup), page 193).135/231
uPSD33xx
Table 75. uPSD33xx Memory Configuration
Runtime Control Registers, CSIOP. A block of
256 bytes is decoded inside the PSD Module for
module control and status (see Table
79., page 145). The base address of these 256 locations
is referred to in this data sheet as csiop
(Chip Select I/O Port), and is selected by the Decode
PLD output signal, CSIOP. The csiop registers
are always viewed by the 8032 as XDATA,
and are accessed with RD and WR signals. The
address range of CSIOP is specified using PSDsoft
Express where the user only has to specify an
address range of 256 bytes, and then the RD or
WR signals are automatically activated for the
specified range. Individual registers within this
block are accessed with an offset from the specified
csiop base address. 39 registers are used out
of the 256 locations to control the output state of I/
O pins, to read I/O pins, to set the memory page,
to control 8032 program and data address space,
to control power management, to READ/WRITE
macrocells inside the General PLD, and other
functions during runtime. Unused locations within
csiop are reserved and should not be accessed.
Memory Page Register. 8032 MCU architecture
has an inherent size limit of 64K bytes in either
program address space or XDATA space. Some
uPSD33xx devices have much more memory that
64K, so special logic such as this page register is
needed to access the extra memory. This 8-bit
page register (Figure 52) can be loaded and read
by the 8032 at runtime as one of the csiop registers.
Page register outputs feed directly into both
PLDs creating extended address signals used to
“page” memory beyond the 64K byte limit (program
space or XDATA). Most 8051 compilers directly
support memory paging, also known as
memory banking. If memory paging is not needed,
or if not all eight page register bits are needed for
memory paging, the remaining bits may be used in
the General PLD for general logic. Page Register
outputs are cleared to logic ’0’ at reset and powerup.
Programmable Logic (PLDs) . The uPSD33xx
contains two PLDs (Figure 63., page 157) that
may optionally run in Turbo or Non-Turbo mode.
PLDs operate faster (less propagation delay)
while in Turbo mode but consume more power
than in Non-Turbo mode. Non-Turbo mode allows
the PLDs to go to standby automatically when no
PLD inputs are changing to conserve power.
The logic configuration (from equations) of both
PLDs is stored with non-volatile Flash technology
and the logic is active upon power-up. PLDs may
NOT be programmed by the 8032, PLD programming
only occurs through the JTAG interface.
Figure 52. Memory Page Register
Device
Main Flash Memory Secondary Flash Memory SRAM
Total
Flash Size
(bytes)
Individual
Sector Size
(bytes)
Number of
Sectors (Sector
Select Signal)
Total
Flash Size
(bytes)
Individual
Sector Size
(bytes)
Number of
Sectors (Sector
Select Signal)
SRAM
Size
(bytes)
uPSD3312 64K 16K 4 (FS0-3) 16K 8K 2 (CSBOOT0-1) 2K
uPSD3333 128K 16K 8 (FS0-7) 32K 8K 4 (CSBOOT0-3) 8K
uPSD3334 256K 32K 8 (FS0-7) 32K 8K 4 (CSBOOT0-3) 8K
uPSD3354 256K 32K 8 (FS0-7) 32K 8K 4 (CSBOOT0-3) 32K
8032
Data
Bus
Load or
Read via
csiop +
offset E0h
D0
D7
D6
D5
D4
D3
D2
D1
Q0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
DPLD
and
GPLD
Page
Register
ChipSelects
and
General
Logic
RST
(PSD Module Reset)
RST
PGR0-7
AI09172uPSD33xx
136/231
PLD #1, Decode PLD (DPLD). This programmable
logic implements memory mapping and is used
to select one of the individual Main Flash memory
segments, one of individual Secondary Flash
memory segments, the SRAM, or the group of
csiop registers when the 8032 presents an address
to DPLD inputs (see Figure 64., page 159).
The DPLD can also optionally drive external chip
select signals on Port D pins. The DPLD also optionally
produces two select signals (PSEL0 and
PSEL1) used to enable a special data bus repeater
function on Port A, referred to as Peripheral I/O
Mode. There are 69 DPLD input signals which include:
8032 address and control signals, Page
Register outputs, PSD Module Port pin inputs, and
GPLD logic feedback.
PLD #2, General PLD (GPLD). This programmable
logic is used to create both combinatorial
and sequential general purpose logic (see Figure
65., page 161). The GPLD contains 16 Output
Macrocells (OMCs) and 20 Input Macrocells
(IMCs). Output Macrocell registers are unique in
that they have direct connection to the 8032 data
bus allowing them to be loaded and read directly
by the 8032 at runtime through OMC registers in
csiop. This direct access is good for making small
peripheral devices (shifters, counters, state machines,
etc.) that are accessed directly by the 8032
with little overhead. There are 69 GPLD inputs
which include: 8032 address and control signals,
Page Register outputs, PSD Module Port pin inputs,
and GPLD feedback.
OMCs. There are two banks of eight OMCs inside
the GPLD, MCELLAB, and MCELLBC, totalling 16
OMCs all together. Each individual OMC is a base
logic element consisting of a flip-flop and some
AND-OR logic (Figure 66., page 162). The general
structure of the GPLD with OMCs is similar in
nature to a 22V10 PLD device with the familiar
sum-of-products (AND-OR) construct. True and
compliment versions of 69 input signals are available
to the inputs of a large AND-OR array. ANDOR
array outputs feed into an OR gate within each
OMC, creating up to 10 product-terms for each
OMC. Logic output of the OR gate can be passed
on as combinatorial logic or combined with a flipflop
within in each OMC to realize sequential logic.
OMC outputs can be used as a buried nodes driving
internal feedback to the AND-OR array, or
OMC outputs can be routed to external pins on
Ports A, B, or C through the OMC Allocator.
OMC Allocator. The OMC allocator (Figure
67., page 163) will route eight of the OMCs from
MCELLAB to pins on either Port A or Port B, and
will route eight of the OMCs from MCELLBC to
pins on either Port B or Port C, based on what is
specified in PSDsoft Express.
IMCs. Inputs from pins on Ports A, B, and C are
routed to IMCs for conditioning (clocking or latching)
as they enter the chip, which is good for sampling
and debouncing inputs. Alternatively, IMCs
can pass port input signals directly to PLD inputs
without clocking or latching (Figure
68., page 167). The 8032 may read the IMCs
asynchronously at any time through IMC registers
in csiop.
Note: The JTAG signals TDO, TDI, TCK, and TMS
on Port C do not route through IMCs, but go directly
to JTAG logic.
I/O Ports. For 80-pin uPSD33xx devices, the
PSD Module has 22 individually configurable I/O
pins distributed over four ports (these I/O are in
addition to I/O on MCU Module). For 52-pin
uPSD33xx devices, the PSD Module has 13 individually
configurable I/O pins distributed over
three ports. See Figure 74., page 181 for I/O port
pin availability on these two packages.
I/O port pins on the PSD Module (Ports A, B, C,
and D) are completely separate from the port pins
on the MCU Module (Ports 1, 3, and 4). They even
have different electrical characteristics. I/O port
pins on the PSD Module are accessed by csiop
registers, or they are controlled by PLD equations.
Conversely, I/O Port pins on the MCU Module are
controlled by the 8032 SFR registers.
Table 76. General I/O pins on PSD Module
Note: Four pins on Port C are dedicated to JTAG, leaving four pins
for general I/O.
Pkg Port A Port B Port D Port D Total
52-pin 0 8 4 1 13
80-pin 8 8 4 2 22137/231
uPSD33xx
Each I/O pin on the PSD Module can be individually
configured for different functions on a pin-bypin
basis (Figure 69., page 169). Following are the
available functions on PSD Module I/O pins.
– MCU I/O: 8032 controls the output state of
each port pin or it reads input state of each
port pin, by accessing csiop registers at runtime.
The direction (in or out) of each pin is
also controlled by csiop registers at run-time.
– PLD I/O: PSDsoft Express logic equations
and pin configuration selections determine if
pins are connected to OMC outputs or IMC
inputs. This is a static and non-volatile
configuration. Port pins connected to PLD
outputs can no longer be driven by the 8032
using MCU I/O output mode.
– Latched MCU Address Output: Port A or
Port B can output de-multiplexed 8032
address signals A0 - A7 on a pin-by-pin basis
as specified in csiop registers at run-time. In
addition, Port B can also be configured to
output de-multiplexed A8-A15 in PSDsoft
Express.
– Data Bus Repeater: Port A can bidirectionally
buffer the 8032 data bus (demultiplexed)
for a specified address range in
PSDsoft Express. This is referred to as
Peripheral I/O Mode in this document.
– Open Drain Outputs: Some port pins can
function as open-drain as specified in csiop
registers at run-time.
– Pins on Port D can be used for external chipselect
outputs originating from the DPLD,
without consuming OMC resources within the
GPLD.
JTAG Port. In-System Programming (ISP) can
be performed through the JTAG signals on Port C.
This serial interface allows programming of the entire
PSD Module device or subsections of the PSD
Module (for example, only Flash memory but not
the PLDs) without the participation of the 8032. A
blank uPSD33xx device soldered to a circuit board
can be completely programmed in 10 to 25 seconds.
The four basic JTAG signals on Port C;
TMS, TCK, TDI, and TDO form the IEEE-1149.1
interface. The PSD Module does not implement
the IEEE-1149.1 Boundary Scan functions, but
uses the JTAG interface for ISP an 8032 debug.
The PSD Module can reside in a standard JTAG
chain with other JTAG devices and it will remain in
BYPASS mode when other devices perform JTAG
functions.
ISP programming time can be reduced as much as
30% by using two optional JTAG signals on Port
C, TSTAT and TERR, in addition to TMS, TCK,
TDI and TDO, and this is referred to as “6-pin
JTAG”. The FlashLINK JTAG programming cable
is available from STMicroelectronics and PSDsoft
Express software is available at no charge from
www.st.com/psm. More JTAG ISP information
maybe found in the section titled “JTAG ISP and
Debug” on page 137.
The MCU module is also included in the JTAG
chain within the uPSD33xx device for 8032 debugging
and emulation. While debugging, the PSD
Module is in BYPASS mode. Conversely, during
ISP, the MCU Module is in BYPASS mode.
Power Management. The PSD Module has bits
in csiop registers that are configured at run-time by
the 8032 to reduce power consumption of the
GPLD. The Turbo Bit in the PMMR0 Register can
be set to logic ’1’ and both PLDs will go to NonTurbo
mode, meaning it will latch its outputs and
go to sleep until the next transition on its inputs.
There is a slight penalty in PLD performance
(longer propagation delay), but significant power
savings are realized. Going to Non-Turbo mode
may require an additional wait state in the 8032
SFR, BUSCON, because memory decode signals
are also delayed. The default state of the Turbo Bit
is logic '0,' meaning by default, the GPLD is in fast
Turbo mode until the Turbo mode is turned off.
Additionally, bits in csiop registers PMMR0 and
PMMR2 can be set by the 8032 to selectively
block signals from entering both PLDs which further
reduces power consumption. There is also an
Automatic Power Down counter that detects lack
of 8032 activity and reduces power consumption
on the PSD Module to its lowest level (see Power
Management, page 137).uPSD33xx
138/231
Security and NVM Sector Protection. A programmable
security bit in the PSD Module protects
its contents from unauthorized viewing and
copying. The security bit is specified in PSDsoft
Express and programmed into the uPSD33xx with
JTAG. Once set, the security bit will block access
of JTAG programming equipment to the PSD Module
Flash memory and PLD configuration, and also
blocks JTAG debugging access to the MCU Module.
The only way to defeat the security bit is to
erase the entire PSD Module using JTAG (the
erase command is the only JTAG command allowed
after the security bit has been set), after
which the device is blank and may be used again.
Additionally and independently, the contents of
each individual Flash memory sector can be write
protected (sector protection) by configuration with
PSDsoft Express. This is typically used to protect
8032 boot code from being corrupted by inadvertent
WRITEs to Flash memory from the 8032.
Status of sector protection bits may be read (but
not written) using two registers in csiop space.
Memory Mapping
There many different ways to place (or map) the
address range of PSD Module memory and I/O
depending on system requirements. The DPLD
provides complete mapping flexibility. Figure 53
shows one possible system memory map. In this
example, 128K bytes of Main Flash memory for a
uPSD3333 device is in 8032 program address
space, and 32K bytes of Secondary Flash memory,
the SRAM, and csiop registers are all in 8032
XDATA space.
In Figure 53, the nomenclature fs0..fs7 are designators
for the individual sectors of Main Flash
memory, 16K bytes each. CSBOOT0..CSBOOT3
are designators for the individual Secondary Flash
memory segments, 8K bytes each. rs0 is the designator
for SRAM, and csiop designates the PSD
Module control register set.
The designer may easily specify memory mapping
in a point-and-click software environment using
PSDsoft Express, creating a non-volatile configuration
when the DPLD is programmed using
JTAG.
8032 Program Address Space. In the example
of Figure 53, six sectors of Main Flash memory
(fs2.. fs7) are paged across three memory pages
in the upper half of program address space, and
the remaining two sectors of Main Flash memory
(fs0, fs1) reside in the lower half of program address
space, and these two sectors are independent
of paging (they reside in “common” program
address space). This paged memory example is
quite common and supported by many 8051 software
compilers.
8032 Data Address Space (XDATA). Four sectors
of Secondary Flash memory reside in the upper
half of 8032 XDATA space in the example of
Figure 53. SRAM and csiop registers are in the
lower half of XDATA space. The 8032 SFR registers
and local SRAM inside the 8032 MCU Module
do not reside in XDATA space, so it is OK to place
PSD Module SRAM or csiop registers at an address
that overlaps the address of internal 8032
MCU Module SRAM and registers.
Figure 53. Typical System Memory Map
0000h
8000h
A000h
C000h
E000h
FFFFh
8032 XDATA
SPACE
(RD and WR)
8032 PROGRAM SPACE
(PSEN)
csboot0
8KB
csboot1
8KB
csboot2
8KB
csboot3
8KB
Page X
fs0, 16KB
Common Memory to All Pages
fs7
16KB
fs5
16KB
fs3
16KB
rs0, 8KB
Page 0 Page 2 Page 1
2000h
0000h
8000h
FFFFh
System
I/O
fs6
16KB
fs4
16KB
fs2
16KB
fs1, 16KB
Common Memory to All Pages
C000h
4000h
csiop
256B
AI09173139/231
uPSD33xx
Specifying the Memory Map with PSDsoft Express.
The memory map example shown in FieuPSD33xx
140/231
EEPROM Emulation. EEPROM emulation is
needed if it is desired to repeatedly change only a
small number of bytes of data in Flash memory. In
this case EEPROM emulation is needed because
although Flash memory can be written byte-bybyte,
it must be erased sector-by-sector, it is not
erasable byte-by-byte (unlike EEPROM which is
written AND erased byte-by-byte). So changing
one or two bytes in Flash memory typically requires
erasing an entire sector each time only one
byte is changed within that sector.
However, two of the 8K byte sectors of Secondary
Flash memory may be used to emulate EEPROM
by using a linked-list software technique to create
a small data set that is maintained by alternating
between the two flash sectors. For example, a
data set of 128 bytes is written and maintained by
software in a distributed fashion across one 8K
byte sector of Secondary Flash memory until it becomes
full. Then the writing continues on the other
8K byte sector while erasing the first 8K byte sector.
This process repeats continuously, bouncing
back and forth between the two 8K byte sectors.
This creates a wear-leveling effect, which increases
the effective number of erase cycles for a data
set of 128 bytes to many times more than the base
100K erase cycles of the Flash memory. EEPROM
emulation in Flash memory is typically faster than
writing to actual EEPROM memory, and more reliable
because the last known value in a data set is
maintained even if a WRITE cycle is corrupted by
a power outage. The EEPROM emulation function
can be called by the firmware, making it appear
that the user is writing a single byte, or data
record, thus hiding all of the data management
that occurs within the two 8K byte flash sectors.
EEPROM emulation firmware for the uPSD33xx is
available from www.st.com/psm.
Alternative Mapping Schemes. Here are more
possible memory maps for the uPSD3333.
Note: Mapping examples would be slightly different
for uPSD3312, uPSD3334, and uPSD3354
because of the different sizes of individual Flash
memory sectors and SRAM as defined in Table
82., page 155.
– Figure 55. Place the larger Main Flash
Memory into program space, but split the
Secondary Flash in half, placing two of it’s
sectors into XDATA space and remaining two
sectors into program space. This method
allows the designer to put IAP code (or boot
code) into two sectors of Secondary Flash in
program space, and use the other two
Secondary Flash sectors for data storage,
such as EEPROM emulation in XDATA space.
– Figure 56. Place both the Main and
Secondary Flash memories into program
space for maximum code storage, with no
Flash memory in XDATA space.
Figure 55. Mapping: Split Second Flash in Half
Figure 56. Mapping: All Flash in Code Space
0000h
8000h
4000h
6000h
FFFFh
8032 XDATA SPACE
(RD and WR)
8032 PROGRAM
SPACE (PSEN)
csboot1, 8KB
Common Memory to All Pages
csboot0, 8KB
Common Memory to All Pages
csboot2
8KB
csboot3
8KB
Page X
rs0, 8KB
csiop, 256B
fs7
16KB
fs3
16KB
fs1
16KB
Page
0
Page
1
Page
2
Page
3
2000h
0000h
8000h
FFFFh
Nothing Mapped
fs6
16KB
fs5
16KB
fs4
16KB
fs2
16KB
fs0
16KB
System I/O
System I/O
C000h
2100h
4000h
2000h
AI09174
0000h
8000h
4000h
6000h
FFFFh
8032 XDATA SPACE
(RD and WR)
8032 PROGRAM
SPACE (PSEN)
csboot1, 8KB
Common Memory to All Pages
csboot0, 8KB
Common Memory to All Pages
csboot2, 8KB
Common Memory to All Pages
csboot3, 8KB
Common Memory to All Pages
Page X
rs0, 8KB
csiop, 256B
fs7
16KB
fs3
16KB
fs1
16KB
Page
0
Page
1
Page
2
Page
3
2000h
0000h
FFFFh
fs6
16KB
fs5
16KB
fs4
16KB
fs2
16KB
fs0
16KB System I/O
C000h
2100h
2000h
AI09175141/231
uPSD33xx
– Figure 57. Place the larger Main Flash
Memory into XDATA space and the smaller
Secondary Flash into program space for
systems that need a large amount of Flash for
data recording or large look-up tables, and not
so much Flash for 8032 firmware.
Figure 57. Mapping: Small Code / Big Data
It is also possible to “reclassify” the Flash memories
during runtime, moving the memories between
XDATA memory space and program
memory space on-the-fly. This essentially means
that the user can override the initial setting during
run-time by writing to a csiop register (the VM Register).
This is useful for IAP, because standard
8051 architecture does not allow writing to program
space. For example, if the user wants to update
firmware in Main Flash memory that is
residing in program space, the user can temporarily
“reclassify” the Main Flash memory into XDATA
space to erase and rewrite it while executing IAP
code from the Secondary Flash memory in program
space. After the writing is complete, the Main
Flash can be “reclassified” back to program space,
then execution can continue from the new code in
Main Flash memory. The mapping example of Figure
57 will accommodate this operation.
Memory Sector Select Rules. When defining
sector select signals (FSx, CSBOOTx, RS0,
CSIOP, PSELx) in PSDsoft Express, keep these
rules in mind:
– Main Flash and Secondary Flash memory
sector select signals may not be larger than
their physical sector size as defined in Table
75., page 135.
– Any Main Flash memory sector select may not
be mapped in the same address range as
another Main Flash sector select (cannot
overlap segments of Main Flash on top of
each other).
– Any Secondary Flash memory sector select
may not be mapped in the same address
range as another Secondary Flash sector
select (cannot overlap segments of
Secondary Flash on top of each other).
– A Secondary Flash memory sector may
overlap a Main Flash memory sector. In the
case of overlap, priority is given to the
Secondary Flash memory sector.
– SRAM, CSIOP, or PSELx may overlap any
Flash memory sector. In the case of overlap,
priority is given to SRAM, CSIOP, or PSELx.
Note: PSELx is for optional Peripheral I/O
Mode on Port A.
– The address range for sector selects for
SRAM, PSELx, and CSIOP must not overlap
each other as they have the same priority,
causing contention if overlapped.
0000h
8000h
4000h
6000h
FFFFh
8032 XDATA SPACE
(RD and WR)
8032 PROGRAM
SPACE (PSEN)
csboot0
8KB
csboot1
8KB
csboot2
8KB
csboot3
8KB
Page X
rs0, 8KB
Common Memory to All Pages
csiop, 256 bytes,
Common to All Pages
fs7
16KB
fs3
16KB
fs1
16KB
Page
0
Page
1
Page
2
Page
3
2000h
0000h
8000h
FFFFh
Nothing
Mapped
fs6
16KB
fs5
16KB
fs4
16KB
fs2
16KB
fs0
16KB
System I/O
C000h
2100h
2000h
AI09176uPSD33xx
142/231
Figure 58 illustrates the priority scheme of the
memory elements of the PSD Module. Priority refers
to which memory will ultimately produce a
byte of data or code to the 8032 MCU for a given
bus cycle. Any memory on a higher level can overlap
and has priority over any memory on a lower
level. Memories on the same level must not overlap.
Example: FS0 is valid when the 8032 produces an
address in the range of 8000h to BFFFh.
CSBOOT0 is valid from 8000h to 9FFFh. RS0 is
valid from 8000h to 87FFh. Any address from the
8032 in the range of RS0 always accesses the
SRAM. Any address in the range of CSBOOT0
greater than 87FFh (and less than 9FFFh) automatically
addresses Secondary Flash memory.
Any address greater than 9FFFh accesses Main
Flash memory. One-half of the Main Flash memory
segment, and one-fourth of the Secondary
Flash memory segment cannot be accessed by
the 8032 in this example.
Figure 58. PSD Module Memory Priority
The VM Register. One of the csiop registers (the
VM Register) controls whether or not the 8032 bus
control signals RD, WR, and PSEN are routed to
the Main Flash memory, the Secondary Flash
memory, or the SRAM. Routing of these signals to
these PSM Module memories determines if memories
reside in 8032 program address space, 8032
XDATA space, or both. The initial setting of the VM
Register is determined by a choice in PSDsoft Express
and programmed into the uPSD33xx in a
non-volatile fashion using JTAG. This initial setting
is loaded into the VM Register upon power-up and
also loaded upon any reset event. However, the
8032 may override the initial VM Register setting
at run-time by writing to the VM Register, which is
useful for IAP.
Table 78., page 143 defines bit functions within
the VM Register.
Note: Bit 7, PIO_EN, is not related to the memory
manipulation functions of Bits 0, 1, 2, 3, and 4.
Also note that SRAM must at least always be in
8032 XDATA space (default condition). Bit 0 allows
the user to optionally place SRAM into 8032
program space in addition to XDATA space.
CSIOP registers are always in XDATA space and
cannot reside in program space.
Figure 59., page 144 illustrates how the VM Register
affects the routing of RD, WR, and PSEN to
the memories on the PSD Module. As an example,
if we apply the value 0Ch to the VM Register to implement
the memory map example shown in Figure
53., page 138, then the routing of RD, WR,
and PSEN would look like that shown in Figure
60., page 145.
In this example, the configuration is specified in
PSDsoft Express and programmed into the
uPSD33xx using JTAG. Upon power-on or any reset
condition, the non-volatile value 0Ch is loaded
into the VM Register. At runtime, the value 0Ch in
the VM Register may be changed (overridden) by
the 8032 if desired to implement IAP or other functions.
Level 1
SRAM,
CSIOP, and
Peripheral I/O
Mode
Highest Priority
Level 2
Secondary
Flash Memory
Level 3
Main Flash Memory
Lowest Priority AI02867E143/231
uPSD33xx
Table 78. VM Register (address = csiop + offset E2h)
Note: 1. Default value of Bits 0, 1, 2, 3, and 4 is loaded from Non-Volatile setting as specified from PSDsoft Express upon any reset or powerup
condition. The default value of these bits can be overridden by 8032 at run-time.
2. Default value of Bit 7 is zero upon any reset condition.
Bit 7
PIO_EN Bit 6 Bit 5
Bit 4
Main Flash
XDATA
Space
Bit 3
Secondary
Flash XDATA
Space
Bit 2
Main Flash
Program
Space
Bit 1
Secondary
Flash
Program
Space
Bit 0
SRAM
Program
Space
0 = disable
Peripheral I/O
Mode on Port A
not used not used
0 = RD or WR
cannot
access Main
Flash
0 = RD or WR
cannot
access
Secondary
Flash
0 = PSEN
cannot
access Main
Flash
0 = PSEN
cannot
access
Secondary
Flash
0 = PSEN
cannot
access
SRAM
1 = enable
Peripheral I/O
Mode on Port A
not used not used
1 = RD or WR
can access
Main Flash
1 = RD or WR
can access
Secondary
Flash
1 = PSEN
can access
Main Flash
1 = PSEN
can access
Secondary
Flash
1 = PSEN
can access
SRAMuPSD33xx
144/231
Figure 59. VM Register Control of Memories
DPLD
Main Flash
Memory
Secondary
Flash
Memory
SRAM
CS
CS CS
FS0 - FS7
CSBOOT0 - CSBOOT3
RS0
WR
VM REG BIT 4
VM REG BIT 3145/231
uPSD33xx
Figure 60. VM Register Example Corresponding to Memory Map Example of Figure 33
Runtime Control Register Definitions (csiop)
The 39 csiop registers are defined in Table 79.
The 8032 can access each register by the address
offset (specified in Table 79) added to the csiop
base address that was specified in PSDsoft Express.
Do not write to unused locations within the
csiop block of 256 registers, they should remain
logic zero.
Table 79. CSIOP Registers and their Offsets (in hexadecimal)
DPLD
Main Flash
Memory
Secondary
Flash
Memory
SRAM
CS
CS CS
FS0 - FS7
CSBOOT0 - CSBOOT3
RS0
WR OE WR OE WR OE
8032 Address
53 Other PLD Inputs
WR
PSEN
RD
VM Register = 0Ch
AI02869D
Register
Name
Port A
(80-pin) Port B Port C Port D Other Description Link
Data In 00h 01h 10h 11h
MCU I/O input mode. Read to obtain
current logic level of pins on Ports A, B,
C, or D. No WRITEs.
Table
95., page
172
Control 02h 03h
Selects MCUI/O or Latched Address
Out mode. Logic 0 = MCU I/O, 1 = 8032
Addr Out. Write to select mode. Read for
status.
Table
107., page
177
Data Out 04h 05h 12h 13h
MCU I/O output mode. Write to set logic
level on pins of Ports A, B, C, or D. Read
to check status. This register has no
effect if a port pin is driven by an OMC
output from PLD.
Table
99., page
172
Direction 06h 07h 14h 15h
MCU I/O mode. Configures port pin as
input or output. Write to set direction of
port pins.
Logic 1 = out, Logic 0 = in. Read to
check status.
Table
103., page
173
Drive Select 08h 09h 16h 17h
Write to configure port pins as either
CMOS push-pull or Open Drain on some
pins, while selecting high slew rate on
other pins. Read to check status. Default
output type is CMOS push-pull.
Table
109., page
179uPSD33xx
146/231
Input
Macrocells 0Ah 0Bh 18h Read to obtain logic state of IMCs. No
WRITEs.
Table
90., page
167
Enable Out OCh 0Dh 1Ah 1Bh
Read state of output enable logic on
each I/O port driver. 1 = driver output is
enabled, 0 = driver is off, and it is in high
impedance state. No WRITEs.
Table
113., page
180
Output
Macrocells AB
(MCELLAB)
20h
Read logic state of MCELLAB outputs
(bank of eight OMCs).
Write to load MCELLAB flip-flops.
Table
86., page
165
Output
Macrocells BC
(MCELLBC)
21h
Read logic state of MCELLBC outputs
(bank of eight OMCs).
Write to load MCELLBC flip-flops.
Table
87., page
165
Mask
Macrocells AB 22h
Write to set mask for MCELLAB. Logic
'1' blocks READs/WRITEs of OMC.
Logic '0' will pass OMC value. Read to
check status.
Table
88., page
166
Mask
Macrocells BC 23h
Write to set mask for MCELLBC. Logic
'1' blocks READs/WRITEs of OMC.
Logic '0' will pass OMC value. Read to
check status.
Table
89., page
166
Main Flash
Sector
Protection
C0h
Read to determine Main Flash Sector
Protection Setting (non-volatile) that was
specified in PSDsoft Express. No
WRITEs.
Table
82., page
155
Security Bit
and Secondary
Flash Sector
Protection
C2h
Read to determine if PSD Module
device Security Bit is active (nonvolatile)
Logic 1 = device secured. Also
read to determine Secondary Flash
Protection Setting (non-volatile) that was
specified in PSDsoft. No WRITEs.
Table
83., page
155
PMMR0 B0h Power Management Register 0. WRITE
and READ.
Table
117., page
188
PMMR2 B4h Power Management Register 2. WRITE
and READ.
Table
118., page
188
PMMR3 C7h
Power Management Register 3. WRITE
and READ. However, Bit 1 can be
cleared only by a reset condition.
Table
119., page
188
Page E0h Memory Page Register. WRITE and
READ.
Figure
52., page
135
VM (Virtual
Memory) E2h
Places PSD Module memories into 8032
Program Address Space and/or 8032
XDATA Address Space. (VM overrides
initial non-volatile setting that was
specified in PSDsoft Express. Reset
restores initial setting)
Table
78., page
143
Register
Name
Port A
(80-pin) Port B Port C Port D Other Description Link147/231
uPSD33xx
PSD Module Detailed Operation
Specific details are given here for the following key
functional areas on the PSD Module:
■ Flash Memories
■ PLDs (DPLD and GPLD)
■ I/O Ports
■ Power Management
■ JTAG ISP and Debug Interface
Flash Memory Operation. The Flash memories
are accessed through the 8032 Address, Data,
and Control Bus interfaces. Flash memories (and
SRAM) cannot be accessed by any other bus
master other than the 8032 MCU (these are not
dual-port memories).
The 8032 cannot write to Flash memory as it
would an SRAM (supply address, supply data,
supply WR strobe, assume the data was correctly
written to memory). Flash memory must first be
“unlocked” with a special instruction sequence of
byte WRITE operations to invoke an internal algorithm
inside either Flash memory array, then a single
data byte is written (programmed) to the Flash
memory array, then programming status is
checked by a byte READ operation or by checking
the Ready/Busy pin (PC3). Table 80., page 148
lists all of the special instruction sequences to program
a byte to either of the Flash memory arrays,
erase the arrays, and check for different types of
status from the arrays.
This unlocking sequence is typical for many Flash
memories to prevent accidental WRITEs by errant
code. However, it is possible to bypass this unlocking
sequence to save time while intentionally
programming Flash memory.
IMPORTANT: The 8032 may not read and execute
code from the same Flash memory array for
which it is directing an instruction sequence. Or
more simply stated, the 8032 may not read code
from the same Flash array that is writing or erasing.
Instead, the 8032 must execute code from an
alternate memory (like SRAM or a different Flash
array) while sending instruction sequences to a
given Flash array. Since the two Flash memory arrays
inside the PSD Module device are completely
independent, the 8032 may read code from one
array while sending instructions to the other. It is
possible, however, to suspend a sector erase operation
in one particular Flash array in order to access
a different sector within that same Flash
array, then resume the erase later.
After a Flash memory array is programmed or
erased it will go to “Read Array” mode, then the
8032 can read from Flash memory just as it would
read from any 8-bit ROM or SRAM device.
Flash Memory Instruction Sequences. An instruction
sequence consists of a sequence of specific
byte WRITE and byte READ operations. Each
byte written to either Flash memory array on the
PSD Module is received by a state machine inside
the Flash array and sequentially decoded to execute
an embedded algorithm. The algorithm is executed
when the correct number of bytes are
properly received and the time between two consecutive
bytes is shorter than the time-out period
of 80µs. Some instruction sequences are structured
to include READ operations after the initial
WRITE operations.
An instruction sequence must be followed exactly.
Any invalid combination of instruction bytes or
time-out between two consecutive bytes while addressing
Flash memory resets the PSD Module
Flash logic into Read Array mode (where Flash
memory is read like a ROM device). The Flash
memories support instruction sequences summarized
in Table 80., page 148.
■ Program a Byte
■ Unlock Sequence Bypass
■ Erase memory by array or by sector
■ Suspend or resume a sector erase
■ Reset to Read Array mode
The first two bytes of an instruction sequence are
8032 bus WRITE operations to “unlock” the Flash
array, followed by writing a command byte. The
bus operations consist of writing the data AAh to
address X555h during the first bus cycle and data
55h to address XAAAh during the second bus cycle.
8032 address signals A12-A15 are “Don’t
care” during the instruction sequence during
WRITE cycles. However, the appropriate sector
select signal (FSx or CSBOOTx) from the DPLD
must be active during the entire instruction sequence
to complete the entire 8032 address (this
includes the page number when memory paging is
used). Ignoring A12-A15 means the user has more
flexibility in memory mapping. For example, in
many traditional Flash memories, instruction sequences
must be written to addresses AAAAh and
5555h, not XAAAh and X555h like supported on
the PSD Module. When AAAAh and 5555h must
be written to, the memory mapping options are limited.
The Main Flash and Secondary Flash memories
each have the same instruction set shown in Table
80., page 148, but the sector select signals determine
which memory array will receive and execute
the instructions.uPSD33xx
148/231
Table 80. Flash Memory Instruction Sequences(1,2)
Instr.
Sequence
Bus
Cycle 1
Bus
Cycle 2
Bus
Cycle 3
Bus
Cycle 4
Bus
Cycle 5
Bus
Cycle 6
Bus
Cycle 7 Link
Read
Memory
Contents
(Read
Array
mode)
Read byte
from any
valid Flash
memory
addr
Read
Memory
Contents., p
age 149
Program
(write) a
Byte to
Flash
Memory
Write AAh
to X555h
(unlock)
Write 55h
to XAAAh
(unlock)
Write A0h
to X555h
(command
)
Write
data byte
to
address
Programmin
g Flash
Memory., pa
ge 150
Bypass
Unlock
Write AAh
to X555h
(unlock)
Write 55h
to XAAAh
(unlock)
Write 20h
to X555h
(command
)
Bypassed
Unlock
Sequence, p
age 153
Program a
Byte to
Flash
Memory
with
Bypassed
Unlock
Write A0h to
XXXXh
(command)
Write data
byte to
address
Bypassed
Unlock
Sequence, p
age 153
Reset
Bypass
Unlock
Write 90h to
XXXXh
(command)
Write 00h
to XXXXh
(command
)
Bypassed
Unlock
Sequence, p
age 153
Flash Bulk
Erase(3)
Write AAh
to X555h
(unlock)
Write 55h
to XAAAh
(unlock)
Write 80h
to X555h
(command
)
Write
AAh to
X555h
(unlock)
Write 55h
to XAAAh
(unlock)
Write 10h
to X555h
(command)
Flash Bulk
Erase., page
153
Flash
Sector
Erase
Write AAh
to X555h
(unlock)
Write 55h
to XAAAh
(unlock)
Write 80h
to X555h
(command
)
Write
AAh to
X555h
(unlock)
Write 55h
to XAAAh
(unlock)
Write 30h
to desired
Sector
(command)
Write 30h
to another
Sector
(command)
Flash Sector
Erase., page
154
Suspend
Sector
Erase
Write B0h to
address that
activates
FSx or
CSBOOTx
where erase
is in
progress
(command)
Suspend
Sector
Erase., page
154
Resume
Sector
Erase
Write 30h to
address that
activates
FSx or
CSBOOTx
where
desired to
resume
erase
(command)
Resume
Sector
Erase., page
154149/231
uPSD33xx
Note: 1. All values are in hexadecimal, X = Don’t care
2. 8032 addresses A12 through A15 are “Don’t care” during the instruction sequence decoding. Only address bits A0-A11 are used
during decoding of Flash memory instruction sequences. The individual sector select signal (FS0 - FS7 or CSBOOT0-CSBOOT3)
which is active during the instruction sequence determines the complete address.
3. Directing this command to any individual sector within a Flash memory array will invoke the bulk erase of all Flash memory sectors
within that array.
Reading Flash Memory. Under typical conditions,
the 8032 may read the Flash memory using
READ operations (READ bus cycles) just as it
would a ROM or RAM device. Alternately, the
8032 may use READ operations to obtain status
information about a Program or Erase operation
that is currently in progress. The following sections
describe the kinds of READ operations.
Read Memory Contents. Flash memory is
placed in the Read Array mode after Power-up, after
a PSD Module reset event, or after receiving a
Reset Flash memory instruction sequence from
the 8032. The 8032 can read Flash memory contents
using standard READ bus cycles anytime the
Flash array is in Read Array mode. Flash memories
will always be in Read Array mode when the
array is not actively engaged in a program or erase
operation.
Reading the Erase/Program Status Bits. The
Flash arrays provide several status bits to be used
by the 8032 to confirm the completion of an erase
or program operation on Flash memory, shown in
Table 81., page 150. The status bits can be read
as many times as needed until an operation is
complete.
The 8032 performs a READ operation to obtain
these status bits while an erase or program operation
is being executed by the state machine inside
each Flash memory array.
Data Polling Flag (DQ7). While programming either
Flash memory, the 8032 may read the Data
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06i)-15.4(h)p)6.3(o))-6.82)7.9(a(o)b)-24.1582 Tw
[dure-7.3(p)-16(l902t)-8.8(he m)-15( 2611]TJ
0 -1.76 TD
-9.0022 Tc
5.0169 T(us)-32.8m)-23.2)-31.65h mus2(o31.65h 22 Tc
5.d169 T(ui(t)14..7(ed by7e)-23.2(t)7.5(s(us)-32.8w)-14.7(h7.5(s(u582.65h2 Tc
5.[-31.65h6(o)-23.5( obt)15.6(a)-23.5(i)81063(n)]TJ15.4(s)-6.5()8.8( o)24.4(sp5( RE)14h)2 TD
02ro9(h.4(s)-6.()8.8( c(s)-6.o TD
02(l)8.p TD
0.7(i)8.)24.4(sRE)14h)e TD
0d)24.4(s.E)14h) Dur6.(i)8)-1(t)15.4(s)-6.5(o)-2-32.878 44.63413.8( ei)8.1(-)]TJ5 or )]TJas)-6.5(8(t)2 .9(eonm)9.6(e)D1(i)c77(o)0.at)-9(u3)-16.9(p)'0..9(m)-'9(rm( )-21551 Tw.5(8(t))7.1(lr)0.9(m)-14a)-23.5se, ou3u3laslel.5(8(t))7o obta -uPSD33xx
150/231
If all the Flash memory sectors selected for erasure
are protected, DQ6 toggles to ’0’ for about
100µs, then returns value of D6 of the previously
addressed byte.
Error Flag (DQ5). During a normal program or
erase operation, the Error Flag Bit (DQ5) is to ’0’.
This bit is set to ’1’ when there is a failure during
Flash memory byte program, sector erase, or bulk
erase operations.
In the case of Flash memory programming, DQ5
Bit indicates an attempt to program a Flash memory
bit from the programmed state of 0, to the
erased state of 1, which is not valid. DQ5 may also
indicate a particular Flash cell is damaged and
cannot be programmed.
In case of an error in a Flash memory sector erase
or byte program operation, the Flash memory sector
in which the error occurred or to which the programmed
byte belongs must no longer be used.
Other Flash memory sectors may still be used.
DQ5 is reset after a Reset Flash instruction sequence.
Erase Time-out Flag (DQ3). The Erase Timeout
Flag Bit (DQ3) reflects the time-out period allowed
between two consecutive sector erase instruction
sequence bytes. If multiple sector erase
commands are desired, the additional sector
erase commands (30h) must be sent by the 8032
within 80us after the previous sector erase command.
DQ3 is 0 before this time period has expired,
indicating it is OK to issue additional sector
erase commands. DQ3 will go to logic ’1’ if the time
has been longer than 80µs since the previous sector
erase command (time has expired), indication
that is not OK to send another sector erase command.
In this case, the 8032 must start a new sector
erase instruction sequence (unlock and
command) beginning again after the current sector
erase operation has completed.
Programming Flash Memory. When a byte of
Flash memory is programmed, individual bits are
programmed to logic '0.' The user cannot program
a bit in Flash memory to a logic ’1’ once it has been
programmed to a logic '0.' A bit must be erased to
logic ’1’, and programmed to logic '0.' That means
Flash memory must be erased prior to being programmed.
A byte of Flash memory is erased to all
1s (FFh). The 8032 may erase the entire Flash
memory array all at once, or erase individual sector-by-sector,
but not erase byte-by-byte. However,
even though the Flash memories cannot be
erased byte-by-byte, the 8032 may program Flash
memory byte-by-byte. This means the 8032 does
not need to program group of bytes (64, 128, etc.)
at one time, like some Flash memories.
Each Flash memory requires the 8032 to send an
instruction sequence to program a byte or to erase
sectors (see Table 80., page 148).
If the byte to be programmed is in a protected
Flash memory sector, the instruction sequence is
ignored.
IMPORTANT: It is mandatory that a chip-select
signal is active for the Flash sector where a programming
instruction sequence is targeted. Make
sure that the correct chip-select equation, FSx, or
CSBOOTx specified in PSDsoft Express matches
the address range that the 8032 firmware is accessing,
otherwise the instruction sequence will
not be recognized by the Flash array. If memory
paging is used, be sure that the 8032 firmware
sets the page register to the correct page number
before issuing an instruction sequence to the
Flash memory segment on a particular memory
page, otherwise the correct sector select signal
will not become active.
Once the 8032 issues a Flash memory program or
erase instruction sequence, it must check the status
bits for completion. The embedded algorithms
that are invoked inside a Flash memory array provide
several ways to give status to the 8032. Status
may be checked using any of three methods:
Data Polling, Data Toggle, or Ready/Busy (pin
PC3).
Table 81. Flash Memory Status Bit Definition
Note: 1. X = Not guaranteed value, can be read either '1' or '0.'
2. DQ7-DQ0 represent the 8032 Data Bus Bits, D7-D0.
Functional Block FSx, or CSBOOTx DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Flash Memory Active (the desired
segment is selected)
Data
Polling
Toggle
Flag
Error
Flag X
Erase
Timeout
XXX151/231
uPSD33xx
Data Polling. Polling on the Data Polling Flag Bit
(DQ7) is a method of checking whether a program
or erase operation is in progress or has completed.
Figure 61 shows the Data Polling algorithm.
When the 8032 issues a program instruction sequence,
the embedded algorithm within the Flash
memory array begins. The 8032 then reads the location
of the byte to be programmed in Flash
memory to check status. The Data Polling Flag Bit
(DQ7) of this location becomes the compliment of
Bit D7 of the original data byte to be programmed.
The 8032 continues to poll this location, comparing
the Data Polling Flag Bit (DQ7) and monitoring
the Error Flag Bit (DQ5). When the Data Polling
Flag Bit (DQ7) matches Bit D7 of the original data,
then the embedded algorithm is complete. If the
Error Flag Bit (DQ5) is '1,' the 8032 should test the
Data Polling Flag Bit (DQ7) again since the Data
Polling Flag Bit (DQ7) may have changed simultaneously
with the Error Flag Bit (DQ5) (see Figure
61).
The Error Flag Bit (DQ5) is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the byte (indicating a bad
Flash cell) or if the 8032 attempted to program bit
to logic ’1’ when that bit was already programmed
to logic ’0’ (must erase to achieve logic ’1’).
It is suggested (as with all Flash memories) to read
the location again after the embedded programming
algorithm has completed, to compare the
byte that was written to the Flash memory with the
byte that was intended to be written.
When using the Data Polling method during an
erase operation, Figure 61 still applies. However,
the Data Polling Flag Bit (DQ7) is '0' until the erase
operation is complete. A ’1’ on the Error Flag Bit
(DQ5) indicates a time-out condition on the Erase
cycle, a ’0’ indicates no error. The 8032 can read
any location within the sector being erased to get
the Data Polling Flag Bit (DQ7) and the Error Flag
Bit (DQ5).
PSDsoft Express generates ANSI C code functions
for implementation of these Data Polling algorithms.
Figure 61. Data Polling Flowchart
READ DQ5 & DQ7
at VALID ADDRESS
START
READ DQ7
FAIL PASS
AI01369B
DQ7 = DATA
YES
NO
YES
NO
DQ5
= 1
DQ7 = DATA
YES
NOuPSD33xx
152/231
Data Toggle. Checking the Toggle Flag Bit
(DQ6) is another method of determining whether a
program or erase operation is in progress or has
completed. Figure 62 shows the Data Toggle algorithm.
When the 8032 issues a program instruction sequence,
the embedded algorithm within the Flash
memory array begins. The 8032 then reads the location
of the byte to be programmed in Flash
memory to check status. The Toggle Flag Bit
(DQ6) of this location toggles each time the 8032
reads this location until the embedded algorithm is
complete. The 8032 continues to read this location,
checking the Toggle Flag Bit (DQ6) and monitoring
the Error Flag Bit (DQ5). When the Toggle
Flag Bit (DQ6) stops toggling (two consecutive
reads yield the same value), then the embedded
algorithm is complete. If the Error Flag Bit (DQ5) is
'1,' the 8032 should test the Toggle Flag Bit (DQ6)
again, since the Toggle Flag Bit (DQ6) may have
changed simultaneously with the Error Flag Bit
(DQ5) (see Figure 62).
The Error Flag Bit (DQ5) is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the byte, or if the 8032 attempted
to program bit to logic ’1’ when that bit
was already programmed to logic ’0’ (must erase
to achieve logic ’1’).
It is suggested (as with all Flash memories) to read
the location again after the embedded programming
algorithm has completed, to compare the
byte that was written to Flash memory with the
byte that was intended to be written.
When using the Data Toggle method during an
erase operation, Figure 62 still applies. the Toggle
Flag Bit (DQ6) toggles until the erase operation is
complete. A ’1’ on the Error Flag Bit (DQ5) indicates
a time-out condition on the Erase cycle, a ’0’
indicates no error. The 8032 can read any location
within the sector being erased to get the Toggle
Flag Bit (DQ6) and the Error Flag Bit (DQ5).
PSDsoft Express generates ANSI C code functions
for implementation of these Data Toggling algorithms.
Figure 62. Data Toggle Flowchart
READ
DQ5 & DQ6
START
READ DQ6
FAIL PASS
AI01370B
DQ6 = TOGGLE
NO
NO
YES
YES
DQ5
= 1
NO
YES
DQ6 = TOGGLE153/231
uPSD33xx
Ready/Busy (PC3). This signal can be used to
output the Ready/Busy status of a program or
erase operation on either Flash memory. The output
on the Ready/Busy pin is a ’0’ (Busy) when either
Flash memory array is being written, or when
either Flash memory array is being erased. The
output is a ’1’ (Ready) when no program or erase
operation is in progress. To activate this function
on this pin, the user must select the “Ready/Busy”
selection in PSDsoft Express when configuring pin
PC3. This pin may be polled by the 8032 or used
as a 8032 interrupt to indicate when an erase or
program operation is complete (requires routing
the signal on PC board from PC3 back into a pin
on the MCU Module). This signal is also available
internally on the PSD Module as an input to both
PLDs (without routing a signal externally on PC
board) and it’s signal name is “rd_bsy”. The
Ready/Busy output can be probed during lab development
to check the timing of Flash memory
programming in the system at run-time.
Bypassed Unlock Sequence. The Bypass Unlock
mode allows the 8032 to program bytes in the
Flash memories faster than using the standard
Flash program instruction sequences because the
typical AAh, 55h unlock bus cycles are bypassed
for each byte that is programmed. Bypassing the
unlock sequence is typically used when the 8032
is intentionally programming a large number of
bytes (such as during IAP). After intentional programming
is complete, typically the Bypass mode
would be disabled, and full protection is back in
place to prevent unwanted WRITEs to Flash memory.
The Bypass Unlock mode is entered by first initiating
two Unlock bus cycles. This is followed by a
third WRITE operation containing the Bypass Unlock
command, 20h (as shown in Table
80., page 148). The Flash memory array that received
that sequence then enters the Bypass Unlock
mode. After this, a two bus cycle program
operation is all that is required to program a byte
in this mode. The first bus cycle in this shortened
program instruction sequence contains the Bypassed
Unlocked Program command, A0h, to any
valid address within the unlocked Flash array. The
second bus cycle contains the address and data of
the byte to be programmed. Programming status
is checked using toggle, polling, or Ready/Busy
just as before. Additional data bytes are programmed
the same way until this Bypass Unlock
mode is exited.
To exit Bypass Unlock mode, the system must issue
the Reset Bypass Unlock instruction sequence.
The first bus cycle of this instruction must
write 90h to any valid address within the unlocked
Flash Array; the second bus cycle must write 00h
to any valid address within the unlocked Flash Array.
After this sequence the Flash returns to Read
Array mode.
During Bypass Unlock Mode, only the Bypassed
Unlock Program instruction, or the Reset Bypass
Unlock instruction is valid, other instruction will be
ignored.
Erasing Flash Memory. Flash memory may be
erased sector-by-sector, or an entire Flash memory
array may be erased with one command (bulk).
Flash Bulk Erase. The Flash Bulk Erase instruction
sequence uses six WRITE operations followed
by a READ operation of the status register,
as described in Table 80., page 148. If any byte of
the Bulk Erase instruction sequence is wrong, the
Bulk Erase instruction sequence aborts and the
device is reset to the Read Array mode. The address
provided by the 8032 during the Flash Bulk
Erase command sequence may select any one of
the eight Flash memory sector select signals FSx
or one of the four signals CSBOOTx. An erase of
the entire Flash memory array will occur in a particular
array even though a command was sent to
just one of the individual Flash memory sectors
within that array.
During a Bulk Erase, the memory status may be
checked by reading the Error Flag Bit (DQ5), the
Toggle Flag Bit (DQ6), and the Data Polling Flag
Bit (DQ7). The Error Flag Bit (DQ5) returns a ’1’ if
there has been an erase failure. Details of acquiring
the status of the Bulk Erase operation are detailed
in the section entitled “Programming Flash
Memory., page 150.
During a Bulk Erase operation, the Flash memory
does not accept any other Flash instruction sequences.uPSD33xx
154/231
Flash Sector Erase. The Sector Erase instruction
sequence uses six WRITE operations, as described
in Table 80., page 148. Additional Flash
Sector Erase commands to other sectors within
the same Flash array may be issued by the 8032
if the additional commands are sent within a limited
amount of time.
The Erase Time-out Flag Bit (DQ3) reflects the
time-out period allowed between two consecutive
sector erase instruction sequence bytes. If multiple
sector erase commands are desired, the additional
sector erase commands (30h) must be sent
by the 8032 to another sector within 80µs after the
previous sector erase command. DQ3 is 0 before
this time period has expired, indicating it is OK to
issue additional sector erase commands. DQ3 will
go to logic ’1’ if the time has been longer than 80µs
since the previous sector erase command (time
has expired), indicating that is not OK to send another
sector erase command. In this case, the
8032 must start a new sector erase instruction sequence
(unlock and command), beginning again
after the current sector erase operation has completed.
During a Sector Erase operation, the memory status
may be checked by reading the Error Flag Bit
(DQ5), the Toggle Flag Bit (DQ6), and the Data
Polling Flag Bit (DQ7), as detailed in Reading the
Erase/Program Status Bits, page 149.
During a Sector Erase operation, a Flash memory
accepts only Reset Flash and Suspend Sector
Erase instruction sequences. Erasure of one
Flash memory sector may be suspended, in order
to read data from another Flash memory sector,
and then resumed.
The address provided with the initial Flash Sector
Erase command sequence (Table 80., page 148)
must select the first desired sector (FSx or CSBOOTx)
to erase. Subsequent sector erase commands
that are appended within the time-out
period must be addressed to other desired segments
within the same Flash memory array.
Suspend Sector Erase. When a Sector Erase
operation is in progress, the Suspend Sector
Erase instruction sequence can be used to suspend
the operation by writing B0h to any valid address
within the Flash array that currently is
undergoing an erase operation. This allows reading
of data from a different Flash memory sector
within the same array after the Erase operation
has been suspended. Suspend Sector Erase is
accepted only during an Erase operation.
There is up to 15µs delay after the Suspend Sector
Erase command is accepted and the array goes to
Read Array mode. The 8032 will monitor the Toggle
Flag Bit (DQ6) to determine when the erase
operation has halted and Read Array mode is active.
If a Suspend Sector Erase instruction sequence
was executed, the following rules apply:
– Attempting to read from a Flash memory
sector that was being erased outputs invalid
data.
– Reading from a Flash memory sector that was
not being erased is valid.
– The Flash memory cannot be programmed,
and only responds to Resume Sector Erase
and Reset Flash instruction sequences.
– If a Reset Flash instruction sequence is
received, data in the Flash memory sector that
was being erased is invalid.
Resume Sector Erase. If a Suspend Sector
Erase instruction sequence was previously executed,
the erase cycle may be resumed with this
instruction sequence. The Resume Sector Erase
instruction sequence consists of writing the command
30h to any valid address within the Flash array
that was suspended as shown in Table
80., page 148.
Reset Flash. The Reset Flash instruction sequence
resets the embedded algorithm running on
the state machine in the targeted Flash memory
(Main or Secondary) and the memory goes into
Read Array mode. The Reset Flash instruction
consists of one bus WRITE cycle as shown in Table
80., page 148, and it must be executed after
any error condition that has occurred during a
Flash memory Program or Erase operation.
It may take the Flash memory up to 25µs to complete
the Reset cycle. The Reset Flash instruction
sequence is ignored when it is issued during a
Program or Bulk Erase operation. The Reset Flash
instruction sequence aborts any on-going Sector
Erase operation and returns the Flash memory to
Read Array mode within 25µs.
Reset Signal Applied to Flash Memory. Whenever
the PSD Module receives a reset signal from
the MCU Module, any operation that is occurring in
either Flash memory array will be aborted and the
array(s) will go to Read Array mode. It may take up
to 25µs to abort an operation and achieve Read
Array mode.
A reset from the MCU Module will result from any
of these events: an active signal on the uPSD33xx
RESET_IN input pin, a watchdog timer time-out,
detection of low VCC, or a JTAG debug channel reset
event.155/231
uPSD33xx
Flash Memory Sector Protection. Each Flash
memory sector can be separately protected
against program and erase operations. This mode
can be activated (or deactivated) by selecting this
feature in PSDsoft Express and then programming
through the JTAG Port. Sector protection can be
selected for individual sectors, and the 8032 cannot
override the protection during run-time. The
8032 can read, but not change, sector protection.
Any attempt to program or erase a protected Flash
memory sector is ignored. The 8032 may read the
contents of a Flash sector even when a sector is
protected.
Sector protection status is not read using Flash
memory instruction sequences, but instead this
status is read by the 8032 reading two registers
within csiop address space shown in Table 82 and
Table 83.
Flash Memory Protection During Power-Up.
Flash memory WRITE operations are automatically
prevented while VDD is ramping up until it rises
above VLKO voltage threshold at which time Flash
memory WRITE operations are allowed.
PSD Module Security Bit. A programmable security
bit in the PSD Module protects its contents
from unauthorized viewing and copying. The security
bit is set using PSDsoft Express and programmed
into the PSD Module with JTAG. When
set, the security bit will block access of JTAG programming
equipment from reading or modifying
the PSD Module Flash memory and PLD configuration.
The security bit also blocks JTAG access to
the MCU Module for debugging. The only way to
defeat the security bit is to erase the entire PSD
Module using JTAG (erase is the only JTAG operation
allowed while security bit is set), after which
the device is blank and may be used again. The
8032 MCU will always have access to Flash mem-uPSD33xx
156/231
PLDs. The PSD Module contains two PLDs: the
Decode PLD (DPLD), and the General PLD
(GPLD), as shown in Figure 63., page 157. Both
PLDs are fed by a common PLD input signal bus,
and additionally, the GPLD is connected to the
8032 data bus.
PLD logic is specified using PSDsoft Express and
programmed into the PSD Module using the JTAG
ISP channel. PLD logic is non-volatile and available
at power-up. PLDs may not be programmed
by the 8032. The PLDs have selectable levels of
performance and power consumption.
The DPLD performs address decoding, and generates
select signals for internal and external components,
such as memory, registers, and I/O ports.
The DPLD can generate External Chip-Select
(ECS1-ECS2) signals on Port D.
The GPLD can be used for logic functions, such as
loadable counters and shift registers, state machines,
encoding and decoding logic. These logic
functions can be constructed from a combination
of 16 Output Macrocells (OMC), 20 Input Macrocells
(IMC), and the AND-OR Array.
Routing of the 16 OMCs outputs can be divided
between pins on three Ports A, B, or C by the OMC
Allocator as shown in Figure 67., page 163. Eight
of the 16 OMCs that can be routed to pins on Port
A or Port B and are named MCELLAB0-
MCELLAB7. The other eight OMCs to be routed to
pins on Port B or Port C and are named
MCELLBC0-MCELLBC7. This routing depends on
the pin number assignments that are specified in
PSDsoft Express for “PLD Outputs” in the Pin Definition
section. OMC outputs can also be routed internally
(not to pins) used as buried nodes to
create shifters, counters, etc.
The AND-OR Array is used to form product terms.
These product terms are configured from the logic
definitions entered in PSDsoft Express. A PLD Input
Bus consisting of 69 signals is connected to
both PLDs. Input signals are shown in Table 84,
both the true and compliment versions of each of
these signals are available at inputs to each PLD.
Note: The 8032 data bus, D0 - D7, does not route
directly to PLD inputs. Instead, the 8032 data bus
has indirect access to the GPLD (not the DPLD)
when the 8032 reads and writes the OMC and IMC
registers within csiop address space.
Turbo Bit and PLDs. The PLDs can minimize
power consumption by going to standby after ALL
the PLD inputs remain unchanged for an extended
time (about 70ns). When the Turbo Bit is set to logic
one (Bit 3 of the csiop PMMR0 Register), Turbo
mode is turned off and then this automatic standby
mode is achieved. Turning off Turbo mode increases
propagation delays while reducing power
consumption. The default state of the Turbo Bit is
logic zero, meaning Turbo mode is on. Additionally,
four bits are available in the csiop PMMR0 and
PMMR2 Registers to block the 8032 bus control
signals (RD, WR, PSEN, ALE) from entering the
PLDs. This reduces power consumption and can
be used only when these 8032 control signals are
not used in PLD logic equations. See Power
Management, page 187.
Table 84. DPLD and GPLD Inputs
Input Source Input Name
Number
of
Signals
8032 Address Bus A0-A15 16
8032 Bus Control Signals PSEN, RD, WR,
ALE 4
Reset from MCU Module RESET 1
Power-Down from AutoPower
Down Counter PDN 1
PortA Input Macrocells
(80-pin devices only) PA0-PA7 8
PortB Input Macrocells PB0-PB7 8
PortC Input Macrocells PC2, PC3, PC4,
PC7 4
Port D Inputs
(52-pin devices have only
PD1)
PD1, PD2 2
Page Register PGR0-PGR7 8
Macrocell OMC bank AB
Feedback
MCELLAB
FB0-7 8
Macrocell OMC bank BC
Feedback
MCELLBC
FB0-7 8
Flash memory Status Bit Ready/Busy 1157/231
uPSD33xx
Figure 63. DPLD and GPLD
GPLD
20 INPUT MACROCELLS
PLD INPUT BUS
PIN FEEDBACK, PORTS A, B, C
NODE FEEDBACK
DPLD
Main Flash Memory Selects (FSx)
AAAAAAAA
BBBBBBBB
C
C
C
C
69 INPUTS
OMC
ALLOCATOR
4 or 8
2 or 4
Secondary Flash Memory Selects (CSBOOTx)
1
SRAM Select (RS0)
1
I/O PORT Select (CSIOP)
2
Periperal I/O Mode Range Selects (PSELx)
1 or 2 External Device Chip-Selects (ECSx)
8
8
4
8
8
4
AND-OR
ARRAY
AND-OR
ARRAY
8032 ADDRESS
8032 BUS CONTROL
PAGE REGISTER
OTHER SIGNALS
16 OUTPUT MACROCELLS
PORT A
(80-pin only) PORT C PORT B 8032 DATA BUS
PIN FEEDBACK, PORT D
PORT D
8032 DATA BUS
8 PLD OUT
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
B
C B
C B
C B
C B
C B
C B
C B
C 8 PLD OUT
69 INPUTS
AI06600AuPSD33xx
158/231
Decode PLD (DPLD). The DPLD (Figure
64., page 159) generates the following memory
decode signals:
■ Eight Main Flash memory sector select signals
(FS0-FS7) with three product terms each
■ Four Secondary Flash memory sector select
signals (CSBOOT0-CSBOOT3) with three
product terms each
■ One SRAM select signal (RS0) with two
product terms
■ One select signal for the base address of 256
PSD Module device control and status
registers (CSIOP) with one product term
■ Two external chip-select output signals for
Port D pins, each with one product term (52-
pin devices only have one pin on Port D)
■ Two chip-select signals (PSEL0, PSEL1) used
to enable the 8032 data bus repeater function
(Peripheral I/O mode) for Port A on 80-pin
devices. Each has one product term.
A product term indicates the logical OR of two or
more inputs. For example, three product terms in
a DPLD output means the final output signal is capable
of representing the logical OR of three different
input signals, each input signal representing
the logical AND of a combination of the 69 PLD inputs.
Using the signal FS0 for example, the user may
create a 3-product term chip select signal that is
logic true when any one of three different address
ranges are true... FS0 = address range 1 OR address
range 2 OR address range 3.
The phrase “one product term” is a bit misleading,
but commonly used in this context. One product
term is the logical AND of two or more inputs, with
no OR logic involved at all, such as the CSIOP signal
in Figure 64., page 159.159/231
uPSD33xx
Figure 64. DPLD Logic Array
FS0
FS1
FS7
FS6
FS5
FS4
FS3
FS2
MAIN
FLASH
MEMORY
SECTOR
SELECTS
CSBOOT0
CSBOOT3
CSBOOT2
CSBOOT1 SECONDARY
FLASH
MEMORY
SECTOR
SELECTS
RS0 SRAM
SELECT
CSIOP I/O & CONTROL
REGISTERS
SELECT
ECS0
ECS1
EXTERNAL
CHIPSELECTS
(PORT D)
PSEL0
PSEL1
PERIPHERAL
I/O MODE
RANGE
SELECTS
8032 ADDRESS (A0 - A15) 16
4
1
POWER-DOWN INDICATOR (PDN) 1
PIN INPUT PORTS A, B, C (IMCs) 20
PIN INPUT PORT D 2
OMC FEEDBACK (MCELLAB.FB0-7) 8
PAGE REGISTER (PGR0 - PGR7) 8
8
1
OMC FEEDBACK (MCELLBC.FB0-7)
PLD INPUT BUS 3
3
3
3
3
3
3
3
3
3
3
3
2
1
1
1
1
1
NUMBER OF
PRODUCT TERMS
AI06601A
PSM MODULE RESET (RST)
FLASH MEM PROG STATUS (RDYBSY)
8032 CNTL (RD, WR, PSEN, ALE)uPSD33xx
160/231
General PLD (GPLD). The GPLD is used to create
general system logic. Figure 63., page 157
shows the architecture of the entire GPLD, and
Figure 65., page 161 shows the relationship between
one OMC, one IMC, and one I/O port pin,
which is representative of pins on Ports A, B, and
C. It is important to understand how these elements
work together. A more detailed description
will follow for the three major blocks (OMC, IMC, I/
O Port) shown in Figure 65. Figure 65 also shows
which csiop registers to access for various PLD
and I/O functions.
The GPLD contains:
■ 16 Output Macrocells (OMC)
■ 20 Input Macrocells (IMC)
■ OMC Allocator
■ Product Term Allocator inside each OMC
■ AND-OR Array capable of generating up to
137 product terms
■ Three I/O Ports, A, B, and C161/231
uPSD33xx
Figure 65. GPLD: One OMC, One IMC, and One I/O Port (typical pin, Port A, B, or C) OUTPUT MACROCELL (OMC) INPUT MACROCELL (IMC) FLIP-FLOP CLOCK GLOBAL CLOCK FLIP-FLOP CLEAR NODE FEEDBACK NATIVE PRODUCT TERMS PRODUCT TERM ALLOCATOR PRODUCT TERMS FROM OTHER OMCs I/O PORT LOGIC PERIPHERAL I/O MODE BIT OUTPUT ENABLE LATCHED 8032 ADDR BIT PSD MODULE PORT PIN 8032 DATA BIT 8032 DATA BIT OUTPUT ENABLE PIN FEEDBACK CLOCK or GATE SIGNAL
PLD INPUT BUS OMC OUT
ALE
TO OTHER
I/O PORT
LOGIC
OMC
ALLOCATOR
RESET
PSD MODULE RESET
FROM
OTHER
MACROCELL
ALLOCATOR
GLOBAL CLOCK
AND-OR ARRAY
CLOCK or GATE
RESET
FLIP-FLOP
AND
OTHER
LOGIC
BORROWED
PRODUCT TERMS
PIN
INPUT
LATCH
OR
PASS
INPUT
SIGNAL
8032
DATA BITS
8032
DATA BITS CSIOP REGISTERS
(DATA OUT,
DIRECTION
CONTROL,
DRIVE)
M
U
X
OMC OUTPUT
FEED
BACK
DIRECTION
CONTROL
DATA OUT
CSIOP
REGISTERS
(DATA IN,
DATA OUT,
DIRECTION,
CONTROL,
DRIVE,
ENABLE)
CSIOP
REGISTERS
(MCELLAB,
MCELLBC)
READ
OMC
LOAD
OMC
CSIOP REGISTERS
(IMCA, IMCB, IMCC)
READ IMC
FLIP-FLOP PRESET
PIN
INPUT DATA IN
69 INPUTS
8032 RD
8032 RD
8032 RD
8032 WR
8032 WR
8032 ADDRESS, DATA, CONTROL BUS
AI06602AuPSD33xx
162/231
Output Macrocell. The GPLD has 16 OMCs. Architecture
of one individual OMC is shown in Figure
66. OMCs can be used for internal node
feedback (buried registers to build shift registers,
etc.), or their outputs may be routed to external
port pins. The user can choose any mixture of
OMCs used for buried functions and OMCs used
to drive port pins.
Referring to Figure 66, for each OMC there are native
product terms available from the AND-OR Array
to form logic, and also borrowed product terms
are available (if unused) from other OMCs. The
polarity of the final product term output is controlled
by the XOR gate. Each OMC can implement
sequential logic using the flip-flop element,
or combinatorial logic when bypassing the flip-flop
as selected by the output multiplexer. An OMC
output can drive a port pin through the OMC Allocator,
it can also drive the 8032 data bus, and also
it can drive a feedback path to the AND-OR Array
inputs, all at the same time.
The flip-flop in each OMC can be synthesized as a
D, T, JK, or SR type in PSDsoft Express. OMC flipflops
are specified using PSDsoft Express in the
“User Defined Nodes” section of the Design Assistant.
Each flip-flop’s clock, preset, and clear inputs
may be driven individually from a product term of
the AND-OR Array, defined by equations in PSDsoft
Express for signals *. c, *.pr, and *.re respectively.
The preset and clear inputs on the flip-flops
are level activated, active-high logic signals. The
clock inputs on the flip-flops are rising-edge logic
signals.
Optionally, the signal CLKIN (pin PD1) can be
used for a common clock source to all OMC flipflops.
Each flip-flop is clocked on the rising edge.
A common clock is specified in PSDsoft Express
by assigning the function “Common Clock Input”
for pin PD1 in the Pin Definition section, and then
choosing the signal CLKIN when specifying the
clock input (*.c) for individual flip-flops in the “User
Defined Nodes” section.
Figure 66. Detail of a Single OMC
D
CLR
PRE
Q
MUX
MUX
M
U
X
M
U
X
PSDsoft
PSDsoft
OUTPUT MACROCELL (OMC)
PT PRESET (.PR) FROM AND-OR ARRAY
BORROWED
PTs
PT CLEAR (.RE)
NODE FEEDBACK (.FB)
POLARITY
SELECT,
PSDsoft
PT ALLOCATOR,
DRAWS FROM LOCAL
AND GLOBAL UNUSED
PRODUCT TERMS.
PSDsoft DICTATES.
LENDED
PTs
DATA BIT FROM 8032
DATA BIT TO 8032
INDICATES MCU WRITE
TO PARTICULAR CSIO
OMC REGISTER
MCU OVERRIDES
PT PRESET AND
CLR DURING
MCU WRITE
MCU READ OF
PARTICULAR CSIOP
OMC REGISTER
OMC
OUTPUT
FROM AND-OR ARRAY
TO PLD INPUT BUS
FROM AND-OR ARRAY NATIVE PTs
ALLOCATED PTs
PT CLOCK (.C) FROM AND-OR ARRAY
GLOBAL CLOCK (CLKIN) FROM PLD INPUT BUS
8032 ADDRESS, DATA, CONTROL BUS
OMC
ALLOCATOR
O
U
T
PRODUCT TERMS
FROM OTHER
OMCs
AI06617A163/231
uPSD33xx
OMC Allocator. Outputs of the 16 OMCs can be
routed to a combination of pins on Port A (80-pin
devices only), Port B, or Port C as shown in Figure
67. OMCs are routed to port pins automatically after
specifying pin numbers in PSDsoft Express.
Routing can occur on a bit-by-bit basis, spitting
OMC assignment between the ports. However,
one OMC can be routed to one only port pin, not
both ports.
Product Term Allocator. Each OMC has a Product
Term Allocator as shown in Figure
66., page 162. PSDsoft Express uses PT Allocators
to give and take product terms to and from
other OMCs to fit a logic design into the available
silicon resources. This happens automatically in
PSDsoft Express, but understanding how PT allocation
works will help the user if the logic design
does not “fit,” in which case the user may try selecting
a different pin or different OMC for the logic
where more product terms may be available. The
following list summarizes how product terms are
allocated to each OMC, as shown in Table
85., page 164.
– MCELLAB0-MCELLAB7 each have three
native product terms and may borrow up to six
more
– MCELLBC0-MCELLBC3 each have four
native product terms and may borrow up to
five more
– MCELLBC4-MCELLBC7 each have four
native product terms and may borrow up to six
more.
Native product terms come from the AND-OR Array.
Each OMC may borrow product terms only
from certain other OMCs, if they are not in use.
Product term allocation does not add any propagation
delay to the logic. The fitter report generated
by PSDsoft Express will show any PT allocation
that has occurred.
If an equation requires more product terms than
are available to it through PT allocation, then “external”
product terms are required, which consumes
other OMCs. This is called product term
expansion and also happens automatically in PSDsoft
Express as needed. PT expansion causes
additional propagation delay because an additional
OMC is consumed by the expansion process
and it’s output is rerouted (or fed back) into the
AND-OR array. The user can examine the fitter report
generated by PSDsoft Express to see resulting
PT allocation and PT expansion (expansion
will have signal names, such as ‘*.fb_0’ or ‘*.fb_1’).
PSDsoft Express will always try to fit the logic design
first by using PT allocation, and if that is not
sufficient then PSDsoft Express will use PT expansion.
Product term expansion may occur in the DPLD
for complex chip select equations for Flash memory
sectors and for SRAM, but this is a rare occurence.
If PSDsoft Express does use PT
expansion in the DPLD, it results in an approximate
15ns additional propagation delay for that
chip select signal, which gives 15ns less time for
the memory to respond. Be aware of this and consider
adding a wait state to the 8032 bus access
(using the SFR named, BUSCON), or lower the
8032 clock frequency to avoid problems with
memory access time.
Figure 67. OMC Allocator
PORT B PINS PORT C PINS
PORT A PINS
(80-pin pkg only)
OMC Bank AB (MCELLAB0-7) OMC Bank BC (MCELLBC0-7)
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 4 3 2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
** **
* = Used for JTAG,
Pin Not Available
to GPLD
AI09177uPSD33xx
164/231
Table 85. OMC Port and Data Bit Assignments
Note: 1. MCELLAB0-MCELLAB7 can be output to Port A pins only on 80-pin devices. Port A is not available on 52-pin devices
2. Port pins PC0, PC1, PC5, and PC6 are dedicated JTAG pins and are not available as outputs for MCELLBC 0, 1, 5, or 6
OMC Port
Assignment(1,2)
Native Product Terms
from AND-OR Array
Maximum Borrowed
Product Terms
Data Bit on 8032 Data
Bus for Loading or
Reading OMC
MCELLAB0 Port A0 or B0 3 6 D0
MCELLAB1 Port A1 or B1 3 6 D1
MCELLAB2 Port A2 or B2 3 6 D2
MCELLAB3 Port A3 or B3 3 6 D3
MCELLAB4 Port A4 or B4 3 6 D4
MCELLAB5 Port A5 or B5 3 6 D5
MCELLAB6 Port A6 or B6 3 6 D6
MCELLAB7 Port A7 or B7 3 6 D7
MCELLBC0 Port B0 4 5 D0
MCELLBC1 Port B1 4 5 D1
MCELLBC2 Port B or C2 4 5 D2
MCELLBC3 Port B3 or C3 4 5 D3
MCELLBC4 Port B4 or C4 4 6 D4
MCELLBC5 Port B5 4 6 D5
MCELLBC6 Port B6 4 6 D6
MCELLBC7 Port B7 orC7 4 6 D7165/231
uPSD33xx
Loading and Reading OMCs. Each of the two
OMC groups (eight OMCs each) occupies a byte
in csiop space, named MCELLAB and MCELLBC
(see Table 86 and Table 87). When the 8032
writes or reads these two OMC registers in csiop it
is accessing each of the OMCs through it’s 8-bit
data bus, with the bit assignment shown in Table
85., page 164. Sometimes it is important to know
the bit assignment when the user builds GPLD logic
that is accessed by the 8032. For example, the
user may create a 4-bit counter that must be loaded
and read by the 8032, so the user must know
which nibble in the corresponding csiop OMC register
the firmware must access. The fitter report
generated by PSDsoft Express will indicate how it
assigned the OMCs and data bus bits to the logic.
The user can optionally force PSDsoft Express to
assign logic to specific OMCs and data bus bits if
desired by using the ‘PROPERTY’ statement in
PSDsoft Express. Please see the PSDsoft Express
User’s Manual for more information on OMC
assignments.
Loading the OMC flip-flops with data from the
8032 takes priority over the PLD logic functions.
As such, the preset, clear, and clock inputs to the
flip-flop can be asynchronously overridden when
the 8032 writes to the csiop registers to load the individual
OMCs.
Table 86. Output Macrocell MCELLAB (address = csiop + offset 20h)
Note: All bits clear to logic ’0’ at power-on reset, but do not clear after warm reset conditions (non-power-on reset)
Table 87. Output Macrocell MCELLBC (address = csiop + offset 21h)
Note: All bits clear to logic ’0’ at power-on reset, but do not clear after warm reset conditions (non-power-on reset)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MCELLAB7 MCELLAB6 MCELLAB5 MCELLAB4 MCELLAB3 MCELLAB2 MCELLAB1 MCELLAB0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MCELLBC7 MCELLBC6 MCELLBC5 MCELLBC4 MCELLBC3 MCELLBC2 MCELLBC1 MCELLBC0uPSD33xx
166/231
OMC Mask Registers. There is one OMC Mask
Register for each of the two groups of eight OMCs
shown in Table 88 and Table 89. The OMC mask
registers are used to block loading of data to individual
OMCs. The default value for the mask registers
is 00h, which allows loading of all OMCs.
When a given bit in a mask register is set to a '1,'
the 8032 is blocked from writing to the associated
OMC flip-flop. For example, suppose that only four
of eight OMCs (MCELLAB0-3) are being used for
a state machine. The user may not want the 8032
write to all the OMCs in MCELLAB because it
would overwrite the state machine registers.
Therefore, the user would want to load the mask
register for MCELLAB with the value 0Fh before
writing OMCs.
Table 88. Output Macrocell MCELLAB Mask Register (address = csiop + offset 22h)
Note: 1. Default is 00h after any reset condition
2. 1 = block writing to individual macrocell, 0 = allow writing to individual macrocell
Table 89. Output Macrocell MCELLBC Mask Register (address = csiop + offset 23h)
Note: 1. Default is 00h after any reset condition
2. 1 = block writing to individual macrocell, 0 = allow writing to individual macrocell
Input Macrocells. The GPLD has 20 IMCs, one
for each pin on Port A (80-pin device only), one for
each pin on Port B, and for the four pins on Port C
that are not JTAG pins. The architecture of one individual
IMC is shown in Figure 68., page 167.
IMCs are individually configurable, and they can
strobe a signal coming in from a port pin as a latch
(gated), or as a register (clocked), or the IMC can
pass the signal without strobing, all prior to driving
the signal onto the PLD input bus. Strobing is useful
for sampling and debouncing inputs (keypad inputs,
etc.) before entering the PLD AND-OR
arrays. The outputs of IMCs can be read by the
8032 asynchronously when the 8032 reads the
csiop registers shown in Table 90, Table 91, and
Table 92., page 167. It is possible to read a PSD
Module port pin using one of two different methods,
one method is by reading IMCs as described
here, the other method is using MCU I/O mode described
in a later section.
The optional IMC clocking or gating signal used to
strobe pin inputs is driven by a product term from
the AND-OR array. There is one clocking or gating
product term available for each group of four
IMCs. Port inputs 0-3 are controlled by one product
term and 4-7 by another. To specify in PSDsoft
Express the method in which a signal will be
strobed as it enters an IMC for a given input pin on
Port A, B, or C, just specify “PT Clocked Register”
to use a rising edge to clock the incoming signal,
or specify “PT Clock Latch” to use an active high
gate signal to latch the incoming signal. Then define
an equation for the IMC clock (.ld) or the IMC
gate (.le) signal in the “I/O Equations” section.
If the user would like to latch an incoming signal
using the gate signal ALE from the 8032, then in
PSDsoft Express, for a given input pin on Port A,
B, or C, specify “Latched Address” as the pin function.
If it is desired to pass an incoming signal through
an IMC directly to the AND-OR array inputs without
clocking or gating (this is most common), in
PSDsoft Express simply specify “Logic or Address”
for the input pin function on Port A, B, or C.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mask
MCELLAB7
Mask
MCELLAB6
Mask
MCELLAB5
Mask
MCELLAB4
Mask
MCELLAB3
Mask
MCELLAB2
Mask
MCELLAB1
Mask
MCELLAB0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mask
MCELLBC7
Mask
MCELLBC6
Mask
MCELLBC5
Mask
MCELLBC4
Mask
MCELLBC3
Mask
MCELLBC2
Mask
MCELLBC1
Mask
MCELLBC0167/231
uPSD33xx
Figure 68. Detail of a Single IMC
Table 90. Input Macrocell Port A(1) (address = csiop + offset 0Ah)
Note: 1. Port A not available on 52-pin uPSD33xx devices
2. 1 = current state of IMC is logic '1,' 0 = current state is logic ’0’
Table 91. Input Macrocell Port B (address = csiop + offset 0Bh)
Note: 1 = current state of IMC is logic '1,' 0 = current state is logic ’0’
Table 92. Input Macrocell Port C (address = csiop + offset 18h)
Note: 1. X = Not guaranteed value, can be read either '1' or '0.' These are JTAG pins.
2. 1 = current state of IMC is logic '1,' 0 = current state is logic ’0’
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IMC PA7 IMC PA6 IMC PA5 IMC PA4 IMC PA3 IMC PA2 IMC PA1 IMC PA0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IMC PB7 IMC PB6 IMC PB5 IMC PB4 IMC PB3 IMC PB2 IMC PB1 IMC PB0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IMC PC7 X X IMC PC4 IMC PC3 IMC PC2 X X
INPUT MACROCELL (IMC)
Q D
G
Q D
M
U
X
M
U
X
PSDsoft
8032 DATA BIT
8032 READ OF PARTICULAR CSIOP IMC REGISTER
PT CLOCK OR GATE (.LD OR .LE)
PIN INPUT
LATCHED INPUT
GATED INPUT (.LD)
(.LE)
ALE
PSDsoft
ALE
8032 ADDR, DATA, CNTL BUS
FROM I/O PORT
LOGIC
INPUT SIGNAL
FROM PIN ON
PORT A, B, or C
FROM AND-OR ARRAY
TO PLD INPUT BUS
THIS SIGAL IS GANGED TO 3 OTHER
IMCs, GROUPING IMC 0 - 3 or IMC 4 - 7. AI06603AuPSD33xx
168/231
I/O Ports. There are four programmable I/O ports
on the PSD Module: Port A (80-pin device only),
Port B, Port C, and Port D. Ports A and B are eight
bits each, Port C is four bits, and Port D is two bits
for 80-pin devices or 1-bit for 52-pin devices. Each
port pin is individually configurable, thus allowing
multiple functions per port. The ports are configured
using PSDsoft Express then programming
with JTAG, and also by the 8032 writing to csiop
registers at run-time.
Topics discussed in this section are:
■ General Port architecture
■ Port Operating Modes
■ Individual Port Structure
General Port Architecture. The general architecture
for a single I/O Port pin is shown in Figure
69., page 169. Port structures for Ports A, B, C,
and D differ slightly and are shown in Figure
74., page 181 though Figure 77., page 186.
Figure 69., page 169 shows four csiop registers
whose outputs are determined by the value that
the 8032 writes to csiop Direction, Drive, Control,
and Data Out. The I/O Port logic contains an output
mux whose mux select signal is determined by
PSDsoft Express and the csiop Control register
bits at run-time. Inputs to this output mux include
the following:
1. Data from the csiop Data Out register for MCU
I/O output mode (All ports)
2. Latched de-multiplexed 8032 Address for
Address Output mode (Ports A and B only)
3. Peripheral I/O mode data bit (Port A only)
4. GPLD OMC output (Ports A, B, and C).
The Port Data Buffer (PDB) provides feedback to
the 8032 and allows only one source at a time to
be read when the 8032 reads various csiop registers.
There is one PDB for each port pin enabling
the 8032 to read the following on a pin-by-pin basis:
1. MCU I/O signal direction setting (csiop
Direction reg)
2. Pin drive type setting (csiop Drive Select reg)
3. Latched Addr Out mode setting (csiop Control
reg)
4. MCU I/O pin output setting (csiop Data Out
reg)
5. Output Enable of pin driver (csiop Enable Out
reg)
6. MCU I/O pin input (csiop Data In reg)
A port pin’s output enable signal is controlled by a
two input OR gate whose inputs come from: a
product term of the AND-OR array; the output of
the csiop Direction Register. If an output enable
from the AND-OR Array is not defined, and the
port pin is not defined as an OMC output, and if
Peripheral I/O mode is not used, then the csiop Direction
Register has sole control of the OE signal.
As shown in Figure 69., page 169, a physical port
pin is connected to the I/O Port logic and is also
separately routed to an IMC, allowing the 8032 to
read a port pin by two different methods (MCU I/O
input mode or read the IMC).
Port Operating Modes. I/O Port logic has several
modes of operation. Table 88., page 166 summarizes
which modes are available on each port.
Each of the port operating modes are described in
following sections. Some operating modes can be
defined using PSDsoft Express, and some by the
8032 writing to the csiop registers at run-time, and
some require both. For example, PLD I/O, Latched
Address Out, and Peripheral I/O modes must be
defined in PSDsoft Express and programmed into
the device using JTAG, but an additional step
must happen at run-time to activate Latched Address
Out mode and Peripheral I/O mode, but not
needed for PLD I/O. In another example, MCU I/O
mode is controlled completely by the 8032 at runtime
and only a simple pin name declaration is
needed in PSDsoft Express for documentation.
Table 89., page 166 summarizes what actions are
needed in PSDsoft Express and what actions are
required by the 8032 at run-time to achieve the
various port functions.169/231
uPSD33xx
Figure 69. Detail of a Single I/O Port (typical of Ports A, B, C)
I/O PORT
LOGIC
O
U
T
P
U
T
M
U
X P
D
B
M
U
X
DIRECTION
DRIVE SELECT
CONTROL
DATA OUT (MCUI/O)
ENABLE OUT
DATA IN (MCUI/O)
D BIT, PERIPH I/O MODE, Port A
PT OUTPUT ENABLE (.OE)
LATCHED ADDR BIT, PORT A or B
OE
MUX
8032
DATA
BIT
OUTPUT
DRIVER
TYPICAL
PIN
PORT A, B, C
PSD MODULE RESET
ONE of 6
CSIOP
REGISTERS
OUTPUT
SELECT
PERIPHERAL I/O
MODE SETS
DIRECTION
(PORT A ONLY)
8032 ADDRESS, DATA, CONTROL BUS
1
2
3
1 4
2
3
4
5
6
FROM OMC OUTPUT
TO IMC
FROM PLD INPUT BUS
FROM AND-OR ARRAY
FROM OMC
ALLOCATOR
D
CLR
DIRECTION
DRIVE
CONTROL
(MCUI/O)
DATA OUT
RESET
PSDsoft
PSELx
PERIPH I/O
DATA BIT
CSIOP
REGISTERS
Q
Q
Q
Q
8032 DRIVE TYPE
DATA
BITS
INPUT
BUFFER
OUTPUT ENABLE
WR RD PIO EN
8032
WR
8032 RD
AI07873AuPSD33xx
170/231
Table 93. Port Operating Modes
Note: 1. MCELLBC outputs available only on pins PC2, PC3, PC4, and PC7.
2. JTAG pins (PC0/TMS, PC1/TCK, PC5/TDI, PC6/TDO) are dedicated to JTAG pin functions (cannot be used for general I/O).
Port Operating Mode Port A (80-pin only) Port B Port C Port D Find it
MCU I/O Yes Yes Yes Yes
MCU I/O
Mode., p
age 172
PLD I/O
OMC MCELLAB Outputs
OMC MCELLBC Outputs
External Chip-Select Outputs
PLD Inputs
Yes
No
No
Yes
Yes
Yes
No
Yes
No
Yes(1)
No
Yes
No
No
Yes
Yes
PLD I/O
Mode., p
age 174
Latched Address Output Yes Yes No No
Latched
Address
Output
Mode, pa
ge 177
Peripheral I/O Mode Yes No No No
Peripher
al I/O
Mode, pa
ge 178
JTAG ISP No No Yes(2) No
JTAG
ISP
Mode., p
age 179171/231
uPSD33xx
Table 94. Port Configuration Setting Requirements
Port
Operating
Mode
Required Action in
PSDsoft Express to
Configure each Pin
Value that 8032
writes to csiop
Control Register at
run-time
Value that 8032
writes to csiop
Direction Register
at run-time
Value that 8032
writes to Bit 7
(PIO_EN) of csiop VM
Register at run-time
MCU I/O
Choose the MCU I/O
function and declare the
pin name
Logic '0' (default)
Logic 1 = Out of
uPSD
Logic 0 = Into uPSD
N/A
PLD I/O
Choose the PLD function
type, declare pin name,
and specify logic
equation(s)
N/A
Direction register
has no effect on a
pin if pin is driven
from OMC output
N/A
Latched Address
Output
Choose Latched Address
Out function, declare pin
name
Logic '1' Logic '1' Only N/A
Peripheral I/O
Choose Peripheral I/O
mode function and
specify address range in
DPLD for PSELx
N/A N/A PIO_EN Bit = Logic 1
(default is '0')
4-PIN JTAG ISP
No action required in
PSDsoft to get 4-pin
JTAG. By default TDO,
TDI, TCK, TMS are
dedicated JTAG
functions.
N/A N/A N/A
6-PIN JTAG ISP
(faster
programming)
Choose JTAG TSTAT
function for pin PC3 and
JTAG TERR function for
pin PC4.
N/A N/A N/AuPSD33xx
172/231
MCU I/O Mode. In MCU I/O mode, the 8032 on
the MCU Module expands its own I/O by using the
I/O Ports on the PSD Module. The 8032 can read
PSD Module I/O pins, set the direction of the I/O
pins, and change the output state of I/O pins by accessing
the Data In, Direction, and Data Out csiop
registers respectively at run-time.
To implement MCU I/O mode, each desired pin is
specified in PSDsoft Express as MCU I/O function
and given a pin name. Then 8032 firmware is written
to set the Direction bit for each corresponding
pin during initialization routines (0 = In, 1 = Out of
the chip), then the 8032 firmware simply reads the
corresponding Data In register to determine the
state of an I/O pin, or writes to a Data Out register
to set the state of a pin. The Direction of each pin
may be changed dynamically by the 8032 if desired.
A mixture of input and output pins within a
single port is allowed. Figure 69., page 169 shows
the Data In, Data Out, and Direction signal paths.
The Data In registers are defined in Table 95 to
Table 98. The Data Out registers are defined in
Table 99 to Table 102., page 173. The Direction
registers are defined in Table 103 to Table
106., page 173.
Table 95. MCU I/O Mode Port A Data In Register(1) (address = csiop + offset 00h)
Note: 1. Port A not available on 52-pin uPSD33xx devices
2. For each bit, 1 = current state of input pin is logic '1,' 0 = current state is logic ’0’
Table 96. MCU I/O Mode Port B Data In Register (address = csiop + offset 01h)
Note: For each bit, 1 = current state of input pin is logic '1,' 0 = current state is logic ’0’
Table 97. MCU I/O Mode Port C Data In Register (address = csiop + offset 10h)
Note: 1. X = Not guaranteed value, can be read either '1' or '0.'
2. For each bit, 1 = current state of input pin is logic '1,' 0 = current state is logic ’0’
Table 98. MCU I/O Mode Port D Data In Register (address = csiop + offset 11h)
Note: 1. X = Not guaranteed value, can be read either '1' or '0.'
2. For each bit, 1 = current state of input pin is logic '1,' 0 = current state is logic ’0’
3. Not available on 52-pin uPSD33xx devices
Table 99. MCU I/O Mode Port A Data Out Register(1) (address = csiop + offset 04h)
Note: 1. Port A not available on 52-pin uPSD33xx devices
2. For each bit, 1 = drive port pin to logic '1,' 0 = drive port pin to logic ’0’
3. Default state of register is 00h after reset or power-up
Table 100. MCU I/O Mode Port B Data Out Register (address = csiop + offset 05h)
Note: 1. For each bit, 1 = drive port pin to logic '1,' 0 = drive port pin to logic ’0’
2. Default state of register is 00h after reset or power-up
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PC7 X X PC4 PC3 PC2 X X
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
XXXXX PD2(3) PD1 X
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0173/231
uPSD33xx
Table 101. MCU I/O Mode Port C Data Out Register (address = csiop + offset 12h)
Note: 1. For each bit, 1 = drive port pin to logic '1,' 0 = drive port pin to logic ’0’
2. Default state of register is 00h after reset or power-up
Table 102. MCU I/O Mode Port D Data Out Register (address = csiop + offset 13h)
Note: 1. For each bit, 1 = drive port pin to logic '1,' 0 = drive port pin to logic ’0’
2. Default state for register is 00h after reset or power-up
3. Not available on 52-pin uPSD33xx devices
Table 103. MCU I/O Mode Port A Direction Register(1) (address = csiop + offset 06h)
Note: 1. Port A not available on 52-pin uPSD33xx devices
2. For each bit, 1 = out from uPSD33xx port pin1, 0 = in to PSD33xx port pin
3. Default state for register is 00h after reset or power-up
Table 104. MCU I/O Mode Port B Direction In Register (address = csiop + offset 07h)
Note: 1. For each bit, 1 = out from uPSD33xx port pin1, 0 = in to PSD33xx port pin
2. Default state for register is 00h after reset or power-up
Table 105. MCU I/O Mode Port C Direction Register (address = csiop + offset 14h)
Note: 1. For each bit, 1 = out from uPSD33xx port pin1, 0 = in to PSD33xx port pin
2. Default state for register is 00h after reset or power-up
Table 106. MCU I/O Mode Port D Direction Register (address = csiop + offset 15h)
Note: 1. For each bit, 1 = out from uPSD33xx port pin1, 0 = in to PSD33xx port pin
2. Default state for register is 00h after reset or power-up
3. Not available on 52-pin uPSD33xx devices
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PC7 N/A N/A PC4 PC3 PC2 N/A N/A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
N/A N/A N/A N/A N/A PD2(3) PD1 N/A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PC7 N/A N/A PC4 PC3 PC2 N/A N/A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
N/A N/A N/A N/A N/A PD2(3) PD1 N/AuPSD33xx
174/231
PLD I/O Mode. Pins on Ports A, B, C, and D can
serve as inputs to either the DPLD or the GPLD.
Inputs to these PLDs from Ports A, B, and C are
routed through IMCs before reaching the PLD input
bus. Inputs to the PLDs from Port D do not
pass through IMCs, but route directly to the PLD
input bus.
Pins on Ports A, B, and C can serve as outputs
from GPLD OMCs, and Port D pins can be outputs
from the DPLD (external chip-selects) which do
not consume OMCs.
Whenever a pin is specified to be a PLD output, it
cannot be used for MCU I/O mode, or other pin
modes. If a pin is specified to be a PLD input, it is
still possible to read the pin using MCU I/O input
mode with the csiop register Data In. Also, the
csiop Direction register can still affect a pin which
is used for a PLD input. The csiop Data Out register
has no effect on a PLD output pin.
Each pin on Ports A, B, C, and D have a tri-state
buffer at the final output stage. The Output Enable
signal for this buffer is driven by the logical OR of
two signals. One signal is an Output Enable signal
generated by the AND-OR array (from an .oe
equation specified in PSDsoft), and the other signal
is the output of the csiop Direction register.
This logic is shown in Figure 69., page 169. At
power-on, all port pins default to high-impedance
input (Direction registers default to 00h). However,
if an equation is written for the Output Enable that
is active at power-on, then the pin will behave as
an output.
PLD I/O equations are specified in PSDsoft Express
and programmed into the uPSD using
JTAG. Figure 70 shows a very simple combinatorial
logic example which is implemented on pins of
Port B.
To give a general idea how PLD logic is implemented
using PSDsoft Express, Figure
71., page 175 illustrates the pin declaration window
of PSDsoft Express, showing the PLD output
at pin PB0 declared as “Combinatorial” in the “PLD
Output” section, and a signal name, “pld_out”, is
specified. The other three signals on pins PB1,
PB2, and PB3 would be declared as “Logic or Address”
in the “PLD Input” section, and given signal
names.
In the “Design Assistant” window of PSDsoft Express
shown in Figure 72., page 176, simply enter
the logic equation for the signal “pld_out” as
shown. Either type in the logic statements or enter
them using a point-and-click method, selecting
various signal names and logic operators available
in the window.
After PSDsoft Express has accepted and realized
the logic from the equations, it synthesizes the logic
statement:
pld_out = ( pld_in_1 # pld_in_2 ) & !pld_in_3;
to be programmed into the GPLD. See the PSDsoft
User’s Manual for all the steps.
Note: If a particular OMC output is specified as an
internal node and not specified as a port pin output
in PSDsoft Express, then the port pin that is associated
with that OMC can be used for other I/O
functions.
Figure 70. Simple PLD Logic Example
PLDIN 1
PLDIN 2
PLDIN 3
PLD OUT PB0
PB3
PB2
PB1
AI09178175/231
uPSD33xx
Figure 71. Pin Declarations in PSDsoft Express for Simple PLD ExampleuPSD33xx
176/231
Figure 72. Using the Design Assistant in PSDsoft Express for Simple PLD Example177/231
uPSD33xx
Latched Address Output Mode. In the MCU
Module, the data bus Bits D0-D15 are multiplexed
with the low address Bits A0-A15, and the ALE signal
is used to separate them with respect to time.
Sometimes it is necessary to send de-multiplexed
address signals to external peripherals or memory
devices. Latched Address Output mode will drive
individual demuxed address signals on pins of
Ports A or B. Port pins can be designated for this
function on a pin-by-pin basis, meaning that an entire
port will not be sacrificed if only a few address
signals are needed.
To activate this mode, the desired pins on Port A
or Port B are designated as “Latched Address Out”
in PSDsoft. Then in the 8032 initialization firmware,
a logic ’1’ is written to the csiop Control register
for Port A or Port B in each bit position that
corresponds to the pin of the port driving an address
signal. Table 107 and Table 108 define the
csiop Control register locations and bit assignments.
The latched low address byte A4-A7 is available
on both Port A and Port B. The high address byte
A8-A15 is available on Port B only. Selection of
high or low address byte is specified in PSDsoft
Express.
Table 107. Latched Address Output, Port A Control Register(1) (address = csiop + offset 02h)
Note: 1. Port A not available on 52-pin uPSD33xx devices
2. For each bit, 1 = drive demuxed 8032 address signal on pin, 0 = pin is default mode, MCU I/O
3. Default state for register is 00h after reset or power-up
Table 108. Latched Address Output, Port B Control Register (address = csiop + offset 03h)
Note: 1. For each bit, 1 = drive demuxed 8032 address signal on pin, 0 = pin is default mode, MCU I/O
2. Default state for register is 00h after reset or power-up
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PA7
(addr A7)
PA6
(addr A6)
PA5
(addr A5)
PA4
(addr A4)
PA3
(addr A3)
PA2
(Addr A2)
PA1
(addr A1)
PA0
(addr A0)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PB7
(addr A7 or
A15)
PB6
(addr A6 or
A14)
PB5
(addr A5 or
A13)
PB4
(addr A4 or
A12)
PB3
(addr A3 or
A11)
PB2
(Addr A2 or
A10)
PB1
(addr A1 or
A9)
PB0
(addr A0 or
A8)uPSD33xx
178/231
Peripheral I/O Mode. This mode will provide a
data bus repeater function for the 8032 to interface
with external parallel peripherals. The mode is
only available on Port A (80-pin devices only) and
the data bus signals, D0 - D7, are de-multiplexed
(no address A0-A7). When active, this mode behaves
like a bidirectional buffer, with the direction
automatically controlled by the 8032 RD and WR
signals for a specified address range. The DPLD
signals PSEL0 and PSEL1 determine this address
range. Figure 69., page 169 shows the action of
Peripheral I/O mode on the Output Enable logic of
the tri-state output driver for a single port pin. Figure
73., page 178 illustrates data repeater the operation.
To activate this mode, choose the pin
function “Peripheral I/O Mode” in PSDsoft Express
on any Port A pin (all eight pins of Port A will automatically
change to this mode). Next in PSDsoft,
specify an address range for the PSELx signals in
the “Chip-Select” section of the “Design Assistant.”
Specify an address range for either PSEL0 or
PSEL1. Always qualify the PSELx equation with
“PSEN is logic '1'” to ensure Peripheral I/O mode
is only active during 8032 data cycles, not code cycles.
Only one equation is needed since PSELx
signals are OR’ed together (Figure 73). Then in
the 8032 initialization firmware, a logic ’1’ is written
to the csiop VM register, Bit 7 (PIO_EN) as shown
in Table 73., page 132. After this, Port A will automatically
perform this repeater function whenever
the 8032 presents an address (and memory page
number, if paging is used) that is within the range
specified by PSELx. Once Port A is designated as
Peripheral I/O mode in PSDsoft Express, it cannot
be used for other functions.
Note: The user can alternatively connect an external
parallel peripheral to the standard 8032 AD0-
AD7 pins on an 80-pin uPSD device (not Port A),
but these pins have multiplexed address and data
signals, with a weaker fanout drive capability.
Figure 73. Peripheral I/O Mode
PSEL1
PORT
A pins
PA0 - PA7
PSEL0
VM REGISTER BIT 7 (PIO EN)
8032 RD
8032 WR
8032 DATA
BUS D0-D7
(DE-MUXED)
8 8
AI02886A179/231
uPSD33xx
JTAG ISP Mode. Four of the pins on Port C are
based on the IEEE 1149.1 JTAG specification and
are used for In-System Programming (ISP) of the
PSD Module and debugging of the 8032 MCU
Module. These pins (TDI, TDO, TMS, TCK) are
dedicated to JTAG and cannot be used for any
other I/O function. There are two optional pins on
Port C (TSTAT and TERR) that can be used to reduce
programming time during ISP. See JTAG
ISP and JTAG Debug, page 195.
Other Port Capabilities. It is possible to change
the type of output drive on the ports at run-time. It
is also possible to read the state of the output enable
signal of the output driver at run-time. The following
sections provide the details.
Port Pin Drive Options. The csiop Drive Select
registers allow reconfiguration of the output drive
type for certain pins on Ports A, B, C, and D. The
8032 can change the default drive type setting at
run-time. The is no action needed in PSDsoft Express
to change or define these pin output drive
types. Figure 69., page 169 shows the csiop Drive
Select register output controlling the pin output
driver. The default setting for drive type for all pins
on Ports A, B, C, and D is a standard CMOS pushpull
output driver.
Note: When a pin on Port A, B, C, D is not used as
an output and has no external device driving it as
an input (floating pin), excess power consumption
can be avoided by placing a weak pull-up resistor
(100KΩ) to VDD which keeps the CMOS input pin
from floating.
Drive Select Registers. The csiop Drive Select
Registers will configure a pin output driver as
Open Drain or CMOS push/pull for some port pins,
and controls the slew rate for other port pins. An
external pull-up resistor should be used for pins
configured as Open Drain, and the resistor should
be sized not to exceed the current sink capability
of the pin (see DC specifications). Open Drain outputs
are diode clamped, thus the maximum voltage
on an pin configured as Open Drain is VDD +
0.7V.
A pin can be configured as Open Drain if its corresponding
bit in the Drive Select Register is set to
logic '1.'
Note: The slew rate is a measurement of the rise
and fall times of an output. A higher slew rate
means a faster output response and may create
more electrical noise. A pin operates in a high slew
rate when the corresponding bit in the Drive Register
is set to '1.' The default rate is standard slew
rate (see AC specifications).
Table 109 through Table 112., page 180 show the
csiop Drive Registers for Ports A, B, C, and D. The
tables summarize which pins can be configured as
Open Drain outputs and which pins the slew rate
can be changed. The default output type is CMOS
push/pull output with normal slew rate.
Enable Out Registers. The state of the output
enable signal for the output driver at each pin on
Ports A, B, C, and D can be read at any time by the
8032 when it reads the csiop Enable Output registers.
Logic '1' means the driver is in output mode,
logic ’0’ means the output driver is in high-impedance
mode, making the pin suitable for input mode
(read by the input buffer shown in Figure
69., page 169). Figure 69 shows the three sources
that can control the pin output enable signal: a
product term from AND-OR array; the csiop Direction
register; or the Peripheral I/O Mode logic (Port
A only). The csiop Enable Out registers represent
the state of the final output enable signal for each
port pin driver, and are defined in Table
113., page 180 through Table 116., page 180.
Table 109. Port A Pin Drive Select Register(1) (address = csiop + offset 08h)
Note: 1. Port A not available on 52-pin uPSD33xx devices
2. For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS push/pull
3. Default state for register is 00h after reset or power-up
Table 110. Port B Pin Drive Select Register (address = csiop + offset 09h)
Note: 1. For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS push/pull
2. Default state for register is 00h after reset or power-up
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PA7
Open Drain
PA6
Open Drain
PA5
Open Drain
PA4
Open Drain
PA3
Slew Rate
PA2
Slew Rate
PA1
Slew Rate
PA0
Slew Rate
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PB7
Open Drain
PB6
Open Drain
PB5
Open Drain
PB4
Open Drain
PB3
Slew Rate
PB2
Slew Rate
PB1
Slew Rate
PB0
Slew RateuPSD33xx
180/231
Table 111. Port C Pin Drive Select Register (address = csiop + offset 16h)
Note: 1. For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS push/pull
2. Default state for register is 00h after reset or power-up
Table 112. Port D Pin Drive Select Register (address = csiop + offset 17h)
Note: 1. For each bit, 1 = pin drive type is selected, 0 = pin drive type is default mode, CMOS push/pull
2. Default state for register is 00h after reset or power-up
3. Pin is not available on 52-pin uPSD33xx devices
Table 113. Port A Enable Out Register(1) (address = csiop + offset 0Ch)
Note: 1. Port A not available on 52-pin uPSD33xx devices
2. For each bit, 1 = pin drive is enabled as an output, 0 = pin drive is off (high-impedance, pin used as input)
Table 114. Port B Enable Out Register (address = csiop + offset 0Dh)
Note: For each bit, 1 = pin drive is enabled as an output, 0 = pin drive is off (high-impedance, pin used as input)
Table 115. Port C Enable Out Register (address = csiop + offset 1Ah)
Note: 1. For each bit, 1 = pin drive is enabled as an output, 0 = pin drive is off (high-impedance, pin used as input)
Table 116. Port D Enable Out Register (address = csiop + offset 1Bh)
Note: 1. For each bit, 1 = pin drive is enabled as an output, 0 = pin drive is off (high-impedance, pin used as input)
2. Pin is not available on 52-pin uPSD33xx devices
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PC7
Open Drain N/A (JTAG) N/A (JTAG) PC4
Open Drain
PC3
Open Drain
PC2
Open Drain N/A (JTAG) N/A (JTAG)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
N/A N/A N/A N/A N/A PD2(3)
Slew Rate
PD1
Slew Rate N/A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PA7 OE PA6 OE PA5 OE PA4 OE PA3 OE PA2 OE PA1 OE PA0 OE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PB7 OE PB6 OE PB5 OE PB4 OE PB3 OE PB2 OE PB1 OE PB0 OE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PC7 OE N/A (JTAG) N/A (JTAG) PC4 OE PC3 OE PC2 OE N/A (JTAG) N/A (JTAG)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
N/A N/A N/A N/A N/A PD2 OE(2) PD1 OE N/A181/231
uPSD33xx
Individual Port Structures. Ports A, B, C, and D
have some differences. The structure of each individual
port is described in the next sections.
Port A Structure. Port A supports the following
operating modes:
■ MCU I/O Mode
■ GPLD Output Mode from Output Macrocells
MCELLABx
■ GPLD Input Mode to Input Macrocells IMCAx
■ Latched Address Output Mode
■ Peripheral I/O Mode
Port A also supports Open Drain/Slew Rate output
drive type options using csiop Drive Select registers.
Pins PA0-PA3 can be configured to fast slew
rate, pins PA4-PA7 can be configured to Open
Drain Mode.
See Figure 74 for details.
Figure 74. Port A Structure
Note: 1. Port pins PA0-PA3 are capable of Fast Slew Rate output drive option. Port pins PA4-PA7 are capable of Open Drain output option.
I/O PORT A
LOGIC
O
U
T
P
U
T
M
U
P X
D
B
M
U
X
DIRECTION
DRIVE SELECT
CONTROL
DATA OUT
(MCUI/O)
ENABLE OUT
DATA IN (MCUI/O)
D BIT, PERIPH I/O MODE
PT OUTPUT ENABLE (.OE)
LATCHED ADDR BIT
OE
MUX
OUTPUT
ENABLE TYPICAL
PIN, PORT A
PSD MODULE RESET
ONE of 6
CSIOP
REGISTERS
OUTPUT
SELECT
PERIPHERAL I/O
MODE SETS
DIRECTION
8032 ADDRESS, DATA, CONTROL BUS
1
2
3
1 4
2
3
4
5
6
FROM OMC OUTPUT (MCELLABx)
FROM PLD
INPUT BUS
FROM ANDOR
ARRAY
FROM OMC
ALLOCATOR
D
CLR
DIRECTION
DRIVE
CONTROL
(MCUI/O)
DATA OUT
8032
WR
RESET
PSDsoft
8032 RD
WR RD PSELx
PERIPH I/O
DATA BIT
TO IMCs
PIO EN
CSIOP
REGISTERS
Q
Q
Q
Q
DRIVE TYPE SELECT(1) 8032
DATA
BITS
8032
DATA
BIT
PIN INPUT
CMOS
BUFFER
NO
HYSTERESIS
VDD VDD
PIN
OUTPUT
1 = OPEN
DRAIN,
PA4 - PA7
1 = FAST
SLEW RATE,
PA0 - PA3
IMCA0 - IMCA7
AI09179uPSD33xx
182/231
Port B Structure. Port B supports the following
operating modes:
■ MCU I/O Mode
■ GPLD Output Mode from Output Macrocells
MCELLABx, or MCELLBCx (OMC allocator
routes these signals)
■ GPLD Input Mode to Input Macrocells IMCBx
■ Latched Address Output Mode
Port B also supports Open Drain/Slew Rate output
drive type options using the csiop Drive Select registers.
Pins PB0-PB3 can be configured to fast
slew rate, pins PB4-PB7 can be configured to
Open Drain Mode.
See Figure 75 for detail.
Figure 75. Port B Structure
Note: 1. Port pins PB0-PB3 are capable of Fast Slew Rate output drive option. Port pins PB4-PB7 are capable of Open Drain output option.
I/O PORT B
LOGIC
O
U
T
P
U
T
M
U
P X
D
B
M
U
X
DIRECTION
DRIVE SELECT
CONTROL
DATA OUT
(MCUI/O)
ENABLE OUT
DATA IN (MCUI/O)
PT OUTPUT ENABLE (.OE)
LATCHED ADDR BIT
OUTPUT
ENABLE
OUTPUT
ENABLE
TYPICAL
PIN, PORT B
PSD MODULE RESET
ONE of 6
CSIOP
REGISTERS
OUTPUT
SELECT
8032 ADDRESS, DATA, CONTROL BUS
1
2
3
1
2
3
4
5
6
FROM OMC OUTPUT
(MCELLABx or MCELLBCx)
FROM PLD
INPUT BUS
FROM ANDOR
ARRAY
FROM OMC
ALLOCATOR
D
CLR
DIRECTION
DRIVE
CONTROL
(MCUI/O)
DATA OUT
8032
WR
RESET
PSDsoft
8032 RD
TO IMCs
CSIOP
REGISTERS
Q
Q
Q
Q
DRIVE TYPE SELECT(1) 8032
DATA
BITS
8032
DATA
BIT
PIN INPUT
CMOS
BUFFER
NO
HYSTERESIS
VDD VDD
PIN
OUTPUT
1 = OPEN
DRAIN,
PB4 - PB7
1 = FAST
SLEW RATE,
PB0 - PB3
IMCB0 - IMCB7
AI09180183/231
uPSD33xx
Port C Structure. Port C supports the following
operating modes on pins PC2, PC3, PC4, PC7:
■ MCU I/O Mode
■ GPLD Output Mode from Output Macrocells
MCELLBC2, MCELLBC3, MCELLBC4,
MCELLBC7
■ GPLD Input Mode to Input Macrocells IMCC2,
IMCC3, IMCC4, IMCC7
See Figure 76., page 184 for detail.
Port C pins can also be configured in PSDsoft for
other dedicated functions:
– Pins PC3 and PC4 support TSTAT and TERR
status indicators, to reduce the amount of time
required for JTAG ISP programming. These
two pins must be used together for this
function, adding to the four standard JTAG
signals. When TSTAT and TERR are used, it
is referred to as “6-pin JTAG”. PC3 and PC4
cannot be used for other functions if they are
used for 6-pin JTAG. See JTAG ISP and
JTAG Debug, page 195 for details.
– PC2 can be used as a voltage input (from
battery or other DC source) to backup the
contents of SRAM when VDD is lost. This
function is specified in PSDsoft Express as
SRAM Standby Mode (battery
backup), page 193.
– PC3 can be used as an output to indicate
when a Flash memory program or erase
operation has completed. This is specified in
PSDsoft Express as Ready/Busy
(PC3), page 153.
– PC4 can be used as an output to indicate
when the SRAM has switched to backup
voltage (when VDD is less than the battery
input voltage on PC2). This is specified in
PSDsoft Express as “Standby-On Indicator”
(see SRAM Standby Mode (battery
backup), page 193).
The remaining four pins (TDI, TDO, TCK, TMS) on
Port C are dedicated to the JTAG function and
cannot be used for any other function. See JTAG
ISP and JTAG Debug, page 195.
Port C also supports the Open Drain output drive
type options on pins PC2, PC3, PC4, and PC7 using
the csiop Drive Select registers.uPSD33xx
184/231
Figure 76. Port C Structure
Note: 1. Pull-up switches to VBAT when SRAM goes to battery back-up mode.
2. Optional function on a specific Port C pin.
I/O PORT C
LOGIC
O
U
T
P
U
T
M
U
P X
D
B
M
U
X
DIRECTION
DRIVE SELECT
DATA OUT
(MCUI/O)
ENABLE OUT
DATA IN (MCUI/O)
PT OUTPUT ENABLE, .OE (JTAG STATE MACHINE
AUTOMATICALLY CONTROLS OE FOR JTAG SIGNALS)
OUTPUT
ENABLE TYPICAL
PIN,
PORT C
PSD MODULE RESET
ONE of 6
CSIOP
REGISTERS
8032 ADDRESS, DATA, CONTROL BUS
1
2
3
4
5
1
2
3
4
5
FROM OMC OUTPUT (MCELLBCx)
STANDBY ON(2) FROM SRAM
BACK-UP CIRCUIT
FROM FLASH MEMORIES
TO/FROM JTAG
STATE MACHINE
FROM PLD
INPUT BUS
FROM ANDOR
ARRAY
FROM OMC
ALLOCATOR
D
CLR
DIRECTION
DRIVE
(MCUI/O)
DATA OUT
8032
WR
RESET
PSDsoft
8032 RD
TO IMCs
CSIOP
REGISTERS
Q
Q
Q
DRIVE TYPE SELECT(2) 8032
DATA
BITS
8032
DATA
BIT
PIN
CMOS INPUT
BUFFER
NO
HYSTERESIS
VDD VDD/VBAT
(1)
VDD/VBAT
(1)
PIN
OUTPUT
50k
PULL-UP
ONLY ON
JTAG TDI,
TMS, TCK
SIGNALS
TO SRAM
BATTERY
BACK-UP
CIRCUIT(2)
IMCC2, IMCC3,
IMCC4, IMCC7
RDY/BSY(2)
TDO, TSTAT(2), TERR(2)
TDI, TMS, TCK
AI09181185/231
uPSD33xx
Port D Structure. Port D has two I/O pins (PD1,
PD2) on 80-pin uPSD33xx devices, and just one
pin (PD1) on 52-pin devices, supporting the following
operating modes:
■ MCU I/O Mode
■ DPLD Output Mode for External Chip Selects,
ECS1, ECS2. This does not consume OMCs
in the GPLD.
■ PLD Input Mode – direct input to the PLD Input
Bus available to DPLD and GPLD. Does not
use IMCs
See Figure 77., page 186 for detail.
Port D pins can also be configured in PSDsoft as
pins for other dedicated functions:
– PD1 can be used as a common clock input to
all 16 OMC Flip-flops (see OMCs, page 136)
and also the Automatic Power-Down
(APD), page 189.
– PD2 can be used as a common chip select
signal (CSI) for the Flash and SRAM
memories on the PSD Module (see Chip Select
Input (CSI), page 191). If driven to logic ’1’
by an external source, CSI will force all
memories into standby mode regardless of
what other internal memory select signals are
doing on the PSD Module. This is specified in
PSDsoft as “PSD Chip Select Input, CSI”.
Port D also supports the Fast Slew Rate output
drive type option using the csiop Drive Select registers.uPSD33xx
186/231
Figure 77. Port D Structure
Note: 1. Optional function on a specific Port D pin.
I/O PORT D
LOGIC
O
U
T
P
U
T
M
U
P X
D
B
M
U
X
DIRECTION
DRIVE SELECT
DATA OUT
(MCUI/O)
ENABLE OUT
DATA IN (MCUI/O)
PT OUTPUT ENABLE (.OE)
OUTPUT
ENABLE
OUTPUT
ENABLE
TYPICAL
PIN, PORT D
PSD MODULE RESET
ONE of 5
CSIOP
REGISTERS
8032 ADDRESS, DATA, CONTROL BUS
1
2
1
2
3
4
5
FROM DPLD EXTERNAL CHIP (ECSx)
FROM PLD
INPUT BUS
FROM ANDOR
ARRAY
FROM DPLD
D
CLR
DIRECTION
DRIVE
(MCUI/O)
DATA OUT
8032
WR
RESET
PSDsoft
8032 RD
TO POWER MANAGEMENT AND PLD INPUT BUS
CSIOP
REGISTERS
Q
Q
Q
8032 DRIVE TYPE SELECT
DATA
BITS
8032
DATA
BIT
PIN INPUT
CMOS
BUFFER
NO
HYSTERESIS
VDD VDD
PIN
OUTPUT
1 = FAST
SLEW RATE
PD1. PIN, PD2.PIN DIRECTLY TO PLD INPUT BUS, NO IMC
CSI(1)
TO POWER MANAGEMENT
CLKIN(1)
AI09182187/231
uPSD33xx
Power Management. The PSD Module offers
configurable power saving options, and also a way
to manage power to the SRAM (battery backup).
These options may be used individually or in combinations.
A top level description for these functions
is given here, then more detailed
descriptions will follow.
– Zero-Power Memory: All memory arrays
(Flash and SRAM) in the PSD Module are built
with zero-power technology, which puts the
memories into standby mode (~ zero DC
current) when 8032 address signals are not
changing. As soon as a transition occurs on
any address input, the affected memory
“wakes up”, changes and latches its outputs,
then goes back to standby. The designer does
not have to do anything special to achieve this
memory standby mode when no inputs are
changing—it happens automatically. Thus,
the slower the 8032 clock, the lower the
current consumption.
Both PLDs (DPLD and GPLD) are also zeropower,
but this is not the default condition. The
8032 must set a bit in one of the csiop PMMR
registers at run-time to achieve zero-power.
– Automatic Power-Down (APD): The APD
feature allows the PSD Module to reach it’s
lowest current consumption levels. If enabled,
the APD counter will time-out when there is a
lack of 8032 bus activity for an extended
amount of time (8032 asleep). After time-out
occurs, all 8032 address and data buffers on
the PSD Module are shut down, preventing
the PSD Module memories and potentially the
PLDs from waking up from standby, even if
address inputs are changing state because of
noise or any external components driving the
address lines. Since the actual address and
data buffers are turned off, current
consumption is even further reduced.
Note: Non-address signals are still available
to PLD inputs and will wake up the PLDs if
these signals are changing state, but will not
wake up the memories.
The APD counter requires a relatively slow
external clock input on pin PD1 that does stop
when the 8032 goes to sleep mode.
– Forced Power-Down (FPD): The MCU can
put the PSD Module into Power-Down mode
with the same results as using APD described
above, but FPD does not rely on the APD
counter. Instead, FPD will force the PSD
Module into Power-Down mode when the
MCU firmware sets a bit in one of the csiop
PMMR registers. This is a good alternative to
APD because no external clock is needed for
the APD counter.
– PSD Module Chip Select Input (CSI): This
input on pin PD2 (80-pin devices only) can be
used to disable the internal memories, placing
them in standby mode even if address inputs
are changing. This feature does not block any
internal signals (the address and data buffers
are still on but signals are ignored) and CSI
does not disable the PLDs. This is a good
alternative to using the APD counter, which
requires an external clock on pin PD1.
– Non-Turbo Mode: The PLDs can operate in
Turbo or non-Turbo modes. Turbo mode has
the shortest signal propagation delay, but
consumes more current than non-Turbo
mode. A csiop register can be written by the
8032 to select modes, the default mode is with
Turbo mode enabled. In non-Turbo mode, the
PLDs can achieve very low standby current (~
zero DC current) while no PLD inputs are
changing, and the PLDs will even use less AC
current when inputs do change compared to
Turbo mode.
When the Turbo mode is enabled, there is a
significant DC current component AND the AC
current component is higher than non-Turbo
mode, as shown in Figure 85., page 202 (5V)
and Figure 86., page 202 (3.3V).
– Blocking Bits: Significant power savings can
be achieved by blocking 8032 bus control
signals (RD, WR, PSEN, ALE) from reaching
PLD inputs, if these signals are not used in
any PLD equations. Blocking is achieved by
the 8032 writing to the “blocking bits” in csiop
PMMR registers. Current consumption of the
PLDs is directly related to the composite
frequency of all transitions on PLD inputs, so
blocking certain PLD inputs can significantly
lower PLD operating frequency and power
consumption (resulting in a lower frequency
on the graphs of Figure 85., page 202 and
Figure 86., page 202).
– SRAM Backup Voltage: Pin PC2 can be
configured in PSDsoft to accept an alternate
DC voltage source (battery) to automatically
retain the contents of SRAM when VDD drops
below this alternate voltage.
Note: It is recommended to prevent unused
inputs from floating on Ports A, B, C, and D by
pulling them up to VDD with a weak external
resistor (100KΩ), or by setting the csiop
Direction register to “output” at run-time for all
unused inputs. This will prevent the CMOS
input buffers of unused input pins from
drawing excessive current.
The csiop PMMR register definitions are shown in
117 through Table 119., page 188.uPSD33xx
188/231
Table 117. Power Management Mode Register PMMR0 (address = csiop + offset B0h)
Note: All the bits of this register are cleared to zero following Power-up. Subsequent Reset (RST) pulses do not clear the registers.
1. Blocking bits should be set to logic ’1’ only if the signal is not needed in a DPLD or GPLD logic equation.
Table 118. Power Management Mode Register PMMR2 (address = csiop + offset B4h)
Note: The bits of this register are cleared to zero following Power-up. Subsequent Reset (RST) pulses do not clear the registers.
1. Blocking bits should be set to logic ’1’ only if the signal is not needed in a DPLD or GPLD logic equation.
Table 119. Power Management Mode Register PMMR3 (address = csiop + offset C7h)
Note: The bits of this register are cleared to zero following Power-up. Subsequent Reset (RST) pulses do not clear the registers.
Bit 0 X 0 Not used, and should be set to zero.
Bit 1 APD Enable 0 Automatic Power Down (APD) counter is disabled.
1 APD counter is enabled
Bit 2 X 0 Not used, and should be set to zero.
Bit 3 PLD Turbo
Disable
0 = on PLD Turbo mode is on
1 = off PLD Turbo mode is off, saving power.
Bit 4
Blocking Bit,
CLKIN to
PLDs(1)
0 = on CLKIN (pin PD1) to the PLD Input Bus is not blocked. Every transition of CLKIN
powers-up the PLDs.
1 = off CLKIN input to PLD Input Bus is blocked, saving power. But CLKIN still goes to APD
counter.
Bit 5
Blocking Bit,
CLKIN to
OMCs Only(1)
0 = on CLKIN input is not blocked from reaching all OMC’s common clock inputs.
1 = off CLKIN input to common clock of all OMCs is blocked, saving power. But CLKIN still
goes to APD counter and all PLD logic besides the common clock input on OMCs.
Bit 6 X 0 Not used, and should be set to zero.
Bit 7 X 0 Not used, and should be set to zero.
Bit 0 X 0 Not used, and should be set to zero.
Bit 1 X 0 Not used, and should be set to zero.
Bit 2 Blocking Bit,
WR to PLDs(1)
0 = on 8032 WR input to the PLD Input Bus is not blocked.
1 = off 8032 WR input to PLD Input Bus is blocked, saving power.
Bit 3 Blocking Bit,
RD to PLDs(1)
0 = on 8032 RD input to the PLD Input Bus is not blocked.
1 = off 8032 RD input to PLD Input Bus is blocked, saving power.
Bit 4
Blocking Bit,
PSEN to
PLDs(1)
0 = on 8032 PSEN input to the PLD Input Bus is not blocked.
1 = off 8032 PSEN input to PLD Input Bus is blocked, saving power.
Bit 5
Blocking Bit,
ALE to
PLDs(1)
0 = on 8032 ALE input to the PLD Input Bus is not blocked.
1 = off 8032 ALE input to PLD Input Bus is blocked, saving power.
Bit 5
Blocking Bit,
PC7 to
PLDs(1)
0 = on Pin PC7 input to the PLD Input Bus is not blocked.
1 = off Pin PC7 input to PLD Input Bus is blocked, saving power.
Bit 7 X 0 Not used, and should be set to zero.
Bit 0 X 0 Not used, and should be set to zero.
Bit 1 FORCE_PD 0 = off APD counter will cause Power-Down Mode if APD is enabled.
1 = on Power-Down mode will be entered immediately regardless of APD activity.
Bit 3-7 X 0 Not used, and should be set to zero.189/231
uPSD33xx
Automatic Power-Down (APD). The APD unit
shown in Figure 63., page 157 puts the PSD Module
into power-down mode by monitoring the activity
of the 8032 Address Latch Enable (ALE) signal.
If the APD unit is enabled by writing a logic ’1’ to
Bit 1 of the csiop PMMR0 register, and if ALE signal
activity has stopped (8032 in sleep mode),
then the four-bit APD counter starts counting up. If
the ALE signal remains inactive for 15 clock periods
of the CLKIN signal (pin PD1), then the APD
counter will reach maximum count and the power
down indicator signal (PDN) goes to logic ’1’ forcing
the PSD Module into power-down mode. During
this time, all buffers on the PSD Module for
8032 address and data signals are disabled in silicon,
preventing the PSD Module memories from
waking up from stand-by mode, even if noise or
other devices are driving the address lines. The
PLDs will also stay in standby mode if the PLDs
are in non-Turbo mode and if all other PLD inputs
(non-address signals) are static.
However, if the ALE signal has a transition before
the APD counter reaches max count, the APD
counter is cleared to zero and the PDN signal will
not go active, preventing power-down mode. To
prevent unwanted APD time-outs during normal
8032 operation (not sleeping), it is important to
choose a clock frequency for CLKIN that will NOT
produce 15 or more pulses within the longest period
between ALE transitions. A 32768 Hz clock signal
is quite often an ideal frequency for CLKIN and
APD, and this frequency is often available on external
supervisor or real-time clock devices.
The “PDN” power-down indicator signal is available
to the PLD input bus to use in any PLD equations
if desired. The user may want to send this
signal as a PLD output to an external device to indicate
the PSD Module is in power-down mode.
PSDsoft Express automatically includes the
“PDN” signal in the DPLD chip select equations for
FSx, CSBOOTx, RS0, and CSIOP.
The following should be kept in mind when the
PSD Module is in power-down mode:
– 8032 address and data bus signals are
blocked from all memories and both PLDs.
– The PSD Module comes out of power-down
mode when: ALE starts pulsing again, or the
CSI input on pin PD2 transitions from logic ’1’
to logic '0,' or the PSD Module reset signal,
RST, transitions from logic ’0’ to logic '1.'
– Various signals can be blocked (prior to
power-down mode) from entering the PLDs by
using “blocking bits” in csiop PMMR registers.
– All memories enter standby mode, and the
state of the PLDs and I/O Ports are
unchanged (if no PLD inputs change). Table
121., page 194 shows the effects of powerdown
mode on I/O pins while in various
operating modes.
– The 8032 Ports 1,3, and 4 on the MCU Module
are not affected at all by power-down mode in
the PSD Module.
– Power-down standby current given in the AC
specifications for PSD Module assume there
are no transitions on any unblocked PLD
input, and there are no output pins driving any
loads.
The APD counter will count whenever Bit 1 of
csiop PMMR0 register is set to logic '1,' and when
the ALE signal is steady at either logic ’1’ or logic
’0’ (not transitioning). Figure 79., page 191 shows
the flow leading up to power-down mode. The only
action required in PSDsoft Express to enable APD
mode is to select the pin function “Common Clock
Input, CLKIN” before programming with JTAG.uPSD33xx
190/231
Forced Power Down (FDP). An alternative to
APD is FPD. The resulting power-savings is the
same, but the PDN signal in Figure 78., page 191
is set and Power-Down mode is entered immediately
when firmware sets the FORCE_PD Bit to
logic '1' in the csiop Register PMMR3 (Bit 1). FPD
will override APD counter activity when
FORCE_PD is set. No external clock source for
the APD counter is needed. The FORCE_PD Bit is
cleared only by a reset condition.
Caution must be used when implementing FPD
because code memory goes off-line as soon as
PSD Module Power-Down mode is entered, leaving
the MCU with no instruction stream to execute.
The MCU Module must put itself into Power-Down
mode after it puts the PSD Module into PowerDown
Mode. How can it do this if code memory
goes off-line? The answer is the Pre-Fetch Queue
(PFQ) in the MCU Module. By using the instruction
scheme shown in the 8051 assembly code example
in Table 120, the PFQ will be loaded with the
final instructions to command the MCU Module to
Power Down mode after the PDS Module goes to
Power-Down mode. In this case, even though the
code memory goes off-line in the PSD Module, the
last few MCU instruction are sourced from the
PFQ.
Table 120. Forced Power-Down Example
PDOWN: ANL A8h, #7Fh ; disable all interrupts
ORL 9Dh, #C0h ; ensure PFQ and BC are enabled
MOV DPTR, #xxC7 ; load XDATA pointer to select PMMR3 register (xx = base
; address of csiop registers)
CLR A ; clear A
JMP LOOP ; first loop - fill PFQ/BQ with Power Down instructions
NOP ; second loop - fetch code from PFQ/BC and set Power-
; Down bits for PSD Module and then MCU Module
LOOP: MOVX @DPTR, A ; set FORCE_PD Bit in PMMR3 in PSD Module in second
; loop
MOV 87h, A ; set PD Bit in PCON Register in MCU Module in second
; loop
MOV A, #02h ; set power-down bit in the A Register, but not in PMMR3 or
; PCON yet in first loop
JMP LOOP ; uPSD enters into Power-Down mode in second loop191/231
uPSD33xx
Figure 78. Automatic Power Down (APD) Unit
Figure 79. Power-Down Mode Flow Chart Chip Select Input (CSI). Pin PD2 of Port D can
optionally be configured in PSDsoft Express as the
PSD Module Chip Select Input, CSI, which is an
active-low logic input. By default, pin PD2 does not
have the CSI function.
When the CSI function is specified in PSDsoft Express,
the CSI signal is automatically included in
DPLD chip select equations for FSx, CSBOOTx,
RS0, and CSIOP. When the CSI pin is driven to
logic ’0’ from an external device, all of these memories
will be available for READ and WRITE operations.
When CSI is driven to logic '1,' none of
these memories are available for selection, regardless
of the address activity from the 8032, reducing
power consumption. The state of the PLD
and port I/O pins are not changed when CSI goes
to logic ’1’ (disabled).
PMMR0, BIT 1 (APD EN)
8032 ALE
PSD MODULE RST_
CSI (pin PD2)
CLKIN (pin PD1)
PDN
OMC OUTPUTS
FSx
CSBOOTx
RS0
CSIOP
8032 DATA FROM MCU MODULE
8032 ADDR FROM MCU MODULE
PDN
PDN
CSI
PMMR3, BIT 1 (FORCE_PD)
ENABLE 1 = FOUND
TRANSITION
1 = FOUND
EDGE
CLEAR
FULL
COUNT
DPLD CHIP
SELECT
EQUATIONS
GPLD
TRANSITION
DETECTION
EDGE
DETECTION
4-BIT APD
UP-COUNTER
ENABLE
CLK
1 = POWER
DOWN MODE
ENABLE
PSD
MODULE
LINE
BUFFERS
8032 DATA
8032 ADDR
WHEN CSI FUNCTION IS SPECIFIED IN PSDSOFT EXPRESS,
CSI IS PART OF EQUATIONS FOR FSx, CSBOOTx, RS0, and CSIOP
AI06608B
Enable APD.
Set PMMR0,
Bit 1 = 1
RESET
OPTIONAL. Disable desired inputs to
PLDs by setting PMMR0 bits 4 and 5,
and PMMR2 bits 2 through 6
ALE idle
for 15 CLKIN
clocks?
PDN = 1, PSD
Module in PowerDown
Mode
YES
NO
AI09183uPSD33xx
192/231
PLD Non-Turbo Mode. The power consumption
and speed of the PLDs are controlled by the Turbo
Bit (Bit 3) in the csiop PMMR0 register. By setting
this bit to logic '1,' the Turbo mode is turned off and
both PLDs consume only stand-by current when
ALL PLD inputs have no transitions for an extended
time (65ns for 5V devices, 100ns for 3.3 V devices),
significantly reducing current consumption.
The PLDs will latch their outputs and go to standby,
drawing very little current. When Turbo mode
is off, PLD propagation delay time is increased as
shown in the AC specifications for the PSD Module.
Since this additional propagation delay also
effects the DPLD, the response time of the memories
on the PSD Module is also lengthened by that
same amount of time. If Turbo mode is off, the
user should add an additional wait state to the
8032 BUSCON SFR register if the 8032 clock frequency
is higher that a particular value. Please refer
to Table 36., page 64 in the MCU Module
section.
The default state of the Turbo Bit is logic '0,' meaning
Turbo mode is on by default (after power-up
and reset conditions) until it is turned off by the
8032 writing to PMMR0.
PLD Current Consumption. Figure
85., page 202 and Figure 86., page 202 (5V and
3.3V devices respectively) show the relationship
between PLD current consumption and the composite
frequency of all the transitions on PLD inputs,
indicating that a higher input frequency
results in higher current consumption.
Current consumption of the PLDs have a DC component
and an AC component. Both need to be
considered when calculating current consumption
for a specific PLD design. When Turbo mode is on,
there is a linear relationship between current and
frequency, and there is a substantial DC current
component consumed by the PSD Module when
there are no transitions on PLD inputs (composite
frequency is zero). The magnitude of this DC current
component is directly proportional to how
many product terms are used in the equations of
both PLDs. PSDsoft Express generates a “fitter”
report that specifies how many product terms were
used in a design out of a total of 186 available
product terms. Figure 85., page 202 and Figure
86., page 202 both give two examples, one with
100% of the 186 product terms used, and another
with 25% of the 186 product terms used.
Turbo Mode Current Consumption. To determine
the AC current component of the specific
PLD design with Turbo mode on, the user will have
to interpolate from the graph, given the number of
product terms specified in the fitter report, and the
estimated composite frequency of PLD input signal
transitions. For the DC component (y-axis
crossing), the user can calculate the number by
multiplying the number of product terms used
(from fitter report) times the DC current per product
term specified in the DC specifications for the
PSD Module. The total PLD current usage is the
sum of its AC and DC components.
Non-Turbo Mode Current Consumption. Notice
in Figure 85., page 202 and Figure
86., page 202 that when Turbo mode is off, the DC
current consumption is “zero” (just standby current)
when the composite frequency of PLD input
transitions is zero (no input transitions). Now moving
up the frequency axis to consider the AC current
component, current consumption remains
considerably less than Turbo mode until PLD input
transitions happen so rapidly that the PLDs do not
have time to latch their outputs and go to standby
between the transitions anymore. This is where
the lines converge on the graphs, and current consumption
becomes the same for PLD input transitions
at this frequency and higher regardless if
Turbo mode is on or off. To determine the current
consumption of the PLDs with Turbo mode off, extrapolate
the AC component from the graph based
on number of product terms and input frequency.
The only DC component in non-Turbo mode is the
PSD Module standby current.
The key to reducing PLD current consumption is to
reduce the composite frequency of transitions on
the PLD input bus, moving down the frequency
scale on the graphs. One way to do this is to carefully
select which signals are entering PLD inputs,
not selecting high frequency signals if they are not
used in PLD equations. Another way is to use PLD
“Blocking Bits” to block certain signals from entering
the PLD input bus.193/231
uPSD33xx
PLD Blocking Bits. Blocking specific signals
from entering the PLDs using bits of the csiop
PMMR registers can further reduce PLD AC current
consumption by lowering the effective composite
frequency of inputs to the PLDs.
Blocking 8032 Bus Control Signals. When the
8032 is active on the MCU Module, four bus control
signals (RD, WR, PSEN, and ALE) are constantly
transitioning to manage 8032 bus traffic.
Each time one of these signals has a transition
from logic ’1’ to '0,' or 0 to '1,' it will wake up the
PLDs if operating in non-Turbo mode, or when in
Turbo mode it will cause the affected PLD gates to
draw current. If equations in the DPLD or GPLD do
not use the signals RD, WR, PSEN, or ALE then
these signals can be blocked which will reduce the
AC current component substantially. These bus
control signals are rarely used in DPLD equations
because they are routed in silicon directly to the
memory arrays of the PSD Module, bypassing the
PLDs. For example, it is NOT necessary to qualify
a memory chip select signal with an MCU write
strobe, such as “fs0 = address range & !WR_”.
Only “fs0 = address range” is needed.
Each of the 8032 bus control signals may be
blocked individually by writing to Bits 2, 3, 4, and 5
of the PMMR2 register shown in Table
118., page 188. Blocking any of these four bus
control signals only prevents them from reaching
the PLDs, but they will always go to the memories
directly.
However, sometimes it is necessary to use these
8032 bus control signals in the GPLD when creating
interface signals to external I/O peripherals.
But it is still possible to save power by dynamically
unblocking the bus signals before reading/writing
the external device, then blocking the signals after
the communication is complete.
The user can also block an input signal coming
from pin PC7 to the PLD input bus if desired by
writing to Bit 6 of PMMR2.
Blocking Common Clock, CLKIN. The input
CLKIN (from pin PD1) can be blocked to reduce
current consumption. CLKIN is used as a common
clock input to all OMC flip-flips, it is a general input
to the PLD input bus, and it is used to clock the
APD counter. In PSDsoft Express, the function of
pin PD1 must be specified as “Common Clock Input,
CLKIN” before programming the device with
JTAG to get the CLKIN function.
Bit 4 of PMMR0 can be set to logic ’1’ to block
CLKIN from reaching the PLD input bus, but
CLKIN will still reach the APD counter.
Bit 5 of PMMR0 can be set to logic ’1’ to block
CLKIN from reaching the OMC flip-flops only, but
CLKIN is still available to the PLD input bus and
the APD counter.
See Table 117., page 188 for details.
SRAM Standby Mode (battery backup). The
SRAM on the PSD Module may optionally be
backed up by an external battery (or other DC
source) to make its contents non-volatile. This is
achieved by connecting a battery to pin PC2 on
Port C and selecting the “SRAM Standby” function
for pin PC2 within PSDsoft Express. Automatic
voltage supply cross-over circuitry is built into the
PSD Module to switch SRAM supply to battery as
soon as VDD drops below the voltage level of the
battery. SRAM contents are protected while battery
voltage is greater than 2.0V. Pin PC4 on Port
C can be used as an output to indicate that a battery
switch-over has occurred. This is configured
in PSDsoft Express by selecting the “Standby On
Indicator” option for pin PC4.
PSD Module Reset Conditions
The PSD Module receives a reset signal from the
MCU Module. This reset signal is referred to as the
“RST” input in PSD Module documentation, and it
is active-low when asserted. The character of the
RST signal generated from the MCU Module is described
in SUPERVISORY
FUNCTIONS, page 65.
Upon power-up, and while RST is asserted, the
PSD Module immediately loads its configuration
from non-volatile bits to configure the PLDs and
other items. PLD logic is operational and ready for
use well before RST is de-asserted. The state of
PLD outputs are determined by equations specified
in PSDsoft Express.
The Flash memories are reset to Read Array
mode after any assertion of RST (even if a program
or erase operation is occurring).
Flash memory WRITE operations are automatically
prevented while VDD is ramping up until it rises
above the VLKO voltage threshold at which time
Flash memory WRITE operations are allowed.
Once the uPSD33xx is up and running, any subsequent
reset operation is referred to as a warm reset,
until power is turned off again. Some PSD
Module functions are reset in different ways depending
if the reset condition was caused from a
power-up reset or a warm reset. Table
121., page 194 summarizes how PSD Module
functions are affected by power-up and warm resets,
as well as the affect of PSD Module powerdown
mode (from APD).
The I/O pins of PSD Module Ports A, B, C, and D
do not have weak internal pull-ups.uPSD33xx
194/231
In MCU I/O mode, Latched Address Out mode,
and Peripheral I/O mode, the pins of Ports A, B, C,
and D become standard CMOS inputs during a reset
condition. If no external devices are driving
these pins during reset, then these inputs may
float and draw excessive current. If low power consumption
is critical during reset, then these floating
inputs should be pulled up externally to VDD with a
weak (100KΩ minimum) resistor.
In PLD I/O mode, pins of Ports A, B, C, and D may
also float during reset if no external device is driving
them, and if there is no equation specified for
the DPLD or GPLD to make them an output. In this
case, a weak external pull-up resistor (100KΩ minimum)
should be used on floating pins to avoid excessive
current draw.
The pins on Ports 1, 3, and 4 of the 8032 MCU
module do have weak internal pull-ups and the inputs
will not float, so no external pull-ups are needed.
Table 121. Function Status During Power-Up Reset, Warm Reset, Power-down Mode
Note: 1. VM register Bit 7 (PIO_EN) and Bit 0 (SRAM in 8032 program space) are cleared to zero at power-up and warm reset conditions.
Port Configuration Power-Up Reset Warm Reset APD Power-down Mode
MCU I/O Pins are in input mode Pins are in input mode Pin logic state is
unchanged
PLD I/O
Pin logic is valid after
internal PSD Module
configuration bits are
loaded. Happens long
before RST is de-asserted
Pin logic is valid and is
determined by PLD logic
equations
Pin logic depends on inputs
to PLD (8032 addresses
are blocked from reaching
PLD inputs during powerdown
mode)
Latched Address Out Mode Pins are High Impedance Pins are High Impedance
Pins logic state not defined
since 8032 address signals
are blocked
Peripheral I/O Mode Pins are High Impedance Pins are High Impedance Pins are High Impedance
JTAG ISP and Debug JTAG channel is active and
available
JTAG channel is active and
available
JTAG channel is active and
available
Register Power-Up Reset Warm Reset APD Power-down Mode
PMMR0 and PMMR2 Cleared to 00h Unchanged Unchanged
Output of OMC Flip-flops Cleared to ’0’ Depends on .re and .pr
equations
Depends on .re and .pr
equations
VM Register(1) Initialized with value that
was specified in PSDsoft
Initialized with value that
was specified in PSDsoft Unchanged
All other csiop registers Cleared to 00h Cleared to 00h Unchanged195/231
uPSD33xx
JTAG ISP and JTAG Debug. An IEEE 1149.1
serial JTAG interface is used on uPSD33xx devices
for ISP (In-System Programming) of the PSD
module, and also for debugging firmware on the
MCU Module. IEEE 1149.1 Boundary Scan operations
are not supported in the uPSD33xx.
The main advantage of JTAG ISP is that a blank
uPSD33xx device may be soldered to a circuit
board and programmed with no involvement of the
8032, meaning that no 8032 firmware needs to be
present for ISP. This is good for manufacturing, for
field updates, and for easy code development in
the lab. JTAG-based programmers and debuggers
for uPSD33xx are available from STMicroelectronics
and 3rd party vendors.
ISP is different than IAP (In-Application Programming).
IAP involves the 8032 to program Flash
memory over any interface supported by the 8032
(e.g., UART, SPI, I2C), which is good for remote
updates over a communication channel.
uPSD33xx devices support both ISP and IAP. The
entire PSD Module (Flash memory and PLD) may
be programmed with JTAG ISP, but only the Flash
memories may be programmed using IAP.
JTAG Chaining Inside the Package. JTAG protocol
allows serial “chaining” of more than one device
in a JTAG chain. The uPSD33xx is
assembled with a stacked die process combining
the PSD Module (one die) and the MCU Module
(the other die). These two die are chained together
within the uPSD33xx package. The standard
JTAG interface has four basic signals:
■ TDI - Serial data into device
■ TDO - Serial data out of device
■ TCK - Common clock
■ TMS - Mode Selection
Every device that supports IEEE 1149.1 JTAG
communication contains a Test Access Port (TAP)
controller, which is a small state machine to manage
JTAG protocol and serial streams of commands
and data. Both the PSD Module and the
MCU Module each contain a TAP controller.
Figure 80 illustrates how these die are chained
within a package. JTAG programming/test equipment
will connect externally to the four IEEE
1149.1 JTAG pins on Port C. The TDI pin on the
uPSD33xx package goes directly to the PSD Module
first, then exits the PSD Module through TDO.
TDO of the PSD Module is connected to TDI of the
MCU Module. The serial path is completed when
TDO of the MCU Module exits the uPSD33xx
package through the TDO pin on Port C. The
JTAG signals TCK and TMS are common to both
modules as specified in IEEE 1149.1. When JTAG
devices are chained, typically one devices is in
BYPASS mode while another device is executing
a JTAG operation. For the uPSD33xx, the PSD
Module is in BYPASS mode while debugging the
MCU Module, and the MCU Module is in BYPASS
mode while performing ISP on the PSD Module.
The RESET_IN input pin on the uPSD33xx package
goes to the MCU Module, and this module will
generate the RST reset signal for the PSD Module.
These reset signals are totally independent of
the JTAG TAP controllers, meaning that the JTAG
channel is operational when the modules are held
in reset. It is required to assert RESET_IN during
ISP. STMicroelectronics and 3rd party JTAG ISP
tools will automatically assert a reset signal during
ISP. However, this reset signal must be connected
to RESET_IN as shown in examples in Figure Figure
81., page 196 and Figure 82., page 198.
Figure 80. JTAG Chain in uPSD33xx Package
JTAG TDI
JTAG TMS
JTAG TCK
JTAG TDO
TDI TMS TCK TDO
TDO TMS TCK TDI
PC3 / TSTAT
PC4 / TERR
TSTAT
TERR
OPTIONAL
JTAG TAP
CONTROLLER
JTAG TAP
CONTROLLER
RESET_IN
OPTIONAL
DEBUG
RESET
RST
8032 MCU
MCU MODULE
PSD MODULE
MAIN
FLASH
MEMORY
2ND
FLASH
MEMORY
PLD
uPSD33XX
IEEE 1149.1
AI09184uPSD33xx
196/231
In-System Programming. The ISP function can
use two different configurations of the JTAG interface:
■ 4-pin JTAG: TDI, TDO, TCK, TMS
■ 6-pin JTAG: Signals above plus TSTAT,
TERR
At power-up, the four basic JTAG signals are all inputs,
waiting for a command to appear on the
JTAG bus from programming or test equipment.
When the enabling command is received, TDO becomes
an output and the JTAG channel is fully
functional. The same command that enables the
JTAG channel may optionally enable the two additional
signals, TSTAT and TERR.
4-pin JTAG ISP (default). The four basic JTAG
pins on Port C are enabled for JTAG operation at
all times. These pins may not be used for other I/
O functions. There is no action needed in PSDsoft
Express to configure a device to use 4-pin JTAG,
as this is the default condition. No 8032 firmware
is needed to use 4-pin ISP because all ISP functions
are controlled from the external JTAG program/test
equipment. Figure 81 shows
recommended connections on a circuit board to a
JTAG program/test tool using 4-pin JTAG. It is required
to connect the RST output signal from the
JTAG program/test equipment to the RESET_IN
input on the uPSD33xx. The RST signal is driven
by the equipment with an Open Drain driver, allowing
other sources (like a push button) to drive
RESET_IN without conflict.
Note: The recommended pull-up resistors and decoupling
capacitor are illustrated in Figure 81.
Figure 81. Recommended 4-pin JTAG Connections
Note: 1. For 5V uPSD33xx devices, pull-up resistors and VCC pin on the JTAG connector should be connected to 5V system VDD.
2. For 3.3V uPSD33xx devices, pull-up resistors and VCC pin on the JTAG connector should be connected to 3.3V system VCC.
3. This signal is driven by an Open-Drain output in the JTAG equipment, allowing more than one source to activate RESETIN.
TMS - PC0
TCK - PC1
SRAM STBY or I/O - PC2
GENERAL I/O - PC3
GENERAL I/O - PC4
TDI - PC5
TDO - PC6
GENERAL I/O - PC7
JTAG
CONN.
100k
typical
TMS
TCK
TDI
TDO
GENERAL I/O
SIGNALS
GND
VCC
(1,2)
RST(3)
uPSD33XX
0.01
µF
CIRCUIT
BOARD
JTAG
Programming
or Test
Equipment
Connects Here
10k
PUSH BUTTON
or ANY OTHER
RESET SOURCE
DEBUG
OPTIONAL
TEST POINT
100k
RESETIN
AI09185197/231
uPSD33xx
6-pin JTAG ISP (optional). The optional signals
TSTAT and TERR are programming status flags
that can reduce programming time by as much as
30% compared to 4-pin JTAG because this status
information does not have to be scanned out of the
device serially. TSTAT and TERR must be used
as a pair for 6-pin JTAG operation.
– TSTAT (pin PC3) indicates when
programming of a single Flash location is
complete. Logic 1 = Ready, Logic 0 = busy.
– TERR (pin PC4) indicates if there was a Flash
programming error. Logic 1 = no error,
Logic 0 = error.
The pin functions for PC3 and PC4 must be selected
as “Dedicated JTAG - TSTAT” and “Dedicated
JTAG - TERR” in PSDsoft Express to enable 6-pin
JTAG ISP.
No 8032 firmware is needed to use 6-pin ISP because
all ISP functions are controlled from the external
JTAG program/test equipment.
TSTAT and TERR are functional only when JTAG
ISP operations are occurring, which means they
are non-functional during JTAG debugging of the
8032 on the MCU Module.
Programming times vary depending on the number
of locations to be programmed and the JTAG
programming equipment, but typical JTAG ISP
programming times are 10 to 25 seconds using 6-
pin JTAG. The signals TSTAT and TERR are not
included in the IEEE 1149.1 specification.
Figure 82., page 198 shows recommended connections
on a circuit board to a JTAG program/test
tool using 6-pin JTAG. It is required to connect the
RST output signal from the JTAG program/test
equipment to the RESET_IN input on the
uPSD33xx. The RST signal is driven by the equipment
with an Open Drain driver, allowing other
sources (like a push button) to drive RESET_IN
without conflict.
Note: The recommended pull-up resistors and decoupling
capacitor are illustrated in Figure 82.uPSD33xx
198/231
Figure 82. Recommended 6-pin JTAG Connections
Note: 1. For 5V uPSD33xx devices, pull-up resistors and VCC pin on the JTAG connector should be connected to 5V system VDD.
2. For 3.3V uPSD33xx devices, pull-up resistors and VCC pin on the JTAG connector should be connected to 3.3V system VCC.
3. This signal is driven by an Open-Drain output in the JTAG equipment, allowing more than one source to activate RESET_IN.
TMS - PC0
TCK - PC1
SRAM STBY or I/O - PC2
TSTAT - PC3
TERR - PC4
TDI - PC5
TDO - PC6
GENERAL I/O - PC7
JTAG
CONN.
100k typical
TMS
TCK
TDI
TERR
TSTAT
TDO
GENERAL I/O
SIGNALS
GND
VCC
(1,2)
RST(3)
uPSD33XX
0.01
µF
CIRCUIT
BOARD
JTAG
Programming
or Test
Equipment
Connects Here
10k
PUSH BUTTON
or ANY OTHER
RESET SOURCE
DEBUG
OPTIONAL
TEST POINT
100k
RESETIN
AI09186199/231
uPSD33xx
Recommended JTAG Connector. There is no
industry standard JTAG connector. STMicroelectronics
recommends a specific JTAG connector
and pinout for uPSD3xxx so programming and debug
equipment will easily connect to the circuit
board. The user does not have to use this connector
if there is a different connection scheme.
The recommended connector scheme can accept
a standard 14-pin ribbon cable connector (2 rows
of 7 pins on 0.1” centers, 0.025” square posts,
standard keying) as shown in Figure 83. See the
STMicroelectronics “FlashLINK, FL-101 User
Manual” for more information.
Figure 83. Recommended JTAG Connector
Chaining uPSD33xx Devices. It is possible to
chain a uPSD33xx device with other uPSD33xx
devices on a circuit board, and also chain with
IEEE 1149.1 compliant devices from other manufacturers.
Figure 84., page 200 shows a chaining
example. The TDO of one device connects to the
TDI of the next device, and so on. Only one device
is performing JTAG operations at any given time
while the other two devices are in BYPASS mode.
Configuration for JTAG chaining can be made in
PSDsoft Express by choosing “More than one device”
when prompted about chaining devices. Notice
in Figure 84., page 200 that the uPSD33xx
devices are chained externally, but also be aware
that the two die within each uPSD33xx device are
chained internally. This internal chaining of die is
transparent to the user and is taken care of by PSDsoft
Express and 3rd party JTAG tool software.
The example in Figure 84., page 200 also shows
how to use 6-pin JTAG when chaining devices.
The signals TSTAT and TERR are configured as
open-drain type signals from PSDsoft Express.
This facilitates a wired-OR connection of TSTAT
signals from multiple uPSD33xx devices and also
a wired-OR connection of TERR signals from
those same multiple devices. PSDsoft Express
puts TSTAT and TERR signals into open-drain
mode by default, requiring external pull-up resistors.
Click on 'Properties' in the JTAG-ISP window
of PSDsoft Express to change to standard CMOS
push-pull outputs if desired, but wired-OR logic is
not possible in CMOS output mode.
TDO
TCK
TMS
VCC
TDI
GND
JEN
TERR
GND
GND
RST
TSTAT
CNTL
TRST
14
12
10
13
11
9
8 7
6 5
4 3
2 1
KEY
WAY
VIEW: Looking into face of shrouded
male connector, with 0.025"
posts on 0.1" centers.
Connector reference:
Molex 70247-1401
This connector accepts a 14-pin
ribbon cable such as:
• Samtec:
HCSD-07-D-06.00-01-S-N
• Digikey:
M3CCK-14065-ND
AI09187uPSD33xx
200/231
Figure 84. Example of Chaining uPSD33xx Devices
Device 1
µPSD33XX
uPSD33XX
TMS
TCK
TDI
TDO
IEEE 1149.1
Compliant
Device
Device 2
Device N
System
Reset
Circuitry
TMS
TCK
TDI
TDO
TSTAT
TERR
CIRCUIT BOARD
JTAG
CONN.
VCC
TMS
TCK
TDI
TSTAT
TERR
TDO
RST
GND
100K 100K
100K
100K
100K
10K
100K
JTAG
Programming
or Test
Equipment
Connects Here
Optional
Optional
TMS
TCK
TDI
TDO
TSTAT
TERR
AI09188201/231
uPSD33xx
Debugging the 8032 MCU Module. The 8032
on the MCU module may be debugged in-circuit
using the same four basic JTAG signals as used
for JTAG ISP (TDI, TDO, TCK, TMS). The signals
TSTAT and TERR are not needed for debugging,
and they will not create a problem if they exist on
the circuit board while debugging. The same connector
specified in Figure 83., page 199 can be
used for ISP or for 8032 debugging. There are 3rd
party suppliers of uPSD33xx JTAG debugging
equipment (check www.st.com/psm). These are
small pods which connect to a PC (or notebook
computer) using a USB interface, and they are
driven by an 8032 Integrated Development Environment
(IDE) running on the PC.
Standard debugging features are provided
through this JTAG interface such as single-step,
breakpoints, trace, memory dump and fill, and others.
There is also a dedicated Debug pin (shown
in Figure 80., page 195) which can be configured
as an output to trigger external devices upon a
programmable internal event (e.g., breakpoint
match), or the pin can be configured as an input so
an external device can initiate an internal debug
event (e.g., break execution). The Debug pin function
is configured by the 8032 IDE debug software
tool. See DEBUG UNIT, page 39 for more details.
The Debug signal should always be pulled up externally
with a weak pull-up (100K minimum) to
VCC even if nothing is connected to it, as shown in
Figure 81., page 196 and Figure 82., page 198.
JTAG Security Setting. A programmable security
bit in the PSD Module protects its contents from
unauthorized viewing and copying. The security
bit is set by clicking on the “Additional PSD Settings”
box in the main flow diagram of PSDsoft Express,
then choosing to set the security bit. Once
a file with this setting is programmed into a
uPSD33xx using JTAG ISP, any further attempts
to communicate with the uPSD33xx using JTAG
will be limited. Once secured, the only JTAG operation
allowed is a full-chip erase. No reading or
modifying Flash memory or PLD logic is allowed.
Debugging operations to the MCU Module are
also not allowed. The only way to defeat the security
bit is to perform a JTAG ISP full-chip erase operation,
after which the device is blank and may be
used again. The 8032 on the MCU Module will always
have access to PSM Module memory contents
through the 8-bit 8032 data bus connecting
the two die, even while the security bit is set.
Initial Delivery State. When delivered from STMicroelectronics,
uPSD33xx devices are erased,
meaning all Flash memory and PLD configuration
bits are logic '1.' Firmware and PLD logic configuration
must be programmed at least the first time
using JTAG ISP. Subsequent programming of
Flash memory may be performed using JTAG ISP,
JTAG debugging, or the 8032 may run firmware to
program Flash memory (IAP).uPSD33xx
202/231
AC/DC PARAMETERS
These tables describe the AD and DC parameters
of the uPSD33xx Devices:
■ DC Electrical Specification
■ AC Timing Specification
■ PLD Timing
– Combinatorial Timing
– Synchronous Clock Mode
– Asynchronous Clock Mode
– Input Macrocell Timing
■ MCU Module Timing
– READ Timing
– WRITE Timing
– Power-down and RESET Timing
The following are issues concerning the parameters
presented:
– In the DC specification the supply current is
given for different modes of operation.
– The AC power component gives the PLD,
Flash memory, and SRAM mA/MHz
specification. Figure 85 and Figure 86 show
the PLD mA/MHz as a function of the number
of Product Terms (PT) used.
– In the PLD timing parameters, add the
required delay when Turbo Bit is '0.'
Figure 85. PLD ICC /Frequency Consumption (5V range)
Figure 86. PLD ICC /Frequency Consumption (3V range)
0
10
20
30
40
60
70
80
90
100
110
VCC = 5V
50
0 10 15 5 20 25
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
ICC – (mA)
TURBO ON (100%)
TURBO ON (25%)
TURBO OFF
TURBO OFF
PT 100%
PT 25%
AI02894
0
10
20
30
40
50
60
VCC = 3V
0 10 15 5 20 25
ICC – (mA)
TURBO ON (100%)
TURBO ON (25%)
TURBO OFF
TURBO OFF
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
PT 100%
PT 25%
AI03100203/231
uPSD33xx
Table 122. PSD Module Example, Typ. Power Calculation at VCC = 5.0V (Turbo Mode Off)
Conditions
MCU Clock Frequency = 12MHz
Highest Composite PLD input frequency
(Freq PLD) = 8MHz
MCU ALE frequency (Freq ALE) = 2MHz
% Flash memory Access = 80%
% SRAM access = 15%
% I/O access = 5% (no additional power above base)
Operational Modes
% Normal = 40%
% Power-down Mode = 60%
Number of product terms used
(from fitter report) = 45 PT
% of total product terms = 45/182 = 24.7%
Turbo Mode = Off
Calculation (using typical values)
ICC total = ICC(MCUactive) x %MCUactive + ICC(PSDactive) x %PSDactive + IPD(pwrdown) x %pwrdown
ICC(MCUactive) = 20mA
IPD(pwrdown) = 250uA
ICC(PSDactive) = ICC(ac) + ICC(dc)
= %flash x 2.5mA/MHz x Freq ALE
+ %SRAM x 1.5mA/MHz x Freq ALE
+ % PLD x (from graph using Freq PLD)
= 0.8 x 2.5mA/MHz x 2MHz + 0.15 x 1.5mA/MHz x 2MHz + 24mA
= (4 + 0.45 + 24) mA
= 28.45mA
ICC total = 20mA x 40% + 28.45mA x 40% + 250uA x 60%
= 8mA + 11.38mA + 150uA
= 19.53mA
This is the operating power with no Flash memory Erase or Program cycles in progress. Calculation is based on all I/O
pins being disconnected and IOUT = 0mA.uPSD33xx
204/231
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings” table may cause permanent
damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not implied.
Exposure to Absolute Maximum Rating conditions
for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 123. Absolute Maximum Ratings
Note: 1. IPC/JEDEC J-STD-020A
2. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 Ω, R2=500 Ω)
DC AND AC PARAMETERS
This section summarizes the operating and measurement
conditions, and the DC and AC characteristics
of the device. The parameters in the DC
and AC Characteristic tables that follow are derived
from tests performed under the Measurement
Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parameters.
Table 124. Operating Conditions (5V Devices)
Table 125. Operating Conditions (3.3V Devices)
Symbol Parameter Min. Max. Unit
TSTG Storage Temperature –65 125 °C
TLEAD Lead Temperature during Soldering (20 seconds max.)(1) 235 °C
VIO Input and Output Voltage (Q = VOH or Hi-Z) –0.5 6.5 V
VCC Supply Voltage –0.5 6.5 V
VPP Device Programmer Supply Voltage –0.5 14.0 V
VESD Electrostatic Discharge Voltage (Human Body Model)(2) –2000 2000 V
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 4.5 5.5 V
TA
Ambient Operating Temperature (industrial) –40 85 °C
Ambient Operating Temperature (commercial) 0 70 °C
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 3.0 3.6 V
TA
Ambient Operating Temperature (industrial) –40 85 °C
Ambient Operating Temperature (commercial) 0 70 °C205/231
uPSD33xx
Table 126. AC Signal Letters for Timing
Note: Example: tAVLX = Time from Address Valid to ALE Invalid.
Table 127. AC Signal Behavior Symbols for
Timing
Note: Example: tAVLX = Time from Address Valid to ALE Invalid.
Figure 87. Switching Waveforms – Key
A Address
C Clock
D Input Data
I Instruction
L ALE
N RESET Input or Output
P PSEN signal
Q Output Data
R RD signal
W WR signal
B VSTBY Output
M Output Macrocell
t Time
L Logic Level Low or ALE
H Logic Level High
V Valid
X No Longer a Valid Logic Level
Z Float
PW Pulse Width
WAVEFORMS INPUTS OUTPUTS
STEADY INPUT
MAY CHANGE FROM
HI TO LO
MAY CHANGE FROM
LO TO HI
DON'T CARE
OUTPUTS ONLY
STEADY OUTPUT
WILL BE CHANGING
FROM HI TO LO
WILL BE CHANGING
LO TO HI
CHANGING, STATE
UNKNOWN
CENTER LINE IS
TRI-STATE
AI03102uPSD33xx
206/231
Table 128. Major Parameters
Parameter Test Conditions/Comments 5.0V Value 3.3V Value Unit
Operating Voltage – 4.5 to 5.5 (PSD);
3.0 to 3.6 (MCU)
3.0 to 3.6
(PSD and MCU) V
Operating Temperature – –40 to 85 –40 to 85 °C
MCU Frequency 8MHz (min) for I2C 1 Min, 40 Max 1 Min, 40 Max MHz
Active Current, Typical
(20% of PLD used; 25°C
operation)
40MHz Crystal, Turbo 50 40 mA
40MHz Crystal, Non-Turbo 48 38 mA
8MHz Crystal, Turbo 21 18 mA
8MHz Crystal, Non-Turbo 10 8 mA
Idle Current, Typical
(20% of PLD used; 25°C
operation)
40MHz Crystal divided by 2048
internally.
All interfaces are disabled.
16 11 mA
Standby Current, Typical Power-down Mode
needs reset to exit. 140 120 µA
SRAM Backup Current, Typical If external battery is attached. 0.5 0.5 µA
I/O Sink/Source Current,
Ports A, B, C, and D
VOL = 0.45V (max);
VOH = 2.4V (min)
IOL = 8 (max);
IOH = –2 (min)
IOL = 4 (max);
IOH = –1 (min) mA
I/O Sink/Source Current,
Port 4
VOL = 0.6V (max);
VOH = 2.4V (min)
IOL = 10 (max);
IOH = –10 (min)
IOL = 10 (max);
IOH = –10 (min) mA
PLD Macrocells For registered or
combinatorial logic 16 16 –
PLD Inputs Inputs from pins, feedback,
or MCU addresses 69 69 –
PLD Outputs Output to pins or
internal feedback 18 18 –
PLD Propagation Delay, Typical,
Turbo Mode PLD input to output 15 22 ns207/231
uPSD33xx
Table 129. Preliminary MCU Module DC Characteristics
Note: 1. Power supply (VCC) is always 3.0 to 3.6V for the MCU Module. VDD for the PSD Module may be 3V or 5V.
2. IPD (Power-down Mode) is measured with: XTAL1 = VSS; XTAL2 = NC; RESET = VCC; Port 0 = VCC; all other pins are disconnected.
3. ICC-CPU (Active Mode) is measured with: XTAL1 driven with tCLCH, tCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC – 0.5V, XTAL2 = NC;
RESET = VSS; Port 0 = VCC; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (approximately
1mA).
4. ICC-CPU (Idle Mode) is measured with: XTAL1 driven with tCLCH, tCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC – 0.5V, XTAL2 = NC;
RESET = VCC; Port 0 = VCC; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (approximately
1mA). All IP clocks are disabled.
5. I/O current = 0mA, all I/O pins are disconnected.
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VCC Supply Voltage(1) 3.0 3.6 V
VIH
High Level Input Voltage
(Ports 0, 1, 2, 3, 4, XTAL1,
RESET)
5V Tolerant - max voltage 5.5V
3.0V < VCC < 3.6V 0.7VCC 5.5 V
VIL
Low Level Input Voltage
(Ports 0, 1, 2, 3, 4, XTAL1,
RESET)
3.0V < VCC < 3.6V VSS – 0.5 0.3VCC V
VOL1 Output Low Voltage (Port 4)
IOL = 10mA 0.6 V
V
VOL2 Output Low Voltage
(Other Ports)
IOL =5mA 0.6 V
V
VOH1 Output High Voltage
(Ports 4 push-pull)
IOH = –10mA 2.4 V
V
VOH2 Output High Voltage
(Port 0 push-pull)
IOH = –5mA 2.4 V
V
VOH3 Output High Voltage
(Other Ports Bi-directional mode)
IOH = –20µA 2.4 V
V
VOP XTAL Open Bias Voltage
(XTAL1, XTAL2) IOL = 3.2mA 1.0 2.0 V
IRST RESET Pin Pull-up Current
(RESET) VIN = VSS –10 –55 uA
IFR
XTAL Feedback Resistor Current
(XTAL1) XTAL1 = VCC; XTAL2 = VSS –20 50 uA
IIHL1 Input High Leakage Current
(Port 0) VSS < VIN < 5.5V –10 10 uA
IIHL2 Input High Leakage Current
(Port 1, 2, 3, 4) VIH = 2.3V –10 10 uA
IILL Input Low Leakage Current
(Port 1, 2, 3, 4) VIL < 0.5V –10 10 uA
IPD
(Note 2) Power-down Mode VCC = 3.6V 65 95 uA
ICC-CPU
(Note
3,4,5)
Active - 12MHz
VCC = 3.6V
14 20 mA
Idle - 12MHz 10 12 mA
Active - 24MHz
VCC = 3.6V
19 30 mA
Idle - 24MHz 13 17 mA
Active - 40MHz
VCC = 3.6V
26 40 mA
Idle - 40MHz 17 22 mAuPSD33xx
208/231
Table 130. PSD Module DC Characteristics (with 5V VDD)
Note: 1. Internal Power-down mode is active.
2. PLD is in non-Turbo mode, and none of the inputs are switching.
3. Please see Figure 85., page 202 for the PLD current calculation.
4. IOUT = 0mA
Symbol Parameter
Test Condition
(in addition to those in
Table 129., page 207)
Min. Typ. Max. Unit
VIH Input High Voltage 4.5V < VDD < 5.5V 2 VDD +0.5 V
VIL Input Low Voltage 4.5V < VDD < 5.5V –0.5 0.8 V
VLKO
VDD (min) for Flash Erase and
Program 2.5 4.2 V
VOL Output Low Voltage
IOL = 20uA, VDD = 4.5V 0.01 0.1 V
IOL = 8mA, VDD = 4.5V 0.25 0.45 V
VOH Output High Voltage Except
VSTBY On
IOH = –20uA, VDD = 4.5V 4.4 4.49 V
IOH = –2mA, VDD = 4.5V 2.4 3.9 V
VOH1 Output High Voltage VSTBY On IOH1 = 1uA VSTBY – 0.8 V
VSTBY SRAM Stand-by Voltage 2.0 VDD V
ISTBY SRAM Stand-by Current VDD = 0V 0.5 1 uA
IIDLE Idle Current (VSTBY input) VDD > VSTBY –0.1 0.1 uA
VDF SRAM Data Retention Voltage Only on VSTBY 2 VDD – 0.2 V
ISB Stand-by Supply Current
for Power-down Mode
CSI > VDD – 0.3V
(Notes 1,2)
120 250 uA
ILI Input Leakage Current VSS < VIN < VDD –1 ±0.1 1 uA
ILO Output Leakage Current 0.45 < VOUT < VDD –10 ±5 10 uA
ICC (DC)
(Note 4)
Operating
Supply
Current
PLD Only
PLD_TURBO = Off,
f = 0MHz (Note 4) 0 uA/PT
PLD_TURBO = On,
f = 0MHz 400 700 uA/PT
Flash memory
During Flash memory
WRITE/Erase Only 15 30 mA
Read only, f = 0MHz 0 0 mA
SRAM f = 0MHz 0 0 mA
ICC (AC)
(Note 4)
PLD AC Adder Note 3
Flash memory AC Adder 1.5 2.5 mA/
MHz
SRAM AC Adder 1.5 3.0 mA/
MHz209/231
uPSD33xx
Table 131. PSD Module DC Characteristics (with 3.3V VDD)
Note: 1. Internal PD is active.
2. PLD is in non-Turbo mode, and none of the inputs are switching.
3. Please see Figure 86., page 202 for the PLD current calculation.
4. IOUT = 0mA
Symbol Parameter
Test Condition
(in addition to those in
Table 129., page 207)
Min. Typ. Max. Unit
VIH High Level Input Voltage 3.0V < VDD < 3.6V 0.7VDD VDD +0.5 V
VIL Low Level Input Voltage 3.0V < VDD < 3.6V –0.5 0.8 V
VLKO
VDD (min) for Flash Erase and
Program 1.5 2.2 V
VOL Output Low Voltage
IOL = 20uA, VDD = 3.0V 0.01 0.1 V
IOL = 4mA, VDD = 3.0V 0.15 0.45 V
VOH Output High Voltage Except
VSTBY On
IOH = –20uA, VDD = 3.0V 2.9 2.99 V
IOH = –1mA, VDD = 3.0V 2.7 2.8 V
VOH1 Output High Voltage VSTBY On IOH1 = 1uA VSTBY – 0.8 V
VSTBY SRAM Stand-by Voltage 2.0 VDD V
ISTBY SRAM Stand-by Current VDD = 0V 0.5 1 uA
IIDLE Idle Current (VSTBY input) VDD > VSTBY –0.1 0.1 uA
VDF SRAM Data Retention Voltage Only on VSTBY 2 VDD – 0.2 V
ISB Stand-by Supply Current
for Power-down Mode
CSI > VDD – 0.3V
(Notes 1,2) 50 100 uA
ILI Input Leakage Current VSS < VIN < VDD –1 ±0.1 1 uA
ILO Output Leakage Current 0.45 < VIN < VDD –10 ±5 10 uA
ICC (DC)
(Note 4)
Operating
Supply
Current
PLD Only
PLD_TURBO = Off,
f = 0MHz (Note 2) 0 uA/PT
PLD_TURBO = On,
f = 0MHz 200 400 uA/PT
Flash memory
During Flash memory
WRITE/Erase Only 10 25 mA
Read only, f = 0MHz 0 0 mA
SRAM f = 0MHz 0 0 mA
ICC (AC)
(Note 4)
PLD AC Adder Note 3
Flash memory AC Adder 1.0 1.5 mA/
MHz
SRAM AC Adder 0.8 1.5 mA/
MHzuPSD33xx
210/231
Figure 88. External PSEN/READ Cycle (80-pin Device Only)
Table 132. External PSEN or READ Cycle AC Characteristics (3V or 5V Device)
Note: 1. BUSCON Register is configured for 4 PFQCLK.
2. Refer to Table 133 for “n” and “m” values.
Table 133. n, m, and x, y Values
Symbol Parameter
40MHz Oscillator(1) Variable Oscillator
1/tCLCL = 8 to 40MHz Unit
Min Max Min Max
tLHLL ALE pulse width 17 tCLCL – 8 ns
tAVLL Address setup to ALE 13 tCLCL – 12 ns
tLLAX Address hold after ALE 7.5 0.5tCLCL – 5 ns
tLLPL ALE to PSEN or RD 7.5 0.5tCLCL – 5 ns
tPLPH PSEN or RD pulse width(2) 40 ntCLCL – 10 ns
tPXIX Input instruction/data hold after
PSEN or RD 2 2 ns
tPHIZ Input instruction/data float after
PSEN or RD 10.5 0.5tCLCL – 2 ns
tPXAV Address hold after PSEN or RD 7.5 0.5tCLCL – 5 ns
tAVIV Address to valid instruction/data in(2) 70 mtCLCL – 5 ns
tAZPL Address float to PSEN or RD –2 –2 ns
# of PFQCLK in
BUSCON Reg.
PSEN (code) Cycle READ Cycle WRITE Cycle
nmnmx y
3 12- - - -
4 232321
5 343432
6 454543
7 - - 5654
tAVLL tPLPH
tPXIZ
tAVIV211/231
uPSD33xx
Figure 89. External WRITE Cycle (80-pin Device Only)
Table 134. External WRITE Cycle AC Characteristics (3V or 5V Device)
Note: 1. BUSCON Register is configured for 4 PFQCLK.
2. Refer to Table 135, page 151 for “n” and “m” values.
Table 135. External Clock Drive
Symbol Parameter
40MHz Oscillator(1) Variable Oscillator
1/tCLCL = 8 to 40MHz Unit
Min Max Min Max
tLHLL ALE pulse width 17 tCLCL – 8 ns
tAVLL Address Setup to ALE 13 tCLCL – 12 ns
tLLAX Address hold after ALE 7.5 0.5tCLCL – 5 ns
tWLWH WR pulse width(2) 40 xtCLCL – 10 ns
tLLWL ALE to WR 7.5 0.5tCLCL – 5 ns
tAVWL Address valid to WR 27.5 1.5tCLCL – 10 ns
tWHLH WR High to ALE High 6.5 14.5 0.5tCLCL – 6 0.5tCLCL + 2 ns
tQVWH Data setup before WR(y) 20 ytCLCL – 5 ns
tWHQX Data hold after WR 6.5 14.5 0.5tCLCL – 6 0.5tCLCL + 2 ns
Symbol Parameter(1)
40MHz Oscillator Variable Oscillator
1/tCLCL = 8 to 40MHz Unit
Min Max Min Max
tCLCL Oscillator period 25 125 ns
tCHCX High time 10 tCLCL – tCLCX ns
tCLCX Low time 10 tCLCL – tCLCX ns
tCLCH Rise time 10 ns
tCHCL Fall time 10 ns
MCU
A8 - A11
MCU
AD0 - AD7
ALE
WR
PSEN
A8-A11 A8-A11
tLLWL tWLWH
tAVLL
tLHLL
tQVWH
A0-A7 DATA OUT A0-A7 INSTR IN
tLLAX
tAVWL
tWHQX
tWHLH
AI07877uPSD33xx
212/231
Table 136. A/D Analog Specification
Note: 1. fIN 2kHz, ACLK = 8MHz, AVREF = VCC = 3.3V
2. AVREF = VCC in 52-pin package.
Symbol Parameter Test Conditions(1) Min. Typ. Max. Unit
IDD
Normal Input = AVREF 4.0 mA
Power-down 40 uA
AVIN Analog Input Voltage GND AVREF V
AVREF(2) Analog Reference Voltage 3.6 V
Accuracy Resolution 10 bits
INL Integral Nonlinearity Input = 0 to AVREF (V)
FOSC ≤ 32MHz ±2 LSB
DNL Differential Nonlinearity Input = 0 to AVREF (V)
FOSC ≤ 32MHz ±2 LSB
SNR Signal to Noise Ratio fSAMPLE = 500ksps 50 54 dB
SNDR Signal to Noise Distortion Ratio 48 52 dB
ACLK ADC Clock 2 8 16 MHz
tC Conversion Time 8MHz 1 4 8 µs
tCAL Power-up Time Calibration Time 16 ms
fIN Analog Input Frequency 60 kHz
THD Total Harmonic Distortion 50 54 dB213/231
uPSD33xx
Figure 90. Input to Output Disable / Enable
Table 137. CPLD Combinatorial Timing (5V PSD Module)
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount
2. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial
output (80-pin package only)
Table 138. CPLD Combinatorial Timing (3V PSD Module)
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount
2. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial
output (80-pin package only)
Symbol Parameter Conditions Min Max PT
Aloc
Turbo
Off
Slew
rate(1) Unit
tPD(2) CPLD Input Pin/Feedback to
CPLD Combinatorial Output 20 + 2 + 10 – 2 ns
tEA CPLD Input to CPLD Output
Enable 21 + 10 – 2 ns
tER CPLD Input to CPLD Output
Disable 21 + 10 – 2 ns
tARP CPLD Register Clear or Preset
Delay 21 + 10 – 2 ns
tARPW CPLD Register Clear or Preset
Pulse Width 10 + 10 ns
tARD CPLD Array Delay Any
macrocell 11 + 2 ns
Symbol Parameter Conditions Min Max PT
Aloc
Turbo
Off
Slew
rate(1) Unit
tPD(2) CPLD Input Pin/Feedback to
CPLD Combinatorial Output 35 + 4 + 20 – 6 ns
tEA CPLD Input to CPLD Output
Enable 38 + 20 – 6 ns
tER CPLD Input to CPLD Output
Disable 38 + 20 – 6 ns
tARP CPLD Register Clear or
Preset Delay 35 + 20 – 6 ns
tARPW CPLD Register Clear or
Preset Pulse Width 18 + 20 ns
tARD CPLD Array Delay Any
macrocell 20 + 4 ns
tER tEA
INPUT
INPUT TO
OUTPUT
ENABLE/DISABLE
AI02863uPSD33xx
214/231
Figure 91. Synchronous Clock Mode Timing – PLD
Table 139. CPLD Macrocell Synchronous Clock Mode Timing (5V PSD Module)
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount.
2. CLKIN (PD1) tCLCL = tCH + tCL.105
3.
Symbol Parameter Conditions Min Max PT
Aloc
Turbo
Off
Slew
rate(1) Unit
fMAX
Maximum Frequency
External Feedback 1/(tS+tCO) 40.0 MHz
Maximum Frequency
Internal Feedback (fCNT) 1/(tS+tCO–10) 66.6 MHz
Maximum Frequency
Pipelined Data 1/(tCH+tCL) 83.3 MHz
tS Input Setup Time 12 + 2 + 10 ns
tH Input Hold Time 0 ns
tCH Clock High Time Clock Input 6 ns
tCL Clock Low Time Clock Input 6 ns
tCO Clock to Output Delay Clock Input 13 – 2 ns
tARD CPLD Array Delay Any macrocell 11 + 2 ns
tMIN Minimum Clock Period(2) tCH+tCL 12 ns
tCH tCL
tCO
tS tH
CLKIN
INPUT
REGISTERED
OUTPUT
AI02860215/231
uPSD33xx
Table 140. CPLD Macrocell Synchronous Clock Mode Timing (3V PSD Module)
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount.
2. CLKIN (PD1) tCLCL = tCH + tCL.
Symbol Parameter Conditions Min Max PT
Aloc
Turbo
Off
Slew
rate(1) Unit
fMAX
Maximum Frequency
External Feedback 1/(tS+tCO) 23.2 MHz
Maximum Frequency
Internal Feedback (fCNT) 1/(tS+tCO–10) 30.3 MHz
Maximum Frequency
Pipelined Data 1/(tCH+tCL) 40.0 MHz
tS Input Setup Time 20 + 4 + 15 ns
tH Input Hold Time 0 ns
tCH Clock High Time Clock Input 15 ns
tCL Clock Low Time Clock Input 10 ns
tCO Clock to Output Delay Clock Input 23 – 6 ns
tARD CPLD Array Delay Any macrocell 20 + 4 ns
tMIN Minimum Clock Period(2) tCH+tCL 25 nsuPSD33xx
216/231
Figure 92. Asynchronous RESET / Preset
Figure 93. Asynchronous Clock Mode Timing (Product Term Clock)
Table 141. CPLD Macrocell Asynchronous Clock Mode Timing (5V PSD Module)
Symbol Parameter Conditions Min Max PT
Aloc
Turbo
Off
Slew
Rate Unit
fMAXA
Maximum Frequency
External Feedback 1/(tSA+tCOA) 38.4 MHz
Maximum Frequency
Internal Feedback (fCNTA) 1/(tSA+tCOA–10) 62.5 MHz
Maximum Frequency
Pipelined Data 1/(tCHA+tCLA) 71.4 MHz
tSA Input Setup Time 7 + 2 + 10 ns
tHA Input Hold Time 8 ns
tCHA Clock Input High Time 9 + 10 ns
tCLA Clock Input Low Time 9 + 10 ns
tCOA Clock to Output Delay 21 + 10 – 2 ns
tARDA CPLD Array Delay Any macrocell 11 + 2 ns
tMINA Minimum Clock Period 1/fCNTA 16 ns
tARP
REGISTER
OUTPUT
tARPW
RESET/PRESET
INPUT
AI02864
tCHA tCLA
tCOA
tSA tHA
CLOCK
INPUT
REGISTERED
OUTPUT
AI02859217/231
uPSD33xx
Table 142. CPLD Macrocell Asynchronous Clock Mode Timing (3V PSD Module)
Symbol Parameter Conditions Min Max PT
Aloc
Turbo
Off
Slew
Rate Unit
fMAXA
Maximum Frequency
External Feedback 1/(tSA+tCOA) 21.7 MHz
Maximum Frequency
Internal Feedback (fCNTA) 1/(tSA+tCOA–10) 27.8 MHz
Maximum Frequency
Pipelined Data 1/(tCHA+tCLA) 33.3 MHz
tSA Input Setup Time 10 + 4 + 15 ns
tHA Input Hold Time 12 ns
tCHA Clock High Time 17 + 15 ns
tCLA Clock Low Time 13 + 15 ns
tCOA Clock to Output Delay 31 + 15 – 6 ns
tARD CPLD Array Delay Any macrocell 20 + 4 ns
tMINA Minimum Clock Period 1/fCNTA 36 nsuPSD33xx
218/231
Figure 94. Input Macrocell Timing (Product Term Clock)
Table 143. Input Macrocell Timing (5V PSD Module)
Note: 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to tAVLX and tLXAX.
Table 144. Input Macrocell Timing (3V PSD Module)
Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX.
Symbol Parameter Conditions Min Max PT
Aloc
Turbo
Off Unit
tIS Input Setup Time (Note 1) 0 ns
tIH Input Hold Time (Note 1) 15 + 10 ns
tINH NIB Input High Time (Note 1) 9 ns
tINL NIB Input Low Time (Note 1) 9 ns
tINO NIB Input to Combinatorial Delay (Note 1) 34 + 2 + 10 ns
Symbol Parameter Conditions Min Max PT
Aloc
Turbo
Off Unit
tIS Input Setup Time (Note 1) 0 ns
tIH Input Hold Time (Note 1) 25 + 15 ns
tINH NIB Input High Time (Note 1) 12 ns
tINL NIB Input Low Time (Note 1) 12 ns
tINO NIB Input to Combinatorial Delay (Note 1) 43 + 4 + 15 ns
tINH tINL
tINO
tIH tIS
PT CLOCK
INPUT
OUTPUT
AI03101219/231
uPSD33xx
Table 145. Program, WRITE and Erase Times (5V, 3V PSD Modules)
Note: 1. Programmed to all zero before erase.
2. Typical after 100K program/erase cycle is 5 seconds.
3. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading.
Symbol Parameter Min. Typ. Max. Unit
Flash Program 8.5 s
Flash Bulk Erase(1) (pre-programmed) 3(2) 10 s
Flash Bulk Erase (not pre-programmed) 5 s
tWHQV3 Sector Erase (pre-programmed) 1 10 s
tWHQV2 Sector Erase (not pre-programmed) 2.2 s
tWHQV1 Byte Program 14 150 µs
Program/Erase Cycles (per Sector) 100,000 cycles
PLD Program/Erase Cycles 1000 cycles
tWHWLO Sector Erase Time-Out 100 µs
tQ7VQV DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)(3) 30 nsuPSD33xx
220/231
Figure 95. Peripheral I/O READ Timing
Table 146. Port A Peripheral Data Mode READ Timing (5V PSD Module)
Note: 1. Any input used to select Port A Data Peripheral Mode.
2. Data is already stable on Port A.
Table 147. Port A Peripheral Data Mode READ Timing (3V PSD Module)
Note: 1. Any input used to select Port A Data Peripheral Mode.
2. Data is already stable on Port A.
Symbol Parameter Conditions Min Max Turbo
Off Unit
tAVQV–PA
Address Valid to Data
Valid (Note 1) 37 + 10 ns
tSLQV–PA CSI Valid to Data Valid 27 + 10 ns
tRLQV–PA RD to Data Valid (Note 2) 32 ns
tDVQV–PA Data In to Data Out Valid 22 ns
tRHQZ–PA RD to Data High-Z 23 ns
Symbol Parameter Conditions Min Max Turbo
Off Unit
tAVQV–PA Address Valid to Data Valid (Note 1) 50 + 20 ns
tSLQV–PA CSI Valid to Data Valid 37 + 20 ns
tRLQV–PA RD to Data Valid (Note 2) 45 ns
tDVQV–PA Data In to Data Out Valid 38 ns
tRHQZ–PA RD to Data High-Z 36 ns
tRLQV (PA)
tDVQV (PA)
tRHQZ (PA)
tSLQV (PA)
tAVQV (PA)
ADDRESS DATA VALID
ALE
A/D BUS
RD
DATA ON PORT A
CSI
AI06610221/231
uPSD33xx
Figure 96. Peripheral I/O WRITE Timing
Table 148. Port A Peripheral Data Mode WRITE Timing (5V PSD Module)
Note: 1. Data stable on Port 0 pins to data on Port A.
Table 149. Port A Peripheral Data Mode WRITE Timing (3V PSD Module)
Note: 1. Data stable on Port 0 pins to data on Port A.
Table 150. Supervisor Reset and LVD
Note: 1. 25µs minimum to abort a Flash memory program or erase cycle in progress.
2. As FOSC decreases, tRST_ACTV increases. Example: tRST_ACTV = 50ms when FOSC = 8MHz.
Symbol Parameter Conditions Min Max Unit
tWLQV–PA WR to Data Propagation Delay 25 ns
tDVQV–PA Data to Port A Data Propagation Delay (Note 1) 22 ns
tWHQZ–PA WR Invalid to Port A Tri-state 20 ns
Symbol Parameter Conditions Min Max Unit
tWLQV–PA WR to Data Propagation Delay 42 ns
tDVQV–PA Data to Port A Data Propagation Delay (Note 1) 38 ns
tWHQZ–PA WR Invalid to Port A Tri-state 33 ns
Symbol Parameter Conditions Min Typ Max Unit
tRST_LO_IN Reset Input Duration 1(1) µs
tRST_ACTV Generated Reset Duration fOSC = 40MHz 10(2) ms
tRST_FIL Reset Input Spike Filter 1 µs
VRST_HYS Reset Input Hysteresis VCC = 3.3V 0.1 V
VRST_THRESH LVD Trip Threshold VCC = 3.3V 2.4 2.6 2.8 V
tDVQV (PA)
tWLQV (PA) tWHQZ (PA)
A/D BUS ADDRESS DATA OUT
WR
PORT A
DATA OUT
ALE
AI06611uPSD33xx
222/231
Table 151. VSTBYON Definitions Timing (5V, 3V PSD Modules)
Note: 1. VSTBYON timing is measured at VCC ramp rate of 2ms.
Figure 97. ISC Timing
Table 152. ISC Timing (5V PSD Module)
Note: 1. For non-PLD Programming, Erase or in ISC By-pass Mode.
2. For Program or Erase PLD only.
Symbol Parameter Conditions Min Typ Max Unit
tBVBH VSTBY Detection to VSTBYON Output High (Note 1) 20 µs
tBXBL
VSTBY Off Detection to VSTBYON Output
Low (Note 1) 20 µs
Symbol Parameter Conditions Min Max Unit
tISCCF Clock (TCK, PC1) Frequency (except for PLD) (Note 1) 20 MHz
tISCCH Clock (TCK, PC1) High Time (except for PLD) (Note 1) 23 ns
tISCCL Clock (TCK, PC1) Low Time (except for PLD) (Note 1) 23 ns
tISCCFP Clock (TCK, PC1) Frequency (PLD only) (Note 2) 5 MHz
tISCCHP Clock (TCK, PC1) High Time (PLD only) (Note 2) 90 ns
tISCCLP Clock (TCK, PC1) Low Time (PLD only) (Note 2) 90 ns
tISCPSU ISC Port Set Up Time 7 ns
tISCPH ISC Port Hold Up Time 5 ns
tISCPCO ISC Port Clock to Output 21 ns
tISCPZV ISC Port High-Impedance to Valid Output 21 ns
tISCPVZ ISC Port Valid Output to High-Impedance 21 ns
ISCCH
TCK
TDI/TMS
ISC OUTPUTS/TDO
ISC OUTPUTS/TDO
t
tISCCL
tISCPSU tISCPH
tISCPVZ
t ISCPZV
tISCPCO
AI02865223/231
uPSD33xx
Table 153. ISC Timing (3V PSD Module)
Note: 1. For non-PLD Programming, Erase or in ISC By-pass Mode.
2. For Program or Erase PLD only.
Figure 98. MCU Module AC Measurement I/O Waveform
Note: AC inputs during testing are driven at VCC–0.5V for a logic '1,' and 0.45V for a logic '0.'
Timing measurements are made at VIH(min) for a logic '1,' and VIL(max) for a logic '0'
Figure 99. PSD Module AC Float I/O Waveform
Note: For timing purposes, a Port pin is considered to be no longer floating when a 100mV change from load voltage occurs, and begins to
float when a 100mV change from the loaded VOH or VOL level occurs
IOL and IOH ≥ 20mA
Symbol Parameter Conditions Min Max Unit
tISCCF Clock (TCK, PC1) Frequency (except for PLD) (Note 1) 12 MHz
tISCCH Clock (TCK, PC1) High Time (except for PLD) (Note 1) 40 ns
tISCCL Clock (TCK, PC1) Low Time (except for PLD) (Note 1) 40 ns
tISCCFP Clock (TCK, PC1) Frequency (PLD only) (Note 2) 5 MHz
tISCCHP Clock (TCK, PC1) High Time (PLD only) (Note 2) 90 ns
tISCCLP Clock (TCK, PC1) Low Time (PLD only) (Note 2) 90 ns
tISCPSU ISC Port Set Up Time 12 ns
tISCPH ISC Port Hold Up Time 5 ns
tISCPCO ISC Port Clock to Output 30 ns
tISCPZV ISC Port High-Impedance to Valid Output 30 ns
tISCPVZ ISC Port Valid Output to High-Impedance 30 ns
AI06650
VCC – 0.5V
0.45V
Test Points
0.2 VCC – 0.1V
0.2 VCC + 0.9V
AI06651
Test Reference Points
VOL + 0.1V
VOH – 0.1V
VLOAD – 0.1V
VLOAD + 0.1V
0.2 VCC – 0.1VuPSD33xx
224/231
Figure 100. External Clock Cycle
Figure 101. PSD Module AC Measurement I/O
Waveform
Figure 102. PSD Module AC Measurement
Load Circuit
Table 154. I/O Pin Capacitance
Note: 1. Sampled only, not 100% tested.
2. Typical values are for TA = 25°C and nominal supply voltages.
3. Maximum for MCU Address and Data lines is 20pF each.
3.0V
0V
Test Point 1.5V
AI03103b
Device
Under Test
2.01 V
195 Ω
CL = 30 pF
(Including Scope and
Jig Capacitance)
AI03104b
Symbol Parameter(1) Test Condition Typ.2 Max. Unit
CIN Input Capacitance (for input pins) VIN = 0V 4 6 pF
COUT
Output Capacitance (for input/
output pins)(3) VOUT = 0V 8 12 pF225/231
uPSD33xx
PACKAGE MECHANICAL INFORMATION
Figure 103. TQFP52 – 52-lead Plastic Thin, Quad, Flat Package Outline
Note: Drawing is not to scale.
QFP-A
Nd
E1
CP
b
e
A2
A
N
A1 α L
D1
D
1
Ne E
c
D2
E2
L1uPSD33xx
226/231
Table 155. TQFP52 – 52-lead Plastic Thin, Quad, Flat Package Mechanical Data
Symb
mm inches
Typ Min Max Typ Min Max
A 1.50 – 1.70 0.059 – 0.067
A1 0.10 0.05 0.20 0.004 0.002 0.008
A2 1.40 1.30 1.50 0.055 0.039 0.059
b – 0.20 0.40 – 0.008 0.016
c – 0.07 0.20 – 0.003 0.008
D 12.00 11.80 12.20 0.472 0.465 0.480
D1 10.00 9.80 10.20 0.394 0.386 0.402
D2 7.80 7.67 7.93 0.307 0.302 0.312
E 12.00 11.80 12.20 0.472 0.465 0.480
E1 10.00 9.80 10.20 0.394 0.386 0.402
E2 7.80 7.67 7.93 0.307 0.302 0.312
e 0.65 – – 0.026 – –
L – 0.45 0.75 – 0.018 0.030
L1 1.00 – – 0.039 – –
α – 0° 7° – 0° 7°
n 52 52
Nd 13 13
Ne 13 13
CP – – 0.10 – – 0.004227/231
uPSD33xx
Figure 104. TQFP80 – 80-lead Plastic Thin, Quad, Flat Package Outline
Note: Drawing is not to scale.
QFP-A
Nd
E1
CP
b
e
A2
A
N
A1 α L
D1
D
1
Ne E
c
D2
E2
L1uPSD33xx
228/231
Table 156. TQFP80 – 80-lead Plastic Thin, Quad, Flat Package Mechanical Data
Symb
mm inches
Typ Min Max Typ Min Max
A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.40 1.35 1.45 0.055 0.053 0.057
b 0.17 0.27 0.007 0.011
c 0.09 0.20 0.004 0.008
D 14.00 0.551
D1 12.00 0.472
D2 9.50 0.374
E 14.00 0.551
E1 12.00 0.472
E2 9.50 0.374
e 0.50 0.020
L 0.45 0.75 0.018 0.030
L1 1.00 0.039
α 0° 7° 0° 7°
n 80 80
Nd 20 20
Ne 20 20
CP 0.08 0.003229/231
uPSD33xx
PART NUMBERING
Table 157. Ordering Information Scheme
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
Example: uPSD 33 3 4 D V – 40 U 6 T
Device Type
uPSD = Microcontroller PSD
Family
33 = Turbo core
SRAM Size
1 = 2Kbyte
3 = 8Kbyte
5 = 32Kbyte
Main Flash Memory Size
2 = 64Kbyte
3 = 128Kbyte
4 = 256Kbyte
IP Mix
D = IP Mix: I2C, SPI, UART (2), IrDA, ADC, Supervisor, PCA
Operating Voltage
blank = VCC = 4.5 to 5.5V
V = VCC = 3.0 to 3.6V
Speed
–40 = 40MHz
Package
T = 52-pin TQFP
U = 80-pin TQFP
Temperature Range
6 = –40 to 85°C
Shipping Option
Tape & Reel Packing = TuPSD33xx
230/231
REVISION HISTORY
Table 158. Document Revision History
Date Version Revision Details
July 1, 2003 1.0 First Issue
15-Jul-03 1.1 Update register information, electrical characteristics (Table 17, 46, 132, 133, 134, 135;
Figure 68)
03-Sep-03 1.2 Update references for Product Catalog
05-Feb-04 2.0 Reformatted; corrected mechanical dimensions (Table 158)
07-May-04 3.0
Reformatted; update characteristics (Figure 3, 4, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60,
61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83,
84; Table 42, 64, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93,
94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112,
113, 114, 115, 116, 117, 118, 121, 129, 130, 131, 136)
14-Sep-04 4.0
Reformatted; updated Feature Summary; added table (Table 128); updated graphics,
mechanical dimensions (Figure 3, 4, 37, 40, 51, 76, 80; Table 2, 3, 6, 7, 8, 9, 10, 11, 37,
38, 40, 51, 77, 84, 119, 120, 121, 129, 155, 156)
29-Oct-04 5.0 Corrected TQFP80 mechanical dimensions (Table 156)
21-Jan-05 6.0 Updated characteristics, SPI section (Figure 3, 41, 42, 45; Table 59, 60, 61, 62, 128,
138, 140, 142, 144, 145, 152, 153)231/231
uPSD33xx
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No lii96ns0.71(i96 i)-12.1-s granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
ESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 1/29
Revision History :
Revision 1.0 (Nov. 02, 2006)
-Original
Revision 1.1 (Mar. 02, 2007)
- Delete BGA ball name of packing dimensions
Revision 1.2 (May. 03, 2007)
- Modify DC Characteristics
Revision 1.3 (May. 14, 2007)
- Modify tSS (1.5ns => 2.5ns) and tSH(1ns => 1.5ns)
Revision 1.4 (Jul. 10, 2007)
- Modify type error ESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 2/29
SDRAM 512K x 32Bit x 2Banks
Synchronous DRAM
FEATURES
z 1.8V power supply
z LVCMOS compatible with multiplexed address
z Dual banks operation
z MRS cycle with address key programs
- CAS Latency (1, 2 & 3 )
- Burst Length (1, 2, 4, 8 & full page)
- Burst Type (Sequential & Interleave)
z EMRS cycle with address key programs.
z All inputs are sampled at the positive going edge of the
system clock
z Burst Read Single-bit Write operation
z Special Function Support.
- PASR (Partial Array Self Refresh )
- TCSR (Temperature compensated Self Refresh)
- DS (Driver Strength)
z DQM for masking
z Auto & self refresh
z 64ms refresh period (4K cycle)
GENERAL DESCRIPTION
The M52D32321A is 33,554,432 bits synchronous high
data rate Dynamic RAM organized as 2 x 524,288 words by
32 bits, fabricated with high performance CMOS technology.
Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
ORDERING INFORMATION
Part NO. MAX
Freq. Package Comments
M52D32321A -10BG 100MHz 90 Ball VFBGA Pb-free
M52D32321A -7.5BG 133MHz 90 Ball VFBGA Pb-free
PIN CONFIGURATION (TOP VIEW)
90 Ball FBGA
1 2 3 4 5 6 7 8 9
A DQ26 DQ24 VSS VDD DQ23 DQ21
B DQ28 VDDQ VSSQ VDDQ VSSQ DQ19
C VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ
D VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ
E VDDQ DQ31 NC NC DQ16 VSSQ
F VSS DQM3 A3 A2 DQM2 VDD
G A4 A5 A6 A10 A0 A1
H A7 A8 NC NC NC NC
J CLK CKE A9 BA CS RAS
K DQM1 NC NC CAS WE DQM0
L VDDQ DQ8 VSS VDD DQ7 VSSQ
M VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ
N VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ
P DQ11 VDDQ VSSQ VDDQ VSSQ DQ4
R DQ13 DQ15 VSS VDD DQ0 DQ2ESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 3/29
FUNCTIONAL BLOCK DIAGRAM
Bank Select Data Input Register
Column Decoder
Latency & Burst Length
Programming Register
512K x 32
512K x 32
Timing Register
CLK CKE CS RAS CAS WE L(U)DQM
LDQM LWCBR
DQi
LDQM
LWE
LRAS LCBR LWE LCAS
CLK
ADD
LCKE
PIN FUNCTION DESCRIPTION
Pin Name Input Function
CLK System Clock Active on the positive going edge to sample all inputs.
CS Chip Select Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM.
CKE Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A0 ~ A10 Address Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
BA Bank Select Address Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS Row Address Strobe Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS Column Address Strobe
Latches column addresses on the positive going edge of the CLK with
CAS low.
Enables column access.
WE Write Enable Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
L(U)DQM Data Input / Output Mask Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active. ESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 4/29
DQ0 ~ 31 Data Input / Output Data inputs/outputs are multiplexed on the same pins.
VDD/VSS Power Supply/Ground Power and ground for the input buffers and the core logic.
VDDQ/VSSQ Data Output Power/Ground Isolated power supply and ground for the output buffers to provide improved
noise immunity.
N.C/RFU No Connection/
Reserved for Future Use This pin is recommended to be left No Connection on the device.
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Value Unit
Voltage on any pin relative to VSS VIN,VOUT -1.0 ~ 4.6 V
Voltage on VDD supply relative to VSS VDD,VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ + 150 °C
Power dissipation PD 0.7 W
Short circuit current IOS 50 MA
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA= 0 °C ~ 70 °C )
Parameter Symbol Min Typ Max Unit Note
Supply voltage VDD,VDDQ 1.7 1.8 1.9 V
Input logic high voltage VIH 0.8 x VDDQ 1.8 VDDQ+0.3 V 1
Input logic low voltage VIL -0.3 0 0.3 V 2
Output logic high voltage VOH VDDQ – 0.2 - - V IOH =-0.1mA
Output logic low voltage VOL - - 0.2 V IOL = 0.1mA
Input leakage current IIL -10 - 10 uA 3
Output leakage current IOL -10 - 10 uA 4
Note : 1.VIH (max) = 2.2V AC for pulse width ≤ 3ns acceptable.
2.VIL (min) = -1.0V AC for pulse width ≤ 3ns acceptable.
3.Any input 0V ≤ VIN ≤ VDDQ, all other pins are not under test = 0V.
4.Dout is disabled, 0V ≤ VOUT ≤ VDDQ.
CAPACITANCE (VDD = 1.8V, TA = 25 °C , f = 1MHz)
Pin Symbol Min Max Unit
CLOCK CCLK 2.0 4.0 pF
RAS , CAS , WE , CS , CKE, LDQM,
UDQM CIN 2.0 4.0 pF
ADDRESS CADD 2.0 4.0 pF
DQ0 ~DQ15 COUT 3.5 6.0 pF ESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 5/29
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 °C ~ 70 °C )
Version
Parameter Symbol Test Condition
CAS
Latency -7.5 -10 Unit Note
Operating Current
(One Bank Active) ICC1 Burst Length = 1
tRC ≥ tRC (min), tCC ≥ tCC (min), IOL= 0mA 55 35 mA 1
Precharge Standby ICC2P CKE ≤ VIL(max), tCC =15ns 0.3 mA
Current in power-down
mode ICC2PS CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞ 0.2 mA
ICC2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC =15ns
Input signals are changed one time during 30ns
3 mA Precharge Standby
Current in non
power-down mode
ICC2NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable 1 mA
ICC3P CKE ≤ VIL(max), tCC =15ns 1.5 Active Standby Current
in power-down mode ICC3PS CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞ 1
mA
ICC3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC=15ns
Input signals are changed one time during 30ns Active Standby Current 10 mA
in non power-down
mode
(One Bank Active) ICC3NS
CKE ≥ VIH (min), CLK ≤ VIL(max), tCC= ∞
Input signals are stable 2.5 mA
Operating Current
(Burst Mode)
ICC4
IOL= 0Ma, Page Burst
All Band Activated, tCCD = tCCD (min) 70 60 mA 1
Refresh Current ICC5 tRC ≥ tRC(min) 40 40 mA 2
TCSR range 45 70 °C
Self Refresh Current ICC6 CKE ≤ 0.2V 2 Banks 180 200
1 Bank 160 180 uA
Deep Power Down
Current
ICC7 CKE ≤ 0.2V 10 uA
Note: 1.Measured with outputs open. Addresses are changed only one time during tCC(min).
2.Refresh period is 64ms. Addresses are changed only one time during tCC(min). ESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 6/29
AC OPERATING TEST CONDITIONS (VDD=1.8V ± 0.1V,TA= 0 C° ~ 70 C° )
Parameter Value Unit
Input levels (Vih/Vil) 0.9 x VDDQ / 0.2 V
Input timing measurement reference level 0.5 x VDDQ V
Input rise and fall time tr / tf = 1 / 1 ns
Output timing measurement reference level 0.5 x VDDQ V
Output load condition See Fig.2
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter Symbol
-7.5 -10
Unit Note
Row active to row active delay tRRD(min) 15 20 ns 1
RAS to CAS delay tRCD(min) 22.5 30 ns 1
Row precharge time tRP(min) 22.5 30 ns 1
tRAS(min) 45 50 ns 1 Row active time
tRAS(max) 100 us
Row cycle time tRC(min) 67.5 90 ns 1
Last data in to new col. Address delay tCDL(min) 1 CLK 2
Last data in to row precharge tRDL(min) 2 CLK 2
Last data in to burst stop tBDL(min) 1 CLK 2
Col. Address to col. Address delay tCCD(min) 1 CLK 3
CAS latency=3 2 Number of valid output data
CAS latency=2 1
ea 4
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.
Z0=50
1.8V
Output
(Fig.2) AC Output Load Circuit
20 pF
Vtt =0.5x VDDQ
VOH(DC) = VDDQ-0.2V, IOH = -0.1mA
VOL(DC) = 0.2V, IOL = 0.1mA
20 pF
Output
(Fig.1) DC Output Load circuit
10.6K
13.9K
50ESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 7/29
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
-7.5 -10 Parameter Symbol Min Max Min Max Unit Note
CAS Latency =3 7.5 9 CLK cycle time CAS Latency =2
tCC
12
1000
15
1000 ns 1
CLK to valid CAS Latency =3 - 7 - 8
output delay CAS Latency =2
tSAC
- 10 - 10
ns 1
Output data hold time tOH 2.0 - 2.0 - ns 2
CLK high pulse width tCH 2.5 - 2.5 - ns 3
CLK low pulse width tCL 2.5 - 2.5 - ns 3
Input setup time tSS 2.5 - 2.5 - ns 3
Input hold time tSH 1.5 - 1.5 - ns 3
CLK to output in Low-Z tSLZ 1 - 1 - ns 2
CAS Latency =3 - 6 - 7 CLK to output in
Hi-Z CAS Latency =2
tSHZ
- 9 - 10
ns -
*All AC parameters are measured from half to half.
Note: 1.Parameters depend on programmed CAS latency.
2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.
3.Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the
parameter. ESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 8/29
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address BA A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Function 0 RFU W.B.L TM CAS Latency BT Burst Length
Test Mode CAS Latency Burst Type Burst Length
A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT = 0 BT = 1
0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1
0 1 Reserved 0 0 1 1 1 Interleave 0 0 1 2 2
1 0 Reserved 0 1 0 2 0 1 0 4 4
1 1 Reserved 0 1 1 3
0 1 1 8 8
1 0 0 Reserved 1 0 0 Reserved Reserved
1 0 1 Reserved 1 0 1 Reserved Reserved
1 1 0 Reserved 1 1 0 Reserved Reserved
1 1 1 Reserved
1 1 1 Full Page Reserved
Full Page Length : 256 ESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 9/29
Extended Mode Register
BA A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus
1 0 ATCSR 0 0 DS TCSR PASR Extended Mode Register
A2-0 Self Refresh Coverage
000 Full Array
001 1/2 of Full Array
010 1/4 of Full Array
011 RFU
100 RFU
101 RFU
110 RFU
PASR
111 RFU
A6-A5 Driver Strength
00 Full Strength
01 1/2 Strength
10 1/4 Strength
DS
11 RFU
A9 ATCSR
ATCSR 0 Enable
1 R
TRUTH TABLE (Deep Power Down Mode)
COMMAND CKEn-1 CKEn CS RAS CAS WE DQM BA A10/AP A9~A0
Entry H L L H H L X Deep Power Down Mode
Exit L H X X X X X
X
(V= Valid, X= Don’t Care, H= Logic High , L = Logic Low)
A4-A3 Maximum Case Temperature
11 85oC
00 70oC
01 45oC
TCSR
10 15oC ESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 10/29
Burst Length and Sequence
(Burst of Two)
Starting Address
(column address A0 binary)
Sequential Addressing
Sequence (decimal)
Interleave Addressing
Sequence (decimal)
0 0,1 0,1
1 1,0 1,0
(Burst of Four)
Starting Address
(column address A1-A0, binary)
Sequential Addressing
Sequence (decimal)
Interleave Addressing
Sequence (decimal)
00 0,1,2,3 0,1,2,3
01 1,2,3,0 1,0,3,2
10 2,3,0,1 2,3,0,1
11 3,0,1,2 3,2,1,0
(Burst of Eight)
Starting Address
(column address A2-A0, binary)
Sequential Addressing
Sequence (decimal)
Interleave Addressing
Sequence (decimal)
000 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7
001 1,2,3,4,5,6,7,0 1,0,3,2,5,4,7,6
010 2,3,4,5,6,7,0,1 2,3,0,1,6,7,4,5
011 3,4,5,6,7,0,1,2 3,2,1,0,7,6,5,4
100 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3
101 5,6,7,0,1,2,3,4 5,4,7,6,1,0,3,2
110 6,7,0,1,2,3,4,5 6,7,4,5,2,3,0,1
111 7,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0
Full page burst is an extension of the above tables of Sequential Addressing, with the length being 256 for 1Mx32 divice.
POWER UP SEQUENCE
1.Apply power and start clock, attempt to maintain CKE= “H”, L(U)DQM = “H” and the other pin are NOP condition at the inputs.
2.Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3.Issue precharge commands for all banks of the devices.
4.Issue 2 or more auto-refresh commands.
5.Issue mode register set command to initialize the mode register.
Cf.)Sequence of 4 & 5 is regardless of the order.ESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 11/29
SIMPLIFIED TRUTH TABLE
COMMAND CKEn-1 CKEn CS RAS CAS WE DQM BA A10/AP A9~A0 Note
Mode Register Set H X L L L L X OP CODE 1,2
Register Extended Mode Register
Set
H X L L L L X OP CODE 1,2
Auto Refresh H 3
Entry H L L L L H X X 3
L H H H 3
Refresh Self Refresh
Exit L H H X X X X X 3
Bank Active & Row Addr. H X L L H H X V Row Address
Auto Precharge Disable L 4 Read &
Column Address Auto Precharge Enable
H X L H L H X V
H
Column
Address
(A0~A7) 4,5
Write & Column Auto Precharge Disable L 4
Address Auto Precharge Enable
H X L H L L X V
H
Column
Address
(A0~A7) 4,5
Burst Stop H X L H H L X X 6
Bank Selection V L 4 Precharge Both Banks H X L L H L X X H X 4
H X X X Entry H L L V V V Clock Suspend or X
Active Power Down Exit L H X X X X X
X
H X X X Entry H L L H H H X
H X X X
Precharge Power Down Mode
Exit L H L V V V X
X
DQM H X V X 7
H H X X X No Operation Command H X L H H H X X
Deep Power Down Mode Entry H L L H H L X
Exit L H X X X X X
X
(V= Valid, X= Don’t Care, H= Logic High , L = Logic Low)
Note:
1. OP Code: Operation Code
A0~A10/AP, BA: Program keys.(@MRS). BA=0 for MRS and BA=1 for EMRS.
2. MRS/EMRS can be issued only at both banks precharge state.
A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”.
Auto / self refresh can be issued only at both banks precharge state.
4. BA: Bank select address.
If “Low”: at read, write, row active and precharge, bank A is selected.
If “High”: at read, write, row active and precharge, bank B is selected.
If A10/AP is “High” at row precharge, BA ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read /write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but
makes
Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) ESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 12/29
Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency=3, Burst Length=1
: D o n ' t C a r e
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
C S
RAS
CAS
ADDR
W E
D Q
DQM
A10/AP
t C H
t C L
t C C
Row Active
BA
*Note1
HIGH
t RCD
t S S
t S S
t S H
t S H
t S S
t S H
t S S
t S S
t S H
t S S
t S S
t S H
R a C a C b C c R b
BS BS BS BS BS BS
R a
Qa D b Q c
R b
Read Write Read
Precharge
Row Active
t R C
t RAS
t R P
t CCD
t RAC
*Note2 *Note2,3 *Note2,3 *Note4 *Note2
*Note 3 *Note 3
*Note2,3
t S H
t SLZ
t SAC
t O H
t S H
t S S t S H
*Note 3 *Note4ESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 13/29
*Note: 1. All inputs expect CKE & DQM can be don’t care when CS is high at the CLK high going edge.
2. Bank active & read/write are controlled by BA.
BA Active & Read/Write
0 Bank A
1 Bank B
3.Enable and disable auto precharge function are controlled by A10/AP in read/write command.
A10/AP BA Operation
0 0 Disable auto precharge, leave bank A active at end of burst.
1 Disable auto precharge, leave bank B active at end of burst.
1 0 Enable auto precharge, precharge bank A at end of burst.
1 Enable auto precharge, precharge bank B at end of burst.
4.A10/AP and BA control bank precharge when precharge command is asserted.
A10/AP BA precharge
0 0 Bank A
0 1 Bank B
1 X Both Banks ESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 14/29
Power Up Sequence
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
ADDR
D Q
DQM
A10/AP
t R P
Key RAa
RAa
Precharge
All Banks
Auto Refresh Auto Refresh Mode Register Set
(A-Bank)
Row Active
: Don't care
t R C t R C
High level is necessary
High level is necessary
BA
High-Z
CS
RAS
CAS
WE
Key
KeyESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 15/29
Read & Write Cycle at Same Bank @Burst Length = 4
*Note: 1.Minimum row cycle times is required to complete internal DRAM operation.
2.Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z(tSHZ) after the clock.
3.Access time from Row active command. tcc*(tRCD +CAS latency-1)+tSAC
4.Ouput will be Hi-Z after the end of burst.(1,2,4,8 bit burst)
Burst can’t end in Full Page Mode.
tRCD
tRC
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
CS
RAS
CAS
ADDR
DQM
BA
CL=2
CL=3
Ra Rb Cb0
tOH
tSAC
tSHZ
tSHZ
tRDL
Row Active Read Precharge
(A-Bank) (A-Bank) (A-Bank)
Precharge
(A-Bank)
Write
(A-Bank)
Row Active
(A-Bank)
*Note3
*Note3
*Note4
*Note4
: Don't care
*Note1
Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3
Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3
tRAC
tRAC
tRDL
Ca0
A10/AP Ra Rb
HIGH
*Note2
WE
tO H
QC tSACESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 16/29
Page Read & Write Cycle at Same Bank @ Burst Length=4
*Note :1.To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus
contention.
2.Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3.DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
CLOCK
CKE
CS
RAS
CAS
BA
ADDR
A10/AP
CL=2
CL=3
WE
DQM
HIGH
tRCD
*Note2
Ra Ca0 Cb0 Cc0 Cd0
Ra
Qa0 Qa1 Qb0 Qb1 Qb2 Dc0 Dc1 Dd0 Dd1
Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 Dd2
tCDL
*Note1
Row Active
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don't care
DQ
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
tRDL
*Note3ESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 17/29
Page Read Cycle at Different Bank @ Burst Length=4
*Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going dege.
2.To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
CLOCK
CKE
CS
RAS
CAS
BA
ADDR
A10/AP
CL=2
CL=3
WE
DQM
HIGH
*Note2
RAa CAa RBb
RAa
Read
(A-Bank)
Row Active
Row Active
(B-Bank)
(A-Bank)
Read
(A-Bank)
Read
(B-Bank)
Read
(A-Bank)
Read
(B-Bank)
Precharge
(A-Bank)
: Don't care
DQ
CBb CAc CBd CAe
QAa0
*Note1
RBb
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 ESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 18/29
Page Write Cycle at Different Bank @Burst Length = 4
*Note: 1.To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2.To interrupt burst write by row precharge, both the write and the precharge banks must be the same.
CLOCK
CKE
CS
RAS
CAS
BA
ADDR
A10/AP
WE
DQM
HIGH
Row Active
(A-Bank)
Row Active
(B-Bank)
Write
(A-Bank)
Precharge
(Both Banks)
: Don't care
DQ
Write
(A-Bank) Write
(B-Bank)
Write
(B-Bank)
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1
RAa RBb
RAa CAa RBb CBb CAc CBd
*Note2
tCDL tRDL
*Note1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 19/29
Read & Write Cycle at Different Bank @ Burst Length = 4
*Note: 1.tCDL should be met to complete write.ESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 20/29
Read & Write Cycle with auto Precharge @ Burst Length =4
*Note: 1.tCDL Should be controlled to meet minimum tRAS before internal precharge start
(In the case of Burst Length=1 & 2 and BRSW mode)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
CAS
ADDR
W E
D Q
DQM
A10/AP
BA
CL=2
CL=3
Row Active
( A - Bank )
Row Active
( B - Bank )
Read with
Auto Precharge
( A - Bank )
Auto Precharge
Start Point
(B-Bank)
: D o n ' t C a r e
Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3
R a
Ra Ca R b C b
R b
Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3
Write with
Auto Precharge
(B-Bank)
HIGH
Auto Precharge
Start Point
( A - Bank)
C S
RASESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 21/29
Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4
*Note:1.DQM is needed to prevent bus contention.
CLOCK
CKE
ADDR
D Q
DQM
A10/AP
R a C a C b C c
R a
Qa0 Qa1 Qa2 Qa3
t SHZ
Qb0 Qb1
t SHZ
Dc0 Dc2
*Note1
Row Active Read
Clock
Suspension Read
Read DQM Write
Write
DQM
Clock
Suspension
Write
DQM
:Don't Care
BA
C S
RAS
CAS
W E
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19ESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 22/29
Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length =Full page
*Note: 1.Burst can’t end in full page mode, so auto precharge can’t issue.
2.About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1,2 on them.
But at burst write, burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of “Full page write burst stop cycle”.
3.Burst stop is valid at every burst length.
CLOCK
CKE
ADDR
D Q
DQM
A10/AP
BA
RAa CAa CAb
RAa
QAa0 QAa1 QAb0 QAb1 QAb2
*Note1
Row Active
(A-Bank)
Read
(A-Bank)
Burst Stop Read
(A-Bank)
:Don't Care
HIGH
CL=2
CL=3
QAa2 QAa3 QAa4 QAb3 QAb4 QAb5
QAa0 QAa1 QAa2 QAa3 QAa4 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
1 1
2 2
Precharge
(A-Bank)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CS
RAS
CAS
WE
*Note2ESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 23/29
Write Interrupted by Precharge Command & Write Burst stop Cycle @ Burst Length =Full page
*Note: 1. Burst can’t end in full page mode, so auto precharge can’t issue.
2.Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by
AC parameter of tRDL.
DQM at write interrupted by precharge command is needed to prevent invalid write.
Input data after Row precharge cycle will be masked internally.
3.Burst stop is valid at every burst length.
CLOCK
CKE
ADDR
D Q
DQM
A10/AP
RAa CAa CAb
RAa
DAa0 DAa1 DAb0 DAb1 DAb2
Row Active
(A-Bank)
Write
(A-Bank)
Burst Stop Write
(A-Bank)
:Don't Care
HIGH
DAa2 DAa3 DAa4 DAb3 DAb4 DAb5
Precharge
(A-Bank)
t BDL t RDL
*Note2
C S
RAS
CAS
W E
BA
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19ESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 24/29
Burst Read Single bit Write Cycle @Burst Length=2
*Note:1.BRSW modes is enabled by setting A9 “High” at MRS(Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to “1” regardless of programmed burst length.
2.When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.
Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command, the precharge
command will be issued after two clock cycles.
CLOCK
CKE
ADDR
CL=2
DQM
A10/AP
BA
RAa RAc
RAa
QAb0
Row Active
(A-Bank)
Write
(A-Bank)
:Don't Care
HIGH
QAb1
Precharge
(A-Bank)
CAa RBb CAb CBc CAd
RAc
DBc0
D Q
CL=3 DAa0 QAb0 QAb1 DBc0
Row Active
(B-Bank)
Row Active
(A-Bank)
Write with
Auto Precharge
(B-Bank)
Read
(A-Bank)
DAa0 QAd0 QAd1
QAd0 QAd1
*Note1
C S
RAS
CAS
W E
RBb
*Note2
Read with
Auto Precharge
(A-Bank) ESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 25/29
Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4
*Note :1.Both banks should be in idle state prior to entering precharge power down mode.
2.CKE should be set high at least 1CLK+tss prior to Row active command.
3.Can not violate minimum refresh specification. (64ms)
CLOCK
CKE
ADDR
D Q
DQM
A10/AP
Active
Power-down
Exit
Precharge
: Don't care
*Note3
*Note2
*Note1
t S S
R a
R a
Qa0 Qa1 Qa2
t SHZ
Precharge
Power-Down
Entry Precharge
Power-Down
Exit
Row Active
Active
Power-down
Entry
Read
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
C a
B A
RAS
CAS
C S
W E
tS S
tS SESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 26/29
Self Refresh Entry & Exit Cycle
*Note: TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS Starts from high.
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst
refresh.
CLOCK
CKE
ADDR
D Q
DQM
A10/AP
Self Refresh Entry Auto Refresh
: Don't care
Self Refresh Exit
Hi-Z Hi-Z
W E
BA
CAS
RAS
C S
*Note2
*Note1
*Note4 t RCmin
*Note6
*Note5
*Note7
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
t S S
*Note3ESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 27/29
Mode Register Set Cycle Auto Refresh Cycle
*Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note: 1. CS ,RAS , CAS & WE activation at the same clock cycle with address key will set internal mode register.
2.Minimum 2 clock cycles should be met before new RAS activation.
3.Please refer to Mode Register Set table.
CLOCK
CKE
ADDR Key
:Don't Care
HIGH
C S
RAS
CAS
HIGH
*Note3
R a
*Note1
D Q Hi-Z
DQM
1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10
Hi-Z
*Note2 t R C
MRS New Command Auto Refresh New Command
W E
0ESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 28/29
PACKING DIMENSIONS
90-BALL SDRAM ( 8x13 mm )
Symbol Dimension in mm Dimension in inch
Min Norm Max Min Norm Max
A 1.00 0.039
A1 0.30 0.35 0.40 0.012 0.014 0.016
A2 0.586 0.023
øb 0.40 0.45 0.50 0.016 0.018 0.020
D 7.90 8.00 8.10 0.311 0.315 0.319
E 12.90 13.00 13.10 0.508 0.512 0.516
D1 6.40 0.252
E1 11.20 0.441
e 0.80 0.031
Controlling dimension : Millimeter.ESMT M52D32321A
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.4 29/29
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or by
any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the
time of publication. ESMT assumes no responsibility for any error in this
document, and reserves the right to change the products or specification in
this document without notice.
The information contained herein is presented only as a guide or examples
for the application of our products. No responsibility is assumed by ESMT for
any infringement of patents, copyrights, or other intellectual property rights of
third parties which may result from its use. No license, either express ,
implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To
minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure,
should be provided by the customer when making application designs.
ESMT's products are not authorized for use in critical applications such as,
but not limited to, life support devices or system, where failure or abnormal
operation may directly affect human lives or cause physical injury or property
damage. If products described here are to be used for such kinds of
application, purchaser must do its own quality assurance testing appropriate
to such applications.
CRUCIAL PART NUMBER MODULE TYPE DENSITY SPEED RANK VOLTAGE COMP CONFIG CAS LATENCY MICRON PART NUMBER
CT4G4RFS8213 RDIMM 288-pin 4GB 2133MT/s Single 1.2V 512M x 8 CL15 MTA9ASF51272PZ-2G1A2
CT8G4RFS4213 RDIMM 288-pin 8GB 2133MT/s Single 1.2V 1024M x 4 CL15 MTA18ASF1G72PZ-2G1A2
CT16G4RFD4213 RDIMM 288-pin 16GB 2133MT/s Dual 1.2V 1024M x 4 CL15 MTA36ASF2G72PZ-2G1A2
CT4G4DFS8213 UDIMM 288-pin 4GB 2133MT/s Single 1.2V 512M x 8 CL15 MTA8ATF51264AZ-2G1A1
CT8G4DFD8213 UDIMM 288-pin 8GB 2133MT/s Dual 1.2V 512M x 8 CL15 MTA16ATF1G64AZ-2G1A1
1
Product performance and efficiency improvements are noted as comparisons between DDR3 and DDR4 memory technologies at their introduction. When it was introduced, DDR3-1066 operated at 1.5V and had an
estimated component density of 8Gb, compared to DDR4-2133, which will operate at 1.2V and have an estimated component density of 16Gb. When voltage reductions and all other energy-saving DDR4 features are
factored in, DDR4 modules are projected to consume up to 40% less power.
2Limited lifetime warranty valid everywhere except Germany and France, where warranty is valid for ten years from date of purchase.
3Program benefits may vary and are subject to change without notice. Customer admittance and continued inclusion to the program is up to the sole discretion of Micron Technology, Inc.
REVISION: 04/18/2014
©2014 Micron Technology, Inc. All rights reserved. Information is subject to change without notice. Crucial and the Crucial logo are trademarks or registered trademarks of Micron
Technology, Inc. All other trademarks and service marks are property of their respective owners. Products and specifications are subject to change without notice. Neither Crucial
nor Micron Technology is responsible for omissions or errors in typography or photography.
NOW SAMPLING:
Crucial®
DDR4 Server Memory
Get early access to Crucial DDR4 modules!
Introducing the Crucial DDR4 Technology
Enablement Program (TEP)
HOW IT WORKS
Enroll in the Crucial DDR4 TEP program and get early access to DDR4 modules and
information. Start the enrollment process today by visiting
www.crucial.com/usa/en/memory-ddr4-info.
ELIGIBILITY
Channel partners who are currently developing or evaluating DDR4-capable platforms
BENEFITS3
• Early access to select Crucial DDR4 modules
• Notification of new DDR4 modules as they become available
• Access to technical resources to aid in product development and evaluation
Now Sampling
The following modules are now included as part of the Crucial DDR4 TEP program. Qualified participants are encouraged to inquire about pricing
and availability. Additional module types, densities, and speeds will be available later this year. Stay tuned!
DDR4 Server Memory:
Product Highlights1
• Increase data throughput – up to 50%
more memory bandwidth
• Enable up to twice the installed server
memory capacity
• Reduce power consumption – up to 40%
more energy efficient
• Easier system cooling – less heat
generated per module
• Optimized for future Intel® Xeon®
processor E5-2600 v3 product family
• Compatible with OEM servers and
warranties
• Backed by the Reliance Program
• Limited lifetime warranty2
Overcome one of the greatest server limitations: memory. From cloud computing and
virtualization to HPC, Big Data and more, memory-dependent server applications require
increasingly higher densities of memory and higher levels of performance than are attainable
on current DDR3 technology. Enter Crucial DDR4 server memory.
More speed. More bandwidth. More efficient.
Next generation DDR4 memory is here.
© 2007 Microchip Technology Inc. DS39605F
PIC18F1220/1320
Data Sheet
18/20/28-Pin High-Performance,
Enhanced Flash Microcontrollers
with 10-Bit A/D and nanoWatt TechnologyDS39605F-page ii © 2007 Microchip Technology Inc.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.© 2007 Microchip Technology Inc. DS39605F-page 1
Low-Power Features:
• Power Managed modes:
- Run: CPU on, peripherals on
- Idle: CPU off, peripherals on
- Sleep: CPU off, peripherals off
• Power Consumption modes:
- PRI_RUN: 150 μA, 1 MHz, 2V
- PRI_IDLE: 37 μA, 1 MHz, 2V
- SEC_RUN: 14 μA, 32 kHz, 2V
- SEC_IDLE: 5.8 μA, 32 kHz, 2V
- RC_RUN: 110 μA, 1 MHz, 2V
- RC_IDLE: 52 μA, 1 MHz, 2V
- Sleep: 0.1 μA, 1 MHz, 2V
• Timer1 Oscillator: 1.1 μA, 32 kHz, 2V
• Watchdog Timer: 2.1 μA
• Two-Speed Oscillator Start-up
Oscillators:
• Four Crystal modes:
- LP, XT, HS: up to 25 MHz
- HSPLL: 4-10 MHz (16-40 MHz internal)
• Two External RC modes, up to 4 MHz
• Two External Clock modes, up to 40 MHz
• Internal oscillator block:
- 8 user-selectable frequencies: 31 kHz, 125 kHz,
250 kHz, 500 kHz, 1 MHz, 2 MHz, 4 MHz, 8 MHz
- 125 kHz to 8 MHz calibrated to 1%
- Two modes select one or two I/O pins
- OSCTUNE – Allows user to shift frequency
• Secondary oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor
- Allows for safe shutdown if peripheral clock stops
Peripheral Highlights:
• High current sink/source 25 mA/25 mA
• Three external interrupts
• Enhanced Capture/Compare/PWM (ECCP) module:
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-Shutdown and Auto-Restart
- Capture is 16-bit, max resolution 6.25 ns (TCY/16)
- Compare is 16-bit, max resolution 100 ns (TCY)
• Compatible 10-bit, up to 13-channel Analog-toDigital
Converter module (A/D) with programmable
acquisition time
• Enhanced USART module:
- Supports RS-485, RS-232 and LIN 1.2
- Auto-Wake-up on Start bit
- Auto-Baud Detect
Special Microcontroller Features:
• 100,000 erase/write cycle Enhanced Flash
program memory typical
• 1,000,000 erase/write cycle Data EEPROM
memory typical
• Flash/Data EEPROM Retention: > 40 years
• Self-programmable under software control
• Priority levels for interrupts
• 8 x 8 Single-Cycle Hardware Multiplier
• Extended Watchdog Timer (WDT):
- Programmable period from 41 ms to 131s
- 2% stability over VDD and Temperature
• Single-supply 5V In-Circuit Serial Programming™
(ICSP™) via two pins
• In-Circuit Debug (ICD) via two pins
• Wide operating voltage range: 2.0V to 5.5V
Device
Program Memory Data Memory
I/O 10-bit
A/D (ch)
ECCP
(PWM) EUSART Timers
Flash 8/16-bit
(bytes)
# Single-Word
Instructions
SRAM
(bytes)
EEPROM
(bytes)
PIC18F1220 4K 2048 256 256 16 7 1 Y 1/3
PIC18F1320 8K 4096 256 256 16 7 1 Y 1/3
18/20/28-Pin High-Performance, Enhanced Flash MCUs
with 10-bit A/D and nanoWatt Technology
PIC18F1220/1320PIC18F1220/1320
DS39605F-page 2 © 2007 Microchip Technology Inc.
Pin Diagrams
RB3/CCP1/P1A
RB2/P1B/INT2
OSC1/CLKI/RA7
OSC2/CLKO/RA6
VDD/AVDD
RB7/PGD/T1OSI/
RB6/PGC/T1OSO/
RB5/PGM/KBI1
RB4/AN6/RX/
RA0/AN0
RA1/AN1/LVDIN
RA4/T0CKI
MCLR/VPP/RA5
VSS/AVSS
RA2/AN2/VREFRA3/AN3/VREF+
RB0/AN4/INT0
RB1/AN5/TX/
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
PIC18F1X20
18-Pin PDIP, SOIC
RB3/CCP1/P1A
RB2/P1B/INT2
OSC1/CLKI/RA7
OSC2/CLKO/RA6
VDD
RB7/PGD/T1OSI/
RB6/PGC/T1OSO/
RB5/PGM/KBI1
RB4/AN6/RX/
RA0/AN0
RA1/AN1/LVDIN
RA4/T0CKI
MCLR/VPP/RA5
VSS
RA2/AN2/VREFRA3/AN3/VREF+
RB0/AN4/INT0
RB1/AN5/TX/
1
2
3
4
5
7
8
9
10
20
19
18
17
16
14
13
12
11
PIC18F1X20
AVSS 6 15 AVDD
20-Pin SSOP
28-Pin QFN
16
2
RA4/T0CKI
RA0/AN0
NC
MCLR/VPP/RA5
NC
AVSS
NC
RA2/AN2/VREFRA3/AN3/VREF+
RA1/AN1/LVDIN
OSC1/CLKI/RA7
OSC2/CLKO/RA6
VDD
NC
AVDD
RB7/PGD/T1OSI/P1D/KBI3
RB6/PGC/T1OSO/T13CKI/P1C/KBI2
NC
RB5/PGM/KBI1
7
PIC18F1X20
1
3
6
5
4
15
21
19
20
17
18
28
27
26
25
24
23
22
8
9
10
11
12
13
14
VSS
NC
NC
RB2/P1B/INT2
RB0/AN4/INT0
RB1/AN5/TX/CK/INT1
NC
RB4/AN6/RX/DT/KBI0 RB3/CCP1/P1A
T13CKI/P1C/KBI2
P1D/KBI3
CK/INT1 DT/KBI0
P1D/KBI3
T13CKI/P1C/KBI2
CK/INT1 DT/KBI0© 2007 Microchip Technology Inc. DS39605F-page 3
PIC18F1220/1320
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 Oscillator Configurations ............................................................................................................................................................ 11
3.0 Power Managed Modes ............................................................................................................................................................. 19
4.0 Reset.......................................................................................................................................................................................... 33
5.0 Memory Organization................................................................................................................................................................. 41
6.0 Flash Program Memory.............................................................................................................................................................. 57
7.0 Data EEPROM Memory ............................................................................................................................................................. 67
8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 71
9.0 Interrupts .................................................................................................................................................................................... 73
10.0 I/O Ports ..................................................................................................................................................................................... 87
11.0 Timer0 Module ........................................................................................................................................................................... 99
12.0 Timer1 Module ......................................................................................................................................................................... 103
13.0 Timer2 Module ......................................................................................................................................................................... 109
14.0 Timer3 Module ......................................................................................................................................................................... 111
15.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 115
16.0 Enhanced Addressable Universal Synchronous Asynchronous Receiver Transmitter (EUSART) .......................................... 131
17.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 155
18.0 Low-Voltage Detect.................................................................................................................................................................. 165
19.0 Special Features of the CPU.................................................................................................................................................... 171
20.0 Instruction Set Summary.......................................................................................................................................................... 191
21.0 Development Support............................................................................................................................................................... 233
22.0 Electrical Characteristics.......................................................................................................................................................... 237
23.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 267
24.0 Packaging Information.............................................................................................................................................................. 285
Appendix A: Revision History............................................................................................................................................................. 291
Appendix B: Device Differences ........................................................................................................................................................ 291
Appendix C: Conversion Considerations ........................................................................................................................................... 292
Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 292
Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 293
Appendix F: Migration from High-End to Enhanced Devices............................................................................................................. 293
Index .................................................................................................................................................................................................. 295
The Microchip Web Site..................................................................................................................................................................... 303
Customer Change Notification Service .............................................................................................................................................. 303
Customer Support.............................................................................................................................................................................. 303
Reader Response .............................................................................................................................................................................. 304
PIC18F1220/1320 Product Identification System .............................................................................................................................. 305PIC18F1220/1320
DS39605F-page 4 © 2007 Microchip Technology Inc.
TO OUR VALUED CUSTOMERS
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.© 2007 Microchip Technology Inc. DS39605F-page 5
PIC18F1220/1320
1.0 DEVICE OVERVIEW
This document contains device specific information for
the following devices:
This family offers the advantages of all PIC18 microcontrollers
– namely, high computational performance at an
economical price – with the addition of high endurance
Enhanced Flash program memory. On top of these features,
the PIC18F1220/1320 family introduces design
enhancements that make these microcontrollers a logical
choice for many high-performance, power sensitive
applications.
1.1 New Core Features
1.1.1 nanoWatt TECHNOLOGY
All of the devices in the PIC18F1220/1320 family incorporate
a range of features that can significantly reduce
power consumption during operation. Key items include:
• Alternate Run Modes: By clocking the controller
from the Timer1 source or the internal oscillator
block, power consumption during code execution
can be reduced by as much as 90%.
• Multiple Idle Modes: The controller can also run
with its CPU core disabled, but the peripherals are
still active. In these states, power consumption can
be reduced even further, to as little as 4% of normal
operation requirements.
• On-the-fly Mode Switching: The power managed
modes are invoked by user code during operation,
allowing the user to incorporate power-saving ideas
into their application’s software design.
• Lower Consumption in Key Modules: The power
requirements for both Timer1 and the Watchdog
Timer have been reduced by up to 80%, with typical
values of 1.1 and 2.1 μA, respectively.
1.1.2 MULTIPLE OSCILLATOR OPTIONS
AND FEATURES
All of the devices in the PIC18F1220/1320 family offer
nine different oscillator options, allowing users a wide
range of choices in developing application hardware.
These include:
• Four Crystal modes, using crystals or ceramic
resonators.
• Two External Clock modes, offering the option of
using two pins (oscillator input and a divide-by-4
clock output), or one pin (oscillator input, with the
second pin reassigned as general I/O).
• Two External RC Oscillator modes, with the same
pin options as the External Clock modes.
• An internal oscillator block, which provides an
8 MHz clock (±2% accuracy) and an INTRC source
(approximately 31 kHz, stable over temperature and
VDD), as well as a range of 6 user-selectable clock
frequencies (from 125 kHz to 4 MHz) for a total of
8 clock frequencies.
Besides its availability as a clock source, the internal
oscillator block provides a stable reference source that
gives the family additional features for robust
operation:
• Fail-Safe Clock Monitor: This option constantly
monitors the main clock source against a reference
signal provided by the internal oscillator. If a clock failure
occurs, the controller is switched to the internal
oscillator block, allowing for continued low-speed
operation, or a safe application shutdown.
• Two-Speed Start-up: This option allows the internal
oscillator to serve as the clock source from Poweron
Reset, or wake-up from Sleep mode, until the
primary clock source is available. This allows for
code execution during what would otherwise be the
clock start-up interval and can even allow an application
to perform routine background activities and
return to Sleep without returning to full power
operation.
1.2 Other Special Features
• Memory Endurance: The Enhanced Flash cells for
both program memory and data EEPROM are rated
to last for many thousands of erase/write cycles –
up to 100,000 for program memory and 1,000,000
for EEPROM. Data retention without refresh is
conservatively estimated to be greater than
40 years.
• Self-programmability: These devices can write to
their own program memory spaces under internal
software control. By using a bootloader routine
located in the protected Boot Block at the top of program
memory, it becomes possible to create an
application that can update itself in the field.
• Enhanced CCP module: In PWM mode, this
module provides 1, 2 or 4 modulated outputs for
controlling half-bridge and full-bridge drivers. Other
features include auto-shutdown, for disabling PWM
outputs on interrupt or other select conditions and
auto-restart, to reactivate outputs once the condition
has cleared.
• Enhanced USART: This serial communication
module features automatic wake-up on Start bit and
automatic baud rate detection and supports RS-232,
RS-485 and LIN 1.2 protocols, making it ideally
suited for use in Local Interconnect Network (LIN)
bus applications.
• 10-bit A/D Converter: This module incorporates
programmable acquisition time, allowing for a
channel to be selected and a conversion to be
initiated without waiting for a sampling period and
thus, reduce code overhead.
• Extended Watchdog Timer (WDT): This enhanced
version incorporates a 16-bit prescaler, allowing a
time-out range from 4 ms to over 2 minutes that is
stable across operating voltage and temperature.
• PIC18F1220 • PIC18F1320PIC18F1220/1320
DS39605F-page 6 © 2007 Microchip Technology Inc.
1.3 Details on Individual Family
Members
Devices in the PIC18F1220/1320 family are available
in 18-pin, 20-pin and 28-pin packages. A block diagram
for this device family is shown in Figure 1-1.
The devices are differentiated from each other only in
the amount of on-chip Flash program memory
(4 Kbytes for the PIC18F1220 device, 8 Kbytes for the
PIC18F1320 device). These and other features are
summarized in Table 1-1.
A block diagram of the PIC18F1220/1320 device
architecture is provided in Figure 1-1. The pinouts for
this device family are listed in Table 1-2.
TABLE 1-1: DEVICE FEATURES
Features PIC18F1220 PIC18F1320
Operating Frequency DC – 40 MHz DC – 40 MHz
Program Memory (Bytes) 4096 8192
Program Memory (Instructions) 2048 4096
Data Memory (Bytes) 256 256
Data EEPROM Memory (Bytes) 256 256
Interrupt Sources 15 15
I/O Ports Ports A, B Ports A, B
Timers 4 4
Enhanced Capture/Compare/PWM Modules 1 1
Serial Communications Enhanced USART Enhanced USART
10-bit Analog-to-Digital Module 7 input channels 7 input channels
Resets (and Delays)
POR, BOR,
RESET Instruction, Stack Full,
Stack Underflow (PWRT, OST),
MCLR (optional), WDT
POR, BOR,
RESET Instruction, Stack Full,
Stack Underflow (PWRT, OST),
MCLR (optional), WDT
Programmable Low-Voltage Detect Yes Yes
Programmable Brown-out Reset Yes Yes
Instruction Set 75 Instructions 75 Instructions
Packages
18-pin SDIP
18-pin SOIC
20-pin SSOP
28-pin QFN
18-pin SDIP
18-pin SOIC
20-pin SSOP
28-pin QFN© 2007 Microchip Technology Inc. DS39605F-page 7
PIC18F1220/1320
FIGURE 1-1: PIC18F1220/1320 BLOCK DIAGRAM
Instruction
Decode &
Control
PORTA
PORTB
RA4/T0CKI
MCLR/VPP/RA5(1)
Enhanced
Timer0 Timer1 Timer2
RA3/AN3/VREF+
RA2/AN2/VREFRA1/AN1/LVDIN
RA0/AN0
Data Latch
Data RAM
Address Latch
Address<12>
12(2)
BSR FSR0
FSR1
FSR2
4 12 4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODH PRODL
8 x 8 Multiply
WREG
8
BIT OP
8 8
ALU<8>
8
Address Latch
(8 Kbytes)
Data Latch
20
21
21
16
8
8
8
inc/dec logic
21 8
Data Bus<8>
8
Instruction
12
3
ROM Latch
Timer3
Bank0, F
PCLATU
PCU
OSC2/CLKO/RA6(2)
USART
8
Register
Table Latch
Table Pointer <2>
inc/dec
logic
RB0/AN4/INT0
RB4/AN6/RX/DT/KBI0
RB1/AN5/TX/CK/INT1
RB2/P1B/INT2
RB3/CCP1/P1A
RB5/PGM/KBI1
RB6/PGC/T1OSO/
RB7/PGD/T1OSI/
OSC2/CLKI/RA7 Decode (2)
Power-up
Timer
Power-on
Reset
Watchdog
Timer
VDD, VSS
Brown-out
Reset
Precision
Reference
Voltage Low-Voltage
Programming
In-Circuit
Debugger
Oscillator
Start-up Timer
Timing
Generation
OSC1(2)
OSC2(2)
T1OSI
T1OSO
INTRC
Oscillator
Fail-Safe
Clock Monitor
Note 1: RA5 is available only when the MCLR Reset is disabled.
2: OSC1, OSC2, CLKI and CLKO are only available in select oscillator modes and when these pins are not being used as digital
I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information.
8
CCP
Enhanced
T13CKI/P1C/KBI2
Program Memory
(4 Kbytes)
PIC18F1220
PIC18F1320
A/D Converter
Data EEPROM
P1D/KBI3
MCLR(1)PIC18F1220/1320
DS39605F-page 8 © 2007 Microchip Technology Inc.
TABLE 1-2: PIC18F1220/1320 PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number
Pin
Type
Buffer
Type Description PDIP/
SOIC SSOP QFN
MCLR/VPP/RA5
MCLR
VPP
RA5
441
I
P
I
ST
—
ST
Master Clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
Programming voltage input.
Digital input.
OSC1/CLKI/RA7
OSC1
CLKI
RA7
16 18 21
I
I
I/O
ST
CMOS
ST
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source
input. ST buffer when configured in RC mode,
CMOS otherwise.
External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
CLKO
RA6
15 17 20
O
O
I/O
—
—
ST
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC, EC and INTRC modes, OSC2 pin outputs
CLKO, which has 1/4 the frequency of OSC1 and
denotes instruction cycle rate.
General purpose I/O pin.
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
1 1 26
I/O
I
ST
Analog
Digital I/O.
Analog input 0.
RA1/AN1/LVDIN
RA1
AN1
LVDIN
2 2 27
I/O
I
I
ST
Analog
Analog
Digital I/O.
Analog input 1.
Low-Voltage Detect input.
RA2/AN2/VREFRA2
AN2
VREF-
677
I/O
I
I
ST
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (low) input.
RA3/AN3/VREF+
RA3
AN3
VREF+
788
I/O
I
I
ST
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (high) input.
RA4/T0CKI
RA4
T0CKI
3 3 28
I/O
I
ST/OD
ST
Digital I/O. Open-drain when configured as output.
Timer0 external clock input.
RA5 See the MCLR/VPP/RA5 pin.
RA6 See the OSC2/CLKO/RA6 pin.
RA7 See the OSC1/CLKI/RA7 pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-drain (no P diode to VDD) © 2007 Microchip Technology Inc. DS39605F-page 9
PIC18F1220/1320
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/AN4/INT0
RB0
AN4
INT0
899
I/O
I
I
TTL
Analog
ST
Digital I/O.
Analog input 4.
External interrupt 0.
RB1/AN5/TX/CK/INT1
RB1
AN5
TX
CK
INT1
9 10 10
I/O
I
O
I/O
I
TTL
Analog
—
ST
ST
Digital I/O.
Analog input 5.
EUSART asynchronous transmit.
EUSART synchronous clock (see related RX/DT).
External interrupt 1.
RB2/P1B/INT2
RB2
P1B
INT2
17 19 23
I/O
O
I
TTL
—
ST
Digital I/O.
Enhanced CCP1/PWM output.
External interrupt 2.
RB3/CCP1/P1A
RB3
CCP1
P1A
18 20 24
I/O
I/O
O
TTL
ST
—
Digital I/O.
Capture 1 input/Compare 1 output/PWM 1 output.
Enhanced CCP1/PWM output.
RB4/AN6/RX/DT/KBI0
RB4
AN6
RX
DT
KBI0
10 11 12
I/O
I
I
I/O
I
TTL
Analog
ST
ST
TTL
Digital I/O.
Analog input 6.
EUSART asynchronous receive.
EUSART synchronous data (see related TX/CK).
Interrupt-on-change pin.
RB5/PGM/KBI1
RB5
PGM
KBI1
11 12 13
I/O
I/O
I
TTL
ST
TTL
Digital I/O.
Low-Voltage ICSP Programming enable pin.
Interrupt-on-change pin.
RB6/PGC/T1OSO/
T13CKI/P1C/KBI2
RB6
PGC
T1OSO
T13CKI
P1C
KBI2
12 13 15
I/O
I/O
O
I
O
I
TTL
ST
—
ST
—
TTL
Digital I/O.
In-Circuit Debugger and ICSP programming clock pin.
Timer1 oscillator output.
Timer1/Timer3 external clock output.
Enhanced CCP1/PWM output.
Interrupt-on-change pin.
RB7/PGD/T1OSI/
P1D/KBI3
RB7
PGD
T1OSI
P1D
KBI3
13 14 16
I/O
I/O
I
O
I
TTL
ST
CMOS
—
TTL
Digital I/O.
In-Circuit Debugger and ICSP programming data pin.
Timer1 oscillator input.
Enhanced CCP1/PWM output.
Interrupt-on-change pin.
VSS 5 5, 6 3, 5 P — Ground reference for logic and I/O pins.
VDD 14 15, 16 17, 19 P — Positive supply for logic and I/O pins.
NC — — 18 — — No connect.
TABLE 1-2: PIC18F1220/1320 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type Description PDIP/
SOIC SSOP QFN
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open-drain (no P diode to VDD) PIC18F1220/1320
DS39605F-page 10 © 2007 Microchip Technology Inc.
NOTES:© 2007 Microchip Technology Inc. DS39605F-page 11
PIC18F1220/1320
2.0 OSCILLATOR
CONFIGURATIONS
2.1 Oscillator Types
The PIC18F1220 and PIC18F1320 devices can be
operated in ten different oscillator modes. The user can
program the configuration bits, FOSC3:FOSC0, in
Configuration Register 1H to select one of these ten
modes:
1. LP Low-Power Crystal
2. XT Crystal/Resonator
3. HS High-Speed Crystal/Resonator
4. HSPLL High-Speed Crystal/Resonator
with PLL enabled
5. RC External Resistor/Capacitor with
FOSC/4 output on RA6
6. RCIO External Resistor/Capacitor with
I/O on RA6
7. INTIO1 Internal Oscillator with FOSC/4
output on RA6 and I/O on RA7
8. INTIO2 Internal Oscillator with I/O on RA6
and RA7
9. EC External Clock with FOSC/4 output
10. ECIO External Clock with I/O on RA6
2.2 Crystal Oscillator/Ceramic
Resonators
In XT, LP, HS or HSPLL Oscillator modes, a crystal or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections.
The oscillator design requires the use of a parallel cut
crystal.
FIGURE 2-1: CRYSTAL/CERAMIC
RESONATOR OPERATION
(XT, LP, HS OR HSPLL
CONFIGURATION)
TABLE 2-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Note: Use of a series cut crystal may give a
frequency out of the crystal manufacturer’s
specifications.
Typical Capacitor Values Used:
Mode Freq OSC1 OSC2
XT 455 kHz
2.0 MHz
4.0 MHz
56 pF
47 pF
33 pF
56 pF
47 pF
33 pF
HS 8.0 MHz
16.0 MHz
27 pF
22 pF
27 pF
22 pF
Capacitor values are for design guidance only.
These capacitors were tested with the resonators
listed below for basic start-up and operation. These
values are not optimized.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes following Table 2-2 for additional
information.
Resonators Used:
455 kHz 4.0 MHz
2.0 MHz 8.0 MHz
16.0 MHz
Note 1: See Table 2-1 and Table 2-2 for initial
values of C1 and C2.
2: A series resistor (RS) may be required for
AT strip cut crystals.
3: RF varies with the oscillator mode chosen.
C1(1)
C2(1)
XTAL
OSC2
OSC1
RF(3)
Sleep
To
Logic
PIC18FXXXX
RS(2)
InternalPIC18F1220/1320
DS39605F-page 12 © 2007 Microchip Technology Inc.
TABLE 2-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 2-2.
FIGURE 2-2: EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
2.3 HSPLL
A Phase Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower frequency
crystal oscillator circuit, or to clock the device up to its
highest rated frequency from a crystal oscillator. This
may be useful for customers who are concerned with
EMI due to high-frequency crystals.
The HSPLL mode makes use of the HS mode oscillator
for frequencies up to 10 MHz. A PLL then multiplies the
oscillator output frequency by 4 to produce an internal
clock frequency up to 40 MHz.
The PLL is enabled only when the oscillator configuration
bits are programmed for HSPLL mode. If
programmed for any other mode, the PLL is not
enabled.
FIGURE 2-3: PLL BLOCK DIAGRAM
Osc Type Crystal
Freq
Typical Capacitor Values
Tested:
C1 C2
LP 32 kHz 33 pF 33 pF
200 kHz 15 pF 15 pF
XT 1 MHz 33 pF 33 pF
4 MHz 27 pF 27 pF
HS 4 MHz 27 pF 27 pF
8 MHz 22 pF 22 pF
20 MHz 15 pF 15 pF
Capacitor values are for design guidance only.
These capacitors were tested with the crystals listed
below for basic start-up and operation. These values
are not optimized.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes following this table for additional
information.
Crystals Used:
32 kHz 4 MHz
200 kHz 8 MHz
1 MHz 20 MHz
Note 1: Higher capacitance increases the stability
of oscillator, but also increases the start-up
time.
2: When operating below 3V VDD, or when
using certain ceramic resonators at any
voltage, it may be necessary to use the
HS mode or switch to a crystal oscillator.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
4: RS may be required to avoid overdriving
crystals with low drive level specification.
5: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
OSC1
Open OSC2
Clock from
Ext. System PIC18FXXXX
(HS Mode) MUX
VCO
Loop
Filter
Crystal
Osc
OSC2
OSC1
PLL Enable
FIN
FOUT
SYSCLK
Phase
Comparator
HS Oscillator Enable
÷4
(from Configuration Register 1H)© 2007 Microchip Technology Inc. DS39605F-page 13
PIC18F1220/1320
2.4 External Clock Input
The EC and ECIO Oscillator modes require an external
clock source to be connected to the OSC1 pin. There is
no oscillator start-up time required after a Power-on
Reset, or after an exit from Sleep mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes, or to synchronize other
logic. Figure 2-4 shows the pin connections for the EC
Oscillator mode.
FIGURE 2-4: EXTERNAL CLOCK INPUT
OPERATION
(EC CONFIGURATION)
The ECIO Oscillator mode functions like the EC mode,
except that the OSC2 pin becomes an additional general
purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-5 shows the pin connections
for the ECIO Oscillator mode.
FIGURE 2-5: EXTERNAL CLOCK INPUT
OPERATION
(ECIO CONFIGURATION)
2.5 RC Oscillator
For timing insensitive applications, the “RC” and
“RCIO” device options offer additional cost savings.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) values
and the operating temperature. In addition to this,
the oscillator frequency will vary from unit to unit due to
normal manufacturing variation. Furthermore, the difference
in lead frame capacitance between package
types will also affect the oscillation frequency, especially
for low CEXT values. The user also needs to take
into account variation, due to tolerance of external
R and C components used. Figure 2-6 shows how the
R/C combination is connected.
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes, or to synchronize other
logic.
FIGURE 2-6: RC OSCILLATOR MODE
The RCIO Oscillator mode (Figure 2-7) functions like
the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).
FIGURE 2-7: RCIO OSCILLATOR MODE
OSC1/CLKI
FOSC/4 OSC2/CLKO
Clock from
Ext. System PIC18FXXXX
OSC1/CLKI
RA6 I/O (OSC2)
Clock from
Ext. System PIC18FXXXX
OSC2/CLKO
CEXT
REXT
PIC18FXXXX
OSC1
FOSC/4
Internal
Clock
VDD
VSS
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20 pF
CEXT
REXT
PIC18FXXXX
OSC1 Internal
Clock
VDD
VSS
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20 pF
RA6 I/O (OSC2)PIC18F1220/1320
DS39605F-page 14 © 2007 Microchip Technology Inc.
2.6 Internal Oscillator Block
The PIC18F1220/1320 devices include an internal
oscillator block, which generates two different clock
signals; either can be used as the system’s clock
source. This can eliminate the need for external
oscillator circuits on the OSC1 and/or OSC2 pins.
The main output (INTOSC) is an 8 MHz clock source,
which can be used to directly drive the system clock. It
also drives a postscaler, which can provide a range of
clock frequencies from 125 kHz to 4 MHz. The
INTOSC output is enabled when a system clock
frequency from 125 kHz to 8 MHz is selected.
The other clock source is the internal RC oscillator
(INTRC), which provides a 31 kHz output. The INTRC
oscillator is enabled by selecting the internal oscillator
block as the system clock source, or when any of the
following are enabled:
• Power-up Timer
• Fail-Safe Clock Monitor
• Watchdog Timer
• Two-Speed Start-up
These features are discussed in greater detail in
Section 19.0 “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC
direct or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (Register 2-2).
2.6.1 INTIO MODES
Using the internal oscillator as the clock source can
eliminate the need for up to two external oscillator pins,
which can then be used for digital I/O. Two distinct
configurations are available:
• In INTIO1 mode, the OSC2 pin outputs FOSC/4,
while OSC1 functions as RA7 for digital input and
output.
• In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output.
2.6.2 INTRC OUTPUT FREQUENCY
The internal oscillator block is calibrated at the factory
to produce an INTOSC output frequency of 8.0 MHz
(see Table 22-6). This changes the frequency of the
INTRC source from its nominal 31.25 kHz. Peripherals
and features that depend on the INTRC source will be
affected by this shift in frequency.
Once set during factory calibration, the INTRC
frequency will remain within ±2% as temperature and
VDD change across their full specified operating
ranges.
2.6.3 OSCTUNE REGISTER
The internal oscillator’s output has been calibrated at
the factory, but can be adjusted in the user’s application.
This is done by writing to the OSCTUNE register
(Register 2-1). The tuning sensitivity is constant
throughout the tuning range.
When the OSCTUNE register is modified, the INTOSC
and INTRC frequencies will begin shifting to the new
frequency. The INTRC clock will reach the new
frequency within 8 clock cycles (approximately
8 * 32 μs = 256 μs). The INTOSC clock will stabilize
within 1 ms. Code execution continues during this shift.
There is no indication that the shift has occurred.
Operation of features that depend on the INTRC clock
source frequency, such as the WDT, Fail-Safe Clock
Monitor and peripherals, will also be affected by the
change in frequency.© 2007 Microchip Technology Inc. DS39605F-page 15
PIC18F1220/1320
REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER
2.7 Clock Sources and Oscillator
Switching
Like previous PIC18 devices, the PIC18F1220/1320
devices include a feature that allows the system clock
source to be switched from the main oscillator to an
alternate low-frequency clock source. PIC18F1220/
1320 devices offer two alternate clock sources. When
enabled, these give additional options for switching to
the various power managed operating modes.
Essentially, there are three clock sources for these
devices:
• Primary oscillators
• Secondary oscillators
• Internal oscillator block
The primary oscillators include the External Crystal
and Resonator modes, the External RC modes, the
External Clock modes and the internal oscillator block.
The particular mode is defined on POR by the contents
of Configuration Register 1H. The details of these
modes are covered earlier in this chapter.
The secondary oscillators are those external sources
not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power managed mode.
PIC18F1220/1320 devices offer only the Timer1
oscillator as a secondary oscillator. This oscillator, in all
power managed modes, is often the time base for
functions such as a real-time clock.
Most often, a 32.768 kHz watch crystal is connected
between the RB6/T1OSO and RB7/T1OSI pins. Like
the LP mode oscillator circuit, loading capacitors are
also connected from each pin to ground. These pins
are also used during ICSP operations.
The Timer1 oscillator is discussed in greater detail in
Section 12.2 “Timer1 Oscillator”.
In addition to being a primary clock source, the internal
oscillator block is available as a power managed
mode clock source. The INTRC source is also used as
the clock source for several special features, such as
the WDT and Fail-Safe Clock Monitor.
The clock sources for the PIC18F1220/1320 devices
are shown in Figure 2-8. See Section 12.0 “Timer1
Module” for further details of the Timer1 oscillator. See
Section 19.1 “Configuration Bits” for configuration
register details.
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 TUN<5:0>: Frequency Tuning bits
011111 = Maximum frequency
• •
• •
000001
000000 = Center frequency. Oscillator module is running at the calibrated frequency.
111111
• •
• •
100000 = Minimum frequency
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownPIC18F1220/1320
DS39605F-page 16 © 2007 Microchip Technology Inc.
2.7.1 OSCILLATOR CONTROL REGISTER
The OSCCON register (Register 2-2) controls several
aspects of the system clock’s operation, both in full
power operation and in power managed modes.
The System Clock Select bits, SCS1:SCS0, select the
clock source that is used when the device is operating in
power managed modes. The available clock sources are
the primary clock (defined in Configuration Register 1H),
the secondary clock (Timer1 oscillator) and the internal
oscillator block. The clock selection has no effect until a
SLEEP instruction is executed and the device enters a
power managed mode of operation. The SCS bits are
cleared on all forms of Reset.
The Internal Oscillator Select bits, IRCF2:IRCF0, select
the frequency output of the internal oscillator block that
is used to drive the system clock. The choices are the
INTRC source, the INTOSC source (8 MHz), or one of
the six frequencies derived from the INTOSC
postscaler (125 kHz to 4 MHz). If the internal oscillator
block is supplying the system clock, changing the
states of these bits will have an immediate change on
the internal oscillator’s output.
The OSTS, IOFS and T1RUN bits indicate which clock
source is currently providing the system clock. The
OSTS indicates that the Oscillator Start-up Timer has
timed out and the primary clock is providing the system
clock in Primary Clock modes. The IOFS bit indicates
when the internal oscillator block has stabilized and is
providing the system clock in RC Clock modes or
during Two-Speed Start-ups. The T1RUN bit
(T1CON<6>) indicates when the Timer1 oscillator is
providing the system clock in Secondary Clock modes.
In power managed modes, only one of these three bits
will be set at any time. If none of these bits are set, the
INTRC is providing the system clock, or the internal
oscillator block has just started and is not yet stable.
The IDLEN bit controls the selective shutdown of the
controller’s CPU in power managed modes. The uses
of these bits are discussed in more detail in
Section 3.0 “Power Managed Modes”.
FIGURE 2-8: PIC18F1220/1320 CLOCK DIAGRAM
Note 1: The Timer1 oscillator must be enabled to
select the secondary clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the Timer1 Control register
(T1CON<3>). If the Timer1 oscillator
is not enabled, then any attempt to select
a secondary clock source when
executing a SLEEP instruction will be
ignored.
2: It is recommended that the Timer1 oscillator
be operating and stable before executing
the SLEEP instruction or a very
long delay may occur while the Timer1
oscillator starts.
PIC18F1220/1320
4 x PLL
CONFIG1H <3:0>
Secondary Oscillator
T1OSCEN
Enable
Oscillator
T1OSO
T1OSI
Clock Source Option
for Other Modules
OSC1
OSC2
Sleep
Primary Oscillator
HSPLL
LP, XT, HS, RC, EC
T1OSC
CPU
Peripherals
IDLEN
Postscaler
MUX
MUX
8
4 MHz
2 MHz
1 MHz
500 kHz
125 kHz
250 kHz
OSCCON<6:4>
111
110
101
100
011
010
001
000 31 kHz
INTRC
Source
Internal
Oscillator
Block
WDT, FSCM
8 MHz
Internal Oscillator
(INTOSC)
OSCCON<6:4>
Clock
Control OSCCON<1:0>© 2007 Microchip Technology Inc. DS39605F-page 17
PIC18F1220/1320
REGISTER 2-2: OSCCON REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R(1) R-0 R/W-0 R/W-0
IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0
bit 7 bit 0
bit 7 IDLEN: Idle Enable bits
1 = Idle mode enabled; CPU core is not clocked in power managed modes
0 = Run mode enabled; CPU core is clocked in Run modes, but not Sleep mode
bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits
111 = 8 MHz (8 MHz source drives clock directly)
110 = 4 MHz
101 = 2 MHz
100 = 1 MHz
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (INTRC source drives clock directly)
bit 3 OSTS: Oscillator Start-up Time-out Status bit
1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running
0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready
bit 2 IOFS: INTOSC Frequency Stable bit
1 = INTOSC frequency is stable
0 = INTOSC frequency is not stable
bit 1-0 SCS1:SCS0: System Clock Select bits
1x = Internal oscillator block (RC modes)
01 = Timer1 oscillator (Secondary modes)
00 = Primary oscillator (Sleep and PRI_IDLE modes)
Note 1: Depends on state of the IESO bit in Configuration Register 1H.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownPIC18F1220/1320
DS39605F-page 18 © 2007 Microchip Technology Inc.
2.7.2 OSCILLATOR TRANSITIONS
The PIC18F1220/1320 devices contain circuitry to
prevent clocking “glitches” when switching between
clock sources. A short pause in the system clock
occurs during the clock switch. The length of this pause
is between 8 and 9 clock periods of the new clock
source. This ensures that the new clock source is
stable and that its pulse width will not be less than the
shortest pulse width of the two clock sources.
Clock transitions are discussed in greater detail in
Section 3.1.2 “Entering Power Managed Modes”.
2.8 Effects of Power Managed Modes
on the Various Clock Sources
When the device executes a SLEEP instruction, the
system is switched to one of the power managed
modes, depending on the state of the IDLEN and
SCS1:SCS0 bits of the OSCCON register. See
Section 3.0 “Power Managed Modes” for details.
When PRI_IDLE mode is selected, the designated primary
oscillator continues to run without interruption.
For all other power managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin, if used by the oscillator) will stop oscillating.
In Secondary Clock modes (SEC_RUN and
SEC_IDLE), the Timer1 oscillator is operating and
providing the system clock. The Timer1 oscillator may
also run in all power managed modes if required to
clock Timer1 or Timer3.
In Internal Oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the system clock
source. The INTRC output can be used directly to
provide the system clock and may be enabled to
support various special features, regardless of the
power managed mode (see Section 19.2 “Watchdog
Timer (WDT)” through Section 19.4 “Fail-Safe Clock
Monitor”). The INTOSC output at 8 MHz may be used
directly to clock the system, or may be divided down
first. The INTOSC output is disabled if the system clock
is provided directly from the INTRC output.
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a realtime
clock. Other features may be operating that do not
require a system clock source (i.e., INTn pins, A/D
conversions and others).
2.9 Power-up Delays
Power-up delays are controlled by two timers, so that
no external Reset circuitry is required for most applications.
The delays ensure that the device is kept in
Reset until the device power supply is stable under normal
circumstances and the primary clock is operating
and stable. For additional information on power-up
delays, see Sections 4.1 through 4.5.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (parameter 33,
Table 22-8) if enabled in Configuration Register 2L.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (LP, XT and HS modes). The
OST does this by counting 1024 oscillator cycles
before allowing the oscillator to clock the device.
When the HSPLL Oscillator mode is selected, the
device is kept in Reset for an additional 2 ms following
the HS mode OST delay, so the PLL can lock to the
incoming clock frequency.
There is a delay of 5 to 10 μs following POR while the
controller becomes ready to execute instructions. This
delay runs concurrently with any other delays. This
may be the only delay that occurs when any of the EC,
RC or INTIO modes are used as the primary clock
source.
TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Oscillator Mode OSC1 Pin OSC2 Pin
RC, INTIO1 Floating, external resistor should pull high At logic low (clock/4 output)
RCIO, INTIO2 Floating, external resistor should pull high Configured as PORTA, bit 6
ECIO Floating, pulled by external clock Configured as PORTA, bit 6
EC Floating, pulled by external clock At logic low (clock/4 output)
LP, XT and HS Feedback inverter disabled at quiescent
voltage level
Feedback inverter disabled at quiescent
voltage level
Note: See Table 4-1 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset.© 2007 Microchip Technology Inc. DS39605F-page 19
PIC18F1220/1320
3.0 POWER MANAGED MODES
The PIC18F1220/1320 devices offer a total of six operating
modes for more efficient power management
(see Table 3-1). These provide a variety of options for
selective power conservation in applications where
resources may be limited (i.e., battery powered
devices).
There are three categories of power managed modes:
• Sleep mode
• Idle modes
• Run modes
These categories define which portions of the device
are clocked and sometimes, what speed. The Run and
Idle modes may use any of the three available clock
sources (primary, secondary or INTOSC multiplexer);
the Sleep mode does not use a clock source.
The clock switching feature offered in other PIC18
devices (i.e., using the Timer1 oscillator in place of the
primary oscillator) and the Sleep mode offered by all
PIC® devices (where all system clocks are stopped) are
both offered in the PIC18F1220/1320 devices
(SEC_RUN and Sleep modes, respectively). However,
additional power managed modes are available that
allow the user greater flexibility in determining what
portions of the device are operating. The power managed
modes are event driven; that is, some specific
event must occur for the device to enter or (more
particularly) exit these operating modes.
For PIC18F1220/1320 devices, the power managed
modes are invoked by using the existing SLEEP
instruction. All modes exit to PRI_RUN mode when triggered
by an interrupt, a Reset or a WDT time-out
(PRI_RUN mode is the normal full power execution
mode; the CPU and peripherals are clocked by the primary
oscillator source). In addition, power managed
Run modes may also exit to Sleep mode, or their
corresponding Idle mode.
3.1 Selecting Power Managed Modes
Selecting a power managed mode requires deciding if
the CPU is to be clocked or not and selecting a clock
source. The IDLEN bit controls CPU clocking, while the
SCS1:SCS0 bits select a clock source. The individual
modes, bit settings, clock sources and affected
modules are summarized in Table 3-1.
3.1.1 CLOCK SOURCES
The clock source is selected by setting the SCS bits of
the OSCCON register (Register 2-2). Three clock
sources are available for use in power managed Idle
modes: the primary clock (as configured in Configuration
Register 1H), the secondary clock (Timer1 oscillator)
and the internal oscillator block. The secondary and
internal oscillator block sources are available for the
power managed modes (PRI_RUN mode is the normal
full power execution mode; the CPU and peripherals are
clocked by the primary oscillator source).
TABLE 3-1: POWER MANAGED MODES
Mode
OSCCON Bits Module Clocking
Available Clock and Oscillator Source IDLEN
<7>
SCS1:SCS0
<1:0> CPU Peripherals
Sleep 0 00 Off Off None – All clocks are disabled
PRI_RUN 0 00 Clocked Clocked Primary – LP, XT, HS, HSPLL, RC, EC, INTRC(1)
This is the normal full power execution mode.
SEC_RUN 0 01 Clocked Clocked Secondary – Timer1 Oscillator
RC_RUN 0 1x Clocked Clocked Internal Oscillator Block(1)
PRI_IDLE 1 00 Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC
SEC_IDLE 1 01 Off Clocked Secondary – Timer1 Oscillator
RC_IDLE 1 1x Off Clocked Internal Oscillator Block(1)
Note 1: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.PIC18F1220/1320
DS39605F-page 20 © 2007 Microchip Technology Inc.
3.1.2 ENTERING POWER MANAGED
MODES
In general, entry, exit and switching between power
managed clock sources requires clock source
switching. In each case, the sequence of events is the
same.
Any change in the power managed mode begins with
loading the OSCCON register and executing a SLEEP
instruction. The SCS1:SCS0 bits select one of three
power managed clock sources; the primary clock (as
defined in Configuration Register 1H), the secondary
clock (the Timer1 oscillator) and the internal oscillator
block (used in RC modes). Modifying the SCS bits will
have no effect until a SLEEP instruction is executed.
Entry to the power managed mode is triggered by the
execution of a SLEEP instruction.
Figure 3-5 shows how the system is clocked while
switching from the primary clock to the Timer1 oscillator.
When the SLEEP instruction is executed, clocks to
the device are stopped at the beginning of the next
instruction cycle. Eight clock cycles from the new clock
source are counted to synchronize with the new clock
source. After eight clock pulses from the new clock
source are counted, clocks from the new clock source
resume clocking the system. The actual length of the
pause is between eight and nine clock periods from the
new clock source. This ensures that the new clock
source is stable and that its pulse width will not be less
than the shortest pulse width of the two clock sources.
Three bits indicate the current clock source: OSTS and
IOFS in the OSCCON register and T1RUN in the
T1CON register. Only one of these bits will be set while
in a power managed mode. When the OSTS bit is set,
the primary clock is providing the system clock. When
the IOFS bit is set, the INTOSC output is providing a
stable 8 MHz clock source and is providing the system
clock. When the T1RUN bit is set, the Timer1 oscillator
is providing the system clock. If none of these bits are
set, then either the INTRC clock source is clocking the
system, or the INTOSC source is not yet stable.
If the internal oscillator block is configured as the primary
clock source in Configuration Register 1H, then
both the OSTS and IOFS bits may be set when in
PRI_RUN or PRI_IDLE modes. This indicates that the
primary clock (INTOSC output) is generating a stable
8 MHz output. Entering an RC power managed mode
(same frequency) would clear the OSTS bit.
3.1.3 MULTIPLE SLEEP COMMANDS
The power managed mode that is invoked with the
SLEEP instruction is determined by the settings of the
IDLEN and SCS bits at the time the instruction is executed.
If another SLEEP instruction is executed, the
device will enter the power managed mode specified by
these same bits at that time. If the bits have changed,
the device will enter the new power managed mode
specified by the new bit settings.
3.1.4 COMPARISONS BETWEEN RUN
AND IDLE MODES
Clock source selection for the Run modes is identical to
the corresponding Idle modes. When a SLEEP instruction
is executed, the SCS bits in the OSCCON register
are used to switch to a different clock source. As a
result, if there is a change of clock source at the time a
SLEEP instruction is executed, a clock switch will occur.
In Idle modes, the CPU is not clocked and is not running.
In Run modes, the CPU is clocked and executing
code. This difference modifies the operation of the
WDT when it times out. In Idle modes, a WDT time-out
results in a wake from power managed modes. In Run
modes, a WDT time-out results in a WDT Reset (see
Table 3-2).
During a wake-up from an Idle mode, the CPU starts
executing code by entering the corresponding Run
mode until the primary clock becomes ready. When the
primary clock becomes ready, the clock source is automatically
switched to the primary clock. The IDLEN and
SCS bits are unchanged during and after the wake-up.
Figure 3-2 shows how the system is clocked during the
clock source switch. The example assumes the device
was in SEC_IDLE or SEC_RUN mode when a wake is
triggered (the primary clock was configured in HSPLL
mode).
Note 1: Caution should be used when modifying a
single IRCF bit. If VDD is less than 3V, it is
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
2: Executing a SLEEP instruction does not
necessarily place the device into Sleep
mode; executing a SLEEP instruction is
simply a trigger to place the controller into
a power managed mode selected by the
OSCCON register, one of which is Sleep
mode.© 2007 Microchip Technology Inc. DS39605F-page 21
PIC18F1220/1320
3.2 Sleep Mode
The power managed Sleep mode in the PIC18F1220/
1320 devices is identical to that offered in all other PIC
microcontrollers. It is entered by clearing the IDLEN
and SCS1:SCS0 bits (this is the Reset state) and
executing the SLEEP instruction. This shuts down the
primary oscillator and the OSTS bit is cleared (see
Figure 3-1).
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the system will not be clocked
until the primary clock source becomes ready (see
Figure 3-2), or it will be clocked from the internal
oscillator block if either the Two-Speed Start-up or the
Fail-Safe Clock Monitor are enabled (see Section 19.0
“Special Features of the CPU”). In either case, the
OSTS bit is set when the primary clock is providing the
system clocks. The IDLEN and SCS bits are not
affected by the wake-up.
3.3 Idle Modes
The IDLEN bit allows the microcontroller’s CPU to be
selectively shut down while the peripherals continue to
operate. Clearing IDLEN allows the CPU to be clocked.
Setting IDLEN disables clocks to the CPU, effectively
stopping program execution (see Register 2-2). The
peripherals continue to be clocked regardless of the
setting of the IDLEN bit.
There is one exception to how the IDLEN bit functions.
When all the low-power OSCCON bits are cleared
(IDLEN:SCS1:SCS0 = 000), the device enters Sleep
mode upon the execution of the SLEEP instruction. This
is both the Reset state of the OSCCON register and the
setting that selects Sleep mode. This maintains
compatibility with other PIC devices that do not offer
power managed modes.
If the Idle Enable bit, IDLEN (OSCCON<7>), is set to a
‘1’ when a SLEEP instruction is executed, the
peripherals will be clocked from the clock source
selected using the SCS1:SCS0 bits; however, the CPU
will not be clocked. Since the CPU is not executing
instructions, the only exits from any of the Idle modes
are by interrupt, WDT time-out or a Reset.
When a wake event occurs, CPU execution is delayed
approximately 10 μs while it becomes ready to execute
code. When the CPU begins executing code, it is
clocked by the same clock source as was selected in
the power managed mode (i.e., when waking from
RC_IDLE mode, the internal oscillator block will clock
the CPU and peripherals until the primary clock source
becomes ready – this is essentially RC_RUN mode).
This continues until the primary clock source becomes
ready. When the primary clock becomes ready, the
OSTS bit is set and the system clock source is
switched to the primary clock (see Figure 3-4). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT
time-out will result in a WDT wake-up to full power
operation.
TABLE 3-2: COMPARISON BETWEEN POWER MANAGED MODES
Power
Managed
Mode
CPU is Clocked by ... WDT Time-out
causes a ...
Peripherals are
Clocked by ...
Clock during Wake-up
(while primary becomes
ready)
Sleep Not clocked (not running) Wake-up Not clocked None or INTOSC multiplexer
if Two-Speed Start-up or
Fail-Safe Clock Monitor are
enabled
Any Idle mode Not clocked (not running) Wake-up Primary, Secondary or
INTOSC multiplexer
Unchanged from Idle mode
(CPU operates as in
corresponding Run mode)
Any Run mode Primary or secondary
clocks or INTOSC
multiplexer
Reset Primary or secondary
clocks or INTOSC
multiplexer
Unchanged from Run modePIC18F1220/1320
DS39605F-page 22 © 2007 Microchip Technology Inc.
FIGURE 3-1: TIMING TRANSITION FOR ENTRY TO SLEEP MODE
FIGURE 3-2: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q2 Q3 Q4
OSC1
Peripheral
Sleep
Program
Q1 Q1
Counter
Clock
CPU
Clock
PC PC + 2
Q3 Q4 Q1 Q2
OSC1
Peripheral
Program PC
PLL Clock
Q3 Q4
Output
CPU Clock
Q1 Q2 Q3 Q4 Q1 Q2
Clock
Counter PC + 6 PC + 8
Q1 Q2 Q3 Q4
Wake Event
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
TOST(1) TPLL(1)
OSTS bit Set
PC + 2 PC + 4© 2007 Microchip Technology Inc. DS39605F-page 23
PIC18F1220/1320
3.3.1 PRI_IDLE MODE
This mode is unique among the three Low-Power Idle
modes, in that it does not disable the primary system
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm up” or transition from another
oscillator.
PRI_IDLE mode is entered by setting the IDLEN bit,
clearing the SCS bits and executing a SLEEP instruction.
Although the CPU is disabled, the peripherals
continue to be clocked from the primary clock source
specified in Configuration Register 1H. The OSTS bit
remains set in PRI_IDLE mode (see Figure 3-3).
When a wake event occurs, the CPU is clocked from
the primary clock source. A delay of approximately
10 μs is required between the wake event and code
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the wakeup,
the OSTS bit remains set. The IDLEN and SCS bits
are not affected by the wake-up (see Figure 3-4).
FIGURE 3-3: TRANSITION TIMING TO PRI_IDLE MODE
FIGURE 3-4: TRANSITION TIMING FOR WAKE FROM PRI_IDLE MODE
Q1
Peripheral
Program PC PC + 2
OSC1
Q3 Q4 Q1
CPU Clock
Clock
Counter
Q2
OSC1
Peripheral
Program PC
CPU Clock
PC + 2
Q1 Q3 Q4
Clock
Counter
Q2
Wake Event
CPU Start-up DelayPIC18F1220/1320
DS39605F-page 24 © 2007 Microchip Technology Inc.
3.3.2 SEC_IDLE MODE
In SEC_IDLE mode, the CPU is disabled, but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered by setting the Idle bit,
modifying bits, SCS1:SCS0 = 01 and executing a
SLEEP instruction. When the clock source is switched
(see Figure 3-5) to the Timer1 oscillator, the primary
oscillator is shut down, the OSTS bit is cleared and the
T1RUN bit is set.
When a wake event occurs, the peripherals continue to
be clocked from the Timer1 oscillator. After a 10 μs
delay following the wake event, the CPU begins executing
code, being clocked by the Timer1 oscillator. The
microcontroller operates in SEC_RUN mode until the
primary clock becomes ready. When the primary clock
becomes ready, a clock switchback to the primary clock
occurs (see Figure 3-6). When the clock switch is complete,
the T1RUN bit is cleared, the OSTS bit is set and
the primary clock is providing the system clock. The
IDLEN and SCS bits are not affected by the wake-up.
The Timer1 oscillator continues to run.
FIGURE 3-5: TIMING TRANSITION FOR ENTRY TO SEC_IDLE MODE
FIGURE 3-6: TIMING TRANSITION FOR WAKE FROM SEC_RUN MODE (HSPLL)
Note: The Timer1 oscillator should already be
running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, peripheral clocks will be delayed
until the oscillator has started; in such situations,
initial oscillator operation is far
from stable and unpredictable operation
may result.
Q2 Q3 Q4
OSC1
Peripheral
Program
Q1
T1OSI
Q1
Counter
Clock
CPU
Clock
PC PC + 2
12345678
Clock Transition
Q1 Q3 Q4
OSC1
Peripheral
Program PC PC + 2
T1OSI
PLL Clock
Q1
PC + 6
Q2
Output
Q3 Q4 Q1
CPU Clock
PC + 4
Clock
Counter
Q2 Q2 Q3
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
Wake from Interrupt Event
TPLL(1)
1 2 3 45678
Clock Transition
OSTS bit Set
TOST(1)© 2007 Microchip Technology Inc. DS39605F-page 25
PIC18F1220/1320
3.3.3 RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled, but the peripherals
continue to be clocked from the internal oscillator
block using the INTOSC multiplexer. This mode allows
for controllable power conservation during Idle periods.
This mode is entered by setting the IDLEN bit, setting
SCS1 (SCS0 is ignored) and executing a SLEEP
instruction. The INTOSC multiplexer may be used to
select a higher clock frequency by modifying the IRCF
bits before executing the SLEEP instruction. When the
clock source is switched to the INTOSC multiplexer
(see Figure 3-7), the primary oscillator is shut down
and the OSTS bit is cleared.
If the IRCF bits are set to a non-zero value (thus,
enabling the INTOSC output), the IOFS bit becomes
set after the INTOSC output becomes stable, in about
1 ms. Clocks to the peripherals continue while the
INTOSC source stabilizes. If the IRCF bits were
previously at a non-zero value before the SLEEP
instruction was executed and the INTOSC source was
already stable, the IOFS bit will remain set. If the IRCF
bits are all clear, the INTOSC output is not enabled and
the IOFS bit will remain clear; there will be no indication
of the current clock source.
When a wake event occurs, the peripherals continue to
be clocked from the INTOSC multiplexer. After a 10 μs
delay following the wake event, the CPU begins executing
code, being clocked by the INTOSC multiplexer.
The microcontroller operates in RC_RUN mode until
the primary clock becomes ready. When the primary
clock becomes ready, a clock switchback to the primary
clock occurs (see Figure 3-8). When the clock switch is
complete, the IOFS bit is cleared, the OSTS bit is set
and the primary clock is providing the system clock.
The IDLEN and SCS bits are not affected by the wakeup.
The INTRC source will continue to run if either the
WDT or the Fail-Safe Clock Monitor is enabled.
FIGURE 3-7: TIMING TRANSITION TO RC_IDLE MODE
FIGURE 3-8: TIMING TRANSITION FOR WAKE FROM RC_RUN MODE (RC_RUN TO PRI_RUN)
Q2 Q3 Q4
OSC1
Peripheral
Program
Q1
INTRC
Q1
Counter
Clock
CPU
Clock
PC PC + 2
12345678
Clock Transition
Q1 Q3 Q4
OSC1
Peripheral
Program PC PC + 2
INTOSC
PLL Clock
Q1
PC + 6
Q2
Output
Q3 Q4 Q1
CPU Clock
PC + 4
Clock
Counter
Q2 Q2 Q3
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
Wake from Interrupt Event
TOST(1) TPLL(1)
12345678
Clock Transition
OSTS bit Set
Multiplexer
Q4PIC18F1220/1320
DS39605F-page 26 © 2007 Microchip Technology Inc.
3.4 Run Modes
If the IDLEN bit is clear when a SLEEP instruction is
executed, the CPU and peripherals are both clocked
from the source selected using the SCS1:SCS0 bits.
While these operating modes may not afford the power
conservation of Idle or Sleep modes, they do allow the
device to continue executing instructions by using a
lower frequency clock source. RC_RUN mode also
offers the possibility of executing code at a frequency
greater than the primary clock.
Wake-up from a power managed Run mode can be
triggered by an interrupt, or any Reset, to return to full
power operation. As the CPU is executing code in Run
modes, several additional exits from Run modes are
possible. They include exit to Sleep mode, exit to a corresponding
Idle mode and exit by executing a RESET
instruction. While the device is in any of the power
managed Run modes, a WDT time-out will result in a
WDT Reset.
3.4.1 PRI_RUN MODE
The PRI_RUN mode is the normal full power execution
mode. If the SLEEP instruction is never executed, the
microcontroller operates in this mode (a SLEEP instruction
is executed to enter all other power managed
modes). All other power managed modes exit to
PRI_RUN mode when an interrupt or WDT time-out
occur.
There is no entry to PRI_RUN mode. The OSTS bit is
set. The IOFS bit may be set if the internal oscillator
block is the primary clock source (see Section 2.7.1
“Oscillator Control Register”).
3.4.2 SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the
“clock switching” feature offered in other PIC18
devices. In this mode, the CPU and peripherals are
clocked from the Timer1 oscillator. This gives users the
option of lower power consumption while still using a
high accuracy clock source.
SEC_RUN mode is entered by clearing the IDLEN bit,
setting SCS1:SCS0 = 01 and executing a SLEEP
instruction. The system clock source is switched to the
Timer1 oscillator (see Figure 3-9), the primary oscillator
is shut down, the T1RUN bit (T1CON<6>) is set and
the OSTS bit is cleared.
When a wake event occurs, the peripherals and CPU
continue to be clocked from the Timer1 oscillator while
the primary clock is started. When the primary clock
becomes ready, a clock switchback to the primary clock
occurs (see Figure 3-6). When the clock switch is complete,
the T1RUN bit is cleared, the OSTS bit is set and
the primary clock is providing the system clock. The
IDLEN and SCS bits are not affected by the wake-up.
The Timer1 oscillator continues to run.
Firmware can force an exit from SEC_RUN mode. By
clearing the T1OSCEN bit (T1CON<3>), an exit from
SEC_RUN back to normal full power operation is triggered.
The Timer1 oscillator will continue to run and
provide the system clock, even though the T1OSCEN
bit is cleared. The primary clock is started. When the
primary clock becomes ready, a clock switchback to the
primary clock occurs (see Figure 3-6). When the clock
switch is complete, the Timer1 oscillator is disabled, the
T1RUN bit is cleared, the OSTS bit is set and the primary
clock is providing the system clock. The IDLEN
and SCS bits are not affected by the wake-up.
FIGURE 3-9: TIMING TRANSITION FOR ENTRY TO SEC_RUN MODE
Note: The Timer1 oscillator should already be
running prior to entering SEC_RUN mode.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_RUN mode will not occur. If the
Timer1 oscillator is enabled, but not yet
running, system clocks will be delayed
until the oscillator has started; in such
situations, initial oscillator operation is far
from stable and unpredictable operation
may result.
Q2 Q3 Q4
OSC1
Peripheral
Program
Q1
T1OSI
Q1
Counter
Clock
CPU
Clock
PC PC + 2
12345678
Clock Transition
Q2 Q3 Q4 Q1 Q2 Q3
PC + 2© 2007 Microchip Technology Inc. DS39605F-page 27
PIC18F1220/1320
3.4.3 RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer and the primary clock is shut
down. When using the INTRC source, this mode provides
the best power conservation of all the Run
modes, while still executing code. It works well for user
applications which are not highly timing sensitive, or do
not require high-speed clocks at all times.
If the primary clock source is the internal oscillator
block (either of the INTIO1 or INTIO2 oscillators), there
are no distinguishable differences between PRI_RUN
and RC_RUN modes during execution. However, a
clock switch delay will occur during entry to and exit
from RC_RUN mode. Therefore, if the primary clock
source is the internal oscillator block, the use of
RC_RUN mode is not recommended.
This mode is entered by clearing the IDLEN bit, setting
SCS1 (SCS0 is ignored) and executing a SLEEP
instruction. The IRCF bits may select the clock
frequency before the SLEEP instruction is executed.
When the clock source is switched to the INTOSC
multiplexer (see Figure 3-10), the primary oscillator is
shut down and the OSTS bit is cleared.
The IRCF bits may be modified at any time to immediately
change the system clock speed. Executing a
SLEEP instruction is not required to select a new clock
frequency from the INTOSC multiplexer.
If the IRCF bits are all clear, the INTOSC output is not
enabled and the IOFS bit will remain clear; there will be
no indication of the current clock source. The INTRC
source is providing the system clocks.
If the IRCF bits are changed from all clear (thus,
enabling the INTOSC output), the IOFS bit becomes
set after the INTOSC output becomes stable. Clocks to
the system continue while the INTOSC source
stabilizes, in approximately 1 ms.
If the IRCF bits were previously at a non-zero value
before the SLEEP instruction was executed and the
INTOSC source was already stable, the IOFS bit will
remain set.
When a wake event occurs, the system continues to be
clocked from the INTOSC multiplexer while the primary
clock is started. When the primary clock becomes
ready, a clock switch to the primary clock occurs (see
Figure 3-8). When the clock switch is complete, the
IOFS bit is cleared, the OSTS bit is set and the primary
clock is providing the system clock. The IDLEN and
SCS bits are not affected by the wake-up. The INTRC
source will continue to run if either the WDT or the
Fail-Safe Clock Monitor is enabled.
FIGURE 3-10: TIMING TRANSITION TO RC_RUN MODE
Note: Caution should be used when modifying a
single IRCF bit. If VDD is less than 3V, it is
possible to select a higher clock speed
than is supported by the low VDD.
Improper device operation may result if
the VDD/FOSC specifications are violated.
Q1 Q2 Q3
OSC1
Peripheral
Program
Q4
INTRC
Q4
Counter
Clock
CPU
Clock
PC PC + 2
12345678
Clock Transition
Q1 Q2 Q3 Q4 Q1 Q2 Q3
PC + 4PIC18F1220/1320
DS39605F-page 28 © 2007 Microchip Technology Inc.
3.4.4 EXIT TO IDLE MODE
An exit from a power managed Run mode to its
corresponding Idle mode is executed by setting the
IDLEN bit and executing a SLEEP instruction. The CPU
is halted at the beginning of the instruction following the
SLEEP instruction. There are no changes to any of the
clock source status bits (OSTS, IOFS or T1RUN).
While the CPU is halted, the peripherals continue to be
clocked from the previously selected clock source.
3.4.5 EXIT TO SLEEP MODE
An exit from a power managed Run mode to Sleep
mode is executed by clearing the IDLEN and
SCS1:SCS0 bits and executing a SLEEP instruction.
The code is no different than the method used to invoke
Sleep mode from the normal operating (full power)
mode.
The primary clock and internal oscillator block are
disabled. The INTRC will continue to operate if the
WDT is enabled. The Timer1 oscillator will continue to
run, if enabled in the T1CON register (Register 12-1).
All clock source status bits are cleared (OSTS, IOFS
and T1RUN).
3.5 Wake from Power Managed Modes
An exit from any of the power managed modes is triggered
by an interrupt, a Reset or a WDT time-out. This
section discusses the triggers that cause exits from
power managed modes. The clocking subsystem
actions are discussed in each of the power managed
modes (see Sections 3.2 through 3.4).
Device behavior during Low-Power mode exits is
summarized in Table 3-3.
3.5.1 EXIT BY INTERRUPT
Any of the available interrupt sources can cause the
device to exit a power managed mode and resume full
power operation. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in
one of the INTCON or PIE registers. The exit sequence
is initiated when the corresponding interrupt flag bit is
set. On all exits from Low-Power mode by interrupt,
code execution branches to the interrupt vector if the
GIE/GIEH bit (INTCON<7>) is set. Otherwise, code
execution continues or resumes without branching
(see Section 9.0 “Interrupts”).
Note: If application code is timing sensitive, it
should wait for the OSTS bit to become set
before continuing. Use the interval during
the low-power exit sequence (before
OSTS is set) to perform timing insensitive
“housekeeping” tasks.© 2007 Microchip Technology Inc. DS39605F-page 29
PIC18F1220/1320
TABLE 3-3: ACTIVITY AND EXIT DELAY ON WAKE FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Clock in Power
Managed Mode
Primary System
Clock
Power
Managed
Mode Exit
Delay
Clock Ready
Status Bit
(OSCCON)
Activity during Wake-up from
Power Managed Mode
Exit by Interrupt Exit by Reset
Primary System
Clock
(PRI_IDLE mode)
LP, XT, HS
5-10 μs(5)
OSTS CPU and peripherals
clocked by primary
clock and executing
instructions.
Not clocked or
Two-Speed Start-up
(if enabled)(3). HSPLL
EC, RC, INTRC(1) —
INTOSC(2) IOFS
T1OSC or
INTRC(1)
LP, XT, HS OST OSTS CPU and peripherals
clocked by selected
power managed mode
clock and executing
instructions until
primary clock source
becomes ready.
HSPLL OST + 2 ms
EC, RC, INTRC(1) 5-10 μs(5) —
INTOSC(2) 1 ms(4) IOFS
INTOSC(2)
LP, XT, HS OST OSTS
HSPLL OST + 2 ms
EC, RC, INTRC(1) 5-10 μs(5) —
INTOSC(2) None IOFS
Sleep mode
LP, XT, HS OST OSTS
Not clocked or
Two-Speed Start-up (if
enabled) until primary
clock source becomes
ready(3).
HSPLL OST + 2 ms
EC, RC, INTRC(1) 5-10 μs(5) —
INTOSC(2) 1 ms(4) IOFS
Note 1: In this instance, refers specifically to the INTRC clock source.
2: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
3: Two-Speed Start-up is covered in greater detail in Section 19.3 “Two-Speed Start-up”.
4: Execution continues during the INTOSC stabilization period.
5: Required delay when waking from Sleep and all Idle modes. This delay runs concurrently with any other
required delays (see Section 3.3 “Idle Modes”).PIC18F1220/1320
DS39605F-page 30 © 2007 Microchip Technology Inc.
3.5.2 EXIT BY RESET
Normally, the device is held in Reset by the Oscillator
Start-up Timer (OST) until the primary clock (defined in
Configuration Register 1H) becomes ready. At that
time, the OSTS bit is set and the device begins
executing code.
Code execution can begin before the primary clock
becomes ready. If either the Two-Speed Start-up (see
Section 19.3 “Two-Speed Start-up”) or Fail-Safe
Clock Monitor (see Section 19.4 “Fail-Safe Clock
Monitor”) are enabled in Configuration Register 1H,
the device may begin execution as soon as the Reset
source has cleared. Execution is clocked by the
INTOSC multiplexer driven by the internal oscillator
block. Since the OSCCON register is cleared following
all Resets, the INTRC clock source is selected. A
higher speed clock may be selected by modifying the
IRCF bits in the OSCCON register. Execution is
clocked by the internal oscillator block until either the
primary clock becomes ready, or a power managed
mode is entered before the primary clock becomes
ready; the primary clock is then shut down.
3.5.3 EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions, depending
on which power managed mode the device is in when
the time-out occurs.
If the device is not executing code (all Idle modes and
Sleep mode), the time-out will result in a wake from the
power managed mode (see Sections 3.2 through 3.4).
If the device is executing code (all Run modes), the
time-out will result in a WDT Reset (see Section 19.2
“Watchdog Timer (WDT)”).
The WDT timer and postscaler are cleared by
executing a SLEEP or CLRWDT instruction, the loss of a
currently selected clock source (if the Fail-Safe Clock
Monitor is enabled) and modifying the IRCF bits in the
OSCCON register if the internal oscillator block is the
system clock source.
3.5.4 EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
Certain exits from power managed modes do not
invoke the OST at all. These are:
• PRI_IDLE mode, where the primary clock source
is not stopped; or
• the primary clock source is not any of LP, XT, HS
or HSPLL modes.
In these cases, the primary clock source either does
not require an oscillator start-up delay, since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC and INTIO
Oscillator modes).
However, a fixed delay (approximately 10 μs) following
the wake event is required when leaving Sleep and Idle
modes. This delay is required for the CPU to prepare
for execution. Instruction execution resumes on the first
clock cycle following this delay.
3.6 INTOSC Frequency Drift
The factory calibrates the internal oscillator block
output (INTOSC) for 8 MHz (see Table 22-6). However,
this frequency may drift as VDD or temperature
changes, which can affect the controller operation in a
variety of ways.
It is possible to adjust the INTOSC frequency by
modifying the value in the OSCTUNE register
(Register 2-1). This has the side effect that the INTRC
clock source frequency is also affected. However, the
features that use the INTRC source often do not require
an exact frequency. These features include the Fail-Safe
Clock Monitor, the Watchdog Timer and the RC_RUN/
RC_IDLE modes when the INTRC clock source is
selected.
Being able to adjust the INTOSC requires knowing
when an adjustment is required, in which direction it
should be made and in some cases, how large a
change is needed. Three examples follow but other
techniques may be used.© 2007 Microchip Technology Inc. DS39605F-page 31
PIC18F1220/1320
3.6.1 EXAMPLE – EUSART
An adjustment may be indicated when the EUSART
begins to generate framing errors, or receives data with
errors while in Asynchronous mode. Framing errors
indicate that the system clock frequency is too high –
try decrementing the value in the OSCTUNE register to
reduce the system clock frequency. Errors in data may
suggest that the system clock speed is too low –
increment OSCTUNE.
3.6.2 EXAMPLE – TIMERS
This technique compares system clock speed to some
reference clock. Two timers may be used; one timer is
clocked by the peripheral clock, while the other is
clocked by a fixed reference source, such as the
Timer1 oscillator.
Both timers are cleared, but the timer clocked by the
reference generates interrupts. When an interrupt
occurs, the internally clocked timer is read and both
timers are cleared. If the internally clocked timer value
is greater than expected, then the internal oscillator
block is running too fast – decrement OSCTUNE.
3.6.3 EXAMPLE – CCP IN CAPTURE
MODE
A CCP module can use free running Timer1 (or
Timer3), clocked by the internal oscillator block and an
external event with a known period (i.e., AC power
frequency). The time of the first event is captured in the
CCPRxH:CCPRxL registers and is recorded for use
later. When the second event causes a capture, the
time of the first event is subtracted from the time of the
second event. Since the period of the external event is
known, the time difference between events can be
calculated.
If the measured time is much greater than the
calculated time, the internal oscillator block is running
too fast – decrement OSCTUNE. If the measured time
is much less than the calculated time, the internal
oscillator block is running too slow – increment
OSCTUNE.PIC18F1220/1320
DS39605F-page 32 © 2007 Microchip Technology Inc.
NOTES:© 2007 Microchip Technology Inc. DS39605F-page 33
PIC18F1220/1320
4.0 RESET
The PIC18F1220/1320 devices differentiate between
various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during Sleep
d) Watchdog Timer (WDT) Reset (during
execution)
e) Programmable Brown-out Reset (BOR)
f) RESET Instruction
g) Stack Full Reset
h) Stack Underflow Reset
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state”, depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register
(Register 4-1), RI, TO, PD, POR and BOR, are set or
cleared differently in different Reset situations, as
indicated in Table 4-2. These bits are used in software
to determine the nature of the Reset. See Table 4-3 for
a full description of the Reset states of all registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 4-1.
The Enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses.
The MCLR pin is not driven low by any internal Resets,
including the WDT.
The MCLR input provided by the MCLR pin can be
disabled with the MCLRE bit in Configuration
Register 3H (CONFIG3H<7>).
FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
R Q
External Reset
MCLR
VDD
OSC1
WDT
Time-out
VDD Rise
Detect
OST/PWRT
INTRC(1)
POR Pulse
OST
10-bit Ripple Counter
PWRT
Chip_Reset
11-bit Ripple Counter
Enable OST(2)
Enable PWRT
Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.
2: See Table 4-1 for time-out situations.
Brown-out
Reset
BOR
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
Sleep
( )_IDLE
1024 Cycles
65.5 ms 32 μs
MCLREPIC18F1220/1320
DS39605F-page 34 © 2007 Microchip Technology Inc.
4.1 Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected. To take advantage of the POR
circuitry, just tie the MCLR pin through a resistor (1k to
10 kΩ) to VDD. This will eliminate external RC components
usually needed to create a Power-on Reset
delay. A minimum rise rate for VDD is specified
(parameter D004). For a slow rise time, see Figure 4-2.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters (voltage,
frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
FIGURE 4-2: EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
4.2 Power-up Timer (PWRT)
The Power-up Timer (PWRT) of the PIC18F1220/1320 is
an 11-bit counter, which uses the INTRC source as the
clock input. This yields a count of 2048 x 32 μs = 65.6 ms.
While the PWRT is counting, the device is held in Reset.
The power-up time delay will vary from chip-to-chip due
to VDD, temperature and process variation. See DC
parameter 33 for details.
The PWRT is enabled by clearing configuration bit,
PWRTEN.
4.3 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter 33). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset, or on exit
from most low-power modes.
4.4 PLL Lock Time-out
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly
different from other oscillator modes. A portion of the
Power-up Timer is used to provide a fixed time-out that
is sufficient for the PLL to lock to the main oscillator frequency.
This PLL lock time-out (TPLL) is typically 2 ms
and follows the Oscillator Start-up Time-out.
4.5 Brown-out Reset (BOR)
A configuration bit, BOR, can disable (if clear/
programmed), or enable (if set) the Brown-out Reset
circuitry. If VDD falls below VBOR (parameter D005) for
greater than TBOR (parameter 35), the brown-out situation
will reset the chip. A Reset may not occur if VDD
falls below VBOR for less than TBOR. The chip will
remain in Brown-out Reset until VDD rises above VBOR.
If the Power-up Timer is enabled, it will be invoked after
VDD rises above VBOR; it then will keep the chip in
Reset for an additional time delay, TPWRT
(parameter 33). If VDD drops below VBOR while the
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be initialized.
Once VDD rises above VBOR, the Power-up Timer
will execute the additional time delay. Enabling BOR
Reset does not automatically enable the PWRT.
4.6 Time-out Sequence
On power-up, the time-out sequence is as follows:
First, after the POR pulse has cleared, PWRT time-out
is invoked (if enabled). Then, the OST is activated. The
total time-out will vary based on oscillator configuration
and the status of the PWRT. For example, in RC mode
with the PWRT disabled, there will be no time-out at all.
Figure 4-3, Figure 4-4, Figure 4-5, Figure 4-6 and
Figure 4-7 depict time-out sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire. Bringing
MCLR high will begin execution immediately
(Figure 4-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXXX device
operating in parallel.
Table 4-2 shows the Reset conditions for some Special
Function Registers, while Table 4-3 shows the Reset
conditions for all the registers.
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 kΩ is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3: R1 ≥ 1 kΩ will limit any current flowing into
MCLR from external capacitor C, in the event
of MCLR/VPP pin breakdown due to Electrostatic
Discharge (ESD) or Electrical
Overstress (EOS).
C
R1
D R
VDD
MCLR
PIC18FXXXX
VDD© 2007 Microchip Technology Inc. DS39605F-page 35
PIC18F1220/1320
TABLE 4-1: TIME-OUT IN VARIOUS SITUATIONS
REGISTER 4-1: RCON REGISTER BITS AND POSITIONS
TABLE 4-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Oscillator
Configuration
Power-up(2) and Brown-out Exit from
Low-Power Mode PWRTEN = 0 PWRTEN = 1
HSPLL 66 ms(1) + 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2)
HS, XT, LP 66 ms(1) + 1024 TOSC 1024 TOSC 1024 TOSC
EC, ECIO 66 ms(1) 5-10 μs(3) 5-10 μs(3)
RC, RCIO 66 ms(1) 5-10 μs(3) 5-10 μs(3)
INTIO1, INTIO2 66 ms(1) 5-10 μs(3) 5-10 μs(3)
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the 4x PLL to lock.
3: The program memory bias start-up time is always invoked on POR, wake-up from Sleep, or on any exit
from power managed mode that disables the CPU and instruction execution.
R/W-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
IPEN — — RI TO PD POR BOR
bit 7 bit 0
Note: Refer to Section 5.14 “RCON Register” for bit definitions.
Condition Program
Counter
RCON
Register RI TO PD POR BOR STKFUL STKUNF
Power-on Reset 0000h 0--1 1100 1 1 1 0 0 0 0
RESET Instruction 0000h 0--0 uuuu 0 u u u u u u
Brown-out 0000h 0--1 11u- 1 1 1 u 0 u u
MCLR during Power Managed
Run modes
0000h 0--u 1uuu u 1 u u u u u
MCLR during Power Managed
Idle modes and Sleep
0000h 0--u 10uu u 1 0 u u u u
WDT Time-out during Full
Power or Power Managed Run
0000h 0--u 0uuu u 0 u u u u u
MCLR during Full Power
Execution
0000h 0--u uuuu u u u u u
u u
Stack Full Reset (STVR = 1) 1 u
Stack Underflow Reset
(STVR = 1)
u 1
Stack Underflow Error (not an
actual Reset, STVR = 0)
0000h u--u uuuu u u u u u u 1
WDT Time-out during Power
Managed Idle or Sleep
PC + 2 u--u 00uu u 0 0 u u u u
Interrupt Exit from Power
Managed modes
PC + 2 u--u u0uu u u 0 u u u u
Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0x000008h or 0x000018h).PIC18F1220/1320
DS39605F-page 36 © 2007 Microchip Technology Inc.
TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register Applicable
Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
TOSU 1220 1320 ---0 0000 ---0 0000 ---0 uuuu(3)
TOSH 1220 1320 0000 0000 0000 0000 uuuu uuuu(3)
TOSL 1220 1320 0000 0000 0000 0000 uuuu uuuu(3)
STKPTR 1220 1320 00-0 0000 00-0 0000 uu-u uuuu(3)
PCLATU 1220 1320 ---0 0000 ---0 0000 ---u uuuu
PCLATH 1220 1320 0000 0000 0000 0000 uuuu uuuu
PCL 1220 1320 0000 0000 0000 0000 PC + 2(2)
TBLPTRU 1220 1320 --00 0000 --00 0000 --uu uuuu
TBLPTRH 1220 1320 0000 0000 0000 0000 uuuu uuuu
TBLPTRL 1220 1320 0000 0000 0000 0000 uuuu uuuu
TABLAT 1220 1320 0000 0000 0000 0000 uuuu uuuu
PRODH 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
PRODL 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
INTCON 1220 1320 0000 000x 0000 000u uuuu uuuu(1)
INTCON2 1220 1320 1111 -1-1 1111 -1-1 uuuu -u-u(1)
INTCON3 1220 1320 11-0 0-00 11-0 0-00 uu-u u-uu(1)
INDF0 1220 1320 N/A N/A N/A
POSTINC0 1220 1320 N/A N/A N/A
POSTDEC0 1220 1320 N/A N/A N/A
PREINC0 1220 1320 N/A N/A N/A
PLUSW0 1220 1320 N/A N/A N/A
FSR0H 1220 1320 ---- 0000 ---- 0000 ---- uuuu
FSR0L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
WREG 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
INDF1 1220 1320 N/A N/A N/A
POSTINC1 1220 1320 N/A N/A N/A
POSTDEC1 1220 1320 N/A N/A N/A
PREINC1 1220 1320 N/A N/A N/A
PLUSW1 1220 1320 N/A N/A N/A
FSR1H 1220 1320 ---- 0000 ---- 0000 ---- uuuu
FSR1L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: Bit 5 of PORTA is enabled if MCLR is disabled.© 2007 Microchip Technology Inc. DS39605F-page 37
PIC18F1220/1320
BSR 1220 1320 ---- 0000 ---- 0000 ---- uuuu
INDF2 1220 1320 N/A N/A N/A
POSTINC2 1220 1320 N/A N/A N/A
POSTDEC2 1220 1320 N/A N/A N/A
PREINC2 1220 1320 N/A N/A N/A
PLUSW2 1220 1320 N/A N/A N/A
FSR2H 1220 1320 ---- 0000 ---- 0000 ---- uuuu
FSR2L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
STATUS 1220 1320 ---x xxxx ---u uuuu ---u uuuu
TMR0H 1220 1320 0000 0000 0000 0000 uuuu uuuu
TMR0L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
T0CON 1220 1320 1111 1111 1111 1111 uuuu uuuu
OSCCON 1220 1320 0000 q000 0000 q000 uuuu qquu
LVDCON 1220 1320 --00 0101 --00 0101 --uu uuuu
WDTCON 1220 1320 ---- ---0 ---- ---0 ---- ---u
RCON(4) 1220 1320 0--1 11q0 0--q qquu u--u qquu
TMR1H 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 1220 1320 0000 0000 u0uu uuuu uuuu uuuu
TMR2 1220 1320 0000 0000 0000 0000 uuuu uuuu
PR2 1220 1320 1111 1111 1111 1111 1111 1111
T2CON 1220 1320 -000 0000 -000 0000 -uuu uuuu
ADRESH 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 1220 1320 00-0 0000 00-0 0000 uu-u uuuu
ADCON1 1220 1320 -000 0000 -000 0000 -uuu uuuu
ADCON2 1220 1320 0-00 0000 0-00 0000 u-uu uuuu
CCPR1H 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 1220 1320 0000 0000 0000 0000 uuuu uuuu
PWM1CON 1220 1320 0000 0000 0000 0000 uuuu uuuu
ECCPAS 1220 1320 0000 0000 0000 0000 uuuu uuuu
TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable
Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: Bit 5 of PORTA is enabled if MCLR is disabled.PIC18F1220/1320
DS39605F-page 38 © 2007 Microchip Technology Inc.
TMR3H 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
TMR3L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
T3CON 1220 1320 0-00 0000 u-uu uuuu u-uu uuuu
SPBRGH 1220 1320 0000 0000 0000 0000 uuuu uuuu
SPBRG 1220 1320 0000 0000 0000 0000 uuuu uuuu
RCREG 1220 1320 0000 0000 0000 0000 uuuu uuuu
TXREG 1220 1320 0000 0000 0000 0000 uuuu uuuu
TXSTA 1220 1320 0000 0010 0000 0010 uuuu uuuu
RCSTA 1220 1320 0000 000x 0000 000x uuuu uuuu
BAUDCTL 1220 1320 -1-1 0-00 -1-1 0-00 -u-u u-uu
EEADR 1220 1320 0000 0000 0000 0000 uuuu uuuu
EEDATA 1220 1320 0000 0000 0000 0000 uuuu uuuu
EECON2 1220 1320 0000 0000 0000 0000 0000 0000
EECON1 1220 1320 xx-0 x000 uu-0 u000 uu-0 u000
IPR2 1220 1320 1--1 -11- 1--1 -11- u--u -uuPIR2
1220 1320 0--0 -00- 0--0 -00- u--u -uu-(1)
PIE2 1220 1320 0--0 -00- 0--0 -00- u--u -uuIPR1
1220 1320 -111 -111 -111 -111 -uuu -uuu
PIR1 1220 1320 -000 -000 -000 -000 -uuu -uuu(1)
PIE1 1220 1320 -000 -000 -000 -000 -uuu -uuu
OSCTUNE 1220 1320 --00 0000 --00 0000 --uu uuuu
TRISB 1220 1320 1111 1111 1111 1111 uuuu uuuu
TRISA(5) 1220 1320 11-1 1111(5) 11-1 1111(5) uu-u uuuu(5)
LATB 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
LATA(5) 1220 1320 xx-x xxxx(5) uu-u uuuu(5) uu-u uuuu(5)
PORTB 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu
PORTA(5,6) 1220 1320 xx0x 0000(5,6) uu0u 0000(5,6) uuuu uuuu(5,6)
TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable
Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: Bit 5 of PORTA is enabled if MCLR is disabled.© 2007 Microchip Technology Inc. DS39605F-page 39
PIC18F1220/1320
FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
FIGURE 4-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOSTPIC18F1220/1320
DS39605F-page 40 © 2007 Microchip Technology Inc.
FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
FIGURE 4-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
0V 1V
5V
TPWRT
TOST
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
PLL TIME-OUT
TPLL
Note: TOST = 1024 clock cycles.
TPLL ≈ 2 ms max. First three stages of the PWRT timer.© 2007 Microchip Technology Inc. DS39605F-page 41
PIC18F1220/1320
5.0 MEMORY ORGANIZATION
There are three memory types in Enhanced MCU
devices. These memory types are:
• Program Memory
• Data RAM
• Data EEPROM
Data and program memory use separate busses,
which allows for concurrent access of these types.
Additional detailed information for Flash program memory
and data EEPROM is provided in Section 6.0
“Flash Program Memory” and Section 7.0 “Data
EEPROM Memory”, respectively.
FIGURE 5-1: PROGRAM MEMORY MAP
AND STACK FOR
PIC18F1220
5.1 Program Memory Organization
A 21-bit program counter is capable of addressing the
2-Mbyte program memory space. Accessing a location
between the physically implemented memory and the
2-Mbyte address will cause a read of all ‘0’s (a NOP
instruction).
The PIC18F1220 has 4 Kbytes of Flash memory and
can store up to 2,048 single-word instructions.
The PIC18F1320 has 8 Kbytes of Flash memory and
can store up to 4,096 single-word instructions.
The Reset vector address is at 0000h and the interrupt
vector addresses are at 0008h and 0018h.
The program memory maps for the PIC18F1220 and
PIC18F1320 devices are shown in Figure 5-1 and
Figure 5-2, respectively.
FIGURE 5-2: PROGRAM MEMORY MAP
AND STACK FOR
PIC18F1320
PC<20:0>
Stack Level 1 •
Stack Level 31
Reset Vector
Low Priority Interrupt Vector
•
•
CALL,RCALL,RETURN
RETFIE,RETLW
21
0000h
0018h
On-Chip
Program Memory
High Priority Interrupt Vector 0008h
User Memory Space
1FFFFFh
1000h
0FFFh
Read ‘0’
200000h
PC<20:0>
Stack Level 1 •
Stack Level 31
Reset Vector
Low Priority Interrupt Vector
•
•
CALL,RCALL,RETURN
RETFIE,RETLW
21
0000h
0018h
2000h
1FFFh
On-Chip
Program Memory
High Priority Interrupt Vector 0008h
User Memory Space
Read ‘0’
1FFFFFh
200000hPIC18F1220/1320
DS39605F-page 42 © 2007 Microchip Technology Inc.
5.2 Return Address Stack
The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC
(Program Counter) is pushed onto the stack when a
CALL or RCALL instruction is executed, or an interrupt
is Acknowledged. The PC value is pulled off the stack
on a RETURN, RETLW or a RETFIE instruction. PCLATU
and PCLATH are not affected by any of the RETURN or
CALL instructions.
The stack operates as a 31-word by 21-bit RAM and a
5-bit stack pointer, with the Stack Pointer initialized to
00000B after all Resets. There is no RAM associated
with Stack Pointer, 00000B. This is only a Reset value.
During a CALL type instruction, causing a push onto the
stack, the Stack Pointer is first incremented and the
RAM location pointed to by the Stack Pointer
(STKPTR) register is written with the contents of the PC
(already pointing to the instruction following the CALL).
During a RETURN type instruction, causing a pop from
the stack, the contents of the RAM location pointed to
by the STKPTR are transferred to the PC and then the
Stack Pointer is decremented.
The stack space is not part of either program or data
space. The Stack Pointer is readable and writable and
the address on the top of the stack is readable and
writable through the top-of-stack Special File
Registers. Data can also be pushed to or popped from
the stack using the top-of-stack SFRs. Status bits
indicate if the stack is full, has overflowed or
underflowed.
5.2.1 TOP-OF-STACK ACCESS
The top of the stack is readable and writable. Three
register locations, TOSU, TOSH and TOSL, hold the
contents of the stack location pointed to by the
STKPTR register (Figure 5-3). This allows users to
implement a software stack if necessary. After a CALL,
RCALL or interrupt, the software can read the pushed
value by reading the TOSU, TOSH and TOSL registers.
These values can be placed on a user defined software
stack. At return time, the software can replace the
TOSU, TOSH and TOSL and do a return.
The user must disable the global interrupt enable bits
while accessing the stack to prevent inadvertent stack
corruption.
5.2.2 RETURN STACK POINTER
(STKPTR)
The STKPTR register (Register 5-1) contains the stack
pointer value, the STKFUL (Stack Full) status bit and
the STKUNF (Stack Underflow) status bits. The value
of the Stack Pointer can be 0 through 31. The Stack
Pointer increments before values are pushed onto the
stack and decrements after values are popped off the
stack. At Reset, the Stack Pointer value will be zero.
The user may read and write the Stack Pointer value.
This feature can be used by a Real-Time Operating
System for return stack maintenance.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit is cleared by software or by a
POR.
The action that takes place when the stack becomes
full depends on the state of the STVR (Stack Overflow
Reset Enable) configuration bit. (Refer to Section 19.1
“Configuration Bits” for a description of the device
configuration bits.) If STVR is set (default), the 31st
push will push the (PC + 2) value onto the stack, set the
STKFUL bit and reset the device. The STKFUL bit will
remain set and the Stack Pointer will be set to zero.
If STVR is cleared, the STKFUL bit will be set on the
31st push and the Stack Pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and STKPTR will remain at 31.
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the Stack
Pointer remains at zero. The STKUNF bit will remain
set until cleared by software or a POR occurs.
FIGURE 5-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Note: Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the Reset vector, where the
stack conditions can be verified and
appropriate actions can be taken. This is
not the same as a Reset, as the contents
of the SFRs are not affected.
00011
001A34h
11111
11110
11101
00010
00001
00000
00010
Return Address Stack
Top-of-Stack 000D58h
TOSU TOSH TOSL
00h 1Ah 34h
STKPTR<4:0>© 2007 Microchip Technology Inc. DS39605F-page 43
PIC18F1220/1320
REGISTER 5-1: STKPTR REGISTER
5.2.3 PUSH AND POP INSTRUCTIONS
Since the Top-of-Stack (TOS) is readable and writable,
the ability to push values onto the stack and pull values
off the stack, without disturbing normal program execution,
is a desirable option. To push the current PC value
onto the stack, a PUSH instruction can be executed.
This will increment the Stack Pointer and load the current
PC value onto the stack. TOSU, TOSH and TOSL
can then be modified to place data or a return address
on the stack.
The ability to pull the TOS value off of the stack and
replace it with the value that was previously pushed
onto the stack, without disturbing normal execution, is
achieved by using the POP instruction. The POP instruction
discards the current TOS by decrementing the
Stack Pointer. The previous value pushed onto the
stack then becomes the TOS value.
5.2.4 STACK FULL/UNDERFLOW RESETS
These Resets are enabled by programming the STVR
bit in Configuration Register 4L. When the STVR bit is
cleared, a full or underflow condition will set the appropriate
STKFUL or STKUNF bit, but not cause a device
Reset. When the STVR bit is set, a full or underflow
condition will set the appropriate STKFUL or STKUNF
bit and then cause a device Reset. The STKFUL or
STKUNF bits are cleared by the user software or a
Power-on Reset.
R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0
bit 7 bit 0
bit 7(1) STKFUL: Stack Full Flag bit
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
bit 6(1) STKUNF: Stack Underflow Flag bit
1 = Stack underflow occurred
0 = Stack underflow did not occur
bit 5 Unimplemented: Read as ‘0’
bit 4-0 SP4:SP0: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.
Legend:
R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownPIC18F1220/1320
DS39605F-page 44 © 2007 Microchip Technology Inc.
5.3 Fast Register Stack
A “fast return” option is available for interrupts. A fast
register stack is provided for the Status, WREG and
BSR registers and is only one in depth. The stack is not
readable or writable and is loaded with the current
value of the corresponding register when the processor
vectors for an interrupt. The values in the registers are
then loaded back into the working registers, if the
RETFIE, FAST instruction is used to return from the
interrupt.
All interrupt sources will push values into the stack
registers. If both low and high priority interrupts are
enabled, the stack registers cannot be used reliably to
return from low priority interrupts. If a high priority interrupt
occurs while servicing a low priority interrupt, the
stack register values stored by the low priority interrupt
will be overwritten. Users must save the key registers
in software during a low priority interrupt.
If interrupt priority is not used, all interrupts may use the
fast register stack for returns from interrupt.
If no interrupts are used, the fast register stack can be
used to restore the Status, WREG and BSR registers at
the end of a subroutine call. To use the fast register
stack for a subroutine call, a CALL LABEL, FAST
instruction must be executed to save the Status,
WREG and BSR registers to the fast register stack. A
RETURN, FAST instruction is then executed to restore
these registers from the fast register stack.
Example 5-1 shows a source code example that uses
the fast register stack during a subroutine call and
return.
EXAMPLE 5-1: FAST REGISTER STACK
CODE EXAMPLE
5.4 PCL, PCLATH and PCLATU
The Program Counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21-bits
wide. The low byte, known as the PCL register, is both
readable and writable. The high byte, or PCH register,
contains the PC<15:8> bits and is not directly readable
or writable. Updates to the PCH register may be performed
through the PCLATH register. The upper byte is
called PCU. This register contains the PC<20:16> bits
and is not directly readable or writable. Updates to the
PCU register may be performed through the PCLATU
register.
The contents of PCLATH and PCLATU will be
transferred to the program counter by any operation
that writes PCL. Similarly, the upper two bytes of the
program counter will be transferred to PCLATH and
PCLATU by an operation that reads PCL. This is useful
for computed offsets to the PC (see Section 5.8.1
“Computed GOTO”).
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the LSB of PCL is fixed to a value of ‘0’.
The PC increments by 2 to address sequential
instructions in the program memory.
The CALL, RCALL, GOTO and program branch instructions
write to the program counter directly. For these
instructions, the contents of PCLATH and PCLATU are
not transferred to the program counter.
CALL SUB1, FAST ;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
•
•
SUB1 •
•
RETURN, FAST ;RESTORE VALUES SAVED
;IN FAST REGISTER STACK© 2007 Microchip Technology Inc. DS39605F-page 45
PIC18F1220/1320
5.5 Clocking Scheme/Instruction
Cycle
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the
Program Counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruction
is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 5-4.
5.6 Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then two cycles are required to complete the instruction
(Example 5-2).
A fetch cycle begins with the Program Counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register” (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 5-4: CLOCK/INSTRUCTION CYCLE
EXAMPLE 5-2: INSTRUCTION PIPELINE FLOW
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKO
(RC Mode)
PC PC + 2 PC + 4
Fetch INST (PC)
Execute INST (PC – 2)
Fetch INST (PC + 2)
Execute INST (PC)
Fetch INST (PC + 4)
Execute INST (PC + 2)
Internal
Phase
Clock
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
TCY0 TCY1 TCY2 TCY3 TCY4 TCY5
1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. BRA SUB_1 Fetch 3 Execute 3
4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP)
5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1PIC18F1220/1320
DS39605F-page 46 © 2007 Microchip Technology Inc.
5.7 Instructions in Program Memory
The program memory is addressed in bytes. Instructions
are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB = 0). Figure 5-5 shows an
example of how instruction words are stored in the program
memory. To maintain alignment with instruction
boundaries, the PC increments in steps of 2 and the
LSB will always read ‘0’ (see Section 5.4 “PCL,
PCLATH and PCLATU”).
The CALL and GOTO instructions have the absolute
program memory address embedded into the instruction.
Since instructions are always stored on word
boundaries, the data contained in the instruction is a
word address. The word address is written to
PC<20:1>, which accesses the desired byte address in
program memory. Instruction #2 in Figure 5-5 shows
how the instruction ‘GOTO 000006h’ is encoded in the
program memory. Program branch instructions, which
encode a relative address offset, operate in the same
manner. The offset value stored in a branch instruction
represents the number of single-word instructions that
the PC will be offset by. Section 20.0 “Instruction Set
Summary” provides further details of the instruction
set.
FIGURE 5-5: INSTRUCTIONS IN PROGRAM MEMORY
5.7.1 TWO-WORD INSTRUCTIONS
PIC18F1220/1320 devices have four two-word
instructions: MOVFF, CALL, GOTO and LFSR. The second
word of these instructions has the 4 MSBs set to ‘1’s and
is decoded as a NOP instruction. The lower 12 bits of the
second word contain data to be used by the instruction.
If the first word of the instruction is executed, the data in
the second word is accessed. If the second word of the
instruction is executed by itself (first word was skipped),
it will execute as a NOP. This action is necessary when
the two-word instruction is preceded by a conditional
instruction that results in a skip operation. A program
example that demonstrates this concept is shown in
Example 5-3. Refer to Section 20.0 “Instruction Set
Summary” for further details of the instruction set.
EXAMPLE 5-3: TWO-WORD INSTRUCTIONS
Word Address
LSB = 1 LSB = 0 ↓
Program Memory
Byte Locations →
000000h
000002h
000004h
000006h
Instruction 1: MOVLW 055h 0Fh 55h 000008h
Instruction 2: GOTO 000006h EFh 03h 00000Ah
F0h 00h 00000Ch
Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh
F4h 56h 000010h
000012h
000014h
CASE 1:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word
1111 0100 0101 0110 ; Execute this word as a NOP
0010 0100 0000 0000 ADDWF REG3 ; continue code
CASE 2:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word
1111 0100 0101 0110 ; 2nd word of instruction
0010 0100 0000 0000 ADDWF REG3 ; continue code© 2007 Microchip Technology Inc. DS39605F-page 47
PIC18F1220/1320
5.8 Look-up Tables
Look-up tables are implemented two ways:
• Computed GOTO
• Table Reads
5.8.1 COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (see Example 5-4).
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW 0xnn
instructions, that returns the value 0xnn to the calling
function.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSB = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
EXAMPLE 5-4: COMPUTED GOTO USING
AN OFFSET VALUE
5.8.2 TABLE READS/TABLE WRITES
A better method of storing data in program memory
allows two bytes of data to be stored in each instruction
location.
Look-up table data may be stored two bytes per program
word by using table reads and writes. The Table
Pointer (TBLPTR) register specifies the byte address
and the Table Latch (TABLAT) register contains the
data that is read from or written to program memory.
Data is transferred to/from program memory, one byte
at a time.
The table read/table write operation is discussed
further in Section 6.1 “Table Reads and Table
Writes”.
5.9 Data Memory Organization
The data memory is implemented as static RAM. Each
register in the data memory has a 12-bit address,
allowing up to 4096 bytes of data memory. Figure 5-6
shows the data memory organization for the
PIC18F1220/1320 devices.
The data memory map is divided into as many as
16 banks that contain 256 bytes each. The lower 4 bits
of the Bank Select Register (BSR<3:0>) select which
bank will be accessed. The upper 4 bits for the BSR are
not implemented.
The data memory contains Special Function Registers
(SFR) and General Purpose Registers (GPR). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratch pad operations in the user’s application.
The SFRs start at the last location of Bank 15
(FFFh) and extend towards F80h. Any remaining space
beyond the SFRs in the Bank may be implemented as
GPRs. GPRs start at the first location of Bank 0 and
grow upwards. Any read of an unimplemented location
will read as ‘0’s.
The entire data memory may be accessed directly or
indirectly. Direct addressing may require the use of the
BSR register. Indirect addressing requires the use of a
File Select Register (FSRn) and a corresponding Indirect
File Operand (INDFn). Each FSR holds a 12-bit
address value that can be used to access any location
in the Data Memory map without banking. See
Section 5.12 “Indirect Addressing, INDF and FSR
Registers” for indirect addressing details.
The instruction set and architecture allow operations
across all banks. This may be accomplished by indirect
addressing or by the use of the MOVFF instruction. The
MOVFF instruction is a two-word/two-cycle instruction
that moves a value from one register to another.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle,
regardless of the current BSR values, an Access Bank
is implemented. A segment of Bank 0 and a segment of
Bank 15 comprise the Access RAM. Section 5.10
“Access Bank” provides a detailed description of the
Access RAM.
5.9.1 GENERAL PURPOSE
REGISTER FILE
Enhanced MCU devices may have banked memory in
the GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other Resets.
Data RAM is available for use as GPR registers by all
instructions. The second half of Bank 15 (F80h to
FFFh) contains SFRs. All other banks of data memory
contain GPRs, starting with Bank 0.
MOVFW OFFSET
CALL TABLE
ORG 0xnn00
TABLE ADDWF PCL
RETLW 0xnn
RETLW 0xnn
RETLW 0xnn
.
.
.PIC18F1220/1320
DS39605F-page 48 © 2007 Microchip Technology Inc.
FIGURE 5-6: DATA MEMORY MAP FOR PIC18F1220/1320 DEVICES
Bank 0
Bank 14
Bank 15
BSR<3:0> Data Memory Map
= 0000
= 1111
080h
07Fh
F80h
FFFh
00h
7Fh
80h
FFh
Access Bank
When a = 0,
The BSR is ignored and the
Access Bank is used.
The first 128 bytes are
General Purpose RAM
(from Bank 0).
The second 128 bytes are
Special Function Registers
(from Bank 15).
When a = 1,
The BSR specifies the Bank
used by the instruction.
F7Fh
F00h
EFFh
0FFh
000h Access RAM
FFh
00h
FFh
00h
GPR
SFR
Unused
Access RAM High
Access RAM Low
Bank 1
to Unused
= 1110 Read ‘00h’
= 0001
(SFRs)© 2007 Microchip Technology Inc. DS39605F-page 49
PIC18F1220/1320
5.9.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 5-1 and Table 5-2.
The SFRs can be classified into two sets: those associated
with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature.
The SFRs are typically distributed among the peripherals
whose functions they control.
The unused SFR locations will be unimplemented and
read as ‘0’s.
TABLE 5-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F1220/1320 DEVICES
Address Name Address Name Address Name Address Name
FFFh TOSU FDFh INDF2(2) FBFh CCPR1H F9Fh IPR1
FFEh TOSH FDEh POSTINC2(2) FBEh CCPR1L F9Eh PIR1
FFDh TOSL FDDh POSTDEC2(2) FBDh CCP1CON F9Dh PIE1
FFCh STKPTR FDCh PREINC2(2) FBCh — F9Ch —
FFBh PCLATU FDBh PLUSW2(2) FBBh — F9Bh OSCTUNE
FFAh PCLATH FDAh FSR2H FBAh — F9Ah —
FF9h PCL FD9h FSR2L FB9h — F99h —
FF8h TBLPTRU FD8h STATUS FB8h — F98h —
FF7h TBLPTRH FD7h TMR0H FB7h PWM1CON F97h —
FF6h TBLPTRL FD6h TMR0L FB6h ECCPAS F96h —
FF5h TABLAT FD5h T0CON FB5h — F95h —
FF4h PRODH FD4h — FB4h — F94h —
FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB
FF2h INTCON FD2h LVDCON FB2h TMR3L F92h TRISA
FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h —
FF0h INTCON3 FD0h RCON FB0h SPBRGH F90h —
FEFh INDF0(2) FCFh TMR1H FAFh SPBRG F8Fh —
FEEh POSTINC0(2) FCEh TMR1L FAEh RCREG F8Eh —
FEDh POSTDEC0(2) FCDh T1CON FADh TXREG F8Dh —
FECh PREINC0(2) FCCh TMR2 FACh TXSTA F8Ch —
FEBh PLUSW0(2) FCBh PR2 FABh RCSTA F8Bh —
FEAh FSR0H FCAh T2CON FAAh BAUDCTL F8Ah LATB
FE9h FSR0L FC9h — FA9h EEADR F89h LATA
FE8h WREG FC8h — FA8h EEDATA F88h —
FE7h INDF1(2) FC7h — FA7h EECON2 F87h —
FE6h POSTINC1(2) FC6h — FA6h EECON1 F86h —
FE5h POSTDEC1(2) FC5h — FA5h — F85h —
FE4h PREINC1(2) FC4h ADRESH FA4h — F84h —
FE3h PLUSW1(2) FC3h ADRESL FA3h — F83h —
FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h —
FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB
FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA
Note 1: Unimplemented registers are read as ‘0’.
2: This is not a physical register.PIC18F1220/1320
DS39605F-page 50 © 2007 Microchip Technology Inc.
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F1220/1320)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Details on
page:
TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 36, 42
TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 36, 42
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 36, 42
STKPTR STKFUL STKUNF — Return Stack Pointer 00-0 0000 36, 43
PCLATU — — bit 21(3) Holding Register for PC<20:16> ---0 0000 36, 44
PCLATH Holding Register for PC<15:8> 0000 0000 36, 44
PCL PC Low Byte (PC<7:0>) 0000 0000 36, 44
TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 36, 60
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 36, 60
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 36, 60
TABLAT Program Memory Table Latch 0000 0000 36, 60
PRODH Product Register High Byte xxxx xxxx 36, 71
PRODL Product Register Low Byte xxxx xxxx 36, 71
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 36, 75
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 1111 -1-1 36, 76
INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 36, 77
INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 36, 53
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 36, 53
POSTDEC0 Uses contents of FSR0 to address data memory– value of FSR0 post-decremented (not a physical register) N/A 36, 53
PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 36, 53
PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 offset by W (not a physical register) N/A 36, 53
FSR0H — — — — Indirect Data Memory Address Pointer 0 High ---- 0000 36, 53
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 36, 53
WREG Working Register xxxx xxxx 36
INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 36, 53
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 36, 53
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 36, 53
PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 36, 53
PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 offset by W (not a physical register) N/A 36, 53
FSR1H — — — — Indirect Data Memory Address Pointer 1 High ---- 0000 36, 53
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 36, 53
BSR — — — — Bank Select Register ---- 0000 37, 52
INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 37, 53
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 37, 53
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 37, 53
PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 37, 53
PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 offset by W (not a physical register) N/A 37, 53
FSR2H — — — — Indirect Data Memory Address Pointer 2 High ---- 0000 37, 53
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 37, 53
STATUS — — — N OV Z DC C ---x xxxx 37, 55
TMR0H Timer0 Register High Byte 0000 0000 37, 101
TMR0L Timer0 Register Low Byte xxxx xxxx 37, 101
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 37, 99
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0000 q000 37, 17
LVDCON — — IVRST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 37, 167
WDTCON — — — — — — — SWDTEN --- ---0 37, 180
RCON IPEN — — RI TO PD POR BOR 0--1 11q0 35, 56, 84
Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read ‘0’
in all other oscillator modes.
2: RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
3: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
4: The RA5 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RA5 reads ‘0’. This bit is read-only.© 2007 Microchip Technology Inc. DS39605F-page 51
PIC18F1220/1320
TMR1H Timer1 Register High Byte xxxx xxxx 37, 108
TMR1L Timer1 Register Low Byte xxxx xxxx 37, 108
T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 37, 103
TMR2 Timer2 Register 0000 0000 37, 109
PR2 Timer2 Period Register 1111 1111 37, 109
T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 37, 109
ADRESH A/D Result Register High Byte xxxx xxxx 37, 164
ADRESL A/D Result Register Low Byte xxxx xxxx 37, 164
ADCON0 VCFG1 VCFG0 — CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 37, 155
ADCON1 — PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 -000 0000 37, 156
ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 37, 157
CCPR1H Capture/Compare/PWM Register 1 High Byte xxxx xxxx 37. 116
CCPR1L Capture/Compare/PWM Register 1 Low Byte xxxx xxxx 37, 116
CCP1CON P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 37, 115
PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 37, 126
ECCPAS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 37, 127
TMR3H Timer3 Register High Byte xxxx xxxx 38, 113
TMR3L Timer3 Register Low Byte xxxx xxxx 38, 113
T3CON RD16 — T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0-00 0000 38, 111
SPBRGH EUSART Baud Rate Generator High Byte 0000 0000 38
SPBRG EUSART Baud Rate Generator Low Byte 0000 0000 38, 135
RCREG EUSART Receive Register 0000 0000 38, 143,
142
TXREG EUSART Transmit Register 0000 0000 38, 140,
142
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 38, 132
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 38, 133
BAUDCTL — RCIDL — SCKP BRG16 — WUE ABDEN -1-1 0-00 38
EEADR EEPROM Address Register 0000 0000 38, 67
EEDATA EEPROM Data Register 0000 0000 38, 70
EECON2 EEPROM Control Register 2 (not a physical register) 0000 0000 38, 58, 67
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 38, 59, 68
IPR2 OSCFIP — — EEIP — LVDIP TMR3IP — 1--1 -11- 38, 83
PIR2 OSCFIF — — EEIF — LVDIF TMR3IF — 0--0 -00- 38, 79
PIE2 OSCFIE — — EEIE — LVDIE TMR3IE — 0--0 -00- 38, 81
IPR1 — ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP -111 -111 38, 82
PIR1 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF -000 -000 38, 78
PIE1 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE -000 -000 38, 80
OSCTUNE — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 38, 15
TRISB Data Direction Control Register for PORTB 1111 1111 38, 98
TRISA TRISA7(2) TRISA6(1) — Data Direction Control Register for PORTA 11-1 1111 38, 89
LATB Read/Write PORTB Data Latch xxxx xxxx 38, 98
LATA LATA<7>(2) LATA<6>(1) — Read/Write PORTA Data Latch xx-x xxxx 38, 89
PORTB Read PORTB pins, Write PORTB Data Latch xxxx xxxx 38, 98
PORTA RA7(2) RA6(1) RA5(4) Read PORTA pins, Write PORTA Data Latch xx0x 0000 38, 89
TABLE 5-2: REGISTER FILE SUMMARY (PIC18F1220/1320) (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Details on
page:
Legend: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read ‘0’
in all other oscillator modes.
2: RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
3: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
4: The RA5 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RA5 reads ‘0’. This bit is read-only.PIC18F1220/1320
DS39605F-page 52 © 2007 Microchip Technology Inc.
5.10 Access Bank
The Access Bank is an architectural enhancement
which is very useful for C compiler code optimization.
The techniques used by the C compiler may also be
useful for programs written in assembly.
This data memory region can be used for:
• Intermediate computational values
• Local variables of subroutines
• Faster context saving/switching of variables
• Common variables
• Faster evaluation/control of SFRs (no banking)
The Access Bank is comprised of the last 128 bytes in
Bank 15 (SFRs) and the first 128 bytes in Bank 0.
These two sections will be referred to as Access RAM
High and Access RAM Low, respectively. Figure 5-6
indicates the Access RAM areas.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register or in
the Access Bank. This bit is denoted as the ‘a’ bit (for
access bit).
When forced in the Access Bank (a = 0), the last
address in Access RAM Low is followed by the first
address in Access RAM High. Access RAM High maps
the Special Function Registers, so these registers can
be accessed without any software overhead. This is
useful for testing status flags and modifying control bits.
5.11 Bank Select Register (BSR)
The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
partitioned into as many as sixteen banks. When using
direct addressing, the BSR should be configured for the
desired bank.
BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read ‘0’s and
writes will have no effect (see Figure 5-7).
A MOVLB instruction has been provided in the instruction
set to assist in selecting banks.
If the currently selected bank is not implemented, any
read will return all ‘0’s and all writes are ignored. The
Status register bits will be set/cleared as appropriate for
the instruction performed.
Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.
A MOVFF instruction ignores the BSR, since the 12-bit
addresses are embedded into the instruction word.
Section 5.12 “Indirect Addressing, INDF and FSR
Registers” provides a description of indirect addressing,
which allows linear addressing of the entire RAM
space.
FIGURE 5-7: DIRECT ADDRESSING
Note 1: For register file map detail, see Table 5-1.
2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers
of the Access Bank.
3: The MOVFF instruction embeds the entire 12-bit address in the instruction.
Data
Memory(1)
Direct Addressing
Bank Select(2) Location Select(3)
BSR<3:0> 7 From Opcode 0 (3)
00h 01h 0Eh 0Fh
Bank 0 Bank 1 Bank 14 Bank 15
1FFh
100h
0FFh
000h
EFFh
E00h
FFFh
F00h
BSR<7:4>
000 0© 2007 Microchip Technology Inc. DS39605F-page 53
PIC18F1220/1320
5.12 Indirect Addressing, INDF and
FSR Registers
Indirect addressing is a mode of addressing data memory,
where the data memory address in the instruction
is not fixed. An FSR register is used as a pointer to the
data memory location that is to be read or written. Since
this pointer is in RAM, the contents can be modified by
the program. This can be useful for data tables in the
data memory and for software stacks. Figure 5-8
shows how the fetched instruction is modified prior to
being executed.
Indirect addressing is possible by using one of the
INDF registers. Any instruction, using the INDF register,
actually accesses the register pointed to by the File
Select Register, FSR. Reading the INDF register itself,
indirectly (FSR = 0), will read 00h. Writing to the INDF
register indirectly, results in a no operation (NOP). The
FSR register contains a 12-bit address, which is shown
in Figure 5-9.
The INDFn register is not a physical register. Addressing
INDFn actually addresses the register whose
address is contained in the FSRn register (FSRn is a
pointer). This is indirect addressing.
Example 5-5 shows a simple use of indirect addressing
to clear the RAM in Bank 1 (locations 100h-1FFh) in a
minimum number of instructions.
EXAMPLE 5-5: HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING
There are three indirect addressing registers. To
address the entire data memory space (4096 bytes),
these registers are 12-bit wide. To store the 12 bits of
addressing information, two 8-bit registers are required:
1. FSR0: composed of FSR0H:FSR0L
2. FSR1: composed of FSR1H:FSR1L
3. FSR2: composed of FSR2H:FSR2L
In addition, there are registers INDF0, INDF1 and
INDF2, which are not physically implemented. Reading
or writing to these registers activates indirect addressing,
with the value in the corresponding FSR register
being the address of the data. If an instruction writes a
value to INDF0, the value will be written to the address
pointed to by FSR0H:FSR0L. A read from INDF1 reads
the data from the address pointed to by
FSR1H:FSR1L. INDFn can be used in code anywhere
an operand can be used.
If INDF0, INDF1 or INDF2 are read indirectly via an
FSR, all ‘0’s are read (zero bit is set). Similarly, if
INDF0, INDF1 or INDF2 are written to indirectly, the
operation will be equivalent to a NOP instruction and the
Status bits are not affected.
5.12.1 INDIRECT ADDRESSING
OPERATION
Each FSR register has an INDF register associated with
it, plus four additional register addresses. Performing an
operation using one of these five registers determines
how the FSR will be modified during indirect addressing.
When data access is performed using one of the five
INDFn locations, the address selected will configure
the FSRn register to:
• Do nothing to FSRn after an indirect access (no
change) – INDFn
• Auto-decrement FSRn after an indirect access
(post-decrement) – POSTDECn
• Auto-increment FSRn after an indirect access
(post-increment) – POSTINCn
• Auto-increment FSRn before an indirect access
(pre-increment) – PREINCn
• Use the value in the WREG register as an offset
to FSRn. Do not modify the value of the WREG or
the FSRn register after an indirect access (no
change) – PLUSWn
When using the auto-increment or auto-decrement
features, the effect on the FSR is not reflected in the
Status register. For example, if the indirect address
causes the FSR to equal ‘0’, the Z bit will not be set.
Auto-incrementing or auto-decrementing an FSR affects
all 12 bits. That is, when FSRnL overflows from an
increment, FSRnH will be incremented automatically.
Adding these features allows the FSRn to be used as a
stack pointer, in addition to its uses for table operations
in data memory.
Each FSR has an address associated with it that
performs an indexed indirect access. When a data
access to this INDFn location (PLUSWn) occurs, the
FSRn is configured to add the signed value in the
WREG register and the value in FSR to form the
address before an indirect access. The FSR value is
not changed. The WREG offset range is -128 to +127.
If an FSR register contains a value that points to one of
the INDFn, an indirect read will read 00h (zero bit is
set), while an indirect write will be equivalent to a NOP
(Status bits are not affected).
If an indirect addressing write is performed when the target
address is an FSRnH or FSRnL register, the data is
written to the FSR register, but no pre- or post-increment/
decrement is performed.
LFSR FSR0,0x100 ;
NEXT CLRF POSTINC0 ; Clear INDF
; register then
; inc pointer
BTFSS FSR0H, 1 ; All done with
; Bank1?
GOTO NEXT ; NO, clear next
CONTINUE ; YES, continue PIC18F1220/1320
DS39605F-page 54 © 2007 Microchip Technology Inc.
FIGURE 5-8: INDIRECT ADDRESSING OPERATION
FIGURE 5-9: INDIRECT ADDRESSING
Opcode Address
File Address = Access of an Indirect Addressing Register
FSR
Instruction
Executed
Instruction
Fetched
RAM
Opcode File
12 12
12
BSR<3:0>
4 8
0h
FFFh
Note 1: For register file map detail, see Table 5-1.
Data
Memory(1)
Indirect Addressing
FSRnH:FSRnL
3 0
0FFFh
0000h
Location Select
11 0
0 7© 2007 Microchip Technology Inc. DS39605F-page 55
PIC18F1220/1320
5.13 Status Register
The Status register, shown in Register 5-2, contains the
arithmetic status of the ALU. As with any other SFR, it
can be the operand for any instruction.
If the Status register is the destination for an instruction
that affects the Z, DC, C, OV or N bits, the results of the
instruction are not written; instead, the status is
updated according to the instruction performed. Therefore,
the result of an instruction with the Status register
as its destination may be different than intended. As an
example, CLRF STATUS will set the Z bit and leave the
remaining Status bits unchanged (‘000u u1uu’).
It is recommended that only BCF, BSF, SWAPF, MOVFF
and MOVWF instructions are used to alter the Status register,
because these instructions do not affect the Z, C,
DC, OV or N bits in the Status register.
For other instructions that do not affect Status bits, see
the instruction set summaries in Table 20-1.
REGISTER 5-2: STATUS REGISTER
Note: The C and DC bits operate as the borrow
and digit borrow bits, respectively, in
subtraction.
U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — — N OV Z DC C
bit 7 bit 0
bit 7-5 Unimplemented: Read as ‘0’
bit 4 N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative (ALU MSB = 1).
1 = Result was negative
0 = Result was positive
bit 3 OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the
7-bit magnitude, which causes the sign bit (bit 7) to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the
2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit
is loaded with either the bit 4 or bit 3 of the source register.
bit 0 C: Carry/borrow bit
For ADDWF, ADDLW, SUBLW and SUBWF instructions:
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the
2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit
is loaded with either the high or low-order bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownPIC18F1220/1320
DS39605F-page 56 © 2007 Microchip Technology Inc.
5.14 RCON Register
The Reset Control (RCON) register contains flag bits
that allow differentiation between the sources of a
device Reset. These flags include the TO, PD, POR,
BOR and RI bits. This register is readable and writable.
REGISTER 5-3: RCON REGISTER
Note 1: If the BOR configuration bit is set (Brownout
Reset enabled), the BOR bit is ‘1’ on
a Power-on Reset. After a Brown-out
Reset has occurred, the BOR bit will be
cleared and must be set by firmware to
indicate the occurrence of the next
Brown-out Reset.
2: It is recommended that the POR bit be set
after a Power-on Reset has been
detected, so that subsequent Power-on
Resets may be detected.
R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0
IPEN — — RI TO PD POR BOR
bit 7 bit 0
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)
bit 6-5 Unimplemented: Read as ‘0’
bit 4 RI: RESET Instruction Flag bit
1 = The RESET instruction was not executed (set by firmware only)
0 = The RESET instruction was executed causing a device Reset
(must be set in software after a Brown-out Reset occurs)
bit 3 TO: Watchdog Time-out Flag bit
1 = Set by power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 2 PD: Power-down Detection Flag bit
1 = Set by power-up or by the CLRWDT instruction
0 = Cleared by execution of the SLEEP instruction
bit 1 POR: Power-on Reset Status bit
1 = A Power-on Reset has not occurred (set by firmware only)
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred (set by firmware only)
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown© 2007 Microchip Technology Inc. DS39605F-page 57
PIC18F1220/1320
6.0 FLASH PROGRAM MEMORY
The Flash program memory is readable, writable and
erasable during normal operation over the entire VDD
range.
A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 8 bytes at a time. Program memory is erased
in blocks of 64 bytes at a time. A “Bulk Erase” operation
may not be issued from user code.
While writing or erasing program memory, instruction
fetches cease until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
6.1 Table Reads and Table Writes
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data
RAM:
• Table Read (TBLRD)
• Table Write (TBLWT)
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
Table read operations retrieve data from program
memory and place it into TABLAT in the data RAM
space. Figure 6-1 shows the operation of a table read
with program memory and data RAM.
Table write operations store data from TABLAT in the
data memory space into holding registers in program
memory. The procedure to write the contents of the
holding registers into program memory is detailed in
Section 6.5 “Writing to Flash Program Memory”.
Figure 6-2 shows the operation of a table write with
program memory and data RAM.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word aligned. Therefore, a table block
can start and end at any byte address. If a table write is
being used to write executable code into program
memory, program instructions will need to be word
aligned (TBLPTRL<0> = 0).
The EEPROM on-chip timer controls the write and
erase times. The write and erase voltages are generated
by an on-chip charge pump rated to operate over
the voltage range of the device for byte or word
operations.
FIGURE 6-1: TABLE READ OPERATION
Table Pointer(1)
Table Latch (8-bit)
Program Memory
TBLPTRH TBLPTRL
TABLAT
TBLPTRU
Instruction: TBLRD*
Note 1: Table Pointer points to a byte in program memory.
Program Memory
(TBLPTR)PIC18F1220/1320
DS39605F-page 58 © 2007 Microchip Technology Inc.
FIGURE 6-2: TABLE WRITE OPERATION
6.2 Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
6.2.1 EECON1 AND EECON2 REGISTERS
EECON1 is the control register for memory accesses.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the memory write and erase sequences.
Control bit, EEPGD, determines if the access will be to
program or data EEPROM memory. When clear,
operations will access the data EEPROM memory.
When set, program memory is accessed.
Control bit, CFGS, determines if the access will be to
the configuration registers, or to program memory/data
EEPROM memory. When set, subsequent operations
access configuration registers. When CFGS is clear,
the EEPGD bit selects either program Flash or data
EEPROM memory.
The FREE bit controls program memory erase operations.
When the FREE bit is set, the erase operation is
initiated on the next WR command. When FREE is
clear, only writes are enabled.
The WREN bit enables and disables erase and write
operations. When set, erase and write operations are
allowed. When clear, erase and write operations are
disabled – the WR bit cannot be set while the WREN bit
is clear. This process helps to prevent accidental writes
to memory due to errant (unexpected) code execution.
Firmware should keep the WREN bit clear at all times,
except when starting erase or write operations. Once
firmware has set the WR bit, the WREN bit may be
cleared. Clearing the WREN bit will not affect the
operation in progress.
The WRERR bit is set when a write operation is
interrupted by a Reset. In these situations, the user can
check the WRERR bit and rewrite the location. It will be
necessary to reload the data and address registers
(EEDATA and EEADR) as these registers have cleared
as a result of the Reset.
Control bits, RD and WR, start read and erase/write
operations, respectively. These bits are set by firmware
and cleared by hardware at the completion of the
operation.
The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructions. See Section 6.3 “Reading the
Flash Program Memory” regarding table reads.
Table Pointer(1) Table Latch (8-bit)
TBLPTRH TBLPTRL TABLAT
Program Memory
(TBLPTR)
TBLPTRU
Instruction: TBLWT*
Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by
TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed
in Section 6.5 “Writing to Flash Program Memory”.
Holding Registers
Program Memory
Note: Interrupt flag bit, EEIF in the PIR2 register,
is set when the write is complete. It must
be cleared in software.© 2007 Microchip Technology Inc. DS39605F-page 59
PIC18F1220/1320
REGISTER 6-1: EECON1 REGISTER
R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0
EEPGD CFGS — FREE WRERR WREN WR RD
bit 7 bit 0
bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access program Flash memory
0 = Access data EEPROM memory
bit 6 CFGS: Flash Program/Data EE or Configuration Select bit
1 = Access configuration registers
0 = Access program Flash or data EEPROM memory
bit 5 Unimplemented: Read as ‘0’
bit 4 FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation – TBLPTR<5:0> are ignored)
0 = Perform write only
bit 3 WRERR: EEPROM Error Flag bit
1 = A write operation was prematurely terminated (any Reset during self-timed programming)
0 = The write operation completed normally
Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows
tracing of the error condition.
bit 2 WREN: Write Enable bit
1 = Allows erase or write cycles
0 = Inhibits erase or write cycles
bit 1 WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
0 = Write cycle completed
bit 0 RD: Read Control bit
1 = Initiates a memory read
(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)
in software. RD bit cannot be set when EEPGD = 1.)
0 = Read completed
Legend:
R = Readable bit S = Settable only U = Unimplemented bit, read as ‘0’
W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared
x = Bit is unknownPIC18F1220/1320
DS39605F-page 60 © 2007 Microchip Technology Inc.
6.2.2 TABLAT – TABLE LATCH REGISTER
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The table latch is used to hold 8-bit
data during data transfers between program memory
and data RAM.
6.2.3 TBLPTR – TABLE POINTER
REGISTER
The Table Pointer (TBLPTR) addresses a byte within
the program memory. The TBLPTR is comprised of
three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three registers
join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. Setting the 22nd bit allows
access to the device ID, the user ID and the
configuration bits.
The Table Pointer (TBLPTR) register is used by the
TBLRD and TBLWT instructions. These instructions can
update the TBLPTR in one of four ways based on the
table operation. These operations are shown in
Table 6-1. These operations on the TBLPTR only affect
the low-order 21 bits.
6.2.4 TABLE POINTER BOUNDARIES
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the Table
Pointer determine which byte is read from program or
configuration memory into TABLAT.
When a TBLWT is executed, the three LSbs of the Table
Pointer (TBLPTR<2:0>) determine which of the eight
program memory holding registers is written to. When
the timed write to program memory (long write) begins,
the 19 MSbs of the Table Pointer (TBLPTR<21:3>) will
determine which program memory block of 8 bytes is
written to (TBLPTR<2:0> are ignored). For more detail,
see Section 6.5 “Writing to Flash Program Memory”.
When an erase of program memory is executed, the
16 MSbs of the Table Pointer (TBLPTR<21:6>) point to
the 64-byte block that will be erased. The Least
Significant bits (TBLPTR<5:0>) are ignored.
Figure 6-3 describes the relevant boundaries of
TBLPTR based on Flash program memory operations.
TABLE 6-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
FIGURE 6-3: TABLE POINTER BOUNDARIES BASED ON OPERATION
Example Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLRD*-
TBLWT*-
TBLPTR is decremented after the read/write
TBLRD+*
TBLWT+*
TBLPTR is incremented before the read/write
21 16 15 8 7 0
ERASE – TBLPTR<21:6>
LONG WRITE – TBLPTR<21:3>
READ or WRITE – TBLPTR<21:0>
TBLPTRU TBLPTRH TBLPTRL© 2007 Microchip Technology Inc. DS39605F-page 61
PIC18F1220/1320
6.3 Reading the Flash Program
Memory
The TBLRD instruction is used to retrieve data from
program memory and place it into data RAM. Table
reads from program memory are performed one byte at
a time.
TBLPTR points to a byte address in program space.
Executing a TBLRD instruction places the byte pointed
to into TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 6-4
shows the interface between the internal program
memory and the TABLAT.
FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY
EXAMPLE 6-1: READING A FLASH PROGRAM MEMORY WORD
Odd (High) Byte
Program Memory
Even (Low) Byte
TABLAT
TBLPTR
Instruction Register
(IR) Read Register
LSB = 1
TBLPTR
LSB = 0
MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the word
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
READ_WORD
TBLRD*+ ; read into TABLAT and increment TBLPTR
MOVFW TABLAT ; get data
MOVWF WORD_EVEN
TBLRD*+ ; read into TABLAT and increment TBLPTR
MOVFW TABLAT ; get data
MOVWF WORD_ODDPIC18F1220/1320
DS39605F-page 62 © 2007 Microchip Technology Inc.
6.4 Erasing Flash Program Memory
The minimum erase block size is 32 words or 64 bytes
under firmware control. Only through the use of an
external programmer, or through ICSP control, can
larger blocks of program memory be bulk erased. Word
erase in Flash memory is not supported.
When initiating an erase sequence from the microcontroller
itself, a block of 64 bytes of program memory
is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased.
TBLPTR<5:0> are ignored.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the Flash
program memory. The CFGS bit must be clear to
access program Flash and data EEPROM memory.
The WREN bit must be set to enable write operations.
The FREE bit is set to select an erase operation. The
WR bit is set as part of the required instruction
sequence (as shown in Example 6-2) and starts the
actual erase operation. It is not necessary to load the
TABLAT register with any data as it is ignored.
For protection, the write initiate sequence using
EECON2 must be used.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
6.4.1 FLASH PROGRAM MEMORY
ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory location is:
1. Load Table Pointer with address of row being
erased.
2. Set the EECON1 register for the erase operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program
memory;
• set WREN bit to enable writes;
• set FREE bit to enable the erase.
3. Disable interrupts.
4. Write 55h to EECON2.
5. Write AAh to EECON2.
6. Set the WR bit. This will begin the row erase
cycle.
7. The CPU will stall for duration of the erase
(about 2 ms using internal timer).
8. Execute a NOP.
9. Re-enable interrupts.
EXAMPLE 6-2: ERASING A FLASH PROGRAM MEMORY ROW
MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW
MOVWF TBLPTRL
ERASE_ROW
BSF EECON1, EEPGD ; point to FLASH program memory
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable Row Erase operation
BCF INTCON, GIE ; disable interrupts
MOVLW 55h
MOVWF EECON2 ; write 55H
Required MOVLW AAh
Sequence MOVWF EECON2 ; write AAH
BSF EECON1, WR ; start erase (CPU stall)
NOP
BSF INTCON, GIE ; re-enable interrupts© 2007 Microchip Technology Inc. DS39605F-page 63
PIC18F1220/1320
6.5 Writing to Flash Program Memory
The programming block size is 4 words or 8 bytes.
Word or byte programming is not supported.
Table writes are used internally to load the holding
registers needed to program the Flash memory. There
are 8 holding registers used by the table writes for
programming.
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction must be executed 8 times for
each programming operation. All of the table write
operations will essentially be short writes, because only
the holding registers are written. At the end of updating
8 registers, the EECON1 register must be written to, to
start the programming operation with a long write.
The long write is necessary for programming the
internal Flash. Instruction execution is halted while in a
long write cycle. The long write will be terminated by
the internal programming timer.
FIGURE 6-5: TABLE WRITES TO FLASH PROGRAM MEMORY
6.5.1 FLASH PROGRAM MEMORY WRITE
SEQUENCE
The sequence of events for programming an internal
program memory location should be:
1. Read 64 bytes into RAM.
2. Update data values in RAM as necessary.
3. Load Table Pointer with address being erased.
4. Do the row erase procedure (see Section 6.4.1
“Flash Program Memory Erase Sequence”).
5. Load Table Pointer with address of first byte
being written.
6. Write the first 8 bytes into the holding registers
with auto-increment.
7. Set the EECON1 register for the write operation:
• set EEPGD bit to point to program memory;
• clear the CFGS bit to access program
memory;
• set WREN bit to enable byte writes.
8. Disable interrupts.
9. Write 55h to EECON2.
10. Write AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
2 ms using internal timer).
13. Execute a NOP.
14. Re-enable interrupts.
15. Repeat steps 6-14 seven times to write
64 bytes.
16. Verify the memory (table read).
This procedure will require about 18 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 6-3.
Holding Register
TABLAT
Holding Register
TBLPTR = xxxxx7
Holding Register
TBLPTR = xxxxx1
Holding Register
TBLPTR = xxxxx0
8 8 8 8
Write Register
TBLPTR = xxxxx2
Program MemoryPIC18F1220/1320
DS39605F-page 64 © 2007 Microchip Technology Inc.
EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY
MOVLW D'64 ; number of bytes in erase block
MOVWF COUNTER
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW ; 6 LSB = 0
MOVWF TBLPTRL
READ_BLOCK
TBLRD*+ ; read into TABLAT, and inc
MOVF TABLAT, W ; get data
MOVWF POSTINC0 ; store data and increment FSR0
DECFSZ COUNTER ; done?
GOTO READ_BLOCK ; repeat
MODIFY_WORD
MOVLW DATA_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW DATA_ADDR_LOW
MOVWF FSR0L
MOVLW NEW_DATA_LOW ; update buffer word and increment FSR0
MOVWF POSTINC0
MOVLW NEW_DATA_HIGH ; update buffer word
MOVWF INDF0
ERASE_BLOCK
MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base
MOVWF TBLPTRU ; address of the memory block
MOVLW CODE_ADDR_HIGH
MOVWF TBLPTRH
MOVLW CODE_ADDR_LOW ; 6 LSB = 0
MOVWF TBLPTRL
BCF EECON1, CFGS ; point to PROG/EEPROM memory
BSF EECON1, EEPGD ; point to FLASH program memory
BSF EECON1, WREN ; enable write to memory
BSF EECON1, FREE ; enable Row Erase operation
BCF INTCON, GIE ; disable interrupts
MOVLW 55h ; Required sequence
MOVWF EECON2 ; write 55H
MOVLW AAh
MOVWF EECON2 ; write AAH
BSF EECON1, WR ; start erase (CPU stall)
NOP
BSF INTCON, GIE ; re-enable interrupts
WRITE_BUFFER_BACK
MOVLW 8 ; number of write buffer groups of 8 bytes
MOVWF COUNTER_HI
MOVLW BUFFER_ADDR_HIGH ; point to buffer
MOVWF FSR0H
MOVLW BUFFER_ADDR_LOW
MOVWF FSR0L
PROGRAM_LOOP
MOVLW 8 ; number of bytes in holding register
MOVWF COUNTER© 2007 Microchip Technology Inc. DS39605F-page 65
PIC18F1220/1320
EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
6.5.2 WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the memory
should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
6.5.3 UNEXPECTED TERMINATION OF
WRITE OPERATION
If a write is terminated by an unplanned event, such as
loss of power or an unexpected Reset, the memory
location just programmed should be verified and reprogrammed
if needed. The WRERR bit is set when a
write operation is interrupted by a MCLR Reset, or a
WDT Time-out Reset during normal operation. In these
situations, users can check the WRERR bit and rewrite
the location.
6.6 Flash Program Operation During
Code Protection
See Section 19.0 “Special Features of the CPU” for
details on code protection of Flash program memory.
TABLE 6-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
WRITE_WORD_TO_HREGS
MOVF POSTINC0, W ; get low byte of buffer data and increment FSR0
MOVWF TABLAT ; present data to table latch
TBLWT+* ; short write
; to internal TBLWT holding register, increment
TBLPTR
DECFSZ COUNTER ; loop until buffers are full
GOTO WRITE_WORD_TO_HREGS
PROGRAM_MEMORY
BCF INTCON, GIE ; disable interrupts
MOVLW 55h ; required sequence
MOVWF EECON2 ; write 55H
MOVLW AAh
MOVWF EECON2 ; write AAH
BSF EECON1, WR ; start program (CPU stall)
NOP
BSF INTCON, GIE ; re-enable interrupts
DECFSZ COUNTER_HI ; loop until done
GOTO PROGRAM_LOOP
BCF EECON1, WREN ; disable write to memory
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
TBLPTRU — — bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 --00 0000
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 0000 0000
TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>) 0000 0000 0000 0000
TABLAT Program Memory Table Latch 0000 0000 0000 0000
INTCON GIE/GIEH PEIE/GIEL TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
EECON2 EEPROM Control Register 2 (not a physical register) — —
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 uu-0 u000
IPR2 OSCFIP — — EEIP — LVDIP TMR3IP — 1--1 -11- 1--1 -11-
PIR2 OSCFIF — — EEIF — LVDIF TMR3IF — 0--0 -00- 0--0 -00-
PIE2 OSCFIE — — EEIE — LVDIE TMR3IE — 0--0 -00- 0--0 -00-
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.PIC18F1220/1320
DS39605F-page 66 © 2007 Microchip Technology Inc.
NOTES:© 2007 Microchip Technology Inc. DS39605F-page 67
PIC18F1220/1320
7.0 DATA EEPROM MEMORY
The data EEPROM is readable and writable during
normal operation over the entire VDD range. The data
memory is not directly mapped in the register file
space. Instead, it is indirectly addressed through the
Special Function Registers (SFR).
There are four SFRs used to read and write the
program and data EEPROM memory. These registers
are:
• EECON1
• EECON2
• EEDATA
• EEADR
The EEPROM data memory allows byte read and write.
When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write and EEADR holds the
address of the EEPROM location being accessed.
These devices have 256 bytes of data EEPROM with
an address range from 00h to FFh.
The EEPROM data memory is rated for high erase/
write cycle endurance. A byte write automatically
erases the location and writes the new data (erasebefore-write).
The write time is controlled by an on-chip
timer. The write time will vary with voltage and
temperature, as well as from chip to chip. Please
refer to parameter D122 (Table 22-1 in Section 22.0
“Electrical Characteristics”) for exact limits.
7.1 EEADR
The address register can address 256 bytes of data
EEPROM.
7.2 EECON1 and EECON2 Registers
EECON1 is the control register for memory accesses.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the memory write and erase sequences.
Control bit, EEPGD, determines if the access will be to
program or data EEPROM memory. When clear,
operations will access the data EEPROM memory.
When set, program memory is accessed.
Control bit, CFGS, determines if the access will be to
the configuration registers or to program memory/data
EEPROM memory. When set, subsequent operations
access configuration registers. When CFGS is clear,
the EEPGD bit selects either program Flash or data
EEPROM memory.
The WREN bit enables and disables erase and write
operations. When set, erase and write operations are
allowed. When clear, erase and write operations are
disabled – the WR bit cannot be set while the WREN bit
is clear. This mechanism helps to prevent accidental
writes to memory due to errant (unexpected) code
execution.
Firmware should keep the WREN bit clear at all times,
except when starting erase or write operations. Once
firmware has set the WR bit, the WREN bit may be
cleared. Clearing the WREN bit will not affect the
operation in progress.
The WRERR bit is set when a write operation is
interrupted by a Reset. In these situations, the user can
check the WRERR bit and rewrite the location. It is
necessary to reload the data and address registers
(EEDATA and EEADR), as these registers have
cleared as a result of the Reset.
Control bits, RD and WR, start read and erase/write
operations, respectively. These bits are set by firmware
and cleared by hardware at the completion of the
operation.
The RD bit cannot be set when accessing program
memory (EEPGD = 1). Program memory is read using
table read instructions. See Section 6.1 “Table Reads
and Table Writes” regarding table reads.
Note: Interrupt flag bit, EEIF in the PIR2 register,
is set when write is complete. It must be
cleared in software.PIC18F1220/1320
DS39605F-page 68 © 2007 Microchip Technology Inc.
REGISTER 7-1: EECON1 REGISTER
R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0
EEPGD CFGS — FREE WRERR WREN WR RD
bit 7 bit 0
bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access program Flash memory
0 = Access data EEPROM memory
bit 6 CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access configuration or calibration registers
0 = Access program Flash or data EEPROM memory
bit 5 Unimplemented: Read as ‘0’
bit 4 FREE: Flash Row Erase Enable bit
1 = Erase the program memory row addressed by TBLPTR on the next WR command
(cleared by completion of erase operation)
0 = Perform write only
bit 3 WRERR: EEPROM Error Flag bit
1 = A write operation was prematurely terminated
(MCLR or WDT Reset during self-timed erase or program operation)
0 = The write operation completed normally
Note: When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows
tracing of the error condition.
bit 2 WREN: Erase/Write Enable bit
1 = Allows erase/write cycles
0 = Inhibits erase/write cycles
bit 1 WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle, or a program memory erase cycle, or write cycle.
(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)
0 = Write cycle is completed
bit 0 RD: Read Control bit
1 = Initiates a memory read
(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)
in software. RD bit cannot be set when EEPGD = 1.)
0 = Read completed
Legend:
R = Readable bit S = Settable only U = Unimplemented bit, read as ‘0’
W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared
x = Bit is unknown© 2007 Microchip Technology Inc. DS39605F-page 69
PIC18F1220/1320
7.3 Reading the Data EEPROM
Memory
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD
control bit (EECON1<7>) and then set control bit, RD
(EECON1<0>). The data is available for the very next
instruction cycle; therefore, the EEDATA register can
be read by the next instruction. EEDATA will hold this
value until another read operation, or until it is written to
by the user (during a write operation).
7.4 Writing to the Data EEPROM
Memory
To write an EEPROM data location, the address must
first be written to the EEADR register and the data
written to the EEDATA register. The sequence in
Example 7-2 must be followed to initiate the write cycle.
The write will not begin if this sequence is not exactly
followed (write 55h to EECON2, write AAh to EECON2,
then set WR bit) for each byte. It is strongly recommended
that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code execution
(i.e., runaway programs). The WREN bit should
be kept clear at all times, except when updating the
EEPROM. The WREN bit is not cleared by hardware.
After a write sequence has been initiated, EECON1,
EEADR and EEDATA cannot be modified. The WR bit
will be inhibited from being set unless the WREN bit is
set. The WREN bit must be set on a previous instruction.
Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Interrupt Flag bit
(EEIF) is set. The user may either enable this interrupt
or poll this bit. EEIF must be cleared by software.
7.5 Write Verify
Depending on the application, good programming
practice may dictate that the value written to the
memory should be verified against the original value.
This should be used in applications where excessive
writes can stress bits near the specification limit.
7.6 Protection Against Spurious Write
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared.
Also, the Power-up Timer (72 ms duration) prevents
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch or software malfunction.
EXAMPLE 7-1: DATA EEPROM READ
EXAMPLE 7-2: DATA EEPROM WRITE
MOVLW DATA_EE_ADDR ;
MOVWF EEADR ; Data Memory Address to read
BCF EECON1, EEPGD ; Point to DATA memory
BSF EECON1, RD ; EEPROM Read
MOVF EEDATA, W ; W = EEDATA
MOVLW DATA_EE_ADDR ;
MOVWF EEADR ; Data Memory Address to write
MOVLW DATA_EE_DATA ;
MOVWF EEDATA ; Data Memory Value to write
BCF EECON1, EEPGD ; Point to DATA memory
BSF EECON1, WREN ; Enable writes
BCF INTCON, GIE ; Disable Interrupts
MOVLW 55h ;
Required MOVWF EECON2 ; Write 55h
Sequence MOVLW AAh ;
MOVWF EECON2 ; Write AAh
BSF EECON1, WR ; Set WR bit to begin write
BSF INTCON, GIE ; Enable Interrupts
SLEEP ; Wait for interrupt to signal write complete
BCF EECON1, WREN ; Disable writesPIC18F1220/1320
DS39605F-page 70 © 2007 Microchip Technology Inc.
7.7 Operation During Code-Protect
Data EEPROM memory has its own code-protect bits in
configuration words. External read and write
operations are disabled if either of these mechanisms
are enabled.
The microcontroller itself can both read and write to the
internal data EEPROM, regardless of the state of the
code-protect configuration bit. Refer to Section 19.0
“Special Features of the CPU” for additional
information.
7.8 Using the Data EEPROM
The data EEPROM is a high endurance, byte addressable
array that has been optimized for the storage of frequently
changing information (e.g., program variables or
other data that are updated often). Frequently changing
values will typically be updated more often than specification
D124. If this is not the case, an array refresh must
be performed. For this reason, variables that change
infrequently (such as constants, IDs, calibration, etc.)
should be stored in Flash program memory.
A simple data EEPROM refresh routine is shown in
Example 7-3.
EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE
TABLE 7-1: REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Note: If data EEPROM is only used to store
constants and/or data that changes rarely,
an array refresh is likely not required. See
specification D124.
CLRF EEADR ; Start at address 0
BCF EECON1, CFGS ; Set for memory
BCF EECON1, EEPGD ; Set for Data EEPROM
BCF INTCON, GIE ; Disable interrupts
BSF EECON1, WREN ; Enable writes
Loop ; Loop to refresh array
BSF EECON1, RD ; Read current address
MOVLW 55h ;
MOVWF EECON2 ; Write 55h
MOVLW AAh ;
MOVWF EECON2 ; Write AAh
BSF EECON1, WR ; Set WR bit to begin write
BTFSC EECON1, WR ; Wait for write to complete
BRA $-2
INCFSZ EEADR, F ; Increment address
BRA Loop ; Not zero, do it again
BCF EECON1, WREN ; Disable writes
BSF INTCON, GIE ; Enable interrupts
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:
POR, BOR
Value on
all other
Resets
INTCON GIE/GIEH PEIE/GIEL TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
EEADR EEPROM Address Register 0000 0000 0000 0000
EEDATA EEPROM Data Register 0000 0000 0000 0000
EECON2 EEPROM Control Register 2 (not a physical register) — —
EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 uu-0 u000
IPR2 OSCFIP — — EEIP — LVDIP TMR3IP — 1--1 -11- 1--1 -11-
PIR2 OSCFIF — — EEIF — LVDIF TMR3IF — 0--0 -00- 0--0 -00-
PIE2 OSCFIE — — EEIE — LVDIE TMR3IE — 0--0 -00- 0--0 -00-
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.© 2007 Microchip Technology Inc. DS39605F-page 71
PIC18F1220/1320
8.0 8 x 8 HARDWARE MULTIPLIER
8.1 Introduction
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18F1220/1320 devices. By making the multiply
a hardware operation, it completes in a single instruction
cycle. This is an unsigned multiply that gives a
16-bit result. The result is stored into the 16-bit product
register pair (PRODH:PRODL). The multiplier does not
affect any flags in the Status register.
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
• Higher computational throughput
• Reduces code size requirements for multiply
algorithms
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 8-1 shows a performance comparison between
Enhanced devices using the single-cycle hardware
multiply and performing the same function without the
hardware multiply.
TABLE 8-1: PERFORMANCE COMPARISON
8.2 Operation
Example 8-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 8-1: 8 x 8 UNSIGNED
MULTIPLY ROUTINE
EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY
ROUTINE
Routine Multiply Method
Program
Memory
(Words)
Cycles
(Max)
Time
@ 40 MHz @ 10 MHz @ 4 MHz
8 x 8 unsigned Without hardware multiply 13 69 6.9 μs 27.6 μs 69 μs
Hardware multiply 1 1 100 ns 400 ns 1 μs
8 x 8 signed Without hardware multiply 33 91 9.1 μs 36.4 μs 91 μs
Hardware multiply 6 6 600 ns 2.4 μs 6 μs
16 x 16 unsigned Without hardware multiply 21 242 24.2 μs 96.8 μs 242 μs
Hardware multiply 28 28 2.8 μs 11.2 μs 28 μs
16 x 16 signed Without hardware multiply 52 254 25.4 μs 102.6 μs 254 μs
Hardware multiply 35 40 4 μs 16 μs 40 μs
MOVF ARG1, W ;
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
MOVF ARG1, W
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
BTFSC ARG2, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG1
MOVF ARG2, W
BTFSC ARG1, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG2 PIC18F1220/1320
DS39605F-page 72 © 2007 Microchip Technology Inc.
Example 8-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 8-1 shows the algorithm
that is used. The 32-bit result is stored in four registers,
RES3:RES0.
EQUATION 8-1: 16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
EXAMPLE 8-3: 16 x 16 UNSIGNED
MULTIPLY ROUTINE
Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers,
RES3:RES0. To account for the sign bits of the arguments,
each argument pairs’ Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
EQUATION 8-2: 16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
EXAMPLE 8-4: 16 x 16 SIGNED
MULTIPLY ROUTINE
MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L ->
; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;
;
MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H ->
; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;
;
MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3,F ;
;
MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
RES3:RES0
= ARG1H:ARG1L • ARG2H:ARG2L
= (ARG1H • ARG2H • 216) +
(ARG1H • ARG2L • 28
) +
(ARG1L • ARG2H • 28
) +
(ARG1L • ARG2L)
MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L ->
; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;
;
MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H ->
; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;
;
MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
;
MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG ;
ADDWFC RES3, F ;
;
BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?
BRA SIGN_ARG1 ; no, check ARG1
MOVF ARG1L, W ;
SUBWF RES2 ;
MOVF ARG1H, W ;
SUBWFB RES3
;
SIGN_ARG1
BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?
BRA CONT_CODE ; no, done
MOVF ARG2L, W ;
SUBWF RES2 ;
MOVF ARG2H, W ;
SUBWFB RES3
;
CONT_CODE
:
RES3:RES0
= ARG1H:ARG1L • ARG2H:ARG2L
= (ARG1H • ARG2H • 216) +
(ARG1H • ARG2L • 28) +
(ARG1L • ARG2H • 28) +
(ARG1L • ARG2L) +
(-1 • ARG2H<7> • ARG1H:ARG1L • 216) +
(-1 • ARG1H<7> • ARG2H:ARG2L • 216) © 2007 Microchip Technology Inc. DS39605F-page 73
PIC18F1220/1320
9.0 INTERRUPTS
The PIC18F1220/1320 devices have multiple interrupt
sources and an interrupt priority feature that allows
each interrupt source to be assigned a high priority
level or a low priority level. The high priority interrupt
vector is at 000008h and the low priority interrupt vector
is at 000018h. High priority interrupt events will
interrupt any low priority interrupts that may be in
progress.
There are ten registers which are used to control
interrupt operation. These registers are:
• RCON
• INTCON
• INTCON2
• INTCON3
• PIR1, PIR2
• PIE1, PIE2
• IPR1, IPR2
It is recommended that the Microchip header files
supplied with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the assembler/
compiler to automatically take care of the placement of
these bits within the specified register.
In general, each interrupt source has three bits to
control its operation. The functions of these bits are:
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high priority or low priority
(INT0 has no priority bit and is always high priority)
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts
globally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set (high priority).
Setting the GIEL bit (INTCON<6>) enables all
interrupts that have the priority bit cleared (low priority).
When the interrupt flag, enable bit and appropriate
global interrupt enable bit are set, the interrupt will
vector immediately to address 000008h or 000018h,
depending on the priority bit setting. Individual
interrupts can be disabled through their corresponding
enable bits.
When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PIC mid-range devices. In
Compatibility mode, the interrupt priority bits for each
source have no effect. INTCON<6> is the PEIE bit,
which enables/disables all peripheral interrupt sources.
INTCON<7> is the GIE bit, which enables/disables all
interrupt sources. All interrupts branch to address
000008h in Compatibility mode.
When an interrupt is responded to, the global interrupt
enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High priority interrupt sources can interrupt a low
priority interrupt. Low priority interrupts are not
processed while high priority interrupts are in progress.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the Interrupt Service
Routine, the source(s) of the interrupt can be determined
by polling the interrupt flag bits. The interrupt
flag bits must be cleared in software before re-enabling
interrupts to avoid recursive interrupts.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or
GIEL, if priority levels are used), which re-enables
interrupts.
For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set, regardless of the
status of their corresponding enable bit or the GIE bit.
Note: Do not use the MOVFF instruction to modify
any of the interrupt control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.PIC18F1220/1320
DS39605F-page 74 © 2007 Microchip Technology Inc.
FIGURE 9-1: INTERRUPT LOGIC
TMR0IE
GIEH/GIE
GIEL/PEIE
Wake-up if in Low-Power Mode
Interrupt to CPU
Vector to Location
0008h
INT2IF
INT2IE
INT2IP
INT1IF
INT1IE
INT1IP
TMR0IF
TMR0IE
TMR0IP
INT0IF
INT0IE
RBIF
RBIE
RBIP
IPEN
TMR0IF
TMR0IP
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
GIEL\PEIE
Interrupt to CPU
Vector to Location
IPEN
IPEN
0018h
INT0IF
INT0IE
INT0IF
INT0IE
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
Additional Peripheral Interrupts
ADIF
ADIE
ADIP
High Priority Interrupt Generation
Low Priority Interrupt Generation
RCIF
RCIE
RCIP
Additional Peripheral Interrupts
GIE\GIEH© 2007 Microchip Technology Inc. DS39605F-page 75
PIC18F1220/1320
9.1 INTCON Registers
The INTCON registers are readable and writable
registers, which contain various enable, priority and
flag bits.
REGISTER 9-1: INTCON REGISTER
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
interrupt enable bit. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
This feature allows for software polling.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
bit 7 bit 0
bit 7 GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts
When IPEN = 1:
1 = Enables all high priority interrupts
0 = Disables all interrupts
bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low priority peripheral interrupts
0 = Disables all low priority peripheral interrupts
bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4 INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Note: A mismatch condition will continue to set this bit. Reading PORTB will end the
mismatch condition and allow the bit to be cleared.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknownPIC18F1220/1320
DS39605F-page 76 © 2007 Microchip Technology Inc.
REGISTER 9-2: INTCON2 REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1
RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP
bit 7 bit 0
bit 7 RBPU: PORTB Pull-up Enable bit
1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG0: External Interrupt 0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 5 INTEDG1: External Interrupt 1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 4 INTEDG2: External Interrupt 2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 3 Unimplemented: Read as ‘0’
bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 Unimplemented: Read as ‘0’
bit 0 RBIP: RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global interrupt enable bit. User software
should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt. This feature allows for software polling.© 2007 Microchip Technology Inc. DS39605F-page 77
PIC18F1220/1320
REGISTER 9-3: INTCON3 REGISTER
R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF
bit 7 bit 0
bit 7 INT2IP: INT2 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6 INT1IP: INT1 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 Unimplemented: Read as ‘0’
bit 4 INT2IE: INT2 External Interrupt Enable bit
1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt
bit 3 INT1IE: INT1 External Interrupt Enable bit
1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt
bit 2 Unimplemented: Read as ‘0’
bit 1 INT2IF: INT2 External Interrupt Flag bit
1 = The INT2 external interrupt occurred (must be cleared in software)
0 = The INT2 external interrupt did not occur
bit 0 INT1IF: INT1 External Interrupt Flag bit
1 = The INT1 external interrupt occurred (must be cleared in software)
0 = The INT1 external interrupt did not occur
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global interrupt enable bit. User software
should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt. This feature allows for software polling.PIC18F1220/1320
DS39605F-page 78 © 2007 Microchip Technology Inc.
9.2 PIR Registers
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2).
REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
Note 1: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE (INTCON<7>).
2: User software should ensure the appropriate
interrupt flag bits are cleared prior to
enabling an interrupt and after servicing
that interrupt.
U-0 R/W-0 R-0 R-0 U-0 R/W-0 R/W-0 R/W-0
— ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5 RCIF: EUSART Receive Interrupt Flag bit
1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)
0 = The EUSART receive buffer is empty
bit 4 TXIF: EUSART Transmit Interrupt Flag bit
1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0 = The EUSART transmit buffer is full
bit 3 Unimplemented: Read as ‘0’
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown© 2007 Microchip Technology Inc. DS39605F-page 79
PIC18F1220/1320
REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 U-0
OSCFIF — — EEIF — LVDIF TMR3IF —
bit 7 bit 0
bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit
1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = System clock operating
bit 6-5 Unimplemented: Read as ‘0’
bit 4 EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit
1 = The write operation is complete (must be cleared in software)
0 = The write operation is not complete or has not been started
bit 3 Unimplemented: Read as ‘0’
bit 2 LVDIF: Low-Voltage Detect Interrupt Flag bit
1 = A low-voltage condition occurred (must be cleared in software)
0 = The device voltage is above the Low-Voltage Detect trip point
bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 register overflowed (must be cleared in software)
0 = TMR3 register did not over