9541I–AT42–05/2013
Features
Number of Keys:
One – configurable as either a single key or a proximity sensor
Technology:
Patented spread-spectrum charge-transfer (direct mode)
Key outline sizes:
6 mm × 6 mm or larger (panel thickness dependent); widely different sizes and
shapes possible
Electrode design:
Solid or ring electrode shapes
PCB Layers required:
One
Electrode materials:
Etched copper, silver, carbon, Indium Tin Oxide (ITO)
Electrode substrates:
PCB, FPCB, plastic films, glass
Panel materials:
Plastic, glass, composites, painted surfaces (low particle density metallic
paints possible)
Panel thickness:
Up to 12 mm glass, 6 mm plastic (electrode size and Cs dependent)
Key sensitivity:
Settable via capacitor (Cs)
Interface:
Digital output, active high
Moisture tolerance:
Increased moisture tolerance based on hardware design and firmware tuning
Operating Voltage:
1.8 V – 5.5 V; 17 µA at 1.8 V typical
Package:
6-pin SOT23-6 RoHS compliant
8-pin UDFN/USON RoHS compliant
Signal processing:
Self-calibration, auto drift compensation, noise filtering
Applications:
Control panels, consumer appliances, proximity sensor applications, toys,
lighting controls, mechanical switch or button,
Patents:
QTouch® (patented charge-transfer method)
HeartBeat (monitors health of device)
Atmel AT42QT1010
Single-key QTouch® Touch Sensor IC
DATASHEETAT42QT1010 [DATASHEET] 2
9541I–AT42–05/2013
1. Pinout and Schematic
1.1 Pinout Configurations
1.1.1 6-pin SOT23-6
1.1.2 8-pin UDFN/USON
Pin 1 ID
OUT
SNS
VDD
SYNC/
MODE
SNSK
VSS
1 6
5
3 4
2
Pin 1 ID
OUT
SNSK
VSS
SNS
VDD
SYNC/MODE
N/C
N/C
4
3
2
1 8
7
6
5AT42QT1010 [DATASHEET] 3 9541I–AT42–05/2013
1.2 Pin Descriptions
1.2.1 6-pin SOT23-6
I Input only O Output only, push-pull I/O Input/output
OD Open drain output P Ground or power
1.2.2 8-pin UDFN/USON
I Input only O Output only, push-pull I/O Input/output
OD Open drain output P Ground or power
Table 1-1. Pin Listing
Name Pin Type Comments If Unused, Connect To...
OUT 1 O Output state –
VSS 2 P Supply ground –
SNSK 3 I/O Sense pin Cs + Key
SNS 4 I/O Sense pin Cs
VDD 5 P Power –
SYNC 6 I SYNC and Mode Input Pin is either SYNC/Slow/Fast Mode, depending on logic
level applied (see Section 3.1 on page 7)
Table 1-2. Pin Listing
Name Pin Type Comments If Unused, Connect To...
SNSK 1 I/O Sense pin Cs + Key
N/C 2 – No connection –
N/C 3 – No connection –
VSS 4 P Supply ground –
OUT 5 O Output state –
SYNC/
MODE 6 I SYNC and Mode Input Pin is either SYNC/Slow/Fast Mode, depending on logic
level applied (see Section 3.1 on page 7)
VDD 7 P Power –
SNS 8 I/O Sense pin CsAT42QT1010 [DATASHEET] 4
9541I–AT42–05/2013
1.3 Schematics
1.3.1 6-pin SOT23-6
Figure 1-1. Basic Circuit Configuration
1.3.2 8-pin UDFN/USON
Figure 1-2. Basic Circuit Configuration
Cs
OUT
VDD
SNSK
SNS
SYNC/MODE
VSS
2
6
4
1 3
5
VDD
Rs
Cx
SENSE
ELECTRODE
Note: A bypass capacitor should be tightly wired
between Vdd and Vss and kept close to pin 5.
Cs
OUT
VDD
SNSK
SNS
SYNC/MODE
VSS
4
6
8
5 1
7
Vdd
Rs
Cx
SENSE
ELECTRODE
Note: A bypass capacitor should be tightly wired
between Vdd and Vss and kept close to pin 5.
2
3
NC
NCAT42QT1010 [DATASHEET] 5 9541I–AT42–05/2013
2. Overview of the AT42QT1010
2.1 Introduction
The AT42QT1010 (QT1010) is a digital burst mode charge-transfer (QT™) sensor that is capable of detecting nearproximity
or touch, making it ideal for implementing touch controls.
With the proper electrode and circuit design, the self-contained digital IC will project a touch or proximity field to
several centimeters through any dielectric like glass, plastic, stone, ceramic, and even most kinds of wood. It can
also turn small metal-bearing objects into intrinsic sensors, making them responsive to proximity or touch. This
capability, coupled with its ability to self-calibrate, can lead to entirely new product concepts.
The QT1010 is designed specifically for human interfaces, like control panels, appliances, toys, lighting controls, or
anywhere a mechanical switch or button may be found. It includes all hardware and signal processing functions
necessary to provide stable sensing under a wide variety of changing conditions. Only a single low-cost capacitor is
required for operation.
2.2 Basic Operation
Figure 1-1 on page 4 and Figure 1-2 on page 4 show basic circuits.
The QT1010 employs bursts of charge-transfer cycles to acquire its signal. Burst mode permits power consumption
in the microamp range, dramatically reduces RF emissions, lowers susceptibility to EMI, and yet permits excellent
response time. Internally the signals are digitally processed to reject impulse noise, using a “consensus” filter which
requires four consecutive confirmations of a detection before the output is activated.
The QT switches and charge measurement hardware functions are all internal to the QT1010.
2.3 Electrode Drive
For optimum noise immunity, the electrode should only be connected to SNSK.
In all cases the rule Cs >> Cx must be observed for proper operation; a typical load capacitance (Cx) ranges from
5 – 20 pF while Cs is usually about 2 – 50 nF.
Increasing amounts of Cx destroy gain, therefore it is important to limit the amount of stray capacitance on both SNS
terminals. This can be done, for example, by minimizing trace lengths and widths and keeping these traces away
from power or ground traces or copper pours.
The traces and any components associated with SNS and SNSK will become touch sensitive and should be treated
with caution to limit the touch area to the desired location.
A series resistor, Rs, should be placed in line with SNSK to the electrode to suppress ESD and EMC effects.
2.4 Sensitivity
2.4.1 Introduction
The sensitivity on the QT1010 is a function of things like the value of Cs, electrode size and capacitance, electrode
shape and orientation, the composition and aspect of the object to be sensed, the thickness and composition of any
overlaying panel material, and the degree of ground coupling of both sensor and object.
2.4.2 Increasing Sensitivity
In some cases it may be desirable to increase sensitivity; for example, when using the sensor with very thick panels
having a low dielectric constant, or when the device is used as a proximity sensor. Sensitivity can often be increased
by using a larger electrode or reducing panel thickness. Increasing electrode size can have diminishing returns, as
high values of Cx will reduce sensor gain. AT42QT1010 [DATASHEET] 6
9541I–AT42–05/2013
The value of Cs also has a dramatic effect on sensitivity, and this can be increased in value with the trade-off of
slower response time and more power. Increasing the electrode's surface area will not substantially increase touch
sensitivity if its diameter is already much larger in surface area than the object being detected. Panel material can
also be changed to one having a higher dielectric constant, which will better help to propagate the field.
In the case of proximity detection, usually the object being detected is on an approaching hand, so a larger surface
area can be effective.
Ground planes around and under the electrode and its SNSK trace will cause high Cx loading and destroy gain. The
possible signal-to-noise ratio benefits of ground area are more than negated by the decreased gain from the circuit,
and so ground areas around electrodes are discouraged. Metal areas near the electrode will reduce the field strength
and increase Cx loading and should be avoided, if possible. Keep ground away from the electrodes and traces.
2.4.3 Decreasing Sensitivity
In some cases the QT1010 may be too sensitive. In this case gain can be easily lowered further by decreasing Cs.
2.4.4 Proximity Sensing
By increasing the sensitivity, the QT1010 can be used as a very effective proximity sensor, allowing the presence of
a nearby object (typically a hand) to be detected.
In this scenario, as the object being sensed is typically a hand, very large electrode sizes can be used, which is
extremely effective in increasing the sensitivity of the detector. In this case, the value of Cs will also need to be
increased to ensure improved sensitivity, as mentioned in Section 2.4.2. Note that, although this affects the
responsiveness of the sensor, it is less of an issue in proximity sensing applications; in such applications it is
necessary to detect simply the presence of a large object, rather than a small, precise touch.AT42QT1010 [DATASHEET] 7 9541I–AT42–05/2013
3. Operation Specifics
3.1 Run Modes
3.1.1 Introduction
The QT1010 has three running modes which depend on the state of the SYNC pin (high or low).
3.1.2 Fast Mode
The QT1010 runs in Fast mode if the SYNC pin is permanently high. In this mode the QT1010 runs at maximum
speed at the expense of increased current consumption. Fast mode is useful when speed of response is the prime
design requirement. The delay between bursts in Fast mode is approximately 1 ms, as shown in Figure 3-1.
Figure 3-1. Fast Mode Bursts (SYNC Held High)
3.1.3 Low Power Mode
The QT1010 runs in Low Power (LP) mode if the SYNC pin is held low. In this mode it sleeps for approximately
80 ms at the end of each burst, saving power but slowing response. On detecting a possible key touch, it temporarily
switches to Fast mode until either the key touch is confirmed or found to be spurious (via the detect integration
process). It then returns to LP mode after the key touch is resolved, as shown in Figure 3-2.
Figure 3-2. Low Power Mode (SYNC Held Low)
SNSK
SYNC
~1 ms
sleep sleep
SYNC
SNSK sleep
fast detect
integrator
OUT
Key
~80 ms
touchAT42QT1010 [DATASHEET] 8
9541I–AT42–05/2013
3.1.4 SYNC Mode
It is possible to synchronize the device to an external clock source by placing an appropriate waveform on the SYNC
pin. SYNC mode can synchronize multiple QT1010 devices to each other to prevent cross-interference, or it can be
used to enhance noise immunity from low frequency sources such as 50Hz or 60Hz mains signals.
The SYNC pin is sampled at the end of each burst. If the device is in Fast mode and the SYNC pin is sampled high,
then the device continues to operate in Fast mode (Figure 3-1 on page 7). If SYNC is sampled low, then the device
goes to sleep. From then on, it will operate in SYNC mode (Figure 3-2). Therefore, to guarantee entry into SYNC
mode the low period of the SYNC signal should be longer than the burst length (Figure 3-3).
Figure 3-3. SYNC Mode (Triggered by SYNC Edges)
However, once SYNC mode has been entered, if the SYNC signal consists of a series of short pulses (>10 µs) then
a burst will only occur on the falling edge of each pulse (Figure 3-4) instead of on each change of SYNC signal, as
normal (Figure 3-3).
In SYNC mode, the device will sleep after each measurement burst (just as in LP mode) but will be awakened by a
change in the SYNC signal in either direction, resulting in a new measurement burst. If SYNC remains unchanged
for a period longer than the LP mode sleep period (about 80 ms), the device will resume operation in either Fast or
LP mode depending on the level of the SYNC pin (Figure 3-3).
There is no detect integrator (DI) in SYNC mode (each touch is a detection) but the Max On-duration will depend on
the time between SYNC pulses; see Section 3.3 and Section 3.4 on page 9. Recalibration timeout is a fixed number
of measurements so will vary with the SYNC period.
Figure 3-4. SYNC Mode (Short Pulses)
SYNC
SYNC
SNSK
SNSK
slow mode sleep period
sleep
sleep
sleep sleep
sleep sleep
Revert to Fast Mode
Revert to Slow Mode
slow mode sleep period
SNSK
SYNC
>10 sμ >10 sμ >10 sμAT42QT1010 [DATASHEET] 9 9541I–AT42–05/2013
3.2 Threshold
The internal signal threshold level is fixed at 10 counts of change with respect to the internal reference level, which in
turn adjusts itself slowly in accordance with the drift compensation mechanism.
The QT1010 employs a hysteresis dropout of two counts of the delta between the reference and threshold levels.
3.3 Max On-duration
If an object or material obstructs the sense pad the signal may rise enough to create a detection, preventing further
operation. To prevent this, the sensor includes a timer which monitors detections. If a detection exceeds the timer
setting the sensor performs a full recalibration. This is known as the Max On-duration feature and is set to ~60s (at
3V in LP mode). This will vary slightly with Cs and if SYNC mode is used. As the internal timebase for Max Onduration
is determined by the burst rate, the use of SYNC can cause dramatic changes in this parameter depending
on the SYNC pulse spacing. For example, at 60Hz SYNC mode the Max On-duration will be ~6s at 3V.
3.4 Detect Integrator
It is desirable to suppress detections generated by electrical noise or from quick brushes with an object. To
accomplish this, the QT1010 incorporates a detect integration (DI) counter that increments with each detection until
a limit is reached, after which the output is activated. If no detection is sensed prior to the final count, the counter is
reset immediately to zero. In the QT1010, the required count is four. In LP mode the device will switch to Fast mode
temporarily in order to resolve the detection more quickly; after a touch is either confirmed or denied the device will
revert back to normal LP mode operation automatically.
The DI can also be viewed as a “consensus filter” that requires four successive detections to create an output.
3.5 Forced Sensor Recalibration
The QT1010 has no recalibration pin; a forced recalibration is accomplished when the device is powered up or after
the recalibration timeout. However, supply drain is low so it is a simple matter to treat the entire IC as a controllable
load; driving the QT1010's Vdd pin directly from another logic gate or a microcontroller port will serve as both power
and “forced recalibration”. The source resistance of most CMOS gates and microcontrollers is low enough to provide
direct power without problem.
3.6 Drift Compensation
Signal drift can occur because of changes in Cx and Cs over time. It is crucial that drift be compensated for,
otherwise false detections, non-detections, and sensitivity shifts will follow.
Drift compensation (Figure 3-5) is performed by making the reference level track the raw signal at a slow rate, but
only while there is no detection in effect. The rate of adjustment must be performed slowly, otherwise legitimate
detections could be ignored. The QT1010 drift compensates using a slew-rate limited change to the reference level;
the threshold and hysteresis values are slaved to this reference.
Once an object is sensed, the drift compensation mechanism ceases since the signal is legitimately high, and
therefore should not cause the reference level to change.AT42QT1010 [DATASHEET] 10
9541I–AT42–05/2013
Figure 3-5. Drift Compensation
The QT1010 drift compensation is asymmetric; the reference level drift-compensates in one direction faster than it
does in the other. Specifically, it compensates faster for decreasing signals than for increasing signals. Increasing
signals should not be compensated for quickly, since an approaching finger could be compensated for partially or
entirely before even approaching the sense electrode. However, an obstruction over the sense pad, for which the
sensor has already made full allowance, could suddenly be removed leaving the sensor with an artificially elevated
reference level and thus become insensitive to touch. In this latter case, the sensor will compensate for the object's
removal very quickly, usually in only a few seconds.
With large values of Cs and small values of Cx, drift compensation will appear to operate more slowly than with the
converse. Note that the positive and negative drift compensation rates are different.
3.7 Response Time
The QT1010's response time is highly dependent on run mode and burst length, which in turn is dependent on Cs
and Cx. With increasing Cs, response time slows, while increasing levels of Cx reduce response time. The response
time will also be a lot slower in LP or SYNC mode due to a longer time between burst measurements.
3.8 Spread Spectrum
The QT1010 modulates its internal oscillator by ±7.5% during the measurement burst. This spreads the generated
noise over a wider band, reducing emission levels. This also reduces susceptibility since there is no longer a single
fundamental burst frequency.
3.9 Output Features
3.9.1 Output
The output of the QT1010 is active-high upon detection. The output will remain active-high for the duration of the
detection, or until the Max On-duration expires, whichever occurs first. If a Max On-duration timeout occurs first, the
sensor performs a full recalibration and the output becomes inactive (low) until the next detection.
3.9.2 HeartBeat Output
The QT1010 output has a HeartBeat “health” indicator superimposed on it in all modes. This operates by taking the
output pin into a three-state mode for 15 µs, once before every QT burst. This output state can be used to determine
that the sensor is operating properly, using one of several simple methods, or it can be ignored.
The HeartBeat indicator can be sampled by using a pull-up resistor on the OUT pin (Figure 3-6), and feeding the
resulting positive-going pulse into a counter, flip flop, one-shot, or other circuit. The pulses will only be visible when
the chip is not detecting a touch.
Threshold
Signal
Hysteresis
Reference
OutputAT42QT1010 [DATASHEET] 11 9541I–AT42–05/2013
Figure 3-6. Obtaining HeartBeat Pulses with a Pull-up Resistor (SOT23-6)
If the sensor is wired to a microcontroller as shown in Figure 3-7 on page 11, the microcontroller can reconfigure the
load resistor to either Vss or Vdd depending on the output state of the QT1010, so that the pulses are evident in
either state.
Figure 3-7. Using a Microcontroller to Obtain HeartBeat Pulses in Either Output State (SOT23-6)
Electromechanical devices like relays will usually ignore the short HeartBeat pulse. The pulse also has too low a duty
cycle to visibly affect LEDs. It can be filtered completely if desired, by adding an RC filter to the output, or if
interfacing directly and only to a high-impedance CMOS input, by doing nothing or at most adding a small noncritical
capacitor from OUT to Vss.
3.9.3 Output Drive
The OUT pin is active high and can sink or source up to 2 mA. When a large value of Cs (>20 nF) is used the OUT
current should be limited to <1 mA to prevent gain-shifting side effects, which happen when the load current creates
voltage drops on the die and bonding wires; these small shifts can materially influence the signal level to cause
detection instability.
OUT
VDD
SNSK
SNS
SYNC/MODE
VSS
2
6
4
1 3
5
VDD
HeartBeat" Pulse Ro
OUT SNSK
SNS
SYNC/MODE 6
4
1 3 Ro
Microcontroller
Port_M.x
Port_M.yAT42QT1010 [DATASHEET] 12
9541I–AT42–05/2013
4. Circuit Guidelines
4.1 More Information
Refer to Application Note QTAN0002, Secrets of a Successful QTouch Design and the Touch Sensors Design Guide
(both downloadable from the Atmel website), for more information on construction and design methods.
4.2 Sample Capacitor
Cs is the charge sensing sample capacitor. The required Cs value depends on the thickness of the panel and its
dielectric constant. Thicker panels require larger values of Cs. Typical values are 2 nF to 50 nF depending on the
sensitivity required; larger values of Cs demand higher stability and better dielectric to ensure reliable sensing.
The Cs capacitor should be a stable type, such as X7R ceramic or PPS film. For more consistent sensing from unit
to unit, 5% tolerance capacitors are recommended. X7R ceramic types can be obtained in 5% tolerance at little or no
extra cost. In applications where high sensitivity (long burst length) is required the use of PPS capacitors is
recommended.
For battery powered operation a higher value sample capacitor is recommended (typical value 8.2 nF).
4.3 UDFN/USON Package Restrictions
The central pad on the underside of the UDFN/USON chip is connected to ground. Do not run any tracks underneath
the body of the chip, only ground.
4.4 Power Supply and PCB Layout
See Section 5.2 on page 14 for the power supply range. At 3 V current drain averages less than 500 µA in Fast
mode.
If the power supply is shared with another electronic system, care should be taken to ensure that the supply is free of
digital spikes, sags, and surges which can adversely affect the QT1010. The QT1010 will track slow changes in Vdd,
but it can be badly affected by rapid voltage fluctuations. It is highly recommended that a separate voltage regulator
be used just for the QT1010 to isolate it from power supply shifts caused by other components.
If desired, the supply can be regulated using a Low Dropout (LDO) regulator, although such regulators often have
poor transient line and load stability. See Application Note QTAN0002, Secrets of a Successful QTouch™ Design for
further information.
Parts placement: The chip should be placed to minimize the SNSK trace length to reduce low frequency pickup,
and to reduce stray Cx which degrades gain. The Cs and Rs resistors (see Figure 1-1 on page 4) should be placed
as close to the body of the chip as possible so that the trace between Rs and the SNSK pin is very short, thereby
reducing the antenna-like ability of this trace to pick up high frequency signals and feed them directly into the chip. A
ground plane can be used under the chip and the associated discrete components, but the trace from the Rs resistor
and the electrode should not run near ground, to reduce loading.
For best EMC performance the circuit should be made entirely with SMT components.
Electrode trace routing: Keep the electrode trace (and the electrode itself) away from other signal, power, and
ground traces including over or next to ground planes. Adjacent switching signals can induce noise onto the sensing
signal; any adjacent trace or ground plane next to, or under, the electrode trace will cause an increase in Cx load and
desensitize the device.
Note: For proper operation a 100 nF (0.1 µF) ceramic bypass capacitor must be used directly between Vdd and
Vss, to prevent latch-up if there are substantial Vdd transients; for example, during an ESD event. The
bypass capacitor should be placed very close to the Vss and Vdd pins.AT42QT1010 [DATASHEET] 13 9541I–AT42–05/2013
4.5 Power On
On initial power up, the QT1010 requires approximately 100 ms to power on to allow power supplies to stabilize.
During this time the OUT pin state is not valid and should be ignored.AT42QT1010 [DATASHEET] 14
9541I–AT42–05/2013
5. Specifications
5.1 Absolute Maximum Specifications
5.2 Recommended Operating Conditions
5.3 AC Specifications
Operating temperature –40°C to +85°C
Storage temperature –55°C to +125°C
VDD 0 to +6.5 V
Max continuous pin current, any control or drive pin ±20 mA
Short circuit duration to Vss, any pin Infinite
Short circuit duration to Vdd, any pin Infinite
Voltage forced onto any pin –0.6V to (Vdd + 0.6) V
CAUTION: Stresses beyond those listed under Absolute Maximum Specifications may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum specification
conditions for extended periods may affect device reliability
VDD +1.8 to 5.5 V
Short-term supply ripple + noise ±20 mV
Long-term supply stability ±100 mV
Cs value 2 to 50 nF
Cx value 5 to 50 pF
Vdd = 3.0 V, Cs = 4.7 nF, Cx = 5 pF, Ta = recommended range, unless otherwise noted
Parameter Description Min Typ Max Units Notes
TRC Recalibration time – 200 – ms Cs, Cx dependent
TPC Charge duration – 3.05 – µs ±7.5% spread spectrum variation
TPT Transfer duration – 9.0 – µs ±7.5% spread spectrum variation
TG1 Time between end of burst and
start of the next (Fast mode) – 1.2 – ms
TG2 Time between end of burst and
start of the next (LP mode) – 80 – ms Increases with decreasing VDD
See Figure 5-1 on page 15AT42QT1010 [DATASHEET] 15 9541I–AT42–05/2013
Figure 5-1. TG2 – Time Between Bursts (LP Mode)
Figure 5-2. TBL – Burst Length
TBL Burst length – 2.45 – ms
VDD, Cs and Cx dependent. See
Section 4.2 for capacitor
selection.
TR Response time – – 100 ms
THB HeartBeat pulse width – 15 – µs
Vdd = 3.0 V, Cs = 4.7 nF, Cx = 5 pF, Ta = recommended range, unless otherwise noted
Parameter Description Min Typ Max Units NotesAT42QT1010 [DATASHEET] 16
9541I–AT42–05/2013
5.4 Signal Processing
5.5 DC Specifications
Vdd = 3.0V, Cs = 4.7 nF, Cx = 5 pF, Ta = recommended range, unless otherwise noted
Description Min Typ Max Units Notes
Threshold differential 10 counts
Hysteresis 2 counts
Consensus filter length 4 samples
Max on-duration 60 seconds (At 3 V in LP mode) Will vary
in SYNC mode and with Vdd
Vdd = 3.0V, Cs = 4.7 nF, Cx = 5 pF, Ta = recommended range, unless otherwise noted
Parameter Description Min Typ Max Units Notes
VDD Supply voltage 1.8 5.5 V
IDD Supply current, Fast mode –
203.0
246.0
378.5
542.5
729.0
– µA
1.8 V
2.0 V
3.0 V
4.0 V
5.0 V
IDDI Supply current, LP mode –
16.5
19.5
34.0
51.5
73.5
– µA
1.8 V
2.0 V
3.0 V
4.0 V
5.0 V
VDDS Supply turn-on slope 10 – – V/s Required for proper start-up
VIL Low input logic level – – 0.2 × Vdd
0.3 × Vdd V Vdd = 1.8 V – 2.4 V
Vdd = 2.4 V – 5.5 V
VHL High input logic level 0.7 × Vdd
0.6 × Vdd – – V Vdd = 1.8 V – 2.4 V
Vdd = 2.4 V – 5.5 V
VOL Low output voltage – – 0.5 V OUT, 4 mA sink
VOH High output voltage 2.3 – – V OUT, 1 mA source
IIL Input leakage current – <0.05 1 µA
CX Load capacitance range 2 – 50 pF
AR Acquisition resolution – 9 14 bitsAT42QT1010 [DATASHEET] 17 9541I–AT42–05/2013
5.6 Mechanical Dimensions
5.6.1 6-pin SOT23-6
9524D–AT42–05/2013
Features
Number of QTouch® Keys:
Up to four
Discrete Outputs:
Four discrete outputs indicating individual key touch
Technology:
Patented spread-spectrum charge-transfer (direct mode)
Electrode Design:
Simple self-capacitance style (refer to the Touch Sensors Design Guide)
Electrode Materials:
Etched copper, silver, carbon, Indium Tin Oxide (ITO)
Electrode Substrates:
PCB, FPCB, plastic films, glass
Panel Materials:
Plastic, glass, composites, painted surfaces (low particle density metallic
paints possible)
Panel Thickness:
Up to 10 mm glass, 5 mm plastic (electrode size dependent)
Key Sensitivity:
Fixed key threshold, sensitivity adjusted via sample capacitor value
Adjacent Key Suppression
Patented Adjacent Key Suppression® (AKS®) technology to enable accurate
key detection
Interface:
Pin-per-key outputs, plus debug mode to observe sensor signals
Moisture Tolerance:
Increased moisture tolerance based on hardware design and firmware tuning
Signal Processing:
Self-calibration, auto drift compensation, noise filtering
Applications:
Mobile, consumer, white goods, toys, kiosks, POS, and so on
Power:
1.8 V – 5.5 V
Package:
20-pin 3 x 3 mm VQFN RoHS compliant
Atmel AT42QT1040
Four-key QTouch® Touch Sensor IC
DATASHEETAT42QT1040 [DATASHEET] 2
9524D–AT42–05/2013
1. Pinout and Schematic
1.1 Pinout Configuration
NC
NC
VSS
VDD
NC
SNS2
SNSK1
SNS1
SNSK0
SNS0 OUT0
OUT1
1
2
3
4
5 11
12
13
14
15
20 19 18 17 16
6 7 8 9 10
QT1040 OUT3
OUT2
SNSK3
SNSK2
NC
NC
NC
SNS3AT42QT1040 [DATASHEET] 3 9524D–AT42–05/2013
1.2 Pin Descriptions
I/O CMOS input and output OD CMOS open drain output P Ground or power
Table 1-1. Pin Listing
Pin Name Type Function Notes If Unused...
1 SNS2 I/O Sense pin To Cs2 Leave open
2 SNSK1 I/O Sense pin and option detect To Cs1 and option resistor +
key
Connect to option
resistor*
3 SNS1 I/O Sense pin To Cs1 Leave open
4 SNSK0 I/O Sense pin and option detect To Cs0 and option resistor +
key
Connect to option
resistor*
5 SNS0 I/O Sense pin To Cs0 Leave open
6 N/C – – –
7 N/C – – –
8 Vss P Supply ground –
9 Vdd P Power –
10 N/C – – –
11 OUT0 OD Out 0 Alternative function: Debug
CLK Leave open
12 OUT1 OD Out 1 Alternative function: Debug
DATA Leave open
13 OUT3 OD Out 3 Leave open
14 OUT2 OD Out 2 Leave open
15 SNSK3 I/O Sense pin To Cs3 + key Leave open
16 SNS3 I/O Sense pin To Cs3 Leave open
17 N/C – – –
18 N/C – – –
19 N/C – – –
20 SNSK2 I/O Sense pin To Cs2 + key Leave open
* Option resistor should always be fitted even if channel is unused and Cs capacitor is not fixed.AT42QT1040 [DATASHEET] 4
9524D–AT42–05/2013
1.3 Schematic
Figure 1-1. Typical Circuit
Suggested regulator manufacturers:
Torex (XC6215 series)
Seiko (S817 series)
BCDSemi (AP2121 series)
For component values in Figure 1-1 check the following sections:
Section 3.1 on page 7: Cs capacitors (Cs0 – Cs3)
Section 3.5 on page 7: Voltage levels
Section 3.3 on page 7: LED traces
SLOW
FAST
OFF
LED3
LED2
LED1
LED0
VDD
VDD
2
1
3
J2
VDD
2
1
3
J1
ON
2 2
5 5
4 4
3 3
1 1
J3
VDD 9 VSS 8
N/C 19
N/C 10
OUT2 14
SNSK3 15
SNSK2 20
SNSK1 2
SNSK0 4
N/C 18
N/C 7
N/C 17
OUT1 12
OUT0 11
SNS3 16
SNS1 3
N/C 6
OUT3 13 SNS0 5
SNS2 1
SPEED SELECT
AKS SELECT
NOTES:
1) The central pad on the underside of the VQFN chip is a Vss pin and should be connected
to ground. Do not put any other tracks underneath the body of the chip.
2) It is important to place all Cs and Rs components physically near to the chip.
Add a 100 nF capacitor close to pin 9.
QT1040
Creg Creg
VREG
Follow regulator manufacturer's
recommended values for input
and output bypass capacitors (Creg).
Key0
Key1
Key2
Key3
VUNREG
GND
Cs0
Cs1
Cs2
Cs3
RL0
RL1
RL2
RL3
RAKS
RFS
Rs0
Rs1
Rs2
Rs3
Example use of output pinsAT42QT1040 [DATASHEET] 5 9524D–AT42–05/2013
2. Overview of the AT42QT1040
2.1 Introduction
The AT42QT1040 (QT1040) is a digital burst mode charge-transfer (QT™) capacitive sensor driver designed for
touch-key applications. The device can sense from one to four keys; one to three keys can be disabled by not
installing their respective sense capacitors. Any of the four channels can be disabled in this way.
The device includes all signal processing functions necessary to provide stable sensing under a wide variety of
changing conditions, and the outputs are fully de-bounced. Only a few external parts are required for operation.
The QT1040 modulates its bursts in a spread-spectrum fashion in order to heavily suppress the effects of external
noise, and to suppress RF emissions.
2.2 Signal Processing
2.2.1 Detect Threshold
The internal signal threshold level is fixed at 10 counts of change with respect to the internal reference level. This in
turn adjusts itself slowly in accordance with the drift compensation mechanism. See Section 3.1 on page 7 for details
on how to adjust the sensitivity of each key.
When going out of detect there is a hysteresis element to the detection. The signal threshold must drop below 8
counts of change with respect to the internal reference level to register as un-touched.
2.2.2 Detection Integrator
The device features a detection integration mechanism, which acts to confirm a detection in a robust fashion. A perkey
counter is incremented each time the key has exceeded its threshold, and a key is only finally declared to be
touched when this counter reaches a fixed limit of 5. In other words, the device has to exceed its threshold, and stay
there for 5 acquisitions in succession without going below the threshold level, before the key is declared to be
touched.
2.2.3 Burst Length Limitations
Burst length is the number of times the charge transfer process is performed on a given channel; that is, the number
of pulses it takes to measure the key capacitance.
The maximum burst length is 2048 pulses. The recommended design is to use a capacitor that gives a signal of
<1000 pulses. Longer bursts take more time and use more power.
Note that the keys are independent of each other. It is therefore possible, for example, to have a signal of 100 on one
key and a signal of 1000 on another.
Refer to Application Note QTAN0002, Secrets of a Successful QTouch Design (downloadable from the Atmel
website), for more information on using a scope to measure the pulses and hence determine the burst length. Refer
also to the Touch Sensors Design Guide.
2.2.4 Adjacent Key Suppression Technology
The device includes the Atmel-patented Adjacent Key Suppression (AKS) technology, to allow the use of tightly
spaced keys on a keypad with no loss of selectability by the user.
There is one global AKS group, implemented so that only one key in the group may be reported as being touched at
any one time.
The use of AKS is selected by connecting a 1 M resistor between Vdd and the SNSK0 pin (see Section 4.1 on
page 9 for more information). When AKS is disabled, any combinations of keys can enter detect.AT42QT1040 [DATASHEET] 6
9524D–AT42–05/2013
2.2.5 Auto Drift Compensation
Signal drift can occur because of changes in Cx and Cs over time. It is crucial that drift be compensated for,
otherwise false detections, non-detections, and sensitivity shifts will follow.
Drift compensation is performed by making the reference level track the raw signal at a slow rate, but only while
there is no detection in effect. The rate of adjustment must be performed slowly otherwise legitimate detections could
be ignored.
Once an object is sensed and a key is in detect, the drift compensation mechanism ceases, since the signal is
legitimately high and should not therefore cause the reference level to change.
The QT1040 drift compensation is asymmetric, that is, the reference level drift-compensates in one direction faster
than it does in the other. Specifically, it compensates faster for decreasing (towards touch) signals than for
increasing (away from touch) signals. The reason for this difference in compensation rates is that increasing signals
should not be compensated for quickly, since a nearby finger could be compensated for partially or entirely before
even approaching the sense electrode. However, decreasing signals need to be compensated for more quickly. For
example, an obstruction over the sense pad (for which the sensor has already made full allowance) could suddenly
be removed, leaving the sensor with an artificially elevated reference level and thus become insensitive to touch. In
this latter case, the sensor will compensate for the object's removal very quickly, usually in only a few seconds.
Negative drift (that is, towards touch) occurs at a rate of ~3 seconds, while positive drift occurs at a rate of
~1 second.
Drifting only occurs when no keys are in detect state.
2.2.6 Response Time
The QT1040 response time is highly dependent on run mode and burst length, which in turn is dependent on Cs and
Cx. With increasing Cs, response time slows, while increasing levels of Cx reduce response time. The response time
will also be slower in slow mode due to a longer time between burst measurements. This mode offers an increased
detection latency in favor of reduced average current consumption.
2.2.7 Spread Spectrum
The QT1040 modulates its internal oscillator by ±7.5% during the measurement burst. This spreads the generated
noise over a wider band reducing emission levels. This also reduces susceptibility since there is no longer a single
fundamental burst frequency.
2.2.8 Max On-duration
If an object or material obstructs the sense pad, the signal may rise enough to create a detection, preventing further
operation. To prevent this, the sensor includes a timer known as the Max On-duration feature which monitors
detections. If a detection exceeds the timer setting, the sensor performs an automatic recalibration. Max On-duration
is set to ~30s.AT42QT1040 [DATASHEET] 7 9524D–AT42–05/2013
3. Wiring and Parts
3.1 Cs Sample Capacitors
Cs0 – Cs3 are the charge sensing sample capacitors; normally they are identical in nominal value. The optimal Cs
values depend on the corresponding keys electrode design, the thickness of the panel and its dielectric constant.
Thicker panels require larger values of Cs. Values can be in the range 2.2 nF (for faster operation) to 22 nF (for best
sensitivity); typical values are 4.7 nF to 10 nF.
The value of Cs should be chosen such that a light touch on a key mounted in a production unit or a prototype panel
causes a reliable detection. The chosen Cs value should never be so large that the key signals exceed ~1000, as
reported by the chip in the debug data.
The Cs capacitors must be X7R or PPS film type, for stability. For consistent sensitivity, they should have a 10%
tolerance. Twenty percent tolerance may cause small differences in sensitivity from key to key and unit to unit. If a
key is not used, the Cs capacitor may be omitted.
3.2 Rs Resistors
The series resistors Rs0 – Rs3 are in line with the electrode connections (close to the QT1040 chip) and are used to
limit electrostatic discharge (ESD) currents and to suppress radio frequency (RF) interference. A typical value is
4.7 k, but up to 20 k can be used if it is found to be of benefit.
Although these resistors may be omitted, the device may become susceptible to external noise or radio frequency
interference (RFI). For details on how to select these resistors refer to Application Note QTAN0002, Secrets of a
Successful QTouch Design, and the Touch Sensors Design Guide, both downloadable from the Touch Technology
area of the Atmel website, www.atmel.com.
3.3 LED Traces and Other Switching Signals
For advice on LEDs and nearby traces, refer to Application Note QTAN0002, Secrets of a Successful QTouch
Design, and the Touch Sensors Design Guide, both downloadable from the Touch Technology area of Atmel’s
website, www.atmel.com.
3.4 PCB Cleanliness
Modern no-clean flux is generally compatible with capacitive sensing circuits.
3.5 Power Supply
See Section 5.2 on page 15 for the power supply range. If the power supply fluctuates slowly with temperature, the
device tracks and compensates for these changes automatically with only minor changes in sensitivity. If the supply
voltage drifts or shifts quickly, the drift compensation mechanism is not able to keep up, causing sensitivity
anomalies or false detections.
The usual power supply considerations with QT parts apply to the device. The power should be clean and come from
a separate regulator if possible. However, this device is designed to minimize the effects of unstable power, and
except in extreme conditions should not require a separate Low Dropout (LDO) regulator.
CAUTION: If a PCB is reworked to correct soldering faults relating to the device, or
to any associated traces or components, be sure that you fully understand the
nature of the flux used during the rework process. Leakage currents from
hygroscopic ionic residues can stop capacitive sensors from functioning. If you
have any doubts, a thorough cleaning after rework may be the only safe option.AT42QT1040 [DATASHEET] 8
9524D–AT42–05/2013
See under Figure 1.3 on page 4 for suggested regulator manufacturers.
It is assumed that a larger bypass capacitor (for example, 1 µF) is somewhere else in the power circuit; for example,
near the regulator.
To assist with transient regulator stability problems, the QT1040 waits 500 µs any time it wakes up from a sleep state
(that is, in Sleep mode) before acquiring, to allow Vdd to fully stabilize.
3.6 VQFN Package Restrictions
The central pad on the underside of the VQFN chip should be connected to ground. Do not run any tracks
underneath the body of the chip, only ground. Figure 3-1 shows an example of good/bad tracking.
Figure 3-1. Examples of Good and Bad Tracking
Caution: A regulator IC shared with other logic can result in erratic operation and is
not advised.
A single ceramic 0.1 µF bypass capacitor, with short traces, should be placed very
close to the power pins of the IC. Failure to do so can result in device oscillation, high
current consumption, erratic operation, and so on.
Example of GOOD tracking Example of BAD trackingAT42QT1040 [DATASHEET] 9 9524D–AT42–05/2013
4. Detailed Operations
4.1 Adjacent Key Suppression
The use of AKS is selected by the connection of a 1 M resistor (RAKS resistor) between the SNSK0 pin and either
Vdd (AKS mode on) or Vss (AKS mode off).
Note: Changing the RAKS option will affect the sensitivity of the particular key. Always check that the sensitivity is
suitable after a change. Retune Cs0 if necessary.
4.2 Discrete Outputs
There are four discrete outputs (channels 0 to 3), located on pins OUT0 to OUT3. An output pin goes active when
the corresponding key is touched. The outputs are open-drain type and are active-low.
On the OUT2 pin there is a ~500 ns low pulse occurring approximately 20 ms after a power-up/reset (see Figure 4-1
for an example oscilloscope trace of this pulse at two zoom levels). This pulse may need to be considered from the
system design perspective.
The discrete outputs have sufficient current sinking capability to directly drive LEDs. Try to limit the sink current to
less than 5 mA per output and be cautious if connecting LEDs to a power supply other than Vdd; if the LED supply is
higher than Vdd it may cause erratic behavior of the QT1040 and back-power the QT1040 through its I/O pins.
Table 4-1. RAKS Resistor
RAKS Connected To... Mode
Vdd AKS on
Vss AKS off
The RAKS resistor should always be connected to either Vdd or Vss and should not be
changed during operation of the device.AT42QT1040 [DATASHEET] 10
9524D–AT42–05/2013
Figure 4-1. ~500 ns Pulse On OUT2 Pin
4.3 Speed Selection
Speed selection is determined by a 1 M resistor (RFS resistor) connected between SNSK1 and either Vdd (Fast
Mode) or Vss (Slow Mode).
In Fast Mode, the device sleeps for 16 ms between burst acquisitions. In Slow Mode, the device sleeps for 64 ms
between acquisitions. Hence, Slow Mode conserves more power but results in slightly less responsiveness.
Note: The RFS resistor should always be connected to either Vdd or Vss and not changed during operation of the
device. Changing the RFS option will affect the sensitivity of the particular key. Always check that the
sensitivity is suitable after a change. Retune Cs1 if necessary.
4.4 Moisture Tolerance
The presence of water (condensation, sweat, spilt water, and so on) on a sensor can alter the signal values
measured and thereby affect the performance of any capacitive device. The moisture tolerance of QTouch devices
can be improved by designing the hardware and fine-tuning the firmware following the recommendations in the
application note Atmel AVR3002: Moisture Tolerant QTouch Design (www.atmel.com/Images/doc42017.pdf).
Pulse on OUT2
SNS0K
OUT2
SNS0K
OUT2
Power-on/ ~20 ms
Reset
Table 4-2. RFS Resistor
RFS Connected To Mode
Vdd Fast mode
Vss Slow modeAT42QT1040 [DATASHEET] 11 9524D–AT42–05/2013
4.5 Calibration
Calibration is the process by which the sensor chip assesses the background capacitance on each channel. During
calibration, a number of samples are taken in quick succession to get a baseline for the channel reference value.
Calibration takes place ~50 ms after power is applied to the device. Calibration also occurs if the Max On-duration is
exceeded or a positive re-calibration occurs.
4.6 Debug Mode
An added feature to this device is a debug option whereby internal parameters from the IC can be clocked out and
monitored externally.
Debug mode is entered by shorting the CS3 capacitor (SNSK3 and SNS3 pins) on power-up and removing the short
within 5 seconds.
Note: If the short is not removed within 5 seconds, debug mode is still entered, but with Channel 3 unusable until
a re-calibration occurs. Note that as Channel 3 will show as being in detect, a recalibration will occur after
Max On-duration (~30 seconds).
Debug CLK pin (OUT0) and Debug Data pin (OUT1) float while debug data is not being output and are driven
outputs once debug output starts (that is, not open drain).
The serial data is clocked out at a rate of ~200 kHz, MSB first, as in Table 4-3.
Table 4-3. Serial Data Output
Byte Purpose Notes
0 Frame Number Framing index number 0-255
1 Chip Version Upper nibble: major revision
Lower nibble: minor revision
2 Reference 0 Low Byte
Unsigned 16-bit integer
3 Reference 0 High Byte
4 Reference 1 Low Byte
Unsigned 16-bit integer
5 Reference 1 High Byte
6 Reference 2 Low Byte
Unsigned 16-bit integer
7 Reference 2 High Byte
8 Reference 3 Low Byte
Unsigned 16-bit integer
9 Reference 3 High Byte
10 Signal 0 Low Byte
Unsigned 16-bit integer
11 Signal 0 High Byte
12 Signal 1 Low Byte
Unsigned 16-bit integer
13 Signal 1 High Byte
14 Signal 2 Low Byte
Unsigned 16-bit integer
15 Signal 2 High Byte
16 Signal 3 Low Byte
Unsigned 16-bit integer
17 Signal 3 High ByteAT42QT1040 [DATASHEET] 12
9524D–AT42–05/2013
Bit 7: This bit is set during calibration
Bits 4 – 6: Contains the number of keys active
Bits 0 – 3: Show the touch status of the corresponding keys
Figure 4-2 to Figure 4-5 show the usefulness of the debug data out feature. Channels can be monitored and tweaked
to the specific application with great accuracy.
18 Delta 0 Low Byte
Signed 16-bit integer
19 Delta 0 High Byte
20 Delta 1 Low Byte
Signed 16-bit integer
21 Delta 1 High Byte
22 Delta 2 Low Byte
Signed 16-bit integer
23 Delta 2 High Byte
24 Delta 3 Low Byte
Signed 16-bit integer
25 Delta 3 High Byte
26 Flags Various operational flags
27 Flags2 Unsigned bytes
28 Status Byte Unsigned byte. See Table 4-4
29 Frame Number Repeat of framing index number in
byte 0
Table 4-4. Status Byte (Byte 28)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CAL Number of Keys (2 – 4) Key 3 Key 2 Key 1 Key 0
Table 4-3. Serial Data Output (Continued)
Byte Purpose NotesAT42QT1040 [DATASHEET] 13 9524D–AT42–05/2013
Figure 4-2. Byte Clocked Out (~5 µs Period)
Figure 4-3. Byte Following Byte (~ 30 µs Period)
Figure 4-4. Full Debug Send (30 Bytes)AT42QT1040 [DATASHEET] 14
9524D–AT42–05/2013
Figure 4-5. Debug Lines Floating Between Debug Data Sends (30 Bytes, ~2 ms to Send)AT42QT1040 [DATASHEET] 15 9524D–AT42–05/2013
5. Specifications
5.1 Absolute Maximum Specifications
5.2 Recommended Operating Conditions
5.3 DC Specifications
Vdd –0.5 to +6.0 V
Max continuous pin current, any control or drive pin ±10 mA
Voltage forced onto any pin –0.5 V to (Vdd + 0.5) V
Operating temperature –40°C to +85°C
Storage temperature –55°C to +125°C
Vdd 1.8 V to 5.5 V
Supply ripple + noise ±20 mV maximum
Cx capacitance per key 2 to 20 pF
Vdd = 5.0 V, Cs = 4.7 nF, Ta = recommended range, unless otherwise noted
Parameter Description Min Typ Max Units Notes
Vil Low input logic level –0.5 – 0.3 V
Vih High input logic level 0.6 × Vdd Vdd Vdd + 0.5 V
Vol Low output voltage 0 – 0.7 V 10 mA sink current
Voh High output voltage 0.8 × Vdd – Vdd V 10 mA source current
Iil Input leakage current – <0.05 1 µA
Rrst Internal RST pull-up resistor 20 – 50 k
CAUTION: Stresses beyond those listed under Absolute Maximum Specifications may cause permanent damage
the device. This is a stress rating only and functional operation of the device at these or other conditions beyo
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximu
specification conditions for extended periods may affect device reliabilityAT42QT1040 [DATASHEET] 16
9524D–AT42–05/2013
5.4 Timing Specifications
5.5 Power Consumption
Parameter Description Min Typ Max Units Notes
TBS Burst duration – 3.5 – ms Cx = 5 pF, Cs = 18 nF
Fc Burst center frequency – 119 – kHz
Fm Burst modulation, percentage –7.5 – +7.5 %
TPW Burst pulse width – 2 – µs
Vdd (V) AKS Mode (RAKS) Speed (RFS) Power Consumption (µA)
1.8
Off Slow 31
Off Fast 104
On Slow 36
On Fast 114
3.3
Off Slow 100
Off Fast 340
On Slow 117
On Fast 380
5.0
Off Slow 215
Off Fast 710
On Slow 245
On Fast 800AT42QT1040 [DATASHEET] 17 9524D–AT42–05/2013
5.6 Mechanical Dimensions
Features
• High performance, low power AVR® 8-bit Microcontroller
• Advanced RISC architecture
– 135 powerful instructions – most single clock cycle execution
– 32 × 8 general purpose working registers
– Fully static operation
– Up to 16MIPS throughput at 16MHz
– On-chip 2-cycle multiplier
• Non-volatile program and data memories
– 64/128Kbytes of in-system self-programmable flash
• Endurance: 100,000 write/erase cycles
– Optional Boot Code section with independent lock bits
• USB boot loader programmed by default in the factory
• In-system programming by on-chip boot program hardware activated after
reset
• True read-while-write operation
• All supplied parts are pre-programed with a default USB bootloader
– 2K/4K (64K/128K flash version) bytes EEPROM
• Endurance: 100,000 write/erase cycles
– 4K/8K (64K/128K flash version) bytes internal SRAM
– Up to 64Kbytes optional external memory space
– Programming lock for software security
• JTAG (IEEE std. 1149.1 compliant) interface
– Boundary-scan capabilities according to the JTAG standard
– Extensive on-chip debug support
– Programming of flash, EEPROM, fuses, and lock bits through the JTAG interface
• USB 2.0 full-speed/low-speed device and on-the-go module
– Complies fully with:
– Universal serial bus specification REV 2.0
– On-the-go supplement to the USB 2.0 specification rev 1.0
– Supports data transfer rates up to 12Mbit/s and 1.5Mbit/s
• USB full-speed/low speed device module with interrupt on transfer completion
– Endpoint 0 for control transfers: up to 64-bytes
– Six programmable endpoints with in or out directions and with bulk, interrupt or
isochronous transfers
– Configurable endpoints size up to 256bytes in double bank mode
– Fully independent 832bytes USB DPRAM for endpoint memory allocation
– Suspend/resume interrupts
– Power-on reset and USB bus reset
– 48MHz PLL for full-speed bus operation
– USB bus disconnection on microcontroller request
• USB OTG reduced host:
– Supports host negotiation protocol (HNP) and session request protocol (SRP) for
OTG dual-role devices
– Provide status and control signals for software implementation of HNP and SRP
– Provides programmable times required for HNP and SRP
• Peripheral features
– Two 8-bit timer/counters with separate prescaler and compare mode
– Two16-bit timer/counter with separate prescaler, compare- and capture mode
8-bit Atmel
Microcontroller
with
64/128Kbytes
of ISP Flash
and USB
Controller
AT90USB646
AT90USB647
AT90USB1286
AT90USB1287
7593L–AVR–09/122
7593L–AVR–09/12
AT90USB64/128
– Real time counter with separate oscillator
– Four 8-bit PWM channels
– Six PWM channels with programmable resolution from 2 to 16 bits
– Output compare modulator
– 8-channels, 10-bit ADC
– Programmable serial USART
– Master/slave SPI serial interface
– Byte oriented 2-wire serial interface
– Programmable watchdog timer with separate on-chip oscillator
– On-chip analog comparator
– Interrupt and wake-up on pin change
• Special microcontroller features
– Power-on reset and programmable brown-out detection
– Internal calibrated oscillator
– External and internal interrupt sources
– Six sleep modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby
• I/O and packages
– 48 programmable I/O lines
– 64-lead TQFP and 64-lead QFN
• Operating voltages
– 2.7 - 5.5V
• Operating temperature
– Industrial (-40°C to +85°C)
• Maximum frequency
– 8MHz at 2.7V - industrial range
– 16MHz at 4.5V - industrial range3
7593L–AVR–09/12
AT90USB64/128
1. Pin configurations
Figure 1-1. Pinout Atmel AT90USB64/128-TQFP.
AT90USB90128/64
TQFP64
(INT.7/AIN.1/UVcon) PE7
UVcc
D-
D+
UGnd
UCap
VBus
(IUID) PE3
(SS/PCINT0) PB0
(INT.6/AIN.0) PE6
(PCINT1/SCLK) PB1
(PDI/PCINT2/MOSI) PB2
(PDO/PCINT3/MISO) PB3
(PCINT4/OC.2A) PB4
(PCINT5/OC.1A) PB5
(PCINT6/OC.1B) PB6
(PCINT7/OC.0A/OC.1C) PB7
(INT4/TOSC1) PE4
(INT.5/TOSC2) PE5
RESET
VCC
GND
XTAL2
XTAL1
(OC0B/SCL/INT0) PD0
(OC2B/SDA/INT1) PD1
(RXD1/INT2) PD2
(TXD1/INT3) PD3
(ICP1) PD4
(XCK1) PD5
PA3 (AD3)
PA4 (AD4)
PA5 (AD5)
PA6 (AD6)
PA7 (AD7)
PE2 (ALE/HWB)
PC7 (A15/IC.3/CLKO)
PC6 (A14/OC.3A)
PC5 (A13/OC.3B)
PC4 (A12/OC.3C)
PC3 (A11/T.3)
PC2 (A10)
PC1 (A9)
PC0 (A8)
PE1 (RD)
PE0 (WR)
AVCC
GND
AREF
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
PF7 (ADC7/TDI)
GND
VCC
PA0 (AD0)
PA1 (AD1)
PA2 (AD2)
(T1) PD6
(T0) PD7
INDEX CORNER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
324
7593L–AVR–09/12
AT90USB64/128
Figure 1-2. Pinout Atmel AT90USB64/128-QFN.
Note: The large center pad underneath the MLF packages is made of metal and internally connected to
GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center
pad is left unconnected, the package might loosen from the board.
2
3
1
4
5
6
7
8
9
10
11
12
13
14
16 33
15
47
46
48
45
44
43
42
41
40
39
38
37
36
35
34
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AT90USB128/64
(64-lead QFN top view)
INDEX CORNER
AVCC
G
N
D
AREF
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
PF7 (ADC7/TDI)
G
N
D
VCC
PA0 (AD0)
PA1 (AD1)
PA2 (AD2)
(INT.7/AIN.1/UVcon) PE7
UVcc
D-
D+
UGnd
UCap
VBus
(IUID) PE3
(SS/PCINT0) PB0
(INT.6/AIN.0) PE6
(PCINT1/SCLK) PB1
(PDI/PCINT2/MOSI) PB2
(PDO/PCINT3/MISO) PB3
(PCINT4/OC.2A) PB4
(PCINT5/OC.1A) PB5
(PCINT6/OC.1B) PB6
(PCI
NT7/OC.0A/OC.1C) PB7
(INT4/TOSC1) PE4
(INT.5/TOSC2) PE5
VCC
G
N
D
XTAL2
XTAL1
(OC0B/SCL/I
NT0) PD0
(OC2B/SDA/I
NT1) PD1
(RXD1/I
NT2) PD2
(TXD1/I
NT3) PD3
(ICP1) PD4
(XCK1) PD5
(T1) PD6
(T0) PD7
RESET
PA3 (AD3)
PA4 (AD4)
PA5 (AD5)
PA6 (AD6)
PA7 (AD7)
PE2 (ALE/HWB)
PC7 (A15/IC.3/CLKO)
PC6 (A14/OC.3A)
PC5 (A13/OC.3B)
PC4 (A12/OC.3C)
PC3 (A11/T.3)
PC2 (A10)
PC1 (A9)
PC0 (A8)
PE1 (RD)
PE0 (WR)5
7593L–AVR–09/12
AT90USB64/128
2. Overview
The Atmel® AVR® AT90USB64/128 is a low-power CMOS 8-bit microcontroller based on the
Atmel® AVR® enhanced RISC architecture. By executing powerful instructions in a single clock
cycle, the AT90USB64/128 achieves throughputs approaching 1MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.6
7593L–AVR–09/12
AT90USB64/128
2.1 Block diagram
Figure 2-1. Block diagram.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
PROGRAM
COUNTER
ST ACK
POINTER
PROGRAM
FLASH
MCU CONTROL
REGISTER SRAM
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
TIMER/
COUNTERS
INSTRUCTION
DECODER
DATA DIR.
REG. PORTB
DATA DIR.
REG. PORTE
DATA DIR.
REG. PORT A
DATA DIR.
REG. PORTD
DATA REGISTER
PORTB
DATA REGISTER
PORTE
DATA REGISTER
PORT A
DATA REGISTER
PORTD
INTERRUPT
UNIT
EEPROM
USART1 SPI
ST ATUS
REGISTER
Z
Y
X
ALU
POR TE DRIVERS POR TB DRIVERS
POR TF DRIVERS POR TA DRIVERS
POR TD DRIVERS
POR TC DRIVERS
PE7 - PE0 PB7 - PB0
PF7 - PF0 PA7 - P A0
RESET
VCC
AGND
GND
AREF
XT AL1
XT AL2
CONTROL
LINES
+
-
ANALOG
COMP ARATOR
PC7 - PC0
INTERNAL
OSCILLA TOR
WATCHDOG
TIMER
8-BIT DA TA BUS
AVCC
USB
TIMING AND
CONTROL
OSCILLA TOR
CALIB. OSC
DATA DIR.
REG. PORT C
DATA REGISTER
PORT C
ON-CHIP DEBUG
JTAG TAP
PROGRAMMING
LOGIC
BOUNDARYSCAN
DATA DIR.
REG. PORT F
DATA REGISTER
PORT F
ADC
POR - BOD
RESET
PD7 - PD0
TWO-WIRE SERIAL
INTERFACE
PLL7
7593L–AVR–09/12
AT90USB64/128
architecture is more code efficient while achieving throughputs up to ten times faster than conventional
CISC microcontrollers.
The Atmel AT90USB64/128 provides the following features: 64/128Kbytes of In-System Programmable
Flash with Read-While-Write capabilities, 2K/4Kbytes EEPROM, 4K/8K bytes
SRAM, 48 general purpose I/O lines, 32 general purpose working registers, Real Time Counter
(RTC), four flexible Timer/Counters with compare modes and PWM, one USART, a byte oriented
2-wire Serial Interface, a 8-channels, 10-bit ADC with optional differential input stage with
programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port,
IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system
and programming and six software selectable power saving modes. The Idle mode stops
the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue
functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling
all other chip functions until the next interrupt or Hardware Reset. In Power-save mode,
the asynchronous timer continues to run, allowing the user to maintain a timer base while the
rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules
except Asynchronous Timer and ADC, to minimize switching noise during ADC
conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the
device is sleeping. This allows very fast start-up combined with low power consumption. In
Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.
The device is manufactured using the Atmel high-density nonvolatile memory technology. The
On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI
serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program
running on the AVR core. The boot program can use any interface to download the
application program in the application Flash memory. Software in the Boot Flash section will
continue to run while the Application Flash section is updated, providing true Read-While-Write
operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a
monolithic chip, the AT90USB64/128 is a powerful microcontroller that provides a highly flexible
and cost effective solution to many embedded control applications.
The AT90USB64/128 AVR is supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators,
and evaluation kits.8
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AT90USB64/128
2.2 Pin descriptions
2.2.1 VCC
Digital supply voltage.
2.2.2 GND
Ground.
2.2.3 AVCC
Analog supply voltage.
2.2.4 Port A (PA7..PA0)
Port A is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port A also serves the functions of various special features of the Atmel AT90USB64/128 as
listed on page 78.
2.2.5 Port B (PB7..PB0)
Port B is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B has better driving capabilities than the other ports.
Port B also serves the functions of various special features of the AT90USB64/128 as listed on
page 79.
2.2.6 Port C (PC7..PC0)
Port C is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of special features of the AT90USB64/128 as listed on page 82.
2.2.7 Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the AT90USB64/128 as listed on
page 83. 9
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AT90USB64/128
2.2.8 Port E (PE7..PE0)
Port E is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port E also serves the functions of various special features of the AT90USB64/128 as listed on
page 86.
2.2.9 Port F (PF7..PF0)
Port F serves as analog inputs to the A/D Converter.
Port F also serves as an 8-bit bidirectional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical
drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will
be activated even if a reset occurs.
Port F also serves the functions of the JTAG interface.
2.2.10 DUSB
Full speed / Low Speed Negative Data Upstream Port. Should be connected to the USB Dconnector
pin with a serial 22Ω resistor.
2.2.11 D+
USB Full speed / Low Speed Positive Data Upstream Port. Should be connected to the USB D+
connector pin with a serial 22Ω resistor.
2.2.12 UGND
USB Pads Ground.
2.2.13 UVCC
USB Pads Internal Regulator Input supply voltage.
2.2.14 UCAP
USB Pads Internal Regulator Output supply voltage. Should be connected to an external capacitor
(1µF).
2.2.15 VBUS
USB VBUS monitor and OTG negociations.
2.2.16 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 9-1 on page
58. Shorter pulses are not guaranteed to generate a reset.
2.2.17 XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.10
7593L–AVR–09/12
AT90USB64/128
2.2.18 XTAL2
Output from the inverting oscillator amplifier.
2.2.19 AVCC
AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected
to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC
through a low-pass filter.
2.2.20 AREF
This is the analog reference pin for the A/D Converter.
3. Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
4. About code examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation
for more details.
These code examples assume that the part specific header file is included before compilation.
For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI"
instructions must be replaced with instructions that allow access to extended I/O. Typically
"LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".11
7593L–AVR–09/12
AT90USB64/128
5. AVR CPU core
5.1 Introduction
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
5.2 Architectural overview
Figure 5-1. Block diagram of the AVR architecture.
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruction
is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Re-programmable Flash memory.
Flash
program
memory
Instruction
register
Instruction
decoder
Program
counter
Control lines
32 x 8
general
purpose
registrers
ALU
Status
and control
I/O lines
EEPROM
Data bus 8-bit
Data
SRAM
Direct addressing
Indirect addressing
Interrupt
unit
SPI
unit
Watchdog
timer
Analog
comparator
I/O Module 2
I/O Module1
I/O Module n12
7593L–AVR–09/12
AT90USB64/128
The fast-access Register File contains 32 × 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical
ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointers
can also be used as an address pointer for look up tables in Flash program memory. These
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single register operations can also be executed in the ALU. After an arithmetic operation,
the Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most AVR instructions have a single 16-bit word format.
Every program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the
Application Program section. Both sections have dedicated Lock bits for write and read/write
protection. The SPM instruction that writes into the Application Flash memory section must
reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack
Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position.
The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers,
SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data
Space locations following those of the Register File, 0x20 - 0x5F. In addition, the Atmel
AT90USB64/128 has Extended I/O space from 0x60 - 0xFF in SRAM where only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
5.3 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general purpose
registers or between a register and an immediate are executed. The ALU operations are divided
into three main categories – arithmetic, logical, and bit-functions. Some implementations of the
architecture also provide a powerful multiplier supporting both signed/unsigned multiplication
and fractional format. See the “Instruction set summary” on page 423 for a detailed description.13
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AT90USB64/128
5.4 Status register
The status register contains information about the result of the most recently executed arithmetic
instruction. This information can be used for altering program flow in order to perform conditional
operations. Note that the status register is updated after all ALU operations, as specified in the
Instruction Set Reference. This will in many cases remove the need for using the dedicated compare
instructions, resulting in faster and more compact code.
The status register is not automatically stored when entering an interrupt routine and restored
when returning from an interrupt. This must be handled by software.
The AVR status register – SREG – is defined as:
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt
enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination
for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful
in BCD arithmetic. See the “Instruction set summary” on page 423 for detailed information.
• Bit 4 – S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement
Overflow Flag V. See the “Instruction set summary” on page 423 for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction set summary” on page 423 for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction set summary” on page 423 for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction
set summary” on page 423 for detailed information.
Bit 7 6 5 4 3 2 1 0
I T H S V N Z C SREG
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 014
7593L–AVR–09/12
AT90USB64/128
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction set
summary” on page 423 for detailed information.
5.5 General purpose register file
The register file is optimized for the AVR Enhanced RISC instruction set. In order to achieve the
required performance and flexibility, the following input/output schemes are supported by the
register file:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 5-2 shows the structure of the 32 general purpose working registers in the CPU.
Figure 5-2. AVR CPU general purpose working registers.
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 5-2, each register is also assigned a data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically implemented
as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file.
5.5.1 The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers
are 16-bit address pointers for indirect addressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in Figure 5-3.
7 0 Addr.
R0 0x00
R1 0x01
R2 0x02
…
R13 0x0D
General R14 0x0E
purpose R15 0x0F
working R16 0x10
registers R17 0x11
…
R26 0x1A X-register Low byte
R27 0x1B X-register High byte
R28 0x1C Y-register Low byte
R29 0x1D Y-register High byte
R30 0x1E Z-register Low byte
R31 0x1F Z-register High byte15
7593L–AVR–09/12
AT90USB64/128
Figure 5-3. The X-, Y-, and Z-registers.
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
5.6 Stack pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations
to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x0100. The initial value of the stack pointer is the last address of the internal
SRAM. The Stack Pointer is decremented by one when data is pushed onto the Stack with the
PUSH instruction, and it is decremented by three when the return address is pushed onto the
Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is incremented by three when data is
popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementations
of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
15 XH XL 0
X-register 7 07 0
R27 (0x1B) R26 (0x1A)
15 YH YL 0
Y-register 7 07 0
R29 (0x1D) R28 (0x1C)
15 ZH ZL 0
Z-register 70 7 0
R31 (0x1F) R30 (0x1E)
Bit 15 14 13 12 11 10 9 8
SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 1 0 0 0 0 0
1111111116
7593L–AVR–09/12
AT90USB64/128
5.6.1 RAMPZ - Extended Z-pointer register for ELPM/SPM
For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown
in Figure 5-4. Note that LPM is not affected by the RAMPZ setting.
Figure 5-4. The Z-pointer used by ELPM and SPM.
The actual number of bits is implementation dependent. Unused bits in an implementation will
always read as zero. For compatibility with future devices, be sure to write these bits to zero.
5.7 Instruction execution timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the
chip. No internal clock division is used.
Figure 5-5 shows the parallel instruction fetches and instruction executions enabled by the Harvard
architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 5-5. The parallel instruction fetches and instruction executions.
Figure 5-6 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destination
register.
Bit 7 6 5 4 3 2 1 0
RAMPZ7 RAMPZ6 RAMPZ5 RAMPZ4 RAMPZ3 RAMPZ2 RAMPZ1 RAMPZ0 RAMPZ
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit (individually) 7 0 7 0 7 0
RAMPZ ZH ZL
Bit (Z-pointer) 23 16 15 8 7 0
clk
1st instruction fetch
1st instruction execute
2nd instruction fetch
2nd instruction execute
3rd instruction fetch
3rd instruction execute
4th instruction fetch
T1 T2 T3 T4
CPU17
7593L–AVR–09/12
AT90USB64/128
Figure 5-6. Single cycle ALU operation.
5.8 Reset and interrupt handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section “Memory programming”
on page 359 for details.
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 68. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL
bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 68 for more information.
The Reset Vector can also be moved to the start of the Boot Flash section by programming the
BOOTRST Fuse, see “Memory programming” on page 359.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled.
The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector
in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)
to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt
Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Total execution time
Register operands fetch
ALU operation execute
Result write back
T1 T2 T3 T4
clkCPU18
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AT90USB64/128
Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The following example shows how this can be used to avoid interrupts during the
timed EEPROM write sequence.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed
before any pending interrupts, as shown in this example.
Assembly code example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
C code example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
__disable_interrupt();
EECR |= (1< CSn2:0 > 1). The number of system clock cycles from
when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles,
where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution.
However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is
connected to.
13.3 External clock source
An external clock source applied to the Tn pin can be used as Timer/Counter clock (clkTn). The
Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized
(sampled) signal is then passed through the edge detector. Figure 13-1 shows a functional
equivalent block diagram of the Tn synchronization and edge detector logic. The registers are
clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the
high period of the internal system clock.
The edge detector generates one clkTn pulse for each positive (CSn2:0 = 7) or negative (CSn2:0
= 6) edge it detects.
Figure 13-1. Tn/T0 pin sampling.
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the Tn pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn has been stable for at least one
system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Tn_sync
(To clock
select logic)
Synchronization Edge detector
D Q D Q
LE
Tn D Q
clkI/O97
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Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the system
clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses
sampling, the maximum frequency of an external clock it can detect is half the sampling frequency
(Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5.
An external clock source can not be prescaled.
Figure 13-2. Prescaler for synchronous Timer/Counters
13.4 GTCCR – General Timer/Counter Control Register
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the corresponding
prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are
halted and can be configured to the same value without the risk of one of them advancing during
configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared
by hardware, and the Timer/Counters start counting simultaneously.
• Bit 0 – PSRSYNC: Prescaler Reset for Synchronous Timer/Counters
When this bit is one, Timer/Counter0 and Timer/Counter1 and Timer/Counter3 prescaler will be
Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note
that Timer/Counter0, Timer/Counter1 and Timer/Counter3 share the same prescaler and a reset
of this prescaler will affect all timers.
PSR10
Clear
Tn
Tn
clkI/O
Synchronization
Synchronization
TIMER/COUNTERn CLOCK SOURCE
clkTn
TIMER/COUNTERn CLOCK SOURCE
clkTn
CSn0
CSn1
CSn2
CSn0
CSn1
CSn2
Bit 7 6 5 4 3 2 1 0
TSM – – – – – PSRASY PSRSYNC GTCCR
Read/write R/W R R R R R R/W R/W
Initial value 0 0 0 0 0 0 0 098
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14. 8-bit Timer/Counter0 with PWM
Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output
Compare Units, and with PWM support. It allows accurate program execution timing (event management)
and wave generation. The main features are:
• Two independent output compare units
• Double buffered output compare registers
• Clear timer on compare match (auto reload)
• Glitch free, phase correct pulse width modulator (PWM)
• Variable PWM period
• Frequency generator
• Three independent interrupt sources (TOV0, OCF0A, and OCF0B)
14.1 Overview
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 14-1. For the actual
placement of I/O pins, refer to “Pinout Atmel AT90USB64/128-TQFP.” on page 3. CPU accessible
I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O
Register and bit locations are listed in the “8-bit Timer/Counter register description” on page 108.
Figure 14-1. 8-bit Timer/Counter block diagram.
14.1.1 Registers
The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit
registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the
Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Interrupt
Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0).
Clock select
Timer/Counter
DATA BUS
OCRnA
OCRnB
=
=
TCNTn
Waveform
generation
Waveform
generation
OCnA
OCnB
=
Fixed
TOP
value
Control logic
= 0
TOP BOTTOM
Count
Clear
Direction
TOVn
(int.req.)
OCnA
(int.req.)
OCnB
(Int.Req.)
TCCRnA TCCRnB
Tn Edge
detector
(From prescaler)
clkTn99
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The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator
to generate a PWM or variable frequency output on the Output Compare pins (OC0A and
OC0B). See “Output compare unit” on page 100. for details. The Compare Match event will also
set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare
interrupt request.
14.1.2 Definitions
Many register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Compare
Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or
bit defines in a program, the precise form must be used, that is, TCNT0 for accessing
Timer/Counter0 counter value and so on.
The definitions in the table below are also used extensively throughout the document.
14.2 Timer/Counter clock sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits
located in the Timer/Counter Control Register (TCCR0B). For details on clock sources and prescaler,
see “Timer/Counter0, Timer/Counter1, and Timer/Counter3 prescalers” on page 96.
14.3 Counter unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure
14-2 shows a block diagram of the counter and its surroundings.
Figure 14-2. Counter unit block diagram.
BOTTOM The counter reaches the BOTTOM when it becomes 0x00.
MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR0A Register. The assignment is dependent
on the mode of operation.
DATA BUS
TCNTn Control logic
count
TOVn
(int.req.)
Clock select
top
Tn Edge
detector
(From prescaler)
clkTn
bottom
direction
clear100
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Signal description (internal signals):
count Increment or decrement TCNT0 by 1.
direction Select between increment and decrement.
clear Clear TCNT0 (set all bits to zero).
clkTn Timer/Counter clock, referred to as clkT0 in the following.
top Signalize that TCNT0 has reached maximum value.
bottom Signalize that TCNT0 has reached minimum value (zero).
Depending of the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source,
selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the
timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of
whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or
count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in
the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter
Control Register B (TCCR0B). There are close connections between how the counter behaves
(counts) and how waveforms are generated on the Output Compare outputs OC0A and OC0B.
For more details about advanced counting sequences and waveform generation, see “Modes of
operation” on page 103.
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by
the WGM02:0 bits. TOV0 can be used for generating a CPU interrupt.
14.4 Output compare unit
The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers
(OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a
match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock
cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output
Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is executed.
Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit
location. The Waveform Generator uses the match signal to generate an output according to
operating mode set by the WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The
maximum and bottom signals are used by the Waveform Generator for handling the special
cases of the extreme values in some modes of operation (“Modes of operation” on page 103).
Figure 14-3 on page 101 shows a block diagram of the Output Compare unit. 101
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Figure 14-3. Output Compare Unit, block diagram.
The OCR0x Registers are double buffered when using any of the Pulse Width Modulation
(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double
buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare
Registers to either top or bottom of the counting sequence. The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR0x Register access may seem complex, but this is not case. When the double buffering
is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is disabled
the CPU will access the OCR0x directly.
14.4.1 Force output compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOC0x) bit. Forcing Compare Match will not set the
OCF0x Flag or reload/clear the timer, but the OC0x pin will be updated as if a real Compare
Match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set, cleared or
toggled).
14.4.2 Compare match blocking by TCNT0 write
All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initialized
to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is
enabled.
14.4.3 Using the output compare unit
Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer
clock cycle, there are risks involved when changing TCNT0 when using the Output Compare
Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0
equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform
generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is
down-counting.
OCFnx (int.req.)
= (8-bit comparator)
OCRnx
OCnx
DATA BUS
TCNTn
WGMn1:0
Waveform generator
top
FOCn
COMnX1:0
bottom102
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The setup of the OC0x should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare
(FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when
changing between Waveform Generation modes.
Be aware that the COM0x1:0 bits are not double buffered together with the compare value.
Changing the COM0x1:0 bits will take effect immediately.
14.5 Compare Match Output Unit
The Compare Output mode (COM0x1:0) bits have two functions. The Waveform Generator uses
the COM0x1:0 bits for defining the Output Compare (OC0x) state at the next Compare Match.
Also, the COM0x1:0 bits control the OC0x pin output source. Figure 14-4 shows a simplified
schematic of the logic affected by the COM0x1:0 bit setting. The I/O Registers, I/O bits, and I/O
pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers
(DDR and PORT) that are affected by the COM0x1:0 bits are shown. When referring to the
OC0x state, the reference is for the internal OC0x Register, not the OC0x pin. If a system reset
occur, the OC0x Register is reset to “0”.
Figure 14-4. Compare Match Output Unit, schematic.
The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform
Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or output)
is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visible
on the pin. The port override function is independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC0x state before the output
is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of
operation. See “8-bit Timer/Counter register description” on page 108.
14.5.1 Compare output mode and waveform generation
The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes.
For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the
OC0x Register is to be performed on the next Compare Match. For compare output actions in
PORT
DDR
D Q
D Q
OCnx
OCnx Pin
D Q Waveform
generator
COMnx1
COMnx0
0
1
DATA BUS
FOCn
clkI/O103
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the non-PWM modes refer to Table 14-1 on page 109. For fast PWM mode, refer to Table 14-2
on page 109, and for phase correct PWM refer to Table 14-3 on page 109.
A change of the COM0x1:0 bits state will have effect at the first Compare Match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOC0x strobe bits.
14.6 Modes of operation
The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins,
is defined by the combination of the Waveform Generation mode (WGM02:0) and Compare Output
mode (COM0x1:0) bits. The Compare Output mode bits do not affect the counting sequence,
while the Waveform Generation mode bits do. The COM0x1:0 bits control whether the PWM output
generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes
the COM0x1:0 bits control whether the output should be set, cleared, or toggled at a Compare
Match (See “Compare Match Output Unit” on page 102.).
For detailed timing information see “Timer/Counter timing diagrams” on page 107.
14.6.1 Normal mode
The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom
(0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same
timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth
bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV0 Flag, the timer resolution can be increased by software.
There are no special cases to consider in the Normal mode, a new counter value can be written
anytime.
The Output Compare Unit can be used to generate interrupts at some given time. Using the Output
Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
14.6.2 Clear Timer on Compare Match (CTC) mode
In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter
value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence
also its resolution. This mode allows greater control of the Compare Match output frequency. It
also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 14-5 on page 104. The counter value
(TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter
(TCNT0) is cleared.104
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Figure 14-5. CTC mode, timing diagram.
An interrupt can be generated each time the counter value reaches the TOP value by using the
OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating
the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running
with none or a low prescaler value must be done with care since the CTC mode does not
have the double buffering feature. If the new value written to OCR0A is lower than the current
value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can
occur.
For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical
level on each Compare Match by setting the Compare Output mode bits to toggle mode
(COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for
the pin is set to output. The waveform generated will have a maximum frequency of fOC0 =
fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following
equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the
counter counts from MAX to 0x00.
14.6.3 Fast PWM mode
The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high frequency
PWM waveform generation option. The fast PWM differs from the other PWM option by
its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM.
TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when WGM2:0 = 7. In noninverting
Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match
between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the output
is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the
operating frequency of the fast PWM mode can be twice as high as the phase correct PWM
mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited
for power regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the TOP value.
The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
TCNTn
OCn
(Toggle)
OCnx Interrupt Flag Set
Period 1 2 3 4
(COMnx1:0 = 1)
f
OCnx
f
clk_I/O
2 ⋅ ⋅ N ( ) 1 + OCRnx = -------------------------------------------------105
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PWM mode is shown in Figure 14-6. The TCNT0 value is in the timing diagram shown as a histogram
for illustrating the single-slope operation. The diagram includes non-inverted and
inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare
Matches between OCR0x and TCNT0.
Figure 14-6. Fast PWM mode, timing diagram.
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the interrupt
is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.
Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output
can be generated by setting the COM0x1:0 to three: Setting the COM0A1:0 bits to one allows
the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available
for the OC0B pin (see Table 14-2 on page 109). The actual OC0x value will only be visible on
the port pin if the data direction for the port pin is set as output. The PWM waveform is generated
by setting (or clearing) the OC0x Register at the Compare Match between OCR0x and
TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the counter is
cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represents special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will
be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result
in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0
bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting
OC0x to toggle its logical level on each Compare Match (COM0x1:0 = 1). The waveform
generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero. This
TCNTn
OCRnx update and
TOVn Interrupt Flag Set
Period 1 2 3
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCRnx Interrupt Flag Set
4 5 6 7
f
OCnxPWM
f
clk_I/O
N ⋅ 256 = ------------------106
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feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output
Compare unit is enabled in the fast PWM mode.
14.6.4 Phase correct PWM mode
The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct
PWM waveform generation option. The phase correct PWM mode is based on a dual-slope
operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM.
TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5. In noninverting
Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match
between TCNT0 and OCR0x while up-counting, and set on the Compare Match while downcounting.
In inverting Output Compare mode, the operation is inverted. The dual-slope operation
has lower maximum operation frequency than single slope operation. However, due to the symmetric
feature of the dual-slope PWM modes, these modes are preferred for motor control
applications.
In phase correct PWM mode the counter is incremented until the counter value matches TOP.
When the counter reaches TOP, it changes the count direction. The TCNT0 value will be equal
to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown
on Figure 14-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating
the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The
small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x
and TCNT0.
Figure 14-7. Phase correct PWM mode, timing diagram.
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The
Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM
value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted
PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to
TOVn Interrupt Flag Set
OCnx Interrupt Flag Set
1 2 3
TCNTn
Period
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCRnx update107
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one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is
not available for the OC0B pin (see Table 14-3 on page 109). The actual OC0x value will only be
visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is
generated by clearing (or setting) the OC0x Register at the Compare Match between OCR0x
and TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at Compare
Match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for
the output when using phase correct PWM can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in Figure 14-7 on page 106 OCnx has a transition from high to low
even though there is no Compare Match. The point of this transition is to guarantee symmetry
around BOTTOM. There are two cases that give a transition without Compare Match.
• OCR0A changes its value from MAX, like in Figure 14-7 on page 106. When the OCR0A
value is MAX the OCn pin value is the same as the result of a down-counting Compare
Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the
result of an up-counting Compare Match
• The timer starts counting from a value higher than the one in OCR0A, and for that reason
misses the Compare Match and hence the OCn change that would have happened on the
way up
14.7 Timer/Counter timing diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set. Figure 14-8 contains timing data for basic Timer/Counter operation. The figure
shows the count sequence close to the MAX value in all modes other than phase correct PWM
mode.
Figure 14-8. Timer/Counter timing diagram, no prescaling.
Figure 14-9 on page 108 shows the same timing data, but with the prescaler enabled.
f
OCnxPCPWM
f
clk_I/O
N ⋅ 510 = ------------------
clkTn
(clkI/O/1)
TOVn
clkI/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1108
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Figure 14-9. Timer/Counter timing diagram, with prescaler (fclk_I/O/8).
Figure 14-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC
mode and PWM mode, where OCR0A is TOP.
Figure 14-10. Timer/Counter timing diagram, setting of OCF0x, with prescaler (fclk_I/O/8).
Figure 14-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast
PWM mode where OCR0A is TOP.
Figure 14-11. Timer/Counter timing diagram, clear timer on Compare Match mode, with prescaler
(fclk_I/O/8)
14.8 8-bit Timer/Counter register description
14.8.1 TCCR0A – Timer/Counter Control Register A
TOVn
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
clkI/O
clkTn
(clkI/O/8)
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clkI/O
clkTn
(clkI/O/8)
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1 TOP BOTTOM BOTTOM + 1
clkI/O
clkTn
(clkI/O/8)
Bit 7 6 5 4 3 2 1 0
COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 TCCR0A
Read/write R/W R/W R/W R/W R R R/W R/W
Initial value 0 0 0 0 0 0 0 0109
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• Bits 7:6 – COM01A:0: Compare Match Output A Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0
bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin
must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM02:0 bit setting. Table 14-1 shows the COM0A1:0 bit functionality when the WGM02:0 bits
are set to a normal or CTC mode (non-PWM).
Table 14-2 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM
mode.
Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Compare
Match is ignored, but the set or clear is done at TOP. See “Fast PWM mode” on page 104
for more details.
Table 14-3 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase correct
PWM mode.
Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Compare
Match is ignored, but the set or clear is done at TOP. See “Phase correct PWM mode” on
page 106 for more details.
Table 14-1. Compare Output mode, non-PWM mode.
COM0A1 COM0A0 Description
0 0 Normal port operation, OC0A disconnected.
0 1 Toggle OC0A on Compare Match
1 0 Clear OC0A on Compare Match
1 1 Set OC0A on Compare Match
Table 14-2. Compare Output mode, Fast PWM mode (1).
COM0A1 COM0A0 Description
0 0 Normal port operation, OC0A disconnected.
0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.
1 0 Clear OC0A on Compare Match, set OC0A at TOP
1 1 Set OC0A on Compare Match, clear OC0A at TOP
Table 14-3. Compare Output mode, phase correct PWM mode (1).
COM0A1 COM0A0 Description
0 0 Normal port operation, OC0A disconnected.
0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.
1 0 Clear OC0A on Compare Match when up-counting. Set OC0A on Compare
Match when down-counting.
1 1 Set OC0A on Compare Match when up-counting. Clear OC0A on Compare
Match when down-counting.110
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• Bits 5:4 – COM0B1:0: Compare Match Output B mode
These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0
bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin
must be set in order to enable the output driver.
When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the
WGM02:0 bit setting. Table 14-1 shows the COM0A1:0 bit functionality when the WGM02:0 bits
are set to a normal or CTC mode (non-PWM).
Table 14-2 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM
mode.
Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare
Match is ignored, but the set or clear is done at TOP. See “Fast PWM mode” on page 104
for more details.
Table 14-3 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct
PWM mode.
Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare
Match is ignored, but the set or clear is done at TOP. See “Phase correct PWM mode” on
page 106 for more details.
• Bits 3, 2 – Res: Reserved bits
These bits are reserved bits in the Atmel AT90USB64/128 and will always read as zero.
Table 14-4. Compare Output mode, non-PWM mode.
COM01 COM00 Description
0 0 Normal port operation, OC0B disconnected.
0 1 Toggle OC0B on Compare Match
1 0 Clear OC0B on Compare Match
1 1 Set OC0B on Compare Match
Table 14-5. Compare Output mode, fast PWM mode (1).
COM01 COM00 Description
0 0 Normal port operation, OC0B disconnected.
0 1 Reserved.
1 0 Clear OC0B on Compare Match, set OC0B at TOP.
1 1 Set OC0B on Compare Match, clear OC0B at TOP.
Table 14-6. Compare Output mode, phase correct PWM mode (1).
COM0A1 COM0A0 Description
0 0 Normal port operation, OC0B disconnected.
0 1 Reserved.
1 0 Clear OC0B on Compare Match when up-counting. Set OC0B on Compare
Match when down-counting.
1 1 Set OC0B on Compare Match when up-counting. Clear OC0B on Compare
Match when down-counting.111
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• Bits 1:0 – WGM01:0: Waveform Generation Mode
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform
generation to be used, see Table 14-7. Modes of operation supported by the Timer/Counter
unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of
Pulse Width Modulation (PWM) modes (see “Modes of operation” on page 103).
Notes: 1. MAX = 0xFF
2. BOTTOM = 0x00
14.8.2 TCCR0B – Timer/Counter Control Register B
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is
changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a
strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the
forced compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0A as TOP.
The FOC0A bit is always read as zero.
• Bit 6 – FOC0B: Force Output Compare B
The FOC0B bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is
changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is implemented as a
Table 14-7. Waveform Generation Mode bit description.
Mode WGM2 WGM1 WGM0
Timer/Counter mode of
operation TOP
Update of
OCRx at
TOV flag
set on (1)(2)
0 0 0 0 Normal 0xFF Immediate MAX
1 0 0 1 PWM, phase correct 0xFF TOP BOTTOM
2 0 1 0 CTC OCRA Immediate MAX
3 0 1 1 Fast PWM 0xFF TOP MAX
4 1 0 0 Reserved – – –
5 1 0 1 PWM, phase correct OCRA TOP BOTTOM
6 1 1 0 Reserved – – –
7 1 1 1 Fast PWM OCRA TOP TOP
Bit 7 6 5 4 3 2 1 0
FOC0A FOC0B – – WGM02 CS02 CS01 CS00 TCCR0B
Read/write W W R R R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0112
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strobe. Therefore it is the value present in the COM0B1:0 bits that determines the effect of the
forced compare.
A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0B as TOP.
The FOC0B bit is always read as zero.
• Bits 5:4 – Res: Reserved bits
These bits are reserved bits and will always read as zero.
• Bit 3 – WGM02: Waveform Generation Mode
See the description in the “TCCR0A – Timer/Counter Control Register A” on page 108.
• Bits 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
14.8.3 TCNT0 – Timer/Counter Register
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare
Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,
introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers.
14.8.4 OCR0A – Output Compare Register A
Table 14-8. Clock Select bit description.
CS02 CS01 CS00 Description
0 0 0 No clock source (Timer/Counter stopped)
0 0 1 clkI/O/(No prescaling)
0 1 0 clkI/O/8 (From prescaler)
0 1 1 clkI/O/64 (From prescaler)
1 0 0 clkI/O/256 (From prescaler)
1 0 1 clkI/O/1024 (From prescaler)
1 1 0 External clock source on T0 pin. Clock on falling edge.
1 1 1 External clock source on T0 pin. Clock on rising edge.
Bit 7 6 5 4 3 2 1 0
TCNT0[7:0] TCNT0
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OCR0A[7:0] OCR0A
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0113
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The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0A pin.
14.8.5 OCR0B – Output Compare Register B
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0B pin.
14.8.6 TIMSK0 – Timer/Counter Interrupt Mask Register
• Bits 7..3, 0 – Res: Reserved bits
These bits are reserved bits and will always read as zero.
• Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter occurs, that is, when the OCF0B bit is set in the
Timer/Counter Interrupt Flag Register – TIFR0.
• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a Compare Match in Timer/Counter0 occurs, that is, when the OCF0A bit is set in the
Timer/Counter 0 Interrupt Flag Register – TIFR0.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, that is, when the TOV0 bit is set in the Timer/Counter 0 Interrupt
Flag Register – TIFR0.
14.8.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register
• Bits 7..3, 0 – Res: Reserved bits
These bits are reserved bits in the Atmel AT90USB64/128 and will always read as zero.
Bit 7 6 5 4 3 2 1 0
OCR0B[7:0] OCR0B
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
– – – – – OCIE0B OCIE0A TOIE0 TIMSK0
Read/write R R R R R R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
– – – – – OCF0B OCF0A TOV0 TIFR0
Read/write R R R R R R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0114
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• Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag
The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in
OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable),
and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.
• Bit 1 – OCF0A: Timer/Counter 0 Output Compare A Match Flag
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data
in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable),
and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by
writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt
Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.
The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 14-7, “Waveform
Generation Mode bit description.” on page 111.115
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15. 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
The 16-bit Timer/Counter unit allows accurate program execution timing (event management),
wave generation, and signal timing measurement. The main features are:
• True 16-bit design (that is, allows 16-bit PWM)
• Three independent output compare units
• Double buffered output compare registers
• One input capture unit
• Input capture noise canceler
• Clear timer on compare match (auto reload)
• Glitch-free, phase correct pulse width modulator (PWM)
• Variable PWM period
• Frequency generator
• External event counter
• Ten independent interrupt sources (TOV1, OCF1A, OCF1B, OCF1C, ICF1, TOV3, OCF3A, OCF3B,
OCF3C, and ICF3)
15.1 Overview
Most register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit
channel. However, when using the register or bit defines in a program, the precise form must be
used, that is, TCNT1 for accessing Timer/Counter1 counter value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 15-1 on page 116. For
the actual placement of I/O pins, see “Pinout Atmel AT90USB64/128-TQFP.” on page 3. CPU
accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific
I/O Register and bit locations are listed in the “16-bit Timer/Counter (Timer/Counter1 and
Timer/Counter3)” on page 115.
The Power Reduction Timer/Counter1 bit, PRTIM1, in “PRR0 – Power Reduction Register 0” on
page 54 must be written to zero to enable Timer/Counter1 module.
The Power Reduction Timer/Counter3 bit, PRTIM3, in “PRR1 – Power Reduction Register 1” on
page 55 must be written to zero to enable Timer/Counter3 module.116
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Figure 15-1. 16-bit Timer/Counter block diagram (1).
Note: 1. Refer to Figure 1-1 on page 3, Table 11-6 on page 79, and Table 11-9 on page 82 for
Timer/Counter1 and 3 and 3 pin placement and description.
15.1.1 Registers
The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Register
(ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16-
bit registers. These procedures are described in the section “Accessing 16-bit registers” on page
117. The Timer/Counter Control Registers (TCCRnA/B/C) are 8-bit registers and have no CPU
access restrictions. Interrupt requests (shorten as Int.Req.) signals are all visible in the Timer
Interrupt Flag Register (TIFRn). All interrupts are individually masked with the Timer Interrupt
Mask Register (TIMSKn). TIFRn and TIMSKn are not shown in the figure since these registers
are shared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the clock select logic is referred to as the timer clock (clkTn).
The double buffered Output Compare Registers (OCRnA/B/C) are compared with the
Timer/Counter value at all time. The result of the compare can be used by the Waveform Generator
to generate a PWM or variable frequency output on the Output Compare pin (OCnA/B/C).
ICFn (Int.Req.)
TOVn
(int.req.)
Clock select
Timer/Counter
DATABUS
ICRn
=
=
=
TCNTn
Waveform
generation
Waveform
generation
Waveform
generation
OCnA
OCnB
OCnC
Noise
canceler
ICPn
=
Fixed
TOP
values
Edge
detector
Control logic
= 0
TOP BOTTOM
Count
Clear
Direction
OCFnA
(Int.Req.)
OCFnB
(Int.Req.)
OCFnC
(Int.Req.)
TCCRnA TCCRnB TCCRnC
( From Analog
Comparator Ouput )
Tn Edge
detector
(From prescaler)
TCLK
OCRnC
OCRnB
OCRnA117
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See “Output Compare units” on page 124.. The compare match event will also set the Compare
Match Flag (OCFnA/B/C) which can be used to generate an Output Compare interrupt request.
The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered)
event on either the Input Capture pin (ICPn) or on the Analog Comparator pins (see
“Analog Comparator” on page 304) The Input Capture unit includes a digital filtering unit (Noise
Canceler) for reducing the chance of capturing noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined
by either the OCRnA Register, the ICRn Register, or by a set of fixed values. When using
OCRnA as TOP value in a PWM mode, the OCRnA Register can not be used for generating a
PWM output. However, the TOP value will in this case be double buffered allowing the TOP
value to be changed in run time. If a fixed TOP value is required, the ICRn Register can be used
as an alternative, freeing the OCRnA to be used as PWM output.
15.1.2 Definitions
The following definitions are used extensively throughout the document:
15.2 Accessing 16-bit registers
The TCNTn, OCRnA/B/C, and ICRn are 16-bit registers that can be accessed by the AVR CPU
via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations.
Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-
bit access. The same Temporary Register is shared between all 16-bit registers within each 16-
bit timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of
a 16-bit register is written by the CPU, the high byte stored in the Temporary Register, and the
low byte written are both copied into the 16-bit register in the same clock cycle. When the low
byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the
Temporary Register in the same clock cycle as the low byte is read.
Not all 16-bit accesses uses the Temporary Register for the high byte. Reading the OCRnA/B/C
16-bit registers does not involve using the Temporary Register.
To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low
byte must be read before the high byte.
The following code examples show how to access the 16-bit timer registers assuming that no
interrupts updates the temporary register. The same principle can be used directly for accessing
the OCRnA/B/C and ICRn Registers. Note that when using “C”, the compiler handles the 16-bit
access.
BOTTOM The counter reaches the BOTTOM when it becomes 0x0000.
MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).
TOP
The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be one of the fixed values:
0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCRnA or ICRn
Register. The assignment is dependent of the mode of operation.118
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Note: 1. See “About code examples” on page 10.
The assembly code example returns the TCNTn value in the r17:r16 register pair.
It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt
occurs between the two instructions accessing the 16-bit register, and the interrupt code
updates the temporary register by accessing the same or any other of the 16-bit Timer Registers,
then the result of the access outside the interrupt will be corrupted. Therefore, when both
the main code and the interrupt code update the temporary register, the main code must disable
the interrupts during the 16-bit access.
Assembly code examples (1)
...
; Set TCNTn to 0x01FF
ldi r17,0x01
ldi r16,0xFF
out TCNTnH,r17
out TCNTnL,r16
; Read TCNTn into r17:r16
in r16,TCNTnL
in r17,TCNTnH
...
C code examples (1)
unsigned int i;
...
/* Set TCNTn to 0x01FF */
TCNTn = 0x1FF;
/* Read TCNTn into i */
i = TCNTn;
...119
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The following code examples show how to do an atomic read of the TCNTn Register contents.
Reading any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.
Note: 1. See “About code examples” on page 10.
The assembly code example returns the TCNTn value in the r17:r16 register pair.
Assembly code example (1)
TIM16_ReadTCNTn:
; Save global interrupt flag
in r18,SREG
; Disable interrupts
cli
; Read TCNTn into r17:r16
in r16,TCNTnL
in r17,TCNTnH
; Restore global interrupt flag
out SREG,r18
ret
C code example (1)
unsigned int TIM16_ReadTCNTn( void )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
__disable_interrupt();
/* Read TCNTn into i */
i = TCNTn;
/* Restore global interrupt flag */
SREG = sreg;
return i;
}120
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The following code examples show how to do an atomic write of the TCNTn Register contents.
Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.
Note: 1. See “About code examples” on page 10.
The assembly code example requires that the r17:r16 register pair contains the value to be written
to TCNTn.
15.2.1 Reusing the Temporary High Byte register
If writing to more than one 16-bit register where the high byte is the same for all registers written,
then the high byte only needs to be written once. However, note that the same rule of atomic
operation described previously also applies in this case.
15.3 Timer/Counter clock sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CSn2:0) bits
located in the Timer/Counter control Register B (TCCRnB). For details on clock sources and
prescaler, see Section “Timer/Counter0, Timer/Counter1, and Timer/Counter3 prescalers” on
page 96.
Assembly code example (1)
TIM16_WriteTCNTn:
; Save global interrupt flag
in r18,SREG
; Disable interrupts
cli
; Set TCNTn to r17:r16
out TCNTnH,r17
out TCNTnL,r16
; Restore global interrupt flag
out SREG,r18
ret
C code example (1)
void TIM16_WriteTCNTn( unsigned int i )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
__disable_interrupt();
/* Set TCNTn to i */
TCNTn = i;
/* Restore global interrupt flag */
SREG = sreg;
}121
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15.4 Counter unit
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.
Figure 15-2 shows a block diagram of the counter and its surroundings.
Figure 15-2. Counter unit block diagram.
Signal description (internal signals):
Count Increment or decrement TCNTn by 1.
Direction Select between increment and decrement.
Clear Clear TCNTn (set all bits to zero).
clkTn Timer/Counter clock.
TOP Signalize that TCNTn has reached maximum value.
BOTTOM Signalize that TCNTn has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) containing
the upper eight bits of the counter, and Counter Low (TCNTnL) containing the lower eight
bits. The TCNTnH Register can only be indirectly accessed by the CPU. When the CPU does an
access to the TCNTnH I/O location, the CPU accesses the high byte temporary register (TEMP).
The temporary register is updated with the TCNTnH value when the TCNTnL is read, and
TCNTnH is updated with the temporary register value when TCNTnL is written. This allows the
CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.
It is important to notice that there are special cases of writing to the TCNTn Register when the
counter is counting that will give unpredictable results. The special cases are described in the
sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clkTn). The clkTn can be generated from an external or internal clock source,
selected by the Clock Select bits (CSn2:0). When no clock source is selected (CSn2:0 = 0) the
timer is stopped. However, the TCNTn value can be accessed by the CPU, independent of
whether clkTn is present or not. A CPU write overrides (has priority over) all counter clear or
count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits
(WGMn3:0) located in the Timer/Counter Control Registers A and B (TCCRnA and TCCRnB).
There are close connections between how the counter behaves (counts) and how waveforms
are generated on the Output Compare outputs OCnx. For more details about advanced counting
sequences and waveform generation, see Section “Modes of operation” on page 127.
TEMP (8-bit)
DATA BUS (8-bit)
TCNTn (16-bit counter)
TCNTnH (8-bit) TCNTnL (8-bit) Control logic
Count
Clear
Direction
TOVn
(Int.Req.)
Clock select
TOP BOTTOM
Tn Edge
detector
(From prescaler)
clkTn122
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The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by
the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt.
15.5 Input Capture unit
The Timer/Counter incorporates an Input Capture unit that can capture external events and give
them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple
events, can be applied via the ICPn pin or alternatively, for the Timer/Counter1 only, via the
Analog Comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle,
and other features of the signal applied. Alternatively the time-stamps can be used for creating a
log of the events.
The Input Capture unit is illustrated by the block diagram shown in Figure 15-3. The elements of
the block diagram that are not directly a part of the input capture unit are gray shaded. The small
“n” in register and bit names indicates the Timer/Counter number.
Figure 15-3. Input Capture Unit block diagram.
Note: The Analog Comparator Output (ACO) can only trigger the Timer/Counter1 ICP – not
Timer/Counter3, 4, or 5.
When a change of the logic level (an event) occurs on the Input Capture Pin (ICPn), alternatively
on the analog Comparator output (ACO), and this change confirms to the setting of the edge
detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter
(TCNTn) is written to the Input Capture Register (ICRn). The Input Capture Flag (ICFn) is set at
the same system clock as the TCNTn value is copied into ICRn Register. If enabled (TICIEn =
1), the input capture flag generates an input capture interrupt. The ICFn flag is automatically
cleared when the interrupt is executed. Alternatively the ICFn flag can be cleared by software by
writing a logical one to its I/O bit location.
ICFn (int.req.)
Analog
comparator
WRITE ICRn (16-bit register)
ICRnH (8-bit)
Noise
canceler
ICPn
Edge
detector
TEMP (8-bit)
DATA BUS (8-bit)
ICRnL (8-bit)
TCNTn (16-bit counter)
TCNTnH (8-bit) TCNTnL (8-bit)
ACO* ACIC* ICNC ICES123
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Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low
byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high byte is copied
into the high byte Temporary Register (TEMP). When the CPU reads the ICRnH I/O location it
will access the TEMP Register.
The ICRn Register can only be written when using a Waveform Generation mode that utilizes
the ICRn Register for defining the counter’s TOP value. In these cases the Waveform Generation
mode (WGMn3:0) bits must be set before the TOP value can be written to the ICRn
Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location
before the low byte is written to ICRnL.
For more information on how to access the 16-bit registers refer to Section “Accessing 16-bit
registers” on page 117.
15.5.1 Input Capture Trigger Source
The main trigger source for the input capture unit is the Input Capture Pin (ICPn).
Timer/Counter1 can alternatively use the analog comparator output as trigger source for the
input capture unit. The Analog Comparator is selected as trigger source by setting the analog
Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register
(ACSR). Be aware that changing trigger source can trigger a capture. The input capture flag
must therefore be cleared after the change.
Both the Input Capture Pin (ICPn) and the Analog Comparator output (ACO) inputs are sampled
using the same technique as for the Tn pin (Figure 13-1 on page 96). The edge detector is also
identical. However, when the noise canceler is enabled, additional logic is inserted before the
edge detector, which increases the delay by four system clock cycles. Note that the input of the
noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform
Generation mode that uses ICRn to define TOP.
An input capture can be triggered by software by controlling the port of the ICPn pin.
15.5.2 Noise Canceler
The Noise Canceler improves noise immunity by using a simple digital filtering scheme. The
noise canceler input is monitored over four samples, and all four must be equal for changing the
output that in turn is used by the edge detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNCn) bit in
Timer/Counter Control Register B (TCCRnB). When enabled the noise canceler introduces additional
four system clock cycles of delay from a change applied to the input, to the update of the
ICRn Register. The noise canceler uses the system clock and is therefore not affected by the
prescaler.
15.5.3 Using the Input Capture unit
The main challenge when using the Input Capture unit is to assign enough processor capacity
for handling the incoming events. The time between two events is critical. If the processor has
not read the captured value in the ICRn Register before the next event occurs, the ICRn will be
overwritten with a new value. In this case the result of the capture will be incorrect.
When using the Input Capture interrupt, the ICRn Register should be read as early in the interrupt
handler routine as possible. Even though the Input Capture interrupt has relatively high
priority, the maximum interrupt response time is dependent on the maximum number of clock
cycles it takes to handle any of the other interrupt requests.124
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Using the Input Capture unit in any mode of operation when the TOP value (resolution) is
actively changed during operation, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after
each capture. Changing the edge sensing must be done as early as possible after the ICRn
Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be
cleared by software (writing a logical one to the I/O bit location). For measuring frequency only,
the clearing of the ICFn Flag is not required (if an interrupt handler is used).
15.6 Output Compare units
The 16-bit comparator continuously compares TCNTn with the Output Compare Register
(OCRnx). If TCNT equals OCRnx the comparator signals a match. A match will set the Output
Compare Flag (OCFnx) at the next timer clock cycle. If enabled (OCIEnx = 1), the Output Compare
Flag generates an Output Compare interrupt. The OCFnx Flag is automatically cleared
when the interrupt is executed. Alternatively the OCFnx Flag can be cleared by software by writing
a logical one to its I/O bit location. The Waveform Generator uses the match signal to
generate an output according to operating mode set by the Waveform Generation mode
(WGMn3:0) bits and Compare Output mode (COMnx1:0) bits. The TOP and BOTTOM signals
are used by the Waveform Generator for handling the special cases of the extreme values in
some modes of operation (see “Modes of operation” on page 127)
A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (that
is, counter resolution). In addition to the counter resolution, the TOP value defines the period
time for waveforms generated by the Waveform Generator.
Figure 15-4 shows a block diagram of the Output Compare unit. The small “n” in the register and
bit names indicates the device number (n = n for Timer/Counter n), and the “x” indicates Output
Compare unit (A/B/C). The elements of the block diagram that are not directly a part of the Output
Compare unit are gray shaded.
Figure 15-4. Output Compare Unit, block diagram.
OCFnx (int.req.)
= (16-bit comparator )
OCRnx buffer (16-bit register)
OCRnxH buf. (8-bit)
OCnx
TEMP (8-bit)
DATA BUS (8-bit)
OCRnxL buf. (8-bit)
TCNTn (16-bit counter)
TCNTnH (8-bit) TCNTnL (8-bit)
WGMn3:0 COMnx1:0
OCRnx (16-bit register)
OCRnxH (8-bit) OCRnxL (8-bit)
Waveform generator
TOP
BOTTOM125
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The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation
(PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the
double buffering is disabled. The double buffering synchronizes the update of the OCRnx Compare
Register to either TOP or BOTTOM of the counting sequence. The synchronization
prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output
glitch-free.
The OCRnx Register access may seem complex, but this is not case. When the double buffering
is enabled, the CPU has access to the OCRnx Buffer Register, and if double buffering is disabled
the CPU will access the OCRnx directly. The content of the OCR1x (Buffer or Compare)
Register is only changed by a write operation (the Timer/Counter does not update this register
automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the high byte
temporary register (TEMP). However, it is a good practice to read the low byte first as when
accessing other 16-bit registers. Writing the OCRnx Registers must be done via the TEMP Register
since the compare of all 16 bits is done continuously. The high byte (OCRnxH) has to be
written first. When the high byte I/O location is written by the CPU, the TEMP Register will be
updated by the value written. Then when the low byte (OCRnxL) is written to the lower eight bits,
the high byte will be copied into the upper 8-bits of either the OCRnx buffer or OCRnx Compare
Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to Section “Accessing 16-bit registers”
on page 117.
15.6.1 Force Output Compare
In non-PWM Waveform Generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOCnx) bit. Forcing compare match will not set the
OCFnx Flag or reload/clear the timer, but the OCnx pin will be updated as if a real compare
match had occurred (the COMn1:0 bits settings define whether the OCnx pin is set, cleared or
toggled).
15.6.2 Compare Match Blocking by TCNTn write
All CPU writes to the TCNTn Register will block any compare match that occurs in the next timer
clock cycle, even when the timer is stopped. This feature allows OCRnx to be initialized to the
same value as TCNTn without triggering an interrupt when the Timer/Counter clock is enabled.
15.6.3 Using the Output Compare unit
Since writing TCNTn in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNTn when using any of the Output Compare
channels, independent of whether the Timer/Counter is running or not. If the value written to
TCNTn equals the OCRnx value, the compare match will be missed, resulting in incorrect waveform
generation. Do not write the TCNTn equal to TOP in PWM modes with variable TOP
values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF.
Similarly, do not write the TCNTn value equal to BOTTOM when the counter is counting down.
The setup of the OCnx should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OCnx value is to use the Force Output Compare
(FOCnx) strobe bits in Normal mode. The OCnx Register keeps its value even when
changing between Waveform Generation modes.
Be aware that the COMnx1:0 bits are not double buffered together with the compare value.
Changing the COMnx1:0 bits will take effect immediately.126
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15.7 Compare Match Output unit
The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses
the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match.
Secondly the COMnx1:0 bits control the OCnx pin output source. Figure 15-5 shows a simplified
schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O
pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers
(DDR and PORT) that are affected by the COMnx1:0 bits are shown. When referring to the
OCnx state, the reference is for the internal OCnx Register, not the OCnx pin. If a system reset
occur, the OCnx Register is reset to “0”.
Figure 15-5. Compare Match Output unit, schematic.
The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform
Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or output)
is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OCnx pin (DDR_OCnx) must be set as output before the OCnx value is visible
on the pin. The port override function is generally independent of the Waveform Generation
mode, but there are some exceptions. Refer to Table 15-1 on page 137, Table 15-2 on page
137, and Table 15-3 on page 138 for details.
The design of the Output Compare pin logic allows initialization of the OCnx state before the output
is enabled. Note that some COMnx1:0 bit settings are reserved for certain modes of
operation. See “16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)” on page 115.
The COMnx1:0 bits have no effect on the Input Capture unit.
15.7.1 Compare Output mode and Waveform generation
The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes.
For all modes, setting the COMnx1:0 = 0 tells the Waveform Generator that no action on the
OCnx Register is to be performed on the next compare match. For compare output actions in the
PORT
DDR
D Q
D Q
OCnx
OCnx pin
D Q Waveform
generator
COMnx1
COMnx0
0
1
DATA BUS
FOCnx
clkI/O127
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non-PWM modes refer to Table 15-1 on page 137. For fast PWM mode refer to Table 15-2 on
page 137, and for phase correct and phase and frequency correct PWM refer to Table 15-3 on
page 138.
A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOCnx strobe bits.
15.8 Modes of operation
The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins,
is defined by the combination of the Waveform Generation mode (WGMn3:0) and Compare Output
mode (COMnx1:0) bits. The Compare Output mode bits do not affect the counting sequence,
while the Waveform Generation mode bits do. The COMnx1:0 bits control whether the PWM output
generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes
the COMnx1:0 bits control whether the output should be set, cleared or toggle at a compare
match (see “Compare Match Output unit” on page 126).
For detailed timing information refer to “Timer/Counter timing diagrams” on page 134.
15.8.1 Normal mode
The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the
BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOVn) will be set in
the same timer clock cycle as the TCNTn becomes zero. The TOVn Flag in this case behaves
like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow
interrupt that automatically clears the TOVn Flag, the timer resolution can be increased by software.
There are no special cases to consider in the Normal mode, a new counter value can be
written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maximum
interval between the external events must not exceed the resolution of the counter. If the interval
between events are too long, the timer overflow interrupt or the prescaler must be used to
extend the resolution for the capture unit.
The Output Compare units can be used to generate interrupts at some given time. Using the
Output Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
15.8.2 Clear Timer on Compare Match (CTC) mode
In Clear Timer on Compare or CTC mode (WGMn3:0 = 4 or 12), the OCRnA or ICRn Register
are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when
the counter value (TCNTn) matches either the OCRnA (WGMn3:0 = 4) or the ICRn (WGMn3:0 =
12). The OCRnA or ICRn define the top value for the counter, hence also its resolution. This
mode allows greater control of the compare match output frequency. It also simplifies the operation
of counting external events.
The timing diagram for the CTC mode is shown in Figure 15-6 on page 128. The counter value
(TCNTn) increases until a compare match occurs with either OCRnA or ICRn, and then counter
(TCNTn) is cleared.128
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Figure 15-6. CTC mode, timing diagram.
An interrupt can be generated at each time the counter value reaches the TOP value by either
using the OCFnA or ICFn Flag according to the register used to define the TOP value. If the
interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However,
changing the TOP to a value close to BOTTOM when the counter is running with none or a
low prescaler value must be done with care since the CTC mode does not have the double buffering
feature. If the new value written to OCRnA or ICRn is lower than the current value of
TCNTn, the counter will miss the compare match. The counter will then have to count to its maximum
value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur.
In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode
using OCRnA for defining TOP (WGMn3:0 = 15) since the OCRnA then will be double buffered.
For generating a waveform output in CTC mode, the OCnA output can be set to toggle its logical
level on each compare match by setting the Compare Output mode bits to toggle mode
(COMnA1:0 = 1). The OCnA value will not be visible on the port pin unless the data direction for
the pin is set to output (DDR_OCnA = 1). The waveform generated will have a maximum frequency
of fOCnA = fclk_I/O/2 when OCRnA is set to zero (0x0000). The waveform frequency is
defined by the following equation:
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOVn Flag is set in the same timer clock cycle that the
counter counts from MAX to 0x0000.
15.8.3 Fast PWM mode
The fast Pulse Width Modulation or fast PWM mode (WGMn3:0 = 5, 6, 7, 14, or 15) provides a
high frequency PWM waveform generation option. The fast PWM differs from the other PWM
options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts
from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is set on
the compare match between TCNTn and OCRnx, and cleared at TOP. In inverting Compare
Output mode output is cleared on compare match and set at TOP. Due to the single-slope operation,
the operating frequency of the fast PWM mode can be twice as high as the phase correct
and phase and frequency correct PWM modes that use dual-slope operation. This high frequency
makes the fast PWM mode well suited for power regulation, rectification, and DAC
applications. High frequency allows physically small sized external components (coils, capacitors),
hence reduces total system cost.
TCNTn
OCnA
(Toggle)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(interrupt on TOP)
Period 1 2 3 4
(COMnA1:0 = 1)
f
OCnA
f
clk_I/O
2 ⋅ ⋅ N ( ) 1 + OCRnA = --------------------------------------------------129
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The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or
OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum
resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be
calculated by using the following equation:
In fast PWM mode the counter is incremented until the counter value matches either one of the
fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 5, 6, or 7), the value in ICRn (WGMn3:0 =
14), or the value in OCRnA (WGMn3:0 = 15). The counter is then cleared at the following timer
clock cycle. The timing diagram for the fast PWM mode is shown in Figure 15-7. The figure
shows fast PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the
timing diagram shown as a histogram for illustrating the single-slope operation. The diagram
includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn
slopes represent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will
be set when a compare match occurs.
Figure 15-7. Fast PWM mode, timing diagram.
The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addition
the OCnA or ICFn Flag is set at the same timer clock cycle as TOVn is set when either OCRnA
or ICRn is used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler
routine can be used for updating the TOP and compare values.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNTn and the OCRnx.
Note that when using fixed TOP values the unused bits are masked to zero when any of the
OCRnx Registers are written.
The procedure for updating ICRn differs from updating OCRnA when used for defining the TOP
value. The ICRn Register is not double buffered. This means that if ICRn is changed to a low
value when the counter is running with none or a low prescaler value, there is a risk that the new
ICRn value written is lower than the current value of TCNTn. The result will then be that the
counter will miss the compare match at the TOP value. The counter will then have to count to the
MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur.
The OCRnA Register however, is double buffered. This feature allows the OCRnA I/O location
RFPWM
log( ) TOP + 1
log( ) 2 = -----------------------------------
TCNTn
OCRnx / TOP Update
and TOVn Interrupt Flag
Set and OCnA Interrupt
Flag Set or ICFn
Interrupt Flag Set
(Interrupt on TOP)
Period 1 2 3 4 5 6 7 8
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)130
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to be written anytime. When the OCRnA I/O location is written the value written will be put into
the OCRnA Buffer Register. The OCRnA Compare Register will then be updated with the value
in the Buffer Register at the next timer clock cycle the TCNTn matches TOP. The update is done
at the same timer clock cycle as the TCNTn is cleared and the TOVn Flag is set.
Using the ICRn Register for defining TOP works well when using fixed TOP values. By using
ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However,
if the base PWM frequency is actively changed (by changing the TOP value), using the OCRnA
as TOP is clearly a better choice due to its double buffer feature.
In fast PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins.
Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output
can be generated by setting the COMnx1:0 to three (see Table on page 137). The actual OCnx
value will only be visible on the port pin if the data direction for the port pin is set as output
(DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at
the compare match between OCRnx and TCNTn, and clearing (or setting) the OCnx Register at
the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represents special cases when generating a PWM
waveform output in the fast PWM mode. If the OCRnx is set equal to BOTTOM (0x0000) the output
will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCRnx equal to TOP
will result in a constant high or low output (depending on the polarity of the output set by the
COMnx1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting
OCnA to toggle its logical level on each compare match (COMnA1:0 = 1). This applies only
if OCR1A is used to define the TOP value (WGM13:0 = 15). The waveform generated will have
a maximum frequency of fOCnA = fclk_I/O/2 when OCRnA is set to zero (0x0000). This feature is
similar to the OCnA toggle in CTC mode, except the double buffer feature of the Output Compare
unit is enabled in the fast PWM mode.
15.8.4 Phase correct PWM mode
The phase correct Pulse Width Modulation or phase correct PWM mode (WGMn3:0 = 1, 2, 3,
10, or 11) provides a high resolution phase correct PWM waveform generation option. The
phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dualslope
operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from
TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is
cleared on the compare match between TCNTn and OCRnx while upcounting, and set on the
compare match while downcounting. In inverting Output Compare mode, the operation is
inverted. The dual-slope operation has lower maximum operation frequency than single slope
operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes
are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined
by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to
f
OCnxPWM
f
clk_I/O
N ⋅ ( ) 1 + TOP = -----------------------------------131
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0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution
in bits can be calculated by using the following equation:
In phase correct PWM mode the counter is incremented until the counter value matches either
one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 1, 2, or 3), the value in ICRn
(WGMn3:0 = 10), or the value in OCRnA (WGMn3:0 = 11). The counter has then reached the
TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clock
cycle. The timing diagram for the phase correct PWM mode is shown on Figure 15-8. The figure
shows phase correct PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn
value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The
diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on
the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx Interrupt
Flag will be set when a compare match occurs.
Figure 15-8. Phase correct PWM mode, timing diagram.
The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. When
either OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn Flag is set accordingly
at the same timer clock cycle as the OCRnx Registers are updated with the double buffer
value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter
reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNTn and the OCRnx.
Note that when using fixed TOP values, the unused bits are masked to zero when any of the
OCRnx Registers are written. As the third period shown in Figure 15-8 illustrates, changing the
TOP actively while the Timer/Counter is running in the phase correct mode can result in an
unsymmetrical output. The reason for this can be found in the time of update of the OCRnx RegRPCPWM
log( ) TOP + 1
log( ) 2 = -----------------------------------
OCRnx/TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(interrupt on TOP)
1 2 3 4
TOVn Interrupt Flag Set
(interrupt on Bottom)
TCNTn
Period
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)132
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ister. Since the OCRnx update occurs at TOP, the PWM period starts and ends at TOP. This
implies that the length of the falling slope is determined by the previous TOP value, while the
length of the rising slope is determined by the new TOP value. When these two values differ the
two slopes of the period will differ in length. The difference in length gives the unsymmetrical
result on the output.
It is recommended to use the phase and frequency correct mode instead of the phase correct
mode when changing the TOP value while the Timer/Counter is running. When using a static
TOP value there are practically no differences between the two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the
OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted
PWM output can be generated by setting the COMnx1:0 to three (see Table 15-3 on page 138).
The actual OCnx value will only be visible on the port pin if the data direction for the port pin is
set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx
Register at the compare match between OCRnx and TCNTn when the counter increments, and
clearing (or setting) the OCnx Register at compare match between OCRnx and TCNTn when
the counter decrements. The PWM frequency for the output when using phase correct PWM can
be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If
OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1:0 = 1, the OC1A output
will toggle with a 50% duty cycle.
15.8.5 Phase and frequency correct PWM mode
The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM
mode (WGMn3:0 = 8 or 9) provides a high resolution phase and frequency correct PWM waveform
generation option. The phase and frequency correct PWM mode is, like the phase correct
PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM
(0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the
Output Compare (OCnx) is cleared on the compare match between TCNTn and OCRnx while
upcounting, and set on the compare match while downcounting. In inverting Compare Output
mode, the operation is inverted. The dual-slope operation gives a lower maximum operation frequency
compared to the single-slope operation. However, due to the symmetric feature of the
dual-slope PWM modes, these modes are preferred for motor control applications.
The main difference between the phase correct, and the phase and frequency correct PWM
mode is the time the OCRnx Register is updated by the OCRnx Buffer Register, (see Figure 15-
8 on page 131 and Figure 15-9 on page 133).
The PWM resolution for the phase and frequency correct PWM mode can be defined by either
ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and
f
OCnxPCPWM
f
clk_I/O
2 ⋅ ⋅ N TOP = ----------------------------133
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the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can
be calculated using the following equation:
In phase and frequency correct PWM mode the counter is incremented until the counter value
matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA (WGMn3:0 = 9). The
counter has then reached the TOP and changes the count direction. The TCNTn value will be
equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency
correct PWM mode is shown on Figure 15-9. The figure shows phase and frequency correct
PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram
shown as a histogram for illustrating the dual-slope operation. The diagram includes noninverted
and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent
compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a
compare match occurs.
Figure 15-9. Phase and frequency correct PWM mode, timing diagram.
The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx
Registers are updated with the double buffer value (at BOTTOM). When either OCRnA or ICRn
is used for defining the TOP value, the OCnA or ICFn Flag set when TCNTn has reached TOP.
The Interrupt Flags can then be used to generate an interrupt each time the counter reaches the
TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNTn and the OCRnx.
As Figure 15-9 shows the output generated is, in contrast to the phase correct mode, symmetrical
in all periods. Since the OCRnx Registers are updated at BOTTOM, the length of the rising
and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore
frequency correct.
RPFCPWM
log( ) TOP + 1
log( ) 2 = -----------------------------------
OCRnx/TOP Updateand
TOVn Interrupt Flag Set
(interrupt on Bottom)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(interrupt on TOP)
1 2 3 4
TCNTn
Period
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)134
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Using the ICRn Register for defining TOP works well when using fixed TOP values. By using
ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However,
if the base PWM frequency is actively changed by changing the TOP value, using the OCRnA as
TOP is clearly a better choice due to its double buffer feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms
on the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and
an inverted PWM output can be generated by setting the COMnx1:0 to three (see Table 15-3 on
page 138). The actual OCnx value will only be visible on the port pin if the data direction for the
port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing)
the OCnx Register at the compare match between OCRnx and TCNTn when the counter increments,
and clearing (or setting) the OCnx Register at compare match between OCRnx and
TCNTn when the counter decrements. The PWM frequency for the output when using phase
and frequency correct PWM can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represents special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be set to high for noninverted
PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A
is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle
with a 50% duty cycle.
15.9 Timer/Counter timing diagrams
The Timer/Counter is a synchronous design and the timer clock (clkTn) is therefore shown as a
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for
modes utilizing double buffering). Figure 15-10 shows a timing diagram for the setting of OCFnx.
Figure 15-10. Timer/Counter timing diagram, setting of OCFnx, no prescaling.
Figure 15-11 on page 135 shows the same timing data, but with the prescaler enabled.
f
OCnxPFCPWM
f
clk_I/O
2 ⋅ ⋅ N TOP = ----------------------------
clkTn
(clkI/O/1)
OCFnx
clkI/O
OCRnx
TCNTn
OCRnx value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2135
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Figure 15-11. Timer/Counter timing diagram, setting of OCFnx, with prescaler (fclk_I/O/8).
Figure 15-12 shows the count sequence close to TOP in various modes. When using phase and
frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams
will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
The same renaming applies for modes that set the TOVn Flag at BOTTOM.
Figure 15-12. Timer/Counter timing diagram, no prescaling.
Figure 15-13 on page 136 shows the same timing data, but with the prescaler enabled.
OCFnx
OCRnx
TCNTn
OCRnx value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clkI/O
clkTn
(clkI/O/8)
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
(update at TOP)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2
Old OCRnx value New OCRnx value
TOP - 1 TOP BOTTOM BOTTOM + 1
clkTn
(clkI/O/1)
clkI/O136
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Figure 15-13. Timer/Counter timing diagram, with prescaler (fclk_I/O/8).
15.10 16-bit Timer/Counter register description
15.10.1 TCCR1A – Timer/Counter1 Control Register A
15.10.2 TCCR3A – Timer/Counter3 Control Register A
• Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A
• Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B
• Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C
The COMnA1:0, COMnB1:0, and COMnC1:0 control the output compare pins (OCnA, OCnB,
and OCnC respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the
OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or
both of the COMnB1:0 bits are written to one, the OCnB output overrides the normal port functionality
of the I/O pin it is connected to. If one or both of the COMnC1:0 bits are written to one,
the OCnC output overrides the normal port functionality of the I/O pin it is connected to. However,
note that the Data Direction Register (DDR) bit corresponding to the OCnA, OCnB or
OCnC pin must be set in order to enable the output driver.
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
(update at TOP)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOP - 1 TOP TOP - 1 TOP - 2
Old OCRnx value New OCRnx value
TOP - 1 TOP BOTTOM BOTTOM + 1
clkI/O
clk Tn
(clkI/O /8)
Bit 7 6 5 4 3 2 1 0
COM1A1 COM1A0 COM1B1 COM1B0 COM1C1 COM1C0 WGM11 WGM10 TCCR1A
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
COM3A1 COM3A0 COM3B1 COM3B0 COM3C1 COM3C0 WGM31 WGM30 TCCR3A
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0137
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When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is
dependent of the WGMn3:0 bits setting. Table 15-1 shows the COMnx1:0 bit functionality when
the WGMn3:0 bits are set to a normal or a CTC mode (non-PWM).
Table 15-2 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast
PWM mode.
Note: A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and
COMnA1/COMnB1/COMnC1 is set. In this case the compare match is ignored, but the set or clear
is done at TOP. See “Fast PWM mode” on page 104. for more details.
Table 15-3 on page 138 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to
the phase correct and frequency correct PWM mode.
Table 15-1. Compare Output mode, non-PWM.
COMnA1/COMnB1/
COMnC1
COMnA0/COMnB0/
COMnC0 Description
0 0 Normal port operation, OCnA/OCnB/OCnC
disconnected.
0 1 Toggle OCnA/OCnB/OCnC on compare match.
1 0 Clear OCnA/OCnB/OCnC on compare match (set
output to low level).
1 1 Set OCnA/OCnB/OCnC on compare match (set
output to high level).
Table 15-2. Compare Output mode, fast PWM.
COMnA1/COMnB1/
COMnC0
COMnA0/COMnB0/
COMnC0 Description
0 0 Normal port operation, OCnA/OCnB/OCnC
disconnected.
0 1
WGM13:0 = 14 or 15: Toggle OC1A on Compare
Match, OC1B and OC1C disconnected (normal port
operation). For all other WGM1 settings, normal port
operation, OC1A/OC1B/OC1C disconnected.
1 0 Clear OCnA/OCnB/OCnC on compare match, set
OCnA/OCnB/OCnC at TOP
1 1 Set OCnA/OCnB/OCnC on compare match, clear
OCnA/OCnB/OCnC at TOP138
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Note: A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and
COMnA1/COMnB1//COMnC1 is set. See “Phase correct PWM mode” on page 106. for more
details.
• Bit 1:0 – WGMn1:0: Waveform Generation mode
Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform
generation to be used, see Table 15-4 on page 138. Modes of operation supported by the
Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode,
and three types of Pulse Width Modulation (PWM) modes. (See “Modes of operation” on page
103.).
Table 15-3. Compare Output mode, phase correct and phase and frequency correct PWM.
COMnA1/COMnB/
COMnC1
COMnA0/COMnB0/
COMnC0 Description
0 0 Normal port operation, OCnA/OCnB/OCnC
disconnected.
0 1
WGM13:0 = 8, 9 10 or 11: Toggle OC1A on
Compare Match, OC1B and OC1C
disconnected (normal port operation). For all
other WGM1 settings, normal port operation,
OC1A/OC1B/OC1C disconnected.
1 0
Clear OCnA/OCnB/OCnC on compare
match when up-counting. Set
OCnA/OCnB/OCnC on compare match
when counting down.
1 1
Set OCnA/OCnB/OCnC on compare match
when up-counting. Clear
OCnA/OCnB/OCnC on compare match
when counting down.
Table 15-4. Waveform Generation mode bit description (1).
Mode WGMn3
WGMn2
(CTCn)
WGMn1
(PWMn1)
WGMn0
(PWMn0)
Timer/Counter mode of
operation TOP
Update of
OCRnx at
TOVn flag
set on
0 0 0 0 0 Normal 0xFFFF Immediate MAX
1 0 0 0 1 PWM, phase correct, 8-bit 0x00FF TOP BOTTOM
2 0 0 1 0 PWM, phase correct, 9-bit 0x01FF TOP BOTTOM
3 0 0 1 1 PWM, phase correct, 10-bit 0x03FF TOP BOTTOM
4 0 1 0 0 CTC OCRnA Immediate MAX
5 0 1 0 1 Fast PWM, 8-bit 0x00FF TOP TOP
6 0 1 1 0 Fast PWM, 9-bit 0x01FF TOP TOP
7 0 1 1 1 Fast PWM, 10-bit 0x03FF TOP TOP
81 0 0 0 PWM, phase and frequency
Correct ICRn BOTTOM BOTTOM
91 0 0 1 PWM, phase and frequency
Correct OCRnA BOTTOM BOTTOM
10 1 0 1 0 PWM, phase correct ICRn TOP BOTTOM139
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Note: 1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and
location of these bits are compatible with previous versions of the timer.
15.10.3 TCCR1B – Timer/Counter1 Control Register B
15.10.4 TCCR3B – Timer/Counter3 Control Register B
• Bit 7 – ICNCn: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is
activated, the input from the Input Capture Pin (ICPn) is filtered. The filter function requires four
successive equal valued samples of the ICPn pin for changing its output. The input capture is
therefore delayed by four Oscillator cycles when the noise canceler is enabled.
• Bit 6 – ICESn: Input Capture Edge Select
This bit selects which edge on the Input Capture Pin (ICPn) that is used to trigger a capture
event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICESn bit is written to one, a rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICESn setting, the counter value is copied into the
Input Capture Register (ICRn). The event will also set the Input Capture Flag (ICFn), and this
can be used to cause an Input Capture Interrupt, if this interrupt is enabled.
When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the
TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the input capture
function is disabled.
• Bit 5 – Reserved bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be
written to zero when TCCRnB is written.
• Bit 4:3 – WGMn3:2: Waveform Generation mode
See TCCRnA Register description.
11 1 0 1 1 PWM, phase correct OCRnA TOP BOTTOM
12 1 1 0 0 CTC ICRn Immediate MAX
13 1 1 0 1 (Reserved) – – –
14 1 1 1 0 Fast PWM ICRn TOP TOP
15 1 1 1 1 Fast PWM OCRnA TOP TOP
Table 15-4. Waveform Generation mode bit description (1). (Continued)
Mode WGMn3
WGMn2
(CTCn)
WGMn1
(PWMn1)
WGMn0
(PWMn0)
Timer/Counter mode of
operation TOP
Update of
OCRnx at
TOVn flag
set on
Bit 7 6 5 4 3 2 1 0
ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B
Read/write R/W R/W R R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ICNC3 ICES3 – WGM33 WGM32 CS32 CS31 CS30 TCCR3B
Read/write R/W R/W R R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0140
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• Bit 2:0 – CSn2:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter, see Figure
14-8 on page 107 and Figure 14-9 on page 108.
If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
15.10.5 TCCR1C – Timer/Counter1 Control Register C
15.10.6 TCCR3C – Timer/Counter3 Control Register C
• Bit 7 – FOCnA: Force Output Compare for Channel A
• Bit 6 – FOCnB: Force Output Compare for Channel B
• Bit 5 – FOCnC: Force Output Compare for Channel C
The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM
mode. When writing a logical one to the FOCnA/FOCnB/FOCnC bit, an immediate compare
match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed
according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are implemented
as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the
effect of the forced compare.
A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in Clear
Timer on Compare Match (CTC) mode using OCRnA as TOP.
The FOCnA/FOCnB/FOCnB bits are always read as zero.
• Bit 4:0 – Reserved bits
These bits are reserved for future use. For ensuring compatibility with future devices, these bits
must be written to zero when TCCRnC is written.
Table 15-5. Clock Select bit description.
CSn2 CSn1 CSn0 Description
0 0 0 No clock source. (Timer/Counter stopped)
0 0 1 clkI/O/1 (no prescaling
0 1 0 clkI/O/8 (from prescaler)
0 1 1 clkI/O/64 (from prescaler)
1 0 0 clkI/O/256 (from prescaler)
1 0 1 clkI/O/1024 (from prescaler)
1 1 0 External clock source on Tn pin. Clock on falling edge
1 1 1 External clock source on Tn pin. Clock on rising edge
Bit 7 6 5 4 3 2 1 0
FOC1A FOC1B FOC1C – – – – – TCCR1C
Read/write W W W R R R R R
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
FOC3A FOC3B FOC3C – – – – – TCCR3C
Read/write W W W R R R R R
Initial value 0 0 0 0 0 0 0 0141
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15.10.7 TCNT1H and TCNT1L – Timer/Counter1
15.10.8 TCNT3H and TCNT3L – Timer/Counter3
The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit
registers” on page 117.
Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a compare
match between TCNTn and one of the OCRnx Registers.
Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock
for all compare units.
15.10.9 OCR1AH and OCR1AL – Output Compare Register 1 A
15.10.10 OCR1BH and OCR1BL – Output Compare Register 1 B
15.10.11 OCR1CH and OCR1CL – Output Compare Register 1 C
Bit 7 6 5 4 3 2 1 0
TCNT1[15:8] TCNT1H
TCNT1[7:0] TCNT1L
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
TCNT3[15:8] TCNT3H
TCNT3[7:0] TCNT3L
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OCR1A[15:8] OCR1AH
OCR1A[7:0] OCR1AL
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OCR1B[15:8] OCR1BH
OCR1B[7:0] OCR1BL
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OCR1C[15:8] OCR1CH
OCR1C[7:0] OCR1CL
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0142
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15.10.12 OCR3AH and OCR3AL – Output Compare Register 3 A
15.10.13 OCR3BH and OCR3BL – Output Compare Register 3 B
15.10.14 OCR3CH and OCR3CL – Output Compare Register 3 C
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNTn). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OCnx pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other
16-bit registers. See “Accessing 16-bit registers” on page 117.
15.10.15 ICR1H and ICR1L – Input Capture Register 1
15.10.16 ICR3H and ICR3L – Input Capture Register 3
The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the
ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers. See “Accessing 16-bit registers” on page 117.
Bit 7 6 5 4 3 2 1 0
OCR3A[15:8] OCR3AH
OCR3A[7:0] OCR3AL
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OCR3B[15:8] OCR3BH
OCR3B[7:0] OCR3BL
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OCR3C[15:8] OCR3CH
OCR3C[7:0] OCR3CL
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ICR1[15:8] ICR1H
ICR1[7:0] ICR1L
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ICR3[15:8] ICR3H
ICR3[7:0] ICR3L
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0143
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15.10.17 TIMSK1 – Timer/Counter1 Interrupt Mask Register
15.10.18 TIMSK3 – Timer/Counter3 Interrupt Mask Register
• Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt
Vector (see “Interrupts” on page 68) is executed when the ICFn Flag, located in TIFRn, is set.
• Bit 3 – OCIEnC: Timer/Countern, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 68) is executed when the OCFnC Flag, located in
TIFRn, is set.
• Bit 2 – OCIEnB: Timer/Countern, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 68) is executed when the OCFnB Flag, located in
TIFRn, is set.
• Bit 1 – OCIEnA: Timer/Countern, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 68) is executed when the OCFnA Flag, located in
TIFRn, is set.
• Bit 0 – TOIEn: Timer/Countern, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Overflow interrupt is enabled. The corresponding Interrupt Vector
(see “Interrupts” on page 68) is executed when the TOVn Flag, located in TIFRn, is set.
15.10.19 TIFR1 – Timer/Counter1 Interrupt Flag Register
15.10.20 TIFR3 – Timer/Counter3 Interrupt Flag Register
Bit 7 6 5 4 3 2 1 0
– – ICIE1 – OCIE1C OCIE1B OCIE1A TOIE1 TIMSK1
Read/write R R R/W R R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
– – ICIE3 – OCIE3C OCIE3B OCIE3A TOIE3 TIMSK3
Read/write R R R/W R R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
– – ICF1 – OCF1C OCF1B OCF1A TOV1 TIFR1
Read/write R R R/W R R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
– – ICF3 – OCF3C OCF3B OCF3A TOV3 TIFR3
Read/write R R R/W R R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0144
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• Bit 5 – ICFn: Timer/Countern, Input Capture Flag
This flag is set when a capture event occurs on the ICPn pin. When the Input Capture Register
(ICRn) is set by the WGMn3:0 to be used as the TOP value, the ICFn Flag is set when the counter
reaches the TOP value.
ICFn is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,
ICFn can be cleared by writing a logic one to its bit location.
• Bit 3– OCFnC: Timer/Countern, Output Compare C Match Flag
This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output
Compare Register C (OCRnC).
Note that a Forced Output Compare (FOCnC) strobe will not set the OCFnC Flag.
OCFnC is automatically cleared when the Output Compare Match C Interrupt Vector is executed.
Alternatively, OCFnC can be cleared by writing a logic one to its bit location.
• Bit 2 – OCFnB: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output
Compare Register B (OCRnB).
Note that a Forced Output Compare (FOCnB) strobe will not set the OCFnB Flag.
OCFnB is automatically cleared when the Output Compare Match B Interrupt Vector is executed.
Alternatively, OCFnB can be cleared by writing a logic one to its bit location.
• Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNTn value matches the Output Compare
Register A (OCRnA).
Note that a Forced Output Compare (FOCnA) strobe will not set the OCFnA Flag.
OCFnA is automatically cleared when the Output Compare Match A Interrupt Vector is executed.
Alternatively, OCFnA can be cleared by writing a logic one to its bit location.
• Bit 0 – TOVn: Timer/Countern, Overflow Flag
The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes,
the TOVn Flag is set when the timer overflows. Refer to Table 15-4 on page 138 for the TOVn
Flag behavior when using another WGMn3:0 bit setting.
TOVn is automatically cleared when the Timer/Countern Overflow Interrupt Vector is executed.
Alternatively, TOVn can be cleared by writing a logic one to its bit location.145
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16. 8-bit Timer/Counter2 with PWM and asynchronous operation
Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main
features are:
• Single channel counter
• Clear timer on compare match (auto reload)
• Glitch-free, phase correct pulse width modulator (PWM)
• Frequency generator
• 10-bit clock prescaler
• Overflow and compare match interrupt sources (TOV2, OCF2A and OCF2B)
• Allows clocking from external 32kHz watch crystal independent of the I/O clock
16.1 Overview
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 16-1. For the actual
placement of I/O pins, see “Pin configurations” on page 3. CPU accessible I/O Registers, including
I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations
are listed in the “8-bit Timer/Counter register description” on page 156.
The Power Reduction Timer/Counter2 bit, PRTIM2, in “PRR0 – Power Reduction Register 0” on
page 54 must be written to zero to enable Timer/Counter2 module.
Figure 16-1. 8-bit Timer/Counter, block diagram.
Timer/counter
DATA BUS
OCRnA
OCRnB
=
=
TCNTn
Waveform
generation
Waveform
generation
OCnA
OCnB
=
Fixed
TOP
value
Control logic
= 0
TOP BOTTOM
Count
Clear
Direction
TOVn
(int.req.)
OCnA
(int.req.)
OCnB
(int.req.)
TCCRnA TCCRnB
clkTn
ASSRn
Synchronization unit
Prescaler
T/C oscillator
clkI/O
clkASY
asynchronous mode
select (ASn)
Synchronized status flags
TOSC1
TOSC2
Status flags
clkI/O146
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16.1.1 Registers
The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit registers.
Interrupt request (abbreviated to Int.Req.) signals are all visible in the Timer Interrupt Flag
Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register
(TIMSK2). TIFR2 and TIMSK2 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from
the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by
the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock
source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive
when no clock source is selected. The output from the Clock Select logic is referred to as the
timer clock (clkT2).
The double buffered Output Compare Register (OCR2A and OCR2B) are compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator
to generate a PWM or variable frequency output on the Output Compare pins (OC2A and
OC2B). See “Output Compare unit” on page 147. for details. The compare match event will also
set the Compare Flag (OCF2A or OCF2B) which can be used to generate an Output Compare
interrupt request.
16.1.2 Definitions
Many register and bit references in this document are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 2. However, when using the register or bit
defines in a program, the precise form must be used, that is, TCNT2 for accessing
Timer/Counter2 counter value and so on.
The definitions in the table below are also used extensively throughout the section.
16.2 Timer/Counter clock sources
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous
clock source. The clock source clkT2 is by default equal to the MCU clock, clkI/O. When the AS2
bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter
Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see “ASSR
– Asynchronous Status Register” on page 161. For details on clock sources and prescaler, see
“Timer/Counter prescaler” on page 164.
16.3 Counter unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure
16-2 on page 147 shows a block diagram of the counter and its surrounding environment.
BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00).
MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR2A Register. The assignment is dependent
on the mode of operation.147
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Figure 16-2. Counter unit block diagram.
Signal description (internal signals):
count Increment or decrement TCNT2 by 1.
direction Selects between increment and decrement.
clear Clear TCNT2 (set all bits to zero).
clkTn Timer/Counter clock, referred to as clkT2 in the following.
top Signalizes that TCNT2 has reached maximum value.
bottom Signalizes that TCNT2 has reached minimum value (zero).
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clkT2). clkT2 can be generated from an external or internal clock source,
selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the
timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of
whether clkT2 is present or not. A CPU write overrides (has priority over) all counter clear or
count operations.
The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in
the Timer/Counter Control Register (TCCR2A) and the WGM22 located in the Timer/Counter
Control Register B (TCCR2B). There are close connections between how the counter behaves
(counts) and how waveforms are generated on the Output Compare outputs OC2A and OC2B.
For more details about advanced counting sequences and waveform generation, see “Modes of
operation” on page 150.
The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by
the WGM22:0 bits. TOV2 can be used for generating a CPU interrupt.
16.4 Output Compare unit
The 8-bit comparator continuously compares TCNT2 with the Output Compare Register
(OCR2A and OCR2B). Whenever TCNT2 equals OCR2A or OCR2B, the comparator signals a
match. A match will set the Output Compare Flag (OCF2A or OCF2B) at the next timer clock
cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output
Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is executed.
Alternatively, the Output Compare Flag can be cleared by software by writing a logical
one to its I/O bit location. The Waveform Generator uses the match signal to generate an output
according to operating mode set by the WGM22:0 bits and Compare Output mode (COM2x1:0)
bits. The max and bottom signals are used by the Waveform Generator for handling the special
cases of the extreme values in some modes of operation (“Modes of operation” on page 150).
Figure 15-10 on page 134 shows a block diagram of the Output Compare unit.
DATA BUS
TCNTn Control logic
count
TOVn
(int.req.)
bottom top
direction
clear
TOSC1
T/C
oscillator
TOSC2
Prescaler
clkI/O
clk Tn148
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Figure 16-3. Output Compare unit, block diagram.
The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM)
modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double
buffering is disabled. The double buffering synchronizes the update of the OCR2x Compare
Register to either top or bottom of the counting sequence. The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR2x Register access may seem complex, but this is not case. When the double buffering
is enabled, the CPU has access to the OCR2x Buffer Register, and if double buffering is disabled
the CPU will access the OCR2x directly.
16.4.1 Force output compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOC2x) bit. Forcing compare match will not set the
OCF2x Flag or reload/clear the timer, but the OC2x pin will be updated as if a real compare
match had occurred (the COM2x1:0 bits settings define whether the OC2x pin is set, cleared or
toggled).
16.4.2 Compare Match Blocking by TCNT2 Write
All CPU write operations to the TCNT2 Register will block any compare match that occurs in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR2x to be initialized
to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is
enabled.
16.4.3 Using the Output Compare unit
Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNT2 when using the Output Compare channel,
independently of whether the Timer/Counter is running or not. If the value written to TCNT2
equals the OCR2x value, the compare match will be missed, resulting in incorrect waveform
generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is
downcounting.
OCFnx (int.req.)
= (8-bit comparator)
OCRnx
OCnx
DATA BUS
TCNTn
WGMn1:0
Waveform generator
top
FOCn
COMnX1:0
bottom149
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The setup of the OC2x should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OC2x value is to use the Force Output Compare
(FOC2x) strobe bit in Normal mode. The OC2x Register keeps its value even when
changing between Waveform Generation modes.
Be aware that the COM2x1:0 bits are not double buffered together with the compare value.
Changing the COM2x1:0 bits will take effect immediately.
16.5 Compare Match Output unit
The Compare Output mode (COM2x1:0) bits have two functions. The Waveform Generator uses
the COM2x1:0 bits for defining the Output Compare (OC2x) state at the next compare match.
Also, the COM2x1:0 bits control the OC2x pin output source. Figure 16-4 shows a simplified
schematic of the logic affected by the COM2x1:0 bit setting. The I/O Registers, I/O bits, and I/O
pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers
(DDR and PORT) that are affected by the COM2x1:0 bits are shown. When referring to the
OC2x state, the reference is for the internal OC2x Register, not the OC2x pin.
Figure 16-4. Compare Match Output unit, schematic.
The general I/O port function is overridden by the Output Compare (OC2x) from the Waveform
Generator if either of the COM2x1:0 bits are set. However, the OC2x pin direction (input or output)
is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OC2x pin (DDR_OC2x) must be set as output before the OC2x value is visible
on the pin. The port override function is independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC2x state before the output
is enabled. Note that some COM2x1:0 bit settings are reserved for certain modes of
operation. See “8-bit Timer/Counter register description” on page 156.
PORT
DDR
D Q
D Q
OCnx
OCnx pin
D Q Waveform
generator
COMnx1
COMnx0
0
1
DATA BU
S
FOCnx
clkI/O150
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16.5.1 Compare Output mode and Waveform generating
The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes.
For all modes, setting the COM2x1:0 = 0 tells the Waveform Generator that no action on the
OC2x Register is to be performed on the next compare match. For compare output actions in the
non-PWM modes refer to Table 16-4 on page 157. For fast PWM mode, refer to Table 16-5 on
page 158, and for phase correct PWM refer to Table 16-6 on page 158.
A change of the COM2x1:0 bits state will have effect at the first compare match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOC2x strobe bits.
16.6 Modes of operation
The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins,
is defined by the combination of the Waveform Generation mode (WGM22:0) and Compare Output
mode (COM2x1:0) bits. The Compare Output mode bits do not affect the counting sequence,
while the Waveform Generation mode bits do. The COM2x1:0 bits control whether the PWM output
generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes
the COM2x1:0 bits control whether the output should be set, cleared, or toggled at a compare
match (see “Compare Match Output unit” on page 149).
For detailed timing information refer to Section “Timer/Counter timing diagrams” on page 154.
16.6.1 Normal mode
The simplest mode of operation is the Normal mode (WGM22:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom
(0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same
timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case behaves like a ninth
bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV2 Flag, the timer resolution can be increased by software.
There are no special cases to consider in the Normal mode, a new counter value can be written
anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the Output
Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
16.6.2 Clear Timer on Compare Match (CTC) mode
In Clear Timer on Compare or CTC mode (WGM22:0 = 2), the OCR2A Register is used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter
value (TCNT2) matches the OCR2A. The OCR2A defines the top value for the counter, hence
also its resolution. This mode allows greater control of the compare match output frequency. It
also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Table 16-5 on page 151. The counter value
(TCNT2) increases until a compare match occurs between TCNT2 and OCR2A, and then counter
(TCNT2) is cleared.151
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Figure 16-5. CTC mode, timing diagram.
An interrupt can be generated each time the counter value reaches the TOP value by using the
OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating
the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running
with none or a low prescaler value must be done with care since the CTC mode does not
have the double buffering feature. If the new value written to OCR2A is lower than the current
value of TCNT2, the counter will miss the compare match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can
occur.
For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical
level on each compare match by setting the Compare Output mode bits to toggle mode
(COM2A1:0 = 1). The OC2A value will not be visible on the port pin unless the data direction for
the pin is set to output. The waveform generated will have a maximum frequency of fOC2A =
fclk_I/O/2 when OCR2A is set to zero (0x00). The waveform frequency is defined by the following
equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the
counter counts from MAX to 0x00.
16.6.3 Fast PWM mode
The fast Pulse Width Modulation or fast PWM mode (WGM22:0 = 3 or 7) provides a high frequency
PWM waveform generation option. The fast PWM differs from the other PWM option by
its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM.
TOP is defined as 0xFF when WGM22:0 = 3, and OCR2A when MGM22:0 = 7. In noninverting
Compare Output mode, the Output Compare (OC2x) is cleared on the compare match
between TCNT2 and OCR2x, and set at BOTTOM. In inverting Compare Output mode, the output
is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the
operating frequency of the fast PWM mode can be twice as high as the phase correct PWM
mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited
for power regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), and therefore reduces total system cost.
TCNTn
OCnx
(Toggle)
OCnx Interrupt Flag Set
Period 1 2 3 4
(COMnx1:0 = 1)
f
OCnx
f
clk_I/O
2 ⋅ ⋅ N ( ) 1 + OCRnx = -------------------------------------------------152
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In fast PWM mode, the counter is incremented until the counter value matches the TOP value.
The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
PWM mode is shown in Figure 16-6. The TCNT2 value is in the timing diagram shown as a histogram
for illustrating the single-slope operation. The diagram includes non-inverted and
inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare
matches between OCR2x and TCNT2.
Figure 16-6. Fast PWM mode, timing diagram.
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches TOP. If the interrupt
is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin.
Setting the COM2x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output
can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3,
and OCR2A when WGM2:0 = 7 (See Table 16-2 on page 157). The actual OC2x value will only
be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform
is generated by setting (or clearing) the OC2x Register at the compare match between
OCR2x and TCNT2, and clearing (or setting) the OC2x Register at the timer clock cycle the
counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will
be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result
in a constantly high or low output (depending on the polarity of the output set by the COM2A1:0
bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting
OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The waveform
TCNTn
OCRnx Update and
TOVn Interrupt Flag Set
Period 1 2 3
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCRnx Interrupt Flag Set
4 5 6 7
f
OCnxPWM
f
clk_I/O
N ⋅ 256 = ------------------153
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generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2A is set to zero. This feature
is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output
Compare unit is enabled in the fast PWM mode.
16.6.4 Phase correct PWM mode
The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phase correct
PWM waveform generation option. The phase correct PWM mode is based on a dual-slope
operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM.
TOP is defined as 0xFF when WGM22:0 = 1, and OCR2A when MGM22:0 = 5. In noninverting
Compare Output mode, the Output Compare (OC2x) is cleared on the compare match
between TCNT2 and OCR2x while upcounting, and set on the compare match while downcounting.
In inverting Output Compare mode, the operation is inverted. The dual-slope operation has
lower maximum operation frequency than single slope operation. However, due to the symmetric
feature of the dual-slope PWM modes, these modes are preferred for motor control
applications.
In phase correct PWM mode the counter is incremented until the counter value matches TOP.
When the counter reaches TOP, it changes the count direction. The TCNT2 value will be equal
to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown
on Figure 16-7. The TCNT2 value is in the timing diagram shown as a histogram for illustrating
the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The
small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x
and TCNT2.
Figure 16-7. Phase correct PWM mode, timing diagram.
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The
Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM
value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM
TOVn Interrupt Flag Set
OCnx Interrupt Flag Set
1 2 3
TCNTn
Period
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCRnx update154
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output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when
WGM2:0 = 3, and OCR2A when MGM2:0 = 7 (see Table 16-3 on page 157). The actual OC2x
value will only be visible on the port pin if the data direction for the port pin is set as output. The
PWM waveform is generated by clearing (or setting) the OC2x Register at the compare match
between OCR2x and TCNT2 when the counter increments, and setting (or clearing) the OC2x
Register at compare match between OCR2x and TCNT2 when the counter decrements. The
PWM frequency for the output when using phase correct PWM can be calculated by the following
equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in Figure 16-7 on page 153 OCnx has a transition from high to low
even though there is no Compare Match. The point of this transition is to guarantee symmetry
around BOTTOM. There are two cases that give a transition without Compare Match.
• OCR2A changes its value from MAX, like in Figure 16-7 on page 153. When the OCR2A
value is MAX the OCn pin value is the same as the result of a down-counting compare match.
To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result
of an up-counting Compare Match
• The timer starts counting from a value higher than the one in OCR2A, and for that reason
misses the Compare Match and hence the OCn change that would have happened on the
way up
16.7 Timer/Counter timing diagrams
The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT2)
is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should be replaced by
the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are
set. Figure 16-8 contains timing data for basic Timer/Counter operation. The figure shows the
count sequence close to the MAX value in all modes other than phase correct PWM mode.
Figure 16-8. Timer/Counter timing diagram, no prescaling.
f
OCnxPCPWM
f
clk_I/O
N ⋅ 510 = ------------------
clkTn
(clkI/O/1)
TOVn
clkI/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1155
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Figure 16-9 shows the same timing data, but with the prescaler enabled.
Figure 16-9. Timer/Counter timing diagram, with prescaler (fclk_I/O/8).
Figure 16-10 shows the setting of OCF2A in all modes except CTC mode.
Figure 16-10. Timer/Counter timing diagram, setting of OCF2A, with prescaler (fclk_I/O/8).
Figure 16-11 on page 156 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode.
TOVn
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
clkI/O
clkTn
(clkI/O/8)
OCFnx
OCRnx
TCNTn
OCRnx value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clkI/O
clkTn
(clkI/O/8)156
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Figure 16-11. Timer/Counter timing diagram, clear timer on compare match mode, with prescaler
(fclk_I/O/8).
16.8 8-bit Timer/Counter register description
16.8.1 TCCR2A – Timer/Counter Control Register A
• Bits 7:6 – COM2A1:0: Compare Match Output A mode
These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0
bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2A pin
must be set in order to enable the output driver.
When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the
WGM22:0 bit setting. Table 16-1 shows the COM2A1:0 bit functionality when the WGM22:0 bits
are set to a normal or CTC mode (non-PWM).
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1 TOP BOTTOM BOTTOM + 1
clkI/O
clkTn
(clkI/O/8)
Bit 7 6 5 4 3 2 1 0
COM2A1 COM2A0 COM2B1 COM2B0 – – WGM21 WGM20 TCCR2A
Read/write R/W R/W R/W R/W R R R/W R/W
Initial value 0 0 0 0 0 0 0 0
Table 16-1. Compare output mode, non-PWM mode.
COM2A1 COM2A0 Description
0 0 Normal port operation, OC2A disconnected
0 1 Toggle OC2A on Compare Match
1 0 Clear OC2A on Compare Match
1 1 Set OC2A on Compare Match157
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Table 16-2 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM
mode.
Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Compare
Match is ignored, but the set or clear is done at TOP. See “Fast PWM mode” on page 151
for more details.
Table 16-3 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase correct
PWM mode.
Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Compare
Match is ignored, but the set or clear is done at TOP. See “Phase correct PWM mode” on
page 153 for more details.
• Bits 5:4 – COM2B1:0: Compare Match Output B mode
These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0
bits are set, the OC2B output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2B pin
must be set in order to enable the output driver.
When OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the
WGM22:0 bit setting. Table 16-4 shows the COM2B1:0 bit functionality when the WGM22:0 bits
are set to a normal or CTC mode (non-PWM).
Table 16-2. Compare Output mode, fast PWM mode (1).
COM2A1 COM2A0 Description
0 0 Normal port operation, OC2A disconnected
0 1 WGM22 = 0: Normal Port Operation, OC0A Disconnected.
WGM22 = 1: Toggle OC2A on Compare Match.
1 0 Clear OC2A on Compare Match, set OC2A at TOP
1 1 Set OC2A on Compare Match, clear OC2A at TOP
Table 16-3. Compare Output mode, phase correct PWM mode (1).
COM2A1 COM2A0 Description
0 0 Normal port operation, OC2A disconnected
0 1 WGM22 = 0: Normal Port Operation, OC2A Disconnected.
WGM22 = 1: Toggle OC2A on Compare Match.
1 0 Clear OC2A on Compare Match when up-counting. Set OC2A on Compare
Match when down-counting.
1 1 Set OC2A on Compare Match when up-counting. Clear OC2A on Compare
Match when down-counting.
Table 16-4. Compare Output mode, non-PWM mode.
COM2B1 COM2B0 Description
0 0 Normal port operation, OC2B disconnected
0 1 Toggle OC2B on Compare Match
1 0 Clear OC2B on Compare Match
1 1 Set OC2B on Compare Match158
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Table 16-5 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to fast PWM
mode.
Note: 1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Compare
Match is ignored, but the set or clear is done at TOP. See “Fast PWM mode” on page 151
for more details.
Table 16-6 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase correct
PWM mode.
Note: 1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Compare
Match is ignored, but the set or clear is done at TOP. See “Phase correct PWM mode” on
page 153 for more details.
• Bits 3, 2 – Res: Reserved bits
These bits are reserved bits in the Atmel AT90USB64/128 and will always read as zero.
• Bits 1:0 – WGM21:0: Waveform Generation mode
Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform
generation to be used, see Table 16-7. Modes of operation supported by the Timer/Counter
unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of
Pulse Width Modulation (PWM) modes (see “Modes of operation” on page 150).
Table 16-5. Compare Output mode, fast PWM mode (1).
COM2B1 COM2B0 Description
0 0 Normal port operation, OC2B disconnected.
0 1 Reserved
1 0 Clear OC2B on Compare Match, set OC2B at TOP
1 1 Set OC2B on Compare Match, clear OC2B at TOP
Table 16-6. Compare Output mode, phase correct PWM mode (1).
COM2B1 COM2B0 Description
0 0 Normal port operation, OC2B disconnected
0 1 Reserved
1 0 Clear OC2B on Compare Match when up-counting. Set OC2B on Compare
Match when down-counting
1 1 Set OC2B on Compare Match when up-counting. Clear OC2B on Compare
Match when down-counting
Table 16-7. Waveform Generation mode bit description.
Mode WGM2 WGM1 WGM0
Timer/Counter
mode of operation TOP
Update of
OCRx at
TOV flag
set on (1)(2)
0 0 0 0 Normal 0xFF Immediate MAX
1 0 0 1 PWM, phase correct 0xFF TOP BOTTOM
2 0 1 0 CTC OCRA Immediate MAX
3 0 1 1 Fast PWM 0xFF TOP MAX
4 1 0 0 Reserved – – –159
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Notes: 1. MAX= 0xFF
2. BOTTOM= 0x00
16.8.2 TCCR2B – Timer/Counter Control Register B
• Bit 7 – FOC2A: Force Output Compare A
The FOC2A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2A bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OC2A output is
changed according to its COM2A1:0 bits setting. Note that the FOC2A bit is implemented as a
strobe. Therefore it is the value present in the COM2A1:0 bits that determines the effect of the
forced compare.
A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR2A as TOP.
The FOC2A bit is always read as zero.
• Bit 6 – FOC2B: Force Output Compare B
The FOC2B bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2B bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OC2B output is
changed according to its COM2B1:0 bits setting. Note that the FOC2B bit is implemented as a
strobe. Therefore it is the value present in the COM2B1:0 bits that determines the effect of the
forced compare.
A FOC2B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR2B as TOP.
The FOC2B bit is always read as zero.
• Bits 5:4 – Res: Reserved bits
These bits are reserved bits in the AT90USB64/128 and will always read as zero.
• Bit 3 – WGM22: Waveform Generation mode
See the description in the “TCCR2A – Timer/Counter Control Register A” on page 156.
5 1 0 1 PWM, phase correct OCRA TOP BOTTOM
6 1 1 0 Reserved – – –
7 1 1 1 Fast PWM OCRA TOP TOP
Table 16-7. Waveform Generation mode bit description. (Continued)
Mode WGM2 WGM1 WGM0
Timer/Counter
mode of operation TOP
Update of
OCRx at
TOV flag
set on (1)(2)
Bit 7 6 5 4 3 2 1 0
FOC2A FOC2B – – WGM22 CS22 CS21 CS20 TCCR2B
Read/write W W R R R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0160
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• Bit 2:0 – CS22:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table
16-8.
16.8.3 TCNT2 – Timer/Counter Register
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare
Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running,
introduces a risk of missing a Compare Match between TCNT2 and the OCR2x Registers.
16.8.4 OCR2A – Output Compare Register A
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC2A pin.
16.8.5 OCR2B – Output Compare Register B
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC2B pin.
Table 16-8. Clock Select bit description.
CS22 CS21 CS20 Description
0 0 0 No clock source (Timer/Counter stopped)
0 0 1 clkT2S/(no prescaling)
0 1 0 clkT2S/8 (from prescaler)
0 1 1 clkT2S/32 (from prescaler)
1 0 0 clkT2S/64 (from prescaler)
1 0 1 clkT2S/128 (from prescaler)
1 1 0 clkT2S/256 (from prescaler)
1 1 1 clkT2S/1024 (from prescaler)
Bit 7 6 5 4 3 2 1 0
TCNT2[7:0] TCNT2
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OCR2A[7:0] OCR2A
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OCR2B[7:0] OCR2B
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0161
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16.9 Asynchronous operation of the Timer/Counter
16.9.1 ASSR – Asynchronous Status Register
• Bit 6 – EXCLK: Enable External Clock Input
When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer
is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a
32 kHz crystal. Writing to EXCLK should be done before asynchronous operation is selected.
Note that the crystal Oscillator will only run when this bit is zero.
• Bit 5 – AS2: Asynchronous Timer/Counter2
When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is
written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscillator
1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A,
OCR2B, TCCR2A and TCCR2B might be corrupted.
• Bit 4 – TCN2UB: Timer/Counter2 Update Busy
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set.
When TCNT2 has been updated from the temporary storage register, this bit is cleared by hardware.
A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value.
• Bit 3 – OCR2AUB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set.
When OCR2A has been updated from the temporary storage register, this bit is cleared by hardware.
A logical zero in this bit indicates that OCR2A is ready to be updated with a new value.
• Bit 2 – OCR2BUB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set.
When OCR2B has been updated from the temporary storage register, this bit is cleared by hardware.
A logical zero in this bit indicates that OCR2B is ready to be updated with a new value.
• Bit 1 – TCR2AUB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set.
When TCCR2A has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new
value.
• Bit 0 – TCR2BUB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes set.
When TCCR2B has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that TCCR2B is ready to be updated with a new
value.
If a write is performed to any of the five Timer/Counter2 Registers while its update busy flag is
set, the updated value might get corrupted and cause an unintentional interrupt to occur.
Bit 7 6 5 4 3 2 1 0
– EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB ASSR
Read/write R R/W R/W R R R R R
Initial value 0 0 0 0 0 0 0 0162
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The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different.
When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A
and TCCR2B the value in the temporary storage register is read.
16.9.2 Asynchronous operation of Timer/Counter2
When Timer/Counter2 operates asynchronously, some considerations must be taken.
• Warning: When switching between asynchronous and synchronous clocking of
Timer/Counter2, the Timer Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A
safe procedure for switching clock source is:
a. Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2.
b. Select clock source by setting AS2 as appropriate.
c. Write new values to TCNT2, OCR2x, and TCCR2x.
d. To switch to asynchronous operation: Wait for TCN2UB, OCR2xUB, and TCR2xUB.
e. Clear the Timer/Counter2 Interrupt Flags.
f. Enable interrupts, if needed.
• The CPU main clock frequency must be more than four times the Oscillator frequency
• When writing to one of the registers TCNT2, OCR2x, or TCCR2x, the value is transferred to a
temporary register, and latched after two positive edges on TOSC1. The user should not
write a new value before the contents of the temporary register have been transferred to its
destination. Each of the five mentioned registers have their individual temporary register,
which means that, for example, writing to TCNT2 does not disturb an OCR2x write in
progress. To detect that a transfer to the destination register has taken place, the
Asynchronous Status Register – ASSR has been implemented
• When entering Power-save or ADC Noise Reduction mode after having written to TCNT2,
OCR2x, or TCCR2x, the user must wait until the written register has been updated if
Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode
before the changes are effective. This is particularly important if any of the Output Compare2
interrupt is used to wake up the device, since the Output Compare function is disabled during
writing to OCR2x or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode
before the corresponding OCR2xUB bit returns to zero, the device will never receive a
compare match interrupt, and the MCU will not wake up
• If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise Reduction
mode, precautions must be taken if the user wants to re-enter one of these modes: The
interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and reentering
sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the
device will fail to wake up. If the user is in doubt whether the time before re-entering Powersave
or ADC Noise Reduction mode is sufficient, the following algorithm can be used to
ensure that one TOSC1 cycle has elapsed:
a. Write a value to TCCR2x, TCNT2, or OCR2x.
b. Wait until the corresponding Update Busy Flag in ASSR returns to zero.
c. Enter Power-save or ADC Noise Reduction mode.
• When the asynchronous operation is selected, the 32.768kHz Oscillator for Timer/Counter2
is always running, except in Power-down and Standby modes. After a Power-up Reset or
wake-up from Power-down or Standby mode, the user should be aware of the fact that this
Oscillator might take as long as one second to stabilize. The user is advised to wait for at
least one second before using Timer/Counter2 after power-up or wake-up from Power-down
or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after 163
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a wake-up from Power-down or Standby mode due to unstable clock signal upon start-up, no
matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin
• Description of wake up from Power-save or ADC Noise Reduction mode when the timer is
clocked asynchronously: When the interrupt condition is met, the wake up process is started
on the following cycle of the timer clock, that is, the timer is always advanced by at least one
before the processor can read the counter value. After wake-up, the MCU is halted for four
cycles, it executes the interrupt routine, and resumes execution from the instruction following
SLEEP
• Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect
result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be
done through a register synchronized to the internal I/O clock domain. Synchronization takes
place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O
clock (clkI/O) again becomes active, TCNT2 will read as the previous value (before entering
sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from
Power-save mode is essentially unpredictable, as it depends on the wake-up time. The
recommended procedure for reading TCNT2 is thus as follows:
a. Write any value to either of the registers OCR2x or TCCR2x.
b. Wait for the corresponding Update Busy Flag to be cleared.
c. Read TCNT2.
• During asynchronous operation, the synchronization of the Interrupt Flags for the
asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is therefore
advanced by at least one before the processor can read the timer value causing the setting of
the Interrupt Flag. The Output Compare pin is changed on the timer clock and is not
synchronized to the processor clock
16.9.3 TIMSK2 – Timer/Counter2 Interrupt Mask Register
• Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable
When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt is executed
if a compare match in Timer/Counter2 occurs, that is, when the OCF2B bit is set in the
Timer/Counter2 Interrupt Flag Register – TIFR2.
• Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable
When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a compare match in Timer/Counter2 occurs, that is, when the OCF2A bit is set in the
Timer/Counter2 Interrupt Flag Register – TIFR2.
• Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter2 occurs, that is, when the TOV2 bit is set in the Timer/Counter2 Interrupt
Flag Register – TIFR2.
Bit 7 6 5 4 3 2 1 0
– – – – – OCIE2B OCIE2A TOIE2 TIMSK2
Read/write R R R R R R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0164
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16.9.4 TIFR2 – Timer/Counter2 Interrupt Flag Register
• Bit 2 – OCF2B: Output Compare Flag 2 B
The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the
data in OCR2B – Output Compare Register2. OCF2B is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF2B is cleared by writing a logic
one to the flag. When the I-bit in SREG, OCIE2B (Timer/Counter2 Compare match Interrupt
Enable), and OCF2B are set (one), the Timer/Counter2 Compare match Interrupt is executed.
• Bit 1 – OCF2A: Output Compare Flag 2 A
The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the
data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic
one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 Compare match Interrupt
Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed.
• Bit 0 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared
by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Interrupt
Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In
PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00.
16.10 Timer/Counter prescaler
Figure 16-12. Prescaler for Timer/Counter2.
Bit 7 6 5 4 3 2 1 0
– – – – – OCF2B OCF2A TOV2 TIFR2
Read/write R R R R R R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
10-BIT T/C PRESCALER
TIMER/COUNTER2 CLOCK SOURCE
clkI/O clkT2S
TOSC1
AS2
CS20
CS21
CS22
clkT2S/8
clkT2S/64
clkT2S/128
clkT2S/1024
clkT2S/256
clkT2S/32
0 PSRASY
Clear
clkT2165
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The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main
system I/O clock clkIO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously
clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter
(RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can
then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock
source for Timer/Counter2. The Oscillator is optimized for use with a 32.768kHz crystal. Applying
an external clock source to TOSC1 is not recommended.
For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clkT2S/32, clkT2S/64,
clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected.
Setting the PSRASY bit in GTCCR resets the prescaler. This allows the user to operate with a
predictable prescaler.
16.10.1 GTCCR – General Timer/Counter Control Register
• Bit 1 – PSRASY: Prescaler Reset Timer/Counter2
When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared
immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous
mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by
hardware if the TSM bit is set. Refer to the description of the Section “GTCCR – General
Timer/Counter Control Register” on page 97 for a description of the Timer/Counter Synchronization
mode.
Bit 7 6 5 4 3 2 1 0
TSM – – – – – PSRASY
PSRSY
NC
GTCCR
Read/write R/W R R R R R R/W R/W
Initial value 0 0 0 0 0 0 0 0166
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17. Output Compare Modulator (OCM1C0A)
17.1 Overview
The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier
frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit
Timer/Counter1 and the Output Compare Unit of the 8-bit Timer/Counter0. For more details
about these Timer/Counters see “Timer/Counter0, Timer/Counter1, and Timer/Counter3 prescalers”
on page 96 and “8-bit Timer/Counter2 with PWM and asynchronous operation” on page
145.
Figure 17-1. Output Compare Modulator, block diagram.
When the modulator is enabled, the two output compare channels are modulated together as
shown in the block diagram (Figure 17-1).
17.2 Description
The Output Compare unit 1C and Output Compare unit 2 shares the PB7 port pin for output. The
outputs of the Output Compare units (OC1C and OC0A) overrides the normal PORTB7 Register
when one of them is enabled (that is, when COMnx1:0 is not equal to zero). When both OC1C
and OC0A are enabled at the same time, the modulator is automatically enabled.
The functional equivalent schematic of the modulator is shown on Figure 17-2. The schematic
includes part of the Timer/Counter units and the port B pin 7 output driver circuit.
Figure 17-2. Output Compare Modulator, schematic.
OC1C
Pin
OC1C /
OC0A / PB7
Timer/Counter 1
Timer/Counter 0 OC0A
PORTB7 DDRB7
D Q D Q
Pin
COMA01
COMA00
DATABUS
OC1C /
OC0A/ PB7
COM1C1
COM1C0
Modulator
1
0
OC1C
D Q
OC0A
D Q
(From Waveform generator)
(From Waveform generator)
0
1
Vcc167
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When the modulator is enabled the type of modulation (logical AND or OR) can be selected by
the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the
COMnx1:0 bit setting.
17.2.1 Timing example
Figure 17-3 illustrates the modulator in action. In this example the Timer/Counter1 is set to operate
in fast PWM mode (non-inverted) and Timer/Counter0 uses CTC waveform mode with toggle
Compare Output mode (COMnx1:0 = 1).
Figure 17-3. Output Compare Modulator, timing diagram.
In this example, Timer/Counter2 provides the carrier, while the modulating signal is generated
by the Output Compare unit C of the Timer/Counter1.
The resolution of the PWM signal (OC1C) is reduced by the modulation. The reduction factor is
equal to the number of system clock cycles of one period of the carrier (OC0A). In this example
the resolution is reduced by a factor of two. The reason for the reduction is illustrated in Figure
17-3 at the second and third period of the PB7 output when PORTB7 equals zero. The period 2
high time is one cycle longer than the period 3 high time, but the result on the PB7 output is
equal in both periods.
1 2
OC0A
(CTC mode)
OC1C
(FPWM mode)
PB7
(PORTB7 = 0)
PB7
(PORTB7 = 1)
(Period) 3
clk I/O168
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18. SPI – Serial Peripheral Interface
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
Atmel AT90USB64/128 and peripheral devices or between several AVR devices. The
AT90USB64/128 SPI includes the following features:
• Full-duplex, three-wire synchronous data transfer
• Master or slave operation
• LSB first or MSB first data transfer
• Seven programmable bit rates
• End of transmission interrupt flag
• Write collision flag protection
• Wake-up from Idle mode
• Double speed (CK/2) Master SPI mode
USART can also be used in Master SPI mode, see “USART in SPI mode” on page 202.
The Power Reduction SPI bit, PRSPI, in “PRR0 – Power Reduction Register 0” on page 54 must
be written to zero to enable SPI module.
Figure 18-1. SPI block diagram (1).
Note: 1. Refer to Figure 1-1 on page 3, and Table 11-6 on page 79 for SPI pin placement.
The interconnection between Master and Slave CPUs with SPI is shown in Figure 18-2 on page
169. The system consists of two shift Registers, and a Master clock generator. The SPI Master
initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. SPI2X SPI2X
DIVIDER
/2/4/8/16/32/64/128169
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Master and Slave prepare the data to be sent in their respective shift Registers, and the Master
generates the required clock pulses on the SCK line to interchange data. Data is always shifted
from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the
Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave
by pulling high the Slave Select, SS, line.
When configured as a Master, the SPI interface has no automatic control of the SS line. This
must be handled by user software before communication can start. When this is done, writing a
byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight
bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of
Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an
interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or
signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be
kept in the Buffer Register for later use.
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long
as the SS pin is driven high. In this state, software may update the contents of the SPI Data
Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin
until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission
Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt
is requested. The Slave may continue to place new data to be sent into SPDR before reading
the incoming data. The last incoming byte will be kept in the Buffer Register for later use.
Figure 18-2. SPI Master-slave interconnection.
The system is single buffered in the transmit direction and double buffered in the receive direction.
This means that bytes to be transmitted cannot be written to the SPI Data Register before
the entire shift cycle is completed. When receiving data, however, a received character must be
read from the SPI Data Register before the next character has been completely shifted in. Otherwise,
the first byte is lost.
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure
correct sampling of the clock signal, the frequency of the SPI clock should never exceed fosc/4.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden
according to Table 18-1 on page 170. For more details on automatic port overrides, refer to
“Alternate port functions” on page 76.
SHIFT
ENABLE170
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Note: 1. See “Alternate functions of Port B” on page 79 for a detailed description of how to define the
direction of the user defined SPI pins.
The following code examples show how to initialize the SPI as a Master and how to perform a
simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction
Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the
actual data direction bits for these pins. For example, if MOSI is placed on pin PB5, replace
DD_MOSI with DDB5 and DDR_SPI with DDRB.
Table 18-1. SPI pin overrides (1).
Pin Direction, master SPI Direction, slave SPI
MOSI User defined Input
MISO Input User defined
SCK User defined Input
SS User defined Input171
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Note: 1. See “About code examples” on page 10.
Assembly code example (1)
SPI_MasterInit:
; Set MOSI and SCK output, all others input
ldi r17,(1<>8);
UBRRLn = (unsigned char)baud;
/* Enable receiver and transmitter */
UCSRnB = (1<> 1) & 0x01;
return ((resh << 8) | resl);
}188
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The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer.
This flag is one when unread data exist in the receive buffer, and zero when the receive
buffer is empty (that is, does not contain any unread data). If the Receiver is disabled (RXENn =
0), the receive buffer will be flushed and consequently the RXCn bit will become zero.
When the Receive Complete Interrupt Enable (RXCIEn) in UCSRnB is set, the USART Receive
Complete interrupt will be executed as long as the RXCn Flag is set (provided that global interrupts
are enabled). When interrupt-driven data reception is used, the receive complete routine
must read the received data from UDRn in order to clear the RXCn Flag, otherwise a new interrupt
will occur once the interrupt routine terminates.
19.6.4 Receiver error flags
The USART Receiver has three error flags: Frame Error (FEn), Data OverRun (DORn) and Parity
Error (UPEn). All can be accessed by reading UCSRnA. Common for the Error Flags is that
they are located in the receive buffer together with the frame for which they indicate the error
status. Due to the buffering of the Error Flags, the UCSRnA must be read before the receive buffer
(UDRn), since reading the UDRn I/O location changes the buffer read location. Another
equality for the Error Flags is that they can not be altered by software doing a write to the flag
location. However, all flags must be set to zero when the UCSRnA is written for upward compatibility
of future USART implementations. None of the Error Flags can generate interrupts.
The Frame Error (FEn) Flag indicates the state of the first stop bit of the next readable frame
stored in the receive buffer. The FEn Flag is zero when the stop bit was correctly read (as one),
and the FEn Flag will be one when the stop bit was incorrect (zero). This flag can be used for
detecting out-of-sync conditions, detecting break conditions and protocol handling. The FEn
Flag is not affected by the setting of the USBSn bit in UCSRnC since the Receiver ignores all,
except for the first, stop bits. For compatibility with future devices, always set this bit to zero
when writing to UCSRnA.
The Data OverRun (DORn) Flag indicates data loss due to a receiver buffer full condition. A
Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting
in the Receive Shift Register, and a new start bit is detected. If the DORn Flag is set there
was one or more serial frame lost between the frame last read from UDRn, and the next frame
read from UDRn. For compatibility with future devices, always write this bit to zero when writing
to UCSRnA. The DORn Flag is cleared when the frame received was successfully moved from
the Shift Register to the receive buffer.
The Parity Error (UPEn) Flag indicates that the next frame in the receive buffer had a Parity
Error when received. If Parity Check is not enabled the UPEn bit will always be read zero. For
compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more
details see “Parity bit calculation” on page 181 and “Parity Checker” on page 188.
19.6.5 Parity Checker
The Parity Checker is active when the high USART Parity mode (UPMn1) bit is set. Type of Parity
Check to be performed (odd or even) is selected by the UPMn0 bit. When enabled, the Parity
Checker calculates the parity of the data bits in incoming frames and compares the result with
the parity bit from the serial frame. The result of the check is stored in the receive buffer together
with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software
to check if the frame had a Parity Error.189
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The UPEn bit is set if the next character that can be read from the receive buffer had a Parity
Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is
valid until the receive buffer (UDRn) is read.
19.6.6 Disabling the Receiver
In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing
receptions will therefore be lost. When disabled (that is, the RXENn is set to zero) the Receiver
will no longer override the normal function of the RxDn port pin. The Receiver buffer FIFO will be
flushed when the Receiver is disabled. Remaining data in the buffer will be lost
19.6.7 Flushing the receive buffer
The receiver buffer FIFO will be flushed when the Receiver is disabled, that is, the buffer will be
emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal
operation, due to for instance an error condition, read the UDRn I/O location until the RXCn Flag
is cleared. The following code example shows how to flush the receive buffer.
Note: 1. See “About code examples” on page 10.
19.7 Asynchronous data reception
The USART includes a clock recovery and a data recovery unit for handling asynchronous data
reception. The clock recovery logic is used for synchronizing the internally generated baud rate
clock to the incoming asynchronous serial frames at the RxDn pin. The data recovery logic samples
and low pass filters each incoming bit, thereby improving the noise immunity of the
Receiver. The asynchronous reception operational range depends on the accuracy of the internal
baud rate clock, the rate of the incoming frames, and the frame size in number of bits.
19.7.1 Asynchronous clock recovery
The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 19-5
on page 190 illustrates the sampling process of the start bit of an incoming frame. The sample
rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double Speed
mode. The horizontal arrows illustrate the synchronization variation due to the sampling process.
Note the larger time variation when using the Double Speed mode (U2Xn = 1) of
operation. Samples denoted zero are samples done when the RxDn line is idle (that is, no communication
activity).
Assembly code example (1)
USART_Flush:
sbis UCSRnA, RXCn
ret
in r16, UDRn
rjmp USART_Flush
C code example (1)
void USART_Flush( void )
{
unsigned char dummy;
while ( UCSRnA & (1<
USBE=1
ID=1
Clock stopped
FRZCLK=1
Macro off
USBE=0
USBE=0
Host
USBE=0
HW
RESET
USBE=1
ID=0
AT90USB647/1287 only
AT90USB646/1286 forced mode247
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22.4.3 Interrupts
Two interrupts vectors are assigned to USB interface.
Figure 22-10. USB interrupt system.
See Section 23.17, page 272 and Section 24.15, page 291 for more details on the Host and
Device interrupts.
USB general
& OTG interrupt
USB device
interrupt
USB host
interrupt
USB general
interrupt vector
Endpoint
interrupt
Pipe
interrupt
USB endpoint/pipe
interrupt vector248
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AT90USB64/128
Figure 22-11. USB general interrupt vector sources.
IDTE
USBCON.1
IDTI
USBINT.1
VBUSTI
USBINT.0 VBUSTE
USBCON.0
STOI
OTGINT.5 STOE
OTGIEN.5
HNPERRI
OTGINT.4 HNPERRE
OTGIEN.4
ROLEEXI
OTGINT.3 ROLEEXE
OTGIEN.3
BCERRI
OTGINT.2 BCERRE
OTGIEN.2
VBERRI
OTGINT.1 VBERRE
OTGIEN.1
SRPI
OTGINT.0 SRPE
OTGIEN.0
USB general
interrupt vector
UPRSMI
UDINT.6 UPRSME
UDIEN.6
EORSMI
UDINT.5 EORSME
UDIEN.5
WAKEUPI
UDINT.4 WAKEUPE
UDIEN.4
EORSTI
UDINT.3 EORSTE
UDIEN.3
SOFI
UDINT.2 SOFE
UDIEN.2
SUSPI
UDINT.0 SUSPE
UDIEN.0
HWUPE
UHIEN.6
HWUPI
UHINT.6
HSOFI
UHINT.5 HSOFE
UHIEN.5
RXRSMI
UHINT.4 RXRSME
UHIEN.4
RSMEDI
UHINT.3 RSMEDE
UHIEN.3
RSTI
UHINT.2 RSTE
UHIEN.2
DDISCI
UHINT.1 DDISCE
UHIEN.1
DCONNI
UHINT.0 DCONNE
UHIEN.0
USB device
interrupt
USB host
interrupt
USB general
interrupt vector
Asynchronous interrupt source
(allows the CPU to wake up from power down mode)249
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Figure 22-12. USB endpoint/pipe Interrupt vector sources.
FLERRE
UEIENX.7
OVERFI
UESTAX.6
UNDERFI
UESTAX.5
NAKINI
UEINTX.6 NAKINE
UEIENX.6
NAKOUTI
UEINTX.4 TXSTPE
UEIENX.4
RXSTPI
UEINTX.3 RXSTPE
UEIENX.3
RXOUTI
UEINTX.2 RXOUTE
UEIENX.2
STALLEDI
UEINTX.1 STALLEDE
UEIENX.1
EPINT
UEINT.X
Endpoint 0
Endpoint 1
Endpoint 2
Endpoint 3
Endpoint 4
Endpoint 5
Endpoint interrupt
TXINI
UEINTX.0 TXINE
UEIENX.0
FLERRE
UPIEN.7
UNDERFI
UPSTAX.5
OVERFI
UPSTAX.6
NAKEDI
UPINTX.6 NAKEDE
UPIEN.6
PERRI
UPINTX.4 PERRE
UPIEN.4
TXSTPI
UPINTX.3 TXSTPE
UPIEN.3
TXOUTI
UPINTX.2 TXOUTE
UPIEN.2
RXSTALLI
UPINTX.1 RXSTALLE
UPIEN.1
RXINI
UPINTX.0 RXINE
UPIEN.0
FLERRE
UPIEN.X
PIPE 0
PIPE 1
PIPE 2
PIPE 3
PIPE 4
PIPE 5
Pipe interrupt
USB endpoint/pipe
interrupt vector
Endpoint 6
PIPE 6250
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Figure 22-13. USB general and OTG controller interrupt system.
There are two kinds of interrupts: processing (that is, their generation are part of the normal processing)
and exception (errors).
Processing interrupts are generated when such events occur:
• USB ID Pad change detection (insert, remove)(IDTI)
• VBUS plug-in detection (insert, remove) (VBUSTI)
• SRP detected(SRPI)
• Role Exchanged(ROLEEXI)
Exception Interrupts are generated with the following events:
• Drop on VBus Detected(VBERRI)
• Error during the B-Connection(BCERRI)
• HNP Error(HNPERRI)
• Time-out detected during Suspend mode(STOII)
22.5 Power modes
22.5.1 Idle mode
In this mode, the CPU core is halted (CPU clock stopped). The Idle mode is taken wether the
USB controller is running or not. The CPU “wakes up” on any USB interrupts.
22.5.2 Power down
In this mode, the oscillator is stopped and halts all the clocks (CPU and peripherals). The USB
controller “wakes up” when:
• the WAKEUPI interrupt is triggered in the Peripheral mode (HOST cleared)
IDTE
USBCON.1
IDTI
USBINT.1
VBUSTI
USBINT.0 VBUSTE
USBCON.0
STOI
OTGINT.5 STOE
OTGIEN.5
HNPERRI
OTGINT.4 HNPERRE
OTGIEN.4
ROLEEXI
OTGINT.3 ROLEEXE
OTGIEN.3
BCERRI
OTGINT.2 BCERRE
OTGIEN.2
VBERRI
OTGINT.1 VBERRE
OTGIEN.1
SRPI
OTGINT.0 SRPE
OTGIEN.0
USB general & OTG
interrupt vector
Asynchronous interrupt source
(allows the CPU to wake up from power down mode251
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• the HWUPI interrupt is triggered in the Host mode (HOST set)
• the IDTI interrupt is triggered
• the VBUSTI interrupt is triggered
22.5.3 Freeze clock
The firmware has the ability to reduce the power consumption by setting the FRZCLK bit, which
freeze the clock of USB controller. When FRZCLK is set, it is still possible to access to the following
registers:
• USBCON, USBSTA, USBINT
• UDCON (detach, ...)
• UDINT
• UDIEN
• UHCON
• UHINT
• UHIEN
Moreover, when FRZCLK is set, only the following interrupts may be triggered:
• WAKEUPI
• IDTI
• VBUSTI
• HWUPI
22.6 Speed control
22.6.1 Device mode
When the USB interface is configured in device mode, the speed selection (Full Speed or Low
Speed) depends on the UDP/UDM pull-up. The LSM bit in UDCON register allows to select an
internal pull up on UDM (Low Speed mode) or UDP (Full Speed mode) data lines.
Figure 22-14. Device mode speed selection.
RPU
DETACH
UDCON.0
UDP
UDM
RPU
LSM
UDCON.2
UCAP USB
regulator252
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22.6.2 Host mode
When the USB interface is configured in host mode, internal Pull Down resistors are activated on
both UDP UDM lines and the interface detects the type of connected device.
22.7 Memory management
The controller does only support the following memory allocation management.
The reservation of a Pipe or an Endpoint can only be made in the increasing order (Pipe/Endpoint
0 to the last Pipe/Endpoint). The firmware shall thus configure them in the same order.
The reservation of a Pipe or an Endpoint “ki
” is done when its ALLOC bit is set. Then, the hardware
allocates the memory and inserts it between the Pipe/Endpoints “ki-1” and “ki+1”. The “ki+1”
Pipe/Endpoint memory “slides” up and its data is lost. Note that the “ki+2” and upper Pipe/Endpoint
memory does not slide.
Clearing a Pipe enable (PEN) or an Endpoint enable (EPEN) does not clear either its ALLOC bit,
or its configuration (EPSIZE/PSIZE, EPBK/PBK). To free its memory, the firmware should clear
ALLOC. Then, the “ki+1” Pipe/Endpoint memory automatically “slides” down. Note that the “ki+2”
and upper Pipe/Endpoint memory does not slide.
The following figure illustrates the allocation and reorganization of the USB memory in a typical
example:
Table 22-1. Allocation and reorganization USB memory flow.
• First, Pipe/Endpoint 0 to Pipe/Endpoint 5 are configured, in the growing order. The memory
of each is reserved in the DPRAM
• Then, the Pipe/Endpoint 3 is disabled (EPEN=0), but its memory reservation is internally kept
by the controller
• Its ALLOC bit is cleared: the Pipe/Endpoint 4 “slides” down, but the Pipe/Endpoint 5 does not
“slide”
• Finally, if the firmware chooses to reconfigure the Pipe/Endpoint 3, with a bigger size. The
controller reserved the memory after the endpoint 2 memory and automatically “slide” the
Pipe/Endpoint 4. The Pipe/Endpoint 5 does not move and a memory conflict appear, in that
Free memory
0
1
2
3
4
5
EPEN=1
ALLOC=1
Free memory
0
1
2
4
5
EPEN=0
(ALLOC=1)
Free memory
0
1
2
4
5
Pipe/Endpoints
activation
Pipe/Endpoint
Disable
Free its memory
(ALLOC=0)
Free memory
0
1
2
3 (bigger size)
5
Pipe/Endpoint
Activatation
Lost memory
4 Conflict253
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both Pipe/Endpoint 4 and 5 use a common area. The data of those endpoints are potentially
lost
Note that:
• the data of Pipe/Endpoint 0 are never lost whatever the activation or deactivation of the
higher Pipe/Endpoint. Its data is lost if it is deactivated
• Deactivate and reactivate the same Pipe/Endpoint with the same parameters does not lead
to a “slide” of the higher endpoints. For those endpoints, the data are preserved
• CFGOK is set by hardware even in the case where there is a “conflict” in the memory
allocation
22.8 PAD suspend
The next figures illustrates the pad behaviour:
• In the “idle” mode, the pad is put in low power consumption mode
• In the “active” mode, the pad is working
Figure 22-15. Pad behaviour.
The SUSPI flag indicated that a suspend state has been detected on the USB bus. This flag
automatically put the USB pad in Idle. The detection of a non-idle event sets the WAKEUPI flag
and wakes-up the USB pad.
Moreover, the pad can also be put in the “idle” mode if the DETACH bit is set. It come back in
the active mode when the DETACH bit is cleared.
Idle mode
Active mode
USBE=1
& DETACH=0
& suspend
USBE=0
| DETACH=1
| suspend
SUSPI Suspend detected = USB pad power down Clear suspend by software
Resume = USB pad wake-up
WAKEUPI Clear resume by software
PAD status
Active Power Down Active254
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22.9 OTG timers customizing
It is possible to refine some OTG timers thanks to the OTGTCON register that contains the
PAGE bits to select the timer and the VALUE bits to adjust the value. User should refer to lastest
releases of the OTG specification to select compliant timings.
• PAGE=00b: AWaitVrise time-out. [OTG]. In Host mode, once VBUSREQ has been set to “1”,
if no VBUS is detected on VBUS pin after this AWaitVrise delay then the VBERRI error flag is
set.
– VALUE=00bTime-out is set to 20ms
– VALUE=01bTime-out is set to 50ms
– VALUE=10bTime-out is set to 70ms
– VALUE=11bTime-out is set to 100ms
• PAGE=01b: VbBusPulsing. [OTG]. In Device mode, this delay corresponds to the pulse
duration on Vbus during a SRP.
– VALUE=00bTime-out is set to 15ms
– VALUE=01bTime-out is set to 23ms
– VALUE=10bTime-out is set to 31ms
– VALUE=11bTime-out is set to 40ms
• PAGE=10b: PdTmOutCnt. [OTG]. In Device mode, when a SRP has been requested to be
sent by the firmware, this delay is waited by the hardware after VBUS has gone below the
“session_valid” threshold voltage and before initiating the first pulse. This delay should be
considered as an approximation of USB lines discharge (pull-down resistors vs. line
capacitance) in order to wait that VBUS has gone below the “b_session_end” threshold
voltae, as defined in the OTG specification.
– VALUE=00bTime-out is set to 93ms
– VALUE=01bTime-out is set to 105ms
– VALUE=10bTime-out is set to 118ms
– VALUE=11bTime-out is set to 131ms
• PAGE=11b: SRPDetTmOut. [OTG]. In Host mode, this delay is the minimum pulse duration
required to detect and accept a valid SRP from a Device.
– VALUE=00bTime-out is set to 1µs
– VALUE=01bTime-out is set to 100µs
– VALUE=10bTime-out is set to 1ms
– VALUE=11bTime-out is set to 11ms255
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22.10 Plug-in detection
The USB connection is detected by the VBUS pad, thanks to the following architecture:
Figure 22-16. Plug-in detection input block diagram.
The control logic of the VBUS pad outputs a signal regarding the VBUS voltage level:
• The “Session_valid” signal is active high when the voltage on the VBUS pad is higher or
equal to 1.4V. If lower than 1.4V, the signal is not active
• The “Vbus_valid” signal is active high when the voltage on the VBUS pad is higher or equal to
4.4V. If lower than 4.4V, the signal is not active
• The VBUS status bit is set when VBUS is greater than “Vbus_valid”. The VBUS status bit is
cleared when VBUS falls below “Session_valid” (hysteresis behavior)
• The VBUSTI flag is set each time the VBUS bit state changes
22.10.1 Peripheral mode
The USB peripheral cannot attach to the bus while VBUS bit is not set.
22.10.2 Host mode
The Host must use the UVCON pin to drive an external power switch or regulator that powers
the Vbus line. The UVCON pin is automatically asserted and set high by hardware when
UVCONE and VBUSREQ bits are set by firmware.
If a device connects (pull-up on DP or DM) within 300ms of Vbus delivery, the DCONNI flag will
rise. But, once VBUSREQ bit has been set, if no peripheral connection is detected within 300ms,
the BCERRI flag (and interrupt) will rise and Vbus delivery will be stopped (UVCON cleared).
If that behavior represents a limitation for the Host application, the following work-around may be
used :
1. UVCONE and VBUSREQ must be cleared.
2. VBUSHWC must be set (to disable hardware control of UVCON pin).
3. PORTE,7 pin (alternate function of UVCON pin) must be set by firmware.
4. a device connection will be detected thanks to the SRPI flag (that may usually be used
to detect a DP/DM pulse sent by an OTG B-Device that requests a new session).
VBUSTI
USBINT.0
VBUS VBUS
USBSTA.0
VSS
VDD
Pad logic
Logic
Session_valid RPU RPU
VBus_pulsing
VBus_discharge
Vbus_valid256
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22.11 ID detection
The ID pin transition is detected thanks to the following architecture:
Figure 22-17. ID detection input block diagram.
The ID pin can be used to detect the USB mode (Peripheral or Host) or software selected. This
allows the UID pin to be used has general purpose I/O even when USB interface is enable.
When the UID pin is selected, by default, (no A-plug or B-plug), the macro is in the Peripheral
mode (internal pull-up). The IDTI interrupt is triggered when a A-plug (Host) is plugged or
unplugged. The interrupt is not triggered when a B-plug (Periph) is plugged or unplugged.
ID detection is independent of USB global interface enable.
22.12 Registers description
22.12.1 USB general registers
• 7 – UIMOD: USB Mode bit
This bit has no effect when the UIDE bit is set (external UID pin activated). Set to enable the
USB device mode. Clear to enable the USB host mode
• 6 – UIDE: UID pin Enable
Set to enable the USB mode selection (peripheral/host) through the UID pin. Clear to enable the
USB mode selection (peripheral/host) with UIMOD bit register.
UIDE should be modified only when the USB interface is disabled (USBE bit cleared).
• 5 – Reserved
The value read from this bit is always 0. Do not set this bit.
• 4 – UVCONE: UVCON pin Enable
Set to enable the UVCON pin control. Clear to disable the UVCON pin control. This bit should be
set only when the USB interface is enable.
RPU
UIMOD
UHWCON.7
UID
ID
USBSTA.1
Internal pull up
VDD
UIDE
UHWCON.6
1
0
Bit 7 6 5 4 3 2 1 0
UIMOD UIDE UVCONE UVREGE UHWCON
Read/write R/W R/W R R/W R R R R/W
Initial value 1 0 0 0 0 0 0 0257
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• 3-1 – Reserved
The value read from these bits is always 0. Do not set these bits.
• 0 – UVREGE: USB pad regulator Enable
Set to enable the USB pad regulator. Clear to disable the USB pad regulator.
• 7 – USBE: USB macro Enable bit
Set to enable the USB controller. Clear to disable and reset the USB controller, to disable the
USB transceiver and to disable the USB controller clock inputs.
• 6 – HOST: HOST bit
Set to enable the Host mode. Clear to enable the device mode.
• 5 – FRZCLK: Freeze USB Clock bit
Set to disable the clock inputs (the ”Resume Detection” is still active). This reduces the power
consumption. Clear to enable the clock inputs.
• 4 – OTGPADE: OTG Pad Enable
Set to enable the OTG pad. Clear to disable the OTG pad. The OTG pad is actually the VBUS
pad.
Note that this bit can be set/cleared even if USBE=0. That allows the VBUS detection even if the
USB macro is disabled. This pad must be enabled in both Host and Device modes in order to
allow USB operation (attaching, transmitting...).
• 3-2 – Reserved
The value read from these bits is always 0. Do not set these bits.
• 1 – IDTE: ID Transition Interrupt Enable bit
Set this bit to enable the ID Transition interrupt generation. Clear this bit to disable the ID Transition
interrupt generation.
• 0 – VBUSTE: VBUS Transition Interrupt Enable bit
Set this bit to enable the VBUS Transition interrupt generation.
Clear this bit to disable the VBUS Transition interrupt generation.
• 7-4 - Reserved
The value read from these bits is always 0. Do not set these bits.
Bit 7 6 5 4 3 2 1 0
USBE HOST FRZCLK OTGPADE - - IDTE VBUSTE USBCON
Read/write R/W R/W R/W R/W R R R/W R/W
Initial value 0 0 1 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
- - - - SPEED ID VBUS USBSTA
Read/write R R R R R R R R
Initial value 0 0 0 0 1 0 1 0258
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• 3 – SPEED: Speed Status Flag
This should be read only when the USB controller operates in host mode, in device mode the
value read from this bit is undeterminated.
Set by hardware when the controller is in FULL-SPEED mode. Cleared by hardware when the
controller is in LOW-SPEED mode.
• 2 – Reserved
The value read from this bit is always 0. Do not set this bit.
• 1 – ID: IUD pin flag
The value read from this bit indicates the state of the UID pin.
• 0 – VBUS: VBus flag
The value read from this bit indicates the state of the VBUS pin. This bit can be used in device
mode to monitor the USB bus connection state of the application. See Section 22.10, page 255
for more details.
7-2 - Reserved
The value read from these bits is always 0. Do not set these bits.
1 – IDTI: D Transition Interrupt flag
Set by hardware when a transition (high to low, low to high) has been detected on the UID pin.
Shall be cleared by software.
• 0 – VBUSTI: IVBUS Transition Interrupt flag
Set by hardware when a transition (high to low, low to high) has been detected on the VBUS
pad.
Shall be cleared by software.
• 7-6 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 5 – HNPREQ: HNP Request bit
Set to initiate the HNP when the controller is in the Device mode (B). Set to accept the HNP
when the controller is in the Host mode (A).
Clear otherwise.
Bit 7 6 5 4 3 2 1 0
- - - - - - IDTI VBUSTI USBINT
Read/write R R R R R R R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
- - HNPREQ SRPREQ SRPSEL VBUSHWC VBUSREQ VBUSRQC OTGCON
Read/write R R R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0259
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• 4 – SRPREQ: SRP Request bit
Set to initiate the SRP when the controller is in Device mode. Cleared by hardware when the
controller is initiating a SRP.
• 3 – SRPSEL: SRP Selection bit
Set to choose VBUS pulsing as SRP method.
Clear to choose data line pulsing as SRP method.
• 2 – VBUSHWC: VBus Hardware Control bit
Set to disable the hardware control over the UVCON pin.
Clear to enable the hardware control over the UVCON pin.
See for more details
• 1 – VBUSREQ: VBUS Request bit
Set to assert the UVCON pin in order to enable the VBUS power supply generation. This bit
shall be used when the controller is in the Host mode.
Cleared by hardware when VBUSRQC is set.
• 0 – VBUSRQC: VBUS Request Clear bit
Set to deassert the UVCON pin in order to enable the VBUS power supply generation. This bit
shall be used when the controller is in the Host mode.
Cleared by hardware immediately after the set.
• 7 – Reserved
This bit is reserved and always set.
• 6-5 – PAGE: Timer page access bit
Set/clear to access a special timer register. See Section 22.9, page 254 for more details.
• 4-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 1-0 – VALUE: Value bit
Set to initialize the new value of the timer. See Section 22.9, page 254 for more details.
Bit 7 6 5 4 3 2 1 0
- PAGE - - - VALUE OTGTCON
Read/write R R/W R/W R R R/W R/W R/W
Initial value 1 0 0 0 0 0 0 0260
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• 7-6 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 5 – STOE: Suspend Time-out Error Interrupt Enable bit
Set to enable the STOI interrupt. Clear to disable the STOI interrupt.
• 4 – HNPERRE: HNP Error Interrupt Enable bit
Set to enable the HNPERRI interrupt. Clear to disable the HNPERRI interrupt.
• 3 – ROLEEXE: Role Exchange Interrupt Enable bit
Set to enable the ROLEEXI interrupt. Clear to disable the ROLEEXI interrupt.
• 2 – BCERRE: B-Connection Error Interrupt Enable bit
Set to enable the BCERRI interrupt. Clear to disable the BCERRI interrupt.
• 1 – VBERRE: VBus Error Interrupt Enable bit
Set to enable the VBERRI interrupt. Clear to disable the VBERRI interrupt.
• 0 – SRPE: SRP Interrupt Enable bit
Set to enable the SRPI interrupt. Clear to disable the SRPI interrupt.
• 7-6 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 5 – STOI: Suspend Time-out Error Interrupt flag
Set by hardware when a time-out error (more than 150ms) has been detected after a suspend.
Shall be cleared by software.
• 4 – HNPERRI: HNP Error Interrupt flag
Set by hardware when an error has been detected during the protocol. Shall be cleared by
software.
• 3 – ROLEEXI: Role Exchange Interrupt flag
Set by hardware when the USB controller has successfully swapped its mode, due to an HNP
negotiation: Host to Device or Device to Host. However the mode selection bit (Host/Device) is
unchanged and must be changed by firmware in order to reach the correct RAM locations and
events bits. Shall be cleared by software.
Bit 7 6 5 4 3 2 1 0
- - STOE HNPERRE ROLEEXE BCERRE VBERRE SRPE OTGIEN
Read/write R R R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
- - STOI HNPERRI ROLEEXI BCERRI VBERRI SRPI OTGINT
Read/write R R R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0261
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• 2 – BCERRI: B-Connection Error Interrupt flag
Set by hardware when an error occur during the B-Connection (that is, if Peripheral has not connected
after 300ms of Vbus delivery request). Shall be cleared by software.
• 1 – VBERRI: V-Bus Error Interrupt flag
Set by hardware when a drop on VBus has been detected. Shall be cleared by software.
• 0 – SRPI: SRP Interrupt flag
Set by hardware when a SRP has been detected. Shall be used in the Host mode only. Shall be
cleared by software.
22.13 USB Software Operating modes
Depending on the USB operating mode, the software should perform some the following
operations:
Power On the USB interface
• Power-On USB pads regulator
• Configure PLL interface
• Enable PLL and wait PLL lock
• Enable USB interface
• Configure USB interface (USB speed, Endpoints configuration...)
• Wait for USB VBUS information connection
• Attach USB device
Power Off the USB interface
• Detach USB interface
• Disable USB interface
• Disable PLL
• Disable USB pad regulator
Suspending the USB interface
• Clear Suspend Bit
• Freeze USB clock
• Disable PLL
• Be sure to have interrupts enable to exit sleep mode
• Make the MCU enter sleep mode
Resuming the USB interface
• Enable PLL
• Wait PLL lock
• Unfreeze USB clock
• Clear Resume information262
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23. USB device operating modes
23.1 Introduction
The USB device controller supports full speed and low speed data transfers. In addition to the
default control endpoint, it provides six other endpoints, which can be configured in control, bulk,
interrupt or isochronous modes:
• Endpoint 0:programmable size FIFO up to 64 bytes, default control endpoint
• Endpoints 1 programmable size FIFO up to 256 bytes in ping-pong mode
• Endpoints 2 to 6: programmable size FIFO up to 64 bytes in ping-pong mode
The controller starts in the “idle” mode. In this mode, the pad consumption is reduced to the
minimum.
23.2 Power-on and reset
The next diagram explains the USB device controller main states on power-on:
Figure 23-1. USB device controller states after reset.
The reset state of the Device controller is:
• the macro clock is stopped in order to minimize the power consumption (FRZCLK set)
• the USB device controller internal state is reset (all the registers are reset to their default
value. Note that DETACH is set.)
• the endpoint banks are reset
• the D+ or D- pull up are not activated (mode Detach)
The D+ or D- pull-up will be activated as soon as the DETACH bit is cleared and VBUS is
present.
The macro is in the ‘Idle’ state after reset with a minimum power consumption and does not
need to have the PLL activated to enter in this state.
The USB device controller can at any time be reset by clearing USBE (disable USB interface).
23.3 Endpoint reset
An endpoint can be reset at any time by setting in the UERST register the bit corresponding to
the endpoint (EPRSTx). This resets:
• the internal state machine on that endpoint
• the Rx and Tx banks are cleared and their internal pointers are restored
Reset
Idle
HW
RESET
USBE=0
USBE=0
USBE=1
UID=1263
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• the UEINTX, UESTA0X and UESTA1X are restored to their reset value
The data toggle field remains unchanged.
The other registers remain unchanged.
The endpoint configuration remains active and the endpoint is still enabled.
The endpoint reset may be associated with a clear of the data toggle command (RSTDT bit) as
an answer to the CLEAR_FEATURE USB command.
23.4 USB reset
When an USB reset is detected on the USB line, the next operations are performed by the
controller:
• all the endpoints are disabled
• the default control endpoint remains configured (see Section 23.3, page 262 for more details)
23.5 Endpoint selection
Prior to any operation performed by the CPU, the endpoint must first be selected. This is done
by setting the EPNUM2:0 bits (UENUM register) with the endpoint number which will be managed
by the CPU.
The CPU can then access to the various endpoint registers and data.
23.6 Endpoint activation
The endpoint is maintained under reset as long as the EPEN bit is not set.
The following flow must be respected in order to activate an endpoint:264
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Figure 23-2. Endpoint activation flow.
As long as the endpoint is not correctly configured (CFGOK cleared), the hardware does not
acknowledge the packets sent by the host.
CFGOK is will not be sent if the Endpoint size parameter is bigger than the DPRAM size.
A clear of EPEN acts as an endpoint reset (see Section 23.3, page 262 for more details). It also
performs the next operation:
• The configuration of the endpoint is kept (EPSIZE, EPBK, ALLOC kept)
• It resets the data toggle field
• The DPRAM memory associated to the endpoint is still reserved
See Section 22.7, page 252 for more details about the memory allocation/reorganization.
23.7 Address setup
The USB device address is set up according to the USB protocol:
• the USB device, after power-up, responds at address 0
• the host sends a SETUP command (SET_ADDRESS(addr))
• the firmware records that address in UADD, but keep ADDEN cleared
• the USB device sends an IN command of 0 bytes (IN 0 Zero Length Packet)
• then, the firmware can enable the USB device address by setting ADDEN. The only accepted
address by the controller is the one stored in UADD
ADDEN and UADD shall not be written at the same time.
UADD contains the default address 00h after a power-up or USB reset.
Endpoint
Activation
CFGOK=1
ERROR
No
Yes
Endpoint activated
Activate the endpoint
Select the endpoint
EPEN=1
UENUM
EPNUM=x
Test the correct endpoint
configuration
UECFG1X ALLOC
EPSIZE
EPBK
Configure:
- the endpoint size
- the bank parametrization
Allocation and reorganization of
the memory is made on-the-fly
UECFG0X EPDIR
EPTYPE
...
Configure:
- the endpoint direction
- the endpoint type265
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ADDEN is cleared by hardware:
• after a power-up reset
• when an USB reset is received
• or when the macro is disabled (USBE cleared)
When this bit is cleared, the default device address 00h is used.
23.8 Suspend, wake-up and resume
After a period of 3ms during which the USB line was inactive, the controller switches to the fullspeed
mode and triggers (if enabled) the SUSPI (suspend) interrupt. The firmware may then set
the FRZCLK bit.
The CPU can also, depending on software architecture, enter in the idle mode to lower again the
power consumption.
There are two ways to recover from the “Suspend” mode:
• First one is to clear the FRZCLK bit. This is possible if the CPU is not in the Idle mode
• Second way, if the CPU is “idle”, is to enable the WAKEUPI interrupt (WAKEUPE set). Then,
as soon as an non-idle signal is seen by the controller, the WAKEUPI interrupt is triggered.
The firmware shall then clear the FRZCLK bit to restart the transfer
There are no relationship between the SUSPI interrupt and the WAKEUPI interrupt: the WAKEUPI
interrupt is triggered as soon as there are non-idle patterns on the data lines. Thus, the
WAKEUPI interrupt can occurs even if the controller is not in the “suspend” mode.
When the WAKEUPI interrupt is triggered, if the SUSPI interrupt bit was already set, it is cleared
by hardware.
When the SUSPI interrupt is triggered, if the WAKEUPI interrupt bit was already set, it is cleared
by hardware.
23.9 Detach
The reset value of the DETACH bit is 1.
It is possible to re-enumerate a device, simply by setting and clearing the DETACH bit.
• Setting DETACH will disconnect the pull-up on the D+ or D- pad (depending on full or low
speed mode selected). Then, clearing DETACH will connect the pull-up on the D+ or D- pad
Figure 23-3. Detach a device in full-speed.
EN=1
D +
UVREF
D -
Detach, then
Attach EN=1
D +
UVREF
D -266
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23.10 Remote Wake-up
The “Remote Wake-up” (or “upstream resume”) request is the only operation allowed to be sent
by the device on its own initiative. Anyway, to do that, the device should first have received a
DEVICE_REMOTE_WAKEUP request from the host.
• First, the USB controller must have detected the “suspend” state of the line: the remote wakeup
can only be sent when a SUSPI flag is set
• The firmware has then the ability to set RMWKUP to send the “upstream resume” stream.
This will automatically be done by the controller after 5ms of inactivity on the USB line
• When the controller starts to send the “upstream resume”, the UPRSMI interrupt is triggered
(if enabled). SUSPI is cleared by hardware
• RMWKUP is cleared by hardware at the end of the “upstream resume”
• If the controller detects a good “End Of Resume” signal from the host, an EORSMI interrupt
is triggered (if enabled)
23.11 STALL request
For each endpoint, the STALL management is performed using two bits:
– STALLRQ (enable stall request)
– STALLRQC (disable stall request)
– STALLEDI (stall sent interrupt)
To send a STALL handshake at the next request, the STALLRQ request bit has to be set. All following
requests will be handshak’ed with a STALL until the STALLRQC bit is set.
Setting STALLRQC automatically clears the STALLRQ bit. The STALLRQC bit is also immediately
cleared by hardware after being set by software. Thus, the firmware will never read this bit
as set.
Each time the STALL handshake is sent, the STALLEDI flag is set by the USB controller and the
EPINTx interrupt will be triggered (if enabled).
The incoming packets will be discarded (RXOUTI and RWAL will not be set).
The host will then send a command to reset the STALL: the firmware just has to set the STALLRQC
bit and to reset the endpoint.
23.11.1 Special consideration for control endpoints
A SETUP request is always ACK’ed.
If a STALL request is set for a Control Endpoint and if a SETUP request occurs, the SETUP
request has to be ACK’ed and the STALLRQ request and STALLEDI sent flags are automatically
reset (RXSETUPI set, TXIN cleared, STALLED cleared, TXINI cleared...).
This management simplifies the enumeration process management. If a command is not supported
or contains an error, the firmware set the STALL request flag and can return to the main
task, waiting for the next SETUP request.
This function is compliant with the Chapter 8 test that may send extra status for a
GET_DESCRIPTOR. The firmware sets the STALL request just after receiving the status. All
extra status will be automatically STALL’ed until the next SETUP request.267
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23.11.2 STALL handshake and retry mechanism
The Retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the
STALLRQ request bit is set and if there is no retry required.
23.12 CONTROL endpoint management
A SETUP request is always ACK’ed. When a new setup packet is received, the RXSTPI interrupt
is triggered (if enabled). The RXOUTI interrupt is not triggered.
The FIFOCON and RWAL fields are irrelevant with CONTROL endpoints. The firmware shall
thus never use them on that endpoints. When read, their value is always 0.
CONTROL endpoints are managed by the following bits:
• RXSTPI is set when a new SETUP is received. It shall be cleared by firmware to
acknowledge the packet and to clear the endpoint bank
• RXOUTI is set when a new OUT data is received. It shall be cleared by firmware to
acknowledge the packet and to clear the endpoint bank
• TXINI is set when the bank is ready to accept a new IN packet. It shall be cleared by firmware
to send the packet and to clear the endpoint bank
23.12.1 Control write
Figure 23-4 shows a control write transaction. During the status stage, the controller will not necessary
send a NAK at the first IN token:
• If the firmware knows the exact number of descriptor bytes that must be read, it can then
anticipate on the status stage and send a ZLP for the next IN token
• or it can read the bytes and poll NAKINI, which tells that all the bytes have been sent by the
host, and the transaction is now in the status stage
Figure 23-4. Control write transaction.
23.12.2 Control read
Figure 23-5 on page 268 shows a control read transaction. The USB controller has to manage
the simultaneous write requests from the CPU and the USB host.
SETUP
RXSTPI
RXOUTI
TXINI
USB line
HW SW
OUT
HW SW
OUT
HW SW
IN IN
NAK
SW
SETUP STATUS DATA268
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Figure 23-5. Control read transaction.
A NAK handshake is always generated at the first status stage command.
When the controller detect the status stage, all the data writen by the CPU are erased, and
clearing TXINI has no effects.
The firmware checks if the transmission is complete or if the reception is complete.
The OUT retry is always ack’ed. This reception:
- set the RXOUTI flag (received OUT data)
- set the TXINI flag (data sent, ready to accept new data)
software algorithm:
set transmit ready
wait (transmit complete OR Receive complete)
if receive complete, clear flag and return
if transmit complete, continue
Once the OUT status stage has been received, the USB controller waits for a SETUP request.
The SETUP request have priority over any other request and has to be ACK’ed. This means that
any other flag should be cleared and the fifo reset when a SETUP is received.
WARNING: the byte counter is reset when the OUT Zero Length Packet is received. The firmware
has to take care of this.
23.13 OUT endpoint management
OUT packets are sent by the host. All the data can be read by the CPU, which acknowledges or
not the bank when it is empty.
23.13.1 Overview
The Endpoint must be configured first.
Each time the current bank is full, the RXOUTI and the FIFOCON bits are set. This triggers an
interrupt if the RXOUTE bit is set. The firmware can acknowledge the USB interrupt by clearing
the RXOUTI bit. The Firmware read the data and clear the FIFOCON bit in order to free the current
bank. If the OUT Endpoint is composed of multiple banks, clearing the FIFOCON bit will
switch to the next bank. The RXOUTI and FIFOCON bits are then updated by hardware in accordance
with the status of the new bank.
SETUP
RXSTPI
RXOUTI
TXINI
USB line
HW SW
IN
HW SW
IN OUT OUT
NAK
SW
SW
HW
Wr Enable
HOST
Wr Enable
CPU
SETUP STATUS DATA269
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RXOUTI shall always be cleared before clearing FIFOCON.
The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can
read data from the bank, and cleared by hardware when the bank is empty.
Figure 23-6. Example with 1 and 2 OUT data bank.
23.13.2 Detailed description
The data are read by the CPU, following the next flow:
• When the bank is filled by the host, an endpoint interrupt (EPINTx) is triggered, if enabled
(RXOUTE set) and RXOUTI is set. The CPU can also poll RXOUTI or FIFOCON, depending
on the software architecture
• The CPU acknowledges the interrupt by clearing RXOUTI
• The CPU can read the number of byte (N) in the current bank (N=BYCT)
• The CPU can read the data from the current bank (“N” read of UEDATX)
• The CPU can free the bank by clearing FIFOCON when all the data is read, that is:
– after “N” read of UEDATX
– as soon as RWAL is cleared by hardware
If the endpoint uses two banks, the second one can be filled by the HOST while the current one
is being read by the CPU. Then, when the CPU clear FIFOCON, the next bank may be already
ready and RXOUTI is set immediately.
23.14 IN endpoint management
IN packets are sent by the USB device controller, upon an IN request from the host. All the data
can be written by the CPU, which acknowledge or not the bank when it is full.
OUT DATA
(to bank 0) ACK
RXOUTI
FIFOCON
HW
OUT DATA
(to bank 0) ACK
HW
SW
SW
SW
read data from CPU
BANK 0
OUT DATA
(to bank 0) ACK
RXOUTI
FIFOCON
HW
OUT DATA
(to bank 1) ACK
SW
SW
Example with 2 OUT data banks
read data from CPU
BANK 0
HW
SW
read data from CPU
BANK 0
read data from CPU
BANK 1
NAK270
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23.14.1 Overview
The Endpoint must be configured first.
The TXINI bit is set by hardware when the current bank becomes free. This triggers an interrupt
if the TXINE bit is set. The FIFOCON bit is set at the same time. The CPU writes into the FIFO
and clears the FIFOCON bit to allow the USB controller to send the data. If the IN Endpoint is
composed of multiple banks, this also switches to the next data bank. The TXINI and FIFOCON
bits are automatically updated by hardware regarding the status of the next bank.
TXINI shall always be cleared before clearing FIFOCON.
The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can
write data to the bank, and cleared by hardware when the bank is full.
Figure 23-7. Example with 1 and 2 IN data bank.
23.14.2 Detailed description
The data are written by the CPU, following the next flow:
• When the bank is empty, an endpoint interrupt (EPINTx) is triggered, if enabled (TXINE set)
and TXINI is set. The CPU can also poll TXINI or FIFOCON, depending the software
architecture choice
• The CPU acknowledges the interrupt by clearing TXINI
• The CPU can write the data into the current bank (write in UEDATX)
• The CPU can free the bank by clearing FIFOCON when all the data are written, that is:
– after “N” write into UEDATX
– as soon as RWAL is cleared by hardware
IN DATA
(bank 0) ACK
TXINI
FIFOCON
HW
write data from CPU
BANK 0
Example with 2 IN data banks
SW
SW SW
SW
IN
IN DATA
(bank 0) ACK
TXINI
FIFOCON write data from CPU
BANK 0
SW
SW SW
SW
IN DATA
(bank 1) ACK
write data from CPU
BANK 0
write data from CPU
BANK 1
SW
HW
write data from CPU
BANK0
NAK271
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If the endpoint uses two banks, the second one can be read by the HOST while the current is
being written by the CPU. Then, when the CPU clears FIFOCON, the next bank may be already
ready (free) and TXINI is set immediately.
23.14.2.1 Abort
An “abort” stage can be produced by the host in some situations:
• In a control transaction: ZLP data OUT received during a IN stage
• In an isochronous IN transaction: ZLP data OUT received on the OUT endpoint during a IN
stage on the IN endpoint
• ...
The KILLBK bit is used to kill the last “written” bank. The best way to manage this abort is to perform
the following operations:
Table 23-1. Abort flow.
23.15 Isochronous mode
23.15.1 Underflow
An underflow can occur during IN stage if the host attempts to read a bank which is empty. In
this situation, the UNDERFI interrupt is triggered.
An underflow can also occur during OUT stage if the host send a packet while the banks are
already full. Typically, he CPU is not fast enough. The packet is lost.
It is not possible to have underflow error during OUT stage, in the CPU side, since the CPU
should read only if the bank is ready to give data (RXOUTI=1 or RWAL=1)
23.15.2 CRC error
A CRC error can occur during OUT stage if the USB controller detects a bad received packet. In
this situation, the STALLEDI interrupt is triggered. This does not prevent the RXOUTI interrupt
from being triggered.
Endpoint
Abort
Abort done
Abort is based on the fact
that no banks are busy,
meaning that nothing has to
be sent.
Disable the TXINI interrupt.
Endpoint
reset
NBUSYBK
=0
Yes
Clear
UEIENX.
TXINE
No
KILLBK=1
KILLBK=1 Yes
Kill the last written
bank.
Wait for the end of the
procedure.
No272
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23.16 Overflow
In Control, Isochronous, Bulk or Interrupt Endpoint, an overflow can occur during OUT stage, if
the host attempts to write in a bank that is too small for the packet. In this situation, the OVERFI
interrupt is triggered (if enabled). The packet is acknowledged and the RXOUTI interrupt is also
triggered (if enabled). The bank is filled with the first bytes of the packet.
It is not possible to have overflow error during IN stage, in the CPU side, since the CPU should
write only if the bank is ready to access data (TXINI=1 or RWAL=1).
23.17 Interrupts
Figure 23-8 shows all the interrupts sources.
Figure 23-8. USB device controller interrupt system.
There are two kinds of interrupts: processing (that is, their generation are part of the normal processing)
and exception (errors).
Processing interrupts are generated when:
• VBUS plug-in detection (insert, remove)(VBUSTI)
• Upstream resume(UPRSMI)
• End of resume(EORSMI)
• Wake up(WAKEUPI)
• End of reset (Speed Initialization)(EORSTI)
• Start of frame(SOFI, if FNCERR=0)
• Suspend detected after 3ms of inactivity(SUSPI)
Exception Interrupts are generated when:
• CRC error in frame number of SOF(SOFI, FNCERR=1)
UPRSMI
UDINT.6 UPRSME
UDIEN.6
EORSMI
UDINT.5 EORSME
UDIEN.5
WAKEUPI
UDINT.4 WAKEUPE
UDIEN.4
EORSTI
UDINT.3 EORSTE
UDIEN.3
SOFI
UDINT.2 SOFE
UDIEN.2
SUSPI
UDINT.0 SUSPE
UDIEN.0
USB device
interrupt273
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Figure 23-9. USB device controller endpoint interrupt system.
Processing interrupts are generated when:
• Ready to accept IN data(EPINTx, TXINI=1)
• Received OUT data(EPINTx, RXOUTI=1)
• Received SETUP(EPINTx, RXSTPI=1)
Exception Interrupts are generated when:
• Stalled packet(EPINTx, STALLEDI=1)
• CRC error on OUT in isochronous mode(EPINTx, STALLEDI=1)
• Overflow in isochronous mode(EPINTx, OVERFI=1)
• Underflow in isochronous mode(EPINTx, UNDERFI=1)
• NAK IN sent(EPINTx, NAKINI=1)
• NAK OUT sent(EPINTx, NAKOUTI=1)
23.18 Registers
23.18.1 USB device general registers
EPINT
UEINT.X
Endpoint 0
Endpoint 1
Endpoint 2
Endpoint 3
Endpoint 4
Endpoint 5
Endpoint interrupt
Endpoint 6
FLERRE
UEIENX.7
OVERFI
UESTAX.6
UNDERFI
UESTAX.5
NAKINI
UEINTX.6 NAKINE
UEIENX.6
NAKOUTI
UEINTX.4 TXSTPE
UEIENX.4
RXSTPI
UEINTX.3 TXOUTE
UEIENX.3
RXOUTI
UEINTX.2 RXOUTE
UEIENX.2
STALLEDI
UEINTX.1 STALLEDE
UEIENX.1
TXINI
UEINTX.0 TXINE
UEIENX.0
Bit 7 6 5 4 3 2 1 0
----- LSM RMWKUP DETACH UDCON
Read/write R R R R R R/W R/W R/W
Initial value 0 0 0 0 0 0 0 1274
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• 7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 2 - LSM - USB Device Low Speed Mode selection
When configured USB is configured in device mode, this bit allows to select the USB the USB
Low Speed or Full Speed Mod.
Clear to select full speed mode (D+ internal pull-up will be activate with the ATTACH bit will be
set) .
Set to select low speed mode (D- internal pull-up will be activate with the ATTACH bit will be
set). This bit has no effect when the USB interface is configured in HOST mode.
• 1- RMWKUP - Remote Wake-up bit
Set to send an “upstream-resume” to the host for a remote wake-up (the SUSPI bit must be set).
Cleared by hardware when signalling finished. Clearing by software has no effect.
See Section 23.10, page 266 for more details.
• 0 - DETACH - Detach bit
Set to physically detach de device (disconnect internal pull-up on D+ or D-).
Clear to reconnect the device. See Section 23.9, page 265 for more details.
• 7 - Reserved
The value read from this bits is always 0. Do not set this bit.
• 6 - UPRSMI - Upstream Resume Interrupt flag
Set by hardware when the USB controller is sending a resume signal called “Upstream
Resume”. This triggers an USB interrupt if UPRSME is set.
Shall be cleared by software (USB clocks must be enabled before). Setting by software has no
effect.
• 5 - EORSMI - End Of Resume Interrupt flag
Set by hardware when the USB controller detects a good “End Of Resume” signal initiated by
the host. This triggers an USB interrupt if EORSME is set.
Shall be cleared by software. Setting by software has no effect.
• 4 - WAKEUPI - Wake-up CPU Interrupt flag
Set by hardware when the USB controller is re-activated by a filtered non-idle signal from the
lines (not by an upstream resume). This triggers an interrupt if WAKEUPE is set. This interrupt
should be enable only to wake up the CPU core from power down mode.
Shall be cleared by software (USB clock inputs must be enabled before). Setting by software
has no effect.
See Section 23.8, page 265 for more details.
Bit 7 6 5 4 3 2 1 0
- UPRSMI EORSMI WAKEUPI EORSTI SOFI - SUSPI UDINT
Read/write
Initial value 0 0 0 0 0 0 0 0275
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• 3 - EORSTI - End Of Reset Interrupt flag
Set by hardware when an “End Of Reset” has been detected by the USB controller. This triggers
an USB interrupt if EORSTE is set.
Shall be cleared by software. Setting by software has no effect.
• 2 - SOFI - Start Of Frame Interrupt flag
Set by hardware when an USB “Start Of Frame” PID (SOF) has been detected (every 1ms). This
triggers an USB interrupt if SOFE is set.
• 1 - Reserved
The value read from this bits is always 0. Do not set this bit
• 0 - SUSPI - Suspend Interrupt flag
Set by hardware when an USB “Suspend” ‘idle bus for three frame periods: a J state for 3ms) is
detected. This triggers an USB interrupt if SUSPE is set.
Shall be cleared by software. Setting by software has no effect.
See Section 23.8, page 265 for more details.
The interrupt bits are set even if their corresponding ‘Enable’ bits is not set.
• 7 - Reserved
The value read from this bits is always 0. Do not set this bit.
• 6 - UPRSME - Upstream Resume Interrupt Enable bit
Set to enable the UPRSMI interrupt.
Clear to disable the UPRSMI interrupt.
• 5 - EORSME - End Of Resume Interrupt Enable bit
Set to enable the EORSMI interrupt.
Clear to disable the EORSMI interrupt.
• 4 - WAKEUPE - Wake-up CPU Interrupt Enable bit
Set to enable the WAKEUPI interrupt. For correct interrupt handle execution, this interrupt
should be enable only before entering power-down mode.
Clear to disable the WAKEUPI interrupt.
• 3 - EORSTE - End Of Reset Interrupt Enable bit
Set to enable the EORSTI interrupt. This bit is set after a reset.
Clear to disable the EORSTI interrupt.
• 2 - SOFE - Start Of Frame Interrupt Enable bit
Set to enable the SOFI interrupt.
Clear to disable the SOFI interrupt.
Bit 7 6 5 4 3 2 1 0
- UPRSME EORSME WAKEUPE EORSTE SOFE - SUSPE UDIEN
Read/write
Initial value 0 0 0 0 0 0 0 0276
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• 1 - Reserved
The value read from this bits is always 0. Do not set this bit
• 0 - SUSPE - Suspend Interrupt Enable Bit
Set to enable the SUSPI interrupt.
Clear to disable the SUSPI interrupt.
• 7 - ADDEN - Address Enable Bit
Set to activate the UADD (USB address).
Cleared by hardware. Clearing by software has no effect.
See Section 23.7, page 264 for more details.
• 6-0 - UADD6:0 - USB Address Bits
Load by software to configure the device address.
• 7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 2-0 - FNUM10:8 - Frame Number Upper Value
Set by hardware. These bits are the three MSB of the 11-bits Frame Number information. They
are provided in the last received SOF packet. FNUM is updated if a corrupted SOF is received.
• Frame Number Lower Value
Set by hardware. These bits are the eight LSB of the 11-bits Frame Number information.
• 7-5 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 4 - FNCERR -Frame Number CRC Error flag
Set by hardware when a corrupted Frame Number in start of frame packet is received.
This bit and the SOFI interrupt are updated at the same time.
Bit 7 6 5 4 3 2 1 0
ADDEN UADD6:0 UDADDR
Read/write W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
- - - - - FNUM10:8 UDFNUMH
Read/write R R R R R R R R
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
FNUM7:0 UDFNUML
Read/write R R R R R R R R
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
- - - FNCERR - - - - UDMFN
Read/write R
Initial value 0 0 0 0 0 0 0 0277
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• 3-0 - Reserved
The value read from these bits is always 0. Do not set these bits.
23.18.2 USB device endpoint registers
• 7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 2-0 - EPNUM2:0 Endpoint Number bits
Load by software to select the number of the endpoint which shall be accessed by the CPU. See
Section 23.5, page 263 for more details.
EPNUM = 111b is forbidden.
• 7 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 6-0 - EPRST6:0 - Endpoint FIFO Reset bits
Set to reset the selected endpoint FIFO prior to any other operation, upon hardware reset or
when an USB bus reset has been received. See Section 23.3, page 262 for more information
Then, clear by software to complete the reset operation and start using the endpoint.
• 7-6 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 5 - STALLRQ - STALL Request Handshake bit
Set to request a STALL answer to the host for the next handshake.
Cleared by hardware when a new SETUP is received. Clearing by software has no effect.
See Section 23.11, page 266 for more details.
• 4 - STALLRQC - STALL Request Clear Handshake bit
Set to disable the STALL handshake mechanism.
Cleared by hardware immediately after the set. Clearing by software has no effect.
See Section 23.11, page 266 for more details.
Bit 7 6 5 4 3 2 1 0
- - - - - EPNUM2:0 UENUM
Read/write R R R R R R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
- EPRST6 EPRST5 EPRST4 EPRST3 EPRST2 EPRST1 EPRST0 UERST
Read/write R R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
- - STALLRQ STALLRQC RSTDT - - EPEN UECONX
Read/write R R W W W R R R/W
Initial value 0 0 0 0 0 0 0 0278
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• RSTDT - Reset Data Toggle bit
Set to automatically clear the data toggle sequence:
For OUT endpoint: the next received packet will have the data toggle 0.
For IN endpoint: the next packet to be sent will have the data toggle 0.
Cleared by hardware instantaneously. The firmware does not have to wait that the bit is cleared.
Clearing by software has no effect.
• 2 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 1 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 0 - EPEN - Endpoint Enable bit
Set to enable the endpoint according to the device configuration. Endpoint 0 shall always be
enabled after a hardware or USB reset and participate in the device configuration.
Clear this bit to disable the endpoint. See Section 23.6, page 263 for more details.
• 7-6 - EPTYPE1:0 - Endpoint Type bits
Set this bit according to the endpoint configuration:
00b: Control10b: Bulk
01b: Isochronous11b: Interrupt
• 5-4 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 3-2 - Reserved for test purpose
The value read from these bits is always 0. Do not set these bits.
• 1 - Reserved
The value read from this bits is always 0. Do not set this bit.
• 0 - EPDIR - Endpoint Direction bit
Set to configure an IN direction for bulk, interrupt or isochronous endpoints.
Clear to configure an OUT direction for bulk, interrupt, isochronous or control endpoints.
Bit 7 6 5 4 3 2 1 0
EPTYPE1:0 - - - - - EPDIR UECFG0X
Read/write R/W R/W R R R R R R/W
Initial value 0 0 0 0 0 0 0 0279
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• 7 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 6-4 - EPSIZE2:0 - Endpoint Size bits
Set this bit according to the endpoint size:
000b: 8 bytes 100b: 128 bytes (only for endpoint 1)
001b: 16 bytes 101b: 256 bytes (only for endpoint 1)
010b: 32 bytes 110b: Reserved. Do not use this configuration
011b: 64 bytes 111b: Reserved. Do not use this configuration
• 3-2 - EPBK1:0 - Endpoint Bank bits
Set this field according to the endpoint size:
00b: One bank
01b: Double bank
1xb: Reserved. Do not use this configuration
• 1 - ALLOC - Endpoint Allocation bit
Set this bit to allocate the endpoint memory.
Clear to free the endpoint memory.
See Section 23.6, page 263 for more details.
• 0 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 7 - CFGOK - Configuration Status flag
Set by hardware when the endpoint X size parameter (EPSIZE) and the bank parametrization
(EPBK) are correct compared to the max FIFO capacity and the max number of allowed bank.
This bit is updated when the bit ALLOC is set.
If this bit is cleared, the user should reprogram the UECFG1X register with correct EPSIZE and
EPBK values.
Bit 7 6 5 4 3 2 1 0
- EPSIZE2:0 EPBK1:0 ALLOC - UECFG1X
Read/write R R/W R/W R/W R/W R/W R/W R
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
CFGOK OVERFI UNDERFI - DTSEQ1:0 NBUSYBK1:0 UESTA0X
Read/write R R/W R/W R/W R R R R
Initial value 0 0 0 0 0 0 0 0280
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• 6 - OVERFI - Overflow Error Interrupt flag
Set by hardware when an overflow error occurs in an isochronous endpoint. An interrupt
(EPINTx) is triggered (if enabled).
See Section 23.15, page 271 for more details.
Shall be cleared by software. Setting by software has no effect.
• 5 - UNDERFI - Flow Error Interrupt flag
Set by hardware when an underflow error occurs in an isochronous endpoint. An interrupt
(EPINTx) is triggered (if enabled).
See Section 23.15, page 271 for more details.
Shall be cleared by software. Setting by software has no effect.
• 4 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 3-2 - DTSEQ1:0 - Data Toggle Sequencing flag
Set by hardware to indicate the PID data of the current bank:
00b Data0
01b Data1
1xb Reserved
For OUT transfer, this value indicates the last data toggle received on the current bank.
For IN transfer, it indicates the Toggle that will be used for the next packet to be sent. This is not
relative to the current bank.
• 1-0 - NBUSYBK1:0 - Busy Bank flag
Set by hardware to indicate the number of busy bank.
For IN endpoint, it indicates the number of busy bank(s), filled by the user, ready for IN transfer.
For OUT endpoint, it indicates the number of busy bank(s) filled by OUT transaction from the
host.
00b All banks are free
01b One busy bank
10b Two busy banks
11b Reserved
• 7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
Bit 7 6 5 4 3 2 1 0
- - - - - CTRLDIR CURRBK1:0 UESTA1X
Read/write R R R R R R R R
Initial value 0 0 0 0 0 0 0 0281
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• 2 - CTRLDIR - Control Direction (flag, and bit for debug purpose)
Set by hardware after a SETUP packet, and gives the direction of the following packet:
- 1 for IN endpoint
- 0 for OUT endpoint
Can not be set or cleared by software.
• 1-0 - CURRBK1:0 - Current Bank (all endpoints except Control endpoint) flag
Set by hardware to indicate the number of the current bank:
00b Bank0
01b Bank1
1xb Reserved
Can not be set or cleared by software.
• 7 - FIFOCON - FIFO Control bit
For OUT and SETUP Endpoint:
Set by hardware when a new OUT message is stored in the current bank, at the same time than
RXOUT or RXSTP.
Clear to free the current bank and to switch to the following bank. Setting by software has no
effect.
For IN Endpoint:
Set by hardware when the current bank is free, at the same time than TXIN.
Clear to send the FIFO data and to switch the bank. Setting by software has no effect.
• 6 - NAKINI - NAK IN Received Interrupt flag
Set by hardware when a NAK handshake has been sent in response of a IN request from the
host. This triggers an USB interrupt if NAKINE is sent.
Shall be cleared by software. Setting by software has no effect.
• 5 - RWAL - Read/Write Allowed flag
Set by hardware to signal:
- for an IN endpoint: the current bank is not full, that is, the firmware can push data into the FIFO,
- for an OUT endpoint: the current bank is not empty, that is, the firmware can read data from the
FIFO.
The bit is never set if STALLRQ is set, or in case of error.
Cleared by hardware otherwise.
This bit shall not be used for the control endpoint.
Bit 7 6 5 4 3 2 1 0
FIFOCON NAKINI RWAL NAKOUTI RXSTPI RXOUTI STALLEDI TXINI UEINTX
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0282
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• 4 - NAKOUTI - NAK OUT Received Interrupt flag
Set by hardware when a NAK handshake has been sent in response of a OUT/PING request
from the host. This triggers an USB interrupt if NAKOUTE is sent.
Shall be cleared by software. Setting by software has no effect.
• 3 - RXSTPI - Received SETUP Interrupt flag
Set by hardware to signal that the current bank contains a new valid SETUP packet. An interrupt
(EPINTx) is triggered (if enabled).
Shall be cleared by software to handshake the interrupt. Setting by software has no effect.
This bit is inactive (cleared) if the endpoint is an IN endpoint.
• 2 - RXOUTI / KILLBK - Received OUT Data Interrupt flag
Set by hardware to signal that the current bank contains a new packet. An interrupt (EPINTx) is
triggered (if enabled).
Shall be cleared by software to handshake the interrupt. Setting by software has no effect.
Kill Bank IN bit
Set this bit to kill the last written bank.
Cleared by hardware when the bank is killed. Clearing by software has no effect.
See page 271 for more details on the Abort.
• 1 - STALLEDI - STALLEDI Interrupt flag
Set by hardware to signal that a STALL handshake has been sent, or that a CRC error has been
detected in a OUT isochronous endpoint.
Shall be cleared by software. Setting by software has no effect.
• 0 - TXINI - Transmitter Ready Interrupt flag
Set by hardware to signal that the current bank is free and can be filled. An interrupt (EPINTx) is
triggered (if enabled).
Shall be cleared by software to handshake the interrupt. Setting by software has no effect.
This bit is inactive (cleared) if the endpoint is an OUT endpoint.
• 7 - FLERRE - Flow Error Interrupt Enable flag
Set to enable an endpoint interrupt (EPINTx) when OVERFI or UNDERFI are sent.
Clear to disable an endpoint interrupt (EPINTx) when OVERFI or UNDERFI are sent.
• 6 - NAKINE - NAK IN Interrupt Enable bit
Set to enable an endpoint interrupt (EPINTx) when NAKINI is set.
Clear to disable an endpoint interrupt (EPINTx) when NAKINI is set.
Bit 7 6 5 4 3 2 1 0
FLERRE NAKINE - NAKOUTE RXSTPE RXOUTE STALLEDE TXINE UEIENX
Read/write R/W R/W R R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0283
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• 5 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 4 - NAKOUTE - NAK OUT Interrupt Enable bit
Set to enable an endpoint interrupt (EPINTx) when NAKOUTI is set.
Clear to disable an endpoint interrupt (EPINTx) when NAKOUTI is set.
• 3 - RXSTPE - Received SETUP Interrupt Enable flag
Set to enable an endpoint interrupt (EPINTx) when RXSTPI is sent.
Clear to disable an endpoint interrupt (EPINTx) when RXSTPI is sent.
• 2 - RXOUTE - Received OUT Data Interrupt Enable flag
Set to enable an endpoint interrupt (EPINTx) when RXOUTI is sent.
Clear to disable an endpoint interrupt (EPINTx) when RXOUTI is sent.
• 1 - STALLEDE - Stalled Interrupt Enable flag
Set to enable an endpoint interrupt (EPINTx) when STALLEDI is sent.
Clear to disable an endpoint interrupt (EPINTx) when STALLEDI is sent.
• 0 - TXINE - Transmitter Ready Interrupt Enable flag
Set to enable an endpoint interrupt (EPINTx) when TXINI is sent.
Clear to disable an endpoint interrupt (EPINTx) when TXINI is sent.
• 7-0 - DAT7:0 -Data bits
Set by the software to read/write a byte from/to the endpoint FIFO selected by EPNUM.
• 7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 2-0 - BYCT10:8 - Byte count (high) bits
Set by hardware. This field is the MSB of the byte count of the FIFO endpoint. The LSB part is
provided by the UEBCLX register.
Bit 7 6 5 4 3 2 1 0
DAT D7 DAT D6 DAT D5 DAT D4 DAT D3 DAT D2 DAT D1 DAT D0 UEDATX
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
- - - - - BYCT D10 BYCT D9 BYCT D8 UEBCHX
Read/write R R R R R R R R
Initial value 0 0 0 0 0 0 0 0284
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• 7-0 - BYCT7:0 - Byte Count (low) bits
Set by the hardware. BYCT10:0 is:
- (for IN endpoint) increased after each writing into the endpoint and decremented after each
byte sent,
- (for OUT endpoint) increased after each byte sent by the host, and decremented after each
byte read by the software.
• 7 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 6-0 - EPINT6:0 - Endpoint Interrupts bits
Set by hardware when an interrupt is triggered by the UEINTX register and if the corresponding
endpoint interrupt enable bit is set.
Cleared by hardware when the interrupt source is served.
Bit 7 6 5 4 3 2 1 0
BYCT D7 BYCT D6 BYCT D5 BYCT D4 BYCT D3 BYCT D2 BYCT D1 BYCT D0 UEBCLX
Read/write R R R R R R R R
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
- EPINT D6 EPINT D5 EPINT D4 EPINT D3 EPINT D2 EPINT D1 EPINT D0 UEINT
Read/write R R R R R R R R
Initial value 0 0 0 0 0 0 0 0285
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24. USB host operating modes
This mode is available only on Atmel AT90USB647/1287 products.
24.1 Pipe description
For the USB Host controller, the term of Pipe is used instead of Endpoint for the USB Device
controller. A Host Pipe corresponds to a Device Endpoint, as described in the USB specification.
Figure 24-1. Pipes and endpoints in a USB system.
In the USB Host controller, a Pipe will be associated to a Device Endpoint, considering the
Device Configuration Descriptors.
24.2 Detach
The reset value of the DETACH bit is 1. Thus, the firmware has the responsibility of clearing this
bit before switching to the Host mode (HOST set).
24.3 Power-on and reset
Figure 24-2 explains the USB host controller main states on power-on.
Figure 24-2. USB host controller states after reset.
Host
Ready
Host
Idle
Device
disconnection
Device
connection
Clock stopped
Macro off
Device
disconnection
Host
Suspend
SOFE=1
SOFE=0286
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USB host controller state after an hardware reset is ‘Reset’. When the USB controller is enabled
and the USB Host controller is selected, the USB controller is in ‘Idle’ state. In this state, the
USB Host controller waits for the Device connection, with a minimum power consumption.
The USB Pad should be in Idle mode. The macro does not need to have the PLL activated to
enter in ‘Host Ready’ state.
The Host controller enters in Suspend state when the USB bus is in Suspend state, that is, when
the Host controller doesn’t generate the Start of Frame. In this state, the USB consumption is
minimum. The Host controller exits to the Suspend state when starting to generate the SOF over
the USB line.
24.4 Device detection
A Device is detected by the USB controller when the USB bus if different from D+ and D- low. In
other words, when the USB Host Controller detects the Device pull-up on the D+ line. To enable
this detection, the Host Controller has to provide the Vbus power supply to the Device.
The Device Disconnection is detected by the USB Host controller when the USB Idle correspond
to D+ and D- low on the USB line.
24.5 Pipe selection
Prior to any operation performed by the CPU, the Pipe must first be selected. This is done by
setting PNUM2:0 bits (UPNUM register) with the Pipe number which will be managed by the
CPU.
The CPU can then access to the various Pipe registers and data.
24.6 Pipe configuration
The following flow (see Figure 24-3 on page 287) must be respected in order to activate a Pipe.287
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Figure 24-3. Pipe activation flow.
Once the Pipe is activated (EPEN set) and, the hardware is ready to send requests to the
Device.
When configured (CFGOK = 1), only the Pipe Token (PTOKEN) and the polling interval for Interrupt
pipe can be modified.
A Control type pipe supports only one bank. Any other value will lead to a configuration error
(CFGOK = 0).
A clear of PEN will reset the configuration of the Pipe. All the corresponding Pipe registers are
reset to there reset values. Please refer to “Memory management” on page 252 for more details.
Note: The firmware has to configure the Default Control Pipe with the following parameters:
• Type: Control
• Token: SETUP
• Data bank: 1
• Size: 64 Bytes
The firmware asks for eight bytes of the Device Descriptor sending a GET_DESCRIPTOR
request. These bytes contains the MaxPacketSize of the Device default control endpoint and the
firmware re-configures the size of the Default Control Pipe with this size parameter.
Pipe
Activ ation
UPCONX
PENABLE=1
UPCFG0X PTYPE
PTOKEN
PEPNUM
CFGOK=1
ERROR
No
Yes
UPCFG2X
INTFRQ
(interrupt only)
Pipe activ ated
and f reezed
UPCFG1X
PSIZE
PBK
CFGMEM
Enable the pipe
Select the Pipe type:
* Type (Control, Bulk, Interrupt)
* Token (IN, OUT, SETUP)
* Endpoint number
Configure the Pipe memory:
* Pipe size
* Number of banks
Configure the polling interval
for Interrupt pipe288
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24.7 USB reset
The USB controller sends a USB Reset when the firmware set the RESET bit. The RSTI bit is
set by hardware when the USB Reset has been sent. This triggers an interrupt if the RSTE has
been set.
When a USB Reset has been sent, all the Pipe configuration and the memory allocation are
reset. The General Host interrupt enable register is left unchanged.
If the bus was previously in suspend mode (SOFEN = 0), the USB controller automatically
switches to the resume mode (HWUPI is set) and the SOFEN bit is set by hardware in order to
generate SOF immediately after the USB Reset.
24.8 Address setup
Once the Device has answer to the first Host requests with the default address (0), the Host
assigns a new address to the device. The Host controller has to send a USB reset to the device
and perform a SET ADDRESS control request, with the new address to be used by the Device.
This control request ended, the firmware write the new address into the UHADDR register. All
following requests, on every Pipes, will be performed using this new address.
When the Host controller send a USB reset, the UHADDR register is reset by hardware and the
following Host requests will be performed using the default address (0).
24.9 Remote wake-up detection
The Host Controller enters in Suspend mode when clearing the SOFEN bit. No more Start Of
Frame is sent on the USB bus and the USB Device enters in Suspend mode 3ms later.
The Device awakes the Host Controller by sending an Upstream Resume (Remote Wake-Up
feature). The Host Controller detects a non-idle state on the USB bus and set the HWUPI bit. If
the non-Idle correspond to an Upstream Resume (K state), the RXRSMI bit is set by hardware.
The firmware has to generate a downstream resume within 1ms and for at least 20ms by setting
the RESUME bit.
Once the downstream Resume has been generated, the SOFEN bit is automatically set by hardware
in order to generate SOF immediately after the USB resume.
24.10 USB pipe reset
The firmware can reset a Pipe using the pipe reset register. The configuration of the pipe and
the data toggle remains unchanged. Only the bank management and the status bits are reset to
their initial values.
To completely reset a Pipe, the firmware has to disable and then enable the pipe.
24.11 Pipe data access
In order to read or to write into the Pipe Fifo, the CPU selects the Pipe number with the UPNUM
register and performs read or write action on the UPDATX register.
Host
Ready
Host
Suspend
SOFE=1
or HWUP=1
SOFE=0289
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24.12 Control pipe management
A Control transaction is composed of three phases:
• SETUP
• Data (IN or OUT)
• Status (OUT or IN)
The firmware has to change the Token for each phase.
The initial data toggle is set for the corresponding token (ONLY for Control Pipe):
• SETUP: Data0
• OUT: Data1
• IN: Data1 (expected data toggle)
24.13 OUT pipe management
The Pipe must be configured and not frozen first.
Note: if the firmware decides to switch to suspend mode (clear SOFEN) even if a bank is ready
to be sent, the USB controller will automatically exit from Suspend mode and the bank will be
sent.
The TXOUT bit is set by hardware when the current bank becomes free. This triggers an interrupt
if the TXOUTE bit is set. The FIFOCON bit is set at the same time. The CPU writes into the
FIFO and clears the FIFOCON bit to allow the USB controller to send the data.
If the OUT Pipe is composed of multiple banks, this also switches to the next data bank. The
TXOUT and FIFOCON bits are automatically updated by hardware regarding the status of the
next bank.290
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Figure 24-4. Example with OUT data banks.
24.14 IN Pipe management
The Pipe must be configured first.
When the Host requires data from the device, the firmware has to determine first the IN mode to
use using the INMODE bit:
• INMODE = 0. The INRQX register is taken in account. The Host controller will perform
(INRQX+1) IN requests on the selected Pipe before freezing the Pipe. This mode avoids to
have extra IN requests on a Pipe
• INMODE = 1. The USB controller will perform infinite IN request until the firmware freezes the
Pipe
The IN request generation will start when the firmware clear the PFREEZE bit.
Each time the current bank is full, the RXIN and the FIFOCON bits are set. This triggers an interrupt
if the RXINE bit is set. The firmware can acknowledge the USB interrupt by clearing the
RXIN bit. The Firmware read the data and clear the FIFOCON bit in order to free the current
OUT DATA
(bank 0) ACK
TXOUT
FIFOCON
HW
Example with 1 OUT data bank
write data from CPU
BANK 0
Example with 2 OUT data banks
SW
SW SW
SW
OUT
OUT DATA
(bank 0) ACK
TXOUT
FIFOCON
write data from CPU
BANK 0
SW
SW SW
SW
OUT DATA
(bank 1) ACK
write data from CPU
BANK 0
write data from CPU
BANK 1
SW
HW
write data from CPU
BANK0
Example with 2 OUT data banks
OUT DATA
(bank 0) ACK
TXOUT
FIFOCON
write data from CPU
BANK 0
SW
SW SW
write data from CPU SW
BANK 1
SW
HW
write data from CPU
BANK0
OUT DATA
(bank 1) ACK291
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bank. If the IN Pipe is composed of multiple banks, clearing the FIFOCON bit will switch to the
next bank. The RXIN and FIFOCON bits are then updated by hardware in accordance with the
status of the new bank.
Figure 24-5. Example with IN data banks.
24.14.1 CRC error (isochronous only)
A CRC error can occur during IN stage if the USB controller detects a bad received packet. In
this situation, the STALLEDI/CRCERRI interrupt is triggered. This does not prevent the RXINI
interrupt from being triggered.
24.15 Interrupt system
Figure 24-6. USB host controller interrupt system.
IN DATA
(to bank 0) ACK
RXIN
FIFOCON
HW
IN DATA
(to bank 0) ACK
HW
SW
SW
SW
Example with 1 IN data bank
read data from CPU
BANK 0
IN DATA
(to bank 0) ACK
RXIN
FIFOCON
HW
IN DATA
(to bank 1) ACK
SW
SW
Example with 2 IN data banks
read data from CPU
BANK 0
HW
SW
read data from CPU
BANK 0
read data from CPU
BANK 1
HWUPE
UHIEN.6
HWUPI
UHINT.6
HSOFI
UHINT.5 HSOFE
UHIEN.5
RXRSMI
UHINT.4 RXRSME
UHIEN.4
RSMEDI
UHINT.3 RSMEDE
UHIEN.3
RSTI
UHINT.2 RSTE
UHIEN.2
DDISCI
UHINT.1 DDISCE
UHIEN.1
DCONNI
UHINT.0 DCONNE
UHIEN.0
USB host
interrupt292
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Figure 24-7. USB device controller pipe interrupt system.
24.16 Registers
24.16.1 General USB host registers
• 7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 2 - RESUME - Send USB Resume
Set this bit to generate a USB Resume on the USB bus.
Cleared by hardware when the USB Resume has been sent. Clearing by software has no effect.
This bit should be set only when the start of frame generation is enable (SOFEN bit set).
• 1 - RESET - Send USB Reset
Set this bit to generate a USB Reset on the USB bus.
Cleared by hardware when the USB Reset has been sent. Clearing by software has no effect.
Refer to the USB reset section for more details.
• 0 - SOFEN - Start Of Frame Generation Enable
Set this bit to generate SOF on the USB bus in full speed mode and keep-alive in low speed
mode.
Clear this bit to disable the SOF generation and to leave the USB bus in Idle state.
FLERRE
UPIEN.7
UNDERFI
UPSTAX.5
OVERFI
UPSTAX.6
NAKEDI
UPINTX.6 NAKEDE
UPIEN.6
PERRI
UPINTX.4 PERRE
UPIEN.4
TXSTPI
UPINTX.3 TXSTPE
UPIEN.3
TXOUTI
UPINTX.2 TXOUTE
UPIEN.2
RXSTALLI
UPINTX.1 RXSTALLE
UPIEN.1
RXINI
UPINTX.0 RXINE
UPIEN.0
FLERRE
UPIEN.7
PIPE 0
PIPE 1
PIPE 2
PIPE 3
PIPE 4
PIPE 5
Pipe interrupt
PIPE 6
Bit 7 6 5 4 3 2 1 0
----- RESUME RESET SOFEN UHCON
Read/write R R R R R R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0293
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• 7 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 6 - HWUPI - Host Wake-Up Interrupt
Set by hardware when a non-idle state is detected on the USB bus.This interrupt should be
enable only to wake up the CPU core from power down mode.
Shall be clear by software to acknowledge the interrupt. Setting by software has no effect.
• 5 - HSOFI - Host Start Of Frame Interrupt
Set by hardware when a SOF is issued by the Host controller. This triggers a USB interrupt
when HSOFE is set. When using the host controller in low speed mode, this bit is also set when
a keep-alive is sent.
Shall be cleared by software to acknowledge the interrupt. Setting by software has no effect.
• 4 - RXRSMI - Upstream Resume Received Interrupt
Set by hardware when an Upstream Resume has been received from the Device.
Shall be cleared by software. Setting by software has no effect.
• 3 - RSMEDI - Downstream Resume Sent Interrupt
Set by hardware when a Downstream Resume has been sent to the Device.
Shall be cleared by software. Setting by software has no effect.
• 2 - RSTI - USB Reset Sent Interrupt
Set by hardware when a USB Reset has been sent to the Device.
Shall be cleared by software. Setting by software has no effect.
• 1 - DDISCI - Device Disconnection Interrupt
Set by hardware when the device has been removed from the USB bus.
Shall be cleared by software. Setting by software has no effect.
• 0 - DCONNI - Device Connection Interrupt
Set by hardware when a new device has been connected to the USB bus.
Shall be cleared by software. Setting by software has no effect.
• 7 - Reserved
The value read from these bits is always 0. Do not set these bits.
Bit 7 6 5 4 3 2 1 0
- HWUPI HSOFI RXRSMI RSMEDI RSTI DDISCI DCONNI UHINT
Read/write R R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
HWUPE HSOFE RXRSME RSMEDE RSTE DDISCE DCONNE UHIEN
Read/write R R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0294
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• 6 - HWUPE - Host Wake-Up Interrupt Enable
Set this bit to enable HWUP interrupt.For correct interrupt handle execution, this interrupt should
be enable only before entering power-down mode.
Clear this bit to disable HWUP interrupt.
• 5 - HSOFE - Host Start Of frame Interrupt Enable
Set this bit to enable HSOF interrupt.
Clear this bit to disable HSOF interrupt.
• 4 - RXRSME -Upstream Resume Received Interrupt Enable
Set this bit to enable the RXRSMI interrupt.
Clear this bit to disable the RXRSMI interrupt.
• 3 - RSMEDE - Downstream Resume Sent Interrupt Enable
Set this bit to enable the RSMEDI interrupt.
Clear this bit to disable the RSMEDI interrupt.
• 2 - RSTE - USB Reset Sent Interrupt Enable
Set this bit to enable the RSTI interrupt.
Clear this bit to disable the RSTI interrupt.
• 1 - DDISCE - Device Disconnection Interrupt Enable
Set this bit to enable the DDISCI interrupt.
Clear this bit to disable the DDISCI interrupt.
• 0 - DCONNE - Device Connection Interrupt Enable
Set this bit to enable the DCONNI interrupt.
Clear this bit to disable the DCONNI interrupt.
• 7 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 6-0 - HADDR6:0 - USB Host Address
These bits contain the address of the USB Device.
Bit 7 6 5 4 3 2 1 0
HADDR6 HADDR5 HADDR4 HADDR3 HADDR2 HADDR1 HADDR0 HADDR6 UHADDR
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0295
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• 7-4 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 3-0 - FNUM10:8 - Frame Number
The value contained in this register is the current SOF number.
This value can be modified by software.
• 7-0 - FNUM7:0 - Frame Number
The value contained in this register is the current SOF number.
This value can be modified by software.
• 7-0 - FLEN7:0 - Frame Length
The value contained the data frame length transmited.
24.16.2 USB Host Pipe registers
• 7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 2-0 - PNUM2:0 - Pipe Number
Select the pipe using this register. The USB Host registers ended by a X correspond then to this
number.
This number is used for the USB controller following the value of the PNUMD bit.
Bit 7 6 5 4 3 2 1 0
- - - - - FNUM10 FNUM9 FNUM8 UHFNUMH
Read/write R R R R R R R R
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
FNUM7 FNUM6 FNUM5 FNUM4 FNUM3 FNUM2 FNUM1 FNUM0 UHFNUML
Read/write R R R R R R R R
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
FLEN7 FLEN6 FLEN5 FLEN4 FLEN3 FLEN2 FLEN1 FLEN0 UHFLEN
Read/write R R R R R R R R
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PNUM2 PNUM1 PNUM0 UPNUM
Read/write RW RW RW
Initial value 0 0 0 0 0 0 0 0296
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• 7 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 6 - P6RST - Pipe 6 Reset
Set this bit to 1 and reset this bit to 0 to reset the Pipe 6.
• 5 - P5RST - Pipe 5 Reset
Set this bit to 1 and reset this bit to 0 to reset the Pipe 5.
• 4 - P4RST - Pipe 4 Reset
Set this bit to 1 and reset this bit to 0 to reset the Pipe 4.
• 3 - P3RST - Pipe 3 Reset
Set this bit to 1 and reset this bit to 0 to reset the Pipe 3.
• 2 - P2RST - Pipe 2 Reset
Set this bit to 1 and reset this bit to 0 to reset the Pipe 2.
• 1 - P1RST - Pipe 1 Reset
Set this bit to 1 and reset this bit to 0 to reset the Pipe 1.
• 0 - P0RST - Pipe 0 Reset
Set this bit to 1 and reset this bit to 0 to reset the Pipe 0.
• 7 - Reserved
The value read from this bit is always 0. Do not set this bit.
• 6 - PFREEZE - Pipe Freeze
Set this bit to Freeze the Pipe requests generation.
Clear this bit to enable the Pipe request generation.
This bit is set by hardware when:
- the pipe is not configured
- a STALL handshake has been received on this Pipe
- An error occurs on the Pipe (UPINTX.PERRI = 1)
- (INRQ+1) In requests have been processed
This bit is set at 1 by hardware after a Pipe reset or a Pipe enable.
Bit 7 6 5 4 3 2 1 0
- P6RST P5RST P4RST P3RST P2RST P1RST P0RST UPRST
Read/write RW RW RW RW RW RW RW
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
- PFREEZE INMODE - RSTDT - - PEN UPCONX
Read/write RW RW RW RW
Initial value 0 0 0 0 0 0 0 0297
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• 5 - INMODE - IN Request mode
Set this bit to allow the USB controller to perform infinite IN requests when the Pipe is not frozen.
Clear this bit to perform a pre-defined number of IN requests. This number is stored in the UINRQX
register.
• 4 - Reserved
The value read from this bit is always 0. Do not set this bit.
• 3 - RSTDT - Reset Data Toggle
Set this bit to reset the Data Toggle to its initial value for the current Pipe.
Cleared by hardware when proceed. Clearing by software has no effect.
• 2 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 1 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 0 - PEN - Pipe Enable
Set to enable the Pipe.
Clear to disable and set the pipe.
• 7-6 - PTYPE1:0 - Pipe Type
Select the type of the Pipe:
- 00: Control
- 01: Isochronous
- 10: Bulk
- 11: Interrupt
• 5-4 - PTOKEN1:0 - Pipe Token
Select the Token to associate to the Pipe
- 00: SETUP
- 01: IN
- 10: OUT
- 11: reserved
• 3-0 - PEPNUM3:0 - Pipe Endpoint Number
Set this field according to the Pipe configuration. Set the number of the Endpoint targeted by the
Pipe. This value is from 0 and 15.
Bit 7 6 5 4 3 2 1 0
PTYPE1 PTYPE0 PTOKEN1 PTOKEN0 PEPNUM3 PEPNUM2 PEPNUM1 PEPNUM0 UPCFG0X
Read/write RW RW RW RW RW RW RW RW
Initial value 0 0 0 0 0 0 0 0298
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• 7 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 6-4 - PSIZE2:0 - Pipe Size
Select the size of the Pipe:
- 000: 8 - 100: 128 (only for endpoint 1)
- 001: 16 - 101: 256 (only for endpoint 1)
- 010: 32 - 110: Reserved. Do not use this configuration.
- 011: 64 - 111: Reserved. Do not use this configuration.
• 3-2 - PBK1:0 - Pipe Bank
Select the number of bank to declare for the current Pipe.
- 00: 1 bank
- 01: 2 banks
- 10: invalid
- 11: invalid
• ALLOC - Configure Pipe Memory
Set to configure the pipe memory with the characteristics.
Clear to update the memory allocation. Refer to the Memory Management chapter for more
details.
7 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 7 - INTFRQ7:0 - Interrupt Pipe Request Frequency
These bits are the maximum value in millisecond of the polling period for an Interrupt Pipe.
This value has no effect for a non-Interrupt Pipe.
Bit 7 6 5 4 3 2 1 0
- PSIZE2:0 PBK1:0 ALLOC - UPCFG1X
Read/write R RW RW RW RW RW RW
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
INTFRQ7 INTFRQ6 INTFRQ5 INTFRQ4 INTFRQ3 INTFRQ2 INTFRQ1 INTFRQ0 UPCFG2X
Read/write RW RW RW RW RW RW RW RW
Initial value 0 0 0 0 0 0 0 0299
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• 7 - CFGOK - Configure Pipe Memory OK
Set by hardware if the required memory configuration has been successfully performed.
Cleared by hardware when the pipe is disabled. The USB reset and the reset pipe have no effect
on the configuration of the pipe.
• 6 - OVERFI - Overflow
Set by hardware when a the current Pipe has received more data than the maximum length of
the current Pipe. An interrupt is triggered if the FLERRE bit is set.
Shall be cleared by software. Setting by software has no effect.
• 5 - UNDERFI - Underflow
Set by hardware when a transaction underflow occurs in the current isochronous or interrupt
Pipe. The Pipe can’t send the data flow required by the device. A ZLP will be sent instead. An
interrupt is triggered if the FLERRE bit is set.
Shall be cleared by software. Setting by software has no effect.
Note: the Host controller has to send a OUT packet, but the bank is empty. A ZLP will be sent
and the UNDERFI bit is set.
• 4 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 3-2 - DTSEQ1:0 - Toggle Sequencing flag
Set by hardware to indicate the PID data of the current bank:
00b Data0
01b Data1
1xb Reserved.
For OUT Pipe, this value indicates the next data toggle that will be sent. This is not relative to the
current bank.
For IN Pipe, this value indicates the last data toggle received on the current bank.
• 1-0 - NBUSYBK1:0 - Busy Bank flag
Set by hardware to indicate the number of busy bank.
For OUT Pipe, it indicates the number of busy bank(s), filled by the user, ready for OUT transfer.
For IN Pipe, it indicates the number of busy bank(s) filled by IN transaction from the Device.
00b All banks are free
01b 1 busy bank
10b 2 busy banks
11b Reserved.
Bit 7 6 5 4 3 2 1 0
CFGOK OVERFI UNDERFI - DTSEQ1:0 NBUSYBK UPSTAX
Read/write R RW RW R R R R
Initial value 0 0 0 0 0 0 0 0300
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• 7-0 - INRQ7:0 - IN Request Number Before Freeze
Enter the number of IN transactions before the USB controller freezes the pipe. The USB controller
will perform (INRQ+1) IN requests before to freeze the Pipe. This counter is automatically
decreased by 1 each time a IN request has been successfully performed.
This register has no effect when the INMODE bit is set (infinite IN requests generation till the
pipe is not frozen).
• 7-6 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 5 - COUNTER1:0 - Error counter
This counter is increased by the USB controller each time an error occurs on the Pipe. When this
value reaches 3, the Pipe is automatically frozen.
Clear these bits by software.
• 4 - CRC16 - CRC16 Error
Set by hardware when a CRC16 error has been detected.
Shall be cleared by software. Setting by software has no effect.
• 3 - TIMEOUT - Time-out Error
Set by hardware when a time-out error has been detected.
Shall be cleared by software. Setting by software has no effect.
• 2 - PID - PID Error
Set by hardware when a PID error has been detected.
Shall be cleared by software. Setting by software has no effect.
• 1 - DATAPID - Data PID Error
Set by hardware when a data PID error has been detected.
Shall be cleared by software. Setting by software has no effect.
• 0 - DATATGL - Bad Data Toggle
Set by hardware when a data toggle error has been detected.
Shall be cleared by software. Setting by software has no effect.
Bit 7 6 5 4 3 2 1 0
INRQ7 INRQ6 INRQ5 INRQ4 INRQ3 INRQ2 INRQ1 INRQ0 UPINRQX
Read/write RW RW RW RW RW RW RW RW
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
- COUNTER1:0 CRC16 TIMEOUT PID DATAPID DATATGL UPERRX
Read/write RW RW RW RW RW RW RW
Initial value 0 0 0 0 0 0 0 0301
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• 7 - FIFOCON - FIFO Control
For OUT and SETUP Pipe:
Set by hardware when the current bank is free, at the same time than TXOUT or TXSTP.
Clear to send the FIFO data and to switch the bank. Setting by software has no effect.
For IN Pipe:
Set by hardware when a new IN message is stored in the current bank, at the same time than
RXIN.
Clear to free the current bank and to switch to the following bank. Setting by software has no
effect.
• 6 - NAKEDI - NAK Handshake received
Set by hardware when a NAK has been received on the current bank of the Pipe. This triggers
an interrupt if the NAKEDE bit is set in the UPIENX register.
Shall be clear to handshake the interrupt. Setting by software has no effect.
• 5 - RWAL - Read/Write Allowed
OUT Pipe:
Set by hardware when the firmware can write a new data into the Pipe FIFO.
Cleared by hardware when the current Pipe FIFO is full.
IN Pipe:
Set by hardware when the firmware can read a new data into the Pipe FIFO.
Cleared by hardware when the current Pipe FIFO is empty.
This bit is also cleared by hardware when the RXSTALL or the PERR bit is set
• 4 - PERRI -PIPE Error
Set by hardware when an error occurs on the current bank of the Pipe. This triggers an interrupt
if the PERRE bit is set in the UPIENX register. Refers to the UPERRX register to determine the
source of the error.
Automatically cleared by hardware when the error source bit is cleared.
• 3 - TXSTPI - SETUP Bank ready
Set by hardware when the current SETUP bank is free and can be filled. This triggers an interrupt
if the TXSTPE bit is set in the UPIENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
• 2 - TXOUTI -OUT Bank ready
Set by hardware when the current OUT bank is free and can be filled. This triggers an interrupt if
the TXOUTE bit is set in the UPIENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
Bit 7 6 5 4 3 2 1 0
FIFOCON NAKEDI RWAL PERRI TXSTPI TXOUTI RXSTALLI RXINI UPINTX
Read/write RW RW RW RW RW RW RW RW
Initial value 0 0 0 0 0 0 0 0302
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• 1 - RXSTALLI / CRCERR - STALL Received / Isochronous CRC Error
Set by hardware when a STALL handshake has been received on the current bank of the Pipe.
The Pipe is automatically frozen. This triggers an interrupt if the RXSTALLE bit is set in the UPIENX
register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
For Isochronous Pipe:
Set by hardware when a CRC error occurs on the current bank of the Pipe. This triggers an interrupt
if the TXSTPE bit is set in the UPIENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
• 0 - RXINI - IN Data received
Set by hardware when a new USB message is stored in the current bank of the Pipe. This triggers
an interrupt if the RXINE bit is set in the UPIENX register.
Shall be cleared to handshake the interrupt. Setting by software has no effect.
• 7 - FLERRE - Flow Error Interrupt enable
Set to enable the OVERFI and UNDERFI interrupts.
Clear to disable the OVERFI and UNDERFI interrupts.
• 6 - NAKEDE -NAK Handshake Received Interrupt Enable
Set to enable the NAKEDI interrupt.
Clear to disable the NAKEDI interrupt.
• 5 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 4 - PERRE -PIPE Error Interrupt Enable
Set to enable the PERRI interrupt.
Clear to disable the PERRI interrupt.
• 3 - TXSTPE - SETUP Bank ready Interrupt Enable
Set to enable the TXSTPI interrupt.
Clear to disable the TXSTPI interrupt.
• 2 - TXOUTE - OUT Bank ready Interrupt Enable
Set to enable the TXOUTI interrupt.
Clear to disable the TXOUTI interrupt.
• 1 - RXSTALLE - STALL Received Interrupt Enable
Set to enable the RXSTALLI interrupt.
Clear to disable the RXSTALLI interrupt.
Bit 7 6 5 4 3 2 1 0
FLERRE NAKEDE - PERRE TXSTPE TXOUTE RXSTALLE RXINE UPIENX
Read/write RW RW RW RW RW RW RW
Initial value 0 0 0 0 0 0 0 0303
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• 0 - RXINE - IN Data received Interrupt Enable
Set to enable the RXINI interrupt.
Clear to disable the RXINI interrupt.
• 7-0 - PDAT7:0 - Pipe Data bits
Set by the software to read/write a byte from/to the Pipe FIFO selected by PNUM.
• 7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 2-0 - PBYCT10:8 - Byte count (high) bits
Set by hardware. This field is the MSB of the byte count of the FIFO endpoint. The LSB part is
provided by the UPBCLX register.
• 7-0 - PBYCT7:0 - Byte Count (low) bits
Set by the hardware. PBYCT10:0 is:
- (for OUT Pipe) increased after each writing into the Pipe and decremented after each byte
sent,
- (for IN Pipe) increased after each byte received by the host, and decremented after each byte
read by the software.
• 7 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 6-0 - PINT6:0 - Pipe Interrupts bits
Set by hardware when an interrupt is triggered by the UPINTX register and if the corresponding
endpoint interrupt enable bit is set.
Cleared by hardware when the interrupt source is served.
Bit 7 6 5 4 3 2 1 0
PDAT7 PDAT6 PDAT5 PDAT4 PDAT3 PDAT2 PDAT1 PDAT0 UPDATX
Read/write RW RW RW RW RW RW RW RW
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
- - - - - PBYCT10 PBYCT9 PBYCT8 UPBCHX
Read/write R R R
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PBYCT7 PBYCT6 PBYCT5 PBYCT4 PBYCT3 PBYCT2 PBYCT1 PBYCT0 UPBCLX
Read/write R R R R R R R R
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
- PINT6 PINT5 PINT4 PINT3 PINT2 PINT1 PINT0 UPINT
Read/write
Initial value 0 0 0 0 0 0 0 0304
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25. Analog Comparator
The Analog Comparator compares the input values on the positive pin AIN0 and negative pin
AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin
AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger
the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate
interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator
output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is
shown in Figure 25-1.
The Power Reduction ADC bit, PRADC, in “PRR0 – Power Reduction Register 0” on page 54
must be disabled by writing a logical zero to be able to use the ADC input MUX.
Figure 25-1. Analog Comparator block diagram (2).
Notes: 1. See Table 25-2 on page 306.
2. Refer to Figure 1-1 on page 3 and Table 11-6 on page 79 for Analog Comparator pin
placement.
25.0.1 ADCSRB – ADC Control and Status Register B
• Bit 6 – ACME: Analog Comparator Multiplexer Enable
When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the
ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written
logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed
description of this bit, see “Analog Comparator multiplexed input” on page 306.
25.0.2 ACSR – Analog Comparator Control and Status Register
ACBG
BANDGAP
REFERENCE
ADC MULTIPLEXER
OUTPUT
ACME
ADEN
(1)
Bit 7 6 5 4 3 2 1 0
– ACME – – - ADTS2 ADTS1 ADTS0 ADCSRB
Read/write R R/W R R R R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 ACSR
Read/write R/W R/W R R/W R/W R/W R/W R/W
Initial value 0 0 N/A 0 0 0 0 0305
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• Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the Analog Comparator is switched off. This bit
can be set at any time to turn off the Analog Comparator. This will reduce power consumption in
Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be
disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is
changed.
• Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog
Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator.
See “Internal voltage reference” on page 62.
• Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly connected to ACO. The
synchronization introduces a delay of 1 - 2 clock cycles.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined
by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set
and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator
interrupt is activated. When written logic zero, the interrupt is disabled.
• Bit 2 – ACIC: Analog Comparator Input Capture Enable
When written logic one, this bit enables the input capture function in Timer/Counter1 to be triggered
by the Analog Comparator. The comparator output is in this case directly connected to the
input capture front-end logic, making the comparator utilize the noise canceler and edge select
features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection
between the Analog Comparator and the input capture function exists. To make the comparator
trigger the Timer/Counter1 Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask
Register (TIMSK1) must be set.
• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator interrupt. The
different settings are shown in Table 25-1.
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by
clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the
bits are changed.
Table 25-1. ACIS1/ACIS0 settings.
ACIS1 ACIS0 Interrupt mode
0 0 Comparator Interrupt on Output Toggle
0 1 Reserved
1 0 Comparator Interrupt on Falling Output Edge
1 1 Comparator Interrupt on Rising Output Edge306
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25.1 Analog Comparator multiplexed input
It is possible to select any of the ADC7..0 pins to replace the negative input to the Analog Comparator.
The ADC multiplexer is used to select this input, and consequently, the ADC must be
switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in
ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), and MUX2..0 in
ADMUX select the input pin to replace the negative input to the Analog Comparator, as shown in
Table 25-2. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog
Comparator.
25.1.1 DIDR1 – Digital Input Disable Register 1
• Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding
PIN Register bit will always read as zero when this bit is set. When an analog signal is
applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be written
logic one to reduce power consumption in the digital input buffer.
Table 25-2. Analog Comparator multiplexed input.
ACME ADEN MUX2..0 Analog Comparator negative input
0 x xxx AIN1
1 1 xxx AIN1
1 0 000 ADC0
1 0 001 ADC1
1 0 010 ADC2
1 0 011 ADC3
1 0 100 ADC4
1 0 101 ADC5
1 0 110 ADC6
1 0 111 ADC7
Bit 7 6 5 4 3 2 1 0
– – – – – – AIN1D AIN0D DIDR1
Read/write R R R R R R R/W R/W
Initial value 0 0 0 0 0 0 0 0307
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26. ADC – Analog to Digital Converter
26.1 Features
• 10-bit resolution
• 0.5 LSB integral non-linearity
• ±2 LSB absolute accuracy
• 65 - 260µs conversion time
• Up to 15ksps at maximum resolution
• Eight multiplexed single ended input channels
• Seven differential input channels
• Optional left adjustment for ADC result readout
• 0 - VCC ADC input voltage range
• Selectable 2.56V ADC reference voltage
• Free running or single conversion mode
• ADC start conversion by auto triggering on interrupt sources
• Interrupt on ADC conversion complete
• Sleep mode noise canceler
26.2 Overview
The Atmel AT90USB64/128 features a 10-bit successive approximation ADC. The ADC is connected
to an 8-channel Analog Multiplexer which allows eight single-ended voltage inputs
constructed from the pins of Port F. The single-ended voltage inputs refer to 0V (GND).
The device also supports 16 differential voltage input combinations. Two of the differential inputs
(ADC1, ADC0 and ADC3, ADC2) are equipped with a programmable gain stage, providing
amplification steps of 0 dB (1×), 20 dB (10×), or 46 dB (200×) on the differential input voltage
before the A/D conversion. Seven differential analog input channels share a common negative
terminal (ADC1), while any other ADC input can be selected as the positive input terminal. If 1×
or 10× gain is used, 8-bit resolution can be expected. If 200× gain is used, 7-bit resolution can
be expected.
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is
held at a constant level during conversion. A block diagram of the ADC is shown in Figure 26-1
on page 308.
The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more than ±0.3V
from VCC. See the paragraph “ADC noise canceler” on page 314 on how to connect this pin.
Internal reference voltages of nominally 2.56V or AVCC are provided on-chip. The voltage reference
may be externally decoupled at the AREF pin by a capacitor for better noise performance.308
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Figure 26-1. Analog to digital converter block schematic.
ADC CONVERSION
COMPLETE IRQ
8-BIT DATA BUS
15 0
ADC MULTIPLEXER
SELECT (ADMUX)
ADC CTRL. & STATUS
REGISTER (ADCSRA)
ADC DATA REGISTER
(ADCH/ADCL)
MUX2
ADIE
ADATE
ADEN
ADSC
ADIF ADIF
MUX1
MUX0
ADPS2
ADPS1
ADPS0
MUX3
CONVERSION LOGIC
10-BIT DAC
+
-
SAMPLE & HOLD
COMPARATOR
INTERNAL
REFERENCE
MUX DECODER MUX4
AVCC
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
REFS1
REFS0
ADLAR
+
-
CHANNEL SELECTION
GAIN SELECTION
ADC[9:0]
ADC MULTIPLEXER
OUTPUT
DIFFERENTIAL
AMPLIFIER
AREF
BANDGAP
REFERENCE
PRESCALER
SINGLE ENDED / DIFFERENTIAL SELECTION
GND
POS.
INPUT
MUX
NEG.
INPUT
MUX
TRIGGER
SELECT
ADTS[2:0]
INTERRUPT
FLAGS
ADHSM
START309
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26.3 Operation
The ADC converts an analog input voltage to a 10-bit digital value through successive approximation.
The minimum value represents GND and the maximum value represents the voltage on
the AREF pin minus 1 LSB. Optionally, AVCC or an internal 2.56V reference voltage may be connected
to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal
voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve
noise immunity.
The analog input channel and differential gain are selected by writing to the MUX bits in
ADMUX. Any of the ADC input pins, as well as GND and a fixed bandgap voltage reference, can
be selected as single ended inputs to the ADC. A selection of ADC input pins can be selected as
positive and negative inputs to the differential amplifier.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and
input channel selections will not go into effect until ADEN is set. The ADC does not consume
power when ADEN is cleared, so it is recommended to switch off the ADC before entering power
saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and
ADCL. By default, the result is presented right adjusted, but can optionally be presented left
adjusted by setting the ADLAR bit in ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data
Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers
is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is
read, neither register is updated and the result from the conversion is lost. When ADCH is read,
ADC access to the ADCH and ADCL Registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes. The ADC
access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt
will trigger even if the result is lost.
26.4 Starting a conversion
A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.
This bit stays high as long as the conversion is in progress and will be cleared by hardware
when the conversion is completed. If a different data channel is selected while a conversion is in
progress, the ADC will finish the current conversion before performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is
enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is
selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (See description of the ADTS
bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal,
the ADC prescaler is reset and a conversion is started. This provides a method of starting conversions
at fixed intervals. If the trigger signal is still set when the conversion completes, a new
conversion will not be started. If another positive edge occurs on the trigger signal during conversion,
the edge will be ignored. Note that an interrupt flag will be set even if the specific
interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus
be triggered without causing an interrupt. However, the interrupt flag must be cleared in order to
trigger a new conversion at the next interrupt event. 310
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Figure 26-2. ADC auto trigger logic.
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon
as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly
sampling and updating the ADC Data Register. The first conversion must be started by
writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive
conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to
one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be
read as one during a conversion, independently of how the conversion was started.
26.5 Prescaling and conversion timing
Figure 26-3. ADC prescaler.
By default, the successive approximation circuitry requires an input clock frequency between
50kHz and 200kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the
input clock frequency to the ADC can be higher than 200kHz to get a higher sample rate. Alternatively,
setting the ADHSM bit in ADCSRB allows an increased ADC clock frequency at the
expense of higher power consumption.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency
from any CPU frequency above 100kHz. The prescaling is set by the ADPS bits in ADCSRA.
The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit
ADSC
ADIF
SOURCE 1
SOURCE n
ADTS[2:0]
CONVERSION
LOGIC
PRESCALER
START CLKADC
.
.
.
. EDGE
DETECTOR
ADATE
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
CK
ADPS0
ADPS1
ADPS2
CK/128
CK/2
CK/4
CK/8
CK/16
CK/32
CK/64
Reset
ADEN
START311
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in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously
reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion
starts at the following rising edge of the ADC clock cycle. See “Differential channels” on page
312 for details on differential conversion timing.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched
on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion
and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is
complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion
mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new
conversion will be initiated on the first rising ADC clock edge.
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures
a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold
takes place two ADC clock cycles after the rising edge on the trigger source signal. Three additional
CPU clock cycles are used for synchronization logic.
In Free Running mode, a new conversion will be started immediately after the conversion completes,
while ADSC remains high. For a summary of conversion times, see Table 26-1 on page
312.
Figure 26-4. ADC timing diagram, first conversion (single conversion mode).
Figure 26-5. ADC timing diagram, single conversion.
Sign and MSB of result
LSB of result
ADC clock
ADSC
Sample & hold
ADIF
ADCH
ADCL
Cycle number
ADEN
1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2
First conversion Next
conversion
3
MUX and REFS
update
MUX
and REFS
update
Conversion
complete
1 2 3 4 5 6 7 8 9 10 11 12 13
Sign and MSB of result
LSB of result
ADC clock
ADSC
ADIF
ADCH
ADCL
Cycle number 1 2
One conversion Next conversion
3
Sample & hold
MUX and REFS
update
Conversion
complete MUX and REFS
update312
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Figure 26-6. ADC timing diagram, auto triggered conversion.
Figure 26-7. ADC timing diagram, free running conversion.
26.5.1 Differential channels
When using differential channels, certain aspects of the conversion need to be taken into
consideration.
Differential conversions are synchronized to the internal clock CKADC2 equal to half the ADC
clock frequency. This synchronization is done automatically by the ADC interface in such a way
that the sample-and-hold occurs at a specific phase of CKADC2. A conversion initiated by the
user (that is, all single conversions, and the first free running conversion) when CKADC2 is low will
take the same amount of time as a single ended conversion (13 ADC clock cycles from the next
prescaled clock cycle). A conversion initiated by the user when CKADC2 is high will take 14 ADC
clock cycles due to the synchronization mechanism. In Free Running mode, a new conversion is
initiated immediately after the previous conversion completes, and since CKADC2 is high at this
time, all automatically started (that is, all but the first) Free Running conversions will take 14
ADC clock cycles.
Table 26-1. ADC conversion time.
Condition First conversion
Normal conversion,
single ended
Auto triggered
conversion
Sample & Hold
(Cycles from Start of Conversion) 14.5 1.5 2
Conversion Time
(Cycles) 25 13 13.5
1 2 3 4 5 6 7 8 9 10 11 12 13
Sign and MSB of result
LSB of result
ADC clock
Trigger
Source
ADIF
ADCH
ADCL
Cycle number 1 2
One conversion Next conversion
Conversion
complete Prescaler
reset
ADATE
Prescaler
reset
Sample &
hold
MUX and REFS
update
11 12 13
Sign and MSB of result
LSB of result
ADC clock
ADSC
ADIF
ADCH
ADCL
Cycle number 1 2
One conversion Next conversion
3 4
Conversion
complete
Sample & hold
MUX and REFS
update313
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If differential channels are used and conversions are started by Auto Triggering, the ADC must
be switched off between conversions. When Auto Triggering is used, the ADC prescaler is reset
before the conversion is started. Since the stage is dependent of a stable ADC clock prior to the
conversion, this conversion will not be valid. By disabling and then re-enabling the ADC between
each conversion (writing ADEN in ADCSRA to “0” then to “1”), only extended conversions are
performed. The result from the extended conversions will be valid. See “Prescaling and conversion
timing” on page 310 for timing details.
The gain stage is optimized for a bandwidth of 4kHz at all gain settings. Higher frequencies may
be subjected to non-linear amplification. An external low-pass filter should be used if the input
signal contains higher frequency components than the gain stage bandwidth. Note that the ADC
clock frequency is independent of the gain stage bandwidth limitation. For example, the ADC
clock period may be 6µs, allowing a channel to be sampled at 12ksps, regardless of the bandwidth
of this channel.
26.6 Changing channel or reference selection
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary
register to which the CPU has random access. This ensures that the channels and reference
selection only takes place at a safe point during the conversion. The channel and reference
selection is continuously updated until a conversion is started. Once the conversion starts, the
channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Continuous
updating resumes in the last ADC clock cycle before the conversion completes (ADIF in
ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after
ADSC is written. The user is thus advised not to write new channel or reference selection values
to ADMUX until one ADC clock cycle after ADSC is written.
If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special
care must be taken when updating the ADMUX Register, in order to control which conversion
will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the
ADMUX Register is changed in this period, the user cannot tell if the next conversion is based
on the old or the new settings. ADMUX can be safely updated in the following ways:
a. When ADATE or ADEN is cleared.
b. During conversion, minimum one ADC clock cycle after the trigger event.
c. After a conversion, before the interrupt flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next ADC
conversion.
Special care should be taken when changing differential channels. Once a differential channel
has been selected, the stage may take as much as 125µs to stabilize to the new value. Thus
conversions should not be started within the first 125µs after selecting a new differential channel.
Alternatively, conversion results obtained within this period should be discarded.
The same settling time should be observed for the first differential conversion after changing
ADC reference (by changing the REFS1:0 bits in ADMUX).
The settling time and gain stage bandwidth is independent of the ADHSM bit setting.314
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26.6.1 ADC input channels
When changing channel selections, the user should observe the following guidelines to ensure
that the correct channel is selected:
• In Single Conversion mode, always select the channel before starting the conversion. The
channel selection may be changed one ADC clock cycle after writing one to ADSC. However,
the simplest method is to wait for the conversion to complete before changing the channel
selection
• In Free Running mode, always select the channel before starting the first conversion. The
channel selection may be changed one ADC clock cycle after writing one to ADSC. However,
the simplest method is to wait for the first conversion to complete, and then change the
channel selection. Since the next conversion has already started automatically, the next
result will reflect the previous channel selection. Subsequent conversions will reflect the new
channel selection
When switching to a differential gain channel, the first conversion result may have a poor accuracy
due to the required settling time for the automatic offset cancellation circuitry. The user
should preferably disregard the first conversion result.
26.6.2 ADC voltage reference
The reference voltage for the ADC (VREF) indicates the conversion range for the ADC. Single
ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as
either AVCC, internal 2.56V reference, or external AREF pin.
AVCC is connected to the ADC through a passive switch. The internal 2.56V reference is generated
from the internal bandgap reference (VBG) through an internal amplifier. In either case, the
external AREF pin is directly connected to the ADC, and the reference voltage can be made
more immune to noise by connecting a capacitor between the AREF pin and ground. VREF can
also be measured at the AREF pin with a high impedant voltmeter. Note that VREF is a high
impedant source, and only a capacitive load should be connected in a system.
If the user has a fixed voltage source connected to the AREF pin, the user may not use the other
reference voltage options in the application, as they will be shorted to the external voltage. If no
external voltage is applied to the AREF pin, the user may switch between AVCC and 2.56V as
reference selection. The first ADC conversion result after switching reference voltage source
may be inaccurate, and the user is advised to discard this result.
If differential channels are used, the selected reference should not be closer to AVCC than indicated
in Table 31-5 on page 397.
26.7 ADC noise canceler
The ADC features a noise canceler that enables conversion during sleep mode to reduce noise
induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC
Noise Reduction and Idle mode. To make use of this feature, the following procedure should be
used:315
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a. Make sure that the ADC is enabled and is not busy converting. Single Conversion
mode must be selected and the ADC conversion complete interrupt must be
enabled.
b. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion
once the CPU has been halted.
c. If no other interrupts occur before the ADC conversion completes, the ADC interrupt
will wake up the CPU and execute the ADC Conversion Complete interrupt
routine. If another interrupt wakes up the CPU before the ADC conversion is complete,
that interrupt will be executed, and an ADC Conversion Complete interrupt
request will be generated when the ADC conversion completes. The CPU will
remain in active mode until a new sleep command is executed.
Note that the ADC will not be automatically turned off when entering other sleep modes than Idle
mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before entering
such sleep modes to avoid excessive power consumption.
If the ADC is enabled in such sleep modes and the user wants to perform differential conversions,
the user is advised to switch the ADC off and on after waking up from sleep to prompt an
extended conversion to get a valid result.
26.7.1 Analog input circuitry
The analog input circuitry for single ended channels is illustrated in Figure 26-8. An analog
source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless
of whether that channel is selected as input for the ADC. When the channel is selected, the
source must drive the S/H capacitor through the series resistance (combined resistance in the
input path).
The ADC is optimized for analog signals with an output impedance of approximately 10kΩ or
less. If such a source is used, the sampling time will be negligible. If a source with higher impedance
is used, the sampling time will depend on how long time the source needs to charge the
S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources
with slowly varying signals, since this minimizes the required charge transfer to the S/H
capacitor.
If differential gain channels are used, the input circuitry looks somewhat different, although
source impedances of a few hundred kΩ or less is recommended.
Signal components higher than the Nyquist frequency (fADC/2) should not be present for either
kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised
to remove high frequency components with a low-pass filter before applying the signals as
inputs to the ADC.
Figure 26-8. Analog input circuitry.
ADCn
I
IH
1..100kΩ
CS/H= 14pF
VCC/2
I
IL316
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26.7.2 Analog noise canceling techniques
Digital circuitry inside and outside the device generates EMI which might affect the accuracy of
analog measurements. If conversion accuracy is critical, the noise level can be reduced by
applying the following techniques:
a. Keep analog signal paths as short as possible. Make sure analog tracks run over
the analog ground plane, and keep them well away from high-speed switching digital
tracks.
b. The AVCC pin on the device should be connected to the digital VCC supply voltage
via an LC network as shown in Figure 26-9.
c. Use the ADC noise canceler function to reduce induced noise from the CPU.
d. If any ADC port pins are used as digital outputs, it is essential that these do not
switch while a conversion is in progress.
Figure 26-9. ADC power connections.
26.7.3 Offset compensation schemes
The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements
as much as possible. The remaining offset in the analog path can be measured
directly by selecting the same channel for both differential inputs. This offset residue can be then
subtracted in software from the measurement results. Using this kind of software based offset
correction, offset on any channel can be reduced below one LSB.
26.7.4 ADC accuracy definitions
An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps
(LSBs). The lowest code is read as 0, and the highest code is read as 2n
-1.
Several parameters describe the deviation from the ideal behavior:
VCC
GND
100nF
Analog ground plane
(ADC0) PF0
(ADC7) PF7
(ADC1) PF1
(ADC2) PF2
(ADC3) PF3
(ADC4) PF4
(ADC5) PF5
(ADC6) PF6
AREF
GND
AVCC
52
53
54
55
56
57
58
59
60
61
62
63
64
1
51
NC
(AD0) PA0
10μH317
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• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition
(at 0.5 LSB). Ideal value: 0 LSB
Figure 26-10. Offset error.
• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last
transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum).
Ideal value: 0 LSB
Figure 26-11. Gain error.
• Integral non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum
deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0
LSB
Output code
VREF Input voltage
Ideal ADC
Actual ADC
Offset
error
Output code
VREF Input voltage
Ideal ADC
Actual ADC
Gain
error318
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Figure 26-12. Integral non-linearity (INL).
• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval
between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB
Figure 26-13. Differential non-linearity (DNL).
• Quantization Error: Due to the quantization of the input voltage into a finite number of codes,
a range of input voltages (1 LSB wide) will code to the same value. Always ±0.5 LSB.
• Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to
an ideal transition for any code. This is the compound effect of offset, gain error, differential
error, non-linearity, and quantization error. Ideal value: ±0.5 LSB.
26.8 ADC conversion result
After the conversion is complete (ADIF is high), the conversion result can be found in the ADC
Result Registers (ADCL, ADCH).
Output code
VREF Input voltage
Ideal ADC
Actual ADC
INL
Output code
0x3FF
0x000
0 VREF Input voltage
DNL
1 LSB319
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For single ended conversion, the result is:
where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see
Table 26-3 on page 322 and Table 26-4 on page 322). 0x000 represents analog ground, and
0x3FF represents the selected reference voltage minus one LSB.
If differential channels are used, the result is:
where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative input pin,
GAIN the selected gain factor and VREF the selected voltage reference. The result is presented
in two’s complement form, from 0x200 (-512d) through 0x1FF (+511d). Note that if the user
wants to perform a quick polarity check of the result, it is sufficient to read the MSB of the result
(ADC9 in ADCH). If the bit is one, the result is negative, and if this bit is zero, the result is positive.
Figure 26-14 shows the decoding of the differential input range.
Table 82 shows the resulting output codes if the differential input channel pair (ADCn - ADCm) is
selected with a reference voltage of VREF.
ADC
VIN ⋅ 1024
VREF
= --------------------------
ADC
VPOS VNEG ( ) – ⋅ ⋅ GAIN 512
VREF
= ------------------------------------------------------------------------320
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Figure 26-14. Differential measurement range.
0
Output code
0x1FF
0x000
VREF Differential input
voltage (volts)
0x3FF
0x200
- VREF321
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Example 1:
– ADMUX = 0xED (ADC3 - ADC2, 10× gain, 2.56V reference, left adjusted result)
– Voltage on ADC3 is 300mV, voltage on ADC2 is 500mV.
– ADCR = 512 × 10 × (300 - 500) / 2560 = -400 = 0x270
– ADCL will thus read 0x00, and ADCH will read 0x9C.
Writing zero to ADLAR right adjusts the result: ADCL = 0x70, ADCH = 0x02.
Example 2:
– ADMUX = 0xFB (ADC3 - ADC2, 1× gain, 2.56V reference, left adjusted result)
– Voltage on ADC3 is 300mV, voltage on ADC2 is 500mV.
– ADCR = 512 × 1 × (300 - 500) / 2560 = -41 = 0x029.
– ADCL will thus read 0x40, and ADCH will read 0x0A.
Writing zero to ADLAR right adjusts the result: ADCL = 0x00, ADCH = 0x29.
26.9 ADC register description
26.9.1 ADMUX – ADC Multiplexer Selection Register
• Bit 7:6 – REFS1:0: Reference Selection bits
These bits select the voltage reference for the ADC, as shown in Table 26-3 on page 322. If
these bits are changed during a conversion, the change will not go in effect until this conversion
Table 26-2. Correlation between input voltage and output codes.
VADCn Read code Corresponding decimal value
VADCm + VREF /GAIN 0x1FF 511
VADCm + 0.999 VREF /GAIN 0x1FF 511
VADCm + 0.998 VREF /GAIN 0x1FE 510
... ... ...
VADCm + 0.001 VREF /GAIN 0x001 1
VADCm 0x000 0
VADCm - 0.001 VREF /GAIN 0x3FF -1
... ... ...
VADCm - 0.999 VREF /GAIN 0x201 -511
VADCm - VREF /GAIN 0x200 -512
Bit 7 6 5 4 3 2 1 0
REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 ADMUX
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0322
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is complete (ADIF in ADCSRA is set). The internal voltage reference options may not be used if
an external reference voltage is being applied to the AREF pin.
• Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the
ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conversions.
For a complete description of this bit, see “ADCL and ADCH – The ADC data register” on
page 324.
• Bits 4:0 – MUX4:0: Analog Channel Selection bits
The value of these bits selects which combination of analog inputs are connected to the ADC.
These bits also select the gain for the differential channels. See Table 26-4 for details. If these
bits are changed during a conversion, the change will not go in effect until this conversion is
complete (ADIF in ADCSRA is set).
Table 26-3. Voltage reference selections for ADC.
REFS1 REFS0 Voltage reference selection
0 0 AREF, internal VREF turned off
0 1 AVCC with external capacitor on AREF pin
1 0 Reserved
1 1 Internal 2.56V Voltage Reference with external capacitor on AREF pin
Table 26-4. Input channel and gain selections.
MUX4..0 Single ended input Positive differential input Negative differential input Gain
00000 ADC0
N/A
00001 ADC1
00010 ADC2
00011 ADC3
00100 ADC4
00101 ADC5
00110 ADC6
00111 ADC7323
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26.9.2 ADCSRA – ADC Control and Status Register A
• Bit 7 – ADEN: ADC Enable
Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the
ADC off while a conversion is in progress, will terminate this conversion.
• Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode,
write this bit to one to start the first conversion. The first conversion after ADSC has been written
after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled,
01000
N/A
(ADC0 / ADC0 / 10x)
01001 ADC1 ADC0 10×
01010 (ADC0 / ADC0 / 200x)
01011 ADC1 ADC0 200×
01100 (Reserved - ADC2 / ADC2 / 10x)
01101 ADC3 ADC2 10×
01110 (ADC2 / ADC2 / 200x)
01111 ADC3 ADC2 200×
10000 ADC0 ADC1 1×
10001 (ADC1 / ADC1 / 1x)
10010 ADC2 ADC1 1×
10011 ADC3 ADC1 1×
10100 ADC4 ADC1 1×
10101 ADC5 ADC1 1×
10110 ADC6 ADC1 1×
10111 ADC7 ADC1 1×
11000 ADC0 ADC2 1×
11001 ADC1 ADC2 1×
11010 (ADC2 / ADC2 / 1x)
11011 ADC3 ADC2 1×
11100 ADC4 ADC2 1×
11101 ADC5 ADC2 1×
11110 1.1V (VBand Gap) N/A
11111 0V (GND)
Table 26-4. Input channel and gain selections. (Continued)
MUX4..0 Single ended input Positive differential input Negative differential input Gain
Bit 7 6 5 4 3 2 1 0
ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSRA
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0324
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will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initialization
of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is complete,
it returns to zero. Writing zero to this bit has no effect.
• Bit 5 – ADATE: ADC Auto Trigger Enable
When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion
on a positive edge of the selected trigger signal. The trigger source is selected by setting
the ADC Trigger Select bits, ADTS in ADCSRB.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the Data Registers are updated. The
ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set.
ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively,
ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-ModifyWrite
on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI
instructions are used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt
is activated.
• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the XTAL frequency and the input clock to the
ADC.
26.9.3 ADCL and ADCH – The ADC data register
26.9.3.1 ADLAR = 0
Table 26-5. ADC prescaler selections.
ADPS2 ADPS1 ADPS0 Division factor
000 2
001 2
010 4
011 8
1 0 0 16
1 0 1 32
1 1 0 64
1 1 1 128
Bit 15 14 13 12 11 10 9 8
– – – – – – ADC9 ADC8 ADCH
ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL
Bit 7 6 5 4 3 2 1 0
Read/write R R R R R R R R
RRRRRRRR
Initial value 0 0 0 0 0 0 0 0
00000000325
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26.9.3.2 ADLAR = 1
When an ADC conversion is complete, the result is found in these two registers. If differential
channels are used, the result is presented in two’s complement form.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision (7 bit + sign bit for differential input
channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then
ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in “ADC conversion result” on
page 318.
26.9.4 ADCSRB – ADC Control and Status Register B
• Bit 7 – ADHSM: ADC High Speed Mode
Writing this bit to one enables the ADC High Speed mode. This mode enables higher conversion
rate at the expense of higher power consumption.
• Bit 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion
will be triggered by the rising edge of the selected interrupt flag. Note that switching from a trigger
source that is cleared to a trigger source that is set, will generate a positive edge on the
trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running
mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set.
Bit 15 14 13 12 11 10 9 8
ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH
ADC1 ADC0 – ––––– ADCL
Bit 7 6 5 4 3 2 1 0
Read/write R R R R R R R R
RRRRRRRR
Initial value 0 0 0 0 0 0 0 0
00000000
Bit 7 6 5 4 3 2 1 0
ADHSM ACME – – – ADTS2 ADTS1 ADTS0 ADCSRB
Read/write R/W R/W R R R R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Table 26-6. ADC auto trigger source selections.
ADTS2 ADTS1 ADTS0 Trigger source
0 0 0 Free running mode
0 0 1 Analog comparator
0 1 0 External interrupt request 0
0 1 1 Timer/Counter0 compare match326
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26.9.5 DIDR0 – Digital Input Disable Register 0
• Bit 7:0 – ADC7D..ADC0D: ADC7:0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled.
The corresponding PIN Register bit will always read as zero when this bit is set. When an
analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this
bit should be written logic one to reduce power consumption in the digital input buffer.
1 0 0 Timer/Counter0 overflow
1 0 1 Timer/Counter1 compare match B
1 1 0 Timer/Counter1 overflow
1 1 1 Timer/Counter1 capture event
Table 26-6. ADC auto trigger source selections. (Continued)
ADTS2 ADTS1 ADTS0 Trigger source
Bit 7 6 5 4 3 2 1 0
ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D DIDR0
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0327
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27. JTAG interface and on-chip debug system
27.0.1 Features
• JTAG (IEEE std. 1149.1 compliant) interface
• Boundary-scan capabilities according to the IEEE std. 1149.1 (JTAG) standard
• Debugger access to:
– All internal peripheral units
– Internal and external RAM
– The internal register file
– Program counter
– EEPROM and flash memories
• Extensive on-chip debug support for break conditions, including
– AVR break instruction
– Break on change of program memory flow
– Single step break
– Program memory break points on single address or address range
– Data memory break points on single address or address range
• Programming of flash, EEPROM, fuses, and lock bits through the JTAG interface
• On-chip debugging supported by Atmel AVR Studio®
27.1 Overview
The AVR IEEE std. 1149.1 compliant JTAG interface can be used for
• Testing PCBs by using the JTAG Boundary-scan capability
• Programming the non-volatile memories, Fuses and Lock bits
• On-chip debugging
A brief description is given in the following sections. Detailed descriptions for Programming via
the JTAG interface, and using the Boundary-scan Chain can be found in the sections “Programming
via the JTAG interface” on page 377 and “IEEE 1149.1 (JTAG) boundary-scan” on page
333, respectively. The On-chip Debug support is considered being private JTAG instructions,
and distributed within Atmel and to selected third party vendors only.
Figure 27-1 on page 328 shows a block diagram of the JTAG interface and the On-chip Debug
system. The TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP
Controller selects either the JTAG Instruction Register or one of several Data Registers as the
scan chain (Shift Register) between the TDI – input and TDO – output. The Instruction Register
holds JTAG instructions controlling the behavior of a Data Register.
The ID-Register, Bypass Register, and the Boundary-scan Chain are the Data Registers used
for board-level testing. The JTAG Programming Interface (actually consisting of several physical
and virtual Data Registers) is used for serial programming via the JTAG interface. The Internal
Scan Chain and Break Point Scan Chain are used for On-chip debugging only.
27.2 TAP – Test Access Port
The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins
constitute the Test Access Port – TAP. These pins are:
• TMS: Test mode select. This pin is used for navigating through the TAP-controller state
machine
• TCK: Test Clock. JTAG operation is synchronous to TCK328
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• TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register
(Scan Chains)
• TDO: Test Data Out. Serial output data from Instruction Register or Data Register
The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not
provided.
When the JTAGEN Fuse is unprogrammed, these four TAP pins are normal port pins, and the
TAP controller is in reset. When programmed, the input TAP signals are internally pulled high
and the JTAG is enabled for Boundary-scan and programming. The device is shipped with this
fuse programmed.
For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is monitored
by the debugger to be able to detect external reset sources. The debugger can also pull
the RESET pin low to reset the whole system, assuming only open collectors on the reset line
are used in the application.
Figure 27-1. Block diagram.
TAP
CONTROLLER
TDI
TDO
TCK
TMS
FLASH
MEMORY
AVR CPU
DIGITAL
PERIPHERAL
UNITS
JTAG / AVR CORE
COMMUNICATION
INTERFACE
BREAKPOINT
UNIT FLOW CONTROL
UNIT
OCD STATUS
AND CONTROL
INTERNAL
SCAN
CHAIN
M
U
X
INSTRUCTION
REGISTER
ID
REGISTER
BYPASS
REGISTER
JTAG PROGRAMMING
INTERFACE
PC
Instruction
Address
Data
BREAKPOINT
SCAN CHAIN
ADDRESS
DECODER
ANALOG
PERIPHERIAL
UNITS
I/O PORT 0
I/O PORT n
BOUNDARY SCAN CHAIN
Analog inputs
Control & clock lines
DEVICE BOUNDARY329
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Figure 27-2. TAP controller state diagram.
27.3 TAP Controller
The TAP Controller is a 16-state finite state machine that controls the operation of the Boundaryscan
circuitry, JTAG programming circuitry, or On-chip Debug system. The state transitions
depicted in Figure 27-2 depend on the signal present on TMS (shown adjacent to each state
transition) at the time of the rising edge at TCK. The initial state after a Power-on Reset is TestLogic-Reset.
As a definition in this document, the LSB is shifted in and out first for all Shift Registers.
Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is:
• At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift
Instruction Register – Shift-IR state. While in this state, shift the four bits of the JTAG
instructions into the JTAG Instruction Register from the TDI input at the rising edge of TCK.
The TMS input must be held low during input of the three LSBs in order to remain in the ShiftIR
state. The MSB of the instruction is shifted in when this state is left by setting TMS high.
While the instruction is shifted in from the TDI pin, the captured IR-state 0x01 is shifted out on
the TDO pin. The JTAG Instruction selects a particular Data Register as path between TDI
and TDO and controls the circuitry surrounding the selected Data Register
Test-logic-reset
Run-test/idle
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Update-IR
Select-DR scan
Capture-DR
0
1
0 11 1
0 0
0 0
1 1
1 0
1
1
0
1
0
0
1 0
1
1
0
1
0
0
0 0
1 1330
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• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched
onto the parallel output from the Shift Register path in the Update-IR state. The Exit-IR,
Pause-IR, and Exit2-IR states are only used for navigating the state machine
• At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift
Data Register – Shift-DR state. While in this state, upload the selected Data Register
(selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI input
at the rising edge of TCK. In order to remain in the Shift-DR state, the TMS input must be
held low during input of all bits except the MSB. The MSB of the data is shifted in when this
state is left by setting TMS high. While the Data Register is shifted in from the TDI pin, the
parallel inputs to the Data Register captured in the Capture-DR state is shifted out on the
TDO pin
• Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data
Register has a latched parallel-output, the latching takes place in the Update-DR state. The
Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating the state machine
As shown in the state diagram, the Run-Test/Idle state need not be entered between selecting
JTAG instruction and using Data Registers, and some JTAG instructions may select certain
functions to be performed in the Run-Test/Idle, making it unsuitable as an Idle state.
Note: Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be
entered by holding TMS high for five TCK clock periods.
For detailed information on the JTAG specification, refer to the literature listed in “Bibliography”
on page 332.
27.4 Using the Boundary-scan chain
A complete description of the Boundary-scan capabilities are given in the section “IEEE 1149.1
(JTAG) boundary-scan” on page 333.
27.5 Using the on-chip debug system
As shown in Figure 27-1 on page 328, the hardware support for on-chip debugging consists
mainly of
• A scan chain on the interface between the internal AVR CPU and the internal peripheral units
• Break Point unit
• Communication interface between the CPU and JTAG system
All read or modify/write operations needed for implementing the Debugger are done by applying
AVR instructions via the internal AVR CPU Scan Chain. The CPU sends the result to an I/O
memory mapped location which is part of the communication interface between the CPU and the
JTAG system.
The Break Point Unit implements Break on Change of Program Flow, Single Step Break, two
Program Memory Break Points, and two combined Break Points. Together, the four Break
Points can be configured as either:
• Four single program memory break points
• Three single program memory break point + one single data memory break point
• Two single program memory break points + two single data memory break points
• Two single program memory break points + one program memory break point with mask
(“range Break Point”)331
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• Two single program memory break points + one data memory break point with mask (“range
Break Point”)
A debugger, like the Atmel AVR Studio, may however use one or more of these resources for its
internal purpose, leaving less flexibility to the end-user.
A list of the On-chip Debug specific JTAG instructions is given in “On-chip debug specific JTAG
instructions” on page 331.
The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the
OCDEN Fuse must be programmed and no Lock bits must be set for the On-chip debug system
to work. As a security feature, the On-chip debug system is disabled when either of the LB1 or
LB2 Lock bits are set. Otherwise, the On-chip debug system would have provided a back-door
into a secured device.
The AVR Studio enables the user to fully control execution of programs on an AVR device with
On-chip Debug capability, AVR In-Circuit Emulator, or the built-in AVR Instruction Set Simulator.
AVR Studio supports source level execution of Assembly programs assembled with Atmel Corporation’s
AVR Assembler and C programs compiled with third party vendors’ compilers.
AVR Studio runs under Microsoft® Windows® 95/98/2000 and Microsoft Windows NT.
For a full description of the Atmel AVR Studio, please refer to the AVR Studio User Guide. Only
highlights are presented in this document.
All necessary execution commands are available in AVR Studio, both on source level and on
disassembly level. The user can execute the program, single step through the code either by
tracing into or stepping over functions, step out of functions, place the cursor on a statement and
execute until the statement is reached, stop the execution, and reset the execution target. In
addition, the user can have an unlimited number of code Break Points (using the BREAK
instruction) and up to two data memory Break Points, alternatively combined as a mask (range)
Break Point.
27.6 On-chip debug specific JTAG instructions
The On-chip debug support is considered being private JTAG instructions, and distributed within
ATMEL and to selected third party vendors only. Instruction opcodes are listed for reference.
27.6.1 PRIVATE0; 0x8
Private JTAG instruction for accessing On-chip debug system.
27.6.2 PRIVATE1; 0x9
Private JTAG instruction for accessing On-chip debug system.
27.6.3 PRIVATE2; 0xA
Private JTAG instruction for accessing On-chip debug system.
27.6.4 PRIVATE3; 0xB
Private JTAG instruction for accessing On-chip debug system.332
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27.7 On-chip Debug related Register in I/O memory
27.7.1 OCDR – On-chip Debug Register
The OCDR Register provides a communication channel from the running program in the microcontroller
to the debugger. The CPU can transfer a byte to the debugger by writing to this
location. At the same time, an internal flag; I/O Debug Register Dirty – IDRD – is set to indicate
to the debugger that the register has been written. When the CPU reads the OCDR Register the
seven LSB will be from the OCDR Register, while the MSB is the IDRD bit. The debugger clears
the IDRD bit when it has read the information.
In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR
Register can only be accessed if the OCDEN Fuse is programmed, and the debugger enables
access to the OCDR Register. In all other cases, the standard I/O location is accessed.
Refer to the debugger documentation for further information on how to use this register.
27.8 Using the JTAG programming capabilities
Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS, TDI, and
TDO. These are the only pins that need to be controlled/observed to perform JTAG programming
(in addition to power pins). It is not required to apply 12V externally. The JTAGEN Fuse
must be programmed and the JTD bit in the MCUCR Register must be cleared to enable the
JTAG Test Access Port.
The JTAG programming capability supports:
• Flash programming and verifying
• EEPROM programming and verifying
• Fuse programming and verifying
• Lock bit programming and verifying
The Lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or LB2 are
programmed, the OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a
security feature that ensures no back-door exists for reading out the content of a secured
device.
The details on programming through the JTAG interface and programming specific JTAG
instructions are given in the section “Programming via the JTAG interface” on page 377.
27.9 Bibliography
For more information about general Boundary-scan, the following literature can be consulted:
• IEEE: IEEE Std. 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan
Architecture, IEEE, 1993.
• Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-Wesley,
1992.
Bit 7 6 5 4 3 2 1 0
MSB/IDRD LSB OCDR
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0333
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28. IEEE 1149.1 (JTAG) boundary-scan
28.1 Features
• JTAG (IEEE std. 1149.1 compliant) interface
• Boundary-scan capabilities according to the JTAG standard
• Full scan of all port functions as well as analog circuitry having off-chip connections
• Supports the optional IDCODE instruction
• Additional public AVR_RESET instruction to reset the AVR
28.2 System overview
The Boundary-scan chain has the capability of driving and observing the logic levels on the digital
I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by
the TDI/TDO signals to form a long Shift Register. An external controller sets up the devices to
drive values at their output pins, and observe the input values received from other devices. The
controller compares the received data with the expected result. In this way, Boundary-scan provides
a mechanism for testing interconnections and integrity of components on Printed Circuits
Boards by using the four TAP signals only.
The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRELOAD,
and EXTEST, as well as the AVR specific public JTAG instruction AVR_RESET can be
used for testing the Printed Circuit Board. Initial scanning of the Data Register path will show the
ID-Code of the device, since IDCODE is the default JTAG instruction. It may be desirable to
have the AVR device in reset during test mode. If not reset, inputs to the device may be determined
by the scan operations, and the internal software may be in an undetermined state when
exiting the test mode. Entering reset, the outputs of any port pin will instantly enter the high
impedance state, making the HIGHZ instruction redundant. If needed, the BYPASS instruction
can be issued to make the shortest possible scan chain through the device. The device can be
set in the reset state either by pulling the external RESET pin low, or issuing the AVR_RESET
instruction with appropriate setting of the Reset Data Register.
The EXTEST instruction is used for sampling external pins and loading output pins with data.
The data from the output latch will be driven out on the pins as soon as the EXTEST instruction
is loaded into the JTAG IR-Register. Therefore, the SAMPLE/PRELOAD should also be used for
setting initial values to the scan ring, to avoid damaging the board when issuing the EXTEST
instruction for the first time. SAMPLE/PRELOAD can also be used for taking a snapshot of the
external pins during normal operation of the part.
The JTAGEN Fuse must be programmed and the JTD bit in the I/O Register MCUCR must be
cleared to enable the JTAG Test Access Port.
When using the JTAG interface for Boundary-scan, using a JTAG TCK clock frequency higher
than the internal chip frequency is possible. The chip clock is not required to run.
28.3 Data registers
The Data Registers relevant for Boundary-scan operations are:
• Bypass Register
• Device Identification Register
• Reset Register
• Boundary-scan Chain334
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28.3.1 Bypass register
The Bypass register consists of a single Shift register stage. When the Bypass register is
selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR
controller state. The Bypass register can be used to shorten the scan chain on a system when
the other devices are to be tested.
28.3.2 Device Identification register
Figure 28-1 shows the structure of the Device Identification register.
Figure 28-1. The Format of the Device Identification register.
28.3.2.1 Version
Version is a 4-bit number identifying the revision of the component. The JTAG version number
follows the revision of the device. Revision A is 0x0, revision B is 0x1 and so on.
28.3.2.2 Part number
The part number is a 16-bit code identifying the component. The JTAG Part Number for Atmel
AT90USB64/128 is listed in Table 28-1.
28.3.2.3 Manufacturer ID
The Manufacturer ID is a 11-bit code identifying the manufacturer. The JTAG manufacturer ID
for ATMEL is listed in Table 28-2.
28.3.3 Reset register
The Reset Register is a test Data Register used to reset the part. Since the AVR tri-states Port
Pins when reset, the Reset Register can also replace the function of the un-implemented
optional JTAG instruction HIGHZ.
A high value in the Reset Register corresponds to pulling the external Reset low. The part is
reset as long as there is a high value present in the Reset Register. Depending on the fuse settings
for the clock options, the part will remain reset for a reset time-out period (refer to “Clock
sources” on page 41) after releasing the Reset Register. The output from this Data Register is
not latched, so the reset will take place immediately, as shown in Figure 28-2 on page 335.
MSB LSB
Bit 31 28 27 12 11 1 0
Device ID Version Part number Manufacturer ID 1
4 bits 16 bits 11 bits 1-bit
Table 28-1. AVR JTAG part number.
Part number JTAG part number (hex)
AVR USB 0x9782
Table 28-2. Manufacturer ID.
Manufacturer JTAG manufacturer ID (hex)
ATMEL 0x01F335
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Figure 28-2. Reset register.
28.3.4 Boundary-scan Chain
The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital
I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
off-chip connections.
See “Boundary-scan chain” on page 337 for a complete description.
28.4 Boundary-scan specific JTAG instructions
The Instruction Register is 4-bit wide, supporting up to 16 instructions. Listed below are the
JTAG instructions useful for Boundary-scan operation. Note that the optional HIGHZ instruction
is not implemented, but all outputs with tri-state capability can be set in high-impedant state by
using the AVR_RESET instruction, since the initial state for all port pins is tri-state.
As a definition in this datasheet, the LSB is shifted in and out first for all Shift Registers.
The OPCODE for each instruction is shown behind the instruction name in hex format. The text
describes which Data Register is selected as path between TDI and TDO for each instruction.
28.4.1 EXTEST; 0x0
Mandatory JTAG instruction for selecting the Boundary-scan Chain as Data Register for testing
circuitry external to the AVR package. For port-pins, Pull-up Disable, Output Control, Output
Data, and Input Data are all accessible in the scan chain. For Analog circuits having off-chip
connections, the interface between the analog and the digital logic is in the scan chain. The contents
of the latched outputs of the Boundary-scan chain is driven out as soon as the JTAG IRRegister
is loaded with the EXTEST instruction.
The active states are:
• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain
• Shift-DR: The Internal Scan Chain is shifted by the TCK input
• Update-DR: Data from the scan chain is applied to output pins
28.4.2 IDCODE; 0x1
Optional JTAG instruction selecting the 32-bit ID-Register as Data Register. The ID-Register
consists of a version number, a device number and the manufacturer code chosen by JEDEC.
This is the default instruction after power-up.
D Q From
TDI
ClockDR · AVR_RESET
To
TDO
From other internal and
external reset sources
Internal reset336
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The active states are:
• Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain
• Shift-DR: The IDCODE scan chain is shifted by the TCK input
28.4.3 SAMPLE_PRELOAD; 0x2
Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the
input/output pins without affecting the system operation. However, the output latches are not
connected to the pins. The Boundary-scan Chain is selected as Data Register.
The active states are:
• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain
• Shift-DR: The Boundary-scan Chain is shifted by the TCK input
• Update-DR: Data from the Boundary-scan chain is applied to the output latches. However,
the output latches are not connected to the pins
28.4.4 AVR_RESET; 0xC
The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or
releasing the JTAG reset source. The TAP controller is not reset by this instruction. The one bit
Reset Register is selected as Data Register. Note that the reset will be active as long as there is
a logic “one” in the Reset Chain. The output from this chain is not latched.
The active states are:
• Shift-DR: The Reset Register is shifted by the TCK input
28.4.5 BYPASS; 0xF
Mandatory JTAG instruction selecting the Bypass Register for Data Register.
The active states are:
• Capture-DR: Loads a logic “0” into the Bypass Register
• Shift-DR: The Bypass Register cell between TDI and TDO is shifted
28.5 Boundary-scan Related Register in I/O memory
28.5.1 MCUCR – MCU Control Register
The MCU Control Register contains control bits for general MCU functions.
• Bits 7 – JTD: JTAG Interface Disable
When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this
bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of
the JTAG interface, a timed sequence must be followed when changing this bit: The application
software must write this bit to the desired value twice within four cycles to change its value. Note
that this bit must not be altered when using the On-chip Debug system.
Bit 7 6 5 4 3 2 1 0
JTD – – PUD – – IVSEL IVCE MCUCR
Read/write R/W R R R/W R R R/W R/W
Initial value 0 0 0 0 0 0 0 0337
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28.5.2 MCUSR – MCU Status Register
The MCU Status Register provides information on which reset source caused an MCU reset.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by
the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic
zero to the flag.
28.6 Boundary-scan chain
The Boundary-scan chain has the capability of driving and observing the logic levels on the digital
I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
off-chip connection.
28.6.1 Scanning the digital port pins
Figure 28-3 on page 338 shows the Boundary-scan Cell for a bi-directional port pin. The pull-up
function is disabled during Boundary-scan when the JTAG IC contains EXTEST or
SAMPLE_PRELOAD. The cell consists of a bi-directional pin cell that combines the three signals
Output Control - OCxn, Output Data - ODxn, and Input Data - IDxn, into only a two-stage
Shift Register. The port and pin indexes are not used in the following description
The Boundary-scan logic is not included in the figures in the datasheet. Figure 28-4 on page 339
shows a simple digital port pin as described in the section “I/O-ports” on page 71. The Boundaryscan
details from Figure 28-3 on page 338 replaces the dashed box in Figure 28-4 on page 339.
When no alternate port function is present, the Input Data - ID - corresponds to the PINxn Register
value (but ID has no synchronizer), Output Data corresponds to the PORT Register, Output
Control corresponds to the Data Direction - DD Register, and the Pull-up Enable - PUExn - corresponds
to logic expression PUD · DDxn · PORTxn.
Digital alternate port functions are connected outside the dotted box in Figure 28-4 on page 339
to make the scan chain read the actual pin value. For analog function, there is a direct connection
from the external pin to the analog circuit. There is no scan chain on the interface between
the digital and the analog circuitry, but some digital control signal to analog circuitry are turned
off to avoid driving contention on the pads.
When JTAG IR contains EXTEST or SAMPLE_PRELOAD the clock is not sent out on the port
pins even if the CKOUT fuse is programmed. Even though the clock is output when the JTAG IR
contains SAMPLE_PRELOAD, the clock is not sampled by the boundary scan.
Bit 7 6 5 4 3 2 1 0
– – – JTRF WDRF BORF EXTRF PORF MCUSR
Read/write R R R R/W R/W R/W R/W R/W
Initial value 0 0 0 See bit description338
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Figure 28-3. Boundary-scan cell for bi-directional port pin with pull-up function.
D Q D Q
G
0
1 0
1
D Q D Q
G
0
1 0
1
0
1
Port Pin (PXn)
ShiftDR To next cell EXTEST Vcc
Output control (OC)
Output data (OD)
Input data (ID)
From last cell ClockDR UpdateDR
FF1 LD1
FF0 LD0
0
1
Pull-up enable (PUE)339
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Figure 28-4. General port pin schematic diagram.
28.6.2 Scanning the RESET pin
The RESET pin accepts 5V active low logic for standard reset operation, and 12V active high
logic for High Voltage Parallel programming. An observe-only cell as shown in Figure 28-5 is
inserted for the 5V reset signal.
Figure 28-5. Observe-only cell.
CLK
RPx
RRx
WRx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
PUD: PULLUP DISABLE
CLK : I/O CLOCK
RDx: READ DDRx
D
L
Q
Q
RESET
RESET
Q
D Q
Q
Q D
CLR
PORTxn
Q
Q D
CLR
DDxn
PINxn
DATA BUS
SLEEP
SLEEP: SLEEP CONTROL
Pxn
I/O
I/O
See Boundary-scan
description for details!
PUExn
OCxn
ODxn
IDxn
PUExn: PULLUP ENABLE for pin Pxn
OCxn: OUTPUT CONTROL for pin Pxn
ODxn: OUTPUT DATA to pin Pxn
IDxn: INPUT DATA from pin Pxn
0
1
D Q
From
previous
cell
ClockDR
ShiftDR
To
next
cell
From system pin To system logic
FF1340
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28.7 Atmel AT90USB64/128 Boundary-scan order
Table 28-3 shows the Scan order between TDI and TDO when the Boundary-scan chain is
selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The
scan order follows the pin-out order as far as possible. Therefore, the bits of Port A and Port Fis
scanned in the opposite bit order of the other ports. Exceptions from the rules are the Scan
chains for the analog circuits, which constitute the most significant bits of the scan chain regardless
of which physical pin they are connected to. In Figure 28-3 on page 338, PXn. Data
corresponds to FF0, PXn. Control corresponds to FF1, PXn. Bit 4, 5, 6 and 7 of Port F is not in
the scan chain, since these pins constitute the TAP pins when the JTAG is enabled. The USB
pads are not included in the boundary-scan.
Table 28-3. AT90USB64/128 Boundary-scan order.
Bit number Signal name Module
88 PE6.Data
Port E
87 PE6.Control
86 PE7.Data
85 PE7.Control
84 PE3.Data
83 PE3.Control
82 PB0.Data
Port B
81 PB0.Control
80 PB1.Data
79 PB1.Control
78 PB2.Data
77 PB2.Control
76 PB3.Data
75 PB3.Control
74 PB4.Data
73 PB4.Control
72 PB5.Data
71 PB5.Control
70 PB6.Data
69 PB6.Control
68 PB7.Data
67 PB7.Control
66 PE4.Data
PORTE
65 PE4.Control
64 PE5.Data
63 PE5.Control
62 RSTT Reset Logic (observe only)341
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61 PD0.Data
Port D
60 PD0.Control
59 PD1.Data
58 PD1.Control
57 PD2.Data
56 PD2.Control
55 PD3.Data
54 PD3.Control
53 PD4.Data
52 PD4.Control
51 PD5.Data
50 PD5.Control
49 PD6.Data
48 PD6.Control
47 PD7.Data
46 PD7.Control
45 PE0.Data
Port E
44 PE0.Control
43 PE1.Data
42 PE1.Control
41 PC0.Data
Port C
40 PC0.Control
39 PC1.Data
38 PC1.Control
37 PC2.Data
36 PC2.Control
35 PC3.Data
34 PC3.Control
33 PC4.Data
32 PC4.Control
31 PC5.Data
30 PC5.Control
29 PC6.Data
28 PC6.Control
27 PC7.Data
26 PC7.Control
Table 28-3. AT90USB64/128 Boundary-scan order. (Continued)
Bit number Signal name Module342
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28.8 Boundary-scan description language files
Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in
a standard format used by automated test-generation software. The order and function of bits in
the Boundary-scan Data Register are included in this description. BSDL files are available for
Atmel AT90USB64/128.
25 PE2.Data
Port E
24 PE2.Control
23 PA7.Data
Port A
22 PA7.Control
21 PA6.Data
20 PA6.Control
19 PA5.Data
18 PA5.Control
17 PA4.Data
16 PA4.Control
15 PA3.Data
14 PA3.Control
13 PA2.Data
12 PA2.Control
11 PA1.Data
10 PA1.Control
9 PA0.Data
8 PA0.Control
7 PF3.Data
Port F
6 PF3.Control
5 PF2.Data
4 PF2.Control
3 PF1.Data
2 PF1.Control
1 PF0.Data
0 PF0.Control
Table 28-3. AT90USB64/128 Boundary-scan order. (Continued)
Bit number Signal name Module343
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29. Boot Loader support – read-while-write self-programming
The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for
downloading and uploading program code by the MCU itself. This feature allows flexible application
software updates controlled by the MCU using a Flash-resident Boot Loader program. The
Boot Loader program can use any available data interface and associated protocol to read code
and write (program) that code into the Flash memory, or read the code from the program memory.
The program code within the Boot Loader section has the capability to write into the entire
Flash, including the Boot Loader memory. The Boot Loader can thus even modify itself, and it
can also erase itself from the code if the feature is not needed anymore. The size of the Boot
Loader memory is configurable with fuses and the Boot Loader has two separate sets of Boot
Lock bits which can be set independently. This gives the user a unique flexibility to select different
levels of protection. General information on SPM and ELPM is provided in See “AVR CPU
core” on page 11.
29.1 Boot Loader features
• Read-while-write self-programming
• Flexible boot memory size
• High security (separate boot lock bits for a flexible protection)
• Separate fuse to select reset vector
• Optimized page (1) size
• Code efficient algorithm
• Efficient read-modify-write support
Note: 1. A page is a section in the Flash consisting of several bytes (see Table 30-11 on page 364)
used during programming. The page organization does not affect normal operation.
29.2 Application and Boot Loader flash sections
The Flash memory is organized in two main sections, the Application section and the Boot
Loader section (see Figure 29-2 on page 346). The size of the different sections is configured by
the BOOTSZ Fuses as shown in Table 29-8 on page 357 and Figure 29-2 on page 346. These
two sections can have different level of protection since they have different sets of Lock bits.
29.2.1 Application section
The Application section is the section of the Flash that is used for storing the application code.
The protection level for the Application section can be selected by the application Boot Lock bits
(Boot Lock bits 0), see Table 29-2 on page 347. The Application section can never store any
Boot Loader code since the SPM instruction is disabled when executed from the Application
section.
29.2.2 BLS – Boot Loader section
While the Application section is used for storing the application code, the The Boot Loader software
must be located in the BLS since the SPM instruction can initiate a programming when
executing from the BLS only. The SPM instruction can access the entire Flash, including the
BLS itself. The protection level for the Boot Loader section can be selected by the Boot Loader
Lock bits (Boot Lock bits 1), see Table 29-3 on page 347.
29.3 Read-while-write and no read-while-write flash sections
Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader software
update is dependent on which address that is being programmed. In addition to the two344
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sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also
divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-WhileWrite
(NRWW) section. The limit between the RWW- and NRWW sections is given in Table 29-
1 and Figure 29-1 on page 345. The main difference between the two sections is:
• When erasing or writing a page located inside the RWW section, the NRWW section can be
read during the operation
• When erasing or writing a page located inside the NRWW section, the CPU is halted during
the entire operation
Note that the user software can never read any code that is located inside the RWW section during
a Boot Loader software operation. The syntax “Read-While-Write section” refers to which
section that is being programmed (erased or written), not which section that actually is being
read during a Boot Loader software update.
29.3.1 RWW – Read-While-Write section
If a Boot Loader software update is programming a page inside the RWW section, it is possible
to read code from the Flash, but only code that is located in the NRWW section. During an ongoing
programming, the software must ensure that the RWW section never is being read. If the
user software is trying to read code that is located inside the RWW section (i.e., by load program
memory, call, or jump instructions or an interrupt) during programming, the software might end
up in an unknown state. To avoid this, the interrupts should either be disabled or moved to the
Boot Loader section. The Boot Loader section is always located in the NRWW section. The
RWW Section Busy bit (RWWSB) in the Store Program Memory Control and Status Register
(SPMCSR) will be read as logical one as long as the RWW section is blocked for reading. After
a programming is completed, the RWWSB must be cleared by software before reading code
located in the RWW section. See “SPMCSR – Store Program Memory Control and Status Register”
on page 349. for details on how to clear RWWSB.
29.3.2 NRWW – No Read-While-Write section
The code located in the NRWW section can be read when the Boot Loader software is updating
a page in the RWW section. When the Boot Loader code updates the NRWW section, the CPU
is halted during the entire Page Erase or Page Write operation.
Table 29-1. Read-While-Write features.
Which section does the Zpointer
address during the
programming?
Which section can
be read during
programming?
Is the CPU
halted?
Read-While-Write
supported?
RWW section NRWW section No Yes
NRWW section None Yes No345
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Figure 29-1. Read-While-Write vs. no Read-While-Write.
Read-While-Write
(RWW) section
No Read-While-Write
(NRWW) section
Z-pointer
Addresses RWW
section
Z-pointer
addresses NRWW
section
CPU is halted
during the operation
Code located in
NRWW section.
Can be read during
the operation346
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Figure 29-2. Memory sections.
Note: 1. The parameters in the figure above are given in Table 29-8 on page 357.
29.4 Boot Loader lock bits
If no Boot Loader capability is needed, the entire Flash is available for application code. The
Boot Loader has two separate sets of Boot Lock bits which can be set independently. This gives
the user a unique flexibility to select different levels of protection.
The user can select:
• To protect the entire Flash from a software update by the MCU
• To protect only the Boot Loader Flash section from a software update by the MCU
• To protect only the Application Flash section from a software update by the MCU
• Allow software update in the entire Flash
See Table 29-2 on page 347 and Table 29-3 on page 347 for further details. The Boot Lock bits
can be set by software and in Serial or in Parallel Programming mode. They can only be cleared
by a Chip Erase command only. The general Write Lock (Lock Bit mode 2) does not control the
programming of the Flash memory by SPM instruction. Similarly, the general Read/Write Lock
(Lock Bit mode 1) does not control reading nor writing by (E)LPM/SPM, if it is attempted.
0x0000
Flashend
Program memory
BOOTSZ = '11'
Application flash section
Boot loader flash section Flashend
Program memory
BOOTSZ = '10'
0x0000
Program memory
BOOTSZ = '01'
Program memory
BOOTSZ = '00'
Application flash section
Boot loader flash section
0x0000
Flashend
Application flash section
Flashend
End RWW
Start NRWW
Application flash section
Boot loader flash section
Boot loader flash section
End RWW
Start NRWW
End RWW
Start NRWW
0x0000
End RWW, end application
Start NRWW, start boot loader
Application flash section Application flash section
Application flash section
Read-While-Write section No Read-While-Write section Read-While-Write section No Read-While-Write section
Read-While-Write section No Read-While-Write section Read-While-Write section No Read-While-Write section
End application
Start boot loader
End application
Start boot loader
End application
Start boot loader347
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Note: 1. “1” means unprogrammed, “0” means programmed.
Note: 1. “1” means unprogrammed, “0” means programmed.
29.5 Entering the Boot Loader program
The boot loader can be executed with three different conditions:
29.5.1 Regular application conditions.
A jump or call from the application program. This may be initiated by a trigger such as a command
received via USART, SPI or USB.
29.5.2 Boot Reset fuse
The Boot Reset Fuse (BOOTRST) can be programmed so that the Reset Vector is pointing to
the Boot Flash start address after a reset. In this case, the Boot Loader is started after a reset.
After the application code is loaded, the program can start executing the application code. Note
that the fuses cannot be changed by the MCU itself. This means that once the Boot Reset Fuse
is programmed, the Reset Vector will always point to the Boot Loader Reset and the fuse can
only be changed through the serial or parallel programming interface.
Table 29-2. Boot Lock Bit0 protection modes (application section) (1).
BLB0 Mode BLB02 BLB01 Protection
1 11 No restrictions for SPM or (E)LPM accessing the
Application section.
2 1 0 SPM is not allowed to write to the Application section.
3 00
SPM is not allowed to write to the Application section, and
(E)LPM executing from the Boot Loader section is not
allowed to read from the Application section. If Interrupt
Vectors are placed in the Boot Loader section, interrupts
are disabled while executing from the Application section.
4 01
(E)LPM executing from the Boot Loader section is not
allowed to read from the Application section. If Interrupt
Vectors are placed in the Boot Loader section, interrupts
are disabled while executing from the Application section.
Table 29-3. Boot Lock Bit1 protection modes (boot loader section) (1).
BLB1 Mode BLB12 BLB11 Protection
1 11 No restrictions for SPM or (E)LPM accessing the Boot
Loader section.
2 1 0 SPM is not allowed to write to the Boot Loader section.
3 00
SPM is not allowed to write to the Boot Loader section,
and (E)LPM executing from the Application section is not
allowed to read from the Boot Loader section. If Interrupt
Vectors are placed in the Application section, interrupts
are disabled while executing from the Boot Loader section.
4 01
(E)LPM executing from the Application section is not
allowed to read from the Boot Loader section. If Interrupt
Vectors are placed in the Application section, interrupts
are disabled while executing from the Boot Loader section.348
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Note: 1. “1” means unprogrammed, “0” means programmed.
29.5.3 External hardware conditions
The Hardware Boot Enable Fuse (HWBE) can be programmed (see Table 29-5) so that upon
special hardware conditions under reset, the boot loader execution is forced after reset.
Note: 1. “1” means unprogrammed, “0” means programmed.
When the HWBE fuse is enable the ALE/HWB pin is configured as input during reset and sampled
during reset rising edge. When ALE/HWB pin is ‘0’ during reset rising edge, the reset vector
will be set as the Boot Loader Reset address and the Boot Loader will be executed (see Figure
29-3).
Figure 29-3. Boot process description.
Table 29-4. Boot reset fuse (1).
BOOTRST Reset address
1 Reset Vector = Application reset (address 0x0000)
0 Reset Vector = Boot loader reset (see Table 29-8 on page 357)
Table 29-5. Hardware boot enable fuse (1).
HWBE Reset address
1 ALE/HWB pin can not be used to force boot loader execution after reset
0 ALE/HWB pin is used during reset to force boot loader execution after reset
HWBE
BOOTRST ?
Ext. hardware
conditions ?
Reset vector = Application reset Reset vector = Boot loader reset
?
RESET
ALE/HWB
t
SHRH t
HHRH349
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29.5.4 SPMCSR – Store Program Memory Control and Status Register
The Store Program Memory Control and Status Register contains the control bits needed to control
the Boot Loader operations.
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM
ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN
bit in the SPMCSR Register is cleared.
• Bit 6 – RWWSB: Read-While-Write Section Busy
When a Self-Programming (Page Erase or Page Write) operation to the RWW section is initiated,
the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section
cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a
Self-Programming operation is completed. Alternatively the RWWSB bit will automatically be
cleared if a page load operation is initiated.
• Bit 5 – SIGRD: Signature Row Read
If this bit is written to one at the same time as SPMEN, the next LPM instruction within three
clock cycles will read a byte from the signature row into the destination register. see “Reading
the Signature Row from software” on page 354 for details. An SPM instruction within four cycles
after SIGRD and SPMEN are set will have no effect. This operation is reserved for future use
and should not be used.
• Bit 4 – RWWSRE: Read-While-Write Section Read Enable
When programming (Page Erase or Page Write) to the RWW section, the RWW section is
blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the
user software must wait until the programming is completed (SPMEN will be cleared). Then, if
the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within
four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while
the Flash is busy with a Page Erase or a Page Write (SPMEN is set). If the RWWSRE bit is written
while the Flash is being loaded, the Flash load operation will abort and the data loaded will
be lost.
• Bit 3 – BLBSET: Boot Lock Bit Set
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock
cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Zpointer
are ignored. The BLBSET bit will automatically be cleared upon completion of the Lock
bit set, or if no SPM instruction is executed within four clock cycles.
An (E)LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCSR
Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the
destination register. See “Reading the Fuse and Lock bits from software” on page 353 for
details.
Bit 7 6 5 4 3 2 1 0
SPMIE RWWSB SIGRD RWWSRE BLBSET PGWRT PGERS SPMEN SPMCSR
Read/write R/W R R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0350
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• Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock
cycles executes Page Write, with the data stored in the temporary buffer. The page address is
taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit
will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four
clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is
addressed.
• Bit 1 – PGERS: Page Erase
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock
cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The
data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase,
or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire
Page Write operation if the NRWW section is addressed.
• Bit 0 – SPMEN: Store Program Memory Enable
This bit enables the SPM instruction for the next four clock cycles. If written to one together with
either RWWSRE, BLBSET, PGWRT’ or PGERS, the following SPM instruction will have a special
meaning, see description above. If only SPMEN is written, the following SPM instruction will
store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of
the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction,
or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write,
the SPMEN bit remains high until the operation is completed.
Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower
five bits will have no effect.
Note: Only one SPM instruction should be active at any time.
29.6 Addressing the flash during self-programming
The Z-pointer is used to address the SPM commands. The Z pointer consists of the Z-registers
ZL and ZH in the register file, and RAMPZ in the I/O space. The number of bits actually used is
implementation dependent. Note that the RAMPZ register is only implemented when the program
space is larger than 64kBytes.
Since the Flash is organized in pages (see Table 30-11 on page 364), the Program Counter can
be treated as having two different sections. One section, consisting of the least significant bits, is
addressing the words within a page, while the most significant bits are addressing the pages.
This is shown in Figure 29-4 on page 351. Note that the Page Erase and Page Write operations
are addressed independently. Therefore it is of major importance that the Boot Loader software
addresses the same page in both the Page Erase and Page Write operation. Once a programming
operation is initiated, the address is latched and the Z-pointer can be used for other
operations.
The (E)LPM instruction use the Z-pointer to store the address. Since this instruction addresses
the Flash byte-by-byte, also bit Z0 of the Z-pointer is used.
Bit 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8
RAMPZ RAMPZ7 RAMPZ6 RAMPZ5 RAMPZ4 RAMPZ3 RAMPZ2 RAMPZ1 RAMPZ0
ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8
ZL (R30) Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0
76543210351
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Figure 29-4. Addressing the flash during SPM (1).
Note: 1. The different variables used in Figure 29-4 are listed in Table 29-10 on page 358.
29.7 Self-programming the flash
The program memory is updated in a page by page fashion. Before programming a page with
the data stored in the temporary page buffer, the page must be erased. The temporary page buffer
is filled one word at a time using SPM and the buffer can be filled either before the Page
Erase command or between a Page Erase and a Page Write operation:
Alternative 1, fill the buffer before a Page Erase
• Fill temporary page buffer
• Perform a Page Erase
• Perform a Page Write
Alternative 2, fill the buffer after Page Erase
• Perform a Page Erase
• Fill temporary page buffer
• Perform a Page Write
If only a part of the page needs to be changed, the rest of the page must be stored (for example
in the temporary page buffer) before the erase, and then be rewritten. When using alternative 1,
the Boot Loader provides an effective Read-Modify-Write feature which allows the user software
to first read the page, do the necessary changes, and then write back the modified data. If alternative
2 is used, it is not possible to read the old data while loading since the page is already
erased. The temporary page buffer can be accessed in a random sequence. It is essential that
the page address used in both the Page Erase and Page Write operation is addressing the same
PROGRAM MEMORY
23 1 0
Z - POINTER
BIT
0
ZPAGEMSB
WORD ADDRESS
WITHIN A PAGE
PAGE ADDRESS
WITHIN THE FLASH
ZPCMSB
INSTRUCTION WORD
PAGE PCWORD[PAGEMSB:0]:
00
01
02
PAGEEND
PAGE
PCPAGE PCWORD
PCMSB PAGEMSB
PROGRAM COUNTER352
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AT90USB64/128
page. See “Simple Assembly Code example for a Boot Loader” on page 355 for an assembly
code example.
29.7.1 Performing page erase by SPM
To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and
execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.
The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will
be ignored during this operation.
• Page Erase to the RWW section: The NRWW section can be read during the Page Erase
• Page Erase to the NRWW section: The CPU is halted during the operation
29.7.2 Filling the Temporary Buffer (page loading)
To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write
“00000001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The
content of PCWORD in the Z-register is used to address the data in the temporary buffer. The
temporary buffer will auto-erase after a Page Write operation or by writing the RWWSRE bit in
SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than
one time to each address without erasing the temporary buffer.
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be
lost.
29.7.3 Performing a Page Write
To execute Page Write, set up the address in the Z-pointer, write “X0000101” to SPMCSR and
execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.
The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to
zero during this operation.
• Page Write to the RWW section: The NRWW section can be read during the Page Write
• Page Write to the NRWW section: The CPU is halted during the operation
29.7.4 Using the SPM interrupt
If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the
SPMEN bit in SPMCSR is cleared. This means that the interrupt can be used instead of polling
the SPMCSR Register in software. When using the SPM interrupt, the Interrupt Vectors should
be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is
blocked for reading. How to move the interrupts is described in “Interrupts” on page 68.
29.7.5 Consideration while updating BLS
Special care must be taken if the user allows the Boot Loader section to be updated by leaving
Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the
entire Boot Loader, and further software updates might be impossible. If it is not necessary to
change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to
protect the Boot Loader software from any internal software changes.
29.7.6 Prevent reading the RWW section during self-programming
During Self-Programming (either Page Erase or Page Write), the RWW section is always
blocked for reading. The user software itself must prevent that this section is addressed during
the self programming operation. The RWWSB in the SPMCSR will be set as long as the RWW
section is busy. During Self-Programming the Interrupt Vector table should be moved to the BLS353
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as described in “Interrupts” on page 68, or the interrupts must be disabled. Before addressing
the RWW section after the programming is completed, the user software must clear the
RWWSB by writing the RWWSRE. See “Simple Assembly Code example for a Boot Loader” on
page 355 for an example.
29.7.7 Setting the Boot Loader Lock bits by SPM
To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR
and execute SPM within four clock cycles after writing SPMCSR. The only accessible Lock bits
are the Boot Lock bits that may prevent the Application and Boot Loader section from any software
update by the MCU.
See Table 29-2 on page 347 and Table 29-3 on page 347 for how the different settings of the
Boot Loader bits affect the Flash access.
If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an
SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCSR.
The Z-pointer is don’t care during this operation, but for future compatibility it is recommended to
load the Z-pointer with 0x0001 (same as used for reading the lOck bits). For future compatibility it
is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing the Lock bits. When programming
the Lock bits the entire Flash can be read during the operation.
29.7.8 EEPROM Write prevents writing to SPMCSR
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCSR Register.
29.7.9 Reading the Fuse and Lock bits from software
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR. When an (E)LPM
instruction is executed within three CPU cycles after the BLBSET and SPMEN bits are set in
SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET and
SPMEN bits will auto-clear upon completion of reading the Lock bits or if no (E)LPM instruction
is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles.
When BLBSET and SPMEN are cleared, (E)LPM will work as described in the Instruction set
Manual.
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET
and SPMEN bits in SPMCSR. When an (E)LPM instruction is executed within three cycles after
the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will
be loaded in the destination register as shown below. Refer to Table 30-5 on page 361 for a
detailed description and mapping of the Fuse Low byte.
Bit 7 6 5 4 3 2 1 0
R0 1 1 BLB12 BLB11 BLB02 BLB01 1 1
Bit 7 6 5 4 3 2 1 0
Rd – – BLB12 BLB11 BLB02 BLB01 LB2 LB1
Bit 7 6 5 4 3 2 1 0
Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0354
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Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an (E)LPM
instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the
SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination register as
shown below. Refer to Table 30-4 on page 361 for detailed description and mapping of the Fuse
High byte.
When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an (E)LPM instruction
is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR,
the value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown
below. Refer to Table 30-3 on page 360 for detailed description and mapping of the Extended
Fuse byte.
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
unprogrammed, will be read as one.
29.7.10 Reading the Signature Row from software
To read the Signature Row from software, load the Z-pointer with the signature byte address
given in Table 29-6 on page 354 and set the SIGRD and SPMEN bits in SPMCSR. When an
LPM instruction is executed within three CPU cycles after the SIGRD and SPMEN bits are set in
SPMCSR, the signature byte value will be loaded in the destination register. The SIGRD and
SPMEN bits will auto-clear upon completion of reading the Signature Row Lock bits or if no LPM
instruction is executed within three CPU cycles. When SIGRD and SPMEN are cleared, LPM will
work as described in the Instruction set Manual.
AT90USB64/128 includes a unique 10-bytes serial number located in the signature row. This
unique serial number can be used as a USB serial number in the device enumeration process.
The pointer addresses to access this unique serial number are given in Table 29-6 on page 354.
Note: All other addresses are reserved for future use.
29.7.11 Preventing flash corruption
During periods of low VCC, the Flash program can be corrupted because the supply voltage is
too low for the CPU and the Flash to operate properly. These issues are the same as for board
level systems using the Flash, and the same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a
regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,
Bit 7 6 5 4 3 2 1 0
Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0
Bit 7 6 5 4 3 2 1 0
Rd – – – – – EFB2 EFB1 EFB0
Table 29-6. Signature Row addressing.
Signature byte Z-pointer address
Device Signature Byte 1 0x0000
Device Signature Byte 2 0x0002
Device Signature Byte 3 0x0004
RC Oscillator Calibration Byte 0x0001
Unique Serial Number From 0x000E to 0x0018355
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AT90USB64/128
the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions
is too low.
Flash corruption can easily be avoided by following these design recommendations (one is
sufficient):
1. If there is no need for a Boot Loader update in the system, program the Boot Loader
Lock bits to prevent any Boot Loader software updates.
2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
This can be done by enabling the internal Brown-out Detector (BOD) if the operating
voltage matches the detection level. If not, an external low VCC reset protection circuit
can be used. If a reset occurs while a write operation is in progress, the write operation
will be completed provided that the power supply voltage is sufficient.
3. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will prevent
the CPU from attempting to decode and execute instructions, effectively protecting
the SPMCSR Register and thus the Flash from unintentional writes.
29.7.12 Programming time for flash when using SPM
The calibrated RC Oscillator is used to time Flash accesses. Table 29-7 shows the typical programming
time for Flash accesses from the CPU.
29.7.13 Simple Assembly Code example for a Boot Loader
;- the routine writes one page of data from RAM to Flash
; the first data location in RAM is pointed to by the Y-pointer
; the first data location in Flash is pointed to by the Z-pointer
;- error handling is not included
;- the routine must be placed inside the Boot space
; (at least the Do_spm sub routine). Only code inside NRWW section can
; be read during Self-Programming (Page Erase and Page Write).
;- registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),
; loophi (r25), spmcsrval (r20)
; storing and restoring of registers is not included in the routine
; register usage can be optimized at the expense of code size
;- it is assumed that either the interrupt table is moved to the Boot
; loader section or that the interrupts are disabled.
.equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB is page size in BYTES, not words
.org SMALLBOOTSTART
Write_page:
; Page Erase
ldi spmcsrval, (1< 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck >= 12MHz
High: > 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck >= 12MHz
30.8.1 Serial programming algorithm
When writing serial data to the Atmel AT90USB64/128, data is clocked on the rising edge of
SCK. When reading data from the AT90USB64/128, data is clocked on the falling edge of SCK.
See Figure 30-11 on page 375 for timing details.
To program and verify the AT90USB64/128 in the serial programming mode, the following
sequence is recommended (See four byte instruction formats in Table 30-16 on page 376):
1. Power-up sequence:
Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems,
the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
2. Wait for at least 20ms and enable serial programming by sending the Programming
Enable serial instruction to pin PDI.
Table 30-14. Pin mapping serial programming.
Symbol Pins (TQFP-64) I/O Description
PDI PB2 I Serial Data in
PDO PB3 O Serial Data out
SCK PB1 I Serial Clock
VCC
GND
XTAL1
SCK
PDO
PDI
RESET
+1.8 - 5.5V
AVCC
+1.8 - 5.5V(2)375
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3. The serial programming instructions will not work if the communication is out of synchronization.
When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not, all
four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give
RESET a positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The memory page is loaded one byte at
a time by supplying the 7 LSB of the address and data together with the Load Program
Memory Page instruction. To ensure correct loading of the page, the data low byte must
be loaded before data high byte is applied for a given address. The Program Memory
Page is stored by loading the Write Program Memory Page instruction with the address
lines 15..8. Before issuing this command, make sure the instruction Load Extended
Address Byte has been used to define the MSB of the address. The extended address
byte is stored until the command is re-issued, i.e., the command needs only be issued
for the first page, and when crossing the 64KWord boundary. If polling (RDY/BSY) is not
used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 30-
15.) Accessing the serial programming interface before the Flash write operation completes
can result in incorrect programming.
5. The EEPROM array is programmed one byte at a time by supplying the address and
data together with the appropriate Write instruction. An EEPROM memory location is
first automatically erased before new data is written. If polling is not used, the user must
wait at least tWD_EEPROM before issuing the next byte. (See Table 30-15.) In a chip
erased device, no 0xFFs in the data file(s) need to be programmed.
6. Any memory location can be verified by using the Read instruction which returns the
content at the selected address at serial output PDO. When reading the Flash memory,
use the instruction Load Extended Address Byte to define the upper address byte,
which is not included in the Read Program Memory instruction. The extended address
byte is stored until the command is re-issued, that is, the command needs only be
issued for the first page, and when crossing the 64KWord boundary.
7. At the end of the programming session, RESET can be set high to commence normal
operation.
8. Power-off sequence (if needed):
Set RESET to “1”.
Turn VCC power off.
Figure 30-11. Serial programming waveforms.
Table 30-15. Minimum wait delay before writing the next Flash or EEPROM location.
Symbol Minimum wait delay
tWD_FLASH 4.5ms
tWD_EEPROM 9.0ms
tWD_ERASE 9.0ms
MSB
MSB
LSB
LSB
SERIAL CLOCK INPUT
(SCK)
SERIAL DATA INPUT
(MOSI)
(MISO)
SAMPLE
SERIAL DATA OUTPUT376
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Table 30-16. Serial programming instruction set.
Instruction
Instruction format
Byte 1 Byte 2 Byte 3 Byte 4 Operation
Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after
RESET goes low.
Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash.
Load Extended Address Byte
0100 1101 0000 0000 cccc cccc xxxx xxxx Defines Extended Address Byte for
Read Program Memory and Write
Program Memory Page.
Read Program Memory
0010 H000 aaaa aaaa bbbb bbbb oooo oooo Read H (high or low) data o from
Program memory at word address
c:a:b.
Load Program Memory Page
0100 H000 xxxx xxxx xxbb bbbb iiii iiii Write H (high or low) data i to Program
Memory page at word address b. Data
low byte must be loaded before Data
high byte is applied within the same
address.
Write Program Memory Page 0100 1100 aaaa aaaa bbxx xxxx xxxx xxxx Write Program Memory Page at
address c:a:b.
Read EEPROM Memory 1010 0000 0000 aaaa bbbb bbbb oooo oooo Read data o from EEPROM memory at
address a:b.
Write EEPROM Memory 1100 0000 0000 aaaa bbbb bbbb iiii iiii Write data i to EEPROM memory at
address a:b.
Load EEPROM Memory
Page (page access)
1100 0001 0000 0000 0000 00bb iiii iiii Load data i to EEPROM memory page
buffer. After data is loaded, program
EEPROM page.
Write EEPROM Memory
Page (page access)
1100 0010 0000 aaaa bbbb bb00 xxxx xxxx Write EEPROM page at address a:b.
Read Lock bits
0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock bits. “0” = programmed, “1”
= unprogrammed. See Table 30-1 on
page 359 for details.
Write Lock bits
1010 1100 111x xxxx xxxx xxxx 11ii iiii Write Lock bits. Set bits = “0” to
program Lock bits. See Table 30-1 on
page 359 for details.
Read Signature Byte 0011 0000 000x xxxx xxxx xxbb oooo oooo Read Signature Byte o at address b.
Write Fuse bits 1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to
unprogram.
Write Fuse High bits 1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to
unprogram.
Write Extended Fuse Bits
1010 1100 1010 0100 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to
unprogram. See Table 30-3 on page
360 for details.
Read Fuse bits 0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fuse bits. “0” = programmed, “1”
= unprogrammed.
Read Fuse High bits 0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fuse High bits. “0” = programmed,
“1” = unprogrammed. 377
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Note: a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in,
x = don’t care.
30.8.2 Serial programming characteristics
For characteristics of the Serial Programming module see “SPI timing characteristics” on page
395.
30.9 Programming via the JTAG interface
Programming through the JTAG interface requires control of the four JTAG specific pins: TCK,
TMS, TDI, and TDO. Control of the reset and clock pins is not required.
To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is
default shipped with the fuse programmed. In addition, the JTD bit in MCUCR must be cleared.
Alternatively, if the JTD bit is set, the external reset can be forced lo
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