8127F–AVR–02/2013
Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
– 54 Powerful Instructions – Most Single Clock Cycle Execution
– 16 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 12 MIPS Throughput at 12 MHz
• Non-volatile Program and Data Memories
– 512/1024 Bytes of In-System Programmable Flash Program Memory
– 32 Bytes Internal SRAM
– Flash Write/Erase Cycles: 10,000
– Data Retention: 20 Years at 85oC / 100 Years at 25oC
• Peripheral Features
– QTouch® Library Support for Capacitive Touch Sensing (1 Channel)
– One 16-bit Timer/Counter with Prescaler and Two PWM Channels
– Programmable Watchdog Timer with Separate On-chip Oscillator
– 4-channel, 8-bit Analog to Digital Converter (ATtiny5/10, only)
– On-chip Analog Comparator
• Special Microcontroller Features
– In-System Programmable (at 5V, only)
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Supply Voltage Level Monitor with Interrupt and Reset
– Internal Calibrated Oscillator
• I/O and Packages
– Four Programmable I/O Lines
– 6-pin SOT and 8-pad UDFN
• Operating Voltage:
– 1.8 – 5.5V
• Programming Voltage:
– 5V
• Speed Grade
– 0 – 4 MHz @ 1.8 – 5.5V
– 0 – 8 MHz @ 2.7 – 5.5V
– 0 – 12 MHz @ 4.5 – 5.5V
• Industrial and Extended Temperature Ranges
• Low Power Consumption
– Active Mode:
• 200µA at 1MHz and 1.8V
– Idle Mode:
• 25µA at 1MHz and 1.8V
– Power-down Mode:
• < 0.1µA at 1.8V
Atmel 8-bit AVR Microcontroller with 512/1024
Bytes In-System Programmable Flash
ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10
Rev. 8127F–AVR–02/2013ATtiny4/5/9/10 [DATASHEET] 2
8127F–AVR–02/2013
1. Pin Configurations
Figure 1-1. Pinout of ATtiny4/5/9/10
1.1 Pin Description
1.1.1 VCC
Supply voltage.
1.1.2 GND
Ground.
1.1.3 Port B (PB3..PB0)
This is a 4-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit. The output
buffers have symmetrical drive characteristics, with both high sink and source capability. As inputs, the port pins
that are externally pulled low will source current if pull-up resistors are activated. Port pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
The port also serves the functions of various special features of the ATtiny4/5/9/10, as listed on page 36.
1.1.4 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock
is not running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 16-4
on page 118. Shorter pulses are not guaranteed to generate a reset.
The reset pin can also be used as a (weak) I/O pin.
1
2
3
6
5
4
(PCINT0/TPIDATA/OC0A/ADC0/AIN0) PB0
GND
(PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1
PB3 (RESET/PCINT3/ADC3)
VCC
PB2 (T0/CLKO/PCINT2/INT0/ADC2)
SOT-23
1
2
3
4
8
7
6
5
(PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1
NC
NC
GND
PB2 (T0/CLKO/PCINT2/INT0/ADC2)
VCC
PB3 (RESET/PCINT3/ADC3)
PB0 (AIN0/ADC0/OC0A/TPIDATA/PCINT0)
UDFNATtiny4/5/9/10 [DATASHEET] 3
8127F–AVR–02/2013
2. Overview
ATtiny4/5/9/10 are low-power CMOS 8-bit microcontrollers based on the compact AVR enhanced RISC architecture.
By executing powerful instructions in a single clock cycle, the ATtiny4/5/9/10 achieve throughputs
approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing
speed.
Figure 2-1. Block Diagram
The AVR core combines a rich instruction set with 16 general purpose working registers and system registers. All
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be
accessed in one single instruction executed in one clock cycle. The resulting architecture is compact and code efficient
while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATtiny4/5/9/10 provide the following features: 512/1024 byte of In-System Programmable Flash, 32 bytes of
SRAM, four general purpose I/O lines, 16 general purpose working registers, a 16-bit timer/counter with two PWM
STACK
POINTER
SRAM
PROGRAM
COUNTER
PROGRAMMING
LOGIC
ISP
INTERFACE
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
RESET FLAG
REGISTER
MCU STATUS
REGISTER
TIMER/
COUNTER0
CALIBRATED
OSCILLATOR
TIMING AND
CONTROL
INTERRUPT
UNIT
ANALOG
COMPARATOR ADC
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
STATUS
REGISTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
VCC RESET
DATA REGISTER
PORT B
DIRECTION
REG. PORT B
DRIVERS
PORT B
GND PB3:0
8-BIT DATA BUSATtiny4/5/9/10 [DATASHEET] 4
8127F–AVR–02/2013
channels, internal and external interrupts, a programmable watchdog timer with internal oscillator, an internal calibrated
oscillator, and four software selectable power saving modes. ATtiny5/10 are also equipped with a fourchannel,
8-bit Analog to Digital Converter (ADC).
Idle mode stops the CPU while allowing the SRAM, timer/counter, ADC (ATtiny5/10, only), analog comparator, and
interrupt system to continue functioning. ADC Noise Reduction mode minimizes switching noise during ADC conversions
by stopping the CPU and all I/O modules except the ADC. In Power-down mode registers keep their
contents and all chip functions are disabled until the next interrupt or hardware reset. In Standby mode, the oscillator
is running while the rest of the device is sleeping, allowing very fast start-up combined with low power
consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The on-chip, in-system
programmable Flash allows program memory to be re-programmed in-system by a conventional, non-volatile
memory programmer.
The ATtiny4/5/9/10 AVR are supported by a suite of program and system development tools, including macro
assemblers and evaluation kits.
2.1 Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10
A comparison of the devices is shown in Table 2-1.
Table 2-1. Differences between ATtiny4, ATtiny5, ATtiny9 and ATtiny10
Device Flash ADC Signature
ATtiny4 512 bytes No 0x1E 0x8F 0x0A
ATtiny5 512 bytes Yes 0x1E 0x8F 0x09
ATtiny9 1024 bytes No 0x1E 0x90 0x08
ATtiny10 1024 bytes Yes 0x1E 0x90 0x03ATtiny4/5/9/10 [DATASHEET] 5
8127F–AVR–02/2013
3. General Information
3.1 Resources
A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available
for download at http://www.atmel.com/microcontroller/avr.
3.2 Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. These
code examples assume that the part specific header file is included before compilation. Be aware that not all C
compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent.
Please confirm with the C compiler documentation for more details.
3.3 Capacitive Touch Sensing
Atmel QTouch Library provides a simple to use solution for touch sensitive interfaces on Atmel AVR microcontrollers.
The QTouch Library includes support for QTouch® and QMatrix® acquisition methods.
Touch sensing is easily added to any application by linking the QTouch Library and using the Application Programming
Interface (API) of the library to define the touch channels and sensors. The application then calls the API to
retrieve channel information and determine the state of the touch sensor.
The QTouch Library is free and can be downloaded from the Atmel website. For more information and details of
implementation, refer to the QTouch Library User Guide – also available from the Atmel website.
3.4 Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20
years at 85°C or 100 years at 25°C.ATtiny4/5/9/10 [DATASHEET] 6
8127F–AVR–02/2013
4. CPU Core
This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct
program execution. The CPU must therefore be able to access memories, perform calculations, control
peripherals, and handle interrupts.
4.1 Architectural Overview
Figure 4-1. Block Diagram of the AVR Architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories
and buses for program and data. Instructions in the program memory are executed with a single level pipelining.
While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept
enables instructions to be executed in every clock cycle. The program memory is In-System reprogrammable
Flash memory.
The fast-access Register File contains 16 x 8-bit general purpose working registers with a single clock cycle
access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands
are output from the Register File, the operation is executed, and the result is stored back in the Register File
– in one clock cycle.
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
16 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
Data Bus 8-bit
Data
SRAM
Direct Addressing
Indirect Addressing
Interrupt
Unit
Watchdog
Timer
Analog
Comparator
Timer/Counter 0
ADCATtiny4/5/9/10 [DATASHEET] 7
8127F–AVR–02/2013
Six of the 16 registers can be used as three 16-bit indirect address register pointers for data space addressing –
enabling efficient address calculations. One of the these address pointers can also be used as an address pointer
for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register,
described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single
register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated
to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, capable of directly addressing
the whole address space. Most AVR instructions have a single 16-bit word format but 32-bit wide instructions also
exist. The actual instruction set varies, as some devices only implement a part of the instruction set.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack
is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the SRAM size
and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or
interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can
easily be accessed through the four different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in
the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have
priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the
priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other
I/O functions. The I/O memory can be accessed as the data space locations, 0x0000 - 0x003F.
4.2 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 16 general purpose working registers.
Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an
immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bitfunctions.
Some implementations of the architecture also provide a powerful multiplier supporting both
signed/unsigned multiplication and fractional format. See document “AVR Instruction Set” and section “Instruction
Set Summary” on page 150 for a detailed description.
4.3 Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction. This
information can be used for altering program flow in order to perform conditional operations. Note that the Status
Register is updated after all ALU operations, as specified in document “AVR Instruction Set” and section “Instruction
Set Summary” on page 150. This will in many cases remove the need for using the dedicated compare
instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when returning
from an interrupt. This must be handled by software.
4.4 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance
and flexibility, the following input/output schemes are supported by the Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• One 16-bit output operand and one 16-bit result inputATtiny4/5/9/10 [DATASHEET] 8
8127F–AVR–02/2013
Figure 4-2 below shows the structure of the 16 general purpose working registers in the CPU.
Figure 4-2. AVR CPU General Purpose Working Registers
Note: A typical implementation of the AVR register file includes 32 general prupose registers but ATtiny4/5/9/10 implement
only 16 registers. For reasons of compatibility the registers are numbered R16...R31, not R0...R15.
Most of the instructions operating on the Register File have direct access to all registers, and most of them are single
cycle instructions.
4.4.1 The X-register, Y-register, and Z-register
Registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit
address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are
defined as described in Figure 4-3.
Figure 4-3. The X-, Y-, and Z-registers
7 0
R16
R17
General R18
Purpose …
Working R26 X-register Low Byte
Registers R27 X-register High Byte
R28 Y-register Low Byte
R29 Y-register High Byte
R30 Z-register Low Byte
R31 Z-register High Byte
15 XH XL 0
X-register 7 07 0
R27 R26
15 YH YL 0
Y-register 7 07 0
R29 R28
15 ZH ZL 0
Z-register 7 07 0
R31 R30ATtiny4/5/9/10 [DATASHEET] 9
8127F–AVR–02/2013
In different addressing modes these address registers function as automatic increment and automatic decrement
(see document “AVR Instruction Set” and section “Instruction Set Summary” on page 150 for details).
4.5 Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses
after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the
Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a
Stack PUSH command decreases the Stack Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This
Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts
are enabled. The Stack Pointer must be set to point above 0x40. The Stack Pointer is decremented by one
when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return
address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when
data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the
Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is
implementation dependent. Note that the data space in some implementations of the AVR architecture is so small
that only SPL is needed. In this case, the SPH Register will not be present.
4.6 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the
CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.
Figure 4-4. The Parallel Instruction Fetches and Instruction Executions
Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture
and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with
the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using
two register operands is executed, and the result is stored back to the destination register.
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPUATtiny4/5/9/10 [DATASHEET] 10
8127F–AVR–02/2013
Figure 4-5. Single Cycle ALU Operation
4.7 Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a
separate Program Vector in the program memory space. All interrupts are assigned individual enable bits which
must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the
interrupt.
The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors.
The complete list of vectors is shown in “Interrupts” on page 35. The list also determines the priority levels of the
different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next
is INT0 – the External Interrupt Request 0.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software
can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current
interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For
these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt
handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing
a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding
interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the
flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit
is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is
set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily
have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will
not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction
before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when
returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be
executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction.
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clkCPUATtiny4/5/9/10 [DATASHEET] 11
8127F–AVR–02/2013
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending
interrupts, as shown in the following example.
Note: See “Code Examples” on page 5.
4.7.1 Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock
cycles the Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle
period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and
this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction
is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution
response time is increased by four clock cycles. This increase comes in addition to the start-up time from the
selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program
Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG
is set.
4.8 Register Description
4.8.1 CCP – Configuration Change Protection Register
• Bits 7:0 – CCP[7:0] – Configuration Change Protection
In order to change the contents of a protected I/O register the CCP register must first be written with the correct
signature. After CCP is written the protected I/O registers may be written to during the next four CPU instruction
cycles. All interrupts are ignored during these cycles. After these cycles interrupts are automatically handled again
by the CPU, and any pending interrupts will be executed according to their priority.
When the protected I/O register signature is written, CCP[0] will read as one as long as the protected feature is
enabled, while CCP[7:1] will always read as zero.
Table 4-1 shows the signatures that are in recognised.
Assembly Code Example
sei ; set Global Interrupt Enable
sleep ; enter sleep, waiting for interrupt
; note: will enter sleep before any pending interrupt(s)
Bit 7 6 5 4 3 2 1 0
0x3C CCP[7:0] CCP
Read/Write W W W W W W W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 4-1. Signatures Recognised by the Configuration Change Protection Register
Signature Group Description
0xD8 IOREG: CLKMSR, CLKPSR, WDTCSR Protected I/O registerATtiny4/5/9/10 [DATASHEET] 12
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4.8.2 SPH and SPL — Stack Pointer Register
4.8.3 SREG – Status Register
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control
is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts
are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an
interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set
and cleared by the application with the SEI and CLI instructions, as described in the document “AVR Instruction
Set” and “Instruction Set Summary” on page 150.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated
bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be
copied into a bit in a register in the Register File by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic.
See document “AVR Instruction Set” and section “Instruction Set Summary” on page 150 for detailed information.
• Bit 4 – S: Sign Bit, S = N V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See
document “AVR Instruction Set” and section “Instruction Set Summary” on page 150 for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See document “AVR Instruction
Set” and section “Instruction Set Summary” on page 150 for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See document “AVR Instruction
Set” and section “Instruction Set Summary” on page 150 for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See document “AVR Instruction Set” and
section “Instruction Set Summary” on page 150 for detailed information.
Bit 15 14 13 12 11 10 9 8
0x3E SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH
0x3D SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
Bit 7 6 5 4 3 2 1 0
0x3F I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0ATtiny4/5/9/10 [DATASHEET] 13
8127F–AVR–02/2013
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See document “AVR Instruction Set” and
section “Instruction Set Summary” on page 150 for detailed information.ATtiny4/5/9/10 [DATASHEET] 14
8127F–AVR–02/2013
5. Memories
This section describes the different memories in the ATtiny4/5/9/10. Devices have two main memory areas, the
program memory space and the data memory space.
5.1 In-System Re-programmable Flash Program Memory
The ATtiny4/5/9/10 contain 512/1024 bytes of on-chip, in-system reprogrammable Flash memory for program storage.
Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 256/512 x 16.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny4/5/9/10 Program Counter
(PC) is 9 bits wide, thus capable of addressing the 256/512 program memory locations, starting at 0x000. “Memory
Programming” on page 106 contains a detailed description on Flash data serial downloading.
Constant tables can be allocated within the entire address space of program memory. Since program memory can
not be accessed directly, it has been mapped to the data memory. The mapped program memory begins at byte
address 0x4000 in data memory (see Figure 5-1 on page 15). Although programs are executed starting from
address 0x000 in program memory it must be addressed starting from 0x4000 when accessed via the data
memory.
Internal write operations to Flash program memory have been disabled and program memory therefore appears to
firmware as read-only. Flash memory can still be written to externally but internal write operations to the program
memory area will not be succesful.
Timing diagrams of instruction fetch and execution are presented in “Instruction Execution Timing” on page 9.
5.2 Data Memory
Data memory locations include the I/O memory, the internal SRAM memory, the non-volatile memory lock bits, and
the Flash memory. See Figure 5-1 on page 15 for an illustration on how the ATtiny4/5/9/10 memory space is
organized.
The first 64 locations are reserved for I/O memory, while the following 32 data memory locations address the internal
data SRAM.
The non-volatile memory lock bits and all the Flash memory sections are mapped to the data memory space.
These locations appear as read-only for device firmware.
The four different addressing modes for data memory are direct, indirect, indirect with pre-decrement, and indirect
with post-increment. In the register file, registers R26 to R31 function as pointer registers for indirect addressing.
The IN and OUT instructions can access all 64 locations of I/O memory. Direct addressing using the LDS and STS
instructions reaches the 128 locations between 0x0040 and 0x00BF.
The indirect addressing reaches the entire data memory space. When using indirect addressing modes with automatic
pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented.ATtiny4/5/9/10 [DATASHEET] 15
8127F–AVR–02/2013
Figure 5-1. Data Memory Map (Byte Addressing)
5.2.1 Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The internal data SRAM
access is performed in two clkCPU cycles as described in Figure 5-2.
Figure 5-2. On-chip Data SRAM Access Cycles
0x0000 ... 0x003F
0x0040 ... 0x005F
0x0060 ... 0x3EFF
0x3F00 ... 0x3F01
0x3F02 ... 0x3F3F
0x3F40 ... 0x3F41
0x3F42 ... 0x3F7F
0x3F80 ... 0x3F81
0x3F82 ... 0x3FBF
0x3FC0 ... 0x3FC3
0x3FC4 ... 0x3FFF
0x4000 ... 0x41FF/0x43FF
0x4400 ... 0xFFFF
I/O SPACE
SRAM DATA MEMORY
(reserved)
NVM LOCK BITS
(reserved)
CONFIGURATION BITS
(reserved)
CALIBRATION BITS
(reserved)
DEVICE ID BITS
(reserved)
FLASH PROGRAM MEMORY
(reserved)
clk
WR
RD
Data
Data
Address Address valid
T1 T2 T3
Compute Address
Read Write
CPU
Memory Access Instruction Next InstructionATtiny4/5/9/10 [DATASHEET] 16
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5.3 I/O Memory
The I/O space definition of the ATtiny4/5/9/10 is shown in “Register Summary” on page 148.
All ATtiny4/5/9/10 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed using the LD
and ST instructions, enabling data transfer between the 16 general purpose working registers and the I/O space.
I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In
these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. See document
“AVR Instruction Set” and section “Instruction Set Summary” on page 150 for more details. When using the I/O
specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that CBI and SBI instructions will only
operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI
instructions work on registers in the address range 0x00 to 0x1F, only.
The I/O and Peripherals Control Registers are explained in later sections.ATtiny4/5/9/10 [DATASHEET] 17
8127F–AVR–02/2013
6. Clock System
Figure 6-1 presents the principal clock systems and their distribution in ATtiny4/5/9/10. All of the clocks need not
be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be
halted by using different sleep modes and power reduction register bits, as described in “Power Management and
Sleep Modes” on page 23. The clock systems is detailed below.
Figure 6-1. Clock Distribution
6.1 Clock Subsystems
The clock subsystems are detailed in the sections below.
6.1.1 CPU Clock – clkCPU
The CPU clock is routed to parts of the system concerned with operation of the AVR Core. Examples of such modules
are the General Purpose Register File, the System Registers and the SRAM data memory. Halting the CPU
clock inhibits the core from performing general operations and calculations.
6.1.2 I/O Clock – clkI/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is also used by the
External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing
such interrupts to be detected even if the I/O clock is halted.
6.1.3 NVM clock - clkNVM
The NVM clock controls operation of the Non-Volatile Memory Controller. The NVM clock is usually active simultaneously
with the CPU clock.
CLOCK CONTROL UNIT
GENERAL
I/O MODULES
ANALOG-TO-DIGITAL
CONVERTER
CPU
CORE
WATCHDOG
TIMER
RESET
LOGIC
CLOCK
PRESCALER
RAM
CLOCK
SWITCH
NVM
CALIBRATED
OSCILLATOR
clk ADC
SOURCE CLOCK
clk I/O
clk CPU
clk NVM
WATCHDOG
CLOCK
WATCHDOG
OSCILLATOR
EXTERNAL
CLOCKATtiny4/5/9/10 [DATASHEET] 18
8127F–AVR–02/2013
6.1.4 ADC Clock – clkADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce
noise generated by digital circuitry. This gives more accurate ADC conversion results.
The ADC is available in ATtiny5/10, only.
6.2 Clock Sources
All synchronous clock signals are derived from the main clock. The device has three alternative sources for the
main clock, as follows:
• Calibrated Internal 8 MHz Oscillator (see page 18)
• External Clock (see page 18)
• Internal 128 kHz Oscillator (see page 19)
See Table 6-3 on page 21 on how to select and change the active clock source.
6.2.1 Calibrated Internal 8 MHz Oscillator
The calibrated internal oscillator provides an approximately 8 MHz clock signal. Though voltage and temperature
dependent, this clock can be very accurately calibrated by the user. See Table 16-2 on page 117, Figure 17-39 on
page 141 and Figure 17-40 on page 141 for more details.
This clock may be selected as the main clock by setting the Clock Main Select bits CLKMS[1:0] in CLKMSR to
0b00. Once enabled, the oscillator will operate with no external components. During reset, hardware loads the calibration
byte into the OSCCAL register and thereby automatically calibrates the oscillator. The accuracy of this
calibration is shown as Factory calibration in Table 16-2 on page 117.
When this oscillator is used as the main clock, the watchdog oscillator will still be used for the watchdog timer and
reset time-out. For more information on the pre-programmed calibration value, see section “Calibration Section” on
page 109.
6.2.2 External Clock
To use the device with an external clock source, CLKI should be driven as shown in Figure 6-2. The external clock
is selected as the main clock by setting CLKMS[1:0] bits in CLKMSR to 0b10.
Figure 6-2. External Clock Drive Configuration
When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure
stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to
unpredictable behavior. It is required to ensure that the MCU is kept in reset during such changes in the clock
frequency.
EXTERNAL
CLOCK
SIGNAL
CLKI
GNDATtiny4/5/9/10 [DATASHEET] 19
8127F–AVR–02/2013
6.2.3 Internal 128 kHz Oscillator
The internal 128 kHz oscillator is a low power oscillator providing a clock of 128 kHz. The frequency depends on
supply voltage, temperature and batch variations. This clock may be select as the main clock by setting the
CLKMS[1:0] bits in CLKMSR to 0b01.
6.2.4 Switching Clock Source
The main clock source can be switched at run-time using the “CLKMSR – Clock Main Settings Register” on page
21. When switching between any clock sources, the clock system ensures that no glitch occurs in the main clock.
6.2.5 Default Clock Source
The calibrated internal 8 MHz oscillator is always selected as main clock when the device is powered up or has
been reset. The synchronous system clock is the main clock divided by 8, controlled by the System Clock Prescaler.
The Clock Prescaler Select Bits can be written later to change the system clock frequency. See “System
Clock Prescaler”.
6.3 System Clock Prescaler
The system clock is derived from the main clock via the System Clock Prescaler. The system clock can be divided
by setting the “CLKPSR – Clock Prescale Register” on page 22. The system clock prescaler can be used to
decrease power consumption at times when requirements for processing power is low or to bring the system clock
within limits of maximum frequency. The prescaler can be used with all main clock source options, and it will affect
the clock frequency of the CPU and all synchronous peripherals.
The System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still
ensuring stable operation.
6.3.1 Switching Prescaler Setting
When switching between prescaler settings, the system clock prescaler ensures that no glitch occurs in the system
clock and that no intermediate frequency is higher than neither the clock frequency corresponding the previous setting,
nor the clock frequency corresponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the main clock, which may be faster than
the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were readable,
and the exact time it takes to switch from one clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock frequency
is active. In this interval, two active clock edges are produced. Here, T1 is the previous clock period, and
T2 is the period corresponding to the new prescaler setting.ATtiny4/5/9/10 [DATASHEET] 20
8127F–AVR–02/2013
6.4 Starting
6.4.1 Starting from Reset
The internal reset is immediately asserted when a reset source goes active. The internal reset is kept asserted until
the reset source is released and the start-up sequence is completed. The start-up sequence includes three steps,
as follows.
1. The first step after the reset source has been released consists of the device counting the reset start-up
time. The purpose of this reset start-up time is to ensure that supply voltage has reached sufficient levels.
The reset start-up time is counted using the internal 128 kHz oscillator. See Table 6-1 for details of reset
start-up time.
Note that the actual supply voltage is not monitored by the start-up logic. The device will count until the
reset start-up time has elapsed even if the device has reached sufficient supply voltage levels earlier.
2. The second step is to count the oscillator start-up time, which ensures that the calibrated internal oscillator
has reached a stable state before it is used by the other parts of the system. The calibrated internal oscillator
needs to oscillate for a minimum number of cycles before it can be considered stable. See Table 6-1
for details of the oscillator start-up time.
3. The last step before releasing the internal reset is to load the calibration and the configuration values from
the Non-Volatile Memory to configure the device properly. The configuration time is listed in Table 6-1.
Notes: 1. After powering up the device or after a reset the system clock is automatically set to calibrated internal 8 MHz oscillator,
divided by 8
6.4.2 Starting from Power-Down Mode
When waking up from Power-Down sleep mode, the supply voltage is assumed to be at a sufficient level and only
the oscillator start-up time is counted to ensure the stable operation of the oscillator. The oscillator start-up time is
counted on the selected main clock, and the start-up time depends on the clock selected. See Table 6-2 for details.
Notes: 1. The start-up time is measured in main clock oscillator cycles.
6.4.3 Starting from Idle / ADC Noise Reduction / Standby Mode
When waking up from Idle, ADC Noise Reduction or Standby Mode, the oscillator is already running and no oscillator
start-up time is introduced.
The ADC is available in ATtiny5/10, only.
Table 6-1. Start-up Times when Using the Internal Calibrated Oscillator
Reset Oscillator Configuration Total start-up time
64 ms 6 cycles 21 cycles 64 ms + 6 oscillator cycles + 21 system clock cycles (1)
Table 6-2. Start-up Time from Power-Down Sleep Mode.
Oscillator start-up time Total start-up time
6 cycles 6 oscillator cycles (1)ATtiny4/5/9/10 [DATASHEET] 21
8127F–AVR–02/2013
6.5 Register Description
6.5.1 CLKMSR – Clock Main Settings Register
• Bit 7:2 – Res: Reserved Bits
These bits are reserved and always read zero.
• Bit 1:0 – CLKMS[1:0]: Clock Main Select Bits
These bits select the main clock source of the system. The bits can be written at run-time to switch the source of
the main clock. The clock system ensures glitch free switching of the main clock source.
The main clock alternatives are shown in Table 6-3.
To avoid unintentional switching of main clock source, a protected change sequence must be followed to change
the CLKMS bits, as follows:
1. Write the signature for change enable of protected I/O register to register CCP
2. Within four instruction cycles, write the CLKMS bits with the desired value
6.5.2 OSCCAL – Oscillator Calibration Register .
• Bits 7:0 – CAL[7:0]: Oscillator Calibration Value
The oscillator calibration register is used to trim the calibrated internal oscillator and remove process variations
from the oscillator frequency. A pre-programmed calibration value is automatically written to this register during
chip reset, giving the factory calibrated frequency as specified in Table 16-2, “Calibration Accuracy of Internal RC
Oscillator,” on page 117.
The application software can write this register to change the oscillator frequency. The oscillator can be calibrated
to frequencies as specified in Table 16-2, “Calibration Accuracy of Internal RC Oscillator,” on page 117. Calibration
outside the range given is not guaranteed.
The CAL[7:0] bits are used to tune the frequency of the oscillator. A setting of 0x00 gives the lowest frequency, and
a setting of 0xFF gives the highest frequency.
Bit 7 6 5 4 3 2 1 0
0x37 – – – – – – CLKMS1 CLKMS0 CLKMSR
Read/Write R R R R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 6-3. Selection of Main Clock
CLKM1 CLKM0 Main Clock Source
0 0 Calibrated Internal 8 MHzOscillator
0 1 Internal 128 kHz Oscillator (WDT Oscillator)
1 0 External clock
1 1 Reserved
Bit 7 6 5 4 3 2 1 0
0x39 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value X X X X X X X XATtiny4/5/9/10 [DATASHEET] 22
8127F–AVR–02/2013
6.5.3 CLKPSR – Clock Prescale Register
• Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system clock. These bits
can be written at run-time to vary the clock frequency and suit the application requirements. As the prescaler
divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced accordingly. The
division factors are given in Table 6-4.
To avoid unintentional changes of clock frequency, a protected change sequence must be followed to change the
CLKPS bits:
1. Write the signature for change enable of protected I/O register to register CCP
2. Within four instruction cycles, write the desired value to CLKPS bits
At start-up, CLKPS bits are reset to 0b0011 to select the clock division factor of 8. If the selected clock source has
a frequency higher than the maximum allowed the application software must make sure a sufficient division factor
is used. To make sure the write procedure is not interrupted, interrupts must be disabled when changing prescaler
settings.
Bit 7 6 5 4 3 2 1 0
0x36 – – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPSR
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 1 1
Table 6-4. Clock Prescaler Select
CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor
0000 1
0001 2
0010 4
0 0 1 1 8 (default)
0 1 0 0 16
0 1 0 1 32
0 1 1 0 64
0 1 1 1 128
1 0 0 0 256
1 0 0 1 Reserved
1 0 1 0 Reserved
1 0 1 1 Reserved
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 ReservedATtiny4/5/9/10 [DATASHEET] 23
8127F–AVR–02/2013
7. Power Management and Sleep Modes
The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low
power applications. In addition, sleep modes enable the application to shut down unused modules in the MCU,
thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to
the application’s requirements.
7.1 Sleep Modes
Figure 6-1 on page 17 presents the different clock systems and their distribution in ATtiny4/5/9/10. The figure is
helpful in selecting an appropriate sleep mode. Table 7-1 shows the different sleep modes and their wake up
sources.
Note: 1. The ADC is available in ATtiny5/10, only
2. For INT0, only level interrupt.
To enter any of the four sleep modes, the SE bits in SMCR must be written to logic one and a SLEEP instruction
must be executed. The SM2:0 bits in the SMCR register select which sleep mode (Idle, ADC Noise Reduction,
Standby or Power-down) will be activated by the SLEEP instruction. See Table 7-2 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for
four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction
following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from
sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.
Note that if a level triggered interrupt is used for wake-up the changed level must be held for some time to wake up
the MCU (and for the MCU to enter the interrupt service routine). See “External Interrupts” on page 36 for details.
7.1.1 Idle Mode
When bits SM2:0 are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but
allowing the analog comparator, timer/counter, watchdog, and the interrupt system to continue operating. This
sleep mode basically halts clkCPU and clkNVM, while allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the timer
overflow. If wake-up from the analog comparator interrupt is not required, the analog comparator can be powered
down by setting the ACD bit in “ACSR – Analog Comparator Control and Status Register” on page 80. This will
reduce power consumption in idle mode. If the ADC is enabled (ATtiny5/10, only), a conversion starts automatically
when this mode is entered.
Table 7-1. Active Clock Domains and Wake-up Sources in Different Sleep Modes
Sleep Mode
Active Clock Domains Oscillators Wake-up Sources clkCPU clkNVM clkIO clkADC (1) Main Clock Source Enabled INT0 and Pin Change ADC (1) Other I/O Watchdog Interrupt
VLM Interrupt
Idle X X X X X X X X
ADC Noise Reduction X X X (2) X XX
Standby X X (2) X
Power-down X (2) XATtiny4/5/9/10 [DATASHEET] 24
8127F–AVR–02/2013
7.1.2 ADC Noise Reduction Mode
When bits SM2:0 are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode,
stopping the CPU but allowing the ADC, the external interrupts, and the watchdog to continue operating (if
enabled). This sleep mode halts clkI/O, clkCPU, and clkNVM, while allowing the other clocks to run.
This mode improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is
enabled, a conversion starts automatically when this mode is entered.
This mode is available in all devices, although only ATtiny5/10 are equipped with an ADC.
7.1.3 Power-down Mode
When bits SM2:0 are written to 010, the SLEEP instruction makes the MCU enter Power-down mode. In this mode,
the oscillator is stopped, while the external interrupts, and the watchdog continue operating (if enabled). Only a
watchdog reset, an external level interrupt on INT0, or a pin change interrupt can wake up the MCU. This sleep
mode halts all generated clocks, allowing operation of asynchronous modules only.
7.1.4 Standby Mode
When bits SM2:0 are written to 100, the SLEEP instruction makes the MCU enter Standby mode. This mode is
identical to Power-down with the exception that the oscillator is kept running. This reduces wake-up time, because
the oscillator is already running and doesn't need to be started up.
7.2 Power Reduction Register
The Power Reduction Register (PRR), see “PRR – Power Reduction Register” on page 26, provides a method to
reduce power consumption by stopping the clock to individual peripherals. When the clock for a peripheral is
stopped then:
• The current state of the peripheral is frozen.
• The associated registers can not be read or written.
• Resources used by the peripheral will remain occupied.
The peripheral should in most cases be disabled before stopping the clock. Clearing the PRR bit wakes up the
peripheral and puts it in the same state as before shutdown.
Peripheral shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption.
See “Supply Current of I/O Modules” on page 121 for examples. In all other sleep modes, the clock is already
stopped.
7.3 Minimizing Power Consumption
There are several issues to consider when trying to minimize the power consumption in an AVR Core controlled
system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so
that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular,
the following modules may need special consideration when trying to achieve the lowest possible power
consumption.
7.3.1 Analog Comparator
When entering Idle mode, the analog comparator should be disabled if not used. In the power-down mode, the
analog comparator is automatically disabled. See “Analog Comparator” on page 80 for further details.ATtiny4/5/9/10 [DATASHEET] 25
8127F–AVR–02/2013
7.3.2 Analog to Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering
any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion.
See “Analog to Digital Converter” on page 82 for details on ADC operation.
The ADC is available in ATtiny5/10, only.
7.3.3 Watchdog Timer
If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is
enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this
will contribute significantly to the total current consumption. Refer to “Watchdog Timer” on page 30 for details on
how to configure the Watchdog Timer.
7.3.4 Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing
is then to ensure that no pins drive resistive loads. In sleep modes where the I/O clock (clkI/O) is stopped, the input
buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed.
In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the
section “Digital Input Enable and Sleep Modes” on page 44 for details on which pins are enabled. If the input buffer
is enabled and the input signal is left floating or has an analog signal level close to VCC/2, the input buffer will use
excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC/2
on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to
the Digital Input Disable Register (DIDR0). Refer to “DIDR0 – Digital Input Disable Register 0” on page 81 for
details.
7.4 Register Description
7.4.1 SMCR – Sleep Mode Control Register
The SMCR Control Register contains control bits for power management.
• Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 3:1 – SM2..SM0: Sleep Mode Select Bits 2..0
These bits select between available sleep modes, as shown in Table 7-2.
Bit 7 6 5 4 3 2 1 0
0x3A – – – – SM2 SM1 SM0 SE SMCR
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 7-2. Sleep Mode Select
SM2 SM1 SM0 Sleep Mode
0 0 0 Idle
0 0 1 ADC noise reduction (1)
0 1 0 Power-down
0 1 1 Reserved
1 0 0 StandbyATtiny4/5/9/10 [DATASHEET] 26
8127F–AVR–02/2013
Note: 1. This mode is available in all devices, although only ATtiny5/10 are equipped with an ADC
• Bit 0 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.
To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to
write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately
after waking up.
7.4.2 PRR – Power Reduction Register
• Bits 7:2 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 1 – PRADC: Power Reduction ADC
Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator
cannot use the ADC input MUX when the ADC is shut down.
The ADC is available in ATtiny5/10, only.
• Bit 0 – PRTIM0: Power Reduction Timer/Counter0
Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation
will continue like before the shutdown.
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
Table 7-2. Sleep Mode Select
SM2 SM1 SM0 Sleep Mode
Bit 7 6 5 4 3 2 1 0
0x35 – – – – – – PRADC PRTIM0 PRR
Read/Write R R R R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0ATtiny4/5/9/10 [DATASHEET] 27
8127F–AVR–02/2013
8. System Control and Reset
8.1 Resetting the AVR
During reset, all I/O registers are set to their initial values, and the program starts execution from the Reset Vector.
The instruction placed at the Reset Vector must be a RJMP – Relative Jump – instruction to the reset handling routine.
If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code
can be placed at these locations. The circuit diagram in Figure 8-1 shows the reset logic. Electrical parameters of
the reset circuitry are defined in section “System and Reset Characteristics” on page 118.
Figure 8-1. Reset Logic
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not
require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the
power to reach a stable level before normal operation starts. The start up sequence is described in “Starting from
Reset” on page 20.
8.2 Reset Sources
The ATtiny4/5/9/10 have three sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT)
• External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum
pulse length
• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled
8.2.1 Power-on Reset
A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detection level is defined in section
“System and Reset Characteristics” on page 118. The POR is activated whenever VCC is below the detection
level. The POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage.
Reset Flag Register
(RSTFLR)
CK Delay Counters
TIMEOUT
WDRF
EXTRF
PORF
DATA BUS
Clock
Generator
SPIKE
FILTER
Pull-up Resistor
Watchdog
Oscillator
Power-on Reset
Circuit
VLMATtiny4/5/9/10 [DATASHEET] 28
8127F–AVR–02/2013
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset
threshold voltage invokes the delay counter, which determines how long the device is kept in reset after VCC rise.
The reset signal is activated again, without any delay, when VCC decreases below the detection level.
Figure 8-2. MCU Start-up, RESET Tied to VCC
Figure 8-3. MCU Start-up, RESET Extended Externally
8.2.2 VCC Level Monitoring
ATtiny4/5/9/10 have a VCC Level Monitoring (VLM) circuit that compares the voltage level at the VCC pin against
fixed trigger levels. The trigger levels are set with VLM2:0 bits, see “VLMCSR – VCC Level Monitoring Control and
Status register” on page 33.
The VLM circuit provides a status flag, VLMF, that indicates if voltage on the VCC pin is below the selected trigger
level. The flag can be read from VLMCSR, but it is also possible to have an interrupt generated when the VLMF
status flag is set. This interrupt is enabled by the VLMIE bit in the VLMCSR register. The flag can be cleared by
changing the trigger level or by writing it to zero. The flag is automatically cleared when the voltage at VCC rises
back above the selected trigger level.
The VLM can also be used to improve reset characteristics at falling supply. Without VLM, the Power-On Reset
(POR) does not activate before supply voltage has dropped to a level where the MCU is not necessarily functional
any more. With VLM, it is possible to generate a reset earlier.
When active, the VLM circuit consumes some power, as illustrated in Figure 17-48 on page 145. To save power
the VLM circuit can be turned off completely, or it can be switched on and off at regular intervals. However, detection
takes some time and it is therefore recommended to leave the circuitry on long enough for signals to settle.
See “VCC Level Monitor” on page 118.
V
TIME-OUT
RESET
RESET
TOUT
INTERNAL
t
VPOT
VRST
CC
V
TIME-OUT
TOUT
TOUT
INTERNAL
CC
t
VPOT
VRST
> t
RESET
RESETATtiny4/5/9/10 [DATASHEET] 29
8127F–AVR–02/2013
When VLM is active and voltage at VCC is above the selected trigger level operation will be as normal and the VLM
can be shut down for a short period of time. If voltage at VCC drops below the selected threshold the VLM will either
flag an interrupt or generate a reset, depending on the configuration.
When the VLM has been configured to generate a reset at low supply voltage it will keep the device in reset as long
as VCC is below the reset level. See Table 8-4 on page 34 for reset level details. If supply voltage rises above the
reset level the condition is removed and the MCU will come out of reset, and initiate the power-up start-up
sequence.
If supply voltage drops enough to trigger the POR then PORF is set after supply voltage has been restored.
8.2.3 External Reset
An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer than the minimum
pulse width (see section “System and Reset Characteristics” on page 118) will generate a reset, even if the clock is
not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset
Threshold Voltage – VRST – on its positive edge, the delay counter starts the MCU after the time-out period – tTOUT
– has expired. External reset is ignored during Power-on start-up count. After Power-on reset the internal reset is
extended only if RESET pin is low when the initial Power-on delay count is complete. See Figure 8-2 and Figure 8-
3 on page 28.
Figure 8-4. External Reset During Operation
8.2.4 Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of
this pulse, the delay timer starts counting the time-out period tTOUT. See page 30 for details on operation of the
Watchdog Timer and Table 16-4 on page 118 for details on reset time-out.
CCATtiny4/5/9/10 [DATASHEET] 30
8127F–AVR–02/2013
Figure 8-5. Watchdog Reset During Operation
8.3 Watchdog Timer
The Watchdog Timer is clocked from an on-chip oscillator, which runs at 128 kHz. See Figure 8-6. By controlling
the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 8-2 on page 32.
The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is
disabled and when a device reset occurs. Ten different clock cycle periods can be selected to determine the reset
period. If the reset period expires without another Watchdog Reset, the ATtiny4/5/9/10 resets and executes from
the Reset Vector. For timing details on the Watchdog Reset, refer to Table 8-3 on page 33.
Figure 8-6. Watchdog Timer
The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can be very helpful
when using the Watchdog to wake-up from Power-down.
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, two different safety
levels are selected by the fuse WDTON as shown in Table 8-1 on page 31. See “Procedure for Changing the
Watchdog Timer Configuration” on page 31 for details.
CK
CC
OSC/2K
OSC/4K
OSC/8K
OSC/16K
OSC/32K
OSC/64K
OSC/128K
OSC/256K
OSC/512K
OSC/1024K
MCU RESET
WATCHDOG
PRESCALER
128 kHz
OSCILLATOR
WATCHDOG
RESET
WDP0
WDP1
WDP2
WDP3
WDE
MUXATtiny4/5/9/10 [DATASHEET] 31
8127F–AVR–02/2013
8.3.1 Procedure for Changing the Watchdog Timer Configuration
The sequence for changing configuration differs between the two safety levels, as follows:
8.3.1.1 Safety Level 1
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to one without any
restriction. A special sequence is needed when disabling an enabled Watchdog Timer. To disable an enabled
Watchdog Timer, the following procedure must be followed:
1. Write the signature for change enable of protected I/O registers to register CCP
2. Within four instruction cycles, in the same operation, write WDE and WDP bits
8.3.1.2 Safety Level 2
In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A protected change
is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following procedure
must be followed:
1. Write the signature for change enable of protected I/O registers to register CCP
2. Within four instruction cycles, write the WDP bit. The value written to WDE is irrelevant
8.3.2 Code Examples
The following code example shows how to turn off the WDT. The example assumes that interrupts are controlled
(e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
Note: See “Code Examples” on page 5.
Table 8-1. WDT Configuration as a Function of the Fuse Settings of WDTON
WDTON
Safety
Level
WDT
Initial State
How to
Disable the WDT
How to
Change Time-out
Unprogrammed 1 Disabled Protected change
sequence
No limitations
Programmed 2 Enabled Always enabled Protected change
sequence
Assembly Code Example
WDT_off:
wdr
; Clear WDRF in RSTFLR
in r16, RSTFLR
andi r16, ~(1<
Table 9-1. Reset and Interrupt Vectors
Vector No. Program Address Label Interrupt Source
1 0x0000 RESET External Pin, Power-on Reset,
VLM Reset, Watchdog Reset
2 0x0001 INT0 External Interrupt Request 0
3 0x0002 PCINT0 Pin Change Interrupt Request 0
4 0x0003 TIM0_CAPT Timer/Counter0 Input Capture
5 0x0004 TIM0_OVF Timer/Counter0 Overflow
6 0x0005 TIM0_COMPA Timer/Counter0 Compare Match A
7 0x0006 TIM0_COMPB Timer/Counter0 Compare Match B
8 0x0007 ANA_COMP Analog Comparator
9 0x0008 WDT Watchdog Time-out
10 0x0009 VLM VCC Voltage Level Monitor
11 0x000A ADC ADC Conversion Complete (1)ATtiny4/5/9/10 [DATASHEET] 36
8127F–AVR–02/2013
0x000B RESET: ldi r16, high(RAMEND); Main program start
0x000C out SPH,r16 ; Set Stack Pointer
0x000D ldi r16, low(RAMEND) ; to top of RAM
0x000E out SPL,r16
0x000F sei ; Enable interrupts
0x0010
... ...
9.2 External Interrupts
External Interrupts are triggered by the INT0 pin or any of the PCINT3..0 pins. Observe that, if enabled, the interrupts
will trigger even if the INT0 or PCINT3..0 pins are configured as outputs. This feature provides a way of
generating a software interrupt. Pin change 0 interrupts PCI0 will trigger if any enabled PCINT3..0 pin toggles. The
PCMSK Register controls which pins contribute to the pin change interrupts. Pin change interrupts on PCINT3..0
are detected asynchronously, which means that these interrupts can be used for waking the part also from sleep
modes other than Idle mode.
The INT0 interrupt can be triggered by a falling or rising edge or a low level. This is set up as shown in “EICRA –
External Interrupt Control Register A” on page 37. When the INT0 interrupt is enabled and configured as level triggered,
the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts
on INT0 requires the presence of an I/O clock, as described in “Clock System” on page 17.
9.2.1 Low Level Interrupt
A low level interrupt on INT0 is detected asynchronously. This means that the interrupt source can be used for
waking the part also from sleep modes other than Idle (the I/O clock is halted in all sleep modes except Idle).
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long
enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of
the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined as
described in “Clock System” on page 17.
If the low level on the interrupt pin is removed before the device has woken up then program execution will not be
diverted to the interrupt service routine but continue from the instruction following the SLEEP command.
9.2.2 Pin Change Interrupt Timing
A timing example of a pin change interrupt is shown in Figure 9-1.ATtiny4/5/9/10 [DATASHEET] 37
8127F–AVR–02/2013
Figure 9-1. Timing of pin change interrupts
9.3 Register Description
9.3.1 EICRA – External Interrupt Control Register A
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bits 7:2 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 1:0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt
mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 9-2. The
value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer
than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If
clk
PCINT(0)
pin_lat
pin_sync
pcint_in_(0)
pcint_syn
pcint_setflag
PCIF
PCINT(0)
pin_sync
pcint_syn pin_lat D Q
LE
pcint_setflag
PCIF
clk
clk PCINT(0) in PCMSK(x)
pcint_in_(0) 0
x
Bit 7 6 5 4 3 2 1 0
0x15 – – – – – – ISC01 ISC00 EICRA
Read/Write R R R R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0ATtiny4/5/9/10 [DATASHEET] 38
8127F–AVR–02/2013
low level interrupt is selected, the low level must be held until the completion of the currently executing instruction
to generate an interrupt.
9.3.2 EIMSK – External Interrupt Mask Register
• Bits 7:1 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 0 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is
enabled. The Interrupt Sense Control bits (ISC01 and ISC00) in the External Interrupt Control Register A (EICRA)
define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity
on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of
External Interrupt Request 0 is executed from the INT0 Interrupt Vector.
9.3.3 EIFR – External Interrupt Flag Register
• Bits 7:1 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 0 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in
SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical
one to it.
This flag is constantly zero when INT0 is configured as a level interrupt.
Table 9-2. Interrupt 0 Sense Control
ISC01 ISC00 Description
0 0 The low level of INT0 generates an interrupt request.
0 1 Any logical change on INT0 generates an interrupt request.
1 0 The falling edge of INT0 generates an interrupt request.
1 1 The rising edge of INT0 generates an interrupt request.
Bit 7 6 5 4 3 2 1 0
0x13 – – – – – – – INTO EIMSK
Read/Write R R R R R R R R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x14 – – – – – – – INTF0 EIFR
Read/Write R R R R R R R R/W
Initial Value 0 0 0 0 0 0 0 0ATtiny4/5/9/10 [DATASHEET] 39
8127F–AVR–02/2013
9.3.4 PCICR – Pin Change Interrupt Control Register
• Bits 7:1 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 0 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is
enabled. Any change on any enabled PCINT3..0 pin will cause an interrupt. The corresponding interrupt of Pin
Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT3..0 pins are enabled individually by
the PCMSK Register.
9.3.5 PCIFR – Pin Change Interrupt Flag Register
• Bits 7:1 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 0 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT3..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in
SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag
is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
9.3.6 PCMSK – Pin Change Mask Register
• Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 3:0 – PCINT3..0: Pin Change Enable Mask 3..0
Each PCINT3..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT3..0 is
set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT3..0 is
cleared, pin change interrupt on the corresponding I/O pin is disabled.
Bit 7 6 5 4 3 2 1 0
0x12 – – – – – – – PCIE0 PCICR
Read/Write R R R R R R R R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x11 – – – – – – – PCIF0 PCIFR
Read/Write R R R R R R R R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x10 – – – – PCINT3 PCINT2 PCINT1 PCINT0 PCMSK
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0ATtiny4/5/9/10 [DATASHEET] 40
8127F–AVR–02/2013
10. I/O Ports
10.1 Overview
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that
the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the
SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling
of pull-up resistors. Each output buffer has symmetrical drive characteristics with both high sink and source
capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable
pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both VCC and
Ground as indicated in Figure 10-1 on page 40. See “Electrical Characteristics” on page 115 for a complete list of
parameters.
Figure 10-1. I/O Pin Equivalent Schematic
All registers and bit references in this section are written in general form. A lower case “x” represents the numbering
letter for the port, and a lower case “n” represents the bit number. However, when using the register or bit
defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented
generally as PORTxn. The physical I/O Registers and bit locations are listed in “Register Description” on
page 50.
Four I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data
Direction Register – DDRx, Pull-up Enable Register – PUEx, and the Port Input Pins – PINx. The Port Input Pins
I/O location is read only, while the Data Register, the Data Direction Register, and the Pull-up Enable Register are
read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit
in the Data Register.
Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page 41. Most port pins
are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes
with the port pin is described in “Alternate Port Functions” on page 45. Refer to the individual module sections
for a full description of the alternate functions.
Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port
as general digital I/O.
Cpin
Logic
Rpu
See Figure
"General Digital I/O" for
Details
PxnATtiny4/5/9/10 [DATASHEET] 41
8127F–AVR–02/2013
10.2 Ports as General Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a functional description of
one I/O-port pin, here generically called Pxn.
Figure 10-2. General Digital I/O(1)
Note: 1. WEx, WRx, WPx, WDx, REx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, and SLEEP
are common to all ports.
10.2.1 Configuring the Pin
Each port pin consists of four register bits: DDxn, PORTxn, PUExn, and PINxn. As shown in “Register Description”
on page 50, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, the
PUExn bits at the PUEx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured
as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.
clk
RPx
RRx
RDx
WDx
WEx
SYNCHRONIZER
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
clkI/O: I/O CLOCK
RDx: READ DDRx
WEx: WRITE PUEx
REx: READ PUEx
D
L
Q
Q
REx
RESET
RESET
Q
D Q
Q
Q D
CLR
PORTxn
Q
Q D
CLR
DDxn
PINxn
DATA BUS
SLEEP
SLEEP: SLEEP CONTROL
Pxn
I/O
WPx
RESET
Q
Q D
CLR
PUExn
0
1
WRx
WPx: WRITE PINx REGISTERATtiny4/5/9/10 [DATASHEET] 42
8127F–AVR–02/2013
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If
PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).
The pull-up resistor is activated, if the PUExn is written logic one. To switch the pull-up resistor off, PUExn has to
be written logic zero.
Table 10-1 summarizes the control signals for the pin value.
Port pins are tri-stated when a reset condition becomes active, even when no clocks are running.
10.2.2 Toggling the Pin
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI
instruction can be used to toggle one single bit in a port.
10.2.3 Break-Before-Make Switching
In Break-Before-Make mode, switching the DDRxn bit from input to output introduces an immediate tri-state period
lasting one system clock cycle, as indicated in Figure 10-3. For example, if the system clock is 4 MHz and the
DDRxn is written to make an output, an immediate tri-state period of 250 ns is introduced before the value of
PORTxn is seen on the port pin.
To avoid glitches it is recommended that the maximum DDRxn toggle frequency is two system clock cycles. The
Break-Before-Make mode applies to the entire port and it is activated by the BBMx bit. For more details, see
“PORTCR – Port Control Register” on page 50.
When switching the DDRxn bit from output to input no immediate tri-state period is introduced.
Table 10-1. Port Pin Configurations
DDxn PORTxn PUExn I/O Pull-up Comment
0 X 0 Input No Tri-state (hi-Z)
0 X 1 Input Yes Sources current if pulled low externally
1 0 0 Output No Output low (sink)
1 0 1 Output Yes
NOT RECOMMENDED.
Output low (sink) and internal pull-up active.
Sources current through the internal pull-up
resistor and consumes power constantly
1 1 0 Output No Output high (source)
1 1 1 Output Yes Output high (source) and internal pull-up activeATtiny4/5/9/10 [DATASHEET] 43
8127F–AVR–02/2013
Figure 10-3. Switching Between Input and Output in Break-Before-Make-Mode
10.2.4 Reading the Pin Value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As
shown in Figure 10-2 on page 41, the PINxn Register bit and the preceding latch constitute a synchronizer. This is
needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces
a delay. Figure 10-4 shows a timing diagram of the synchronization when reading an externally applied pin
value. The maximum and minimum propagation delays are denoted tpd,max and tpd,min respectively.
Figure 10-4. Synchronization when Reading an Externally Applied Pin value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when
the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC
LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at
the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition
on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 10-5
on page 44. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the
delay tpd through the synchronizer is one system clock period.
out DDRx, r16 nop
0x02 0x01
SYSTEM CLK
INSTRUCTIONS
DDRx
intermediate tri-state cycle
out DDRx, r17
PORTx 0x55
0x01
intermediate tri-state cycle
Px0
Px1
tri-state
tri-state tri-state
r17 0x01
r16 0x02
XXX in r17, PINx
0x00 0xFF
INSTRUCTIONS
SYNC LATCH
PINxn
r17
XXX
SYSTEM CLK
tpd, max
tpd, minATtiny4/5/9/10 [DATASHEET] 44
8127F–AVR–02/2013
Figure 10-5. Synchronization when Reading a Software Assigned Pin Value
10.2.5 Digital Input Enable and Sleep Modes
As shown in Figure 10-2 on page 41, the digital input signal can be clamped to ground at the input of the schmitttrigger.
The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down and Standby
modes to avoid high power consumption if some input signals are left floating, or have an analog signal level close
to VCC/2.
SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled,
SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in
“Alternate Port Functions” on page 45.
If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising
Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding
External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these
sleep mode produces the requested logic change.
10.2.6 Unconnected Pins
If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of
the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to
reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle
mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the
pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use
an external pull-up or pulldown. Connecting unused pins directly to VCC or GND is not recommended, since this
may cause excessive currents if the pin is accidentally configured as an output.
out PORTx, r16 nop in r17, PINx
0xFF
0x00 0xFF
SYSTEM CLK
r16
INSTRUCTIONS
SYNC LATCH
PINxn
r17
t pdATtiny4/5/9/10 [DATASHEET] 45
8127F–AVR–02/2013
10.2.7 Program Example
The following code example shows how to set port B pin 0 high, pin 1 low, and define the port pins from 2 to 3 as
input with a pull-up assigned to port pin 2. The resulting pin values are read back again, but as previously discussed,
a nop instruction is included to be able to read back the value recently assigned to some of the pins.
Note: See “Code Examples” on page 5.
10.3 Alternate Port Functions
Most port pins have alternate functions in addition to being general digital I/Os. In Figure 10-6 below is shown how
the port pin control signals from the simplified Figure 10-2 on page 41 can be overridden by alternate functions.
Assembly Code Example
...
; Define pull-ups and set outputs high
; Define directions for port pins
ldi r16,(1<> Cx must be observed for proper operation; a typical load capacitance (Cx) ranges from
5 – 20 pF while Cs is usually about 2 – 50 nF.
Increasing amounts of Cx destroy gain, therefore it is important to limit the amount of stray capacitance on both SNS
terminals. This can be done, for example, by minimizing trace lengths and widths and keeping these traces away
from power or ground traces or copper pours.
The traces and any components associated with SNS and SNSK will become touch sensitive and should be treated
with caution to limit the touch area to the desired location.
A series resistor, Rs, should be placed in line with SNSK to the electrode to suppress ESD and EMC effects.
2.4 Sensitivity
2.4.1 Introduction
The sensitivity on the QT1010 is a function of things like the value of Cs, electrode size and capacitance, electrode
shape and orientation, the composition and aspect of the object to be sensed, the thickness and composition of any
overlaying panel material, and the degree of ground coupling of both sensor and object.
2.4.2 Increasing Sensitivity
In some cases it may be desirable to increase sensitivity; for example, when using the sensor with very thick panels
having a low dielectric constant, or when the device is used as a proximity sensor. Sensitivity can often be increased
by using a larger electrode or reducing panel thickness. Increasing electrode size can have diminishing returns, as
high values of Cx will reduce sensor gain. AT42QT1010 [DATASHEET] 6
9541I–AT42–05/2013
The value of Cs also has a dramatic effect on sensitivity, and this can be increased in value with the trade-off of
slower response time and more power. Increasing the electrode's surface area will not substantially increase touch
sensitivity if its diameter is already much larger in surface area than the object being detected. Panel material can
also be changed to one having a higher dielectric constant, which will better help to propagate the field.
In the case of proximity detection, usually the object being detected is on an approaching hand, so a larger surface
area can be effective.
Ground planes around and under the electrode and its SNSK trace will cause high Cx loading and destroy gain. The
possible signal-to-noise ratio benefits of ground area are more than negated by the decreased gain from the circuit,
and so ground areas around electrodes are discouraged. Metal areas near the electrode will reduce the field strength
and increase Cx loading and should be avoided, if possible. Keep ground away from the electrodes and traces.
2.4.3 Decreasing Sensitivity
In some cases the QT1010 may be too sensitive. In this case gain can be easily lowered further by decreasing Cs.
2.4.4 Proximity Sensing
By increasing the sensitivity, the QT1010 can be used as a very effective proximity sensor, allowing the presence of
a nearby object (typically a hand) to be detected.
In this scenario, as the object being sensed is typically a hand, very large electrode sizes can be used, which is
extremely effective in increasing the sensitivity of the detector. In this case, the value of Cs will also need to be
increased to ensure improved sensitivity, as mentioned in Section 2.4.2. Note that, although this affects the
responsiveness of the sensor, it is less of an issue in proximity sensing applications; in such applications it is
necessary to detect simply the presence of a large object, rather than a small, precise touch.AT42QT1010 [DATASHEET] 7 9541I–AT42–05/2013
3. Operation Specifics
3.1 Run Modes
3.1.1 Introduction
The QT1010 has three running modes which depend on the state of the SYNC pin (high or low).
3.1.2 Fast Mode
The QT1010 runs in Fast mode if the SYNC pin is permanently high. In this mode the QT1010 runs at maximum
speed at the expense of increased current consumption. Fast mode is useful when speed of response is the prime
design requirement. The delay between bursts in Fast mode is approximately 1 ms, as shown in Figure 3-1.
Figure 3-1. Fast Mode Bursts (SYNC Held High)
3.1.3 Low Power Mode
The QT1010 runs in Low Power (LP) mode if the SYNC pin is held low. In this mode it sleeps for approximately
80 ms at the end of each burst, saving power but slowing response. On detecting a possible key touch, it temporarily
switches to Fast mode until either the key touch is confirmed or found to be spurious (via the detect integration
process). It then returns to LP mode after the key touch is resolved, as shown in Figure 3-2.
Figure 3-2. Low Power Mode (SYNC Held Low)
SNSK
SYNC
~1 ms
sleep sleep
SYNC
SNSK sleep
fast detect
integrator
OUT
Key
~80 ms
touchAT42QT1010 [DATASHEET] 8
9541I–AT42–05/2013
3.1.4 SYNC Mode
It is possible to synchronize the device to an external clock source by placing an appropriate waveform on the SYNC
pin. SYNC mode can synchronize multiple QT1010 devices to each other to prevent cross-interference, or it can be
used to enhance noise immunity from low frequency sources such as 50Hz or 60Hz mains signals.
The SYNC pin is sampled at the end of each burst. If the device is in Fast mode and the SYNC pin is sampled high,
then the device continues to operate in Fast mode (Figure 3-1 on page 7). If SYNC is sampled low, then the device
goes to sleep. From then on, it will operate in SYNC mode (Figure 3-2). Therefore, to guarantee entry into SYNC
mode the low period of the SYNC signal should be longer than the burst length (Figure 3-3).
Figure 3-3. SYNC Mode (Triggered by SYNC Edges)
However, once SYNC mode has been entered, if the SYNC signal consists of a series of short pulses (>10 µs) then
a burst will only occur on the falling edge of each pulse (Figure 3-4) instead of on each change of SYNC signal, as
normal (Figure 3-3).
In SYNC mode, the device will sleep after each measurement burst (just as in LP mode) but will be awakened by a
change in the SYNC signal in either direction, resulting in a new measurement burst. If SYNC remains unchanged
for a period longer than the LP mode sleep period (about 80 ms), the device will resume operation in either Fast or
LP mode depending on the level of the SYNC pin (Figure 3-3).
There is no detect integrator (DI) in SYNC mode (each touch is a detection) but the Max On-duration will depend on
the time between SYNC pulses; see Section 3.3 and Section 3.4 on page 9. Recalibration timeout is a fixed number
of measurements so will vary with the SYNC period.
Figure 3-4. SYNC Mode (Short Pulses)
SYNC
SYNC
SNSK
SNSK
slow mode sleep period
sleep
sleep
sleep sleep
sleep sleep
Revert to Fast Mode
Revert to Slow Mode
slow mode sleep period
SNSK
SYNC
>10 sμ >10 sμ >10 sμAT42QT1010 [DATASHEET] 9 9541I–AT42–05/2013
3.2 Threshold
The internal signal threshold level is fixed at 10 counts of change with respect to the internal reference level, which in
turn adjusts itself slowly in accordance with the drift compensation mechanism.
The QT1010 employs a hysteresis dropout of two counts of the delta between the reference and threshold levels.
3.3 Max On-duration
If an object or material obstructs the sense pad the signal may rise enough to create a detection, preventing further
operation. To prevent this, the sensor includes a timer which monitors detections. If a detection exceeds the timer
setting the sensor performs a full recalibration. This is known as the Max On-duration feature and is set to ~60s (at
3V in LP mode). This will vary slightly with Cs and if SYNC mode is used. As the internal timebase for Max Onduration
is determined by the burst rate, the use of SYNC can cause dramatic changes in this parameter depending
on the SYNC pulse spacing. For example, at 60Hz SYNC mode the Max On-duration will be ~6s at 3V.
3.4 Detect Integrator
It is desirable to suppress detections generated by electrical noise or from quick brushes with an object. To
accomplish this, the QT1010 incorporates a detect integration (DI) counter that increments with each detection until
a limit is reached, after which the output is activated. If no detection is sensed prior to the final count, the counter is
reset immediately to zero. In the QT1010, the required count is four. In LP mode the device will switch to Fast mode
temporarily in order to resolve the detection more quickly; after a touch is either confirmed or denied the device will
revert back to normal LP mode operation automatically.
The DI can also be viewed as a “consensus filter” that requires four successive detections to create an output.
3.5 Forced Sensor Recalibration
The QT1010 has no recalibration pin; a forced recalibration is accomplished when the device is powered up or after
the recalibration timeout. However, supply drain is low so it is a simple matter to treat the entire IC as a controllable
load; driving the QT1010's Vdd pin directly from another logic gate or a microcontroller port will serve as both power
and “forced recalibration”. The source resistance of most CMOS gates and microcontrollers is low enough to provide
direct power without problem.
3.6 Drift Compensation
Signal drift can occur because of changes in Cx and Cs over time. It is crucial that drift be compensated for,
otherwise false detections, non-detections, and sensitivity shifts will follow.
Drift compensation (Figure 3-5) is performed by making the reference level track the raw signal at a slow rate, but
only while there is no detection in effect. The rate of adjustment must be performed slowly, otherwise legitimate
detections could be ignored. The QT1010 drift compensates using a slew-rate limited change to the reference level;
the threshold and hysteresis values are slaved to this reference.
Once an object is sensed, the drift compensation mechanism ceases since the signal is legitimately high, and
therefore should not cause the reference level to change.AT42QT1010 [DATASHEET] 10
9541I–AT42–05/2013
Figure 3-5. Drift Compensation
The QT1010 drift compensation is asymmetric; the reference level drift-compensates in one direction faster than it
does in the other. Specifically, it compensates faster for decreasing signals than for increasing signals. Increasing
signals should not be compensated for quickly, since an approaching finger could be compensated for partially or
entirely before even approaching the sense electrode. However, an obstruction over the sense pad, for which the
sensor has already made full allowance, could suddenly be removed leaving the sensor with an artificially elevated
reference level and thus become insensitive to touch. In this latter case, the sensor will compensate for the object's
removal very quickly, usually in only a few seconds.
With large values of Cs and small values of Cx, drift compensation will appear to operate more slowly than with the
converse. Note that the positive and negative drift compensation rates are different.
3.7 Response Time
The QT1010's response time is highly dependent on run mode and burst length, which in turn is dependent on Cs
and Cx. With increasing Cs, response time slows, while increasing levels of Cx reduce response time. The response
time will also be a lot slower in LP or SYNC mode due to a longer time between burst measurements.
3.8 Spread Spectrum
The QT1010 modulates its internal oscillator by ±7.5% during the measurement burst. This spreads the generated
noise over a wider band, reducing emission levels. This also reduces susceptibility since there is no longer a single
fundamental burst frequency.
3.9 Output Features
3.9.1 Output
The output of the QT1010 is active-high upon detection. The output will remain active-high for the duration of the
detection, or until the Max On-duration expires, whichever occurs first. If a Max On-duration timeout occurs first, the
sensor performs a full recalibration and the output becomes inactive (low) until the next detection.
3.9.2 HeartBeat Output
The QT1010 output has a HeartBeat “health” indicator superimposed on it in all modes. This operates by taking the
output pin into a three-state mode for 15 µs, once before every QT burst. This output state can be used to determine
that the sensor is operating properly, using one of several simple methods, or it can be ignored.
The HeartBeat indicator can be sampled by using a pull-up resistor on the OUT pin (Figure 3-6), and feeding the
resulting positive-going pulse into a counter, flip flop, one-shot, or other circuit. The pulses will only be visible when
the chip is not detecting a touch.
Threshold
Signal
Hysteresis
Reference
OutputAT42QT1010 [DATASHEET] 11 9541I–AT42–05/2013
Figure 3-6. Obtaining HeartBeat Pulses with a Pull-up Resistor (SOT23-6)
If the sensor is wired to a microcontroller as shown in Figure 3-7 on page 11, the microcontroller can reconfigure the
load resistor to either Vss or Vdd depending on the output state of the QT1010, so that the pulses are evident in
either state.
Figure 3-7. Using a Microcontroller to Obtain HeartBeat Pulses in Either Output State (SOT23-6)
Electromechanical devices like relays will usually ignore the short HeartBeat pulse. The pulse also has too low a duty
cycle to visibly affect LEDs. It can be filtered completely if desired, by adding an RC filter to the output, or if
interfacing directly and only to a high-impedance CMOS input, by doing nothing or at most adding a small noncritical
capacitor from OUT to Vss.
3.9.3 Output Drive
The OUT pin is active high and can sink or source up to 2 mA. When a large value of Cs (>20 nF) is used the OUT
current should be limited to <1 mA to prevent gain-shifting side effects, which happen when the load current creates
voltage drops on the die and bonding wires; these small shifts can materially influence the signal level to cause
detection instability.
OUT
VDD
SNSK
SNS
SYNC/MODE
VSS
2
6
4
1 3
5
VDD
HeartBeat" Pulse Ro
OUT SNSK
SNS
SYNC/MODE 6
4
1 3 Ro
Microcontroller
Port_M.x
Port_M.yAT42QT1010 [DATASHEET] 12
9541I–AT42–05/2013
4. Circuit Guidelines
4.1 More Information
Refer to Application Note QTAN0002, Secrets of a Successful QTouch Design and the Touch Sensors Design Guide
(both downloadable from the Atmel website), for more information on construction and design methods.
4.2 Sample Capacitor
Cs is the charge sensing sample capacitor. The required Cs value depends on the thickness of the panel and its
dielectric constant. Thicker panels require larger values of Cs. Typical values are 2 nF to 50 nF depending on the
sensitivity required; larger values of Cs demand higher stability and better dielectric to ensure reliable sensing.
The Cs capacitor should be a stable type, such as X7R ceramic or PPS film. For more consistent sensing from unit
to unit, 5% tolerance capacitors are recommended. X7R ceramic types can be obtained in 5% tolerance at little or no
extra cost. In applications where high sensitivity (long burst length) is required the use of PPS capacitors is
recommended.
For battery powered operation a higher value sample capacitor is recommended (typical value 8.2 nF).
4.3 UDFN/USON Package Restrictions
The central pad on the underside of the UDFN/USON chip is connected to ground. Do not run any tracks underneath
the body of the chip, only ground.
4.4 Power Supply and PCB Layout
See Section 5.2 on page 14 for the power supply range. At 3 V current drain averages less than 500 µA in Fast
mode.
If the power supply is shared with another electronic system, care should be taken to ensure that the supply is free of
digital spikes, sags, and surges which can adversely affect the QT1010. The QT1010 will track slow changes in Vdd,
but it can be badly affected by rapid voltage fluctuations. It is highly recommended that a separate voltage regulator
be used just for the QT1010 to isolate it from power supply shifts caused by other components.
If desired, the supply can be regulated using a Low Dropout (LDO) regulator, although such regulators often have
poor transient line and load stability. See Application Note QTAN0002, Secrets of a Successful QTouch™ Design for
further information.
Parts placement: The chip should be placed to minimize the SNSK trace length to reduce low frequency pickup,
and to reduce stray Cx which degrades gain. The Cs and Rs resistors (see Figure 1-1 on page 4) should be placed
as close to the body of the chip as possible so that the trace between Rs and the SNSK pin is very short, thereby
reducing the antenna-like ability of this trace to pick up high frequency signals and feed them directly into the chip. A
ground plane can be used under the chip and the associated discrete components, but the trace from the Rs resistor
and the electrode should not run near ground, to reduce loading.
For best EMC performance the circuit should be made entirely with SMT components.
Electrode trace routing: Keep the electrode trace (and the electrode itself) away from other signal, power, and
ground traces including over or next to ground planes. Adjacent switching signals can induce noise onto the sensing
signal; any adjacent trace or ground plane next to, or under, the electrode trace will cause an increase in Cx load and
desensitize the device.
Note: For proper operation a 100 nF (0.1 µF) ceramic bypass capacitor must be used directly between Vdd and
Vss, to prevent latch-up if there are substantial Vdd transients; for example, during an ESD event. The
bypass capacitor should be placed very close to the Vss and Vdd pins.AT42QT1010 [DATASHEET] 13 9541I–AT42–05/2013
4.5 Power On
On initial power up, the QT1010 requires approximately 100 ms to power on to allow power supplies to stabilize.
During this time the OUT pin state is not valid and should be ignored.AT42QT1010 [DATASHEET] 14
9541I–AT42–05/2013
5. Specifications
5.1 Absolute Maximum Specifications
5.2 Recommended Operating Conditions
5.3 AC Specifications
Operating temperature –40°C to +85°C
Storage temperature –55°C to +125°C
VDD 0 to +6.5 V
Max continuous pin current, any control or drive pin ±20 mA
Short circuit duration to Vss, any pin Infinite
Short circuit duration to Vdd, any pin Infinite
Voltage forced onto any pin –0.6V to (Vdd + 0.6) V
CAUTION: Stresses beyond those listed under Absolute Maximum Specifications may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum specification
conditions for extended periods may affect device reliability
VDD +1.8 to 5.5 V
Short-term supply ripple + noise ±20 mV
Long-term supply stability ±100 mV
Cs value 2 to 50 nF
Cx value 5 to 50 pF
Vdd = 3.0 V, Cs = 4.7 nF, Cx = 5 pF, Ta = recommended range, unless otherwise noted
Parameter Description Min Typ Max Units Notes
TRC Recalibration time – 200 – ms Cs, Cx dependent
TPC Charge duration – 3.05 – µs ±7.5% spread spectrum variation
TPT Transfer duration – 9.0 – µs ±7.5% spread spectrum variation
TG1 Time between end of burst and
start of the next (Fast mode) – 1.2 – ms
TG2 Time between end of burst and
start of the next (LP mode) – 80 – ms Increases with decreasing VDD
See Figure 5-1 on page 15AT42QT1010 [DATASHEET] 15 9541I–AT42–05/2013
Figure 5-1. TG2 – Time Between Bursts (LP Mode)
Figure 5-2. TBL – Burst Length
TBL Burst length – 2.45 – ms
VDD, Cs and Cx dependent. See
Section 4.2 for capacitor
selection.
TR Response time – – 100 ms
THB HeartBeat pulse width – 15 – µs
Vdd = 3.0 V, Cs = 4.7 nF, Cx = 5 pF, Ta = recommended range, unless otherwise noted
Parameter Description Min Typ Max Units NotesAT42QT1010 [DATASHEET] 16
9541I–AT42–05/2013
5.4 Signal Processing
5.5 DC Specifications
Vdd = 3.0V, Cs = 4.7 nF, Cx = 5 pF, Ta = recommended range, unless otherwise noted
Description Min Typ Max Units Notes
Threshold differential 10 counts
Hysteresis 2 counts
Consensus filter length 4 samples
Max on-duration 60 seconds (At 3 V in LP mode) Will vary
in SYNC mode and with Vdd
Vdd = 3.0V, Cs = 4.7 nF, Cx = 5 pF, Ta = recommended range, unless otherwise noted
Parameter Description Min Typ Max Units Notes
VDD Supply voltage 1.8 5.5 V
IDD Supply current, Fast mode –
203.0
246.0
378.5
542.5
729.0
– µA
1.8 V
2.0 V
3.0 V
4.0 V
5.0 V
IDDI Supply current, LP mode –
16.5
19.5
34.0
51.5
73.5
– µA
1.8 V
2.0 V
3.0 V
4.0 V
5.0 V
VDDS Supply turn-on slope 10 – – V/s Required for proper start-up
VIL Low input logic level – – 0.2 × Vdd
0.3 × Vdd V Vdd = 1.8 V – 2.4 V
Vdd = 2.4 V – 5.5 V
VHL High input logic level 0.7 × Vdd
0.6 × Vdd – – V Vdd = 1.8 V – 2.4 V
Vdd = 2.4 V – 5.5 V
VOL Low output voltage – – 0.5 V OUT, 4 mA sink
VOH High output voltage 2.3 – – V OUT, 1 mA source
IIL Input leakage current – <0.05 1 µA
CX Load capacitance range 2 – 50 pF
AR Acquisition resolution – 9 14 bitsAT42QT1010 [DATASHEET] 17 9541I–AT42–05/2013
5.6 Mechanical Dimensions
5.6.1 6-pin SOT23-6
9524D–AT42–05/2013
Features
Number of QTouch® Keys:
Up to four
Discrete Outputs:
Four discrete outputs indicating individual key touch
Technology:
Patented spread-spectrum charge-transfer (direct mode)
Electrode Design:
Simple self-capacitance style (refer to the Touch Sensors Design Guide)
Electrode Materials:
Etched copper, silver, carbon, Indium Tin Oxide (ITO)
Electrode Substrates:
PCB, FPCB, plastic films, glass
Panel Materials:
Plastic, glass, composites, painted surfaces (low particle density metallic
paints possible)
Panel Thickness:
Up to 10 mm glass, 5 mm plastic (electrode size dependent)
Key Sensitivity:
Fixed key threshold, sensitivity adjusted via sample capacitor value
Adjacent Key Suppression
Patented Adjacent Key Suppression® (AKS®) technology to enable accurate
key detection
Interface:
Pin-per-key outputs, plus debug mode to observe sensor signals
Moisture Tolerance:
Increased moisture tolerance based on hardware design and firmware tuning
Signal Processing:
Self-calibration, auto drift compensation, noise filtering
Applications:
Mobile, consumer, white goods, toys, kiosks, POS, and so on
Power:
1.8 V – 5.5 V
Package:
20-pin 3 x 3 mm VQFN RoHS compliant
Atmel AT42QT1040
Four-key QTouch® Touch Sensor IC
DATASHEETAT42QT1040 [DATASHEET] 2
9524D–AT42–05/2013
1. Pinout and Schematic
1.1 Pinout Configuration
NC
NC
VSS
VDD
NC
SNS2
SNSK1
SNS1
SNSK0
SNS0 OUT0
OUT1
1
2
3
4
5 11
12
13
14
15
20 19 18 17 16
6 7 8 9 10
QT1040 OUT3
OUT2
SNSK3
SNSK2
NC
NC
NC
SNS3AT42QT1040 [DATASHEET] 3 9524D–AT42–05/2013
1.2 Pin Descriptions
I/O CMOS input and output OD CMOS open drain output P Ground or power
Table 1-1. Pin Listing
Pin Name Type Function Notes If Unused...
1 SNS2 I/O Sense pin To Cs2 Leave open
2 SNSK1 I/O Sense pin and option detect To Cs1 and option resistor +
key
Connect to option
resistor*
3 SNS1 I/O Sense pin To Cs1 Leave open
4 SNSK0 I/O Sense pin and option detect To Cs0 and option resistor +
key
Connect to option
resistor*
5 SNS0 I/O Sense pin To Cs0 Leave open
6 N/C – – –
7 N/C – – –
8 Vss P Supply ground –
9 Vdd P Power –
10 N/C – – –
11 OUT0 OD Out 0 Alternative function: Debug
CLK Leave open
12 OUT1 OD Out 1 Alternative function: Debug
DATA Leave open
13 OUT3 OD Out 3 Leave open
14 OUT2 OD Out 2 Leave open
15 SNSK3 I/O Sense pin To Cs3 + key Leave open
16 SNS3 I/O Sense pin To Cs3 Leave open
17 N/C – – –
18 N/C – – –
19 N/C – – –
20 SNSK2 I/O Sense pin To Cs2 + key Leave open
* Option resistor should always be fitted even if channel is unused and Cs capacitor is not fixed.AT42QT1040 [DATASHEET] 4
9524D–AT42–05/2013
1.3 Schematic
Figure 1-1. Typical Circuit
Suggested regulator manufacturers:
Torex (XC6215 series)
Seiko (S817 series)
BCDSemi (AP2121 series)
For component values in Figure 1-1 check the following sections:
Section 3.1 on page 7: Cs capacitors (Cs0 – Cs3)
Section 3.5 on page 7: Voltage levels
Section 3.3 on page 7: LED traces
SLOW
FAST
OFF
LED3
LED2
LED1
LED0
VDD
VDD
2
1
3
J2
VDD
2
1
3
J1
ON
2 2
5 5
4 4
3 3
1 1
J3
VDD 9 VSS 8
N/C 19
N/C 10
OUT2 14
SNSK3 15
SNSK2 20
SNSK1 2
SNSK0 4
N/C 18
N/C 7
N/C 17
OUT1 12
OUT0 11
SNS3 16
SNS1 3
N/C 6
OUT3 13 SNS0 5
SNS2 1
SPEED SELECT
AKS SELECT
NOTES:
1) The central pad on the underside of the VQFN chip is a Vss pin and should be connected
to ground. Do not put any other tracks underneath the body of the chip.
2) It is important to place all Cs and Rs components physically near to the chip.
Add a 100 nF capacitor close to pin 9.
QT1040
Creg Creg
VREG
Follow regulator manufacturer's
recommended values for input
and output bypass capacitors (Creg).
Key0
Key1
Key2
Key3
VUNREG
GND
Cs0
Cs1
Cs2
Cs3
RL0
RL1
RL2
RL3
RAKS
RFS
Rs0
Rs1
Rs2
Rs3
Example use of output pinsAT42QT1040 [DATASHEET] 5 9524D–AT42–05/2013
2. Overview of the AT42QT1040
2.1 Introduction
The AT42QT1040 (QT1040) is a digital burst mode charge-transfer (QT™) capacitive sensor driver designed for
touch-key applications. The device can sense from one to four keys; one to three keys can be disabled by not
installing their respective sense capacitors. Any of the four channels can be disabled in this way.
The device includes all signal processing functions necessary to provide stable sensing under a wide variety of
changing conditions, and the outputs are fully de-bounced. Only a few external parts are required for operation.
The QT1040 modulates its bursts in a spread-spectrum fashion in order to heavily suppress the effects of external
noise, and to suppress RF emissions.
2.2 Signal Processing
2.2.1 Detect Threshold
The internal signal threshold level is fixed at 10 counts of change with respect to the internal reference level. This in
turn adjusts itself slowly in accordance with the drift compensation mechanism. See Section 3.1 on page 7 for details
on how to adjust the sensitivity of each key.
When going out of detect there is a hysteresis element to the detection. The signal threshold must drop below 8
counts of change with respect to the internal reference level to register as un-touched.
2.2.2 Detection Integrator
The device features a detection integration mechanism, which acts to confirm a detection in a robust fashion. A perkey
counter is incremented each time the key has exceeded its threshold, and a key is only finally declared to be
touched when this counter reaches a fixed limit of 5. In other words, the device has to exceed its threshold, and stay
there for 5 acquisitions in succession without going below the threshold level, before the key is declared to be
touched.
2.2.3 Burst Length Limitations
Burst length is the number of times the charge transfer process is performed on a given channel; that is, the number
of pulses it takes to measure the key capacitance.
The maximum burst length is 2048 pulses. The recommended design is to use a capacitor that gives a signal of
<1000 pulses. Longer bursts take more time and use more power.
Note that the keys are independent of each other. It is therefore possible, for example, to have a signal of 100 on one
key and a signal of 1000 on another.
Refer to Application Note QTAN0002, Secrets of a Successful QTouch Design (downloadable from the Atmel
website), for more information on using a scope to measure the pulses and hence determine the burst length. Refer
also to the Touch Sensors Design Guide.
2.2.4 Adjacent Key Suppression Technology
The device includes the Atmel-patented Adjacent Key Suppression (AKS) technology, to allow the use of tightly
spaced keys on a keypad with no loss of selectability by the user.
There is one global AKS group, implemented so that only one key in the group may be reported as being touched at
any one time.
The use of AKS is selected by connecting a 1 M resistor between Vdd and the SNSK0 pin (see Section 4.1 on
page 9 for more information). When AKS is disabled, any combinations of keys can enter detect.AT42QT1040 [DATASHEET] 6
9524D–AT42–05/2013
2.2.5 Auto Drift Compensation
Signal drift can occur because of changes in Cx and Cs over time. It is crucial that drift be compensated for,
otherwise false detections, non-detections, and sensitivity shifts will follow.
Drift compensation is performed by making the reference level track the raw signal at a slow rate, but only while
there is no detection in effect. The rate of adjustment must be performed slowly otherwise legitimate detections could
be ignored.
Once an object is sensed and a key is in detect, the drift compensation mechanism ceases, since the signal is
legitimately high and should not therefore cause the reference level to change.
The QT1040 drift compensation is asymmetric, that is, the reference level drift-compensates in one direction faster
than it does in the other. Specifically, it compensates faster for decreasing (towards touch) signals than for
increasing (away from touch) signals. The reason for this difference in compensation rates is that increasing signals
should not be compensated for quickly, since a nearby finger could be compensated for partially or entirely before
even approaching the sense electrode. However, decreasing signals need to be compensated for more quickly. For
example, an obstruction over the sense pad (for which the sensor has already made full allowance) could suddenly
be removed, leaving the sensor with an artificially elevated reference level and thus become insensitive to touch. In
this latter case, the sensor will compensate for the object's removal very quickly, usually in only a few seconds.
Negative drift (that is, towards touch) occurs at a rate of ~3 seconds, while positive drift occurs at a rate of
~1 second.
Drifting only occurs when no keys are in detect state.
2.2.6 Response Time
The QT1040 response time is highly dependent on run mode and burst length, which in turn is dependent on Cs and
Cx. With increasing Cs, response time slows, while increasing levels of Cx reduce response time. The response time
will also be slower in slow mode due to a longer time between burst measurements. This mode offers an increased
detection latency in favor of reduced average current consumption.
2.2.7 Spread Spectrum
The QT1040 modulates its internal oscillator by ±7.5% during the measurement burst. This spreads the generated
noise over a wider band reducing emission levels. This also reduces susceptibility since there is no longer a single
fundamental burst frequency.
2.2.8 Max On-duration
If an object or material obstructs the sense pad, the signal may rise enough to create a detection, preventing further
operation. To prevent this, the sensor includes a timer known as the Max On-duration feature which monitors
detections. If a detection exceeds the timer setting, the sensor performs an automatic recalibration. Max On-duration
is set to ~30s.AT42QT1040 [DATASHEET] 7 9524D–AT42–05/2013
3. Wiring and Parts
3.1 Cs Sample Capacitors
Cs0 – Cs3 are the charge sensing sample capacitors; normally they are identical in nominal value. The optimal Cs
values depend on the corresponding keys electrode design, the thickness of the panel and its dielectric constant.
Thicker panels require larger values of Cs. Values can be in the range 2.2 nF (for faster operation) to 22 nF (for best
sensitivity); typical values are 4.7 nF to 10 nF.
The value of Cs should be chosen such that a light touch on a key mounted in a production unit or a prototype panel
causes a reliable detection. The chosen Cs value should never be so large that the key signals exceed ~1000, as
reported by the chip in the debug data.
The Cs capacitors must be X7R or PPS film type, for stability. For consistent sensitivity, they should have a 10%
tolerance. Twenty percent tolerance may cause small differences in sensitivity from key to key and unit to unit. If a
key is not used, the Cs capacitor may be omitted.
3.2 Rs Resistors
The series resistors Rs0 – Rs3 are in line with the electrode connections (close to the QT1040 chip) and are used to
limit electrostatic discharge (ESD) currents and to suppress radio frequency (RF) interference. A typical value is
4.7 k, but up to 20 k can be used if it is found to be of benefit.
Although these resistors may be omitted, the device may become susceptible to external noise or radio frequency
interference (RFI). For details on how to select these resistors refer to Application Note QTAN0002, Secrets of a
Successful QTouch Design, and the Touch Sensors Design Guide, both downloadable from the Touch Technology
area of the Atmel website, www.atmel.com.
3.3 LED Traces and Other Switching Signals
For advice on LEDs and nearby traces, refer to Application Note QTAN0002, Secrets of a Successful QTouch
Design, and the Touch Sensors Design Guide, both downloadable from the Touch Technology area of Atmel’s
website, www.atmel.com.
3.4 PCB Cleanliness
Modern no-clean flux is generally compatible with capacitive sensing circuits.
3.5 Power Supply
See Section 5.2 on page 15 for the power supply range. If the power supply fluctuates slowly with temperature, the
device tracks and compensates for these changes automatically with only minor changes in sensitivity. If the supply
voltage drifts or shifts quickly, the drift compensation mechanism is not able to keep up, causing sensitivity
anomalies or false detections.
The usual power supply considerations with QT parts apply to the device. The power should be clean and come from
a separate regulator if possible. However, this device is designed to minimize the effects of unstable power, and
except in extreme conditions should not require a separate Low Dropout (LDO) regulator.
CAUTION: If a PCB is reworked to correct soldering faults relating to the device, or
to any associated traces or components, be sure that you fully understand the
nature of the flux used during the rework process. Leakage currents from
hygroscopic ionic residues can stop capacitive sensors from functioning. If you
have any doubts, a thorough cleaning after rework may be the only safe option.AT42QT1040 [DATASHEET] 8
9524D–AT42–05/2013
See under Figure 1.3 on page 4 for suggested regulator manufacturers.
It is assumed that a larger bypass capacitor (for example, 1 µF) is somewhere else in the power circuit; for example,
near the regulator.
To assist with transient regulator stability problems, the QT1040 waits 500 µs any time it wakes up from a sleep state
(that is, in Sleep mode) before acquiring, to allow Vdd to fully stabilize.
3.6 VQFN Package Restrictions
The central pad on the underside of the VQFN chip should be connected to ground. Do not run any tracks
underneath the body of the chip, only ground. Figure 3-1 shows an example of good/bad tracking.
Figure 3-1. Examples of Good and Bad Tracking
Caution: A regulator IC shared with other logic can result in erratic operation and is
not advised.
A single ceramic 0.1 µF bypass capacitor, with short traces, should be placed very
close to the power pins of the IC. Failure to do so can result in device oscillation, high
current consumption, erratic operation, and so on.
Example of GOOD tracking Example of BAD trackingAT42QT1040 [DATASHEET] 9 9524D–AT42–05/2013
4. Detailed Operations
4.1 Adjacent Key Suppression
The use of AKS is selected by the connection of a 1 M resistor (RAKS resistor) between the SNSK0 pin and either
Vdd (AKS mode on) or Vss (AKS mode off).
Note: Changing the RAKS option will affect the sensitivity of the particular key. Always check that the sensitivity is
suitable after a change. Retune Cs0 if necessary.
4.2 Discrete Outputs
There are four discrete outputs (channels 0 to 3), located on pins OUT0 to OUT3. An output pin goes active when
the corresponding key is touched. The outputs are open-drain type and are active-low.
On the OUT2 pin there is a ~500 ns low pulse occurring approximately 20 ms after a power-up/reset (see Figure 4-1
for an example oscilloscope trace of this pulse at two zoom levels). This pulse may need to be considered from the
system design perspective.
The discrete outputs have sufficient current sinking capability to directly drive LEDs. Try to limit the sink current to
less than 5 mA per output and be cautious if connecting LEDs to a power supply other than Vdd; if the LED supply is
higher than Vdd it may cause erratic behavior of the QT1040 and back-power the QT1040 through its I/O pins.
Table 4-1. RAKS Resistor
RAKS Connected To... Mode
Vdd AKS on
Vss AKS off
The RAKS resistor should always be connected to either Vdd or Vss and should not be
changed during operation of the device.AT42QT1040 [DATASHEET] 10
9524D–AT42–05/2013
Figure 4-1. ~500 ns Pulse On OUT2 Pin
4.3 Speed Selection
Speed selection is determined by a 1 M resistor (RFS resistor) connected between SNSK1 and either Vdd (Fast
Mode) or Vss (Slow Mode).
In Fast Mode, the device sleeps for 16 ms between burst acquisitions. In Slow Mode, the device sleeps for 64 ms
between acquisitions. Hence, Slow Mode conserves more power but results in slightly less responsiveness.
Note: The RFS resistor should always be connected to either Vdd or Vss and not changed during operation of the
device. Changing the RFS option will affect the sensitivity of the particular key. Always check that the
sensitivity is suitable after a change. Retune Cs1 if necessary.
4.4 Moisture Tolerance
The presence of water (condensation, sweat, spilt water, and so on) on a sensor can alter the signal values
measured and thereby affect the performance of any capacitive device. The moisture tolerance of QTouch devices
can be improved by designing the hardware and fine-tuning the firmware following the recommendations in the
application note Atmel AVR3002: Moisture Tolerant QTouch Design (www.atmel.com/Images/doc42017.pdf).
Pulse on OUT2
SNS0K
OUT2
SNS0K
OUT2
Power-on/ ~20 ms
Reset
Table 4-2. RFS Resistor
RFS Connected To Mode
Vdd Fast mode
Vss Slow modeAT42QT1040 [DATASHEET] 11 9524D–AT42–05/2013
4.5 Calibration
Calibration is the process by which the sensor chip assesses the background capacitance on each channel. During
calibration, a number of samples are taken in quick succession to get a baseline for the channel reference value.
Calibration takes place ~50 ms after power is applied to the device. Calibration also occurs if the Max On-duration is
exceeded or a positive re-calibration occurs.
4.6 Debug Mode
An added feature to this device is a debug option whereby internal parameters from the IC can be clocked out and
monitored externally.
Debug mode is entered by shorting the CS3 capacitor (SNSK3 and SNS3 pins) on power-up and removing the short
within 5 seconds.
Note: If the short is not removed within 5 seconds, debug mode is still entered, but with Channel 3 unusable until
a re-calibration occurs. Note that as Channel 3 will show as being in detect, a recalibration will occur after
Max On-duration (~30 seconds).
Debug CLK pin (OUT0) and Debug Data pin (OUT1) float while debug data is not being output and are driven
outputs once debug output starts (that is, not open drain).
The serial data is clocked out at a rate of ~200 kHz, MSB first, as in Table 4-3.
Table 4-3. Serial Data Output
Byte Purpose Notes
0 Frame Number Framing index number 0-255
1 Chip Version Upper nibble: major revision
Lower nibble: minor revision
2 Reference 0 Low Byte
Unsigned 16-bit integer
3 Reference 0 High Byte
4 Reference 1 Low Byte
Unsigned 16-bit integer
5 Reference 1 High Byte
6 Reference 2 Low Byte
Unsigned 16-bit integer
7 Reference 2 High Byte
8 Reference 3 Low Byte
Unsigned 16-bit integer
9 Reference 3 High Byte
10 Signal 0 Low Byte
Unsigned 16-bit integer
11 Signal 0 High Byte
12 Signal 1 Low Byte
Unsigned 16-bit integer
13 Signal 1 High Byte
14 Signal 2 Low Byte
Unsigned 16-bit integer
15 Signal 2 High Byte
16 Signal 3 Low Byte
Unsigned 16-bit integer
17 Signal 3 High ByteAT42QT1040 [DATASHEET] 12
9524D–AT42–05/2013
Bit 7: This bit is set during calibration
Bits 4 – 6: Contains the number of keys active
Bits 0 – 3: Show the touch status of the corresponding keys
Figure 4-2 to Figure 4-5 show the usefulness of the debug data out feature. Channels can be monitored and tweaked
to the specific application with great accuracy.
18 Delta 0 Low Byte
Signed 16-bit integer
19 Delta 0 High Byte
20 Delta 1 Low Byte
Signed 16-bit integer
21 Delta 1 High Byte
22 Delta 2 Low Byte
Signed 16-bit integer
23 Delta 2 High Byte
24 Delta 3 Low Byte
Signed 16-bit integer
25 Delta 3 High Byte
26 Flags Various operational flags
27 Flags2 Unsigned bytes
28 Status Byte Unsigned byte. See Table 4-4
29 Frame Number Repeat of framing index number in
byte 0
Table 4-4. Status Byte (Byte 28)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CAL Number of Keys (2 – 4) Key 3 Key 2 Key 1 Key 0
Table 4-3. Serial Data Output (Continued)
Byte Purpose NotesAT42QT1040 [DATASHEET] 13 9524D–AT42–05/2013
Figure 4-2. Byte Clocked Out (~5 µs Period)
Figure 4-3. Byte Following Byte (~ 30 µs Period)
Figure 4-4. Full Debug Send (30 Bytes)AT42QT1040 [DATASHEET] 14
9524D–AT42–05/2013
Figure 4-5. Debug Lines Floating Between Debug Data Sends (30 Bytes, ~2 ms to Send)AT42QT1040 [DATASHEET] 15 9524D–AT42–05/2013
5. Specifications
5.1 Absolute Maximum Specifications
5.2 Recommended Operating Conditions
5.3 DC Specifications
Vdd –0.5 to +6.0 V
Max continuous pin current, any control or drive pin ±10 mA
Voltage forced onto any pin –0.5 V to (Vdd + 0.5) V
Operating temperature –40°C to +85°C
Storage temperature –55°C to +125°C
Vdd 1.8 V to 5.5 V
Supply ripple + noise ±20 mV maximum
Cx capacitance per key 2 to 20 pF
Vdd = 5.0 V, Cs = 4.7 nF, Ta = recommended range, unless otherwise noted
Parameter Description Min Typ Max Units Notes
Vil Low input logic level –0.5 – 0.3 V
Vih High input logic level 0.6 × Vdd Vdd Vdd + 0.5 V
Vol Low output voltage 0 – 0.7 V 10 mA sink current
Voh High output voltage 0.8 × Vdd – Vdd V 10 mA source current
Iil Input leakage current – <0.05 1 µA
Rrst Internal RST pull-up resistor 20 – 50 k
CAUTION: Stresses beyond those listed under Absolute Maximum Specifications may cause permanent damage
the device. This is a stress rating only and functional operation of the device at these or other conditions beyo
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximu
specification conditions for extended periods may affect device reliabilityAT42QT1040 [DATASHEET] 16
9524D–AT42–05/2013
5.4 Timing Specifications
5.5 Power Consumption
Parameter Description Min Typ Max Units Notes
TBS Burst duration – 3.5 – ms Cx = 5 pF, Cs = 18 nF
Fc Burst center frequency – 119 – kHz
Fm Burst modulation, percentage –7.5 – +7.5 %
TPW Burst pulse width – 2 – µs
Vdd (V) AKS Mode (RAKS) Speed (RFS) Power Consumption (µA)
1.8
Off Slow 31
Off Fast 104
On Slow 36
On Fast 114
3.3
Off Slow 100
Off Fast 340
On Slow 117
On Fast 380
5.0
Off Slow 215
Off Fast 710
On Slow 245
On Fast 800AT42QT1040 [DATASHEET] 17 9524D–AT42–05/2013
5.6 Mechanical Dimensions
Features
• High performance, low power AVR® 8-bit Microcontroller
• Advanced RISC architecture
– 135 powerful instructions – most single clock cycle execution
– 32 × 8 general purpose working registers
– Fully static operation
– Up to 16MIPS throughput at 16MHz
– On-chip 2-cycle multiplier
• Non-volatile program and data memories
– 64/128Kbytes of in-system self-programmable flash
• Endurance: 100,000 write/erase cycles
– Optional Boot Code section with independent lock bits
• USB boot loader programmed by default in the factory
• In-system programming by on-chip boot program hardware activated after
reset
• True read-while-write operation
• All supplied parts are pre-programed with a default USB bootloader
– 2K/4K (64K/128K flash version) bytes EEPROM
• Endurance: 100,000 write/erase cycles
– 4K/8K (64K/128K flash version) bytes internal SRAM
– Up to 64Kbytes optional external memory space
– Programming lock for software security
• JTAG (IEEE std. 1149.1 compliant) interface
– Boundary-scan capabilities according to the JTAG standard
– Extensive on-chip debug support
– Programming of flash, EEPROM, fuses, and lock bits through the JTAG interface
• USB 2.0 full-speed/low-speed device and on-the-go module
– Complies fully with:
– Universal serial bus specification REV 2.0
– On-the-go supplement to the USB 2.0 specification rev 1.0
– Supports data transfer rates up to 12Mbit/s and 1.5Mbit/s
• USB full-speed/low speed device module with interrupt on transfer completion
– Endpoint 0 for control transfers: up to 64-bytes
– Six programmable endpoints with in or out directions and with bulk, interrupt or
isochronous transfers
– Configurable endpoints size up to 256bytes in double bank mode
– Fully independent 832bytes USB DPRAM for endpoint memory allocation
– Suspend/resume interrupts
– Power-on reset and USB bus reset
– 48MHz PLL for full-speed bus operation
– USB bus disconnection on microcontroller request
• USB OTG reduced host:
– Supports host negotiation protocol (HNP) and session request protocol (SRP) for
OTG dual-role devices
– Provide status and control signals for software implementation of HNP and SRP
– Provides programmable times required for HNP and SRP
• Peripheral features
– Two 8-bit timer/counters with separate prescaler and compare mode
– Two16-bit timer/counter with separate prescaler, compare- and capture mode
8-bit Atmel
Microcontroller
with
64/128Kbytes
of ISP Flash
and USB
Controller
AT90USB646
AT90USB647
AT90USB1286
AT90USB1287
7593L–AVR–09/122
7593L–AVR–09/12
AT90USB64/128
– Real time counter with separate oscillator
– Four 8-bit PWM channels
– Six PWM channels with programmable resolution from 2 to 16 bits
– Output compare modulator
– 8-channels, 10-bit ADC
– Programmable serial USART
– Master/slave SPI serial interface
– Byte oriented 2-wire serial interface
– Programmable watchdog timer with separate on-chip oscillator
– On-chip analog comparator
– Interrupt and wake-up on pin change
• Special microcontroller features
– Power-on reset and programmable brown-out detection
– Internal calibrated oscillator
– External and internal interrupt sources
– Six sleep modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby
• I/O and packages
– 48 programmable I/O lines
– 64-lead TQFP and 64-lead QFN
• Operating voltages
– 2.7 - 5.5V
• Operating temperature
– Industrial (-40°C to +85°C)
• Maximum frequency
– 8MHz at 2.7V - industrial range
– 16MHz at 4.5V - industrial range3
7593L–AVR–09/12
AT90USB64/128
1. Pin configurations
Figure 1-1. Pinout Atmel AT90USB64/128-TQFP.
AT90USB90128/64
TQFP64
(INT.7/AIN.1/UVcon) PE7
UVcc
D-
D+
UGnd
UCap
VBus
(IUID) PE3
(SS/PCINT0) PB0
(INT.6/AIN.0) PE6
(PCINT1/SCLK) PB1
(PDI/PCINT2/MOSI) PB2
(PDO/PCINT3/MISO) PB3
(PCINT4/OC.2A) PB4
(PCINT5/OC.1A) PB5
(PCINT6/OC.1B) PB6
(PCINT7/OC.0A/OC.1C) PB7
(INT4/TOSC1) PE4
(INT.5/TOSC2) PE5
RESET
VCC
GND
XTAL2
XTAL1
(OC0B/SCL/INT0) PD0
(OC2B/SDA/INT1) PD1
(RXD1/INT2) PD2
(TXD1/INT3) PD3
(ICP1) PD4
(XCK1) PD5
PA3 (AD3)
PA4 (AD4)
PA5 (AD5)
PA6 (AD6)
PA7 (AD7)
PE2 (ALE/HWB)
PC7 (A15/IC.3/CLKO)
PC6 (A14/OC.3A)
PC5 (A13/OC.3B)
PC4 (A12/OC.3C)
PC3 (A11/T.3)
PC2 (A10)
PC1 (A9)
PC0 (A8)
PE1 (RD)
PE0 (WR)
AVCC
GND
AREF
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
PF7 (ADC7/TDI)
GND
VCC
PA0 (AD0)
PA1 (AD1)
PA2 (AD2)
(T1) PD6
(T0) PD7
INDEX CORNER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
324
7593L–AVR–09/12
AT90USB64/128
Figure 1-2. Pinout Atmel AT90USB64/128-QFN.
Note: The large center pad underneath the MLF packages is made of metal and internally connected to
GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center
pad is left unconnected, the package might loosen from the board.
2
3
1
4
5
6
7
8
9
10
11
12
13
14
16 33
15
47
46
48
45
44
43
42
41
40
39
38
37
36
35
34
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AT90USB128/64
(64-lead QFN top view)
INDEX CORNER
AVCC
G
N
D
AREF
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
PF7 (ADC7/TDI)
G
N
D
VCC
PA0 (AD0)
PA1 (AD1)
PA2 (AD2)
(INT.7/AIN.1/UVcon) PE7
UVcc
D-
D+
UGnd
UCap
VBus
(IUID) PE3
(SS/PCINT0) PB0
(INT.6/AIN.0) PE6
(PCINT1/SCLK) PB1
(PDI/PCINT2/MOSI) PB2
(PDO/PCINT3/MISO) PB3
(PCINT4/OC.2A) PB4
(PCINT5/OC.1A) PB5
(PCINT6/OC.1B) PB6
(PCI
NT7/OC.0A/OC.1C) PB7
(INT4/TOSC1) PE4
(INT.5/TOSC2) PE5
VCC
G
N
D
XTAL2
XTAL1
(OC0B/SCL/I
NT0) PD0
(OC2B/SDA/I
NT1) PD1
(RXD1/I
NT2) PD2
(TXD1/I
NT3) PD3
(ICP1) PD4
(XCK1) PD5
(T1) PD6
(T0) PD7
RESET
PA3 (AD3)
PA4 (AD4)
PA5 (AD5)
PA6 (AD6)
PA7 (AD7)
PE2 (ALE/HWB)
PC7 (A15/IC.3/CLKO)
PC6 (A14/OC.3A)
PC5 (A13/OC.3B)
PC4 (A12/OC.3C)
PC3 (A11/T.3)
PC2 (A10)
PC1 (A9)
PC0 (A8)
PE1 (RD)
PE0 (WR)5
7593L–AVR–09/12
AT90USB64/128
2. Overview
The Atmel® AVR® AT90USB64/128 is a low-power CMOS 8-bit microcontroller based on the
Atmel® AVR® enhanced RISC architecture. By executing powerful instructions in a single clock
cycle, the AT90USB64/128 achieves throughputs approaching 1MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.6
7593L–AVR–09/12
AT90USB64/128
2.1 Block diagram
Figure 2-1. Block diagram.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
PROGRAM
COUNTER
ST ACK
POINTER
PROGRAM
FLASH
MCU CONTROL
REGISTER SRAM
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
TIMER/
COUNTERS
INSTRUCTION
DECODER
DATA DIR.
REG. PORTB
DATA DIR.
REG. PORTE
DATA DIR.
REG. PORT A
DATA DIR.
REG. PORTD
DATA REGISTER
PORTB
DATA REGISTER
PORTE
DATA REGISTER
PORT A
DATA REGISTER
PORTD
INTERRUPT
UNIT
EEPROM
USART1 SPI
ST ATUS
REGISTER
Z
Y
X
ALU
POR TE DRIVERS POR TB DRIVERS
POR TF DRIVERS POR TA DRIVERS
POR TD DRIVERS
POR TC DRIVERS
PE7 - PE0 PB7 - PB0
PF7 - PF0 PA7 - P A0
RESET
VCC
AGND
GND
AREF
XT AL1
XT AL2
CONTROL
LINES
+
-
ANALOG
COMP ARATOR
PC7 - PC0
INTERNAL
OSCILLA TOR
WATCHDOG
TIMER
8-BIT DA TA BUS
AVCC
USB
TIMING AND
CONTROL
OSCILLA TOR
CALIB. OSC
DATA DIR.
REG. PORT C
DATA REGISTER
PORT C
ON-CHIP DEBUG
JTAG TAP
PROGRAMMING
LOGIC
BOUNDARYSCAN
DATA DIR.
REG. PORT F
DATA REGISTER
PORT F
ADC
POR - BOD
RESET
PD7 - PD0
TWO-WIRE SERIAL
INTERFACE
PLL7
7593L–AVR–09/12
AT90USB64/128
architecture is more code efficient while achieving throughputs up to ten times faster than conventional
CISC microcontrollers.
The Atmel AT90USB64/128 provides the following features: 64/128Kbytes of In-System Programmable
Flash with Read-While-Write capabilities, 2K/4Kbytes EEPROM, 4K/8K bytes
SRAM, 48 general purpose I/O lines, 32 general purpose working registers, Real Time Counter
(RTC), four flexible Timer/Counters with compare modes and PWM, one USART, a byte oriented
2-wire Serial Interface, a 8-channels, 10-bit ADC with optional differential input stage with
programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port,
IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system
and programming and six software selectable power saving modes. The Idle mode stops
the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue
functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling
all other chip functions until the next interrupt or Hardware Reset. In Power-save mode,
the asynchronous timer continues to run, allowing the user to maintain a timer base while the
rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules
except Asynchronous Timer and ADC, to minimize switching noise during ADC
conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the
device is sleeping. This allows very fast start-up combined with low power consumption. In
Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.
The device is manufactured using the Atmel high-density nonvolatile memory technology. The
On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI
serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program
running on the AVR core. The boot program can use any interface to download the
application program in the application Flash memory. Software in the Boot Flash section will
continue to run while the Application Flash section is updated, providing true Read-While-Write
operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a
monolithic chip, the AT90USB64/128 is a powerful microcontroller that provides a highly flexible
and cost effective solution to many embedded control applications.
The AT90USB64/128 AVR is supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators,
and evaluation kits.8
7593L–AVR–09/12
AT90USB64/128
2.2 Pin descriptions
2.2.1 VCC
Digital supply voltage.
2.2.2 GND
Ground.
2.2.3 AVCC
Analog supply voltage.
2.2.4 Port A (PA7..PA0)
Port A is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port A also serves the functions of various special features of the Atmel AT90USB64/128 as
listed on page 78.
2.2.5 Port B (PB7..PB0)
Port B is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B has better driving capabilities than the other ports.
Port B also serves the functions of various special features of the AT90USB64/128 as listed on
page 79.
2.2.6 Port C (PC7..PC0)
Port C is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of special features of the AT90USB64/128 as listed on page 82.
2.2.7 Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the AT90USB64/128 as listed on
page 83. 9
7593L–AVR–09/12
AT90USB64/128
2.2.8 Port E (PE7..PE0)
Port E is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port E also serves the functions of various special features of the AT90USB64/128 as listed on
page 86.
2.2.9 Port F (PF7..PF0)
Port F serves as analog inputs to the A/D Converter.
Port F also serves as an 8-bit bidirectional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical
drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will
be activated even if a reset occurs.
Port F also serves the functions of the JTAG interface.
2.2.10 DUSB
Full speed / Low Speed Negative Data Upstream Port. Should be connected to the USB Dconnector
pin with a serial 22Ω resistor.
2.2.11 D+
USB Full speed / Low Speed Positive Data Upstream Port. Should be connected to the USB D+
connector pin with a serial 22Ω resistor.
2.2.12 UGND
USB Pads Ground.
2.2.13 UVCC
USB Pads Internal Regulator Input supply voltage.
2.2.14 UCAP
USB Pads Internal Regulator Output supply voltage. Should be connected to an external capacitor
(1µF).
2.2.15 VBUS
USB VBUS monitor and OTG negociations.
2.2.16 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 9-1 on page
58. Shorter pulses are not guaranteed to generate a reset.
2.2.17 XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.10
7593L–AVR–09/12
AT90USB64/128
2.2.18 XTAL2
Output from the inverting oscillator amplifier.
2.2.19 AVCC
AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected
to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC
through a low-pass filter.
2.2.20 AREF
This is the analog reference pin for the A/D Converter.
3. Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
4. About code examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation
for more details.
These code examples assume that the part specific header file is included before compilation.
For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI"
instructions must be replaced with instructions that allow access to extended I/O. Typically
"LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".11
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5. AVR CPU core
5.1 Introduction
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
5.2 Architectural overview
Figure 5-1. Block diagram of the AVR architecture.
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruction
is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Re-programmable Flash memory.
Flash
program
memory
Instruction
register
Instruction
decoder
Program
counter
Control lines
32 x 8
general
purpose
registrers
ALU
Status
and control
I/O lines
EEPROM
Data bus 8-bit
Data
SRAM
Direct addressing
Indirect addressing
Interrupt
unit
SPI
unit
Watchdog
timer
Analog
comparator
I/O Module 2
I/O Module1
I/O Module n12
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The fast-access Register File contains 32 × 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical
ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointers
can also be used as an address pointer for look up tables in Flash program memory. These
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single register operations can also be executed in the ALU. After an arithmetic operation,
the Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most AVR instructions have a single 16-bit word format.
Every program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the
Application Program section. Both sections have dedicated Lock bits for write and read/write
protection. The SPM instruction that writes into the Application Flash memory section must
reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack
Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position.
The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers,
SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data
Space locations following those of the Register File, 0x20 - 0x5F. In addition, the Atmel
AT90USB64/128 has Extended I/O space from 0x60 - 0xFF in SRAM where only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
5.3 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general purpose
registers or between a register and an immediate are executed. The ALU operations are divided
into three main categories – arithmetic, logical, and bit-functions. Some implementations of the
architecture also provide a powerful multiplier supporting both signed/unsigned multiplication
and fractional format. See the “Instruction set summary” on page 423 for a detailed description.13
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5.4 Status register
The status register contains information about the result of the most recently executed arithmetic
instruction. This information can be used for altering program flow in order to perform conditional
operations. Note that the status register is updated after all ALU operations, as specified in the
Instruction Set Reference. This will in many cases remove the need for using the dedicated compare
instructions, resulting in faster and more compact code.
The status register is not automatically stored when entering an interrupt routine and restored
when returning from an interrupt. This must be handled by software.
The AVR status register – SREG – is defined as:
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt
enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination
for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful
in BCD arithmetic. See the “Instruction set summary” on page 423 for detailed information.
• Bit 4 – S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement
Overflow Flag V. See the “Instruction set summary” on page 423 for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction set summary” on page 423 for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction set summary” on page 423 for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction
set summary” on page 423 for detailed information.
Bit 7 6 5 4 3 2 1 0
I T H S V N Z C SREG
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 014
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• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction set
summary” on page 423 for detailed information.
5.5 General purpose register file
The register file is optimized for the AVR Enhanced RISC instruction set. In order to achieve the
required performance and flexibility, the following input/output schemes are supported by the
register file:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 5-2 shows the structure of the 32 general purpose working registers in the CPU.
Figure 5-2. AVR CPU general purpose working registers.
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 5-2, each register is also assigned a data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically implemented
as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file.
5.5.1 The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers
are 16-bit address pointers for indirect addressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in Figure 5-3.
7 0 Addr.
R0 0x00
R1 0x01
R2 0x02
…
R13 0x0D
General R14 0x0E
purpose R15 0x0F
working R16 0x10
registers R17 0x11
…
R26 0x1A X-register Low byte
R27 0x1B X-register High byte
R28 0x1C Y-register Low byte
R29 0x1D Y-register High byte
R30 0x1E Z-register Low byte
R31 0x1F Z-register High byte15
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Figure 5-3. The X-, Y-, and Z-registers.
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
5.6 Stack pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations
to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x0100. The initial value of the stack pointer is the last address of the internal
SRAM. The Stack Pointer is decremented by one when data is pushed onto the Stack with the
PUSH instruction, and it is decremented by three when the return address is pushed onto the
Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is incremented by three when data is
popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementations
of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
15 XH XL 0
X-register 7 07 0
R27 (0x1B) R26 (0x1A)
15 YH YL 0
Y-register 7 07 0
R29 (0x1D) R28 (0x1C)
15 ZH ZL 0
Z-register 70 7 0
R31 (0x1F) R30 (0x1E)
Bit 15 14 13 12 11 10 9 8
SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 1 0 0 0 0 0
1111111116
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5.6.1 RAMPZ - Extended Z-pointer register for ELPM/SPM
For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown
in Figure 5-4. Note that LPM is not affected by the RAMPZ setting.
Figure 5-4. The Z-pointer used by ELPM and SPM.
The actual number of bits is implementation dependent. Unused bits in an implementation will
always read as zero. For compatibility with future devices, be sure to write these bits to zero.
5.7 Instruction execution timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the
chip. No internal clock division is used.
Figure 5-5 shows the parallel instruction fetches and instruction executions enabled by the Harvard
architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 5-5. The parallel instruction fetches and instruction executions.
Figure 5-6 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destination
register.
Bit 7 6 5 4 3 2 1 0
RAMPZ7 RAMPZ6 RAMPZ5 RAMPZ4 RAMPZ3 RAMPZ2 RAMPZ1 RAMPZ0 RAMPZ
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit (individually) 7 0 7 0 7 0
RAMPZ ZH ZL
Bit (Z-pointer) 23 16 15 8 7 0
clk
1st instruction fetch
1st instruction execute
2nd instruction fetch
2nd instruction execute
3rd instruction fetch
3rd instruction execute
4th instruction fetch
T1 T2 T3 T4
CPU17
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Figure 5-6. Single cycle ALU operation.
5.8 Reset and interrupt handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section “Memory programming”
on page 359 for details.
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 68. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL
bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 68 for more information.
The Reset Vector can also be moved to the start of the Boot Flash section by programming the
BOOTRST Fuse, see “Memory programming” on page 359.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled.
The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector
in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)
to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt
Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Total execution time
Register operands fetch
ALU operation execute
Result write back
T1 T2 T3 T4
clkCPU18
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Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The following example shows how this can be used to avoid interrupts during the
timed EEPROM write sequence.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed
before any pending interrupts, as shown in this example.
Assembly code example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
C code example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
__disable_interrupt();
EECR |= (1< CSn2:0 > 1). The number of system clock cycles from
when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles,
where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution.
However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is
connected to.
13.3 External clock source
An external clock source applied to the Tn pin can be used as Timer/Counter clock (clkTn). The
Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized
(sampled) signal is then passed through the edge detector. Figure 13-1 shows a functional
equivalent block diagram of the Tn synchronization and edge detector logic. The registers are
clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the
high period of the internal system clock.
The edge detector generates one clkTn pulse for each positive (CSn2:0 = 7) or negative (CSn2:0
= 6) edge it detects.
Figure 13-1. Tn/T0 pin sampling.
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the Tn pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn has been stable for at least one
system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Tn_sync
(To clock
select logic)
Synchronization Edge detector
D Q D Q
LE
Tn D Q
clkI/O97
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Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the system
clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses
sampling, the maximum frequency of an external clock it can detect is half the sampling frequency
(Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5.
An external clock source can not be prescaled.
Figure 13-2. Prescaler for synchronous Timer/Counters
13.4 GTCCR – General Timer/Counter Control Register
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the corresponding
prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are
halted and can be configured to the same value without the risk of one of them advancing during
configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared
by hardware, and the Timer/Counters start counting simultaneously.
• Bit 0 – PSRSYNC: Prescaler Reset for Synchronous Timer/Counters
When this bit is one, Timer/Counter0 and Timer/Counter1 and Timer/Counter3 prescaler will be
Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note
that Timer/Counter0, Timer/Counter1 and Timer/Counter3 share the same prescaler and a reset
of this prescaler will affect all timers.
PSR10
Clear
Tn
Tn
clkI/O
Synchronization
Synchronization
TIMER/COUNTERn CLOCK SOURCE
clkTn
TIMER/COUNTERn CLOCK SOURCE
clkTn
CSn0
CSn1
CSn2
CSn0
CSn1
CSn2
Bit 7 6 5 4 3 2 1 0
TSM – – – – – PSRASY PSRSYNC GTCCR
Read/write R/W R R R R R R/W R/W
Initial value 0 0 0 0 0 0 0 098
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14. 8-bit Timer/Counter0 with PWM
Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output
Compare Units, and with PWM support. It allows accurate program execution timing (event management)
and wave generation. The main features are:
• Two independent output compare units
• Double buffered output compare registers
• Clear timer on compare match (auto reload)
• Glitch free, phase correct pulse width modulator (PWM)
• Variable PWM period
• Frequency generator
• Three independent interrupt sources (TOV0, OCF0A, and OCF0B)
14.1 Overview
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 14-1. For the actual
placement of I/O pins, refer to “Pinout Atmel AT90USB64/128-TQFP.” on page 3. CPU accessible
I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O
Register and bit locations are listed in the “8-bit Timer/Counter register description” on page 108.
Figure 14-1. 8-bit Timer/Counter block diagram.
14.1.1 Registers
The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit
registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the
Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Interrupt
Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0).
Clock select
Timer/Counter
DATA BUS
OCRnA
OCRnB
=
=
TCNTn
Waveform
generation
Waveform
generation
OCnA
OCnB
=
Fixed
TOP
value
Control logic
= 0
TOP BOTTOM
Count
Clear
Direction
TOVn
(int.req.)
OCnA
(int.req.)
OCnB
(Int.Req.)
TCCRnA TCCRnB
Tn Edge
detector
(From prescaler)
clkTn99
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The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator
to generate a PWM or variable frequency output on the Output Compare pins (OC0A and
OC0B). See “Output compare unit” on page 100. for details. The Compare Match event will also
set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare
interrupt request.
14.1.2 Definitions
Many register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Compare
Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or
bit defines in a program, the precise form must be used, that is, TCNT0 for accessing
Timer/Counter0 counter value and so on.
The definitions in the table below are also used extensively throughout the document.
14.2 Timer/Counter clock sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits
located in the Timer/Counter Control Register (TCCR0B). For details on clock sources and prescaler,
see “Timer/Counter0, Timer/Counter1, and Timer/Counter3 prescalers” on page 96.
14.3 Counter unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure
14-2 shows a block diagram of the counter and its surroundings.
Figure 14-2. Counter unit block diagram.
BOTTOM The counter reaches the BOTTOM when it becomes 0x00.
MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR0A Register. The assignment is dependent
on the mode of operation.
DATA BUS
TCNTn Control logic
count
TOVn
(int.req.)
Clock select
top
Tn Edge
detector
(From prescaler)
clkTn
bottom
direction
clear100
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Signal description (internal signals):
count Increment or decrement TCNT0 by 1.
direction Select between increment and decrement.
clear Clear TCNT0 (set all bits to zero).
clkTn Timer/Counter clock, referred to as clkT0 in the following.
top Signalize that TCNT0 has reached maximum value.
bottom Signalize that TCNT0 has reached minimum value (zero).
Depending of the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clkT0). clkT0 can be generated from an external or internal clock source,
selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the
timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of
whether clkT0 is present or not. A CPU write overrides (has priority over) all counter clear or
count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in
the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter
Control Register B (TCCR0B). There are close connections between how the counter behaves
(counts) and how waveforms are generated on the Output Compare outputs OC0A and OC0B.
For more details about advanced counting sequences and waveform generation, see “Modes of
operation” on page 103.
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by
the WGM02:0 bits. TOV0 can be used for generating a CPU interrupt.
14.4 Output compare unit
The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers
(OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a
match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock
cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output
Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is executed.
Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit
location. The Waveform Generator uses the match signal to generate an output according to
operating mode set by the WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The
maximum and bottom signals are used by the Waveform Generator for handling the special
cases of the extreme values in some modes of operation (“Modes of operation” on page 103).
Figure 14-3 on page 101 shows a block diagram of the Output Compare unit. 101
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Figure 14-3. Output Compare Unit, block diagram.
The OCR0x Registers are double buffered when using any of the Pulse Width Modulation
(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double
buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare
Registers to either top or bottom of the counting sequence. The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR0x Register access may seem complex, but this is not case. When the double buffering
is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is disabled
the CPU will access the OCR0x directly.
14.4.1 Force output compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOC0x) bit. Forcing Compare Match will not set the
OCF0x Flag or reload/clear the timer, but the OC0x pin will be updated as if a real Compare
Match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set, cleared or
toggled).
14.4.2 Compare match blocking by TCNT0 write
All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initialized
to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is
enabled.
14.4.3 Using the output compare unit
Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer
clock cycle, there are risks involved when changing TCNT0 when using the Output Compare
Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0
equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform
generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is
down-counting.
OCFnx (int.req.)
= (8-bit comparator)
OCRnx
OCnx
DATA BUS
TCNTn
WGMn1:0
Waveform generator
top
FOCn
COMnX1:0
bottom102
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The setup of the OC0x should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare
(FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when
changing between Waveform Generation modes.
Be aware that the COM0x1:0 bits are not double buffered together with the compare value.
Changing the COM0x1:0 bits will take effect immediately.
14.5 Compare Match Output Unit
The Compare Output mode (COM0x1:0) bits have two functions. The Waveform Generator uses
the COM0x1:0 bits for defining the Output Compare (OC0x) state at the next Compare Match.
Also, the COM0x1:0 bits control the OC0x pin output source. Figure 14-4 shows a simplified
schematic of the logic affected by the COM0x1:0 bit setting. The I/O Registers, I/O bits, and I/O
pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers
(DDR and PORT) that are affected by the COM0x1:0 bits are shown. When referring to the
OC0x state, the reference is for the internal OC0x Register, not the OC0x pin. If a system reset
occur, the OC0x Register is reset to “0”.
Figure 14-4. Compare Match Output Unit, schematic.
The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform
Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or output)
is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visible
on the pin. The port override function is independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC0x state before the output
is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of
operation. See “8-bit Timer/Counter register description” on page 108.
14.5.1 Compare output mode and waveform generation
The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes.
For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the
OC0x Register is to be performed on the next Compare Match. For compare output actions in
PORT
DDR
D Q
D Q
OCnx
OCnx Pin
D Q Waveform
generator
COMnx1
COMnx0
0
1
DATA BUS
FOCn
clkI/O103
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the non-PWM modes refer to Table 14-1 on page 109. For fast PWM mode, refer to Table 14-2
on page 109, and for phase correct PWM refer to Table 14-3 on page 109.
A change of the COM0x1:0 bits state will have effect at the first Compare Match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOC0x strobe bits.
14.6 Modes of operation
The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins,
is defined by the combination of the Waveform Generation mode (WGM02:0) and Compare Output
mode (COM0x1:0) bits. The Compare Output mode bits do not affect the counting sequence,
while the Waveform Generation mode bits do. The COM0x1:0 bits control whether the PWM output
generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes
the COM0x1:0 bits control whether the output should be set, cleared, or toggled at a Compare
Match (See “Compare Match Output Unit” on page 102.).
For detailed timing information see “Timer/Counter timing diagrams” on page 107.
14.6.1 Normal mode
The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom
(0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same
timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth
bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV0 Flag, the timer resolution can be increased by software.
There are no special cases to consider in the Normal mode, a new counter value can be written
anytime.
The Output Compare Unit can be used to generate interrupts at some given time. Using the Output
Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
14.6.2 Clear Timer on Compare Match (CTC) mode
In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter
value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence
also its resolution. This mode allows greater control of the Compare Match output frequency. It
also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 14-5 on page 104. The counter value
(TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter
(TCNT0) is cleared.104
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Figure 14-5. CTC mode, timing diagram.
An interrupt can be generated each time the counter value reaches the TOP value by using the
OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating
the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running
with none or a low prescaler value must be done with care since the CTC mode does not
have the double buffering feature. If the new value written to OCR0A is lower than the current
value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can
occur.
For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical
level on each Compare Match by setting the Compare Output mode bits to toggle mode
(COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for
the pin is set to output. The waveform generated will have a maximum frequency of fOC0 =
fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following
equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the
counter counts from MAX to 0x00.
14.6.3 Fast PWM mode
The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high frequency
PWM waveform generation option. The fast PWM differs from the other PWM option by
its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM.
TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when WGM2:0 = 7. In noninverting
Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match
between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the output
is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the
operating frequency of the fast PWM mode can be twice as high as the phase correct PWM
mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited
for power regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the TOP value.
The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
TCNTn
OCn
(Toggle)
OCnx Interrupt Flag Set
Period 1 2 3 4
(COMnx1:0 = 1)
f
OCnx
f
clk_I/O
2 ⋅ ⋅ N ( ) 1 + OCRnx = -------------------------------------------------105
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PWM mode is shown in Figure 14-6. The TCNT0 value is in the timing diagram shown as a histogram
for illustrating the single-slope operation. The diagram includes non-inverted and
inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare
Matches between OCR0x and TCNT0.
Figure 14-6. Fast PWM mode, timing diagram.
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the interrupt
is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.
Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output
can be generated by setting the COM0x1:0 to three: Setting the COM0A1:0 bits to one allows
the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available
for the OC0B pin (see Table 14-2 on page 109). The actual OC0x value will only be visible on
the port pin if the data direction for the port pin is set as output. The PWM waveform is generated
by setting (or clearing) the OC0x Register at the Compare Match between OCR0x and
TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the counter is
cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represents special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will
be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result
in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0
bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting
OC0x to toggle its logical level on each Compare Match (COM0x1:0 = 1). The waveform
generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero. This
TCNTn
OCRnx update and
TOVn Interrupt Flag Set
Period 1 2 3
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCRnx Interrupt Flag Set
4 5 6 7
f
OCnxPWM
f
clk_I/O
N ⋅ 256 = ------------------106
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feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Output
Compare unit is enabled in the fast PWM mode.
14.6.4 Phase correct PWM mode
The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct
PWM waveform generation option. The phase correct PWM mode is based on a dual-slope
operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM.
TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5. In noninverting
Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match
between TCNT0 and OCR0x while up-counting, and set on the Compare Match while downcounting.
In inverting Output Compare mode, the operation is inverted. The dual-slope operation
has lower maximum operation frequency than single slope operation. However, due to the symmetric
feature of the dual-slope PWM modes, these modes are preferred for motor control
applications.
In phase correct PWM mode the counter is incremented until the counter value matches TOP.
When the counter reaches TOP, it changes the count direction. The TCNT0 value will be equal
to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown
on Figure 14-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating
the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The
small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x
and TCNT0.
Figure 14-7. Phase correct PWM mode, timing diagram.
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The
Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM
value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted
PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to
TOVn Interrupt Flag Set
OCnx Interrupt Flag Set
1 2 3
TCNTn
Period
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCRnx update107
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one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is
not available for the OC0B pin (see Table 14-3 on page 109). The actual OC0x value will only be
visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is
generated by clearing (or setting) the OC0x Register at the Compare Match between OCR0x
and TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at Compare
Match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for
the output when using phase correct PWM can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in Figure 14-7 on page 106 OCnx has a transition from high to low
even though there is no Compare Match. The point of this transition is to guarantee symmetry
around BOTTOM. There are two cases that give a transition without Compare Match.
• OCR0A changes its value from MAX, like in Figure 14-7 on page 106. When the OCR0A
value is MAX the OCn pin value is the same as the result of a down-counting Compare
Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the
result of an up-counting Compare Match
• The timer starts counting from a value higher than the one in OCR0A, and for that reason
misses the Compare Match and hence the OCn change that would have happened on the
way up
14.7 Timer/Counter timing diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set. Figure 14-8 contains timing data for basic Timer/Counter operation. The figure
shows the count sequence close to the MAX value in all modes other than phase correct PWM
mode.
Figure 14-8. Timer/Counter timing diagram, no prescaling.
Figure 14-9 on page 108 shows the same timing data, but with the prescaler enabled.
f
OCnxPCPWM
f
clk_I/O
N ⋅ 510 = ------------------
clkTn
(clkI/O/1)
TOVn
clkI/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1108
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Figure 14-9. Timer/Counter timing diagram, with prescaler (fclk_I/O/8).
Figure 14-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC
mode and PWM mode, where OCR0A is TOP.
Figure 14-10. Timer/Counter timing diagram, setting of OCF0x, with prescaler (fclk_I/O/8).
Figure 14-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast
PWM mode where OCR0A is TOP.
Figure 14-11. Timer/Counter timing diagram, clear timer on Compare Match mode, with prescaler
(fclk_I/O/8)
14.8 8-bit Timer/Counter register description
14.8.1 TCCR0A – Timer/Counter Control Register A
TOVn
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
clkI/O
clkTn
(clkI/O/8)
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clkI/O
clkTn
(clkI/O/8)
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1 TOP BOTTOM BOTTOM + 1
clkI/O
clkTn
(clkI/O/8)
Bit 7 6 5 4 3 2 1 0
COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 TCCR0A
Read/write R/W R/W R/W R/W R R R/W R/W
Initial value 0 0 0 0 0 0 0 0109
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• Bits 7:6 – COM01A:0: Compare Match Output A Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0
bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin
must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM02:0 bit setting. Table 14-1 shows the COM0A1:0 bit functionality when the WGM02:0 bits
are set to a normal or CTC mode (non-PWM).
Table 14-2 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM
mode.
Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Compare
Match is ignored, but the set or clear is done at TOP. See “Fast PWM mode” on page 104
for more details.
Table 14-3 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase correct
PWM mode.
Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Compare
Match is ignored, but the set or clear is done at TOP. See “Phase correct PWM mode” on
page 106 for more details.
Table 14-1. Compare Output mode, non-PWM mode.
COM0A1 COM0A0 Description
0 0 Normal port operation, OC0A disconnected.
0 1 Toggle OC0A on Compare Match
1 0 Clear OC0A on Compare Match
1 1 Set OC0A on Compare Match
Table 14-2. Compare Output mode, Fast PWM mode (1).
COM0A1 COM0A0 Description
0 0 Normal port operation, OC0A disconnected.
0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.
1 0 Clear OC0A on Compare Match, set OC0A at TOP
1 1 Set OC0A on Compare Match, clear OC0A at TOP
Table 14-3. Compare Output mode, phase correct PWM mode (1).
COM0A1 COM0A0 Description
0 0 Normal port operation, OC0A disconnected.
0 1 WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.
1 0 Clear OC0A on Compare Match when up-counting. Set OC0A on Compare
Match when down-counting.
1 1 Set OC0A on Compare Match when up-counting. Clear OC0A on Compare
Match when down-counting.110
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• Bits 5:4 – COM0B1:0: Compare Match Output B mode
These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0
bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin
must be set in order to enable the output driver.
When OC0B is connected to the pin, the function of the COM0B1:0 bits depends on the
WGM02:0 bit setting. Table 14-1 shows the COM0A1:0 bit functionality when the WGM02:0 bits
are set to a normal or CTC mode (non-PWM).
Table 14-2 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast PWM
mode.
Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare
Match is ignored, but the set or clear is done at TOP. See “Fast PWM mode” on page 104
for more details.
Table 14-3 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase correct
PWM mode.
Note: 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Compare
Match is ignored, but the set or clear is done at TOP. See “Phase correct PWM mode” on
page 106 for more details.
• Bits 3, 2 – Res: Reserved bits
These bits are reserved bits in the Atmel AT90USB64/128 and will always read as zero.
Table 14-4. Compare Output mode, non-PWM mode.
COM01 COM00 Description
0 0 Normal port operation, OC0B disconnected.
0 1 Toggle OC0B on Compare Match
1 0 Clear OC0B on Compare Match
1 1 Set OC0B on Compare Match
Table 14-5. Compare Output mode, fast PWM mode (1).
COM01 COM00 Description
0 0 Normal port operation, OC0B disconnected.
0 1 Reserved.
1 0 Clear OC0B on Compare Match, set OC0B at TOP.
1 1 Set OC0B on Compare Match, clear OC0B at TOP.
Table 14-6. Compare Output mode, phase correct PWM mode (1).
COM0A1 COM0A0 Description
0 0 Normal port operation, OC0B disconnected.
0 1 Reserved.
1 0 Clear OC0B on Compare Match when up-counting. Set OC0B on Compare
Match when down-counting.
1 1 Set OC0B on Compare Match when up-counting. Clear OC0B on Compare
Match when down-counting.111
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• Bits 1:0 – WGM01:0: Waveform Generation Mode
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform
generation to be used, see Table 14-7. Modes of operation supported by the Timer/Counter
unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of
Pulse Width Modulation (PWM) modes (see “Modes of operation” on page 103).
Notes: 1. MAX = 0xFF
2. BOTTOM = 0x00
14.8.2 TCCR0B – Timer/Counter Control Register B
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is
changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a
strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the
forced compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0A as TOP.
The FOC0A bit is always read as zero.
• Bit 6 – FOC0B: Force Output Compare B
The FOC0B bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is
changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is implemented as a
Table 14-7. Waveform Generation Mode bit description.
Mode WGM2 WGM1 WGM0
Timer/Counter mode of
operation TOP
Update of
OCRx at
TOV flag
set on (1)(2)
0 0 0 0 Normal 0xFF Immediate MAX
1 0 0 1 PWM, phase correct 0xFF TOP BOTTOM
2 0 1 0 CTC OCRA Immediate MAX
3 0 1 1 Fast PWM 0xFF TOP MAX
4 1 0 0 Reserved – – –
5 1 0 1 PWM, phase correct OCRA TOP BOTTOM
6 1 1 0 Reserved – – –
7 1 1 1 Fast PWM OCRA TOP TOP
Bit 7 6 5 4 3 2 1 0
FOC0A FOC0B – – WGM02 CS02 CS01 CS00 TCCR0B
Read/write W W R R R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0112
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strobe. Therefore it is the value present in the COM0B1:0 bits that determines the effect of the
forced compare.
A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0B as TOP.
The FOC0B bit is always read as zero.
• Bits 5:4 – Res: Reserved bits
These bits are reserved bits and will always read as zero.
• Bit 3 – WGM02: Waveform Generation Mode
See the description in the “TCCR0A – Timer/Counter Control Register A” on page 108.
• Bits 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
14.8.3 TCNT0 – Timer/Counter Register
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare
Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,
introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers.
14.8.4 OCR0A – Output Compare Register A
Table 14-8. Clock Select bit description.
CS02 CS01 CS00 Description
0 0 0 No clock source (Timer/Counter stopped)
0 0 1 clkI/O/(No prescaling)
0 1 0 clkI/O/8 (From prescaler)
0 1 1 clkI/O/64 (From prescaler)
1 0 0 clkI/O/256 (From prescaler)
1 0 1 clkI/O/1024 (From prescaler)
1 1 0 External clock source on T0 pin. Clock on falling edge.
1 1 1 External clock source on T0 pin. Clock on rising edge.
Bit 7 6 5 4 3 2 1 0
TCNT0[7:0] TCNT0
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OCR0A[7:0] OCR0A
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0113
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The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0A pin.
14.8.5 OCR0B – Output Compare Register B
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0B pin.
14.8.6 TIMSK0 – Timer/Counter Interrupt Mask Register
• Bits 7..3, 0 – Res: Reserved bits
These bits are reserved bits and will always read as zero.
• Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter occurs, that is, when the OCF0B bit is set in the
Timer/Counter Interrupt Flag Register – TIFR0.
• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a Compare Match in Timer/Counter0 occurs, that is, when the OCF0A bit is set in the
Timer/Counter 0 Interrupt Flag Register – TIFR0.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, that is, when the TOV0 bit is set in the Timer/Counter 0 Interrupt
Flag Register – TIFR0.
14.8.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register
• Bits 7..3, 0 – Res: Reserved bits
These bits are reserved bits in the Atmel AT90USB64/128 and will always read as zero.
Bit 7 6 5 4 3 2 1 0
OCR0B[7:0] OCR0B
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
– – – – – OCIE0B OCIE0A TOIE0 TIMSK0
Read/write R R R R R R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
– – – – – OCF0B OCF0A TOV0 TIFR0
Read/write R R R R R R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0114
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• Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag
The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in
OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable),
and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.
• Bit 1 – OCF0A: Timer/Counter 0 Output Compare A Match Flag
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data
in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable),
and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by
writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt
Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.
The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 14-7, “Waveform
Generation Mode bit description.” on page 111.115
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15. 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)
The 16-bit Timer/Counter unit allows accurate program execution timing (event management),
wave generation, and signal timing measurement. The main features are:
• True 16-bit design (that is, allows 16-bit PWM)
• Three independent output compare units
• Double buffered output compare registers
• One input capture unit
• Input capture noise canceler
• Clear timer on compare match (auto reload)
• Glitch-free, phase correct pulse width modulator (PWM)
• Variable PWM period
• Frequency generator
• External event counter
• Ten independent interrupt sources (TOV1, OCF1A, OCF1B, OCF1C, ICF1, TOV3, OCF3A, OCF3B,
OCF3C, and ICF3)
15.1 Overview
Most register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit
channel. However, when using the register or bit defines in a program, the precise form must be
used, that is, TCNT1 for accessing Timer/Counter1 counter value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 15-1 on page 116. For
the actual placement of I/O pins, see “Pinout Atmel AT90USB64/128-TQFP.” on page 3. CPU
accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific
I/O Register and bit locations are listed in the “16-bit Timer/Counter (Timer/Counter1 and
Timer/Counter3)” on page 115.
The Power Reduction Timer/Counter1 bit, PRTIM1, in “PRR0 – Power Reduction Register 0” on
page 54 must be written to zero to enable Timer/Counter1 module.
The Power Reduction Timer/Counter3 bit, PRTIM3, in “PRR1 – Power Reduction Register 1” on
page 55 must be written to zero to enable Timer/Counter3 module.116
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Figure 15-1. 16-bit Timer/Counter block diagram (1).
Note: 1. Refer to Figure 1-1 on page 3, Table 11-6 on page 79, and Table 11-9 on page 82 for
Timer/Counter1 and 3 and 3 pin placement and description.
15.1.1 Registers
The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Register
(ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16-
bit registers. These procedures are described in the section “Accessing 16-bit registers” on page
117. The Timer/Counter Control Registers (TCCRnA/B/C) are 8-bit registers and have no CPU
access restrictions. Interrupt requests (shorten as Int.Req.) signals are all visible in the Timer
Interrupt Flag Register (TIFRn). All interrupts are individually masked with the Timer Interrupt
Mask Register (TIMSKn). TIFRn and TIMSKn are not shown in the figure since these registers
are shared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the clock select logic is referred to as the timer clock (clkTn).
The double buffered Output Compare Registers (OCRnA/B/C) are compared with the
Timer/Counter value at all time. The result of the compare can be used by the Waveform Generator
to generate a PWM or variable frequency output on the Output Compare pin (OCnA/B/C).
ICFn (Int.Req.)
TOVn
(int.req.)
Clock select
Timer/Counter
DATABUS
ICRn
=
=
=
TCNTn
Waveform
generation
Waveform
generation
Waveform
generation
OCnA
OCnB
OCnC
Noise
canceler
ICPn
=
Fixed
TOP
values
Edge
detector
Control logic
= 0
TOP BOTTOM
Count
Clear
Direction
OCFnA
(Int.Req.)
OCFnB
(Int.Req.)
OCFnC
(Int.Req.)
TCCRnA TCCRnB TCCRnC
( From Analog
Comparator Ouput )
Tn Edge
detector
(From prescaler)
TCLK
OCRnC
OCRnB
OCRnA117
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See “Output Compare units” on page 124.. The compare match event will also set the Compare
Match Flag (OCFnA/B/C) which can be used to generate an Output Compare interrupt request.
The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered)
event on either the Input Capture pin (ICPn) or on the Analog Comparator pins (see
“Analog Comparator” on page 304) The Input Capture unit includes a digital filtering unit (Noise
Canceler) for reducing the chance of capturing noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined
by either the OCRnA Register, the ICRn Register, or by a set of fixed values. When using
OCRnA as TOP value in a PWM mode, the OCRnA Register can not be used for generating a
PWM output. However, the TOP value will in this case be double buffered allowing the TOP
value to be changed in run time. If a fixed TOP value is required, the ICRn Register can be used
as an alternative, freeing the OCRnA to be used as PWM output.
15.1.2 Definitions
The following definitions are used extensively throughout the document:
15.2 Accessing 16-bit registers
The TCNTn, OCRnA/B/C, and ICRn are 16-bit registers that can be accessed by the AVR CPU
via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations.
Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-
bit access. The same Temporary Register is shared between all 16-bit registers within each 16-
bit timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of
a 16-bit register is written by the CPU, the high byte stored in the Temporary Register, and the
low byte written are both copied into the 16-bit register in the same clock cycle. When the low
byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the
Temporary Register in the same clock cycle as the low byte is read.
Not all 16-bit accesses uses the Temporary Register for the high byte. Reading the OCRnA/B/C
16-bit registers does not involve using the Temporary Register.
To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low
byte must be read before the high byte.
The following code examples show how to access the 16-bit timer registers assuming that no
interrupts updates the temporary register. The same principle can be used directly for accessing
the OCRnA/B/C and ICRn Registers. Note that when using “C”, the compiler handles the 16-bit
access.
BOTTOM The counter reaches the BOTTOM when it becomes 0x0000.
MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).
TOP
The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be one of the fixed values:
0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCRnA or ICRn
Register. The assignment is dependent of the mode of operation.118
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Note: 1. See “About code examples” on page 10.
The assembly code example returns the TCNTn value in the r17:r16 register pair.
It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt
occurs between the two instructions accessing the 16-bit register, and the interrupt code
updates the temporary register by accessing the same or any other of the 16-bit Timer Registers,
then the result of the access outside the interrupt will be corrupted. Therefore, when both
the main code and the interrupt code update the temporary register, the main code must disable
the interrupts during the 16-bit access.
Assembly code examples (1)
...
; Set TCNTn to 0x01FF
ldi r17,0x01
ldi r16,0xFF
out TCNTnH,r17
out TCNTnL,r16
; Read TCNTn into r17:r16
in r16,TCNTnL
in r17,TCNTnH
...
C code examples (1)
unsigned int i;
...
/* Set TCNTn to 0x01FF */
TCNTn = 0x1FF;
/* Read TCNTn into i */
i = TCNTn;
...119
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The following code examples show how to do an atomic read of the TCNTn Register contents.
Reading any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.
Note: 1. See “About code examples” on page 10.
The assembly code example returns the TCNTn value in the r17:r16 register pair.
Assembly code example (1)
TIM16_ReadTCNTn:
; Save global interrupt flag
in r18,SREG
; Disable interrupts
cli
; Read TCNTn into r17:r16
in r16,TCNTnL
in r17,TCNTnH
; Restore global interrupt flag
out SREG,r18
ret
C code example (1)
unsigned int TIM16_ReadTCNTn( void )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
__disable_interrupt();
/* Read TCNTn into i */
i = TCNTn;
/* Restore global interrupt flag */
SREG = sreg;
return i;
}120
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The following code examples show how to do an atomic write of the TCNTn Register contents.
Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle.
Note: 1. See “About code examples” on page 10.
The assembly code example requires that the r17:r16 register pair contains the value to be written
to TCNTn.
15.2.1 Reusing the Temporary High Byte register
If writing to more than one 16-bit register where the high byte is the same for all registers written,
then the high byte only needs to be written once. However, note that the same rule of atomic
operation described previously also applies in this case.
15.3 Timer/Counter clock sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CSn2:0) bits
located in the Timer/Counter control Register B (TCCRnB). For details on clock sources and
prescaler, see Section “Timer/Counter0, Timer/Counter1, and Timer/Counter3 prescalers” on
page 96.
Assembly code example (1)
TIM16_WriteTCNTn:
; Save global interrupt flag
in r18,SREG
; Disable interrupts
cli
; Set TCNTn to r17:r16
out TCNTnH,r17
out TCNTnL,r16
; Restore global interrupt flag
out SREG,r18
ret
C code example (1)
void TIM16_WriteTCNTn( unsigned int i )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
__disable_interrupt();
/* Set TCNTn to i */
TCNTn = i;
/* Restore global interrupt flag */
SREG = sreg;
}121
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15.4 Counter unit
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.
Figure 15-2 shows a block diagram of the counter and its surroundings.
Figure 15-2. Counter unit block diagram.
Signal description (internal signals):
Count Increment or decrement TCNTn by 1.
Direction Select between increment and decrement.
Clear Clear TCNTn (set all bits to zero).
clkTn Timer/Counter clock.
TOP Signalize that TCNTn has reached maximum value.
BOTTOM Signalize that TCNTn has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) containing
the upper eight bits of the counter, and Counter Low (TCNTnL) containing the lower eight
bits. The TCNTnH Register can only be indirectly accessed by the CPU. When the CPU does an
access to the TCNTnH I/O location, the CPU accesses the high byte temporary register (TEMP).
The temporary register is updated with the TCNTnH value when the TCNTnL is read, and
TCNTnH is updated with the temporary register value when TCNTnL is written. This allows the
CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.
It is important to notice that there are special cases of writing to the TCNTn Register when the
counter is counting that will give unpredictable results. The special cases are described in the
sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clkTn). The clkTn can be generated from an external or internal clock source,
selected by the Clock Select bits (CSn2:0). When no clock source is selected (CSn2:0 = 0) the
timer is stopped. However, the TCNTn value can be accessed by the CPU, independent of
whether clkTn is present or not. A CPU write overrides (has priority over) all counter clear or
count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits
(WGMn3:0) located in the Timer/Counter Control Registers A and B (TCCRnA and TCCRnB).
There are close connections between how the counter behaves (counts) and how waveforms
are generated on the Output Compare outputs OCnx. For more details about advanced counting
sequences and waveform generation, see Section “Modes of operation” on page 127.
TEMP (8-bit)
DATA BUS (8-bit)
TCNTn (16-bit counter)
TCNTnH (8-bit) TCNTnL (8-bit) Control logic
Count
Clear
Direction
TOVn
(Int.Req.)
Clock select
TOP BOTTOM
Tn Edge
detector
(From prescaler)
clkTn122
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The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by
the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt.
15.5 Input Capture unit
The Timer/Counter incorporates an Input Capture unit that can capture external events and give
them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple
events, can be applied via the ICPn pin or alternatively, for the Timer/Counter1 only, via the
Analog Comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle,
and other features of the signal applied. Alternatively the time-stamps can be used for creating a
log of the events.
The Input Capture unit is illustrated by the block diagram shown in Figure 15-3. The elements of
the block diagram that are not directly a part of the input capture unit are gray shaded. The small
“n” in register and bit names indicates the Timer/Counter number.
Figure 15-3. Input Capture Unit block diagram.
Note: The Analog Comparator Output (ACO) can only trigger the Timer/Counter1 ICP – not
Timer/Counter3, 4, or 5.
When a change of the logic level (an event) occurs on the Input Capture Pin (ICPn), alternatively
on the analog Comparator output (ACO), and this change confirms to the setting of the edge
detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter
(TCNTn) is written to the Input Capture Register (ICRn). The Input Capture Flag (ICFn) is set at
the same system clock as the TCNTn value is copied into ICRn Register. If enabled (TICIEn =
1), the input capture flag generates an input capture interrupt. The ICFn flag is automatically
cleared when the interrupt is executed. Alternatively the ICFn flag can be cleared by software by
writing a logical one to its I/O bit location.
ICFn (int.req.)
Analog
comparator
WRITE ICRn (16-bit register)
ICRnH (8-bit)
Noise
canceler
ICPn
Edge
detector
TEMP (8-bit)
DATA BUS (8-bit)
ICRnL (8-bit)
TCNTn (16-bit counter)
TCNTnH (8-bit) TCNTnL (8-bit)
ACO* ACIC* ICNC ICES123
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Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low
byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high byte is copied
into the high byte Temporary Register (TEMP). When the CPU reads the ICRnH I/O location it
will access the TEMP Register.
The ICRn Register can only be written when using a Waveform Generation mode that utilizes
the ICRn Register for defining the counter’s TOP value. In these cases the Waveform Generation
mode (WGMn3:0) bits must be set before the TOP value can be written to the ICRn
Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location
before the low byte is written to ICRnL.
For more information on how to access the 16-bit registers refer to Section “Accessing 16-bit
registers” on page 117.
15.5.1 Input Capture Trigger Source
The main trigger source for the input capture unit is the Input Capture Pin (ICPn).
Timer/Counter1 can alternatively use the analog comparator output as trigger source for the
input capture unit. The Analog Comparator is selected as trigger source by setting the analog
Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register
(ACSR). Be aware that changing trigger source can trigger a capture. The input capture flag
must therefore be cleared after the change.
Both the Input Capture Pin (ICPn) and the Analog Comparator output (ACO) inputs are sampled
using the same technique as for the Tn pin (Figure 13-1 on page 96). The edge detector is also
identical. However, when the noise canceler is enabled, additional logic is inserted before the
edge detector, which increases the delay by four system clock cycles. Note that the input of the
noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform
Generation mode that uses ICRn to define TOP.
An input capture can be triggered by software by controlling the port of the ICPn pin.
15.5.2 Noise Canceler
The Noise Canceler improves noise immunity by using a simple digital filtering scheme. The
noise canceler input is monitored over four samples, and all four must be equal for changing the
output that in turn is used by the edge detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNCn) bit in
Timer/Counter Control Register B (TCCRnB). When enabled the noise canceler introduces additional
four system clock cycles of delay from a change applied to the input, to the update of the
ICRn Register. The noise canceler uses the system clock and is therefore not affected by the
prescaler.
15.5.3 Using the Input Capture unit
The main challenge when using the Input Capture unit is to assign enough processor capacity
for handling the incoming events. The time between two events is critical. If the processor has
not read the captured value in the ICRn Register before the next event occurs, the ICRn will be
overwritten with a new value. In this case the result of the capture will be incorrect.
When using the Input Capture interrupt, the ICRn Register should be read as early in the interrupt
handler routine as possible. Even though the Input Capture interrupt has relatively high
priority, the maximum interrupt response time is dependent on the maximum number of clock
cycles it takes to handle any of the other interrupt requests.124
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Using the Input Capture unit in any mode of operation when the TOP value (resolution) is
actively changed during operation, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after
each capture. Changing the edge sensing must be done as early as possible after the ICRn
Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be
cleared by software (writing a logical one to the I/O bit location). For measuring frequency only,
the clearing of the ICFn Flag is not required (if an interrupt handler is used).
15.6 Output Compare units
The 16-bit comparator continuously compares TCNTn with the Output Compare Register
(OCRnx). If TCNT equals OCRnx the comparator signals a match. A match will set the Output
Compare Flag (OCFnx) at the next timer clock cycle. If enabled (OCIEnx = 1), the Output Compare
Flag generates an Output Compare interrupt. The OCFnx Flag is automatically cleared
when the interrupt is executed. Alternatively the OCFnx Flag can be cleared by software by writing
a logical one to its I/O bit location. The Waveform Generator uses the match signal to
generate an output according to operating mode set by the Waveform Generation mode
(WGMn3:0) bits and Compare Output mode (COMnx1:0) bits. The TOP and BOTTOM signals
are used by the Waveform Generator for handling the special cases of the extreme values in
some modes of operation (see “Modes of operation” on page 127)
A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (that
is, counter resolution). In addition to the counter resolution, the TOP value defines the period
time for waveforms generated by the Waveform Generator.
Figure 15-4 shows a block diagram of the Output Compare unit. The small “n” in the register and
bit names indicates the device number (n = n for Timer/Counter n), and the “x” indicates Output
Compare unit (A/B/C). The elements of the block diagram that are not directly a part of the Output
Compare unit are gray shaded.
Figure 15-4. Output Compare Unit, block diagram.
OCFnx (int.req.)
= (16-bit comparator )
OCRnx buffer (16-bit register)
OCRnxH buf. (8-bit)
OCnx
TEMP (8-bit)
DATA BUS (8-bit)
OCRnxL buf. (8-bit)
TCNTn (16-bit counter)
TCNTnH (8-bit) TCNTnL (8-bit)
WGMn3:0 COMnx1:0
OCRnx (16-bit register)
OCRnxH (8-bit) OCRnxL (8-bit)
Waveform generator
TOP
BOTTOM125
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The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation
(PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the
double buffering is disabled. The double buffering synchronizes the update of the OCRnx Compare
Register to either TOP or BOTTOM of the counting sequence. The synchronization
prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output
glitch-free.
The OCRnx Register access may seem complex, but this is not case. When the double buffering
is enabled, the CPU has access to the OCRnx Buffer Register, and if double buffering is disabled
the CPU will access the OCRnx directly. The content of the OCR1x (Buffer or Compare)
Register is only changed by a write operation (the Timer/Counter does not update this register
automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the high byte
temporary register (TEMP). However, it is a good practice to read the low byte first as when
accessing other 16-bit registers. Writing the OCRnx Registers must be done via the TEMP Register
since the compare of all 16 bits is done continuously. The high byte (OCRnxH) has to be
written first. When the high byte I/O location is written by the CPU, the TEMP Register will be
updated by the value written. Then when the low byte (OCRnxL) is written to the lower eight bits,
the high byte will be copied into the upper 8-bits of either the OCRnx buffer or OCRnx Compare
Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to Section “Accessing 16-bit registers”
on page 117.
15.6.1 Force Output Compare
In non-PWM Waveform Generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOCnx) bit. Forcing compare match will not set the
OCFnx Flag or reload/clear the timer, but the OCnx pin will be updated as if a real compare
match had occurred (the COMn1:0 bits settings define whether the OCnx pin is set, cleared or
toggled).
15.6.2 Compare Match Blocking by TCNTn write
All CPU writes to the TCNTn Register will block any compare match that occurs in the next timer
clock cycle, even when the timer is stopped. This feature allows OCRnx to be initialized to the
same value as TCNTn without triggering an interrupt when the Timer/Counter clock is enabled.
15.6.3 Using the Output Compare unit
Since writing TCNTn in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNTn when using any of the Output Compare
channels, independent of whether the Timer/Counter is running or not. If the value written to
TCNTn equals the OCRnx value, the compare match will be missed, resulting in incorrect waveform
generation. Do not write the TCNTn equal to TOP in PWM modes with variable TOP
values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF.
Similarly, do not write the TCNTn value equal to BOTTOM when the counter is counting down.
The setup of the OCnx should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OCnx value is to use the Force Output Compare
(FOCnx) strobe bits in Normal mode. The OCnx Register keeps its value even when
changing between Waveform Generation modes.
Be aware that the COMnx1:0 bits are not double buffered together with the compare value.
Changing the COMnx1:0 bits will take effect immediately.126
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15.7 Compare Match Output unit
The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses
the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match.
Secondly the COMnx1:0 bits control the OCnx pin output source. Figure 15-5 shows a simplified
schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O
pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers
(DDR and PORT) that are affected by the COMnx1:0 bits are shown. When referring to the
OCnx state, the reference is for the internal OCnx Register, not the OCnx pin. If a system reset
occur, the OCnx Register is reset to “0”.
Figure 15-5. Compare Match Output unit, schematic.
The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform
Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or output)
is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OCnx pin (DDR_OCnx) must be set as output before the OCnx value is visible
on the pin. The port override function is generally independent of the Waveform Generation
mode, but there are some exceptions. Refer to Table 15-1 on page 137, Table 15-2 on page
137, and Table 15-3 on page 138 for details.
The design of the Output Compare pin logic allows initialization of the OCnx state before the output
is enabled. Note that some COMnx1:0 bit settings are reserved for certain modes of
operation. See “16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)” on page 115.
The COMnx1:0 bits have no effect on the Input Capture unit.
15.7.1 Compare Output mode and Waveform generation
The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes.
For all modes, setting the COMnx1:0 = 0 tells the Waveform Generator that no action on the
OCnx Register is to be performed on the next compare match. For compare output actions in the
PORT
DDR
D Q
D Q
OCnx
OCnx pin
D Q Waveform
generator
COMnx1
COMnx0
0
1
DATA BUS
FOCnx
clkI/O127
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non-PWM modes refer to Table 15-1 on page 137. For fast PWM mode refer to Table 15-2 on
page 137, and for phase correct and phase and frequency correct PWM refer to Table 15-3 on
page 138.
A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOCnx strobe bits.
15.8 Modes of operation
The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins,
is defined by the combination of the Waveform Generation mode (WGMn3:0) and Compare Output
mode (COMnx1:0) bits. The Compare Output mode bits do not affect the counting sequence,
while the Waveform Generation mode bits do. The COMnx1:0 bits control whether the PWM output
generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes
the COMnx1:0 bits control whether the output should be set, cleared or toggle at a compare
match (see “Compare Match Output unit” on page 126).
For detailed timing information refer to “Timer/Counter timing diagrams” on page 134.
15.8.1 Normal mode
The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the
BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOVn) will be set in
the same timer clock cycle as the TCNTn becomes zero. The TOVn Flag in this case behaves
like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow
interrupt that automatically clears the TOVn Flag, the timer resolution can be increased by software.
There are no special cases to consider in the Normal mode, a new counter value can be
written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maximum
interval between the external events must not exceed the resolution of the counter. If the interval
between events are too long, the timer overflow interrupt or the prescaler must be used to
extend the resolution for the capture unit.
The Output Compare units can be used to generate interrupts at some given time. Using the
Output Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
15.8.2 Clear Timer on Compare Match (CTC) mode
In Clear Timer on Compare or CTC mode (WGMn3:0 = 4 or 12), the OCRnA or ICRn Register
are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when
the counter value (TCNTn) matches either the OCRnA (WGMn3:0 = 4) or the ICRn (WGMn3:0 =
12). The OCRnA or ICRn define the top value for the counter, hence also its resolution. This
mode allows greater control of the compare match output frequency. It also simplifies the operation
of counting external events.
The timing diagram for the CTC mode is shown in Figure 15-6 on page 128. The counter value
(TCNTn) increases until a compare match occurs with either OCRnA or ICRn, and then counter
(TCNTn) is cleared.128
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Figure 15-6. CTC mode, timing diagram.
An interrupt can be generated at each time the counter value reaches the TOP value by either
using the OCFnA or ICFn Flag according to the register used to define the TOP value. If the
interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However,
changing the TOP to a value close to BOTTOM when the counter is running with none or a
low prescaler value must be done with care since the CTC mode does not have the double buffering
feature. If the new value written to OCRnA or ICRn is lower than the current value of
TCNTn, the counter will miss the compare match. The counter will then have to count to its maximum
value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur.
In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode
using OCRnA for defining TOP (WGMn3:0 = 15) since the OCRnA then will be double buffered.
For generating a waveform output in CTC mode, the OCnA output can be set to toggle its logical
level on each compare match by setting the Compare Output mode bits to toggle mode
(COMnA1:0 = 1). The OCnA value will not be visible on the port pin unless the data direction for
the pin is set to output (DDR_OCnA = 1). The waveform generated will have a maximum frequency
of fOCnA = fclk_I/O/2 when OCRnA is set to zero (0x0000). The waveform frequency is
defined by the following equation:
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOVn Flag is set in the same timer clock cycle that the
counter counts from MAX to 0x0000.
15.8.3 Fast PWM mode
The fast Pulse Width Modulation or fast PWM mode (WGMn3:0 = 5, 6, 7, 14, or 15) provides a
high frequency PWM waveform generation option. The fast PWM differs from the other PWM
options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts
from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is set on
the compare match between TCNTn and OCRnx, and cleared at TOP. In inverting Compare
Output mode output is cleared on compare match and set at TOP. Due to the single-slope operation,
the operating frequency of the fast PWM mode can be twice as high as the phase correct
and phase and frequency correct PWM modes that use dual-slope operation. This high frequency
makes the fast PWM mode well suited for power regulation, rectification, and DAC
applications. High frequency allows physically small sized external components (coils, capacitors),
hence reduces total system cost.
TCNTn
OCnA
(Toggle)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(interrupt on TOP)
Period 1 2 3 4
(COMnA1:0 = 1)
f
OCnA
f
clk_I/O
2 ⋅ ⋅ N ( ) 1 + OCRnA = --------------------------------------------------129
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The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or
OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum
resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be
calculated by using the following equation:
In fast PWM mode the counter is incremented until the counter value matches either one of the
fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 5, 6, or 7), the value in ICRn (WGMn3:0 =
14), or the value in OCRnA (WGMn3:0 = 15). The counter is then cleared at the following timer
clock cycle. The timing diagram for the fast PWM mode is shown in Figure 15-7. The figure
shows fast PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the
timing diagram shown as a histogram for illustrating the single-slope operation. The diagram
includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn
slopes represent compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will
be set when a compare match occurs.
Figure 15-7. Fast PWM mode, timing diagram.
The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addition
the OCnA or ICFn Flag is set at the same timer clock cycle as TOVn is set when either OCRnA
or ICRn is used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler
routine can be used for updating the TOP and compare values.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNTn and the OCRnx.
Note that when using fixed TOP values the unused bits are masked to zero when any of the
OCRnx Registers are written.
The procedure for updating ICRn differs from updating OCRnA when used for defining the TOP
value. The ICRn Register is not double buffered. This means that if ICRn is changed to a low
value when the counter is running with none or a low prescaler value, there is a risk that the new
ICRn value written is lower than the current value of TCNTn. The result will then be that the
counter will miss the compare match at the TOP value. The counter will then have to count to the
MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur.
The OCRnA Register however, is double buffered. This feature allows the OCRnA I/O location
RFPWM
log( ) TOP + 1
log( ) 2 = -----------------------------------
TCNTn
OCRnx / TOP Update
and TOVn Interrupt Flag
Set and OCnA Interrupt
Flag Set or ICFn
Interrupt Flag Set
(Interrupt on TOP)
Period 1 2 3 4 5 6 7 8
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)130
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to be written anytime. When the OCRnA I/O location is written the value written will be put into
the OCRnA Buffer Register. The OCRnA Compare Register will then be updated with the value
in the Buffer Register at the next timer clock cycle the TCNTn matches TOP. The update is done
at the same timer clock cycle as the TCNTn is cleared and the TOVn Flag is set.
Using the ICRn Register for defining TOP works well when using fixed TOP values. By using
ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However,
if the base PWM frequency is actively changed (by changing the TOP value), using the OCRnA
as TOP is clearly a better choice due to its double buffer feature.
In fast PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins.
Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output
can be generated by setting the COMnx1:0 to three (see Table on page 137). The actual OCnx
value will only be visible on the port pin if the data direction for the port pin is set as output
(DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at
the compare match between OCRnx and TCNTn, and clearing (or setting) the OCnx Register at
the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represents special cases when generating a PWM
waveform output in the fast PWM mode. If the OCRnx is set equal to BOTTOM (0x0000) the output
will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCRnx equal to TOP
will result in a constant high or low output (depending on the polarity of the output set by the
COMnx1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting
OCnA to toggle its logical level on each compare match (COMnA1:0 = 1). This applies only
if OCR1A is used to define the TOP value (WGM13:0 = 15). The waveform generated will have
a maximum frequency of fOCnA = fclk_I/O/2 when OCRnA is set to zero (0x0000). This feature is
similar to the OCnA toggle in CTC mode, except the double buffer feature of the Output Compare
unit is enabled in the fast PWM mode.
15.8.4 Phase correct PWM mode
The phase correct Pulse Width Modulation or phase correct PWM mode (WGMn3:0 = 1, 2, 3,
10, or 11) provides a high resolution phase correct PWM waveform generation option. The
phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dualslope
operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from
TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is
cleared on the compare match between TCNTn and OCRnx while upcounting, and set on the
compare match while downcounting. In inverting Output Compare mode, the operation is
inverted. The dual-slope operation has lower maximum operation frequency than single slope
operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes
are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined
by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to
f
OCnxPWM
f
clk_I/O
N ⋅ ( ) 1 + TOP = -----------------------------------131
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0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution
in bits can be calculated by using the following equation:
In phase correct PWM mode the counter is incremented until the counter value matches either
one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 1, 2, or 3), the value in ICRn
(WGMn3:0 = 10), or the value in OCRnA (WGMn3:0 = 11). The counter has then reached the
TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clock
cycle. The timing diagram for the phase correct PWM mode is shown on Figure 15-8. The figure
shows phase correct PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn
value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The
diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on
the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx Interrupt
Flag will be set when a compare match occurs.
Figure 15-8. Phase correct PWM mode, timing diagram.
The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. When
either OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn Flag is set accordingly
at the same timer clock cycle as the OCRnx Registers are updated with the double buffer
value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter
reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNTn and the OCRnx.
Note that when using fixed TOP values, the unused bits are masked to zero when any of the
OCRnx Registers are written. As the third period shown in Figure 15-8 illustrates, changing the
TOP actively while the Timer/Counter is running in the phase correct mode can result in an
unsymmetrical output. The reason for this can be found in the time of update of the OCRnx RegRPCPWM
log( ) TOP + 1
log( ) 2 = -----------------------------------
OCRnx/TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(interrupt on TOP)
1 2 3 4
TOVn Interrupt Flag Set
(interrupt on Bottom)
TCNTn
Period
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)132
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ister. Since the OCRnx update occurs at TOP, the PWM period starts and ends at TOP. This
implies that the length of the falling slope is determined by the previous TOP value, while the
length of the rising slope is determined by the new TOP value. When these two values differ the
two slopes of the period will differ in length. The difference in length gives the unsymmetrical
result on the output.
It is recommended to use the phase and frequency correct mode instead of the phase correct
mode when changing the TOP value while the Timer/Counter is running. When using a static
TOP value there are practically no differences between the two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the
OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted
PWM output can be generated by setting the COMnx1:0 to three (see Table 15-3 on page 138).
The actual OCnx value will only be visible on the port pin if the data direction for the port pin is
set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx
Register at the compare match between OCRnx and TCNTn when the counter increments, and
clearing (or setting) the OCnx Register at compare match between OCRnx and TCNTn when
the counter decrements. The PWM frequency for the output when using phase correct PWM can
be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If
OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1:0 = 1, the OC1A output
will toggle with a 50% duty cycle.
15.8.5 Phase and frequency correct PWM mode
The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM
mode (WGMn3:0 = 8 or 9) provides a high resolution phase and frequency correct PWM waveform
generation option. The phase and frequency correct PWM mode is, like the phase correct
PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM
(0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the
Output Compare (OCnx) is cleared on the compare match between TCNTn and OCRnx while
upcounting, and set on the compare match while downcounting. In inverting Compare Output
mode, the operation is inverted. The dual-slope operation gives a lower maximum operation frequency
compared to the single-slope operation. However, due to the symmetric feature of the
dual-slope PWM modes, these modes are preferred for motor control applications.
The main difference between the phase correct, and the phase and frequency correct PWM
mode is the time the OCRnx Register is updated by the OCRnx Buffer Register, (see Figure 15-
8 on page 131 and Figure 15-9 on page 133).
The PWM resolution for the phase and frequency correct PWM mode can be defined by either
ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and
f
OCnxPCPWM
f
clk_I/O
2 ⋅ ⋅ N TOP = ----------------------------133
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the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can
be calculated using the following equation:
In phase and frequency correct PWM mode the counter is incremented until the counter value
matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA (WGMn3:0 = 9). The
counter has then reached the TOP and changes the count direction. The TCNTn value will be
equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency
correct PWM mode is shown on Figure 15-9. The figure shows phase and frequency correct
PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram
shown as a histogram for illustrating the dual-slope operation. The diagram includes noninverted
and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent
compare matches between OCRnx and TCNTn. The OCnx Interrupt Flag will be set when a
compare match occurs.
Figure 15-9. Phase and frequency correct PWM mode, timing diagram.
The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx
Registers are updated with the double buffer value (at BOTTOM). When either OCRnA or ICRn
is used for defining the TOP value, the OCnA or ICFn Flag set when TCNTn has reached TOP.
The Interrupt Flags can then be used to generate an interrupt each time the counter reaches the
TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNTn and the OCRnx.
As Figure 15-9 shows the output generated is, in contrast to the phase correct mode, symmetrical
in all periods. Since the OCRnx Registers are updated at BOTTOM, the length of the rising
and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore
frequency correct.
RPFCPWM
log( ) TOP + 1
log( ) 2 = -----------------------------------
OCRnx/TOP Updateand
TOVn Interrupt Flag Set
(interrupt on Bottom)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(interrupt on TOP)
1 2 3 4
TCNTn
Period
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)134
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Using the ICRn Register for defining TOP works well when using fixed TOP values. By using
ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However,
if the base PWM frequency is actively changed by changing the TOP value, using the OCRnA as
TOP is clearly a better choice due to its double buffer feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms
on the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and
an inverted PWM output can be generated by setting the COMnx1:0 to three (see Table 15-3 on
page 138). The actual OCnx value will only be visible on the port pin if the data direction for the
port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing)
the OCnx Register at the compare match between OCRnx and TCNTn when the counter increments,
and clearing (or setting) the OCnx Register at compare match between OCRnx and
TCNTn when the counter decrements. The PWM frequency for the output when using phase
and frequency correct PWM can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represents special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be set to high for noninverted
PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A
is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle
with a 50% duty cycle.
15.9 Timer/Counter timing diagrams
The Timer/Counter is a synchronous design and the timer clock (clkTn) is therefore shown as a
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for
modes utilizing double buffering). Figure 15-10 shows a timing diagram for the setting of OCFnx.
Figure 15-10. Timer/Counter timing diagram, setting of OCFnx, no prescaling.
Figure 15-11 on page 135 shows the same timing data, but with the prescaler enabled.
f
OCnxPFCPWM
f
clk_I/O
2 ⋅ ⋅ N TOP = ----------------------------
clkTn
(clkI/O/1)
OCFnx
clkI/O
OCRnx
TCNTn
OCRnx value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2135
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Figure 15-11. Timer/Counter timing diagram, setting of OCFnx, with prescaler (fclk_I/O/8).
Figure 15-12 shows the count sequence close to TOP in various modes. When using phase and
frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams
will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
The same renaming applies for modes that set the TOVn Flag at BOTTOM.
Figure 15-12. Timer/Counter timing diagram, no prescaling.
Figure 15-13 on page 136 shows the same timing data, but with the prescaler enabled.
OCFnx
OCRnx
TCNTn
OCRnx value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clkI/O
clkTn
(clkI/O/8)
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
(update at TOP)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2
Old OCRnx value New OCRnx value
TOP - 1 TOP BOTTOM BOTTOM + 1
clkTn
(clkI/O/1)
clkI/O136
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Figure 15-13. Timer/Counter timing diagram, with prescaler (fclk_I/O/8).
15.10 16-bit Timer/Counter register description
15.10.1 TCCR1A – Timer/Counter1 Control Register A
15.10.2 TCCR3A – Timer/Counter3 Control Register A
• Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A
• Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B
• Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C
The COMnA1:0, COMnB1:0, and COMnC1:0 control the output compare pins (OCnA, OCnB,
and OCnC respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the
OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or
both of the COMnB1:0 bits are written to one, the OCnB output overrides the normal port functionality
of the I/O pin it is connected to. If one or both of the COMnC1:0 bits are written to one,
the OCnC output overrides the normal port functionality of the I/O pin it is connected to. However,
note that the Data Direction Register (DDR) bit corresponding to the OCnA, OCnB or
OCnC pin must be set in order to enable the output driver.
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
(update at TOP)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOP - 1 TOP TOP - 1 TOP - 2
Old OCRnx value New OCRnx value
TOP - 1 TOP BOTTOM BOTTOM + 1
clkI/O
clk Tn
(clkI/O /8)
Bit 7 6 5 4 3 2 1 0
COM1A1 COM1A0 COM1B1 COM1B0 COM1C1 COM1C0 WGM11 WGM10 TCCR1A
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
COM3A1 COM3A0 COM3B1 COM3B0 COM3C1 COM3C0 WGM31 WGM30 TCCR3A
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0137
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When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is
dependent of the WGMn3:0 bits setting. Table 15-1 shows the COMnx1:0 bit functionality when
the WGMn3:0 bits are set to a normal or a CTC mode (non-PWM).
Table 15-2 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast
PWM mode.
Note: A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and
COMnA1/COMnB1/COMnC1 is set. In this case the compare match is ignored, but the set or clear
is done at TOP. See “Fast PWM mode” on page 104. for more details.
Table 15-3 on page 138 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to
the phase correct and frequency correct PWM mode.
Table 15-1. Compare Output mode, non-PWM.
COMnA1/COMnB1/
COMnC1
COMnA0/COMnB0/
COMnC0 Description
0 0 Normal port operation, OCnA/OCnB/OCnC
disconnected.
0 1 Toggle OCnA/OCnB/OCnC on compare match.
1 0 Clear OCnA/OCnB/OCnC on compare match (set
output to low level).
1 1 Set OCnA/OCnB/OCnC on compare match (set
output to high level).
Table 15-2. Compare Output mode, fast PWM.
COMnA1/COMnB1/
COMnC0
COMnA0/COMnB0/
COMnC0 Description
0 0 Normal port operation, OCnA/OCnB/OCnC
disconnected.
0 1
WGM13:0 = 14 or 15: Toggle OC1A on Compare
Match, OC1B and OC1C disconnected (normal port
operation). For all other WGM1 settings, normal port
operation, OC1A/OC1B/OC1C disconnected.
1 0 Clear OCnA/OCnB/OCnC on compare match, set
OCnA/OCnB/OCnC at TOP
1 1 Set OCnA/OCnB/OCnC on compare match, clear
OCnA/OCnB/OCnC at TOP138
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Note: A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and
COMnA1/COMnB1//COMnC1 is set. See “Phase correct PWM mode” on page 106. for more
details.
• Bit 1:0 – WGMn1:0: Waveform Generation mode
Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform
generation to be used, see Table 15-4 on page 138. Modes of operation supported by the
Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode,
and three types of Pulse Width Modulation (PWM) modes. (See “Modes of operation” on page
103.).
Table 15-3. Compare Output mode, phase correct and phase and frequency correct PWM.
COMnA1/COMnB/
COMnC1
COMnA0/COMnB0/
COMnC0 Description
0 0 Normal port operation, OCnA/OCnB/OCnC
disconnected.
0 1
WGM13:0 = 8, 9 10 or 11: Toggle OC1A on
Compare Match, OC1B and OC1C
disconnected (normal port operation). For all
other WGM1 settings, normal port operation,
OC1A/OC1B/OC1C disconnected.
1 0
Clear OCnA/OCnB/OCnC on compare
match when up-counting. Set
OCnA/OCnB/OCnC on compare match
when counting down.
1 1
Set OCnA/OCnB/OCnC on compare match
when up-counting. Clear
OCnA/OCnB/OCnC on compare match
when counting down.
Table 15-4. Waveform Generation mode bit description (1).
Mode WGMn3
WGMn2
(CTCn)
WGMn1
(PWMn1)
WGMn0
(PWMn0)
Timer/Counter mode of
operation TOP
Update of
OCRnx at
TOVn flag
set on
0 0 0 0 0 Normal 0xFFFF Immediate MAX
1 0 0 0 1 PWM, phase correct, 8-bit 0x00FF TOP BOTTOM
2 0 0 1 0 PWM, phase correct, 9-bit 0x01FF TOP BOTTOM
3 0 0 1 1 PWM, phase correct, 10-bit 0x03FF TOP BOTTOM
4 0 1 0 0 CTC OCRnA Immediate MAX
5 0 1 0 1 Fast PWM, 8-bit 0x00FF TOP TOP
6 0 1 1 0 Fast PWM, 9-bit 0x01FF TOP TOP
7 0 1 1 1 Fast PWM, 10-bit 0x03FF TOP TOP
81 0 0 0 PWM, phase and frequency
Correct ICRn BOTTOM BOTTOM
91 0 0 1 PWM, phase and frequency
Correct OCRnA BOTTOM BOTTOM
10 1 0 1 0 PWM, phase correct ICRn TOP BOTTOM139
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Note: 1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and
location of these bits are compatible with previous versions of the timer.
15.10.3 TCCR1B – Timer/Counter1 Control Register B
15.10.4 TCCR3B – Timer/Counter3 Control Register B
• Bit 7 – ICNCn: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is
activated, the input from the Input Capture Pin (ICPn) is filtered. The filter function requires four
successive equal valued samples of the ICPn pin for changing its output. The input capture is
therefore delayed by four Oscillator cycles when the noise canceler is enabled.
• Bit 6 – ICESn: Input Capture Edge Select
This bit selects which edge on the Input Capture Pin (ICPn) that is used to trigger a capture
event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICESn bit is written to one, a rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICESn setting, the counter value is copied into the
Input Capture Register (ICRn). The event will also set the Input Capture Flag (ICFn), and this
can be used to cause an Input Capture Interrupt, if this interrupt is enabled.
When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the
TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the input capture
function is disabled.
• Bit 5 – Reserved bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be
written to zero when TCCRnB is written.
• Bit 4:3 – WGMn3:2: Waveform Generation mode
See TCCRnA Register description.
11 1 0 1 1 PWM, phase correct OCRnA TOP BOTTOM
12 1 1 0 0 CTC ICRn Immediate MAX
13 1 1 0 1 (Reserved) – – –
14 1 1 1 0 Fast PWM ICRn TOP TOP
15 1 1 1 1 Fast PWM OCRnA TOP TOP
Table 15-4. Waveform Generation mode bit description (1). (Continued)
Mode WGMn3
WGMn2
(CTCn)
WGMn1
(PWMn1)
WGMn0
(PWMn0)
Timer/Counter mode of
operation TOP
Update of
OCRnx at
TOVn flag
set on
Bit 7 6 5 4 3 2 1 0
ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B
Read/write R/W R/W R R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ICNC3 ICES3 – WGM33 WGM32 CS32 CS31 CS30 TCCR3B
Read/write R/W R/W R R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0140
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• Bit 2:0 – CSn2:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter, see Figure
14-8 on page 107 and Figure 14-9 on page 108.
If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
15.10.5 TCCR1C – Timer/Counter1 Control Register C
15.10.6 TCCR3C – Timer/Counter3 Control Register C
• Bit 7 – FOCnA: Force Output Compare for Channel A
• Bit 6 – FOCnB: Force Output Compare for Channel B
• Bit 5 – FOCnC: Force Output Compare for Channel C
The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM
mode. When writing a logical one to the FOCnA/FOCnB/FOCnC bit, an immediate compare
match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed
according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are implemented
as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the
effect of the forced compare.
A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in Clear
Timer on Compare Match (CTC) mode using OCRnA as TOP.
The FOCnA/FOCnB/FOCnB bits are always read as zero.
• Bit 4:0 – Reserved bits
These bits are reserved for future use. For ensuring compatibility with future devices, these bits
must be written to zero when TCCRnC is written.
Table 15-5. Clock Select bit description.
CSn2 CSn1 CSn0 Description
0 0 0 No clock source. (Timer/Counter stopped)
0 0 1 clkI/O/1 (no prescaling
0 1 0 clkI/O/8 (from prescaler)
0 1 1 clkI/O/64 (from prescaler)
1 0 0 clkI/O/256 (from prescaler)
1 0 1 clkI/O/1024 (from prescaler)
1 1 0 External clock source on Tn pin. Clock on falling edge
1 1 1 External clock source on Tn pin. Clock on rising edge
Bit 7 6 5 4 3 2 1 0
FOC1A FOC1B FOC1C – – – – – TCCR1C
Read/write W W W R R R R R
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
FOC3A FOC3B FOC3C – – – – – TCCR3C
Read/write W W W R R R R R
Initial value 0 0 0 0 0 0 0 0141
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15.10.7 TCNT1H and TCNT1L – Timer/Counter1
15.10.8 TCNT3H and TCNT3L – Timer/Counter3
The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit
registers” on page 117.
Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a compare
match between TCNTn and one of the OCRnx Registers.
Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock
for all compare units.
15.10.9 OCR1AH and OCR1AL – Output Compare Register 1 A
15.10.10 OCR1BH and OCR1BL – Output Compare Register 1 B
15.10.11 OCR1CH and OCR1CL – Output Compare Register 1 C
Bit 7 6 5 4 3 2 1 0
TCNT1[15:8] TCNT1H
TCNT1[7:0] TCNT1L
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
TCNT3[15:8] TCNT3H
TCNT3[7:0] TCNT3L
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OCR1A[15:8] OCR1AH
OCR1A[7:0] OCR1AL
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OCR1B[15:8] OCR1BH
OCR1B[7:0] OCR1BL
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OCR1C[15:8] OCR1CH
OCR1C[7:0] OCR1CL
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0142
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15.10.12 OCR3AH and OCR3AL – Output Compare Register 3 A
15.10.13 OCR3BH and OCR3BL – Output Compare Register 3 B
15.10.14 OCR3CH and OCR3CL – Output Compare Register 3 C
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNTn). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OCnx pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other
16-bit registers. See “Accessing 16-bit registers” on page 117.
15.10.15 ICR1H and ICR1L – Input Capture Register 1
15.10.16 ICR3H and ICR3L – Input Capture Register 3
The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the
ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers. See “Accessing 16-bit registers” on page 117.
Bit 7 6 5 4 3 2 1 0
OCR3A[15:8] OCR3AH
OCR3A[7:0] OCR3AL
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OCR3B[15:8] OCR3BH
OCR3B[7:0] OCR3BL
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OCR3C[15:8] OCR3CH
OCR3C[7:0] OCR3CL
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ICR1[15:8] ICR1H
ICR1[7:0] ICR1L
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ICR3[15:8] ICR3H
ICR3[7:0] ICR3L
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0143
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15.10.17 TIMSK1 – Timer/Counter1 Interrupt Mask Register
15.10.18 TIMSK3 – Timer/Counter3 Interrupt Mask Register
• Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt
Vector (see “Interrupts” on page 68) is executed when the ICFn Flag, located in TIFRn, is set.
• Bit 3 – OCIEnC: Timer/Countern, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 68) is executed when the OCFnC Flag, located in
TIFRn, is set.
• Bit 2 – OCIEnB: Timer/Countern, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 68) is executed when the OCFnB Flag, located in
TIFRn, is set.
• Bit 1 – OCIEnA: Timer/Countern, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 68) is executed when the OCFnA Flag, located in
TIFRn, is set.
• Bit 0 – TOIEn: Timer/Countern, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Overflow interrupt is enabled. The corresponding Interrupt Vector
(see “Interrupts” on page 68) is executed when the TOVn Flag, located in TIFRn, is set.
15.10.19 TIFR1 – Timer/Counter1 Interrupt Flag Register
15.10.20 TIFR3 – Timer/Counter3 Interrupt Flag Register
Bit 7 6 5 4 3 2 1 0
– – ICIE1 – OCIE1C OCIE1B OCIE1A TOIE1 TIMSK1
Read/write R R R/W R R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
– – ICIE3 – OCIE3C OCIE3B OCIE3A TOIE3 TIMSK3
Read/write R R R/W R R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
– – ICF1 – OCF1C OCF1B OCF1A TOV1 TIFR1
Read/write R R R/W R R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
– – ICF3 – OCF3C OCF3B OCF3A TOV3 TIFR3
Read/write R R R/W R R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0144
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• Bit 5 – ICFn: Timer/Countern, Input Capture Flag
This flag is set when a capture event occurs on the ICPn pin. When the Input Capture Register
(ICRn) is set by the WGMn3:0 to be used as the TOP value, the ICFn Flag is set when the counter
reaches the TOP value.
ICFn is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,
ICFn can be cleared by writing a logic one to its bit location.
• Bit 3– OCFnC: Timer/Countern, Output Compare C Match Flag
This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output
Compare Register C (OCRnC).
Note that a Forced Output Compare (FOCnC) strobe will not set the OCFnC Flag.
OCFnC is automatically cleared when the Output Compare Match C Interrupt Vector is executed.
Alternatively, OCFnC can be cleared by writing a logic one to its bit location.
• Bit 2 – OCFnB: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output
Compare Register B (OCRnB).
Note that a Forced Output Compare (FOCnB) strobe will not set the OCFnB Flag.
OCFnB is automatically cleared when the Output Compare Match B Interrupt Vector is executed.
Alternatively, OCFnB can be cleared by writing a logic one to its bit location.
• Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNTn value matches the Output Compare
Register A (OCRnA).
Note that a Forced Output Compare (FOCnA) strobe will not set the OCFnA Flag.
OCFnA is automatically cleared when the Output Compare Match A Interrupt Vector is executed.
Alternatively, OCFnA can be cleared by writing a logic one to its bit location.
• Bit 0 – TOVn: Timer/Countern, Overflow Flag
The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes,
the TOVn Flag is set when the timer overflows. Refer to Table 15-4 on page 138 for the TOVn
Flag behavior when using another WGMn3:0 bit setting.
TOVn is automatically cleared when the Timer/Countern Overflow Interrupt Vector is executed.
Alternatively, TOVn can be cleared by writing a logic one to its bit location.145
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16. 8-bit Timer/Counter2 with PWM and asynchronous operation
Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main
features are:
• Single channel counter
• Clear timer on compare match (auto reload)
• Glitch-free, phase correct pulse width modulator (PWM)
• Frequency generator
• 10-bit clock prescaler
• Overflow and compare match interrupt sources (TOV2, OCF2A and OCF2B)
• Allows clocking from external 32kHz watch crystal independent of the I/O clock
16.1 Overview
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 16-1. For the actual
placement of I/O pins, see “Pin configurations” on page 3. CPU accessible I/O Registers, including
I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations
are listed in the “8-bit Timer/Counter register description” on page 156.
The Power Reduction Timer/Counter2 bit, PRTIM2, in “PRR0 – Power Reduction Register 0” on
page 54 must be written to zero to enable Timer/Counter2 module.
Figure 16-1. 8-bit Timer/Counter, block diagram.
Timer/counter
DATA BUS
OCRnA
OCRnB
=
=
TCNTn
Waveform
generation
Waveform
generation
OCnA
OCnB
=
Fixed
TOP
value
Control logic
= 0
TOP BOTTOM
Count
Clear
Direction
TOVn
(int.req.)
OCnA
(int.req.)
OCnB
(int.req.)
TCCRnA TCCRnB
clkTn
ASSRn
Synchronization unit
Prescaler
T/C oscillator
clkI/O
clkASY
asynchronous mode
select (ASn)
Synchronized status flags
TOSC1
TOSC2
Status flags
clkI/O146
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16.1.1 Registers
The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit registers.
Interrupt request (abbreviated to Int.Req.) signals are all visible in the Timer Interrupt Flag
Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register
(TIMSK2). TIFR2 and TIMSK2 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from
the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by
the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock
source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive
when no clock source is selected. The output from the Clock Select logic is referred to as the
timer clock (clkT2).
The double buffered Output Compare Register (OCR2A and OCR2B) are compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator
to generate a PWM or variable frequency output on the Output Compare pins (OC2A and
OC2B). See “Output Compare unit” on page 147. for details. The compare match event will also
set the Compare Flag (OCF2A or OCF2B) which can be used to generate an Output Compare
interrupt request.
16.1.2 Definitions
Many register and bit references in this document are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 2. However, when using the register or bit
defines in a program, the precise form must be used, that is, TCNT2 for accessing
Timer/Counter2 counter value and so on.
The definitions in the table below are also used extensively throughout the section.
16.2 Timer/Counter clock sources
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous
clock source. The clock source clkT2 is by default equal to the MCU clock, clkI/O. When the AS2
bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter
Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see “ASSR
– Asynchronous Status Register” on page 161. For details on clock sources and prescaler, see
“Timer/Counter prescaler” on page 164.
16.3 Counter unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure
16-2 on page 147 shows a block diagram of the counter and its surrounding environment.
BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00).
MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR2A Register. The assignment is dependent
on the mode of operation.147
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Figure 16-2. Counter unit block diagram.
Signal description (internal signals):
count Increment or decrement TCNT2 by 1.
direction Selects between increment and decrement.
clear Clear TCNT2 (set all bits to zero).
clkTn Timer/Counter clock, referred to as clkT2 in the following.
top Signalizes that TCNT2 has reached maximum value.
bottom Signalizes that TCNT2 has reached minimum value (zero).
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clkT2). clkT2 can be generated from an external or internal clock source,
selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the
timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of
whether clkT2 is present or not. A CPU write overrides (has priority over) all counter clear or
count operations.
The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in
the Timer/Counter Control Register (TCCR2A) and the WGM22 located in the Timer/Counter
Control Register B (TCCR2B). There are close connections between how the counter behaves
(counts) and how waveforms are generated on the Output Compare outputs OC2A and OC2B.
For more details about advanced counting sequences and waveform generation, see “Modes of
operation” on page 150.
The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by
the WGM22:0 bits. TOV2 can be used for generating a CPU interrupt.
16.4 Output Compare unit
The 8-bit comparator continuously compares TCNT2 with the Output Compare Register
(OCR2A and OCR2B). Whenever TCNT2 equals OCR2A or OCR2B, the comparator signals a
match. A match will set the Output Compare Flag (OCF2A or OCF2B) at the next timer clock
cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output
Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is executed.
Alternatively, the Output Compare Flag can be cleared by software by writing a logical
one to its I/O bit location. The Waveform Generator uses the match signal to generate an output
according to operating mode set by the WGM22:0 bits and Compare Output mode (COM2x1:0)
bits. The max and bottom signals are used by the Waveform Generator for handling the special
cases of the extreme values in some modes of operation (“Modes of operation” on page 150).
Figure 15-10 on page 134 shows a block diagram of the Output Compare unit.
DATA BUS
TCNTn Control logic
count
TOVn
(int.req.)
bottom top
direction
clear
TOSC1
T/C
oscillator
TOSC2
Prescaler
clkI/O
clk Tn148
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Figure 16-3. Output Compare unit, block diagram.
The OCR2x Register is double buffered when using any of the Pulse Width Modulation (PWM)
modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double
buffering is disabled. The double buffering synchronizes the update of the OCR2x Compare
Register to either top or bottom of the counting sequence. The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR2x Register access may seem complex, but this is not case. When the double buffering
is enabled, the CPU has access to the OCR2x Buffer Register, and if double buffering is disabled
the CPU will access the OCR2x directly.
16.4.1 Force output compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOC2x) bit. Forcing compare match will not set the
OCF2x Flag or reload/clear the timer, but the OC2x pin will be updated as if a real compare
match had occurred (the COM2x1:0 bits settings define whether the OC2x pin is set, cleared or
toggled).
16.4.2 Compare Match Blocking by TCNT2 Write
All CPU write operations to the TCNT2 Register will block any compare match that occurs in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR2x to be initialized
to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is
enabled.
16.4.3 Using the Output Compare unit
Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNT2 when using the Output Compare channel,
independently of whether the Timer/Counter is running or not. If the value written to TCNT2
equals the OCR2x value, the compare match will be missed, resulting in incorrect waveform
generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is
downcounting.
OCFnx (int.req.)
= (8-bit comparator)
OCRnx
OCnx
DATA BUS
TCNTn
WGMn1:0
Waveform generator
top
FOCn
COMnX1:0
bottom149
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The setup of the OC2x should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OC2x value is to use the Force Output Compare
(FOC2x) strobe bit in Normal mode. The OC2x Register keeps its value even when
changing between Waveform Generation modes.
Be aware that the COM2x1:0 bits are not double buffered together with the compare value.
Changing the COM2x1:0 bits will take effect immediately.
16.5 Compare Match Output unit
The Compare Output mode (COM2x1:0) bits have two functions. The Waveform Generator uses
the COM2x1:0 bits for defining the Output Compare (OC2x) state at the next compare match.
Also, the COM2x1:0 bits control the OC2x pin output source. Figure 16-4 shows a simplified
schematic of the logic affected by the COM2x1:0 bit setting. The I/O Registers, I/O bits, and I/O
pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers
(DDR and PORT) that are affected by the COM2x1:0 bits are shown. When referring to the
OC2x state, the reference is for the internal OC2x Register, not the OC2x pin.
Figure 16-4. Compare Match Output unit, schematic.
The general I/O port function is overridden by the Output Compare (OC2x) from the Waveform
Generator if either of the COM2x1:0 bits are set. However, the OC2x pin direction (input or output)
is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OC2x pin (DDR_OC2x) must be set as output before the OC2x value is visible
on the pin. The port override function is independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC2x state before the output
is enabled. Note that some COM2x1:0 bit settings are reserved for certain modes of
operation. See “8-bit Timer/Counter register description” on page 156.
PORT
DDR
D Q
D Q
OCnx
OCnx pin
D Q Waveform
generator
COMnx1
COMnx0
0
1
DATA BU
S
FOCnx
clkI/O150
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16.5.1 Compare Output mode and Waveform generating
The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes.
For all modes, setting the COM2x1:0 = 0 tells the Waveform Generator that no action on the
OC2x Register is to be performed on the next compare match. For compare output actions in the
non-PWM modes refer to Table 16-4 on page 157. For fast PWM mode, refer to Table 16-5 on
page 158, and for phase correct PWM refer to Table 16-6 on page 158.
A change of the COM2x1:0 bits state will have effect at the first compare match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOC2x strobe bits.
16.6 Modes of operation
The mode of operation, that is, the behavior of the Timer/Counter and the Output Compare pins,
is defined by the combination of the Waveform Generation mode (WGM22:0) and Compare Output
mode (COM2x1:0) bits. The Compare Output mode bits do not affect the counting sequence,
while the Waveform Generation mode bits do. The COM2x1:0 bits control whether the PWM output
generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes
the COM2x1:0 bits control whether the output should be set, cleared, or toggled at a compare
match (see “Compare Match Output unit” on page 149).
For detailed timing information refer to Section “Timer/Counter timing diagrams” on page 154.
16.6.1 Normal mode
The simplest mode of operation is the Normal mode (WGM22:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom
(0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same
timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case behaves like a ninth
bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV2 Flag, the timer resolution can be increased by software.
There are no special cases to consider in the Normal mode, a new counter value can be written
anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the Output
Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
16.6.2 Clear Timer on Compare Match (CTC) mode
In Clear Timer on Compare or CTC mode (WGM22:0 = 2), the OCR2A Register is used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter
value (TCNT2) matches the OCR2A. The OCR2A defines the top value for the counter, hence
also its resolution. This mode allows greater control of the compare match output frequency. It
also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Table 16-5 on page 151. The counter value
(TCNT2) increases until a compare match occurs between TCNT2 and OCR2A, and then counter
(TCNT2) is cleared.151
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Figure 16-5. CTC mode, timing diagram.
An interrupt can be generated each time the counter value reaches the TOP value by using the
OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating
the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running
with none or a low prescaler value must be done with care since the CTC mode does not
have the double buffering feature. If the new value written to OCR2A is lower than the current
value of TCNT2, the counter will miss the compare match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can
occur.
For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical
level on each compare match by setting the Compare Output mode bits to toggle mode
(COM2A1:0 = 1). The OC2A value will not be visible on the port pin unless the data direction for
the pin is set to output. The waveform generated will have a maximum frequency of fOC2A =
fclk_I/O/2 when OCR2A is set to zero (0x00). The waveform frequency is defined by the following
equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the
counter counts from MAX to 0x00.
16.6.3 Fast PWM mode
The fast Pulse Width Modulation or fast PWM mode (WGM22:0 = 3 or 7) provides a high frequency
PWM waveform generation option. The fast PWM differs from the other PWM option by
its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM.
TOP is defined as 0xFF when WGM22:0 = 3, and OCR2A when MGM22:0 = 7. In noninverting
Compare Output mode, the Output Compare (OC2x) is cleared on the compare match
between TCNT2 and OCR2x, and set at BOTTOM. In inverting Compare Output mode, the output
is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the
operating frequency of the fast PWM mode can be twice as high as the phase correct PWM
mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited
for power regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), and therefore reduces total system cost.
TCNTn
OCnx
(Toggle)
OCnx Interrupt Flag Set
Period 1 2 3 4
(COMnx1:0 = 1)
f
OCnx
f
clk_I/O
2 ⋅ ⋅ N ( ) 1 + OCRnx = -------------------------------------------------152
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In fast PWM mode, the counter is incremented until the counter value matches the TOP value.
The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
PWM mode is shown in Figure 16-6. The TCNT2 value is in the timing diagram shown as a histogram
for illustrating the single-slope operation. The diagram includes non-inverted and
inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare
matches between OCR2x and TCNT2.
Figure 16-6. Fast PWM mode, timing diagram.
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches TOP. If the interrupt
is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin.
Setting the COM2x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output
can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3,
and OCR2A when WGM2:0 = 7 (See Table 16-2 on page 157). The actual OC2x value will only
be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform
is generated by setting (or clearing) the OC2x Register at the compare match between
OCR2x and TCNT2, and clearing (or setting) the OC2x Register at the timer clock cycle the
counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will
be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result
in a constantly high or low output (depending on the polarity of the output set by the COM2A1:0
bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting
OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The waveform
TCNTn
OCRnx Update and
TOVn Interrupt Flag Set
Period 1 2 3
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCRnx Interrupt Flag Set
4 5 6 7
f
OCnxPWM
f
clk_I/O
N ⋅ 256 = ------------------153
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generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2A is set to zero. This feature
is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output
Compare unit is enabled in the fast PWM mode.
16.6.4 Phase correct PWM mode
The phase correct PWM mode (WGM22:0 = 1 or 5) provides a high resolution phase correct
PWM waveform generation option. The phase correct PWM mode is based on a dual-slope
operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM.
TOP is defined as 0xFF when WGM22:0 = 1, and OCR2A when MGM22:0 = 5. In noninverting
Compare Output mode, the Output Compare (OC2x) is cleared on the compare match
between TCNT2 and OCR2x while upcounting, and set on the compare match while downcounting.
In inverting Output Compare mode, the operation is inverted. The dual-slope operation has
lower maximum operation frequency than single slope operation. However, due to the symmetric
feature of the dual-slope PWM modes, these modes are preferred for motor control
applications.
In phase correct PWM mode the counter is incremented until the counter value matches TOP.
When the counter reaches TOP, it changes the count direction. The TCNT2 value will be equal
to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown
on Figure 16-7. The TCNT2 value is in the timing diagram shown as a histogram for illustrating
the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The
small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x
and TCNT2.
Figure 16-7. Phase correct PWM mode, timing diagram.
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The
Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM
value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM
TOVn Interrupt Flag Set
OCnx Interrupt Flag Set
1 2 3
TCNTn
Period
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCRnx update154
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output can be generated by setting the COM2x1:0 to three. TOP is defined as 0xFF when
WGM2:0 = 3, and OCR2A when MGM2:0 = 7 (see Table 16-3 on page 157). The actual OC2x
value will only be visible on the port pin if the data direction for the port pin is set as output. The
PWM waveform is generated by clearing (or setting) the OC2x Register at the compare match
between OCR2x and TCNT2 when the counter increments, and setting (or clearing) the OC2x
Register at compare match between OCR2x and TCNT2 when the counter decrements. The
PWM frequency for the output when using phase correct PWM can be calculated by the following
equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in Figure 16-7 on page 153 OCnx has a transition from high to low
even though there is no Compare Match. The point of this transition is to guarantee symmetry
around BOTTOM. There are two cases that give a transition without Compare Match.
• OCR2A changes its value from MAX, like in Figure 16-7 on page 153. When the OCR2A
value is MAX the OCn pin value is the same as the result of a down-counting compare match.
To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result
of an up-counting Compare Match
• The timer starts counting from a value higher than the one in OCR2A, and for that reason
misses the Compare Match and hence the OCn change that would have happened on the
way up
16.7 Timer/Counter timing diagrams
The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT2)
is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should be replaced by
the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are
set. Figure 16-8 contains timing data for basic Timer/Counter operation. The figure shows the
count sequence close to the MAX value in all modes other than phase correct PWM mode.
Figure 16-8. Timer/Counter timing diagram, no prescaling.
f
OCnxPCPWM
f
clk_I/O
N ⋅ 510 = ------------------
clkTn
(clkI/O/1)
TOVn
clkI/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1155
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Figure 16-9 shows the same timing data, but with the prescaler enabled.
Figure 16-9. Timer/Counter timing diagram, with prescaler (fclk_I/O/8).
Figure 16-10 shows the setting of OCF2A in all modes except CTC mode.
Figure 16-10. Timer/Counter timing diagram, setting of OCF2A, with prescaler (fclk_I/O/8).
Figure 16-11 on page 156 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode.
TOVn
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
clkI/O
clkTn
(clkI/O/8)
OCFnx
OCRnx
TCNTn
OCRnx value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clkI/O
clkTn
(clkI/O/8)156
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Figure 16-11. Timer/Counter timing diagram, clear timer on compare match mode, with prescaler
(fclk_I/O/8).
16.8 8-bit Timer/Counter register description
16.8.1 TCCR2A – Timer/Counter Control Register A
• Bits 7:6 – COM2A1:0: Compare Match Output A mode
These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0
bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2A pin
must be set in order to enable the output driver.
When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the
WGM22:0 bit setting. Table 16-1 shows the COM2A1:0 bit functionality when the WGM22:0 bits
are set to a normal or CTC mode (non-PWM).
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1 TOP BOTTOM BOTTOM + 1
clkI/O
clkTn
(clkI/O/8)
Bit 7 6 5 4 3 2 1 0
COM2A1 COM2A0 COM2B1 COM2B0 – – WGM21 WGM20 TCCR2A
Read/write R/W R/W R/W R/W R R R/W R/W
Initial value 0 0 0 0 0 0 0 0
Table 16-1. Compare output mode, non-PWM mode.
COM2A1 COM2A0 Description
0 0 Normal port operation, OC2A disconnected
0 1 Toggle OC2A on Compare Match
1 0 Clear OC2A on Compare Match
1 1 Set OC2A on Compare Match157
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Table 16-2 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM
mode.
Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Compare
Match is ignored, but the set or clear is done at TOP. See “Fast PWM mode” on page 151
for more details.
Table 16-3 shows the COM2A1:0 bit functionality when the WGM22:0 bits are set to phase correct
PWM mode.
Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Compare
Match is ignored, but the set or clear is done at TOP. See “Phase correct PWM mode” on
page 153 for more details.
• Bits 5:4 – COM2B1:0: Compare Match Output B mode
These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0
bits are set, the OC2B output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2B pin
must be set in order to enable the output driver.
When OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the
WGM22:0 bit setting. Table 16-4 shows the COM2B1:0 bit functionality when the WGM22:0 bits
are set to a normal or CTC mode (non-PWM).
Table 16-2. Compare Output mode, fast PWM mode (1).
COM2A1 COM2A0 Description
0 0 Normal port operation, OC2A disconnected
0 1 WGM22 = 0: Normal Port Operation, OC0A Disconnected.
WGM22 = 1: Toggle OC2A on Compare Match.
1 0 Clear OC2A on Compare Match, set OC2A at TOP
1 1 Set OC2A on Compare Match, clear OC2A at TOP
Table 16-3. Compare Output mode, phase correct PWM mode (1).
COM2A1 COM2A0 Description
0 0 Normal port operation, OC2A disconnected
0 1 WGM22 = 0: Normal Port Operation, OC2A Disconnected.
WGM22 = 1: Toggle OC2A on Compare Match.
1 0 Clear OC2A on Compare Match when up-counting. Set OC2A on Compare
Match when down-counting.
1 1 Set OC2A on Compare Match when up-counting. Clear OC2A on Compare
Match when down-counting.
Table 16-4. Compare Output mode, non-PWM mode.
COM2B1 COM2B0 Description
0 0 Normal port operation, OC2B disconnected
0 1 Toggle OC2B on Compare Match
1 0 Clear OC2B on Compare Match
1 1 Set OC2B on Compare Match158
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Table 16-5 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to fast PWM
mode.
Note: 1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Compare
Match is ignored, but the set or clear is done at TOP. See “Fast PWM mode” on page 151
for more details.
Table 16-6 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase correct
PWM mode.
Note: 1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Compare
Match is ignored, but the set or clear is done at TOP. See “Phase correct PWM mode” on
page 153 for more details.
• Bits 3, 2 – Res: Reserved bits
These bits are reserved bits in the Atmel AT90USB64/128 and will always read as zero.
• Bits 1:0 – WGM21:0: Waveform Generation mode
Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform
generation to be used, see Table 16-7. Modes of operation supported by the Timer/Counter
unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of
Pulse Width Modulation (PWM) modes (see “Modes of operation” on page 150).
Table 16-5. Compare Output mode, fast PWM mode (1).
COM2B1 COM2B0 Description
0 0 Normal port operation, OC2B disconnected.
0 1 Reserved
1 0 Clear OC2B on Compare Match, set OC2B at TOP
1 1 Set OC2B on Compare Match, clear OC2B at TOP
Table 16-6. Compare Output mode, phase correct PWM mode (1).
COM2B1 COM2B0 Description
0 0 Normal port operation, OC2B disconnected
0 1 Reserved
1 0 Clear OC2B on Compare Match when up-counting. Set OC2B on Compare
Match when down-counting
1 1 Set OC2B on Compare Match when up-counting. Clear OC2B on Compare
Match when down-counting
Table 16-7. Waveform Generation mode bit description.
Mode WGM2 WGM1 WGM0
Timer/Counter
mode of operation TOP
Update of
OCRx at
TOV flag
set on (1)(2)
0 0 0 0 Normal 0xFF Immediate MAX
1 0 0 1 PWM, phase correct 0xFF TOP BOTTOM
2 0 1 0 CTC OCRA Immediate MAX
3 0 1 1 Fast PWM 0xFF TOP MAX
4 1 0 0 Reserved – – –159
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Notes: 1. MAX= 0xFF
2. BOTTOM= 0x00
16.8.2 TCCR2B – Timer/Counter Control Register B
• Bit 7 – FOC2A: Force Output Compare A
The FOC2A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2A bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OC2A output is
changed according to its COM2A1:0 bits setting. Note that the FOC2A bit is implemented as a
strobe. Therefore it is the value present in the COM2A1:0 bits that determines the effect of the
forced compare.
A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR2A as TOP.
The FOC2A bit is always read as zero.
• Bit 6 – FOC2B: Force Output Compare B
The FOC2B bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR2B is written when operating in PWM mode. When writing a logical one to the FOC2B bit,
an immediate Compare Match is forced on the Waveform Generation unit. The OC2B output is
changed according to its COM2B1:0 bits setting. Note that the FOC2B bit is implemented as a
strobe. Therefore it is the value present in the COM2B1:0 bits that determines the effect of the
forced compare.
A FOC2B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR2B as TOP.
The FOC2B bit is always read as zero.
• Bits 5:4 – Res: Reserved bits
These bits are reserved bits in the AT90USB64/128 and will always read as zero.
• Bit 3 – WGM22: Waveform Generation mode
See the description in the “TCCR2A – Timer/Counter Control Register A” on page 156.
5 1 0 1 PWM, phase correct OCRA TOP BOTTOM
6 1 1 0 Reserved – – –
7 1 1 1 Fast PWM OCRA TOP TOP
Table 16-7. Waveform Generation mode bit description. (Continued)
Mode WGM2 WGM1 WGM0
Timer/Counter
mode of operation TOP
Update of
OCRx at
TOV flag
set on (1)(2)
Bit 7 6 5 4 3 2 1 0
FOC2A FOC2B – – WGM22 CS22 CS21 CS20 TCCR2B
Read/write W W R R R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0160
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• Bit 2:0 – CS22:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table
16-8.
16.8.3 TCNT2 – Timer/Counter Register
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare
Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running,
introduces a risk of missing a Compare Match between TCNT2 and the OCR2x Registers.
16.8.4 OCR2A – Output Compare Register A
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC2A pin.
16.8.5 OCR2B – Output Compare Register B
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC2B pin.
Table 16-8. Clock Select bit description.
CS22 CS21 CS20 Description
0 0 0 No clock source (Timer/Counter stopped)
0 0 1 clkT2S/(no prescaling)
0 1 0 clkT2S/8 (from prescaler)
0 1 1 clkT2S/32 (from prescaler)
1 0 0 clkT2S/64 (from prescaler)
1 0 1 clkT2S/128 (from prescaler)
1 1 0 clkT2S/256 (from prescaler)
1 1 1 clkT2S/1024 (from prescaler)
Bit 7 6 5 4 3 2 1 0
TCNT2[7:0] TCNT2
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OCR2A[7:0] OCR2A
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OCR2B[7:0] OCR2B
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0161
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16.9 Asynchronous operation of the Timer/Counter
16.9.1 ASSR – Asynchronous Status Register
• Bit 6 – EXCLK: Enable External Clock Input
When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer
is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a
32 kHz crystal. Writing to EXCLK should be done before asynchronous operation is selected.
Note that the crystal Oscillator will only run when this bit is zero.
• Bit 5 – AS2: Asynchronous Timer/Counter2
When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is
written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscillator
1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A,
OCR2B, TCCR2A and TCCR2B might be corrupted.
• Bit 4 – TCN2UB: Timer/Counter2 Update Busy
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set.
When TCNT2 has been updated from the temporary storage register, this bit is cleared by hardware.
A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value.
• Bit 3 – OCR2AUB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set.
When OCR2A has been updated from the temporary storage register, this bit is cleared by hardware.
A logical zero in this bit indicates that OCR2A is ready to be updated with a new value.
• Bit 2 – OCR2BUB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set.
When OCR2B has been updated from the temporary storage register, this bit is cleared by hardware.
A logical zero in this bit indicates that OCR2B is ready to be updated with a new value.
• Bit 1 – TCR2AUB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set.
When TCCR2A has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new
value.
• Bit 0 – TCR2BUB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes set.
When TCCR2B has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that TCCR2B is ready to be updated with a new
value.
If a write is performed to any of the five Timer/Counter2 Registers while its update busy flag is
set, the updated value might get corrupted and cause an unintentional interrupt to occur.
Bit 7 6 5 4 3 2 1 0
– EXCLK AS2 TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB ASSR
Read/write R R/W R/W R R R R R
Initial value 0 0 0 0 0 0 0 0162
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The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different.
When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A
and TCCR2B the value in the temporary storage register is read.
16.9.2 Asynchronous operation of Timer/Counter2
When Timer/Counter2 operates asynchronously, some considerations must be taken.
• Warning: When switching between asynchronous and synchronous clocking of
Timer/Counter2, the Timer Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A
safe procedure for switching clock source is:
a. Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2.
b. Select clock source by setting AS2 as appropriate.
c. Write new values to TCNT2, OCR2x, and TCCR2x.
d. To switch to asynchronous operation: Wait for TCN2UB, OCR2xUB, and TCR2xUB.
e. Clear the Timer/Counter2 Interrupt Flags.
f. Enable interrupts, if needed.
• The CPU main clock frequency must be more than four times the Oscillator frequency
• When writing to one of the registers TCNT2, OCR2x, or TCCR2x, the value is transferred to a
temporary register, and latched after two positive edges on TOSC1. The user should not
write a new value before the contents of the temporary register have been transferred to its
destination. Each of the five mentioned registers have their individual temporary register,
which means that, for example, writing to TCNT2 does not disturb an OCR2x write in
progress. To detect that a transfer to the destination register has taken place, the
Asynchronous Status Register – ASSR has been implemented
• When entering Power-save or ADC Noise Reduction mode after having written to TCNT2,
OCR2x, or TCCR2x, the user must wait until the written register has been updated if
Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode
before the changes are effective. This is particularly important if any of the Output Compare2
interrupt is used to wake up the device, since the Output Compare function is disabled during
writing to OCR2x or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode
before the corresponding OCR2xUB bit returns to zero, the device will never receive a
compare match interrupt, and the MCU will not wake up
• If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise Reduction
mode, precautions must be taken if the user wants to re-enter one of these modes: The
interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and reentering
sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the
device will fail to wake up. If the user is in doubt whether the time before re-entering Powersave
or ADC Noise Reduction mode is sufficient, the following algorithm can be used to
ensure that one TOSC1 cycle has elapsed:
a. Write a value to TCCR2x, TCNT2, or OCR2x.
b. Wait until the corresponding Update Busy Flag in ASSR returns to zero.
c. Enter Power-save or ADC Noise Reduction mode.
• When the asynchronous operation is selected, the 32.768kHz Oscillator for Timer/Counter2
is always running, except in Power-down and Standby modes. After a Power-up Reset or
wake-up from Power-down or Standby mode, the user should be aware of the fact that this
Oscillator might take as long as one second to stabilize. The user is advised to wait for at
least one second before using Timer/Counter2 after power-up or wake-up from Power-down
or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after 163
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a wake-up from Power-down or Standby mode due to unstable clock signal upon start-up, no
matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin
• Description of wake up from Power-save or ADC Noise Reduction mode when the timer is
clocked asynchronously: When the interrupt condition is met, the wake up process is started
on the following cycle of the timer clock, that is, the timer is always advanced by at least one
before the processor can read the counter value. After wake-up, the MCU is halted for four
cycles, it executes the interrupt routine, and resumes execution from the instruction following
SLEEP
• Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect
result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be
done through a register synchronized to the internal I/O clock domain. Synchronization takes
place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O
clock (clkI/O) again becomes active, TCNT2 will read as the previous value (before entering
sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from
Power-save mode is essentially unpredictable, as it depends on the wake-up time. The
recommended procedure for reading TCNT2 is thus as follows:
a. Write any value to either of the registers OCR2x or TCCR2x.
b. Wait for the corresponding Update Busy Flag to be cleared.
c. Read TCNT2.
• During asynchronous operation, the synchronization of the Interrupt Flags for the
asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is therefore
advanced by at least one before the processor can read the timer value causing the setting of
the Interrupt Flag. The Output Compare pin is changed on the timer clock and is not
synchronized to the processor clock
16.9.3 TIMSK2 – Timer/Counter2 Interrupt Mask Register
• Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable
When the OCIE2B bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match B interrupt is enabled. The corresponding interrupt is executed
if a compare match in Timer/Counter2 occurs, that is, when the OCF2B bit is set in the
Timer/Counter2 Interrupt Flag Register – TIFR2.
• Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable
When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a compare match in Timer/Counter2 occurs, that is, when the OCF2A bit is set in the
Timer/Counter2 Interrupt Flag Register – TIFR2.
• Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter2 occurs, that is, when the TOV2 bit is set in the Timer/Counter2 Interrupt
Flag Register – TIFR2.
Bit 7 6 5 4 3 2 1 0
– – – – – OCIE2B OCIE2A TOIE2 TIMSK2
Read/write R R R R R R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0164
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16.9.4 TIFR2 – Timer/Counter2 Interrupt Flag Register
• Bit 2 – OCF2B: Output Compare Flag 2 B
The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the
data in OCR2B – Output Compare Register2. OCF2B is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF2B is cleared by writing a logic
one to the flag. When the I-bit in SREG, OCIE2B (Timer/Counter2 Compare match Interrupt
Enable), and OCF2B are set (one), the Timer/Counter2 Compare match Interrupt is executed.
• Bit 1 – OCF2A: Output Compare Flag 2 A
The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the
data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic
one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 Compare match Interrupt
Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed.
• Bit 0 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared
by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Interrupt
Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In
PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00.
16.10 Timer/Counter prescaler
Figure 16-12. Prescaler for Timer/Counter2.
Bit 7 6 5 4 3 2 1 0
– – – – – OCF2B OCF2A TOV2 TIFR2
Read/write R R R R R R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
10-BIT T/C PRESCALER
TIMER/COUNTER2 CLOCK SOURCE
clkI/O clkT2S
TOSC1
AS2
CS20
CS21
CS22
clkT2S/8
clkT2S/64
clkT2S/128
clkT2S/1024
clkT2S/256
clkT2S/32
0 PSRASY
Clear
clkT2165
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The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main
system I/O clock clkIO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously
clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter
(RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can
then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock
source for Timer/Counter2. The Oscillator is optimized for use with a 32.768kHz crystal. Applying
an external clock source to TOSC1 is not recommended.
For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clkT2S/32, clkT2S/64,
clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected.
Setting the PSRASY bit in GTCCR resets the prescaler. This allows the user to operate with a
predictable prescaler.
16.10.1 GTCCR – General Timer/Counter Control Register
• Bit 1 – PSRASY: Prescaler Reset Timer/Counter2
When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared
immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous
mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by
hardware if the TSM bit is set. Refer to the description of the Section “GTCCR – General
Timer/Counter Control Register” on page 97 for a description of the Timer/Counter Synchronization
mode.
Bit 7 6 5 4 3 2 1 0
TSM – – – – – PSRASY
PSRSY
NC
GTCCR
Read/write R/W R R R R R R/W R/W
Initial value 0 0 0 0 0 0 0 0166
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17. Output Compare Modulator (OCM1C0A)
17.1 Overview
The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier
frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit
Timer/Counter1 and the Output Compare Unit of the 8-bit Timer/Counter0. For more details
about these Timer/Counters see “Timer/Counter0, Timer/Counter1, and Timer/Counter3 prescalers”
on page 96 and “8-bit Timer/Counter2 with PWM and asynchronous operation” on page
145.
Figure 17-1. Output Compare Modulator, block diagram.
When the modulator is enabled, the two output compare channels are modulated together as
shown in the block diagram (Figure 17-1).
17.2 Description
The Output Compare unit 1C and Output Compare unit 2 shares the PB7 port pin for output. The
outputs of the Output Compare units (OC1C and OC0A) overrides the normal PORTB7 Register
when one of them is enabled (that is, when COMnx1:0 is not equal to zero). When both OC1C
and OC0A are enabled at the same time, the modulator is automatically enabled.
The functional equivalent schematic of the modulator is shown on Figure 17-2. The schematic
includes part of the Timer/Counter units and the port B pin 7 output driver circuit.
Figure 17-2. Output Compare Modulator, schematic.
OC1C
Pin
OC1C /
OC0A / PB7
Timer/Counter 1
Timer/Counter 0 OC0A
PORTB7 DDRB7
D Q D Q
Pin
COMA01
COMA00
DATABUS
OC1C /
OC0A/ PB7
COM1C1
COM1C0
Modulator
1
0
OC1C
D Q
OC0A
D Q
(From Waveform generator)
(From Waveform generator)
0
1
Vcc167
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When the modulator is enabled the type of modulation (logical AND or OR) can be selected by
the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the
COMnx1:0 bit setting.
17.2.1 Timing example
Figure 17-3 illustrates the modulator in action. In this example the Timer/Counter1 is set to operate
in fast PWM mode (non-inverted) and Timer/Counter0 uses CTC waveform mode with toggle
Compare Output mode (COMnx1:0 = 1).
Figure 17-3. Output Compare Modulator, timing diagram.
In this example, Timer/Counter2 provides the carrier, while the modulating signal is generated
by the Output Compare unit C of the Timer/Counter1.
The resolution of the PWM signal (OC1C) is reduced by the modulation. The reduction factor is
equal to the number of system clock cycles of one period of the carrier (OC0A). In this example
the resolution is reduced by a factor of two. The reason for the reduction is illustrated in Figure
17-3 at the second and third period of the PB7 output when PORTB7 equals zero. The period 2
high time is one cycle longer than the period 3 high time, but the result on the PB7 output is
equal in both periods.
1 2
OC0A
(CTC mode)
OC1C
(FPWM mode)
PB7
(PORTB7 = 0)
PB7
(PORTB7 = 1)
(Period) 3
clk I/O168
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18. SPI – Serial Peripheral Interface
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
Atmel AT90USB64/128 and peripheral devices or between several AVR devices. The
AT90USB64/128 SPI includes the following features:
• Full-duplex, three-wire synchronous data transfer
• Master or slave operation
• LSB first or MSB first data transfer
• Seven programmable bit rates
• End of transmission interrupt flag
• Write collision flag protection
• Wake-up from Idle mode
• Double speed (CK/2) Master SPI mode
USART can also be used in Master SPI mode, see “USART in SPI mode” on page 202.
The Power Reduction SPI bit, PRSPI, in “PRR0 – Power Reduction Register 0” on page 54 must
be written to zero to enable SPI module.
Figure 18-1. SPI block diagram (1).
Note: 1. Refer to Figure 1-1 on page 3, and Table 11-6 on page 79 for SPI pin placement.
The interconnection between Master and Slave CPUs with SPI is shown in Figure 18-2 on page
169. The system consists of two shift Registers, and a Master clock generator. The SPI Master
initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. SPI2X SPI2X
DIVIDER
/2/4/8/16/32/64/128169
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Master and Slave prepare the data to be sent in their respective shift Registers, and the Master
generates the required clock pulses on the SCK line to interchange data. Data is always shifted
from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the
Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave
by pulling high the Slave Select, SS, line.
When configured as a Master, the SPI interface has no automatic control of the SS line. This
must be handled by user software before communication can start. When this is done, writing a
byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight
bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of
Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an
interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or
signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be
kept in the Buffer Register for later use.
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long
as the SS pin is driven high. In this state, software may update the contents of the SPI Data
Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin
until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission
Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt
is requested. The Slave may continue to place new data to be sent into SPDR before reading
the incoming data. The last incoming byte will be kept in the Buffer Register for later use.
Figure 18-2. SPI Master-slave interconnection.
The system is single buffered in the transmit direction and double buffered in the receive direction.
This means that bytes to be transmitted cannot be written to the SPI Data Register before
the entire shift cycle is completed. When receiving data, however, a received character must be
read from the SPI Data Register before the next character has been completely shifted in. Otherwise,
the first byte is lost.
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure
correct sampling of the clock signal, the frequency of the SPI clock should never exceed fosc/4.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden
according to Table 18-1 on page 170. For more details on automatic port overrides, refer to
“Alternate port functions” on page 76.
SHIFT
ENABLE170
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Note: 1. See “Alternate functions of Port B” on page 79 for a detailed description of how to define the
direction of the user defined SPI pins.
The following code examples show how to initialize the SPI as a Master and how to perform a
simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction
Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the
actual data direction bits for these pins. For example, if MOSI is placed on pin PB5, replace
DD_MOSI with DDB5 and DDR_SPI with DDRB.
Table 18-1. SPI pin overrides (1).
Pin Direction, master SPI Direction, slave SPI
MOSI User defined Input
MISO Input User defined
SCK User defined Input
SS User defined Input171
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Note: 1. See “About code examples” on page 10.
Assembly code example (1)
SPI_MasterInit:
; Set MOSI and SCK output, all others input
ldi r17,(1<>8);
UBRRLn = (unsigned char)baud;
/* Enable receiver and transmitter */
UCSRnB = (1<> 1) & 0x01;
return ((resh << 8) | resl);
}188
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The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer.
This flag is one when unread data exist in the receive buffer, and zero when the receive
buffer is empty (that is, does not contain any unread data). If the Receiver is disabled (RXENn =
0), the receive buffer will be flushed and consequently the RXCn bit will become zero.
When the Receive Complete Interrupt Enable (RXCIEn) in UCSRnB is set, the USART Receive
Complete interrupt will be executed as long as the RXCn Flag is set (provided that global interrupts
are enabled). When interrupt-driven data reception is used, the receive complete routine
must read the received data from UDRn in order to clear the RXCn Flag, otherwise a new interrupt
will occur once the interrupt routine terminates.
19.6.4 Receiver error flags
The USART Receiver has three error flags: Frame Error (FEn), Data OverRun (DORn) and Parity
Error (UPEn). All can be accessed by reading UCSRnA. Common for the Error Flags is that
they are located in the receive buffer together with the frame for which they indicate the error
status. Due to the buffering of the Error Flags, the UCSRnA must be read before the receive buffer
(UDRn), since reading the UDRn I/O location changes the buffer read location. Another
equality for the Error Flags is that they can not be altered by software doing a write to the flag
location. However, all flags must be set to zero when the UCSRnA is written for upward compatibility
of future USART implementations. None of the Error Flags can generate interrupts.
The Frame Error (FEn) Flag indicates the state of the first stop bit of the next readable frame
stored in the receive buffer. The FEn Flag is zero when the stop bit was correctly read (as one),
and the FEn Flag will be one when the stop bit was incorrect (zero). This flag can be used for
detecting out-of-sync conditions, detecting break conditions and protocol handling. The FEn
Flag is not affected by the setting of the USBSn bit in UCSRnC since the Receiver ignores all,
except for the first, stop bits. For compatibility with future devices, always set this bit to zero
when writing to UCSRnA.
The Data OverRun (DORn) Flag indicates data loss due to a receiver buffer full condition. A
Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting
in the Receive Shift Register, and a new start bit is detected. If the DORn Flag is set there
was one or more serial frame lost between the frame last read from UDRn, and the next frame
read from UDRn. For compatibility with future devices, always write this bit to zero when writing
to UCSRnA. The DORn Flag is cleared when the frame received was successfully moved from
the Shift Register to the receive buffer.
The Parity Error (UPEn) Flag indicates that the next frame in the receive buffer had a Parity
Error when received. If Parity Check is not enabled the UPEn bit will always be read zero. For
compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more
details see “Parity bit calculation” on page 181 and “Parity Checker” on page 188.
19.6.5 Parity Checker
The Parity Checker is active when the high USART Parity mode (UPMn1) bit is set. Type of Parity
Check to be performed (odd or even) is selected by the UPMn0 bit. When enabled, the Parity
Checker calculates the parity of the data bits in incoming frames and compares the result with
the parity bit from the serial frame. The result of the check is stored in the receive buffer together
with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software
to check if the frame had a Parity Error.189
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The UPEn bit is set if the next character that can be read from the receive buffer had a Parity
Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is
valid until the receive buffer (UDRn) is read.
19.6.6 Disabling the Receiver
In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing
receptions will therefore be lost. When disabled (that is, the RXENn is set to zero) the Receiver
will no longer override the normal function of the RxDn port pin. The Receiver buffer FIFO will be
flushed when the Receiver is disabled. Remaining data in the buffer will be lost
19.6.7 Flushing the receive buffer
The receiver buffer FIFO will be flushed when the Receiver is disabled, that is, the buffer will be
emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal
operation, due to for instance an error condition, read the UDRn I/O location until the RXCn Flag
is cleared. The following code example shows how to flush the receive buffer.
Note: 1. See “About code examples” on page 10.
19.7 Asynchronous data reception
The USART includes a clock recovery and a data recovery unit for handling asynchronous data
reception. The clock recovery logic is used for synchronizing the internally generated baud rate
clock to the incoming asynchronous serial frames at the RxDn pin. The data recovery logic samples
and low pass filters each incoming bit, thereby improving the noise immunity of the
Receiver. The asynchronous reception operational range depends on the accuracy of the internal
baud rate clock, the rate of the incoming frames, and the frame size in number of bits.
19.7.1 Asynchronous clock recovery
The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 19-5
on page 190 illustrates the sampling process of the start bit of an incoming frame. The sample
rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double Speed
mode. The horizontal arrows illustrate the synchronization variation due to the sampling process.
Note the larger time variation when using the Double Speed mode (U2Xn = 1) of
operation. Samples denoted zero are samples done when the RxDn line is idle (that is, no communication
activity).
Assembly code example (1)
USART_Flush:
sbis UCSRnA, RXCn
ret
in r16, UDRn
rjmp USART_Flush
C code example (1)
void USART_Flush( void )
{
unsigned char dummy;
while ( UCSRnA & (1<
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