ATmega329/3290/649/6490 Datasheet - Farnell Element 14 - Revenir à l'accueil

 

 

Branding Farnell element14 (France)

 

Farnell Element 14 :

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Everything You Need To Know About Arduino

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Tutorial 01 for Arduino: Getting Acquainted with Arduino

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The Cube® 3D Printer

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What's easier- DIY Dentistry or our new our website features?

 

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Ben Heck's Getting Started with the BeagleBone Black Trailer

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Ben Heck's Home-Brew Solder Reflow Oven 2.0 Trailer

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Get Started with Pi Episode 3 - Online with Raspberry Pi

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Discover Simulink Promo -- Exclusive element14 Webinar

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Ben Heck's TV Proximity Sensor Trailer

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Ben Heck's PlayStation 4 Teardown Trailer

See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…

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Get Started with Pi Episode 4 - Your First Raspberry Pi Project

Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.

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Ben Heck Anti-Pickpocket Wallet Trailer

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Molex Earphones - The 14 Holiday Products of Newark element14 Promotion

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Tripp Lite Surge Protector - The 14 Holiday Products of Newark element14 Promotion

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Microchip ChipKIT Pi - The 14 Holiday Products of Newark element14 Promotion

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Beagle Bone Black - The 14 Holiday Products of Newark element14 Promotion

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3M E26, LED Lamps - The 14 Holiday Products of Newark element14 Promotion

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3M Colored Duct Tape - The 14 Holiday Products of Newark element14 Promotion

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Tenma Soldering Station - The 14 Holiday Products of Newark element14 Promotion

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Duratool Screwdriver Kit - The 14 Holiday Products of Newark element14 Promotion

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Cubify 3D Cube - The 14 Holiday Products of Newark element14 Promotion

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Bud Boardganizer - The 14 Holiday Products of Newark element14 Promotion

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Raspberry Pi Starter Kit - The 14 Holiday Products of Newark element14 Promotion

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Fluke 323 True-rms Clamp Meter - The 14 Holiday Products of Newark element14 Promotion

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Dymo RHINO 6000 Label Printer - The 14 Holiday Products of Newark element14 Promotion

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3M LED Advanced Lights A-19 - The 14 Holiday Products of Newark element14 Promotion

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Innovative LPS Resistor Features Very High Power Dissipation

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Charge Injection Evaluation Board for DG508B Multiplexer Demo

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Ben Heck The Great Glue Gun Trailer Part 2

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Introducing element14 TV

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Ben Heck Time to Meet Your Maker Trailer

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Détecteur de composants

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Recherche intégrée

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Ben Builds an Accessibility Guitar Trailer Part 1

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Ben Builds an Accessibility Guitar - Part 2 Trailer

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PiFace Control and Display Introduction

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Flashmob Farnell

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Express Yourself in 3D with Cube 3D Printers from Newark element14

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Farnell YouTube Channel Move

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Farnell: Design with the best

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French Farnell Quest

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Altera - 3 Ways to Quickly Adapt to Changing Ethernet Protocols

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Cy-Net3 Network Module

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MC AT - Professional and Precision Series Thin Film Chip Resistors

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Solderless LED Connector

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PSA-T Series Spectrum Analyser: PSA1301T/ PSA2701T

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3-axis Universal Motion Controller For Stepper Motor Drivers: TMC429

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Voltage Level Translation

Puce électronique / Microchip :

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Microchip - 8-bit Wireless Development Kit

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 2 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 3 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 1 of 3

Sans fil - Wireless :

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Microchip - 8-bit Wireless Development Kit

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Wireless Power Solutions - Wurth Electronics, Texas Instruments, CadSoft and element14

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Analog Devices - Remote Water Quality Monitoring via a Low Power, Wireless Network

Texas instrument :

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Texas Instruments - Automotive LED Headlights

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Texas Instruments - Digital Power Solutions

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Texas Instruments - Industrial Sensor Solutions

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Texas Instruments - Wireless Pen Input Demo (Mobile World Congress)

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Texas Instruments - Industrial Automation System Components

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Texas Instruments - TMS320C66x - Industry's first 10-GHz fixed/floating point DSP

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Texas Instruments - TMS320C66x KeyStone Multicore Architecture

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Texas Instruments - Industrial Interfaces

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Texas Instruments - Concerto™ MCUs - Connectivity without compromise

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Texas Instruments - Stellaris Robot Chronos

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Texas Instruments - DRV8412-C2-KIT, Brushed DC and Stepper Motor Control Kit

Ordinateurs :

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Ask Ben Heck - Connect Raspberry Pi to Car Computer

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Ben's Portable Raspberry Pi Computer Trailer

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Ben's Raspberry Pi Portable Computer Trailer 2

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Ben Heck's Pocket Computer Trailer

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Ask Ben Heck - Atari Computer

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Ask Ben Heck - Using Computer Monitors for External Displays

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Raspberry Pi Partnership with BBC Computer Literacy Project - Answers from co-founder Eben Upton

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Installing RaspBMC on your Raspberry Pi with the Farnell element14 Accessory kit

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Raspberry Pi Served - Joey Hudy

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Happy Birthday Raspberry Pi

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Raspberry Pi board B product overview

Logiciels :

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Ask Ben Heck - Best Opensource or Free CAD Software

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Tektronix FPGAView™ software makes debugging of FPGAs faster than ever!

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Ask Ben Heck - Best Open-Source Schematic Capture and PCB Layout Software

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Introduction to Cadsoft EAGLE PCB Design Software in Chinese

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Altera - Developing Software for Embedded Systems on FPGAs

Tutoriels :

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Ben Heck The Great Glue Gun Trailer Part 1

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the knode tutorial - element14

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Ben's Autodesk 123D Tutorial Trailer

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Ben's CadSoft EAGLE Tutorial Trailer

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Ben Heck's Soldering Tutorial Trailer

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Ben Heck's AVR Dev Board tutorial

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Ben Heck's Pinball Tutorial Trailer

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Ben Heck's Interface Tutorial Trailer

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First Stage with Python and PiFace Digital

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Cypress - Getting Started with PSoC® 3 - Part 2

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Energy Harvesting Challenge

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New Features of CadSoft EAGLE v6

Autres documentations :

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Features • High Performance, Low Power Atmel®AVR® 8-Bit Microcontroller • Advanced RISC Architecture – 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16MHz – On-Chip 2-cycle Multiplier • High Endurance Non-volatile Memory Segments – In-System Self-programmable Flash Program Memory • 32KBytes (ATmega329/ATmega3290) • 64KBytes (ATmega649/ATmega6490) – EEPROM • 1Kbytes (ATmega329/ATmega3290) • 2Kbytes (ATmega649/ATmega6490) – Internal SRAM • 2Kbytes (ATmega329/ATmega3290) • 4Kbytes (ATmega649/ATmega6490) – Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C(1) – Optional Boot Code Section with Independent Lock Bits • In-System Programming by On-chip Boot Program • True Read-While-Write Operation – Programming Lock for Software Security • JTAG (IEEE std. 1149.1 compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface • Peripheral Features – 4 x 25 Segment LCD Driver (ATmega329/ATmega649) – 4 x 40 Segment LCD Driver (ATmega3290/ATmega6490) – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Four PWM Channels – 8-channel, 10-bit ADC – Programmable Serial USART – Master/Slave SPI Serial Interface – Universal Serial Interface with Start Condition Detector – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change • Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources – Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby • I/O and Packages – 53/68 Programmable I/O Lines – 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP • Speed Grade: – ATmega329V/ATmega3290V/ATmega649V/ATmega6490V: – 0 - 4MHz @ 1.8 - 5.5V, 0 - 8MHz @ 2.7 - 5.5V – ATmega329/3290/649/6490: – 0 - 8MHz @ 2.7 - 5.5V, 0 - 16MHz @ 4.5 - 5.5V • Temperature range: – -40°C to 85°C Industrial • Ultra-Low Power Consumption – Active Mode: • 1MHz, 1.8V: 350µA • 32kHz, 1.8V: 20µA (including Oscillator) • 32kHz, 1.8V: 40µA (including Oscillator and LCD) – Power-down Mode: • 100nA at 1.8V 8-bit Atmel Microcontroller with In-System Programmable Flash ATmega329/V ATmega3290/V ATmega649/V ATmega6490/V 2552K–AVR–04/112 2552K–AVR–04/11 ATmega329/3290/649/6490 1. Pin Configurations Figure 1-1. Pinout ATmega3290/6490 (OC2A/PCINT15) PB7 DNC (T1/SEG33) PG3 (T0/SEG32) PG4 RESET/PG5 VCC GND (TOSC2) XTAL2 (TOSC1) XTAL1 DNC DNC (PCINT26/SEG31) PJ2 (PCINT27/SEG30) PJ3 (PCINT28/SEG29) PJ4 (PCINT29/SEG28) PJ5 (PCINT30/SEG27) PJ6 DNC (ICP1/SEG26) PD0 (INT0/SEG25) PD1 (SEG24) PD2 (SEG23) PD3 (SEG22) PD4 (SEG21) PD5 (SEG20) PD6 (SEG19) PD7 AVCC AGND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) DNC DNC PH7 (PCINT23/SEG36) PH6 (PCINT22/SEG37) PH5 (PCINT21/SEG38) PH4 (PCINT20/SEG39) DNC DNC GND VCC DNC PA0 (COM0) PA1 (COM1) PA2 (COM2) PA3 (COM3) PA4 (SEG0) PA5 (SEG1) PA6 (SEG2) PA7 (SEG3) PG2 (SEG4) PC7 (SEG5) PC6 (SEG6) DNC PH3 (PCINT19/SEG7) PH2 (PCINT18/SEG8) PH1 (PCINT17/SEG9) PH0 (PCINT16/SEG10) DNC DNC DNC DNC PC5 (SEG11) PC4 (SEG12) PC3 (SEG13) PC2 (SEG14) PC1 (SEG15) PC0 (SEG16) PG1 (SEG17) PG0 (SEG18) INDEX CORNER ATmega3290/6490 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 LCDCAP (RXD/PCINT0) PE0 (TXD/PCINT1) PE1 (XCK/AIN0/PCINT2) PE2 (AIN1/PCINT3) PE3 (USCK/SCL/PCINT4) PE4 (DI/SDA/PCINT5) PE5 (DO/PCINT6) PE6 (CLKO/PCINT7) PE7 VCC GND DNC (PCINT24/SEG35) PJ0 (PCINT25/SEG34) PJ1 DNC DNC DNC DNC (SS/PCINT8) PB0 (SCK/PCINT9) PB1 (MOSI/PCINT10) PB2 (MISO/PCINT11) PB3 (OC0A/PCINT12) PB4 (OC1A/PCINT13) PB5 (OC1B/PCINT14) PB6 TQFP3 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 1-2. Pinout ATmega329/649 Note: The large center pad underneath the QFN/MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board. PC0 (SEG12) VCC A GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC 17 61 60 18 59 20 58 19 21 57 22 56 23 55 24 54 25 53 26 52 27 51 28 29 50 49 30 31 32 (RXD/PCINT0) PE0 (TXD/PCINT1) PE1 LCDCAP (XCK/AIN0/PCINT2) PE2 (AIN1/PCINT3) PE3 (USCK/SCL/PCINT4) PE4 (DI/SDA/PCINT5) PE5 (DO/PCINT6) PE6 (CLKO/PCINT7) PE7 (SCK/PCINT9) PB1 (MOSI/PCINT10) PB2 (MISO/PCINT11) PB3 (OC0A/PCINT12) PB4 (OC2A/PCINT15) PB7 (T1/SEG24) PG3 (OC1B/PCINT14) PB6 (T0/SEG23) PG4 (OC1A/PCINT13) PB5 PC1 (SEG11) PG0 (SEG14) (SEG15) PD7 PC2 (SEG10) PC3 (SEG9) PC4 (SEG8) PC5 (SEG7) PC6 (SEG6) PC7 (SEG5) PA7 (SEG3) PG2 (SEG4) PA6 (SEG2) PA5 (SEG1) PA4 (SEG0) PA3 (COM3) PA0 (COM0) PA1 (COM1) PA2 (COM2) PG1 (SEG13) (SEG19) PD3 (SEG18) PD4 (SEG17) PD5 (SEG16) PD6 (SEG20) PD2 (ICP1/SEG22) PD0 (INT0/SEG21) PD1 (TOSC2) XTAL2 (TOSC1) XTAL1 RESET/PG5 V GND CC INDEX CORNER (SS/PCINT8) PB0 2 3 1 4 5 6 7 8 9 10 11 12 13 14 16 15 64 63 62 47 46 48 45 44 43 42 41 40 39 38 37 36 35 33 34 ATmega329/6494 2552K–AVR–04/11 ATmega329/3290/649/6490 2. Overview The ATmega329/3290/649/6490 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega329/3290/649/6490 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram PROGRAM COUNTER INTERNAL OSCILLATOR WATCHDOG TIMER STACK POINTER PROGRAM FLASH MCU CONTROL REGISTER SRAM GENERAL PURPOSE REGISTERS INSTRUCTION REGISTER TIMER/ COUNTERS INSTRUCTION DECODER DATA DIR. REG. PORTB DATA DIR. REG. PORTE DATA DIR. REG. PORTA DATA DIR. REG. PORTD DATA REGISTER PORTB DATA REGISTER PORTE DATA REGISTER PORTA DATA REGISTER PORTD TIMING AND CONTROL OSCILLATOR INTERRUPT UNIT EEPROM USART SPI STATUS REGISTER Z Y X ALU PORTE DRIVERS PORTB DRIVERS PORTF DRIVERS PORTA DRIVERS PORTD DRIVERS PORTC DRIVERS PE0 - PE7 PB0 - PB7 PF0 - PF7 PA0 - PA7 GND VCC XTAL1 XTAL2 CONTROL LINES + - ANALOG COMPARATOR PC0 - PC7 8-BIT DATA BUS RESET CALIB. OSC DATA DIR. REG. PORTC DATA REGISTER PORTC ON-CHIP DEBUG JTAG TAP PROGRAMMING LOGIC BOUNDARYSCAN DATA DIR. REG. PORTF DATA REGISTER PORTF ADC PD0 - PD7 DATA DIR. REG. PORTG DATA REG. PORTG PORTG DRIVERS PG0 - PG4 AGND AREF AVCC UNIVERSAL SERIAL INTERFACE AVR CPU LCD CONTROLLER/ DRIVER PORTH DRIVERS PH0 - PH7 DATA DIR. REG. PORTH DATA REGISTER PORTH PORTJ DRIVERS PJ0 - PJ6 DATA DIR. REG. PORTJ DATA REGISTER PORTJ5 2552K–AVR–04/11 ATmega329/3290/649/6490 The Atmel® AVR® core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The Atmel ATmega329/3290/649/6490 provides the following features: 32/64K bytes of In-System Programmable Flash with Read-While-Write capabilities, 1/2K bytes EEPROM, 2/4K byte SRAM, 54/69 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, a complete On-chip LCD controller with internal contrast control, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer and the LCD controller continues to run, allowing the user to maintain a timer base and operate the LCD display while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer, LCD controller and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip In-System re-Programmable (ISP) Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega329/3290/649/6490 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The Atmel ATmega329/3290/649/6490 is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.6 2552K–AVR–04/11 ATmega329/3290/649/6490 2.2 Comparison between ATmega329, ATmega3290, ATmega649 and ATmega6490 The ATmega329, ATmega3290, ATmega649, and ATmega6490 differs only in memory sizes, pin count and pinout. Table 2-1 on page 6 summarizes the different configurations for the four devices. 2.3 Pin Descriptions The following section describes the I/O-pin special functions. 2.3.1 VCC Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega329/3290/649/6490 as listed on page 67. 2.3.4 Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B has better driving capabilities than the other ports. Port B also serves the functions of various special features of the ATmega329/3290/649/6490 as listed on page 68. Table 2-1. Configuration Summary Device Flash EEPROM RAM LCD Segments General Purpose I/O Pins ATmega329 32Kbytes 1Kbytes 2Kbytes 4 x 25 54 ATmega3290 32Kbytes 1K bytes 2Kbytes 4 x 40 69 ATmega649 64Kbytes 2Kbytes 4Kbytes 4 x 25 54 ATmega6490 64Kbytes 2Kbytes 4Kbytes 4 x 40 697 2552K–AVR–04/11 ATmega329/3290/649/6490 2.3.5 Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega329/3290/649/6490 as listed on page 71. 2.3.6 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega329/3290/649/6490 as listed on page 73. 2.3.7 Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega329/3290/649/6490 as listed on page 75. 2.3.8 Port F (PF7..PF0) Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs. Port F also serves the functions of the JTAG interface.8 2552K–AVR–04/11 ATmega329/3290/649/6490 2.3.9 Port G (PG5..PG0) Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features of the ATmega329/3290/649/6490 as listed on page 75. 2.3.10 Port H (PH7..PH0) Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up resistors are activated. The Port H pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port H also serves the functions of various special features of the ATmega3290/6490 as listed on page 75. 2.3.11 Port J (PJ6..PJ0) Port J is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port J output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port J also serves the functions of various special features of the ATmega3290/6490 as listed on page 75. 2.3.12 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in “System and Reset Characteristics” on page 330. Shorter pulses are not guaranteed to generate a reset. 2.3.13 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 2.3.14 XTAL2 Output from the inverting Oscillator amplifier. 2.3.15 AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 2.3.16 AREF This is the analog reference pin for the A/D Converter.9 2552K–AVR–04/11 ATmega329/3290/649/6490 2.3.17 LCDCAP An external capacitor (typical > 470nF) must be connected to the LCDCAP pin as shown in Figure 23-2. This capacitor acts as a reservoir for LCD power (VLCD). A large capacitance reduces ripple on VLCD but increases the time until VLCD reaches its target value. 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 1. 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 5. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.10 2552K–AVR–04/11 ATmega329/3290/649/6490 6. AVR CPU Core 6.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 6.2 Architectural Overview Figure 6-1. Block Diagram of the AVR Architecture In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. Flash Program Memory Instruction Register Instruction Decoder Program Counter Control Lines 32 x 8 General Purpose Registrers ALU Status and Control I/O Lines EEPROM Data Bus 8-bit Data SRAM Direct Addressing Indirect Addressing Interrupt Unit SPI Unit Watchdog Timer Analog Comparator I/O Module 2 I/O Module1 I/O Module n11 2552K–AVR–04/11 ATmega329/3290/649/6490 The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega329/3290/649/6490 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. 6.3 ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.12 2552K–AVR–04/11 ATmega329/3290/649/6490 6.4 AVR Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 6.4.1 SREG – AVR Status Register The AVR Status Register – SREG – is defined as: • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. • Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information. • Bit 4 – S: Sign Bit, S = N ⊕ V The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information. • Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. Bit 7 6 5 4 3 2 1 0 0x3F (0x5F) I T H S V N Z C SREG Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 013 2552K–AVR–04/11 ATmega329/3290/649/6490 • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 6.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 6-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 6-2. AVR CPU General Purpose Working Registers Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 6-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 … R13 0x0D General R14 0x0E Purpose R15 0x0F Working R16 0x10 Registers R17 0x11 … R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte14 2552K–AVR–04/11 ATmega329/3290/649/6490 6.5.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 6-3. Figure 6-3. The X-, Y-, and Z-registers In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 6.6 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. 15 XH XL 0 X-register 7 07 0 R27 (0x1B) R26 (0x1A) 15 YH YL 0 Y-register 7 07 0 R29 (0x1D) R28 (0x1C) 15 ZH ZL 0 Z-register 70 7 0 R31 (0x1F) R30 (0x1E) Bit 15 14 13 12 11 10 9 8 0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 76543210 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0000000015 2552K–AVR–04/11 ATmega329/3290/649/6490 6.7 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 6-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 6-4. The Parallel Instruction Fetches and Instruction Executions Figure 6-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 6-5. Single Cycle ALU Operation 6.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Programming” on page 293 for details. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 49. The list also determines the priority levels of the different interrupts. The lower the address the higher is the clk 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch T1 T2 T3 T4 CPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back T1 T2 T3 T4 clkCPU16 2552K–AVR–04/11 ATmega329/3290/649/6490 priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 49 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 278. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMWE ; start EEPROM write sbi EECR, EEWE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1< xxx ; .org 0x3802/0x7802 0x3804/0x7804 jmp EXT_INT0 ; IRQ0 Handler 0x3806/0x7806 jmp PCINT0 ; PCINT0 Handler ... ... ... ; 0x1C2C jmp SPM_RDY ; Store Program Memory Ready Handler When the BOOTRST Fuse is programmed and the Boot section size set to 4K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments .org 0x0002 0x0002 jmp EXT_INT0 ; IRQ0 Handler 0x002 2 jmp USI_OVF ; USI Overflow Handler 0x002 4 jmp ANA_COMP ; Analog Comparator Handler 0x002 6 jmp ADC ; ADC Conversion Complete Handler 0x002 8 jmp EE_RDY ; EEPROM Ready Handler 0x002 A jmp SPM_RDY ; SPM Ready Handler 0x002 C jmp LCD_SOF ; LCD Start of Frame Handler 0x002 E jmp PCINT2 ; PCINT2 Handler 0x003 0 jmp PCINT3 ; PCINT3 Handler ; 0x003 2 RESET : ldi r16, high(RAMEND) ; Main program start 0x003 3 out SPH,r16 ; Set Stack Pointer to top of RAM 0x003 4 ldi r16, low(RAMEND) 0x003 5 out SPL,r16 0x003 6 sei ; Enable interrupts 0x003 7 xxx ... ... ...52 2552K–AVR–04/11 ATmega329/3290/649/6490 0x0004 jmp PCINT0 ; PCINT0 Handler ... ... ... ; 0x002C jmp SPM_RDY ; Store Program Memory Ready Handler ; .org 0x3800/0x7800 0x3800/0x7801RESET:ldir16,high(RAMEND); Main program start 0x3801/0x7801 out SPH,r16 ; Set Stack Pointer to top of RAM 0x3802/0x7802 ldi r16,low(RAMEND) 0x3803/0x7803 out SPL,r16 0x3804/0x7804 sei ; Enable interrupts 0x3805/0x7805 xxx When the BOOTRST Fuse is programmed, the Boot section size set to 4K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments ; .org 0x3800/0x7800 0x3800/0x7800 jmp RESET ; Reset handler 0x3802/0x7802 jmp EXT_INT0 ; IRQ0 Handler 0x3804/0x7804 jmp PCINT0 ; PCINT0 Handler ... ... ... ; 0x382C/0x782C jmp SPM_RDY ; Store Program Memory Ready Handler ; 0x382E/0x782ERESET:ldir16,high(RAMEND); Main program start 0x382F/0x782F out SPH,r16 ; Set Stack Pointer to top of RAM 0x3830/0x7830 ldi r16,low(RAMEND) 0x3831/0x7831 out SPL,r16 0x3832/0x7832 sei ; Enable interrupts 0x3833/0x7833 xxx 11.1.1 Moving Interrupts Between Application and Boot Space The MCU Control Register controls the placement of the Interrupt Vector table. 11.2 Register Description 11.2.1 MCUCR – MCU Control Register • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the Boot Flash Section is determined by the BOOTSZ Fuses. Refer to the section “Boot Loader Support – Read-While-Write Bit 7 6 5 4 3 2 1 0 0x35 (0x55) JTD – – PUD – – IVSEL IVCE MCUCR Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 053 2552K–AVR–04/11 ATmega329/3290/649/6490 Self-Programming” on page 278 for details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit: 1. Write the Interrupt Vector Change Enable (IVCE) bit to one. 2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling. Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section “Boot Loader Support – Read-WhileWrite Self-Programming” on page 278 for details on Boot Lock bits. • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below. Assembly Code Example Move_interrupts: ;Get MCUCR in r16, MCUCR mov r17, r16 ; Enable change of Interrupt Vectors ori r16, (1< CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is connected to. 15.0.3 External Clock Source An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock (clkT1/clkT0). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 15-1 shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the internal system clock. The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects. Figure 15-1. T1/T0 Pin Sampling The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated. Tn_sync (To Clock Select Logic) Synchronization Edge Detector D Q D Q LE Tn D Q clkI/O108 2552K–AVR–04/11 ATmega329/3290/649/6490 Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 15-2. Prescaler for Timer/Counter0 and Timer/Counter1(1) Note: 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 15-1. 15.1 Register Description 15.1.1 GTCCR – General Timer/Counter Control Register • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting simultaneously. • Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0 PSR10 Clear clkT1 clkT0 T1 T0 clkI/O Synchronization Synchronization Bit 7 6 5 4 3 2 1 0 0x23 (0x43) TSM – – – – – PSR2 PSR10 GTCCR Read/Write R/W R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0109 2552K–AVR–04/11 ATmega329/3290/649/6490 When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers.110 2552K–AVR–04/11 ATmega329/3290/649/6490 16. 16-bit Timer/Counter1 16.1 Features The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e., Allows 16-bit PWM) • Two independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceler • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Variable PWM Period • Frequency Generator • External Event Counter • Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1) 16.2 Overview Most register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on. A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 16-1. For the actual placement of I/O pins, refer to “Pinout ATmega3290/6490” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “Register Description” on page 132. The PRTIM1 bit in “Power Reduction Register” on page 37 must be written to zero to enable the Timer/Counter1 module.111 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 16-1. 16-bit Timer/Counter Block Diagram(1) Note: 1. Refer to Figure 1-1 on page 2, Table 13-5 on page 68, and Table 13-11 on page 72 for Timer/Counter1 pin placement and description. 16.2.1 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are described in the section “Accessing 16-bit Registers” on page 113. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR1). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK1). TIFR1 and TIMSK1 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T1 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT1). The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter value at all time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC1A/B). See “OutClock Select Timer/Counter DATA BUS OCRnA OCRnB ICRn = = TCNTn Waveform Generation Waveform Generation OCnA OCnB Noise Canceler ICPn = Fixed TOP Values Edge Detector Control Logic = 0 TOP BOTTOM Count Clear Direction TOVn (Int.Req.) OCnA (Int.Req.) OCnB (Int.Req.) ICFn (Int.Req.) TCCRnA TCCRnB ( From Analog Comparator Ouput ) Tn Edge Detector ( From Prescaler ) clkTn112 2552K–AVR–04/11 ATmega329/3290/649/6490 put Compare Units” on page 119.. The compare match event will also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICP1) or on the Analog Comparator pins (See “Analog Comparator” on page 207.) The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCR1A Register, the ICR1 Register, or by a set of fixed values. When using OCR1A as TOP value in a PWM mode, the OCR1A Register can not be used for generating a PWM output. However, the TOP value will in this case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP value is required, the ICR1 Register can be used as an alternative, freeing the OCR1A to be used as PWM output. 16.2.2 Definitions The following definitions are used extensively throughout the section: 16.2.3 Compatibility The 16-bit Timer/Counter has been updated and improved from previous versions of the 16-bit AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier version regarding: • All 16-bit Timer/Counter related I/O Register address locations, including Timer Interrupt Registers. • Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers. • Interrupt Vectors. The following control bits have changed name, but have same functionality and register location: • PWM10 is changed to WGM10. • PWM11 is changed to WGM11. • CTC1 is changed to WGM12. The following bits are added to the 16-bit Timer/Counter Control Registers: • FOC1A and FOC1B are added to TCCR1C. • WGM13 is added to TCCR1B. The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. Table 16-1. Definitions of Timer/Counter values. BOTTOM The counter reaches the BOTTOM when it becomes 0x0000. MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCR1A or ICR1 Register. The assignment is dependent of the mode of operation.113 2552K–AVR–04/11 ATmega329/3290/649/6490 16.3 Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a 16-bit register is written by the CPU, the high byte stored in the temporary register, and the low byte written are both copied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read. Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR1A/B 16- bit registers does not involve using the temporary register. To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte. The following code examples show how to access the 16-bit Timer Registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCR1A/B and ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit access. Note: 1. See “About Code Examples” on page 9. The assembly code example returns the TCNT1 value in the r17:r16 register pair. It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit Timer Registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both Assembly Code Examples(1) ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ... C Code Examples(1) unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into i */ i = TCNT1; ...114 2552K–AVR–04/11 ATmega329/3290/649/6490 the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Note: 1. See “About Code Examples” on page 9. The assembly code example returns the TCNT1 value in the r17:r16 register pair. Assembly Code Example(1) TIM16_ReadTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ; Restore global interrupt flag out SREG,r18 ret C Code Example(1) unsigned int TIM16_ReadTCNT1( void ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Read TCNT1 into i */ i = TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; }115 2552K–AVR–04/11 ATmega329/3290/649/6490 The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Note: 1. See “About Code Examples” on page 9. The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNT1. 16.3.1 Reusing the Temporary High Byte Register If writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. Assembly Code Example(1) TIM16_WriteTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Set TCNT1 to r17:r16 out TCNT1H,r17 out TCNT1L,r16 ; Restore global interrupt flag out SREG,r18 ret C Code Example(1) void TIM16_WriteTCNT1( unsigned int i ) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Set TCNT1 to i */ TCNT1 = i; /* Restore global interrupt flag */ SREG = sreg; }116 2552K–AVR–04/11 ATmega329/3290/649/6490 16.4 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits located in the Timer/Counter control Register B (TCCR1B). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 107. 16.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 16-2 shows a block diagram of the counter and its surroundings. Figure 16-2. Counter Unit Block Diagram Signal description (internal signals): Count Increment or decrement TCNT1 by 1. Direction Select between increment and decrement. Clear Clear TCNT1 (set all bits to zero). clkT1 Timer/Counter clock. TOP Signalize that TCNT1 has reached maximum value. BOTTOM Signalize that TCNT1 has reached minimum value (zero). The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) containing the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU does an access to the TCNT1H I/O location, the CPU accesses the high byte temporary register (TEMP). The temporary register is updated with the TCNT1H value when the TCNT1L is read, and TCNT1H is updated with the temporary register value when TCNT1L is written. This allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is important to notice that there are special cases of writing to the TCNT1 Register when the counter is counting that will give unpredictable results. The special cases are described in the sections where they are of importance. Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT1). The clkT1 can be generated from an external or internal clock source, selected by the Clock Select bits (CS12:0). When no clock source is selected (CS12:0 = 0) the timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of TEMP (8-bit) DATA BUS (8-bit) TCNTn (16-bit Counter) TCNTnH (8-bit) TCNTnL (8-bit) Control Logic Count Clear Direction TOVn (Int.Req.) Clock Select TOP BOTTOM Tn Edge Detector ( From Prescaler ) clkTn117 2552K–AVR–04/11 ATmega329/3290/649/6490 whether clkT1 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the Waveform Generation mode bits (WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC1x. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 123. The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 16.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP1 pin or alternatively, via the analog-comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events. The Input Capture unit is illustrated by the block diagram shown in Figure 16-3. The elements of the block diagram that are not directly a part of the Input Capture unit are gray shaded. The small “n” in register and bit names indicates the Timer/Counter number. Figure 16-3. Input Capture Unit Block Diagram When a change of the logic level (an event) occurs on the Input Capture pin (ICP1), alternatively on the Analog Comparator output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter (TCNT1) is written to the Input Capture Register (ICR1). The Input Capture Flag (ICF1) is set at the same system clock as the TCNT1 value is copied into ICR1 Register. If enabled (ICIE1 = 1), the Input Capture Flag generates an Input Capture interrupt. The ICF1 Flag is automatically ICFn (Int.Req.) Analog Comparator WRITE ICRn (16-bit Register) ICRnH (8-bit) Noise Canceler ICPn Edge Detector TEMP (8-bit) DATA BUS (8-bit) ICRnL (8-bit) TCNTn (16-bit Counter) TCNTnH (8-bit) TCNTnL (8-bit) ACO* ACIC* ICNC ICES118 2552K–AVR–04/11 ATmega329/3290/649/6490 cleared when the interrupt is executed. Alternatively the ICF1 Flag can be cleared by software by writing a logical one to its I/O bit location. Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the low byte (ICR1L) and then the high byte (ICR1H). When the low byte is read the high byte is copied into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP Register. The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Generation mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is written to ICR1L. For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 113. 16.6.1 Input Capture Trigger Source The main trigger source for the Input Capture unit is the Input Capture pin (ICP1). Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change. Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled using the same technique as for the T1 pin (Figure 15-1 on page 107). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. Note that the input of the noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform Generation mode that uses ICR1 to define TOP. An Input Capture can be triggered by software by controlling the port of the ICP1 pin. 16.6.2 Noise Canceler The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in Timer/Counter Control Register B (TCCR1B). When enabled the noise canceler introduces additional four system clock cycles of delay from a change applied to the input, to the update of the ICR1 Register. The noise canceler uses the system clock and is therefore not affected by the prescaler. 16.6.3 Using the Input Capture Unit The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the incoming events. The time between two events is critical. If the processor has not read the captured value in the ICR1 Register before the next event occurs, the ICR1 will be overwritten with a new value. In this case the result of the capture will be incorrect. When using the Input Capture interrupt, the ICR1 Register should be read as early in the interrupt handler routine as possible. Even though the Input Capture interrupt has relatively high119 2552K–AVR–04/11 ATmega329/3290/649/6490 priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICR1 Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). 16.7 Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF1x Flag is automatically cleared when the interrupt is executed. Alternatively the OCF1x Flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the Waveform Generation mode (WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP and BOTTOM signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (See “Modes of Operation” on page 123.) A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the Waveform Generator. Figure 16-4 shows a block diagram of the Output Compare unit. The small “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded.120 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 16-4. Output Compare Unit, Block Diagram The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR1x Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x directly. The content of the OCR1x (Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the high byte temporary register (TEMP). However, it is a good practice to read the low byte first as when accessing other 16-bit registers. Writing the OCR1x Registers must be done via the TEMP Register since the compare of all 16 bits is done continuously. The high byte (OCR1xH) has to be written first. When the high byte I/O location is written by the CPU, the TEMP Register will be updated by the value written. Then when the low byte (OCR1xL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare Register in the same system clock cycle. For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 113. 16.7.1 Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC1x) bit. Forcing compare match will not set the OCF1x Flag or reload/clear the timer, but the OC1x pin will be updated as if a real compare match had occurred (the COM11:0 bits settings define whether the OC1x pin is set, cleared or toggled). OCFnx (Int.Req.) = (16-bit Comparator ) OCRnx Buffer (16-bit Register) OCRnxH Buf. (8-bit) OCnx TEMP (8-bit) DATA BUS (8-bit) OCRnxL Buf. (8-bit) TCNTn (16-bit Counter) TCNTnH (8-bit) TCNTnL (8-bit) WGMn3:0 COMnx1:0 OCRnx (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) Waveform Generator TOP BOTTOM121 2552K–AVR–04/11 ATmega329/3290/649/6490 16.7.2 Compare Match Blocking by TCNT1 Write All CPU writes to the TCNT1 Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled. 16.7.3 Using the Output Compare Unit Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT1 when using any of the Output Compare units, independent of whether the Timer/Counter is running or not. If the value written to TCNT1 equals the OCR1x value, the compare match will be missed, resulting in incorrect waveform generation. Do not write the TCNT1 equal to TOP in PWM modes with variable TOP values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF. Similarly, do not write the TCNT1 value equal to BOTTOM when the counter is counting down. The setup of the OC1x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC1x value is to use the Force Output Compare (FOC1x) strobe bits in Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately.122 2552K–AVR–04/11 ATmega329/3290/649/6490 16.8 Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 16-5 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to the OC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a system reset occur, the OC1x Register is reset to “0”. Figure 16-5. Compare Match Output Unit, Schematic The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform Generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x value is visible on the pin. The port override function is generally independent of the Waveform Generation mode, but there are some exceptions. Refer to Table 16-2, Table 16-3 and Table 16-4 for details. The design of the Output Compare pin logic allows initialization of the OC1x state before the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation. See “Register Description” on page 132. The COM1x1:0 bits have no effect on the Input Capture unit. PORT DDR D Q D Q OCnx OCnx Pin D Q Waveform Generator COMnx1 COMnx0 0 1 DATA BUS FOCnx clkI/O123 2552K–AVR–04/11 ATmega329/3290/649/6490 16.8.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no action on the OC1x Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 16-2 on page 132. For fast PWM mode refer to Table 16-3 on page 133, and for phase correct and phase and frequency correct PWM refer to Table 16-4 on page 133. A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits. 16.9 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Output mode (COM1x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM1x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM1x1:0 bits control whether the output should be set, cleared or toggle at a compare match (See “Compare Match Output Unit” on page 122.) For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 130. 16.9.1 Normal Mode The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOV1) will be set in the same timer clock cycle as the TCNT1 becomes zero. The TOV1 Flag in this case behaves like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV1 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the external events must not exceed the resolution of the counter. If the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 16.9.2 Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Register are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for the counter, hence also its resolution. This124 2552K–AVR–04/11 ATmega329/3290/649/6490 mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 16-6. The counter value (TCNT1) increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. Figure 16-6. CTC Mode, Timing Diagram An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR1A or ICR1 is lower than the current value of TCNT1, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode using OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double buffered. For generating a waveform output in CTC mode, the OC1A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM1A1:0 = 1). The OC1A value will not be visible on the port pin unless the data direction for the pin is set to output (DDR_OC1A = 1). The waveform generated will have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). The waveform frequency is defined by the following equation: The N variable represents the prescaler factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV1 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000. 16.9.3 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x, and set at BOTTOM. In inverting Compare TCNTn OCnA (Toggle) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) Period 1 2 3 4 (COMnA1:0 = 1) f OCnA f clk_I/O 2 ⋅ ⋅ N ( ) 1 + OCRnA = --------------------------------------------------125 2552K–AVR–04/11 ATmega329/3290/649/6490 Output mode output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 = 14), or the value in OCR1A (WGM13:0 = 15). The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 16-7. The figure shows fast PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. Figure 16-7. Fast PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition the OC1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A or ICR1 is used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and compare values. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values the unused bits are masked to zero when any of the OCR1x Registers are written. RFPWM log( ) TOP + 1 log( ) 2 = ----------------------------------- TCNTn OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) Period 1 2 3 4 5 6 7 8 OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3)126 2552K–AVR–04/11 ATmega329/3290/649/6490 The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value. The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new ICR1 value written is lower than the current value of TCNT1. The result will then be that the counter will miss the compare match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location to be written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set. Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed (by changing the TOP value), using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to three (see Table 16-3 on page 133). The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the compare match between OCR1x and TCNT1, and clearing (or setting) the OC1x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR1x is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR1x equal to TOP will result in a constant high or low output (depending on the polarity of the output set by the COM1x1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC1A to toggle its logical level on each compare match (COM1A1:0 = 1). This applies only if OCR1A is used to define the TOP value (WGM13:0 = 15). The waveform generated will have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). This feature is similar to the OC1A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 16.9.4 Phase Correct PWM Mode The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dualslope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x while counting up, and set on the compare match while counting down. In inverting Output Compare mode, the operation is f OCnxPWM f clk_I/O N ⋅ ( ) 1 + TOP = -----------------------------------127 2552K–AVR–04/11 ATmega329/3290/649/6490 inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 16-8. The figure shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. Figure 16-8. Phase Correct PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accordingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. RPCPWM log( ) TOP + 1 log( ) 2 = ----------------------------------- OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) 1 2 3 4 TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn Period OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3)128 2552K–AVR–04/11 ATmega329/3290/649/6490 Note that when using fixed TOP values, the unused bits are masked to zero when any of the OCR1x Registers are written. As the third period shown in Figure 16-8 illustrates, changing the TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Register. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output. It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically no differences between the two modes of operation. In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to three (See Table 1 on page 133). The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the compare match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at compare match between OCR1x and TCNT1 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle. 16.9.5 Phase and Frequency Correct PWM Mode The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation option. The phase and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x while counting up, and set on the compare match while counting down. In inverting Compare Output mode, the operation is inverted. The dual-slope operation gives a lower maximum operation frequency compared to the single-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the OCR1x Register is updated by the OCR1x Buffer Register, (see Figure 16- 8 and Figure 16-9). f OCnxPCPWM f clk_I/O 2 ⋅ ⋅ N TOP = ----------------------------129 2552K–AVR–04/11 ATmega329/3290/649/6490 The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown on Figure 16-9. The figure shows phase and frequency correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes noninverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. Figure 16-9. Phase and Frequency Correct PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag set when TCNT1 has reached TOP. The Interrupt Flags can then be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x. As Figure 16-9 shows the output generated is, in contrast to the phase correct mode, symmetrical in all periods. Since the OCR1x Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct. RPFCPWM log( ) TOP + 1 log( ) 2 = ----------------------------------- OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) 1 2 3 4 TCNTn Period OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3)130 2552K–AVR–04/11 ATmega329/3290/649/6490 Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to three (See Table 1 on page 133). The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the compare match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at compare match between OCR1x and TCNT1 when the counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for noninverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle. 16.10 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double buffering). Figure 16-10 shows a timing diagram for the setting of OCF1x. Figure 16-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling Figure 16-11 shows the same timing data, but with the prescaler enabled. f OCnxPFCPWM f clk_I/O 2 ⋅ ⋅ N TOP = ---------------------------- clkTn (clkI/O/1) OCFnx clkI/O OCRnx TCNTn OCRnx Value OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2131 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 16-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8) Figure 16-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM. Figure 16-12. Timer/Counter Timing Diagram, no Prescaling Figure 16-13 shows the same timing data, but with the prescaler enabled. OCFnx OCRnx TCNTn OCRnx Value OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 clkI/O clkTn (clkI/O/8) TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 Old OCRnx Value New OCRnx Value TOP - 1 TOP BOTTOM BOTTOM + 1 clkTn (clkI/O/1) clkI/O132 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 16-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) 16.11 Register Description 16.11.1 TCCR1A – Timer/Counter1 Control Register A • Bit 7:6 – COM1A1:0: Compare Output Mode for Unit A • Bit 5:4 – COM1B1:0: Compare Output Mode for Unit B The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respectively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC1A or OC1B pin must be set in order to enable the output driver. When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is dependent of the WGM13:0 bits setting. Table 16-2 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to a Normal or a CTC mode (non-PWM). TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 Old OCRnx Value New OCRnx Value TOP - 1 TOP BOTTOM BOTTOM + 1 clkI/O clkTn (clkI/O/8) Bit 7 6 5 4 3 2 1 0 (0x80) COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 TCCR1A Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 16-2. Compare Output Mode, non-PWM COM1A1/COM1B1 COM1A0/COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 Toggle OC1A/OC1B on Compare Match. 1 0 Clear OC1A/OC1B on Compare Match (Set output to low level). 1 1 Set OC1A/OC1B on Compare Match (Set output to high level).133 2552K–AVR–04/11 ATmega329/3290/649/6490 Table 16-3 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the compare match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 124. for more details. Table 16-4 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See “Phase Correct PWM Mode” on page 126. for more details. • Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 16-5. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 123.). Table 16-3. Compare Output Mode, Fast PWM(1) COM1A1/COM1B1 COM1A0/COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 14 or 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected. 1 0 Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at BOTTOM (non-inverting mode). 1 1 Set OC1A/OC1B on Compare Match, clear OC1A/OC1B at BOTTOM (inverting mode). Table 16-4. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1) COM1A1/COM1B1 COM1A0/COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 9 or 11: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected. 1 0 Clear OC1A/OC1B on Compare Match when upcounting. Set OC1A/OC1B on Compare Match when counting down. 1 1 Set OC1A/OC1B on Compare Match when upcounting. Clear OC1A/OC1B on Compare Match when counting down.134 2552K–AVR–04/11 ATmega329/3290/649/6490 Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. 16.11.2 TCCR1B – Timer/Counter1 Control Register B • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture pin (ICP1) is filtered. The filter function requires four successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled. • Bit 6 – ICES1: Input Capture Edge Select This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. Table 16-5. Waveform Generation Mode Bit Description(1) Mode WGM13 WGM12 (CTC1) WGM11 (PWM11) WGM10 (PWM10) Timer/Counter Mode of Operation TOP Update of OCR1x at TOV1 Flag Set on 00 0 0 0 Normal 0xFFFF Immediate MAX 1 0 0 0 1 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM 2 0 0 1 0 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM 3 0 0 1 1 PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM 4 0 1 0 0 CTC OCR1A Immediate MAX 5 0 1 0 1 Fast PWM, 8-bit 0x00FF BOTTOM TOP 6 0 1 1 0 Fast PWM, 9-bit 0x01FF BOTTOM TOP 7 0 1 1 1 Fast PWM, 10-bit 0x03FF BOTTOM TOP 8 1 0 0 0 PWM, Phase and Frequency Correct ICR1 BOTTOM BOTTOM 9 1 0 0 1 PWM, Phase and Frequency Correct OCR1A BOTTOM BOTTOM 10 1 0 1 0 PWM, Phase Correct ICR1 TOP BOTTOM 11 1 0 1 1 PWM, Phase Correct OCR1A TOP BOTTOM 12 1 1 0 0 CTC ICR1 Immediate MAX 13 1 1 0 1 (Reserved) – – – 14 1 1 1 0 Fast PWM ICR1 BOTTOM TOP 15 1 1 1 1 Fast PWM OCR1A BOTTOM TOP Bit 7 6 5 4 3 2 1 0 (0x81) ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0135 2552K–AVR–04/11 ATmega329/3290/649/6490 When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled. • Bit 5 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCR1B is written. • Bit 4:3 – WGM13:2: Waveform Generation Mode See TCCR1A Register description. • Bit 2:0 – CS12:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure 16-10 and Figure 16-11. If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 16.11.3 TCCR1C – Timer/Counter1 Control Register C • Bit 7 – FOC1A: Force Output Compare for Unit A • Bit 6 – FOC1B: Force Output Compare for Unit B The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. Table 16-6. Clock Select Bit Description CS12 CS11 CS10 Description 000 No clock source (Timer/Counter stopped). 0 0 1 clkI/O/1 (No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T1 pin. Clock on falling edge. 1 1 1 External clock source on T1 pin. Clock on rising edge. Bit 7 6 5 4 3 2 1 0 (0x82) FOC1A FOC1B – – – – – – TCCR1C Read/Write R/W R/W R R R R R R Initial Value 0 0 0 0 0 0 0 0136 2552K–AVR–04/11 ATmega329/3290/649/6490 A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. 16.11.4 TCNT1H and TCNT1L – Timer/Counter1 The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 113. Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a compare match between TCNT1 and one of the OCR1x Registers. Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock for all compare units. 16.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A 16.11.6 OCR1BH and OCR1BL – Output Compare Register 1 B The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC1x pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 113. Bit 7 6 5 4 3 2 1 0 (0x85) TCNT1[15:8] TCNT1H (0x84) TCNT1[7:0] TCNT1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 (0x89) OCR1A[15:8] OCR1AH (0x88) OCR1A[7:0] OCR1AL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 (0x8B) OCR1B[15:8] OCR1BH (0x8A) OCR1B[7:0] OCR1BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0137 2552K–AVR–04/11 ATmega329/3290/649/6490 16.11.7 ICR1H and ICR1L – Input Capture Register 1 The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 113. 16.11.8 TIMSK1 – Timer/Counter1 Interrupt Mask Register • Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 49.) is executed when the ICF1 Flag, located in TIFR1, is set. • Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 49.) is executed when the OCF1B Flag, located in TIFR1, is set. • Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 49.) is executed when the OCF1A Flag, located in TIFR1, is set. • Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 49.) is executed when the TOV1 Flag, located in TIFR1, is set. Bit 7 6 5 4 3 2 1 0 (0x87) ICR1[15:8] ICR1H (0x86) ICR1[7:0] ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 (0x6F) – – ICIE1 – – OCIE1B OCIE1A TOIE1 TIMSK1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0138 2552K–AVR–04/11 ATmega329/3290/649/6490 16.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value. ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location. • Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B (OCR1B). Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag. OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location. Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A (OCR1A). Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag. OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location. • Bit 0 – TOV1: Timer/Counter1, Overflow Flag The setting of this flag is dependent of the WGM13:0 bits setting. In Normal and CTC modes, the TOV1 Flag is set when the timer overflows. Refer to Table 16-5 on page 134 for the TOV1 Flag behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. Bit 7 6 5 4 3 2 1 0 0x16 (0x36) – – ICF1 – – OCF1B OCF1A TOV1 TIFR1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0139 2552K–AVR–04/11 ATmega329/3290/649/6490 17. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 17.1 Features Timer/Counter2 is a general purpose, single compare unit, 8-bit Timer/Counter module. The main features are: • Single Compare Unit Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Frequency Generator • 10-bit Clock Prescaler • Overflow and Compare Match Interrupt Sources (TOV2 and OCF2A) • Allows Clocking from External 32kHz Watch Crystal Independent of the I/O Clock 17.2 Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 17-1. For the actual placement of I/O pins, refer to “Pinout ATmega3290/6490” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “Register Description” on page 153. Figure 17-1. 8-bit Timer/Counter Block Diagram Timer/Counter DATA BUS = TCNTn Waveform Generation OCnx = 0 Control Logic = 0xFF BOTTOM TOP count clear direction TOVn (Int.Req.) OCnx (Int.Req.) Synchronization Unit OCRnx TCCRnx ASSRn Status flags clkI/O clkASY Synchronized Status flags asynchronous mode select (ASn) TOSC1 T/C Oscillator TOSC2 Prescaler clkTn clkI/O140 2552K–AVR–04/11 ATmega329/3290/649/6490 17.2.1 Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT2). The double buffered Output Compare Register (OCR2A) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC2A). See “Output Compare Unit” on page 141. for details. The compare match event will also set the Compare Flag (OCF2A) which can be used to generate an Output Compare interrupt request. 17.2.2 Definitions Many register and bit references in this document are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 2. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT2 for accessing Timer/Counter2 counter value and so on. The definitions in Table 17-1 are also used extensively throughout the section. 17.3 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The clock source clkT2 is by default equal to the MCU clock, clkI/O. When the AS2 bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see “ASSR – Asynchronous Status Register” on page 155. For details on clock sources and prescaler, see “Timer/Counter Prescaler” on page 152. 17.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 17-2 shows a block diagram of the counter and its surrounding environment. Table 17-1. Definitions of Timer/Counter values. BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00). MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR2A Register. The assignment is dependent on the mode of operation.141 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 17-2. Counter Unit Block Diagram Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clkT2 Timer/Counter clock. top Signalizes that TCNT2 has reached maximum value. bottom Signalizes that TCNT2 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of whether clkT2 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in the Timer/Counter Control Register (TCCR2A). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare output OC2A. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 145. The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt. 17.5 Output Compare Unit The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2A). Whenever TCNT2 equals OCR2A, the comparator signals a match. A match will set the Output Compare Flag (OCF2A) at the next timer clock cycle. If enabled (OCIE2A = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF2A Flag is automatically cleared when the interrupt is executed. Alternatively, the OCF2A Flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM21:0 bits and Compare Output mode (COM2A1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (“Modes of Operation” on page 145). Figure 17-3 shows a block diagram of the Output Compare unit. DATA BUS TCNTn Control Logic count TOVn (Int.Req.) bottom top direction clear TOSC1 T/C Oscillator TOSC2 Prescaler clkI/O clk Tn142 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 17-3. Output Compare Unit, Block Diagram The OCR2A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2A Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR2A Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR2A Buffer Register, and if double buffering is disabled the CPU will access the OCR2A directly. 17.5.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC2A) bit. Forcing compare match will not set the OCF2A Flag or reload/clear the timer, but the OC2A pin will be updated as if a real compare match had occurred (the COM2A1:0 bits settings define whether the OC2A pin is set, cleared or toggled). 17.5.2 Compare Match Blocking by TCNT2 Write All CPU write operations to the TCNT2 Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR2A to be initialized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is enabled. 17.5.3 Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the Output Compare unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2A value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is counting down. OCFnx (Int.Req.) = (8-bit Comparator ) OCRnx OCnx DATA BUS TCNTn WGMn1:0 Waveform Generator top FOCn COMnX1:0 bottom143 2552K–AVR–04/11 ATmega329/3290/649/6490 The setup of the OC2A should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2A value is to use the Force Output Compare (FOC2A) strobe bit in Normal mode. The OC2A Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM2A1:0 bits are not double buffered together with the compare value. Changing the COM2A1:0 bits will take effect immediately.144 2552K–AVR–04/11 ATmega329/3290/649/6490 17.6 Compare Match Output Unit The Compare Output mode (COM2A1:0) bits have two functions. The Waveform Generator uses the COM2A1:0 bits for defining the Output Compare (OC2A) state at the next compare match. Also, the COM2A1:0 bits control the OC2A pin output source. Figure 17-4 shows a simplified schematic of the logic affected by the COM2A1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM2A1:0 bits are shown. When referring to the OC2A state, the reference is for the internal OC2A Register, not the OC2A pin. Figure 17-4. Compare Match Output Unit, Schematic The general I/O port function is overridden by the Output Compare (OC2A) from the Waveform Generator if either of the COM2A1:0 bits are set. However, the OC2A pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC2A pin (DDR_OC2A) must be set as output before the OC2A value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC2A state before the output is enabled. Note that some COM2A1:0 bit settings are reserved for certain modes of operation. See “Register Description” on page 153. 17.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM2A1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2A1:0 = 0 tells the Waveform Generator that no action on the OC2A Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 17-3 on page 154. For fast PWM mode, refer to Table 17-4 on page 154, and for phase correct PWM refer to Table 17-5 on page 154. PORT DDR D Q D Q OCnx OCnx Pin D Q Waveform Generator COMnx1 COMnx0 0 1 DATA BUS FOCnx clkI/O145 2552K–AVR–04/11 ATmega329/3290/649/6490 A change of the COM2A1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC2A strobe bits. 17.7 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM21:0) and Compare Output mode (COM2A1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM2A1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM2A1:0 bits control whether the output should be set, cleared, or toggled at a compare match (See “Compare Match Output Unit” on page 144.). For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 149. 17.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV2 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 17.7.2 Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2A Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the OCR2A. The OCR2A defines the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 17-5. The counter value (TCNT2) increases until a compare match occurs between TCNT2 and OCR2A, and then counter (TCNT2) is cleared.146 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 17-5. CTC Mode, Timing Diagram An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR2A is lower than the current value of TCNT2, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM2A1:0 = 1). The OC2A value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC2A = fclk_I/O/2 when OCR2A is set to zero (0x00). The waveform frequency is defined by the following equation: The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 17.7.3 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 3) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC2A) is cleared on the compare match between TCNT2 and OCR2A, and set at BOTTOM. In inverting Compare Output mode, the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast TCNTn OCnx (Toggle) OCnx Interrupt Flag Set Period 1 2 3 4 (COMnx1:0 = 1) f OCnx f clk_I/O 2 ⋅ ⋅ N ( ) 1 + OCRnx = -------------------------------------------------147 2552K–AVR–04/11 ATmega329/3290/649/6490 PWM mode is shown in Figure 17-6. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2A and TCNT2. Figure 17-6. Fast PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2A pin. Setting the COM2A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM2A1:0 to three (See Table 17-4 on page 154). The actual OC2A value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC2A Register at the compare match between OCR2A and TCNT2, and clearing (or setting) the OC2A Register at the timer clock cycle the counter is cleared (changes from MAX to BOTTOM). The PWM frequency for the output can be calculated by the following equation: The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM2A1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2A to toggle its logical level on each compare match (COM2A1:0 = 1). The waveform generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2A is set to zero. This feature is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. TCNTn OCRnx Update and TOVn Interrupt Flag Set Period 1 2 3 OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3) OCRnx Interrupt Flag Set 4 5 6 7 f OCnxPWM f clk_I/O N ⋅ 256 = ------------------148 2552K–AVR–04/11 ATmega329/3290/649/6490 17.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM21:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In noninverting Compare Output mode, the Output Compare (OC2A) is cleared on the compare match between TCNT2 and OCR2A while counting up, and set on the compare match while counting down. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT2 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 17-7. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2A and TCNT2. Figure 17-7. Phase Correct PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2A pin. Setting the COM2A1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM2A1:0 to three (See Table 17-5 on page 154). The actual OC2A value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2A Register at the compare match between OCR2A and TCNT2 when the counter increments, and setting (or clearing) the OC2A Register at compare match between OCR2A and TCNT2 when the counter TOVn Interrupt Flag Set OCnx Interrupt Flag Set 1 2 3 TCNTn Period OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3) OCRnx Update149 2552K–AVR–04/11 ATmega329/3290/649/6490 decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. At the very start of period 2 in Figure 17-7 OCn has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match. • OCR2A changes its value from MAX, like in Figure 17-7. When the OCR2A value is MAX the OCn pin value is the same as the result of a down-counting compare match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an upcounting Compare Match. • The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. 17.8 Timer/Counter Timing Diagrams The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT2) is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should be replaced by the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are set. Figure 17-8 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 17-8. Timer/Counter Timing Diagram, no Prescaling Figure 17-9 shows the same timing data, but with the prescaler enabled. f OCnxPCPWM f clk_I/O N ⋅ 510 = ------------------ clkTn (clkI/O/1) TOVn clkI/O TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1150 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 17-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) Figure 17-10 shows the setting of OCF2A in all modes except CTC mode. Figure 17-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (fclk_I/O/8) Figure 17-11 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. Figure 17-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8) TOVn TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 clkI/O clkTn (clkI/O/8) OCFnx OCRnx TCNTn OCRnx Value OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 clkI/O clkTn (clkI/O/8) OCFnx OCRnx TCNTn (CTC) TOP TOP - 1 TOP BOTTOM BOTTOM + 1 clkI/O clkTn (clkI/O/8)151 2552K–AVR–04/11 ATmega329/3290/649/6490 17.9 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2A, and TCCR2A might be corrupted. A safe procedure for switching clock source is: 1. Disable the Timer/Counter2 interrupts by clearing OCIE2A and TOIE2. 2. Select clock source by setting AS2 as appropriate. 3. Write new values to TCNT2, OCR2A, and TCCR2A. 4. To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and TCR2UB. 5. Clear the Timer/Counter2 Interrupt Flags. 6. Enable interrupts, if needed. • The CPU main clock frequency must be more than four times the Oscillator frequency. • When writing to one of the registers TCNT2, OCR2A, or TCCR2A, the value is transferred to a temporary register, and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary register have been transferred to its destination. Each of the three mentioned registers have their individual temporary register, which means that e.g. writing to TCNT2 does not disturb an OCR2A write in progress. To detect that a transfer to the destination register has taken place, the Asynchronous Status Register – ASSR has been implemented. • When entering Power-save or ADC Noise Reduction mode after having written to TCNT2, OCR2A, or TCCR2A, the user must wait until the written register has been updated if Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode before the changes are effective. This is particularly important if the Output Compare2 interrupt is used to wake up the device, since the Output Compare function is disabled during writing to OCR2A or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode before the OCR2UB bit returns to zero, the device will never receive a compare match interrupt, and the MCU will not wake up. • If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise Reduction mode, precautions must be taken if the user wants to re-enter one of these modes: The interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and reentering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the user is in doubt whether the time before re-entering Powersave or ADC Noise Reduction mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: 1. Write a value to TCCR2A, TCNT2, or OCR2A. 2. Wait until the corresponding Update Busy Flag in ASSR returns to zero. 3. Enter Power-save or ADC Noise Reduction mode. • When the asynchronous operation is selected, the 32.768kHz Oscillator for Timer/Counter2 is always running, except in Power-down and Standby modes. After a Power-up Reset or wake-up from Power-down or Standby mode, the user should be aware of the fact that this Oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using Timer/Counter2 after power-up or wake-up from Power-down or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after a wake-up from Power-down or Standby mode due to unstable clock signal upon startup, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. • Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four 152 2552K–AVR–04/11 ATmega329/3290/649/6490 cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP. • Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When waking up from Powersave mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will read as the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-save mode is essentially unpredictable, as it depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows: 1. Write any value to either of the registers OCR2A or TCCR2A. 2. Wait for the corresponding Update Busy Flag to be cleared. 3. Read TCNT2. During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the Interrupt Flag. The Output Compare pin is changed on the timer clock and is not synchronized to the processor clock. 17.10 Timer/Counter Prescaler Figure 17-12. Prescaler for Timer/Counter2 The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clkIO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port C. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter2. The Oscillator is optimized for use with a 32.768kHz crystal. If applying an external clock on TOSC1, the EXCLK bit in ASSR must be set. 10-BIT T/C PRESCALER TIMER/COUNTER2 CLOCK SOURCE clkI/O clkT2S TOSC1 AS2 CS20 CS21 CS22 clkT2S/8 clkT2S/64 clkT2S/128 clkT2S/1024 clkT2S/256 clkT2S/32 0 PSR2 Clear clkT2153 2552K–AVR–04/11 ATmega329/3290/649/6490 For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clkT2S/32, clkT2S/64, clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected. Setting the PSR2 bit in GTCCR resets the prescaler. This allows the user to operate with a predictable prescaler. 17.11 Register Description 17.11.1 TCCR2A – Timer/Counter Control Register A • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2A is written when operating in PWM mode. When writing a logical one to the FOC2A bit, an immediate compare match is forced on the Waveform Generation unit. The OC2A output is changed according to its COM2A1:0 bits setting. Note that the FOC2A bit is implemented as a strobe. Therefore it is the value present in the COM2A1:0 bits that determines the effect of the forced compare. A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2A as TOP. The FOC2A bit is always read as zero. • Bit 6, 3 – WGM21:0: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 17-2 and “Modes of Operation” on page 145. Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. • Bit 5:4 – COM2A1:0: Compare Match Output Mode A These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC2A pin must be set in order to enable the output driver. Bit 7 6 5 4 3 2 1 0 (0xB0) FOC2A WGM20 COM2A1 COM2A0 WGM21 CS22 CS21 CS20 TCCR2A Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 17-2. Waveform Generation Mode Bit Description(1) Mode WGM21 (CTC2) WGM20 (PWM2) Timer/Counter Mode of Operation TOP Update of OCR2A at TOV2 Flag Set on 00 0 Normal 0xFF Immediate MAX 1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 1 0 CTC OCR2A Immediate MAX 3 1 1 Fast PWM 0xFF BOTTOM MAX154 2552K–AVR–04/11 ATmega329/3290/649/6490 When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the WGM21:0 bit setting. Table 17-3 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (non-PWM). Table 17-4 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM mode. Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the compare match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 146 for more details. Table 17-5 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct PWM mode. Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the compare match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 148 for more details. Table 17-3. Compare Output Mode, non-PWM Mode COM2A1 COM2A0 Description 0 0 Normal port operation, OC2A disconnected. 0 1 Toggle OC2A on compare match. 1 0 Clear OC2A on compare match. 1 1 Set OC2A on compare match. Table 17-4. Compare Output Mode, Fast PWM Mode(1) COM2A1 COM2A0 Description 0 0 Normal port operation, OC2A disconnected. 0 1 Reserved 1 0 Clear OC2A on compare match, set OC2A at BOTTOM, (non-inverting mode). 1 1 Set OC2A on compare match, clear OC2A at BOTTOM, (inverting mode) Table 17-5. Compare Output Mode, Phase Correct PWM Mode(1) COM2A1 COM2A0 Description 0 0 Normal port operation, OC2A disconnected. 0 1 Reserved 1 0 Clear OC2A on compare match when up-counting. Set OC2A on compare match when counting down. 1 1 Set OC2A on compare match when up-counting. Clear OC2A on compare match when counting down.155 2552K–AVR–04/11 ATmega329/3290/649/6490 • Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 17-6. 17.11.2 TCNT2 – Timer/Counter Register The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a compare match between TCNT2 and the OCR2A Register. 17.11.3 OCR2A – Output Compare Register A The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2A pin. 17.11.4 ASSR – Asynchronous Status Register • Bit 4 – EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32kHz crystal. Writing to EXCLK should be done before asynchronous operation is selected. Note that the crystal Oscillator will only run when this bit is zero. Table 17-6. Clock Select Bit Description CS22 CS21 CS20 Description 000 No clock source (Timer/Counter stopped). 0 0 1 clkT2S/(No prescaling) 0 1 0 clkT2S/8 (From prescaler) 0 1 1 clkT2S/32 (From prescaler) 1 0 0 clkT2S/64 (From prescaler) 1 0 1 clkT2S/128 (From prescaler) 1 1 0 clkT2S/256 (From prescaler) 1 1 1 clkT2S/1024 (From prescaler) Bit 7 6 5 4 3 2 1 0 (0xB2) TCNT2[7:0] TCNT2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 (0xB3) OCR2A[7:0] OCR2A Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 (0xB6) – – – EXCLK AS2 TCN2UB OCR2UB TCR2UB ASSR Read/Write R R R R/W R/W R R R Initial Value 0 0 0 0 0 0 0 0156 2552K–AVR–04/11 ATmega329/3290/649/6490 • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A, and TCCR2A might be corrupted. • Bit 2 – TCN2UB: Timer/Counter2 Update Busy When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value. • Bit 1 – OCR2UB: Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set. When OCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new value. • Bit 0 – TCR2UB: Timer/Counter Control Register2 Update Busy When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set. When TCCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new value. If a write is performed to any of the three Timer/Counter2 Registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. The mechanisms for reading TCNT2, OCR2A, and TCCR2A are different. When reading TCNT2, the actual timer value is read. When reading OCR2A or TCCR2A, the value in the temporary storage register is read. 17.11.5 TIMSK2 – Timer/Counter2 Interrupt Mask Register • Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is set in the Timer/Counter 2 Interrupt Flag Register – TIFR2. • Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2 Interrupt Flag Register – TIFR2. Bit 7 6 5 4 3 2 1 0 (0x70) – – – – – – OCIE2A TOIE2 TIMSK2 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0157 2552K–AVR–04/11 ATmega329/3290/649/6490 17.11.6 TIFR2 – Timer/Counter2 Interrupt Flag Register • Bit 1 – OCF2A: Output Compare Flag 2 A The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed. • Bit 0 – TOV2: Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00. 17.11.7 GTCCR – General Timer/Counter Control Register • Bit 1 – PSR2: Prescaler Reset Timer/Counter2 When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the “Bit 7 – TSM: Timer/Counter Synchronization Mode” on page 108 for a description of the Timer/Counter Synchronization mode. Bit 7 6 5 4 3 2 1 0 0x17 (0x37) – – – – – – OCF2A TOV2 TIFR2 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x23 (0x43) TSM – – – – – PSR2 PSR10 GTCCR Read/Write R/W R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0158 2552K–AVR–04/11 ATmega329/3290/649/6490 18. SPI – Serial Peripheral Interface 18.1 Features The ATmega329/3290/649/6490 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode 18.2 Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega329/3290/649/6490 and peripheral devices or between several AVR devices. A simplified block diagram of the Serial Peripheral Interface is shown in Figure 18-1. The PRSPI bit in “Power Reduction Register” on page 37 must be written to zero to enable the SPI module. Figure 18-1. SPI Block Diagram(1) Note: 1. Refer to Figure 1-1 on page 2, and Table 13-6 on page 68 for SPI pin placement. SPI2X SPI2X DIVIDER /2/4/8/16/32/64/128159 2552K–AVR–04/11 ATmega329/3290/649/6490 The interconnection between Master and Slave CPUs with SPI is shown in Figure 18-2. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line. When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the Buffer Register for later use. When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use. Figure 18-2. SPI Master-slave Interconnection The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received character must be read from the SPI Data Register before the next character has been completely shifted in. Otherwise, the first byte is lost. In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high period should be: Low period: longer than 2 CPU clock cycles. High period: longer than 2 CPU clock cycles. SHIFT ENABLE160 2552K–AVR–04/11 ATmega329/3290/649/6490 When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 18-1. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 65. Note: 1. See “Alternate Functions of Port B” on page 68 for a detailed description of how to define the direction of the user defined SPI pins. Table 18-1. SPI Pin Overrides(1) Pin Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input161 2552K–AVR–04/11 ATmega329/3290/649/6490 The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. Note: 1. See “About Code Examples” on page 9. Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<>8); UBRR0L = (unsigned char)ubrr; /* Enable receiver and transmitter */ UCSR0B = (1<> 1) & 0x01; return ((resh << 8) | resl); }180 2552K–AVR–04/11 ATmega329/3290/649/6490 19.7.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero. When the Receive Complete Interrupt Enable (RXCIEn) in UCSRnB is set, the USART Receive Complete interrupt will be executed as long as the RXCn Flag is set (provided that global interrupts are enabled). When interrupt-driven data reception is used, the receive complete routine must read the received data from UDRn in order to clear the RXCn Flag, otherwise a new interrupt will occur once the interrupt routine terminates. 19.7.4 Receiver Error Flags The USART Receiver has three Error Flags: Frame Error (FEn), Data OverRun (DORn) and Parity Error (UPEn). All can be accessed by reading UCSRnA. Common for the Error Flags is that they are located in the receive buffer together with the frame for which they indicate the error status. Due to the buffering of the Error Flags, the UCSRnA must be read before the receive buffer (UDRn), since reading the UDRn I/O location changes the buffer read location. Another equality for the Error Flags is that they can not be altered by software doing a write to the flag location. However, all flags must be set to zero when the UCSRnA is written for upward compatibility of future USART implementations. None of the Error Flags can generate interrupts. The Frame Error (FEn) Flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. The FEn Flag is zero when the stop bit was correctly read (as one), and the FEn Flag will be one when the stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. The FEn Flag is not affected by the setting of the USBSn bit in UCSRnC since the Receiver ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. The Data OverRun (DORn) Flag indicates data loss due to a receiver buffer full condition. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. If the DORn Flag is set there was one or more serial frame lost between the frame last read from UDRn, and the next frame read from UDRn. For compatibility with future devices, always write this bit to zero when writing to UCSRnA. The DORn Flag is cleared when the frame received was successfully moved from the Shift Register to the receive buffer. The Parity Error (UPEn) Flag indicates that the next frame in the receive buffer had a Parity Error when received. If Parity Check is not enabled the UPEn bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more details see “Parity Bit Calculation” on page 173 and “Parity Checker” on page 180. 19.7.5 Parity Checker The Parity Checker is active when the high USART Parity mode (UPMn1) bit is set. Type of Parity Check to be performed (odd or even) is selected by the UPMn0 bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPEn) Flag can then be read by software to check if the frame had a Parity Error.181 2552K–AVR–04/11 ATmega329/3290/649/6490 The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. 19.7.6 Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e., the RXENn is set to zero) the Receiver will no longer override the normal function of the RxD port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost 19.7.7 Flushing the Receive Buffer The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDRn I/O location until the RXCn Flag is cleared. The following code example shows how to flush the receive buffer. Note: 1. See “About Code Examples” on page 9. 19.8 Asynchronous Data Reception The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the RxD pin. The data recovery logic samples and low pass filters each incoming bit, thereby improving the noise immunity of the Receiver. The asynchronous reception operational range depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. 19.8.1 Asynchronous Clock Recovery The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 19-5 illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The horizontal arrows illustrate the synchronization variation due to the sampling process. Note the larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done when the RxD line is idle (i.e., no communication activity). Assembly Code Example(1) USART_Flush: sbis UCSR0A, RXC0 ret in r16, UDR0 rjmp USART_Flush C Code Example(1) void USART_Flush( void ) { unsigned char dummy; while ( UCSR0A & (1< 470 nF) must be connected to the LCDCAP pin as shown in Figure 23-2. This capacitor acts as a reservoir for LCD power (VLCD). A large capacitance reduces ripple on VLCD but increases the time until VLCD reaches its target value. Figure 23-2. LCDCAP Connection 23.1.8 LCD Buffer Driver Intermediate voltage levels are generated from buffers/drivers. The buffers are active the amount of time specified by LCDDC[2:0] in LCDCCR. Then LCD output pins are tri-stated and buffers are switched off. Shortening the drive time will reduce power consumption, but displays with high internal resistance or capacitance may need longer drive time to achieve sufficient contrast. 23.1.9 Display requirements When using more than one common pin, the maximum period the LCD drivers can be turned on for each voltage transition on the LCD pins is 50% of the prescaled LCD clock period, clkLCD_PS. To avoid flickering, it is recommended to keep the framerate above 30Hz, thus giving a maximum drive time of approximately 2ms when using 1/2 or 1/4 duty, and approximately 2.7ms 1 2 3 64 63 62 LCDCAP231 2552K–AVR–04/11 ATmega329/3290/649/6490 when using 1/3 duty. To achieve satisfactory contrast, all segments on the LCD display must therefore be able to be fully charged/discharged within 2 or 2.7ms, depending on the number of common pins. 23.1.10 Minimizing power consumption By keeping the percentage of the time the LCD drivers are turned on at a minimum, the power consumption of the LCD driver can be minimized. This can be achieved by using the lowest acceptable frame rate, and using low power waveform if possible. The drive time should be kept at the lowest setting that achieves satisfactory contrast for a particular display, while allowing some headroom for production variations between individual LCD drivers and displays. Note that some of the highest LCD voltage settings may result in high power consumption when VCC is below 2.0V. The recommended maximum LCD voltage is 2*(VCC - 0.2V). 23.2 Mode of Operation 23.2.1 Static Duty and Bias If all segments on a LCD have one electrode common, then each segment must have a unique terminal. This kind of display is driven with the waveform shown in Figure 23-3. SEG0 - COM0 is the voltage across a segment that is on, and SEG1 - COM0 is the voltage across a segment that is off. Figure 23-3. Driving a LCD with One Common Terminal 23.2.2 1/2 Duty and 1/2 Bias For LCD with two common terminals (1/2 duty) a more complex waveform must be used to individually control segments. Although 1/3 bias can be selected 1/2 bias is most common for these displays. Waveform is shown in Figure 23-4. SEG0 - COM0 is the voltage across a segment that is on, and SEG0 - COM1 is the voltage across a segment that is off. VLCD GND VLCD GND VLCD GND -VLCD SEG0 COM0 SEG0 - COM0 Frame Frame VLCD GND VLCD GND GND SEG1 COM0 SEG1 - COM0 Frame Frame232 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 23-4. Driving a LCD with Two Common Terminals 23.2.3 1/3 Duty and 1/3 Bias 1/3 bias is usually recommended for LCD with three common terminals (1/3 duty). Waveform is shown in Figure 23-5. SEG0 - COM0 is the voltage across a segment that is on and SEG0- COM1 is the voltage across a segment that is off. Figure 23-5. Driving a LCD with Three Common Terminals 23.2.4 1/4 Duty and 1/3 Bias 1/3 bias is optimal for LCD displays with four common terminals (1/4 duty). Waveform is shown in Figure 23-6. SEG0 - COM0 is the voltage across a segment that is on and SEG0 - COM1 is the voltage across a segment that is off. VLCD GND VLCD 1/ 2VLCD GND VLCD 1/ 2VLCD GND -1/ 2VLCD -VLCD SEG0 COM0 SEG0 - COM0 Frame Frame VLCD GND VLCD 1/ 2VLCD GND VLCD 1/ 2VLCD GND -1/ 2VLCD -VLCD SEG0 COM1 SEG0 - COM1 Frame Frame VLCD 2/ 3VLCD 1/ 3VLCD GND VLCD 2/ 3VLCD 1/ 3VLCD GND VLCD 2/ 3VLCD 1/ 3VLCD GND -1/ 3VLCD -2/ 3VLCD -VLCD SEG0 COM0 SEG0 - COM0 Frame Frame VLCD 2/ 3VLCD 1/ 3VLCD GND VLCD 2/ 3VLCD 1/ 3VLCD GND VLCD 2/ 3VLCD 1/ 3VLCD GND -1/ 3VLCD -2/ 3VLCD -VLCD SEG0 COM1 SEG0 - COM1 Frame Frame233 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 23-6. Driving a LCD with Four Common Terminals 23.2.5 Low Power Waveform To reduce toggle activity and hence power consumption a low power waveform can be selected by writing LCDAB to one. Low power waveform requires two subsequent frames with the same display data to obtain zero DC voltage. Consequently data latching and Interrupt Flag is only set every second frame. Default and low power waveform is shown in Figure 23-7 for 1/3 duty and 1/3 bias. For other selections of duty and bias, the effect is similar. Figure 23-7. Default and Low Power Waveform 23.2.6 Operation in Sleep Mode When synchronous LCD clock is selected (LCDCS = 0) the LCD display will operate in Idle mode and Power-save mode with any clock source. An asynchronous clock from TOSC1 can be selected as LCD clock by writing the LCDCS bit to one when Calibrated Internal RC Oscillator is selected as system clock source. The LCD will then operate in Idle mode, ADC Noise Reduction mode and Power-save mode. VLCD 2/ 3VLCD 1/ 3VLCD GND VLCD 2/ 3VLCD 1/ 3VLCD GND VLCD 2/ 3VLCD 1/ 3VLCD GND -1/ 3VLCD -2/ 3VLCD -VLCD SEG0 COM0 SEG0 - COM0 Frame Frame VLCD 2/ 3VLCD 1/ 3VLCD GND VLCD 2/ 3VLCD 1/ 3VLCD GND VLCD 2/ 3VLCD 1/ 3VLCD GND -1/ 3VLCD -2/ 3VLCD -VLCD SEG0 COM1 SEG0 - COM1 Frame Frame VLCD 2/ 3VLCD 1/ 3VLCD GND VLCD 2/ 3VLCD 1/ 3VLCD GND VLCD 2/ 3VLCD 1/ 3VLCD GND -1/ 3VLCD -2/ 3VLCD -VLCD SEG0 COM0 SEG0 - COM0 Frame Frame VLCD 2/ 3VLCD 1/ 3VLCD GND VLCD 2/ 3VLCD 1/ 3VLCD GND VLCD 2/ 3VLCD 1/ 3VLCD GND -1/ 3VLCD -2/ 3VLCD -VLCD SEG0 COM0 SEG0 - COM0 Frame Frame234 2552K–AVR–04/11 ATmega329/3290/649/6490 When EXCLK in ASSR Register is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32kHz crystal. See “Asynchronous Operation of Timer/Counter2” on page 151 for further details. Before entering Power-down mode, Standby mode or ADC Noise Reduction mode with synchronous LCD clock selected, the user have to disable the LCD. Refer to “Disabling the LCD” on page 237. 23.2.7 Display Blanking When LCDBL is written to one, the LCD is blanked after completing the current frame. All segments and common pins are connected to GND, discharging the LCD. Display memory is preserved. Display blanking should be used before disabling the LCD to avoid DC voltage across segments, and a slowly fading image. 23.2.8 Port Mask For LCD with less than 25/40 segment terminals, it is possible to mask some of the unused pins and use them as ordinary port pins instead. Refer to Table 23-3 for details. Unused common pins are automatically configured as port pins.235 2552K–AVR–04/11 ATmega329/3290/649/6490 23.3 LCD Usage The following section describes how to use the LCD. 23.3.1 LCD Initialization Prior to enabling the LCD some initialization must be preformed. The initialization process normally consists of setting the frame rate, duty, bias and port mask. LCD contrast is set initially, but can also be adjusted during operation. Consider the following LCD as an example: Figure 23-8. Display: TN Positive, Reflective Number of common terminals: 3 Number of segment terminals: 21 Bias system: 1/3 Bias Drive system: 1/3 Duty Operating voltage: 3.0 ± 0.3 V 1b 1c 2a 2b 2e 2c 2f 2d 2g COM3 COM0 COM1 COM2 SEG0 SEG1 SEG2 1b,1c 2c 2f 2a 2d 2g 2b 2e .. COM2 SEG0 SEG1 SEG2 ATmega329 COM0 COM1 Connection table LCD 51 50 49 48 47 46 45236 2552K–AVR–04/11 ATmega329/3290/649/6490 Note: 1. See “About Code Examples” on page 9. Before a re-initialization is done, the LCD controller/driver should be disabled Assembly Code Example(1) LCD_Init: ; Use 32 kHz crystal oscillator ; 1/3 Bias and 1/3 duty, SEG21:SEG24 is used as port pins ldi r16, (1< 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck ≥ 12MHz High: > 2 CPU clock cycles for fck < 12MHz, 3 CPU clock cycles for fck ≥ 12MHz 27.7.2 Serial Programming Algorithm When writing serial data to the ATmega329/3290/649/6490, data is clocked on the rising edge of SCK. When reading data from the ATmega329/3290/649/6490, data is clocked on the falling edge of SCK. See Figure 27-11 for timing details. To program and verify the ATmega329/3290/649/6490 in the serial programming mode, the following sequence is recommended (See four byte instruction formats in Table 27-15): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”. 2. Wait for at least 20ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI. 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time. The page size is found in Table 27-10 on page 298. The memory page is loaded one byte at a time by supplying the 6/7 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 8 MSB of the address. If polling is not used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 27-14.) Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming. 5. A: The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling (RDY/BSY) is not used, the user must wait at least tWD_EEPROM before issuing the next byte (See Table 27-14.) In a chip erased device, no 0xFFs in the data file(s) need to be programmed. B: The EEPROM array is programmed one page at a time. The Memory page is loaded one byte at a time by supplying the 2 LSB of the address and data together with the Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading the Write EEPROM Memory Page Instruction with the 4 MSB of the address. When using EEPROM page access only byte locations loaded with the Load EEPROM Memory Page instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is not used, the used must wait at least tWD_EEPROM before issuing the next page (See Table 27-11). In a chip erased device, no 0xFF in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. 7. At the end of the programming session, RESET can be set high to commence normal operation.310 2552K–AVR–04/11 ATmega329/3290/649/6490 8. Power-off sequence (if needed): Set RESET to “1”. Turn VCC power off. Figure 27-11. Serial Programming Waveforms 27.7.3 Serial Programming Instruction set Table 27-15 and Figure 27-12 on page 312 describes the Instruction set. Table 27-14. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay tWD_FUSE 4.5ms tWD_FLASH 4.5ms tWD_EEPROM 9.0ms tWD_ERASE 9.0ms MSB MSB LSB LSB SERIAL CLOCK INPUT (SCK) SERIAL DATA INPUT (MOSI) (MISO) SAMPLE SERIAL DATA OUTPUT Table 27-15. Serial Programming Instruction Set Instruction/Operation Instruction Format Byte 1 Byte 2 Byte 3 Byte4 Programming Enable $AC $53 $00 $00 Chip Erase (Program Memory/EEPROM) $AC $80 $00 $00 Poll RDY/BSY $F0 $00 $00 data byte out Load Instructions Load Extended Address byte(1) $4D $00 Extended adr $00 Load Program Memory Page, High byte $48 $00 adr LSB high data byte in Load Program Memory Page, Low byte $40 $00 adr LSB low data byte in Load EEPROM Memory Page (page access) $C1 $00 0000 00aa / 0000 0aaa data byte in Read Instructions Read Program Memory, High byte $28 adr MSB adr LSB high data byte out Read Program Memory, Low byte $20 adr MSB adr LSB low data byte out Read EEPROM Memory $A0 0000 00aa / 0000 0aaa aaaa aaaa data byte out311 2552K–AVR–04/11 ATmega329/3290/649/6490 Note: 1. Not all instructions are applicable for all parts 2. a = address 3. Bits are programmed ‘0’, unprogrammed ‘1’. 4. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) . 5. Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size. 6. See htt://www.atmel.com/avr for Application Notes regarding programming and programmers. If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until this bit returns ‘0’ before the next instruction is carried out. Within the same page, the low data byte must be loaded prior to the high data byte. After data is loaded to the page buffer, program the EEPROM page, see Figure 27-12. Read Lock bits $58 $00 $00 data byte out Read Signature Byte $30 $00 0000 000aa data byte out Read Fuse bits $50 $00 $00 data byte out Read Fuse High bits $58 $08 $00 data byte out Read Extended Fuse Bits $50 $08 $00 data byte out Read Calibration Byte $38 $00 $00 data byte out Write Instructions Write Program Memory Page $4C adr MSB adr LSB $00 Write EEPROM Memory $C0 0000 00aa / 0000 0aaa aaaa aaaa data byte in Write EEPROM Memory Page (page access) $C2 0000 00aa / 0000 0aaa aaaa aa00 / aaaa a000 $00 Write Lock bits $AC $E0 $00 data byte in Write Fuse bits $AC $A0 $00 data byte in Write Fuse High bits $AC $A8 $00 data byte in Write Extended Fuse Bits $AC $A4 $00 data byte in Table 27-15. Serial Programming Instruction Set Instruction/Operation Instruction Format Byte 1 Byte 2 Byte 3 Byte4312 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 27-12. Serial Programming Instruction example 27.7.4 SPI Serial Programming Characteristics For characteristics of the SPI module see “SPI Timing Characteristics” on page 331. Byte 1 Byte 2 Byte 3 Byte 4 Adr LSB Bit 15 B 0 Serial Programming Instruction Program Memory/ EEPROM Memory Page 0 Page 1 Page 2 Page N-1 Page Buffer Write Program Memory Page/ Write EEPROM Memory Page Load Program Memory Page (High/Low Byte)/ Load EEPROM Memory Page (page access) Byte 1 Byte 2 Byte 3 Byte 4 Bit 15 B 0 Adr MSB Page Offset Page Number Adr MSB Adr LSB313 2552K–AVR–04/11 ATmega329/3290/649/6490 27.8 Programming via the JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI, and TDO. Control of the reset and clock pins is not required. To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is default shipped with the fuse programmed. In addition, the JTD bit in MCUCSR must be cleared. Alternatively, if the JTD bit is set, the external reset can be forced low. Then, the JTD bit will be cleared after two chip clocks, and the JTAG pins are available for programming. This provides a means of using the JTAG pins as normal port pins in Running mode while still allowing In-System Programming via the JTAG interface. Note that this technique can not be used when using the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must be dedicated for this purpose. During programming the clock frequency of the TCK Input must be less than the maximum frequency of the chip. The System Clock Prescaler can not be used to divide the TCK Clock Input into a sufficiently low frequency. As a definition in this data sheet, the LSB is shifted in and out first of all Shift Registers. 27.8.1 Programming Specific JTAG Instructions The Instruction Register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions useful for programming are listed below. The OPCODE for each instruction is shown behind the instruction name in hex format. The text describes which Data Register is selected as path between TDI and TDO for each instruction. The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be used as an idle state between JTAG sequences. The state machine sequence for changing the instruction word is shown in Figure 27-13.314 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 27-13. State Machine Sequence for Changing the Instruction Word 27.8.2 AVR_RESET (0xC) The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the device out from the Reset mode. The TAP controller is not reset by this instruction. The one bit Reset Register is selected as Data Register. Note that the reset will be active as long as there is a logic “one” in the Reset Chain. The output from this chain is not latched. The active states are: • Shift-DR: The Reset Register is shifted by the TCK input. 27.8.3 PROG_ENABLE (0x4) The AVR specific public JTAG instruction for enabling programming via the JTAG port. The 16- bit Programming Enable Register is selected as Data Register. The active states are the following: • Shift-DR: The programming enable signature is shifted into the Data Register. • Update-DR: The programming enable signature is compared to the correct value, and Programming mode is entered if the signature is valid. Test-Logic-Reset Run-Test/Idle Shift-DR Exit1-DR Pause-DR Exit2-DR Update-DR Select-IR Scan Capture-IR Shift-IR Exit1-IR Pause-IR Exit2-IR Update-IR Select-DR Scan Capture-DR 0 1 0 11 1 0 0 0 0 1 1 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1315 2552K–AVR–04/11 ATmega329/3290/649/6490 27.8.4 PROG_COMMANDS (0x5) The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as Data Register. The active states are the following: • Capture-DR: The result of the previous command is loaded into the Data Register. • Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous command and shifting in the new command. • Update-DR: The programming command is applied to the Flash inputs • Run-Test/Idle: One clock cycle is generated, executing the applied command (not always required, see Table 27-16 below). 27.8.5 PROG_PAGELOAD (0x6) The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port. An 8-bit Flash Data Byte Register is selected as the Data Register. This is physically the 8 LSBs of the Programming Command Register. The active states are the following: • Shift-DR: The Flash Data Byte Register is shifted by the TCK input. • Update-DR: The content of the Flash Data Byte Register is copied into a temporary register. A write sequence is initiated that within 11 TCK cycles loads the content of the temporary register into the Flash page buffer. The AVR automatically alternates between writing the low and the high byte for each new Update-DR state, starting with the low byte for the first Update-DR encountered after entering the PROG_PAGELOAD command. The Program Counter is pre-incremented before writing the low byte, except for the first written byte. This ensures that the first data is written to the address set up by PROG_COMMANDS, and loading the last location in the page buffer does not make the program counter increment into the next page. 27.8.6 PROG_PAGEREAD (0x7) The AVR specific public JTAG instruction to directly capture the Flash content via the JTAG port. An 8-bit Flash Data Byte Register is selected as the Data Register. This is physically the 8 LSBs of the Programming Command Register. The active states are the following: • Capture-DR: The content of the selected Flash byte is captured into the Flash Data Byte Register. The AVR automatically alternates between reading the low and the high byte for each new Capture-DR state, starting with the low byte for the first Capture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is post-incremented after reading each high byte, including the first read byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last location in the page makes the program counter increment into the next page. • Shift-DR: The Flash Data Byte Register is shifted by the TCK input. 27.8.7 Data Registers The Data Registers are selected by the JTAG instruction registers described in section “Programming Specific JTAG Instructions” on page 313. The Data Registers relevant for programming operations are: • Reset Register • Programming Enable Register • Programming Command Register • Flash Data Byte Register316 2552K–AVR–04/11 ATmega329/3290/649/6490 27.8.8 Reset Register The Reset Register is a Test Data Register used to reset the part during programming. It is required to reset the part before entering Programming mode. A high value in the Reset Register corresponds to pulling the external reset low. The part is reset as long as there is a high value present in the Reset Register. Depending on the Fuse settings for the clock options, the part will remain reset for a Reset Time-out period (refer to “Clock Sources” on page 27) after releasing the Reset Register. The output from this Data Register is not latched, so the reset will take place immediately, as shown in Figure 25-2 on page 253. 27.8.9 Programming Enable Register The Programming Enable Register is a 16-bit register. The contents of this register is compared to the programming enable signature, binary code 0b1010_0011_0111_0000. When the contents of the register is equal to the programming enable signature, programming via the JTAG port is enabled. The register is reset to 0 on Power-on Reset, and should always be reset when leaving Programming mode. Figure 27-14. Programming Enable Register 27.8.10 Programming Command Register The Programming Command Register is a 15-bit register. This register is used to serially shift in programming commands, and to serially shift out the result of the previous command, if any. The JTAG Programming Instruction Set is shown in Table 27-16. The state sequence when shifting in the programming commands is illustrated in Figure 27-16. TDI TDO D A T A = D Q ClockDR & PROG_ENABLE Programming Enable 0xA370317 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 27-15. Programming Command Register TDI TDO S T R O B E S A D D R E S S / D A T A Flash EEPROM Fuses Lock Bits318 2552K–AVR–04/11 ATmega329/3290/649/6490 Table 27-16. JTAG Programming Instruction Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes 1a. Chip Erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx (2) 2a. Enter Flash Write 0100011_00010000 xxxxxxx_xxxxxxxx 2b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (9) 2c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 2d. Load Data Low Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx 2e. Load Data High Byte 0010111_iiiiiiii xxxxxxx_xxxxxxxx 2f. Latch Data 0110111_00000000 1110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 2g. Write Flash Page 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 2h. Poll for Page Write Complete 0110111_00000000 xxxxxox_xxxxxxxx (2) 3a. Enter Flash Read 0100011_00000010 xxxxxxx_xxxxxxxx 3b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (9) 3c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 3d. Read Data Low and High Byte 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo Low byte High byte 4a. Enter EEPROM Write 0100011_00010001 xxxxxxx_xxxxxxxx 4b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (9) 4c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 4d. Load Data Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx 4e. Latch Data 0110111_00000000 1110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 4f. Write EEPROM Page 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 4g. Poll for Page Write Complete 0110011_00000000 xxxxxox_xxxxxxxx (2) 5a. Enter EEPROM Read 0100011_00000011 xxxxxxx_xxxxxxxx 5b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (9)319 2552K–AVR–04/11 ATmega329/3290/649/6490 5c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 5d. Read Data Byte 0110011_bbbbbbbb 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 6a. Enter Fuse Write 0100011_01000000 xxxxxxx_xxxxxxxx 6b. Load Data Low Byte(6) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 6c. Write Fuse Extended Byte 0111011_00000000 0111001_00000000 0111011_00000000 0111011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6d. Poll for Fuse Write Complete 0110111_00000000 xxxxxox_xxxxxxxx (2) 6e. Load Data Low Byte(7) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 6f. Write Fuse High Byte 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6g. Poll for Fuse Write Complete 0110111_00000000 xxxxxox_xxxxxxxx (2) 6h. Load Data Low Byte(7) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (3) 6i. Write Fuse Low Byte 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6j. Poll for Fuse Write Complete 0110011_00000000 xxxxxox_xxxxxxxx (2) 7a. Enter Lock Bit Write 0100011_00100000 xxxxxxx_xxxxxxxx 7b. Load Data Byte(9) 0010011_11iiiiii xxxxxxx_xxxxxxxx (4) 7c. Write Lock Bits 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 7d. Poll for Lock Bit Write complete 0110011_00000000 xxxxxox_xxxxxxxx (2) 8a. Enter Fuse/Lock Bit Read 0100011_00000100 xxxxxxx_xxxxxxxx 8b. Read Extended Fuse Byte(6) 0111010_00000000 0111011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 8c. Read Fuse High Byte(7) 0111110_00000000 0111111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 8d. Read Fuse Low Byte(8) 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 8e. Read Lock Bits(9) 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxoooooo (5) Table 27-16. JTAG Programming Instruction Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes320 2552K–AVR–04/11 ATmega329/3290/649/6490 Notes: 1. This command sequence is not required if the seven MSB are correctly set by the previous command sequence (which is normally the case). 2. Repeat until o = “1”. 3. Set bits to “0” to program the corresponding Fuse, “1” to unprogram the Fuse. 4. Set bits to “0” to program the corresponding Lock bit, “1” to leave the Lock bit unchanged. 5. “0” = programmed, “1” = unprogrammed. 6. The bit mapping for Fuses Extended byte is listed in Table 27-3 on page 294 7. The bit mapping for Fuses High byte is listed in Table 27-4 on page 295 8. The bit mapping for Fuses Low byte is listed in Table 27-5 on page 295 9. The bit mapping for Lock bits byte is listed in Table 27-1 on page 293 10. Address bits exceeding PCMSB and EEAMSB (Table 27-10 and Table 27-11) are don’t care 11. All TDI and TDO sequences are represented by binary digits (0b...). 8f. Read Fuses and Lock Bits 0111010_00000000 0111110_00000000 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo (5) Fuse Ext. byte Fuse High byte Fuse Low byte Lock bits 9a. Enter Signature Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx 9b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 9c. Read Signature Byte 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 10a. Enter Calibration Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx 10b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 10c. Read Calibration Byte 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo 11a. Load No Operation Command 0100011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx Table 27-16. JTAG Programming Instruction Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence TDO Sequence Notes321 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 27-16. State Machine Sequence for Changing/Reading the Data Word 27.8.11 Flash Data Byte Register The Flash Data Byte Register provides an efficient way to load the entire Flash page buffer before executing Page Write, or to read out/verify the content of the Flash. A state machine sets up the control signals to the Flash and senses the strobe signals from the Flash, thus only the data words need to be shifted in/out. The Flash Data Byte Register actually consists of the 8-bit scan chain and a 8-bit temporary register. During page load, the Update-DR state copies the content of the scan chain over to the temporary register and initiates a write sequence that within 11 TCK cycles loads the content of the temporary register into the Flash page buffer. The AVR automatically alternates between writing the low and the high byte for each new Update-DR state, starting with the low byte for the first Update-DR encountered after entering the PROG_PAGELOAD command. The Program Counter is pre-incremented before writing the low byte, except for the first written byte. This ensures that the first data is written to the address set up by PROG_COMMANDS, and loading the last location in the page buffer does not make the Program Counter increment into the next page. During Page Read, the content of the selected Flash byte is captured into the Flash Data Byte Register during the Capture-DR state. The AVR automatically alternates between reading the low and the high byte for each new Capture-DR state, starting with the low byte for the first CapTest-Logic-Reset Run-Test/Idle Shift-DR Exit1-DR Pause-DR Exit2-DR Update-DR Select-IR Scan Capture-IR Shift-IR Exit1-IR Pause-IR Exit2-IR Update-IR Select-DR Scan Capture-DR 0 1 0 11 1 0 0 0 0 1 1 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1322 2552K–AVR–04/11 ATmega329/3290/649/6490 ture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is post-incremented after reading each high byte, including the first read byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last location in the page makes the program counter increment into the next page. Figure 27-17. Flash Data Byte Register The state machine controlling the Flash Data Byte Register is clocked by TCK. During normal operation in which eight bits are shifted for each Flash byte, the clock cycles needed to navigate through the TAP controller automatically feeds the state machine for the Flash Data Byte Register with sufficient number of clock pulses to complete its operation transparently for the user. However, if too few bits are shifted between each Update-DR state during page load, the TAP controller should stay in the Run-Test/Idle state for some TCK cycles to ensure that there are at least 11 TCK cycles between each Update-DR state. 27.8.12 Programming Algorithm All references below of type “1a”, “1b”, and so on, refer to Table 27-16. 27.8.13 Entering Programming Mode 1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register. 2. Enter instruction PROG_ENABLE and shift 0b1010_0011_0111_0000 in the Programming Enable Register. 27.8.14 Leaving Programming Mode 1. Enter JTAG instruction PROG_COMMANDS. 2. Disable all programming instructions by using no operation instruction 11a. 3. Enter instruction PROG_ENABLE and shift 0b0000_0000_0000_0000 in the programming Enable Register. 4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register. TDI TDO D A T A Flash EEPROM Fuses Lock Bits STROBES ADDRESS State Machine323 2552K–AVR–04/11 ATmega329/3290/649/6490 27.8.15 Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS. 2. Start Chip Erase using programming instruction 1a. 3. Poll for Chip Erase complete using programming instruction 1b, or wait for tWLRH_CE (refer to Table 27-12 on page 307). 27.8.16 Programming the Flash Before programming the Flash a Chip Erase must be performed, see “Performing Chip Erase” on page 323. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load address High byte using programming instruction 2b. 4. Load address Low byte using programming instruction 2c. 5. Load data using programming instructions 2d, 2e and 2f. 6. Repeat steps 4 and 5 for all instruction words in the page. 7. Write the page using programming instruction 2g. 8. Poll for Flash write complete using programming instruction 2h, or wait for tWLRH (refer to Table 27-12 on page 307). 9. Repeat steps 3 to 7 until all data have been programmed. A more efficient data transfer can be achieved using the PROG_PAGELOAD instruction: 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load the page address using programming instructions 2b and 2c. PCWORD (refer to Table 27-10 on page 298) is used to address within one page and must be written as 0. 4. Enter JTAG instruction PROG_PAGELOAD. 5. Load the entire page by shifting in all instruction words in the page byte-by-byte, starting with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page. Use Update-DR to copy the contents of the Flash Data Byte Register into the Flash page location and to auto-increment the Program Counter before each new word. 6. Enter JTAG instruction PROG_COMMANDS. 7. Write the page using programming instruction 2g. 8. Poll for Flash write complete using programming instruction 2h, or wait for tWLRH (refer to Table 27-12 on page 307). 9. Repeat steps 3 to 8 until all data have been programmed. 27.8.17 Reading the Flash 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load address using programming instructions 3b and 3c. 4. Read data using programming instruction 3d. 5. Repeat steps 3 and 4 until all data have been read. A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction: 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a.324 2552K–AVR–04/11 ATmega329/3290/649/6490 3. Load the page address using programming instructions 3b and 3c. PCWORD (refer to Table 27-10 on page 298) is used to address within one page and must be written as 0. 4. Enter JTAG instruction PROG_PAGEREAD. 5. Read the entire page (or Flash) by shifting out all instruction words in the page (or Flash), starting with the LSB of the first instruction in the page (Flash) and ending with the MSB of the last instruction in the page (Flash). The Capture-DR state both captures the data from the Flash, and also auto-increments the program counter after each word is read. Note that Capture-DR comes before the shift-DR state. Hence, the first byte which is shifted out contains valid data. 6. Enter JTAG instruction PROG_COMMANDS. 7. Repeat steps 3 to 6 until all data have been read. 27.8.18 Programming the EEPROM Before programming the EEPROM a Chip Erase must be performed, see “Performing Chip Erase” on page 323. 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable EEPROM write using programming instruction 4a. 3. Load address High byte using programming instruction 4b. 4. Load address Low byte using programming instruction 4c. 5. Load data using programming instructions 4d and 4e. 6. Repeat steps 4 and 5 for all data bytes in the page. 7. Write the data using programming instruction 4f. 8. Poll for EEPROM write complete using programming instruction 4g, or wait for tWLRH (refer to Table 27-12 on page 307). 9. Repeat steps 3 to 8 until all data have been programmed. Note that the PROG_PAGELOAD instruction can not be used when programming the EEPROM. 27.8.19 Reading the EEPROM 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable EEPROM read using programming instruction 5a. 3. Load address using programming instructions 5b and 5c. 4. Read data using programming instruction 5d. 5. Repeat steps 3 and 4 until all data have been read. Note that the PROG_PAGEREAD instruction can not be used when reading the EEPROM. 27.8.20 Programming the Fuses 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse write using programming instruction 6a. 3. Load data high byte using programming instructions 6b. A bit value of “0” will program the corresponding fuse, a “1” will unprogram the fuse. 4. Write Fuse High byte using programming instruction 6c. 5. Poll for Fuse write complete using programming instruction 6d, or wait for tWLRH (refer to Table 27-12 on page 307). 6. Load data low byte using programming instructions 6e. A “0” will program the fuse, a “1” will unprogram the fuse. 7. Write Fuse low byte using programming instruction 6f.325 2552K–AVR–04/11 ATmega329/3290/649/6490 8. Poll for Fuse write complete using programming instruction 6g, or wait for tWLRH (refer to Table 27-12 on page 307). 27.8.21 Programming the Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Lock bit write using programming instruction 7a. 3. Load data using programming instructions 7b. A bit value of “0” will program the corresponding lock bit, a “1” will leave the lock bit unchanged. 4. Write Lock bits using programming instruction 7c. 5. Poll for Lock bit write complete using programming instruction 7d, or wait for tWLRH (refer to Table 27-12 on page 307). Reading the Fuses and Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse/Lock bit read using programming instruction 8a. 3. To read all Fuses and Lock bits, use programming instruction 8e. To only read Fuse High byte, use programming instruction 8b. To only read Fuse Low byte, use programming instruction 8c. To only read Lock bits, use programming instruction 8d. Reading the Signature Bytes 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Signature byte read using programming instruction 9a. 3. Load address 0x00 using programming instruction 9b. 4. Read first signature byte using programming instruction 9c. 5. Repeat steps 3 and 4 with address 0x01 and address 0x02 to read the second and third signature bytes, respectively. Reading the Calibration Byte 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Calibration byte read using programming instruction 10a. 3. Load address 0x00 using programming instruction 10b. Read the calibration byte using programming instruction 10c.326 2552K–AVR–04/11 ATmega329/3290/649/6490 28. Electrical Characteristics 28.1 Absolute Maximum Ratings* 28.2 DC Characteristics Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Maximum Operating Voltage ............................................ 6.0V DC Current per I/O Pin ................................................ 40.0mA DC Current VCC and GND Pins................................. 200.0mA Table 28-1. TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) Symbol Parameter Condition Min. Typ. Max. Units VIL Input Low Voltage, Except XTAL1 pin VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V -0.5 -0.5 0.2VCC(1) 0.3VCC(1) V VIL1 Input Low Voltage, XTAL1 pin VCC = 1.8V - 5.5V -0.5 0.1VCC(1) V VIH Input High Voltage, Except XTAL1 and RESET pins VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V 0.7VCC(2) 0.6VCC(2) VCC + 0.5 VCC + 0.5 V VIH1 Input High Voltage, XTAL1 pin VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V 0.8VCC(2) 0.7VCC(2) VCC + 0.5 VCC + 0.5 V VIH2 Input High Voltage, RESET pin VCC = 1.8V - 5.5V 0.85VCC(2) VCC + 0.5 V VOL Output Low Voltage(3), Port A, C, D, E, F, G, H, J IOL = 10mA, VCC = 5V IOL = 5mA, VCC = 3V 0.7 0.5 V VOL1 Output Low Voltage(3), Port B I OL = 20mA, VCC = 5V IOL = 10mA, VCC = 3V 0.7 0.5 V VOH Output High Voltage(4), Port A, C, D, E, F, G, H, J IOH = -10mA, VCC = 5V IOH = -5mA, VCC = 3V 4.2 2.3 V VOH1 Output High Voltage(4), Port B IOH = -20mA, VCC = 5V IOH = -10mA, VCC = 3V 4.2 2.3 V IIL Input Leakage Current I/O Pin VCC = 5.5V, pin low (absolute value) 1 µA IIH Input Leakage Current I/O Pin VCC = 5.5V, pin high (absolute value) 1 µA RRST Reset Pull-up Resistor 20 100 kΩ RPU I/O Pin Pull-up Resistor 20 100 kΩ327 2552K–AVR–04/11 ATmega329/3290/649/6490 Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low 2. “Min” means the lowest value where the pin is guaranteed to be read as high 3. Although each I/O port can sink more than the test conditions (20mA at VCC = 5V, 10mA at VCC = 3V for Port B and 10mA at VCC = 5V, 5mA at VCC = 3V for all other ports) under steady state conditions (non-transient), the following must be observed: TQFP and QFN/MLF Package: 1] The sum of all IOL, for all ports, should not exceed 400 mA. 2] The sum of all IOL, for ports A0 - A7, C4 - C7, G2 should not exceed 100mA. 3] The sum of all IOL, for ports B0 - B7, E0 - E7, G3 - G5 should not exceed 100mA. 4] The sum of all IOL, for ports D0 - D7, C0 - C3, G0 - G1 should not exceed 100mA. 5] The sum of all IOL, for ports F0 - F7, should not exceed 100mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test conditions (20 mA at VCC = 5V, 10 mA at VCC = 3V for Port B and 10mA at VCC = 5V, 5mA at VCC = 3V for all other ports) under steady state conditions (non-transient), the following must be observed: TQFP and QFN/MLF Package: 1] The sum of all IOL, for all ports, should not exceed 400mA. 2] The sum of all IOL, for ports A0 - A7, C4 - C7, G2 should not exceed 100mA. 3] The sum of all IOL, for ports B0 - B7, E0 - E7, G3 - G5 should not exceed 100mA. 4] The sum of all IOL, for ports D0 - D7, C0 - C3, G0 - G1 should not exceed 100mA. 5] The sum of all IOL, for ports F0 - F7, should not exceed 100 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. Typical values at 25°C. ICC Power Supply Current Active 1MHz, VCC = 2V 1.5 mA Active 4MHz, VCC = 3V 3.5 mA Active 8MHz, VCC = 5V 12 mA Idle 1MHz, VCC = 2V 0.45 mA Idle 4MHz, VCC = 3V 1.5 mA Idle 8MHz, VCC = 5V 5.5 mA Power-down mode(5) WDT enabled, VCC = 3V 7 15 µA WDT disabled, VCC = 3V 0.25 2 µA VACIO Analog Comparator Input Offset Voltage VCC = 5V Vin = VCC/2 <10 40 mV IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/2 -50 50 nA tACID Analog Comparator Propagation Delay VCC = 2.7V VCC = 4.0V 750 500 ns Table 28-1. TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition Min. Typ. Max. Units328 2552K–AVR–04/11 ATmega329/3290/649/6490 28.3 Speed Grades Figure 28-1. Maximum Frequency vs. VCC (4 - 8MHz). Figure 28-2. Maximum Frequency vs. VCC (8 - 16MHz). 8 MHz 4 MHz 1.8V 2.7V 5.5V Safe Operating Area 16 MHz 8 MHz 2.7V 4.5V 5.5V Safe Operating Area329 2552K–AVR–04/11 ATmega329/3290/649/6490 28.4 Clock Characteristics 28.4.1 Calibrated Internal RC Oscillator Accuracy Notes: 1. Voltage range for ATmega329V/3290V/649V/6490V. 2. Voltage range for ATmega329/3290/649/6490. 28.4.2 External Clock Drive Waveforms Figure 28-3. External Clock Drive Waveforms 28.4.3 External Clock Drive Table 28-2. Calibration Accuracy of Internal RC Oscillator Frequency VCC Temperature Calibration Accuracy Factory Calibration 8.0MHz 3V 25°C ±10% User Calibration 7.3 - 8.1MHz 1.8V - 5.5V(1) 2.7V - 5.5V(2) -40°C - 85°C ±1% VIL1 VIH1 Table 28-3. External Clock Drive Symbol Parameter VCC=1.8-5.5V VCC=2.7-5.5V VCC=4.5-5.5V Min. Max. Min. Max. Min. Max. Units 1/tCLCL Oscillator Frequency 040 8 0 16 MHz tCLCL Clock Period 1000 125 62.5 ns tCHCX High Time 400 50 25 ns tCLCX Low Time 400 50 25 ns tCLCH Rise Time 2.0 1.6 0.5 μs tCHCL Fall Time 2.0 1.6 0.5 μs ΔtCLCL Change in period from one clock cycle to the next 2 2 2%330 2552K–AVR–04/11 ATmega329/3290/649/6490 28.5 System and Reset Characteristics Notes: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling) Notes: 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-Out Reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 10 for ATmega329/3290/649/6490V and BODLEVEL = 01 for ATmega329/3290/649/6490L. Table 28-4. Reset, Brown-out, and Internal Voltage Reference Characteristics Symbol Parameter Condition Min Typ Max Units VPOT Power-on Reset Threshold Voltage (rising) TA = -40°C to 85°C 0.7 1.0 1.4 V Power-on Reset Threshold Voltage (falling)(1) TA = -40°C to 85°C 0.05 0.9 1.3 V VPSR Power-on Slope Rate 0.01 4.5 V/ms VRST RESET Pin Threshold Voltage VCC = 3V 0.2 VCC 0.85 VCC V t RST Minimum pulse width on RESET Pin VCC = 3V 800 ns VHYST Brown-out Detector Hysteresis 50 mV tBOD Min Pulse Width on Brown-out Reset 2 µs VBG Bandgap reference voltage VCC = 2.7V, TA = 25°C 1.0 1.1 1.2 V t BG Bandgap reference start-up time VCC = 2.7V, TA = 25°C 40 70 µs I BG Bandgap reference current consumption VCC = 2.7V, TA = 25°C 15 µA Table 28-5. BODLEVEL Fuse Coding(1) BODLEVEL 1:0 Fuses Min VBOT Typ VBOT Max VBOT Units 11 BOD Disabled 10 1.7 1.8 2.0 01 2.5 2.7 2.9 V 00 4.1 4.3 4.5331 2552K–AVR–04/11 ATmega329/3290/649/6490 28.6 SPI Timing Characteristics See Figure 28-4 and Figure 28-5 for details. Note: 1. In SPI Programming mode the minimum SCK high/low period is: - 2 tCLCL for fCK < 12MHz - 3 tCLCL for fCK > 12MHz Figure 28-4. SPI Interface Timing Requirements (Master Mode) Table 28-6. SPI Timing Parameters Description Mode Min Typ Max 1 SCK period Master See Table 18-5 ns 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.5 • tsck 7 SCK to out Master 10 8 SCK to out high Master 10 9 SS low to out Slave 15 10 SCK period Slave 4 • tck 11 SCK high/low(1) Slave 2 • tck 12 Rise/Fall time Slave 1.6 µs 13 Setup Slave 10 ns 14 Hold Slave tck 15 SCK to out Slave 15 16 SCK to SS high Slave 20 17 SS high to tri-state Slave 10 18 SS low to SCK Slave 20 • tck MOSI (Data Output) SCK (CPOL = 1) MISO (Data Input) SCK (CPOL = 0) SS MSB LSB MSB LSB ... ... 6 1 2 2 4 5 3 7 8332 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 28-5. SPI Interface Timing Requirements (Slave Mode) MISO (Data Output) SCK (CPOL = 1) MOSI (Data Input) SCK (CPOL = 0) SS MSB LSB MSB LSB ... ... 10 11 11 13 14 12 15 17 9 X 16333 2552K–AVR–04/11 ATmega329/3290/649/6490 28.7 ADC Characteristics Table 28-7. ADC Characteristics Symbol Parameter Condition Min Typ Max Units Resolution Single Ended Conversion 10 Bits Differential Conversion 8 Bits Absolute accuracy (Including INL, DNL, quantization error, gain and offset error) Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200kHz 2 2.5 LSB Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 1MHz 4.5 LSB Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200kHz Noise Reduction Mode 2 LSB Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 1MHz Noise Reduction Mode 4.5 LSB Integral Non-Linearity (INL) Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200kHz 0.5 LSB Differential Non-Linearity (DNL) Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200kHz 0.25 LSB Gain Error Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200kHz 2 LSB Offset Error Single Ended Conversion VREF = 4V, VCC = 4V, ADC clock = 200kHz 2 LSB Conversion Time Free Running Conversion 13 260 µs Clock Frequency Single Ended Conversion 50 1000 kHz AVCC Analog Supply Voltage VCC - 0.3 VCC + 0.3 V VREF Reference Voltage Single Ended Conversion 1.0 AVCC V Differential Conversion 1.0 AVCC - 0.5 V VIN Pin Input Voltage Single Ended Channels GND VREF V Differential Channels GND AVCC V Input Range Single Ended Channels GND VREF V Differential Channels(1) -0.85VREF VREF V Input Bandwidth Single Ended Channels 38.5 kHz Differential Channels 4 kHz334 2552K–AVR–04/11 ATmega329/3290/649/6490 Note: 1. Voltage difference between channels. 28.8 LCD Controller Characteristics VINT Internal Voltage Reference 1.0 1.1 1.2 V RREF Reference Input Resistance 32 kΩ RAIN Analog Input Resistance 100 MΩ Table 28-8. LCD Controller Characteristics Symbol Parameter Condition Min. Typ Max Units ILCD LCD Driver Current Total for All COM and SEG pins 6 µA RSEG Segment Driver Output Impedance 10 kΩ RCOM Blackplane Driver Output Impedance 2 kΩ Table 28-7. ADC Characteristics (Continued) Symbol Parameter Condition Min Typ Max Units335 2552K–AVR–04/11 ATmega329/3290/649/6490 29. Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. All Active- and Idle current consumption measurements are done with all bits in the PRR register set and thus, the corresponding I/O modules are turned off. Also the Analog Comparator is disabled during these measurements. See “Power Reduction Register” on page 37 for details. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. 29.0.1 Active Supply Current Figure 29-1. Active Supply Current vs. Frequency (0.1 - 1.0MHz) 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) ICC (m A)336 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 29-2. Active Supply Current vs. Frequency (1 - 16MHz)) Figure 29-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16 Frequency (MHz) ICC (mA) 0 2 4 6 8 10 12 14 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 85°C 25°C -40°C337 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 29-4. Active Supply Current vs. VCC (Internal RC Oscillator, CKDIV8 Programmed, 1MHz) Figure 29-5. Active Supply Current vs. VCC (32kHz External Oscillator) 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 85°C 25°C -40°C 85 °C 25 °C -40 °C 0 10 20 30 40 50 60 70 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA)338 2552K–AVR–04/11 ATmega329/3290/649/6490 29.0.2 Idle Supply Current Figure 29-6. Idle Supply Current vs. Frequency (0.1 - 1.0MHz) Figure 29-7. Idle Supply Current vs. Frequency (1 - 16MHz) 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) ICC (mA) 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 0 1 2 3 4 5 6 0 2 4 6 8 10 12 14 16 Frequency (MHz) ICC (mA) 1.8 V339 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 29-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) Figure 29-9. Idle Supply Current vs. VCC (Internal RC Oscillator, CKDIV8 Programmed, 1 MHz) 0 1 2 3 4 5 6 7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 85°C 25°C -40°C 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 85 C° 25 C° -40 C°340 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 29-10. Idle Supply Current vs. VCC (32kHz External Oscillator) 29.0.3 Supply Current of I/O modules The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction Register. See “Power Reduction Register” on page 37 for details. It is possible to calculate the typical current consumption based on the numbers from Table 29-2 for other VCC and frequency settings than listed in Table 29-1. 85 °C 25 °C -40 °C 0 5 10 15 20 25 30 35 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA) Table 29-1. Additional Current Consumption for the different I/O modules (absolute values) PRR bit Typical numbers VCC = 2V, F = 1MHz VCC = 3V, F = 4MHz VCC = 5V, F = 8MHz PRADC 17µA 116µA 562µA PRUSART0 9µA 59µA 248µA PRSPI 10µA 62µA 257µA PRTIM1 5µA 33µA 135µA PRLCD 6µA 36µA 146µA Table 29-2. Additional Current Consumption (percentage) in Active and Idle mode PRR bit Additional Current consumption compared to Active with external clock (see Figure 29-1 and Figure 29-2) Additional Current consumption compared to Idle with external clock (see Figure 29-6 and Figure 29-7) PRADC 5.4% 16.8% PRUSART0 2.7% 8.5% PRSPI 2.9% 9.0% PRTIM1 1.5% 4.8% PRLCD 1.7% 5.2%341 2552K–AVR–04/11 ATmega329/3290/649/6490 29.0.3.1 Example Calculate the expected current consumption in idle mode with USART0, TIMER1, and SPI enabled at VCC = 3.0V and F = 1MHz. Table 29-2 shows that we need to add 8.5% for the USART0, 9% for the SPI, and 4.8% for the TIMER1 module. From Figure 29-6, we find that the idle current consumption is ~0.16mA at VCC = 3.0V and F = 1MHz. The total current consumption in idle mode with USART0, TIMER1, and SPI enabled, gives: 29.0.4 Power-down Supply Current Figure 29-11. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) Figure 29-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) ICCtotal ≈ ≈ 0.16mA • ( ) 1 0.0 + ++ 85 0.09 0.048 0.20mA 85 °C 25 °C -40 °C 0 0.5 1 1.5 2 2.5 3 3.5 4 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA) 85 °C 25 °C -40 °C 0 2 4 6 8 10 12 14 16 18 20 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA)342 2552K–AVR–04/11 ATmega329/3290/649/6490 29.0.5 Power-save Supply Current Figure 29-13. Power-save Supply Current vs. VCC (Watchdog Timer Disabled) 29.0.6 Standby Supply Current Figure 29-14. Standby Supply Current vs. VCC (Low Power Crystal Oscillator) 0 5 10 15 20 25 30 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA) 85°C 25°C 6MHz Xtal 6MHz Res. 4MHz Xtal 4MHz Res. 455kHz Res. 32kHz Xtal 2MHz Xtal 2MHz Res. 1MHz Res. 0 20 40 60 80 100 120 140 160 180 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA)343 2552K–AVR–04/11 ATmega329/3290/649/6490 29.0.7 Pin Pull-up Figure 29-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) Figure 29-16. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 0 20 40 60 80 100 120 140 160 012345 VIO (V) IIO (uA) 85°C 25°C -40°C 0 10 20 30 40 50 60 70 80 90 0 0.5 1 1.5 2 2.5 3 VIO (V) IIO (uA) 85°C 25°C -40°C344 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 29-17. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V) Figure 29-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) 0 10 20 30 40 50 60 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOP (V) IOP (uA) 85°C 25°C -40°C 0 20 40 60 80 100 120 012345 VRESET (V) IRESET (uA) -40°C 25°C 85°C345 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 29-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) Figure 29-20. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 0 10 20 30 40 50 60 70 0 0.5 1 1.5 2 2.5 3 VRESET (V) IRESET (uA) -40°C 25°C 85°C 0 5 10 15 20 25 30 35 40 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VRESET (V) IRESET (uA) -40°C 25°C 85°C346 2552K–AVR–04/11 ATmega329/3290/649/6490 29.0.8 Pin Driver Strength Figure 29-21. I/O Pin Source Current vs. Output Voltage, Ports A, C, D, E, F, G, H, J (VCC = 5V) Figure 29-22. I/O Pin Source Current vs. Output Voltage, Ports A, C, D, E, F, G, H, J (VCC = 2.7V) 0 10 20 30 40 50 60 70 0123456 VOH (V) IOH (mA) 85°C 25°C -40°C 0 5 10 15 20 25 0 0.5 1 1.5 2 2.5 3 VOH (V) IOH (mA) 85°C 25°C -40°C347 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 29-23. I/O Pin Source Current vs. Output Voltage, Ports A, C, D, E, F, G, H, J (VCC = 1.8V) Figure 29-24. I/O Pin Source Current vs. Output Voltage, Port B (VCC= 5V) 0 1 2 3 4 5 6 7 8 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOH (V) IOH (mA) 85°C 25°C -40°C 0 10 20 30 40 50 60 70 80 01234 VOH (V) IOH (mA) 85°C 25°C -40°C348 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 29-25. I/O Pin Source Current vs. Output Voltage, Port B (VCC = 2.7V) Figure 29-26. I/O Pin Source Current vs. Output Voltage, Port B (VCC = 1.8V) 0 5 10 15 20 25 30 35 0 0.5 1 1.5 2 2.5 3 VOH (V) IOH (mA) 85°C 25°C -40°C 0 1 2 3 4 5 6 7 8 9 10 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOH (V) IOH (mA) 85°C 25°C -40°C349 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 29-27. I/O Pin Sink Current vs. Output Voltage, Ports A, C, D, E, F, G, H, J (VCC = 5V) Figure 29-28. I/O Pin Sink Current vs. Output Voltage, Ports A, C, D, E, F, G, H, J (VCC = 2.7V) 0 5 10 15 20 25 30 35 40 45 50 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) IOL (mA) 85°C 25°C -40°C 0 2 4 6 8 10 12 14 16 18 20 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) IOL (mA) 85°C 25°C -40°C350 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 29-29. I/O Pin Sink Current vs. Output Voltage, Ports A, C, D, E, F, G, H, J (VCC = 1.8V) Figure 29-30. I/O Pin Sink Current vs. Output Voltage, Port B (VCC = 5V) 0 1 2 3 4 5 6 7 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) IOL (mA) 85°C 25°C -40°C 0 10 20 30 40 50 60 70 80 90 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) IOL (mA) 85°C 25°C -40°C351 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 29-31. I/O Pin Sink Current vs. Output Voltage, Port B (VCC = 2.7V) Figure 29-32. I/O Pin Sink Current vs. Output Voltage, Port B (VCC = 1.8V) 0 5 10 15 20 25 30 35 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) IOL (mA) 85°C 25°C -40°C 0 2 4 6 8 10 12 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VOL (V) IOL (mA) 85°C 25°C -40°C352 2552K–AVR–04/11 ATmega329/3290/649/6490 29.0.9 Pin Thresholds and hysteresis Figure 29-33. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) Figure 29-34. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V) 85°C 25°C -40°C 0 0.5 1 1.5 2 2.5 3 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V) 85°C 25°C -40°C353 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 29-35. I/O Pin Input Hysteresis vs. VCC Figure 29-36. Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) 0 0.1 0.2 0.3 0.4 0.5 0.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) 85°C 25°C -40°C Input Hysteresis (V) 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V) 85°C 25°C -40°C354 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 29-37. Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) Figure 29-38. Reset Input Pin Hysteresis vs. VCC 0 0.5 1 1.5 2 2.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V) 85°C 25°C -40°C 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Input Hysteresis (V) 85°C 25°C -40°C355 2552K–AVR–04/11 ATmega329/3290/649/6490 29.0.10 BOD Thresholds and Analog Comparator Offset Figure 29-39. BOD Thresholds vs. Temperature (BOD Level is 4.3V) Figure 29-40. BOD Thresholds vs. Temperature (BOD Level is 2.7V) Rising VCC Falling VCC 4 4.1 4.2 4.3 4.4 4.5 4.6 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) Threshold (V) Rising VCC Falling VCC 2.4 2.5 2.6 2.7 2.8 2.9 3 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) Threshol d ( V)356 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 29-41. BOD Thresholds vs. Temperature (BOD Level is 1.8V) Figure 29-42. Bandgap Voltage vs. VCC 1.7 1.75 1.8 1.85 1.9 1.95 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) Threshold (V) Rising VCC Falling VCC 85°C 25°C -40°C 1.068 1.069 1.07 1.071 1.072 1.073 1.074 1.075 1.076 1.5 2 2.5 3 3.5 4 4.5 5 VCC (V) Bandgap Voltage (V)357 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 29-43. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V) Figure 29-44. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 2.7V) 85°C 25°C -40°C 0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Common Mode Voltage (V) Comparator Offset Voltage (V) 85°C 25°C 0 -40°C 0.0005 0.001 0.0015 0.002 0.0025 0.003 0.0035 0 0.5 1 1.5 2 2.5 3 Common Mode Voltage (V) Comparator Offset Voltage (V)358 2552K–AVR–04/11 ATmega329/3290/649/6490 29.0.11 Internal Oscillator Speed Figure 29-45. Watchdog Oscillator Frequency vs. VCC Figure 29-46. Calibrated 8MHz RC Oscillator Frequency vs. Temperature 85 °C 25 °C -40 °C 1000 1050 1100 1150 1200 1250 1300 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) FRC (kHz) 5.5 V 4.5 V 3.3 V 2.7 V 1.8 V 7.2 7.4 7.6 7.8 8 8.2 8.4 8.6 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) FRC (M Hz)359 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 29-47. Calibrated 8MHz RC Oscillator Frequency vs. VCC Figure 29-48. Calibrated 8MHz RC Oscillator Frequency vs. Osccal Value 85 °C 25 °C -40 °C 7.2 7.4 7.6 7.8 8 8.2 8.4 8.6 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) FRC (MHz) 85 °C 25 °C -40 °C 4 6 8 10 12 14 16 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL VALUE FRC (M Hz)360 2552K–AVR–04/11 ATmega329/3290/649/6490 29.0.12 Current Consumption of Peripheral Units Figure 29-49. Brownout Detector Current vs. VCC Figure 29-50. ADC Current vs. VCC (AREF = AVCC) 85 °C 25 °C -40 °C 0 5 10 15 20 25 30 35 40 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA) 0 50 100 150 200 250 300 350 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA) 85°C 25°C -40°C361 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 29-51. AREF External Reference Current vs. VCC Figure 29-52. 32kHz TOSC Current vs. VCC (Watchdog Timer Disabled) 0 20 40 60 80 100 120 140 160 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) IAREF (uA) 85°C 25°C -40°C 0 5 10 15 20 25 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA) 85°C 25°C362 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 29-53. Watchdog Timer Current vs. VCC Figure 29-54. Analog Comparator Current vs. VCC 0 2 4 6 8 10 12 14 16 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA) 85°C 25°C -40°C 0 20 40 60 80 100 120 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA) 85°C 25°C -40°C363 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 29-55. Programming Current vs. VCC 29.0.13 Current Consumption in Reset and Reset Pulsewidth Figure 29-56. Reset Supply Current vs. VCC (0.1 - 1.0MHz, Excluding Current Through The Reset Pull-up) 85 °C 25 °C -40 °C 0 2 4 6 8 10 12 14 16 18 20 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) ICC (mA)364 2552K–AVR–04/11 ATmega329/3290/649/6490 Figure 29-57. Reset Supply Current vs. VCC (1 - 16MHz, Excluding Current Through The Reset Pull-up) Figure 29-58. Reset Pulse Width vs. VCC 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0 0.5 1 1.5 2 2.5 3 0 2 4 6 8 10 12 14 16 Frequency (MHz) ICC (mA) 0 500 1000 1500 2000 2500 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Pulsewidth (ns) 85°C 25°C -40°C365 2552K–AVR–04/11 ATmega329/3290/649/6490 30. Register Summary Note: Registers with bold type only available in ATmega3290/6490. Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xFF) LCDDR19 SEG339 SEG338 SEG337 SEG336 SEG335 SEG334 SEG333 SEG332 244 (0xFE) LCDDR18 SEG331 SEG330 SEG329 SEG328 SEG327 SEG326 SEG325 SEG324 244 (0xFD) LCDDR17 SEG323 SEG322 SEG321 SEG320 SEG319 SEG318 SEG317 SEG316 244 (0xFC) LCDDR16 SEG315 SEG314 SEG313 SEG312 SEG311 SEG310 SEG309 SEG308 244 (0xFB) LCDDR15 SEG307 SEG306 SEG305 SEG304 SEG303 SEG302 SEG301 SEG300 244 (0xFA) LCDDR14 SEG239 SEG238 SEG237 SEG236 SEG235 SEG234 SEG233 SEG232 244 (0xF9) LCDDR13 SEG231 SEG230 SEG229 SEG228 SEG227 SEG226 SEG225 SEG224 244 (0xF8) LCDDR12 SEG223 SEG222 SEG221 SEG220 SEG219 SEG218 SEG217 SEG216 244 (0xF7) LCDDR11 SEG215 SEG214 SEG213 SEG212 SEG211 SEG210 SEG209 SEG208 244 (0xF6) LCDDR10 SEG207 SEG206 SEG205 SEG204 SEG203 SEG202 SEG201 SEG200 244 (0xF5) LCDDR09 SEG139 SEG138 SEG137 SEG136 SEG135 SEG134 SEG133 SEG132 244 (0xF4) LCDDR08 SEG131 SEG130 SEG129 SEG128 SEG127 SEG126 SEG125 SEG124 244 (0xF3) LCDDR07 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 244 (0xF2) LCDDR06 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 244 (0xF1) LCDDR05 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 244 (0xF0) LCDDR04 SEG039 SEG038 SEG037 SEG036 SEG035 SEG034 SEG033 SEG032 244 (0xEF) LCDDR03 SEG031 SEG030 SEG029 SEG028 SEG027 SEG026 SEG025 SEG024 244 (0xEE) LCDDR02 SEG023 SEG022 SEG021 SEG020 SEG019 SEG018 SEG017 SEG016 244 (0xED) LCDDR01 SEG015 SEG014 SEG013 SEG012 SEG011 SEG010 SEG009 SEG008 244 (0xEC) LCDDR00 SEG007 SEG006 SEG005 SEG004 SEG003 SEG002 SEG001 SEG000 244 (0xEB) Reserved - - - - - - - - (0xEA) Reserved - - - - - - - - (0xE9) Reserved - - - - - - - - (0xE8) Reserved - - - - - - - - (0xE7) LCDCCR LCDDC2 LCDDC1 LCDDC0 - LCDCC3 LCDCC2 LCDCC1 LCDCC0 243 (0xE6) LCDFRR - LCDPS2 LCDPS1 LCDPS0 - LCDCD2 LCDCD1 LCDCD0 241 (0xE5) LCDCRB LCDCS LCD2B LCDMUX1 LCDMUX0 LCDPM3 LCDPM2 LCDPM1 LCDPM0 239 (0xE4) LCDCRA LCDEN LCDAB - LCDIF LCDIE - - LCDBL 239 (0xE3) Reserved - - - - - - - - (0xE2) Reserved - - - - - - - - (0xE1) Reserved - - - - - - - - (0xE0) Reserved - - - - - - - - (0xDF) Reserved - - - - - - - - (0xDE) Reserved - - - - - - - - (0xDD) PORTJ - PORTJ6 PORTJ5 PORTJ4 PORTJ3 PORTJ2 PORTJ1 PORTJ0 90 (0xDC) DDRJ - DDJ6 DDJ5 DDJ4 DDJ3 DDJ2 DDJ1 DDJ0 90 (0xDB) PINJ - PINJ6 PINJ5 PINJ4 PINJ3 PINJ2 PINJ1 PINJ0 90 (0xDA) PORTH PORTH7 PORTH6 PORTH5 PORTH4 PORTH3 PORTH2 PORTH1 PORTH0 89 (0xD9) DDRH DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 90 (0xD8) PINH PINH7 PINH6 PINH5 PINH4 PINH3 PINH2 PINH1 PINH0 90 (0xD7) Reserved - - - - - - - - (0xD6) Reserved - - - - - - - - (0xD5) Reserved - - - - - - - - (0xD4) Reserved - - - - - - - - (0xD3) Reserved - - - - - - - - (0xD2) Reserved - - - - - - - - (0xD1) Reserved - - - - - - - - (0xD0) Reserved - - - - - - - - (0xCF) Reserved - - - - - - - - (0xCE) Reserved - - - - - - - - (0xCD) Reserved - - - - - - - - (0xCC) Reserved - - - - - - - - (0xCB) Reserved - - - - - - - - (0xCA) Reserved - - - - - - - - (0xC9) Reserved - - - - - - - - (0xC8) Reserved - - - - - - - - (0xC7) Reserved - - - - - - - - (0xC6) UDR0 USART0 Data Register 190 (0xC5) UBRR0H USART0 Baud Rate Register High 194 (0xC4) UBRR0L USART0 Baud Rate Register Low 194366 2552K–AVR–04/11 ATmega329/3290/649/6490 (0xC3) Reserved - - - - - - - - (0xC2) UCSR0C - UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 192 (0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 191 (0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 190 (0xBF) Reserved - - - - - - - - (0xBE) Reserved - - - - - - - - (0xBD) Reserved - - - - - - - - (0xBC) Reserved - - - - - - - - (0xBB) Reserved - - - - - - - - (0xBA) USIDR USI Data Register 203 (0xB9) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 203 (0xB8) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC 204 (0xB7) Reserved - - - - - - - - (0xB6) ASSR - - - EXCLK AS2 TCN2UB OCR2UB TCR2UB 155 (0xB5) Reserved - - - - - - - - (0xB4) Reserved - - - - - - - - (0xB3) OCR2A Timer/Counter 2 Output Compare Register A 155 (0xB2) TCNT2 Timer/Counter2 155 (0xB1) Reserved - - - - - - - - (0xB0) TCCR2A FOC2A WGM20 COM2A1 COM2A0 WGM21 CS22 CS21 CS20 153 (0xAF) Reserved - - - - - - - - (0xAE) Reserved - - - - - - - - (0xAD) Reserved - - - - - - - - (0xAC) Reserved - - - - - - - - (0xAB) Reserved - - - - - - - - (0xAA) Reserved - - - - - - - - (0xA9) Reserved - - - - - - - - (0xA8) Reserved - - - - - - - - (0xA7) Reserved - - - - - - - - (0xA6) Reserved - - - - - - - - (0xA5) Reserved - - - - - - - - (0xA4) Reserved - - - - - - - - (0xA3) Reserved - - - - - - - - (0xA2) Reserved - - - - - - - - (0xA1) Reserved - - - - - - - - (0xA0) Reserved - - - - - - - - (0x9F) Reserved - - - - - - - - (0x9E) Reserved - - - - - - - - (0x9D) Reserved - - - - - - - - (0x9C) Reserved - - - - - - - - (0x9B) Reserved - - - - - - - - (0x9A) Reserved - - - - - - - - (0x99) Reserved - - - - - - - - (0x98) Reserved - - - - - - - - (0x97) Reserved - - - - - - - - (0x96) Reserved - - - - - - - - (0x95) Reserved - - - - - - - - (0x94) Reserved - - - - - - - - (0x93) Reserved - - - - - - - - (0x92) Reserved - - - - - - - - (0x91) Reserved - - - - - - - - (0x90) Reserved - - - - - - - - (0x8F) Reserved - - - - - - - - (0x8E) Reserved - - - - - - - - (0x8D) Reserved - - - - - - - - (0x8C) Reserved - - - - - - - - (0x8B) OCR1BH Timer/Counter1 Output Compare Register B High 136 (0x8A) OCR1BL Timer/Counter1 Output Compare Register B Low 136 (0x89) OCR1AH Timer/Counter1 Output Compare Register A High 136 (0x88) OCR1AL Timer/Counter1 Output Compare Register A Low 136 (0x87) ICR1H Timer/Counter1 Input Capture Register High 137 (0x86) ICR1L Timer/Counter1 Input Capture Register Low 137 (0x85) TCNT1H Timer/Counter1 High 136 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page367 2552K–AVR–04/11 ATmega329/3290/649/6490 (0x84) TCNT1L Timer/Counter1 Low 136 (0x83) Reserved - - - - - - - - (0x82) TCCR1C FOC1A FOC1B - - - - - - 135 (0x81) TCCR1B ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS10 134 (0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 - - WGM11 WGM10 132 (0x7F) DIDR1 - - - - - - AIN1D AIN0D 210 (0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 227 (0x7D) Reserved - - - - - - - - (0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 223 (0x7B) ADCSRB - ACME - - - ADTS2 ADTS1 ADTS0 209/227 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 225 (0x79) ADCH ADC Data Register High 226 (0x78) ADCL ADC Data Register Low 226 (0x77) Reserved - - - - - - - - (0x76) Reserved - - - - - - - - (0x75) Reserved - - - - - - - - (0x74) Reserved - - - - - - - - (0x73) PCMSK3 - PCINT30 PCINT29 PCINT28 PCINT27 PCINT26 PCINT25 PCINT24 57 (0x72) Reserved - - - - - - - - (0x71) Reserved - - - - - - - - (0x70) TIMSK2 - - - - - - OCIE2A TOIE2 156 (0x6F) TIMSK1 - - ICIE1 - - OCIE1B OCIE1A TOIE1 137 (0x6E) TIMSK0 - - - - - - OCIE0A TOIE0 106 (0x6D) PCMSK2 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 57 (0x6C) PCMSK1 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 58 (0x6B) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 58 (0x6A) Reserved - - - - - - - - (0x69) EICRA - - - - - - ISC01 ISC00 55 (0x68) Reserved - - - - - - - - (0x67) Reserved - - - - - - - - (0x66) OSCCAL Oscillator Calibration Register [CAL7..0] 32 (0x65) Reserved - - - - - - - - (0x64) PRR - - - PRLCD PRTIM1 PRSPI PSUSART0 PRADC 40 (0x63) Reserved - - - - - - - - (0x62) Reserved - - - - - - - - (0x61) CLKPR CLKPCE - - - CLKPS3 CLKPS2 CLKPS1 CLKPS0 33 (0x60) WDTCR - - - WDCE WDE WDP2 WDP1 WDP0 48 0x3F (0x5F) SREG I T H S V N Z C 12 0x3E (0x5E) SPH Stack Pointer High 14 0x3D (0x5D) SPL Stack Pointer Low 14 0x3C (0x5C) Reserved - - - - - - - - 0x3B (0x5B) Reserved - - - - - - - - 0x3A (0x5A) Reserved - - - - - - - - 0x39 (0x59) Reserved - - - - - - - - 0x38 (0x58) Reserved - - - - - - - - 0x37 (0x57) SPMCSR SPMIE RWWSB - RWWSRE BLBSET PGWRT PGERS SPMEN 291 0x36 (0x56) Reserved 0x35 (0x55) MCUCR JTD - - PUD - - IVSEL IVCE 52/87/254 0x34 (0x54) MCUSR - - - JTRF WDRF BORF EXTRF PORF 47 0x33 (0x53) SMCR - - - - SM2 SM1 SM0 SE 39 0x32 (0x52) Reserved - - - - - - - - 0x31 (0x51) OCDR IDRD/OCDR7 OCDR6 OCDR5 OCDR4 OCDR3 OCDR2 OCDR1 OCDR0 250 0x30 (0x50) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 209 0x2F (0x4F) Reserved - - - - - - - - 0x2E (0x4E) SPDR SPI Data Register 167 0x2D (0x4D) SPSR SPIF WCOL - - - - - SPI2X 167 0x2C (0x4C) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 165 0x2B (0x4B) GPIOR2 General Purpose I/O Register 25 0x2A (0x4A) GPIOR1 General Purpose I/O Register 25 0x29 (0x49) Reserved - - - - - - - - 0x28 (0x48) Reserved - - - - - - - - 0x27 (0x47) OCR0A Timer/Counter0 Output Compare A 105 0x26 (0x46) TCNT0 Timer/Counter0 105 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page368 2552K–AVR–04/11 ATmega329/3290/649/6490 Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega329/3290/649/6490 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 0x25 (0x45) Reserved - - - - - - - - 0x24 (0x44) TCCR0A FOC0A WGM00 COM0A1 COM0A0 WGM01 CS02 CS01 CS00 103 0x23 (0x43) GTCCR TSM - - - - - PSR2 PSR10 108/157 0x22 (0x42) EEARH - - - - - EEPROM Address Register High 22 0x21 (0x41) EEARL EEPROM Address Register Low 22 0x20 (0x40) EEDR EEPROM Data Register 22 0x1F (0x3F) EECR - - - - EERIE EEMWE EEWE EERE 22 0x1E (0x3E) GPIOR0 General Purpose I/O Register 25 0x1D (0x3D) EIMSK PCIE3 PCIE2 PCIE1 PCIE0 - - - INT0 55 0x1C (0x3C) EIFR PCIF3 PCIF2 PCIF1 PCIF0 - - - INTF0 56 0x1B (0x3B) Reserved - - - - - - - - 0x1A (0x3A) Reserved - - - - - - - - 0x19 (0x39) Reserved - - - - - - - - 0x18 (0x38) Reserved - - - - - - - - 0x17 (0x37) TIFR2 - - - - - - OCF2A TOV2 157 0x16 (0x36) TIFR1 - - ICF1 - - OCF1B OCF1A TOV1 138 0x15 (0x35) TIFR0 - - - - - - OCF0A TOV0 106 0x14 (0x34) PORTG - - - PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 89 0x13 (0x33) DDRG - - - DDG4 DDG3 DDG2 DDG1 DDG0 89 0x12 (0x32) PING - - PING5 PING4 PING3 PING2 PING1 PING0 89 0x11 (0x31) PORTF PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0 89 0x10 (0x30) DDRF DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 89 0x0F (0x2F) PINF PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 89 0x0E (0x2E) PORTE PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 88 0x0D (0x2D) DDRE DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 88 0x0C (0x2C) PINE PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 89 0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 88 0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 88 0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 88 0x08 (0x28) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 88 0x07 (0x27) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 88 0x06 (0x26) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 88 0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 87 0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 87 0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 87 0x02 (0x22) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 87 0x01 (0x21) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 87 0x00 (0x20) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 87 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page369 2552K–AVR–04/11 ATmega329/3290/649/6490 31. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1 COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1 NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1 INC Rd Increment Rd ← Rd + 1 Z,N,V 1 DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1 SER Rd Set Register Rd ← 0xFF None 1 MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2 MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2 MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2 FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2 FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr) << 1 Z,C 2 FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2 BRANCH INSTRUCTIONS RJMP k Relative Jump PC ← PC + k + 1 None 2 IJMP Indirect Jump to (Z) PC ← Z None 2 JMP k Direct Jump PC ← k None 3 RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3 ICALL Indirect Call to (Z) PC ← Z None 3 CALL k Direct Subroutine Call PC ← k None 4 RET Subroutine Return PC ← STACK None 4 RETI Interrupt Return PC ← STACK I 4 CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3 CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2370 2552K–AVR–04/11 ATmega329/3290/649/6490 BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1 BSET s Flag Set SREG(s) ← 1 SREG(s) 1 BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) ← T None 1 SEC Set Carry C ← 1 C1 CLC Clear Carry C ← 0 C 1 SEN Set Negative Flag N ← 1 N 1 CLN Clear Negative Flag N ← 0 N 1 SEZ Set Zero Flag Z ← 1 Z1 CLZ Clear Zero Flag Z ← 0 Z 1 SEI Global Interrupt Enable I ← 1 I1 CLI Global Interrupt Disable I ← 0 I 1 SES Set Signed Test Flag S ← 1 S1 CLS Clear Signed Test Flag S ← 0 S 1 SEV Set Twos Complement Overflow. V ← 1 V1 CLV Clear Twos Complement Overflow V ← 0 V 1 SET Set T in SREG T ← 1 T1 CLT Clear T in SREG T ← 0 T 1 SEH Set Half Carry Flag in SREG H ← 1 H1 CLH Clear Half Carry Flag in SREG H ← 0 H 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers Rd ← Rr None 1 MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1 LDI Rd, K Load Immediate Rd ← K None 1 LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2 LD Rd, Y Load Indirect Rd ← (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd ← (k) None 2 ST X, Rr Store Indirect (X) ← Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2 ST Y, Rr Store Indirect (Y) ← Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2 ST Z, Rr Store Indirect (Z) ← Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2 STS k, Rr Store Direct to SRAM (k) ← Rr None 2 LPM Load Program Memory R0 ← (Z) None 3 LPM Rd, Z Load Program Memory Rd ← (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3 SPM Store Program Memory (Z) ← R1:R0 None - Mnemonics Operands Description Operation Flags #Clocks371 2552K–AVR–04/11 ATmega329/3290/649/6490 IN Rd, P In Port Rd ← P None 1 OUT P, Rr Out Port P ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/timer) None 1 BREAK Break For On-chip Debug Only None N/A Mnemonics Operands Description Operation Flags #Clocks372 2552K–AVR–04/11 ATmega329/3290/649/6490 32. Ordering Information Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC see Figure 28-1 on page 328 and Figure 28-2 on page 328. 4. Tape & Reel 32.1 ATmega329 Speed (MHz)(3) Power Supply Ordering Code(2) Package Type(1) Operational Range 8 1.8 - 5.5V ATmega329V-8AU ATmega329V-8AUR(4) ATmega329V-8MU ATmega329V-8MUR(4) 64A 64A 64M1 64M1 Industrial (-40°C to 85°C) 16 2.7 - 5.5V ATmega329-16AU ATmega329-16AUR(4) ATmega329-16MU ATmega329-16MUR(4) 64A 64A 64M1 64M1 Industrial (-40°C to 85°C) Package Type 64A 64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP) 64M1 64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 100A 100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)373 2552K–AVR–04/11 ATmega329/3290/649/6490 Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC see Figure 28-1 on page 328 and Figure 28-2 on page 328. 4. Tape & Reel 32.2 ATmega3290 Speed (MHz)(3) Power Supply Ordering Code(2) Package Type(1) Operational Range 8 1.8 - 5.5V ATmega3290V-8AU ATmega3290V-8AUR(4) 100A 100A Industrial (-40°C to 85°C) 16 2.7 - 5.5V ATmega3290-16AU ATmega3290-16AUR(4) 100A 100A Industrial (-40°C to 85°C) Package Type 64A 64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP) 64M1 64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 100A 100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)374 2552K–AVR–04/11 ATmega329/3290/649/6490 Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC see Figure 28-1 on page 328 and Figure 28-2 on page 328. 4. Tape & Reel 32.3 ATmega649 Speed (MHz)(3) Power Supply Ordering Code(2) Package Type(1) Operational Range 8 1.8 - 5.5V ATmega649V-8AU ATmega649V-8AUR(4) ATmega649V-8MU ATmega649V-8MUR(4) 64A 64A 64M1 64M1 Industrial (-40°C to 85°C) 16 2.7 - 5.5V ATmega649-16AU ATmega649-16AUR(4) ATmega649-16MU ATmega649-16MUR(4) 64A 64A 64M1 64M1 Industrial (-40°C to 85°C) Package Type 64A 64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP) 64M1 64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 100A 100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)375 2552K–AVR–04/11 ATmega329/3290/649/6490 Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed Grades see Figure 28-1 on page 328 and Figure 28-2 on page 328. 4. Tape & Reel 32.4 ATmega6490 Speed (MHz)(3) Power Supply Ordering Code(2) Package Type(1) Operational Range 8 1.8 - 5.5V ATmega6490V-8AU ATmega6490V-8AUR(4) 100A 100A Industrial (-40°C to 85°C) 16 2.7 - 5.5V ATmega6490-16AU ATmega6490-16AUR(4) 100A 100A Industrial (-40°C to 85°C) Package Type 64A 64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP) 64M1 64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 100A 100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)376 2552K–AVR–04/11 ATmega329/3290/649/6490 33. Packaging Information 33.1 64A 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 64A C 2010-10-20 PIN 1 IDENTIFIER 0°~7° PIN 1 L C A1 A2 A D1 D e E1 E B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.00 16.25 D1 13.90 14.00 14.10 Note 2 E 15.75 16.00 16.25 E1 13.90 14.00 14.10 Note 2 B 0.30 – 0.45 C 0.09 – 0.20 L 0.45 – 0.75 e 0.80 TYP377 2552K–AVR–04/11 ATmega329/3290/649/6490 33.2 64M1 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, 64M1 H 2010-10-19 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 0.80 0.90 1.00 A1 – 0.02 0.05 b 0.18 0.25 0.30 D D2 5.20 5.40 5.60 8.90 9.00 9.10 E 8.90 9.00 9.10 E2 5.20 5.40 5.60 e 0.50 BSC L 0.35 0.40 0.45 Notes: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. TOP VIEW SIDE VIEW BOTTOM VIEW D E Marked Pin# 1 ID SEATING PLANE A1 C A 0.08 C 1 2 3 K 1.25 1.40 1.55 E2 D2 b e Pin #1 Corner L Pin #1 Triangle Pin #1 Chamfer (C 0.30) Option A Option B Pin #1 Notch (0.20 R) Option C K K 5.40 mm Exposed Pad, Micro Lead Frame Package (MLF) 378 2552K–AVR–04/11 ATmega329/3290/649/6490 33.3 100A 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 100A D 2010-10-20 PIN 1 IDENTIFIER 0°~7° PIN 1 L C A1 A2 A D1 D e E1 E B A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.00 16.25 D1 13.90 14.00 14.10 Note 2 E 15.75 16.00 16.25 E1 13.90 14.00 14.10 Note 2 B 0.17 – 0.27 C 0.09 – 0.20 L 0.45 – 0.75 e 0.50 TYP Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE379 2552K–AVR–04/11 ATmega329/3290/649/6490 34. Errata 34.1 ATmega329 34.1.1 ATmega329 rev. C • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem Fix/Wortkaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 34.1.2 ATmega329 rev. B Not sampled. 34.1.3 ATmega329 rev. A • LCD contrast voltage too high • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. LCD contrast voltage too high When the LCD is active and using low power waveform, the LCD contrast voltage can be too high. This occurs when VCC is higher than VLCD, and when using low LCD drivetime. Problem Fix/Workaround There are several possible workarounds: - Use normal waveform instead of low power waveform - Use drivetime of 375 µs or longer 2. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem Fix/Wortkaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx).380 2552K–AVR–04/11 ATmega329/3290/649/6490 34.2 ATmega3290 34.2.1 ATmega3290 rev. C • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem Fix/Wortkaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 34.2.2 ATmega3290 rev. B Not sampled. 34.2.3 ATmega3290 rev. A • LCD contrast voltage too high • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. LCD contrast voltage too high When the LCD is active and using low power waveform, the LCD contrast voltage can be too high. This occurs when VCC is higher than VLCD, and when using low LCD drivetime. Problem Fix/Workaround There are several possible workarounds: - Use normal waveform instead of low power waveform - Use drivetime of 375 µs or longer 2. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem Fix/Wortkaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx).381 2552K–AVR–04/11 ATmega329/3290/649/6490 34.3 ATmega649 34.3.1 ATmega649 rev. A • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem Fix/Wortkaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx). 34.4 ATmega6490 34.4.1 ATmega6490 rev. A • Interrupts may be lost when writing the timer registers in the asynchronous timer 1. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronous timer clock is written when the asynchronous Timer/Counter register (TCNTx) is 0x00. Problem Fix/Wortkaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register (TCCRx), asynchronous Timer Counter Register (TCNTx), or asynchronous Output Compare Register (OCRx).382 2552K–AVR–04/11 ATmega329/3290/649/6490 35. Datasheet Revision History Please note that the referring page numbers in this section are referring to this document.The referring revision in this section are referring to the document revision. 35.1 Rev. 2552K – 04/11 35.2 Rev. 2552J – 08/07 35.3 Rev. 2552I – 04/07 35.4 Rev. 2552H – 11/06 1. Removed “Preliminary” from the front page. 2. Removed “Disclaimer Section” from the datasheet. 3. Updated Table 28-5 on page 330 “BODLEVEL Fuse Coding(1)” . 4. Updated Table 28-8 on page 334 “LCD Controller Characteristics” . 5. Updated “Ordering Information” on page 372 to include “Tape & Reel” devices. The “AI” and “MI” devices removed. 6. Updated “Errata” on page 379. 7. Updated the datasheet according to the Atmel new brand style guide, including the last page. 1. Updated “Features” on page 1. 2. Added “Data Retention” on page 9. 3. Updated “Serial Programming Algorithm” on page 309. 4. Updated “Speed Grades” on page 328. 5. Updated “System and Reset Characteristics” on page 330. 6. Moved Register Descriptions to the end of each chapter. 1. Updated date in backpage 2. Updated column in Table 28-5 on page 330. 1. Updated Table 28-7 on page 333. 2. Updated note in Table 28-7 on page 333 and Table 28-2 on page 329.383 2552K–AVR–04/11 ATmega329/3290/649/6490 35.5 Rev. 2552G – 07/06 35.6 Rev. 2552F – 06/06 35.7 Rev. 2552E – 04/06 35.8 Rev. 2552D – 03/06 35.9 Rev. 2552C – 03/06 1. Updated Table 14-2 on page 104, Table 14-4 on page 104, Table 16-3 on page 133, Table 16-5 on page 134, Table 16-5 on page 134, Table 17-2 on page 153 and Table 17-4 on page 154. 2. Updated “Fast PWM Mode” on page 124. 3. Updated Features in “USI – Universal Serial Interface” on page 195. 4. Added “Clock speed considerations.” on page 202. 5. “Errata” on page 379. 1. Updated “Calibrated Internal RC Oscillator” on page 29. 2. Updated “OSCCAL – Oscillator Calibration Register” on page 32 3. Added Table 28-2 on page 329. 1. Updated “Calibrated Internal RC Oscillator” on page 29. 1. Updated “Errata” on page 379. 1. Added “Resources” on page 9. 2. Added Addresses in Registers. 3. Updated number of General Purpose I/O pins. 4. Updated code example in “Bit 0 – IVCE: Interrupt Vector Change Enable” on page 53. 5. Updated Introduction in “I/O-Ports” on page 59. 6. Updated “SPI – Serial Peripheral Interface” on page 158. 7. Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page 209. 8. Updated Features in “Analog to Digital Converter” on page 211. 9. Updated “Prescaling and Conversion Timing” on page 214. 10. Updated features in “LCD Controller” on page 228. 11. Updated “ATmega329/3290/649/6490 Boot Loader Parameters” on page 290. 12. Updated “DC Characteristics” on page 310. 13. Updated “” on page 334.384 2552K–AVR–04/11 ATmega329/3290/649/6490 35.10 Rev. 2552B – 05/05 35.11 Rev. 2552A –11/04 1. MLF-package alternative changed to “Quad Flat No-Lead/Micro Lead Frame Package QFN/MLF”. 2. Added “Pin Change Interrupt Timing” on page 54. 3. Updated Table 23-6 on page 242, Table 23-7 on page 243 and Table 27-15 on page 310. 4. Added Figure 27-12 on page 312. 5. Updated Figure 22-9 on page 219 and Figure 27-5 on page 304. 6. Updated algorithm “Enter Programming Mode” on page 299. 7. Added “Supply Current of I/O modules” on page 340. 8. Updated “Ordering Information” on page 372. 1. Initial version.i 2552K–AVR–04/11 ATmega329/3290/649/6490 Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 2 Overview ................................................................................................... 4 2.1 Block Diagram ...................................................................................................4 2.2 Comparison between ATmega329, ATmega3290, ATmega649 and ATmega6490 6 2.3 Pin Descriptions .................................................................................................6 3 Resources ................................................................................................. 9 4 Data Retention .......................................................................................... 9 5 About Code Examples ............................................................................. 9 6 AVR CPU Core ........................................................................................ 10 6.1 Overview ..........................................................................................................10 6.2 Architectural Overview .....................................................................................10 6.3 ALU – Arithmetic Logic Unit .............................................................................11 6.4 AVR Status Register ........................................................................................12 6.5 General Purpose Register File ........................................................................13 6.6 Stack Pointer ...................................................................................................14 6.7 Instruction Execution Timing ...........................................................................15 6.8 Reset and Interrupt Handling ...........................................................................15 7 AVR ATmega329/3290/649/6490 Memories ......................................... 18 7.1 In-System Reprogrammable Flash Program Memory .....................................18 7.2 SRAM Data Memory ........................................................................................19 7.3 EEPROM Data Memory ..................................................................................20 7.4 I/O Memory ......................................................................................................21 7.5 Register Description ........................................................................................22 8 System Clock and Clock Options ......................................................... 26 8.1 Clock Systems and their Distribution ...............................................................26 8.2 Clock Sources .................................................................................................27 8.3 Crystal Oscillator .............................................................................................28 8.4 Low-frequency Crystal Oscillator .....................................................................29 8.5 Calibrated Internal RC Oscillator .....................................................................29 8.6 External Clock .................................................................................................31ii 2552K–AVR–04/11 ATmega329/3290/649/6490 8.7 Clock Output Buffer .........................................................................................31 8.8 Timer/Counter Oscillator ..................................................................................32 8.9 System Clock Prescaler ..................................................................................32 8.10 Register Description ........................................................................................32 9 Power Management and Sleep Modes ................................................. 35 9.1 Idle Mode .........................................................................................................36 9.2 ADC Noise Reduction Mode ............................................................................36 9.3 Power-down Mode ...........................................................................................36 9.4 Power-save Mode ............................................................................................36 9.5 Standby Mode .................................................................................................37 9.6 Power Reduction Register ...............................................................................37 9.7 Minimizing Power Consumption ......................................................................37 9.8 Register Description ........................................................................................39 10 System Control and Reset .................................................................... 41 10.1 Resetting the AVR ...........................................................................................41 10.2 Reset Sources .................................................................................................41 10.3 Power-on Reset ...............................................................................................42 10.4 External Reset .................................................................................................43 10.5 Brown-out Detection ........................................................................................43 10.6 Watchdog Reset ..............................................................................................44 10.7 Internal Voltage Reference ..............................................................................44 10.8 Watchdog Timer ..............................................................................................45 10.9 Timed Sequences for Changing the Configuration of the Watchdog Timer ....47 10.10 Register Description ........................................................................................47 11 Interrupts ................................................................................................ 49 11.1 Interrupt Vectors in ATmega329/3290/649/6490 .............................................49 11.2 Register Description ........................................................................................52 12 External Interrupts ................................................................................. 54 12.1 Pin Change Interrupt Timing ............................................................................54 12.2 Register Description ........................................................................................55 13 I/O-Ports .................................................................................................. 59 13.1 Introduction ......................................................................................................59 13.2 Ports as General Digital I/O .............................................................................60 13.3 Alternate Port Functions ..................................................................................65iii 2552K–AVR–04/11 ATmega329/3290/649/6490 13.4 Register Description ........................................................................................87 14 8-bit Timer/Counter0 with PWM ............................................................ 91 14.1 Features ..........................................................................................................91 14.2 Overview ..........................................................................................................91 14.3 Timer/Counter Clock Sources .........................................................................92 14.4 Counter Unit ....................................................................................................93 14.5 Output Compare Unit .......................................................................................93 14.6 Compare Match Output Unit ............................................................................95 14.7 Modes of Operation .........................................................................................97 14.8 Timer/Counter Timing Diagrams ...................................................................101 14.9 Register Description ......................................................................................103 15 Timer/Counter0 and Timer/Counter1 Prescalers .............................. 107 15.1 Register Description ......................................................................................108 16 16-bit Timer/Counter1 .......................................................................... 110 16.1 Features ........................................................................................................110 16.2 Overview ........................................................................................................110 16.3 Accessing 16-bit Registers ............................................................................113 16.4 Timer/Counter Clock Sources .......................................................................116 16.5 Counter Unit ..................................................................................................116 16.6 Input Capture Unit .........................................................................................117 16.7 Output Compare Units ...................................................................................119 16.8 Compare Match Output Unit ..........................................................................122 16.9 Modes of Operation .......................................................................................123 16.10 Timer/Counter Timing Diagrams ...................................................................130 16.11 Register Description ......................................................................................132 17 8-bit Timer/Counter2 with PWM and Asynchronous Operation ...... 139 17.1 Features ........................................................................................................139 17.2 Overview ........................................................................................................139 17.3 Timer/Counter Clock Sources .......................................................................140 17.4 Counter Unit ..................................................................................................140 17.5 Output Compare Unit .....................................................................................141 17.6 Compare Match Output Unit ..........................................................................144 17.7 Modes of Operation .......................................................................................145 17.8 Timer/Counter Timing Diagrams ...................................................................149 17.9 Asynchronous Operation of Timer/Counter2 .................................................151iv 2552K–AVR–04/11 ATmega329/3290/649/6490 17.10 Timer/Counter Prescaler ...............................................................................152 17.11 Register Description ......................................................................................153 18 SPI – Serial Peripheral Interface ......................................................... 158 18.1 Features ........................................................................................................158 18.2 Overview ........................................................................................................158 18.3 SS Pin Functionality ......................................................................................163 18.4 Data Modes ...................................................................................................164 18.5 Register Description ......................................................................................165 19 USART0 ................................................................................................. 168 19.1 Features ........................................................................................................168 19.2 Overview ........................................................................................................168 19.3 Clock Generation ...........................................................................................169 19.4 Frame Formats ..............................................................................................172 19.5 USART Initialization .......................................................................................173 19.6 Data Transmission – The USART Transmitter ..............................................175 19.7 Data Reception – The USART Receiver .......................................................177 19.8 Asynchronous Data Reception ......................................................................181 19.9 Multi-processor Communication Mode ..........................................................185 19.10 Examples of Baud Rate Setting .....................................................................186 19.11 Register Description ......................................................................................190 20 USI – Universal Serial Interface .......................................................... 195 20.1 Features ........................................................................................................195 20.2 Overview ........................................................................................................195 20.3 Functional Descriptions .................................................................................196 20.4 Alternative USI Usage ...................................................................................202 20.5 Register Descriptions ....................................................................................203 21 Analog Comparator ............................................................................. 207 21.1 Overview ........................................................................................................207 21.2 Analog Comparator Multiplexed Input ...........................................................208 21.3 Register Description ......................................................................................209 22 Analog to Digital Converter ................................................................ 211 22.1 Features ........................................................................................................211 22.2 Operation .......................................................................................................212 22.3 Starting a Conversion ....................................................................................213v 2552K–AVR–04/11 ATmega329/3290/649/6490 22.4 Prescaling and Conversion Timing ................................................................214 22.5 Changing Channel or Reference Selection ...................................................216 22.6 ADC Conversion Result .................................................................................221 22.7 Register Description ......................................................................................223 23 LCD Controller ..................................................................................... 228 23.1 Features ........................................................................................................228 23.2 Mode of Operation .........................................................................................231 23.3 LCD Usage ....................................................................................................235 23.4 Register Description ......................................................................................239 24 JTAG Interface and On-chip Debug System ..................................... 245 24.1 Features ........................................................................................................245 24.2 Overview ........................................................................................................245 24.3 Test Access Port – TAP ................................................................................245 24.4 TAP Controller ...............................................................................................247 24.5 Using the Boundary-scan Chain ....................................................................248 24.6 Using the On-chip Debug System .................................................................248 24.7 On-chip Debug Specific JTAG Instructions ...................................................249 24.8 Using the JTAG Programming Capabilities ...................................................250 24.9 Bibliography ...................................................................................................250 24.10 Register Description ......................................................................................250 25 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 251 25.1 Features ........................................................................................................251 25.2 System Overview ...........................................................................................251 25.3 Data Registers ...............................................................................................251 25.4 Boundary-scan Specific JTAG Instructions ...................................................253 25.5 Boundary-scan Related Register in I/O Memory ...........................................254 25.6 Boundary-scan Chain ....................................................................................255 25.7 ATmega329/3290/649/6490 Boundary-scan Order .......................................264 25.8 Boundary-scan Description Language Files ..................................................277 26 Boot Loader Support – Read-While-Write Self-Programming ......... 278 26.1 Features ........................................................................................................278 26.2 Application and Boot Loader Flash Sections .................................................278 26.3 Read-While-Write and No Read-While-Write Flash Sections ........................278 26.4 Boot Loader Lock Bits ...................................................................................281 26.5 Entering the Boot Loader Program ................................................................282vi 2552K–AVR–04/11 ATmega329/3290/649/6490 26.6 Addressing the Flash During Self-Programming ...........................................283 26.7 Self-Programming the Flash ..........................................................................283 26.8 Register Description ......................................................................................291 27 Memory Programming ......................................................................... 293 27.1 Program And Data Memory Lock Bits ...........................................................293 27.2 Fuse Bits ........................................................................................................294 27.3 Signature Bytes .............................................................................................296 27.4 Calibration Byte .............................................................................................296 27.5 Parallel Programming Parameters, Pin Mapping, and Commands ...............296 27.6 Parallel Programming ....................................................................................299 27.7 Serial Downloading ........................................................................................308 27.8 Programming via the JTAG Interface ............................................................313 28 Electrical Characteristics .................................................................... 326 28.1 Absolute Maximum Ratings* .........................................................................326 28.2 DC Characteristics .........................................................................................326 28.3 Speed Grades ...............................................................................................328 28.4 Clock Characteristics .....................................................................................329 28.5 System and Reset Characteristics ................................................................330 28.6 SPI Timing Characteristics ............................................................................331 28.7 ADC Characteristics ......................................................................................333 28.8 LCD Controller Characteristics ......................................................................334 29 Typical Characteristics ........................................................................ 335 30 Register Summary ............................................................................... 365 31 Instruction Set Summary .................................................................... 369 32 Ordering Information ........................................................................... 372 32.1 ATmega329 ...................................................................................................372 32.2 ATmega3290 .................................................................................................373 32.3 ATmega649 ...................................................................................................374 32.4 ATmega6490 .................................................................................................375 33 Packaging Information ........................................................................ 376 33.1 64A ................................................................................................................376 33.2 64M1 ..............................................................................................................377 33.3 100A ..............................................................................................................378vii 2552K–AVR–04/11 ATmega329/3290/649/6490 34 Errata ..................................................................................................... 379 34.1 ATmega329 ...................................................................................................379 34.2 ATmega3290 .................................................................................................380 34.3 ATmega649 ...................................................................................................381 34.4 ATmega6490 .................................................................................................381 35 Datasheet Revision History ................................................................ 382 35.1 Rev. 2552K – 04/11 .......................................................................................382 35.2 Rev. 2552J – 08/07 .......................................................................................382 35.3 Rev. 2552I – 04/07 ........................................................................................382 35.4 Rev. 2552H – 11/06 .......................................................................................382 35.5 Rev. 2552G – 07/06 ......................................................................................383 35.6 Rev. 2552F – 06/06 .......................................................................................383 35.7 Rev. 2552E – 04/06 .......................................................................................383 35.8 Rev. 2552D – 03/06 .......................................................................................383 35.9 Rev. 2552C – 03/06 .......................................................................................383 35.10 Rev. 2552B – 05/05 .......................................................................................384 35.11 Rev. 2552A –11/04 ........................................................................................384 Table of Contents....................................................................................... i2552K–AVR–04/11 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1)(408) 441-0311 Fax: (+1)(408) 487-2600 www.atmel.com Atmel Asia Limited Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 JAPAN Tel: (+81)(3) 3523-3551 Fax: (+81)(3) 3523-7581 © 2011 Atmel Corporation. All rights reserved. Atmel®, Atmel logo and combinations thereof, AVR® and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. 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Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Throughput at 20 MHz • Data and Non-volatile Program and Data Memories – 2/4K Bytes of In-System Self Programmable Flash • Endurance 10,000 Write/Erase Cycles – 128/256 Bytes In-System Programmable EEPROM • Endurance: 100,000 Write/Erase Cycles – 128/256 Bytes Internal SRAM – Programming Lock for Flash Program and EEPROM Data Security • Peripheral Features – One 8-bit Timer/Counter with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes – Four PWM Channels – On-chip Analog Comparator – Programmable Watchdog Timer with On-chip Oscillator – USI – Universal Serial Interface – Full Duplex USART • Special Microcontroller Features – debugWIRE On-chip Debugging – In-System Programmable via SPI Port – External and Internal Interrupt Sources – Low-power Idle, Power-down, and Standby Modes – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit – Internal Calibrated Oscillator • I/O and Packages – 18 Programmable I/O Lines – 20-pin PDIP, 20-pin SOIC, 20-pad MLF/VQFN • Operating Voltage – 1.8 – 5.5V • Speed Grades – 0 – 4 MHz @ 1.8 – 5.5V – 0 – 10 MHz @ 2.7 – 5.5V – 0 – 20 MHz @ 4.5 – 5.5V • Industrial Temperature Range: -40°C to +85°C • Low Power Consumption – Active Mode • 190 µA at 1.8V and 1MHz – Idle Mode • 24 µA at 1.8V and 1MHz – Power-down Mode • 0.1 µA at 1.8V and +25°C 8-bit Microcontroller with 2/4K Bytes In-System Programmable Flash ATtiny2313A ATtiny4313 Rev. 8246B–AVR–09/112 8246B–AVR–09/11 ATtiny2313A/4313 1. Pin Configurations Figure 1-1. Pinout ATtiny2313A/4313 (PCINT10/RESET/dW) PA2 (PCINT11/RXD) PD0 (PCINT12/TXD) PD1 (PCINT9/XTAL2) PA1 (PCINT8/CLKI/XTAL1) PA0 (PCINT13/CKOUT/XCK/INT0) PD2 (PCINT14/INT1) PD3 (PCINT15/T0) PD4 (PCINT16/OC0B/T1) PD5 GND 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 VCC PB7 (USCK/SCL/SCK/PCINT7) PB6 (MISO/DO/PCINT6) PB5 (MOSI/DI/SDA/PCINT5) PB4 (OC1B/PCINT4) PB3 (OC1A/PCINT3) PB2 (OC0A/PCINT2) PB1 (AIN1/PCINT1) PB0 (AIN0/PCINT0) PD6 (ICPI/PCINT17) PDIP/SOIC 1 2 3 4 5 MLF/VQFN 15 14 13 12 11 20 19 18 17 16 6 7 8 9 10 (PCINT12/TXD) PD1 (PCINT9/XTAL2) PA1 (PCINT8/CLKI/XTAL1) PA0 (PCINT13/CKOUT/XCK/INT0) PD2 (PCINT14/INT1) PD3 (PCINT15/T0) PD4 (PCINT16/OC0B/T1) PD5 GND (PCINT17/ICPI) PD6 (AIN0/PCINT0) PB0 PB5 (MOSI/DI/SDA/PCINT5) PB4 (OC1B/PCINT4) PB3 (OC1A/PCINT3) PB2 (OC0A/PCINT2) PB1 (AIN1/PCINT1) PD0 (RXD/PCINT11) PA2 (RESET/dW/PCINT10) VCC PB7 (USCK/SCL/SCK/PCINT7) PB6 (MISO/DO/PCINT6) NOTE: Bottom pad should be soldered to ground.3 8246B–AVR–09/11 ATtiny2313A/4313 1.1 Pin Descriptions 1.1.1 VCC Digital supply voltage. 1.1.2 GND Ground. 1.1.3 Port A (PA2..PA0) Port A is a 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability, except PA2 which has the RESET capability. To use pin PA2 as I/O pin, instead of RESET pin, program (“0”) RSTDISBL fuse. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATtiny2313A/4313 as listed on page 62. 1.1.4 Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny2313A/4313 as listed on page 63. 1.1.5 Port D (PD6..PD0) Port D is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATtiny2313A/4313 as listed on page 67. 1.1.6 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided that the reset pin has not been disabled. The minimum pulse length is given in Table 22-3 on page 201. Shorter pulses are not guaranteed to generate a reset. The Reset Input is an alternate function for PA2 and dW. The reset pin can also be used as a (weak) I/O pin. 1.1.7 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. XTAL1 is an alternate function for PA0.4 8246B–AVR–09/11 ATtiny2313A/4313 1.1.8 XTAL2 Output from the inverting Oscillator amplifier. XTAL2 is an alternate function for PA1.5 8246B–AVR–09/11 ATtiny2313A/4313 2. Overview The ATtiny2313A/4313 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny2313A/4313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram PROGRAM COUNTER PROGRAM FLASH INSTRUCTION REGISTER GND VCC INSTRUCTION DECODER CONTROL LINES STACK POINTER SRAM GENERAL PURPOSE REGISTER ALU STATUS REGISTER PROGRAMMING LOGIC SPI 8-BIT DATA BUS XTAL1 XTAL2 RESET INTERNAL OSCILLATOR OSCILLATOR WATCHDOG TIMER TIMING AND CONTROL MCU CONTROL REGISTER MCU STATUS REGISTER TIMER/ COUNTERS INTERRUPT UNIT EEPROM USI USART ANALOG COMPARATOR DATA REGISTER PORTB DATA DIR. REG. PORTB DATA REGISTER PORTA DATA DIR. REG. PORTA PORTB DRIVERS PB0 - PB7 PORTA DRIVERS PA0 - PA2 DATA REGISTER PORTD DATA DIR. REG. PORTD PORTD DRIVERS PD0 - PD6 ON-CHIP DEBUGGER INTERNAL CALIBRATED OSCILLATOR6 8246B–AVR–09/11 ATtiny2313A/4313 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny2313A/4313 provides the following features: 2/4K bytes of In-System Programmable Flash, 128/256 bytes EEPROM, 128/256 bytes SRAM, 18 general purpose I/O lines, 32 general purpose working registers, a single-wire Interface for On-chip Debugging, two flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, or by a conventional non-volatile memory programmer. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATtiny2313A/4313 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATtiny2313A/4313 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 2.2 Comparison Between ATtiny2313A and ATtiny4313 The ATtiny2313A and ATtiny4313 differ only in memory sizes. Table 2-1 summarizes the different memory sizes for the two devices. Table 2-1. Memory Size Summary Device Flash EEPROM RAM ATtiny2313A 2K Bytes 128 Bytes 128 Bytes ATtiny4313 4K Bytes 256 Bytes 256 Bytes7 8246B–AVR–09/11 ATtiny2313A/4313 3. About 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O Registers located in the extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically, this means “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Note that not all AVR devices include an extended I/O map. 3.3 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.8 8246B–AVR–09/11 ATtiny2313A/4313 4. CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 4.1 Architectural Overview Figure 4-1. Block Diagram of the AVR Architecture In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Flash Program Memory Instruction Register Instruction Decoder Program Counter Control Lines 32 x 8 General Purpose Registrers ALU Status and Control I/O Lines EEPROM Data Bus 8-bit Data SRAM Direct Addressing Indirect Addressing Interrupt Unit SPI Unit Watchdog Timer Analog Comparator I/O Module 2 I/O Module1 I/O Module n9 8246B–AVR–09/11 ATtiny2313A/4313 Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. 4.2 ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description. 4.3 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.10 8246B–AVR–09/11 ATtiny2313A/4313 The AVR Status Register – SREG – is defined as: • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. • Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information. • Bit 4 – S: Sign Bit, S = N ⊕ V The S-bit is always an exclusive or between the negative flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information. • Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. Bit 7 6 5 4 3 2 1 0 0x3F (0x5F) I T H S V N Z C SREG Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 011 8246B–AVR–09/11 ATtiny2313A/4313 4.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 4-2. AVR CPU General Purpose Working Registers Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 4-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. 4.4.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3. 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 … R13 0x0D General R14 0x0E Purpose R15 0x0F Working R16 0x10 Registers R17 0x11 … R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte12 8246B–AVR–09/11 ATtiny2313A/4313 Figure 4-3. The X-, Y-, and Z-registers In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.5 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The Stack Pointer is implemented as one 8-bit register in the I/O space. 4.6 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. 15 XH XL 0 X-register 7 07 0 R27 (0x1B) R26 (0x1A) 15 YH YL 0 Y-register 7 07 0 R29 (0x1D) R28 (0x1C) 15 ZH ZL 0 Z-register 70 7 0 R31 (0x1F) R30 (0x1E) Bit 7 6 5 4 3 2 1 0 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND13 8246B–AVR–09/11 ATtiny2313A/4313 Figure 4-4. The Parallel Instruction Fetches and Instruction Executions Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 4-5. Single Cycle ALU Operation 4.7 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 48. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. Refer to “Interrupts” on page 48 for more information. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be clk 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch T1 T2 T3 T4 CPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back T1 T2 T3 T4 clkCPU14 8246B–AVR–09/11 ATtiny2313A/4313 cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.. When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1< xxx ... ... ... ... 9.2 External Interrupts External Interrupts are triggered by the INT0 or INT1 pin or any of the PCINT17..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0, INT1 or PCINT17..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. Pin change 0 interrupts PCI0 will trigger if any enabled PCINT7..0 pin toggles. Pin change 1 interrupts PCI1 will trigger if any enabled PCINT10..8 pin toggles. Pin change 2 interrupts PCI2 will trigger, if any enabled PCINT17..11 pin toggles. The PCMSK0, PCMSK1, and PCMSK2 Registers control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT17..0 are detected asynchronously, which means that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The INT0 and INT1 interrupts can be triggered by a falling or rising edge or a low level. This is set up as shown in “MCUCR – MCU Control Register” on page 51. When the INT0 or INT1 interrupt is enabled and configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT0 or INT1 requires the presence of an I/O clock, as described in “Clock Sources” on page 27.50 8246B–AVR–09/11 ATtiny2313A/4313 9.2.1 Low Level Interrupt A low level interrupt on INT0 or INT1 is detected asynchronously. This means that the interrupt source can be used for waking the part also from sleep modes other than Idle (the I/O clock is halted in all sleep modes except Idle). Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL fuses, as described in “Clock System” on page 26. If the low level on the interrupt pin is removed before the device has woken up then program execution will not be diverted to the interrupt service routine but continue from the instruction following the SLEEP command. 9.2.2 Pin Change Interrupt Timing A timing example of a pin change interrupt is shown in Figure 9-1. Figure 9-1. Timing of pin change interrupts clk PCINT(0) pin_lat pin_sync pcint_in_(0) pcint_syn pcint_setflag PCIF PCINT(0) pin_sync pcint_syn pin_lat D Q LE pcint_setflag PCIF clk clk PCINT(0) in PCMSK(x) pcint_in_(0) 0 x51 8246B–AVR–09/11 ATtiny2313A/4313 9.3 Register Description 9.3.1 MCUCR – MCU Control Register The External Interrupt Control Register contains control bits for interrupt sense control. • Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT1 pin that activate the interrupt are defined in Table 9-2. The value on the INT1 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt • Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding