ATmega8/L datasheet - Atmel - Farnell Element 14 - Revenir à l'accueil

 

 

Branding Farnell element14 (France)

 

Farnell Element 14 :

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Everything You Need To Know About Arduino

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Tutorial 01 for Arduino: Getting Acquainted with Arduino

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The Cube® 3D Printer

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What's easier- DIY Dentistry or our new our website features?

 

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Ben Heck's Getting Started with the BeagleBone Black Trailer

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Ben Heck's Home-Brew Solder Reflow Oven 2.0 Trailer

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Get Started with Pi Episode 3 - Online with Raspberry Pi

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Discover Simulink Promo -- Exclusive element14 Webinar

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Ben Heck's TV Proximity Sensor Trailer

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Ben Heck's PlayStation 4 Teardown Trailer

See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…

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Get Started with Pi Episode 4 - Your First Raspberry Pi Project

Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.

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Ben Heck Anti-Pickpocket Wallet Trailer

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Molex Earphones - The 14 Holiday Products of Newark element14 Promotion

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Tripp Lite Surge Protector - The 14 Holiday Products of Newark element14 Promotion

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Microchip ChipKIT Pi - The 14 Holiday Products of Newark element14 Promotion

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Beagle Bone Black - The 14 Holiday Products of Newark element14 Promotion

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3M E26, LED Lamps - The 14 Holiday Products of Newark element14 Promotion

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3M Colored Duct Tape - The 14 Holiday Products of Newark element14 Promotion

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Tenma Soldering Station - The 14 Holiday Products of Newark element14 Promotion

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Duratool Screwdriver Kit - The 14 Holiday Products of Newark element14 Promotion

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Cubify 3D Cube - The 14 Holiday Products of Newark element14 Promotion

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Bud Boardganizer - The 14 Holiday Products of Newark element14 Promotion

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Raspberry Pi Starter Kit - The 14 Holiday Products of Newark element14 Promotion

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Fluke 323 True-rms Clamp Meter - The 14 Holiday Products of Newark element14 Promotion

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Dymo RHINO 6000 Label Printer - The 14 Holiday Products of Newark element14 Promotion

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3M LED Advanced Lights A-19 - The 14 Holiday Products of Newark element14 Promotion

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Innovative LPS Resistor Features Very High Power Dissipation

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Charge Injection Evaluation Board for DG508B Multiplexer Demo

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Ben Heck The Great Glue Gun Trailer Part 2

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Introducing element14 TV

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Ben Heck Time to Meet Your Maker Trailer

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Détecteur de composants

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Recherche intégrée

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Ben Builds an Accessibility Guitar Trailer Part 1

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Ben Builds an Accessibility Guitar - Part 2 Trailer

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PiFace Control and Display Introduction

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Flashmob Farnell

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Express Yourself in 3D with Cube 3D Printers from Newark element14

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Farnell YouTube Channel Move

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Farnell: Design with the best

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French Farnell Quest

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Altera - 3 Ways to Quickly Adapt to Changing Ethernet Protocols

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Cy-Net3 Network Module

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MC AT - Professional and Precision Series Thin Film Chip Resistors

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Solderless LED Connector

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PSA-T Series Spectrum Analyser: PSA1301T/ PSA2701T

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3-axis Universal Motion Controller For Stepper Motor Drivers: TMC429

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Voltage Level Translation

Puce électronique / Microchip :

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Microchip - 8-bit Wireless Development Kit

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 2 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 3 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 1 of 3

Sans fil - Wireless :

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Microchip - 8-bit Wireless Development Kit

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Wireless Power Solutions - Wurth Electronics, Texas Instruments, CadSoft and element14

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Analog Devices - Remote Water Quality Monitoring via a Low Power, Wireless Network

Texas instrument :

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Texas Instruments - Automotive LED Headlights

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Texas Instruments - Digital Power Solutions

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Texas Instruments - Industrial Sensor Solutions

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Texas Instruments - Wireless Pen Input Demo (Mobile World Congress)

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Texas Instruments - Industrial Automation System Components

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Texas Instruments - TMS320C66x - Industry's first 10-GHz fixed/floating point DSP

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Texas Instruments - TMS320C66x KeyStone Multicore Architecture

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Texas Instruments - Industrial Interfaces

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Texas Instruments - Concerto™ MCUs - Connectivity without compromise

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Texas Instruments - Stellaris Robot Chronos

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Texas Instruments - DRV8412-C2-KIT, Brushed DC and Stepper Motor Control Kit

Ordinateurs :

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Ask Ben Heck - Connect Raspberry Pi to Car Computer

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Ben's Portable Raspberry Pi Computer Trailer

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Ben's Raspberry Pi Portable Computer Trailer 2

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Ben Heck's Pocket Computer Trailer

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Ask Ben Heck - Atari Computer

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Ask Ben Heck - Using Computer Monitors for External Displays

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Raspberry Pi Partnership with BBC Computer Literacy Project - Answers from co-founder Eben Upton

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Installing RaspBMC on your Raspberry Pi with the Farnell element14 Accessory kit

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Raspberry Pi Served - Joey Hudy

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Happy Birthday Raspberry Pi

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Raspberry Pi board B product overview

Logiciels :

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Ask Ben Heck - Best Opensource or Free CAD Software

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Tektronix FPGAView™ software makes debugging of FPGAs faster than ever!

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Ask Ben Heck - Best Open-Source Schematic Capture and PCB Layout Software

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Introduction to Cadsoft EAGLE PCB Design Software in Chinese

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Altera - Developing Software for Embedded Systems on FPGAs

Tutoriels :

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Ben Heck The Great Glue Gun Trailer Part 1

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the knode tutorial - element14

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Ben's Autodesk 123D Tutorial Trailer

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Ben's CadSoft EAGLE Tutorial Trailer

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Ben Heck's Soldering Tutorial Trailer

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Ben Heck's AVR Dev Board tutorial

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Ben Heck's Pinball Tutorial Trailer

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Ben Heck's Interface Tutorial Trailer

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First Stage with Python and PiFace Digital

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Cypress - Getting Started with PSoC® 3 - Part 2

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Energy Harvesting Challenge

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New Features of CadSoft EAGLE v6

Autres documentations :

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Features • High-performance, Low-power Atmel®AVR® 8-bit Microcontroller • Advanced RISC Architecture – 130 Powerful Instructions – Most Single-clock Cycle Execution – 32 × 8 General Purpose Working Registers – Fully Static Operation – Up to 16MIPS Throughput at 16MHz – On-chip 2-cycle Multiplier • High Endurance Non-volatile Memory segments – 8Kbytes of In-System Self-programmable Flash program memory – 512Bytes EEPROM – 1Kbyte Internal SRAM – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C(1) – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation – Programming Lock for Software Security • Peripheral Features – Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Three PWM Channels – 8-channel ADC in TQFP and QFN/MLF package Eight Channels 10-bit Accuracy – 6-channel ADC in PDIP package Six Channels 10-bit Accuracy – Byte-oriented Two-wire Serial Interface – Programmable Serial USART – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator • Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby • I/O and Packages – 23 Programmable I/O Lines – 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF • Operating Voltages – 2.7V - 5.5V (ATmega8L) – 4.5V - 5.5V (ATmega8) • Speed Grades – 0 - 8MHz (ATmega8L) – 0 - 16MHz (ATmega8) • Power Consumption at 4Mhz, 3V, 25C – Active: 3.6mA – Idle Mode: 1.0mA – Power-down Mode: 0.5µA 8-bit Atmel with 8KBytes InSystem Programmable Flash ATmega8 ATmega8L Rev.2486AA–AVR–02/20132 2486AA–AVR–02/2013 ATmega8(L) Pin Configurations 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 (INT1) PD3 (XCK/T0) PD4 GND VCC GND VCC (XTAL1/TOSC1) PB6 (XTAL2/TOSC2) PB7 PC1 (ADC1) PC0 (ADC0) ADC7 GND AREF ADC6 AVCC PB5 (SCK) 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 (T1) PD5 (AIN0) PD6 (AIN1) PD7 (ICP1) PB0 (OC1A) PB1 (SS/OC1B) PB2 (MOSI/OC2) PB3 (MISO) PB4 PD2 (INT0) PD1 (TXD) PD0 (RXD) PC6 (RESET) PC5 (ADC5/SCL) PC4 (ADC4/SDA) PC3 (ADC3) PC2 (ADC2) TQFP Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 (RESET) PC6 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (XCK/T0) PD4 VCC GND (XTAL1/TOSC1) PB6 (XTAL2/TOSC2) PB7 (T1) PD5 (AIN0) PD6 (AIN1) PD7 (ICP1) PB0 PC5 (ADC5/SCL) PC4 (ADC4/SDA) PC3 (ADC3) PC2 (ADC2) PC1 (ADC1) PC0 (ADC0) GND AREF AVCC PB5 (SCK) PB4 (MISO) PB3 (MOSI/OC2) PB2 (SS/OC1B) PB1 (OC1A) PDIP 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 MLF Top View (INT1) PD3 (XCK/T0) PD4 GND VCC GND VCC (XTAL1/TOSC1) PB6 (XTAL2/TOSC2) PB7 PC1 (ADC1) PC0 (ADC0) ADC7 GND AREF ADC6 AVCC PB5 (SCK) (T1) PD5 (AIN0) PD6 (AIN1) PD7 (ICP1) PB0 (OC1A) PB1 (SS/OC1B) PB2 (MOSI/OC2) PB3 (MISO) PB4 PD2 (INT0) PD1 (TXD) PD0 (RXD) PC6 (RESET) PC5 (ADC5/SCL) PC4 (ADC4/SDA) PC3 (ADC3) PC2 (ADC2) NOTE: The large center pad underneath the MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the PCB to ensure good mechanical stability. If the center pad is left unconneted, the package might loosen from the PCB.3 2486AA–AVR–02/2013 ATmega8(L) Overview The Atmel®AVR® ATmega8 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8 achieves throughputs approaching 1MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 1. Block Diagram INTERNAL OSCILLATOR OSCILLATOR WATCHDOG TIMER MCU CTRL. & TIMING OSCILLATOR TIMERS/ COUNTERS INTERRUPT UNIT STACK POINTER EEPROM SRAM STATUS REGISTER USART PROGRAM COUNTER PROGRAM FLASH INSTRUCTION REGISTER INSTRUCTION DECODER PROGRAMMING LOGIC SPI ADC INTERFACE COMP. INTERFACE PORTC DRIVERS/BUFFERS PORTC DIGITAL INTERFACE GENERAL PURPOSE REGISTERS X Y Z ALU + - PORTB DRIVERS/BUFFERS PORTB DIGITAL INTERFACE PORTD DIGITAL INTERFACE PORTD DRIVERS/BUFFERS XTAL1 XTAL2 CONTROL LINES VCC GND MUX & ADC AGND AREF PC0 - PC6 PB0 - PB7 PD0 - PD7 AVR CPU TWI RESET4 2486AA–AVR–02/2013 ATmega8(L) The Atmel®AVR® core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega8 provides the following features: 8 Kbytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes of EEPROM, 1 Kbyte of SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte oriented Twowire Serial Interface, a 6-channel ADC (eight channels in TQFP and QFN/MLF packages) with 10-bit accuracy, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Powerdown mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next Interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The Flash Program memory can be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash Section will continue to run while the Application Flash Section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega8 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. The ATmega8 is supported with a full suite of program and system development tools, including C compilers, macro assemblers, program simulators, and evaluation kits. Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Minimum and Maximum values will be available after the device is characterized.5 2486AA–AVR–02/2013 ATmega8(L) Pin Descriptions VCC Digital supply voltage. GND Ground. Port B (PB7..PB0) XTAL1/XTAL2/TOSC1/ TOSC2 Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator amplifier. If the Internal Calibrated RC Oscillator is used as chip clock source, PB7..6 is used as TOSC2..1 input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set. The various special features of Port B are elaborated in “Alternate Functions of Port B” on page 58 and “System Clock and Clock Options” on page 25. Port C (PC5..PC0) Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. PC6/RESET If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6 differ from those of the other pins of Port C. If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page 38. Shorter pulses are not guaranteed to generate a Reset. The various special features of Port C are elaborated on page 61. Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega8 as listed on page 63. RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page 38. Shorter pulses are not guaranteed to generate a reset.6 2486AA–AVR–02/2013 ATmega8(L) AVCC AVCC is the supply voltage pin for the A/D Converter, Port C (3..0), and ADC (7..6). It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. Note that Port C (5..4) use digital supply voltage, VCC. AREF AREF is the analog reference pin for the A/D Converter. ADC7..6 (TQFP and QFN/MLF Package Only) In the TQFP and QFN/MLF package, ADC7..6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels.7 2486AA–AVR–02/2013 ATmega8(L) Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 1. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.8 2486AA–AVR–02/2013 ATmega8(L) About Code Examples This datasheet contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.9 2486AA–AVR–02/2013 ATmega8(L) Atmel AVR CPU Core Introduction This section discusses the Atmel®AVR® core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 2. Block Diagram of the AVR MCU Architecture In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 × 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers Flash Program Memory Instruction Register Instruction Decoder Program Counter Control Lines 32 x 8 General Purpose Registrers ALU Status and Control I/O Lines EEPROM Data Bus 8-bit Data SRAM Direct Addressing Indirect Addressing Interrupt Unit SPI Unit Watchdog Timer Analog Comparator i/O Module 2 i/O Module1 i/O Module n10 2486AA–AVR–02/2013 ATmega8(L) can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-register, Y-register, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. The Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every Program memory address contains a 16-bit or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot program section and the Application program section. Both sections have dedicated Lock Bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F.11 2486AA–AVR–02/2013 ATmega8(L) Arithmetic Logic Unit – ALU The high-performance Atmel®AVR® ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. For a detailed description, see “Instruction Set Summary” on page 311. Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. The AVR Status Register – SREG – is defined as: • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the Instruction Set Reference. • Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information. • Bit 4 – S: Sign Bit, S = N V The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information. • Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. Bit 7 6 5 4 3 2 1 0 I T H S V N Z C SREG Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 012 2486AA–AVR–02/2013 ATmega8(L) • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a Carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 3 shows the structure of the 32 general purpose working registers in the CPU. Figure 3. AVR CPU General Purpose Working Registers Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 3, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-pointer, Y-pointer, and Z-pointer Registers can be set to index any register in the file. 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 … R13 0x0D General R14 0x0E Purpose R15 0x0F Working R16 0x10 Registers R17 0x11 … R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte13 2486AA–AVR–02/2013 ATmega8(L) The X-register, Yregister and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y and Z are defined as described in Figure 4. Figure 4. The X-register, Y-register and Z-Register In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the Instruction Set Reference for details). Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when address is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The Atmel®AVR® CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. 15 XH XL 0 X-register 7 0 7 0 R27 (0x1B) R26 (0x1A) 15 YH YL 0 Y-register 7 0 7 0 R29 (0x1D) R28 (0x1C) 15 ZH ZL 0 Z-register 7 0 7 0 R31 (0x1F) R30 (0x1E) Bit 15 14 13 12 11 10 9 8 SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 76543210 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0000000014 2486AA–AVR–02/2013 ATmega8(L) Figure 5 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 5. The Parallel Instruction Fetches and Instruction Executions Figure 6 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 6. Single Cycle ALU Operation Reset and Interrupt Handling The Atmel®AVR® provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock Bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Programming” on page 215 for details. The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of Vectors is shown in “Interrupts” on page 46. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the boot Flash section by setting the Interrupt Vector Select (IVSEL) bit in the General Interrupt Control Register (GICR). Refer to “Interrupts” on page 46 for more information. The Reset Vector can also be moved to the start of the boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – ReadWhile-Write Self-Programming” on page 202. clk 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch T1 T2 T3 T4 CPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back T1 T2 T3 T4 clkCPU15 2486AA–AVR–02/2013 ATmega8(L) When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the global interrupt enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMWE ; start EEPROM write sbi EECR, EEWE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1< xxx ... ... ... Table 19. Reset and Interrupt Vectors Placement BOOTRST(1) IVSEL Reset Address Interrupt Vectors Start Address 1 0 0x000 0x001 1 1 0x000 Boot Reset Address + 0x001 0 0 Boot Reset Address 0x001 0 1 Boot Reset Address Boot Reset Address + 0x00148 2486AA–AVR–02/2013 ATmega8(L) When the BOOTRST Fuse is unprogrammed, the boot section size set to 2Kbytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: AddressLabels Code Comments $000 rjmp RESET ; Reset handler ; $001 RESET:ldi r16,high(RAMEND); Main program start $002 out SPH,r16 ; Set Stack Pointer to top of RAM $003 ldi r16,low(RAMEND) $004 out SPL,r16 $005 sei ; Enable interrupts $006 xxx ; .org $c01 $c01 rjmp EXT_INT0 ; IRQ0 Handler $c02 rjmp EXT_INT1 ; IRQ1 Handler ... ... ... ; $c12 rjmp SPM_RDY ; Store Program Memory Ready Handler When the BOOTRST Fuse is programmed and the boot section size set to 2Kbytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: AddressLabels Code Comments .org $001 $001 rjmp EXT_INT0 ; IRQ0 Handler $002 rjmp EXT_INT1 ; IRQ1 Handler ... ... ... ; $012 rjmp SPM_RDY ; Store Program Memory Ready Handler ; .org $c00 $c00 rjmp RESET ; Reset handler ; $c01 RESET:ldi r16,high(RAMEND); Main program start $c02 out SPH,r16 ; Set Stack Pointer to top of RAM $c03 ldi r16,low(RAMEND) $c04 out SPL,r16 $c05 sei ; Enable interrupts $c06 xxx49 2486AA–AVR–02/2013 ATmega8(L) When the BOOTRST Fuse is programmed, the boot section size set to 2Kbytes, and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: AddressLabels Code Comments ; .org $c00 $c00 rjmp RESET ; Reset handler $c01 rjmp EXT_INT0 ; IRQ0 Handler $c02 rjmp EXT_INT1 ; IRQ1 Handler ... ... ... ; $c12 rjmp SPM_RDY ; Store Program Memory Ready Handler $c13 RESET: ldi r16,high(RAMEND); Main program start $c14 out SPH,r16 ; Set Stack Pointer to top of RAM $c15 ldi r16,low(RAMEND) $c16 out SPL,r16 $c17 sei ; Enable interrupts $c18 xxx Moving Interrupts Between Application and Boot Space The General Interrupt Control Register controls the placement of the Interrupt Vector table. General Interrupt Control Register – GICR • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the boot Flash section is determined by the BOOTSZ Fuses. Refer to the section “Boot Loader Support – Read-While-Write Self-Programming” on page 202 for details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit: 1. Write the Interrupt Vector Change Enable (IVCE) bit to one 2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling. Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section “Boot Loader Support – Read-While-Write Self-Programming” on page 202 for details on Boot Lock Bits. Bit 7 6 5 4 3 2 1 0 INT1 INT0 – – – – IVSEL IVCE GICR Read/Write R/W R/W R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 050 2486AA–AVR–02/2013 ATmega8(L) • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below. Assembly Code Example Move_interrupts: ; Enable change of Interrupt Vectors ldi r16, (1< CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is connected to. External Clock Source An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock (clkT1/clkT0). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 30 shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the internal system clock. The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects. Figure 30. T1/T0 Pin Sampling The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated. Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses Tn_sync (To Clock Select Logic) Synchronization Edge Detector D Q D Q LE Tn D Q clkI/O74 2486AA–AVR–02/2013 ATmega8(L) sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 31. Prescaler for Timer/Counter0 and Timer/Counter1(1) Note: 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 30 on page 73 Special Function IO Register – SFIOR • Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0 When this bit is written to one, the Timer/Counter1 and Timer/Counter0 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. This bit will always be read as zero. PSR10 Clear clkT1 clkT0 T1 T0 clkI/O Synchronization Synchronization Bit 7 6 5 4 3 2 1 0 – – – – ACME PUD PSR2 PSR10 SFIOR Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 075 2486AA–AVR–02/2013 ATmega8(L) 16-bit Timer/Counter1 The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (that is, allows 16-bit PWM) • Two Independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceler • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Variable PWM Period • Frequency Generator • External Event Counter • Four Independent Interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1) Overview Most register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit channel. However, when using the register or bit defines in a program, the precise form must be used, that is, TCNT1 for accessing Timer/Counter1 counter value and so on. A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 32 on page 76. For the actual placement of I/O pins, refer to “Pin Configurations” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “16-bit Timer/Counter Register Description” on page 96.76 2486AA–AVR–02/2013 ATmega8(L) Figure 32. 16-bit Timer/Counter Block Diagram(1) Note: 1. Refer to “Pin Configurations” on page 2, Table 22 on page 58, and Table 28 on page 63 for Timer/Counter1 pin placement and description Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are described in the section “Accessing 16-bit Registers” on page 77. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T1 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clkT1). The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter value at all time. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare Pin (OC1A/B). See “Output Compare Units” on page 83. The Compare Match event will also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. Clock Select Timer/Counter DATA BUS OCRnA OCRnB ICRn = = TCNTn Waveform Generation Waveform Generation OCnA OCnB Noise Canceler ICPn = Fixed TOP Values Edge Detector Control Logic = 0 TOP BOTTOM Count Clear Direction TOVn (Int. Req.) OCFnA (Int. Req.) OCFnB (Int.Req.) ICFn (Int.Req.) TCCRnA TCCRnB ( From Analog Comparator Ouput ) Tn Edge Detector ( From Prescaler ) clkTn77 2486AA–AVR–02/2013 ATmega8(L) The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture Pin (ICP1) or on the Analog Comparator pins (see “Analog Comparator” on page 186). The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCR1A Register, the ICR1 Register, or by a set of fixed values. When using OCR1A as TOP value in a PWM mode, the OCR1A Register can not be used for generating a PWM output. However, the TOP value will in this case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP value is required, the ICR1 Register can be used as an alternative, freeing the OCR1A to be used as PWM output. Definitions The following definitions are used extensively throughout the document: Compatibility The 16-bit Timer/Counter has been updated and improved from previous versions of the 16-bit AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier version regarding: • All 16-bit Timer/Counter related I/O Register address locations, including Timer Interrupt Registers • Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers • Interrupt Vectors The following control bits have changed name, but have same functionality and register location: • PWM10 is changed to WGM10 • PWM11 is changed to WGM11 • CTC1 is changed to WGM12 The following bits are added to the 16-bit Timer/Counter Control Registers: • FOC1A and FOC1B are added to TCCR1A • WGM13 is added to TCCR1B The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. The 16-bit timer has a single 8-bit register for temporary storing of the High byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within the 16-bit timer. Accessing the Low byte triggers the 16-bit read or write operation. When the Low byte of a 16-bit register is written by the CPU, the High byte stored in the temporary register, and the Low byte written are both copied into the 16-bit register in the same clock cycle. When the Low byte Table 35. Definitions BOTTOM The counter reaches the BOTTOM when it becomes 0x0000. MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCR1A or ICR1 Register. The assignment is dependent of the mode of operation.78 2486AA–AVR–02/2013 ATmega8(L) of a 16-bit register is read by the CPU, the High byte of the 16-bit register is copied into the temporary register in the same clock cycle as the Low byte is read. Not all 16-bit accesses uses the temporary register for the High byte. Reading the OCR1A/B 16- bit registers does not involve using the temporary register. To do a 16-bit write, the High byte must be written before the Low byte. For a 16-bit read, the Low byte must be read before the High byte. The following code examples show how to access the 16-bit Timer Registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCR1A/B and ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit access. Note: 1. See “About Code Examples” on page 8 The assembly code example returns the TCNT1 value in the r17:r16 Register pair. It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit Timer Registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example(1) ... ; Set TCNT1 to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ... C Code Example(1) unsigned int i; ... /* Set TCNT1 to 0x01FF */ TCNT1 = 0x1FF; /* Read TCNT1 into i */ i = TCNT1; ...79 2486AA–AVR–02/2013 ATmega8(L) Note: 1. See “About Code Examples” on page 8 The assembly code example returns the TCNT1 value in the r17:r16 Register pair. Assembly Code Example(1) TIM16_ReadTCNT1: ; Save Global Interrupt Flag in r18,SREG ; Disable interrupts cli ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ; Restore Global Interrupt Flag out SREG,r18 ret C Code Example(1) unsigned int TIM16_ReadTCNT1( void ) { unsigned char sreg; unsigned int i; /* Save Global Interrupt Flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into i */ i = TCNT1; /* Restore Global Interrupt Flag */ SREG = sreg; return i; }80 2486AA–AVR–02/2013 ATmega8(L) The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Note: 1. See “About Code Examples” on page 8 The assembly code example requires that the r17:r16 Register pair contains the value to be written to TCNT1. Reusing the Temporary High Byte Register If writing to more than one 16-bit register where the High byte is the same for all registers written, then the High byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the clock select (CS12:0) bits located in the Timer/Counter Control Register B (TCCR1B). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 73. Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 33 on page 81 shows a block diagram of the counter and its surroundings. Assembly Code Example(1) TIM16_WriteTCNT1: ; Save Global Interrupt Flag in r18,SREG ; Disable interrupts cli ; Set TCNT1 to r17:r16 out TCNT1H,r17 out TCNT1L,r16 ; Restore Global Interrupt Flag out SREG,r18 ret C Code Example(1) void TIM16_WriteTCNT1( unsigned int i ) { unsigned char sreg; unsigned int i; /* Save Global Interrupt Flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNT1 to i */ TCNT1 = i; /* Restore Global Interrupt Flag */ SREG = sreg; }81 2486AA–AVR–02/2013 ATmega8(L) Figure 33. Counter Unit Block Diagram Signal description (internal signals): count Increment or decrement TCNT1 by 1 direction Select between increment and decrement clear Clear TCNT1 (set all bits to zero) clkT1 Timer/Counter clock TOP Signalize that TCNT1 has reached maximum value BOTTOM Signalize that TCNT1 has reached minimum value (zero) The 16-bit counter is mapped into two 8-bit I/O memory locations: counter high (TCNT1H) containing the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU does an access to the TCNT1H I/O location, the CPU accesses the High byte temporary register (TEMP). The temporary register is updated with the TCNT1H value when the TCNT1L is read, and TCNT1H is updated with the temporary register value when TCNT1L is written. This allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is important to notice that there are special cases of writing to the TCNT1 Register when the counter is counting that will give unpredictable results. The special cases are described in the sections where they are of importance. Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT1). The clkT1 can be generated from an external or internal clock source, selected by the clock select bits (CS12:0). When no clock source is selected (CS12:0 = 0) the timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of whether clkT1 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the Waveform Generation mode bits (WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare Outputs OC1x. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 87. The Timer/Counter Overflow (TOV1) fLag is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP1 pin or alternatively, via the Analog Comparator unit. TEMP (8-bit) DATA BUS (8-bit) TCNTn (16-bit Counter) TCNTnH (8-bit) TCNTnL (8-bit) Control Logic count clear direction TOVn (Int. Req.) Clock Select TOP BOTTOM Tn Edge Detector ( From Prescaler ) clkTn82 2486AA–AVR–02/2013 ATmega8(L) The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events. The Input Capture unit is illustrated by the block diagram shown in Figure 34. The elements of the block diagram that are not directly a part of the Input Capture unit are gray shaded. The small “n” in register and bit names indicates the Timer/Counter number. Figure 34. Input Capture Unit Block Diagram When a change of the logic level (an event) occurs on the Input Capture Pin (ICP1), alternatively on the Analog Comparator Output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter (TCNT1) is written to the Input Capture Register (ICR1). The Input Capture Flag (ICF1) is set at the same system clock as the TCNT1 value is copied into ICR1 Register. If enabled (TICIE1 = 1), the Input Capture Flag generates an Input Capture interrupt. The ICF1 Flag is automatically cleared when the interrupt is executed. Alternatively the ICF1 Flag can be cleared by software by writing a logical one to its I/O bit location. Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the Low byte (ICR1L) and then the High byte (ICR1H). When the Low byte is read the High byte is copied into the High byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will access the TEMP Register. The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Generation mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1 Register. When writing the ICR1 Register the High byte must be written to the ICR1H I/O location before the Low byte is written to ICR1L. For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 77. Input Capture Pin Source The main trigger source for the Input Capture unit is the Input Capture Pin (ICP1). Timer/Counter 1 can alternatively use the Analog Comparator Output as trigger source for the Input Capture ICFn (Int. Req.) Analog Comparator WRITE ICRn (16-bit Register) ICRnH (8-bit) Noise Canceler ICPn Edge Detector TEMP (8-bit) DATA BUS (8-bit) ICRnL (8-bit) TCNTn (16-bit Counter) TCNTnH (8-bit) TCNTnL (8-bit) ACO* ACIC* ICNC ICES83 2486AA–AVR–02/2013 ATmega8(L) unit. The Analog Comparator is selected as trigger source by setting the Analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change. Both the Input Capture Pin (ICP1) and the Analog Comparator Output (ACO) inputs are sampled using the same technique as for the T1 pin (Figure 30 on page 73). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. Note that the input of the noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform Generation mode that uses ICR1 to define TOP. An Input Capture can be triggered by software by controlling the port of the ICP1 pin. Noise Canceler The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in Timer/Counter Control Register B (TCCR1B). When enabled the noise canceler introduces additional four system clock cycles of delay from a change applied to the input, to the update of the ICR1 Register. The noise canceler uses the system clock and is therefore not affected by the prescaler. Using the Input Capture Unit The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the incoming events. The time between two events is critical. If the processor has not read the captured value in the ICR1 Register before the next event occurs, the ICR1 will be overwritten with a new value. In this case the result of the capture will be incorrect. When using the Input Capture interrupt, the ICR1 Register should be read as early in the interrupt handler routine as possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICR1 Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). Output Compare Units The 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF1x Flag is automatically cleared when the interrupt is executed. Alternatively the OCF1x Flag can be cleared by software by writing a logical one to its I/O bit location. The waveform generator uses the match signal to generate an output according to operating mode set by the Waveform Generation mode (WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP and BOTTOM signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation (see “Modes of Operation” on page 87). A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (that is counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the waveform generator.84 2486AA–AVR–02/2013 ATmega8(L) Figure 35 shows a block diagram of the Output Compare unit. The small “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded. Figure 35. Output Compare Unit, Block Diagram The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR1x Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x directly. The content of the OCR1x (Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the High byte temporary register (TEMP). However, it is a good practice to read the Low byte first as when accessing other 16-bit registers. Writing the OCR1x Registers must be done via the TEMP Register since the compare of all 16-bit is done continuously. The High byte (OCR1xH) has to be written first. When the High byte I/O location is written by the CPU, the TEMP Register will be updated by the value written. Then when the Low byte (OCR1xL) is written to the lower eight bits, the High byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare Register in the same system clock cycle. For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 77. OCFnx (Int.Req.) = (16-bit Comparator ) OCRnx Buffer (16-bit Register) OCRnxH Buf. (8-bit) OCnx TEMP (8-bit) DATA BUS (8-bit) OCRnxL Buf. (8-bit) TCNTn (16-bit Counter) TCNTnH (8-bit) TCNTnL (8-bit) WGMn3:0 COMnx1:0 OCRnx (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) Waveform Generator TOP BOTTOM85 2486AA–AVR–02/2013 ATmega8(L) Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC1x) bit. Forcing Compare Match will not set the OCF1x Flag or reload/clear the timer, but the OC1x pin will be updated as if a real Compare Match had occurred (the COM1x1:0 bits settings define whether the OC1x pin is set, cleared or toggled). Compare Match Blocking by TCNT1 Write All CPU writes to the TCNT1 Register will block any Compare Match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled. Using the Output Compare Unit Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT1 when using any of the Output Compare channels, independent of whether the Timer/Counter is running or not. If the value written to TCNT1 equals the OCR1x value, the Compare Match will be missed, resulting in incorrect waveform generation. Do not write the TCNT1 equal to TOP in PWM modes with variable TOP values. The Compare Match for the TOP will be ignored and the counter will continue to 0xFFFF. Similarly, do not write the TCNT1 value equal to BOTTOM when the counter is downcounting. The setup of the OC1x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC1x value is to use the Force Output Compare (FOC1x) strobe bits in Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The waveform generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next Compare Match. Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 36 on page 86 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to the OC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a System Reset occur, the OC1x Register is reset to “0”.86 2486AA–AVR–02/2013 ATmega8(L) Figure 36. Compare Match Output Unit, Schematic The general I/O port function is overridden by the Output Compare (OC1x) from the waveform generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x value is visible on the pin. The port override function is generally independent of the Waveform Generation mode, but there are some exceptions. Refer to Table 36 on page 96, Table 37 on page 96 and Table 38 on page 97 for details. The design of the Output Compare Pin logic allows initialization of the OC1x state before the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation. See “16-bit Timer/Counter Register Description” on page 96. The COM1x1:0 bits have no effect on the Input Capture unit. PORT DDR D Q D Q OCnx OCnx Pin D Q Waveform Generator COMnx1 COMnx0 0 1 DATABUS FOCnx clkI/O87 2486AA–AVR–02/2013 ATmega8(L) Compare Output Mode and Waveform Generation The waveform generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1:0 = 0 tells the waveform generator that no action on the OC1x Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 36 on page 96. For fast PWM mode refer to Table 37 on page 96, and for phase correct and phase and frequency correct PWM refer to Table 38 on page 97. A change of the COM1x1:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits. Modes of Operation The mode of operation (that is, the behavior of the Timer/Counter and the Output Compare pins) is defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Output mode (COM1x1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM1x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM1x1:0 bits control whether the output should be set, cleared or toggle at a Compare Match. See “Compare Match Output Unit” on page 85. For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 94. Normal Mode The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOV1) will be set in the same timer clock cycle as the TCNT1 becomes zero. The TOV1 Flag in this case behaves like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV1 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the external events must not exceed the resolution of the counter. If the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Register are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 37 on page 88. The counter value (TCNT1) increases until a Compare Match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared.88 2486AA–AVR–02/2013 ATmega8(L) Figure 37. CTC Mode, Timing Diagram An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR1A or ICR1 is lower than the current value of TCNT1, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before the Compare Match can occur. In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode using OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double buffered. For generating a waveform output in CTC mode, the OC1A output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM1A1:0 = 1). The OC1A value will not be visible on the port pin unless the data direction for the pin is set to output (DDR_OC1A = 1). The waveform generated will have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). The waveform frequency is defined by the following equation: The N variable represents the prescaler factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV1 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000. Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the Compare Match between TCNT1 and OCR1x, and set at BOTTOM. In inverting Compare Output mode output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-bit, 9-bit, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the TCNTn OCnA (Toggle) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) Period 1 2 3 4 (COMnA1:0 = 1) f OCnA f clk_I/O 2   N   1 + OCRnA = --------------------------------------------------89 2486AA–AVR–02/2013 ATmega8(L) maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 = 14), or the value in OCR1A (WGM13:0 = 15). The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 38. The figure shows fast PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a Compare Match occurs. Figure 38. Fast PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition the OCF1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A or ICR1 is used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and compare values. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a Compare Match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values the unused bits are masked to zero when any of the OCR1x Registers are written. The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value. The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new ICR1 value written is lower than the current value of TCNT1. The result will then be that the counter will miss the Compare Match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the Compare Match can occur. The OCR1A Register, however, is double buffered. This feature allows the OCR1A I/O location to be written anytime. When the OCR1A I/O location is written the value written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set. RFPWM log  TOP + 1 log  2 = ----------------------------------- TCNTn OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) Period 1 2 3 4 5 6 7 8 OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3)90 2486AA–AVR–02/2013 ATmega8(L) Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed (by changing the TOP value), using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to 3. See Table 37 on page 96. The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the Compare Match between OCR1x and TCNT1, and clearing (or setting) the OC1x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR1x is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR1x equal to TOP will result in a constant high or low output (depending on the polarity of the output set by the COM1x1:0 bits). A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC1A to toggle its logical level on each Compare Match (COM1A1:0 = 1). This applies only if OCR1A is used to define the TOP value (WGM13:0 = 15). The waveform generated will have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). This feature is similar to the OC1A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. Phase Correct PWM Mode The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dualslope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the Compare Match between TCNT1 and OCR1x while upcounting, and set on the Compare Match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-bit, 9-bit, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation: In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1 (WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 39 on page 91. The figure shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operaf OCnxPWM f clk_I/O N    1 + TOP = ----------------------------------- RPCPWM log  TOP + 1 log  2 = -----------------------------------91 2486AA–AVR–02/2013 ATmega8(L) tion. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a Compare Match occurs. Figure 39. Phase Correct PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accordingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a Compare Match will never occur between the TCNT1 and the OCR1x. Note that when using fixed TOP values, the unused bits are masked to zero when any of the OCR1x Registers are written. As the third period shown in Figure 39 illustrates, changing the TOP actively while the Timer/Counter is running in the Phase Correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Register. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output. It is recommended to use the Phase and Frequency Correct mode instead of the Phase Correct mode when changing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically no differences between the two modes of operation. In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to 3. See Table 38 on page 97. The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the Compare Match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at Compare Match between OCR1x and TCNT1 when OCRnx / TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) 1 2 3 4 TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn Period OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3)92 2486AA–AVR–02/2013 ATmega8(L) the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value (WMG13:0 = 11) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle. Phase and Frequency Correct PWM Mode The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation option. The phase and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the Compare Match between TCNT1 and OCR1x while upcounting, and set on the Compare Match while downcounting. In inverting Compare Output mode, the operation is inverted. The dual-slope operation gives a lower maximum operation frequency compared to the single-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the OCR1x Register is updated by the OCR1x Buffer Register, (see Figure 39 on page 91 and Figure 40 on page 93). The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown on Figure 40 on page 93. The figure shows phase and frequency correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a Compare Match occurs. f OCnxPCPWM f clk_I/O 2   N TOP = ---------------------------- RPFCPWM log  TOP + 1 log  2 = -----------------------------------93 2486AA–AVR–02/2013 ATmega8(L) Figure 40. Phase and Frequency Correct PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag set when TCNT1 has reached TOP. The Interrupt Flags can then be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a Compare Match will never occur between the TCNT1 and the OCR1x. As Figure 40 shows the output generated is, in contrast to the Phase Correct mode, symmetrical in all periods. Since the OCR1x Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct. Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM1x1:0 to 3. See Table 38 on page 97. The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the Compare Match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at Compare Match between OCR1x and TCNT1 when the counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be calculated by the following equation: The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the OCRnx / TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) 1 2 3 4 TCNTn Period OCnx OCnx (COMnx1:0 = 2) (COMnx1:0 = 3) f OCnxPFCPWM f clk_I/O 2   N TOP = ----------------------------94 2486AA–AVR–02/2013 ATmega8(L) output will be continuously low and if set equal to TOP the output will be set to high for noninverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle. Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double buffering). Figure 41 shows a timing diagram for the setting of OCF1x. Figure 41. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling Figure 42 shows the same timing data, but with the prescaler enabled. Figure 42. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8) Figure 43 on page 95 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timclkTn (clkI/O/1) OCFnx clkI/O OCRnx TCNTn OCRnx Value OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCFnx OCRnx TCNTn OCRnx Value OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 clkI/O clkTn (clkI/O/8)95 2486AA–AVR–02/2013 ATmega8(L) ing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM. Figure 43. Timer/Counter Timing Diagram, no Prescaling Figure 44 shows the same timing data, but with the prescaler enabled. Figure 44. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 Old OCRnx Value New OCRnx Value TOP - 1 TOP BOTTOM BOTTOM + 1 clkTn (clkI/O/1) clkI/O TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 Old OCRnx Value New OCRnx Value TOP - 1 TOP BOTTOM BOTTOM + 1 clkI/O clkTn (clkI/O/8)96 2486AA–AVR–02/2013 ATmega8(L) 16-bit Timer/Counter Register Description Timer/Counter 1 Control Register A – TCCR1A • Bit 7:6 – COM1A1:0: Compare Output Mode for channel A • Bit 5:4 – COM1B1:0: Compare Output Mode for channel B The COM1A1:0 and COM1B1:0 control the Output Compare Pins (OC1A and OC1B respectively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC1A or OC1B pin must be set in order to enable the output driver. When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is dependent of the WGM13:0 bits setting. Table 36 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to a normal or a CTC mode (non-PWM). Table 37 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode. Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the Compare Match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 88 for more details Bit 7 6 5 4 3 2 1 0 COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 TCCR1A Read/Write R/W R/W R/W R/W W W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 36. Compare Output Mode, Non-PWM COM1A1/ COM1B1 COM1A0/ COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 Toggle OC1A/OC1B on Compare Match 1 0 Clear OC1A/OC1B on Compare Match (Set output to low level) 1 1 Set OC1A/OC1B on Compare Match (Set output to high level) Table 37. Compare Output Mode, Fast PWM(1) COM1A1/ COM1B1 COM1A0/ COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected. 1 0 Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at BOTTOM, (non-inverting mode) 1 1 Set OC1A/OC1B on Compare Match, clear OC1A/OC1B at BOTTOM, (inverting mode)97 2486AA–AVR–02/2013 ATmega8(L) Table 38 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See “Phase Correct PWM Mode” on page 90 for more details • Bit 3 – FOC1A: Force Output Compare for channel A • Bit 2 – FOC1B: Force Output Compare for channel B The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate Compare Match is forced on the waveform generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare Match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. • Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 39. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 87). Table 38. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1) COM1A1/ COM1B1 COM1A0/ COM1B0 Description 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 9 or 14: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected. 1 0 Clear OC1A/OC1B on Compare Match when up-counting. Set OC1A/OC1B on Compare Match when downcounting. 1 1 Set OC1A/OC1B on Compare Match when up-counting. Clear OC1A/OC1B on Compare Match when downcounting. Table 39. Waveform Generation Mode Bit Description Mode WGM13 WGM12 (CTC1) WGM11 (PWM11) WGM10 (PWM10) Timer/Counter Mode of Operation(1) TOP Update of OCR1x TOV1 Flag Set on 0 0 0 0 0 Normal 0xFFFF Immediate MAX 1 0 0 0 1 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM 2 0 0 1 0 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM 3 0 0 1 1 PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM 4 0 1 0 0 CTC OCR1A Immediate MAX 5 0 1 0 1 Fast PWM, 8-bit 0x00FF BOTTOM TOP 6 0 1 1 0 Fast PWM, 9-bit 0x01FF BOTTOM TOP98 2486AA–AVR–02/2013 ATmega8(L) Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer Timer/Counter 1 Control Register B – TCCR1B • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture Pin (ICP1) is filtered. The filter function requires four successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled. • Bit 6 – ICES1: Input Capture Edge Select This bit selects which edge on the Input Capture Pin (ICP1) that is used to trigger a capture event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled. • Bit 5 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCR1B is written. • Bit 4:3 – WGM13:2: Waveform Generation Mode See TCCR1A Register description. • Bit 2:0 – CS12:0: Clock Select The three clock select bits select the clock source to be used by the Timer/Counter, see Figure 41 on page 94 and Figure 42 on page 94. 7 0 1 1 1 Fast PWM, 10-bit 0x03FF BOTTOM TOP 8 1 0 0 0 PWM, Phase and Frequency Correct ICR1 BOTTOM BOTTOM 9 1 0 0 1 PWM, Phase and Frequency Correct OCR1A BOTTOM BOTTOM 10 1 0 1 0 PWM, Phase Correct ICR1 TOP BOTTOM 11 1 0 1 1 PWM, Phase Correct OCR1A TOP BOTTOM 12 1 1 0 0 CTC ICR1 Immediate MAX 13 1 1 0 1 (Reserved) – – – 14 1 1 1 0 Fast PWM ICR1 BOTTOM TOP 15 1 1 1 1 Fast PWM OCR1A BOTTOM TOP Table 39. Waveform Generation Mode Bit Description (Continued) Mode WGM13 WGM12 (CTC1) WGM11 (PWM11) WGM10 (PWM10) Timer/Counter Mode of Operation(1) TOP Update of OCR1x TOV1 Flag Set on Bit 7 6 5 4 3 2 1 0 ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 099 2486AA–AVR–02/2013 ATmega8(L) If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. Timer/Counter 1 – TCNT1H and TCNT1L The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and Low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 77. Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a Compare Match between TCNT1 and one of the OCR1x Registers. Writing to the TCNT1 Register blocks (removes) the Compare Match on the following timer clock for all compare units. Output Compare Register 1 A – OCR1AH and OCR1AL Output Compare Register 1 B – OCR1BH and OCR1BL Table 40. Clock Select Bit Description CS12 CS11 CS10 Description 0 0 0 No clock source. (Timer/Counter stopped) 0 0 1 clkI/O/1 (No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T1 pin. Clock on falling edge 1 1 1 External clock source on T1 pin. Clock on rising edge Bit 7 6 5 4 3 2 1 0 TCNT1[15:8] TCNT1H TCNT1[7:0] TCNT1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OCR1A[15:8] OCR1AH OCR1A[7:0] OCR1AL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OCR1B[15:8] OCR1BH OCR1B[7:0] OCR1BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0100 2486AA–AVR–02/2013 ATmega8(L) The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare Interrupt, or to generate a waveform output on the OC1x pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and Low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 77. Input Capture Register 1 – ICR1H and ICR1L The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator Output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and Low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 77. Timer/Counter Interrupt Mask Register – TIMSK(1) Note: 1. This register contains interrupt control bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections • Bit 5 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture Interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 46) is executed when the ICF1 Flag, located in TIFR, is set. • Bit 4 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A match interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 46) is executed when the OCF1A Flag, located in TIFR, is set. • Bit 3 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare B match interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 46) is executed when the OCF1B Flag, located in TIFR, is set. • Bit 2 – TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 46) is executed when the TOV1 Flag, located in TIFR, is set. Bit 7 6 5 4 3 2 1 0 ICR1[15:8] ICR1H ICR1[7:0] ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 – TOIE0 TIMSK Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0101 2486AA–AVR–02/2013 ATmega8(L) Timer/Counter Interrupt Flag Register – TIFR(1) Note: 1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are described in this section. The remaining bits are described in their respective timer sections • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value. ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location. • Bit 4 – OCF1A: Timer/Counter1, Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A (OCR1A). Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag. OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location. • Bit 3 – OCF1B: Timer/Counter1, Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B (OCR1B). Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag. OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location. • Bit 2 – TOV1: Timer/Counter1, Overflow Flag The setting of this flag is dependent of the WGM13:0 bits setting. In normal and CTC modes, the TOV1 Flag is set when the timer overflows. Refer to Table 39 on page 97 for the TOV1 Flag behavior when using another WGM13:0 bit setting. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. Bit 7 6 5 4 3 2 1 0 OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 – TOV0 TIFR Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0102 2486AA–AVR–02/2013 ATmega8(L) 8-bit Timer/Counter2 with PWM and Asynchronous Operation Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, phase Correct Pulse Width Modulator (PWM) • Frequency Generator • 10-bit Clock Prescaler • Overflow and Compare Match Interrupt Sources (TOV2 and OCF2) • Allows Clocking from External 32kHz Watch Crystal Independent of the I/O Clock Overview A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 45. For the actual placement of I/O pins, refer to “Pin Configurations” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “8-bit Timer/Counter Register Description” on page 114. Figure 45. 8-bit Timer/Counter Block Diagram Timer/Counter DATA BUS = TCNTn Waveform Generation OCn = 0 Control Logic = 0xFF BOTTOM TOP count clear direction TOVn (Int. Req.) OCn (Int. Req.) Synchronization Unit OCRn TCCRn ASSRn Status Flags clkI/O clkASY Synchronized Status Flags asynchronous Mode Select (ASn) TOSC1 T/C Oscillator TOSC2 Prescaler clkTn clkI/O103 2486AA–AVR–02/2013 ATmega8(L) Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clkT2). The double buffered Output Compare Register (OCR2) is compared with the Timer/Counter value at all times. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare Pin (OC2). For details, see “Output Compare Unit” on page 105. The Compare Match event will also set the Compare Flag (OCF2) which can be used to generate an Output Compare interrupt request. Definitions Many register and bit references in this document are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 2. However, when using the register or bit defines in a program, the precise form must be used (that is, TCNT2 for accessing Timer/Counter2 counter value and so on). The definitions in Table 41 are also used extensively throughout the document. Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The clock source clkT2 is by default equal to the MCU clock, clkI/O. When the AS2 bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see “Asynchronous Status Register – ASSR” on page 117. For details on clock sources and prescaler, see “Timer/Counter Prescaler” on page 120. Table 41. Definitions BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00). MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR2 Register. The assignment is dependent on the mode of operation.104 2486AA–AVR–02/2013 ATmega8(L) Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 46 shows a block diagram of the counter and its surrounding environment. Figure 46. Counter Unit Block Diagram Signal description (internal signals): count Increment or decrement TCNT2 by 1 direction Selects between increment and decrement clear Clear TCNT2 (set all bits to zero) clkT2 Timer/Counter clock TOP Signalizes that TCNT2 has reached maximum value BOTTOM Signalizes that TCNT2 has reached minimum value (zero) Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the clock select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of whether clkT2 is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in the Timer/Counter Control Register (TCCR2). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare Output OC2. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 108. The Timer/Counter Overflow (TOV2) Flag is set according to the mode of operation selected by the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt. DATA BUS TCNTn Control Logic count TOVn (Int. Req.) BOTTOM TOP direction clear TOSC1 T/C Oscillator TOSC2 Prescaler clkI/O clk Tn105 2486AA–AVR–02/2013 ATmega8(L) Output Compare Unit The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2). Whenever TCNT2 equals OCR2, the comparator signals a match. A match will set the Output Compare Flag (OCF2) at the next timer clock cycle. If enabled (OCIE2 = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF2 Flag is automatically cleared when the interrupt is executed. Alternatively, the OCF2 Flag can be cleared by software by writing a logical one to its I/O bit location. The waveform generator uses the match signal to generate an output according to operating mode set by the WGM21:0 bits and Compare Output mode (COM21:0) bits. The max and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation (see “Modes of Operation” on page 108). Figure 47 shows a block diagram of the Output Compare unit. Figure 47. Output Compare Unit, Block Diagram The OCR2 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2 Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR2 Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR2 Buffer Register, and if double buffering is disabled the CPU will access the OCR2 directly. OCFn (Int. Req.) = (8-bit Comparator ) OCRn OCxy DATA BUS TCNTn WGMn1:0 Waveform Generator TOP FOCn COMn1:0 BOTTOM106 2486AA–AVR–02/2013 ATmega8(L) Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC2) bit. Forcing Compare Match will not set the OCF2 Flag or reload/clear the timer, but the OC2 pin will be updated as if a real Compare Match had occurred (the COM21:0 bits settings define whether the OC2 pin is set, cleared or toggled). Compare Match Blocking by TCNT2 Write All CPU write operations to the TCNT2 Register will block any Compare Match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR2 to be initialized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is enabled. Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the Output Compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2 value, the Compare Match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. The setup of the OC2 should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2 value is to use the Force Output Compare (FOC2) strobe bit in Normal mode. The OC2 Register keeps its value even when changing between waveform generation modes. Be aware that the COM21:0 bits are not double buffered together with the compare value. Changing the COM21:0 bits will take effect immediately.107 2486AA–AVR–02/2013 ATmega8(L) Compare Match Output Unit The Compare Output mode (COM21:0) bits have two functions. The waveform generator uses the COM21:0 bits for defining the Output Compare (OC2) state at the next Compare Match. Also, the COM21:0 bits control the OC2 pin output source. Figure 48 shows a simplified schematic of the logic affected by the COM21:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM21:0 bits are shown. When referring to the OC2 state, the reference is for the internal OC2 Register, not the OC2 pin. Figure 48. Compare Match Output Unit, Schematic The general I/O port function is overridden by the Output Compare (OC2) from the waveform generator if either of the COM21:0 bits are set. However, the OC2 pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC2 pin (DDR_OC2) must be set as output before the OC2 value is visible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare Pin logic allows initialization of the OC2 state before the output is enabled. Note that some COM21:0 bit settings are reserved for certain modes of operation. See “8-bit Timer/Counter Register Description” on page 114. PORT DDR D Q D Q OCn OCn Pin D Q Waveform Generator COMn1 COMn0 0 1 DATABUS FOCn clkI/O108 2486AA–AVR–02/2013 ATmega8(L) Compare Output Mode and Waveform Generation The Waveform Generator uses the COM21:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM21:0 = 0 tells the waveform generator that no action on the OC2 Register is to be performed on the next Compare Match. For compare output actions in the nonPWM modes refer to Table 43 on page 115. For fast PWM mode, refer to Table 44 on page 115, and for phase correct PWM refer to Table 45 on page 116. A change of the COM21:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC2 strobe bits. Modes of Operation The mode of operation (that is, the behavior of the Timer/Counter and the Output Compare pins) is defined by the combination of the Waveform Generation mode (WGM21:0) and Compare Output mode (COM21:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM21:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM21:0 bits control whether the output should be set, cleared, or toggled at a Compare Match (see “Compare Match Output Unit” on page 107). For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 112. Normal Mode The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV2 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.109 2486AA–AVR–02/2013 ATmega8(L) Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the OCR2. The OCR2 defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 49. The counter value (TCNT2) increases until a Compare Match occurs between TCNT2 and OCR2, and then counter (TCNT2) is cleared. Figure 49. CTC Mode, Timing Diagram An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2 Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR2 is lower than the current value of TCNT2, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur. For generating a waveform output in CTC mode, the OC2 output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM21:0 = 1). The OC2 value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC2 = fclk_I/O/2 when OCR2 is set to zero (0x00). The waveform frequency is defined by the following equation: The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. TCNTn OCn (Toggle) OCn Interrupt Flag Set Period 1 2 3 4 (COMn1:0 = 1) f OCn f clk_I/O 2   N   1 + OCRn = ----------------------------------------------110 2486AA–AVR–02/2013 ATmega8(L) Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 3) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC2) is cleared on the Compare Match between TCNT2 and OCR2, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 50. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2. Figure 50. Fast PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the COM21:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM21:0 to 3 (see Table 44 on page 115). The actual OC2 value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC2 Register at the Compare Match between OCR2 and TCNT2, and clearing (or setting) the OC2 Register at the timer clock cycle the counter is cleared (changes from MAX to BOTTOM). The PWM frequency for the output can be calculated by the following equation: The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). TCNTn OCRn Update and TOVn Interrupt Flag Set Period 1 2 3 OCn OCn (COMn1:0 = 2) (COMn1:0 = 3) OCRn Interrupt Flag Set 4 5 6 7 f OCnPWM f clk_I/O N  256 = ------------------111 2486AA–AVR–02/2013 ATmega8(L) The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2 equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM21:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2 to toggle its logical level on each Compare Match (COM21:0 = 1). The waveform generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2 is set to zero. This feature is similar to the OC2 toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. Phase Correct PWM Mode The phase correct PWM mode (WGM21:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In noninverting Compare Output mode, the Output Compare (OC2) is cleared on the Compare Match between TCNT2 and OCR2 while upcounting, and set on the Compare Match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT2 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 51. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2. Figure 51. Phase Correct PWM Mode, Timing Diagram TOVn Interrupt Flag Set OCn Interrupt Flag Set 1 2 3 TCNTn Period OCn OCn (COMn1:0 = 2) (COMn1:0 = 3) OCRn Update112 2486AA–AVR–02/2013 ATmega8(L) The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the COM21:0 bits to 2 will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM21:0 to 3 (see Table 45 on page 116). The actual OC2 value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2 Register at the Compare Match between OCR2 and TCNT2 when the counter increments, and setting (or clearing) the OC2 Register at Compare Match between OCR2 and TCNT2 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR2 is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for noninverted PWM mode. For inverted PWM the output will have the opposite logic values. At the very start of period 2 in Figure 51 on page 111 OCn has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match: • OCR2A changes its value from MAX, like in Figure 51 on page 111. When the OCR2A value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match • The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up Timer/Counter Timing Diagrams The following figures show the Timer/Counter in Synchronous mode, and the timer clock (clkT2) is therefore shown as a clock enable signal. In Asynchronous mode, clkI/O should be replaced by the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are set. Figure 52 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 52. Timer/Counter Timing Diagram, no Prescaling f OCnPCPWM f clk_I/O N  510 = ------------------ clkTn (clkI/O/1) TOVn clkI/O TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1113 2486AA–AVR–02/2013 ATmega8(L) Figure 53 shows the same timing data, but with the prescaler enabled. Figure 53. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) Figure 54 shows the setting of OCF2 in all modes except CTC mode. Figure 54. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (fclk_I/O/8) TOVn TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 clkI/O clkTn (clkI/O/8) OCFn OCRn TCNTn OCRn Value OCRn - 1 OCRn OCRn + 1 OCRn + 2 clkI/O clkTn (clkI/O/8)114 2486AA–AVR–02/2013 ATmega8(L) Figure 55 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. Figure 55. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (fclk_I/O/8) 8-bit Timer/Counter Register Description Timer/Counter Control Register – TCCR2 • Bit 7 – FOC2: Force Output Compare The FOC2 bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2 is written when operating in PWM mode. When writing a logical one to the FOC2 bit, an immediate Compare Match is forced on the waveform generation unit. The OC2 output is changed according to its COM21:0 bits setting. Note that the FOC2 bit is implemented as a strobe. Therefore it is the value present in the COM21:0 bits that determines the effect of the forced compare. A FOC2 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2 as TOP. The FOC2 bit is always read as zero. • Bit 6:3 – WGM21:0: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 42 on page 115 and “Modes of Operation” on page 108. OCFn OCRn TCNTn (CTC) TOP TOP - 1 TOP BOTTOM BOTTOM + 1 clkI/O clkTn (clkI/O/8) Bit 7 6 5 4 3 2 1 0 FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 TCCR2 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0115 2486AA–AVR–02/2013 ATmega8(L) Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer • Bit 5:4 – COM21:0: Compare Match Output Mode These bits control the Output Compare Pin (OC2) behavior. If one or both of the COM21:0 bits are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC2 pin must be set in order to enable the output driver. When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0 bit setting. Table 43 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (non-PWM). Table 44 shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM mode. Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare Match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 110 for more details Table 42. Waveform Generation Mode Bit Description Mode WGM21 (CTC2) WGM20 (PWM2) Timer/Counter Mode of Operation(1) TOP Update of OCR2 TOV2 Flag Set 0 0 0 Normal 0xFF Immediate MAX 1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 1 0 CTC OCR2 Immediate MAX 3 1 1 Fast PWM 0xFF BOTTOM MAX Table 43. Compare Output Mode, Non-PWM Mode COM21 COM20 Description 0 0 Normal port operation, OC2 disconnected 0 1 Toggle OC2 on Compare Match 1 0 Clear OC2 on Compare Match 1 1 Set OC2 on Compare Match Table 44. Compare Output Mode, Fast PWM Mode(1) COM21 COM20 Description 0 0 Normal port operation, OC2 disconnected 0 1 Reserved 1 0 Clear OC2 on Compare Match, set OC2 at BOTTOM, (non-inverting mode) 1 1 Set OC2 on Compare Match, clear OC2 at BOTTOM, (inverting mode)116 2486AA–AVR–02/2013 ATmega8(L) Table 45 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct PWM mode. Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 111 for more details • Bit 2:0 – CS22:0: Clock Select The three clock select bits select the clock source to be used by the Timer/Counter, see Table 46. Timer/Counter Register – TCNT2 The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match between TCNT2 and the OCR2 Register. Output Compare Register – OCR2 The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2 pin. Table 45. Compare Output Mode, Phase Correct PWM Mode(1) COM21 COM20 Description 0 0 Normal port operation, OC2 disconnected 0 1 Reserved 1 0 Clear OC2 on Compare Match when up-counting. Set OC2 on Compare Match when downcounting 1 1 Set OC2 on Compare Match when up-counting. Clear OC2 on Compare Match when downcounting Table 46. Clock Select Bit Description CS22 CS21 CS20 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clkT2S/(No prescaling) 0 1 0 clkT2S/8 (From prescaler) 0 1 1 clkT2S/32 (From prescaler) 1 0 0 clkT2S/64 (From prescaler) 1 0 1 clkT2S/128 (From prescaler) 1 1 0 clkT2S/256 (From prescaler) 1 1 1 clkT2S/1024 (From prescaler) Bit 7 6 5 4 3 2 1 0 TCNT2[7:0] TCNT2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OCR2[7:0] OCR2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0117 2486AA–AVR–02/2013 ATmega8(L) Asynchronous Operation of the Timer/Counter Asynchronous Status Register – ASSR • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter 2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter 2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2, and TCCR2 might be corrupted. • Bit 2 – TCN2UB: Timer/Counter2 Update Busy When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value. • Bit 1 – OCR2UB: Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes set. When OCR2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2 is ready to be updated with a new value. • Bit 0 – TCR2UB: Timer/Counter Control Register2 Update Busy When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes set. When TCCR2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2 is ready to be updated with a new value. If a write is performed to any of the three Timer/Counter2 Registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. The mechanisms for reading TCNT2, OCR2, and TCCR2 are different. When reading TCNT2, the actual timer value is read. When reading OCR2 or TCCR2, the value in the temporary storage register is read. Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2, and TCCR2 might be corrupted. A safe procedure for switching clock source is: 1. Disable the Timer/Counter2 interrupts by clearing OCIE2 and TOIE2 2. Select clock source by setting AS2 as appropriate 3. Write new values to TCNT2, OCR2, and TCCR2 4. To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and TCR2UB 5. Clear the Timer/Counter2 Interrupt Flags 6. Enable interrupts, if needed • The Oscillator is optimized for use with a 32.768kHz watch crystal. Applying an external clock to the TOSC1 pin may result in incorrect Timer/Counter2 operation. The CPU main clock frequency must be more than four times the Oscillator frequency • When writing to one of the registers TCNT2, OCR2, or TCCR2, the value is transferred to a temporary register, and latched after two positive edges on TOSC1. The user should not Bit 7 6 5 4 3 2 1 0 – – – – AS2 TCN2UB OCR2UB TCR2UB ASSR Read/Write R R R R R/W R R R Initial Value 0 0 0 0 0 0 0 0118 2486AA–AVR–02/2013 ATmega8(L) write a new value before the contents of the temporary register have been transferred to its destination. Each of the three mentioned registers have their individual temporary register, which means that, for example, writing to TCNT2 does not disturb an OCR2 write in progress. To detect that a transfer to the destination register has taken place, the Asynchronous Status Register – ASSR has been implemented • When entering Power-save mode after having written to TCNT2, OCR2, or TCCR2, the user must wait until the written register has been updated if Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode before the changes are effective. This is particularly important if the Output Compare2 interrupt is used to wake up the device, since the Output Compare function is disabled during writing to OCR2 or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode before the OCR2UB bit returns to zero, the device will never receive a Compare Match interrupt, and the MCU will not wake up • If Timer/Counter2 is used to wake the device up from Power-save mode, precautions must be taken if the user wants to re-enter one of these modes: The interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and re-entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the user is in doubt whether the time before re-entering Power-save or Extended Standby mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: 1. Write a value to TCCR2, TCNT2, or OCR2 2. Wait until the corresponding Update Busy Flag in ASSR returns to zero 3. Enter Power-save or Extended Standby mode • When the asynchronous operation is selected, the 32.768kHZ Oscillator for Timer/Counter2 is always running, except in Power-down and Standby modes. After a Power-up Reset or Wake-up from Power-down or Standby mode, the user should be aware of the fact that this Oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using Timer/Counter2 after Power-up or Wake-up from Power-down or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after a wake-up from Power-down or Standby mode due to unstable clock signal upon startup, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin • Description of wake up from Power-save or Extended Standby mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP • Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When waking up from Powersave mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will read as the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-save mode is essentially unpredictable, as it depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows: 1. Write any value to either of the registers OCR2 or TCCR2 2. Wait for the corresponding Update Busy Flag to be cleared 3. Read TCNT2119 2486AA–AVR–02/2013 ATmega8(L) • During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the Interrupt Flag. The Output Compare Pin is changed on the timer clock and is not synchronized to the processor clock Timer/Counter Interrupt Mask Register – TIMSK • Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable When the OCIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter2 occurs (that is, when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register – TIFR). • Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs (that is, when the TOV2 bit is set in the Timer/Counter Interrupt Flag Register – TIFR). Timer/Counter Interrupt Flag Register – TIFR • Bit 7 – OCF2: Output Compare Flag 2 The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2 and the data in OCR2 – Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding interrupt Handling Vector. Alternatively, OCF2 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2 (Timer/Counter2 Compare Match Interrupt Enable), and OCF2 are set (one), the Timer/Counter2 Compare Match Interrupt is executed. • Bit 6 – TOV2: Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt Handling Vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00. Bit 7 6 5 4 3 2 1 0 OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 – TOIE0 TIMSK Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 – TOV0 TIFR Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0120 2486AA–AVR–02/2013 ATmega8(L) Timer/Counter Prescaler Figure 56. Prescaler for Timer/Counter2 The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clkI/O. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port B. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter2. The Oscillator is optimized for use with a 32.768kHz crystal. Applying an external clock source to TOSC1 is not recommended. For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clkT2S/32, clkT2S/64, clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected. Setting the PSR2 bit in SFIOR resets the prescaler. This allows the user to operate with a predictable prescaler. Special Function IO Register – SFIOR • Bit 1 – PSR2: Prescaler Reset Timer/Counter2 When this bit is written to one, the Timer/Counter2 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock. If this bit is written when Timer/Counter2 is operating in Asynchronous mode, the bit will remain one until the prescaler has been reset. 10-BIT T/C PRESCALER TIMER/COUNTER2 CLOCK SOURCE clkI/O clkT2S TOSC1 AS2 CS20 CS21 CS22 clkT2S/8 clkT2S/64 clkT2S/128 clkT2S/1024 clkT2S/256 clkT2S/32 0 PSR2 Clear clkT2 Bit 7 6 5 4 3 2 1 0 – – – – ACME PUD PSR2 PSR10 SFIOR Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0121 2486AA–AVR–02/2013 ATmega8(L) Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega8 and peripheral devices or between several AVR devices. The ATmega8 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode Figure 57. SPI Block Diagram(1) Note: 1. Refer to “Pin Configurations” on page 2, and Table 22 on page 58 for SPI pin placement The interconnection between Master and Slave CPUs with SPI is shown in Figure 58 on page 122. The system consists of two Shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective Shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line. When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a SPI2X SPI2X DIVIDER /2/4/8/16/32/64/128122 2486AA–AVR–02/2013 ATmega8(L) byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the Buffer Register for later use. When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission Flag, SPIF is set. If the SPI interrupt enable bit, SPIE, in the SPCR Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use. Figure 58. SPI Master-Slave Interconnection The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received character must be read from the SPI Data Register before the next character has been completely shifted in. Otherwise, the first byte is lost. In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high periods should be: Low period: longer than 2 CPU clock cycles High period: longer than 2 CPU clock cycles When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 47. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 56. Note: 1. See “Port B Pins Alternate Functions” on page 58 for a detailed description of how to define the direction of the user defined SPI pins Table 47. SPI Pin Overrides(1) Pin Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input MSB MASTER LSB 8 BIT SHIFT REGISTER MSB SLAVE LSB 8 BIT SHIFT REGISTER MISO MOSI SPI CLOCK GENERATOR SCK SS MISO MOSI SCK SS VCC SHIFT ENABLE123 2486AA–AVR–02/2013 ATmega8(L) The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. For example if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. Note: 1. See “About Code Examples” on page 8 Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<>8); UBRRL = (unsigned char)ubrr; /* Enable receiver and transmitter */ UCSRB = (1<> 1) & 0x01; return ((resh << 8) | resl); }141 2486AA–AVR–02/2013 ATmega8(L) Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXC) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (that is, does not contain any unread data). If the Receiver is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit will become zero. When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART Receive Complete Interrupt will be executed as long as the RXC Flag is set (provided that global interrupts are enabled). When interrupt-driven data reception is used, the receive complete routine must read the received data from UDR in order to clear the RXC Flag, otherwise a new interrupt will occur once the interrupt routine terminates. Receiver Error Flags The USART Receiver has three error flags: Frame Error (FE), Data OverRun (DOR) and Parity Error (PE). All can be accessed by reading UCSRA. Common for the error flags is that they are located in the receive buffer together with the frame for which they indicate the error status. Due to the buffering of the error flags, the UCSRA must be read before the receive buffer (UDR), since reading the UDR I/O location changes the buffer read location. Another equality for the error flags is that they can not be altered by software doing a write to the flag location. However, all flags must be set to zero when the UCSRA is written for upward compatibility of future USART implementations. None of the error flags can generate interrupts. The Frame Error (FE) Flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. The FE Flag is zero when the stop bit was correctly read (as one), and the FE Flag will be one when the stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. The FE Flag is not affected by the setting of the USBS bit in UCSRC since the Receiver ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when writing to UCSRA. The Data OverRun (DOR) Flag indicates data loss due to a Receiver buffer full condition. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. If the DOR Flag is set there was one or more serial frame lost between the frame last read from UDR, and the next frame read from UDR. For compatibility with future devices, always write this bit to zero when writing to UCSRA. The DOR Flag is cleared when the frame received was successfully moved from the Shift Register to the receive buffer. The Parity Error (PE) Flag indicates that the next frame in the receive buffer had a parity error when received. If parity check is not enabled the PE bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRA. For more details see “Parity Bit Calculation” on page 134 and “Parity Checker” . Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (PE) Flag can then be read by software to check if the frame had a parity error. The PE bit is set if the next character that can be read from the receive buffer had a parity error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is read.142 2486AA–AVR–02/2013 ATmega8(L) Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (that is, the RXEN is set to zero) the Receiver will no longer override the normal function of the RxD port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost Flushing the Receive Buffer The Receiver buffer FIFO will be flushed when the Receiver is disabled (that is, the buffer will be emptied of its contents). Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDR I/O location until the RXC Flag is cleared. The following code example shows how to flush the receive buffer. Note: 1. See “About Code Examples” on page 8 Asynchronous Data Reception The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the RxD pin. The data recovery logic samples and low pass filters each incoming bit, thereby improving the noise immunity of the Receiver. The asynchronous reception operational range depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. Asynchronous Clock Recovery The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 65 illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The horizontal arrows illustrate the synchronization variation due to the sampling process. Note the larger time variation when using the Double Speed mode (U2X = 1) of operation. Samples denoted zero are samples done when the RxD line is idle (that is, no communication activity). Figure 65. Start Bit Sampling When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in Assembly Code Example(1) USART_Flush: sbis UCSRA, RXC ret in r16, UDR rjmp USART_Flush C Code Example(1) void USART_Flush( void ) { unsigned char dummy; while ( UCSRA & (1< 2 CPU clock cycles for fck <12MHz, 3 CPU clock cycles for fck >=12MHz High:> 2 CPU clock cycles for fck <12MHz, 3 CPU clock cycles for fck >=12MHz Table 96. Pin Mapping Serial Programming Symbol Pins I/O Description MOSI PB3 I Serial data in MISO PB4 O Serial data out SCK PB5 I Serial clock VCC GND XTAL1 SCK MISO MOSI RESET PB3 PB4 PB5 +2.7V - 5.5V AVCC +2.7V - 5.5V (2)231 2486AA–AVR–02/2013 ATmega8(L) Serial Programming Algorithm When writing serial data to the ATmega8, data is clocked on the rising edge of SCK. When reading data from the ATmega8, data is clocked on the falling edge of SCK. See Figure 113 on page 232 for timing details. To program and verify the ATmega8 in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in Table 98 on page 233): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during Power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0” 2. Wait for at least 20ms and enable Serial Programming by sending the Programming Enable serial instruction to pin MOSI 3. The Serial Programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command 4. The Flash is programmed one page at a time. The page size is found in Table 89 on page 218. The memory page is loaded one byte at a time by supplying the 5 LSB of the address and data together with the Load Program memory Page instruction. To ensure correct loading of the page, the data Low byte must be loaded before data High byte is applied for a given address. The Program memory Page is stored by loading the Write Program memory Page instruction with the 7MSB of the address. If polling is not used, the user must wait at least tWD_FLASH before issuing the next page (see Table 97 on page 232). Note: If other commands than polling (read) are applied before any write operation (FLASH, EEPROM, Lock Bits, Fuses) is completed, it may result in incorrect programming 5. The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not used, the user must wait at least tWD_EEPROM before issuing the next byte (see Table 97 on page 232). In a chip erased device, no 0xFFs in the data file(s) need to be programmed 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO 7. At the end of the programming session, RESET can be set high to commence normal operation 8. Power-off sequence (if needed): Set RESET to “1” Turn VCC power off Data Polling Flash When a page is being programmed into the Flash, reading an address location within the page being programmed will give the value 0xFF. At the time the device is ready for a new page, the programmed value will read correctly. This is used to determine when the next page can be written. Note that the entire page is written simultaneously and any address within the page can be used for polling. Data polling of the Flash will not work for the value 0xFF, so when programming this value, the user will have to wait for at least tWD_FLASH before programming the next page. As a chip-erased device contains 0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be skipped. See Table 97 on page 232 for tWD_FLASH value.232 2486AA–AVR–02/2013 ATmega8(L) Data Polling EEPROM When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value 0xFF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value 0xFF, but the user should have the following in mind: As a chip-erased device contains 0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be skipped. This does not apply if the EEPROM is Re-programmed without chip-erasing the device. In this case, data polling cannot be used for the value 0xFF, and the user will have to wait at least tWD_EEPROM before programming the next byte. See Table 97 for tWD_EEPROM value. Figure 113. Serial Programming Waveforms Table 97. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay tWD_FUSE 4.5ms tWD_FLASH 4.5ms tWD_EEPROM 9.0ms tWD_ERASE 9.0ms MSB MSB LSB LSB SERIAL CLOCK INPUT (SCK) SERIAL DATA INPUT (MOSI) (MISO) SAMPLE SERIAL DATA OUTPUT233 2486AA–AVR–02/2013 ATmega8(L) Note: a = address high bits b = address low bits H = 0 – Low byte, 1 – High byte o = data out i = data in x = don’t care Table 98. Serial Programming Instruction Set Instruction Instruction Format Byte 1 Byte 2 Byte 3 Byte 4 Operation Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after RESET goes low Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash Read Program Memory 0010 H000 0000 aaaa bbbb bbbb oooo oooo Read H (high or low) data o from Program memory at word address a:b Load Program Memory Page 0100 H000 0000 xxxx xxxb bbbb iiii iiii Write H (high or low) data i to Program memory page at word address b. Data Low byte must be loaded before Data High byte is applied within the same address Write Program Memory Page 0100 1100 0000 aaaa bbbx xxxx xxxx xxxx Write Program memory Page at address a:b Read EEPROM Memory 1010 0000 00xx xxxa bbbb bbbb oooo oooo Read data o from EEPROM memory at address a:b Write EEPROM Memory 1100 0000 00xx xxxa bbbb bbbb iiii iiii Write data i to EEPROM memory at address a:b Read Lock Bits 0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock Bits. “0” = programmed, “1” = unprogrammed. See Table 85 on page 215 for details Write Lock Bits 1010 1100 111x xxxx xxxx xxxx 11ii iiii Write Lock Bits. Set bits = “0” to program Lock Bits. See Table 85 on page 215 for details Read Signature Byte 0011 0000 00xx xxxx xxxx xxbb oooo oooo Read Signature Byte o at address b Write Fuse Bits 1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to unprogram. See Table 88 on page 217 for details Write Fuse High Bits 1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to unprogram. See Table 87 on page 216 for details Read Fuse Bits 0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fuse Bits. “0” = programmed, “1” = unprogrammed. See Table 88 on page 217 for details Read Fuse High Bits 0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fuse high bits. “0” = programmed, “1” = unprogrammed. See Table 87 on page 216 for details Read Calibration Byte 0011 1000 00xx xxxx 0000 00bb oooo oooo Read Calibration Byte234 2486AA–AVR–02/2013 ATmega8(L) SPI Serial Programming Characteristics For characteristics of the SPI module, see “SPI Timing Characteristics” on page 239.235 2486AA–AVR–02/2013 ATmega8(L) Electrical Characteristics – TA = -40°C to 85°C Note: Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. DC Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Maximum Operating Voltage ............................................ 6.0V DC Current per I/O Pin ................................................ 40.0mA DC Current VCC and GND Pins................................. 300.0mA TA = -40C to +85C, VCC = 2.7V to 5.5V (unless otherwise noted) Symbol Parameter Condition Min Typ Max Units VIL Input Low Voltage except XTAL1 and RESET pins VCC = 2.7V - 5.5V -0.5 0.2 VCC(1) V VIH Input High Voltage except XTAL1 and RESET pins VCC = 2.7V - 5.5V 0.6VCC(2) VCC + 0.5 VIL1 Input Low Voltage XTAL1 pin VCC = 2.7V - 5.5V -0.5 0.1VCC(1) VIH1 Input High Voltage XTAL 1 pin VCC = 2.7V - 5.5V 0.8VCC(2) VCC + 0.5 VIL2 Input Low Voltage RESET pin VCC = 2.7V - 5.5V -0.5 0.2 VCC VIH2 Input High Voltage RESET pin VCC = 2.7V - 5.5V 0.9VCC(2) VCC + 0.5 VIL3 Input Low Voltage RESET pin as I/O VCC = 2.7V - 5.5V -0.5 0.2VCC VIH3 Input High Voltage RESET pin as I/O VCC = 2.7V - 5.5V 0.6VCC(2) 0.7VCC(2) VCC + 0.5 VOL Output Low Voltage(3) (Ports B,C,D) I OL = 20mA, VCC = 5V IOL = 10mA, VCC = 3V 0.9 0.6 VOH Output High Voltage(4) (Ports B,C,D) I OH = -20mA, VCC = 5V IOH = -10mA, VCC = 3V 4.2 2.2 IIL Input Leakage Current I/O Pin Vcc = 5.5V, pin low (absolute value) 1 µA I IH Input Leakage Current I/O Pin Vcc = 5.5V, pin high (absolute value) 1 RRST Reset Pull-up Resistor 30 80 k236 2486AA–AVR–02/2013 ATmega8(L) Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low 2. “Min” means the lowest value where the pin is guaranteed to be read as high 3. Although each I/O port can sink more than the test conditions (20mA at Vcc = 5V, 10mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed: PDIP, TQFP, and QFN/MLF Package: 1] The sum of all IOL, for all ports, should not exceed 300mA. 2] The sum of all IOL, for ports C0 - C5 should not exceed 100mA. 3] The sum of all IOL, for ports B0 - B7, C6, D0 - D7 and XTAL2, should not exceed 200mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition 4. Although each I/O port can source more than the test conditions (20mA at Vcc = 5V, 10mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed: PDIP, TQFP, and QFN/MLF Package: 1] The sum of all IOH, for all ports, should not exceed 300mA. 2] The sum of all IOH, for port C0 - C5, should not exceed 100mA. 3] The sum of all IOH, for ports B0 - B7, C6, D0 - D7 and XTAL2, should not exceed 200mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition 5. Minimum VCC for Power-down is 2.5V Rpu I/O Pin Pull-up Resistor 20 50 k ICC Power Supply Current Active 4MHz, VCC = 3V (ATmega8L) 3 5 mA Active 8MHz, VCC = 5V (ATmega8) 11 15 Idle 4MHz, VCC = 3V (ATmega8L) 1 2 Idle 8MHz, VCC = 5V (ATmega8) 4.5 7 Power-down mode(5) WDT enabled, VCC = 3V < 22 28 µA WDT disabled, VCC = 3V < 1 3 VACIO Analog Comparator Input Offset Voltage VCC = 5V Vin = VCC/2 40 mV IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/2 -50 50 nA tACPD Analog Comparator Propagation Delay VCC = 2.7V VCC = 5.0V 750 500 ns TA = -40C to +85C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition Min Typ Max Units237 2486AA–AVR–02/2013 ATmega8(L) External Clock Drive Waveforms Figure 114. External Clock Drive Waveforms External Clock Drive Notes: 1. R should be in the range 3k - 100k, and C should be at least 20pF. The C values given in the table includes pin capacitance. This will vary with package type 2. The frequency will vary with package type and board layout VIL1 VIH1 Table 99. External Clock Drive Symbol Parameter VCC = 2.7V to 5.5V VCC = 4.5V to 5.5V Min Max Min Max Units 1/tCLCL Oscillator Frequency 0 8 0 16 MHz tCLCL Clock Period 125 62.5 tCHCX High Time 50 25 ns tCLCX Low Time 50 25 tCLCH Rise Time 1.6 0.5 s tCHCL Fall Time 1.6 0.5 tCLCL Change in period from one clock cycle to the next 2 2% Table 100. External RC Oscillator, Typical Frequencies R [k] (1) C [pF] f(2) 33 22 650kHz 10 22 2.0MHz238 2486AA–AVR–02/2013 ATmega8(L) Two-wire Serial Interface Characteristics Table 101 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega8 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 115 on page 239. Notes: 1. In ATmega8, this parameter is characterized and not 100% tested 2. Required only for fSCL > 100kHz 3. Cb = capacitance of one bus line in pF 4. fCK = CPU clock frequency Table 101. Two-wire Serial Bus Requirements Symbol Parameter Condition Min Max Units VIL Input Low-voltage -0.5 0.3VCC V VIH Input High-voltage 0.7VCC VCC + 0.5 Vhys(1) Hysteresis of Schmitt Trigger Inputs 0.05VCC(2) – VOL(1) Output Low-voltage 3mA sink Current 0 0.4 tr (1) Rise Time for both SDA and SCL 20 + 0.1Cb (3)(2) 300 tof ns (1) Output Fall Time from VIHmin to VILmax 10pF < Cb < 400pF(3) 20 + 0.1Cb (3)(2) 250 tSP(1) Spikes Suppressed by Input Filter 0 50(2) Ii Input Current each I/O Pin 0.1VCC < Vi < 0.9VCC -10 10 µA Ci (1) Capacitance for each I/O Pin – 10 pF fSCL SCL Clock Frequency fCK(4) > max(16fSCL, 250kHz)(5) 0 400 kHz Rp Value of Pull-up resistor fSCL  100kHz fSCL > 100kHz tHD;STA Hold Time (repeated) START Condition fSCL  100kHz 4.0 – µs fSCL > 100kHz 0.6 – tLOW Low Period of the SCL Clock fSCL  100kHz(6) 4.7 – fSCL > 100kHz(7) 1.3 – tHIGH High period of the SCL clock fSCL  100kHz 4.0 – fSCL > 100kHz 0.6 – tSU;STA Set-up time for a repeated START condition fSCL  100kHz 4.7 – fSCL > 100kHz 0.6 – tHD;DAT Data hold time fSCL  100kHz 0 3.45 fSCL > 100kHz 0 0.9 tSU;DAT Data setup time fSCL  100kHz 250 – ns fSCL > 100kHz 100 – tSU;STO Setup time for STOP condition fSCL  100kHz 4.0 – µs fSCL > 100kHz 0.6 – tBUF Bus free time between a STOP and START condition fSCL  100kHz 4.7 – fSCL > 100kHz 1.3 – VCC – 0.4V 3mA ---------------------------- 1000ns Cb -------------------  VCC – 0.4V 3mA ---------------------------- 300ns Cb ----------------239 2486AA–AVR–02/2013 ATmega8(L) 5. This requirement applies to all ATmega8 Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial Bus need only obey the general fSCL requirement 6. The actual low period generated by the ATmega8 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus fCK must be greater than 6MHz for the low time requirement to be strictly met at fSCL = 100kHz 7. The actual low period generated by the ATmega8 Two-wire Serial Interface is (1/fSCL - 2/fCK), thus the low time requirement will not be strictly met for fSCL > 308kHz when fCK = 8MHz. Still, ATmega8 devices connected to the bus may communicate at full speed (400kHz) with other ATmega8 devices, as well as any other device with a proper tLOW acceptance margin Figure 115. Two-wire Serial Bus Timing SPI Timing Characteristics See Figure 116 on page 240 and Figure 117 on page 240 for details. Note: 1. In SPI Programming mode the minimum SCK high/low period is: - 2tCLCL for fCK < 12MHz - 3tCLCL for fCK > 12MHz t SU;STA t LOW t HIGH t LOW t of t HD;STA t HD;DAT t SU;DAT t SU;STO t BUF SCL SDA t r Table 102. SPI Timing Parameters Description Mode Min Typ Max 1 SCK period Master See Table 50 on page 126 ns 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.5 • tSCK 7 SCK to out Master 10 8 SCK to out high Master 10 9 SS low to out Slave 15 10 SCK period Slave 4 • tck 11 SCK high/low(1) Slave 2 • tck 12 Rise/Fall time Slave 1600 13 Setup Slave 10 14 Hold Slave 10 15 SCK to out Slave 15 16 SCK to SS high Slave 20 17 SS high to tri-state Slave 10 18 SS low to SCK Salve 2 • tck240 2486AA–AVR–02/2013 ATmega8(L) Figure 116. SPI interface timing requirements (Master Mode) Figure 117. SPI interface timing requirements (Slave Mode) MOSI (Data Output) SCK (CPOL = 1) MISO (Data Input) SCK (CPOL = 0) SS MSB LSB MSB LSB ... ... 6 1 2 2 4 5 3 7 8 MISO (Data Output) SCK (CPOL = 1) MOSI (Data Input) SCK (CPOL = 0) SS MSB LSB MSB LSB ... ... 10 11 11 13 14 12 15 17 9 X 16 18241 2486AA–AVR–02/2013 ATmega8(L) ADC Characteristics Notes: 1. Values are guidelines only 2. Minimum for AVCC is 2.7V 3. Maximum for AVCC is 5.5V 4. Maximum conversion time is 1/50kHz × 25 = 0.5ms Table 103. ADC Characteristics Symbol Parameter Condition Min(1) Typ(1) Max(1) Units Resolution Single Ended Conversion 10 Bits Absolute accuracy (including INL, DNL, Quantization Error, Gain, and Offset Error) Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200kHz 1.75 LSB Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 1MHz 3 Integral Non-linearity (INL) Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200kHz 0.75 Differential Non-linearity (DNL) Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200kHz 0.5 Gain Error Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200kHz 1 Offset Error Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200kHz 1 Conversion Time(4) Free Running Conversion 13 260 µs Clock Frequency 50 1000 kHz AVCC Analog Supply Voltage VCC - 0.3(2) VCC + 0.3(3) V VREF Reference Voltage 2.0 AVCC VIN Input voltage GND VREF Input bandwidth 38.5 kHz VINT Internal Voltage Reference 2.3 2.56 2.9 V RREF Reference Input Resistance 32 k RAIN Analog Input Resistance 55 100 M242 2486AA–AVR–02/2013 ATmega8(L) Electrical Characteristics – TA = -40°C to 105°C Note: Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Maximum Operating Voltage ............................................ 6.0V DC Current per I/O Pin ............................................... 40.0 mA DC Current VCC and GND Pins................................ 200.0 mA DC Characteristics TA = -40C to 105C, VCC = 2.7V to 5.5V (unless otherwise noted) Symbol Parameter Condition Min Typ Max Units VIL Input Low Voltage Except XTAL1 pin -0.5 0.2 VCC(1) V VIL1 Input Low Voltage XTAL1 pin, External Clock Selected -0.5 0.1 VCC(1) V VIH Input High Voltage Except XTAL1 and RESET pins 0.6 VCC(2) VCC + 0.5 V VIH1 Input High Voltage XTAL1 pin, External Clock Selected 0.8 VCC(2) VCC + 0.5 V VIH2 Input High Voltage RESET pin 0.9 VCC(2) VCC + 0.5 V VOL Output Low Voltage(3) (Ports A,B,C,D) I OL = 20 mA, VCC = 5V IOL = 10 mA, VCC = 3V 0.8 0.6 V V VOH Output High Voltage(4) (Ports A,B,C,D) IOH = -20 mA, VCC = 5V IOH = -10 mA, VCC = 3V 4.0 2.2 V V IIL Input Leakage Current I/O Pin Vcc = 5.5V, pin low (absolute value) 3 µA IIH Input Leakage Current I/O Pin Vcc = 5.5V, pin high (absolute value) 3 µA RRST Reset Pull-up Resistor 30 80 k Rpu I/O Pin Pull-up Resistor 20 50 k243 2486AA–AVR–02/2013 ATmega8(L) Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low 2. “Min” means the lowest value where the pin is guaranteed to be read as high 3. Although each I/O port can sink more than the test conditions (20mA at Vcc = 5V, 10mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed: PDIP Package: 1] The sum of all IOL, for all ports, should not exceed 400 mA. 2] The sum of all IOL, for ports C0 - C5 should not exceed 200 mA. 3] The sum of all IOL, for ports B0 - B7, C6, D0 - D7 and XTAL2, should not exceed 100 mA. TQFP and MLF Package: 1] The sum of all IOL, for all ports, should not exceed 400 mA. 2] The sum of all IOL, for ports C0 - C5, should not exceed 200 mA. 3] The sum of all IOL, for ports C6, D0 - D4, should not exceed 300 mA. 4] The sum of all IOL, for ports B0 - B7, D5 - D7, should not exceed 300 mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test conditions (20mA at Vcc = 5V, 10mA at Vcc = 3V) under steady state conditions (non-transient), the following must be observed: PDIP Package: 1] The sum of all IOH, for all ports, should not exceed 400 mA. 2] The sum of all IOH, for port C0 - C5, should not exceed 100 mA. 3] The sum of all IOH, for ports B0 - B7, C6, D0 - D7 and XTAL2, should not exceed 100 mA. TQFP and MLF Package: 1] The sum of all IOH, for all ports, should not exceed 400 mA. 2] The sum of all IOH, for ports C0 - C5, should not exceed 200 mA. 3] The sum of all IOH, for ports C6, D0 - D4, should not exceed 300 mA. 4] The sum of all IOH, for ports B0 - B7, D5 - D7, should not exceed 300 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. Minimum VCC for Power-down is 2.5V. I CC Power Supply Current Active 4 MHz, VCC = 3V (ATmega8L) 6 mA Active 8 MHz, VCC = 5V (ATmega8) 15 mA Idle 4 MHz, VCC = 3V (ATmega8L) 3 mA Idle 8 MHz, VCC = 5V (ATmega8) 8 mA Power-down mode(5) WDT enabled, VCC = 3V 35 µA WDT disabled, VCC = 3V 6 µA VACIO Analog Comparator Input Offset Voltage VCC = 5V Vin = VCC/2 20 mV IACLK Analog Comparator Input Leakage Current VCC = 5V Vin = VCC/2 -50 50 nA tACPD Analog Comparator Propagation Delay VCC = 2.7V VCC = 5.0V 750 500 ns DC Characteristics TA = -40C to 105C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition Min Typ Max Units244 2486AA–AVR–02/2013 ATmega8(L) ATmega8 Typical Characteristics – TA = -40°C to 85°C The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with Rail-to-Rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as: CL × VCC × f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. Active Supply Current Figure 118. Active Supply Current vs. Frequency (0.1MHz - 1.0MHz) 0 0.5 1 1.5 2 2.5 3 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) ICC (mA) 5.5V 5.0V 4.5V 3.3V 3.0V 2.7V 4.0V245 2486AA–AVR–02/2013 ATmega8(L) Figure 119. Active Supply Current vs. Frequency (1MHz - 20MHz) Figure 120. Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz) 0 5 10 15 20 25 30 0246 8 10 12 14 16 18 20 Frequency (MHz) ICC (mA) 5.5V 5.0V 4.5V 3.3V 2.7V 3.0V 0 2 4 6 8 10 12 14 16 18 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 85°C 25°C -40°C246 2486AA–AVR–02/2013 ATmega8(L) Figure 121. Active Supply Current vs. VCC (Internal RC Oscillator, 4MHz) Figure 122. Active Supply Current vs. VCC (Internal RC Oscillator, 2MHz) 0 2 4 6 8 10 12 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 85°C 25°C -40°C 0 1 2 3 4 5 6 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 85°C 25°C -40°C247 2486AA–AVR–02/2013 ATmega8(L) Figure 123. Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) Figure 124. Active Supply Current vs. VCC (32kHz External Oscillator) 0 0.5 1 1.5 2 2.5 3 3.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 25°C 85°C -40°C 0 20 40 60 80 100 120 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA) 25°C248 2486AA–AVR–02/2013 ATmega8(L) Idle Supply Current Figure 125. Idle Supply Current vs. Frequency (0.1MHz - 1.0MHz) Figure 126. Idle Supply Current vs. Frequency (1MHz - 20MHz) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) ICC (mA) 5.5V 4.5V 4.0V 3.3V 3.0V 2.7V 5.0V 0 2 4 6 8 10 12 14 0246 8 10 12 14 16 18 20 Frequency (MHz) ICC (mA) 5.5V 4.5V 4.0V 3.3V 3.0V 2.7V 5.0V249 2486AA–AVR–02/2013 ATmega8(L) Figure 127. Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz) Figure 128. Idle Supply Current vs. VCC (Internal RC Oscillator, 4MHz) 0 1 2 3 4 5 6 7 8 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 85°C 25°C -40°C 0 0.5 1 1.5 2 2.5 3 3.5 4 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 85°C 25°C -40°C250 2486AA–AVR–02/2013 ATmega8(L) Figure 129. Idle Supply Current vs. VCC (Internal RC Oscillator, 2MHz) Figure 130. Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 85°C 25°C -40°C 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 85°C 25°C -40°C251 2486AA–AVR–02/2013 ATmega8(L) Figure 131. Idle Supply Current vs. VCC (32kHz External Oscillator) Power-down Supply Current Figure 132. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 0 5 10 15 20 25 30 35 40 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA) 25°C 0 0.5 1 1.5 2 2.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA) 85°C 25°C -40°C252 2486AA–AVR–02/2013 ATmega8(L) Figure 133. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) Power-save Supply Current Figure 134. Power-save Supply Current vs. VCC (Watchdog Timer Disabled) 0 10 20 30 40 50 60 70 80 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA) 85°C 25°C -40°C 0 5 10 15 20 25 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA) 25°C253 2486AA–AVR–02/2013 ATmega8(L) Standby Supply Current Figure 135. Standby Supply Current vs. VCC (455kHz Resonator, Watchdog Timer Disabled) Figure 136. Standby Supply Current vs. VCC (1MHz Resonator, Watchdog Timer Disabled) 0 10 20 30 40 50 60 70 80 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA) 0 10 20 30 40 50 60 70 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA)254 2486AA–AVR–02/2013 ATmega8(L) Figure 137. Standby Supply Current vs. VCC (2MHz Resonator, Watchdog Timer Disabled) Figure 138. Standby Supply Current vs. VCC (2MHz Xtal, Watchdog Timer Disabled) 0 10 20 30 40 50 60 70 80 90 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA) 0 10 20 30 40 50 60 70 80 90 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA)255 2486AA–AVR–02/2013 ATmega8(L) Figure 139. Standby Supply Current vs. VCC (4MHz Resonator, Watchdog Timer Disabled) Figure 140. Standby Supply Current vs. VCC (4MHz Xtal, Watchdog Timer Disabled) 0 20 40 60 80 100 120 140 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA) 0 20 40 60 80 100 120 140 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA)256 2486AA–AVR–02/2013 ATmega8(L) Figure 141. Standby Supply Current vs. VCC (6MHz Resonator, Watchdog Timer Disabled) Figure 142. Standby Supply Current vs. VCC (6MHz Xtal, Watchdog Timer Disabled) 0 20 40 60 80 100 120 140 160 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA) 0 20 40 60 80 100 120 140 160 180 200 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA)257 2486AA–AVR–02/2013 ATmega8(L) Pin Pull-up Figure 143. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) Figure 144. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 0 20 40 60 80 100 120 140 160 012 3 4 56 VOP (V) IIO (µA) 85°C 25°C -40°C 0 10 20 30 40 50 60 70 80 90 0 0.5 1 1.5 2 2.5 3 VOP (V) IIO (µA) 85°C 25°C -40°C258 2486AA–AVR–02/2013 ATmega8(L) Figure 145. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) Figure 146. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 0 20 40 60 80 100 012 VRESET (V) IRESET (µA) 85°C 25°C - 40°C 0 5 10 15 20 25 30 35 40 45 0 0.5 1 1.5 2 2.5 VRESET (V) IRESET (µA) 85°C 25°C -40°C259 2486AA–AVR–02/2013 ATmega8(L) Pin Driver Strength Figure 147. I/O Pin Source Current vs. Output Voltage (VCC = 5V) Figure 148. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) 0 10 20 30 40 50 60 70 80 VOH (V) IOH (mA) 85°C 25°C -40°C 0 5 10 15 20 25 30 0 0.5 1 1.5 2 2.5 3 VOH (V) IOH (mA) 85°C 25°C -40°C260 2486AA–AVR–02/2013 ATmega8(L) Figure 149. I/O Pin Sink Current vs. Output Voltage (VCC = 5V) Figure 150. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V) 0 10 20 30 40 50 60 70 80 90 0 0.5 1 1.5 2 2.5 VOL (V) IOL (mA) 85°C 25°C -40°C 0 5 10 15 20 25 30 35 0 0.5 1 1.5 2 2.5 VOL (V) IOL (mA) 85°C 25°C -40°C261 2486AA–AVR–02/2013 ATmega8(L) Figure 151. Reset Pin as I/O – Pin Source Current vs. Output Voltage (VCC = 5V) Figure 152. Reset Pin as I/O – Pin Source Current vs. Output Voltage (VCC = 2.7V) 0 0.5 1 1.5 2 2.5 3 3.5 4 2 2.5 3 3.5 4 4.5 VOH (V) Current (mA) 85°C 25°C -40°C 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 VOH (V) Current (mA) 85°C 25°C -40°C262 2486AA–AVR–02/2013 ATmega8(L) Figure 153. Reset Pin as I/O – Pin Sink Current vs. Output Voltage (VCC = 5V) Figure 154. Reset Pin as I/O – Pin Sink Current vs. Output Voltage (VCC = 2.7V) 0 2 4 6 8 10 12 14 0 0.5 1 1.5 2 2.5 VOL (V) Current (mA) 85°C 25°C -40°C 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 0.5 1 1.5 2 2.5 VOL (V) Current (mA) 85°C 25°C -40°C263 2486AA–AVR–02/2013 ATmega8(L) Pin Thresholds and Hysteresis Figure 155. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) Figure 156. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) 0 0.5 1 1.5 2 2.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V) 85°C 25°C -40°C 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V) 85°C 25°C -40°C264 2486AA–AVR–02/2013 ATmega8(L) Figure 157. I/O Pin Input Hysteresis vs. VCC Figure 158. Reset Pin as I/O – Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Input Hysteresis (V) 85°C 25°C -40°C 0 0.5 1 1.5 2 2.5 3 3.5 4 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V) 85°C 25°C -40°C265 2486AA–AVR–02/2013 ATmega8(L) Figure 159. Reset Pin as I/O – Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) Figure 160. Reset Pin as I/O – Pin Hysteresis vs. VCC 0 0.5 1 1.5 2 2.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V) 85°C 25°C -40°C 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Input Hysteresis (V) 85°C 25°C -40°C266 2486AA–AVR–02/2013 ATmega8(L) Figure 161. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as “1”) Figure 162. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as “0”) 0 0.5 1 1.5 2 2.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V) 85°C 25°C -40°C 0 0.5 1 1.5 2 2.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V) 85°C 25°C -40°C267 2486AA–AVR–02/2013 ATmega8(L) Figure 163. Reset Input Pin Hysteresis vs. VCC Bod Thresholds and Analog Comparator Offset Figure 164. BOD Thresholds vs. Temperature (BOD Level is 4.0V) 0 0.2 0.4 0.6 0.8 1 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Input Hysteresis (V) 85°C 25°C -40°C 3.7 3.8 3.9 4 4.1 4.2 4.3 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (°C) Threshold (V) Rising VCC Falling VCC268 2486AA–AVR–02/2013 ATmega8(L) Figure 165. BOD Thresholds vs. Temperature (BOD Level is 2.7V) Figure 166. Bandgap Voltage vs. VCC 2.4 2.5 2.6 2.7 2.8 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (°C) Threshold (V) Rising VCC Falling VCC 1.29 1.295 1.3 1.305 1.31 1.315 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Bandgap Voltage (V) -40°C 25°C 85°C269 2486AA–AVR–02/2013 ATmega8(L) Figure 167. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V) Figure 168. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 2.7V) -0.006 -0.005 -0.004 -0.003 -0.002 -0.001 0 0.001 0.002 0.003 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Common Mode Voltage (V) Comparator Offset Voltage (V) 85°C 25°C -40°C -0.005 -0.004 -0.003 -0.002 -0.001 0 0.001 0.002 0.003 0 0.5 1 1.5 2 2.5 3 Common Mode Voltage (V) Comparator Offset Voltage (V) 85°C 25°C -40°C270 2486AA–AVR–02/2013 ATmega8(L) Internal Oscillator Speed Figure 169. Watchdog Oscillator Frequency vs. VCC Figure 170. Calibrated 8MHz RC Oscillator Frequency vs. Temperature 1100 1120 1140 1160 1180 1200 1220 1240 1260 2.5 3 3.5 4 4.5 5 5.5 VCC (V) FRC (kHz) 85°C 25°C -40°C 6.5 6.7 6.9 7.1 7.3 7.5 7.7 7.9 8.1 8.3 8.5 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) FRC (MHz) 5.5V 2.7V 4.0V271 2486AA–AVR–02/2013 ATmega8(L) Figure 171. Calibrated 8MHz RC Oscillator Frequency vs. VCC Figure 172. Calibrated 8MHz RC Oscillator Frequency vs. Osccal Value 6.5 6.7 6.9 7.1 7.3 7.5 7.7 7.9 8.1 8.3 8.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) FRC (MHz) 85°C 25°C -40°C 4 6 8 10 12 14 16 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE FRC (MHz)272 2486AA–AVR–02/2013 ATmega8(L) Figure 173. Calibrated 4MHz RC Oscillator Frequency vs. Temperature Figure 174. Calibrated 4MHz RC Oscillator Frequency vs. VCC 3.5 3.6 3.7 3.8 3.9 4 4.1 4.2 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) FRC (MHz) 5.5V 2.7V 4.0V 3.5 3.6 3.7 3.8 3.9 4 4.1 4.2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) FRC (MHz) 85°C 25°C -40°C273 2486AA–AVR–02/2013 ATmega8(L) Figure 175. Calibrated 4MHz RC Oscillator Frequency vs. Osccal Value Figure 176. Calibrated 2MHz RC Oscillator Frequency vs. Temperature 2 3 4 5 6 7 8 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE FRC (MHz) 1.8 1.85 1.9 1.95 2 2.05 2.1 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) FRC (MHz) 5.5V 2.7V 4.0V274 2486AA–AVR–02/2013 ATmega8(L) Figure 177. Calibrated 2MHz RC Oscillator Frequency vs. VCC Figure 178. Calibrated 2MHz RC Oscillator Frequency vs. Osccal Value 1.7 1.8 1.9 2 2.1 2.2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) FRC (MHz) 85°C 25°C -40°C 0.8 1.3 1.8 2.3 2.8 3.3 3.8 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE FRC (MHz)275 2486AA–AVR–02/2013 ATmega8(L) Figure 179. Calibrated 1MHz RC Oscillator Frequency vs. Temperature Figure 180. Calibrated 1MHz RC Oscillator Frequency vs. VCC 0.9 0.92 0.94 0.96 0.98 1 1.02 1.04 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) FRC (MHz) 5.5V 2.7V 4.0V 0.9 0.95 1 1.05 1.1 2.5 3 3.5 4 4.5 5 5.5 VCC (V) FRC (MHz) 85°C 25°C -40°C276 2486AA–AVR–02/2013 ATmega8(L) Figure 181. Calibrated 1MHz RC Oscillator Frequency vs. Osccal Value Current Consumption of Peripheral Units Figure 182. Brown-out Detector Current vs. VCC 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE FRC (MHz) 0 5 10 15 20 25 30 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA) 25°C 85°C -40°C277 2486AA–AVR–02/2013 ATmega8(L) Figure 183. ADC Current vs. VCC (AREF = AVCC) Figure 184. AREF External Reference Current vs. VCC 0 50 100 150 200 250 300 350 400 450 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA) 85°C 25°C -40°C 0 50 100 150 200 250 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA) 85°C 25°C -40°C278 2486AA–AVR–02/2013 ATmega8(L) Figure 185. 32kHz TOSC Current vs. VCC (Watchdog Timer Disabled) Figure 186. Watchdog Timer Current vs. VCC 0 5 10 15 20 25 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA) 25°C 0 10 20 30 40 50 60 70 80 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA) 85°C 25°C -40°C279 2486AA–AVR–02/2013 ATmega8(L) Figure 187. Analog Comparator Current vs. VCC Figure 188. Programming Current vs. VCC 0 10 20 30 40 50 60 70 80 90 100 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (µA) 25°C 85°C -40°C 0 1 2 3 4 5 6 7 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 25°C 85°C -40°C280 2486AA–AVR–02/2013 ATmega8(L) Current Consumption in Reset and Reset Pulsewidth Figure 189. Reset Supply Current vs. VCC (0.1MHz - 1.0MHz, Excluding Current Through The Reset Pull-up) Figure 190. Reset Supply Current vs. VCC (1MHz - 20MHz, Excluding Current Through The Reset Pull-up) 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) ICC (mA) 5.5V 5.0V 4.5V 3.3V 3.0V 2.7V 4.0V 0 5 10 15 20 25 0246 8 10 12 14 16 18 20 Frequency (MHz) ICC (mA) 5.5V 5.0V 4.5V 3.3V 3.0V 2.7V281 2486AA–AVR–02/2013 ATmega8(L) Figure 191. Reset Pulse Width vs. VCC 0 200 400 600 800 1000 1200 1400 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Pulsewidth (ns) 85°C 25°C -40°C282 2486AA–AVR–02/2013 ATmega8(L) ATmega8 Typical Characteristics – TA = -40°C to 105°C The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with Rail-to-Rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. Active Supply Current Figure 0-1. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 0 2 4 6 8 10 12 14 16 18 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 85°C 25°C -40°C 105°C283 2486AA–AVR–02/2013 ATmega8(L) Figure 0-2. Active Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) Figure 0-3. Active Supply Current vs. VCC (Internal RC Oscillator, 2 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 4 MHz 0 2 4 6 8 10 12 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 85°C 25°C -40°C 105°C ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 2 MHz 0 1 2 3 4 5 6 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 85°C 25°C -40°C 105°C284 2486AA–AVR–02/2013 ATmega8(L) Figure 0-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) Idle Supply Current Figure 0-5. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) ACTIVE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 0 0.5 1 1.5 2 2.5 3 3.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 85°C 25°C -40°C 105°C IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 8 MHz 0 1 2 3 4 5 6 7 8 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 85°C 25°C -40°C 105°C285 2486AA–AVR–02/2013 ATmega8(L) Figure 0-6. Idle Supply Current vs. VCC (Internal RC Oscillator, 4 MHz) Figure 0-7. Idle Supply Current vs. VCC (Internal RC Oscillator, 2 MHz) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 4 MHz 0 0.5 1 1.5 2 2.5 3 3.5 4 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 85°C 25°C -40°C 105°C IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 2 MHz 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 85°C 25°C -40°C 105°C286 2486AA–AVR–02/2013 ATmega8(L) Figure 0-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) Power-down Supply Current Figure 0-9. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) IDLE SUPPLY CURRENT vs. VCC INTERNAL RC OSCILLATOR, 1 MHz 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (mA) 85°C 25°C -40°C 105°C POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER DISABLED 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA) 105°C 25°C -40°C 85°C287 2486AA–AVR–02/2013 ATmega8(L) Figure 0-10. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) Pin Pull-up Figure 0-11. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) POWER-DOWN SUPPLY CURRENT vs. VCC WATCHDOG TIMER ENABLED 0 10 20 30 40 50 60 70 80 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA) 85°C 25°C -40°C 105°C I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5V 0 20 40 60 80 100 120 140 160 0123 VOP (V) IOP (uA) 85°C 25°C -40°C 105°C288 2486AA–AVR–02/2013 ATmega8(L) Figure 0-12. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) Figure 0-13. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7V 0 10 20 30 40 50 60 70 80 90 0 0.5 1 1.5 2 2.5 3 VOP (V) IOP (uA) 85°C 25°C -40°C 105°C RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 5V 0 20 40 60 80 100 012 VRESET (V) IRESET (uA) 85°C 25°C 105°C -40°C289 2486AA–AVR–02/2013 ATmega8(L) Figure 0-14. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) Pin Driver Strength Figure 0-15. I/O Pin Source Current vs. Output Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE Vcc = 2.7V 0 5 10 15 20 25 30 35 40 45 0 0.5 1 1.5 2 2.5 VRESET (V) IRESET (uA) 85°C 25°C -40°C 105°C I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 0 10 20 30 40 50 60 70 80 01234 VOH (V) IOH (mA) 85°C 25°C -40°C 105°C290 2486AA–AVR–02/2013 ATmega8(L) Figure 0-16. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V) Figure 0-17. I/O Pin Sink Current vs. Output Voltage (VCC = 5V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 0 5 10 15 20 25 30 0 0.5 1 1.5 2 2.5 3 VOH (V) IOH (mA) 85°C 25°C -40°C 105°C I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 0 10 20 30 40 50 60 70 80 90 0 0.5 1 1.5 2 2.5 VOL (V) IOL (mA) 85°C 25°C -40°C 105°C291 2486AA–AVR–02/2013 ATmega8(L) Figure 0-18. I/O Pin Sink Current vs. Output Voltage (VCC = 2.7V) Figure 0-19. Reset Pin as I/O – Pin Source Current vs. Output Voltage (VCC = 5V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 0 5 10 15 20 25 30 35 0 0.5 1 1.5 2 2.5 VOL (V) IOL (mA) 85°C 25°C -40°C 105°C RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 0 0.5 1 1.5 2 2.5 3 3.5 4 2 2.5 3 3.5 4 4.5 VOH (V) Current (mA) 85°C 25°C -40°C 105°C292 2486AA–AVR–02/2013 ATmega8(L) Figure 0-20. Reset Pin as I/O – Pin Source Current vs. Output Voltage (VCC = 2.7V) Figure 0-21. Reset Pin as I/O – Pin Sink Current vs. Output Voltage (VCC = 5V) RESET PIN AS I/O - SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 VOH (V) Current (mA) 85°C 25°C -40°C 105 °C RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 0 2 4 6 8 10 12 14 0 0.5 1 1.5 2 2.5 VOL (V) Current (mA) 85°C 25°C -40°C 105°C293 2486AA–AVR–02/2013 ATmega8(L) Figure 0-22. Reset Pin as I/O – Pin Sink Current vs. Output Voltage (VCC = 2.7V) Pin Thresholds and Hysteresis Figure 0-23. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) RESET PIN AS I/O - SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 0.5 1 1.5 2 2.5 VOL (V) Current (mA) 85°C 25°C -40°C 105°C I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIH, IO PIN READ AS '1' 0 0.5 1 1.5 2 2.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V) 85°C 105°C -40°C 25°C294 2486AA–AVR–02/2013 ATmega8(L) Figure 0-24. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) Figure 0-25. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC VIL, IO PIN READ AS '0' 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V) 85°C 25°C -40°C 105°C I/O PIN INPUT HYSTERESIS vs. VCC 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V) 85°C 25°C -40°C 105°C295 2486AA–AVR–02/2013 ATmega8(L) Figure 0-26. Reset Pin as I/O – Input Threshold Voltage vs. VCC (VIH,I/O Pin Read as “1”) Figure 0-27. Reset Pin as I/O – Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) RESET PIN AS I/O - INPUT THRESHOLD VOLTAGE vs. VCC VIH, RESET PIN READ AS '1' 0 0.5 1 1.5 2 2.5 3 3.5 4 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V) 85°C 25°C -40°C 105°C RESET PIN AS I/O - INPUT THRESHOLD VOLTAGE vs. VCC VIL, RESET PIN READ AS '0' 0 0.5 1 1.5 2 2.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V) 85°C 25°C -40°C 105°C296 2486AA–AVR–02/2013 ATmega8(L) Figure 0-28. Reset Pin as I/O – Pin Hysteresis vs. VCC Figure 0-29. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as “1”) RESET PIN AS I/O - PIN HYSTERESIS vs. VCC 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V) 85°C 25°C -40°C 105°C RESET INPUT THRESHOLD VOLTAGE vs. VCC VIH, RESET PIN READ AS '1' 0 0.5 1 1.5 2 2.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V) 85°C 25°C -40°C 105°C297 2486AA–AVR–02/2013 ATmega8(L) Figure 0-30. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as “0”) Figure 0-31. Reset Input Pin Hysteresis vs. VCC RESET INPUT THRESHOLD VOLTAGE vs. VCC VIL, RESET PIN READ AS '0' 0 0.5 1 1.5 2 2.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V) 85°C 25°C -40°C 105°C RESET INPUT PIN HYSTERESIS vs. VCC 0 0.2 0.4 0.6 0.8 1 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Threshold (V) 85°C 25°C -40°C 105°C298 2486AA–AVR–02/2013 ATmega8(L) Bod Thresholds and Analog Comparator Offset Figure 0-32. BOD Thresholds vs. Temperature (BOD Level is 4.0V) Figure 0-33. BOD Thresholds vs. Temperature (BOD Level is 2.7V) BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 4.0V 3.8 3.9 4 4.1 4.2 4.3 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature (˚C) Threshold (V) Rising VCC Falling VCC BOD THRESHOLDS vs. TEMPERATURE BODLEVEL IS 2.7V 2.4 2.5 2.6 2.7 2.8 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature (˚C) Threshold (V) Rising VCC Falling VCC299 2486AA–AVR–02/2013 ATmega8(L) Figure 0-34. Bandgap Voltage vs. VCC Figure 0-35. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 5V) BANDGAP VOLTAGE vs. VCC 1.29 1.295 1.3 1.305 1.31 1.315 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Bandgap Voltage (V) 85°C 25°C -40°C 105°C ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE VCC = 5V -0.006 -0.005 -0.004 -0.003 -0.002 -0.001 0 0.001 0.002 0.003 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Common Mode Voltage (V) Comparator Offset Voltage (V) 85°C 25°C -40°C 105°C300 2486AA–AVR–02/2013 ATmega8(L) Figure 0-36. Analog Comparator Offset Voltage vs. Common Mode Voltage (VCC = 2.7V) Internal Oscillator Speed Figure 0-37. Watchdog Oscillator Frequency vs. VCC ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE VCC = 2.7V -0.005 -0.004 -0.003 -0.002 -0.001 0 0.001 0.002 0.003 0 0.5 1 1.5 2 2.5 3 Common Mode Voltage (V) Comparator Offset Voltage (V) 85°C 25°C -40°C 105°C WATCHDOG OSCILLATOR FREQUENCY vs. VCC 1080 1100 1120 1140 1160 1180 1200 1220 1240 1260 2.5 3 3.5 4 4.5 5 5.5 VCC (V) FRC (kHz) 85°C 25°C -40°C 105°C301 2486AA–AVR–02/2013 ATmega8(L) Figure 0-38. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature Figure 0-39. Calibrated 8 MHz RC Oscillator Frequency vs. VCC CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 6.5 6.7 6.9 7.1 7.3 7.5 7.7 7.9 8.1 8.3 8.5 -60 -40 -20 0 20 40 60 80 100 120 Temperature (˚C) FRC (MHz) 5.5V 2.7V 4.0V CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. VCC 6.5 6.7 6.9 7.1 7.3 7.5 7.7 7.9 8.1 8.3 8.5 2.5 3 3.5 4 4.5 5 5.5 VCC (V) FRC (MHz) 85°C 25°C -40°C 105°C302 2486AA–AVR–02/2013 ATmega8(L) Figure 0-40. Calibrated 4 MHz RC Oscillator Frequency vs. Temperature Figure 0-41. Calibrated 4 MHz RC Oscillator Frequency vs. VCC CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 3.5 3.6 3.7 3.8 3.9 4 4.1 4.2 -60 -40 -20 0 20 40 60 80 100 120 Temperature (˚C) FRC (MHz) 5.5V 2.7V 4.0V CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. VCC 3.5 3.6 3.7 3.8 3.9 4 4.1 4.2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) FRC (MHz) 85°C 25°C -40°C 105°C303 2486AA–AVR–02/2013 ATmega8(L) Figure 0-42. Calibrated 2 MHz RC Oscillator Frequency vs. Temperature Figure 0-43. Calibrated 2 MHz RC Oscillator Frequency vs. VCC CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 1.75 1.8 1.85 1.9 1.95 2 2.05 2.1 -60 -40 -20 0 20 40 60 80 100 120 Temperature (˚C) FRC (MHz) 5.5V 2.7V 4.0V CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. VCC 1.7 1.8 1.9 2 2.1 2.2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) FRC (MHz) 85°C 25°C -40°C 105°C304 2486AA–AVR–02/2013 ATmega8(L) Figure 0-44. Calibrated 1 MHz RC Oscillator Frequency vs. Temperature Figure 0-45. Calibrated 1 MHz RC Oscillator Frequency vs. VCC CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 0.9 0.92 0.94 0.96 0.98 1 1.02 1.04 -60 -40 -20 0 20 40 60 80 100 120 Temperature (˚C) FRC (MHz) 5.5V 2.7V 4.0V CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. VCC 0.9 0.95 1 1.05 1.1 2.5 3 3.5 4 4.5 5 5.5 VCC (V) FRC (MHz) 85°C 25°C -40°C 105°C305 2486AA–AVR–02/2013 ATmega8(L) Current Consumption of Peripheral Units Figure 0-46. Brown-out Detector Current vs. VCC Figure 0-47. ADC Current vs. VCC (AREF = AVCC) BROWNOUT DETECTOR CURRENT vs. VCC 0 5 10 15 20 25 30 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA) 25°C 85°C -40°C 105°C ADC CURRENT vs. VCC AREF = AVCC 0 50 100 150 200 250 300 350 400 450 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA) 85°C 25°C -40°C 105°C306 2486AA–AVR–02/2013 ATmega8(L) Figure 0-48. AREF External Reference Current vs. VCC Figure 0-49. Watchdog Timer Current vs. VCC AREF EXTERNAL REFERENCE CURRENT vs. VCC 0 50 100 150 200 250 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA) 85°C 25°C -40°C 105°C WATCHDOG TIMER CURRENT vs. VCC 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA) 105°C 25°C -40°C 85°C307 2486AA–AVR–02/2013 ATmega8(L) Figure 0-50. Analog Comparator Current vs. VCC Figure 0-51. Programming Current vs. VCC ANALOG COMPARATOR CURRENT vs. VCC 0 20 40 60 80 100 120 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA) 25°C 105°C -40°C 85°C PROGRAMMING CURRENT vs. VCC 0 1 2 3 4 5 6 7 2.5 3 3.5 4 4.5 5 5.5 VCC (V) ICC (uA) 25°C 85°C -40°C 105°C308 2486AA–AVR–02/2013 ATmega8(L) Current Consumption in Reset and Reset Pulsewidth Figure 0-52. Reset Pulse Width vs. VCC RESET PULSE WIDTH vs. VCC 0 200 400 600 800 1000 1200 1400 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Pulsewidth (ns) 85°C 25°C -40°C 105°C309 2486AA–AVR–02/2013 ATmega8(L) Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x3F (0x5F) SREG I T H S V N Z C 11 0x3E (0x5E) SPH – – – – – SP10 SP9 SP8 13 0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 13 0x3C (0x5C) Reserved 0x3B (0x5B) GICR INT1 INT0 – – – – IVSEL IVCE 49, 67 0x3A (0x5A) GIFR INTF1 INTF0 – – – – – – 67 0x39 (0x59) TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 – TOIE0 72, 100, 119 0x38 (0x58) TIFR OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 – TOV0 72, 101, 119 0x37 (0x57) SPMCR SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN 206 0x36 (0x56) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 165 0x35 (0x55) MCUCR SE SM2 SM1 SM0 ISC11 ISC10 ISC01 ISC00 33, 66 0x34 (0x54) MCUCSR – – – – WDRF BORF EXTRF PORF 41 0x33 (0x53) TCCR0 – – – – – CS02 CS01 CS00 71 0x32 (0x52) TCNT0 Timer/Counter0 (8 Bits) 72 0x31 (0x51) OSCCAL Oscillator Calibration Register 31 0x30 (0x50) SFIOR – – – – ACME PUD PSR2 PSR10 58, 74, 120, 186 0x2F (0x4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 96 0x2E (0x4E) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 98 0x2D (0x4D) TCNT1H Timer/Counter1 – Counter Register High byte 99 0x2C (0x4C) TCNT1L Timer/Counter1 – Counter Register Low byte 99 0x2B (0x4B) OCR1AH Timer/Counter1 – Output Compare Register A High byte 99 0x2A (0x4A) OCR1AL Timer/Counter1 – Output Compare Register A Low byte 99 0x29 (0x49) OCR1BH Timer/Counter1 – Output Compare Register B High byte 99 0x28 (0x48) OCR1BL Timer/Counter1 – Output Compare Register B Low byte 99 0x27 (0x47) ICR1H Timer/Counter1 – Input Capture Register High byte 100 0x26 (0x46) ICR1L Timer/Counter1 – Input Capture Register Low byte 100 0x25 (0x45) TCCR2 FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 114 0x24 (0x44) TCNT2 Timer/Counter2 (8 Bits) 116 0x23 (0x43) OCR2 Timer/Counter2 Output Compare Register 116 0x22 (0x42) ASSR – – – – AS2 TCN2UB OCR2UB TCR2UB 117 0x21 (0x41) WDTCR – – – WDCE WDE WDP2 WDP1 WDP0 43 0x20(1) (0x40)(1) UBRRH URSEL – – – UBRR[11:8] 152 UCSRC URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL 150 0x1F (0x3F) EEARH – – – – – – – EEAR8 20 0x1E (0x3E) EEARL EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 20 0x1D (0x3D) EEDR EEPROM Data Register 20 0x1C (0x3C) EECR – – – – EERIE EEMWE EEWE EERE 20 0x1B (0x3B) Reserved 0x1A (0x3A) Reserved 0x19 (0x39) Reserved 0x18 (0x38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 65 0x17 (0x37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 65 0x16 (0x36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 65 0x15 (0x35) PORTC – PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 65 0x14 (0x34) DDRC – DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 65 0x13 (0x33) PINC – PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 65 0x12 (0x32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 65 0x11 (0x31) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 65 0x10 (0x30) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 65 0x0F (0x2F) SPDR SPI Data Register 127 0x0E (0x2E) SPSR SPIF WCOL – – – – – SPI2X 126 0x0D (0x2D) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 125 0x0C (0x2C) UDR USART I/O Data Register 148 0x0B (0x2B) UCSRA RXC TXC UDRE FE DOR PE U2X MPCM 148 0x0A (0x2A) UCSRB RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 149 0x09 (0x29) UBRRL USART Baud Rate Register Low byte 152 0x08 (0x28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 186 0x07 (0x27) ADMUX REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 199 0x06 (0x26) ADCSRA ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 200 0x05 (0x25) ADCH ADC Data Register High byte 201 0x04 (0x24) ADCL ADC Data Register Low byte 201 0x03 (0x23) TWDR Two-wire Serial Interface Data Register 167 0x02 (0x22) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 167310 2486AA–AVR–02/2013 ATmega8(L) Notes: 1. Refer to the USART description (“USART” on page 129) for details on how to access UBRRH and UCSRC (“Accessing UBRRH/UCSRC Registers” on page 146) 2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written 3. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only 0x01 (0x21) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 166 0x00 (0x20) TWBR Two-wire Serial Interface Bit Rate Register 165 Register Summary (Continued) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page311 2486AA–AVR–02/2013 ATmega8(L) Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd  Rd + Rr Z, C, N, V, H 1 ADC Rd, Rr Add with Carry two Registers Rd  Rd + Rr + C Z, C, N, V, H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl  Rdh:Rdl + K Z, C, N, V, S 2 SUB Rd, Rr Subtract two Registers Rd  Rd - Rr Z, C, N, V, H 1 SUBI Rd, K Subtract Constant from Register Rd  Rd - K Z, C, N, V, H 1 SBC Rd, Rr Subtract with Carry two Registers Rd  Rd - Rr - C Z, C, N, V, H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd  Rd - K - C Z, C, N ,V, H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl  Rdh:Rdl - K Z, C, N, V, S 2 AND Rd, Rr Logical AND Registers Rd Rd  Rr Z, N, V 1 ANDI Rd, K Logical AND Register and Constant Rd  Rd K Z, N, V 1 OR Rd, Rr Logical OR Registers Rd  Rd v Rr Z, N, V 1 ORI Rd, K Logical OR Register and Constant Rd Rd v K Z, N, V 1 EOR Rd, Rr Exclusive OR Registers Rd  Rd  Rr Z, N, V 1 COM Rd One’s Complement Rd  0xFF  Rd Z, C, N, V 1 NEG Rd Two’s Complement Rd  0x00  Rd Z, C, N, V, H 1 SBR Rd,K Set Bit(s) in Register Rd  Rd v K Z, N, V 1 CBR Rd,K Clear Bit(s) in Register Rd  Rd  (0xFF - K) Z, N, V 1 INC Rd Increment Rd  Rd + 1 Z, N, V 1 DEC Rd Decrement Rd  Rd  1 Z, N, V 1 TST Rd Test for Zero or Minus Rd  Rd  Rd Z, N, V 1 CLR Rd Clear Register Rd  Rd  Rd Z, N, V 1 SER Rd Set Register Rd  0xFF None 1 MUL Rd, Rr Multiply Unsigned R1:R0  Rd x Rr Z, C 2 MULS Rd, Rr Multiply Signed R1:R0  Rd x Rr Z, C 2 MULSU Rd, Rr Multiply Signed with Unsigned R1:R0  Rd x Rr Z, C 2 FMUL Rd, Rr Fractional Multiply Unsigned R1:R0  (Rd x Rr) << 1 Z, C 2 FMULS Rd, Rr Fractional Multiply Signed R1:R0  (Rd x Rr) << 1 Z, C 2 FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0  (Rd x Rr) << 1 Z, C 2 BRANCH INSTRUCTIONS RJMP k Relative Jump PC PC + k + 1 None 2 IJMP Indirect Jump to (Z) PC  Z None 2 RCALL k Relative Subroutine Call PC  PC + k + 1 None 3 ICALL Indirect Call to (Z) PC  Z None 3 RET Subroutine Return PC  STACK None 4 RETI Interrupt Return PC  STACK I 4 CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC PC + 2 or 3 None 1 / 2 / 3 CP Rd,Rr Compare Rd  Rr Z, N, V, C, H 1 CPC Rd,Rr Compare with Carry Rd  Rr  C Z, N, V, C, H 1 CPI Rd,K Compare Register with Immediate Rd  K Z, N, V, C, H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC  PC + 2 or 3 None 1 / 2 / 3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC  PC + 2 or 3 None 1 / 2 / 3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC  PC + 2 or 3 None 1 / 2 / 3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC  PC + 2 or 3 None 1 / 2 / 3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PCPC+k + 1 None 1 / 2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PCPC+k + 1 None 1 / 2 BREQ k Branch if Equal if (Z = 1) then PC  PC + k + 1 None 1 / 2 BRNE k Branch if Not Equal if (Z = 0) then PC  PC + k + 1 None 1 / 2 BRCS k Branch if Carry Set if (C = 1) then PC  PC + k + 1 None 1 / 2 BRCC k Branch if Carry Cleared if (C = 0) then PC  PC + k + 1 None 1 / 2 BRSH k Branch if Same or Higher if (C = 0) then PC  PC + k + 1 None 1 / 2 BRLO k Branch if Lower if (C = 1) then PC  PC + k + 1 None 1 / 2 BRMI k Branch if Minus if (N = 1) then PC  PC + k + 1 None 1 / 2 BRPL k Branch if Plus if (N = 0) then PC  PC + k + 1 None 1 / 2 BRGE k Branch if Greater or Equal, Signed if (N  V= 0) then PC  PC + k + 1 None 1 / 2 BRLT k Branch if Less Than Zero, Signed if (N  V= 1) then PC  PC + k + 1 None 1 / 2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC  PC + k + 1 None 1 / 2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC  PC + k + 1 None 1 / 2 BRTS k Branch if T Flag Set if (T = 1) then PC  PC + k + 1 None 1 / 2 BRTC k Branch if T Flag Cleared if (T = 0) then PC  PC + k + 1 None 1 / 2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC  PC + k + 1 None 1 / 2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC  PC + k + 1 None 1 / 2312 2486AA–AVR–02/2013 ATmega8(L) Mnemonics Operands Description Operation Flags #Clocks BRIE k Branch if Interrupt Enabled if ( I = 1) then PC  PC + k + 1 None 1 / 2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC  PC + k + 1 None 1 / 2 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers Rd  Rr None 1 MOVW Rd, Rr Copy Register Word Rd+1:Rd  Rr+1:Rr None 1 LDI Rd, K Load Immediate Rd  K None 1 LD Rd, X Load Indirect Rd  (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd  (X), X  X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X  X - 1, Rd  (X) None 2 LD Rd, Y Load Indirect Rd  (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd  (Y), Y  Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y  Y - 1, Rd  (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd  (Y + q) None 2 LD Rd, Z Load Indirect Rd  (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd  (Z), Z  Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z  Z - 1, Rd  (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd  (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd  (k) None 2 ST X, Rr Store Indirect (X) Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) Rr, X  X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X  X - 1, (X)  Rr None 2 ST Y, Rr Store Indirect (Y)  Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y)  Rr, Y  Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y  Y - 1, (Y)  Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q)  Rr None 2 ST Z, Rr Store Indirect (Z)  Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z)  Rr, Z  Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z  Z - 1, (Z)  Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q)  Rr None 2 STS k, Rr Store Direct to SRAM (k)  Rr None 2 LPM Load Program Memory R0  (Z) None 3 LPM Rd, Z Load Program Memory Rd  (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd  (Z), Z  Z+1 None 3 SPM Store Program Memory (Z)  R1:R0 None - IN Rd, P In Port Rd  P None 1 OUT P, Rr Out Port P  Rr None 1 PUSH Rr Push Register on Stack STACK  Rr None 2 POP Rd Pop Register from Stack Rd  STACK None 2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b)  1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b)  0 None 2 LSL Rd Logical Shift Left Rd(n+1)  Rd(n), Rd(0)  0 Z, C, N, V 1 LSR Rd Logical Shift Right Rd(n)  Rd(n+1), Rd(7)  0 Z, C, N, V 1 ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z, C, N, V 1 ROR Rd Rotate Right Through Carry Rd(7)C,Rd(n) Rd(n+1),CRd(0) Z, C, N, V 1 ASR Rd Arithmetic Shift Right Rd(n)  Rd(n+1), n=0..6 Z, C, N, V 1 SWAP Rd Swap Nibbles Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) None 1 BSET s Flag Set SREG(s)  1 SREG(s) 1 BCLR s Flag Clear SREG(s)  0 SREG(s) 1 BST Rr, b Bit Store from Register to T T  Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b)  T None 1 SEC Set Carry C  1 C1 CLC Clear Carry C  0 C 1 SEN Set Negative Flag N  1 N1 CLN Clear Negative Flag N  0 N 1 SEZ Set Zero Flag Z  1 Z1 CLZ Clear Zero Flag Z  0 Z 1 SEI Global Interrupt Enable I  1 I1 CLI Global Interrupt Disable I 0 I 1 SES Set Signed Test Flag S  1 S1 CLS Clear Signed Test Flag S  0 S 1 SEV Set Twos Complement Overflow. V  1 V1 CLV Clear Twos Complement Overflow V  0 V 1 SET Set T in SREG T  1 T1 Instruction Set Summary (Continued)313 2486AA–AVR–02/2013 ATmega8(L) Mnemonics Operands Description Operation Flags #Clocks CLT Clear T in SREG T  0 T 1 SEH Set Half Carry Flag in SREG H  1 H1 CLH Clear Half Carry Flag in SREG H  0 H 1 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/timer) None 1 Instruction Set Summary (Continued)314 2486AA–AVR–02/2013 ATmega8(L) Ordering Information Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green 3. Tape & Reel 4. See characterization specification at 105C Speed (MHz) Power Supply (V) Ordering Code(2) Package(1) Operation Range 8 2.7 - 5.5 ATmega8L-8AU ATmega8L-8AUR(3) ATmega8L-8PU ATmega8L-8MU ATmega8L-8MUR(3) 32A 32A 28P3 32M1-A 32M1-A Industrial (-40C to 85C) 16 4.5 - 5.5 ATmega8-16AU ATmega8-16AUR(3) ATmega8-16PU ATmega8-16MU ATmega8-16MUR(3) 32A 32A 28P3 32M1-A 32M1-A 8 2.7 - 5.5 ATmega8L-8AN ATmega8L-8ANR(3) ATmega8L-8PN ATmega8L-8MN ATmega8L-8MUR(3) 32A 32A 28P3 32M1-A 32M1-A Industrial (-40C to 105C) 16 4.5 - 5.5 ATmega8-16AN ATmega8-16ANR(3) ATmega8-16PN ATmega8-16MN ATmega8-16MUR(3) 32A 32A 28P3 32M1-A 32M1-A Package Type 32A 32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP) 28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) 32M1-A 32-pad, 5 × 5 × 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)315 2486AA–AVR–02/2013 ATmega8(L) Packaging Information 32A TITLE DRAWING NO. REV. 32A, 32-lead, 7 x 7mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (TQFP) 32A C 2010-10-20 PIN 1 IDENTIFIER 0°~7° PIN 1 L C A1 A2 A D1 D e E1 E B Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 8.75 9.00 9.25 D1 6.90 7.00 7.10 Note 2 E 8.75 9.00 9.25 E1 6.90 7.00 7.10 Note 2 B 0.30 – 0.45 C 0.09 – 0.20 L 0.45 – 0.75 e 0.80 TYP COMMON DIMENSIONS (Unit of measure = mm) SYMBOL MIN NOM MAX NOTE316 2486AA–AVR–02/2013 ATmega8(L) 28P3 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 28P3, 28-lead (0.300"/7.62mm Wide) Plastic Dual Inline Package (PDIP) 28P3 B 09/28/01 PIN 1 E1 A1 B REF E B1 C L SEATING PLANE A 0º ~ 15º D e eB B2 (4 PLACES) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 4.5724 A1 0.508 – – D 34.544 – 34.798 Note 1 E 7.620 – 8.255 E1 7.112 – 7.493 Note 1 B 0.381 – 0.533 B1 1.143 – 1.397 B2 0.762 – 1.143 L 3.175 – 3.429 C 0.203 – 0.356 eB – – 10.160 e 2.540 TYP Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25mm (0.010"). 317 2486AA–AVR–02/2013 ATmega8(L) 32M1-A 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 32M1-A, 32-pad, 5 x 5 x 1.0mm Body, Lead Pitch 0.50mm, 32M1-A E 5/25/06 3.10mm Exposed Pad, Micro Lead Frame Package (MLF) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D1 D E1 E b e A3 A2 A1 A D2 E2 0.08 C L 1 2 3 P P 0 1 2 3 A 0.80 0.90 1.00 A1 – 0.02 0.05 A2 – 0.65 1.00 A3 0.20 REF b 0.18 0.23 0.30 D D1 D2 2.95 3.10 3.25 4.90 5.00 5.10 4.70 4.75 4.80 4.70 4.75 4.80 4.90 5.00 5.10 E E1 E2 2.95 3.10 3.25 e 0.50 BSC L 0.30 0.40 0.50 P – – 0.60 – – 12o Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. TOP VIEW SIDE VIEW BOTTOM VIEW 0 Pin 1 ID Pin #1 Notch (0.20 R) K 0.20 – – K K318 2486AA–AVR–02/2013 ATmega8(L) Errata The revision letter in this section refers to the revision of the ATmega8 device. ATmega8 Rev. D to I, M • First Analog Comparator conversion may be delayed • Interrupts may be lost when writing the timer registers in the asynchronous timer • Signature may be Erased in Serial Programming Mode • CKOPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32KHz Oscillator is Used to Clock the Asynchronous Timer/Counter2 • Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request 1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take longer than expected on some devices. Problem Fix / Workaround When the device has been powered or reset, disable then enable theAnalog Comparator before the first conversion. 2. Interrupts may be lost when writing the timer registers in the asynchronous timer The interrupt will be lost if a timer register that is synchronized to the asynchronous timer clock is written when the asynchronous Timer/Counter register(TCNTx) is 0x00. Problem Fix / Workaround Always check that the asynchronous Timer/Counter register neither have the value 0xFF nor 0x00 before writing to the asynchronous Timer Control Register(TCCRx), asynchronous Timer Counter Register(TCNTx), or asynchronous Output Compare Register(OCRx). 3. Signature may be Erased in Serial Programming Mode If the signature bytes are read before a chiperase command is completed, the signature may be erased causing the device ID and calibration bytes to disappear. This is critical, especially, if the part is running on internal RC oscillator. Problem Fix / Workaround: Ensure that the chiperase command has exceeded before applying the next command. 4. CKOPT Does not Enable Internal Capacitors on XTALn/TOSCn Pins when 32KHz Oscillator is Used to Clock the Asynchronous Timer/Counter2 When the internal RC Oscillator is used as the main clock source, it is possible to run the Timer/Counter2 asynchronously by connecting a 32KHz Oscillator between XTAL1/TOSC1 and XTAL2/TOSC2. But when the internal RC Oscillator is selected as the main clock source, the CKOPT Fuse does not control the internal capacitors on XTAL1/TOSC1 and XTAL2/TOSC2. As long as there are no capacitors connected to XTAL1/TOSC1 and XTAL2/TOSC2, safe operation of the Oscillator is not guaranteed. Problem Fix / Workaround Use external capacitors in the range of 20pF - 36pF on XTAL1/TOSC1 and XTAL2/TOSC2. This will be fixed in ATmega8 Rev. G where the CKOPT Fuse will control internal capacitors also when internal RC Oscillator is selected as main clock source. For ATmega8 Rev. G, CKOPT = 0 (programmed) will enable the internal capacitors on XTAL1 and XTAL2. Customers who want compatibility between Rev. G and older revisions, must ensure that CKOPT is unprogrammed (CKOPT = 1).319 2486AA–AVR–02/2013 ATmega8(L) 5. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request. Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an unexpected EEPROM interrupt request. Problem Fix / Workaround Always use OUT or SBI to set EERE in EECR.320 2486AA–AVR–02/2013 ATmega8(L) Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. Changes from Rev. 2486Z- 02/11 to Rev. 2486AA- 02/2013 1. Updated the datasheet according to the Atmel new Brand Style Guide. 2.Removed the reference to “On-chip debugging” from the content. 3.Added “Electrical Characteristics – TA = -40°C to 105°C” on page 242. 4.Added “ATmega8 Typical Characteristics – TA = -40°C to 105°C” on page 282. 5.Updated “Ordering Information” on page 314. Changes from Rev. 2486Y- 10/10 to Rev. 2486Z- 02/11 1. Updated the datasheet according to the Atmel new Brand Style Guide. 2. Updated “Ordering Information” on page 314. Added Ordering Information for “Tape & Reel” devices Changes from Rev. 2486X- 06/10 to Rev. 2486Y- 10/10 1. Max Rise/Fall time in Table 102 on page 239 has been corrected from 1.6ns to 1600ns. 2. Note is added to “Performing Page Erase by SPM” on page 209. 3. Updated/corrected several short-cuts and added some new ones. 4. Updated last page according to new standard. Changes from Rev. 2486W- 02/10 to Rev. 2486X- 06/10 1. Updated “DC Characteristics” on page 235 with new VOL maximum value (0.9V and 0.6V). Changes from Rev. 2486V- 05/09 to Rev. 2486W- 02/10 1. Updated “ADC Characteristics” on page 241 with VINT maximum value (2.9V). Changes from Rev. 2486U- 08/08 to Rev. 2486V- 05/09 1. Updated “Errata” on page 318. 2. Updated the last page with Atmel’s new adresses. Changes from Rev. 2486T- 05/08 to Rev. 2486U- 08/08 1. Updated “DC Characteristics” on page 235 with I CC typical values.321 2486AA–AVR–02/2013 ATmega8(L) Changes from Rev. 2486S- 08/07 to Rev. 2486T- 05/08 1. Updated Table 98 on page 233. 2. Updated “Ordering Information” on page 314. - Commercial Ordering Code removed. - No Pb-free packaging option removed. Changes from Rev. 2486R- 07/07 to Rev. 2486S- 08/07 1. Updated “Features” on page 1. 2. Added “Data Retention” on page 7. 3. Updated “Errata” on page 318. 4. Updated “Slave Mode” on page 125. Changes from Rev. 2486Q- 10/06 to Rev. 2486R- 07/07 1. Added text to Table 81 on page 211. 2. Fixed typo in “Peripheral Features” on page 1. 3. Updated Table 16 on page 42. 4. Updated Table 75 on page 199. 5. Removed redundancy and updated typo in Notes section of “DC Characteristics” on page 235. Changes from Rev. 2486P- 02/06 to Rev. 2486Q- 10/06 1. Updated “Timer/Counter Oscillator” on page 32. 2. Updated “Fast PWM Mode” on page 88. 3. Updated code example in “USART Initialization” on page 134. 4. Updated Table 37 on page 96, Table 39 on page 97, Table 42 on page 115, Table 44 on page 115, and Table 98 on page 233. 5. Updated “Errata” on page 318. Changes from Rev. 2486O-10/04 to Rev. 2486P- 02/06 1. Added “Resources” on page 7. 2. Updated “External Clock” on page 32. 3. Updated “Serial Peripheral Interface – SPI” on page 121. 4. Updated Code Example in “USART Initialization” on page 134. 5. Updated Note in “Bit Rate Generator Unit” on page 164. 6. Updated Table 98 on page 233. 7. Updated Note in Table 103 on page 241.322 2486AA–AVR–02/2013 ATmega8(L) 8. Updated “Errata” on page 318. Changes from Rev. 2486N-09/04 to Rev. 2486O-10/04 1. Removed to instances of “analog ground”. Replaced by “ground”. 2. Updated Table 7 on page 29, Table 15 on page 38, and Table 100 on page 237. 3. Updated “Calibrated Internal RC Oscillator” on page 30 with the 1MHz default value. 4. Table 89 on page 218 and Table 90 on page 218 moved to new section “Page Size” on page 218. 5. Updated descripton for bit 4 in “Store Program Memory Control Register – SPMCR” on page 206. 6. Updated “Ordering Information” on page 314. Changes from Rev. 2486M-12/03 to Rev. 2486N-09/04 1. Added note to MLF package in “Pin Configurations” on page 2. 2. Updated “Internal Voltage Reference Characteristics” on page 42. 3. Updated “DC Characteristics” on page 235. 4. ADC4 and ADC5 support 10-bit accuracy. Document updated to reflect this. Updated features in “Analog-to-Digital Converter” on page 189. Updated “ADC Characteristics” on page 241. 5. Removed reference to “External RC Oscillator application note” from “External RC Oscillator” on page 28. Changes from Rev. 2486L-10/03 to Rev. 2486M-12/03 1. Updated “Calibrated Internal RC Oscillator” on page 30. Changes from Rev. 2486K-08/03 to Rev. 2486L-10/03 1. Removed “Preliminary” and TBDs from the datasheet. 2. Renamed ICP to ICP1 in the datasheet. 3. Removed instructions CALL and JMP from the datasheet. 4. Updated tRST in Table 15 on page 38, VBG in Table 16 on page 42, Table 100 on page 237 and Table 102 on page 239. 5. Replaced text “XTAL1 and XTAL2 should be left unconnected (NC)” after Table 9 in “Calibrated Internal RC Oscillator” on page 30. Added text regarding XTAL1/XTAL2 and CKOPT Fuse in “Timer/Counter Oscillator” on page 32. 6. Updated Watchdog Timer code examples in “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 45. 7. Removed bit 4, ADHSM, from “Special Function IO Register – SFIOR” on page 58. 8. Added note 2 to Figure 103 on page 208.323 2486AA–AVR–02/2013 ATmega8(L) 9. Updated item 4 in the “Serial Programming Algorithm” on page 231. 10. Added tWD_FUSE to Table 97 on page 232 and updated Read Calibration Byte, Byte 3, in Table 98 on page 233. 11. Updated Absolute Maximum Ratings* and DC Characteristics in “Electrical Characteristics – TA = -40°C to 85°C” on page 235. Changes from Rev. 2486J-02/03 to Rev. 2486K-08/03 1. Updated VBOT values in Table 15 on page 38. 2. Updated “ADC Characteristics” on page 241. 3. Updated “ATmega8 Typical Characteristics – TA = -40°C to 85°C” on page 244. 4. Updated “Errata” on page 318. Changes from Rev. 2486I-12/02 to Rev. 2486J-02/03 1. Improved the description of “Asynchronous Timer Clock – clkASY” on page 26. 2. Removed reference to the “Multipurpose Oscillator” application note and the “32kHz Crystal Oscillator” application note, which do not exist. 3. Corrected OCn waveforms in Figure 38 on page 89. 4. Various minor Timer 1 corrections. 5. Various minor TWI corrections. 6. Added note under “Filling the Temporary Buffer (Page Loading)” on page 209 about writing to the EEPROM during an SPM Page load. 7. Removed ADHSM completely. 8. Added section “EEPROM Write during Power-down Sleep Mode” on page 23. 9. Removed XTAL1 and XTAL2 description on page 5 because they were already described as part of “Port B (PB7..PB0) XTAL1/XTAL2/TOSC1/TOSC2” on page 5. 10. Improved the table under “SPI Timing Characteristics” on page 239 and removed the table under “SPI Serial Programming Characteristics” on page 234. 11. Corrected PC6 in “Alternate Functions of Port C” on page 61. 12. Corrected PB6 and PB7 in “Alternate Functions of Port B” on page 58. 13. Corrected 230.4 Mbps to 230.4 kbps under “Examples of Baud Rate Setting” on page 153. 14. Added information about PWM symmetry for Timer 2 in “Phase Correct PWM Mode” on page 111. 15. Added thick lines around accessible registers in Figure 76 on page 163.324 2486AA–AVR–02/2013 ATmega8(L) 16. Changed “will be ignored” to “must be written to zero” for unused Z-pointer bits under “Performing a Page Write” on page 209. 17. Added note for RSTDISBL Fuse in Table 87 on page 216. 18. Updated drawings in “Packaging Information” on page 315. Changes from Rev. 2486H-09/02 to Rev. 2486I-12/02 1. Added errata for Rev D, E, and F on page 318. Changes from Rev. 2486G-09/02 to Rev. 2486H-09/02 1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles. Changes from Rev. 2486F-07/02 to Rev. 2486G-09/02 1. Updated Table 103, “ADC Characteristics,” on page 241. Changes from Rev. 2486E-06/02 to Rev. 2486F-07/02 1. Changes in “Digital Input Enable and Sleep Modes” on page 55. 2. Addition of OCS2 in “MOSI/OC2 – Port B, Bit 3” on page 59. 3. The following tables have been updated: Table 51, “CPOL and CPHA Functionality,” on page 127, Table 59, “UCPOL Bit Settings,” on page 152, Table 72, “Analog Comparator Multiplexed Input(1),” on page 188, Table 73, “ADC Conversion Time,” on page 193, Table 75, “Input Channel Selections,” on page 199, and Table 84, “Explanation of Different Variables used in Figure 103 on page 208 and the Mapping to the Z-pointer,” on page 214. 4. Changes in “Reading the Calibration Byte” on page 227. 5. Corrected Errors in Cross References. Changes from Rev. 2486D-03/02 to Rev. 2486E-06/02 1. Updated Some Preliminary Test Limits and Characterization Data The following tables have been updated: Table 15, “Reset Characteristics,” on page 38, Table 16, “Internal Voltage Reference Characteristics,” on page 42, DC Characteristics on page 235, Table , “ADC Characteristics,” on page 241. 2. Changes in External Clock Frequency Added the description at the end of “External Clock” on page 32. Added period changing data in Table 99, “External Clock Drive,” on page 237. 3. Updated TWI Chapter More details regarding use of the TWI bit rate prescaler and a Table 65, “TWI Bit Rate Prescaler,” on page 167.325 2486AA–AVR–02/2013 ATmega8(L) Changes from Rev. 2486C-03/02 to Rev. 2486D-03/02 1. Updated Typical Start-up Times. The following tables has been updated: Table 5, “Start-up Times for the Crystal Oscillator Clock Selection,” on page 28, Table 6, “Start-up Times for the Low-frequency Crystal Oscillator Clock Selection,” on page 28, Table 8, “Start-up Times for the External RC Oscillator Clock Selection,” on page 29, and Table 12, “Start-up Times for the External Clock Selection,” on page 32. 2. Added “ATmega8 Typical Characteristics – TA = -40°C to 85°C” on page 244. Changes from Rev. 2486B-12/01 to Rev. 2486C-03/02 1. Updated TWI Chapter. More details regarding use of the TWI Power-down operation and using the TWI as Master with low TWBRR values are added into the datasheet. Added the note at the end of the “Bit Rate Generator Unit” on page 164. Added the description at the end of “Address Match Unit” on page 164. 2. Updated Description of OSCCAL Calibration Byte. In the datasheet, it was not explained how to take advantage of the calibration bytes for 2, 4, and 8MHz Oscillator selections. This is now added in the following sections: Improved description of “Oscillator Calibration Register – OSCCAL” on page 31 and “Calibration Byte” on page 218. 3. Added Some Preliminary Test Limits and Characterization Data. Removed some of the TBD’s in the following tables and pages: Table 3 on page 26, Table 15 on page 38, Table 16 on page 42, Table 17 on page 44, “TA = -40°C to +85°C, VCC = 2.7V to 5.5V (unless otherwise noted)” on page 235, Table 99 on page 237, and Table 102 on page 239. 4. Updated Programming Figures. Figure 104 on page 219 and Figure 112 on page 230 are updated to also reflect that AVCC must be connected during Programming mode. 5. Added a Description on how to Enter Parallel Programming Mode if RESET Pin is Disabled or if External Oscillators are Selected. Added a note in section “Enter Programming Mode” on page 221.1 2486AA–AVR–02/2013 ATmega8(L) Table of Contents Features 1 Pin Configurations 2 Overview 3 Block Diagram 3 Disclaimer 4 Pin Descriptions 5 Resources 7 Data Retention 7 About Code Examples 8 Atmel AVR CPU Core 9 Introduction 9 Architectural Overview 9 Arithmetic Logic Unit – ALU 11 Status Register 11 General Purpose Register File 12 Stack Pointer 13 Instruction Execution Timing 13 Reset and Interrupt Handling 14 AVR ATmega8 Memories 17 In-System Reprogrammable Flash Program Memory 17 SRAM Data Memory 18 Data Memory Access Times 19 EEPROM Data Memory 19 I/O Memory 24 System Clock and Clock Options 25 Clock Systems and their Distribution 25 Clock Sources 26 Crystal Oscillator 27 Low-frequency Crystal Oscillator 28 External RC Oscillator 28 Calibrated Internal RC Oscillator 30 External Clock 32 Timer/Counter Oscillator 32 Power Management and Sleep Modes 33 Idle Mode 342 2486AA–AVR–02/2013 ATmega8(L) ADC Noise Reduction Mode 34 Power-down Mode 34 Power-save Mode 34 Standby Mode 35 Minimizing Power Consumption 35 System Control and Reset 37 Internal Voltage Reference 42 Watchdog Timer 43 Timed Sequences for Changing the Configuration of the Watchdog Timer 45 Interrupts 46 Interrupt Vectors in ATmega8 46 I/O Ports 51 Introduction 51 Ports as General Digital I/O 52 Alternate Port Functions 56 Register Description for I/O Ports 65 External Interrupts 66 8-bit Timer/Counter0 69 Overview 69 Timer/Counter Clock Sources 70 Counter Unit 70 Operation 70 Timer/Counter Timing Diagrams 70 8-bit Timer/Counter Register Description 71 Timer/Counter0 and Timer/Counter1 Prescalers 73 16-bit Timer/Counter1 75 Overview 75 Accessing 16-bit Registers 77 Timer/Counter Clock Sources 80 Counter Unit 80 Input Capture Unit 81 Output Compare Units 83 Compare Match Output Unit 85 Modes of Operation 87 Timer/Counter Timing Diagrams 94 16-bit Timer/Counter Register Description 96 8-bit Timer/Counter2 with PWM and Asynchronous Operation 102 Overview 1023 2486AA–AVR–02/2013 ATmega8(L) Timer/Counter Clock Sources 103 Counter Unit 104 Output Compare Unit 105 Compare Match Output Unit 107 Modes of Operation 108 Timer/Counter Timing Diagrams 112 8-bit Timer/Counter Register Description 114 Asynchronous Operation of the Timer/Counter 117 Timer/Counter Prescaler 120 Serial Peripheral Interface – SPI 121 SS Pin Functionality 125 Data Modes 127 USART 129 Overview 129 Clock Generation 130 Frame Formats 133 USART Initialization 134 Data Transmission – The USART Transmitter 136 Data Reception – The USART Receiver 138 Asynchronous Data Reception 142 Multi-processor Communication Mode 145 Accessing UBRRH/UCSRC Registers 146 USART Register Description 148 Examples of Baud Rate Setting 153 Two-wire Serial Interface 157 Features 157 Two-wire Serial Interface Bus Definition 157 Data Transfer and Frame Format 158 Multi-master Bus Systems, Arbitration and Synchronization 161 Overview of the TWI Module 163 TWI Register Description 165 Using the TWI 168 Transmission Modes 171 Multi-master Systems and Arbitration 184 Analog Comparator 186 Analog Comparator Multiplexed Input 188 Analog-to-Digital Converter 189 Features 189 Starting a Conversion 191 Prescaling and Conversion Timing 191 Changing Channel or Reference Selection 1944 2486AA–AVR–02/2013 ATmega8(L) ADC Noise Canceler 195 ADC Conversion Result 199 Boot Loader Support – Read-While-Write Self-Programming 202 Boot Loader Features 202 Application and Boot Loader Flash Sections 202 Read-While-Write and No Read-While-Write Flash Sections 202 Boot Loader Lock Bits 204 Entering the Boot Loader Program 205 Addressing the Flash During Self-Programming 207 Self-Programming the Flash 208 Memory Programming 215 Program And Data Memory Lock Bits 215 Fuse Bits 216 Signature Bytes 218 Calibration Byte 218 Page Size 218 Parallel Programming Parameters, Pin Mapping, and Commands 219 Parallel Programming 221 Serial Downloading 230 Serial Programming Pin Mapping 230 Electrical Characteristics – TA = -40°C to 85°C 235 Absolute Maximum Ratings* 235 DC Characteristics 235 External Clock Drive Waveforms 237 External Clock Drive 237 Two-wire Serial Interface Characteristics 238 SPI Timing Characteristics 239 ADC Characteristics 241 Electrical Characteristics – TA = -40°C to 105°C 242 Absolute Maximum Ratings* 242 DC Characteristics TA = -40C to 105C, VCC = 2.7V to 5.5V (unless otherwise noted) 242 ATmega8 Typical Characteristics – TA = -40°C to 85°C 244 ATmega8 Typical Characteristics – TA = -40°C to 105°C 282 Active Supply Current 282 Idle Supply Current 284 Power-down Supply Current 286 Pin Pull-up 287 Pin Driver Strength 289 Pin Thresholds and Hysteresis 2935 2486AA–AVR–02/2013 ATmega8(L) Bod Thresholds and Analog Comparator Offset 298 Internal Oscillator Speed 300 Current Consumption of Peripheral Units 305 Current Consumption in Reset and Reset Pulsewidth 308 Register Summary 309 Instruction Set Summary 311 Ordering Information 314 Packaging Information 315 32A 315 28P3 316 32M1-A 317 Errata 318 ATmega8 Rev. D to I, M 318 Datasheet Revision History 320 Changes from Rev. 2486Z- 02/11 to Rev. 2486AA- 02/2013 320 Changes from Rev. 2486Y- 10/10 to Rev. 2486Z- 02/11 320 Changes from Rev. 2486X- 06/10 to Rev. 2486Y- 10/10 320 Changes from Rev. 2486W- 02/10 to Rev. 2486X- 06/10 320 Changes from Rev. 2486V- 05/09 to Rev. 2486W- 02/10 320 Changes from Rev. 2486U- 08/08 to Rev. 2486V- 05/09 320 Changes from Rev. 2486T- 05/08 to Rev. 2486U- 08/08 320 Changes from Rev. 2486S- 08/07 to Rev. 2486T- 05/08 321 Changes from Rev. 2486R- 07/07 to Rev. 2486S- 08/07 321 Changes from Rev. 2486Q- 10/06 to Rev. 2486R- 07/07 321 Changes from Rev. 2486P- 02/06 to Rev. 2486Q- 10/06 321 Changes from Rev. 2486O-10/04 to Rev. 2486P- 02/06 321 Changes from Rev. 2486N-09/04 to Rev. 2486O-10/04 322 Changes from Rev. 2486M-12/03 to Rev. 2486N-09/04 322 Changes from Rev. 2486L-10/03 to Rev. 2486M-12/03 322 Changes from Rev. 2486K-08/03 to Rev. 2486L-10/03 322 Changes from Rev. 2486J-02/03 to Rev. 2486K-08/03 323 Changes from Rev. 2486I-12/02 to Rev. 2486J-02/03 323 Changes from Rev. 2486H-09/02 to Rev. 2486I-12/02 324 Changes from Rev. 2486G-09/02 to Rev. 2486H-09/02 324 Changes from Rev. 2486F-07/02 to Rev. 2486G-09/02 324 Changes from Rev. 2486E-06/02 to Rev. 2486F-07/02 324 Changes from Rev. 2486D-03/02 to Rev. 2486E-06/02 324 Changes from Rev. 2486C-03/02 to Rev. 2486D-03/02 325 Changes from Rev. 2486B-12/01 to Rev. 2486C-03/02 3252486AA–AVR–02/2013 Atmel Corporation 1600 Technology Drive San Jose, CA 95110 USA Tel: (+1) (408) 441-0311 Fax: (+1) (408) 487-2600 www.atmel.com Atmel Asia Limited Unit 01-5 & 16, 19F BEA Tower, Millennium City 5 418 Kwun Tong Roa Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg 1-6-4 Osaki, Shinagawa-ku Tokyo 141-0032 JAPAN Tel: (+81) (3) 6417-0300 Fax: (+81) (3) 6417-0370 © 2013 Atmel Corporation. All rights reserved. / Rev.: 2486AA–AVR–02/2013 Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. 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Table of Contents 1 8127F–AVR–02/2013 Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture – 54 Powerful Instructions – Most Single Clock Cycle Execution – 16 x 8 General Purpose Working Registers – Fully Static Operation – Up to 12 MIPS Throughput at 12 MHz • Non-volatile Program and Data Memories – 512/1024 Bytes of In-System Programmable Flash Program Memory – 32 Bytes Internal SRAM – Flash Write/Erase Cycles: 10,000 – Data Retention: 20 Years at 85oC / 100 Years at 25oC • Peripheral Features – QTouch® Library Support for Capacitive Touch Sensing (1 Channel) – One 16-bit Timer/Counter with Prescaler and Two PWM Channels – Programmable Watchdog Timer with Separate On-chip Oscillator – 4-channel, 8-bit Analog to Digital Converter (ATtiny5/10, only) – On-chip Analog Comparator • Special Microcontroller Features – In-System Programmable (at 5V, only) – External and Internal Interrupt Sources – Low Power Idle, ADC Noise Reduction, and Power-down Modes – Enhanced Power-on Reset Circuit – Programmable Supply Voltage Level Monitor with Interrupt and Reset – Internal Calibrated Oscillator • I/O and Packages – Four Programmable I/O Lines – 6-pin SOT and 8-pad UDFN • Operating Voltage: – 1.8 – 5.5V • Programming Voltage: – 5V • Speed Grade – 0 – 4 MHz @ 1.8 – 5.5V – 0 – 8 MHz @ 2.7 – 5.5V – 0 – 12 MHz @ 4.5 – 5.5V • Industrial and Extended Temperature Ranges • Low Power Consumption – Active Mode: • 200µA at 1MHz and 1.8V – Idle Mode: • 25µA at 1MHz and 1.8V – Power-down Mode: • < 0.1µA at 1.8V Atmel 8-bit AVR Microcontroller with 512/1024 Bytes In-System Programmable Flash ATtiny4 / ATtiny5 / ATtiny9 / ATtiny10 Rev. 8127F–AVR–02/2013ATtiny4/5/9/10 [DATASHEET] 2 8127F–AVR–02/2013 1. Pin Configurations Figure 1-1. Pinout of ATtiny4/5/9/10 1.1 Pin Description 1.1.1 VCC Supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB3..PB0) This is a 4-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit. The output buffers have symmetrical drive characteristics, with both high sink and source capability. As inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port pins are tri-stated when a reset condition becomes active, even if the clock is not running. The port also serves the functions of various special features of the ATtiny4/5/9/10, as listed on page 36. 1.1.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 16-4 on page 118. Shorter pulses are not guaranteed to generate a reset. The reset pin can also be used as a (weak) I/O pin. 1 2 3 6 5 4 (PCINT0/TPIDATA/OC0A/ADC0/AIN0) PB0 GND (PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1 PB3 (RESET/PCINT3/ADC3) VCC PB2 (T0/CLKO/PCINT2/INT0/ADC2) SOT-23 1 2 3 4 8 7 6 5 (PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1 NC NC GND PB2 (T0/CLKO/PCINT2/INT0/ADC2) VCC PB3 (RESET/PCINT3/ADC3) PB0 (AIN0/ADC0/OC0A/TPIDATA/PCINT0) UDFNATtiny4/5/9/10 [DATASHEET] 3 8127F–AVR–02/2013 2. Overview ATtiny4/5/9/10 are low-power CMOS 8-bit microcontrollers based on the compact AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny4/5/9/10 achieve throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. Figure 2-1. Block Diagram The AVR core combines a rich instruction set with 16 general purpose working registers and system registers. All registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is compact and code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny4/5/9/10 provide the following features: 512/1024 byte of In-System Programmable Flash, 32 bytes of SRAM, four general purpose I/O lines, 16 general purpose working registers, a 16-bit timer/counter with two PWM STACK POINTER SRAM PROGRAM COUNTER PROGRAMMING LOGIC ISP INTERFACE INTERNAL OSCILLATOR WATCHDOG TIMER RESET FLAG REGISTER MCU STATUS REGISTER TIMER/ COUNTER0 CALIBRATED OSCILLATOR TIMING AND CONTROL INTERRUPT UNIT ANALOG COMPARATOR ADC GENERAL PURPOSE REGISTERS X Y Z ALU STATUS REGISTER PROGRAM FLASH INSTRUCTION REGISTER INSTRUCTION DECODER CONTROL LINES VCC RESET DATA REGISTER PORT B DIRECTION REG. PORT B DRIVERS PORT B GND PB3:0 8-BIT DATA BUSATtiny4/5/9/10 [DATASHEET] 4 8127F–AVR–02/2013 channels, internal and external interrupts, a programmable watchdog timer with internal oscillator, an internal calibrated oscillator, and four software selectable power saving modes. ATtiny5/10 are also equipped with a fourchannel, 8-bit Analog to Digital Converter (ADC). Idle mode stops the CPU while allowing the SRAM, timer/counter, ADC (ATtiny5/10, only), analog comparator, and interrupt system to continue functioning. ADC Noise Reduction mode minimizes switching noise during ADC conversions by stopping the CPU and all I/O modules except the ADC. In Power-down mode registers keep their contents and all chip functions are disabled until the next interrupt or hardware reset. In Standby mode, the oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined with low power consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The on-chip, in-system programmable Flash allows program memory to be re-programmed in-system by a conventional, non-volatile memory programmer. The ATtiny4/5/9/10 AVR are supported by a suite of program and system development tools, including macro assemblers and evaluation kits. 2.1 Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10 A comparison of the devices is shown in Table 2-1. Table 2-1. Differences between ATtiny4, ATtiny5, ATtiny9 and ATtiny10 Device Flash ADC Signature ATtiny4 512 bytes No 0x1E 0x8F 0x0A ATtiny5 512 bytes Yes 0x1E 0x8F 0x09 ATtiny9 1024 bytes No 0x1E 0x90 0x08 ATtiny10 1024 bytes Yes 0x1E 0x90 0x03ATtiny4/5/9/10 [DATASHEET] 5 8127F–AVR–02/2013 3. General Information 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/microcontroller/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. 3.3 Capacitive Touch Sensing Atmel QTouch Library provides a simple to use solution for touch sensitive interfaces on Atmel AVR microcontrollers. The QTouch Library includes support for QTouch® and QMatrix® acquisition methods. Touch sensing is easily added to any application by linking the QTouch Library and using the Application Programming Interface (API) of the library to define the touch channels and sensors. The application then calls the API to retrieve channel information and determine the state of the touch sensor. The QTouch Library is free and can be downloaded from the Atmel website. For more information and details of implementation, refer to the QTouch Library User Guide – also available from the Atmel website. 3.4 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.ATtiny4/5/9/10 [DATASHEET] 6 8127F–AVR–02/2013 4. CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 4.1 Architectural Overview Figure 4-1. Block Diagram of the AVR Architecture In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System reprogrammable Flash memory. The fast-access Register File contains 16 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Flash Program Memory Instruction Register Instruction Decoder Program Counter Control Lines 16 x 8 General Purpose Registrers ALU Status and Control I/O Lines Data Bus 8-bit Data SRAM Direct Addressing Indirect Addressing Interrupt Unit Watchdog Timer Analog Comparator Timer/Counter 0 ADCATtiny4/5/9/10 [DATASHEET] 7 8127F–AVR–02/2013 Six of the 16 registers can be used as three 16-bit indirect address register pointers for data space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, capable of directly addressing the whole address space. Most AVR instructions have a single 16-bit word format but 32-bit wide instructions also exist. The actual instruction set varies, as some devices only implement a part of the instruction set. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the four different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O memory can be accessed as the data space locations, 0x0000 - 0x003F. 4.2 ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 16 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bitfunctions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See document “AVR Instruction Set” and section “Instruction Set Summary” on page 150 for a detailed description. 4.3 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in document “AVR Instruction Set” and section “Instruction Set Summary” on page 150. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 4.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • One 16-bit output operand and one 16-bit result inputATtiny4/5/9/10 [DATASHEET] 8 8127F–AVR–02/2013 Figure 4-2 below shows the structure of the 16 general purpose working registers in the CPU. Figure 4-2. AVR CPU General Purpose Working Registers Note: A typical implementation of the AVR register file includes 32 general prupose registers but ATtiny4/5/9/10 implement only 16 registers. For reasons of compatibility the registers are numbered R16...R31, not R0...R15. Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. 4.4.1 The X-register, Y-register, and Z-register Registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3. Figure 4-3. The X-, Y-, and Z-registers 7 0 R16 R17 General R18 Purpose … Working R26 X-register Low Byte Registers R27 X-register High Byte R28 Y-register Low Byte R29 Y-register High Byte R30 Z-register Low Byte R31 Z-register High Byte 15 XH XL 0 X-register 7 07 0 R27 R26 15 YH YL 0 Y-register 7 07 0 R29 R28 15 ZH ZL 0 Z-register 7 07 0 R31 R30ATtiny4/5/9/10 [DATASHEET] 9 8127F–AVR–02/2013 In different addressing modes these address registers function as automatic increment and automatic decrement (see document “AVR Instruction Set” and section “Instruction Set Summary” on page 150 for details). 4.5 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x40. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. 4.6 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 4-4. The Parallel Instruction Fetches and Instruction Executions Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. clk 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch T1 T2 T3 T4 CPUATtiny4/5/9/10 [DATASHEET] 10 8127F–AVR–02/2013 Figure 4-5. Single Cycle ALU Operation 4.7 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 35. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back T1 T2 T3 T4 clkCPUATtiny4/5/9/10 [DATASHEET] 11 8127F–AVR–02/2013 When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in the following example. Note: See “Code Examples” on page 5. 4.7.1 Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 4.8 Register Description 4.8.1 CCP – Configuration Change Protection Register • Bits 7:0 – CCP[7:0] – Configuration Change Protection In order to change the contents of a protected I/O register the CCP register must first be written with the correct signature. After CCP is written the protected I/O registers may be written to during the next four CPU instruction cycles. All interrupts are ignored during these cycles. After these cycles interrupts are automatically handled again by the CPU, and any pending interrupts will be executed according to their priority. When the protected I/O register signature is written, CCP[0] will read as one as long as the protected feature is enabled, while CCP[7:1] will always read as zero. Table 4-1 shows the signatures that are in recognised. Assembly Code Example sei ; set Global Interrupt Enable sleep ; enter sleep, waiting for interrupt ; note: will enter sleep before any pending interrupt(s) Bit 7 6 5 4 3 2 1 0 0x3C CCP[7:0] CCP Read/Write W W W W W W W R/W Initial Value 0 0 0 0 0 0 0 0 Table 4-1. Signatures Recognised by the Configuration Change Protection Register Signature Group Description 0xD8 IOREG: CLKMSR, CLKPSR, WDTCSR Protected I/O registerATtiny4/5/9/10 [DATASHEET] 12 8127F–AVR–02/2013 4.8.2 SPH and SPL — Stack Pointer Register 4.8.3 SREG – Status Register • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the document “AVR Instruction Set” and “Instruction Set Summary” on page 150. • Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See document “AVR Instruction Set” and section “Instruction Set Summary” on page 150 for detailed information. • Bit 4 – S: Sign Bit, S = N V The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See document “AVR Instruction Set” and section “Instruction Set Summary” on page 150 for detailed information. • Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See document “AVR Instruction Set” and section “Instruction Set Summary” on page 150 for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See document “AVR Instruction Set” and section “Instruction Set Summary” on page 150 for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See document “AVR Instruction Set” and section “Instruction Set Summary” on page 150 for detailed information. Bit 15 14 13 12 11 10 9 8 0x3E SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH 0x3D SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 76543210 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND Bit 7 6 5 4 3 2 1 0 0x3F I T H S V N Z C SREG Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0ATtiny4/5/9/10 [DATASHEET] 13 8127F–AVR–02/2013 • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See document “AVR Instruction Set” and section “Instruction Set Summary” on page 150 for detailed information.ATtiny4/5/9/10 [DATASHEET] 14 8127F–AVR–02/2013 5. Memories This section describes the different memories in the ATtiny4/5/9/10. Devices have two main memory areas, the program memory space and the data memory space. 5.1 In-System Re-programmable Flash Program Memory The ATtiny4/5/9/10 contain 512/1024 bytes of on-chip, in-system reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 256/512 x 16. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny4/5/9/10 Program Counter (PC) is 9 bits wide, thus capable of addressing the 256/512 program memory locations, starting at 0x000. “Memory Programming” on page 106 contains a detailed description on Flash data serial downloading. Constant tables can be allocated within the entire address space of program memory. Since program memory can not be accessed directly, it has been mapped to the data memory. The mapped program memory begins at byte address 0x4000 in data memory (see Figure 5-1 on page 15). Although programs are executed starting from address 0x000 in program memory it must be addressed starting from 0x4000 when accessed via the data memory. Internal write operations to Flash program memory have been disabled and program memory therefore appears to firmware as read-only. Flash memory can still be written to externally but internal write operations to the program memory area will not be succesful. Timing diagrams of instruction fetch and execution are presented in “Instruction Execution Timing” on page 9. 5.2 Data Memory Data memory locations include the I/O memory, the internal SRAM memory, the non-volatile memory lock bits, and the Flash memory. See Figure 5-1 on page 15 for an illustration on how the ATtiny4/5/9/10 memory space is organized. The first 64 locations are reserved for I/O memory, while the following 32 data memory locations address the internal data SRAM. The non-volatile memory lock bits and all the Flash memory sections are mapped to the data memory space. These locations appear as read-only for device firmware. The four different addressing modes for data memory are direct, indirect, indirect with pre-decrement, and indirect with post-increment. In the register file, registers R26 to R31 function as pointer registers for indirect addressing. The IN and OUT instructions can access all 64 locations of I/O memory. Direct addressing using the LDS and STS instructions reaches the 128 locations between 0x0040 and 0x00BF. The indirect addressing reaches the entire data memory space. When using indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented.ATtiny4/5/9/10 [DATASHEET] 15 8127F–AVR–02/2013 Figure 5-1. Data Memory Map (Byte Addressing) 5.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 5-2. Figure 5-2. On-chip Data SRAM Access Cycles 0x0000 ... 0x003F 0x0040 ... 0x005F 0x0060 ... 0x3EFF 0x3F00 ... 0x3F01 0x3F02 ... 0x3F3F 0x3F40 ... 0x3F41 0x3F42 ... 0x3F7F 0x3F80 ... 0x3F81 0x3F82 ... 0x3FBF 0x3FC0 ... 0x3FC3 0x3FC4 ... 0x3FFF 0x4000 ... 0x41FF/0x43FF 0x4400 ... 0xFFFF I/O SPACE SRAM DATA MEMORY (reserved) NVM LOCK BITS (reserved) CONFIGURATION BITS (reserved) CALIBRATION BITS (reserved) DEVICE ID BITS (reserved) FLASH PROGRAM MEMORY (reserved) clk WR RD Data Data Address Address valid T1 T2 T3 Compute Address Read Write CPU Memory Access Instruction Next InstructionATtiny4/5/9/10 [DATASHEET] 16 8127F–AVR–02/2013 5.3 I/O Memory The I/O space definition of the ATtiny4/5/9/10 is shown in “Register Summary” on page 148. All ATtiny4/5/9/10 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed using the LD and ST instructions, enabling data transfer between the 16 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. See document “AVR Instruction Set” and section “Instruction Set Summary” on page 150 for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the status flags are cleared by writing a logical one to them. Note that CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work on registers in the address range 0x00 to 0x1F, only. The I/O and Peripherals Control Registers are explained in later sections.ATtiny4/5/9/10 [DATASHEET] 17 8127F–AVR–02/2013 6. Clock System Figure 6-1 presents the principal clock systems and their distribution in ATtiny4/5/9/10. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes and power reduction register bits, as described in “Power Management and Sleep Modes” on page 23. The clock systems is detailed below. Figure 6-1. Clock Distribution 6.1 Clock Subsystems The clock subsystems are detailed in the sections below. 6.1.1 CPU Clock – clkCPU The CPU clock is routed to parts of the system concerned with operation of the AVR Core. Examples of such modules are the General Purpose Register File, the System Registers and the SRAM data memory. Halting the CPU clock inhibits the core from performing general operations and calculations. 6.1.2 I/O Clock – clkI/O The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. 6.1.3 NVM clock - clkNVM The NVM clock controls operation of the Non-Volatile Memory Controller. The NVM clock is usually active simultaneously with the CPU clock. CLOCK CONTROL UNIT GENERAL I/O MODULES ANALOG-TO-DIGITAL CONVERTER CPU CORE WATCHDOG TIMER RESET LOGIC CLOCK PRESCALER RAM CLOCK SWITCH NVM CALIBRATED OSCILLATOR clk ADC SOURCE CLOCK clk I/O clk CPU clk NVM WATCHDOG CLOCK WATCHDOG OSCILLATOR EXTERNAL CLOCKATtiny4/5/9/10 [DATASHEET] 18 8127F–AVR–02/2013 6.1.4 ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. The ADC is available in ATtiny5/10, only. 6.2 Clock Sources All synchronous clock signals are derived from the main clock. The device has three alternative sources for the main clock, as follows: • Calibrated Internal 8 MHz Oscillator (see page 18) • External Clock (see page 18) • Internal 128 kHz Oscillator (see page 19) See Table 6-3 on page 21 on how to select and change the active clock source. 6.2.1 Calibrated Internal 8 MHz Oscillator The calibrated internal oscillator provides an approximately 8 MHz clock signal. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. See Table 16-2 on page 117, Figure 17-39 on page 141 and Figure 17-40 on page 141 for more details. This clock may be selected as the main clock by setting the Clock Main Select bits CLKMS[1:0] in CLKMSR to 0b00. Once enabled, the oscillator will operate with no external components. During reset, hardware loads the calibration byte into the OSCCAL register and thereby automatically calibrates the oscillator. The accuracy of this calibration is shown as Factory calibration in Table 16-2 on page 117. When this oscillator is used as the main clock, the watchdog oscillator will still be used for the watchdog timer and reset time-out. For more information on the pre-programmed calibration value, see section “Calibration Section” on page 109. 6.2.2 External Clock To use the device with an external clock source, CLKI should be driven as shown in Figure 6-2. The external clock is selected as the main clock by setting CLKMS[1:0] bits in CLKMSR to 0b10. Figure 6-2. External Clock Drive Configuration When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the MCU is kept in reset during such changes in the clock frequency. EXTERNAL CLOCK SIGNAL CLKI GNDATtiny4/5/9/10 [DATASHEET] 19 8127F–AVR–02/2013 6.2.3 Internal 128 kHz Oscillator The internal 128 kHz oscillator is a low power oscillator providing a clock of 128 kHz. The frequency depends on supply voltage, temperature and batch variations. This clock may be select as the main clock by setting the CLKMS[1:0] bits in CLKMSR to 0b01. 6.2.4 Switching Clock Source The main clock source can be switched at run-time using the “CLKMSR – Clock Main Settings Register” on page 21. When switching between any clock sources, the clock system ensures that no glitch occurs in the main clock. 6.2.5 Default Clock Source The calibrated internal 8 MHz oscillator is always selected as main clock when the device is powered up or has been reset. The synchronous system clock is the main clock divided by 8, controlled by the System Clock Prescaler. The Clock Prescaler Select Bits can be written later to change the system clock frequency. See “System Clock Prescaler”. 6.3 System Clock Prescaler The system clock is derived from the main clock via the System Clock Prescaler. The system clock can be divided by setting the “CLKPSR – Clock Prescale Register” on page 22. The system clock prescaler can be used to decrease power consumption at times when requirements for processing power is low or to bring the system clock within limits of maximum frequency. The prescaler can be used with all main clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. The System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. 6.3.1 Switching Prescaler Setting When switching between prescaler settings, the system clock prescaler ensures that no glitch occurs in the system clock and that no intermediate frequency is higher than neither the clock frequency corresponding the previous setting, nor the clock frequency corresponding to the new setting. The ripple counter that implements the prescaler runs at the frequency of the main clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were readable, and the exact time it takes to switch from one clock division to another cannot be exactly predicted. From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock frequency is active. In this interval, two active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting.ATtiny4/5/9/10 [DATASHEET] 20 8127F–AVR–02/2013 6.4 Starting 6.4.1 Starting from Reset The internal reset is immediately asserted when a reset source goes active. The internal reset is kept asserted until the reset source is released and the start-up sequence is completed. The start-up sequence includes three steps, as follows. 1. The first step after the reset source has been released consists of the device counting the reset start-up time. The purpose of this reset start-up time is to ensure that supply voltage has reached sufficient levels. The reset start-up time is counted using the internal 128 kHz oscillator. See Table 6-1 for details of reset start-up time. Note that the actual supply voltage is not monitored by the start-up logic. The device will count until the reset start-up time has elapsed even if the device has reached sufficient supply voltage levels earlier. 2. The second step is to count the oscillator start-up time, which ensures that the calibrated internal oscillator has reached a stable state before it is used by the other parts of the system. The calibrated internal oscillator needs to oscillate for a minimum number of cycles before it can be considered stable. See Table 6-1 for details of the oscillator start-up time. 3. The last step before releasing the internal reset is to load the calibration and the configuration values from the Non-Volatile Memory to configure the device properly. The configuration time is listed in Table 6-1. Notes: 1. After powering up the device or after a reset the system clock is automatically set to calibrated internal 8 MHz oscillator, divided by 8 6.4.2 Starting from Power-Down Mode When waking up from Power-Down sleep mode, the supply voltage is assumed to be at a sufficient level and only the oscillator start-up time is counted to ensure the stable operation of the oscillator. The oscillator start-up time is counted on the selected main clock, and the start-up time depends on the clock selected. See Table 6-2 for details. Notes: 1. The start-up time is measured in main clock oscillator cycles. 6.4.3 Starting from Idle / ADC Noise Reduction / Standby Mode When waking up from Idle, ADC Noise Reduction or Standby Mode, the oscillator is already running and no oscillator start-up time is introduced. The ADC is available in ATtiny5/10, only. Table 6-1. Start-up Times when Using the Internal Calibrated Oscillator Reset Oscillator Configuration Total start-up time 64 ms 6 cycles 21 cycles 64 ms + 6 oscillator cycles + 21 system clock cycles (1) Table 6-2. Start-up Time from Power-Down Sleep Mode. Oscillator start-up time Total start-up time 6 cycles 6 oscillator cycles (1)ATtiny4/5/9/10 [DATASHEET] 21 8127F–AVR–02/2013 6.5 Register Description 6.5.1 CLKMSR – Clock Main Settings Register • Bit 7:2 – Res: Reserved Bits These bits are reserved and always read zero. • Bit 1:0 – CLKMS[1:0]: Clock Main Select Bits These bits select the main clock source of the system. The bits can be written at run-time to switch the source of the main clock. The clock system ensures glitch free switching of the main clock source. The main clock alternatives are shown in Table 6-3. To avoid unintentional switching of main clock source, a protected change sequence must be followed to change the CLKMS bits, as follows: 1. Write the signature for change enable of protected I/O register to register CCP 2. Within four instruction cycles, write the CLKMS bits with the desired value 6.5.2 OSCCAL – Oscillator Calibration Register . • Bits 7:0 – CAL[7:0]: Oscillator Calibration Value The oscillator calibration register is used to trim the calibrated internal oscillator and remove process variations from the oscillator frequency. A pre-programmed calibration value is automatically written to this register during chip reset, giving the factory calibrated frequency as specified in Table 16-2, “Calibration Accuracy of Internal RC Oscillator,” on page 117. The application software can write this register to change the oscillator frequency. The oscillator can be calibrated to frequencies as specified in Table 16-2, “Calibration Accuracy of Internal RC Oscillator,” on page 117. Calibration outside the range given is not guaranteed. The CAL[7:0] bits are used to tune the frequency of the oscillator. A setting of 0x00 gives the lowest frequency, and a setting of 0xFF gives the highest frequency. Bit 7 6 5 4 3 2 1 0 0x37 – – – – – – CLKMS1 CLKMS0 CLKMSR Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 6-3. Selection of Main Clock CLKM1 CLKM0 Main Clock Source 0 0 Calibrated Internal 8 MHzOscillator 0 1 Internal 128 kHz Oscillator (WDT Oscillator) 1 0 External clock 1 1 Reserved Bit 7 6 5 4 3 2 1 0 0x39 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X XATtiny4/5/9/10 [DATASHEET] 22 8127F–AVR–02/2013 6.5.3 CLKPSR – Clock Prescale Register • Bits 7:4 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written at run-time to vary the clock frequency and suit the application requirements. As the prescaler divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced accordingly. The division factors are given in Table 6-4. To avoid unintentional changes of clock frequency, a protected change sequence must be followed to change the CLKPS bits: 1. Write the signature for change enable of protected I/O register to register CCP 2. Within four instruction cycles, write the desired value to CLKPS bits At start-up, CLKPS bits are reset to 0b0011 to select the clock division factor of 8. If the selected clock source has a frequency higher than the maximum allowed the application software must make sure a sufficient division factor is used. To make sure the write procedure is not interrupted, interrupts must be disabled when changing prescaler settings. Bit 7 6 5 4 3 2 1 0 0x36 – – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPSR Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 1 1 Table 6-4. Clock Prescaler Select CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor 0000 1 0001 2 0010 4 0 0 1 1 8 (default) 0 1 0 0 16 0 1 0 1 32 0 1 1 0 64 0 1 1 1 128 1 0 0 0 256 1 0 0 1 Reserved 1 0 1 0 Reserved 1 0 1 1 Reserved 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 ReservedATtiny4/5/9/10 [DATASHEET] 23 8127F–AVR–02/2013 7. Power Management and Sleep Modes The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications. In addition, sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 7.1 Sleep Modes Figure 6-1 on page 17 presents the different clock systems and their distribution in ATtiny4/5/9/10. The figure is helpful in selecting an appropriate sleep mode. Table 7-1 shows the different sleep modes and their wake up sources. Note: 1. The ADC is available in ATtiny5/10, only 2. For INT0, only level interrupt. To enter any of the four sleep modes, the SE bits in SMCR must be written to logic one and a SLEEP instruction must be executed. The SM2:0 bits in the SMCR register select which sleep mode (Idle, ADC Noise Reduction, Standby or Power-down) will be activated by the SLEEP instruction. See Table 7-2 for a summary. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Note that if a level triggered interrupt is used for wake-up the changed level must be held for some time to wake up the MCU (and for the MCU to enter the interrupt service routine). See “External Interrupts” on page 36 for details. 7.1.1 Idle Mode When bits SM2:0 are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing the analog comparator, timer/counter, watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkNVM, while allowing the other clocks to run. Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the timer overflow. If wake-up from the analog comparator interrupt is not required, the analog comparator can be powered down by setting the ACD bit in “ACSR – Analog Comparator Control and Status Register” on page 80. This will reduce power consumption in idle mode. If the ADC is enabled (ATtiny5/10, only), a conversion starts automatically when this mode is entered. Table 7-1. Active Clock Domains and Wake-up Sources in Different Sleep Modes Sleep Mode Active Clock Domains Oscillators Wake-up Sources clkCPU clkNVM clkIO clkADC (1) Main Clock Source Enabled INT0 and Pin Change ADC (1) Other I/O Watchdog Interrupt VLM Interrupt Idle X X X X X X X X ADC Noise Reduction X X X (2) X XX Standby X X (2) X Power-down X (2) XATtiny4/5/9/10 [DATASHEET] 24 8127F–AVR–02/2013 7.1.2 ADC Noise Reduction Mode When bits SM2:0 are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, and the watchdog to continue operating (if enabled). This sleep mode halts clkI/O, clkCPU, and clkNVM, while allowing the other clocks to run. This mode improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered. This mode is available in all devices, although only ATtiny5/10 are equipped with an ADC. 7.1.3 Power-down Mode When bits SM2:0 are written to 010, the SLEEP instruction makes the MCU enter Power-down mode. In this mode, the oscillator is stopped, while the external interrupts, and the watchdog continue operating (if enabled). Only a watchdog reset, an external level interrupt on INT0, or a pin change interrupt can wake up the MCU. This sleep mode halts all generated clocks, allowing operation of asynchronous modules only. 7.1.4 Standby Mode When bits SM2:0 are written to 100, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the oscillator is kept running. This reduces wake-up time, because the oscillator is already running and doesn't need to be started up. 7.2 Power Reduction Register The Power Reduction Register (PRR), see “PRR – Power Reduction Register” on page 26, provides a method to reduce power consumption by stopping the clock to individual peripherals. When the clock for a peripheral is stopped then: • The current state of the peripheral is frozen. • The associated registers can not be read or written. • Resources used by the peripheral will remain occupied. The peripheral should in most cases be disabled before stopping the clock. Clearing the PRR bit wakes up the peripheral and puts it in the same state as before shutdown. Peripheral shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. See “Supply Current of I/O Modules” on page 121 for examples. In all other sleep modes, the clock is already stopped. 7.3 Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR Core controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. 7.3.1 Analog Comparator When entering Idle mode, the analog comparator should be disabled if not used. In the power-down mode, the analog comparator is automatically disabled. See “Analog Comparator” on page 80 for further details.ATtiny4/5/9/10 [DATASHEET] 25 8127F–AVR–02/2013 7.3.2 Analog to Digital Converter If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. See “Analog to Digital Converter” on page 82 for details on ADC operation. The ADC is available in ATtiny5/10, only. 7.3.3 Watchdog Timer If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Watchdog Timer” on page 30 for details on how to configure the Watchdog Timer. 7.3.4 Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is then to ensure that no pins drive resistive loads. In sleep modes where the I/O clock (clkI/O) is stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 44 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or has an analog signal level close to VCC/2, the input buffer will use excessive power. For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC/2 on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the Digital Input Disable Register (DIDR0). Refer to “DIDR0 – Digital Input Disable Register 0” on page 81 for details. 7.4 Register Description 7.4.1 SMCR – Sleep Mode Control Register The SMCR Control Register contains control bits for power management. • Bits 7:4 – Res: Reserved Bits These bits are reserved and will always read zero. • Bits 3:1 – SM2..SM0: Sleep Mode Select Bits 2..0 These bits select between available sleep modes, as shown in Table 7-2. Bit 7 6 5 4 3 2 1 0 0x3A – – – – SM2 SM1 SM0 SE SMCR Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 7-2. Sleep Mode Select SM2 SM1 SM0 Sleep Mode 0 0 0 Idle 0 0 1 ADC noise reduction (1) 0 1 0 Power-down 0 1 1 Reserved 1 0 0 StandbyATtiny4/5/9/10 [DATASHEET] 26 8127F–AVR–02/2013 Note: 1. This mode is available in all devices, although only ATtiny5/10 are equipped with an ADC • Bit 0 – SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. 7.4.2 PRR – Power Reduction Register • Bits 7:2 – Res: Reserved Bits These bits are reserved and will always read zero. • Bit 1 – PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down. The ADC is available in ATtiny5/10, only. • Bit 0 – PRTIM0: Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved Table 7-2. Sleep Mode Select SM2 SM1 SM0 Sleep Mode Bit 7 6 5 4 3 2 1 0 0x35 – – – – – – PRADC PRTIM0 PRR Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0ATtiny4/5/9/10 [DATASHEET] 27 8127F–AVR–02/2013 8. System Control and Reset 8.1 Resetting the AVR During reset, all I/O registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 8-1 shows the reset logic. Electrical parameters of the reset circuitry are defined in section “System and Reset Characteristics” on page 118. Figure 8-1. Reset Logic The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not require any clock source to be running. After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts. The start up sequence is described in “Starting from Reset” on page 20. 8.2 Reset Sources The ATtiny4/5/9/10 have three sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT) • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length • Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled 8.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detection level is defined in section “System and Reset Characteristics” on page 118. The POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage. Reset Flag Register (RSTFLR) CK Delay Counters TIMEOUT WDRF EXTRF PORF DATA BUS Clock Generator SPIKE FILTER Pull-up Resistor Watchdog Oscillator Power-on Reset Circuit VLMATtiny4/5/9/10 [DATASHEET] 28 8127F–AVR–02/2013 A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in reset after VCC rise. The reset signal is activated again, without any delay, when VCC decreases below the detection level. Figure 8-2. MCU Start-up, RESET Tied to VCC Figure 8-3. MCU Start-up, RESET Extended Externally 8.2.2 VCC Level Monitoring ATtiny4/5/9/10 have a VCC Level Monitoring (VLM) circuit that compares the voltage level at the VCC pin against fixed trigger levels. The trigger levels are set with VLM2:0 bits, see “VLMCSR – VCC Level Monitoring Control and Status register” on page 33. The VLM circuit provides a status flag, VLMF, that indicates if voltage on the VCC pin is below the selected trigger level. The flag can be read from VLMCSR, but it is also possible to have an interrupt generated when the VLMF status flag is set. This interrupt is enabled by the VLMIE bit in the VLMCSR register. The flag can be cleared by changing the trigger level or by writing it to zero. The flag is automatically cleared when the voltage at VCC rises back above the selected trigger level. The VLM can also be used to improve reset characteristics at falling supply. Without VLM, the Power-On Reset (POR) does not activate before supply voltage has dropped to a level where the MCU is not necessarily functional any more. With VLM, it is possible to generate a reset earlier. When active, the VLM circuit consumes some power, as illustrated in Figure 17-48 on page 145. To save power the VLM circuit can be turned off completely, or it can be switched on and off at regular intervals. However, detection takes some time and it is therefore recommended to leave the circuitry on long enough for signals to settle. See “VCC Level Monitor” on page 118. V TIME-OUT RESET RESET TOUT INTERNAL t VPOT VRST CC V TIME-OUT TOUT TOUT INTERNAL CC t VPOT VRST > t RESET RESETATtiny4/5/9/10 [DATASHEET] 29 8127F–AVR–02/2013 When VLM is active and voltage at VCC is above the selected trigger level operation will be as normal and the VLM can be shut down for a short period of time. If voltage at VCC drops below the selected threshold the VLM will either flag an interrupt or generate a reset, depending on the configuration. When the VLM has been configured to generate a reset at low supply voltage it will keep the device in reset as long as VCC is below the reset level. See Table 8-4 on page 34 for reset level details. If supply voltage rises above the reset level the condition is removed and the MCU will come out of reset, and initiate the power-up start-up sequence. If supply voltage drops enough to trigger the POR then PORF is set after supply voltage has been restored. 8.2.3 External Reset An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer than the minimum pulse width (see section “System and Reset Characteristics” on page 118) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – VRST – on its positive edge, the delay counter starts the MCU after the time-out period – tTOUT – has expired. External reset is ignored during Power-on start-up count. After Power-on reset the internal reset is extended only if RESET pin is low when the initial Power-on delay count is complete. See Figure 8-2 and Figure 8- 3 on page 28. Figure 8-4. External Reset During Operation 8.2.4 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the time-out period tTOUT. See page 30 for details on operation of the Watchdog Timer and Table 16-4 on page 118 for details on reset time-out. CCATtiny4/5/9/10 [DATASHEET] 30 8127F–AVR–02/2013 Figure 8-5. Watchdog Reset During Operation 8.3 Watchdog Timer The Watchdog Timer is clocked from an on-chip oscillator, which runs at 128 kHz. See Figure 8-6. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 8-2 on page 32. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a device reset occurs. Ten different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATtiny4/5/9/10 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to Table 8-3 on page 33. Figure 8-6. Watchdog Timer The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can be very helpful when using the Watchdog to wake-up from Power-down. To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, two different safety levels are selected by the fuse WDTON as shown in Table 8-1 on page 31. See “Procedure for Changing the Watchdog Timer Configuration” on page 31 for details. CK CC OSC/2K OSC/4K OSC/8K OSC/16K OSC/32K OSC/64K OSC/128K OSC/256K OSC/512K OSC/1024K MCU RESET WATCHDOG PRESCALER 128 kHz OSCILLATOR WATCHDOG RESET WDP0 WDP1 WDP2 WDP3 WDE MUXATtiny4/5/9/10 [DATASHEET] 31 8127F–AVR–02/2013 8.3.1 Procedure for Changing the Watchdog Timer Configuration The sequence for changing configuration differs between the two safety levels, as follows: 8.3.1.1 Safety Level 1 In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to one without any restriction. A special sequence is needed when disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer, the following procedure must be followed: 1. Write the signature for change enable of protected I/O registers to register CCP 2. Within four instruction cycles, in the same operation, write WDE and WDP bits 8.3.1.2 Safety Level 2 In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A protected change is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following procedure must be followed: 1. Write the signature for change enable of protected I/O registers to register CCP 2. Within four instruction cycles, write the WDP bit. The value written to WDE is irrelevant 8.3.2 Code Examples The following code example shows how to turn off the WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Note: See “Code Examples” on page 5. Table 8-1. WDT Configuration as a Function of the Fuse Settings of WDTON WDTON Safety Level WDT Initial State How to Disable the WDT How to Change Time-out Unprogrammed 1 Disabled Protected change sequence No limitations Programmed 2 Enabled Always enabled Protected change sequence Assembly Code Example WDT_off: wdr ; Clear WDRF in RSTFLR in r16, RSTFLR andi r16, ~(1< Table 9-1. Reset and Interrupt Vectors Vector No. Program Address Label Interrupt Source 1 0x0000 RESET External Pin, Power-on Reset, VLM Reset, Watchdog Reset 2 0x0001 INT0 External Interrupt Request 0 3 0x0002 PCINT0 Pin Change Interrupt Request 0 4 0x0003 TIM0_CAPT Timer/Counter0 Input Capture 5 0x0004 TIM0_OVF Timer/Counter0 Overflow 6 0x0005 TIM0_COMPA Timer/Counter0 Compare Match A 7 0x0006 TIM0_COMPB Timer/Counter0 Compare Match B 8 0x0007 ANA_COMP Analog Comparator 9 0x0008 WDT Watchdog Time-out 10 0x0009 VLM VCC Voltage Level Monitor 11 0x000A ADC ADC Conversion Complete (1)ATtiny4/5/9/10 [DATASHEET] 36 8127F–AVR–02/2013 0x000B RESET: ldi r16, high(RAMEND); Main program start 0x000C out SPH,r16 ; Set Stack Pointer 0x000D ldi r16, low(RAMEND) ; to top of RAM 0x000E out SPL,r16 0x000F sei ; Enable interrupts 0x0010 ... ... 9.2 External Interrupts External Interrupts are triggered by the INT0 pin or any of the PCINT3..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT3..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. Pin change 0 interrupts PCI0 will trigger if any enabled PCINT3..0 pin toggles. The PCMSK Register controls which pins contribute to the pin change interrupts. Pin change interrupts on PCINT3..0 are detected asynchronously, which means that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The INT0 interrupt can be triggered by a falling or rising edge or a low level. This is set up as shown in “EICRA – External Interrupt Control Register A” on page 37. When the INT0 interrupt is enabled and configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT0 requires the presence of an I/O clock, as described in “Clock System” on page 17. 9.2.1 Low Level Interrupt A low level interrupt on INT0 is detected asynchronously. This means that the interrupt source can be used for waking the part also from sleep modes other than Idle (the I/O clock is halted in all sleep modes except Idle). Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined as described in “Clock System” on page 17. If the low level on the interrupt pin is removed before the device has woken up then program execution will not be diverted to the interrupt service routine but continue from the instruction following the SLEEP command. 9.2.2 Pin Change Interrupt Timing A timing example of a pin change interrupt is shown in Figure 9-1.ATtiny4/5/9/10 [DATASHEET] 37 8127F–AVR–02/2013 Figure 9-1. Timing of pin change interrupts 9.3 Register Description 9.3.1 EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control. • Bits 7:2 – Res: Reserved Bits These bits are reserved and will always read zero. • Bits 1:0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 9-2. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If clk PCINT(0) pin_lat pin_sync pcint_in_(0) pcint_syn pcint_setflag PCIF PCINT(0) pin_sync pcint_syn pin_lat D Q LE pcint_setflag PCIF clk clk PCINT(0) in PCMSK(x) pcint_in_(0) 0 x Bit 7 6 5 4 3 2 1 0 0x15 – – – – – – ISC01 ISC00 EICRA Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0ATtiny4/5/9/10 [DATASHEET] 38 8127F–AVR–02/2013 low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. 9.3.2 EIMSK – External Interrupt Mask Register • Bits 7:1 – Res: Reserved Bits These bits are reserved and will always read zero. • Bit 0 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control bits (ISC01 and ISC00) in the External Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector. 9.3.3 EIFR – External Interrupt Flag Register • Bits 7:1 – Res: Reserved Bits These bits are reserved and will always read zero. • Bit 0 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is constantly zero when INT0 is configured as a level interrupt. Table 9-2. Interrupt 0 Sense Control ISC01 ISC00 Description 0 0 The low level of INT0 generates an interrupt request. 0 1 Any logical change on INT0 generates an interrupt request. 1 0 The falling edge of INT0 generates an interrupt request. 1 1 The rising edge of INT0 generates an interrupt request. Bit 7 6 5 4 3 2 1 0 0x13 – – – – – – – INTO EIMSK Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x14 – – – – – – – INTF0 EIFR Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0ATtiny4/5/9/10 [DATASHEET] 39 8127F–AVR–02/2013 9.3.4 PCICR – Pin Change Interrupt Control Register • Bits 7:1 – Res: Reserved Bits These bits are reserved and will always read zero. • Bit 0 – PCIE0: Pin Change Interrupt Enable 0 When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT3..0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT3..0 pins are enabled individually by the PCMSK Register. 9.3.5 PCIFR – Pin Change Interrupt Flag Register • Bits 7:1 – Res: Reserved Bits These bits are reserved and will always read zero. • Bit 0 – PCIF0: Pin Change Interrupt Flag 0 When a logic change on any PCINT3..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. 9.3.6 PCMSK – Pin Change Mask Register • Bits 7:4 – Res: Reserved Bits These bits are reserved and will always read zero. • Bits 3:0 – PCINT3..0: Pin Change Enable Mask 3..0 Each PCINT3..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT3..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT3..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. Bit 7 6 5 4 3 2 1 0 0x12 – – – – – – – PCIE0 PCICR Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x11 – – – – – – – PCIF0 PCIFR Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x10 – – – – PCINT3 PCINT2 PCINT1 PCINT0 PCMSK Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0ATtiny4/5/9/10 [DATASHEET] 40 8127F–AVR–02/2013 10. I/O Ports 10.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors. Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both VCC and Ground as indicated in Figure 10-1 on page 40. See “Electrical Characteristics” on page 115 for a complete list of parameters. Figure 10-1. I/O Pin Equivalent Schematic All registers and bit references in this section are written in general form. A lower case “x” represents the numbering letter for the port, and a lower case “n” represents the bit number. However, when using the register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Registers and bit locations are listed in “Register Description” on page 50. Four I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data Direction Register – DDRx, Pull-up Enable Register – PUEx, and the Port Input Pins – PINx. The Port Input Pins I/O location is read only, while the Data Register, the Data Direction Register, and the Pull-up Enable Register are read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit in the Data Register. Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page 41. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in “Alternate Port Functions” on page 45. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. Cpin Logic Rpu See Figure "General Digital I/O" for Details PxnATtiny4/5/9/10 [DATASHEET] 41 8127F–AVR–02/2013 10.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 10-2. General Digital I/O(1) Note: 1. WEx, WRx, WPx, WDx, REx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, and SLEEP are common to all ports. 10.2.1 Configuring the Pin Each port pin consists of four register bits: DDxn, PORTxn, PUExn, and PINxn. As shown in “Register Description” on page 50, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, the PUExn bits at the PUEx I/O address, and the PINxn bits at the PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. clk RPx RRx RDx WDx WEx SYNCHRONIZER WDx: WRITE DDRx WRx: WRITE PORTx RRx: READ PORTx REGISTER RPx: READ PORTx PIN clkI/O: I/O CLOCK RDx: READ DDRx WEx: WRITE PUEx REx: READ PUEx D L Q Q REx RESET RESET Q D Q Q Q D CLR PORTxn Q Q D CLR DDxn PINxn DATA BUS SLEEP SLEEP: SLEEP CONTROL Pxn I/O WPx RESET Q Q D CLR PUExn 0 1 WRx WPx: WRITE PINx REGISTERATtiny4/5/9/10 [DATASHEET] 42 8127F–AVR–02/2013 If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). The pull-up resistor is activated, if the PUExn is written logic one. To switch the pull-up resistor off, PUExn has to be written logic zero. Table 10-1 summarizes the control signals for the pin value. Port pins are tri-stated when a reset condition becomes active, even when no clocks are running. 10.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 10.2.3 Break-Before-Make Switching In Break-Before-Make mode, switching the DDRxn bit from input to output introduces an immediate tri-state period lasting one system clock cycle, as indicated in Figure 10-3. For example, if the system clock is 4 MHz and the DDRxn is written to make an output, an immediate tri-state period of 250 ns is introduced before the value of PORTxn is seen on the port pin. To avoid glitches it is recommended that the maximum DDRxn toggle frequency is two system clock cycles. The Break-Before-Make mode applies to the entire port and it is activated by the BBMx bit. For more details, see “PORTCR – Port Control Register” on page 50. When switching the DDRxn bit from output to input no immediate tri-state period is introduced. Table 10-1. Port Pin Configurations DDxn PORTxn PUExn I/O Pull-up Comment 0 X 0 Input No Tri-state (hi-Z) 0 X 1 Input Yes Sources current if pulled low externally 1 0 0 Output No Output low (sink) 1 0 1 Output Yes NOT RECOMMENDED. Output low (sink) and internal pull-up active. Sources current through the internal pull-up resistor and consumes power constantly 1 1 0 Output No Output high (source) 1 1 1 Output Yes Output high (source) and internal pull-up activeATtiny4/5/9/10 [DATASHEET] 43 8127F–AVR–02/2013 Figure 10-3. Switching Between Input and Output in Break-Before-Make-Mode 10.2.4 Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As shown in Figure 10-2 on page 41, the PINxn Register bit and the preceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. Figure 10-4 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted tpd,max and tpd,min respectively. Figure 10-4. Synchronization when Reading an Externally Applied Pin value Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 10-5 on page 44. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is one system clock period. out DDRx, r16 nop 0x02 0x01 SYSTEM CLK INSTRUCTIONS DDRx intermediate tri-state cycle out DDRx, r17 PORTx 0x55 0x01 intermediate tri-state cycle Px0 Px1 tri-state tri-state tri-state r17 0x01 r16 0x02 XXX in r17, PINx 0x00 0xFF INSTRUCTIONS SYNC LATCH PINxn r17 XXX SYSTEM CLK tpd, max tpd, minATtiny4/5/9/10 [DATASHEET] 44 8127F–AVR–02/2013 Figure 10-5. Synchronization when Reading a Software Assigned Pin Value 10.2.5 Digital Input Enable and Sleep Modes As shown in Figure 10-2 on page 41, the digital input signal can be clamped to ground at the input of the schmitttrigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down and Standby modes to avoid high power consumption if some input signals are left floating, or have an analog signal level close to VCC/2. SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in “Alternate Port Functions” on page 45. If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change. 10.2.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pulldown. Connecting unused pins directly to VCC or GND is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output. out PORTx, r16 nop in r17, PINx 0xFF 0x00 0xFF SYSTEM CLK r16 INSTRUCTIONS SYNC LATCH PINxn r17 t pdATtiny4/5/9/10 [DATASHEET] 45 8127F–AVR–02/2013 10.2.7 Program Example The following code example shows how to set port B pin 0 high, pin 1 low, and define the port pins from 2 to 3 as input with a pull-up assigned to port pin 2. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Note: See “Code Examples” on page 5. 10.3 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. In Figure 10-6 below is shown how the port pin control signals from the simplified Figure 10-2 on page 41 can be overridden by alternate functions. Assembly Code Example ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<