ATtiny2313A/4313 Data Sheet - Atmel - Farnell Element 14 - Revenir à l'accueil

 

 

Branding Farnell element14 (France)

 

Farnell Element 14 :

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Everything You Need To Know About Arduino

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Tutorial 01 for Arduino: Getting Acquainted with Arduino

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The Cube® 3D Printer

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What's easier- DIY Dentistry or our new our website features?

 

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Ben Heck's Getting Started with the BeagleBone Black Trailer

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Ben Heck's Home-Brew Solder Reflow Oven 2.0 Trailer

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Get Started with Pi Episode 3 - Online with Raspberry Pi

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Discover Simulink Promo -- Exclusive element14 Webinar

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Ben Heck's TV Proximity Sensor Trailer

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Ben Heck's PlayStation 4 Teardown Trailer

See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…

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Get Started with Pi Episode 4 - Your First Raspberry Pi Project

Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.

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Ben Heck Anti-Pickpocket Wallet Trailer

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Molex Earphones - The 14 Holiday Products of Newark element14 Promotion

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Tripp Lite Surge Protector - The 14 Holiday Products of Newark element14 Promotion

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Microchip ChipKIT Pi - The 14 Holiday Products of Newark element14 Promotion

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Beagle Bone Black - The 14 Holiday Products of Newark element14 Promotion

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3M E26, LED Lamps - The 14 Holiday Products of Newark element14 Promotion

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3M Colored Duct Tape - The 14 Holiday Products of Newark element14 Promotion

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Tenma Soldering Station - The 14 Holiday Products of Newark element14 Promotion

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Duratool Screwdriver Kit - The 14 Holiday Products of Newark element14 Promotion

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Cubify 3D Cube - The 14 Holiday Products of Newark element14 Promotion

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Bud Boardganizer - The 14 Holiday Products of Newark element14 Promotion

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Raspberry Pi Starter Kit - The 14 Holiday Products of Newark element14 Promotion

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Fluke 323 True-rms Clamp Meter - The 14 Holiday Products of Newark element14 Promotion

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Dymo RHINO 6000 Label Printer - The 14 Holiday Products of Newark element14 Promotion

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3M LED Advanced Lights A-19 - The 14 Holiday Products of Newark element14 Promotion

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Innovative LPS Resistor Features Very High Power Dissipation

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Charge Injection Evaluation Board for DG508B Multiplexer Demo

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Ben Heck The Great Glue Gun Trailer Part 2

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Introducing element14 TV

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Ben Heck Time to Meet Your Maker Trailer

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Détecteur de composants

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Recherche intégrée

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Ben Builds an Accessibility Guitar Trailer Part 1

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Ben Builds an Accessibility Guitar - Part 2 Trailer

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PiFace Control and Display Introduction

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Flashmob Farnell

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Express Yourself in 3D with Cube 3D Printers from Newark element14

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Farnell YouTube Channel Move

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Farnell: Design with the best

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French Farnell Quest

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Altera - 3 Ways to Quickly Adapt to Changing Ethernet Protocols

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Cy-Net3 Network Module

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MC AT - Professional and Precision Series Thin Film Chip Resistors

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Solderless LED Connector

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PSA-T Series Spectrum Analyser: PSA1301T/ PSA2701T

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3-axis Universal Motion Controller For Stepper Motor Drivers: TMC429

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Voltage Level Translation

Puce électronique / Microchip :

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Microchip - 8-bit Wireless Development Kit

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 2 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 3 of 3

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Microchip - Introduction to mTouch Capacitive Touch Sensing Part 1 of 3

Sans fil - Wireless :

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Microchip - 8-bit Wireless Development Kit

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Wireless Power Solutions - Wurth Electronics, Texas Instruments, CadSoft and element14

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Analog Devices - Remote Water Quality Monitoring via a Low Power, Wireless Network

Texas instrument :

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Texas Instruments - Automotive LED Headlights

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Texas Instruments - Digital Power Solutions

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Texas Instruments - Industrial Sensor Solutions

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Texas Instruments - Wireless Pen Input Demo (Mobile World Congress)

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Texas Instruments - Industrial Automation System Components

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Texas Instruments - TMS320C66x - Industry's first 10-GHz fixed/floating point DSP

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Texas Instruments - TMS320C66x KeyStone Multicore Architecture

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Texas Instruments - Industrial Interfaces

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Texas Instruments - Concerto™ MCUs - Connectivity without compromise

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Texas Instruments - Stellaris Robot Chronos

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Texas Instruments - DRV8412-C2-KIT, Brushed DC and Stepper Motor Control Kit

Ordinateurs :

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Ask Ben Heck - Connect Raspberry Pi to Car Computer

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Ben's Portable Raspberry Pi Computer Trailer

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Ben's Raspberry Pi Portable Computer Trailer 2

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Ben Heck's Pocket Computer Trailer

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Ask Ben Heck - Atari Computer

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Ask Ben Heck - Using Computer Monitors for External Displays

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Raspberry Pi Partnership with BBC Computer Literacy Project - Answers from co-founder Eben Upton

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Installing RaspBMC on your Raspberry Pi with the Farnell element14 Accessory kit

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Raspberry Pi Served - Joey Hudy

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Happy Birthday Raspberry Pi

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Raspberry Pi board B product overview

Logiciels :

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Ask Ben Heck - Best Opensource or Free CAD Software

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Tektronix FPGAView™ software makes debugging of FPGAs faster than ever!

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Ask Ben Heck - Best Open-Source Schematic Capture and PCB Layout Software

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Introduction to Cadsoft EAGLE PCB Design Software in Chinese

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Altera - Developing Software for Embedded Systems on FPGAs

Tutoriels :

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Ben Heck The Great Glue Gun Trailer Part 1

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the knode tutorial - element14

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Ben's Autodesk 123D Tutorial Trailer

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Ben's CadSoft EAGLE Tutorial Trailer

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Ben Heck's Soldering Tutorial Trailer

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Ben Heck's AVR Dev Board tutorial

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Ben Heck's Pinball Tutorial Trailer

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Ben Heck's Interface Tutorial Trailer

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First Stage with Python and PiFace Digital

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Cypress - Getting Started with PSoC® 3 - Part 2

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Energy Harvesting Challenge

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New Features of CadSoft EAGLE v6

Autres documentations :

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Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Throughput at 20 MHz • Data and Non-volatile Program and Data Memories – 2/4K Bytes of In-System Self Programmable Flash • Endurance 10,000 Write/Erase Cycles – 128/256 Bytes In-System Programmable EEPROM • Endurance: 100,000 Write/Erase Cycles – 128/256 Bytes Internal SRAM – Programming Lock for Flash Program and EEPROM Data Security • Peripheral Features – One 8-bit Timer/Counter with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes – Four PWM Channels – On-chip Analog Comparator – Programmable Watchdog Timer with On-chip Oscillator – USI – Universal Serial Interface – Full Duplex USART • Special Microcontroller Features – debugWIRE On-chip Debugging – In-System Programmable via SPI Port – External and Internal Interrupt Sources – Low-power Idle, Power-down, and Standby Modes – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit – Internal Calibrated Oscillator • I/O and Packages – 18 Programmable I/O Lines – 20-pin PDIP, 20-pin SOIC, 20-pad MLF/VQFN • Operating Voltage – 1.8 – 5.5V • Speed Grades – 0 – 4 MHz @ 1.8 – 5.5V – 0 – 10 MHz @ 2.7 – 5.5V – 0 – 20 MHz @ 4.5 – 5.5V • Industrial Temperature Range: -40°C to +85°C • Low Power Consumption – Active Mode • 190 µA at 1.8V and 1MHz – Idle Mode • 24 µA at 1.8V and 1MHz – Power-down Mode • 0.1 µA at 1.8V and +25°C 8-bit Microcontroller with 2/4K Bytes In-System Programmable Flash ATtiny2313A ATtiny4313 Rev. 8246B–AVR–09/112 8246B–AVR–09/11 ATtiny2313A/4313 1. Pin Configurations Figure 1-1. Pinout ATtiny2313A/4313 (PCINT10/RESET/dW) PA2 (PCINT11/RXD) PD0 (PCINT12/TXD) PD1 (PCINT9/XTAL2) PA1 (PCINT8/CLKI/XTAL1) PA0 (PCINT13/CKOUT/XCK/INT0) PD2 (PCINT14/INT1) PD3 (PCINT15/T0) PD4 (PCINT16/OC0B/T1) PD5 GND 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 VCC PB7 (USCK/SCL/SCK/PCINT7) PB6 (MISO/DO/PCINT6) PB5 (MOSI/DI/SDA/PCINT5) PB4 (OC1B/PCINT4) PB3 (OC1A/PCINT3) PB2 (OC0A/PCINT2) PB1 (AIN1/PCINT1) PB0 (AIN0/PCINT0) PD6 (ICPI/PCINT17) PDIP/SOIC 1 2 3 4 5 MLF/VQFN 15 14 13 12 11 20 19 18 17 16 6 7 8 9 10 (PCINT12/TXD) PD1 (PCINT9/XTAL2) PA1 (PCINT8/CLKI/XTAL1) PA0 (PCINT13/CKOUT/XCK/INT0) PD2 (PCINT14/INT1) PD3 (PCINT15/T0) PD4 (PCINT16/OC0B/T1) PD5 GND (PCINT17/ICPI) PD6 (AIN0/PCINT0) PB0 PB5 (MOSI/DI/SDA/PCINT5) PB4 (OC1B/PCINT4) PB3 (OC1A/PCINT3) PB2 (OC0A/PCINT2) PB1 (AIN1/PCINT1) PD0 (RXD/PCINT11) PA2 (RESET/dW/PCINT10) VCC PB7 (USCK/SCL/SCK/PCINT7) PB6 (MISO/DO/PCINT6) NOTE: Bottom pad should be soldered to ground.3 8246B–AVR–09/11 ATtiny2313A/4313 1.1 Pin Descriptions 1.1.1 VCC Digital supply voltage. 1.1.2 GND Ground. 1.1.3 Port A (PA2..PA0) Port A is a 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability, except PA2 which has the RESET capability. To use pin PA2 as I/O pin, instead of RESET pin, program (“0”) RSTDISBL fuse. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATtiny2313A/4313 as listed on page 62. 1.1.4 Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny2313A/4313 as listed on page 63. 1.1.5 Port D (PD6..PD0) Port D is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATtiny2313A/4313 as listed on page 67. 1.1.6 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided that the reset pin has not been disabled. The minimum pulse length is given in Table 22-3 on page 201. Shorter pulses are not guaranteed to generate a reset. The Reset Input is an alternate function for PA2 and dW. The reset pin can also be used as a (weak) I/O pin. 1.1.7 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. XTAL1 is an alternate function for PA0.4 8246B–AVR–09/11 ATtiny2313A/4313 1.1.8 XTAL2 Output from the inverting Oscillator amplifier. XTAL2 is an alternate function for PA1.5 8246B–AVR–09/11 ATtiny2313A/4313 2. Overview The ATtiny2313A/4313 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny2313A/4313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram PROGRAM COUNTER PROGRAM FLASH INSTRUCTION REGISTER GND VCC INSTRUCTION DECODER CONTROL LINES STACK POINTER SRAM GENERAL PURPOSE REGISTER ALU STATUS REGISTER PROGRAMMING LOGIC SPI 8-BIT DATA BUS XTAL1 XTAL2 RESET INTERNAL OSCILLATOR OSCILLATOR WATCHDOG TIMER TIMING AND CONTROL MCU CONTROL REGISTER MCU STATUS REGISTER TIMER/ COUNTERS INTERRUPT UNIT EEPROM USI USART ANALOG COMPARATOR DATA REGISTER PORTB DATA DIR. REG. PORTB DATA REGISTER PORTA DATA DIR. REG. PORTA PORTB DRIVERS PB0 - PB7 PORTA DRIVERS PA0 - PA2 DATA REGISTER PORTD DATA DIR. REG. PORTD PORTD DRIVERS PD0 - PD6 ON-CHIP DEBUGGER INTERNAL CALIBRATED OSCILLATOR6 8246B–AVR–09/11 ATtiny2313A/4313 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny2313A/4313 provides the following features: 2/4K bytes of In-System Programmable Flash, 128/256 bytes EEPROM, 128/256 bytes SRAM, 18 general purpose I/O lines, 32 general purpose working registers, a single-wire Interface for On-chip Debugging, two flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, or by a conventional non-volatile memory programmer. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATtiny2313A/4313 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATtiny2313A/4313 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 2.2 Comparison Between ATtiny2313A and ATtiny4313 The ATtiny2313A and ATtiny4313 differ only in memory sizes. Table 2-1 summarizes the different memory sizes for the two devices. Table 2-1. Memory Size Summary Device Flash EEPROM RAM ATtiny2313A 2K Bytes 128 Bytes 128 Bytes ATtiny4313 4K Bytes 256 Bytes 256 Bytes7 8246B–AVR–09/11 ATtiny2313A/4313 3. About 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O Registers located in the extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically, this means “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Note that not all AVR devices include an extended I/O map. 3.3 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.8 8246B–AVR–09/11 ATtiny2313A/4313 4. CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 4.1 Architectural Overview Figure 4-1. Block Diagram of the AVR Architecture In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Flash Program Memory Instruction Register Instruction Decoder Program Counter Control Lines 32 x 8 General Purpose Registrers ALU Status and Control I/O Lines EEPROM Data Bus 8-bit Data SRAM Direct Addressing Indirect Addressing Interrupt Unit SPI Unit Watchdog Timer Analog Comparator I/O Module 2 I/O Module1 I/O Module n9 8246B–AVR–09/11 ATtiny2313A/4313 Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. 4.2 ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description. 4.3 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.10 8246B–AVR–09/11 ATtiny2313A/4313 The AVR Status Register – SREG – is defined as: • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. • Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information. • Bit 4 – S: Sign Bit, S = N ⊕ V The S-bit is always an exclusive or between the negative flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information. • Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. Bit 7 6 5 4 3 2 1 0 0x3F (0x5F) I T H S V N Z C SREG Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 011 8246B–AVR–09/11 ATtiny2313A/4313 4.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 4-2. AVR CPU General Purpose Working Registers Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 4-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. 4.4.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3. 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 … R13 0x0D General R14 0x0E Purpose R15 0x0F Working R16 0x10 Registers R17 0x11 … R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte12 8246B–AVR–09/11 ATtiny2313A/4313 Figure 4-3. The X-, Y-, and Z-registers In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.5 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The Stack Pointer is implemented as one 8-bit register in the I/O space. 4.6 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. 15 XH XL 0 X-register 7 07 0 R27 (0x1B) R26 (0x1A) 15 YH YL 0 Y-register 7 07 0 R29 (0x1D) R28 (0x1C) 15 ZH ZL 0 Z-register 70 7 0 R31 (0x1F) R30 (0x1E) Bit 7 6 5 4 3 2 1 0 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND13 8246B–AVR–09/11 ATtiny2313A/4313 Figure 4-4. The Parallel Instruction Fetches and Instruction Executions Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 4-5. Single Cycle ALU Operation 4.7 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 48. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. Refer to “Interrupts” on page 48 for more information. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be clk 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch T1 T2 T3 T4 CPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back T1 T2 T3 T4 clkCPU14 8246B–AVR–09/11 ATtiny2313A/4313 cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.. When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1< xxx ... ... ... ... 9.2 External Interrupts External Interrupts are triggered by the INT0 or INT1 pin or any of the PCINT17..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0, INT1 or PCINT17..0 pins are configured as outputs. This feature provides a way of generating a software interrupt. Pin change 0 interrupts PCI0 will trigger if any enabled PCINT7..0 pin toggles. Pin change 1 interrupts PCI1 will trigger if any enabled PCINT10..8 pin toggles. Pin change 2 interrupts PCI2 will trigger, if any enabled PCINT17..11 pin toggles. The PCMSK0, PCMSK1, and PCMSK2 Registers control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT17..0 are detected asynchronously, which means that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The INT0 and INT1 interrupts can be triggered by a falling or rising edge or a low level. This is set up as shown in “MCUCR – MCU Control Register” on page 51. When the INT0 or INT1 interrupt is enabled and configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT0 or INT1 requires the presence of an I/O clock, as described in “Clock Sources” on page 27.50 8246B–AVR–09/11 ATtiny2313A/4313 9.2.1 Low Level Interrupt A low level interrupt on INT0 or INT1 is detected asynchronously. This means that the interrupt source can be used for waking the part also from sleep modes other than Idle (the I/O clock is halted in all sleep modes except Idle). Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL fuses, as described in “Clock System” on page 26. If the low level on the interrupt pin is removed before the device has woken up then program execution will not be diverted to the interrupt service routine but continue from the instruction following the SLEEP command. 9.2.2 Pin Change Interrupt Timing A timing example of a pin change interrupt is shown in Figure 9-1. Figure 9-1. Timing of pin change interrupts clk PCINT(0) pin_lat pin_sync pcint_in_(0) pcint_syn pcint_setflag PCIF PCINT(0) pin_sync pcint_syn pin_lat D Q LE pcint_setflag PCIF clk clk PCINT(0) in PCMSK(x) pcint_in_(0) 0 x51 8246B–AVR–09/11 ATtiny2313A/4313 9.3 Register Description 9.3.1 MCUCR – MCU Control Register The External Interrupt Control Register contains control bits for interrupt sense control. • Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT1 pin that activate the interrupt are defined in Table 9-2. The value on the INT1 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt • Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 9-3. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. Bit 7 6 5 4 3 2 1 0 0x35 (0x55) PUD SM1 SE SM0 ISC11 ISC10 ISC01 ISC00 MCUCR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 9-2. Interrupt 1 Sense Control ISC11 ISC10 Description 0 0 The low level of INT1 generates an interrupt request. 0 1 Any logical change on INT1 generates an interrupt request. 1 0 The falling edge of INT1 generates an interrupt request. 1 1 The rising edge of INT1 generates an interrupt request. Table 9-3. Interrupt 0 Sense Control ISC01 ISC00 Description 0 0 The low level of INT0 generates an interrupt request. 0 1 Any logical change on INT0 generates an interrupt request. 1 0 The falling edge of INT0 generates an interrupt request. 1 1 The rising edge of INT0 generates an interrupt request.52 8246B–AVR–09/11 ATtiny2313A/4313 9.3.2 GIMSK – General Interrupt Mask Register • Bits 2..0 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bit 7 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control bits (ISC11 and ISC10) in the External Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from the INT1 Interrupt Vector. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control bits (ISC01 and ISC00) in the External Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector. • Bit 5 – PCIE0: Pin Change Interrupt Enable 0 When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register. • Bit 4 – PCIE2: Pin Change Interrupt Enable 2 When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 2 is enabled. Any change on any enabled PCINT17..11 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI2 Interrupt Vector. PCINT17..11 pins are enabled individually by the PCMSK2 Register. • Bit 3 – PCIE1: Pin Change Interrupt Enable 1 When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled. Any change on any enabled PCINT10..8 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT10..8 pins are enabled individually by the PCMSK1 Register. Bit 7 6 5 4 3 2 1 0 0x3B (0x5B) INT1 INT0 PCIE0 PCIE2 PCIE1 – – – GIMSK Read/Write R/W R/W R/W R/W R/W R R R Initial Value 0 0 0 0 0 0 0 053 8246B–AVR–09/11 ATtiny2313A/4313 9.3.3 GIFR – General Interrupt Flag Register • Bits 2..0 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bit 7 – INTF1: External Interrupt Flag 1 When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT1 is configured as a level interrupt. • Bit 6 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt. • Bit 5 – PCIF0: Pin Change Interrupt Flag 0 When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF becomes set (one). If the I-bit in SREG and the PCIE0 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. • Bit 4 – PCIF2: Pin Change Interrupt Flag 2 When a logic change on any PCINT17..11 pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in SREG and the PCIE2 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. • Bit 3 – PCIF1: Pin Change Interrupt Flag 1 When a logic change on any PCINT10..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. 9.3.4 PCMSK2 – Pin Change Mask Register 2 • Bit 7 – Res: Reserved Bit These bits are reserved and will always read as zero. Bit 7 6 5 4 3 2 1 0 0x3A (0x5A) INTF1 INTF0 PCIF0 PCIF2 PCIF1 – – – GIFR Read/Write R/W R/W R/W R/W R/W R R R Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x05 (0x25) – PCINT17 PCINT16 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCMSK2 Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 054 8246B–AVR–09/11 ATtiny2313A/4313 • Bits 6..0 – PCINT17..11: Pin Change Enable Mask 17..11 Each PCINT17..11 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT17..11 is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT17..11 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 9.3.5 PCMSK1 – Pin Change Mask Register 1 • Bits 7:3 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bits 2..0 – PCINT10..8: Pin Change Enable Mask 10..8 Each PCINT10..8 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT10..8 is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT10..8 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 9.3.6 PCMSK0 – Pin Change Mask Register 0 • Bits 7..0 – PCINT7..0: Pin Change Enable Mask 7..0 Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. Bit 7 6 5 4 3 2 1 0 0x04 (0x24) – – – – – PCINT10 PCINT9 PCINT8 PCMSK1 Read/Write R R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x20 (0x40) PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 055 8246B–AVR–09/11 ATtiny2313A/4313 10. I/O-Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both VCC and Ground as indicated in Figure 10-1 on page 55. See “Electrical Characteristics” on page 198 for a complete list of parameters. Figure 10-1. I/O Pin Equivalent Schematic All registers and bit references in this section are written in general form. A lower case “x” represents the numbering letter for the port, and a lower case “n” represents the bit number. However, when using the register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Registers and bit locations are listed in “Register Description” on page 69. Three I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the pull-up function for all pins in all ports when set. Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page 56. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in “Alternate Port Functions” on page 60. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. Cpin Logic Rpu See Figure "General Digital I/O" for Details Pxn56 8246B–AVR–09/11 ATtiny2313A/4313 10.1 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 10-2. General Digital I/O(1) Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports. 10.1.1 Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register Description” on page 69, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). clk RPx RRx RDx WDx PUD SYNCHRONIZER WDx: WRITE DDRx WRx: WRITE PORTx RRx: READ PORTx REGISTER RPx: READ PORTx PIN PUD: PULLUP DISABLE clkI/O: I/O CLOCK RDx: READ DDRx D L Q Q RESET RESET Q D Q Q Q D CLR PORTxn Q Q D CLR DDxn PINxn DATA BUS SLEEP SLEEP: SLEEP CONTROL Pxn I/O WPx 0 1 WRx WPx: WRITE PINx REGISTER57 8246B–AVR–09/11 ATtiny2313A/4313 10.1.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 10.1.3 Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b10) as an intermediate step. Table 10-1 summarizes the control signals for the pin value. 10.1.4 Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As shown in Figure 10-2 on page 56, the PINxn Register bit and the preceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. Figure 10-3 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted tpd,max and tpd,min respectively. Figure 10-3. Synchronization when Reading an Externally Applied Pin value Table 10-1. Port Pin Configurations DDxn PORTxn PUD (in MCUCR) I/O Pull-up Comment 0 0 X Input No Tri-state (Hi-Z) 0 1 0 Input Yes Pxn will source current if ext. pulled low 0 1 1 Input No Tri-state (Hi-Z) 1 0 X Output No Output Low (Sink) 1 1 X Output No Output High (Source) XXX in r17, PINx 0x00 0xFF INSTRUCTIONS SYNC LATCH PINxn r17 XXX SYSTEM CLK tpd, max tpd, min58 8246B–AVR–09/11 ATtiny2313A/4313 Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 10-4 on page 58. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is one system clock period. Figure 10-4. Synchronization when Reading a Software Assigned Pin Value 10.1.5 Digital Input Enable and Sleep Modes As shown in Figure 10-2 on page 56, the digital input signal can be clamped to ground at the input of the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down and Standby modes to avoid high power consumption if some input signals are left floating, or have an analog signal level close to VCC/2. SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in “Alternate Port Functions” on page 60. If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change. 10.1.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is out PORTx, r16 nop in r17, PINx 0xFF 0x00 0xFF SYSTEM CLK r16 INSTRUCTIONS SYNC LATCH PINxn r17 t pd59 8246B–AVR–09/11 ATtiny2313A/4313 important, it is recommended to use an external pull-up or pulldown. Connecting unused pins directly to VCC or GND is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output. 10.1.7 Program Examples The following code example shows how to set port A pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with a pull-up assigned to port pin 4. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Note: Two temporary registers are used to minimize the time from pull-ups are set on pins 0, 1 and 4, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. Note: 1. See “Code Examples” on page 7. Assembly Code Example ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1< CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is connected to. 13.3 External Clock Source An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock (clkT1/clkT0). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 13-1 shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the internal system clock. The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects. Figure 13-1. T1/T0 Pin Sampling The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated. Tn_sync (To Clock Select Logic) Synchronization Edge Detector D Q D Q LE Tn D Q clkI/O119 8246B–AVR–09/11 ATtiny2313A/4313 Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 13-2. Prescaler for Timer/Counter0 and Timer/Counter1(1) Note: 1. The synchronization logic on the input pins (T1/T0) is shown in Figure 13-1 on page 118. 13.4 Register Description 13.4.1 GTCCR – General Timer/Counter Control Register • Bits 7..1 – Res: Reserved Bits These bits are reserved bits in the ATtiny2313A/4313 and will always read as zero. • Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0 When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. PSR10 Clear clkT1 clkT0 T1 T0 clkI/O Synchronization Synchronization Bit 7 6 5 4 3 2 1 0 0x23 (0x43) — — — — — — — PSR10 GTCCR Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0120 8246B–AVR–09/11 ATtiny2313A/4313 14. USART 14.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous Communication Mode 14.2 Overview The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. A simplified block diagram of the USART Transmitter is shown in Figure 14-1. CPU accessible I/O Registers and I/O pins are shown in bold. Figure 14-1. USART Block Diagram(1) Note: 1. Refer to Figure 1-1 on page 2, Table 10-9 on page 68, and Table 10-6 on page 66 for USART pin placement. PARITY GENERATOR UBRR[H:L] UDR (Transmit) UCSRA UCSRB UCSRC BAUD RATE GENERATOR TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER RxD TxD PIN CONTROL UDR (Receive) PIN CONTROL XCK DATA RECOVERY CLOCK RECOVERY PIN CONTROL TX CONTROL RX CONTROL PARITY CHECKER DATA BUS OSC SYNC LOGIC Clock Generator Transmitter Receiver121 8246B–AVR–09/11 ATtiny2313A/4313 The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control registers are shared by all units. The Clock Generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only used by synchronous transfer mode. The Transmitter consists of a single write buffer, a serial Shift Register, Parity Generator and Control logic for handling different serial frame formats. The write buffer allows a continuous transfer of data without any delay between frames. The Receiver is the most complex part of the USART module due to its clock and data recovery units. The recovery units are used for asynchronous data reception. In addition to the recovery units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level receive buffer (UDR). The Receiver supports the same frame formats as the Transmitter, and can detect Frame Error, Data OverRun and Parity Errors. 14.2.1 AVR USART vs. AVR UART – Compatibility The USART is fully compatible with the AVR UART regarding: • Bit locations inside all USART Registers. • Baud Rate Generation. • Transmitter Operation. • Transmit Buffer Functionality. • Receiver Operation. However, the receive buffering has two improvements that will affect the compatibility in some special cases: • A second Buffer Register has been added. The two Buffer Registers operate as a circular FIFO buffer. Therefore the UDR must only be read once for each incoming data! More important is the fact that the error flags (FE and DOR) and the ninth data bit (RXB8) are buffered with the data in the receive buffer. Therefore the status bits must always be read before the UDR Register is read. Otherwise the error status will be lost since the buffer state is lost. • The Receiver Shift Register can now act as a third buffer level. This is done by allowing the received data to remain in the serial Shift Register (see Figure 14-1) if the Buffer Registers are full, until a new start bit is detected. The USART is therefore more resistant to Data OverRun (DOR) error conditions. The following control bits have changed name, but have same functionality and register location: • CHR9 is changed to UCSZ2. • OR is changed to DOR. 14.3 Clock Generation The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation: Normal asynchronous, Double Speed asynchronous, Master synchronous and Slave synchronous mode. The UMSEL bit in USART Control and Status Register C (UCSRC) selects between asynchronous and synchronous operation. Double Speed (asynchronous mode only) is controlled by the U2X found in the UCSRA Register. When using synchronous mode (UMSEL = 1), the Data Direction Register for the XCK122 8246B–AVR–09/11 ATtiny2313A/4313 pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using synchronous mode. Figure 14-2 shows a block diagram of the clock generation logic. Figure 14-2. Clock Generation Logic, Block Diagram Signal description: txclk Transmitter clock (Internal Signal). rxclk Receiver base clock (Internal Signal). xcki Input from XCK pin (internal Signal). Used for synchronous slave operation. xcko Clock output to XCK pin (Internal Signal). Used for synchronous master operation. fosc XTAL pin frequency (System Clock). 14.3.1 Internal Clock Generation – The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The description in this section refers to Figure 14-2. The USART Baud Rate Register (UBRR) and the down-counter connected to it function as a programmable prescaler or baud rate generator. The down-counter, running at system clock (fosc), is loaded with the UBRR value each time the counter has counted down to zero or when the UBRRL Register is written. A clock is generated each time the counter reaches zero. This clock is the baud rate generator clock output (= fosc/(UBRR+1)). The Transmitter divides the baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator output is used directly by the Receiver’s clock and data recovery units. However, the recovery units use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the UMSEL, U2X and DDR_XCK bits. Table 14-1 contains equations for calculating the baud rate (in bits per second) and for calculating the UBRR value for each mode of operation using an internally generated clock source. Prescaling Down-Counter /2 UBRR /4 /2 fosc UBRR+1 Sync Register OSC XCK Pin txclk U2X UMSEL DDR_XCK 0 1 0 1 xcki xcko DDR_XCK rxclk 0 1 1 0 Edge Detector UCPOL123 8246B–AVR–09/11 ATtiny2313A/4313 Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps) BAUD Baud rate (in bits per second, bps) fOSC System Oscillator clock frequency UBRR Contents of the UBRRH and UBRRL Registers, (0-4095) Some examples of UBRR values for some system clock frequencies are found in Table 14-9 (see page 142). 14.3.2 Double Speed Operation (U2X) The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only has effect for the asynchronous operation. Set this bit to zero when using synchronous operation. Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for asynchronous communication. Note however that the Receiver will in this case only use half the number of samples (reduced from 16 to 8) for data sampling and clock recovery, and therefore a more accurate baud rate setting and system clock are required when this mode is used. For the Transmitter, there are no downsides. 14.3.3 External Clock External clocking is used by the synchronous slave modes of operation. The description in this section refers to Figure 14-2 for details. External clock input from the XCK pin is sampled by a synchronization register to minimize the chance of meta-stability. The output from the synchronization register must then pass through an edge detector before it can be used by the Transmitter and Receiver. This process introduces a two CPU clock period delay and therefore the maximum external XCK clock frequency is limited by the following equation: Note that fosc depends on the stability of the system clock source. It is therefore recommended to add some margin to avoid possible loss of data due to frequency variations. Table 14-1. Equations for Calculating Baud Rate Register Setting Operating Mode Equation for Calculating Baud Rate(1) Equation for Calculating UBRR Value Asynchronous Normal mode (U2X = 0) Asynchronous Double Speed mode (U2X = 1) Synchronous Master mode BAUD f OSC 16( ) UBRR + 1 = -------------------------------------- UBRR f OSC 16BAUD = ------------------------ – 1 BAUD f OSC 8( ) UBRR + 1 = ----------------------------------- UBRR f OSC 8BAUD = -------------------- – 1 BAUD f OSC 2( ) UBRR + 1 = ----------------------------------- UBRR f OSC 2BAUD = -------------------- – 1 f XCK f OSC 4 < -----------124 8246B–AVR–09/11 ATtiny2313A/4313 14.3.4 Synchronous Clock Operation When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) is changed. Figure 14-3. Synchronous Mode XCK Timing. The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is used for data change. As Figure 14-3 shows, when UCPOL is zero the data will be changed at rising XCK edge and sampled at falling XCK edge. If UCPOL is set, the data will be changed at falling XCK edge and sampled at rising XCK edge. 14.4 Frame Formats A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of the following as valid frame formats: • 1 start bit • 5, 6, 7, 8, or 9 data bits • no, even or odd parity bit • 1 or 2 stop bits A frame starts with the start bit followed by the least significant data bit. Then the next data bits, up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle (high) state. Figure 14-4 illustrates the possible combinations of the frame formats. Bits inside brackets are optional. Figure 14-4. Frame Formats RxD / TxD XCK RxD / TxD UCPOL = 0 XCK UCPOL = 1 Sample Sample (IDLE) St Sp1 [Sp2] 0 2 3 4 [5] [6] [7] [8] [P] 1 (St / IDLE) FRAME125 8246B–AVR–09/11 ATtiny2313A/4313 St Start bit, always low. (n) Data bits (0 to 8). P Parity bit. Can be odd or even. Sp Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits in UCSRB and UCSRC. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter. The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame. The USART Parity mode (UPM1:0) bits enable and set the type of parity bit. The selection between one or two stop bits is done by the USART Stop Bit Select (USBS) bit. The Receiver ignores the second stop bit. An FE (Frame Error) will therefore only be detected in the cases where the first stop bit is zero. 14.4.1 Parity Bit Calculation The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of the exclusive or is inverted. The relation between the parity bit and data bits is as follows: Peven Parity bit using even parity Podd Parity bit using odd parity dn Data bit n of the character If used, the parity bit is located between the last data bit and first stop bit of a serial frame. 14.5 USART Initialization The USART has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the initialization. Before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the registers are changed. The TXC flag can be used to check that the Transmitter has completed all transfers, and the RXC flag can be used to check that there are no unread data in the receive buffer. Note that the TXC flag must be cleared before each transmission (before UDR is written) if it is used for this purpose. Peven dn – 1 … d3 d2 d1 d0 0 Podd ⊕⊕⊕⊕⊕⊕ dn – 1 … d3 d2 d1 d0 ⊕⊕⊕⊕⊕⊕ 1 = =126 8246B–AVR–09/11 ATtiny2313A/4313 The following simple USART initialization code examples show one assembly and one C function that are equal in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers. Note: 1. See “Code Examples” on page 7. More advanced initialization routines can be made that include frame format as parameters, disable interrupts and so on. However, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization code can be placed directly in the main routine, or be combined with initialization code for other I/O modules. 14.6 Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overridden by the USART and given the function as the Transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions. If synchronous operation is used, the clock on the XCK pin will be overridden and used as transmission clock. Assembly Code Example(1) USART_Init: ; Set baud rate out UBRRH, r17 out UBRRL, r16 ; Enable receiver and transmitter ldi r16, (1<>8); UBRRL = (unsigned char)baud; /* Enable receiver and transmitter */ UCSRB = (1<> 1) & 0x01; return ((resh << 8) | resl); }132 8246B–AVR–09/11 ATtiny2313A/4313 The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. 14.7.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXC) flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit will become zero. When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART Receive Complete interrupt will be executed as long as the RXC flag is set (provided that global interrupts are enabled). When interrupt-driven data reception is used, the receive complete routine must read the received data from UDR in order to clear the RXC flag, otherwise a new interrupt will occur once the interrupt routine terminates. 14.7.4 Receiver Error Flags The USART Receiver has three error flags: Frame Error (FE), Data OverRun (DOR) and Parity Error (UPE). All can be accessed by reading UCSRA. Common for the error flags is that they are located in the receive buffer together with the frame for which they indicate the error status. Due to the buffering of the error flags, the UCSRA must be read before the receive buffer (UDR), since reading the UDR I/O location changes the buffer read location. Another equality for the error flags is that they can not be altered by software doing a write to the flag location. However, all flags must be set to zero when the UCSRA is written for upward compatibility of future USART implementations. None of the error flags can generate interrupts. The Frame Error (FE) flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. The FE flag is zero when the stop bit was correctly read (as one), and the FE flag will be one when the stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. The FE flag is not affected by the setting of the USBS bit in UCSRC since the Receiver ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when writing to UCSRA. The Data OverRun (DOR) flag indicates data loss due to a receiver buffer full condition. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. If the DOR flag is set there was one or more serial frame lost between the frame last read from UDR, and the next frame read from UDR. For compatibility with future devices, always write this bit to zero when writing to UCSRA. The DOR flag is cleared when the frame received was successfully moved from the Shift Register to the receive buffer. The Parity Error (UPE) Flag indicates that the next frame in the receive buffer had a Parity Error when received. If Parity Check is not enabled the UPE bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRA. For more details see “Parity Bit Calculation” on page 125 and “Parity Checker” on page 132. 14.7.5 Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of Parity Check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the Parity133 8246B–AVR–09/11 ATtiny2313A/4313 Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPE) flag can then be read by software to check if the frame had a Parity Error. The UPE bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPM1 = 1). This bit is valid until the receive buffer (UDR) is read. 14.7.6 Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e., the RXEN is set to zero) the Receiver will no longer override the normal function of the RxD port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost 14.7.7 Flushing the Receive Buffer The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDR I/O location until the RXC flag is cleared. The following code example shows how to flush the receive buffer. Note: 1. See “Code Examples” on page 7. 14.8 Asynchronous Data Reception The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the RxD pin. The data recovery logic samples and low pass filters each incoming bit, thereby improving the noise immunity of the Receiver. The asynchronous reception operational range depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. 14.8.1 Asynchronous Clock Recovery The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 14-5 illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times Assembly Code Example(1) USART_Flush: sbis UCSRA, RXC ret in r16, UDR rjmp USART_Flush C Code Example(1) void USART_Flush( void ) { unsigned char dummy; while ( UCSRA & (1< MSB MSB 6 5 4 3 2 1 LSB 1 2 3 4 5 6 7 8 6 5 4 3 2 1 LSB USCK USCK DO DI A B C D E CYCLE ( Reference )159 8246B–AVR–09/11 ATtiny2313A/4313 SPITransfer_loop: out USICR,r17 in r16, USISR sbrs r16, USIOIF rjmp SPITransfer_loop in r16,USIDR ret The code is size optimized using only eight instructions (plus return). The code example assumes that the DO and USCK pins have been enabled as outputs in DDRA. The value stored in register r16 prior to the function is called is transferred to the slave device, and when the transfer is completed the data received from the slave is stored back into the register r16. The second and third instructions clear the USI Counter Overflow Flag and the USI counter value. The fourth and fifth instructions set three-wire mode, positive edge clock, count at USITC strobe, and toggle USCK. The loop is repeated 16 times. The following code demonstrates how to use the USI as an SPI master with maximum speed (fSCK = fCK/2): SPITransfer_Fast: out USIDR,r16 ldi r16,(1< 2 CPU clock cycles – When fck >= 12MHz: 3 CPU clock cycles • Minimum high period of serial clock: – When fck < 12MHz: > 2 CPU clock cycles – When fck >= 12MHz: 3 CPU clock cycles VCC GND XTAL1 SCK MISO MOSI RESET +1.8 - 5.5V195 8246B–AVR–09/11 ATtiny2313A/4313 21.3.1 Pin Mapping The pin mapping is listed in Table 21-7. Note that not all parts use the SPI pins dedicated for the internal SPI interface. 21.3.2 Programming Algorithm When writing serial data to the ATtiny2313A/4313, data is clocked on the rising edge of SCK. When reading data from the ATtiny2313A/4313, data is clocked on the falling edge of SCK. See Figure 22-6 on page 205 and Figure 22-7 on page 205 for timing details. To program and verify the ATtiny2313A/4313 in the serial programming mode, the following sequence is recommended (See Table 21-8, “Serial Programming Instruction Set,” on page 196): 1. Power-up sequence: apply power between VCC and GND while RESET and SCK are set to “0” – In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse after SCK has been set to '0'. The duration of the pulse must be at least tRST plus two CPU clock cycles. See Table 22-3 on page 201 for definition of minimum pulse width on RESET pin, tRST 2. Wait for at least 20 ms and then enable serial programming by sending the Programming Enable serial instruction to the MOSI pin 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync, the second byte (0x53) will echo back when issuing the third byte of the Programming Enable instruction – Regardless if the echo is correct or not, all four bytes of the instruction must be transmitted – If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command 4. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 4 LSB of the address and data together with the Load Program Memory Page instruction. – To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address – The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 6 MSB of the address – If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 21-9 on page 197). Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming. 5. The EEPROM can be programmed one byte or one page at a time. Table 21-7. Pin Mapping Serial Programming Symbol Pins I/O Description MOSI PB5 I Serial Data in MISO PB6 O Serial Data out SCK PB7 I Serial Clock196 8246B–AVR–09/11 ATtiny2313A/4313 – A: Byte programming. The EEPROM array is programmed one byte at a time by supplying the address and data together with the Write instruction. EEPROM memory locations are automatically erased before new data is written. If polling (RDY/BSY) is not used, the user must wait at least tWD_EEPROM before issuing the next byte (See Table 21-9). In a chip erased device, no 0xFFs in the data file(s) need to be programmed – B: Page programming (the EEPROM array is programmed one page at a time). The memory page is loaded one byte at a time by supplying the 6 LSB of the address and data together with the Load EEPROM Memory Page instruction. The EEPROM memory page is stored by loading the Write EEPROM Memory Page Instruction with the 7 MSB of the address. When using EEPROM page access only byte locations loaded with the Load EEPROM Memory Page instruction are altered and the remaining locations remain unchanged. If polling (RDY/BSY) is not used, the user must wait at least tWD_EEPROM before issuing the next byte (See Table 21-9). In a chip erased device, no 0xFF in the data file(s) need to be programmed 6. Any memory location can be verified by using the Read instruction, which returns the content at the selected address at the serial output pin (MISO) 7. At the end of the programming session, RESET can be set high to commence normal operation 8. Power-off sequence (if required): set RESET to “1”, and turn VCC power off 21.3.3 Programming Instruction Set The instruction set for serial programming is described in Table 21-8. Table 21-8. Serial Programming Instruction Set Instruction Instruction Format Byte 1 Byte 2 Byte 3 Byte4 Operation Programming Enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after RESET goes low. Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash. Read Program Memory 0010 H000 0000 00aa bbbb bbbb oooo oooo Read H (high or low) data o from Program memory at word address a:b. Load Program Memory Page 0100 H000 000x xxxx xxxx bbbb iiii iiii Write H (high or low) data i to Program Memory page at word address b. Data low byte must be loaded before Data high byte is applied within the same address. Write Program Memory Page 0100 1100 0000 00aa bbbb xxxx xxxx xxxx Write Program Memory Page at address a:b. Read EEPROM Memory 1010 0000 000x xxxx xbbb bbbb oooo oooo Read data o from EEPROM memory at address b. Write EEPROM Memory 1100 0000 000x xxxx xbbb bbbb iiii iiii Write data i to EEPROM memory at address b. Load EEPROM Memory Page (page access) 1100 0001 0000 0000 0000 00bb iiii iiii Load data i to EEPROM memory page buffer. After data is loaded, program EEPROM page.197 8246B–AVR–09/11 ATtiny2313A/4313 Note: a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care If the LSB of RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until this bit returns ‘0’ before the next instruction is carried out. Within the same page, the low data byte must be loaded prior to the high data byte. After data is loaded to the page buffer, program the EEPROM page. 21.4 Programming Time for Flash and EEPROM Flash and EEPROM wait times are listed in Table 21-9. Write EEPROM Memory Page (page access) 1100 0010 00xx xxxx xbbb bb00 xxxx xxxx Write EEPROM page at address b. Read Lock bits 0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock bits. “0” = programmed, “1” = unprogrammed. See Table 20-1 on page 178 for details. Write Lock bits 1010 1100 111x xxxx xxxx xxxx 11ii iiii Write Lock bits. Set bits = “0” to program Lock bits. See Table 20-1 on page 178 for details. Read Signature Byte 0011 0000 000x xxxx xxxx xxbb oooo oooo Read Signature Byte o at address b. Write Fuse bits 1010 1100 1010 0000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to unprogram. Write Fuse High bits 1010 1100 1010 1000 xxxx xxxx iiii iiii Set bits = “0” to program, “1” to unprogram. Write Extended Fuse Bits 1010 1100 1010 0100 xxxx xxxx xxxx xxxi Set bits = “0” to program, “1” to unprogram. Read Fuse bits 0101 0000 0000 0000 xxxx xxxx oooo oooo Read Fuse bits. “0” = programmed, “1” = unprogrammed. Read Fuse High bits 0101 1000 0000 1000 xxxx xxxx oooo oooo Read Fuse High bits. “0” = programmed, “1” = unprogrammed. Read Extended Fuse Bits 0101 0000 0000 1000 xxxx xxxx oooo oooo Read Extended Fuse bits. “0” = programmed, “1” = unprogrammed. Read Calibration Byte 0011 1000 000x xxxx 0000 000b oooo oooo Read Calibration Byte at address b. Poll RDY/BSY 1111 0000 0000 0000 xxxx xxxx xxxx xxxo If o = “1”, a programming operation is still busy. Wait until this bit returns to “0” before applying another command. Table 21-8. Serial Programming Instruction Set Instruction Instruction Format Byte 1 Byte 2 Byte 3 Byte4 Operation Table 21-9. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay tWD_FLASH 4.5 ms tWD_EEPROM 4.0 ms tWD_ERASE 9.0 ms tWD_FUSE 4.5 ms198 8246B–AVR–09/11 ATtiny2313A/4313 22. Electrical Characteristics 22.1 Absolute Maximum Ratings* 22.2 DC Characteristics Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Maximum Operating Voltage ............................................ 6.0V DC Current per I/O Pin ............................................... 40.0 mA DC Current VCC and GND Pins................................ 200.0 mA TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) Symbol Parameter Condition Min. Typ. Max. Units VIL Input Low Voltage except XTAL1 and RESET pin VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V -0.5 0.2VCC 0.3VCC V VIH Input High-voltage except XTAL1 and RESET pins VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V 0.7VCC (1) 0.6VCC (1) VCC +0.5 (2) V VIL1 Input Low Voltage XTAL1 pin VCC = 1.8V - 5.5V -0.5 0.1VCC V VIH1 Input High-voltage XTAL1 pin VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V 0.8VCC (1) 0.7VCC (1) VCC +0.5 (2) V VIL2 Input Low Voltage RESET pin VCC = 1.8V - 5.5V -0.5 0.2VCC V VIH2 Input High-voltage RESET pin VCC = 1.8V - 5.5V 0.9VCC (1) VCC +0.5 (2) V VIL3 Input Low Voltage RESET pin as I/O VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V -0.5 0.2VCC 0.3VCC V VIH3 Input High-voltage RESET pin as I/O VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V 0.7VCC (1) 0.6VCC (1) VCC +0.5 (2) V VOL Output Low Voltage(3) (Except Reset Pin)(5) IOL = 20 mA, VCC = 5V IOL = 10mA, VCC = 3V 0.8 0.6 V V VOH Output High-voltage(4) (Except Reset Pin)(5) IOH = -20 mA, VCC = 5V IOH = -10 mA, VCC = 3V 4.2 2.4 V V I IL Input Leakage Current I/O Pin VCC = 5.5V, pin low (absolute value) 1(6) µA IIH Input Leakage Current I/O Pin VCC = 5.5V, pin high (absolute value) 1(6) µA RRST Reset Pull-up Resistor 30 60 kΩ Rpu I/O Pin Pull-up Resistor 20 50 kΩ199 8246B–AVR–09/11 ATtiny2313A/4313 Notes: 1. “Min” means the lowest value where the pin is guaranteed to be read as high. 2. “Max” means the highest value where the pin is guaranteed to be read as low. 3. Although each I/O port can sink more than the test conditions (20 mA at VCC = 5V, 10 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: 1] The sum of all IOL, for all ports, should not exceed 60 mA. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition. 4. Although each I/O port can source more than the test conditions (20 mA at VCC = 5V, 10 mA at VCC = 3V) under steady state conditions (non-transient), the following must be observed: 1] The sum of all IOH, for all ports, should not exceed 60 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. 5. The RESET pin must tolerate high voltages when entering and operating in programming modes and, as a consequence, has a weak drive strength as compared to regular I/O pins. See Figure 23-29 and Figure 23-30. 6. These are test limits, which account for leakage currents of the test environment. Actual device leakage currents are lower. 7. Values using methods described in “Minimizing Power Consumption” on page 36. Power Reduction is enabled (PRR = 0xFF), the external clock is selected (CKSEL = 0000), and there is no I/O drive. 8. BOD Disabled. I CC Power Supply Current Active 1MHz, VCC = 2V(7) 0.2 0.55 mA Active 4MHz, VCC = 3V(7) 1.3 2.5 mA Active 8MHz, VCC = 5V(7) 3.9 7 mA Idle 1MHz, VCC = 2V(7) 0.03 0.15 mA Idle 4MHz, VCC = 3V(7) 0.25 0.6 mA Idle 8MHz, VCC = 5V(7) 1 2 mA Power-down mode WDT enabled, VCC = 3V(8) 4 10 µA WDT disabled, VCC = 3V(8) < 0.15 2 µA TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) (Continued) Symbol Parameter Condition Min. Typ. Max. Units200 8246B–AVR–09/11 ATtiny2313A/4313 22.3 Speed The maximum operating frequency of the device is dependent on supply voltage, VCC . The relationship between supply voltage and maximum operating frequency is piecewise linear, as shown in Figure 22-1. Figure 22-1. Maximum Frequency vs. VCC 22.4 Clock Characteristics 22.4.1 Calibrated Internal RC Oscillator Accuracy It is possible to manually calibrate the internal oscillator to be more accurate than default factory calibration. Note that the oscillator frequency depends on temperature and voltage. Voltage and temperature characteristics can be found in Figure 23-46 on page 229, and Figure 23-47 on page 230. Notes: 1. Accuracy of oscillator frequency at calibration point (fixed temperature and fixed voltage). 4 MHz 1.8V 5.5V 4.5V 20 MHz 2.7V 10 MHz Table 22-1. Calibration Accuracy of Internal RC Oscillator Calibration Method Target Frequency VCC Temperature Accuracy at given Voltage & Temperature(1) Factory Calibration 4.0 / 8.0MHz 3V 25°C ±10% User Calibration Fixed frequency within: 3.1 – 4.7 MHz / 7.3 – 9.1MHz Fixed voltage within: 1.8V – 5.5V Fixed temperature within: -40°C – 85°C ±2%201 8246B–AVR–09/11 ATtiny2313A/4313 22.4.2 External Clock Drive Figure 22-2. External Clock Drive Waveform 22.5 System and Reset Characteristics Notes: 1. When RESET pin used as reset (not as I/O). 2. Not tested in production. VIL1 VIH1 Table 22-2. External Clock Drive Symbol Parameter VCC = 1.8 - 5.5V VCC = 2.7 - 5.5V VCC = 4.5 - 5.5V Min. Max. Min. Max. Min. Max. Units 1/tCLCL Clock Frequency 0 4 0 10 0 20 MHz tCLCL Clock Period 250 100 50 ns tCHCX High Time 100 40 20 ns tCLCX Low Time 100 40 20 ns tCLCH Rise Time 2.0 1.6 0.5 µs tCHCL Fall Time 2.0 1.6 0.5 µs ΔtCLCL Change in period from one clock cycle to the next 2 2 2 % Table 22-3. Reset, Brown-out, and Internal Voltage Characteristics Symbol Parameter Condition Min Typ Max Units VRST RESET Pin Threshold Voltage 0.2 VCC 0.8VCC V t RST Minimum pulse width on RESET Pin (1)(2) VCC = 1.8 - 5.5V 2.5 µs VHYST Brown-out Detector Hysteresis (2) 50 mV tBOD Min Pulse Width on Brown-out Reset (2) 2 µs VBG Internal bandgap reference voltage VCC = 2.7V TA = 25°C 1.0 1.1 1.2 V tBG Internal bandgap reference start-up time (2) VCC = 2.7V TA = 25°C 40 70 µs IBG Internal bandgap reference current consumption (2) VCC = 2.7V TA = 25°C 15 µA202 8246B–AVR–09/11 ATtiny2313A/4313 22.5.1 Enhanced Power-On Reset Notes: 1. Values are guidelines, only. 2. Threshold where device is released from reset when voltage is rising. 3. The Power-on Reset will not work unless the supply voltage has been below VPOA. 22.5.2 Brown-Out Detection Note: 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-out Reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed. 22.6 Analog Comparator Characteristics Note: All parameters are based on simulation results and they are not tested in production Table 22-4. Characteristics of Enhanced Power-On Reset. TA = -40 – 85°C Symbol Parameter Min(1) Typ(1) Max(1) Units VPOR Release threshold of power-on reset (2) 1.1 1.4 1.6 V VPOA Activation threshold of power-on reset (3) 0.6 1.3 1.6 V SRON Power-On Slope Rate 0.01 V/ms Table 22-5. VBOT vs. BODLEVEL Fuse Coding BODLEVEL [1:0] Fuses Min(1) Typ(1) Max(1) Units 11 BOD Disabled 10 1.7 1.8 2.0 01 2.5 2.7 2.9 V 00 4.1 4.3 4.5 Table 22-6. Analog Comparator Characteristics, TA = -40°C - 85°C Symbol Parameter Condition Min Typ Max Units VACIO Input Offset Voltage VCC = 5V, VIN = VCC / 2 < 10 40 mV IACLK Input Leakage Current VCC = 5V, VIN = VCC / 2 -50 50 nA tACPD Analog Propagation Delay (from saturation to slight overdrive) VCC = 2.7V 750 ns VCC = 4.0V 500 Analog Propagation Delay (large step change) VCC = 2.7V 100 VCC = 4.0V 75 tDPD Digital Propagation Delay VCC = 1.8V - 5.5 1 2 CLK203 8246B–AVR–09/11 ATtiny2313A/4313 22.7 Parallel Programming Characteristics Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands. 2. tWLRH_CE is valid for the Chip Erase command. Table 22-7. Parallel Programming Characteristics, VCC = 5V ± 10% Symbol Parameter Min Typ Max Units VPP Programming Enable Voltage 11.5 12.5 V I PP Programming Enable Current 250 μA t DVXH Data and Control Valid before XTAL1 High 67 ns tXLXH XTAL1 Low to XTAL1 High 200 ns tXHXL XTAL1 Pulse Width High 150 ns tXLDX Data and Control Hold after XTAL1 Low 67 ns tXLWL XTAL1 Low to WR Low 0 ns tXLPH XTAL1 Low to PAGEL high 0 ns tPLXH PAGEL low to XTAL1 high 150 ns tBVPH BS1 Valid before PAGEL High 67 ns tPHPL PAGEL Pulse Width High 150 ns tPLBX BS1 Hold after PAGEL Low 67 ns tWLBX BS2/1 Hold after WR Low 67 ns tPLWL PAGEL Low to WR Low 67 ns tBVWL BS1 Valid to WR Low 67 ns tWLWH WR Pulse Width Low 150 ns tWLRL WR Low to RDY/BSY Low 0 1 μs t WLRH WR Low to RDY/BSY High(1) 3.7 4.5 ms tWLRH_CE WR Low to RDY/BSY High for Chip Erase(2) 7.5 9 ms tXLOL XTAL1 Low to OE Low 0 ns tBVDV BS1 Valid to DATA valid 0 1000 ns tOLDV OE Low to DATA Valid 1000 ns t OHDZ OE High to DATA Tri-stated 1000 ns204 8246B–AVR–09/11 ATtiny2313A/4313 Figure 22-3. Parallel Programming Timing, Including some General Timing Requirements Figure 22-4. Parallel Programming Timing, Loading Sequence with Timing Requirements(1) Note: 1. The timing requirements shown in Figure 22-3 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation. Figure 22-5. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1) Note: 1. The timing requirements shown in Figure 22-3 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation. Data & Contol (DATA, XA0/1, BS1, BS2) XTAL1 t XHXL t WLWH t DVXH t XLDX t PLWL t WLRH WR RDY/BSY PAGEL t PHPL t PLBX t BVPH t XLWL t WLBX tBVWL WLRL XTAL1 PAGEL t XLXH PLXH t t XLPH DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) BS1 XA0 XA1 LOAD ADDRESS (LOW BYTE) LOAD DATA (LOW BYTE) LOAD DATA (HIGH BYTE) LOAD DATA LOAD ADDRESS (LOW BYTE) XTAL1 OE DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) BS1 XA0 XA1 LOAD ADDRESS (LOW BYTE) READ DATA (LOW BYTE) READ DATA (HIGH BYTE) LOAD ADDRESS (LOW BYTE) t BVDV t OLDV t XLOL t OHDZ205 8246B–AVR–09/11 ATtiny2313A/4313 22.8 Serial Programming Characteristics Figure 22-6. Serial Programming Timing Note: 2 tCLCL for fck < 12 MHz, 3 tCLCL for fck >= 12 MHz Figure 22-7. Serial Programming Waveform Table 22-8. Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 1.8 - 5.5V (Unless Otherwise Noted) Symbol Parameter Min Typ Max Units 1/tCLCL Oscillator Frequency (ATtiny2313A/4313) 0 4 MHz tCLCL Oscillator Period (ATtiny2313A/4313) 250 ns 1/tCLCL Oscillator Frequency (ATtiny2313A/4313, VCC = 4.5V - 5.5V) 0 20 MHz t CLCL Oscillator Period (ATtiny2313A/4313, VCC = 4.5V - 5.5V) 50 ns tSHSL SCK Pulse Width High 2 tCLCL* ns tSLSH SCK Pulse Width Low 2 tCLCL* ns tOVSH MOSI Setup to SCK High tCLCL ns t SHOX MOSI Hold after SCK High 2 tCLCL ns tSLIV SCK Low to MISO Valid 100 ns MOSI MISO SCK t OVSH t SHSL t t SHOX SLSH MSB MSB LSB LSB SERIAL CLOCK INPUT (SCK) SERIAL DATA INPUT (MOSI) (MISO) SAMPLE SERIAL DATA OUTPUT206 8246B–AVR–09/11 ATtiny2313A/4313 23. Typical Characteristics The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indications of how the part will behave. The following charts show typical behavior. These figures are not tested during manufacturing. During characterisation devices are operated at frequencies higher than test limits but they are not guaranteed to function properly at frequencies higher than the ordering code indicates. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. Current consumption is a function of several factors such as operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. A sine wave generator with rail-to-rail output is used as clock source but current consumption in Power-Down mode is independent of clock selection. The difference between current consumption in Power-Down mode with Watchdog Timer enabled and Power-Down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. The current drawn from pins with a capacitive load may be estimated (for one pin) as follows: where VCC = operating voltage, CL = load capacitance and fSW = average switching frequency of I/O pin. 23.1 Effect of Power Reduction Peripheral modules are enabled and disabled via control bits in the Power Reduction Register. See “Power Reduction Register” on page 35 for details. I CP VCC CL × × f SW ≈ Table 23-1. Additional Current Consumption (Absolute) for Peripherals of ATtiny2313A/4313 PRR bit Typical numbers VCC = 2V, f = 1MHz VCC = 3V, f = 4MHz VCC = 5V, f = 8MHz PRTIM0 2 µA 11 µA 50 µA PRTIM1 5 µA 30 µA 120 µA PRUSI 2 µA 11 µA 50 µA PRUSART 4 µA 22 µA 95 µA207 8246B–AVR–09/11 ATtiny2313A/4313 23.2 ATtiny2313A 23.2.1 Current Consumption in Active Mode Figure 23-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) Figure 23-2. Active Supply Current vs. Frequency (1 - 20 MHz) ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY (ATtiny2313A) (PRR=0xFF) 5.5 V 5.0 V 4.5 V 3.3 V 2.7 V 1.8 V 0 0,2 0,4 0,6 0,8 1 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) ICC (mA) ACTIVE SUPPLY CURRENT vs. FREQUENCY (ATtiny2313A) (PRR=0xFF) 0 2 4 6 8 10 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) ICC (mA) 1.8V 2.7V 3.3V 4.5V 5.0V 5.5V208 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) Figure 23-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) ACTIVE SUPPLY CURRENT vs. VCC (ATtiny2313A) INTERNAL RC OSCILLATOR, 8 MHz 85 °C 25 °C -40 °C 0 1 2 3 4 5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (mA) ACTIVE SUPPLY CURRENT vs. VCC (ATtiny2313A) INTERNAL RC OSCILLATOR, 1 MHz 85 °C 25 °C -40 °C 0 0,2 0,4 0,6 0,8 1 1,2 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (mA)209 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-5. Active Supply Current vs. VCC (Internal RC Oscillator, 128 KHz) 23.2.2 Current Consumption in Idle Mode Figure 23-6. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. VCC (ATtiny2313A) INTERNAL RC OSCILLATOR, 128 KHz 85 °C 25 °C -40 °C 0 0,02 0,04 0,06 0,08 0,1 0,12 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (mA) IDLE SUPPLY CURRENT vs. LOW FREQUENCY (ATtiny2313A) (PRR=0xFF) 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0 0,02 0,04 0,06 0,08 0,1 0,12 0,14 0,16 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) ICC (mA)210 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-7. Idle Supply Current vs. Frequency (1 - 20 MHz) Figure 23-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY (ATtiny2313A) (PRR=0xFF) 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0 0,5 1 1,5 2 2,5 3 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) ICC (mA) IDLE SUPPLY CURRENT vs. VCC (ATtiny2313A) INTERNAL RC OSCILLATOR, 8 MHz 85 °C 25 °C -40 °C 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (mA)211 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-9. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) Figure 23-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 KHz) IDLE SUPPLY CURRENT vs. VCC (ATtiny2313A) INTERNAL RC OSCILLATOR, 1 MHz 85 °C 25 °C -40 °C 0 0,05 0,1 0,15 0,2 0,25 0,3 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (mA) IDLE SUPPLY CURRENT vs. VCC (ATtiny2313A) INTERNAL RC OSCILLATOR, 128 KHz 85 °C 25 °C -40 °C 0 0,005 0,01 0,015 0,02 0,025 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (mA)212 8246B–AVR–09/11 ATtiny2313A/4313 23.2.3 Current Consumption in Power-down Mode Figure 23-11. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) Figure 23-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. VCC (ATtiny2313A) WATCHDOG TIMER DISABLED 85 °C 25 °C -40 °C 0 0,1 0,2 0,3 0,4 0,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (uA) POWER-DOWN SUPPLY CURRENT vs. VCC (ATtiny2313A) WATCHDOG TIMER ENABLED 85 °C 25 °C -40 °C 0 1 2 3 4 5 6 7 8 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (uA)213 8246B–AVR–09/11 ATtiny2313A/4313 23.2.4 Current Consumption in Reset Figure 23-13. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up) Figure 23-14. Reset Supply Current vs. VCC (1 - 20 MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs. VCC (ATtiny2313A) EXCLUDING CURRENT THROUGH THE RESET PULLUP 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0 0,02 0,04 0,06 0,08 0,1 0,12 0,14 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) ICC (mA) 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V RESET SUPPLY CURRENT vs. VCC (ATtiny2313A) EXCLUDING CURRENT THROUGH THE RESET PULLUP 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 2,2 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) ICC (mA)214 8246B–AVR–09/11 ATtiny2313A/4313 23.2.5 Current Consumption of Peripheral Units Figure 23-15. Brownout Detector Current vs. VCC Figure 23-16. Programming Current vs. VCC (ATtiny2313A) Note: Above programming current based on simulation and characterisation of similar device (ATtiny24A). BROWNOUT DETECTOR CURRENT vs. VCC (ATtiny2313A) BOD level = 1.8V 85 °C 25 °C -40 °C 0 5 10 15 20 25 30 35 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (uA) PROGRAMMING CURRENT vs. VCC 85 °C 25 °C -40 °C 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (uA)215 8246B–AVR–09/11 ATtiny2313A/4313 23.2.6 Pull-up Resistors Figure 23-17. Pull-up Resistor Current vs. Input Voltage (I/O Pin, VCC = 1.8V) Figure 23-18. Pull-up Resistor Current vs. Input Voltage (I/O Pin, VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE (ATtiny2313A) 0 10 20 30 40 50 60 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VOP (V) IOP (uA) 85 °C 25 °C -40 °C 85 °C 25 °C -40 °C I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE (ATtiny2313A) 0 10 20 30 40 50 60 70 80 90 0 0,5 1 1,5 2 2,5 3 VOP (V) IOP (uA)216 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-19. Pull-up Resistor Current vs. Input Voltage (I/O Pin, VCC = 5V) Figure 23-20. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) 85 °C 25 °C -40 °C I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE (ATtiny2313A) 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 VOP (V) IOP (uA) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE (ATtiny2313A) -40 °C 25 °C 85 °C 0 5 10 15 20 25 30 35 40 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VRESET (V) IRESET (uA)217 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-21. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) Figure 23-22. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) -40 °C 25 °C 85 °C RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE (ATtiny2313A) 0 10 20 30 40 50 60 0 0,5 1 1,5 2 2,5 3 VRESET (V) IRESET (uA) -40 °C 25 °C 85 °C RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE (ATtiny2313A) 0 20 40 60 80 100 120 0 0,5 1 1,5 2 2,5 3 3,5 4 4,5 5 VRESET (V) IRESET (uA)218 8246B–AVR–09/11 ATtiny2313A/4313 23.2.7 Output Driver Strength Figure 23-23. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 1.8V) Figure 23-24. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT (ATtiny2313A) Vcc = 1.8V 85 °C 25 °C -40 °C 0 0,05 0,1 0,15 0,2 0,25 0,3 0,35 0,4 0 0,5 1 1,5 2 2,5 3 3,5 4 4,5 5 IOL (mA) VOL (V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT (ATtiny2313A) Vcc = 3V 85 °C 25 °C -40 °C 0 0,2 0,4 0,6 0 2 4 6 8 10 IOL (mA) VOL (V)219 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-25. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 5V) Figure 23-26. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 1.8V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT (ATtiny2313A) Vcc = 5V 85 °C 25 °C -40 °C 0 0,1 0,2 0,3 0,4 0,5 0,6 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) VOL (V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT (ATtiny2313A) Vcc = 1.8V 85 °C 25 °C -40 °C 1,2 1,3 1,4 1,5 1,6 1,7 1,8 1,9 0 0,5 1 1,5 2 2,5 3 3,5 4 4,5 5 IOH (mA) VOH (V)220 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-27. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 3V) Figure 23-28. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT (ATtiny2313A) Vcc = 3V 85 °C 25 °C -40 °C 2,5 2,6 2,7 2,8 2,9 3 3,1 0 2 4 6 8 10 IOH (mA) VOH (V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT (ATtiny2313A) Vcc = 5V 85 °C 25 °C -40 °C 4,3 4,5 4,7 4,9 5,1 0 5 10 15 20 IOH (mA) VOH (V)221 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-29. VOL: Output Voltage vs. Sink Current (Reset Pin as I/O, T = 25°C) Figure 23-30. VOH: Output Voltage vs. Source Current (Reset Pin as I/O, T = 25°C) RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT (ATtiny2313A) 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 0 1 2 3 4 IOL (mA) VOL (V) 5.0 V 1.8 V 3.0 V RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT (ATtiny2313A) 5.0 V 3.0 V 1.8 V 0 1 2 3 4 5 0 0,2 0,4 0,6 0,8 1 IOH (mA) VOH (V)222 8246B–AVR–09/11 ATtiny2313A/4313 23.2.8 Input Thresholds and Hysteresis (for I/O Ports) Figure 23-31. VIH: Input Threshold Voltage vs. VCC (I/O Pin Read as ‘1’) Figure 23-32. VIL: Input Threshold Voltage vs. VCC (I/O Pin, Read as ‘0’) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC (ATtiny2313A) VIH, IO PIN READ AS '1' 0 0,5 1 1,5 2 2,5 3 3,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Threshold (V) 85 °C 25 °C -40 °C I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC (ATtiny2313A) VIL, IO PIN READ AS '0' 0 0,5 1 1,5 2 2,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Threshold (V) 85 °C 25 °C -40 °C223 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-33. VIH-VIL: Input Hysteresis vs. VCC (I/O Pin) Figure 23-34. VIH: Input Threshold Voltage vs. VCC (Reset Pin as I/O, Read as ‘1’) I/O PIN INPUT HYSTERESIS vs. VCC (ATtiny2313A) 85 °C 25 °C -40 °C 0 0,1 0,2 0,3 0,4 0,5 0,6 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Input Hysteresis (V) RESET PIN AS I/O THRESHOLD VOLTAGE vs. VCC (ATtiny2313A) VIH, RESET READ AS '1' 85 °C 25 °C -40 °C 0 0,5 1 1,5 2 2,5 3 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Threshold (V)224 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-35. VIL: Input Threshold Voltage vs. VCC (Reset Pin as I/O, Read as ‘0’) Figure 23-36. VIH-VIL: Input Hysteresis vs. VCC (Reset Pin as I/O) RESET PIN AS I/O THRESHOLD VOLTAGE vs. VCC (ATtiny2313A) VIL, RESET READ AS '0' 0 0,5 1 1,5 2 2,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Threshold (V) 85 °C 25 °C -40 °C RESET PIN AS IO, INPUT HYSTERESIS vs. VCC (ATtiny2313A) VIL, IO PIN READ AS "0" 85 °C 25 °C -40 °C 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Input Hysteresis (V)225 8246B–AVR–09/11 ATtiny2313A/4313 23.2.9 BOD, Bandgap and Reset Figure 23-37. BOD Thresholds vs. Temperature (BOD Level is 4.3V) Figure 23-38. BOD Thresholds vs. Temperature (BOD Level is 2.7V) BOD THRESHOLDS vs. TEMPERATURE (BOD Level set to 4.3V) (ATtiny2313A) BODLEVEL = 4.3V 4,22 4,24 4,26 4,28 4,3 4,32 4,34 4,36 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (C) Threshold (V) VCC RISING VCC FALLING BOD THRESHOLDS vs. TEMPERATURE (BOD Level set to 2.7V) (ATtiny2313A) BODLEVEL = 2.7V 2,66 2,68 2,7 2,72 2,74 2,76 2,78 -40 -20 0 20 40 60 80 100 Temperature (C) Threshold (V) VCC RISING VCC FALLING226 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-39. BOD Thresholds vs. Temperature (BOD Level is 1.8V) Figure 23-40. Bandgap Voltage vs. Supply Voltage BOD THRESHOLDS vs. TEMPERATURE (BOD Level set to 1.8V) (ATtiny2313A) BODLEVEL = 1.8V 1,78 1,79 1,8 1,81 1,82 1,83 1,84 -40 -20 0 20 40 60 80 100 Temperature (C) Threshold (V) VCC RISING VCC FALLING BANDGAP VOLTAGE vs. VCC (ATtiny2313A) CALIBRATED 0,95 1 1,05 1,1 1,15 1,2 1,5 2 2,5 3 3,5 4 4,5 5 5,5 Vcc (V) Bandgap Voltage (V)227 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-41. Bandgap Voltage vs. Temperature Figure 23-42. VIH: Input Threshold Voltage vs. VCC (Reset Pin, Read as ‘1’) BANDGAP VOLTAGE vs. TEMP (ATtiny2313A) (Vcc=5V) CALIBRATED 1 1,02 1,04 1,06 1,08 1,1 1,12 1,14 1,16 -40 -20 0 20 40 60 80 100 Temperature Bandgap Voltage (V) RESET INPUT THRESHOLD VOLTAGE vs. VCC (ATtiny2313A) VIH, IO PIN READ AS '1' 85 °C 25 °C -40 °C 0 0,5 1 1,5 2 2,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Threshold (V)228 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-43. VIL: Input Threshold Voltage vs. VCC (Reset Pin, Read as ‘0’) Figure 23-44. VIH-VIL: Input Hysteresis vs. VCC (Reset Pin) RESET INPUT THRESHOLD VOLTAGE vs. VCC (ATtiny2313A) VIL, IO PIN READ AS '0' 85 °C 25 °C -40 °C 0 0,5 1 1,5 2 2,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Threshold (V) RESET PIN INPUT HYSTERESIS vs. VCC (ATtiny2313A) 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Input Hysteresis (V) 85 °C 25 °C -40 °C229 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-45. Minimum Reset Pulse Width vs. VCC 23.2.10 Internal Oscillator Speed Figure 23-46. Calibrated 8 MHz RC Oscillator Frequency vs. VCC MINIMUM RESET PULSE WIDTH vs. VCC (ATtiny2313A) 85 °C 25 °C -40 °C 0 200 400 600 800 1000 1200 1400 1600 1800 2000 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Pulsewidth (ns) CALIBRATED 8.0MHz RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE (ATtiny2313A) 7 7,2 7,4 7,6 7,8 8 8,2 8,4 8,6 8,8 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) FRC (MHz) 85 °C 25 °C -40 °C230 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-47. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature Figure 23-48. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 8.0MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE (ATtiny2313A) 5.0 V 3.0 V 1.8 V 7 7,5 8 8,5 9 -40 -20 0 20 40 60 80 100 Temperature FRC (MHz) CALIBRATED 8.0MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE (ATtiny2313A) (Vcc=3V) 85 °C 25 °C -40 °C 0 2 4 6 8 10 12 14 0 16 32 48 64 80 96 112 OSCCAL (X1) FRC (MHz)231 8246B–AVR–09/11 ATtiny2313A/4313 23.3 ATtiny4313 23.3.1 Current Consumption in Active Mode Figure 23-49. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz) Figure 23-50. Active Supply Current vs. Frequency (1 - 20 MHz) ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY (ATtiny4313) (PRR=0xFF) 5.5 V 5.0 V 4.5 V 3.3 V 2.7 V 1.8 V 0 0,2 0,4 0,6 0,8 1 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) ICC (mA) ACTIVE SUPPLY CURRENT vs. FREQUENCY (ATtiny4313) (PRR=0xFF) 0 2 4 6 8 10 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) ICC (mA) 1.8V 2.7V 3.3V 4.5V 5.0V 5.5V232 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-51. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) Figure 23-52. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) ACTIVE SUPPLY CURRENT vs. VCC (ATtiny4313) INTERNAL RC OSCILLATOR, 8 MHz 85 °C 25 °C -40 °C 0 1 2 3 4 5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (mA) ACTIVE SUPPLY CURRENT vs. VCC (ATtiny4313) INTERNAL RC OSCILLATOR, 1 MHz 85 °C 25 °C -40 °C 0 0,2 0,4 0,6 0,8 1 1,2 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (mA)233 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-53. Active Supply Current vs. VCC (Internal RC Oscillator, 128 KHz) 23.3.2 Current Consumption in Idle Mode Figure 23-54. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. VCC (ATtiny4313) INTERNAL RC OSCILLATOR, 128 KHz 85 °C 25 °C -40 °C 0 0,02 0,04 0,06 0,08 0,1 0,12 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (mA) IDLE SUPPLY CURRENT vs. LOW FREQUENCY (ATtiny4313) (PRR=0xFF) 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0 0,02 0,04 0,06 0,08 0,1 0,12 0,14 0,16 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) ICC (mA)234 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-55. Idle Supply Current vs. Frequency (1 - 20 MHz) Figure 23-56. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY (ATtiny4313) (PRR=0xFF) 0 0,5 1 1,5 2 2,5 3 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) ICC (mA) 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V IDLE SUPPLY CURRENT vs. VCC (ATtiny4313) INTERNAL RC OSCILLATOR, 8 MHz 85 °C 25 °C -40 °C 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (mA)235 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-57. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz) Figure 23-58. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 KHz) IDLE SUPPLY CURRENT vs. VCC (ATtiny4313) INTERNAL RC OSCILLATOR, 1 MHz 85 °C 25 °C -40 °C 0 0,1 0,2 0,3 0,4 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (mA) IDLE SUPPLY CURRENT vs. VCC (ATtiny4313) INTERNAL RC OSCILLATOR, 128 KHz 85 °C 25 °C -40 °C 0 0,005 0,01 0,015 0,02 0,025 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (mA)236 8246B–AVR–09/11 ATtiny2313A/4313 23.3.3 Current Consumption in Power-down Mode Figure 23-59. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) Figure 23-60. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. VCC (ATtiny4313) WATCHDOG TIMER DISABLED 85 °C 25 °C -40 °C 0 0,1 0,2 0,3 0,4 0,5 0,6 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (uA) POWER-DOWN SUPPLY CURRENT vs. VCC (ATtiny4313) WATCHDOG TIMER ENABLED 85 °C 25 °C -40 °C 0 1 2 3 4 5 6 7 8 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (uA)237 8246B–AVR–09/11 ATtiny2313A/4313 23.3.4 Current Consumption in Reset Figure 23-61. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up) Figure 23-62. Reset Supply Current vs. VCC (1 - 20 MHz, Excluding Current Through The Reset Pull-up) RESET SUPPLY CURRENT vs. VCC (ATtiny4313) EXCLUDING CURRENT THROUGH THE RESET PULLUP 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V 0 0,02 0,04 0,06 0,08 0,1 0,12 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 Frequency (MHz) ICC (mA) RESET SUPPLY CURRENT vs. VCC (ATtiny4313) EXCLUDING CURRENT THROUGH THE RESET PULLUP 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 2,2 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) ICC (mA) 5.5 V 5.0 V 4.5 V 4.0 V 3.3 V 2.7 V 1.8 V238 8246B–AVR–09/11 ATtiny2313A/4313 23.3.5 Current Consumption of Peripheral Units Figure 23-63. Brownout Detector Current vs. VCC Figure 23-64. Programming Current vs. VCC (ATtiny4313) Note: Above programming current based on simulation and characterisation of similar device (ATtiny44A). BROWNOUT DETECTOR CURRENT vs. VCC (ATtiny4313) BOD level = 1.8V 85 °C 25 °C -40 °C 0 5 10 15 20 25 30 35 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (uA) PROGRAMMING CURRENT vs. VCC 85 °C 25 °C -40 °C 0 2000 4000 6000 8000 10000 12000 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) ICC (uA)239 8246B–AVR–09/11 ATtiny2313A/4313 23.3.6 Pull-up Resistors Figure 23-65. Pull-up Resistor Current vs. Input Voltage (I/O Pin, VCC = 1.8V) Figure 23-66. Pull-up Resistor Current vs. Input Voltage (I/O Pin, VCC = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE (ATtiny4313) 0 10 20 30 40 50 60 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VOP (V) IOP (uA) 85 °C 25 °C -40 °C I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE (ATtiny4313) 0 10 20 30 40 50 60 70 80 0 0,5 1 1,5 2 2,5 3 VOP (V) IOP (uA) 85 °C 25 °C -40 °C240 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-67. Pull-up Resistor Current vs. Input Voltage (I/O Pin, VCC = 5V) Figure 23-68. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE (ATtiny4313) 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 VOP (V) IOP (uA) 85 °C 25 °C -40 °C RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE (ATtiny4313) 0 5 10 15 20 25 30 35 40 0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 VRESET (V) IRESET (uA) 85 °C 25 °C -40 °C241 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-69. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) Figure 23-70. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE (ATtiny4313) 0 10 20 30 40 50 60 0 0,5 1 1,5 2 2,5 3 VRESET (V) IRESET (uA) 85 °C 25 °C -40 °C RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE (ATtiny4313) 0 20 40 60 80 100 120 0 1 2 3 4 5 6 VRESET (V) IRESET (uA)242 8246B–AVR–09/11 ATtiny2313A/4313 23.3.7 Output Driver Strength Figure 23-71. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 1.8V) Figure 23-72. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 3V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT (ATtiny4313) 0 0,05 0,1 0,15 0,2 0,25 0,3 0,35 0,4 0 0,5 1 1,5 2 2,5 3 3,5 4 4,5 5 IOL (mA) VOL (V) VCC = 1.8V 85 °C 25 °C -40 °C I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT (ATtiny4313) 0 0,1 0,2 0,3 0,4 0,5 0,6 0 2 4 6 8 10 IOL (mA) VOL (V) VCC = 3V 85 °C 25 °C -40 °C243 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-73. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 5V) Figure 23-74. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 1.8V) I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT (ATtiny4313) 85 °C 25 °C -40 °C 0 0,1 0,2 0,3 0,4 0,5 0,6 0 2 4 6 8 10 12 14 16 18 20 IOL (mA) VOL (V) VCC = 5V I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT (ATtiny4313) 1 1,2 1,4 1,6 1,8 2 0 0,5 1 1,5 2 2,5 3 3,5 4 4,5 5 IOH (mA) VOH (V) VCC = 1.8V 85 °C 25 °C -40 °C244 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-75. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 3V) Figure 23-76. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 5V) I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT (ATtiny4313) 2,5 2,6 2,7 2,8 2,9 3 3,1 0 2 4 6 8 10 IOH (mA) VOH (V) VCC = 3V 85 °C 25 °C -40 °C I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT (ATtiny4313) 85 °C 25 °C -40 °C 4,3 4,5 4,7 4,9 5,1 0 5 10 15 20 IOH (mA) VOH (V) VCC = 5V245 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-77. VOL: Output Voltage vs. Sink Current (Reset Pin as I/O, T = 25°C) Figure 23-78. VOH: Output Voltage vs. Source Current (Reset Pin as I/O, T = 25°C) RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT (ATtiny4313) 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 0 1 2 3 4 IOL (mA) VOL (V) 5.0 V 1.8 V 3.0 V RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT (ATtiny4313) 0 1 2 3 4 5 0 0,2 0,4 0,6 0,8 1 IOH (mA) VOH (V) 5.0V 3.0V 1.8V246 8246B–AVR–09/11 ATtiny2313A/4313 23.3.8 Input Thresholds and Hysteresis (for I/O Ports) Figure 23-79. VIH: Input Threshold Voltage vs. VCC (I/O Pin Read as ‘1’) Figure 23-80. VIL: Input Threshold Voltage vs. VCC (I/O Pin, Read as ‘0’) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC (ATtiny4313) VIH, IO PIN READ AS '1' 85 °C 25 °C -40 °C 0 0,5 1 1,5 2 2,5 3 3,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Threshold (V) I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC (ATtiny4313) VIL, IO PIN READ AS '0' 85 °C 25 °C -40 °C 0 0,5 1 1,5 2 2,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Threshold (V)247 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-81. VIH-VIL: Input Hysteresis vs. VCC (I/O Pin) Figure 23-82. VIH: Input Threshold Voltage vs. VCC (Reset Pin as I/O, Read as ‘1’) I/O PIN INPUT HYSTERESIS vs. VCC (ATtiny4313) 85 °C 25 °C -40 °C 0 0,1 0,2 0,3 0,4 0,5 0,6 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Input Hysteresis (V) RESET PIN AS I/O THRESHOLD VOLTAGE vs. VCC (ATtiny4313) VIH, RESET READ AS '1' 85 °C 25 °C -40 °C 0 0,5 1 1,5 2 2,5 3 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Threshold (V)248 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-83. VIL: Input Threshold Voltage vs. VCC (Reset Pin as I/O, Read as ‘0’) Figure 23-84. VIH-VIL: Input Hysteresis vs. VCC (Reset Pin as I/O) RESET PIN AS I/O THRESHOLD VOLTAGE vs. VCC (ATtiny4313) VIL, RESET READ AS '0' 85 °C 25 °C -40 °C 0 0,5 1 1,5 2 2,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Threshold (V) RESET PIN AS IO, INPUT HYSTERESIS vs. VCC (ATtiny4313) VIL, IO PIN READ AS "0" 85 °C 25 °C -40 °C 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Input Hysteresis (V)249 8246B–AVR–09/11 ATtiny2313A/4313 23.3.9 BOD, Bandgap and Reset Figure 23-85. BOD Thresholds vs. Temperature (BOD Level is 4.3V) Figure 23-86. BOD Thresholds vs. Temperature (BOD Level is 2.7V) BOD THRESHOLDS vs. TEMPERATURE (BOD Level set to 4.3V) (ATtiny4313) BOD Level = 4.3V 4,16 4,18 4,2 4,22 4,24 4,26 4,28 4,3 4,32 4,34 4,36 4,38 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (C) Threshold (V) VCC RISING VCC FALLING BOD THRESHOLDS vs. TEMPERATURE (BOD Level set to 2.7V) (ATtiny4313) BOD Level = 2.7V 2,62 2,64 2,66 2,68 2,7 2,72 2,74 2,76 2,78 -40 -20 0 20 40 60 80 100 Temperature (C) Threshold (V) VCC RISING VCC FALLING250 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-87. BOD Thresholds vs. Temperature (BOD Level is 1.8V) Figure 23-88. Bandgap Voltage vs. Supply Voltage 1,76 1,77 1,78 1,79 1,8 1,81 1,82 1,83 1,84 -40 -20 0 20 40 60 80 100 Temperature (C) Threshold (V) BOD THRESHOLDS vs. TEMPERATURE (BOD Level set to 1.8V) (ATtiny4313) BOD Level = 1.8V VCC RISING VCC FALLING BANDGAP VOLTAGE vs. VCC (ATtiny4313) CALIBRATED 0,95 1 1,05 1,1 1,15 1,2 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Bandgap Voltage (V)251 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-89. Bandgap Voltage vs. Temperature Figure 23-90. VIH: Input Threshold Voltage vs. VCC (Reset Pin, Read as ‘1’) BANDGAP VOLTAGE vs. TEMP (ATtiny4313) (Vcc=5V) CALIBRATED 1 1,02 1,04 1,06 1,08 1,1 1,12 1,14 -40 -20 0 20 40 60 80 100 Temperature Bandgap Voltage (V) RESET INPUT THRESHOLD VOLTAGE vs. VCC (ATtiny4313) VIH, IO PIN READ AS '1' 85 °C 25 °C -40 °C 0 0,5 1 1,5 2 2,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Threshold (V)252 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-91. VIL: Input Threshold Voltage vs. VCC (Reset Pin, Read as ‘0’) Figure 23-92. VIH-VIL: Input Hysteresis vs. VCC (Reset Pin) RESET INPUT THRESHOLD VOLTAGE vs. VCC (ATtiny4313) VIL, IO PIN READ AS '0' 85 °C 25 °C -40 °C 0 0,5 1 1,5 2 2,5 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Threshold (V) RESET PIN INPUT HYSTERESIS vs. VCC (ATtiny4313) 85 °C 25 °C -40 °C 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Input Hysteresis (V)253 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-93. Minimum Reset Pulse Width vs. VCC 23.3.10 Internal Oscillator Speed Figure 23-94. Calibrated 8 MHz RC Oscillator Frequency vs. VCC MINIMUM RESET PULSE WIDTH vs. VCC (ATtiny4313) 85 °C 25 °C -40 °C 0 200 400 600 800 1000 1200 1400 1600 1800 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) Pulsewidth (ns) CALIBRATED 8.0MHz RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE (ATtiny4313) 7,2 7,4 7,6 7,8 8 8,2 8,4 8,6 1,5 2 2,5 3 3,5 4 4,5 5 5,5 VCC (V) FRC (MHz) 85 °C 25 °C -40 °C254 8246B–AVR–09/11 ATtiny2313A/4313 Figure 23-95. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature Figure 23-96. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value CALIBRATED 8.0MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE (ATtiny4313) 5.0 V 3.0 V 1.8 V 7,4 7,6 7,8 8 8,2 8,4 8,6 -40 -20 0 20 40 60 80 100 Temperature FRC (MHz) CALIBRATED 8.0MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE (ATtiny4313) (Vcc=3V) 85 °C 25 °C -40 °C 0 2 4 6 8 10 12 14 0 16 32 48 64 80 96 112 OSCCAL (X1) FRC (MHz)255 8246B–AVR–09/11 ATtiny2313A/4313 24. Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x3F (0x5F) SREG I T H S V N Z C 9 0x3E (0x5E) Reserved – – – – – – – – 0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 12 0x3C (0x5C) OCR0B Timer/Counter0 – Compare Register B 86 0x3B (0x5B) GIMSK INT1 INT0 PCIE0 PCIE2 PCIE1 – – – 52 0x3A (0x5A) GIFR INTF1 INTF0 PCIF0 PCIF2 PCIF1 – – – 53 0x39 (0x59) TIMSK TOIE1 OCIE1A OCIE1B – ICIE1 OCIE0B TOIE0 OCIE0A 87, 116 0x38 (0x58) TIFR TOV1 OCF1A OCF1B – ICF1 OCF0B TOV0 OCF0A 87, 117 0x37 (0x57) SPMCSR – – RSIG CTPB RFLB PGWRT PGERS SPMEN 176 0x36 (0x56) OCR0A Timer/Counter0 – Compare Register A 86 0x35 (0x55) MCUCR PUD SM1 SE SM0 ISC11 ISC10 ISC01 ISC00 37, 51, 69 0x34 (0x54) MCUSR – – – – WDRF BORF EXTRF PORF 45 0x33 (0x53) TCCR0B FOC0A FOC0B – – WGM02 CS02 CS01 CS00 85 0x32 (0x52) TCNT0 Timer/Counter0 (8-bit) 86 0x31 (0x51) OSCCAL – CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 32 0x30 (0x50) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 82 0x2F (0x4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 111 0x2E (0x4E) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 113 0x2D (0x4D) TCNT1H Timer/Counter1 – Counter Register High Byte 115 0x2C (0x4C) TCNT1L Timer/Counter1 – Counter Register Low Byte 115 0x2B (0x4B) OCR1AH Timer/Counter1 – Compare Register A High Byte 115 0x2A (0x4A) OCR1AL Timer/Counter1 – Compare Register A Low Byte 115 0x29 (0x49) OCR1BH Timer/Counter1 – Compare Register B High Byte 115 0x28 (0x48) OCR1BL Timer/Counter1 – Compare Register B Low Byte 115 0x27 (0x47) Reserved – – – – – – – – 0x26 (0x46) CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 32 0x25 (0x45) ICR1H Timer/Counter1 - Input Capture Register High Byte 116 0x24 (0x44) ICR1L Timer/Counter1 - Input Capture Register Low Byte 116 0x23 (0x43) GTCCR – – – – – – – PSR10 119 0x22 (ox42) TCCR1C FOC1A FOC1B – – – – – – 114 0x21 (0x41) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 45 0x20 (0x40) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 54 0x1F (0x3F) Reserved – – – – – – – – 0x1E (0x3E) EEAR – EEPROM Address Register 24 0x1D (0x3D) EEDR EEPROM Data Register 23 0x1C (0x3C) EECR – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE 24 0x1B (0x3B) PORTA – – – – – PORTA2 PORTA1 PORTA0 69 0x1A (0x3A) DDRA – – – – – DDA2 DDA1 DDA0 69 0x19 (0x39) PINA – – – – – PINA2 PINA1 PINA0 70 0x18 (0x38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 70 0x17 (0x37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 70 0x16 (0x36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 70 0x15 (0x35) GPIOR2 General Purpose I/O Register 2 25 0x14 (0x34) GPIOR1 General Purpose I/O Register 1 25 0x13 (0x33) GPIOR0 General Purpose I/O Register 0 25 0x12 (0x32) PORTD – PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 70 0x11 (0x31) DDRD – DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 70 0x10 (0x30) PIND – PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 70 0x0F (0x2F) USIDR USI Data Register 166 0x0E (0x2E) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 165 0x0D (0x2D) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC 163 0x0C (0x2C) UDR UART Data Register (8-bit) 137 0x0B (0x2B) UCSRA RXC TXC UDRE FE DOR UPE U2X MPCM 138 0x0A (0x2A) UCSRB RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 139 0x09 (0x29) UBRRL UBRRH[7:0] 141 0x08 (0x28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 168 0x07 (0x27) BODCR – – – – – – BODS BODSE 38 0x06 (0x26) PRR – – – – PRTIM1 PRTIM0 PRUSI PRUSART 37 0x05 (0x25) PCMSK2 – PCINT17 PCINT16 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 53 0x04 (0x24) PCMSK1 – – – – – PCINT10 PCINT9 PCINT8 54 0x03 (0x23) UCSRC UMSEL1 UMSEL0 UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL 140 0x02 (0x22) UBRRH – – – – UBRRH[11:8] 141 0x01 (0x21) DIDR – – – – – – AIN1D AIN0D 169 0x00 (0x20) USIBR USI Buffer Register 167256 8246B–AVR–09/11 ATtiny2313A/4313 Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. 257 8246B–AVR–09/11 ATtiny2313A/4313 25. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1 COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1 NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1 INC Rd Increment Rd ← Rd + 1 Z,N,V 1 DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1 SER Rd Set Register Rd ← 0xFF None 1 BRANCH INSTRUCTIONS RJMP k Relative Jump PC ← PC + k + 1 None 2 IJMP Indirect Jump to (Z) PC ← Z None 2 RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3 ICALL Indirect Call to (Z) PC ← Z None 3 RET Subroutine Return PC ← STACK None 4 RETI Interrupt Return PC ← STACK I 4 CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3 CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1258 8246B–AVR–09/11 ATtiny2313A/4313 ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1 BSET s Flag Set SREG(s) ← 1 SREG(s) 1 BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) ← T None 1 SEC Set Carry C ← 1 C1 CLC Clear Carry C ← 0 C 1 SEN Set Negative Flag N ← 1 N1 CLN Clear Negative Flag N ← 0 N 1 SEZ Set Zero Flag Z ← 1 Z1 CLZ Clear Zero Flag Z ← 0 Z 1 SEI Global Interrupt Enable I ← 1 I1 CLI Global Interrupt Disable I ← 0 I 1 SES Set Signed Test Flag S ← 1 S1 CLS Clear Signed Test Flag S ← 0 S 1 SEV Set Twos Complement Overflow. V ← 1 V1 CLV Clear Twos Complement Overflow V ← 0 V 1 SET Set T in SREG T ← 1 T1 CLT Clear T in SREG T ← 0 T 1 SEH Set Half Carry Flag in SREG H ← 1 H1 CLH Clear Half Carry Flag in SREG H ← 0 H 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers Rd ← Rr None 1 MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1 LDI Rd, K Load Immediate Rd ← K None 1 LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2 LD Rd, Y Load Indirect Rd ← (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd ← (k) None 2 ST X, Rr Store Indirect (X) ← Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2 ST Y, Rr Store Indirect (Y) ← Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2 ST Z, Rr Store Indirect (Z) ← Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2 STS k, Rr Store Direct to SRAM (k) ← Rr None 2 LPM Load Program Memory R0 ← (Z) None 3 LPM Rd, Z Load Program Memory Rd ← (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3 SPM Store Program Memory (Z) ← R1:R0 None - IN Rd, P In Port Rd ← P None 1 OUT P, Rr Out Port P ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/timer) None 1 BREAK Break For On-chip Debug Only None N/A Mnemonics Operands Description Operation Flags #Clocks259 8246B–AVR–09/11 ATtiny2313A/4313 26. Ordering Information Notes: 1. For speed vs. supply voltage, see section 22.3 “Speed” on page 200. 2. All packages are Pb-free, halide-free and fully green, and they comply with the European directive for Restriction of Hazardous Substances (RoHS). 3. Code indicators: – H: NiPdAu lead finish – U or N: matte tin – R: tape & reel 4. Can also be supplied in wafer form. Contact your local Atmel sales office for ordering information and minimum quantities. 5. NiPdAu finish 6. Topside markings : – 1st Line: T2313 – 2nd Line: Axx – 3rd Line: xxx 26.1 ATtiny2313A Speed (MHz) (1) Supply Voltage (V) Temperature Range Package (2) Ordering Code (3) 20 1.8 – 5.5 Industrial (-40°C to +85°C) (4) 20P3 ATtiny2313A-PU 20S ATtiny2313A-SU ATtiny2313A-SUR 20M1 ATtiny2313A-MU ATtiny2313A-MUR 20M2 (5)(6) ATtiny2313A-MMH ATtiny2313A-MMHR Package Type 20P3 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20S 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC) 20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead / Micro Lead Frame Package (MLF) 20M2 20-pad, 3 x 3 x 0.85 mm Body, Very Thin Quad Flat No Lead Package (VQFN)260 8246B–AVR–09/11 ATtiny2313A/4313 Notes: 1. For speed vs. supply voltage, see section 22.3 “Speed” on page 200. 2. All packages are Pb-free, halide-free and fully green, and they comply with the European directive for Restriction of Hazardous Substances (RoHS). 3. Code indicators: – H: NiPdAu lead finish – U or N: matte tin – R: tape & reel 4. Can also be supplied in wafer form. Contact your local Atmel sales office for ordering information and minimum quantities. 5. NiPdAu finish 6. Topside markings: – 1st Line: T4313 – 2nd Line: Axx – 3rd Line: xxx 26.2 ATtiny4313 Speed (MHz) (1) Supply Voltage (V) Temperature Range Package (2) Ordering Code (3) 20 1.8 – 5.5 Industrial (-40°C to +85°C) (4) 20P3 ATtiny4313-PU 20S ATtiny4313-SU ATtiny4313-SUR 20M1 ATtiny4313-MU ATtiny4313-MUR 20M2 (5)(6) ATtiny4313-MMH ATtiny4313-MMHR Package Type 20P3 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20S 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC) 20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (MLF) 20M2 20-pad, 3 x 3 x 0.85 mm Body, Very Thin Quad Flat No Lead Package (VQFN)261 8246B–AVR–09/11 ATtiny2313A/4313 27. Packaging Information 27.1 20P3 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) 20P3 D 2010-10-19 PIN 1 E1 A1 B E B1 C L SEATING PLANE A D e eB eC COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 5.334 A1 0.381 – – D 25.493 – 25.984 Note 2 E 7.620 – 8.255 E1 6.096 – 7.112 Note 2 B 0.356 – 0.559 B1 1.270 – 1.551 L 2.921 – 3.810 C 0.203 – 0.356 eB – – 10.922 eC 0.000 – 1.524 e 2.540 TYP Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 262 8246B–AVR–09/11 ATtiny2313A/4313 27.2 20S263 8246B–AVR–09/11 ATtiny2313A/4313 27.3 20M1 2325 Orchard Parkway San Jose, CA 95131 TITLE DRAWING NO. R REV. 20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, 20M1 A 10/27/04 2.6 mm Exposed Pad, Micro Lead Frame Package (MLF) A 0.70 0.75 0.80 A1 – 0.01 0.05 A2 0.20 REF b 0.18 0.23 0.30 D 4.00 BSC D2 2.45 2.60 2.75 E 4.00 BSC E2 2.45 2.60 2.75 e 0.50 BSC L 0.35 0.40 0.55 SIDE VIEW Pin 1 ID Pin #1 Notch (0.20 R) BOTTOM VIEW TOP VIEW Note: Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D E e A2 A1 A D2 E2 0.08 C L 1 2 3 b 1 2 3264 8246B–AVR–09/11 ATtiny2313A/4313 27.4 20M2 TITLE GPC DRAWING NO. REV. Package Drawing Contact: packagedrawings@atmel.com ZFC B 20M2 20M2, 20-pad, 3 x 3 x 0.85 mm Body, Lead Pitch 0.45 mm, 1.55 x 1.55 mm Exposed Pad, Thermally Enhanced Plastic Very Thin Quad Flat No Lead Package (VQFN) 10/24/08 15 14 13 12 11 1 2 3 4 5 16 17 18 19 20 10 9 8 7 6 D2 E2 e b L K Pin #1 Chamfer (C 0.3) D E SIDE VIEW A1 y Pin 1 ID BOTTOM VIEW TOP VIEW A C C0.18 (8X) 0.3 Ref (4x) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 0.75 0.80 0.85 A1 0.00 0.02 0.05 b 0.17 0.22 0.27 C 0.152 D 2.90 3.00 3.10 D2 1.40 1.55 1.70 E 2.90 3.00 3.10 E2 1.40 1.55 1.70 e – 0.45 – L 0.35 0.40 0.45 K 0.20 – – y 0.00 – 0.08 265 8246B–AVR–09/11 ATtiny2313A/4313 28. Errata The revision letters in this section refer to the revision of the corresponding ATtiny2313A/4313 device. 28.1 ATtiny2313A 28.1.1 Rev. D No known errata. 28.1.2 Rev. A – C These device revisions were referred to as ATtiny2313/ATtiny2313V. 28.2 ATtiny4313 28.2.1 Rev. A No known errata.266 8246B–AVR–09/11 ATtiny2313A/4313 29. Datasheet Revision History 29.1 Rev. 8246B – 10/11 1. Updated device status from Preliminary to Final. 2. Updated document template. 3. Added order codes for tape&reel devices, on page 259 and page 260 4. Updated figures: – Figure 23-33 on page 223 – Figure 23-44 on page 228 – Figure 23-81 on page 247 – Figure 23-92 on page 252 5. Updated sections: – Section 5. “Memories” on page 16 – Section 19. “Self-Programming” on page 173 – Section 20. “Lock Bits, Fuse Bits and Device Signature” on page 178 – Section 21. “External Programming” on page 184 – Section 26. “Ordering Information” on page 259 29.2 Rev. 8246A – 11/09 1. Initial revision. Created from document 2543_t2313. 2. Updated datasheet template. 3. Added VQFN in the Pinout Figure 1-1 on page 2. 4. Added Section 7.2 “Software BOD Disable” on page 35. 5. Added Section 7.3 “Power Reduction Register” on page 35. 6. Updated Table 7-2, “Sleep Mode Select,” on page 37. 7. Added Section 7.5.3 “BODCR – Brown-Out Detector Control Register” on page 38. 8. Added reset disable function in Figure 8-1 on page 39. 9. Added pin change interrupts PCINT1 and PCINT2 in Table 9-1 on page 48. 10. Added PCINT17..8 and PCMSK2..1 in Section 9.2 “External Interrupts” on page 49. 11. Added Section 9.3.4 “PCMSK2 – Pin Change Mask Register 2” on page 53. 12. Added Section 9.3.5 “PCMSK1 – Pin Change Mask Register 1” on page 54. 13. Updated Section 10.2.1 “Alternate Functions of Port A” on page 62. 14. Updated Section 10.2.2 “Alternate Functions of Port B” on page 63. 15. Updated Section 10.2.3 “Alternate Functions of Port D” on page 67. 16. Added UMSEL1 and UMSEL0 in Section 14.10.4 “UCSRC – USART Control and Status Register C” on page 140. 17. Added Section 15. “USART in SPI Mode” on page 146. 18. Added USI Buffer Register (USIBR) in Section 16.2 “Overview” on page 156 and in Figure 16-1 on page 156. 19. Added Section 16.5.4 “USIBR – USI Buffer Register” on page 167. 20. Updated Section 19.6.3 “Reading Device Signature Imprint Table from Firmware” on page 175.267 8246B–AVR–09/11 ATtiny2313A/4313 21. Updated Section 19.7.1 “SPMCSR – Store Program Memory Control and Status Register” on page 176. 22. Added Section 20.3 “Device Signature Imprint Table” on page 180. 23. Updated Section 20.3.1 “Calibration Byte” on page 181. 24. Changed BS to BS1 in Section 20.6.13 “Reading the Signature Bytes” on page 189. 25. Updated Section 22.2 “DC Characteristics” on page 198. 26. Added Section 23.1 “Effect of Power Reduction” on page 206. 27. Updated characteristic plots in Section 23. “Typical Characteristics” for ATtiny2313A (pages 207 - 230), and added plots for ATtiny4313 (pages 231 - 254). 28. Updated Section 24. “Register Summary” on page 255 . 29. Updated Section 26. “Ordering Information” on page 259, added the package type 20M2 and the ordering code -MMH (VQFN), and added the topside marking note.268 8246B–AVR–09/11 ATtiny2313A/4313i 8246B–AVR–09/11 ATtiny2313A/4313 Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 1.1 Pin Descriptions .................................................................................................3 2 Overview ................................................................................................... 5 2.1 Block Diagram ...................................................................................................5 2.2 Comparison Between ATtiny2313A and ATtiny4313 ........................................6 3 About ......................................................................................................... 7 3.1 Resources .........................................................................................................7 3.2 Code Examples .................................................................................................7 3.3 Data Retention ...................................................................................................7 4 CPU Core .................................................................................................. 8 4.1 Architectural Overview .......................................................................................8 4.2 ALU – Arithmetic Logic Unit ...............................................................................9 4.3 Status Register ..................................................................................................9 4.4 General Purpose Register File ........................................................................10 4.5 Stack Pointer ...................................................................................................12 4.6 Instruction Execution Timing ...........................................................................12 4.7 Reset and Interrupt Handling ...........................................................................13 5 Memories ................................................................................................ 15 5.1 Program Memory (Flash) .................................................................................15 5.2 Data Memory (SRAM) and Register Files .......................................................16 5.3 Data Memory (EEPROM) ................................................................................17 5.4 Register Description ........................................................................................22 6 Clock System ......................................................................................... 25 6.1 Clock Subsystems ...........................................................................................25 6.2 Clock Sources .................................................................................................26 6.3 System Clock Prescaler ..................................................................................30 6.4 Clock Output Buffer .........................................................................................31 6.5 Register Description ........................................................................................31 7 Power Management and Sleep Modes ................................................. 33 7.1 Sleep Modes ....................................................................................................33 7.2 Software BOD Disable .....................................................................................34ii 8246B–AVR–09/11 ATtiny2313A/4313 7.3 Power Reduction Register ...............................................................................34 7.4 Minimizing Power Consumption ......................................................................35 7.5 Register Description ........................................................................................36 8 System Control and Reset .................................................................... 38 8.1 Resetting the AVR ...........................................................................................38 8.2 Reset Sources .................................................................................................39 8.3 Internal Voltage Reference ..............................................................................41 8.4 Watchdog Timer ..............................................................................................41 8.5 Register Description ........................................................................................44 9 Interrupts ................................................................................................ 47 9.1 Interrupt Vectors ..............................................................................................47 9.2 External Interrupts ...........................................................................................48 9.3 Register Description ........................................................................................50 10 I/O-Ports .................................................................................................. 54 10.1 Ports as General Digital I/O .............................................................................55 10.2 Alternate Port Functions ..................................................................................59 10.3 Register Description ........................................................................................68 11 8-bit Timer/Counter0 with PWM ............................................................ 70 11.1 Features ..........................................................................................................70 11.2 Overview ..........................................................................................................70 11.3 Clock Sources .................................................................................................71 11.4 Counter Unit ....................................................................................................71 11.5 Output Compare Unit .......................................................................................72 11.6 Compare Match Output Unit ............................................................................74 11.7 Modes of Operation .........................................................................................75 11.8 Timer/Counter Timing Diagrams .....................................................................79 11.9 Register Description ........................................................................................81 12 16-bit Timer/Counter1 ............................................................................ 88 12.1 Features ..........................................................................................................88 12.2 Overview ..........................................................................................................88 12.3 Timer/Counter Clock Sources .........................................................................90 12.4 Counter Unit ....................................................................................................90 12.5 Input Capture Unit ...........................................................................................91 12.6 Output Compare Units .....................................................................................93iii 8246B–AVR–09/11 ATtiny2313A/4313 12.7 Compare Match Output Unit ............................................................................95 12.8 Modes of Operation .........................................................................................96 12.9 Timer/Counter Timing Diagrams ...................................................................104 12.10 Accessing 16-bit Registers ............................................................................106 12.11 Register Description ......................................................................................110 13 Timer/Counter0 and Timer/Counter1 Prescalers .............................. 117 13.1 Internal Clock Source ....................................................................................117 13.2 Prescaler Reset .............................................................................................117 13.3 External Clock Source ...................................................................................117 13.4 Register Description ......................................................................................118 14 USART ................................................................................................... 119 14.1 Features ........................................................................................................119 14.2 Overview ........................................................................................................119 14.3 Clock Generation ...........................................................................................120 14.4 Frame Formats ..............................................................................................123 14.5 USART Initialization .......................................................................................124 14.6 Data Transmission – The USART Transmitter ..............................................125 14.7 Data Reception – The USART Receiver .......................................................129 14.8 Asynchronous Data Reception ......................................................................132 14.9 Multi-processor Communication Mode ..........................................................135 14.10 Register Description ......................................................................................136 14.11 Examples of Baud Rate Setting .....................................................................141 15 USART in SPI Mode ............................................................................. 145 15.1 Features ........................................................................................................145 15.2 Overview ........................................................................................................145 15.3 Clock Generation ...........................................................................................145 15.4 SPI Data Modes and Timing ..........................................................................146 15.5 Frame Formats ..............................................................................................147 15.6 Data Transfer .................................................................................................149 15.7 AVR USART MSPIM vs. AVR SPI ................................................................151 15.8 Register Description ......................................................................................152 16 USI – Universal Serial Interface .......................................................... 155 16.1 Features ........................................................................................................155 16.2 Overview ........................................................................................................155 16.3 Functional Descriptions .................................................................................156iv 8246B–AVR–09/11 ATtiny2313A/4313 16.4 Alternative USI Usage ...................................................................................162 16.5 Register Description ......................................................................................162 17 Analog Comparator ............................................................................. 167 17.1 Register Description ......................................................................................167 18 debugWIRE On-chip Debug System .................................................. 169 18.1 Features ........................................................................................................169 18.2 Overview ........................................................................................................169 18.3 Physical Interface ..........................................................................................169 18.4 Software Break Points ...................................................................................170 18.5 Limitations of debugWIRE .............................................................................170 18.6 Register Description ......................................................................................171 19 Self-Programming ................................................................................ 172 19.1 Features ........................................................................................................172 19.2 Overview ........................................................................................................172 19.3 Lock Bits ........................................................................................................172 19.4 Self-Programming the Flash ..........................................................................172 19.5 Preventing Flash Corruption ..........................................................................175 19.6 Programming Time for Flash when Using SPM ............................................175 19.7 Register Description ......................................................................................175 20 Lock Bits, Fuse Bits and Device Signature ....................................... 177 20.1 Lock Bits ........................................................................................................177 20.2 Fuse Bits ........................................................................................................178 20.3 Device Signature Imprint Table .....................................................................179 20.4 Reading Lock Bits, Fuse Bits and Signature Data from Software .................180 21 External Programming ........................................................................ 183 21.1 Memory Parametrics .....................................................................................183 21.2 Parallel Programming ....................................................................................183 21.3 Serial Programming .......................................................................................192 21.4 Programming Time for Flash and EEPROM .................................................196 22 Electrical Characteristics .................................................................... 198 22.1 Absolute Maximum Ratings* .........................................................................198 22.2 DC Characteristics .........................................................................................198 22.3 Speed ............................................................................................................199 22.4 Clock Characteristics .....................................................................................200v 8246B–AVR–09/11 ATtiny2313A/4313 22.5 System and Reset Characteristics ................................................................201 22.6 Analog Comparator Characteristics ...............................................................202 22.7 Parallel Programming Characteristics ...........................................................203 22.8 Serial Programming Characteristics ..............................................................205 23 Typical Characteristics ........................................................................ 206 23.1 Effect of Power Reduction .............................................................................206 23.2 ATtiny2313A ..................................................................................................207 23.3 ATtiny4313 ....................................................................................................231 24 Register Summary ............................................................................... 255 25 Instruction Set Summary .................................................................... 257 26 Ordering Information ........................................................................... 259 26.1 ATtiny2313A ..................................................................................................259 26.2 ATtiny4313 ....................................................................................................260 27 Packaging Information ........................................................................ 261 27.1 20P3 ..............................................................................................................261 27.2 20S ................................................................................................................262 27.3 20M1 ..............................................................................................................263 27.4 20M2 ..............................................................................................................264 28 Errata ..................................................................................................... 265 28.1 ATtiny2313A ..................................................................................................265 28.2 ATtiny4313 ....................................................................................................265 29 Datasheet Revision History ................................................................ 266 29.1 Rev. 8246B – 10/11 .......................................................................................266 29.2 Rev. 8246A – 11/09 .......................................................................................2668246B–AVR–09/11 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Limited Unit 01-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 JAPAN Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support avr@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. 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Features • High Performance, Low Power AVR® 8-bit Microcontroller • Advanced RISC Architecture – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation • High Endurance, Non-volatile Memory Segments – 2K/4K/8K Bytes of In-System, Self-programmable Flash Program Memory • Endurance: 10,000 Write/Erase Cycles – 128/256/512 Bytes of In-System Programmable EEPROM • Endurance: 100,000 Write/Erase Cycles – 128/256/512 Bytes of Internal SRAM – Data Retention: 20 years at 85°C / 100 years at 25°C – Programming Lock for Self-programming Flash & EEPROM Data Security • Peripheral Features – One 8-bit and One 16-bit Timer/Counter with Two PWM Channels, Each – 10-bit ADC • 8 Single-ended Channels • 12 Differential ADC Channel Pairs with Programmable Gain (1x / 20x) – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Universal Serial Interface • Special Microcontroller Features – debugWIRE On-chip Debug System – In-System Programmable via SPI Port – Internal and External Interrupt Sources • Pin Change Interrupt on 12 Pins – Low Power Idle, ADC Noise Reduction, Standby and Power-down Modes – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit with Software Disable Function – Internal Calibrated Oscillator – On-chip Temperature Sensor • I/O and Packages – Available in 20-pin QFN/MLF/VQFN, 14-pin SOIC, 14-pin PDIP and 15-ball UFBGA – Twelve Programmable I/O Lines • Operating Voltage: – 1.8 – 5.5V • Speed Grade: – 0 – 4 MHz @ 1.8 – 5.5V – 0 – 10 MHz @ 2.7 – 5.5V – 0 – 20 MHz @ 4.5 – 5.5V • Industrial Temperature Range: -40°C to +85°C • Low Power Consumption – Active Mode: • 210 µA at 1.8V and 1 MHz – Idle Mode: • 33 µA at 1.8V and 1 MHz – Power-down Mode: • 0.1 µA at 1.8V and 25°C 8-bit Microcontroller with 2K/4K/8K Bytes In-System Programmable Flash ATtiny24A ATtiny44A ATtiny84A Rev. 8183F–AVR–06/122 8183F–AVR–06/12 ATtiny24A/44A/84A 1. Pin Configurations Figure 1-1. Pinout of ATtiny24A/44A/84A Table 1-1. UFBGA - Pinout ATtiny24A/44A/84A (top view) 1234 A PA5 PA6 PB2 B PA4 PA7 PB1 PB3 C PA3 PA2 PA1 PB0 D PA0 GND GND VCC 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC (PCINT8/XTAL1/CLKI) PB0 (PCINT9/XTAL2) PB1 (PCINT11/RESET/dW) PB3 (PCINT10/INT0/OC0A/CKOUT) PB2 (PCINT7/ICP/OC0B/ADC7) PA7 (PCINT6/OC1A/SDA/MOSI/DI/ADC6) PA6 GND PA0 (ADC0/AREF/PCINT0) PA1 (ADC1/AIN0/PCINT1) PA2 (ADC2/AIN1/PCINT2) PA3 (ADC3/T0/PCINT3) PA4 (ADC4/USCK/SCL/T1/PCINT4) PA5 (ADC5/DO/MISO/OC1B/PCINT5) PDIP/SOIC 1 2 3 4 5 QFN/MLF/VQFN 15 14 13 12 11 20 19 18 17 16 6 7 8 9 10 NOTE Bottom pad should be soldered to ground. DNC: Do Not Connect DNC DNC GND VCC DNC PA7 (PCINT7/ICP/OC0B/ADC7) PB2 (PCINT10/INT0/OC0A/CKOUT) PB3 (PCINT11/RESET/dW) PB1 (PCINT9/XTAL2) PB0 (PCINT8/XTAL1/CLKI) PA5 DNC DNC DNC PA6 Pin 16: PA6 (PCINT6/OC1A/SDA/MOSI/DI/ADC6) Pin 20: PA5 (ADC5/DO/MISO/OC1B/PCINT5) (ADC4/USCK/SCL/T1/PCINT4) PA4 (ADC3/T0/PCINT3) PA3 (ADC2/AIN1/PCINT2) PA2 (ADC1/AIN0/PCINT1) PA1 (ADC0/AREF/PCINT0) PA03 8183F–AVR–06/12 ATtiny24A/44A/84A 1.1 Pin Descriptions 1.1.1 VCC Supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB3:PB0) Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability except PB3 which has the RESET capability. To use pin PB3 as an I/O pin, instead of RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny24A/44A/84A as listed in Section 10.2 “Alternate Port Functions” on page 58. 1.1.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 20-4 on page 176. Shorter pulses are not guaranteed to generate a reset. The reset pin can also be used as a (weak) I/O pin. 1.1.5 Port A (PA7:PA0) Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A has alternate functions as analog inputs for the ADC, analog comparator, timer/counter, SPI and pin change interrupt as described in “Alternate Port Functions” on page 58.4 8183F–AVR–06/12 ATtiny24A/44A/84A 2. Overview ATtiny24A/44A/84A are low-power CMOS 8-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny24A/44A/84A achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 2-1. Block Diagram The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. WATCHDOG TIMER MCU CONTROL REGISTER TIMER/ COUNTER0 DATA DIR. REG.PORT A DATA REGISTER PORT A PROGRAMMING LOGIC TIMING AND CONTROL MCU STATUS REGISTER PORT A DRIVERS PA[7:0] VCC GND + _ ANALOG COMPARATOR 8-BIT DATABUS ADC ISP INTERFACE INTERRUPT UNIT EEPROM INTERNAL OSCILLATOR OSCILLATORS CALIBRATED OSCILLATOR INTERNAL DATA DIR. REG.PORT B DATA REGISTER PORT B PORT B DRIVERS PB[3:0] PROGRAM COUNTER STACK POINTER PROGRAM FLASH SRAM GENERAL PURPOSE REGISTERS INSTRUCTION REGISTER INSTRUCTION DECODER STATUS REGISTER Z Y X ALU CONTROL LINES TIMER/ COUNTER15 8183F–AVR–06/12 ATtiny24A/44A/84A The ATtiny24A/44A/84A provides the following features: 2K/4K/8K byte of In-System Programmable Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 12 general purpose I/O lines, 32 general purpose working registers, an 8-bit Timer/Counter with two PWM channels, a 16-bit timer/counter with two PWM channels, Internal and External Interrupts, a 8-channel 10-bit ADC, programmable gain stage (1x, 20x) for 12 differential ADC channel pairs, a programmable Watchdog Timer with internal oscillator, internal calibrated oscillator, and four software selectable power saving modes. Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. ADC Noise Reduction mode minimizes switching noise during ADC conversions by stopping the CPU and all I/O modules except the ADC. In Power-down mode registers keep their contents and all chip functions are disbaled until the next interrupt or hardware reset. In Standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined with low power consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The onchip ISP Flash allows the Program memory to be re-programmed in-system through an SPI serial interface, by a conventional non-volatile memory programmer or by an on-chip boot code running on the AVR core. The ATtiny24A/44A/84A AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators and Evaluation kits.6 8183F–AVR–06/12 ATtiny24A/44A/84A 3. General Information 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O Registers located in the extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically, this means “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Note that not all AVR devices include an extended I/O map. 3.3 Capacitive Touch Sensing Atmel QTouch Library provides a simple to use solution for touch sensitive interfaces on Atmel AVR microcontrollers. The QTouch Library includes support for QTouch® and QMatrix® acquisition methods. Touch sensing is easily added to any application by linking the QTouch Library and using the Application Programming Interface (API) of the library to define the touch channels and sensors. The application then calls the API to retrieve channel information and determine the state of the touch sensor. The QTouch Library is free and can be downloaded from the Atmel website. For more information and details of implementation, refer to the QTouch Library User Guide – also available from the Atmel website. 3.4 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 3.5 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device has been characterized.7 8183F–AVR–06/12 ATtiny24A/44A/84A 4. CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 4.1 Architectural Overview Figure 4-1. Block Diagram of the AVR Architecture In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory. Flash Program Memory Instruction Register Instruction Decoder Program Counter Control Lines 32 x 8 General Purpose Registrers ALU Status and Control I/O Lines EEPROM Data Bus 8-bit Data SRAM Direct Addressing Indirect Addressing Interrupt Unit Watchdog Timer Analog Comparator Timer/Counter 0 Timer/Counter 1 Universal Serial Interface ADC8 8183F–AVR–06/12 ATtiny24A/44A/84A The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, capable of directly addressing the whole address space. Most AVR instructions have a single 16-bit word format but 32-bit wide instructions also exist. The actual instruction set varies, as some devices only implement a part of the instruction set. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. 4.2 ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description. 4.3 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.9 8183F–AVR–06/12 ATtiny24A/44A/84A The Status Register is neither automatically stored when entering an interrupt routine, nor restored when returning from an interrupt. This must be handled by software. 4.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 4-2 below shows the structure of the 32 general purpose working registers in the CPU. Figure 4-2. AVR CPU General Purpose Working Registers Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 4-2, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. 4.4.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3 below. Figure 4-3. The X-, Y-, and Z-registers 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 … R13 0x0D General R14 0x0E Purpose R15 0x0F Working R16 0x10 Registers R17 0x11 … R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte 15 XH XL 010 8183F–AVR–06/12 ATtiny24A/44A/84A In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.5 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. 4.6 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. X-register 7 0 7 0 R27 (0x1B) R26 (0x1A) 15 YH YL 0 Y-register 7 0 7 0 R29 (0x1D) R28 (0x1C) 15 ZH ZL 0 Z-register 7 0 7 0 R31 (0x1F) R30 (0x1E)11 8183F–AVR–06/12 ATtiny24A/44A/84A Figure 4-4. The Parallel Instruction Fetches and Instruction Executions Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 4-5. Single Cycle ALU Operation 4.7 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 47. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) clk 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch T1 T2 T3 T4 CPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back T1 T2 T3 T4 clkCPU12 8183F–AVR–06/12 ATtiny24A/44A/84A to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Note: See “Code Examples” on page 6. Assembly Code Example in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1< ... ... 9.2 External Interrupts External Interrupts are triggered by the INT0 pin or any of the PCINT[11:0] pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT[11:0] pins are configured as outputs. This feature provides a way of generating a software interrupt. Pin change 0 interrupts PCI0 will trigger if any enabled PCINT[7:0] pin toggles. Pin change 1 interrupts PCI1 will trigger if any enabled PCINT[11:8] pin toggles. The PCMSK0 and PCMSK1 Registers control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT[11:0] are detected asynchronously, which means that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The INT0 interrupt can be triggered by a falling or rising edge or a low level. This is set up as shown in “MCUCR – MCU Control Register” on page 50. When the INT0 interrupt is enabled and configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT0 requires the presence of an I/O clock, as described in “Clock Sources” on page 25. 9.2.1 Low Level Interrupt A low level interrupt on INT0 is detected asynchronously. This means that the interrupt source can be used for waking the part also from sleep modes other than Idle (the I/O clock is halted in all sleep modes except Idle).49 8183F–AVR–06/12 ATtiny24A/44A/84A Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL fuses, as described in “Clock System” on page 24. If the low level on the interrupt pin is removed before the device has woken up then program execution will not be diverted to the interrupt service routine but continue from the instruction following the SLEEP command. 9.2.2 Pin Change Interrupt Timing A timing example of a pin change interrupt is shown in Figure 9-1. Figure 9-1. Timing of pin change interrupts clk PCINT(0) pin_lat pin_sync pcint_in_(0) pcint_syn pcint_setflag PCIF PCINT(0) pin_sync pcint_syn pin_lat D Q LE pcint_setflag PCIF clk clk PCINT(0) in PCMSK(x) pcint_in_(0) 0 x50 8183F–AVR–06/12 ATtiny24A/44A/84A 9.3 Register Description 9.3.1 MCUCR – MCU Control Register The External Interrupt Control Register A contains control bits for interrupt sense control. • Bits 1:0 – ISC0[1:0]: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 9-2. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. 9.3.2 GIMSK – General Interrupt Mask Register • Bits 7, 3:0 – Res: Reserved Bits These bits are reserved in the ATtiny24A/44A and will always read as zero. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control bits (ISC01 and ISC00) in the External Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector. • Bit 5 – PCIE1: Pin Change Interrupt Enable 1 When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled. Any change on any enabled PCINT[11:8] pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT[11:8] pins are enabled individually by the PCMSK1 Register. Bit 7 6 5 4 3 2 1 0 0x35 (0x55) BODS PUD SE SM1 SM0 BODSE ISC01 ISC00 MCUCR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 9-2. Interrupt 0 Sense Control ISC01 ISC00 Description 0 0 The low level of INT0 generates an interrupt request. 0 1 Any logical change on INT0 generates an interrupt request. 1 0 The falling edge of INT0 generates an interrupt request. 1 1 The rising edge of INT0 generates an interrupt request. Bit 7 6 5 4 3 2 1 0 0x3B (0x5B) – INT0 PCIE1 PCIE0 – – – – GIMSK Read/Write R R/W R/W R/W1 R R R R Initial Value 0 0 0 0 0 0 0 051 8183F–AVR–06/12 ATtiny24A/44A/84A • Bit 4 – PCIE0: Pin Change Interrupt Enable 0 When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT[7:0] pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT[7:0] pins are enabled individually by the PCMSK0 Register. 9.3.3 GIFR – General Interrupt Flag Register • Bits 7, 3:0 – Res: Reserved Bits These bits are reserved in the ATtiny24A/44A and will always read as zero. • Bit 6 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt. • Bit 5 – PCIF1: Pin Change Interrupt Flag 1 When a logic change on any PCINT[11:8] pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. • Bit 4 – PCIF0: Pin Change Interrupt Flag 0 When a logic change on any PCINT[7:0] pin triggers an interrupt request, PCIF becomes set (one). If the I-bit in SREG and the PCIE0 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. 9.3.4 PCMSK1 – Pin Change Mask Register 1 • Bits 7:4 – Res: Reserved Bits These bits are reserved in the ATtiny24A/44A and will always read as zero. • Bits 3:0 – PCINT[11:8]: Pin Change Enable Mask 11:8 Each PCINT[11:8] bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[11:8] is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT[11:8] is cleared, pin change interrupt on the corresponding I/O pin is disabled. Bit 7 6 5 4 3 2 1 0 0x3A (0x5A) – INTF0 PCIF1 PCIF0 – – – – GIFR Read/Write R R/W R/W R/W R R R R Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 0x20 (0x40) – – – – PCINT11 PCINT10 PCINT9 PCINT8 PCMSK1 Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 052 8183F–AVR–06/12 ATtiny24A/44A/84A 9.3.5 PCMSK0 – Pin Change Mask Register 0 • Bits 7:0 – PCINT[7:0]: Pin Change Enable Mask 7:0 Each PCINT[7:0] bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[7:0] is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT[7:0] is cleared, pin change interrupt on the corresponding I/O pin is disabled. Bit 7 6 5 4 3 2 1 0 0x12 (0x32) PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 053 8183F–AVR–06/12 ATtiny24A/44A/84A 10. I/O Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both VCC and Ground as indicated in Figure 10-1 on page 53. See “Electrical Characteristics” on page 173 for a complete list of parameters. Figure 10-1. I/O Pin Equivalent Schematic All registers and bit references in this section are written in general form. A lower case “x” represents the numbering letter for the port, and a lower case “n” represents the bit number. However, when using the register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Registers and bit locations are listed in “Register Description” on page 66. Three I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the pull-up function for all pins in all ports when set. Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page 54. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in “Alternate Port Functions” on page 58. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. Cpin Logic Rpu See Figure "General Digital I/O" for Details Pxn54 8183F–AVR–06/12 ATtiny24A/44A/84A 10.1 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 10-2. General Digital I/O(1) Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports. 10.1.1 Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register Description” on page 66, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). clk RPx RRx RDx WDx PUD SYNCHRONIZER WDx: WRITE DDRx WRx: WRITE PORTx RRx: READ PORTx REGISTER RPx: READ PORTx PIN PUD: PULLUP DISABLE clkI/O: I/O CLOCK RDx: READ DDRx D L Q Q RESET RESET Q D Q Q Q D CLR PORTxn Q Q D CLR DDxn PINxn DATA BU S SLEEP SLEEP: SLEEP CONTROL Pxn I/O WPx 0 1 WRx WPx: WRITE PINx REGISTER55 8183F–AVR–06/12 ATtiny24A/44A/84A 10.1.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 10.1.3 Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b10) as an intermediate step. Table 10-1 summarizes the control signals for the pin value. 10.1.4 Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As shown in Figure 10-2 on page 54, the PINxn Register bit and the preceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. Figure 10-3 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted tpd,max and tpd,min respectively. Figure 10-3. Synchronization when Reading an Externally Applied Pin value Table 10-1. Port Pin Configurations DDxn PORTxn PUD (in MCUCR) I/O Pull-up Comment 0 0 X Input No Tri-state (Hi-Z) 0 1 0 Input Yes Pxn will source current if ext. pulled low 0 1 1 Input No Tri-state (Hi-Z) 1 0 X Output No Output Low (Sink) 1 1 X Output No Output High (Source) XXX in r17, PINx 0x00 0xFF INSTRUCTIONS SYNC LATCH PINxn r17 XXX SYSTEM CLK tpd, max tpd, min56 8183F–AVR–06/12 ATtiny24A/44A/84A Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 10-4 on page 56. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is one system clock period. Figure 10-4. Synchronization when Reading a Software Assigned Pin Value 10.1.5 Digital Input Enable and Sleep Modes As shown in Figure 10-2 on page 54, the digital input signal can be clamped to ground at the input of the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down and Standby modes to avoid high power consumption if some input signals are left floating, or have an analog signal level close to VCC/2. SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in “Alternate Port Functions” on page 58. If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change. 10.1.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is out PORTx, r16 nop in r17, PINx 0xFF 0x00 0xFF SYSTEM CLK r16 INSTRUCTIONS SYNC LATCH PINxn r17 t pd57 8183F–AVR–06/12 ATtiny24A/44A/84A important, it is recommended to use an external pull-up or pulldown. Connecting unused pins directly to VCC or GND is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output. 10.1.7 Program Examples The following code example shows how to set port A pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 5 as input with a pull-up assigned to port pin 4. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Note: Two temporary registers are used to minimize the time from pull-ups are set on pins 0, 1 and 4, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. Note: See “Code Examples” on page 6. Assembly Code Example ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1< MSB MSB 6 5 4 3 2 1 LSB 1 2 3 4 5 6 7 8 6 5 4 3 2 1 LSB USCK USCK DO DI A B C D E CYCLE ( Reference )119 8183F–AVR–06/12 ATtiny24A/44A/84A SPITransfer_loop: out USICR,r17 in r16, USISR sbrs r16, USIOIF rjmp SPITransfer_loop in r16,USIDR ret The code is size optimized using only eight instructions (plus return). The code example assumes that the DO and USCK pins have been enabled as outputs in DDRA. The value stored in register r16 prior to the function is called is transferred to the slave device, and when the transfer is completed the data received from the slave is stored back into the register r16. The second and third instructions clear the USI Counter Overflow Flag and the USI counter value. The fourth and fifth instructions set three-wire mode, positive edge clock, count at USITC strobe, and toggle USCK. The loop is repeated 16 times. The following code demonstrates how to use the USI as an SPI master with maximum speed (fSCK = fCK/2): SPITransfer_Fast: out USIDR,r16 ldi r16,(1<