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Farnell PDF
ATtiny24A/44A/84A - Atmel - Farnell Element 14
ATtiny24A/44A/84A - Atmel - Farnell Element 14
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Farnell Element 14 :
See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…
Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.
Puce électronique / Microchip :
Sans fil - Wireless :
Texas instrument :
Ordinateurs :
Logiciels :
Tutoriels :
Autres documentations :
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Features
• High Performance, Low Power AVR® 8-bit Microcontroller
• Advanced RISC Architecture
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
• High Endurance, Non-volatile Memory Segments
– 2K/4K/8K Bytes of In-System, Self-programmable Flash Program Memory
• Endurance: 10,000 Write/Erase Cycles
– 128/256/512 Bytes of In-System Programmable EEPROM
• Endurance: 100,000 Write/Erase Cycles
– 128/256/512 Bytes of Internal SRAM
– Data Retention: 20 years at 85°C / 100 years at 25°C
– Programming Lock for Self-programming Flash & EEPROM Data Security
• Peripheral Features
– One 8-bit and One 16-bit Timer/Counter with Two PWM Channels, Each
– 10-bit ADC
• 8 Single-ended Channels
• 12 Differential ADC Channel Pairs with Programmable Gain (1x / 20x)
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Universal Serial Interface
• Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– Internal and External Interrupt Sources
• Pin Change Interrupt on 12 Pins
– Low Power Idle, ADC Noise Reduction, Standby and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit with Software Disable Function
– Internal Calibrated Oscillator
– On-chip Temperature Sensor
• I/O and Packages
– Available in 20-pin QFN/MLF/VQFN, 14-pin SOIC, 14-pin PDIP and 15-ball UFBGA
– Twelve Programmable I/O Lines
• Operating Voltage:
– 1.8 – 5.5V
• Speed Grade:
– 0 – 4 MHz @ 1.8 – 5.5V
– 0 – 10 MHz @ 2.7 – 5.5V
– 0 – 20 MHz @ 4.5 – 5.5V
• Industrial Temperature Range: -40°C to +85°C
• Low Power Consumption
– Active Mode:
• 210 µA at 1.8V and 1 MHz
– Idle Mode:
• 33 µA at 1.8V and 1 MHz
– Power-down Mode:
• 0.1 µA at 1.8V and 25°C
8-bit
Microcontroller
with 2K/4K/8K
Bytes In-System
Programmable
Flash
ATtiny24A
ATtiny44A
ATtiny84A
Rev. 8183F–AVR–06/122
8183F–AVR–06/12
ATtiny24A/44A/84A
1. Pin Configurations
Figure 1-1. Pinout of ATtiny24A/44A/84A
Table 1-1. UFBGA - Pinout ATtiny24A/44A/84A (top view)
1234
A PA5 PA6 PB2
B PA4 PA7 PB1 PB3
C PA3 PA2 PA1 PB0
D PA0 GND GND VCC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
(PCINT8/XTAL1/CLKI) PB0
(PCINT9/XTAL2) PB1
(PCINT11/RESET/dW) PB3
(PCINT10/INT0/OC0A/CKOUT) PB2
(PCINT7/ICP/OC0B/ADC7) PA7
(PCINT6/OC1A/SDA/MOSI/DI/ADC6) PA6
GND
PA0 (ADC0/AREF/PCINT0)
PA1 (ADC1/AIN0/PCINT1)
PA2 (ADC2/AIN1/PCINT2)
PA3 (ADC3/T0/PCINT3)
PA4 (ADC4/USCK/SCL/T1/PCINT4)
PA5 (ADC5/DO/MISO/OC1B/PCINT5)
PDIP/SOIC
1
2
3
4
5
QFN/MLF/VQFN
15
14
13
12
11
20
19
18
17
16
6
7
8
9
10
NOTE
Bottom pad should be
soldered to ground.
DNC: Do Not Connect
DNC
DNC
GND
VCC
DNC
PA7 (PCINT7/ICP/OC0B/ADC7)
PB2 (PCINT10/INT0/OC0A/CKOUT)
PB3 (PCINT11/RESET/dW)
PB1 (PCINT9/XTAL2)
PB0 (PCINT8/XTAL1/CLKI)
PA5
DNC
DNC
DNC
PA6
Pin 16: PA6 (PCINT6/OC1A/SDA/MOSI/DI/ADC6)
Pin 20: PA5 (ADC5/DO/MISO/OC1B/PCINT5)
(ADC4/USCK/SCL/T1/PCINT4) PA4
(ADC3/T0/PCINT3) PA3
(ADC2/AIN1/PCINT2) PA2
(ADC1/AIN0/PCINT1) PA1
(ADC0/AREF/PCINT0) PA03
8183F–AVR–06/12
ATtiny24A/44A/84A
1.1 Pin Descriptions
1.1.1 VCC
Supply voltage.
1.1.2 GND
Ground.
1.1.3 Port B (PB3:PB0)
Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability except PB3 which has the RESET capability. To use pin PB3 as an I/O pin, instead of
RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins that are externally pulled low
will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny24A/44A/84A as listed
in Section 10.2 “Alternate Port Functions” on page 58.
1.1.4 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running and provided the reset pin has not been disabled. The minimum
pulse length is given in Table 20-4 on page 176. Shorter pulses are not guaranteed to
generate a reset.
The reset pin can also be used as a (weak) I/O pin.
1.1.5 Port A (PA7:PA0)
Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port A has alternate functions as analog inputs for the ADC, analog comparator, timer/counter,
SPI and pin change interrupt as described in “Alternate Port Functions” on page 58.4
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2. Overview
ATtiny24A/44A/84A are low-power CMOS 8-bit microcontrollers based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the
ATtiny24A/44A/84A achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
Figure 2-1. Block Diagram
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than conventional
CISC microcontrollers.
WATCHDOG
TIMER
MCU CONTROL
REGISTER
TIMER/
COUNTER0
DATA DIR.
REG.PORT A
DATA REGISTER
PORT A
PROGRAMMING
LOGIC
TIMING AND
CONTROL
MCU STATUS
REGISTER
PORT A DRIVERS
PA[7:0]
VCC
GND
+
_
ANALOG
COMPARATOR
8-BIT DATABUS
ADC
ISP INTERFACE
INTERRUPT
UNIT
EEPROM
INTERNAL
OSCILLATOR
OSCILLATORS
CALIBRATED
OSCILLATOR
INTERNAL
DATA DIR.
REG.PORT B
DATA REGISTER
PORT B
PORT B DRIVERS
PB[3:0]
PROGRAM
COUNTER
STACK
POINTER
PROGRAM
FLASH SRAM
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
STATUS
REGISTER
Z
Y
X
ALU CONTROL
LINES
TIMER/
COUNTER15
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The ATtiny24A/44A/84A provides the following features: 2K/4K/8K byte of In-System Programmable
Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 12 general purpose I/O
lines, 32 general purpose working registers, an 8-bit Timer/Counter with two PWM channels, a
16-bit timer/counter with two PWM channels, Internal and External Interrupts, a 8-channel 10-bit
ADC, programmable gain stage (1x, 20x) for 12 differential ADC channel pairs, a programmable
Watchdog Timer with internal oscillator, internal calibrated oscillator, and four software selectable
power saving modes. Idle mode stops the CPU while allowing the SRAM, Timer/Counter,
ADC, Analog Comparator, and Interrupt system to continue functioning. ADC Noise Reduction
mode minimizes switching noise during ADC conversions by stopping the CPU and all I/O modules
except the ADC. In Power-down mode registers keep their contents and all chip functions
are disbaled until the next interrupt or hardware reset. In Standby mode, the crystal/resonator
oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined
with low power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The onchip
ISP Flash allows the Program memory to be re-programmed in-system through an SPI
serial interface, by a conventional non-volatile memory programmer or by an on-chip boot code
running on the AVR core.
The ATtiny24A/44A/84A AVR is supported with a full suite of program and system development
tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators and Evaluation
kits.6
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3. General Information
3.1 Resources
A comprehensive set of drivers, application notes, data sheets and descriptions on development
tools are available for download at http://www.atmel.com/avr.
3.2 Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. These code examples assume that the part specific header file is included before
compilation. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation
for more details.
For I/O Registers located in the extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically, this
means “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Note that not all
AVR devices include an extended I/O map.
3.3 Capacitive Touch Sensing
Atmel QTouch Library provides a simple to use solution for touch sensitive interfaces on Atmel
AVR microcontrollers. The QTouch Library includes support for QTouch® and QMatrix® acquisition
methods.
Touch sensing is easily added to any application by linking the QTouch Library and using the
Application Programming Interface (API) of the library to define the touch channels and sensors.
The application then calls the API to retrieve channel information and determine the state of the
touch sensor.
The QTouch Library is free and can be downloaded from the Atmel website. For more information
and details of implementation, refer to the QTouch Library User Guide – also available from
the Atmel website.
3.4 Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
3.5 Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max values
will be available after the device has been characterized.7
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4. CPU Core
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
4.1 Architectural Overview
Figure 4-1. Block Diagram of the AVR Architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the Program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruction
is pre-fetched from the Program memory. This concept enables instructions to be executed
in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
Direct Addressing
Indirect Addressing
Interrupt
Unit
Watchdog
Timer
Analog
Comparator
Timer/Counter 0
Timer/Counter 1
Universal
Serial Interface
ADC8
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The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical
ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointers
can also be used as an address pointer for look up tables in Flash Program memory. These
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single register operations can also be executed in the ALU. After an arithmetic operation,
the Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, capable of
directly addressing the whole address space. Most AVR instructions have a single 16-bit word
format but 32-bit wide instructions also exist. The actual instruction set varies, as some devices
only implement a part of the instruction set.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack
Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position.
The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers,
SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data
Space locations following those of the Register File, 0x20 - 0x5F.
4.2 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general purpose
registers or between a register and an immediate are executed. The ALU operations are divided
into three main categories – arithmetic, logical, and bit-functions. Some implementations of the
architecture also provide a powerful multiplier supporting both signed/unsigned multiplication
and fractional format. See the “Instruction Set” section for a detailed description.
4.3 Status Register
The Status Register contains information about the result of the most recently executed arithmetic
instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the Instruction Set Reference. This will in many cases remove the need for using the
dedicated compare instructions, resulting in faster and more compact code.9
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The Status Register is neither automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt. This must be handled by software.
4.4 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve
the required performance and flexibility, the following input/output schemes are supported by the
Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 4-2 below shows the structure of the 32 general purpose working registers in the CPU.
Figure 4-2. AVR CPU General Purpose Working Registers
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 4-2, each register is also assigned a Data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically implemented
as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
4.4.1 The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers
are 16-bit address pointers for indirect addressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in Figure 4-3 below.
Figure 4-3. The X-, Y-, and Z-registers
7 0 Addr.
R0 0x00
R1 0x01
R2 0x02
…
R13 0x0D
General R14 0x0E
Purpose R15 0x0F
Working R16 0x10
Registers R17 0x11
…
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte
15 XH XL 010
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In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
4.5 Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations
to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack
with the PUSH instruction, and it is decremented by two when the return address is pushed onto
the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is incremented by two when data is
popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementations
of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
4.6 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the
chip. No internal clock division is used.
Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard
architecture and the fast access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
X-register 7 0 7 0
R27 (0x1B) R26 (0x1A)
15 YH YL 0
Y-register 7 0 7 0
R29 (0x1D) R28 (0x1C)
15 ZH ZL 0
Z-register 7 0 7 0
R31 (0x1F) R30 (0x1E)11
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Figure 4-4. The Parallel Instruction Fetches and Instruction Executions
Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destination
register.
Figure 4-5. Single Cycle ALU Operation
4.7 Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate Program Vector in the Program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt.
The lowest addresses in the Program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 47. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt
Request 0.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled.
The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector
in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clkCPU12
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ATtiny24A/44A/84A
to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt
Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The following example shows how this can be used to avoid interrupts during the
timed EEPROM write sequence.
Note: See “Code Examples” on page 6.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<
... ...
9.2 External Interrupts
External Interrupts are triggered by the INT0 pin or any of the PCINT[11:0] pins. Observe that, if
enabled, the interrupts will trigger even if the INT0 or PCINT[11:0] pins are configured as outputs.
This feature provides a way of generating a software interrupt. Pin change 0 interrupts
PCI0 will trigger if any enabled PCINT[7:0] pin toggles. Pin change 1 interrupts PCI1 will trigger
if any enabled PCINT[11:8] pin toggles. The PCMSK0 and PCMSK1 Registers control which
pins contribute to the pin change interrupts. Pin change interrupts on PCINT[11:0] are detected
asynchronously, which means that these interrupts can be used for waking the part also from
sleep modes other than Idle mode.
The INT0 interrupt can be triggered by a falling or rising edge or a low level. This is set up as
shown in “MCUCR – MCU Control Register” on page 50. When the INT0 interrupt is enabled
and configured as level triggered, the interrupt will trigger as long as the pin is held low. Note
that recognition of falling or rising edge interrupts on INT0 requires the presence of an I/O clock,
as described in “Clock Sources” on page 25.
9.2.1 Low Level Interrupt
A low level interrupt on INT0 is detected asynchronously. This means that the interrupt source
can be used for waking the part also from sleep modes other than Idle (the I/O clock is halted in
all sleep modes except Idle).49
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Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt
will be generated. The start-up time is defined by the SUT and CKSEL fuses, as described
in “Clock System” on page 24.
If the low level on the interrupt pin is removed before the device has woken up then program
execution will not be diverted to the interrupt service routine but continue from the instruction following
the SLEEP command.
9.2.2 Pin Change Interrupt Timing
A timing example of a pin change interrupt is shown in Figure 9-1.
Figure 9-1. Timing of pin change interrupts
clk
PCINT(0)
pin_lat
pin_sync
pcint_in_(0)
pcint_syn
pcint_setflag
PCIF
PCINT(0)
pin_sync
pcint_syn pin_lat D Q
LE
pcint_setflag
PCIF
clk
clk PCINT(0) in PCMSK(x)
pcint_in_(0) 0
x50
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9.3 Register Description
9.3.1 MCUCR – MCU Control Register
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bits 1:0 – ISC0[1:0]: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding
interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in Table 9-2. The value on the INT0 pin is sampled before detecting edges.
If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate
an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
selected, the low level must be held until the completion of the currently executing instruction to
generate an interrupt.
9.3.2 GIMSK – General Interrupt Mask Register
• Bits 7, 3:0 – Res: Reserved Bits
These bits are reserved in the ATtiny24A/44A and will always read as zero.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external
pin interrupt is enabled. The Interrupt Sense Control bits (ISC01 and ISC00) in the External
Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising
and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt
request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt
Request 0 is executed from the INT0 Interrupt Vector.
• Bit 5 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 1 is enabled. Any change on any enabled PCINT[11:8] pin will cause an interrupt.
The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1
Interrupt Vector. PCINT[11:8] pins are enabled individually by the PCMSK1 Register.
Bit 7 6 5 4 3 2 1 0
0x35 (0x55) BODS PUD SE SM1 SM0 BODSE ISC01 ISC00 MCUCR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 9-2. Interrupt 0 Sense Control
ISC01 ISC00 Description
0 0 The low level of INT0 generates an interrupt request.
0 1 Any logical change on INT0 generates an interrupt request.
1 0 The falling edge of INT0 generates an interrupt request.
1 1 The rising edge of INT0 generates an interrupt request.
Bit 7 6 5 4 3 2 1 0
0x3B (0x5B) – INT0 PCIE1 PCIE0 – – – – GIMSK
Read/Write R R/W R/W R/W1 R R R R
Initial Value 0 0 0 0 0 0 0 051
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• Bit 4 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 0 is enabled. Any change on any enabled PCINT[7:0] pin will cause an interrupt.
The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0
Interrupt Vector. PCINT[7:0] pins are enabled individually by the PCMSK0 Register.
9.3.3 GIFR – General Interrupt Flag Register
• Bits 7, 3:0 – Res: Reserved Bits
These bits are reserved in the ATtiny24A/44A and will always read as zero.
• Bit 6 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set
(one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the corresponding
Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT0 is configured as a level interrupt.
• Bit 5 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT[11:8] pin triggers an interrupt request, PCIF1 becomes set
(one). If the I-bit in SREG and the PCIE1 bit in GIMSK are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively,
the flag can be cleared by writing a logical one to it.
• Bit 4 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT[7:0] pin triggers an interrupt request, PCIF becomes set
(one). If the I-bit in SREG and the PCIE0 bit in GIMSK are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively,
the flag can be cleared by writing a logical one to it.
9.3.4 PCMSK1 – Pin Change Mask Register 1
• Bits 7:4 – Res: Reserved Bits
These bits are reserved in the ATtiny24A/44A and will always read as zero.
• Bits 3:0 – PCINT[11:8]: Pin Change Enable Mask 11:8
Each PCINT[11:8] bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT[11:8] is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT[11:8] is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
Bit 7 6 5 4 3 2 1 0
0x3A (0x5A) – INTF0 PCIF1 PCIF0 – – – – GIFR
Read/Write R R/W R/W R/W R R R R
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x20 (0x40) – – – – PCINT11 PCINT10 PCINT9 PCINT8 PCMSK1
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 052
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9.3.5 PCMSK0 – Pin Change Mask Register 0
• Bits 7:0 – PCINT[7:0]: Pin Change Enable Mask 7:0
Each PCINT[7:0] bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT[7:0] is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT[7:0] is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
Bit 7 6 5 4 3 2 1 0
0x12 (0x32) PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 053
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10. I/O Ports
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.
This means that the direction of one port pin can be changed without unintentionally changing
the direction of any other pin with the SBI and CBI instructions. The same applies when changing
drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as
input). Each output buffer has symmetrical drive characteristics with both high sink and source
capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually
selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have
protection diodes to both VCC and Ground as indicated in Figure 10-1 on page 53. See “Electrical
Characteristics” on page 173 for a complete list of parameters.
Figure 10-1. I/O Pin Equivalent Schematic
All registers and bit references in this section are written in general form. A lower case “x” represents
the numbering letter for the port, and a lower case “n” represents the bit number. However,
when using the register or bit defines in a program, the precise form must be used. For example,
PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Registers
and bit locations are listed in “Register Description” on page 66.
Three I/O memory address locations are allocated for each port, one each for the Data Register
– PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins
I/O location is read only, while the Data Register and the Data Direction Register are read/write.
However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding
bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the
pull-up function for all pins in all ports when set.
Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page
54. Most port pins are multiplexed with alternate functions for the peripheral features on the
device. How each alternate function interferes with the port pin is described in “Alternate Port
Functions” on page 58. Refer to the individual module sections for a full description of the alternate
functions.
Note that enabling the alternate function of some of the port pins does not affect the use of the
other pins in the port as general digital I/O.
Cpin
Logic
Rpu
See Figure
"General Digital I/O" for
Details
Pxn54
8183F–AVR–06/12
ATtiny24A/44A/84A
10.1 Ports as General Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a functional
description of one I/O-port pin, here generically called Pxn.
Figure 10-2. General Digital I/O(1)
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,
SLEEP, and PUD are common to all ports.
10.1.1 Configuring the Pin
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register
Description” on page 66, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits
at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to
be configured as an output pin. The port pins are tri-stated when reset condition becomes active,
even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven
high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port
pin is driven low (zero).
clk
RPx
RRx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
PUD: PULLUP DISABLE
clkI/O: I/O CLOCK
RDx: READ DDRx
D
L
Q
Q
RESET
RESET
Q
D Q
Q
Q D
CLR
PORTxn
Q
Q D
CLR
DDxn
PINxn
DATA BU
S
SLEEP
SLEEP: SLEEP CONTROL
Pxn
I/O
WPx
0
1
WRx
WPx: WRITE PINx REGISTER55
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ATtiny24A/44A/84A
10.1.2 Toggling the Pin
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
Note that the SBI instruction can be used to toggle one single bit in a port.
10.1.3 Switching Between Input and Output
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}
= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output
low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable,
as a high-impedant environment will not notice the difference between a strong high driver
and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all
pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}
= 0b10) as an intermediate step.
Table 10-1 summarizes the control signals for the pin value.
10.1.4 Reading the Pin Value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in Figure 10-2 on page 54, the PINxn Register bit and the preceding
latch constitute a synchronizer. This is needed to avoid metastability if the physical pin
changes value near the edge of the internal clock, but it also introduces a delay. Figure 10-3
shows a timing diagram of the synchronization when reading an externally applied pin value.
The maximum and minimum propagation delays are denoted tpd,max and tpd,min respectively.
Figure 10-3. Synchronization when Reading an Externally Applied Pin value
Table 10-1. Port Pin Configurations
DDxn PORTxn
PUD
(in MCUCR) I/O Pull-up Comment
0 0 X Input No Tri-state (Hi-Z)
0 1 0 Input Yes Pxn will source current if ext. pulled low
0 1 1 Input No Tri-state (Hi-Z)
1 0 X Output No Output Low (Sink)
1 1 X Output No Output High (Source)
XXX in r17, PINx
0x00 0xFF
INSTRUCTIONS
SYNC LATCH
PINxn
r17
XXX
SYSTEM CLK
tpd, max
tpd, min56
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ATtiny24A/44A/84A
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated
by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed
between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indicated
in Figure 10-4 on page 56. The out instruction sets the “SYNC LATCH” signal at the
positive edge of the clock. In this case, the delay tpd through the synchronizer is one system
clock period.
Figure 10-4. Synchronization when Reading a Software Assigned Pin Value
10.1.5 Digital Input Enable and Sleep Modes
As shown in Figure 10-2 on page 54, the digital input signal can be clamped to ground at the
input of the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep
Controller in Power-down and Standby modes to avoid high power consumption if some input
signals are left floating, or have an analog signal level close to VCC/2.
SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt
request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various
other alternate functions as described in “Alternate Port Functions” on page 58.
If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as
“Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt
is not enabled, the corresponding External Interrupt Flag will be set when resuming from the
above mentioned Sleep mode, as the clamping in these sleep mode produces the requested
logic change.
10.1.6 Unconnected Pins
If some pins are unused, it is recommended to ensure that these pins have a defined level. Even
though most of the digital inputs are disabled in the deep sleep modes as described above, floating
inputs should be avoided to reduce current consumption in all other modes where the digital
inputs are enabled (Reset, Active mode and Idle mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
In this case, the pull-up will be disabled during reset. If low power consumption during reset is
out PORTx, r16 nop in r17, PINx
0xFF
0x00 0xFF
SYSTEM CLK
r16
INSTRUCTIONS
SYNC LATCH
PINxn
r17
t pd57
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ATtiny24A/44A/84A
important, it is recommended to use an external pull-up or pulldown. Connecting unused pins
directly to VCC or GND is not recommended, since this may cause excessive currents if the pin is
accidentally configured as an output.
10.1.7 Program Examples
The following code example shows how to set port A pins 0 and 1 high, 2 and 3 low, and define
the port pins from 4 to 5 as input with a pull-up assigned to port pin 4. The resulting pin values
are read back again, but as previously discussed, a nop instruction is included to be able to read
back the value recently assigned to some of the pins.
Note: Two temporary registers are used to minimize the time from pull-ups are set on pins 0, 1 and 4,
until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as
strong high drivers.
Note: See “Code Examples” on page 6.
Assembly Code Example
...
; Define pull-ups and set outputs high
; Define directions for port pins
ldi r16,(1<
MSB
MSB
6 5 4 3 2 1 LSB
1 2 3 4 5 6 7 8
6 5 4 3 2 1 LSB
USCK
USCK
DO
DI
A B C D E
CYCLE ( Reference )119
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ATtiny24A/44A/84A
SPITransfer_loop:
out USICR,r17
in r16, USISR
sbrs r16, USIOIF
rjmp SPITransfer_loop
in r16,USIDR
ret
The code is size optimized using only eight instructions (plus return). The code example
assumes that the DO and USCK pins have been enabled as outputs in DDRA. The value stored
in register r16 prior to the function is called is transferred to the slave device, and when the
transfer is completed the data received from the slave is stored back into the register r16.
The second and third instructions clear the USI Counter Overflow Flag and the USI counter
value. The fourth and fifth instructions set three-wire mode, positive edge clock, count at USITC
strobe, and toggle USCK. The loop is repeated 16 times.
The following code demonstrates how to use the USI as an SPI master with maximum speed
(fSCK = fCK/2):
SPITransfer_Fast:
out USIDR,r16
ldi r16,(1< 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
• High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
19.5.1 Serial Programming Algorithm
When writing serial data to the ATtiny24A/44A/84A, data is clocked on the rising edge of SCK.
When reading, data is clocked on the falling edge of SCK. See Figure 20-3 and Figure 20-4 for
timing details.
To program and verify the ATtiny24A/44A/84A in the Serial Programming mode, the following
sequence is recommended (see four byte instruction formats in Table 19-12):
1. Power-up sequence:
Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems,
the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse after SCK has been set to '0'. The duration
of the pulse must be at least tRST (the minimum pulse width on RESET pin, see Table
20-4 on page 176) plus two CPU clock cycles.
2. Wait for at least 20 ms and enable serial programming by sending the Programming
Enable serial instruction to pin MOSI.
3. The serial programming instructions will not work if the communication is out of synchronization.
When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not, all
four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give
RESET a positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The memory page is loaded one byte at
a time by supplying the 5 LSB of the address and data together with the Load Program
memory Page instruction. To ensure correct loading of the page, the data low byte must
be loaded before data high byte is applied for a given address. The Program memory
Page is stored by loading the Write Program memory Page instruction with the 3 MSB
of the address. If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH
before issuing the next page. (See Table 19-11 on page 164.) Accessing the serial programming
interface before the Flash write operation completes can result in incorrect
programming.
5. A: The EEPROM array is programmed one byte at a time by supplying the address and
data together with the appropriate Write instruction. An EEPROM memory location is
first automatically erased before new data is written. If polling (RDY/BSY) is not used,
the user must wait at least tWD_EEPROM before issuing the next byte. (See Table 19-11
on page 164.) In a chip erased device, no 0xFFs in the data file(s) need to be programmed.
B: The EEPROM array is programmed one page at a time. The Memory page is loaded
one byte at a time by supplying the 2 LSB of the address and data together with the
Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by
loading the Write EEPROM Memory Page Instruction with the 4 MSB of the address.
When using EEPROM page access only byte locations loaded with the Load EEPROM
Memory Page instruction is altered. The remaining locations remain unchanged. If polling
(RDY/BSY) is not used, the used must wait at least tWD_EEPROM before issuing the
next page (See Table 19-11 on page 164). In a chip erased device, no 0xFF in the data
file(s) need to be programmed.
6. Any memory location can be verified by using the Read instruction which returns the
content at the selected address at serial output MISO.164
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ATtiny24A/44A/84A
7. At the end of the programming session, RESET can be set high to commence normal
operation.
8. Power-off sequence (if needed):
Set RESET to “1”.
Turn VCC power off.
19.5.2 Serial Programming Instruction set
The instruction set is described in Table 19-12 and Figure 19-2 on page 165.
Table 19-11. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
Symbol Minimum Wait Delay
tWD_FLASH 4.5 ms
tWD_EEPROM 4.0 ms
tWD_ERASE 9.0 ms
tWD_FUSE 4.5 ms
Table 19-12. Serial Programming Instruction Set
Instruction/Operation(1)
Instruction Format
Byte 1 Byte 2 Byte 3 Byte4
Programming Enable $AC $53 $00 $00
Chip Erase (Program Memory/EEPROM) $AC $80 $00 $00
Poll RDY/BSY $F0 $00 $00 data byte out
Load Instructions
Load Extended Address byte $4D $00 Extended adr $00
Load Program Memory Page, High byte $48 adr MSB adr LSB high data byte in
Load Program Memory Page, Low byte $40 adr MSB adr LSB low data byte in
Load EEPROM Memory Page (page access) $C1 $00 adr LSB data byte in
Read Instructions
Read Program Memory, High byte $28 adr MSB adr LSB high data byte out
Read Program Memory, Low byte $20 adr MSB adr LSB low data byte out
Read EEPROM Memory $A0 $00 adr LSB data byte out
Read Lock bits $58 $00 $00 data byte out
Read Signature Byte $30 $00 adr LSB data byte out
Read Fuse bits $50 $00 $00 data byte out
Read Fuse High bits $58 $08 $00 data byte out
Read Extended Fuse Bits $50 $08 $00 data byte out
Read Calibration Byte $38 $00 $00 data byte out
Write Instructions(6)
Write Program Memory Page $4C adr MSB adr LSB $00
Write EEPROM Memory $C0 $00 adr LSB data byte in
Write EEPROM Memory Page (page access) $C2 $00 adr LSB $00165
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ATtiny24A/44A/84A
Notes: 1. Not all instructions are applicable for all parts.
2. a = address
3. Bits are programmed ‘0’, unprogrammed ‘1’.
4. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) .
5. Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size.
6. Instructions accessing program memory use a word address. This address may be random within the page range.
7. See http://www.atmel.com/avr for Application Notes regarding programming and programmers.
Figure 19-2. Serial Programming Instruction example
If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until
this bit returns ‘0’ before the next instruction is carried out.
Within the same page, the low data byte must be loaded prior to the high data byte.
Write Lock bits $AC $E0 $00 data byte in
Write Fuse bits $AC $A0 $00 data byte in
Write Fuse High bits $AC $A8 $00 data byte in
Write Extended Fuse Bits $AC $A4 $00 data byte in
Table 19-12. Serial Programming Instruction Set (Continued)
Instruction/Operation(1)
Instruction Format
Byte 1 Byte 2 Byte 3 Byte4
Byte 1 Byte 2 Byte 3 Byte 4
Adr MSB Adr LSB
Bit 15 B 0
Serial Programming Instruction
Program Memory/
EEPROM Memory
Page 0
Page 1
Page 2
Page N-1
Page Buffer
Write Program Memory Page/
Write EEPROM Memory Page
Load Program Memory Page (High/Low Byte)/
Load EEPROM Memory Page (page access)
Byte 1 Byte 2 Byte 3 Byte 4
Bit 15 B 0
Adr MSB Adr LSB
Page Offset
Page Number
Adr MSB Adr LSB166
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ATtiny24A/44A/84A
After data is loaded to the page buffer, program the EEPROM page, see Figure 19-2 on page
165.
19.6 High-voltage Serial Programming
This section describes how to program and verify Flash Program memory, EEPROM Data memory,
Lock bits and Fuse bits in the ATtiny24A/44A/84A.
Figure 19-3. High-voltage Serial Programming
The minimum period for the Serial Clock Input (SCI) during High-voltage Serial Programming is
220 ns.
19.7 High-Voltage Serial Programming Algorithm
To program and verify the ATtiny24A/44A/84A in the High-voltage Serial Programming mode,
the following sequence is recommended (See instruction formats in Table 19-16 on page 170):
Table 19-13. Pin Name Mapping
Signal Name in High-voltage
Serial Programming Mode Pin Name I/O Function
SDI PA6 I Serial Data Input
SII PA5 I Serial Instruction Input
SDO PA4 O Serial Data Output
SCI PB0 I Serial Clock Input (min. 220ns period)
Table 19-14. Pin Values Used to Enter Programming Mode
Pin Symbol Value
PA0 Prog_enable[0] 0
PA1 Prog_enable[1] 0
PA2 Prog_enable[2] 0
VCC
GND
SDO
SII
SDI
(RESET)
+4.5 - 5.5V
PA6
PA5
PA4
PB3
+11.5 - 12.5V
SCI PB0
PA2:0167
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ATtiny24A/44A/84A
19.7.1 Enter High-voltage Serial Programming Mode
The following algorithm puts the device in High-voltage Serial Programming mode:
1. Set Prog_enable pins listed in Table 19-14 on page 166 to “000”, RESET pin and VCC
to 0V.
2. Apply 4.5 - 5.5V between VCC and GND. Ensure that VCC reaches at least 1.8V within
the next 20 µs.
3. Wait 20 - 60 µs, and apply 11.5 - 12.5V to RESET.
4. Keep the Prog_enable pins unchanged for at least 10 µs after the High-voltage has
been applied to ensure the Prog_enable Signature has been latched.
5. Release the Prog_enable[2] pin after tHVRST has elapsed.
6. Wait at least 300 µs before giving any serial instructions on SDI/SII.
7. Exit Programming mode by power the device down or by bringing RESET pin to 0V.
If the rise time of the VCC is unable to fulfill the requirements listed above, the following alternative
algorithm can be used:
1. Set Prog_enable pins listed in Table 19-14 on page 166 to “000”, RESET pin and VCC
to 0V.
2. Apply 4.5 - 5.5V between VCC and GND.
3. Monitor VCC, and as soon as VCC reaches 0.9 - 1.1V, apply 11.5 - 12.5V to RESET.
4. Keep the Prog_enable pins unchanged for at least 10 µs after the High-voltage has
been applied to ensure the Prog_enable Signature has been latched.
5. Release the Prog_enable[2] pin to avoid drive contention on the Prog_enable[2]/SDO
pin.
6. Wait until VCC actually reaches 4.5 - 5.5V before giving any serial instructions on
SDI/SII.
7. Exit Programming mode by power the device down or by bringing RESET pin to 0V.
Table 19-15. High-voltage Reset Characteristics
Supply Voltage RESET Pin High-voltage Threshold
Minimum High-voltage Period for
Latching Prog_enable
VCC VHVRST tHVRST
4.5V 11.5V 100 ns
5.5V 11.5V 100 ns168
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19.7.2 Considerations for Efficient Programming
The loaded command and address are retained in the device during programming. For efficient
programming, the following should be considered.
• The command needs only be loaded once when writing or reading multiple memory
locations.
• Skip writing the data value 0xFF that is the contents of the entire EEPROM (unless the
EESAVE Fuse is programmed) and Flash after a Chip Erase.
• Address High byte needs only be loaded before programming or reading a new 256 word
window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes
reading.
19.7.3 Chip Erase
The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock bits are
not reset until the Program memory has been completely erased. The Fuse bits are not
changed. A Chip Erase must be performed before the Flash and/or EEPROM are reprogrammed.
1. Load command “Chip Erase” (see Table 19-16 on page 170).
2. Wait after Instr. 3 until SDO goes high for the “Chip Erase” cycle to finish.
3. Load Command “No Operation”.
Note: 1. The EEPROM memory is preserved during Chip Erase if the EESAVE Fuse is programmed.
19.7.4 Programming the Flash
The Flash is organized in pages, see “Page Size” on page 161. When programming the Flash,
the program data is latched into a page buffer. This allows one page of program data to be programmed
simultaneously. The following procedure describes how to program the entire Flash
memory:
1. Load Command “Write Flash” (see Table 19-16 on page 170).
2. Load Flash Page Buffer.
3. Load Flash High Address and Program Page. Wait after Instr. 3 until SDO goes high
for the “Page Programming” cycle to finish.
4. Repeat 2 through 3 until the entire Flash is programmed or until all data has been
programmed.
5. End Page Programming by Loading Command “No Operation”.
When writing or reading serial data to the ATtiny24A/44A/84A, data is clocked on the rising edge
of the serial clock, see Figure 20-5 on page 181, Figure 19-3 on page 166 and Table 20-12 on
page 181 for details.169
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ATtiny24A/44A/84A
Figure 19-4. Addressing the Flash which is Organized in Pages
Figure 19-5. High-voltage Serial Programming Waveforms
19.7.5 Programming the EEPROM
The EEPROM is organized in pages, see Table 20-11 on page 180. When programming the
EEPROM, the data is latched into a page buffer. This allows one page of data to be programmed
simultaneously. The programming algorithm for the EEPROM Data memory is as
follows (refer to Table 19-16 on page 170):
1. Load Command “Write EEPROM”.
2. Load EEPROM Page Buffer.
3. Program EEPROM Page. Wait after Instr. 2 until SDO goes high for the “Page Programming”
cycle to finish.
4. Repeat 2 through 3 until the entire EEPROM is programmed or until all data has been
programmed.
5. End Page Programming by Loading Command “No Operation”.
PROGRAM MEMORY
WORD ADDRESS
WITHIN A PAGE
PAGE ADDRESS
WITHIN THE FLASH
INSTRUCTION WORD
PAGE PCWORD[PAGEMSB:0]:
00
01
02
PAGEEND
PAGE
PCPAGE PCWORD
PCMSB PAGEMSB
PROGRAM
COUNTER
MSB
MSB
MSB LSB
LSB
LSB
0 1 2 3 4 5 6 7 8 9 10
SDI
PA6
SII
PA5
SDO
PA4
SCI
PB0170
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ATtiny24A/44A/84A
19.7.6 Reading the Flash
The algorithm for reading the Flash memory is as follows (refer to Table 19-16 on page 170):
1. Load Command "Read Flash".
2. Read Flash Low and High Bytes. The contents at the selected address are available at
serial output SDO.
19.7.7 Reading the EEPROM
The algorithm for reading the EEPROM memory is as follows (refer to Table 19-16 on page
170):
1. Load Command “Read EEPROM”.
2. Read EEPROM Byte. The contents at the selected address are available at serial output
SDO.
19.7.8 Programming and Reading the Fuse and Lock Bits
The algorithms for programming and reading the Fuse Low/High bits and Lock bits are shown in
Table 19-16 on page 170.
19.7.9 Reading the Signature Bytes and Calibration Byte
The algorithms for reading the Signature bytes and Calibration byte are shown in Table 19-16 on
page 170.
19.7.10 Power-off sequence
Set SCI to “0”. Set RESET to “1”. Turn VCC power off.
Table 19-16. High-voltage Serial Programming Instruction Set for ATtiny24A/44A/84A
Instruction
Instruction Format
Instr.1/5 Instr.2/6 Instr.3/7 Instr.4 Operation Remarks
Chip Erase
SDI
SII
SDO
0_1000_0000_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_0100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
x_xxxx_xxxx_xx
Wait after Instr.3 until SDO
goes high for the Chip Erase
cycle to finish.
Load “Write
Flash”
Command
SDI
SII
SDO
0_0001_0000_00
0_0100_1100_00
x_xxxx_xxxx_xx
Enter Flash Programming code.
Load Flash
Page Buffer
SDI
SII
SDO
0_ bbbb_bbbb _00
0_0000_1100_00
x_xxxx_xxxx_xx
0_eeee_eeee_00
0_0010_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1101_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
x_xxxx_xxxx_xx
Repeat after Instr. 1 - 7until the
entire page buffer is filled or
until all data within the page is
filled.(2)
SDI
SII
SDO
0_dddd_dddd_00
0_0011_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0111_1101_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0111_1100_00
x_xxxx_xxxx_xx
Instr 5-7.
Load Flash
High Address
and Program
Page
SDI
SII
SDO
0_0000_000a_00
0_0001_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_0100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
x_xxxx_xxxx_xx
Wait after Instr 3 until SDO
goes high. Repeat Instr. 2 - 3
for each loaded Flash Page
until the entire Flash or all data
is programmed. Repeat Instr. 1
for a new 256 byte page.(2)171
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ATtiny24A/44A/84A
Load “Read
Flash”
Command
SDI
SII
SDO
0_0000_0010_00
0_0100_1100_00
x_xxxx_xxxx_xx
Enter Flash Read mode.
Read Flash
Low and High
Bytes
SDI
SII
SDO
0_bbbb_bbbb_00
0_0000_1100_00
x_xxxx_xxxx_xx
0_0000_000a_00
0_0001_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1000_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
q_qqqq_qqqx_xx
Repeat Instr. 1, 3 - 6 for each
new address. Repeat Instr. 2 for
a new 256 byte page.
SDI
SII
SDO
0_0000_0000_00
0_0111_1000_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0111_1100_00
p_pppp_pppx_xx
Instr 5 - 6.
Load “Write
EEPROM”
Command
SDI
SII
SDO
0_0001_0001_00
0_0100_1100_00
x_xxxx_xxxx_xx
Enter EEPROM Programming
mode.
Load
EEPROM
Page Buffer
SDI
SII
SDO
0_bbbb_bbbb_00
0_0000_1100_00
x_xxxx_xxxx_xx
0_aaaa_aaaa_00
0_0001_1100_00
x_xxxx_xxxx_xx
0_eeee_eeee_00
0_0010_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1101_00
x_xxxx_xxxx_xx
Repeat Instr. 1 - 5 until the
entire page buffer is filled or
until all data within the page is
filled.(3)
SDI
SII
SDO
0_0000_0000_00
0_0110_1100_00
x_xxxx_xxxx_xx
Program
EEPROM
Page
SDI
SII
SDO
0_0000_0000_00
0_0110_0100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
x_xxxx_xxxx_xx
Wait after Instr. 2 until SDO
goes high. Repeat Instr. 1 - 2
for each loaded EEPROM page
until the entire EEPROM or all
data is programmed.
Write
EEPROM
Byte
SDI
SII
SDO
0_bbbb_bbbb_00
0_0000_1100_00
x_xxxx_xxxx_xx
0_aaaa_aaaa_00
0_0001_1100_00
x_xxxx_xxxx_xx
0_eeee_eeee_00
0_0010_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1101_00
x_xxxx_xxxx_xx
Repeat Instr. 1 - 6 for each new
address. Wait after Instr. 6 until
SDO goes high.(4)
SDI
SII
SDO
0_0000_0000_00
0_0110_0100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
x_xxxx_xxxx_xx
Instr. 5-6
Load “Read
EEPROM”
Command
SDI
SII
SDO
0_0000_0011_00
0_0100_1100_00
x_xxxx_xxxx_xx
Enter EEPROM Read mode.
Read
EEPROM
Byte
SDI
SII
SDO
0_bbbb_bbbb_00
0_0000_1100_00
x_xxxx_xxxx_xx
0_aaaa_aaaa_00
0_0001_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1000_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
q_qqqq_qqq0_00
Repeat Instr. 1, 3 - 4 for each
new address. Repeat Instr. 2 for
a new 256 byte page.
Write Fuse
Low Bits
SDI
SII
SDO
0_0100_0000_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_A987_6543_00
0_0010_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_0100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
x_xxxx_xxxx_xx
Wait after Instr. 4 until SDO
goes high. Write A - 3 = “0” to
program the Fuse bit.
Write Fuse
High Bits
SDI
SII
SDO
0_0100_0000_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_IHGF_EDCB_00
0_0010_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0111_0100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0111_1100_00
x_xxxx_xxxx_xx
Wait after Instr. 4 until SDO
goes high. Write F - B = “0” to
program the Fuse bit.
Write Fuse
Extended Bits
SDI
SII
SDO
0_0100_0000_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_0000_000J_00
0_0010_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_0110_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1110_00
x_xxxx_xxxx_xx
Wait after Instr. 4 until SDO
goes high. Write J = “0” to
program the Fuse bit.
Table 19-16. High-voltage Serial Programming Instruction Set for ATtiny24A/44A/84A (Continued)
Instruction
Instruction Format
Instr.1/5 Instr.2/6 Instr.3/7 Instr.4 Operation Remarks172
8183F–AVR–06/12
ATtiny24A/44A/84A
Notes: 1. a = address high bits, b = address low bits, d = data in high bits, e = data in low bits, p = data out high bits, q = data out low
bits, x = don’t care, 1 = Lock Bit1, 2 = Lock Bit2, 3 = CKSEL0 Fuse, 4 = CKSEL1 Fuse, 5 = CKSEL2 Fuse, 6 = CKSEL3
Fuse, 7 = SUT0 Fuse, 8 = SUT1 Fuse, 9 = CKOUT Fuse, A = CKDIV8 Fuse, B = BODLEVEL0 Fuse, C = BODLEVEL1
Fuse, D= BODLEVEL2 Fuse, E = EESAVE Fuse, F = WDTON Fuse, G = SPIEN Fuse, H = DWEN Fuse, I = RSTDISBL
Fuse, J = SELFPRGEN Fuse
2. For page sizes less than 256 words, parts of the address (bbbb_bbbb) will be parts of the page address.
3. For page sizes less than 256 bytes, parts of the address (bbbb_bbbb) will be parts of the page address.
4. The EEPROM is written page-wise. But only the bytes that are loaded into the page are actually written to the EEPROM.
Page-wise EEPROM access is more efficient when multiple bytes are to be written to the same page. Note that auto-erase
of EEPROM is not available in High-voltage Serial Programming, only in SPI Programming.
Write Lock
Bits
SDI
SII
SDO
0_0010_0000_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_0000_0021_00
0_0010_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_0100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
x_xxxx_xxxx_xx
Wait after Instr. 4 until SDO
goes high. Write 2 - 1 = “0” to
program the Lock Bit.
Read Fuse
Low Bits
SDI
SII
SDO
0_0000_0100_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1000_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
A_9876_543x_xx
Reading A - 3 = “0” means the
Fuse bit is programmed.
Read Fuse
High Bits
SDI
SII
SDO
0_0000_0100_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0111_1010_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0111_1100_00
I_HGFE_DCBx_xx
Reading F - B = “0” means the
Fuse bit is programmed.
Read Fuse
Extended Bits
SDI
SII
SDO
0_0000_0100_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1010_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1110_00
x_xxxx_xxJx_xx
Reading J = “0” means the
Fuse bit is programmed.
Read Lock
Bits
SDI
SII
SDO
0_0000_0100_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0111_1000_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
x_xxxx_x21x_xx
Reading 2, 1 = “0” means the
Lock bit is programmed.
Read
Signature
Bytes
SDI
SII
SDO
0_0000_1000_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_0000_00bb_00
0_0000_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1000_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
q_qqqq_qqqx_xx
Repeats Instr 2 4 for each
signature byte address.
Read
Calibration
Byte
SDI
SII
SDO
0_0000_1000_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0000_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0111_1000_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0111_1100_00
p_pppp_pppx_xx
Load “No
Operation”
Command
SDI
SII
SDO
0_0000_0000_00
0_0100_1100_00
x_xxxx_xxxx_xx
Table 19-16. High-voltage Serial Programming Instruction Set for ATtiny24A/44A/84A (Continued)
Instruction
Instruction Format
Instr.1/5 Instr.2/6 Instr.3/7 Instr.4 Operation Remarks173
8183F–AVR–06/12
ATtiny24A/44A/84A
20. Electrical Characteristics
20.1 Absolute Maximum Ratings*
20.2 DC Characteristics
Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature ..................................... -65°C to +150°C
Voltage on any Pin except RESET
with respect to Ground ................................-0.5V to VCC+0.5V
Voltage on RESET with respect to Ground......-0.5V to +13.0V
Maximum Operating Voltage ............................................ 6.0V
DC Current per I/O Pin ............................................... 40.0 mA
DC Current VCC and GND Pins ................................ 200.0 mA
Table 20-1. DC Characteristics. TA = -40°C to +85°C
Symbol Parameter Condition Min Typ(1) Max Units
VIL
Input Low Voltage
VCC = 1.8V - 2.4V -0.5 0.2VCC(3) V
VCC = 2.4V - 5.5V -0.5 0.3VCC(3) V
Input Low Voltage,
RESET Pin as Reset (4) VCC = 1.8V - 5.5 -0.5 0.2VCC(3)
VIH
Input High-voltage
Except RESET pin
VCC = 1.8V - 2.4V 0.7VCC(2) VCC +0.5 V
VCC = 2.4V - 5.5V 0.6VCC(2) VCC +0.5 V
Input High-voltage
RESET pin as Reset (4) VCC = 1.8V to 5.5V 0.9VCC(2) VCC +0.5 V
VOL
Output Low Voltage (5)
Except RESET pin (7)
IOL = 10 mA, VCC = 5V 0.6 V
IOL = 5 mA, VCC = 3V 0.5 V
VOH
Output High-voltage (6)
Except RESET pin (7)
IOH = -10 mA, VCC = 5V 4.3 V
IOH = -5 mA, VCC = 3V 2.5 V
ILIL
Input Leakage
Current I/O Pin
VCC = 5.5V, pin low
(absolute value) < 0.05 1(8) µA
ILIH
Input Leakage
Current I/O Pin
VCC = 5.5V, pin high
(absolute value) < 0.05 1(8) µA
RPU
Pull-up Resistor, I/O Pin VCC = 5.5V, input low 20 50 kΩ
Pull-up Resistor, Reset Pin VCC = 5.5V, input low 30 60 kΩ174
8183F–AVR–06/12
ATtiny24A/44A/84A
Notes: 1. Typical values at 25°C.
2. “Min” means the lowest value where the pin is guaranteed to be read as high.
3. “Max” means the highest value where the pin is guaranteed to be read as low.
4. Not tested in production.
5. Although each I/O port can sink more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state
conditions (non-transient), the sum of all IOL (for all ports) should not exceed 60 mA. If IOL exceeds the test conditions, VOL
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test condition.
6. Although each I/O port can source more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state
conditions (non-transient), the sum of all IOH (for all ports) should not exceed 60 mA. If IOH exceeds the test condition, VOH
may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition.
7. The RESET pin must tolerate high voltages when entering and operating in programming modes and, as a consequence,
has a weak drive strength as compared to regular I/O pins. See Figure 21-87, Figure 21-88, Figure 21-89, and Figure 21-90
(starting on page 226).
8. These are test limits, which account for leakage currents of the test environment. Actual device leakage currents are lower.
9. Values are with external clock using methods described in “Minimizing Power Consumption” on page 35. Power Reduction
is enabled (PRR = 0xFF) and there is no I/O drive.
10. BOD Disabled.
20.3 Speed
The maximum operating frequency of the device depends on VCC. As shown in Figure 20-1, the
relationship between maximum frequency and VCC is linear in the region 1.8V < VCC < 4.5V.
Figure 20-1. Maximum Frequency vs. VCC
ICC
Supply Current,
Active Mode (9)
f = 1 MHz, VCC = 2V 0.25 0.5 mA
f = 4 MHz, VCC = 3V 1.2 2 mA
f = 8 MHz, VCC = 5V 4.4 7 mA
Supply Current,
Idle Mode (9)
f = 1 MHz, VCC = 2V 0.04 0.2 mA
f = 4 MHz, VCC = 3V 0.25 0.6 mA
f = 8 MHz, VCC = 5V 1.3 2 mA
Supply Current,
Power-Down Mode (10)
WDT enabled, VCC = 3V 4 10 µA
WDT disabled, VCC = 3V 0.13 2 µA
Table 20-1. DC Characteristics. TA = -40°C to +85°C (Continued)
Symbol Parameter Condition Min Typ(1) Max Units
4 MHz
1.8V 5.5V 4.5V
20 MHz175
8183F–AVR–06/12
ATtiny24A/44A/84A
20.4 Clock Characteristics
20.4.1 Accuracy of Calibrated Internal Oscillator
It is possible to manually calibrate the internal oscillator to be more accurate than default factory
calibration. Note that the oscillator frequency depends on temperature and voltage. Voltage and
temperature characteristics can be found in Figure 21-109 on page 237 and Figure 21-110 on
page 238.
Notes: 1. Accuracy of oscillator frequency at calibration point (fixed temperature and fixed voltage).
20.4.2 External Clock Drive
Figure 20-2. External Clock Drive Waveform
Table 20-2. Calibration Accuracy of Internal RC Oscillator
Calibration
Method Target Frequency VCC Temperature
Accuracy at given voltage
& temperature (1)
Factory
Calibration 8.0 MHz 3V 25°C ±10%
User
Calibration
Fixed frequency within:
7.3 – 8.1 MHz
Fixed voltage within:
1.8V – 5.5V
Fixed temperature
within:
-40°C to +85°C
±1%
VIL1
VIH1
Table 20-3. External Clock Drive Characteristics
Symbol Parameter
VCC = 1.8 - 5.5V VCC = 2.7 - 5.5V VCC = 4.5 - 5.5V
Min. Max. Min. Max. Min. Max. Units
1/tCLCL Clock Frequency 0 4 0 10 0 20 MHz
tCLCL Clock Period 250 100 50 ns
tCHCX High Time 100 40 20 ns
tCLCX Low Time 100 40 20 ns
tCLCH Rise Time 2.0 1.6 0.5 µs
tCHCL Fall Time 2.0 1.6 0.5 µs
ΔtCLCL Change in period from one clock cycle to the next 2 2 2 %176
8183F–AVR–06/12
ATtiny24A/44A/84A
20.5 System and Reset Characteristics
Note: 1. Values are guidelines, only
20.5.1 Power-On Reset
Note: 1. Values are guidelines, only
2. Threshold where device is released from reset when voltage is rising
3. The Power-on Reset will not work unless the supply voltage has been below VPOA
20.5.2 Brown-Out Detection
Note: 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where
this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees
that a Brown-out Reset will occur before VCC drops to a voltage where correct
operation of the microcontroller is no longer guaranteed.
Table 20-4. Reset, Brown-out, and Internal Voltage Characteristics
Symbol Parameter Condition Min(1) Typ(1) Max(1) Units
VRST RESET pin threshold voltage 0.2 VCC 0.9VCC V
tRST
Minimum pulse width on
RESET pin
VCC = 1.8V
VCC = 3V
VCC = 5V
2000
700
400
ns
VHYST Brown-out Detector hysteresis 50 mV
tBOD
Minimum pulse width on
Brown-out Reset 2 µs
VBG
Internal bandgap reference
voltage
VCC = 5V
TA = 25°C 1.0 1.1 1.2 V
tBG
Internal bandgap reference
start-up time
VCC = 5V
TA = 25°C 40 70 µs
IBG
Internal bandgap reference
current consumption
VCC = 5V
TA = 25°C 15 µA
Table 20-5. Characteristics of Enhanced Power-On Reset. TA = = -40°C to +85°C
Symbol Parameter Min(1) Typ(1) Max(1) Units
VPOR Release threshold of power-on reset (2) 1.1 1.4 1.6 V
VPOA Activation threshold of power-on reset (3) 0.6 1.3 1.6 V
SRON Power-On Slope Rate 0.01 V/ms
Table 20-6. VBOT vs. BODLEVEL Fuse Coding
BODLEVEL[2:0] Fuses Min(1) Typ(1) Max(1) Units
111 BOD Disabled
110 1.7 1.8 2.0
101 2.5 2.7 2.9 V
100 4.1 4.3 4.5
0XX Reserved177
8183F–AVR–06/12
ATtiny24A/44A/84A
20.6 ADC Characteristics
Table 20-7. ADC Characteristics, Single Ended Channels. T = -40°C to +85°C
Symbol Parameter Condition Min Typ Max Units
Resolution 10 Bits
Absolute accuracy
(Including INL, DNL, and
Quantization, Gain and Offset
Errors)
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz 2.0 LSB
VREF = 4V, VCC = 4V,
ADC clock = 1 MHz 2.5 LSB
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz
Noise Reduction Mode
1.5 LSB
VREF = 4V, VCC = 4V,
ADC clock = 1 MHz
Noise Reduction Mode
2.0 LSB
Integral Non-Linearity (INL)
(Accuracy after Offset and
Gain Calibration)
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz 1.0 LSB
Differential Non-linearity
(DNL)
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz 0.5 LSB
Gain Error VREF = 4V, VCC = 4V,
ADC clock = 200 kHz 2.0 LSB
Offset Error (Absolute) VREF = 4V, VCC = 4V,
ADC clock = 200 kHz 1.5 LSB
Conversion Time Free Running Conversion 14 280 µs
Clock Frequency 50 1000 kHz
VIN Input Voltage GND VREF V
Input Bandwidth 38.5 kHz
AREF External Voltage Reference 2.0 VCC V
VINT Internal Voltage Reference 1.0 1.1 1.2 V
RREF Reference Input Resistance 32 kΩ
RAIN Analog Input Resistance 100 MΩ
ADC Conversion Output 0 1023 LSB178
8183F–AVR–06/12
ATtiny24A/44A/84A
Table 20-8. ADC Characteristics, Differential Channels (Unipolar Mode), TA = -40°C to +85°C
Symbol Parameter Condition Min Typ Max Units
Resolution
Gain = 1x 10 Bits
Gain = 20x 10 Bits
Absolute accuracy
(Including INL, DNL, and Quantization, Gain
and Offset Errors)
Gain = 1x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz
10 LSB
Gain = 20x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz
15 LSB
Integral Non-Linearity (INL)
(Accuracy after Offset and Gain Calibration)
Gain = 1x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz
4 LSB
Gain = 20x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz
10 LSB
Gain Error
Gain = 1x 10 LSB
Gain = 20x 15 LSB
Offset Error
Gain = 1x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz
3 LSB
Gain = 20x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz
4 LSB
Conversion Time Free Running Conversion 70 280 µs
Clock Frequency 50 200 kHz
VIN Input Voltage GND VCC V
VDIFF Input Differential Voltage VREF/Gain V
Input Bandwidth 4 kHz
AREF External Reference Voltage 2.0 VCC - 1.0 V
VINT Internal Voltage Reference 1.0 1.1 1.2 V
RREF Reference Input Resistance 32 kΩ
RAIN Analog Input Resistance 100 MΩ
ADC Conversion Output 0 1023 LSB179
8183F–AVR–06/12
ATtiny24A/44A/84A
Table 20-9. ADC Characteristics, Differential Channels (Bipolar Mode), TA = -40°C to +85°C
Symbol Parameter Condition Min Typ Max Units
Resolution
Gain = 1x 10 Bits
Gain = 20x 10 Bits
Absolute accuracy
(Including INL, DNL, and Quantization, Gain
and Offset Errors)
Gain = 1x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz
8 LSB
Gain = 20x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz
8 LSB
Integral Non-Linearity (INL)
(Accuracy after Offset and Gain Calibration)
Gain = 1x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz
4 LSB
Gain = 20x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz
5 LSB
Gain Error
Gain = 1x 4 LSB
Gain = 20x 5 LSB
Offset Error
Gain = 1x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz
3 LSB
Gain = 20x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz
4 LSB
Conversion Time Free Running Conversion 70 280 µs
Clock Frequency 50 200 kHz
VIN Input Voltage GND VCC V
VDIFF Input Differential Voltage VREF/Gain V
Input Bandwidth 4 kHz
AREF External Reference Voltage 2.0 VCC - 1.0 V
VINT Internal Voltage Reference 1.0 1.1 1.2 V
RREF Reference Input Resistance 32 kΩ
RAIN Analog Input Resistance 100 MΩ
ADC Conversion Output -512 511 LSB180
8183F–AVR–06/12
ATtiny24A/44A/84A
20.7 Analog Comparator Characteristics
Note: All parameters are based on simulation results and are not tested in production
20.8 Serial Programming Characteristics
Figure 20-3. Serial Programming Timing
Figure 20-4. Serial Programming Waveform
Table 20-10. Analog Comparator Characteristics, TA = -40°C to +85°C
Symbol Parameter Condition Min Typ Max Units
VAIO Input Offset Voltage VCC = 5V, VIN = VCC / 2 < 10 40 mV
ILAC Input Leakage Current VCC = 5V, VIN = VCC / 2 -50 50 nA
tAPD
Analog Propagation Delay
(from saturation to slight overdrive)
VCC = 2.7V 750
ns
VCC = 4.0V 500
Analog Propagation Delay
(large step change)
VCC = 2.7V 100
VCC = 4.0V 75
tDPD Digital Propagation Delay VCC = 1.8V - 5.5 1 2 CLK
Table 20-11. Serial Programming Characteristics, TA = -40°C to +85°C, VCC = 1.8 - 5.5V
(Unless Otherwise Noted)
Symbol Parameter Min Typ Max Units
1/tCLCL Oscillator Frequency 0 4 MHz
tCLCL Oscillator Period 250 ns
1/tCLCL Oscillator Freq. (VCC = 4.5V - 5.5V) 0 20 MHz
MOSI
MISO
SCK
t
OVSH
t
SHSL
t t
SHOX SLSH
MSB
MSB
LSB
LSB
SERIAL CLOCK INPUT
(SCK)
SERIAL DATA INPUT
(MOSI)
(MISO)
SAMPLE
SERIAL DATA OUTPUT181
8183F–AVR–06/12
ATtiny24A/44A/84A
Note: 1. 2 tCLCL for fck < 12 MHz, 3 tCLCL for fck >= 12 MHz
20.9 High-Voltage Serial Programming Characteristics
Figure 20-5. High-voltage Serial Programming Timing
tCLCL Oscillator Period (VCC = 4.5V - 5.5V) 50 ns
tSHSL SCK Pulse Width High 2 tCLCL(1) ns
tSLSH SCK Pulse Width Low 2 tCLCL(1) ns
tOVSH MOSI Setup to SCK High tCLCL ns
tSHOX MOSI Hold after SCK High 2 tCLCL ns
Table 20-11. Serial Programming Characteristics, TA = -40°C to +85°C, VCC = 1.8 - 5.5V
(Unless Otherwise Noted)
Symbol Parameter Min Typ Max Units
Table 20-12. High-voltage Serial Programming Characteristics
TA = 25°C, VCC = 5V (Unless otherwise noted)
Symbol Parameter Min Typ Max Units
tSHSL SCI (PB0) Pulse Width High 125 ns
tSLSH SCI (PB0) Pulse Width Low 125 ns
tIVSH SDI (PA6), SII (PB1) Valid to SCI (PB0) High 50 ns
tSHIX SDI (PA6), SII (PB1) Hold after SCI (PB0) High 50 ns
tSHOV SCI (PB0) High to SDO (PA4) Valid 16 ns
tWLWH_PFB Wait after Instr. 3 for Write Fuse Bits 2.5 ms
SDI (PA6), SII (PA5)
SDO (PA4)
SCI (PB0)
t
IVSH
t
SHSL
t t
SHIX SLSH
t
SHOV182
8183F–AVR–06/12
ATtiny24A/44A/84A
21. Typical Characteristics
The data contained in this section is largely based on simulations and characterization of similar
devices in the same process and design methods. Thus, the data should be treated as indications
of how the part will behave.
The following charts show typical behavior. These figures are not tested during manufacturing.
During characterisation devices are operated at frequencies higher than test limits but they are
not guaranteed to function properly at frequencies higher than the ordering code indicates.
All current consumption measurements are performed with all I/O pins configured as inputs and
with internal pull-ups enabled. Current consumption is a function of several factors such as operating
voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed
and ambient temperature. The dominating factors are operating voltage and frequency.
A sine wave generator with rail-to-rail output is used as clock source but current consumption in
Power-Down mode is independent of clock selection. The difference between current consumption
in Power-Down mode with Watchdog Timer enabled and Power-Down mode with Watchdog
Timer disabled represents the differential current drawn by the Watchdog Timer.
The current drawn from pins with a capacitive load may be estimated (for one pin) as follows:
where VCC = operating voltage, CL = load capacitance and fSW = average switching frequency of
I/O pin.
21.1 Supply Current of I/O Modules
The tables and formulas below can be used to calculate the additional current consumption for
the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules
is controlled by the Power Reduction Register. See “Power Reduction Register” on page 35 for
details.
Table 21-2 below can be used for calculating typical current consumption for other supply voltages
and frequencies than those mentioned in the Table 21-1 above.
I
CP VCC CL × × f
SW ≈
Table 21-1. Additional Current Consumption for the different I/O modules (absolute values)
PRR bit
Typical numbers
VCC = 2V, f = 1 MHz VCC = 3V, f = 4 MHz VCC = 5V, f = 8 MHz
PRTIM1 1.6 µA 11 µA 48 µA
PRTIM0 4.4 µA 29 µA 120 µA
PRUSI 1.6 µA 11 µA 48 µA
PRADC 8.0 µA 55 µA 240 µA183
8183F–AVR–06/12
ATtiny24A/44A/84A
21.1.1 Example
Calculate the expected current consumption in idle mode with USI, TIMER0, and ADC enabled
at VCC = 2.0V and f = 1 MHz. From Table 21-2 on page 183, third column, we see that we need
to add 5% for the USI, 10% for TIMER0, and 20% for the ADC. Reading from Figure 21-61 on
page 213, we find that current consumption in idle mode at 2V and 1 MHz is about 0.04 mA. The
total current consumption in idle mode with USI, TIMER0, and ADC enabled is therefore:
21.2 ATtiny24A
21.2.1 Current Consumption in Active Mode
Figure 21-1. Active Supply Current vs. Low Frequency
0.1 - 1.0 MHz, PRR = 0xFF
Table 21-2. Additional Current Consumption (percentage) in Active and Idle mode
PRR bit
Current consumption additional to
active mode with external clock
(see Figure 21-56 and Figure 21-57)
Current consumption additional to
idle mode with external clock
(see Figure 21-61 and Figure 21-62)
PRTIM1 1 % 5 %
PRTIM0 3 % 10 %
PRUSI 1 % 5 %
PRADC 5 % 20 %
ICCTOT ≈ ≈ 0,05mA × ( ) 1 0,05 0,10 0,20 +++ 0,06mA
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0
0,2
0,4
0,6
0,8
1
0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1
Frequency (MHz)
ICC (mA)184
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-2. Active Supply Current vs. Frequency
1 - 20 MHz, PRR = 0xFF
Figure 21-3. Active Supply Current vs. VCC
Internal RC Oscillator, 8 MHz
0
2
4
6
8
10
12
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)
ICC (mA)
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
85 °C
25 °C
-40 °C
0
1
2
3
4
5
6
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (mA)185
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-4. Active Supply Current vs. VCC
Internal RC Oscillator, 1 MHz
Figure 21-5. Active Supply Current vs. VCC
Internal RC Oscillator, 128 kHz
85 °C
25 °C
-40 °C
0
0,2
0,4
0,6
0,8
1
1,2
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (mA)
85 °C
25 °C
-40 °C
0
0,02
0,04
0,06
0,08
0,1
0,12
0,14
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (mA)186
8183F–AVR–06/12
ATtiny24A/44A/84A
21.2.2 Current Consumption in Idle Mode
Figure 21-6. Idle Supply Current vs. Low Frequency
0.1 - 1.0 MHz, PRR = 0xFF
Figure 21-7. Idle Supply Current vs. Frequency
1 - 20 MHz, PRR = 0xFF
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0
0,02
0,04
0,06
0,08
0,1
0,12
0,14
0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1
Frequency (MHz)
ICC (mA)
0
0,5
1
1,5
2
2,5
3
3,5
4
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)
ICC (mA)
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V187
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-8. Idle Supply Current vs. VCC
Internal RC Oscillator, 8 MHz
Figure 21-9. Idle Supply Current vs. VCC
Internal RC Oscillator, 1 MHz
85 °C
25 °C
-40 °C
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,6
1,8
2
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (mA)
85 °C
25 °C
-40 °C
0
0,05
0,1
0,15
0,2
0,25
0,3
0,35
0,4
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (mA)188
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-10. Idle Supply Current vs. VCC
Internal RC Oscillator, 128 kHz
21.2.3 Current Consumption in Power-down Mode
Figure 21-11. Power-down Supply Current vs. VCC
Watchdog Timer Disabled
85 °C
25 °C
-40 °C
0
0,005
0,01
0,015
0,02
0,025
0,03
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (mA)
85 °C
25 °C
-40 °C
0
0,2
0,4
0,6
0,8
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (uA)189
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-12. Power-down Supply Current vs. VCC
Watchdog Timer Enabled
21.2.4 Current Consumption in Reset
Figure 21-13. Reset Supply Current vs. VCC
0.1 - 1.0 MHz, Excluding Current through Reset Pull-up
85 °C
25 °C
-40 °C
0
2
4
6
8
10
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (uA)
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0
0,02
0,04
0,06
0,08
0,1
0,12
0,14
0,16
0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1
Frequency (MHz)
ICC (mA)190
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-14. Reset Supply Current vs. VCC
1 - 20 MHz, Excluding Current through Reset Pull-up
21.2.5 Current Consumption of Peripheral Units
Figure 21-15. ADC Current vs. VCC
4 MHz Frequency
0
0,5
1
1,5
2
2,5
3
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)
ICC (mA)
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0
100
200
300
400
500
600
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (uA)191
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-16. AREF Pin Current vs. Pin Voltage
Figure 21-17. Analog Comparator Current vs. VCC
4 MHz Frequency
0
20
40
60
80
100
120
140
160
180
200
1,5 2 2,5 3 3,5 4 4,5 5 5,5
AREF (V)
AREF pin current (uA)
0
20
40
60
80
100
120
140
160
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (uA)192
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-18. Programming Current vs. VCC
Figure 21-19. Brownout Detector Current vs. VCC
BOD Level = 1.8V
85 °C
25 °C
-40 °C
0
1000
2000
3000
4000
5000
6000
7000
8000
9000
10000
1,5 2,5 3,5 4,5 5,5
VCC (V)
ICC (uA)
85 °C
25 °C
-40 °C
0
5
10
15
20
25
30
35
40
45
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (uA)193
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-20. Watchdog Timer Current vs. VCC
21.2.6 Pull-up Resistors
Figure 21-21. Pull-up Resistor Current vs. Input Voltage
I/O Pin, VCC = 1.8V
85 °C
25 °C
-40 °C
0
1
2
3
4
5
6
7
8
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (uA)
85 °C
-40 °C
25 °C
0
10
20
30
40
50
60
0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
VOP (V)
IOP (uA)194
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-22. Pull-up Resistor Current vs. Input Voltage
I/O Pin, VCC = 2.7V
Figure 21-23. Pull-up Resistor Current vs. Input Voltage
I/O Pin, VCC = 5V
0
10
20
30
40
50
60
70
80
0 0,5 1 1,5 2 2,5 3
VOP (V)
IOP (uA)
85 °C
-40 °C
25 °C
0
20
40
60
80
100
120
140
160
0 1 2 3 4 5 6
VOP (V)
IOP (uA)
85 °C
-40 °C
25 °C195
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-24. Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 1.8V
Figure 21-25. Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 2.7V
0
5
10
15
20
25
30
35
40
0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
VRESET (V)
IRESET (uA)
85 °C
-40 °C
25 °C
0
10
20
30
40
50
60
0 0,5 1 1,5 2 2,5 3
VRESET (V)
IRESET (uA)
85 °C
-40 °C
25 °C196
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-26. Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 5V
21.2.7 Output Driver Strength
Figure 21-27. VOL: Output Voltage vs. Sink Current
I/O Pin, VCC = 3V
0
20
40
60
80
100
120
0 1 2 3 4 5 6
VRESET (V)
IRESET (uA)
85 °C
-40 °C
25 °C
85 °C
25 °C
-40 °C
0
0,2
0,4
0,6
0,8
1
1,2
0 5 10 15 20
IOL (mA)
VOL (V)197
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-28. VOL: Output Voltage vs. Sink Current
I/O Pin, VCC = 5V
Figure 21-29. VOH: Output Voltage vs. Source Current
I/O Pin, VCC = 3V
85 °C
25 °C
-40 °C
0
0,1
0,2
0,3
0,4
0,5
0,6
0 5 10 15 20
IOL (mA)
VOL (V)
85 °C
25 °C
-40 °C
1,8
2
2,2
2,4
2,6
2,8
3
3,2
0 5 10 15 20
IOH (mA)
VOH (V)198
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-30. VOH: Output Voltage vs. Source Current
I/O Pin, VCC = 5V
Figure 21-31. VOL: Output Voltage vs. Sink Current
Reset Pin as I/O, VCC = 3V
85 °C
25 °C
-40 °C
4,2
4,4
4,6
4,8
5
5,2
0 5 10 15 20
IOH (mA)
VOH (V)
85 °C
25 °C
-40 °C
0
0,2
0,4
0,6
0,8
1
1,2
1,4
0 0,5 1 1,5 2 2,5 3
IOL (mA)
VOL (V)199
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-32. VOL: Output Voltage vs. Sink Current
Reset Pin as I/O, VCC = 5V
Figure 21-33. VOH: Output Voltage vs. Source Current
Reset Pin as I/O, VCC = 3V
85 °C
25 °C
-40 °C
0
0,2
0,4
0,6
0,8
1
1,2
0 0,5 1 1,5 2 2,5 3 3,5 4 4,5 5
IOL (mA)
VOL (V)
85 °C
25 °C
-40 °C
0
0,5
1
1,5
2
2,5
3
0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
IOH (mA)
VOH (V)200
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-34. VOH: Output Voltage vs. Source Current
Reset Pin as I/O, VCC = 5V
21.2.8 Input Threshold and Hysteresis (for I/O Ports)
Figure 21-35. VIH: Input Threshold Voltage vs. VCC
I/O Pin, Read as ‘1’
85 °C
25 °C
-40 °C
0
0,5
1
1,5
2
2,5
3
3,5
4
4,5
0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
IOH (mA)
VOH (V)
85 °C
25 °C
-40 °C
0
0,5
1
1,5
2
2,5
3
3,5
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Threshold (V)201
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-36. VIL: Input Threshold Voltage vs. VCC
I/O Pin, Read as ‘0’
Figure 21-37. VIH-VIL: Input Hysteresis vs. VCC
I/O Pin
0
0,5
1
1,5
2
2,5
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Threshold (V)
85 °C
25 °C
-40 °C
85 °C
25 °C
-40 °C
0
0,1
0,2
0,3
0,4
0,5
0,6
0,7
0,8
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Input Hysteresis (V)202
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-38. VIH: Input Threshold Voltage vs. VCC
Reset Pin as I/O, Read as ‘1’
Figure 21-39. VIL: Input Threshold Voltage vs. VCC
Reset Pin as I/O, Read as ‘0’
85 °C
25 °C
-40 °C
0
0,5
1
1,5
2
2,5
3
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Threshold (V)
85 °C
25 °C
-40 °C
0
0,5
1
1,5
2
2,5
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Threshold (V)203
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-40. VIH-VIL: Input Hysteresis vs. VCC
Reset Pin as I/O
21.2.9 BOD, Bandgap and Reset
Figure 21-41. BOD Threshold vs. Temperature
BODLEVEL is 4.3V
85 °C
25 °C
-40 °C
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
Input Hysteresis (V)
RISING VCC
FALLING VCC
4,26
4,28
4,3
4,32
4,34
4,36
4,38
4,4
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature (C)
Threshold (V)204
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-42. BOD Threshold vs. Temperature
BODLEVEL is 2.7V
Figure 21-43. BOD Threshold vs. Temperature
BODLEVEL is 1.8V
2,68
2,7
2,72
2,74
2,76
2,78
2,8
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature (C)
Threshold (V)
RISING VCC
FALLING VCC
RISING VCC
FALLING VCC
1,77
1,78
1,79
1,8
1,81
1,82
1,83
1,84
1,85
1,86
1,87
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature (C)
Threshold (V)205
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-44. Bandgap Voltage vs. Supply Voltage
Figure 21-45. Bandgap Voltage vs. Temperature
1
1,02
1,04
1,06
1,08
1,1
1,12
1,14
1,16
1,18
1,2
1,5 2 2,5 3 3,5 4 4,5 5 5,5
Vcc (V)
Bandgap Voltage (V)
1
1,02
1,04
1,06
1,08
1,1
1,12
1,14
1,16
1,18
1,2
-40 -20 0 20 40 60 80 100
Temperature (C)
Bandgap Voltage (V)206
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-46. VIH: Input Threshold Voltage vs. VCC
Reset Pin, Read as ‘1’
Figure 21-47. VIL: Input Threshold Voltage vs. VCC
Reset Pin, Read as ‘0’
85 °C
25 °C
-40 °C
0
0,5
1
1,5
2
2,5
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Threshold (V)
85 °C
25 °C
-40 °C
0
0,5
1
1,5
2
2,5
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Threshold (V)207
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-48. VIH-VIL: Input Hysteresis vs. VCC
Reset Pin
Figure 21-49. Minimum Reset Pulse Width vs. VCC
85 °C
25 °C
-40 °C
0
0,1
0,2
0,3
0,4
0,5
0,6
0,7
0,8
0,9
1
1 1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Input Hysteresis (V)
85 °C
25 °C
-40 °C
0
200
400
600
800
1000
1200
1400
1600
1800
2000
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Pulsewidth (ns)208
8183F–AVR–06/12
ATtiny24A/44A/84A
21.2.10 Analog Comparator Offset
Figure 21-50. Analog Comparator Offset
VCC = 5V
21.2.11 Internal Oscillator Speed
Figure 21-51. Watchdog Oscillator Frequency vs. VCC
85
25
-40
-0.008
-0.006
-0.004
-0.002
0
0.002
0.004
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VIN (V)
Offset (V)
85 °C
25 °C
-40 °C
112
114
116
118
120
122
124
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
FRC (kHz)209
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-52. Watchdog Oscillator Frequency vs. Temperature
Figure 21-53. Calibrated 8 MHz RC Oscillator Frequency vs. VCC
5.5 V
3.0 V
1.8 V
112
114
116
118
120
122
124
-40 -20 0 20 40 60 80 100
Temperature (C)
FRC (kHz)
85 °C
25 °C
-40 °C
7,4
7,6
7,8
8
8,2
8,4
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
FRC (MHz)210
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-54. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature
Figure 21-55. Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value
VCC = 3V
5.5 V
3.0 V
1.8 V
7,5
7,6
7,7
7,8
7,9
8
8,1
8,2
8,3
8,4
-40 -20 0 20 40 60 80 100
Temperature (C)
FRC (MHz)
85 °C
25 °C
-40 °C
0
4
8
12
16
20
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
OSCCAL (X1)
FRC (MHz)211
8183F–AVR–06/12
ATtiny24A/44A/84A
21.3 ATtiny44A
21.3.1 Current Consumption in Active Mode
Figure 21-56. Active Supply Current vs. Low Frequency
0.1 - 1.0 MHz, PRR = 0xFF
Figure 21-57. Active Supply Current vs. frequency
1 - 20 MHz, PRR = 0xFF
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0
0.2
0.4
0.6
0.8
1
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)
ICC (mA)
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0
2
4
6
8
10
12
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)
ICC (mA)212
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-58. Active Supply Current vs. VCC
Internal RC Oscillator, 8 MHz
Figure 21-59. Active Supply Current vs. VCC
Internal RC Oscillator, 1 MHz
85 °C
25 °C
-40 °C
0
1
2
3
4
5
6
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
ICC (mA)
85 °C
25 °C
-40 °C
0
0.2
0.4
0.6
0.8
1
1.2
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
ICC (mA)213
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-60. Active Supply Current vs. VCC
Internal RC Oscillator, 128 kHz
21.3.2 Current Consumption in Idle Mode
Figure 21-61. Idle Supply Current vs. Low Frequency
0.1 - 1.0 MHz, PRR = 0xFF
85 °C
25 °C
-40 °C
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
ICC (mA)
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0.2
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)
ICC (mA)214
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-62. Idle Supply Current vs. Frequency
1 - 20 MHz, PRR = 0xFF
Figure 21-63. Idle Supply Current vs. VCC
Internal RC Oscillator, 8 MHz
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V 0
0.5
1
1.5
2
2.5
3
3.5
4
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)
ICC (mA)
85 °C
25 °C
-40 °C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
ICC (mA)215
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-64. Idle Supply Current vs. VCC
Internal RC Oscillator, 1 MHz
Figure 21-65. Idle Supply Current vs. VCC
Internal RC Oscillator, 128 kHz
85 °C
25 °C
-40 °C
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
ICC (mA)
85 °C
25 °C
-40 °C
0
0.005
0.01
0.015
0.02
0.025
0.03
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
ICC (mA)216
8183F–AVR–06/12
ATtiny24A/44A/84A
21.3.3 Standby Supply Current
Figure 21-66. Standby Supply Current vs. VCC
4 MHz External Crystal, 22 pF External Capacitors, Watchdog Timer Disabled
21.3.4 Current Consumption in Power-down Mode
Figure 21-67. Power-down Supply Current vs. VCC
Watchdog Timer Disabled
85 °C
25 °C
-40 °C
0
0.02
0.04
0.06
0.08
0.1
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
ICC (mA)
85 °C
25 °C
-40 °C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
ICC (uA)217
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-68. Power-down Supply Current vs. VCC
Watchdog Timer Enabled
21.3.5 Current Consumption in Reset
Figure 21-69. Reset Supply Current vs. VCC
0.1 - 1.0 MHz, Excluding Current through Reset Pull-up
85 °C
25 °C
-40 °C
0
2
4
6
8
10
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
ICC (uA)
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Frequency (MHz)
ICC (mA)218
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-70. Reset Supply Current vs. VCC
1 - 20 MHz, Excluding Current Through Reset Pull-up
21.3.6 Current Consumption of Peripheral Units
Figure 21-71. ADC Current vs. VCC
4 MHz Frequency
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0
0.5
1
1.5
2
2.5
3
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)
ICC (mA)
0
100
200
300
400
500
600
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
ICC (uA)219
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-72. AREF Pin Current vs. Pin Voltage
Figure 21-73. Analog Comparator Current vs. VCC
4 MHz Frequency
0
20
40
60
80
100
120
140
160
180
1.5 2 2.5 3 3.5 4 4.5 5 5.5
AREF (V)
AREF pin current (uA)
0
20
40
60
80
100
120
140
160
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
ICC (uA)220
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-74. Programming Current vs. VCC
Figure 21-75. Brownout Detector Current vs. VCC
BOD Level = 1.8V
85 °C
25 °C
-40 °C
0
2000
4000
6000
8000
10000
12000
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
ICC (uA)
85 °C
25 °C
-40 °C
0
5
10
15
20
25
30
35
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
ICC (uA)221
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-76. Watchdog Timer Current vs. VCC
21.3.7 Pull-up Resistors
Figure 21-77. Pull-up Resistor Current vs. Input Voltage
I/O Pin, VCC = 1.8V
85 °C
25 °C
-40 °C
0
0.001
0.002
0.003
0.004
0.005
0.006
0.007
0.008
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
ICC (mA)
85 °C
25 °C
-40 °C 0
10
20
30
40
50
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VOP (V)
IOP (uA)222
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-78. Pull-up Resistor Current vs. Input Voltage
I/O Pin, VCC = 2.7V
Figure 21-79. Pull-up Resistor Current vs. Input Voltage
I/O Pin, VCC = 5V
85 °C
25 °C
-40 °C 0
10
20
30
40
50
60
70
80
0 0.5 1 1.5 2 2.5 3
VOP (V)
IOP (uA)
85 °C
25 °C
-40 °C 0
20
40
60
80
100
120
140
160
012345
VOP (V)
IOP (uA)223
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-80. Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 1.8V
Figure 21-81. Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 2.7V
0
5
10
15
20
25
30
35
40
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VRESET (V)
IRESET (uA)
85 °C
25 °C
-40 °C
85 °C
25 °C
0 -40 °C
10
20
30
40
50
60
0 0.5 1 1.5 2 2.5 3
VRESET (V)
IRESET (uA)224
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-82. Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 5V
21.3.8 Output Driver Strength
Figure 21-83. VOL: Output Voltage vs. Sink Current
I/O Pin, VCC = 3V
85 °C
25 °C
-40 °C 0
20
40
60
80
100
120
012345
VRESET (V)
IRESET (uA)
85 °C
25 °C
-40 °C
0
0.2
0.4
0.6
0.8
1
1.2
0 5 10 15 20
IOL (mA)
VOL (V)225
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-84. VOL: Output Voltage vs. Sink Current
I/O Pin, VCC = 5V
Figure 21-85. VOH: Output Voltage vs. Source Current
I/O Pin, VCC = 3V
85 °C
25 °C
-40 °C
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0 5 10 15 20
IOL (mA)
VOL (V)
85 °C
25 °C
-40 °C
1.8
2
2.2
2.4
2.6
2.8
3
3.2
0 5 10 15 20
IOH (mA)
VOH (V)226
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-86. VOH: Output Voltage vs. Source Current
I/O Pin, VCC = 5V
Figure 21-87. VOL: Output Voltage vs. Sink Current
Reset Pin as I/O, VCC = 3V
85 °C
25 °C
-40 °C
4.2
4.4
4.6
4.8
5
5.2
0 5 10 15 20
IOH (mA)
VOH (V)
85 °C
25 °C
-40 °C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0 0.5 1 1.5 2 2.5 3
IOL (mA)
VOL (V)227
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-88. VOL: Output Voltage vs. Sink Current
Reset Pin as I/O, VCC = 5V
Figure 21-89. VOH: Output Voltage vs. Source Current
Reset Pin as I/O, VCC = 3V
85 °C
25 °C
-40 °C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
012345678
IOL (mA)
VOL (V)
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
3
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
IOH (mA)
VOH (V)228
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-90. VOH: Output Voltage vs. Source Current
Reset Pin as I/O, VCC = 5V
21.3.9 Input Threshold and Hysteresis (for I/O Ports)
Figure 21-91. VIH: Input Threshold Voltage vs. VCC
IO Pin, Read as ‘1’
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
IOH (mA)
VOH (V)
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
3
3.5
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
Threshold (V)229
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-92. VIL: Input Threshold Voltage vs. VCC
I/O Pin, Read as ‘0’
Figure 21-93. VIH-VIL: Input Hysteresis vs. VCC
I/O Pin
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
Threshold (V)
85 °C
25 °C
-40 °C
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
Input Hysteresis (V)230
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-94. VIH: Input Threshold Voltage vs. VCC
Reset Pin as I/O, Read as ‘1’
Figure 21-95. VIL: Input Threshold Voltage vs. VCC
Reset Pin as I/O, Read as ‘0’
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
3
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
Threshold (V)
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
Threshold (V)231
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-96. VIH-VIL: Input Hysteresis vs. VCC
Reset Pin as I/O
21.3.10 BOD, Bandgap and Reset
Figure 21-97. BOD Threshold vs. Temperature
BODLEVEL is 4.3V
85 °C
25 °C
-40 °C
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
Input Hysteresis (V)
4.2
4.22
4.24
4.26
4.28
4.3
4.32
4.34
4.36
-40 -20 0 20 40 60 80 100
Temperature (C)
Threshold (V)
RISING VCC
FALLING VCC232
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-98. BOD Threshold vs. Temperature
BODLEVEL is 2.7V
Figure 21-99. BOD Threshold vs. Temperature
BODLEVEL is 1.8V
2.64
2.66
2.68
2.7
2.72
2.74
2.76
2.78
-40 -20 0 20 40 60 80 100
Temperature (C)
Threshold (V)
RISING VCC
FALLING VCC
RISING VCC
FALLING VCC
1.77
1.78
1.79
1.8
1.81
1.82
1.83
1.84
-40 -20 0 20 40 60 80 100
Temperature (C)
Threshold (V)233
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-100. Bandgap Voltage vs. Supply Voltage
Figure 21-101. Bandgap Voltage vs. Temperature
1
1.02
1.04
1.06
1.08
1.1
1.12
1.14
1.16
1.18
1.2
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
Bandgap Voltage (V)
1
1.02
1.04
1.06
1.08
1.1
1.12
1.14
1.16
1.18
1.2
-40 -20 0 20 40 60 80 100
Temperature (C)
Bandgap Voltage (V)234
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-102. VIH: Input Threshold Voltage vs. VCC
Reset Pin, Read as ‘1’
Figure 21-103. VIL: Input Threshold Voltage vs. VCC
Reset Pin, Read as ‘0’
85 °C
25 °C
-40 °C
0
0,5
1
1,5
2
2,5
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Threshold (V)
85 °C
25 °C
-40 °C
0
0,5
1
1,5
2
2,5
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Threshold (V)235
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-104. VIH-VIL: Input Hysteresis vs. VCC
Reset Pin
Figure 21-105. Minimum Reset Pulse Width vs. VCC
85 °C
25 °C
-40 °C
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
Input Hysteresis (V)
85 °C
25 °C
-40 °C
0
200
400
600
800
1000
1200
1400
1600
1800
2000
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
Pulsewidth (ns)236
8183F–AVR–06/12
ATtiny24A/44A/84A
21.3.11 Analog Comparator Offset
Figure 21-106. Analog Comparator Offset
VCC = 5V
21.3.12 Internal Oscillator Speed
Figure 21-107. Watchdog Oscillator Frequency vs. VCC
85
25
-40
-0.007
-0.006
-0.005
-0.004
-0.003
-0.002
-0.001
0
0.001
0.002
0.003
0.004
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VIN (V)
Offset (V)
85 °C
25 °C
-40 °C
0.108
0.11
0.112
0.114
0.116
0.118
0.12
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
Frequency (MHz)237
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-108. Watchdog Oscillator Frequency vs. Temperature
Figure 21-109. Calibrated 8 MHz RC Oscillator Frequency vs. VCC
5.5 V
3.0 V
1.8 V
0.106
0.108
0.11
0.112
0.114
0.116
0.118
0.12
-40 -20 0 20 40 60 80 100
Temperature (C)
Frequency (MHz)
7.4
7.6
7.8
8
8.2
8.4
1.5 2 2.5 3 3.5 4 4.5 5 5.5
V CC (V)
Frequency (MHz)
85 °C
25 °C
-40 °C238
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-110. Calibrated 8 MHz RC oscillator Frequency vs. Temperature
Figure 21-111. Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value
VCC = 3V
5.0 V
3.0 V
1.8 V
7.5
7.6
7.7
7.8
7.9
8
8.1
8.2
-40 -20 0 20 40 60 80 100
Temperature (C)
Frequency (MHz)
85 °C
25 °C
-40 °C
0
2
4
6
8
10
12
14
16
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
OSCCAL (X1)
Frequency (MHz)239
8183F–AVR–06/12
ATtiny24A/44A/84A
21.4 ATtiny84A
21.4.1 Current Consumption in Active Mode
Figure 21-112. Active Supply Current vs. Low Frequency
0.1 - 1.0 MHz, PRR = 0xFF
Figure 21-113. Active Supply Current vs. Frequency
1 - 20 MHz, PRR = 0xFF
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0
0,2
0,4
0,6
0,8
1
0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1
Frequency (MHz)
ICC (mA)
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0
2
4
6
8
10
12
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)
ICC (mA)240
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-114. Active Supply Current vs. VCC
Internal RC Oscillator, 8 MHz
Figure 21-115. Active Supply Current vs. VCC
Internal RC Oscillator, 1 MHz
85 °C
25 °C
-40 °C
0
0,5
1
1,5
2
2,5
3
3,5
4
4,5
5
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (mA)
85 °C
25 °C
-40 °C
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (mA)241
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-116. Active Supply Current vs. VCC
Internal RC Oscillator, 128 kHz
21.4.2 Current Consumption in Idle Mode
Figure 21-117. Idle Supply Current vs. Low Frequency
0.1 - 1.0 MHz, PRR = 0xFF
85 °C
25 °C
-40 °C
0
0,02
0,04
0,06
0,08
0,1
0,12
0,14
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (mA)
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0
0,02
0,04
0,06
0,08
0,1
0,12
0,14
0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1
Frequency (MHz)
ICC (mA)242
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-118. Idle Supply Current vs. Frequency
1 - 20 MHz, PRR = 0xFF
Figure 21-119. Idle Supply Current vs. VCC
Internal RC Oscillator, 8 MHz
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V 0
0,5
1
1,5
2
2,5
3
3,5
4
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)
ICC (mA)
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,6
1,8
2
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (mA)
85 °C
25 °C
-40 °C243
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-120. Idle Supply Current vs. VCC
Internal RC Oscillator, 1 MHz
Figure 21-121. Idle Supply Current vs. VCC
Internal RC Oscillator, 128 kHz
85 °C
25 °C
-40 °C
0
0,05
0,1
0,15
0,2
0,25
0,3
0,35
0,4
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (mA)
0
0,005
0,01
0,015
0,02
0,025
0,03
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (mA)
85 °C
25 °C
-40 °C244
8183F–AVR–06/12
ATtiny24A/44A/84A
21.4.3 Current Consumption in Power-down Mode
Figure 21-122. Power-down Supply Current vs. VCC
Watchdog Timer Disabled
Figure 21-123. Power-down Supply Current vs. VCC
Watchdog Timer Enabled
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,6
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (uA)
85 °C
25 °C
-40 °C
0
2
4
6
8
10
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (uA)
85 °C
25 °C
-40 °C245
8183F–AVR–06/12
ATtiny24A/44A/84A
21.4.4 Current Consumption in Reset
Figure 21-124. Reset Supply Current vs. VCC
0.1 - 1.0 MHz, Excluding Current through Reset Pull-up
Figure 21-125. Reset Supply Current vs. VCC
1 - 20 MHz, Excluding Current through Reset Pull-up
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0
0,02
0,04
0,06
0,08
0,1
0,12
0,14
0,16
0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1
Frequency (MHz)
ICC (mA)
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V 0
0,5
1
1,5
2
2,5
3
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)
ICC (mA)246
8183F–AVR–06/12
ATtiny24A/44A/84A
21.4.5 Current Consumption of Peripheral Units
Figure 21-126. ADC Current vs. VCC
4 MHz Frequency
Figure 21-127. AREF Pin Current vs. Pin Voltage
0
100
200
300
400
500
600
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (uA)
0
20
40
60
80
100
120
140
160
1,5 2 2,5 3 3,5 4 4,5 5 5,5
AREF (V)
AREF pin current (uA)247
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-128. Analog Comparator Current vs. VCC
4 MHz Frequency
Figure 21-129. Programming Current vs. VCC
0
20
40
60
80
100
120
140
160
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (uA)
85 °C
25 °C
-40 °C
0
1000
2000
3000
4000
5000
6000
7000
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (uA)248
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-130. Brownout Detector Current vs. VCC
BOD Level = 1.8V
21.4.6 Pull-up Resistors
Figure 21-131. Pull-up Resistor Current vs. Input Voltage
I/O Pin, VCC = 1.8V
85 °C
25 °C
-40 °C
0
5
10
15
20
25
30
35
40
45
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (uA)
85 °C
25 °C
-40 °C
0
10
20
30
40
50
60
0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
VOP (V)
IOP (uA)249
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-132. Pull-up Resistor Current vs. Input Voltage
I/O Pin, VCC = 2.7V
Figure 21-133. Pull-up Resistor Current vs. Input Voltage
I/O Pin, VCC = 5V
85 °C
25 °C
-40 °C 0
10
20
30
40
50
60
70
80
0 0,5 1 1,5 2 2,5 3
VOP (V)
IOP (uA)
85 °C
25 °C
-40 °C 0
20
40
60
80
100
120
140
160
0 1 2 3 4 5 6
VOP (V)
IOP (uA)250
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-134. Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 1.8V
Figure 21-135. Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 2.7V
85 °C
25 °C
-40 °C
0
5
10
15
20
25
30
35
40
0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
VRESET (V)
IRESET (uA)
85 °C
25 °C
-40 °C
0
10
20
30
40
50
60
0 0,5 1 1,5 2 2,5 3
VRESET (V)
IRESET (uA)251
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-136. Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 5V
21.4.7 Output Driver Strength
Figure 21-137. VOL: Output Voltage vs. Sink Current
I/O Pin, VCC = 3V
85 °C
25 °C
-40 °C
0
20
40
60
80
100
120
0 0,5 1 1,5 2 2,5 3 3,5 4 4,5 5
VRESET (V)
IRESET (uA)
85 °C
25 °C
-40 °C
0
0,2
0,4
0,6
0,8
1
1,2
0 2 4 6 8 10 12 14 16 18 20
IOL (mA)
VOL (V)252
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-138. VOL: Output Voltage vs. Sink Current
I/O Pin, VCC = 5V
Figure 21-139. VOH: Output Voltage vs. Source Current
I/O Pin, VCC = 3V
85 °C
25 °C
-40 °C
0
0,1
0,2
0,3
0,4
0,5
0,6
0,7
0 2 4 6 8 10 12 14 16 18 20
IOL (mA)
VOL (V)
85 °C
25 °C
-40 °C
1,8
2
2,2
2,4
2,6
2,8
3
3,2
0 2 4 6 8 10 12 14 16 18 20
IOH (mA)
VOH (V)253
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-140. VOH: Output Voltage vs. Source Current
I/O Pin, VCC = 5V
Figure 21-141. VOL: Output Voltage vs. Sink Current
Reset Pin as I/O, VCC = 3V
85 °C
25 °C
-40 °C
4,2
4,4
4,6
4,8
5
5,2
0 2 4 6 8 10 12 14 16 18 20
IOH (mA)
VOH (V)
0
0,2
0,4
0,6
0,8
1
1,2
1,4
0 0,5 1 1,5 2 2,5 3
IOL (mA)
VOL (V)
85 °C
25 °C
-40 °C254
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-142. VOL: Output Voltage vs. Sink Current
Reset Pin as I/O, VCC = 5V
Figure 21-143. VOH: Output Voltage vs. Source Current
Reset Pin as I/O, VCC = 3V
85 °C
25 °C
-40 °C
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,6
1,8
2
012345678
IOL (mA)
VOL (V)
0
0,5
1
1,5
2
2,5
3
0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
IOH (mA)
VOH (V)
85 °C
25 °C
-40 °C255
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-144. VOH: Output Voltage vs. Source Current
Reset Pin as I/O, VCC = 5V
21.4.8 Input Threshold and Hysteresis (for I/O Ports)
Figure 21-145. VIH: Input Threshold Voltage vs. VCC
I/O Pin, Read as ‘1’
0
0,5
1
1,5
2
2,5
3
3,5
4
4,5
5
0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
IOH (mA)
VOH (V)
85 °C
25 °C
-40 °C
0
0,5
1
1,5
2
2,5
3
3,5
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Threshold (V)
85 °C
25 °C
-40 °C256
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-146. VIL: Input Threshold Voltage vs. VCC
I/O Pin, Read as ‘0’
Figure 21-147. VIH-VIL: Input Hysteresis vs. VCC
I/O Pin
85 °C
25 °C
-40 °C
0
0,5
1
1,5
2
2,5
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Threshold (V)
0
0,1
0,2
0,3
0,4
0,5
0,6
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Input Hysteresis (V)
85 °C
25 °C
-40 °C257
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-148. VIH: Input Threshold Voltage vs. VCC
Reset Pin as I/O, Read as ‘1’
Figure 21-149. VIL: Input Threshold Voltage vs. VCC
Reset Pin as I/O, Read as ‘0’
0
0,5
1
1,5
2
2,5
3
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Threshold (V)
85 °C
25 °C
-40 °C
0
0,5
1
1,5
2
2,5
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Threshold (V)
85 °C
25 °C
-40 °C258
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-150. VIH-VIL: Input Hysteresis vs. VCC
Reset Pin as I/O
21.4.9 BOD, Bandgap and Reset
Figure 21-151. BOD Threshold vs. Temperature
BODLEVEL is 4.3V
85 °C
25 °C
-40 °C
0
0,1
0,2
0,3
0,4
0,5
0,6
0,7
0,8
0,9
1
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Input Hysteresis (V) 4,24
4,26
4,28
4,3
4,32
4,34
4,36
4,38
4,4
4,42
-40 -20 0 20 40 60 80 100
Temperature (C)
Threshold (V)
RISING VCC
FALLING VCC259
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-152. BOD Threshold vs. Temperature
BODLEVEL is 2.7V
Figure 21-153. Bandgap Voltage vs. Supply Voltage
2,66
2,68
2,7
2,72
2,74
2,76
2,78
2,8
2,82
-40 -20 0 20 40 60 80 100
Temperature (C)
Threshold (V)
RISING VCC
FALLING VCC
1
1,02
1,04
1,06
1,08
1,1
1,12
1,14
1,16
1,18
1,2
1,5 2 2,5 3 3,5 4 4,5 5 5,5
Vcc (V)
Bandgap Voltage (V)260
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-154. Bandgap Voltage vs. Temperature
Figure 21-155. VIH: Input Threshold Voltage vs. VCC
Reset Pin, Read as ‘1’
1
1,02
1,04
1,06
1,08
1,1
1,12
1,14
1,16
1,18
1,2
-40 -20 0 20 40 60 80 100
Temperature (C)
Bandgap Voltage (V)
0
0,5
1
1,5
2
2,5
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Threshold (V)
85 °C
25 °C
-40 °C261
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-156. VIL: Input Threshold Voltage vs. VCC
Reset Pin, Read as ‘0’
Figure 21-157. VIH-VIL: Input Hysteresis vs. VCC
Reset Pin
0
0,5
1
1,5
2
2,5
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Threshold (V)
85 °C
25 °C
-40 °C
0
0,1
0,2
0,3
0,4
0,5
0,6
0,7
0,8
0,9
1
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Input Hysteresis (V)
85 °C
25 °C
-40 °C262
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-158. Minimum Reset Pulse Width vs. VCC
21.4.10 Analog Comparator Offset
Figure 21-159. Analog Comparator Offset
VCC = 5V
0
200
400
600
800
1000
1200
1400
1600
1800
2000
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Pulsewidth (ns)
85 °C
25 °C
-40 °C
85
25
-40
-0.012
-0.01
-0.008
-0.006
-0.004
-0.002
0
0.002
0.004
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Vin (V)
Offset (V)263
8183F–AVR–06/12
ATtiny24A/44A/84A
21.4.11 Internal Oscillator Speed
Figure 21-160. Watchdog Oscillator Frequency vs. VCC
Figure 21-161. Watchdog Oscillator Frequency vs. Temperature
108
110
112
114
116
118
120
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
FRC (kHz)
85 °C
25 °C
-40 °C
5.5 V
3.0 V
1.8 V
106
108
110
112
114
116
118
120
-40 -20 0 20 40 60 80 100
Temperature (C)
FRC (kHz)264
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-162. Calibrated 8 MHz RC Oscillator Frequency vs. VCC
Figure 21-163. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature
7,4
7,5
7,6
7,7
7,8
7,9
8
8,1
8,2
8,3
8,4
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
FRC (MHz)
85 °C
25 °C
-40 °C
5.0 V
3.0 V
1.8 V
7,5
7,6
7,7
7,8
7,9
8
8,1
8,2
8,3
8,4
-40 -20 0 20 40 60 80 100
Temperature (C)
FRC (MHz)265
8183F–AVR–06/12
ATtiny24A/44A/84A
Figure 21-164. Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value
VCC = 3V
0
2
4
6
8
10
12
14
16
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
OSCCAL (X1)
FRC (MHz)
85 °C
25 °C
-40 °C266
8183F–AVR–06/12
ATtiny24A/44A/84A
22. Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
0x3F (0x5F) SREG I T H S V N Z C Page 14
0x3E (0x5E) SPH – – – – – – SP9 SP8 Page 13
0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 Page 13
0x3C (0x5C) OCR0B Timer/Counter0 – Output Compare Register B Page 83
0x3B (0x5B) GIMSK – INT0 PCIE1 PCIE0 – – – – Page 50
0x3A (0x5A) GIFR – INTF0 PCIF1 PCIF0 – – – – Page 51
0x39 (0x59) TIMSK0 – – – – – OCIE0B OCIE0A TOIE0 Page 83
0x38 (0x58) TIFR0 – – – – – OCF0B OCF0A TOV0 Page 84
0x37 (0x57) SPMCSR – – RSIG CTPB RFLB PGWRT PGERS SPMEN Page 156
0x36 (0x56) OCR0A Timer/Counter0 – Output Compare Register A Page 83
0x35 (0x55) MCUCR BODS PUD SE SM1 SM0 BODSE ISC01 ISC00 Pages 36, 50, 66
0x34 (0x54) MCUSR – – – – WDRF BORF EXTRF PORF Page 44
0x33 (0x53) TCCR0B FOC0A FOC0B – – WGM02 CS02 CS01 CS00 Page 82
0x32 (0x52) TCNT0 Timer/Counter0 Page 83
0x31 (0x51) OSCCAL CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 Page 31
0x30 (0x50) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 Page 79
0x2F (0x4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 Page 106
0x2E (0x4E) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 Page 108
0x2D (0x4D) TCNT1H Timer/Counter1 – Counter Register High Byte Page 110
0x2C (0x4C) TCNT1L Timer/Counter1 – Counter Register Low Byte Page 110
0x2B (0x4B) OCR1AH Timer/Counter1 – Compare Register A High Byte Page 110
0x2A (0x4A) OCR1AL Timer/Counter1 – Compare Register A Low Byte Page 110
0x29 (0x49) OCR1BH Timer/Counter1 – Compare Register B High Byte Page 110
0x28 (0x48) OCR1BL Timer/Counter1 – Compare Register B Low Byte Page 110
0x27 (0x47) DWDR DWDR[7:0] Page 151
0x26 (0x46) CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 Page 31
0x25 (0x45) ICR1H Timer/Counter1 - Input Capture Register High Byte Page 111
0x24 (0x44) ICR1L Timer/Counter1 - Input Capture Register Low Byte Page 111
0x23 (0x43) GTCCR TSM – – – – – – PSR10 Page 114
0x22 (0x42) TCCR1C FOC1A FOC1B – – – – – – Page 109
0x21 (0x41) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 Page 44
0x20 (0x40) PCMSK1 – – – – PCINT11 PCINT10 PCINT9 PCINT8 Page 51
0x1F (0x3F) EEARH – – – – – – – EEAR8 Page 20
0x1E (0x3E) EEARL EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 Page 21
0x1D (0x3D) EEDR EEPROM Data Register Page 21
0x1C (0x3C) EECR – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE Page 23
0x1B (0x3B) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 Page 66
0x1A (0x3A) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 Page 66
0x19 (0x39) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 Page 67
0x18 (0x38) PORTB – – – – PORTB3 PORTB2 PORTB1 PORTB0 Page 67
0x17 (0x37) DDRB – – – – DDB3 DDB2 DDB1 DDB0 Page 67
0x16 (0x36) PINB – – – – PINB3 PINB2 PINB1 PINB0 Page 67
0x15 (0x35) GPIOR2 General Purpose I/O Register 2 Page 22
0x14 (0x34) GPIOR1 General Purpose I/O Register 1 Page 23
0x13 (0x33) GPIOR0 General Purpose I/O Register 0 Page 23
0x12 (0x32) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 Page 52
0x11 (0x31)) Reserved –
0x10 (0x30) USIBR USI Buffer Register Page 127
0x0F (0x2F) USIDR USI Data Register Page 126
0x0E (0x2E) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 Page 125
0x0D (0x2D) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC Page 123
0x0C (0x2C) TIMSK1 – – ICIE1 – – OCIE1B OCIE1A TOIE1 Page 111
0x0B (0x2B) TIFR1 – – ICF1 – – OCF1B OCF1A TOV1 Page 112
0x0A (0x2A) Reserved –
0x09 (0x29) Reserved –
0x08 (0x28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 Page 129
0x07 (0x27) ADMUX REFS1 REFS0 MUX5 MUX4 MUX3 MUX2 MUX1 MUX0 Page 144
0x06 (0x26) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 Page 146
0x05 (0x25) ADCH ADC Data Register High Byte Page 148
0x04 (0x24) ADCL ADC Data Register Low Byte Page 148
0x03 (0x23) ADCSRB BIN ACME – ADLAR – ADTS2 ADTS1 ADTS0 Pages 130, 148
0x02 (0x22) Reserved –
0x01 (0x21) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D Pages 131, 149
0x00 (0x20) PRR – – – – PRTIM1 PRTIM0 PRUSI PRADC Page 37267
8183F–AVR–06/12
ATtiny24A/44A/84A
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.268
8183F–AVR–06/12
ATtiny24A/44A/84A
23. Instruction Set Summary
Mnemonics Operands Description Operation Flags #Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1
ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1
ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2
SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1
SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1
SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1
SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1
SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1
ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1
OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1
ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1
EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1
COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1
NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1
SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1
CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1
INC Rd Increment Rd ← Rd + 1 Z,N,V 1
DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1
TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1
CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1
SER Rd Set Register Rd ← 0xFF None 1
BRANCH INSTRUCTIONS
RJMP k Relative Jump PC ← PC + k + 1 None 2
IJMP Indirect Jump to (Z) PC ← Z None 2
RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3
ICALL Indirect Call to (Z) PC ← Z None 3
RET Subroutine Return PC ← STACK None 4
RETI Interrupt Return PC ← STACK I 4
CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3
CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1
CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1
CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3
SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3
SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3
SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2
BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2
BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2
BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2
BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2
BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2
BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2
BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2
BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2
BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2
BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2
BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2
BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2
BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2
BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2
BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2
CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2
LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1
LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1
ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1269
8183F–AVR–06/12
ATtiny24A/44A/84A
ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1
ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1
BSET s Flag Set SREG(s) ← 1 SREG(s) 1
BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1
BST Rr, b Bit Store from Register to T T ← Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) ← T None 1
SEC Set Carry C ← 1 C1
CLC Clear Carry C ← 0 C 1
SEN Set Negative Flag N ← 1 N1
CLN Clear Negative Flag N ← 0 N 1
SEZ Set Zero Flag Z ← 1 Z1
CLZ Clear Zero Flag Z ← 0 Z 1
SEI Global Interrupt Enable I ← 1 I1
CLI Global Interrupt Disable I ← 0 I 1
SES Set Signed Test Flag S ← 1 S1
CLS Clear Signed Test Flag S ← 0 S 1
SEV Set Twos Complement Overflow. V ← 1 V1
CLV Clear Twos Complement Overflow V ← 0 V 1
SET Set T in SREG T ← 1 T1
CLT Clear T in SREG T ← 0 T 1
SEH Set Half Carry Flag in SREG H ← 1 H1
CLH Clear Half Carry Flag in SREG H ← 0 H 1
DATA TRANSFER INSTRUCTIONS
MOV Rd, Rr Move Between Registers Rd ← Rr None 1
MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1
LDI Rd, K Load Immediate Rd ← K None 1
LD Rd, X Load Indirect Rd ← (X) None 2
LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2
LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2
LD Rd, Y Load Indirect Rd ← (Y) None 2
LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2
LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2
LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2
LD Rd, Z Load Indirect Rd ← (Z) None 2
LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2
LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2
LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2
LDS Rd, k Load Direct from SRAM Rd ← (k) None 2
ST X, Rr Store Indirect (X) ← Rr None 2
ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2
ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2
ST Y, Rr Store Indirect (Y) ← Rr None 2
ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2
ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2
STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2
ST Z, Rr Store Indirect (Z) ← Rr None 2
ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2
ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2
STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2
STS k, Rr Store Direct to SRAM (k) ← Rr None 2
LPM Load Program Memory R0 ← (Z) None 3
LPM Rd, Z Load Program Memory Rd ← (Z) None 3
LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3
SPM Store Program Memory (z) ← R1:R0 None
IN Rd, P In Port Rd ← P None 1
OUT P, Rr Out Port P ← Rr None 1
PUSH Rr Push Register on Stack STACK ← Rr None 2
POP Rd Pop Register from Stack Rd ← STACK None 2
MCU CONTROL INSTRUCTIONS
NOP No Operation None 1
SLEEP Sleep (see specific descr. for Sleep function) None 1
WDR Watchdog Reset (see specific descr. for WDR/Timer) None 1
BREAK Break For On-chip Debug Only None N/A
Mnemonics Operands Description Operation Flags #Clocks270
8183F–AVR–06/12
ATtiny24A/44A/84A
24. Ordering Information
Notes: 1. For speed vs. supply voltage, see section 20.3 “Speed” on page 174.
2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous
Substances (RoHS)
3. Code indicators:
– H: NiPdAu lead finish
– F, N, U: matte tin
– R: tape & reel
4. Topside marking for ATtiny24A: T24 / Axx / manufacturing data
5. Also supplied in wafer form. Contact your local Atmel sales office for ordering information and minimum quantities.
6. For typical and electrical characteristics, see “Appendix A – ATtiny24A/44A Specification at 105°C”.
7. For typical and electrical characteristics, see “Appendix B – ATtiny24A/44A/84A Specification at 125°C”.
24.1 ATtiny24A
Speed (MHz) (1) Supply Voltage (V) Temperature Range Package (2) Ordering Code (3)
20 1.8 – 5.5V
Industrial
(-40°C to +85°C) (5)
14S1
ATtiny24A-SSU
ATtiny24A-SSUR
14P3 ATtiny24A-PU
15CC1
ATtiny24A-CCU
ATtiny24A-CCUR
20M1
ATtiny24A-MU
ATtiny24A-MUR
20M2
ATtiny24A-MMH (4)
ATtiny24A-MMHR (4)
Industrial
(-40°C to +105°C) (6) 14S1
ATtiny24A-SSN
ATtiny24A-SSNR
Industrial
(-40°C to +125°C) (7)
14S1
ATtiny24A-SSF
ATtiny24A-SSFR
20M1
ATtiny24A-MF
ATtiny24A-MFR
20M2
ATtiny24A-MM8
ATtiny24A-MM8R
Package Type
14S1 14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC)
14P3 14-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
15CC1 15-ball (4 x 4 Array), 0.65 mm Pitch, 3.0 x 3.0 x 0.6 mm, Ultra Thin, Fine-Pitch Ball Grid Array Package (UFBGA)
20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No Lead / Micro Lead Frame Package (QFN/MLF)
20M2 20-pad, 3 x 3 x 0.85 mm Body, Very Thin Quad Flat No Lead Package (VQFN)271
8183F–AVR–06/12
ATtiny24A/44A/84A
Notes: 1. For speed vs. supply voltage, see section 20.3 “Speed” on page 174.
2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous
Substances (RoHS).
3. Code indicators:
– H: NiPdAu lead finish
– F, N, U: matte tin
– R: tape & reel
4. Topside marking for ATtiny44A:
– 1st Line: T44
– 2nd Line: Axx
– 3rd Line: manufacturing data
5. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
6. For typical and electrical characteristics, see “Appendix A – ATtiny24A/44A Specification at 105°C”.
7. For typical and electrical characteristics, see “Appendix B – ATtiny24A/44A/84A Specification at 125°C”.
24.2 ATtiny44A
Speed (MHz) (1) Supply Voltage (V) Temperature Range Package (2) Ordering Code (3)
20 1.8 – 5.5V
Industrial
(-40°C to +85°C) (5)
14S1
ATtiny44A-SSU
ATtiny44A-SSUR
14P3 ATtiny44A-PU
15CC1
ATtiny44A-CCU
ATtiny44A-CCUR
20M1
ATtiny44A-MU
ATtiny44A-MUR
20M2
ATtiny44A-MMH (4)
ATtiny44A-MMHR (4)
Industrial
(-40°C to +105°C) (6) 14S1
ATtiny44A-SSN
ATtiny44A-SSNR
Industrial
(-40°C to +125°C) (7)
14S1
ATtiny44A-SSF
ATtiny44A-SSFR
20M1
ATtiny44A-MF
ATtiny44A-MFR
Package Type
14S1 14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC)
14P3 14-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
15CC1 15-ball (4 x 4 Array), 0.65 mm Pitch, 3.0 x 3.0 x 0.6 mm, Ultra Thin, Fine-Pitch Ball Grid Array Package (UFBGA)
20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No Lead / Micro Lead Frame Package (QFN/MLF)
20M2 20-pad, 3 x 3 x 0.85 mm Body, Very Thin Quad Flat No Lead Package (VQFN)272
8183F–AVR–06/12
ATtiny24A/44A/84A
Notes: 1. For speed vs. supply voltage, see section 20.3 “Speed” on page 174.
2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous
Substances (RoHS).
3. Code indicators:
– H: NiPdAu lead finish
– F, N, U: matte tin
– R: tape & reel
4. Topside marking for ATtiny84A:
– 1st Line: T84
– 2nd Line: Axx
– 3rd Line: manufacturing data
5. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
6. For typical and electrical characteristics, see “Appendix A – ATtiny24A/44A Specification at 105°C”.
7. For typical and electrical characteristics, see “Appendix B – ATtiny24A/44A/84A Specification at 125°C”.
24.3 ATtiny84A
Speed (MHz) (1) Supply Voltage (V) Temperature Range Package (2) Ordering Code (3)
20 1.8 – 5.5V
Industrial
(-40°C to +85°C) (5)
14S1
ATtiny84A-SSU
ATtiny84A-SSUR
14P3 ATtiny84A-PU
15CC1
ATtiny84A-CCU
ATtiny84A-CCUR
20M1
ATtiny84A-MU
ATtiny84A-MUR
20M2
ATtiny84A-MMH (4)
ATtiny84A-MMHR (4)
Industrial
(-40°C to +125°C) (7) 14S1
ATtiny84A-SSF
ATtiny84A-SSFR
Package Type
14S1 14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC)
14P3 14-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
15CC1 15-ball (4 x 4 Array), 0.65 mm Pitch, 3.0 x 3.0 x 0.6 mm, Ultra Thin, Fine-Pitch Ball Grid Array Package (UFBGA)
20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No Lead / Micro Lead Frame Package (QFN/MLF)
20M2 20-pad, 3 x 3 x 0.85 mm Body, Very Thin Quad Flat No Lead Package (VQFN)273
8183F–AVR–06/12
ATtiny24A/44A/84A
25. Packaging Information
25.1 14S1
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
14S1, 14-lead, 0.150" Wide Body, Plastic Gull
Wing Small Outline Package (SOIC)
2/5/02
14S1 A
A1
E
L
Side View
Top View End View
E H
b
N
1
e
A
D
COMMON DIMENSIONS
(Unit of Measure = mm/inches)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012, Variation AB for additional information.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusion and gate burrs shall not
exceed 0.15 mm (0.006") per side.
3. Dimension E does not include inter-lead Flash or protrusion. Inter-lead flash and protrusions shall not exceed 0.25 mm
(0.010") per side.
4. L is the length of the terminal for soldering to a substrate.
5. The lead width B, as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value
of 0.61 mm (0.024") per side.
A 1.35/0.0532 – 1.75/0.0688
A1 0.1/.0040 – 0.25/0.0098
b 0.33/0.0130 – 0.5/0.02005
D 8.55/0.3367 – 8.74/0.3444 2
E 3.8/0.1497 – 3.99/0.1574 3
H 5.8/0.2284 – 6.19/0.2440
L 0.41/0.0160 – 1.27/0.0500 4
e 1.27/0.050 BSC274
8183F–AVR–06/12
ATtiny24A/44A/84A
25.2 14P3
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
14P3, 14-lead (0.300"/7.62 mm Wide) Plastic Dual
Inline Package (PDIP) 14P3 B
2010-10-20
PIN
1
E1
A1
B
E
B1
C
L
SEATING PLANE
A
D
e
eB
eC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A – – 5.334
A1 0.381 – –
D 18.669 – 19.685 Note 2
E 7.620 – 8.255
E1 6.096 – 7.112 Note 2
B 0.356 – 0.559
B1 1.143 – 1.778
L 2.921 – 3.810
C 0.203 – 0.356
eB – – 10.922
eC 0.000 – 1.524
e 2.540 TYP
Notes: 1. This package conforms to JEDEC reference MS-001, Variation AA.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 275
8183F–AVR–06/12
ATtiny24A/44A/84A
25.3 15CC1
TITLE GPC DRAWING NO. REV.
Package Drawing Contact:
R packagedrawings@atmel.com CBC C
15CC1, 15-ball (4 x 4 Array), 3.0 x 3.0 x 0.6 mm
package, ball pitch 0.65 mm,
Ultra thin, Fine-Pitch Ball Grid Array Package (UFBGA)
15CC1
07/06/10
A – – 0.60
A1 0.12 – –
A2 0.38 REF
b 0.25 0.30 0.35 1
b1 0.25 – – 2
D 2.90 3.00 3.10
D1 1.95 BSC
E 2.90 3.00 3.10
E1 1.95 BSC
e 0.65 BSC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
TOP VIEW
123 4
A
B
C
D
E
D
15-Øb
D
C
B
A
Pin#1 ID
0.08
A1
A
D1
E1
A2
A1 BALL CORNER
e
123 4
SIDE VIEW
b1
BOTTOM VIEW
e
Note1: Dimension “b” is measured at the maximum ball dia. in a plane parallel
to the seating plane.
Note2: Dimension “b1” is the solderable surface defined by the opening of the
solder resist layer.276
8183F–AVR–06/12
ATtiny24A/44A/84A
25.4 20M1
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, 20M1 B
10/27/04
2.6 mm Exposed Pad, Micro Lead Frame Package (MLF)
A 0.70 0.75 0.80
A1 – 0.01 0.05
A2 0.20 REF
b 0.18 0.23 0.30
D 4.00 BSC
D2 2.45 2.60 2.75
E 4.00 BSC
E2 2.45 2.60 2.75
e 0.50 BSC
L 0.35 0.40 0.55
SIDE VIEW
Pin 1 ID
Pin #1
Notch
(0.20 R)
BOTTOM VIEW
TOP VIEW
Note: Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5.
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D
E
e
A2
A1
A
D2
E2
0.08 C
L
1
2
3
b
1
2
3277
8183F–AVR–06/12
ATtiny24A/44A/84A
25.5 20M2
TITLE GPC DRAWING NO. REV.
Package Drawing Contact:
packagedrawings@atmel.com ZFC B 20M2
20M2, 20-pad, 3 x 3 x 0.85 mm Body, Lead Pitch 0.45 mm,
1.55 x 1.55 mm Exposed Pad, Thermally Enhanced
Plastic Very Thin Quad Flat No Lead Package (VQFN)
10/24/08
15
14
13
12
11
1
2
3
4
5
16 17 18 19 20
10 9 8 7 6
D2
E2
e
b
L K
Pin #1 Chamfer
(C 0.3)
D
E SIDE VIEW
A1
y
Pin 1 ID
BOTTOM VIEW
TOP VIEW
A
C
C0.18 (8X)
0.3 Ref (4x)
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 0.75 0.80 0.85
A1 0.00 0.02 0.05
b 0.17 0.22 0.27
C 0.152
D 2.90 3.00 3.10
D2 1.40 1.55 1.70
E 2.90 3.00 3.10
E2 1.40 1.55 1.70
e – 0.45 –
L 0.35 0.40 0.45
K 0.20 – –
y 0.00 – 0.08 278
8183F–AVR–06/12
ATtiny24A/44A/84A
26. Errata
The revision letters in this section refer to the revision of the corresponding ATtiny24A/44A/84A
device.
26.1 ATtiny24A
26.1.1 Rev. H
No known errata.
26.1.2 Rev. G
Not sampled.
26.1.3 Rev. F
Not sampled.
26.2 ATtiny44A
26.2.1 Rev. G
No known errata. Yield improvement.
26.2.2 Rev. F
No known errata.
26.2.3 Rev. E
Not sampled.
26.3 ATtiny84A
26.3.1 Rev. C
No known errata.279
8183F–AVR–06/12
ATtiny24A/44A/84A
27. Datasheet Revision History
27.1 Rev. 8183F – 06/12
1. Updated:
– Table 16-1 on page 138
– Figure 16-7 on page 137
– “Ordering Information” on page 270
27.2 Rev. 8183E – 01/12
1. Updated:
– Production status for ATtiny24A and ATtiny84A
– “Start Condition Detector” on page 122
– “Ordering Information” on page 270, 271, and 272
27.3 Rev. 8183D – 04/11
1. Added errata for ATtiny44A rev. G in Section 26. “Errata” on page 278
27.4 Rev. 8183C – 03/11
1. Added:
– ATtiny84A, including typical characteristics plots
– Section 3.3 “Capacitive Touch Sensing” on page 6
– Table 6-8, “Capacitance of Low-Frequency Crystal Oscillator,” on page 28
– Analog Comparator Offset plots for ATtiny24A (Figure 21.2.10 on page 208) and
ATtiny44A (Figure 21.3.11 on page 236)
– Extended temperature part numbers in Section 24. “Ordering Information” on page
270
2. Updated:
– Bit syntax throughout the datasheet, e.g. from CS02:0 to CS0[2:0]
– Section 6.4 “Clock Output Buffer” on page 30, changed CLKO to CKOUT
– Table 16-4, “Single-Ended Input channel Selections,” on page 145, added note for
Internal 1.1V Reference
– Table 19-16, “High-voltage Serial Programming Instruction Set for
ATtiny24A/44A/84A,” on page 170, adjusted notes
– Table 20-1, “DC Characteristics. TA = -40°C to +85°C,” on page 173, adjusted notes
27.5 Rev. 8183B – 03/10
1. Updated template.
2. Added UFBGA package (15CC1) in: “Features” on page 1, “Pin Configurations” on
page 2, Section 24. “Ordering Information” on page 270, and Section 25.3 “15CC1” on
page 275.
3. Separated typical characteristic plots, added Section 21.2 “ATtiny24A” on page 183.
4. Updated sections:
– Section 14.5.4 “USIBR – USI Buffer Register” on page 127, header updated280
8183F–AVR–06/12
ATtiny24A/44A/84A
– Section 24. “Ordering Information” on page 270, added tape & reel and topside
marking, updated notes
5. Updated Figures:
– Figure 4-1 “Block Diagram of the AVR Architecture” on page 7
– Figure 8-1 “Reset Logic” on page 38
– Figure 14-1 “Universal Serial Interface, Block Diagram” on page 116, USIDB ->
USIBR
– Figure 19-5 “High-voltage Serial Programming Waveforms” on page 169
6. Updated Tables:
– Table 19-11, “Minimum Wait Delay Before Writing the Next Flash or EEPROM
Location,” on page 164, updated value for tWD_ERASE
27.6 Rev. 8183A – 12/08
1. Initial revision. Created from document 8006H.
2. Updated "Ordering Information" on page 278 and page 278. Pb-plated packages are no
longer offered and there are no separate ordering codes for commercial operation
range, the only available option now is industrial. Also, updated some order codes to
reflect changes in leadframe composition and added VQFN package option.
3. Updated data sheet template.
4. Removed all references to 8K device.
5. Updated characteristic plots of section “Typical Characteristics”, starting on page 182.
6. Added characteristic plots:
– “Bandgap Voltage vs. Supply Voltage” on page 233
– “Bandgap Voltage vs. Temperature” on page 233
7. Updated sections:
– “Features” on page 1
– “Power Reduction Register” on page 35
– “Analog Comparator” on page 128
– “Features” on page 132
– “Operation” on page 133
– “Starting a Conversion” on page 134
– “ADC Voltage Reference” on page 139
– “Speed” on page 174
8. Updated Figures:
– “Program Memory Map” on page 15
– “Data Memory Map” on page 16
9. Update Tables:
– “Device Signature Bytes” on page 161
– “DC Characteristics. TA = -40°C to +85°C” on page 173
– “Additional Current Consumption for the different I/O modules (absolute values)” on
page 182
– “Additional Current Consumption (percentage) in Active and Idle mode” on page 183i
8183F–AVR–06/12
ATtiny24A/44A/84A
Table of Contents
Features ..................................................................................................... 1
1 Pin Configurations ................................................................................... 2
1.1 Pin Descriptions .................................................................................................3
2 Overview ................................................................................................... 4
3 General Information ................................................................................. 6
3.1 Resources .........................................................................................................6
3.2 Code Examples .................................................................................................6
3.3 Capacitive Touch Sensing .................................................................................6
3.4 Data Retention ...................................................................................................6
3.5 Disclaimer ..........................................................................................................6
4 CPU Core .................................................................................................. 7
4.1 Architectural Overview .......................................................................................7
4.2 ALU – Arithmetic Logic Unit ...............................................................................8
4.3 Status Register ..................................................................................................8
4.4 General Purpose Register File ..........................................................................9
4.5 Stack Pointer ...................................................................................................10
4.6 Instruction Execution Timing ...........................................................................10
4.7 Reset and Interrupt Handling ...........................................................................11
4.8 Register Description ........................................................................................13
5 Memories ................................................................................................ 15
5.1 In-System Re-programmable Flash Program Memory ....................................15
5.2 SRAM Data Memory ........................................................................................15
5.3 EEPROM Data Memory ..................................................................................16
5.4 I/O Memory ......................................................................................................20
5.5 Register Description ........................................................................................20
6 Clock System ......................................................................................... 24
6.1 Clock Subsystems ...........................................................................................24
6.2 Clock Sources .................................................................................................25
6.3 System Clock Prescaler ..................................................................................30
6.4 Clock Output Buffer .........................................................................................30
6.5 Register Description ........................................................................................31
7 Power Management and Sleep Modes ................................................. 33ii
8183F–AVR–06/12
ATtiny24A/44A/84A
7.1 Sleep Modes ....................................................................................................33
7.2 Software BOD Disable .....................................................................................34
7.3 Power Reduction Register ...............................................................................35
7.4 Minimizing Power Consumption ......................................................................35
7.5 Register Description ........................................................................................36
8 System Control and Reset .................................................................... 38
8.1 Resetting the AVR ...........................................................................................38
8.2 Reset Sources .................................................................................................39
8.3 Internal Voltage Reference ..............................................................................41
8.4 Watchdog Timer ..............................................................................................41
8.5 Register Description ........................................................................................44
9 Interrupts ................................................................................................ 47
9.1 Interrupt Vectors ..............................................................................................47
9.2 External Interrupts ...........................................................................................48
9.3 Register Description ........................................................................................50
10 I/O Ports .................................................................................................. 53
10.1 Ports as General Digital I/O .............................................................................54
10.2 Alternate Port Functions ..................................................................................58
10.3 Register Description ........................................................................................66
11 8-bit Timer/Counter0 with PWM ............................................................ 68
11.1 Features ..........................................................................................................68
11.2 Overview ..........................................................................................................68
11.3 Clock Sources .................................................................................................69
11.4 Counter Unit ....................................................................................................69
11.5 Output Compare Unit .......................................................................................70
11.6 Compare Match Output Unit ............................................................................72
11.7 Modes of Operation .........................................................................................73
11.8 Timer/Counter Timing Diagrams .....................................................................77
11.9 Register Description ........................................................................................79
12 16-bit Timer/Counter1 ............................................................................ 85
12.1 Features ..........................................................................................................85
12.2 Overview ..........................................................................................................85
12.3 Timer/Counter Clock Sources .........................................................................87
12.4 Counter Unit ....................................................................................................87iii
8183F–AVR–06/12
ATtiny24A/44A/84A
12.5 Input Capture Unit ...........................................................................................88
12.6 Output Compare Units .....................................................................................90
12.7 Compare Match Output Unit ............................................................................92
12.8 Modes of Operation .........................................................................................94
12.9 Timer/Counter Timing Diagrams ...................................................................101
12.10 Accessing 16-bit Registers ............................................................................103
12.11 Register Description ......................................................................................106
13 Timer/Counter Prescaler ..................................................................... 113
13.1 Prescaler Reset .............................................................................................113
13.2 External Clock Source ...................................................................................113
13.3 Register Description ......................................................................................114
14 USI – Universal Serial Interface .......................................................... 116
14.1 Features ........................................................................................................116
14.2 Overview ........................................................................................................116
14.3 Functional Descriptions .................................................................................117
14.4 Alternative USI Usage ...................................................................................123
14.5 Register Descriptions ....................................................................................123
15 Analog Comparator ............................................................................. 128
15.1 Analog Comparator Multiplexed Input ...........................................................128
15.2 Register Description ......................................................................................129
16 Analog to Digital Converter ................................................................ 132
16.1 Features ........................................................................................................132
16.2 Overview ........................................................................................................132
16.3 Operation .......................................................................................................133
16.4 Starting a Conversion ....................................................................................134
16.5 Prescaling and Conversion Timing ................................................................135
16.6 Changing Channel or Reference Selection ...................................................138
16.7 ADC Noise Canceler .....................................................................................139
16.8 Analog Input Circuitry ....................................................................................139
16.9 Noise Canceling Techniques .........................................................................140
16.10 ADC Accuracy Definitions .............................................................................140
16.11 ADC Conversion Result .................................................................................142
16.12 Temperature Measurement ...........................................................................143
16.13 Register Description ......................................................................................144iv
8183F–AVR–06/12
ATtiny24A/44A/84A
17 debugWIRE On-chip Debug System .................................................. 150
17.1 Features ........................................................................................................150
17.2 Overview ........................................................................................................150
17.3 Physical Interface ..........................................................................................150
17.4 Software Break Points ...................................................................................151
17.5 Limitations of debugWIRE .............................................................................151
17.6 Register Description ......................................................................................151
18 Self-Programming the Flash ............................................................... 152
18.1 Performing Page Erase by SPM ....................................................................152
18.2 Filling the Temporary Buffer (Page Loading) .................................................152
18.3 Performing a Page Write ...............................................................................153
18.4 Addressing the Flash During Self-Programming ...........................................153
18.5 EEPROM Write Prevents Writing to SPMCSR ..............................................154
18.6 Reading Lock, Fuse and Signature Data from Software ...............................154
18.7 Preventing Flash Corruption ..........................................................................156
18.8 Programming Time for Flash when Using SPM ............................................156
18.9 Register Description ......................................................................................156
19 Memory Programming ......................................................................... 158
19.1 Program And Data Memory Lock Bits ...........................................................158
19.2 Fuse Bytes .....................................................................................................159
19.3 Device Signature Imprint Table .....................................................................160
19.4 Page Size ......................................................................................................161
19.5 Serial Programming .......................................................................................162
19.6 High-voltage Serial Programming ..................................................................166
19.7 High-Voltage Serial Programming Algorithm .................................................166
20 Electrical Characteristics .................................................................... 173
20.1 Absolute Maximum Ratings* .........................................................................173
20.2 DC Characteristics .........................................................................................173
20.3 Speed ............................................................................................................174
20.4 Clock Characteristics .....................................................................................175
20.5 System and Reset Characteristics ................................................................176
20.6 ADC Characteristics ......................................................................................177
20.7 Analog Comparator Characteristics ...............................................................180
20.8 Serial Programming Characteristics ..............................................................180
20.9 High-Voltage Serial Programming Characteristics ........................................181v
8183F–AVR–06/12
ATtiny24A/44A/84A
21 Typical Characteristics ........................................................................ 182
21.1 Supply Current of I/O Modules ......................................................................182
21.2 ATtiny24A ......................................................................................................183
21.3 ATtiny44A ......................................................................................................211
21.4 ATtiny84A ......................................................................................................239
22 Register Summary ............................................................................... 266
23 Instruction Set Summary .................................................................... 268
24 Ordering Information ........................................................................... 270
24.1 ATtiny24A ......................................................................................................270
24.2 ATtiny44A ......................................................................................................271
24.3 ATtiny84A ......................................................................................................272
25 Packaging Information ........................................................................ 273
25.1 14S1 ..............................................................................................................273
25.2 14P3 ..............................................................................................................274
25.3 15CC1 ...........................................................................................................275
25.4 20M1 ..............................................................................................................276
25.5 20M2 ..............................................................................................................277
26 Errata ..................................................................................................... 278
26.1 ATtiny24A ......................................................................................................278
26.2 ATtiny44A ......................................................................................................278
26.3 ATtiny84A ......................................................................................................278
27 Datasheet Revision History ................................................................ 279
27.1 Rev. 8183F – 06/12 .......................................................................................279
27.2 Rev. 8183E – 01/12 .......................................................................................279
27.3 Rev. 8183D – 04/11 .......................................................................................279
27.4 Rev. 8183C – 03/11 .......................................................................................279
27.5 Rev. 8183B – 03/10 .......................................................................................279
27.6 Rev. 8183A – 12/08 .......................................................................................2808183F–AVR–06/12
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Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
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and product names may be trademarks of others.
Atmel Xplained Pro
Atmel® Xplained Pro kits provide a complete and easy to use low-cost development platform for evaluating and prototyping
your Atmel Flash-based microcontrollers (MCUs) designs.
The Xplained Pro kits offer expansion ports that allow you to connect extension boards to provide more system functionality
including OLED LCD displays, buttons, sensors and more, for fast application prototyping. You can purchase add-on boards
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Evaluation Kit Contents SAP Code Price
SAM4L Xplained Pro Evaluation Kit SAM4L MCU Board ATSAM4L-XPRO $39
SAM4S Xplained Pro Evaluation Kit SAM4S MCU Board ATSAM4S-XPRO $39
ATmega256RFR2 Xplained Pro
Evaluation Kit ATmega256RFR2 MCU Board ATMEGA256RFR2-XPRO $39
SAM4L Xplained Pro Starter Kit SAM4L MCU Board
4 Extension Boards: Segment LCD, OLED Display, I/O, Prototyping ATSAM4L-XSTK $109
SAM4S Xplained Pro Starter Kit SAM4S MCU Board
3 Extension Boards: OLED Display, I/O, Prototyping ATSAM4S-XSTK $99
RFR2 Xplained Pro Starter Kit 3 Extension Boards: OLED Display, I/O, Prototyping ATMEGA256RFR2-XSTK $99
OLED Xplained Pro Extension Extension board with 128x32 OLED Display,
3 Buttons and 3 LEDs ATOLED1-XPRO $22
Segment LCD Xplained Pro Extension Extension Board with LCD Segment Display ATSLCD1-XPRO $22
I/O Xplained Pro Extension Extension Board with Light Sensor, Temperature Sensor,
Micro SD Card, UART Loopback ATIO1-XPRO $27
Prototyping Xplained Pro Extension Prototyping Extension Board with Bread-boarding Area ATPROTO1-XPRO $18
Not recommended for new designs - Use XMEGA A1U series 8067O–AVR–06/2013
Features
High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller
Nonvolatile program and data memories
64K - 128KBytes of in-system self-programmable flash
4K - 8KBytes boot section
2 KBBytes EEPROM
4 KB - 8 KBBytes internal SRAM
External bus interface for up to 16Mbytes SRAM
External bus interface for up to 128Mbit SDRAM
Peripheral features
Four-channel DMA controller
Eight-channel event system
Eight 16-bit timer/counters
Four timer/counters with 4 output compare or input capture channels
Four timer/counters with 2 output compare or input capture channels
High resolution extension on all timer/counters
Advanced waveform extension (AWeX) on two timer/counters
Eight USARTs with IrDA support for one USART
Four two-wire interfaces with dual address match (I2
C and SMBus compatible)
Four serial peripheral interfaces (SPIs)
AES and DES crypto engine
16-bit real time counter (RTC) with separate oscillator
Two sixteen channel, 12-bit, 2msps Analog to Digital Converters
Two two-channel, 12-bit, 1msps Digital to Analog Converters
Four Analog Comparators (ACs) with window compare function, and current sources
External interrupts on all general purpose I/O pins
Programmable watchdog timer with separate on-chip ultra low power oscillator
QTouch® library support
Capacitive touch buttons, sliders and wheels
Special microcontroller features
Power-on reset and programmable brown-out detection
Internal and external clock options with PLL and prescaler
Programmable multilevel interrupt controller
Five sleep modes
Programming and debug interfaces
JTAG (IEEE 1149.1 compliant) interface, including boundary scan
PDI (Program and Debug Interface)
I/O and packages
78 Programmable I/O pins
100 lead TQFP
100 ball BGA
100 ball VFBGA
Operating voltage
1.6 – 3.6V
Operating frequency
0 – 12MHz from 1.6V
0 – 32MHz from 2.7V
8/16-bit XMEGA A1 Microcontroller
ATxmega128A1 / ATxmega64A1
Preliminary
8067O–AVR–06/2013
Not recommended for new designs -
Use XMEGA A1U series[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 2
8067O–AVR–06/2013
‘
1. Ordering Information
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
3. For packaging information, see “Packaging information” on page 70.
Typical Applications
Ordering Code Flash (B) E2 SRAM Speed (MHz) Power Supply Package(1)(2)(3) Temp
ATxmega128A1-AU
128K + 8K 2 KB 8 KB
32 1.6 - 3.6V
100A
-40C - 85C
ATxmega128A1-AUR
ATxmega64A1-AU
64K + 4K 2 KB 4 KB
ATxmega64A1-AUR
ATxmega128A1-CU
128K + 8K 2 KB 8 KB
100C1
ATxmega128A1CUR
ATxmega64A1-CU
64K + 4K 2 KB 4 KB
ATxmega64A1-CUR
ATxmega128A1-C7U
128K + 8K 2 KB 8 KB
100C2
ATxmega128A1-C7UR
ATxmega64A1-C7U
64K + 4K 2 KB 4 KB
ATxmega64A1-C7UR
Package Type
100A 100-lead, 14 x 14 x 1.0mm, 0.5mm lead pitch, thin profile plastic quad flat package (TQFP)
100C1 100-ball, 9 x 9 x 1.2mm body, ball pitch 0.88mm, chip ball grid array (CBGA)
100C2 100-ball, 7 x 7 x 1.0mm body, ball pitch 0.65mm, very thin fine-pitch ball grid array (VFBGA)
Industrial control Climate control Low power battery applications
Factory automation RF and ZigBee® Power tools
Building control Sensor control HVAC
Board control Optical Utility metering
White goods Medical applications[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 3
8067O–AVR–06/2013
2. Pinout/Block Diagram
Figure 2-1. Block diagram and pinout
Notes: 1. For full details on pinout and pin functions refer to “Pinout and Pin Functions” on page 55.
2. VCC/GND on pin 83/84 are swapped compared to other VCC/GND to allow easier routing of GND to 32kHz crystal.
INDEX CORNER
PA6
PA7
GND
AVCC
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
GND
VCC
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
GND
VCC
PD0
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PD1
PD2
PD3
PD4
PD5
PD6
PD7
GND
VCC
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
GND
VCC
PF0
PF1
PF2
PF3
PF4
PF5
PK0
VCC
GND
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
VCC
GND
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
VCC
GND
PF7
PF6
PA5
PA4
PA3
PA2
PA1
PA0
AVCC
GND
PR1
PR0
RESET/PDI
PDI
PQ3
PQ2
PQ1
PQ0
GND
VCC
PK7
PK6
PK5
PK4
PK3
PK2
PK1
FLASH
RAM
E 2PROM DMA
Interrupt Controlle r
OCD
External Bus Interface
ADC A
ADC B
DAC B
DAC A
AC A0
AC A1
AC B0
AC B1
Port
A Port B
Event System ctrl
Port K
Port J
Port H
Port R Port Q
Power
Contro l
Reset
Contro l
Watchdog
OSC/CLK
Contro l BOD POR
RTC
EVENT ROUTING NETWORK
DATA BU S
DATA BU S
VREF
TEMP
Port C
CPU
T/C0:1
USART0:1
TWI
SPI
Port D Port E Port F
T/C0:1
USART0/1
TWI
SPI
T/C0:1
USART0:1
TWI
SPI
T/C0:1
USART0:1
TWI
SPI[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 4
8067O–AVR–06/2013
Figure 2-2. CBGA-pinout
Table 2-1. CBGA-pinout.
1 2 3 4 5 6 7 8 9 10
A PK0 VCC GND PJ3 VCC GND PH1 GND VCC PF7
B PK3 PK2 PK1 PJ4 PH7 PH4 PH2 PH0 PF6 PF5
C VCC PK5 PK4 PJ5 PJ0 PH5 PH3 PF2 PF3 VCC
D GND PK6 PK7 PJ6 PJ1 PH6 PF0 PF1 PF4 GND
E PQ0 PQ1 PQ2 PJ7 PJ2 PE7 PE6 PE5 PE4 PE3
F PR1 PR0 RESET/
PDI PDI PQ3 PC2 PE2 PE1 PE0 VCC
G GND PA1 PA4 PB3 PB4 PC1 PC6 PD7 PD6 GND
H AVCC PA2 PA5 PB2 PB5 PC0 PC5 PD5 PD4 PD3
J PA0 PA3 PB0 PB1 PB6 PC3 PC4 PC7 PD2 PD1
K PA6 PA7 GND AVCC PB7 VCC GND VCC GND PD0
A
B
C
D
E
F
G
H
J
K
1 2 3 4 5 6 7 8 9 10
A
B
C
D
E
F
G
H
J
K
10 9 8 7 6 5 4 3 2 1
Top view Bottom view[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 5
8067O–AVR–06/2013
3. Overview
The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based
on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA devices
achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system
designer to optimize power consumption versus processing speed.
The Atmel AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are
directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single
instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs
many times faster than conventional single-accumulator or CISC based microcontrollers.
The AVR XMEGA A1 devices provide the following features: in-system programmable flash with read-while-write
capabilities; internal EEPROM and SRAM; four-channel DMA controller, eight-channel event system and programmable
multilevel interrupt controller, 78 general purpose I/O lines, 16-bit real-time counter (RTC); eight flexible, 16-bit
timer/counters with compare and PWM channels, eight USARTs; four two-wire serial interfaces (TWIs); four serial
peripheral interfaces (SPIs); AES and DES cryptographic engine; two 16-channel, 12-bit ADCs with programmable gain;
two 2-channel, 12-bit DACs; four Analog Comparators (ACs) with window mode; programmable watchdog timer with
separate internal oscillator; accurate internal oscillators with PLL and prescaler; and programmable brown-out detection.
The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available. The
devices also have an IEEE std. 1149.1 compliant JTAG interface, and this can also be used for boundary scan, on-chip
debug and programming.
The XMEGA A1 devices have five software selectable power saving modes. The idle mode stops the CPU while allowing
the SRAM, DMA controller, event system, interrupt controller, and all peripherals to continue functioning. The powerdown
mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the next
TWI or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to run, allowing
the application to maintain a timer base while the rest of the device is sleeping. In standby mode, the external crystal
oscillator keeps running while the rest of the device is sleeping. This allows very fast startup from the external crystal,
combined with low power consumption. In extended standby mode, both the main oscillator and the asynchronous timer
continue to run. To further reduce power consumption, the peripheral clock to each individual peripheral can optionally be
stopped in active mode and idle sleep mode.
Atmel offers a free QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR
microcontrollers.
The device are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory can
be reprogrammed in-system through the PDI or JTAG interfaces. A boot loader running in the device can use any
interface to download the application program to the flash memory. The boot loader software in the boot flash section will
continue to run while the application flash section is updated, providing true read-while-write operation. By combining an
8/16-bit RISC CPU with in-system, self-programmable flash, the AVR XMEGA is a powerful microcontroller family that
provides a highly flexible and cost effective solution for many embedded applications.
All Atmel AVR XMEGA devices are supported with a full suite of program and system development tools, including C
compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 6
8067O–AVR–06/2013
3.1 Block Diagram
Figure 3-1. XMEGA A1 Block Diagram
VBAT
Power
Supervision
Battery Backup
Controller
Real Time
Counter
32.768 kHz
XOSC
Power
Supervision
POR/BOD &
RESET PORT A (8)
PORT B (8)
EVENT ROUTING NETWORK
DMA
Controller
BUS
Matrix
SRAM
EBI
ADCA
DACA
ACA
DACB
ADCB
ACB
OCD
PORT K (8)
PORT J (8)
PORT H (8)
PDI
Watchdog
Timer
Watchdog
Oscillator
Interrupt
Controller
DATA BUS
Prog/Debug
Controller
PORT R (2)
Oscillator
Circuits/
Clock
Generation
Oscillator
Control
Real Time
Counter
Event System
Controller
JTAG
Sleep
Controller
DES
IRCOM
PORT G (8)
PORT L (8)
PORT Q (8)
PORT M (8)
PORT C (8) TCC0:1 USARTC0:1 SPIC
TWIC
PORT D (8) TCD0:1 USARTD0:1 SPID
TWID
TCF0:1
USARTF0:1
SPIF
TWIF
TCE0:1
USARTE0:1
SPIE
TWIE
PORT E (8) PORT F (8)
EVENT ROUTING NETWORK
AES
AREFA
AREFB
PORT N (8)
PORT P (8)
CPU
NVM Controller
Flash EEPROM
DATA BUS
Int. Refs.
Tempref
Digital function
Analog function
Bus masters / Programming / Debug
Oscillator / Crystal / Clock
General Purpose I/O
EBI[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 7
8067O–AVR–06/2013
4. Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
http://www.atmel.com/avr.
4.1 Recommended reading
XMEGA A Manual
XMEGA A Application Notes
This device data sheet only contains part specific information and a short description of each peripheral and module. The
XMEGA A Manual describes the modules and peripherals in depth. The XMEGA A application notes contain example
code and show applied use of the modules and peripherals.
The XMEGA A Manual and Application Notes are available from http://www.atmel.com/avr.
5. Capacitive touch sensing
The Atmel QTouch library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR
microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced
reporting of touch keys and includes Adjacent Key Suppression® (AKS®) technology for unambiguous detection of key
events. The QTouch library includes support for the QTouch and QMatrix acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch library for the AVR
microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the
touch sensing API’s to retrieve the channel information and determine the touch sensor states.
The QTouch library is FREE and downloadable from the Atmel website at the following location:
www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the QTouch library user guide -
also available for download from the Atmel website.
6. Disclaimer
For devices that are not available yet, typical values contained in this datasheet are based on simulations and
characterization of other AVR XMEGA microcontrollers manufactured on the same process technology. Min. and Max
values will be available after the device is characterized.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 8
8067O–AVR–06/2013
7. AVR CPU
7.1 Features
8/16-bit high performance AVR RISC Architecture
138 instructions
Hardware multiplier
32x8-bit registers directly connected to the ALU
Stack in SRAM
Stack Pointer accessible in I/O memory space
Direct addressing of up to 16M Bytes of program and data memory
True 16/24-bit access to 16/24-bit I/O registers
Support for 8-, 16- and 32-bit Arithmetic
Configuration Change Protection of system critical features
7.2 Overview
All Atmel AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and
perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the
program in the flash memory. Interrupt handling is described in a separate section, refer to “Interrupts and Programmable
Multilevel Interrupt Controller” on page 29.
7.3 Architectural Overview
In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories
and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to
be executed on every clock cycle. For details of all AVR instructions, refer to http://www.atmel.com/avr.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 9
8067O–AVR–06/2013
Figure 7-1. Block diagram of the AVR CPU architecture.
The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a
register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is
updated to reflect information about the result of the operation.
The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purpose working registers all have
single clock cycle access time allowing single-cycle arithmetic logic unit (ALU) operation between registers or between a
register and an immediate. Six of the 32 registers can be used as three 16-bit address pointers for program and data
space addressing, enabling efficient address calculations.
The memory spaces are linear. The data memory space and the program memory space are two different memory
spaces.
The data memory space is divided into I/O registers, SRAM, and external RAM. In addition, the EEPROM can be
memory mapped in the data memory.
All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the I/O
memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3F.
The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be accessed as
data space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions.
The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five different
addressing modes supported in the AVR architecture. The first SRAM address is 0x2000.
Data addresses 0x1000 to 0x1FFF are reserved for memory mapping of EEPROM.
The program memory is divided in two sections, the application program section and the boot program section. Both
sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for selfprogramming
of the application flash memory must reside in the boot program section. The application section contains
an application table section with separate lock bits for write and read/write protection. The application table section can
be used for safe storing of nonvolatile data in the program memory.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 10
8067O–AVR–06/2013
7.4 ALU - Arithmetic Logic Unit
The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a
register. Single-register operations can also be executed. The ALU operates in direct connection with all 32 general
purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register
and an immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the
status register is updated to reflect information about the result of the operation.
ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit
arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit aritmetic. The hardware
multiplier supports signed and unsigned multiplication and fractional format.
7.4.1 Hardware Multiplier
The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different
variations of signed and unsigned integer and fractional numbers:
Multiplication of unsigned integers
Multiplication of signed integers
Multiplication of a signed integer with an unsigned integer
Multiplication of unsigned fractional numbers
Multiplication of signed fractional numbers
Multiplication of a signed fractional number with an unsigned one
A multiplication takes two CPU clock cycles.
7.5 Program Flow
After reset, the CPU starts to execute instructions from the lowest address in the flash program memory ‘0.’ The program
counter (PC) addresses the next instruction to be fetched.
Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole
address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general
data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After
reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the
I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be
accessed through the five different addressing modes supported in the AVR CPU.
7.6 Status Register
The status register (SREG) contains information about the result of the most recently executed arithmetic or logic
instruction. This information can be used for altering program flow in order to perform conditional operations. Note that
the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many
cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
The status register is not automatically stored when entering an interrupt routine nor restored when returning from an
interrupt. This must be handled by software.
The status register is accessible in the I/O memory space.
7.6.1 Stack and Stack Pointer
The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing
temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit
registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and
POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing
data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded [Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 11
8067O–AVR–06/2013
after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point
above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled.
During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be
two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program
memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices
with more than 128KB of program memory, the return address is three bytes, and hence the SP is
decremented/incremented by three. The return address is popped off the stack when returning from interrupts using the
RETI instruction, and from subroutine calls using the RET instruction.
The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one
when data is popped off the stack using the POP instruction.
To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts
for up to four instructions or until the next I/O memory write.
After reset the stack pointer is initialized to the highest address of the SRAM. See Table 8-2 on page 15.
7.7 Register File
The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The register
file supports the following input/output schemes:
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient
address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash
program memory.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 12
8067O–AVR–06/2013
8. Memories
8.1 Features
Flash Program Memory
One linear address space
In-System Programmable
Self-Programming and Bootloader support
Application Section for application code
Application Table Section for application code or data storage
Boot Section for application code or bootloader code
Separate lock bits and protection for all sections
Built in fast CRC check of a selectable flash program memory section
Data Memory
One linear address space
Single cycle access from CPU
SRAM
EEPROM
Byte and page accessible
Optional memory mapping for direct load and store
I/O Memory
Configuration and Status registers for all peripherals and modules
16 bit-accessible General Purpose Register for global variables or flags
External Memory support
SRAM
SDRAM
Memory mapped external hardware
Bus arbitration
Safe and deterministic handling of CPU and DMA Controller priority
Separate buses for SRAM, EEPROM, I/O Memory and External Memory access
Simultaneous bus access for CPU and DMA Controller
Production Signature Row Memory for factory programmed data
Device ID for each microcontroller device type
Serial number for each device
Oscillator calibration bytes
ADC, DAC and temperature sensor calibration data
User Signature Row
One flash page in size
Can be read and written from software
Content is kept after chip erase
8.2 Overview
The Atmel AVR architecture has two main memory spaces, the program memory and the data memory. Executable code
can reside only in the program memory, while data can be stored in the program memory and the data memory. The data
memory includes the internal SRAM, and EEPROM for nonvolatile data storage. All memory spaces are linear and
require no memory bank switching. Nonvolatile memory (NVM) spaces can be locked for further write and read/write
operations. This prevents unrestricted access to the application software.
A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can
only be written by an external programmer.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 13
8067O–AVR–06/2013
The available memory size configurations are shown in “Ordering Information” on page 2. In addition each device has a
flash memory signature rows for calibration data, device identification, serial number etc.
8.3 In-System Programmable Flash Program Memory
he Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The flash
memory can be accessed for read and write from an external programmer through the PDI or from application software
running in the device.
All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized
in two main sections, the application section and the boot loader section. The sizes of the different sections are fixed, but
device-dependent. These two sections have separate lock bits, and can have different levels of protection. The store
program memory (SPM) instruction, which is used to write to the flash from the application software, will only operate
when executed from the boot loader section.
The application section contains an application table section with separate lock settings. This enables safe storage of
nonvolatile data in the program memory.
Figure 8-1. Flash Program Memory (Hexadecimal address)
8.3.1 Application Section
The Application section is the section of the flash that is used for storing the executable application code. The protection
level for the application section can be selected by the boot lock bits for this section. The application section can not store
any boot loader code since the SPM instruction cannot be executed from the application section.
8.3.2 Application Table Section
The application table section is a part of the application section of the flash memory that can be used for storing data.
The size is identical to the boot loader section. The protection level for the application table section can be selected by
the boot lock bits for this section. The possibilities for different protection levels on the application section and the
application table section enable safe parameter storage in the program memory. If this section is not used for data,
application code can reside here.
8.3.3 Boot Loader Section
While the application section is used for storing the application code, the boot loader software must be located in the boot
loader section because the SPM instruction can only initiate programming when executing from this section. The SPM
instruction can access the entire flash, including the boot loader section itself. The protection level for the boot loader
section can be selected by the boot loader lock bits. If this section is not used for boot loader software, application code
can be stored here.
Word Address
ATxega128A1 ATxmega64A1
0 0 Application Section (Bytes)
(128K/64K)
...
EFFF / 77FF
F000 / 7800 Application Table Section (Bytes)
FFFF / 7FFF (8K/4K)
10000 / 8000 Boot Section (Bytes)
10FFF / 87FF (8K/4K)[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 14
8067O–AVR–06/2013
8.3.4 Production Signature Row
The production signature row is a separate memory section for factory programmed data. It contains calibration data for
functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the
corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to
the corresponding peripheral registers from software. For details on calibration conditions, refer to “Electrical
Characteristics” on page 76.
The production signature row also contains an ID that identifies each microcontroller device type and a serial number for
each manufactured device. The serial number consists of the production lot number, wafer number, and wafer
coordinates for the device. The device ID for the available devices is shown in Table 8-1.
The production signature row cannot be written or erased, but it can be read from application software and external
programmers.
Table 8-1. Device ID bytes.
8.3.5 User Signature Row
The user signature row is a separate memory section that is fully accessible (read and write) from application software
and external programmers. It is one flash page in size, and is meant for static user parameter storage, such as calibration
data, custom serial number, identification numbers, random number seeds, etc. This section is not erased by chip erase
commands that erase the flash, and requires a dedicated erase command. This ensures parameter storage during
multiple program/erase operations and on-chip debug sessions.
8.4 Fuses and Lock bits
The fuses are used to configure important system functions, and can only be written from an external programmer. The
application software can read the fuses. The fuses are used to configure reset sources such as brownout detector and
watchdog, startup configuration, JTAG enable, and JTAG user ID.
The lock bits are used to set protection levels for the different flash sections (that is, if read and/or write access should be
blocked). Lock bits can be written by external programmers and application software, but only to stricter protection levels.
Chip erase is the only way to erase the lock bits. To ensure that flash contents are protected even during chip erase, the
lock bits are erased after the rest of the flash memory has been erased.
An unprogrammed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value zero.
Both fuses and lock bits are reprogrammable like the flash program memory.
8.5 Data Memory
The data memory contains the I/O memory, internal SRAM, optionally memory mapped EEPROM, and external memory
if available. The data memory is organized as one continuous memory section, see Figure 8-2 on page 15. To simplify
development, I/O Memory, EEPROM and SRAM will always have the same start addresses for all Atmel AVR XMEGA
devices. The address space for External Memory will always start at the end of Internal SRAM and end at address
0xFFFFFF.
Device Device ID bytes
Byte 2 Byte 1 Byte 0
ATxmega64A1 4E 96 1E
ATxmega128A1 4C 97 1E[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 15
8067O–AVR–06/2013
Figure 8-2. Data Memory Map (Hexadecimal address)
8.6 EEPROM
XMEGA AU devices have EEPROM for nonvolatile data storage. It is either addressable in a separate data space
(default) or memory mapped and accessed in normal data space. The EEPROM supports both byte and page access.
Memory mapped EEPROM allows highly efficient EEPROM reading and EEPROM buffer loading. When doing this,
EEPROM is accessible using load and store instructions. Memory mapped EEPROM will always start at hexadecimal
address 0x1000.
8.7 I/O Memory
The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O
memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions,
which is used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT
instructions can address I/O memory locations in the range 0x00 - 0x3F directly. In the address range 0x00 - 0x1F,
single- cycle instructions for manipulation and checking of individual bits are available.
The I/O memory address for all peripherals and modules in XMEGA A1U is shown in the “Peripheral Module Address
Map” on page 62.
8.7.1 General Purpose I/O Registers
The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for
storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
8.8 External Memory
Four ports can be used for external memory, supporting external SRAM, SDRAM, and memory mapped peripherals such
as LCD displays. Refer to “EBI – External Bus Interface” on page 47. The external memory address space will always
start at the end of internal SRAM.
8.9 Data Memory and Bus Arbitration
Since the data memory is organized as four separate sets of memories, the different bus masters (CPU, DMA controller
read and DMA controller write, etc.) can access different memory sections at the same time.
Byte Address ATxmega128A1 Byte Address ATxmega64A1
0 I/O Registers
(4 KB)
0 I/O Registers
FFF FFF (4 KB)
1000 EEPROM
(2 KB)
1000 EEPROM
17FF 17FF (2 KB)
RESERVED RESERVED
2000 Internal SRAM
(8 KB)
2000 Internal SRAM
3FFF 2FFF (4 KB)
4000 External Memory
(0 to 16 MB)
3000 External Memory
FFFFFF FFFFFF (0 to 16 MB)[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 16
8067O–AVR–06/2013
8.10 Memory Timing
Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from
SRAM takes two cycles. For burst read (DMA), new data are available every cycle. EEPROM page load (write) takes one
cycle, and three cycles are required for read. For burst read, new data are available every second cycle. External
memory has multi-cycle read and write. The number of cycles depends on the type of memory and configuration of the
external bus interface. Refer to the instruction summary for more details on instructions and instruction timing.
8.11 Device ID and Revision
Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A
separate register contains the revision number of the device.
8.12 I/O Memory Protection
Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the
I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the lock is
enabled, all related I/O registers are locked and they can not be written from the application software. The lock registers
themselves are protected by the configuration change protection mechanism.
8.13 JTAG Disable
It is possible to disable the JTAG interface from the application software. This will prevent all external JTAG access to the
device until the next device reset or until JTAG is enabled again from the application software. As long as JTAG is
disabled, the I/O pins required for JTAG can be used as normal I/O pins.
8.14 Flash and EEPROM Page Size
The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the
flash and byte accessible for the EEPROM.
Table 8-2 shows the Flash Program Memory organization. Flash write and erase operations are performed on one page
at a time, while reading the Flash is done one byte at a time. For Flash access the Z-pointer (Z[m:n]) is used for
addressing. The most significant bits in the address (FPAGE) gives the page number and the least significant address
bits (FWORD) gives the word in the page.
Table 8-2. Number of words and Pages in the Flash.
Table 8-3 shows EEPROM memory organization for the Atmel AVR XMEGA A1U devices. EEPROM write and erase
operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at a time. For
EEPROM access the NVM Address Register (ADDR[m:n]) is used for addressing. The most significant bits in the
address (E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the page.
Device PC size Flash
Page
Size FWORD FPAGE Application Boot
bits bytes words Size No of
pages
Size No of
pages
ATxmega64A1 16 64K + 4K 128 Z[7:1] Z[16:8] 64K 256 4K 16
ATxmega128A1 17 128K+ 8K 256 Z[8:1] Z[17:9] 128K 256 8K 16[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 17
8067O–AVR–06/2013
Table 8-3. Number of Bytes and Pages in the EEPROM.
8.14.1 I/O Memory
All peripherals and modules are addressable through I/O memory locations in the data memory space. All I/O memory
locations can be accessed by the Load (LD/LDS/LDD) and Store (ST/STS/STD) instructions, transferring data between
the 32 general purpose registers in the CPU and the I/O Memory.
The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F directly.
I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. The
value of single bits can be checked by using the SBIS and SBIC instructions on these registers.
The I/O memory address for all peripherals and modules in XMEGA A1 is shown in the “Peripheral Module Address Map”
on page 62.
Device EEPROM Page Size E2BYTE E2PAGE No of pages
Size bytes
ATxmega64A1 2 KB 32 ADDR[4:0] ADDR[10:5] 64
ATxmega128A1 2 KB 32 ADDR[4:0 ADDR[10:5] 64[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 18
8067O–AVR–06/2013
9. DMAC - Direct Memory Access Controller
9.1 Features
Allows High-speed data transfer
From memory to peripheral
From memory to memory
From peripheral to memory
From peripheral to peripheral
4 Channels
From 1 byte and up to 16M bytes transfers in a single transaction
Multiple addressing modes for source and destination address
Increment
Decrement
Static
1, 2, 4, or 8 byte Burst Transfers
Programmable priority between channels
9.2 Overview
The four-channel direct memory access (DMA) controller can transfer data between memories and peripherals, and thus
offload these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU
time. The four DMA channels enable up to four independent and parallel transfers.
The DMA controller can move data between SRAM and peripherals, between SRAM locations and directly between
peripheral registers. With access to all peripherals, the DMA controller can handle automatic transfer of data to/from
communication modules. The DMA controller can also read from memory mapped EEPROM.
Data transfers are done in continuous bursts of 1, 2, 4, or 8 bytes. They build block transfers of configurable size from 1
byte to 64KB. A repeat counter can be used to repeat each block transfer for single transactions up to 16MB. Source and
destination addressing can be static, incremental or decremental. Automatic reload of source and/or destination
addresses can be done after each burst or block transfer, or when a transaction is complete. Application software,
peripherals, and events can trigger DMA transfers.
The four DMA channels have individual configuration and control settings. This include source, destination, transfer
triggers, and transaction sizes. They have individual interrupt settings. Interrupt requests can be generated when a
transaction is complete or when the DMA controller detects an error on a DMA channel.
To allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer when the
first is finished, and vice versa.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 19
8067O–AVR–06/2013
10. Event System
10.1 Features
Inter-peripheral communication and signalling with minimum latency
CPU and DMA independent operation
8 Event Channels allows for up to 8 signals to be routed at the same time
Events can be generated by
Timer/Counters (TCxn)
Real Time Counter (RTC)
Analog to Digital Converters (ADCx)
Analog Comparators (ACx)
Ports (PORTx)
System Clock (ClkSYS)
Software (CPU)
Events can be used by
Timer/Counters (TCxn)
Analog to Digital Converters (ADCx)
Digital to Analog Converters (DACx)
Ports (PORTx)
DMA Controller (DMAC)
IR Communication Module (IRCOM)
The same event can be used by multiple peripherals for synchronized timing
Advanced Features
Manual Event Generation from software (CPU)
Quadrature Decoding
Digital Filtering
Functions in Active and Idle mode
10.2 Overview
The Event System is a set of features for inter-peripheral communication. It enables the possibility for a change of state
in one peripheral to automatically trigger actions in one or more peripherals. These changes in a peripheral that will
trigger actions in other peripherals are configurable by software. It is a simple, but powerful system as it allows for
autonomous control of peripherals without any use of interrupts, CPU or DMA resources.
The indication of a change in a peripheral is referred to as an event, and is usually the same as the interrupt conditions
for that peripheral. Events are passed between peripherals using a dedicated routing network called the Event Routing
Network. Figure 10-1 on page 20 shows a basic block diagram of the Event System with the Event Routing Network and
the peripherals to which it is connected. This highly flexible system can be used for simple routing of signals, pin
functions or for sequencing of events.
The maximum latency is two CPU clock cycles from when an event is generated in one peripheral, until the actions are
triggered in one or more other peripherals.
The Event System is functional in both Active and Idle modes.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 20
8067O–AVR–06/2013
Figure 10-1. Event system block diagram.
he event routing network consists of eight software-configurable multiplexers that control how events are routed and
used. These are called event channels, and allow for up to eight parallel event routing configurations. The maximum
routing latency is two peripheral clock cycles. The event system works in both active mode and idle sleep mode.
DAC Timer /
Counters
ADC
Real Time
Counter
Port pins
CPU /
Software
DMA
Controller
IRCOM
Event Routing Network
Event
System
Controller
clkPER
Prescaler
AC[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 21
8067O–AVR–06/2013
11. System Clock and Clock options
11.1 Features
Fast start-up time
Safe run-time clock switching
Internal Oscillators:
32 MHz run-time calibrated RC oscillator
2 MHz run-time calibrated RC oscillator
32.768 kHz calibrated RC oscillator
32 kHz Ultra Low Power (ULP) oscillator with 1 kHz ouput
External clock options
0.4 - 16 MHz Crystal Oscillator
32 kHz Crystal Oscillator
External clock
PLL with internal and external clock options with 1 to 31x multiplication
Clock Prescalers with 1x to 2048x division
Fast peripheral clock running at two and four times the CPU clock speed
Automatic Run-Time Calibration of internal oscillators
Crystal Oscillator failure detection
11.2 Overview
Atmel AVR XMEGA devices have a flexible clock system supporting a large number of clock sources. It incorporates
both accurate internal oscillators and external crystal oscillator and resonator support. A high-frequency phase locked
loop (PLL) and clock prescalers can be used to generate a wide range of clock frequencies. An oscillator failure monitor
can be enabled to issue a non-maskable interrupt and switch to the internal oscillator if the external oscillator or PLL fails.
When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device
will always start up running from the 2MHz internal oscillator. During normal operation, the system clock source and
prescalers can be changed from software at any time.
Figure 11-1 on page 22 presents the principal clock system in the XMEGA A1U family devices. Not all of the clocks need
to be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and power
reduction registers as described in “Power Management and Sleep Modes” on page 24.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 22
8067O–AVR–06/2013
Figure 11-1. The clock system, clock sources and clock distribution
11.3 Clock Options
The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the clock
sources can be directly enabled and disabled from software, while others are automatically enabled or disabled,
depending on peripheral settings. After reset, the device starts up running from the 2MHz internal oscillator. The other
clock sources and PLL are turned off by default.
The internal oscillators do not require any external components to run. For details on characteristics and accuracy of the
internal oscillators, refer to the device datasheet.
11.3.1 32 kHz Ultra Low Power Internal Oscillator
This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low
power clock source, and it is not designed for high accuracy. The oscillator employs a built-in prescaler that provides a
1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device.
This oscillator can be selected as the clock source for the RTC.
Real Time
Counter Peripherals RAM AVR CPU Non-Volatile
Memory
Watchdog
Timer
Brown-out
Detector
System Clock Prescalers
System Clock Multiplexer
(SCLKSEL)
PLLSRC
RTCSRC
DIV32
32 kHz
Int. ULP
32.768 kHz
Int. OSC
32.768 kHz
TOSC
2 MHz
Int. Osc
32 MHz
Int. Osc
0.4 – 16 MHz
XTAL
DIV32
DIV32
DIV4
XOSCSEL
PLL
TOSC1
TOSC2
XTAL1
XTAL2
clkSYS clkRTC
clkPER2
clkPER
clkCPU
clkPER4[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 23
8067O–AVR–06/2013
11.3.2 32.768 kHz Calibrated Internal Oscillator
This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency
close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the
oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz
output.
11.3.3 32.768 kHz Crystal Oscillator
A 32.768kHz crystal oscillator can be connected between the 1 and 2 pins and enables a dedicated low frequency
oscillator input circuit. A low power mode with reduced voltage swing on 2 is available. This oscillator can be used as a
clock source for the system clock and RTC.
11.3.4 0.4 - 16 MHz Crystal Oscillator
This oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4 - 16MHz.
11.3.5 2 MHz Run-time Calibrated Internal Oscillator
The 2MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated during production to
provide a default frequency which is close to its nominal frequency. The oscillator can use the 32kHz Calibrated Internal
Oscillator or the 32kHz Crystal Oscillator as a source for calibrating the frequency run-time to compensate for
temperature and voltage drift hereby optimizing the accuracy of the oscillator.
11.3.6 32 MHz Run-time Calibrated Internal Oscillator
The 32MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated during production to
provide a default frequency which is close to its nominal frequency. The oscillator can use the 32kHz Calibrated Internal
Oscillator or the 32kHz Crystal Oscillator as a source for calibrating the frequency run-time to compensate for
temperature and voltage drift hereby optimizing the accuracy of the oscillator.
11.3.7 External Clock input
The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator.
XTAL1 can be used as input for an external clock signal. The 1 and 2 pins is dedicated to driving a 32.768kHz crystal
oscillator.
11.3.8 PLL with Multiplication factor 1 - 31x
The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a userselectable
multiplication factor of from 1 to 31. In combination with the prescalers, this gives a wide range of output
frequencies from all clock sources.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 24
8067O–AVR–06/2013
12. Power Management and Sleep Modes
12.1 Features
Power management for adjusting power consumption and functions
5 sleep modes
Idle
Power-down
Power-save
Standby
Extended standby
Power reduction register to disable clock and turn off unused peripherals in active and idle modes
12.2 Overview
Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.
This enables the Atmel AVR XMEGA microcontroller to stop unused modules to save power.
All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing application
code. When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the
device again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals
and all enabled reset sources can restore the microcontroller from sleep to active mode.
In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. When
this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. This
reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power
management than sleep modes alone.
12.3 Sleep Modes
Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. XMEGA
microcontrollers have five different sleep modes tuned to match the typical functional stages during application
execution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to wake the
device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. When an
enabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normal
program execution from the first instruction after the SLEEP instruction. If other, higher priority interrupts are pending
when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt
service routine for the wake-up interrupt is executed. After wake-up, the CPU is halted for four cycles before execution
starts.
The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device will
reset, start up, and execute from the reset vector.
12.3.1 Idle Mode
In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed), but
all peripherals, including the interrupt controller, event system and DMA controller are kept running. Any enabled
interrupt will wake the device.
12.3.2 Power-down Mode
In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of
asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the twowire
interface address match interrupt and asynchronous port interrupts, e.g pin change.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 25
8067O–AVR–06/2013
12.3.3 Power-save Mode
Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep
running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt.
12.3.4 Standby Mode
Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running
while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time.
12.3.5 Extended Standby Mode
Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are
kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 26
8067O–AVR–06/2013
13. System Control and Reset
13.1 Features
Multiple reset sources for safe operation and device reset
Power-On Reset
External Reset
Watchdog Reset
Brown-Out Reset
PDI reset
Software reset
Asynchronous reset
No running clock in the device is required for reset
Reset status register
13.2 Overview
The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where
operation should not start or continue, such as when the microcontroller operates below its power supply rating. If a reset
source goes active, the device enters and is kept in reset until all reset sources have released their reset. The I/O pins
are immediately tri-stated. The program counter is set to the reset vector location, and all I/O registers are set to their
initial values. The SRAM content is kept. However, if the device accesses the SRAM when a reset occurs, the content of
the accessed location can not be guaranteed.
After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts
running from the reset vector address. By default, this is the lowest program memory address, 0, but it is possible to
move the reset vector to the lowest address in the boot section.
The reset functionality is asynchronous, and so no running system clock is required to reset the device. The software
reset feature makes it possible to issue a controlled system reset from the user software.
The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and shows
which sources have issued a reset since the last power-on.
13.3 Reset Sequence
A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is
active. When all reset requests are released, the device will go through three stages before the device starts running
again:
Reset counter delay
Oscillator startup
Oscillator calibration
If another reset requests occurs during this process, the reset sequence will start over again.
13.4 Reset Sources
13.4.1 Power-On Reset
TA power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the VCC rises and
reaches the POR threshold voltage (VPOT), and this will start the reset sequence.
The POR is also activated to power down the device properly when the VCC falls and drops below the VPOT level.
The VPOT level is higher for falling VCC than for rising VCC. Consult the datasheet for POR characteristics data.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 27
8067O–AVR–06/2013
13.4.2 Brownout Detection
The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed,
programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip
erase and when the PDI is enabled.
13.4.3 External Reset
The external reset circuit is connected to the external RESET pin. The external reset will trigger when the RESET pin is
driven below the RESET pin threshold voltage, VRST, for longer than the minimum pulse period, tEXT. The reset will be
held as long as the pin is kept low. The RESET pin includes an internal pull-up resistor.
13.4.4 Watchdog Reset
The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from
the software within a programmable timeout period, a watchdog reset will be given. The watchdog reset is active for one
to two clock cycles of the 2MHz internal oscillator. For more details see “WDT - Watchdog Timer” on page 28.
13.4.5 Software reset
The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset
control register.The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to execute any
instruction from when a software reset is requested until it is issued.
13.4.6 Program and Debug Interface Reset
The program and debug interface reset contains a separate reset source that is used to reset the device during external
programming and debugging. This reset source is accessible only from external debuggers and programmers.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 28
8067O–AVR–06/2013
13.5 WDT - Watchdog Timer
13.5.1 Features
Issues a device reset if the timer is not reset before its timeout period
Asynchronous operation from dedicated oscillator
1kHz output of the 32kHz ultra low power oscillator
11 selectable timeout periods, from 8ms to 8s
Two operation modes:
Normal mode
Window mode
Configuration lock to prevent unwanted changes
13.6 Overview
The watchdog timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover
from error situations such as runaway or deadlocked code. The WDT is a timer, configured to a predefined timeout
period, and is constantly running when enabled. If the WDT is not reset within the timeout period, it will issue a
microcontroller reset. The WDT is reset by executing the WDR (watchdog timer reset) instruction from the application
code.
The window mode makes it possible to define a time slot or window inside the total timeout period during which WDT
must be reset. If the WDT is reset outside this window, either too early or too late, a system reset will be issued.
Compared to the normal mode, this can also catch situations where a code error causes constant WDR execution.
The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a CPU-independent clock
source, and will continue to operate to issue a system reset even if the main clocks fail.
The configuration change protection mechanism ensures that the WDT settings cannot be changed by accident. For
increased safety, a fuse for locking the WDT settings is also available.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 29
8067O–AVR–06/2013
14. Interrupts and Programmable Multilevel Interrupt Controller
14.1 Features
Short and predictable interrupt response time
Separate interrupt configuration and vector address for each interrupt
Programmable multilevel interrupt controller
Interrupt prioritizing according to level and vector address
Three selectable interrupt levels for all interrupts: low, medium and high
Selectable, round-robin priority scheme within low-level interrupts
Non-maskable interrupts for critical functions
Interrupt vectors optionally placed in the application section or the boot loader section
14.2 Overview
Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have
one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it
will generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt
controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged
by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed.
All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are
prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level
interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the
interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest
interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are
serviced within a certain amount of time.
Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions.
14.3 Interrupt vectors
The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts in
each peripheral. The base addresses for the Atmel AVR XMEGA A1U devices are shown in Table 14-1. Offset
addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA AU manual. For
peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 14-1. The program address is
the word address.
Table 14-1. Reset and Interrupt vectors
Program Address
(Base Address) Source Interrupt Description
0x000 RESET
0x002 OSCF_INT_vect Crystal Oscillator Failure Interrupt vector (NMI)
0x004 PORTC_INT_base Port C Interrupt base
0x008 PORTR_INT_base Port R Interrupt base
0x00C DMA_INT_base DMA Controller Interrupt base
0x014 RTC_INT_base Real Time Counter Interrupt base
0x018 TWIC_INT_base Two-Wire Interface on Port C Interrupt base[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 30
8067O–AVR–06/2013
0x01C TCC0_INT_base Timer/Counter 0 on port C Interrupt base
0x028 TCC1_INT_base Timer/Counter 1 on port C Interrupt base
0x030 SPIC_INT_vect SPI on port C Interrupt vector
0x032 USARTC0_INT_base USART 0 on port C Interrupt base
0x038 USARTC1_INT_base USART 1 on port C Interrupt base
0x03E AES_INT_vect AES Interrupt vector
0x040 NVM_INT_base Non-Volatile Memory Interrupt base
0x044 PORTB_INT_base Port B Interrupt base
0x048 ACB_INT_base Analog Comparator on Port B Interrupt base
0x04E ADCB_INT_base Analog to Digital Converter on Port B Interrupt base
0x056 PORTE_INT_base Port E Interrupt base
0x05A TWIE_INT_base Two-Wire Interface on Port E Interrupt base
0x05E TCE0_INT_base Timer/Counter 0 on port E Interrupt base
0x06A TCE1_INT_base Timer/Counter 1 on port E Interrupt base
0x072 SPIE_INT_vect SPI on port E Interrupt vector
0x074 USARTE0_INT_base USART 0 on port E Interrupt base
0x07A USARTE1_INT_base USART 1 on port E Interrupt base
0x080 PORTD_INT_base Port D Interrupt base
0x084 PORTA_INT_base Port A Interrupt base
0x088 ACA_INT_base Analog Comparator on Port A Interrupt base
0x08E ADCA_INT_base Analog to Digital Converter on Port A Interrupt base
0x096 TWID_INT_base Two-Wire Interface on Port D Interrupt base
0x09A TCD0_INT_base Timer/Counter 0 on port D Interrupt base
0x0A6 TCD1_INT_base Timer/Counter 1 on port D Interrupt base
0x0AE SPID_INT_vector SPI on port D Interrupt vector
0x0B0 USARTD0_INT_base USART 0 on port D Interrupt base
0x0B6 USARTD1_INT_base USART 1 on port D Interrupt base
0x0BC PORTQ_INT_base Port Q INT base
0x0C0 PORTH_INT_base Port H INT base
0x0C4 PORTJ_INT_base Port J INT base
0x0C8 PORTK_INT_base Port K INT base
0x0D0 PORTF_INT_base Port F INT base
0x0D4 TWIF_INT_base Two-Wire Interface on Port F INT base
Program Address
(Base Address) Source Interrupt Description[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 31
8067O–AVR–06/2013
0x0D8 TCF0_INT_base Timer/Counter 0 on port F Interrupt base
0x0E4 TCF1_INT_base Timer/Counter 1 on port F Interrupt base
0x0EC SPIF_INT_vector SPI ion port F Interrupt base
0x0EE USARTF0_INT_base USART 0 on port F Interrupt base
0x0F4 USARTF1_INT_base USART 1 on port F Interrupt base
Program Address
(Base Address) Source Interrupt Description[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 32
8067O–AVR–06/2013
15. I/O Ports
15.1 Features
78 General purpose input and output pins with individual configuration
Output driver with configurable driver and pull settings:
Totem-pole
Wired-AND
Wired-OR
Bus-keeper
Inverted I/O
Input with synchronous and/or asynchronous sensing with interrupts and events
Sense both edges
Sense rising edges
Sense falling edges
Sense low level
Optional pull-up and pull-down resistor on input and Wired-OR/AND configurations
Optional slew rate control
Asynchronous pin change sensing that can wake the device from all sleep modes
Two port interrupts with pin masking per I/O port
Efficient and safe access to port pins
Hardware read-modify-write through dedicated toggle/clear/set registers
Configuration of multiple pins in a single operation
Mapping of port registers into bit-accessible I/O memory space
Peripheral clocks output on port pin
Real-time counter clock output to port pin
Event channels can be output on port pin
Remapping of digital peripheral pin functions
Selectable USART, SPI, and timer/counter input/output pin locations
15.2 Overview
One port consists of up to eight port pins: pin 0 to 7. Each port pin can be configured as input or output with configurable
driver and pull settings. They also implement synchronous and asynchronous input sensing with interrupts and events for
selectable pin change conditions. Asynchronous pin-change sensing means that a pin change can wake the device from
all sleep modes, included the modes where no clocks are running.
All functions are individual and configurable per pin, but several pins can be configured in a single operation. The pins
have hardware read-modify-write (RMW) functionality for safe and correct change of drive value and/or pull resistor
configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other
pin.
The port pin configuration also controls input and output selection of other device functions. It is possible to have both the
peripheral clock and the real-time clock output to a port pin, and available for external use. The same applies to events
from the event system that can be used to synchronize and control external functions. Other digital peripherals, such as
USART, SPI, and timer/counters, can be remapped to selectable pin locations in order to optimize pin-out versus
application needs.
The notation of these ports are PORTA, PORTB, PORTC, PORTD, PORTE, PORTF, PORTH, PORTJ, PORTK, PORTQ
and PORTR.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 33
8067O–AVR–06/2013
15.3 Output Driver
All port pins (Pn) have programmable output configuration. The port pins also have configurable slew rate limitation to
reduce electromagnetic emission.
15.3.1 Push-pull
Figure 15-1. I/O configuration - Totem-pole
15.3.2 Pull-down
Figure 15-2. I/O configuration - Totem-pole with pull-down (on input)
15.3.3 Pull-up
Figure 15-3. I/O configuration - Totem-pole with pull-up (on input)
INn
OUTn
DIRn
Pn
INn
OUTn
DIRn
Pn
INn
OUTn
DIRn
Pn[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 34
8067O–AVR–06/2013
15.3.4 Bus-keeper
The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level
was ‘1’, and pull-down if the last level was ‘0’.
Figure 15-4. I/O configuration - Totem-pole with bus-keeper
15.3.5 Others
Figure 15-5. Output configuration - Wired-OR with optional pull-down
Figure 15-6. I/O configuration - Wired-AND with optional pull-up
INn
OUTn
DIRn
Pn
INn
OUTn
Pn
INn
OUTn
Pn[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 35
8067O–AVR–06/2013
15.4 Input sensing
Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is
shown in Figure 15-7 on page 35.
Figure 15-7. Input sensing system overview
When a pin is configured with inverted I/O the pin value is inverted before the input sensing.
15.5 Port Interrupt
Each ports have two interrupts with seperate priority and interrupt vector. All pins on the port can be individually selected
as source for each of the interrupts. The interrupts are then triggered according to the input sense configuration for each
pin configured as source for the interrupt.
15.6 Alternate Port Functions
In addition to the input/output functions on all port pins, most pins have alternate functions. This means that other
modules or peripherals connected to the port can use the port pins for their functions, such as communication or pulsewidth
modulation. “Pinout and Pin Functions” on page 55 shows which modules on peripherals that enables alternate
functions on a pin, and what alternate functions that is available on a pin.
INVERTED I/O
Interrupt
Control IREQ
Event
Pn
D Q
R
D Q
R
Synchronizer
INn
EDGE
DETECT
Asynchronous sensing
Synchronous sensing
EDGE
DETECT[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 36
8067O–AVR–06/2013
16. T/C - 16-bit Timer/Counter
16.1 Features
Eight 16-bit Timer/Counters
Four Timer/Counters of type 0
Four Timer/Counters of type 1
Four Compare or Capture (CC) Channels in Timer/Counter 0
Two Compare or Capture (CC) Channels in Timer/Counter 1
Double Buffered Timer Period Setting
Double Buffered Compare or Capture Channels
Waveform Generation:
Single Slope Pulse Width Modulation
Dual Slope Pulse Width Modulation
Frequency Generation
Input Capture:
Input Capture with Noise Cancelling
Frequency capture
Pulse width capture
32-bit input capture
Event Counter with Direction Control
Timer Overflow and Timer Error Interrupts and Events
One Compare Match or Capture Interrupt and Event per CC Channel
Supports DMA Operation
Hi-Resolution Extension (Hi-Res)
Advanced Waveform Extension (AWEX)
16.2 Overview
Atmel AVR XMEGA devices have a set of eight flexible 16-bit timer/counters (TC). Their capabilities include accurate
program execution timing, frequency and waveform generation, and input capture with time and frequency measurement
of digital signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit capture.
A timer/counter consists of a base counter and a set of compare or capture (CC) channels. The base counter can be
used to count clock cycles or events. It has direction control and period setting that can be used for timing. The CC
channels can be used together with the base counter to do compare match control, frequency generation, and pulse
width waveform modulation, as well as various input capture operations. A timer/counter can be configured for either
capture or compare functions, but cannot perform both at the same time.
A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system.
The event system can also be used for direction control and capture trigger or to synchronize operations.
There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and
timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0.
Only Timer/Counter 0 has the split mode feature that split it into 2 8-bit Timer/Counters with four compare channels each.
Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced
waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and highside
output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers. It can
also generate a synchronized bit pattern across the port pins.
The advanced waveform extension can be enabled to provide extra and more advanced features for the Timer/Counter.
This is only available for Timer/Counter 0. See “AWeX - Advanced Waveform Extension” on page 38 for more details.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 37
8067O–AVR–06/2013
The high-resolution (hi-res) extension can be used to increase the waveform output resolution by four or eight times by
using an internal clock source running up to four times faster than the peripheral clock. See “Hi-Res - High Resolution
Extension” on page 39 for more details.
Figure 16-1. Overview of a Timer/Counter and closely related peripherals
PORTC, PORTD, PORTE and PORTF each has one Timer/Counter 0 and one Timer/Counter1. Notation of these
Timer/Counters are TCC0 (Time/Counter C0), TCC1, TCD0, TCD1, TCE0, TCE1, TCF0, and TCF1, respectively.
AWeX
Compare/Capture Channel D
Compare/Capture Channel C
Compare/Capture Channel B
Compare/Capture Channel A
Waveform
Generation Buffer
Comparator
Hi-Res
Fault
Protection
Capture
Control
Base Counter
Counter
Control Logic
Timer Period
Prescaler
DTI
Dead-Time
Insertion
Pattern
Generation
clkPER4
PORT
Event
System
clkPER
Timer/Counter[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 38
8067O–AVR–06/2013
17. AWeX - Advanced Waveform Extension
17.1 Features
Output with complementary output from each Capture channel
Four Dead Time Insertion (DTI) Units, one for each Capture channel
8-bit DTI Resolution
Separate High and Low Side Dead-Time Setting
Double Buffered Dead-Time
Event Controlled Fault Protection
Single Channel Multiple Output Operation (for BLDC motor control)
Double Buffered Pattern Generation
17.2 Overview
The advanced waveform extension (AWeX) provides extra functions to the timer/counter in waveform generation (WG)
modes. It is primarily intended for use with different types of motor control and other power control applications. It
enables low- and high side output with dead-time insertion and fault protection for disabling and shutting down external
drivers. It can also generate a synchronized bit pattern across the port pins.
Each of the waveform generator outputs from the Timer/Counter 0 are split into a complimentary pair of outputs when
any AWeX features are enabled. These output pairs go through a dead-time insertion (DTI) unit that generates the noninverted
low side (LS) and inverted high side (HS) of the WG output with dead-time insertion between LS and HS
switching. The DTI output will override the normal port value according to the port override setting.
The pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In addition,
the WG output from compare channel A can be distributed to and override all the port pins. When the pattern generator
unit is enabled, the DTI unit is bypassed.
The fault protection unit is connected to the event system, enabling any event to trigger a fault condition that will disable
the AWeX output. The event system ensures predictable and instant fault reaction, and gives great flexibility in the
selection of fault triggers.
The AWeX is available for TCC0 and TCE0. The notation of these are AWEXC and AWEXE.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 39
8067O–AVR–06/2013
18. Hi-Res - High Resolution Extension
18.1 Features
Increases Waveform Generator resolution by 2-bits (4x)
Supports Frequency, single- and dual-slope PWM operation
Supports the AWeX when this is enabled and used for the same Timer/Counter
18.2 Overview
TThe high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a
timer/counter by four or eight. It can be used for a timer/counter doing frequency, single-slope PWM, or dual-slope PWM
generation. It can also be used with the AWeX if this is used for the same timer/counter.
The hi-res extension uses the peripheral 4x clock (ClkPER4). The system clock prescalers must be configured so the
peripheral 4x clock frequency is four times higher than the peripheral and CPU clock frequency when the hi-res extension
is enabled.
There are four hi-res extensions that each can be enabled for each timer/counters pair on PORTC, PORTD, PORTE and
PORTF. The notation of these peripherals are HIRESC, HIRESD, HIRESE and HIRESF, respectively.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 40
8067O–AVR–06/2013
19. RTC - 16-bit Real-Time Counter
19.1 Features
16-bit resolution
Selectable clock source
32.768kHz external crystal
External clock
32.768kHz internal oscillator
32kHz internal ULP oscillator
Programmable 10-bit clock prescaling
One compare register
One period register
Clear counter on period overflow
Optional interrupt/event on overflow and compare match
19.2 Overview
The 16-bit real-time counter (RTC) is a counter that typically runs continuously, including in low-power sleep modes, to
keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular intervals.
The reference clock is typically the 1.024kHz output from a high-accuracy crystal of 32.768kHz, and this is the
configuration most optimized for low power consumption. The faster 32.768kHz output can be selected if the RTC needs
a resolution higher than 1ms. The RTC can also be clocked from an external clock signal, the 32.768kHz internal
oscillator or the 32kHz internal ULP oscillator.
The RTC includes a 10-bit programmable prescaler that can scale down the reference clock before it reaches the
counter. A wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock source, the
maximum resolution is 30.5µs, and time-out periods can range up to 2000 seconds. With a resolution of 1s, the
maximum timeout period is more than18 hours (65536 seconds). The RTC can give a compare interrupt and/or event
when the counter equals the compare register value, and an overflow interrupt and/or event when it equals the period
register value.
Figure 19-1. Real Time Counter overview
32.768kHz Crystal Osc
32.768kHz Int. Osc
TOSC1
TOSC2
External Clock
DIV32
DIV32
32kHz int ULP (DIV32)
RTCSRC
10-bit
prescaler
clkRTC
CNT
PER
COMP
=
=
”match”/
Compare
TOP/
Overflow[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 41
8067O–AVR–06/2013
20. TWI - Two-Wire Interface
20.1 Features
Four identical two-wire interface peripherals
Bidirectional two-wire communication interface
Phillips I2C compatible
System Management Bus (SMBus) compatible
Bus master and slave operation supported
Slave operation
Single bus master operation
Bus master in multi-master bus environment
Multi-master arbitration
Flexible slave address match functions
7-bit and general call address recognition in hardware
10-bit addressing supported
Address mask register for dual address match or address range masking
Optional software address recognition for unlimited number of addresses
Slave can operate in all sleep modes, including power-down
Slave address match can wake device from all sleep modes, including power-down
100kHz and 400kHz bus frequency support
Slew-rate limited output drivers
Input filter for bus noise and spike suppression
Support arbitration between start repeated start and data bit (SMBus)
Slave arbitration allows support for address resolve protocol (ARP) (SMBus)
20.2 Overview
The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I2C and System Management Bus
(SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each bus line.
A device connected to the bus must act as a master or a slave. The master initiates a data transaction by addressing a
slave on the bus and telling whether it wants to transmit or receive data. One bus can have many slaves and one or
several masters that can take control of the bus. An arbitration process handles priority if more than one master tries to
transmit data at the same time. Mechanisms for resolving bus contention are inherent in the protocol.
The TWI module supports master and slave functionality. The master and slave functionality are separated from each
other, and can be enabled and configured separately. The master module supports multi-master bus operation and
arbitration. It contains the baud rate generator. Both 100kHz and 400kHz bus frequency is supported. Quick command
and smart mode can be enabled to auto-trigger operations and reduce software complexity.
The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is
also supported. A dedicated address mask register can act as a second address match register or as a register for
address range masking. The slave continues to operate in all sleep modes, including power-down mode. This enables
the slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the address
matching to let this be handled in software instead.
The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors, collision,
and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave
modes. [Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 42
8067O–AVR–06/2013
It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external
TWI bus driver. This can be used for applications where the device operates from a different VCC voltage than used by
the TWI bus.
PORTC, PORTD, PORTE, and PORTF each has one TWI. Notation of these peripherals are TWIC, TWID, TWIE, and
TWIF.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 43
8067O–AVR–06/2013
21. SPI - Serial Peripheral Interface
21.1 Features
Four identical SPI peripherals
Full-duplex, three-wire synchronous data transfer
Master or slave operation
Lsb first or msb first data transfer
Eight programmable bit rates
Interrupt flag at the end of transmission
Write collision flag to indicate data collision
Wake up from idle sleep mode
Double speed master mode
21.2 Overview
The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. It
allows fast communication between an Atmel AVR XMEGA device and peripheral devices or between several
microcontrollers. The SPI supports full-duplex communication.
A device connected to the bus must act as a master or slave. The master initiates and controls all data transactions.
PORTC, PORTD, PORTE, and PORTF each has one SPI. Notation of these peripherals are SPIC, SPID, SPIE, and
SPIF.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 44
8067O–AVR–06/2013
22. USART
22.1 Features
Eight identical USART peripherals
Full-duplex operation
Asynchronous or synchronous operation
Synchronous clock rates up to 1/2 of the device clock frequency
Asynchronous clock rates up to 1/8 of the device clock frequency
Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits
Fractional baud rate generator
Can generate desired baud rate from any system clock frequency
No need for external oscillator with certain frequencies
Built-in error detection and correction schemes
Odd or even parity generation and parity check
Data overrun and framing error detection
Noise filtering includes false start bit detection and digital low-pass filter
Separate interrupts for
Transmit complete
Transmit data register empty
Receive complete
Multiprocessor communication mode
Addressing scheme to address a specific devices on a multidevice bus
Enable unaddressed devices to automatically ignore all frames
Master SPI mode
Double buffered operation
Operation up to 1/2 of the peripheral clock frequency
IRCOM module for IrDA compliant pulse modulation/demodulation
22.2 Overview
The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible serial
communication module. The USART supports full-duplex communication and asynchronous and synchronous operation.
The USART can be configured to operate in SPI master mode and used for SPI communication.
Communication is frame based, and the frame format can be customized to support a wide range of standards. The
USART is buffered in both directions, enabling continued data transmission without any delay between frames. Separate
interrupts for receive and transmit complete enable fully interrupt driven communication. Frame error and buffer overflow
are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can
also be enabled.
The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART baud rates
from any system clock frequencies. This removes the need to use an external crystal oscillator with a specific frequency
to achieve a required baud rate. It also supports external clock input in synchronous slave operation.
When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and receive
buffers, shift registers, and baud rate generator enabled. Pin control and interrupt generation are identical in both modes.
The registers are used in both modes, but their functionality differs for some control settings.
An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and
demodulation for baud rates up to 115.2Kbps.
PORTC, PORTD, PORTE, and PORTF each has two USARTs. Notation of these peripherals are USARTC0, USARTC1,
USARTD0, USARTD1, USARTE0, USARTE1, USARTF0 and USARTF1.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 45
8067O–AVR–06/2013
23. IRCOM - IR Communication Module
23.1 Features
Pulse modulation/demodulation for infrared communication
IrDA compatible for baud rates up to 115.2Kbps
Selectable pulse modulation scheme
3/16 of the baud rate period
Fixed pulse period, 8-bit programmable
Pulse modulation disabled
Built-in filtering
Can be connected to and used by any USART
23.2 Overview
Atmel AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates
up to 115.2Kbps. It can be connected to any USART to enable infrared pulse encoding/decoding for that USART.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 46
8067O–AVR–06/2013
24. AES and DES Crypto Engine
24.1 Features
Data Encryption Standard (DES) CPU instruction
Advanced Encryption Standard (AES) crypto module
DES Instruction
Encryption and decryption
DES supported
Encryption/decryption in 16 CPU clock cycles per 8-byte block
AES crypto module
Encryption and decryption
Supports 128-bit keys
Supports XOR data load mode to the state memory
Encryption/decryption in 375 clock cycles per 16-byte block
24.2 Overview
The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two commonly used standards for
cryptography. These are supported through an AES peripheral module and a DES CPU instruction, and the
communication interfaces and the CPU can use these for fast, encrypted communication and secure data storage.
DES is supported by an instruction in the AVR CPU. The 8-byte key and 8-byte data blocks must be loaded into the
register file, and then the DES instruction must be executed 16 times to encrypt/decrypt the data block.
The AES crypto module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key. The key and data must
be loaded into the key and state memory in the module before encryption/decryption is started. It takes 375 peripheral
clock cycles before the encryption/decryption is done. The encrypted/encrypted data can then be read out, and an
optional interrupt can be generated. The AES crypto module also has DMA support with transfer triggers when
encryption/decryption is done and optional auto-start of encryption/decryption when the state memory is fully loaded.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 47
8067O–AVR–06/2013
25. EBI – External Bus Interface
25.1 Features
Supports SRAM up to:
512KB using 3-port EBI configuration
16MB using 3-port EBI configuration
Supports SDRAM up to:
128Mb using 3-port EBI configuration
Four software configurable chip selects
Software configurable wait state insertion
Can run from the 2x peripheral clock frequency for fast access
25.2 Overview
The External Bus Interface (EBI) is used to connect external peripherals and memory for access through the data
memory space. When the EBI is enabled, data address space outside the internal SRAM becomes available using
dedicated EBI pins.
The EBI can interface external SRAM, SDRAM, and peripherals, such as LCD displays and other memory mapped
devices.
The address space for the external memory is selectable from 256 bytes (8-bit) up to 16MB (24-bit). Various multiplexing
modes for address and data lines can be selected for optimal use of pins when more or fewer pins are available for the
EBI. The complete memory will be mapped into one linear data address space continuing from the end of the internal
SRAM.
The EBI has four chip selects, each with separate configuration. Each can be configured for SRAM, SRAM low pin count
(LPC), or SDRAM.
The EBI is clocked from the fast, 2x peripheral clock, running up to two times faster than the CPU.
Four-bit and eight-bit SDRAM are supported, and SDRAM configurations, such as CAS latency and refresh rate, are
configurable in software.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 48
8067O–AVR–06/2013
26. ADC - 12-bit Analog to Digital Converter
26.1 Features
Two ADCs with 12-bit resolution
2Msps sample rate for each ADC
Signed and unsigned conversions
4 result registers with individual input channel control for each ADC
8 single ended inputs for each ADC
8x4 differential inputs for each ADC
4 internal inputs:
Integrated Temperature Sensor
DAC Output
VCC voltage divided by 10
Bandgap voltage
Software selectable gain of 2, 4, 8, 16, 32 or 64
Software selectable resolution of 8- or 12-bit.
Internal or External Reference selection
Event triggered conversion for accurate timing
DMA transfer of conversion results
Interrupt/Event on compare result
26.2 Overview
XMEGA A1 devices have two Analog to Digital Converters (ADC), see Figure 26-1 on page 49. The two ADC modules
can be operated simultaneously, individually or synchronized.
The ADC converts analog voltages to digital values. The ADC has 12-bit resolution and is capable of converting up to 2
million samples per second. The input selection is flexible, and both single-ended and differential measurements can be
done. For differential measurements an optional gain stage is available to increase the dynamic range. In addition
several internal signal inputs are available. The ADC can provide both signed and unsigned results.
This is a pipeline ADC. A pipeline ADC consists of several consecutive stages, where each stage convert one part of the
result. The pipeline design enables high sample rate at low clock speeds, and remove limitations on samples speed
versus propagation delay. This also means that a new analog voltage can be sampled and a new ADC measurement
started while other ADC measurements are ongoing.
ADC measurements can either be started by application software or an incoming event from another peripheral in the
device. Four different result registers with individual input selection (MUX selection) are provided to make it easier for the
application to keep track of the data. Each result register and MUX selection pair is referred to as an ADC Channel. It is
possible to use DMA to move ADC results directly to memory or peripherals when conversions are done.
Both internal and external analog reference voltages can be used. An accurate internal 1.0V reference is available.
An integrated temperature sensor is available and the output from this can be measured with the ADC. The output from
the DAC, VCC/10 and the Bandgap voltage can also be measured by the ADC.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 49
8067O–AVR–06/2013
Figure 26-1. ADC overview
Each ADC has four MUX selection registers with a corresponding result register. This means that four channels can be
sampled within 1.5 µs without any intervention by the application other than starting the conversion. The results will be
available in the result registers.
The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 3.5
µs for 12-bit to 2.5 µs for 8-bit result.
ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This eases calculation when
the result is represented as a signed integer (signed 16-bit number).
PORTA and PORTB each has one ADC. Notation of these peripherals are ADCA and ADCB, respectively.
CH1 Result
CH0 Result
CH2 Result
Compare
<
>
Threshold
(Int Req)
Internal 1.00V
Internal VCC/1.6V
AREFA
AREFB
VINP
VINN
Internal
signals
Internal
signals
CH3 Result
ADC0
ADC7
ADC4
ADC7
ADC0
ADC3
•
•
•
Int. signals
Int. signals
Reference
Voltage
1x - 64x •
•
•
•
•
•
ADC0
ADC7
•
•
•[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 50
8067O–AVR–06/2013
27. DAC - 12-bit Digital to Analog Converter
27.1 Features
12-bit resolution
Two independent, continuous-drive output channels
Up to one million samples per second conversion rate
Built-in calibration that removes:
Offset error
Gain error
Multiple conversion trigger sources
On new available data
Events from the event system
High drive capabilities and support for
Resistive loads
Capacitive loads
Combined resistive and capacitive loads
Internal and external reference options
DAC output available as input to analog comparator and ADC
Low-power mode, with reduced drive strength
Optional DMA transfer of data
27.2 Overview
The XMEGA A1 devices features two 12-bit, 1 Msps DACs with built-in offset and gain calibration, see Figure 27-1 on
page 50.
A DAC converts a digital value into an analog signal. The DAC may use an internal 1.0 voltage as the upper limit for
conversion, but it is also possible to use the supply voltage or any applied voltage in-between. The external reference
input is shared with the ADC reference input.
Figure 27-1. DAC overview
CH1DATA
CH0DATA
Trigger
Internal 1.00V
AREFA
AREFB
AVCC
D
A
T
A
DAC CTRL
DAC CH0
REFSEL
Enable
12
12
ADC
DAC
DAC CH1
Output
Control and Driver[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 51
8067O–AVR–06/2013
Each DAC has one continuous output with high drive capabilities for both resistive and capacitive loads. It is also
possible to split the continuous time channel into two Sample and Hold (S/H) channels, each with separate data
conversion registers.
A DAC conversion may be started from the application software by writing the data conversion registers. The DAC can
also be configured to do conversions triggered by the Event System to have regular timing, independent of the
application software. DMA may be used for transferring data from memory locations to DAC data registers.
The DAC has a built-in calibration system to reduce offset and gain error when loading with a calibration value from
software.
PORTA and PORTB each has one DAC. Notation of these peripherals are DACA and DACB. respectively.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 52
8067O–AVR–06/2013
28. AC - Analog Comparator
28.1 Features
Four Analog Comparators
Selectable propagation delay versus current consumption
Selectable hysteresis
No
Small
Large
Analog comparator output available on pin
Flexible input selection
All pins on the port
Output from the DAC
Bandgap reference voltage
A 64-level programmable voltage scaler of the internal VCC voltage
Interrupt and event generation on:
Rising edge
Falling edge
Toggle
Window function interrupt and event generation on:
Signal above window
Signal inside window
Signal below window
Constant current source with configurable output pin selection
28.2 Overview
The analog comparator (AC) compares the voltage levels on two inputs and gives a digital output based on this
comparison. The analog comparator may be configured to generate interrupt requests and/or events upon several
different combinations of input change.
Two important properties of the analog comparator’s dynamic behavior are: hysteresis and propagation delay. Both of
these parameters may be adjusted in order to achieve the optimal operation for each application.
The input selection includes analog port pins, several internal signals, and a 64-level programmable voltage scaler. The
analog comparator output state can also be output on a pin for use by external devices.
A constant current source can be enabled and output on a selectable pin. This can be used to replace, for example,
external resistors used to charge capacitors in capacitive touch sensing applications.
The analog comparators are always grouped in pairs on each port. These are called analog comparator 0 (AC0) and
analog comparator 1 (AC1). They have identical behavior, but separate control registers. Used as pair, they can be set in
window mode to compare a signal to a voltage range instead of a voltage level.
PORTA and PORTB each has one AC pair. Notations are ACA and ACB, respectively.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 53
8067O–AVR–06/2013
Figure 28-1. Analog comparator overview
The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in
Figure 28-2.
Figure 28-2. Analog comparator window function
ACnMUXCTRL ACnCTRL
Interrupt
Mode
Enable
Enable
Hysteresis
Hysteresis
AC1OUT
WINCTRL
Interrupt
Sensititivity
Control
&
Window
Function
Events
Interrupts
AC0OUT
Pin Input
Pin Input
Pin Input
Pin Input
Voltage
Scaler
DAC
Bandgap
+
-
+
-
AC0
+
-
AC1
+
-
Input signal
Upper limit of window
Lower limit of window
Interrupt
sensitivity
control
Interrupts
Events[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 54
8067O–AVR–06/2013
29. Programming and Debugging
29.1 Features
Programming
External programming through PDI or JTAG interfaces
Minimal protocol overhead for fast operation
Built-in error detection and handling for reliable operation
Boot loader support for programming through any communication interface
Debugging
Nonintrusive, real-time, on-chip debug system
No software or hardware resources required from device except pin connection
Program flow control
Go, Stop, Reset, Step Into, Step Over, Step Out, Run-to-Cursor
Unlimited number of user program breakpoints
Unlimited number of user data breakpoints, break on:
Data location read, write, or both read and write
Data location content equal or not equal to a value
Data location content is greater or smaller than a value
Data location content is within or outside a range
No limitation on device clock frequency
Program and Debug Interface (PDI)
Two-pin interface for external programming and debugging
Uses the Reset pin and a dedicated pin
No I/O pins required during programming or debugging
JTAG interface
Four-pin, IEEE Std. 1149.1 compliant interface for programming and debugging
Boundary scan capabilities according to IEEE Std. 1149.1 (JTAG)
29.2 Overview
The Program and Debug Interface (PDI) is an Atmel proprietary interface for external programming and on-chip
debugging of a device.
The PDI supports fast programming of nonvolatile memory (NVM) spaces; flash, EEPOM, fuses, lock bits, and the user
signature row.
Debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. It does not require any
software or hardware resources except for the device pin connection. Using the Atmel tool chain, it offers complete
program flow control and support for an unlimited number of program and complex data breakpoints. Application debug
can be done from a C or other high-level language source code level, as well as from an assembler and disassembler
level.
Programming and debugging can be done through two physical interfaces. The primary one is the PDI physical layer,
which is available on all devices. This is a two-pin interface that uses the Reset pin for the clock input (PDI_CLK) and one
other dedicated pin for data input and output (PDI_DATA). A JTAG interface is also available on most devices, and this
can be used for programming and debugging through the four-pin JTAG interface. The JTAG interface is IEEE Std.
1149.1 compliant, and supports boundary scan. Any external programmer or on-chip debugger/emulator can be directly
connected to either of these interfaces. Unless otherwise stated, all references to the PDI assume access through the
PDI physical layer.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 55
8067O–AVR–06/2013
30. Pinout and Pin Functions
The pinout of XMEGA A1 is shown in “Pinout/Block Diagram” on page 3. In addition to general I/O functionality, each pin
may have several functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of
the alternate pin functions can be used at time.
30.1 Alternate Pin Function Description
The tables below shows the notation for all pin functions available and describes its function.
30.1.1 Operation/Power Supply
30.1.2 Port Interrupt functions
30.1.3 Analog functions
30.1.4 EBI functions
VCC Digital supply voltage
AVCC Analog supply voltage
GND Ground
SYNC Port pin with full synchronous and limited asynchronous interrupt function
ASYNC Port pin with full synchronous and full asynchronous interrupt function
ACn Analog Comparator input pin n
AC0OUT Analog Comparator 0 Output
ADCn Analog to Digital Converter input pin n
DACn Digital to Analog Converter output pin n
AREF Analog Reference input pin
An Address line n
Dn Data line n
CSn Chip Select n
ALEn Address Latch Enable pin n (SRAM)
RE Read Enable (SRAM)
WE External Data Memory Write (SRAM /SDRAM)
BAn Bank Address (SDRAM)
CAS Column Access Strobe (SDRAM)
CKE SDRAM Clock Enable (SDRAM)[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 56
8067O–AVR–06/2013
30.1.5 Timer/Counter and AWEX functions
30.1.6 Communication functions
30.1.7 Oscillators, Clock and Event
CLK SDRAM Clock (SDRAM)
DQM Data Mask Signal/Output Enable (SDRAM)
RAS Row Access Strobe (SDRAM)
2P 2 Port Interface
3P 3 Port Interface
OCnx Output Compare Channel x for Timer/Counter n
OCnx Inverted Output Compare Channel x for Timer/Counter n
OCnxLS Output Compare Channel x Low Side for Timer/Counter n
OCnxHS Output Compare Channel x High Side for Timer/Counter n
SCL Serial Clock for TWI
SDA Serial Data for TWI
SCLIN Serial Clock In for TWI when external driver interface is enabled
SCLOUT Serial Clock Out for TWI when external driver interface is enabled
SDAIN Serial Data In for TWI when external driver interface is enabled
SDAOUT Serial Data Out for TWI when external driver interface is enabled
XCKn Transfer Clock for USART n
RXDn Receiver Data for USART n
TXDn Transmitter Data for USART n
SS Slave Select for SPI
MOSI Master Out Slave In for SPI
MISO Master In Slave Out for SPI
SCK Serial Clock for SPI
n Timer Oscillator pin n
XTALn Input/Output for inverting Oscillator pin n
CLKOUT Peripheral Clock Output
EVOUT Event Channel 0 Output[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 57
8067O–AVR–06/2013
30.1.8 Debug/System functions
RESET Reset pin
PDI_CLK Program and Debug Interface Clock pin
PDI_DATA Program and Debug Interface Data pin
TCK JTAG Test Clock
TDI JTAG Test Data In
TDO JTAG Test Data Out
TMS JTAG Test Mode Select[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 58
8067O–AVR–06/2013
30.2 Alternate Pin Functions
The tables below show the primary/default function for each pin on a port in the first column, the pin number in the
second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that
enable and use the alternate pin functions.
Table 30-1. Port A - Alternate functions.
Table 30-2. Port B - Alternate functions.
Table 30-3. Port C - Alternate functions.
PORT A PIN # INTERRUPT ADCA
POS
ADCA
NEG
ADCA
GAINPOS
ADCA
GAINNEG
ACA
POS
ACA
NEG
ACA
OUT
DACA REFA
GND 93
AVCC 94
PA0 95 SYNC ADC0 ADC0 ADC0 AC0 AC0 AREF
PA1 96 SYNC ADC1 ADC1 ADC1 AC1 AC1
PA2 97 SYNC/ASYNC ADC2 ADC2 ADC2 AC2 DAC0
PA3 98 SYNC ADC3 ADC3 ADC3 AC3 AC3 DAC1
PA4 99 SYNC ADC4 ADC4 ADC4 AC4
PA5 100 SYNC ADC5 ADC5 ADC5 AC5 AC5
PA6 1 SYNC ADC6 ADC6 ADC6 AC6
PA7 2 SYNC ADC7 ADC7 ADC7 AC7 AC0OUT
PORT B PIN # INTERRUPT ADCB
POS
ADCB
NEG
ADCB
GAINPOS
ADCB
GAINNEG
ACB
POS
ACB
NEG
ACB
OUT
DACB REFB JTAG
GND 3
AVCC 4
PB0 5 SYNC ADC0 ADC0 ADC0 AC0 AC0 AREF
PB1 6 SYNC ADC1 ADC1 ADC1 AC1 AC1
PB2 7 SYNC/ASYNC ADC2 ADC2 ADC2 AC2 DAC0
PB3 8 SYNC ADC3 ADC3 ADC3 AC3 AC3 DAC1
PB4 9 SYNC ADC4 ADC4 ADC4 AC4 TMS
PB5 10 SYNC ADC5 ADC5 ADC5 AC5 AC5 TDI
PB6 11 SYNC ADC6 ADC6 ADC6 AC6 TCK
PB7 12 SYNC ADC7 ADC7 ADC7 AC7 AC0OUT TDO
PORT C PIN # INTERRUPT TCC0 AWEXC TCC1 USARTC0 USARTC1 SPIC TWIC CLOCKOUT EVENTOUT
GND 13
VCC 14
PC0 15 SYNC OC0A OC0ALS SDA
PC1 16 SYNC OC0B OC0AHS XCK0 SCL
PC2 17 SYNC/ASYNC OC0C OC0BLS RXD0[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 59
8067O–AVR–06/2013
Table 30-4. Port D - Alternate functions.
Table 30-5. Port E - Alternate functions.
Table 30-6. Port F - Alternate functions.
PC3 18 SYNC OC0D OC0BHS TXD0
PC4 19 SYNC OC0CLS OC1A SS
PC5 20 SYNC OC0CHS OC1B XCK1 MOSI
PC6 21 SYNC OC0DLS RXD1 MISO
PC7 22 SYNC OC0DHS TXD1 SCK CLKOUT EVOUT
PORT D PIN # INTERRUPT TCD0 TCD1 USARTD0 USARTD1 SPID TWID CLOCKOUT EVENTOUT
GND 23
VCC 24
PD0 25 SYNC OC0A SDA
PD1 26 SYNC OC0B XCK0 SCL
PD2 27 SYNC/ASYNC OC0C RXD0
PD3 28 SYNC OC0D TXD0
PD4 29 SYNC OC1A SS
PD5 30 SYNC OC1B XCK1 MOSI
PD6 31 SYNC RXD1 MISO
PD7 32 SYNC TXD1 SCK CLKOUT EVOUT
PORT E PIN # INTERRUPT TCE0 AWEXE TCE1 USARTE0 USARTE1 SPIE TWIE CLOCKOUT EVENTOUT
GND 33
VCC 34
PE0 35 SYNC OC0A OC0ALS SDA
PE1 36 SYNC OC0B OC0AHS XCK0 SCL
PE2 37 SYNC/ASYNC OC0C OC0BLS RXD0
PE3 38 SYNC OC0D OC0BHS TXD0
PE4 39 SYNC OC0CLS OC1A SS
PE5 40 SYNC OC0CHS OC1B XCK1 MOSI
PE6 41 SYNC OC0DLS RXD1 MISO
PE7 42 SYNC OC0DHS TXD1 SCK CLKOUT EVOUT
PORT F PIN # INTERRUPT TCF0 TCF1 USARTF0 USARTF1 SPIF TWIF
GND 43
VCC 44
PF0 45 SYNC OC0A SDA
PORT C PIN # INTERRUPT TCC0 AWEXC TCC1 USARTC0 USARTC1 SPIC TWIC CLOCKOUT EVENTOUT[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 60
8067O–AVR–06/2013
Table 30-7. Port H - Alternate functions.
Table 30-8. Port J - Alternate functions.
PF1 46 SYNC OC0B XCK0 SCL
PF2 47 SYNC/ASYNC OC0C RXD0
PF3 48 SYNC OC0D TXD0
PF4 49 SYNC OC1A SS
PF5 50 SYNC OC1B XCK1 MOSI
PF6 51 SYNC RXD1 MISO
PF7 52 SYNC TXD1 SCK
PORT H PIN # INTERRUPT SDRAM 3P SRAM ALE1 3P SRAM ALE12 3P LPC ALE1 3P LPC ALE1 2P LPC ALE12 2P
GND 53
VCC 54
PH0 55 SYNC WE WE WE WE WE WE
PH1 56 SYNC CAS RE RE RE RE RE
PH2 57 SYNC/ASYNC RAS ALE1 ALE1 ALE1 ALE1 ALE1
PH3 58 SYNC DQM ALE2 ALE2
PH4 59 SYNC BA0 CS0/A16 CS0 CS0/A16 CS0 CS0/A16
PH5 60 SYNC BA1 CS1/A17 CS1 CS1/A17 CS1 CS1/A17
PH6 61 SYNC CKE CS2/A18 CS2 CS2/A18 CS2 CS2/A18
PH7 62 SYNC CLK CS3/A19 CS3 CS3/A19 CS3 CS3/A19
PORT J PIN # INTERRUPT SDRAM 3P SRAM ALE1 3P SRAM ALE12 3P LPC ALE1 3P LPC ALE1 2P LPC ALE12 2P
GND 63
VCC 64
PJ0 65 SYNC D0 D0 D0 D0/A0 D0/A0 D0/A0/A8
PJ1 66 SYNC D1 D1 D1 D1/A1 D1/A1 D1/A1/A9
PJ2 67 SYNC/ASYNC D2 D2 D2 D2/A2 D2/A2 D2/A2/A10
PJ3 68 SYNC D3 D3 D3 D3/A3 D3/A3 D3/A3/A11
PJ4 69 SYNC A8 D4 D4 D4/A4 D4/A4 D4/A4/A12
PJ5 70 SYNC A9 D5 D5 D5/A5 D5/A5 D5/A5/A13
PJ6 71 SYNC A10 D6 D6 D6/A6 D6/A6 D6/A6/A14
PJ7 72 SYNC A11 D7 D7 D7/A7 D7/A7 D7/A7/A15
PORT F PIN # INTERRUPT TCF0 TCF1 USARTF0 USARTF1 SPIF TWIF[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 61
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Table 30-9. Port K - Alternate functions.
Table 30-10. Port Q - Alternate functions.
Table 30-11. Port R - Alternate functions.
PORT K PIN # INTERRUPT SDRAM 3P SRAM ALE1 3P SRAM ALE12 3P LPC ALE1 3P LPC ALE1 2P LPC ALE12 2P
GND 73
VCC 74
PK0 75 SYNC A0 A0/A8 A0/A8/A16 A8
PK1 76 SYNC A1 A1/A9 A1/A9/A17 A9
PK2 77 SYNC/ASYNC A2 A2/A10 A2/A10/A18 A10
PK3 78 SYNC A3 A3/A11 A3/A11/A19 A11
PK4 79 SYNC A4 A4/A12 A4/A12/A20 A12
PK5 80 SYNC A5 A5/A13 A5/A13/A21 A13
PK6 81 SYNC A6 A6/A14 A6/A14/A22 A14
PK7 82 SYNC A7 A7/A15 A7/A15/A23 A15
PORT Q PIN # INTERRUPT
VCC 83
GND 84
PQ0 85 SYNC TOSC1 (Input)
PQ1 86 SYNC TOSC2 (Output)
PQ2 87 SYNC/ASYNC
PQ3 88 SYNC
PORT R PIN # INTERRUPT PDI XTAL
PDI 89 PDI_DATA
RESET 90 PDI_CLOCK
PRO 91 SYNC XTAL2
PR1 92 SYNC XTAL1[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 62
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31. Peripheral Module Address Map
The address maps show the base address for each peripheral and module in XMEGA A1. For complete register
description and summary for each peripheral module, refer to the XMEGA A Manual.
Table 31-1. Peripheral Module Address Map
Base Address Name Description
0x0000 GPIO General Purpose IO Registers
0x0010 VPORT0 Virtual Port 0
0x0014 VPORT1 Virtual Port 1
0x0018 VPORT2 Virtual Port 2
0x001C VPORT3 Virtual Port 3
0x0030 CPU CPU
0x0040 CLK Clock Control
0x0048 SLEEP Sleep Controller
0x0050 OSC Oscillator Control
0x0060 DFLLRC32M DFLL for the 32 MHz Internal RC Oscillator
0x0068 DFLLRC2M DFLL for the 2 MHz RC Oscillator
0x0070 PR Power Reduction
0x0078 RST Reset Controller
0x0080 WDT Watch-Dog Timer
0x0090 MCU MCU Control
0x00A0 PMIC Programmable Multilevel Interrupt Controller
0x00B0 PORTCFG Port Configuration
0x00C0 AES AES Module
0x0100 DMA DMA Controller
0x0180 EVSYS Event System
0x01C0 NVM Non Volatile Memory (NVM) Controller
0x0200 ADCA Analog to Digital Converter on port A
0x0240 ADCB Analog to Digital Converter on port B
0x0300 DACA Digital to Analog Converter on port A
0x0320 DACB Digital to Analog Converter on port B
0x0380 ACA Analog Comparator pair on port A
0x0390 ACB Analog Comparator pair on port B
0x0400 RTC Real Time Counter
0x0440 EBI External Bus Interface
0x0480 TWIC Two Wire Interface on port C
0x0490 TWID Two Wire Interface on port D[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 63
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0x04A0 TWIE Two Wire Interface on port E
0x04B0 TWIF Two Wire Interface on port F
0x0600 PORTA Port A
0x0620 PORTB Port B
0x0640 PORTC Port C
0x0660 PORTD Port D
0x0680 PORTE Port E
0x06A0 PORTF Port F
0x06E0 PORTH Port H
0x0700 PORTJ Port J
0x0720 PORTK Port K
0x07C0 PORTQ Port Q
0x07E0 PORTR Port R
0x0800 TCC0 Timer/Counter 0 on port C
0x0840 TCC1 Timer/Counter 1 on port C
0x0880 AWEXC Advanced Waveform Extension on port C
0x0890 HIRESC High Resolution Extension on port C
0x08A0 USARTC0 USART 0 on port C
0x08B0 USARTC1 USART 1 on port C
0x08C0 SPIC Serial Peripheral Interface on port C
0x08F8 IRCOM Infrared Communication Module
0x0900 TCD0 Timer/Counter 0 on port D
0x0940 TCD1 Timer/Counter 1 on port D
0x0990 HIRESD High Resolution Extension on port D
0x09A0 USARTD0 USART 0 on port D
0x09B0 USARTD1 USART 1 on port D
0x09C0 SPID Serial Peripheral Interface on port D
0x0A00 TCE0 Timer/Counter 0 on port E
0x0A40 TCE1 Timer/Counter 1 on port E
0x0A80 AWEXE Advanced Waveform Extension on port E
0x0A90 HIRESE High Resolution Extension on port E
0x0AA0 USARTE0 USART 0 on port E
0x0AB0 USARTE1 USART 1 on port E
0x0AC0 SPIE Serial Peripheral Interface on port E
0x0B00 TCF0 Timer/Counter 0 on port F
Base Address Name Description[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 64
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0x0B40 TCF1 Timer/Counter 1 on port F
0x0B90 HIRESF High Resolution Extension on port F
0x0BA0 USARTF0 USART 0 on port F
0x0BB0 USARTF1 USART 1 on port F
0x0BC0 SPIF Serial Peripheral Interface on port F
Base Address Name Description[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 65
8067O–AVR–06/2013
32. Instruction Set Summary
Mnemonics Operands Description Operation Flags #Clocks
Arithmetic and Logic Instructions
ADD Rd, Rr Add without Carry Rd Rd + Rr Z,C,N,V,S,H 1
ADC Rd, Rr Add with Carry Rd Rd + Rr + C Z,C,N,V,S,H 1
ADIW Rd, K Add Immediate to Word Rd Rd + 1:Rd + K Z,C,N,V,S 2
SUB Rd, Rr Subtract without Carry Rd Rd - Rr Z,C,N,V,S,H 1
SUBI Rd, K Subtract Immediate Rd Rd - K Z,C,N,V,S,H 1
SBC Rd, Rr Subtract with Carry Rd Rd - Rr - C Z,C,N,V,S,H 1
SBCI Rd, K Subtract Immediate with Carry Rd Rd - K - C Z,C,N,V,S,H 1
SBIW Rd, K Subtract Immediate from Word Rd + 1:Rd Rd + 1:Rd - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Rd Rd Rr Z,N,V,S 1
ANDI Rd, K Logical AND with Immediate Rd Rd K Z,N,V,S 1
OR Rd, Rr Logical OR Rd Rd v Rr Z,N,V,S 1
ORI Rd, K Logical OR with Immediate Rd Rd v K Z,N,V,S 1
EOR Rd, Rr Exclusive OR Rd Rd Rr Z,N,V,S 1
COM Rd One’s Complement Rd $FF - Rd Z,C,N,V,S 1
NEG Rd Two’s Complement Rd $00 - Rd Z,C,N,V,S,H 1
SBR Rd,K Set Bit(s) in Register Rd Rd v K Z,N,V,S 1
CBR Rd,K Clear Bit(s) in Register Rd Rd ($FFh - K) Z,N,V,S 1
INC Rd Increment Rd Rd + 1 Z,N,V,S 1
DEC Rd Decrement Rd Rd - 1 Z,N,V,S 1
TST Rd Test for Zero or Minus Rd Rd Rd Z,N,V,S 1
CLR Rd Clear Register Rd Rd Rd Z,N,V,S 1
SER Rd Set Register Rd $FF None 1
MUL Rd,Rr Multiply Unsigned R1:R0 Rd x Rr (UU) Z,C 2
MULS Rd,Rr Multiply Signed R1:R0 Rd x Rr (SS) Z,C 2
MULSU Rd,Rr Multiply Signed with Unsigned R1:R0 Rd x Rr (SU) Z,C 2
FMUL Rd,Rr Fractional Multiply Unsigned R1:R0 Rd x Rr<<1 (UU) Z,C 2
FMULS Rd,Rr Fractional Multiply Signed R1:R0 Rd x Rr<<1 (SS) Z,C 2
FMULSU Rd,Rr Fractional Multiply Signed with Unsigned R1:R0 Rd x Rr<<1 (SU) Z,C 2
DES K Data Encryption if (H = 0) then R15:R0
else if (H = 1) then R15:R0
Encrypt(R15:R0, K)
Decrypt(R15:R0, K)
1/2
Branch Instructions
RJMP k Relative Jump PC PC + k + 1 None 2
IJMP Indirect Jump to (Z) PC(15:0)
PC(21:16)
Z,
0
None 2
EIJMP Extended Indirect Jump to (Z) PC(15:0)
PC(21:16)
Z,
EIND
None 2
JMP k Jump PC k None 3[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 66
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RCALL k Relative Call Subroutine PC PC + k + 1 None 2 / 3(1)
ICALL Indirect Call to (Z) PC(15:0)
PC(21:16)
Z,
0
None 2 / 3(1)
EICALL Extended Indirect Call to (Z) PC(15:0)
PC(21:16)
Z,
EIND
None 3(1)
CALL k call Subroutine PC k None 3 / 4(1)
RET Subroutine Return PC STACK None 4 / 5(1)
RETI Interrupt Return PC STACK I 4 / 5(1)
CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC PC + 2 or 3 None 1 / 2 / 3
CP Rd,Rr Compare Rd - Rr Z,C,N,V,S,H 1
CPC Rd,Rr Compare with Carry Rd - Rr - C Z,C,N,V,S,H 1
CPI Rd,K Compare with Immediate Rd - K Z,C,N,V,S,H 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC PC + 2 or 3 None 1 / 2 / 3
SBRS Rr, b Skip if Bit in Register Set if (Rr(b) = 1) PC PC + 2 or 3 None 1 / 2 / 3
SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b) = 0) PC PC + 2 or 3 None 2 / 3 / 4
SBIS A, b Skip if Bit in I/O Register Set If (I/O(A,b) =1) PC PC + 2 or 3 None 2 / 3 / 4
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC PC + k + 1 None 1 / 2
BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC PC + k + 1 None 1 / 2
BREQ k Branch if Equal if (Z = 1) then PC PC + k + 1 None 1 / 2
BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 None 1 / 2
BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1 None 1 / 2
BRCC k Branch if Carry Cleared if (C = 0) then PC PC + k + 1 None 1 / 2
BRSH k Branch if Same or Higher if (C = 0) then PC PC + k + 1 None 1 / 2
BRLO k Branch if Lower if (C = 1) then PC PC + k + 1 None 1 / 2
BRMI k Branch if Minus if (N = 1) then PC PC + k + 1 None 1 / 2
BRPL k Branch if Plus if (N = 0) then PC PC + k + 1 None 1 / 2
BRGE k Branch if Greater or Equal, Signed if (N V= 0) then PC PC + k + 1 None 1 / 2
BRLT k Branch if Less Than, Signed if (N V= 1) then PC PC + k + 1 None 1 / 2
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC PC + k + 1 None 1 / 2
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC PC + k + 1 None 1 / 2
BRTS k Branch if T Flag Set if (T = 1) then PC PC + k + 1 None 1 / 2
BRTC k Branch if T Flag Cleared if (T = 0) then PC PC + k + 1 None 1 / 2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1 None 1 / 2
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None 1 / 2
BRIE k Branch if Interrupt Enabled if (I = 1) then PC PC + k + 1 None 1 / 2
BRID k Branch if Interrupt Disabled if (I = 0) then PC PC + k + 1 None 1 / 2
Data Transfer Instructions
MOV Rd, Rr Copy Register Rd Rr None 1
MOVW Rd, Rr Copy Register Pair Rd+1:Rd Rr+1:Rr None 1
Mnemonics Operands Description Operation Flags #Clocks[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 67
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LDI Rd, K Load Immediate Rd K None 1
LDS Rd, k Load Direct from data space Rd (k) None 2(1)(2)
LD Rd, X Load Indirect Rd (X) None 1(1)(2)
LD Rd, X+ Load Indirect and Post-Increment Rd
X
(X)
X + 1
None 1(1)(2)
LD Rd, -X Load Indirect and Pre-Decrement X X - 1,
Rd (X)
X - 1
(X)
None 2(1)(2)
LD Rd, Y Load Indirect Rd (Y) (Y) None 1(1)(2)
LD Rd, Y+ Load Indirect and Post-Increment Rd
Y
(Y)
Y + 1
None 1(1)(2)
LD Rd, -Y Load Indirect and Pre-Decrement Y
Rd
Y - 1
(Y)
None 2(1)(2)
LDD Rd, Y+q Load Indirect with Displacement Rd (Y + q) None 2(1)(2)
LD Rd, Z Load Indirect Rd (Z) None 1(1)(2)
LD Rd, Z+ Load Indirect and Post-Increment Rd
Z
(Z),
Z+1
None 1(1)(2)
LD Rd, -Z Load Indirect and Pre-Decrement Z
Rd
Z - 1,
(Z)
None 2(1)(2)
LDD Rd, Z+q Load Indirect with Displacement Rd (Z + q) None 2(1)(2)
STS k, Rr Store Direct to Data Space (k) Rd None 2(1)
ST X, Rr Store Indirect (X) Rr None 1(1)
ST X+, Rr Store Indirect and Post-Increment (X)
X
Rr,
X + 1
None 1(1)
ST -X, Rr Store Indirect and Pre-Decrement X
(X)
X - 1,
Rr
None 2(1)
ST Y, Rr Store Indirect (Y) Rr None 1(1)
ST Y+, Rr Store Indirect and Post-Increment (Y)
Y
Rr,
Y + 1
None 1(1)
ST -Y, Rr Store Indirect and Pre-Decrement Y
(Y)
Y - 1,
Rr
None 2(1)
STD Y+q, Rr Store Indirect with Displacement (Y + q) Rr None 2(1)
ST Z, Rr Store Indirect (Z) Rr None 1(1)
ST Z+, Rr Store Indirect and Post-Increment (Z)
Z
Rr
Z + 1
None 1(1)
ST -Z, Rr Store Indirect and Pre-Decrement Z Z - 1 None 2(1)
STD Z+q,Rr Store Indirect with Displacement (Z + q) Rr None 2(1)
LPM Load Program Memory R0 (Z) None 3
LPM Rd, Z Load Program Memory Rd (Z) None 3
LPM Rd, Z+ Load Program Memory and Post-Increment Rd
Z
(Z),
Z + 1
None 3
ELPM Extended Load Program Memory R0 (RAMPZ:Z) None 3
ELPM Rd, Z Extended Load Program Memory Rd (RAMPZ:Z) None 3
ELPM Rd, Z+ Extended Load Program Memory and PostIncrement
Rd
Z
(RAMPZ:Z),
Z + 1
None 3
SPM Store Program Memory (RAMPZ:Z) R1:R0 None -
Mnemonics Operands Description Operation Flags #Clocks[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 68
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SPM Z+ Store Program Memory and Post-Increment
by 2
(RAMPZ:Z)
Z
R1:R0,
Z + 2
None -
IN Rd, A In From I/O Location Rd I/O(A) None 1
OUT A, Rr Out To I/O Location I/O(A) Rr None 1
PUSH Rr Push Register on Stack STACK Rr None 1(1)
POP Rd Pop Register from Stack Rd STACK None 2(1)
Bit and Bit-test Instructions
LSL Rd Logical Shift Left Rd(n+1)
Rd(0)
C
Rd(n),
0,
Rd(7)
Z,C,N,V,H 1
LSR Rd Logical Shift Right Rd(n)
Rd(7)
C
Rd(n+1),
0,
Rd(0)
Z,C,N,V 1
ROL Rd Rotate Left Through Carry Rd(0)
Rd(n+1)
C
C,
Rd(n),
Rd(7)
Z,C,N,V,H 1
ROR Rd Rotate Right Through Carry Rd(7)
Rd(n)
C
C,
Rd(n+1),
Rd(0)
Z,C,N,V 1
ASR Rd Arithmetic Shift Right Rd(n) Rd(n+1), n=0..6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3..0) Rd(7..4) None 1
BSET s Flag Set SREG(s) 1 SREG(s) 1
BCLR s Flag Clear SREG(s) 0 SREG(s) 1
SBI A, b Set Bit in I/O Register I/O(A, b) 1 None 1
CBI A, b Clear Bit in I/O Register I/O(A, b) 0 None 1
BST Rr, b Bit Store from Register to T T Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) T None 1
SEC Set Carry C 1 C 1
CLC Clear Carry C 0 C 1
SEN Set Negative Flag N 1 N 1
CLN Clear Negative Flag N 0 N 1
SEZ Set Zero Flag Z 1 Z 1
CLZ Clear Zero Flag Z 0 Z 1
SEI Global Interrupt Enable I 1 I 1
CLI Global Interrupt Disable I 0 I 1
SES Set Signed Test Flag S 1 S 1
CLS Clear Signed Test Flag S 0 S 1
SEV Set Two’s Complement Overflow V 1 V 1
CLV Clear Two’s Complement Overflow V 0 V 1
SET Set T in SREG T 1 T 1
CLT Clear T in SREG T 0 T 1
SEH Set Half Carry Flag in SREG H 1 H 1
CLH Clear Half Carry Flag in SREG H 0 H 1
Mnemonics Operands Description Operation Flags #Clocks[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 69
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Notes: 1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface.
2. One extra cycle must be added when accessing Internal SRAM.
MCU Control Instructions
BREAK Break (See specific descr. for BREAK) None 1
NOP No Operation None 1
SLEEP Sleep (see specific descr. for Sleep) None 1
WDR Watchdog Reset (see specific descr. for WDR) None 1
Mnemonics Operands Description Operation Flags #Clocks[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 70
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33. Packaging information
33.1 100A
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 100A D
2010-10-20
PIN 1 IDENTIFIER
0°~7°
PIN 1
L
C
A1 A2 A
D1
D
e E1 E
B
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 15.75 16.00 16.25
D1 13.90 14.00 14.10 Note 2
E 15.75 16.00 16.25
E1 13.90 14.00 14.10 Note 2
B 0.17 – 0.27
C 0.09 – 0.20
L 0.45 – 0.75
e 0.50 TYP
Notes:
1. This package conforms to JEDEC reference MS-026, Variation AED.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.08 mm maximum.
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 71
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33.2 100C1
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
100C1, 100-ball, 9 x 9 x 1.2 mm Body, Ball Pitch 0.80 mm
Chip Array BGA Package (CBGA) 100C1 A
5/25/06
TOP VIEW
SIDE VIEW
BOTTOM VIEW
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 1.10 – 1.20
A1 0.30 0.35 0.40
D 8.90 9.00 9.10
E 8.90 9.00 9.10
D1 7.10 7.20 7.30
E1 7.10 7.20 7.30
Øb 0.35 0.40 0.45
e 0.80 TYP
Marked A1 Identifier
8 7 6 5 4 3 2 1
A
B
C
D
E
9
F
G
H
I
J
10
0.90 TYP
0.90 TYP
A1 Corner
0.12 Z
E
D
e
e
Øb
A
A1
E1
D1[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 72
8067O–AVR–06/2013
33.3 100C2
TITLE GPC DRAWING NO. REV.
Package Drawing Contact:
packagedrawings@atmel.com CIF A 100C2
100C2, 100-ball (10 x 10 Array), 0.65 mm Pitch,
7.0 x 7.0 x 1.0 mm, Very Thin, Fine-Pitch
Ball Grid Array Package (VFBGA)
12/23/08
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A – – 1.00
A1 0.20 – –
A2 0.65 – –
D 6.90 7.00 7.10
D1 5.85 BSC
E 6.90 7.00 7.10
E1 5.85 BSC
b 0.30 0.35 0.40
e 0.65 BSC
TOP VIEW
SIDE VIEW
A1 BALL ID
J
I
H
G
F
E
D
C
B
A
12 3 4 5 6 7 8 9 10
A
A1
A2
D
E
0.10
E1
D1
100 - Ø0.35 ± 0.05
e
A1 BALL CORNER
BOTTOM VIEW
b e[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 73
8067O–AVR–06/2013
34. Electrical Characteristics
34.1 Absolute Maximum Ratings*
34.2 DC Characteristics
Table 34-1. Current consumption.
Operating Temperature . . . . . . . . . . . -55C to +125C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only
and functional operation of the device at these
or other conditions beyond those indicated in
the operational sections of this specification is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature . . . . . . . . . . . . . -65C to +150°C
Voltage on any Pin with respect to Ground-0.5V to VCC+0.5V
Maximum Operating Voltage . . . . . . . . . . . . . . . . 3.6V
DC Current per I/O Pin. . . . . . . . . . . . . . . . . . 20.0 mA
DC Current VCC and GND Pins . . . . . . . . . . 200.0 mA
Symbol Parameter Condition Min Typ Max Units
ICC
Active mode(1)
1 MHz, Ext. Clk
VCC = 1.8V 365
µA
VCC = 3.0V 790
2 MHz, Ext. Clk
VCC = 1.8V 690 800
VCC = 3.0V 1400 1600
32 MHz, Ext. Clk VCC = 3.0V 18.35 20 mA
Idle mode(1)
1 MHz, Ext. Clk
VCC = 1.8V 135
µA
VCC = 3.0V 255
2 MHz, Ext. Clk
VCC = 1.8V 270 380
VCC = 3.0V 510 650
32 MHz, Ext. Clk VCC = 3.0V 8.15 9.2 mA
Power-down mode
All Functions Disabled VCC = 3.0V 0.1
µA
All Functions Disabled, T = 85°C VCC = 3.0V 2 5
ULP, WDT, Sampled BOD
VCC = 1.8V 0.5
VCC = 3.0V 0.6
ULP, WDT, Sampled BOD, T=85°C VCC = 3.0V 3 10
Power-save mode
RTC 1 kHz from Low Power 32 kHz
VCC = 1.8V 0.52
VCC = 3.0V 0.55 µA
RTC from Low Power 32 kHz VCC = 3.0V 1.16[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 74
8067O–AVR–06/2013
Note: 1. All Power Reduction Registers set. Typical numbers measured at T = 25°C if nothing else is specified.
2. with no prescaling
Module current consumption(2)
ICC
RC32M 395
µA
RC32M w/DFLL Internal 32.768 kHz oscillator as DFLL source TBD
RC2M 120
RC2M w/DFLL Internal 32.768 kHz oscillator as DFLL source 155
RC32K 30
PLL Multiplication factor = 10x 195
Watchdog normal mode TBD
BOD Continuous mode 120
BOD Sampled mode 1
Internal 1.00 V ref 85
Temperature reference 80
RTC with int. 32 kHz RC as
source No prescaling 30
RTC with ULP as source No prescaling 1
ADC 250 kS/s - Int. 1V Ref 3.6
DAC Normal Mode 1000 kS/s, Single channel, Int. 1V Ref 1.8 mA
DAC Low-Power Mode 1000 KS/s, Single channel, Int. 1V Ref 1
AC High-speed 220
µA
AC Low-power 110
USART Rx and Tx enabled, 9600 BAUD 7.5
DMA 180
Timer/Counter Prescaler DIV1 18
AES 195
Flash/EEPROM
Programming
Vcc = 2V 20
mA
Vcc = 3V 30
Symbol Parameter Condition Min Typ Max Units[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 75
8067O–AVR–06/2013
34.3 Speed
Table 34-2. Operating voltage and frequency.
The maximum CPU clock frequency of the XMEGA A1 devices is depending on VCC. As shown in Figure 34-1 on page
75 the Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V.
Figure 34-1. Maximum Frequency vs. Vcc
Symbol Parameter Condition Min Typ Max Units
ClkCPU CPU clock frequency
VCC = 1.6V 0 12
MHz
VCC = 1.8V 0 12
VCC = 2.7V 0 32
VCC = 3.6V 0 32
1.8
12
32
MHz
1.6 2.7 3.6 V
Safe Operating Area[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 76
8067O–AVR–06/2013
34.4 Flash and EEPROM Memory Characteristics
Table 34-3. Endurance and data retention.
Table 34-4. Programming time.
Notes: 1. Programming is timed from the internal 2 MHz oscillator.
2. EEPROM is not erased if the EESAVE fuse is programmed.
34.5 ADC Characteristics
Table 34-5. ADC characteristics
Symbol Parameter Condition Min Typ Max Units
Flash
Write/Erase cycles
25°C 10K
Cycle
85°C 10K
Data retention
25°C 100
Year
55°C 25
EEPROM
Write/Erase cycles
25°C 80K
Cycle
85°C 30K
Data retention
25°C 100
Year
55°C 25
Symbol Parameter Condition Min Typ(1) Max Units
Chip Erase Flash, EEPROM(2) and SRAM Erase 40
ms
Flash
Page Erase 4
Page Write 6
Page WriteAutomatic Page Erase and Write 12
EEPROM
Page Erase 4
Page Write 6
Page Write Automatic Page Erase and Write 12
Symbol Parameter Condition Min Typ Max Units
RES Resolution Programmable: 8/12 8 12 12 Bits
INL Integral Non-Linearity 500 kS/s -5 <±1 5 LSB
DNL Differential Non-Linearity 500 kS/s < ±0.75 LSB
Gain Error ±10 mV
Offset Error ±2 mV
ADCclk ADC Clock frequency Max is 1/4 of
Peripheral Clock
VCC2.0V 2000
kHz
VCC<2.0V 500[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 77
8067O–AVR–06/2013
Table 34-6. ADC gain stage characteristics.
Conversion rate
VCC2.0V 2000
ksps
VCC<2.0V 500
Conversion time
(propagation delay)
(RES+2)/2+GAIN
RES = 8 or 12, GAIN = 0 or 1
5 7 8
ADCclk
cycles
Sampling Time 1/2 ADCclk cycle 0.25 µS
Conversion range 0 VREF V
AVCC Analog Supply Voltage Vcc-0.3 Vcc+0.3 V
VREF Reference voltage 1.0 Vcc-0.6 V
Input bandwidth
VCC2.0V 2000
kHz
VCC<2.0V 500
INT1V Internal 1.00V reference 1.00 V
INTVCC Internal VCC/1.6 VCC/1.6 V
SCALEDVCC Scaled internal VCC/10 input VCC/10 V
RAREF Reference input resistance >10 M
Start-up time 12 24
ADCclk
cycles
Internal input sampling speed Temp. sensor, VCC/10, Bandgap 100 ksps
Symbol Parameter Condition Min Typ Max Units
Gain error 1 to 64 gain < ±1 %
Offset error < ±1 mV
Vrms Noise level at input 64x gain
VREF = Int. 1V 0.12
mV
VREF = Ext. 2V 0.06
Clock rate Same as ADC 1000 kHz
Symbol Parameter Condition Min Typ Max Units[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 78
8067O–AVR–06/2013
34.6 DAC Characteristics
Table 34-7. DAC characteristics.
34.7 Analog Comparator Characteristics
Table 34-8. Analog Comparator characteristics.
34.8 Bandgap Characteristics
Table 34-9. Bandgap voltage characteristics.
Symbol Parameter Condition Min Typ Max Units
INL Integral Non-Linearity VCC = 1.6-3.6V VREF = Ext. ref 5 LSB
DNL Differential Non-Linearity VCC = 1.6-3.6V
VREF = Ext. ref 0.6 <±1
LSB
VREF= AVCC 0.6
Fclk Conversion rate 1000 ksps
AREF External reference voltage 1.1 AVCC-0.6 V
Reference input impedance >10 M
Max output voltage Rload=100k AVCC*0.98 V
Min output voltage Rload=100k 0.01 V
Symbol Parameter Condition Min Typ Max Units
Voff Input Offset Voltage VCC = 1.6 - 3.6V <±5 mV
Ilk Input Leakage Current VCC = 1.6 - 3.6V < 1000 pA
Vhys1 Hysteresis, No VCC = 1.6 - 3.6V 0 mV
Vhys2 Hysteresis, Small VCC = 1.6 - 3.6V mode = HS 25 mV
Vhys3 Hysteresis, Large VCC = 1.6 - 3.6V mode = HS 50 mV
tdelay Propagation delay
VCC = 3.0V, T= 85°C mode = HS 100
V ns CC = 1.6 - 3.6V mode = HS 70
VCC = 1.6 - 3.6V mode = LP 140
Symbol Parameter Condition Min Typ Max Units
Bandgap startup time As reference for ADC or DAC 1 Clk_PER + 2.5µs µs
Bandgap voltage 1.1 V[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 79
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34.9 Brownout Detection Characteristics
Table 34-10. Brownout Detection characteristics.
Note: 1. BOD is calibrated to BOD level 0 at 85°C, and BOD level 0 is the default level.
34.10 PAD Characteristics
Table 34-11. PAD characteristics.
ADC/DAC ref
T= 85°C, After calibration 0.99 1.01
V
1
Variation over voltage and temperature VCC = 1.6 - 3.6V, T = -40C to 85C ±5 %
Symbol Parameter Condition Min Typ Max Units
Symbol Parameter Condition Min Typ Max Units
BOD level 0 falling Vcc 1.6
V
BOD level 1 falling Vcc 1.9
BOD level 2 falling Vcc 2.1
BOD level 3 falling Vcc 2.4
BOD level 4 falling Vcc 2.6
BOD level 5 falling Vcc 2.9
BOD level 6 falling Vcc 3.2
BOD level 7 falling Vcc 3.4
Hysteresis BOD level 0-5 2 %
Symbol Parameter Condition Min Typ Max Units
VIH Input High Voltage
VCC = 2.4 - 3.6V 0.7*VCC VCC+0.5
V
VCC = 1.6 - 2.4V 0.8*VCC VCC+0.5
VIL Input Low Voltage
VCC = 2.4 - 3.6V -0.5 0.3*VCC
V
VCC = 1.6 - 2.4V -0.5 0.2*VCC
VOL Output Low Voltage GPIO
IOL = 15 mA, VCC = 3.3V 0.45 0.76
IOL = 10 mA, VCC = 3.0V 0.3 0.64 V
IOL= 5 mA, VCC = 1.8V 0.2 0.46[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 80
8067O–AVR–06/2013
34.11 POR Characteristics
Table 34-12. Power-on Reset characteristics.
34.12 Reset Characteristics
Table 34-13. Reset characteristics.
34.13 Oscillator Characteristics
Table 34-14. Internal 32.768kHz oscillator characteristics.
VOH Output High Voltage GPIO
IOH = -8 mA, VCC = 3.3V 2.6 3
IOH = -6 mA, VCC = 3.0V 2.1 2.2 V
IOH = -2 mA, VCC = 1.8V 1.4 1.6
IIL Input Leakage Current I/O pin <0.001 1 µA
IIH Input Leakage Current I/O pin <0.001 1 µA
RP I/O pin Pull/Buss keeper Resistor 20 k
RRST Reset pin Pull-up Resistor 20 k
Input hysteresis 0.5 V
Symbol Parameter Condition Min Typ Max Units
Symbol Parameter Condition Min Typ Max Units
VPOT- POR threshold voltage falling Vcc 1 V
VPOT+ POR threshold voltage rising Vcc 1.4 V
Symbol Parameter Condition Min Typ Max Units
Minimum reset pulse width 90 ns
Reset threshold voltage
VCC = 2.7 - 3.6V 0.45*VCC
V
VCC = 1.6 - 2.7V 0.42*VCC
Symbol Parameter Condition Min Typ Max Units
Accuracy T = 85C, VCC = 3V,
After production calibration -0.5 0.5 %[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 81
8067O–AVR–06/2013
Table 34-15. Internal 2MHz oscillator characteristics.
Table 34-16. Internal 32MHz oscillator characteristics.
Table 34-17. Internal 32kHz, ULP oscillator characteristics.
Table 34-18. Maximum load capacitance (CL) and ESR recommendation for 32.768kHz crystal.
Table 34-19. Device wake-up time from sleep.
Notes: 1. Non-prescaled System Clock source.
2. Time from pin change on external interrupt pin to first available clock cycle. Additional interrupt response time is minimum 5 system clock source cycles.
Symbol Parameter Condition Min Typ Max Units
Accuracy T = 85C, VCC = 3V,
After production calibration -1.5 1.5 %
DFLL Calibration step size T = 25C, VCC = 3V 0.175 %
Symbol Parameter Condition Min Typ Max Units
Accuracy T = 85C, VCC = 3V,
After production calibration -1.5 1.5 %
DFLL Calibration stepsize T = 25C, VCC = 3V 0.2 %
Symbol Parameter Condition Min Typ Max Units
Output frequency 32 kHz ULP OSC T = 85C, VCC = 3.0V 26 kHz
Crystal CL [pF] Max ESR [k]
6.5 60
9 35
Symbol Parameter Condition(1) Min Typ(2) Max Units
Idle Sleep, Standby and Extended
Standby sleep mode
Int. 32.768 kHz RC 130
µS
Int. 2 MHz RC 2
Ext. 2 MHz Clock 2
Int. 32 MHz RC 0.17
Power-save and Power-down
Sleep mode
Int. 32.768 kHz RC 320
Int. 2 MHz RC 10.3
Ext. 2 MHz Clock 4.5
Int. 32 MHz RC 5.8[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 82
8067O–AVR–06/2013
35. Typical Characteristics
35.1 Active Supply Current
Figure 35-1. Active Supply Current vs. Frequency
fSYS = 1 - 32 MHz, T = 25°C
Figure 35-2. Active Supply Current vs. VCC
fSYS = 1.0 MHz
3.3V
3.0V
2.7V
0
5
10
15
20
25
0 4 8 12 16 20 24 28 32
Frequency [MHz]
Icc [mA]
1.8V
2.2V
85°C
25°C
-40°C
0
200
400
600
800
1000
1200
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Vcc [V]
Icc [uA][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 83
8067O–AVR–06/2013
35.2 Idle Supply Current
Figure 35-3. Idle Supply Current vs. Frequency
fSYS = 1 - 32 MHz, T = 25°C
Figure 35-4. Active Supply Current vs. VCC
fSYS = 1.0 MHz
,
3.3V
3.0V
2.7V
0
1
2
3
4
5
6
7
8
9
10
0 4 8 12 16 20 24 28 32
Frequency [MHz]
Icc [mA]
1.8V
2.2V
85°C
25°C
-40°C
0
50
100
150
200
250
300
350
400
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Vcc [V]
Icc [uA][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 84
8067O–AVR–06/2013
35.3 Power-down Supply Current
Figure 35-5. Power-down Supply Current vs. Temperature
35.4 Power-save Supply Current
Figure 35-6. Power-save Supply Current vs. Temperature
Sampled BOD, WDT, RTC from ULP enabled
3.3V
3.0V
2.7V
2.2V
1.8V
0
0.5
1
1.5
2
2.5
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature [°C]
Icc [uA]
3.3V
2.7V
2.2V
1.8V
0
0.5
1
1.5
2
2.5
3
3.5
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature [°C]
Icc [uA][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 85
8067O–AVR–06/2013
35.5 Pin Pull-up
Figure 35-7. I/O Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 1.8V
Figure 35-8. I/O Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.0V
85 °C 25 °C
-40 °C
0
20
40
60
80
100
0 0.2 0.4 0.6 0.8 1 1.2 1.4
vreset [V]
Ireset [uA]
85 °C
25 °C
-40 °C
0
20
40
60
80
100
120
140
160
180
0 0.5 1 1.5 2 2.5
vreset [V]
Ireset [uA][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 86
8067O–AVR–06/2013
Figure 35-9. I/O Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.3V
35.6 Pin Thresholds and Hysteresis
Figure 35-10.I/O Pin Input Threshold Voltage vs. VCC
VIH - I/O Pin Read as “1”
85 °C
25 °C
-40 °C
0
20
40
60
80
100
120
140
160
180
0 0.5 1 1.5 2 2.5 3
vreset [V]
Ireset [uA]
85 °C
25 °C
-40 °C
0
0.5
1
1.5
2
2.5
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Vcc [V]
Vthreshold [V][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 87
8067O–AVR–06/2013
Figure 35-11.I/O Pin Input Threshold Voltage vs. VCC
VIL - I/O Pin Read as “0”
Figure 35-12.I/O Pin Input Hysteresis vs. VCC.
85 °C
25 °C
-40 °C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Vcc [V]
Vthreshold [V]
85 °C
25 °C
-40 °C
0
0.2
0.4
0.6
0.8
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Vcc [V]
Vthreshold [V][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 88
8067O–AVR–06/2013
Figure 35-13.Reset Input Threshold Voltage vs. VCC
VIH - I/O Pin Read as “1”
Figure 35-14.Reset Input Threshold Voltage vs. VCC
VIL - I/O Pin Read as “0”
85 °C
25 °C
-40 °C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Vcc [V]
Vthreshold [V]
85 °C
25 °C
-40 °C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Vcc [V]
Vthreshold [V][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 89
8067O–AVR–06/2013
35.7 Bod Thresholds
Figure 35-15.BOD Thresholds vs. Temperature
BOD Level = 1.6V
Figure 35-16.BOD Thresholds vs. Temperature
BOD Level = 2.9V
Rising Vcc
Falling Vcc
1.602
1.608
1.614
1.62
1.626
1.632
1.638
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature [°C]
VBOT [V]
Rising Vcc
Falling Vcc
2.905
2.92
2.935
2.95
2.965
2.98
2.995
3.01
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature [°C]
VBOT [V][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 90
8067O–AVR–06/2013
35.8 Bandgap
Figure 35-17.Internal 1.00V Reference vs. Temperature.
35.9 Analog Comparator
Figure 35-18.Analog Comparator Hysteresis vs. VCC
High-speed, Small hysteresis
3.0V
1.8V
0.999
0.9995
1
1.0005
1.001
1.0015
1.002
1.0025
1.003
1.0035
1.004
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature [°C]
VREF [V]
25°C
0
5
10
15
20
25
30
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Vcc [V]
Hysteresis [mV][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 91
8067O–AVR–06/2013
Figure 35-19.Analog Comparator Hysteresis vs. VCC, High-speed
Large hysteresis
Figure 35-20.Analog Comparator Propagation Delay vs. VCC
High-speed
25°C
0
10
20
30
40
50
60
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Vcc [V]
Hysteresis [mV]
25°C
0
20
40
60
80
100
120
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
Vcc [V]
Propagation Delay [ns][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 92
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35.10 Oscillators and Wake-up Time
Figure 35-21.Internal 32.768 kHz Oscillator Frequency vs. Temperature
1.024 kHz output
Figure 35-22.Ultra Low-Power (ULP) Oscillator Frequency vs. Temperature
1 kHz output
p
3.0 V
1.8 V
0.99
0.995
1
1.005
1.01
1.015
1.02
1.025
1.03
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
T [°C]
f [kHz]
p
3.0 V
1.8 V
0.87
0.88
0.89
0.9
0.91
0.92
0.93
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
T [°C]
f1kHz output [kHz][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 93
8067O–AVR–06/2013
Figure 35-23.Internal 2 MHz Oscillator CalA Calibration Step Size
T = -40 to 85C, VCC = 3V
Figure 35-24.Internal 2 MHz Oscillator CalB Calibration Step Size
T = -40 to 85C, VCC = 3V
0
0.001
0.002
0.003
0.004
0.005
0.006
0 20 40 60 80 100 120 140
CALA [LSB]
Step size: f [MHz]
0
0.005
0.01
0.015
0.02
0.025
0.03
0.035
0.04
0 10 20 30 40 50 60 70
CALB [LSB]
Step size: f [MHz][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 94
8067O–AVR–06/2013
Figure 35-25.Internal 32 MHz Oscillator CalA Calibration Step Size
T = -40 to 85C, VCC = 3V
Figure 35-26.Internal 32 MHz Oscillator CalB Calibration Step Size
T = -40 to 85C, VCC = 3V
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0 20 40 60 80 100 120 140
CALA
Step size: f [MHz]
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0 10 20 30 40 50 60 70
CALB
Step size: f [MHz][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 95
8067O–AVR–06/2013
35.11 PDI Speed
Figure 35-27.PDI Speed vs. VCC
25 °C
0
5
10
15
20
25
30
35
1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
VCC [V]
fMAX [MHz][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 96
8067O–AVR–06/2013
36. Errata
36.1 ATxmega64A1and ATxmega128A1 rev. H
Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously
VCC voltage scaler for AC is non-linear
The ADC has up to ±2 LSB inaccuracy
ADC gain stage output range is limited to 2.4 V
Sampling speed limited to 500 ksps for supply voltage below 2.0V
ADC Event on compare match non-functional
Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
Accuracy lost on first three samples after switching input to ADC gain stage
The input difference between two succeeding ADC samples is limited by VREF
Increased noise when using internal 1.0V reference at low temperature
Configuration of PGM and CWCM not as described in XMEGA A Manual
PWM is not restarted properly after a fault in cycle-by-cycle mode
BOD will be enabled at any reset
BODACT fuse location is not correct
Sampled BOD in Active mode will cause noise when bandgap is used as reference
DAC has up to ±10 LSB noise in Sampled Mode
DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V
DAC refresh may be blocked in S/H mode
Conversion lost on DAC channel B in event triggered mode
Both DFLLs and both oscillators have to be enabled for one to work
Access error when multiple bus masters are accessing SDRAM
EEPROM page buffer always written when NVM DATA0 is written
Pending full asynchronous pin change interrupts will not wake the device
Pin configuration does not affect Analog Comparator Output
Low level interrupt triggered when pin input is disabled
JTAG enable does not override Analog Comparator B output
NMI Flag for Crystal Oscillator Failure automatically cleared
Flash Power Reduction Mode can not be enabled when entering sleep
Some NVM Commands are non-functional
Crystal start-up time required after power-save even if crystal is source for RTC
Setting PRHIRES bit makes PWM output unavailable
Accessing EBI address space with PREBI set will lock Bus Master
RTC Counter value not correctly read after sleep
Pending asynchronous RTC-interrupts will not wake up device
TWI, the minimum I2C SCL low time could be violated in Master Read mode
TWI address-mask feature is non-functional
TWI, a general address call will match independent of the R/W-bit value
TWI Transmit collision flag not cleared on repeated start
Clearing TWI Stop Interrupt Flag may lock the bus[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 97
8067O–AVR–06/2013
TWI START condition at bus timeout will cause transaction to be dropped
TWI Data Interrupt Flag erroneously read as set
WDR instruction inside closed window will not issue reset
1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously
If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as input
for another AC, the first comparator will be affected for up to 1 µs and could potentially give a wrong comparison
result.
Problem fix/Workaround
If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before enabling
any of them.
2. VCC voltage scaler for AC is non-linear
The 6-bit VCC voltage scaler in the Analog Comparators is non-linear.
Figure 36-1. Analog Comparator Voltage Scaler vs. Scalefac
T = 25°C
Problem fix/Workaround
Use external voltage input for the analog comparator if accurate voltage levels are needed
3. The ADC has up to ±2 LSB inaccuracy
The ADC will have up to ±2 LSB inaccuracy, visible as a saw-tooth pattern on the input voltage/ output value transfer
function of the ADC. The inaccuracy increases with increasing voltage reference reaching ±2 LSB with 3V
reference.
3.3 V
2.7 V
1.8 V
0
0.5
1
1.5
2
2.5
3
3.5
0 5 10 15 20 25 30 35 40 45 50 55 60 65
SCALEFAC
VSCALE [V][Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 98
8067O–AVR–06/2013
Problem fix/Workaround
None, the actual ADC resolution will be reduced with up to ±2 LSB.
4. ADC gain stage output range is limited to 2.4 V
The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential input will only give correct
output when below 2.4 V/gain. For the available gain settings, this gives a differential input range of:
Problem fix/Workaround
Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a correct result, or keep
ADC voltage reference below 2.4 V.
5. Sampling speed limited to 500 ksps for supply voltage below 2.0V
The sampling frequency is limited to 500 ksps for supply voltage below 2.0V. At higher sampling rate the INL error
will be several hundred LSB.
Problem fix/Workaround
None.
6. ADC Event on compare match non-functional
ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to
BELOW or ABOVE.
Problem fix/Workaround
Enable and use interrupt on compare match when using the compare function.
7. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
The ADC can not be used to do bandgap measurements when VCC is below 2.7V.
Problem fix/Workaround
– 1x gain: 2.4 V
– 2x gain: 1.2 V
– 4x gain: 0.6 V
– 8x gain: 300 mV
– 16x gain: 150 mV
– 32x gain: 75 mV
– 64x gain: 38 mV[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 99
8067O–AVR–06/2013
None.
8. Accuracy lost on first three samples after switching input to ADC gain stage
Due to memory effect in the ADC gain stage, the first three samples after changing input channel must be disregarded
to achieve 12-bit accuracy.
Problem fix/Workaround
Run three ADC conversions and discard these results after changing input channels to ADC gain stage.
9. The input difference between two succeeding ADC samples is limited by VREF
If the difference in input between two samples changes more than the size of the reference, the ADC will not be
able to convert the data correctly. Two conversions will be required before the conversion is correct.
Problem fix/Workaround
Discard the first conversion if input is changed more than VREF, or ensure that the input never changes more then
VREF.
10. Increased noise when using internal 1.0V reference at low temperature
When operating at below 0C and using internal 1.0V reference the RMS noise will be up 4 LSB, Peak-to-peak
noise up to 25 LSB.
Problem fix/Workaround
Use averaging to remove noise.
11. Configuration of PGM and CWCM not as described in XMEGA A Manual
Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM), but not Common Waveform
Channel Mode.
Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode (CWCM) will enable both
Pattern Generation Mode and Common Waveform Channel Mode.
Problem fix/Workaround
12 PWM is not restarted properly after a fault in cycle-by-cycle mode
When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal operation
at first update after fault condition is no longer present.
PGM CWCM Description
0 0 PGM and CWCM disabled
0 1 PGM enabled
1 0 PGM and CWCM enabled
1 1 PGM enabled[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 100
8067O–AVR–06/2013
Problem fix/Workaround
Do a write to any AWeX I/O register to re-enable the output.
13. BOD will be enabled after any reset
If any reset source goes active, the BOD will be enabled and keep the device in reset if the VCC voltage is below
the programmed BOD level. During Power-On Reset, reset will not be released until VCC is above the programmed
BOD level even if the BOD is disabled.
Problem fix/Workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
14. BODACT fuse location is not correct
The fuses for enabling BOD in active mode (BODACT) are located at FUSEBYTE2, bit 2 and 3 and not in FUSEBYTE
5 as described in the XMEGA A Manual.
Problem fix/Workaround
Access the fuses in FUSEBYTE2.
15. Sampled BOD in Active mode will cause noise when bandgap is used as reference
Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap
reference for ADC, DAC and Analog Comparator.
Problem fix/Workaround
If the bandgap is used as reference for either the ADC, DAC or Analog Comparator, the BOD must not be set in
sampled mode.
16. DAC has up to ±10 LSB noise in Sampled Mode
The DAC has noise of up to ±10 LSB in Sampled Mode for entire operation range.
Problem fix/Workaround
Use the DAC in continuous mode.
17. DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V
Using the DAC with a reference voltage above 2.4V or VCC - 0.6V will give inaccurate output when converting
codes that give below 0.75V output:
±10 LSB for continuous mode
±200 LSB for Sample and Hold mode
Problem fix/Workaround
None.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 101
8067O–AVR–06/2013
18. DAC has up to ±10 LSB noise in Sampled Mode
If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is done at maximum rate
(i.e. the DAC is always busy doing conversion for this channel), this will block refresh signals to the second channel.
Problem fix/Workaround
When using the DAC in S/H mode, ensure that none of the channels is running at maximum conversion rate, or
ensure that the conversion rate of both channels is high enough to not require refresh.
19. Conversion lost on DAC channel B in event triggered mode
If during dual channel operation channel 1 is set in auto trigged conversion mode, channel 1 conversions are occasionally
lost. This means that not all data-values written to the Channel 1 data register are converted.
Problem fix/Workaround
Keep the DAC conversion interval in the range 000-001 (1 and 3 CLK), and limit the Peripheral clock frequency so
the conversion internal never is shorter than 1.5 µs.
20. Both DFLLs and both oscillators have to be enabled for one to work
In order to use the automatic runtime calibration for the 2 MHz or the 32 MHz internal oscillators, the DFLL for both
oscillators and both oscillators have to be enabled for one to work.
Problem fix/Workaround
Enable both DFLLs and both oscillators when using automatic runtime calibration for either of the internal
oscillators.
21. Access error when multiple bus masters are accessing SDRAM
If one bus master (CPU and DMA channels) is using the EBI to access an SDRAM in burst mode and another bus
master is accessing the same row number in a different BANK of the SDRAM in the cycle directly after the burst
access is complete, the access for the second bus master will fail.
Problem fix/Workaround
Do not put stack pointer in SDRAM and use DMA Controller in 1 byte burst mode if CPU and DMA Controller are
required to access SDRAM at the same time.
22. EEPROM page buffer always written when NVM DATA0 is written
If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM page buffer.
Problem fix/Workaround
Before writing to NVM DATA0, for example when doing software CRC or flash page buffer write, check if EEPROM
page buffer active loading flag (EELOAD) is set. Do not write NVM DATA0 when EELOAD is set.
23. Pending full asynchronous pin change interrupts will not wake the device[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 102
8067O–AVR–06/2013
Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction is
executed, will be ignored until the device is woken from another source or the source triggers again. This applies
when entering all sleep modes where the System Clock is stopped.
Problem fix/Workaround
None.
24. Pin configuration does not affect Analog Comparator Output
The Output/Pull and inverted pin configuration does not affect the Analog Comparator output function.
Problem fix/Workaround
None for Output/Pull configuration.
For inverted I/O, configure the Analog Comparator to give an inverted result (i.e. connect positive input to the negative
AC input and vice versa), or use and external inverter to change polarity of Analog Comparator output.
25. Low level interrupt triggered when pin input is disabled
If a pin input is disabled, but pin is configured to trigger on low level, interrupt request will be sent.
Problem fix/Workaround
Ensure that Interrupt mask for the disabled pin is cleared.
26. JTAG enable does not override Analog Comparator B output
When JTAG is enabled this will not override the Analog Comparator B (ACB) output, AC0OUT on pin 7 if this is
enabled.
Problem fix/Workaround
Use Analog Comparator output for ACA when JTAG is used, or use the PDI as debug interface.
27. NMI Flag for Crystal Oscillator Failure automatically cleared
NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI interrupt
handler.
Problem fix/Workaround
This device revision has only one NMI interrupt source, so checking the interrupt source in software is not
required.
28. Flash Power Reduction Mode can not be enabled when entering sleep
If Flash Power Reduction Mode is enabled when entering Power-save or Extended Standby sleep mode, the
device will only wake up on every fourth wake-up request. If Flash Power Reduction Mode is enabled when entering
Idle sleep mode, the wake-up time will vary with up to 16 CPU clock cycles.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 103
8067O–AVR–06/2013
Problem fix/Workaround
Disable Flash Power Reduction mode before entering sleep mode.
29. Some NVM Commands are non-functional
The following NVM commands are non-functional:
Problem fix/Workaround
None for Flash Range CRC
Use separate programming commands for accessing application and boot section.
30. Crystal start-up time required after power-save even if crystal is source for RTC
Even if 32.768 kHz crystal is used for RTC during sleep, the clock from the crystal will not be ready for the system
before the specified start-up time. See "XOSCSEL[3:0]: Crystal Oscillator Selection" in XMEGA A Manual. If BOD
is used in active mode, the BOD will be on during this period (0.5s).
Problem fix/Workaround
If faster start-up is required, go to sleep with internal oscillator as system clock.
31. Setting PRHIRES bit makes PWM output unavailable
Setting the HIRES Power Reduction (PR) bit for PORTx will make any Frequency or PWM output for the corresponding
Timer/Counters (TCx0 and TCx1) unavailable on the pin even if the Hi-Res is not used.
Problem fix/Workaround
Do not write the HIRES PR bit on PORTx when frequency or PWM output from TCx0/1 is used.
– 0x2B Erase Flash Page
– 0x2E Write Flash Page
– 0x2F Erase & Write Flash Page
– 0x3A Flash Range CRC
– 0x22 Erase Application Section Page
– 0x24 Write Application Section Page
– 0x25 Erase & Write Application Section Page
– 0x2A Erase Boot Loader Section Page
– 0x2C Write Boot Loader Section Page
– 0x2D Erase & Write Boot Loader Section Page[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 104
8067O–AVR–06/2013
32. Accessing EBI address space with PREBI set will lock Bus Master
If EBI Power Reduction Bit is set while EBI is enabled, accessing external memory could result in bus hang-up,
blocking all further access to all data memory.
Problem fix/Workaround
Ensure that EBI is disabled before setting EBI Power Reduction bit.
33. RTC Counter value not correctly read after sleep
If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to bit 0 of RTC PER as
the device is entering sleep, the value in the RTC count register can not be read correctly within the first prescaled
RTC clock cycle after wakeup. The value read will be the same as the value in the register when entering sleep.
The same applies if RTC Compare Match is used as wake-up source.
Problem fix/Workaround
Wait at least one prescaled RTC clock cycle before reading the RTC CNT value.
34. Pending asynchronous RTC-interrupts will not wake up device
Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed, will
be ignored until the device is woken from another source or the source triggers again.
Problem fix/Workaround
None.
35. TWI, the minimum I2
C SCL low time could be violated in Master Read mode
If the TWI is in Master Read mode and issues a Repeated Start on the bus, this will immediately release the SCL
line even if one complete SCL low period has not passed. This means that the minimum SCL low time in the I2C
specification could be violated.
Problem fix/Workaround
If this is a problem in the application, ensure in software that the Repeated Start is never issued before one SCL
low time has passed.
36. TWI address-mask feature is non-functional
The address-mask feature is non-functional, so the TWI can not perform hardware address match on more than
one address.
Problem fix/Workaround
If the TWI must respond to multiple addresses, enable Promiscuous Mode for the TWI to respond to all address
and implement the address-mask function in software.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 105
8067O–AVR–06/2013
37. TWI, a general address call will match independent of the R/W-bit value
When the TWI is in Slave mode and a general address call is issued on the bus, the TWI Slave will get an address
match regardless of the received R/W bit.
Problem fix/Workaround
Use software to check the R/W-bit on general call address match.
38. TWI Transmit collision flag not cleared on repeated start
The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only cleared on
start.
Problem fix/Workaround
Clear the flag in software after address interrupt.
39. Clearing TWI Stop Interrupt Flag may lock the bus
If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets this
flag due to a new address received, CLKHOLD is not cleared and the SCL line is not released. This will lock the
bus.
Problem fix/Workaround
Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for the
SCL pin to be low before clearing APIF.
Code:
/* Only clear the interrupt flag if within a "safe zone". */
while ( /* Bus not IDLE: */
((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) !=
TWI_MASTER_BUSSTATE_IDLE_gc)) &&
/* SCL not held by slave: */
!(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm)
)
{
/* Ensure that the SCL line is low */
if ( !(COMMS_PORT.IN & PIN1_bm) )
if ( !(COMMS_PORT.IN & PIN1_bm) )
break;
}
/* Check for an pending address match interrupt */
if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) )
{
/* Safely clear interrupt flag */
COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm;
}[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 106
8067O–AVR–06/2013
40. TWI START condition at bus timeout will cause transaction to be dropped
If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected, the
transaction will be dropped.
Problem fix/Workaround
None.
41. TWI Data Interrupt Flag erroneously read as set
When issuing the TWI slave response command CMD=0b11, it takes 1 Peripheral Clock cycle to clear the data
interrupt flag (DIF). A read of DIF directly after issuing the command will show the DIF still set.
Problem fix/Workaround
Add one NOP instruction before checking DIF.
42. WDR instruction inside closed window will not issue reset
When a WDR instruction is execute within one ULP clock cycle after updating the window control register, the
counter can be cleared without giving a system reset.
Problem fix/Workaround
Wait at least one ULP clock cycle before executing a WDR instruction.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 107
8067O–AVR–06/2013
36.2 ATxmega64A1 and ATxmega128A1 rev. G
Bootloader Section in Flash is non-functional
Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously
DAC is nonlinear and inaccurate when reference is above 2.4V
ADC gain stage output range is limited to 2.4 V
The ADC has up to ±2 LSB inaccuracy
TWI, a general address call will match independent of the R/W-bit value
TWI, the minimum I2
C SCL low time could be violated in Master Read mode
Setting HIRES PR bit makes PWM output unavailable
EEPROM erase and write does not work with all System Clock sources
BOD will be enabled after any reset
Propagation delay analog Comparator increasing to 2 ms at -40C
Sampled BOD in Active mode will cause noise when bandgap is used as reference
Default setting for SDRAM refresh period too low
Flash Power Reduction Mode can not be enabled when entering sleep mode
Enabling Analog Comparator B output will cause JTAG failure
JTAG enable does not override Analog Comparator B output
Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
DAC refresh may be blocked in S/H mode
Inverted I/O enable does not affect Analog Comparator Output
Both DFLLs and both oscillators has to be enabled for one to work
1. Bootloader Section in Flash is non-functional
The Bootloader Section is non-functional, and bootloader or application code cannot reside in this part of the
Flash.
Problem fix/Workaround
None, do not use the Bootloader Section.
2. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously
If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as input
for the another AC, the first comparator will be affected for up to 1 us and could potentially give a wrong comparison
result.
Problem fix/Workaround
If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before enabling
any of them.
3. DAC is nonlinear and inaccurate when reference is above 2.4V
Using the DAC with a reference voltage above 2.4V give inaccurate output when converting codes that give below
0.75V output:
±20 LSB for continuous mode[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 108
8067O–AVR–06/2013
±200 LSB for Sample and Hold mode
Problem fix/Workaround
None, avoid using a voltage reference above 2.4V.
4. ADC gain stage output range is limited to 2.4 V
The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential input will only give correct
output when below 2.4 V/gain. For the available gain settings, this gives a differential input range of:
Problem fix/Workaround
Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a correct result, or keep
ADC voltage reference below 2.4 V.
5. The ADC has up to ±2 LSB inaccuracy
The ADC will have up to ±2 LSB inaccuracy, visible as a saw-tooth pattern on the input voltage/ output value transfer
function of the ADC. The inaccuracy increases with increasing voltage reference reaching ±2 LSB with 3V
reference.
Problem fix/Workaround
None, the actual ADC resolution will be reduced with up to ±2 LSB.
6. TWI, a general address call will match independent of the R/W-bit value
When the TWI is in Slave mode and a general address call is issued on the bus, the TWI Slave will get an address
match regardless of the R/W-bit (ADDR[0] bit) value in the Slave Address Register.
Problem fix/Workaround
Use software to check the R/W-bit on general call address match.
– 1x gain: 2.4 V
– 2x gain: 1.2 V
– 4x gain: 0.6 V
– 8x gain: 300 mV
– 16x gain: 150 mV
– 32x gain: 75 mV
– 64x gain: 38 mV[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 109
8067O–AVR–06/2013
7. TWI, the minimum I2
C SCL low time could be violated in Master Read mode
When the TWI is in Master Read mode and issuing a Repeated Start on the bus, this will immediately release the
SCL line even if one complete SCL low period has not passed. This means that the minimum SCL low time in the
I
2
C specification could be violated.
Problem fix/Workaround
If this causes a potential problem in the application, software must ensure that the Repeated Start is never issued
before one SCL low time has passed.
8. Setting HIRES PR bit makes PWM output unavailable
Setting the HIRES Power Reduction (PR) bit for PORTx will make any Frequency or PWM output for the corresponding
Timer/Counters (TCx0 and TCx1) unavailable on the pin.
Problem fix/Workaround
Do not write the HIRES PR bit on PORTx when frequency or PWM output from TCx0/1 is used.
9. EEPROM erase and write does not work with all System Clock sources
When doing EEPROM erase or Write operations with other clock sources than the 2 MHz RCOSC, Flash will be
read wrongly for one or two clock cycles at the end of the EEPROM operation.
Problem fix/Workaround
Alt 1: Use the internal 2 MHz RCOSC when doing erase or write operations on EEPROM.
Alt 2: Ensure to be in sleep mode while completing erase or write on EEPROM. After starting erase or write operations
on EEPROM, other interrupts should be disabled and the device put to sleep.
10. BOD will be enabled after any reset
If any reset source goes active, the BOD will be enabled and keep the device in reset if the VCC voltage is below
the programmed BOD level. During Power-On Reset, reset will not be released until VCC is above the programmed
BOD level even if the BOD is disabled.
Problem fix/Workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
11. Propagation delay analog Comparator increasing to 2 ms at -40 °C
When the analog comparator is used at temperatures reaching down to -40 °C, the propagation delay will increase
to ~2 ms.
Problem fix/Workaround
None[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 110
8067O–AVR–06/2013
12. Sampled BOD in Active mode will cause noise when bandgap is used as reference
Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap
reference for ADC and DAC.
Problem fix/Workaround
If the bandgap is used as reference for either the ADC or the DAC, the BOD must not be set in sampled mode.
13. Default setting for SDRAM refresh period too low
If the SDRAM refresh period is set to a value less then 0x20, the SDRAM content may be corrupted when accessing
through On-Chip Debug sessions.
Problem fix/Workaround
The SDRAM refresh period (REFRESHH/L) should not be set to a value less then 0x20.
14. Flash Power Reduction Mode can not be enabled when entering sleep mode
If Flash Power Reduction Mode is enabled when entering Power-save or Extended Standby sleep mode, the
device will only wake up on every fourth wake-up request.
If Flash Power Reduction Mode is enabled when entering Idle sleep mode, the wake-up time will vary with up to 16
CPU clock cycles.
Problem fix/Workaround
Disable Flash Power Reduction mode before entering sleep mode.
15. JTAG enable does not override Analog Comparator B output
When JTAG is enabled this will not override the Anlog Comparator B (ACB)ouput, AC0OUT on pin 7 if this is
enabled.
Problem fix/Workaround
AC0OUT for ACB should not be enabled when JTAG is used. Use only analog comparator output for ACA when
JTAG is used, or use the PDI as debug interface.
16. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
The ADC cannot be used to do bandgap measurements when VCC is below 2.7V.
Problem fix/Workaround
If internal voltages must be measured when VCC is below 2.7V, measure the internal 1.00V reference instead of
the bandgap.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 111
8067O–AVR–06/2013
17. DAC refresh may be blocked in S/H mode
If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is done at maximum rate
(i.e. the DAC is always busy doing conversion for this channel), this will block refresh signals to the second channel.
Problem fix/Workarund
When using the DAC in S/H mode, ensure that none of the channels is running at maximum conversion rate, or
ensure that the conversion rate of both channels is high enough to not require refresh.
18. Inverted I/O enable does not affect Analog Comparator Output
The inverted I/O pin function does not affect the Analog Comparator output function.
Problem fix/Workarund
Configure the analog comparator setup to give a inverted result (i.e. connect positive input to the negative AC input
and vice versa), or use and externel inverter to change polarity of Analog Comparator Output.
19. Both DFLLs and both oscillators has to be enabled for one to work
In order to use the automatic runtime calibration for the 2 MHz or the 32 MHz internal oscilla-tors, the DFLL for
both oscillators and both oscillators has to be enabled for one to work.
Problem fix/Workarund
Enabled both DFLLs and oscillators when using automatic runtime calibration for one of the internal oscillators. [Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 112
8067O–AVR–06/2013
37. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The referring revision in this
section are referring to the document revision.
37.1 8067O – 06/2013
37.2 8067N – 03/2013
37.3 8067M – 09/2010
37.4 8067L – 08/2010
1. Not recommended for new designs - Use XMEGA A1U series.
1. Removed all references to ATxmega192A1, ATxmega256A1 and ATxmega384A1.
2. Updated module description. Based on the XMEGA A1U device datasheet.
3. Updated analog comparator (AC) overview, Figure 28-1 on page 53.
4. Updated “ADC Characteristics” on page 76.
5 Updated page erase time in “Flash and EEPROM Memory Characteristics” on page 76.
6 Updated Output low voltage conditions from IOH to IOL in “PAD Characteristics” on page 79.
7. Removed TBDs from:
“DC Characteristics” on page 73.
“DAC Characteristics” on page 78.
“Bandgap Characteristics” on page 78.
8. Updated “Errata” on page 96 to be valid for both ATxmega64A1 and ATxmega128A1.
9. Removed Boundary Scan Order table.
1. Updated Errata “ATxmega64A1and ATxmega128A1 rev. H” on page 96
1. Removed Footnote 3 of Figure 2-1 on page 3
2. Updated “Features” on page 32. Event Channel 0 output on port pin 7
3. Updated “DC Characteristics” on page 73, by adding ICC for Flash/EEPROM Programming.
4. Added AVCC in “ADC Characteristics” on page 76.
5. Updated Start up time in “ADC Characteristics” on page 76. [Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 113
8067O–AVR–06/2013
37.5 8067K – 02/2010
37.6 8067J – 02/2010
37.7 8067I – 04/2009
37.8 8067H – 04/2009
6. Updated “DAC Characteristics” on page 78. Removed DC output impedance.
7. Fixed typo in “Packaging information” section.
8. Fixed typo in “Errata” section.
1. Added “PDI Speed vs. VCC” on page 95.
1. Removed JTAG Reset from the datasheet.
2. Updated “Timer/Counter and AWEX functions” on page 56.
3. Updated “Alternate Pin Functions” on page 58.
3. Updated all “Electrical Characteristics” on page 73.
4. Updated “PAD Characteristics” on page 79.
5. Changed Internal Oscillator Speed to “Oscillators and Wake-up Time” on page 92.
6. Updated “Errata” on page 96
1. Updated “Ordering Information” on page 2.
2. Updated “PAD Characteristics” on page 79.
1. Editorial updates.
2. Updated “Overview” on page 54.
3. Updated Table 29-9 on page 54.
4. Updated “Peripheral Module Address Map” on page 62. IRCOM has address map: 0x08F8.
5. Updated “Electrical Characteristics” on page 73.
6. Updated “PAD Characteristics” on page 79.
7. Updated “Typical Characteristics” on page 82.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 114
8067O–AVR–06/2013
37.9 8067G – 11/2008
37.10 8067F – 09/2008
37.11 8067E – 08/2008
37.12 8067D – 07/2008
1. Updated “Block Diagram” on page 6.
2. Updated feature list in “Memories” on page 12.
3. Updated “Programming and Debugging” on page 54.
4. Updated “Peripheral Module Address Map” on page 62. IRCOM has address 0x8F0.
5. Added “Electrical Characteristics” on page 73.
6. Added “Typical Characteristics” on page 82.
7. Added “ATxmega64A1and ATxmega128A1 rev. H” on page 96.
8. Updated “ATxmega64A1 and ATxmega128A1 rev. G” on page 107.
1. Updated “Features” on page 1
2. Updated “Ordering Information” on page 2
3. Updated Figure 7-1 on page 11 and Figure 7-2 on page 11.
4. Updated Table 7-2 on page 15.
5. Updated “Features” on page 48 and “Overview” on page 48.
6. Removed “Interrupt Vector Summary” section from datasheet.
1. Changed Figure 2-1’s title to “Block diagram and pinout” on page 3.
2. Updated Figure 2-2 on page 4.
3. Updated Table 29-2 on page 51 and Table 29-3 on page 52.
1. Updated “Ordering Information” on page 2.
2. Updated “Peripheral Module Address Map” on page 62.
3. Inserted “Interrupt Vector Summary” on page 56.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 115
8067O–AVR–06/2013
37.13 8067C – 06/2008
37.14 8067B – 05/2008
37.15 8067A – 02/2008
1. Updated the Front page and “Features” on page 1.
2. Updated the “DC Characteristics” on page 73.
3. Updated Figure 3-1 on page 6.
4. Added “Flash and EEPROM Page Size” on page 15.
5. Updated Table 33-6 on page 72 with new data: Gain Error, Offset Error and Signal -to-Noise
Ratio (SNR).
6. Updated Errata “ATxmega64A1 and ATxmega128A1 rev. G” on page 107.
1. Updated “Pinout/Block Diagram” on page 3 and “Pinout and Pin Functions” on page 55.
2. Added XMEGA A1 Block Diagram, Figure 3-1 on page 6.
3. Updated “Overview” on page 5 included the XMEGA A1 explanation text on page 6.
4. Updated AVR CPU “Features” on page 8.
5. Updated Event System block diagram, Figure 10-1 on page 20.
6. Updated “Interrupts and Programmable Multilevel Interrupt Controller” on page 29.
7. Updated “AC - Analog Comparator” on page 52.
8. Updated “Alternate Pin Function Description” on page 55.
9. Updated “Alternate Pin Functions” on page 58.
10. Updated “Typical Characteristics” on page 82.
11. Updated “Ordering Information” on page 2.
12. Updated “Overview” on page 5.
13. Updated Figure 6-1 on page 8.
14. Inserted a new Figure 16-1 on page 37.
15. Updated Speed grades in “Speed” on page 75.
16. Added a new ATxmega384A1 device in “Features” on page 1, updated “Ordering Information” on
page 2 and “Memories” on page 12.
17. Replaced the Figure 3-1 on page 6 by a new XMEGA A1 detailed block diagram.
18. Inserted Errata “ATxmega64A1 and ATxmega128A1 rev. G” on page 107.
1. Initial revision.[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 116
8067O–AVR–06/2013[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 1
8067O–AVR–06/2013
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Pinout/Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4. Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Recommended reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5. Capacitive touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6. Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
7. AVR CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7.3 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7.4 ALU - Arithmetic Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7.5 Program Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7.6 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7.7 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
8. Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8.3 In-System Programmable Flash Program Memory. . . . . . . . . . . . . . . . . . . . . 13
8.4 Fuses and Lock bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.5 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8.6 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.7 I/O Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.8 External Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.9 Data Memory and Bus Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.10 Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8.11 Device ID and Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8.12 I/O Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8.13 JTAG Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8.14 Flash and EEPROM Page Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9. DMAC - Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . 18
9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10. Event System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
11. System Clock and Clock options . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 2
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11.3 Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
12. Power Management and Sleep Modes . . . . . . . . . . . . . . . . . . . . . . 24
12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
12.3 Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
13. System Control and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
13.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
13.3 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
13.4 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
13.5 WDT - Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
13.6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
14. Interrupts and Programmable Multilevel Interrupt Controller . . . . . . 29
14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
14.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
14.3 Interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
15. I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
15.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
15.3 Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
15.4 Input sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
15.5 Port Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
15.6 Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
16. T/C - 16-bit Timer/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
16.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
17. AWeX - Advanced Waveform Extension . . . . . . . . . . . . . . . . . . . . . 38
17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
17.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
18. Hi-Res - High Resolution Extension . . . . . . . . . . . . . . . . . . . . . . . . . 39
18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
18.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
19. RTC - 16-bit Real-Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
19.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
20. TWI - Two-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
20.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
21. SPI - Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
21.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
21.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
22. USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 3
8067O–AVR–06/2013
22.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
22.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
23. IRCOM - IR Communication Module . . . . . . . . . . . . . . . . . . . . . . . . 45
23.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
23.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
24. AES and DES Crypto Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
24.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
24.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
25. EBI – External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
25.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
25.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
26. ADC - 12-bit Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . 48
26.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
26.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
27. DAC - 12-bit Digital to Analog Converter . . . . . . . . . . . . . . . . . . . . . 50
27.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
27.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
28. AC - Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
28.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
28.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
29. Programming and Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
29.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
29.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
30. Pinout and Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
30.1 Alternate Pin Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
30.2 Alternate Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
31. Peripheral Module Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
32. Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
33. Packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
33.1 100A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
33.2 100C1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
33.3 100C2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
34. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
34.1 Absolute Maximum Ratings*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
34.2 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
34.3 Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
34.4 Flash and EEPROM Memory Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 76
34.5 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
34.6 DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
34.7 Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
34.8 Bandgap Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
34.9 Brownout Detection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 4
8067O–AVR–06/2013
34.10 PAD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
34.11 POR Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
34.12 Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
34.13 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
35. Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
35.1 Active Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
35.2 Idle Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
35.3 Power-down Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
35.4 Power-save Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
35.5 Pin Pull-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
35.6 Pin Thresholds and Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
35.7 Bod Thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
35.8 Bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
35.9 Analog Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
35.10 Oscillators and Wake-up Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
35.11 PDI Speed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
36. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
36.1 ATxmega64A1and ATxmega128A1 rev. H. . . . . . . . . . . . . . . . . . . . . . . . . . . 96
36.2 ATxmega64A1 and ATxmega128A1 rev. G . . . . . . . . . . . . . . . . . . . . . . . . . 107
37. Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
37.1 8067O – 06/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
37.2 8067N – 03/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
37.3 8067M – 09/2010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
37.4 8067L – 08/2010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
37.5 8067K – 02/2010. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
37.6 8067J – 02/2010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
37.7 8067I – 04/2009 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
37.8 8067H – 04/2009 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
37.9 8067G – 11/2008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
37.10 8067F – 09/2008. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
37.11 8067E – 08/2008. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
37.12 8067D – 07/2008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
37.13 8067C – 06/2008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
37.14 8067B – 05/2008. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
37.15 8067A – 02/2008. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1[Not recommended for new designs - Use XMEGA A1U series] XMEGA A1 [DATASHEET] 5
8067O–AVR–06/2013Atmel Corporation
1600 Technology Drive
San Jose, CA 95110
USA
Tel: (+1) (408) 441-0311
Fax: (+1) (408) 487-2600
www.atmel.com
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JAPAN
Tel: (+81) (3) 6417-0300
Fax: (+81) (3) 6417-0370
© 2013 Atmel Corporation. All rights reserved. / Rev.: 8067O–AVR–06/2013
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this
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Atmel-42075B-MCU-Atmel SAM4S Xplained Pro-USER GUIDE-03/2013
USER GUIDE
Atmel SAM4S Xplained Pro
Preface
The Atmel® SAM4S Xplained Pro evaluation kit is a hardware platform to
evaluate the ATSAM4SD32C microcontroller.
Supported by the Atmel Studio integrated development platform, the kit provides
easy access to the features of the Atmel ATSAM4SD32C and explains how to
integrate the device in a custom design.
The Xplained Pro MCU series evaluation kits include an on-board Embedded
Debugger, and no external tools are necessary to program or debug the
ATSAM4SD32C.
The Xplained Pro extension series evaluation kits offers additional peripherals to
extend the features of the board and ease the development of custom designs.Atmel SAM4S Xplained Pro [USER GUIDE]
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Table of Contents
Preface .......................................................................................... 1
1. Introduction .............................................................................. 3
1.1. Features .............................................................................. 3
1.2. Kit overview ......................................................................... 3
2. Getting started ......................................................................... 5
2.1. Quick-start ........................................................................... 5
2.2. Connecting the kit ................................................................. 5
2.3. Design documentation and related links ..................................... 5
3. Xplained Pro ............................................................................ 6
3.1. Embedded Debugger ............................................................. 6
3.2. Hardware identification system ................................................. 6
3.3. Power supply ....................................................................... 7
3.3.1. Measuring SAM4S power consumption ......................... 7
3.4. Standard headers and connectors ............................................ 7
3.4.1. Xplained Pro extension header .................................... 7
3.4.2. Xplained Pro LCD connector ....................................... 8
3.4.3. Power header ......................................................... 10
4. Hardware user guide ............................................................ 11
4.1. Connectors ......................................................................... 11
4.1.1. I/O extension headers .............................................. 11
4.1.2. LCD extension connector .......................................... 12
4.1.3. Other headers ........................................................ 14
4.2. Peripherals ......................................................................... 14
4.2.1. NAND Flash ........................................................... 14
4.2.2. SD Card connector .................................................. 15
4.2.3. Crystals ................................................................. 15
4.2.4. Mechanical buttons .................................................. 16
4.2.5. LED ...................................................................... 16
4.2.6. Analog reference ..................................................... 16
4.3. Embedded Debugger implementation ...................................... 16
4.3.1. Serial Wire Debug ................................................... 16
4.3.2. Virtual COM port ..................................................... 16
4.3.3. Atmel Data Gateway Interface ................................... 17
5. Hardware revision history and known issues ........................ 18
5.1. Identifying product ID and revision .......................................... 18
5.2. Revision 5 .......................................................................... 18
5.3. Revision 4 .......................................................................... 18
6. Document revision history ..................................................... 19
7. Evaluation board/kit important notice .................................... 20Atmel SAM4S Xplained Pro [USER GUIDE]
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1. Introduction
1.1 Features
● Atmel ATSAM4SD32C microcontroller
● Embedded debugger (EDBG)
● USB interface
● Programming and debugging (target) through Serial Wire Debug (SWD)
● Virtual COM-port interface to target via UART
● Atmel Data Gateway Interface (DGI) to target via synchronous SPI or TWI
● Four GPIOs connected to target for code instrumentation
● Digital I/O
● Two mechanical buttons (user and reset button)
● One user LED
● Three extension headers
● LCD display header
● USB interface for host and device function (target)
● 2Gb NAND Flash for non-volatile storage
● SD card connector
● Adjustable analog reference
● Three possible power sources
● External power
● Embedded debugger USB
● Target USB
● 12MHz crystal
● 32kHz crystal
1.2 Kit overview
The Atmel SAM4S Xplained Pro evaluation kit is a hardware platform to evaluate the Atmel ATSAM4SD32C.
The kit offers a set of features that enables the ATSAM4SD32C user to get started using the ATSAM4SD32C
peripherals right away and to get an understanding of how to integrate the device in their own design.Atmel SAM4S Xplained Pro [USER GUIDE]
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Figure 1.1. SAM4S Xplained Pro evaluation kit overviewAtmel SAM4S Xplained Pro [USER GUIDE]
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2. Getting started
2.1 Quick-start
3 Steps to start exploring the Atmel Xplained Pro Platform
● Download and install Atmel Studio1
.
● Launch Atmel Studio.
● Connect an USB cable to the DEBUG USB port.
2.2 Connecting the kit
When connecting Atmel SAM4S Xplained Pro to your computer for the first time, the operating system will do a
driver software installation. The driver file supports both 32-bit and 64-bit versions of Microsoft® Windows® XP
and Windows 7.
Once connected the green power LED will be lit and Atmel Studio will autodetect which Xplained Pro
evaluation- and extension kit(s) that's connected. You'll be presented with relevant information like datasheets
and kit documentation. You also have the option to launch Atmel Software Framework (ASF) example
applications. The target device is programmed and debugged by the on-board Embedded Debugger and no
external programmer or debugger tool is needed. Please refer to the Atmel Studio user guide2
for information
regarding how to compile and program the kit.
2.3 Design documentation and related links
The following list contains links to the most relevant documents and software for SAM4S Xplained Pro.
1. Xplained Pro products 3
- Atmel Xplained Pro is a series of small-sized and easy-to-use evaluation kits
for 8- and 32-bit Atmel microcontrollers. It consists of a series of low cost MCU boards for evaluation and
demonstration of features and capabilities of different MCU families.
2. SAM4S Xplained Pro User Guide 4
- PDF version of this User Guide.
3. SAM4S Xplained Pro Design Documentation 5
- Package containing schematics, BOM, assembly
drawings, 3D plots, layer plots etc.
4. Atmel Studio 6
- Free Atmel IDE for development of C/C++ and assembler code for Atmel
microcontrollers.
5. IAR Embedded Workbench®
7
for ARM®. This is a commercial C/C++ compiler that is available for
ARM. There is a 30 day evaluation version as well as a code size limited kick-start version available from
their website. The code size limit is 16K for devices with M0, M0+ and M1 cores and 32K for devices with
other cores.
6. Atmel sample store 8
- Atmel sample store where you can order samples of devices.
1
http://www.atmel.com/atmelstudio
2
http://www.atmel.com/atmelstudio
3
http://www.atmel.com/XplainedPro
4
http://www.atmel.com/Images/Atmel-42075-SAM4S-Xplained-Pro_User-Guide.pdf
5
http://www.atmel.com/Images/Atmel-42075-SAM4S-Xplained-Pro_User-Guide.zip
6
http://www.atmel.com/atmelstudio
7
http://www.iar.com/en/Products/IAR-Embedded-Workbench/ARM/
8
http://www.atmel.com/system/samplesstoreAtmel SAM4S Xplained Pro [USER GUIDE]
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3. Xplained Pro
Xplained Pro is an evaluation platform that provides the full Atmel microcontroller experience. The platform
consists of a series of Microcontroller (MCU) boards and extension boards that are integrated with Atmel
Studio, have Atmel Software Framework (ASF) drivers and demo code, support data streaming and more.
Xplained Pro MCU boards support a wide range of Xplained Pro extension boards that are connected through
a set of standardized headers and connectors. Each extension board has an identification (ID) chip to uniquely
identify which boards are mounted on a Xplained Pro MCU board. This information is used to present relevant
user guides, application notes, datasheets and example code through Atmel Studio. Available Xplained Pro
MCU and extension boards can be purchased in the Atmel Web Store
1
.
3.1 Embedded Debugger
The SAM4S Xplained Pro contains the Atmel® Embedded Debugger (EDBG) for on-board debugging. The
EDBG is a composite USB device of 3 interfaces; a debugger, Virtual COM Port and Data Gateway Interface
(DGI).
In conjunction with Atmel Studio, the EDBG debugger interface can program and debug the ATSAM4SD32C.
On the SAM4S Xplained Pro, the SWD interface is connected between the EDBG and the ATSAM4SD32C.
The Virtual COM Port is connected to a UART port on the ATSAM4SD32C (see section “Embedded Debugger
implementation” on page 16 for pinout), and provides an easy way to communicate with the target
application through a simple terminal software. It offers variable baud rate, parity and stop bit settings. Note
that the settings on the target device UART must match the settings given in the terminal software.
The DGI consists of several physical data interfaces for communication with the host computer. Please,
see section “Embedded Debugger implementation” on page 16 for available interfaces and pinout.
Communication over the interfaces are bidirectional. It can be used to send events and values from the
ATSAM4SD32C, or as a generic printf-style data channel. Traffic over the interfaces can be timestamped on
the EDBG for more accurate tracing of events. Note that timestamping imposes an overhead that reduces
maximal throughput. The DGI uses a proprietary protocol, and is thus only compatible with Atmel Studio.
The EDBG controls two LEDs on SAM4S Xplained Pro, a power LED and a status LED. Table 3.1, “EDBG LED
control” shows how the LEDs are controlled in different operation modes.
Table 3.1. EDBG LED control
Operation mode Power LED Status LED
Normal operation Power LED is lit when power is
applied to the board.
Activity indicator, LED flashes
every time something happens on
the EDBG.
Bootloader mode (idle) The power LED and the status LED blinks simultaneously.
Bootloader mode (firmware
upgrade)
The power LED and the status LED blinks in an alternating pattern.
For further documentation on the EDBG, see the EDBG User Guide.
3.2 Hardware identification system
All Xplained Pro compatible extension boards have an Atmel ATSHA204 crypto authentication chip mounted.
This chip contains information that identifies the extension with its name and some extra data. When an
Xplained Pro extension board is connected to an Xplained Pro MCU board the information is read and sent
to Atmel Studio. The Atmel Kits extension, installed with Atmel Studio, will give relevant information, code
examples and links to relevant documents. Table 3.2, “Xplained Pro ID chip content” shows the data fields
stored in the ID chip with example content.
Table 3.2. Xplained Pro ID chip content
Data Field Data Type Example Content
Manufacturer ASCII string Atmel’\0’
Product Name ASCII string Segment LCD1 Xplained Pro’\0’
Product Revision ASCII string 02’\0’
Product Serial Number ASCII string 1774020200000010’\0’
Minimum Voltage [mV] uint16_t 3000
1
http://store.atmel.com/CBC.aspx?q=c:100113Atmel SAM4S Xplained Pro [USER GUIDE]
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Data Field Data Type Example Content
Maximum Voltage [mV] uint16_t 3600
Maximum Current [mA] uint16_t 30
3.3 Power supply
The SAM4S Xplained Pro kit can be powered either by USB or by an external power source through the 4-
pin power header, marked PWR. This connector is described in “Power header” on page 10. The available
power sources and specifications are listed in Table 3.3, “Power sources for SAM4S Xplained Pro”.
Table 3.3. Power sources for SAM4S Xplained Pro
Power input Voltage requirements Current requirements Connector marking
External power 5 V +/- 2 % (+/- 100 mV)
for USB host operation.
4.3 V to 5.5 V if USB
host operation is not
required
Recommended
minimum is 1A to be
able to provide enough
current for connected
USB devices and the
board itself.
Recommended
maximum is 2A due
to the input protection
maximum current
specification.
PWR
Embedded debugger
USB
4.4V to 5.25V
(according to USB spec)
500 mA (according to
USB spec)
DEBUG USB
Target USB 4.4V to 5.25V
(according to USB spec)
500 mA (according to
USB spec)
TARGET USB
The kit will automatically detect which power sources are available and choose which one to use according to
the following priority:
1. External power
2. Embedded debugger USB
3. Target USB
Note External power is required when the 500mA through the USB connector is not enough to power a
connected USB device in a USB host application.
3.3.1 Measuring SAM4S power consumption
As part of an evaluation of the SAM4S it can be of interest to measure its power consumption. Because the
device has a separate power plane (VCC_MCU_P3V3) on this board it is possible to measure the current
consumption by measuring the current that is flowing into this plane. The VCC_MCU_P3V3 plane is connected
via a jumper to the main power plane (VCC_TARGET_P3V3) and by replacing the jumper with an ampere
meter it is possible to determine the current consumption. To locate the current measurement header, please
refer to Figure 1.1, “SAM4S Xplained Pro evaluation kit overview”.
Warning Do not power the board without having the jumper or an ampere meter mounted. This can cause
the SAM4S to be powered through its I/O pins and cause undefined operation of the device.
3.4 Standard headers and connectors
3.4.1 Xplained Pro extension header
All Xplained Pro kits have one or more dual row, 20 pin, 100mil extension headers. Xplained Pro MCU boards
have male headers while Xplained Pro extensions have their female counterparts. Note that all pins are
not always connected. However, all the connected pins follow the defined pin-out described in Table 3.4,
“Xplained Pro extension header”. The extension headers can be used to connect a wide variety of Xplained ProAtmel SAM4S Xplained Pro [USER GUIDE]
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extensions to Xplained Pro MCU boards and to access the pins of the target MCU on Xplained Pro MCU board
directly.
Table 3.4. Xplained Pro extension header
Pin number Name Description
1 ID Communication line to the ID chip on extension board.
2 GND Ground
3 ADC(+) Analog to digital converter , alternatively positive part of differential
ADC
4 ADC(-) Analog to digital converter , alternatively negative part of
differential ADC
5 GPIO1 General purpose IO
6 GPIO2 General purpose IO
7 PWM(+) Pulse width modulation , alternatively positive part of differential
PWM
8 PWM(-) Pulse width modulation , alternatively positive part of differential
PWM
9 IRQ/GPIO Interrupt request line and/or general purpose IO.
10 SPI_SS_B/GPIO Slave select for SPI and/or general purpose IO.
11 TWI_SDA Data line for two wire interface. Always implemented, bus type.
12 TWI_SCL Clock line for two wire interface. Always implemented, bus type.
13 USART_RX Receiver line of Universal Synchronous and Asynchronous serial
Receiver and Transmitter
14 USART_TX Transmitter line of Universal Synchronous and Asynchronous
serial Receiver and Transmitter
15 SPI_SS_A Slave select for SPI. Should be unique if possible.
16 SPI_MOSI Master out slave in line of Serial peripheral interface. Always
implemented, bus type
17 SPI_MISO Master in slave out line of Serial peripheral interface. Always
implemented, bus type
18 SPI_SCK Clock for Serial peripheral interface. Always implemented, bus
type
19 GND Ground
20 VCC Power for extension board
3.4.2 Xplained Pro LCD connector
The LCD connector provides the ability to connect to display extensions that have a parallel interface. The
connector implements signals for a MCU parallel bus interface and a LCD controller interface as well as signals
for a touchcontroller. The connector pin-out definition is shown in Table 3.5, “Xplained Pro LCD connector”.
Note that usually only one display interface is implemented, either LCD controller or the MCU bus interface.
A FPC/FFC connector with 50 pins and 0.5mm pitch is used for the LCD connector. The connector
(XF2M-5015-1A) from Omron is used on several designs and can be used as a reference.
Table 3.5. Xplained Pro LCD connector
Pin number Name RGB interface
description
MCU interface
description
1 ID Communication line to ID chip on extension board.
2 GND Ground
3 D0 Data line
4 D1 Data line
5 D2 Data line
6 D3 Data lineAtmel SAM4S Xplained Pro [USER GUIDE]
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Pin number Name RGB interface
description
MCU interface
description
7 GND Ground
8 D4 Data line
9 D5 Data line
10 D6 Data line
11 D7 Data line
12 GND Ground
13 D8 Data line
14 D9 Data line
15 D10 Data line
16 D11 Data line
17 GND Ground
18 D12 Data line
19 D12 Data line
20 D14 Data line
21 D15 Data line
22 GND Ground
23 D16 Data line
24 D17 Data line
25 D18 Data line
26 D19 Data line
27 GND Ground
28 D20 Data line
29 D21 Data line
30 D22 Data line
31 D23 Data line
32 GND Ground
33 PCLK /
CMD_DATA_SEL
Pixel clock Command and data
select. One address line
of the MCU for displays
where it is possible to
select either the register
or the data interface.
34 VSYNC / CS Vertical synchronization Chip select
35 HSYNC / WE Horizontal
synchronization
Write enable signal
36 DATA ENABLE / RE Data enable signal Read enable signal
37 SPI SCK Clock for Serial peripheral interface
38 SPI MOSI Master out slave in line of Serial peripheral interface
39 SPI MISO Master in slave out line of Serial peripheral interface
40 SPI SS Slave select for SPI. Should be unique if possible
41 ENABLE Display enable signal
42 TWI SDA I2C data line (maxTouch)
43 TWI SCL I2C clock line (maxTouch)
44 IRQ1 maxTouch interrupt lineAtmel SAM4S Xplained Pro [USER GUIDE]
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Pin number Name RGB interface
description
MCU interface
description
45 IRQ2 Interrupt line for other I2C devices
46 PWM Backlight control
47 RESET Reset for both display and maxTouch
48 VCC 3.3V power supply for extension board
49 VCC 3.3V power supply for extension board
50 GND Ground
3.4.3 Power header
The power header can be used to connect external power to the SAM4S Xplained Pro kit. The kit will
automatically detect and switch to the external power if supplied. The power header can also be used as supply
for external peripherals or extension boards. Care must be taken not to exceed the total current limitation of the
on-board regulator for the 3.3V regulated output. To locate the current measurement header, please refer to
Figure 1.1, “SAM4S Xplained Pro evaluation kit overview”
Table 3.6. Power header PWR
Pin number PWR header Pin name Description
1 VEXT_P5V0 External 5V input
2 GND Ground
3 VCC_P5V0 Unregulated 5V (output, derived
from one of the input sources)
4 VCC_P3V3 Regulated 3.3V (output, used as
main power for the kit)
Note If the board is powered from a battery source it is recommended to use the PWR header. If there
is a power source connected to EDBG USB, the EDBG is activated and it will consume more
power.Atmel SAM4S Xplained Pro [USER GUIDE]
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4. Hardware user guide
4.1 Connectors
This chapter describes the implementation of the relevant connectors and headers on SAM4S Xplained Pro
and their connection to the ATSAM4SD32C. The tables of connections in this chapter also describes which
signals are shared between the headers and on-board functionality.
4.1.1 I/O extension headers
The SAM4S Xplained Pro headers EXT1, EXT2 and EXT3 offers access to the I/O of the microcontroller in
order to expand the board e.g. by connecting extensions to the board. These headers all comply with the
standard extension header specified in Xplained Pro Standard Extension Header. All headers have a pitch of
2.54 mm.
Table 4.1. Extension header EXT1
Pin on EXT1 SAM4S pin Function Shared functionality
1 - - Communication line to ID chip on
extension board.
2 - - GND
3 PA17 AD[0]
4 PA18 AD[1]
5 PA24 GPIO PIOD Interface Header
6 PA25 GPIO PIOD Interface Header
7 PA23 PWMH0 PIOD Interface Header
8 PA19 PWML0
9 PA1 WKUP1/GPIO
10 PA6 GPIO DGI_GPIO0 on EDBG
11 PA3 TWD0 EXT2 and EDBG
12 PA4 TWCK0 EXT2 and EDBG
13 PA21 USART1/RXD1 EXT2
14 PA22 USART1/TXD1 EXT2
15 PA11 SPI/NPCS[0]
16 PA13 SPI/MOSI EXT2, EXT3, LCD connector (EXT4) and
EDBG
17 PA12 SPI/MISO EXT2, EXT3, LCD connector (EXT4) and
EDBG
18 PA14 SPI/SPCK EXT2, EXT3, LCD connector (EXT4) and
EDBG
19 - - GND
20 - - VCC
Table 4.2. Extension header EXT2
Pin on EXT2 SAM4S pin Function Shared functionality
1 - - Communication line to ID chip on
extension board.
2 - - GND
3 PB0 AD[4]
4 PB1 AD[5]
5 PC24 GPIO DGI_GPIO2 on EDBG
6 PC25 GPIO DGI_GPIO3 on EDBG
7 PC19 PWMH1Atmel SAM4S Xplained Pro [USER GUIDE]
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Pin on EXT2 SAM4S pin Function Shared functionality
8 PA20 PWML1
9 PC26 GPIO
10 PC27 GPIO
11 PA3 TWD0 EXT1 and EDBG
12 PA4 TWCK0 EXT1 and EDBG
13 PA21 USART1/RXD1 EXT1
14 PA22 USART1/TXD1 EXT1
15 PA9 SPI/NPCS[1] LCD connector (EXT4)
16 PA13 SPI/MOSI EXT1, EXT3, LCD connector (EXT4) and
EDBG
17 PA12 SPI/MISO EXT1, EXT3, LCD connector (EXT4) and
EDBG
18 PA14 SPI/SPCK EXT1, EXT3, LCD connector (EXT4) and
EDBG
19 - - GND
20 - - VCC
Table 4.3. Extension header EXT3
Pin on EXT3 SAM4S pin Function Shared functionality
1 - - Communication line to ID chip on
extension board.
2 - - GND
3 PC29 AD[13]
4 PC30 AD[14]
5 PC21 GPIO
6 PC22 GPIO DGI_GPIO1 on EDBG
7 PC20 PWMH2
8 PA16 PWML2 PIOD Header
9 PA0 WKUP0/GPIO LCD connector (EXT4)
10 PC31 GPIO
11 PB4 TWD1 LCD connector (EXT4)
12 PB5 TWCK1 LCD connector (EXT4)
13 PB2 USART1/RXD1 CDC UART
14 PB3 USART1/TXD1 CDC UART
15 PA10 SPI/NPCS[2] LCD connector (EXT4)
16 PA13 SPI/MOSI EXT1, EXT2, LCD connector (EXT4) and
EDBG
17 PA12 SPI/MISO EXT1, EXT2, LCD connector (EXT4) and
EDBG
18 PA14 SPI/SPCK EXT1, EXT2, LCD connector (EXT4) and
EDBG
19 - - GND
20 - - VCC
4.1.2 LCD extension connector
Extension connector EXT4 is a special connector for LCD displays. The physical connector is an Omron
Electronics XF2M-5015-1A FPC connector.Atmel SAM4S Xplained Pro [USER GUIDE]
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Table 4.4. LCD display connector EXT4
Pin on EXT4 SAM4S pin Function Shared functionality
1 - - Communication line to ID chip on
extension board.
2 - - GND
3 PC0 D0 NAND Flash
4 PC1 D1 NAND Flash
5 PC2 D2 NAND Flash
6 PC3 D3 NAND Flash
7 - - GND
8 PC4 D4 NAND Flash
9 PC5 D5 NAND Flash
10 PC6 D6 NAND Flash
11 PC7 D7 NAND Flash
12 - - GND
13 - -
14 - -
15 - -
16 - -
17 - - GND
18 - -
19 - -
20 - -
21 - -
22 - - GND
23 - -
24 - -
25 - -
26 - -
27 - - GND
28 - -
29 - -
30 - -
31 - -
32 - - GND
33 PC18 A0
34 PC15 NPCS[1]
35 PC8 NWE
36 PC11 NRD
37
38
39
40
41 PB14 GPIO
42 PB4 TWD1/SDA EXT3Atmel SAM4S Xplained Pro [USER GUIDE]
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Pin on EXT4 SAM4S pin Function Shared functionality
43 PB5 TWCK1/SCL EXT3
44 PA0 WKUP0 EXT3
45 - -
46 PA15 PWML3 PIOD Interface header
47 PC28 GPIO
48 - VCC_P3V3
49 - VCC_P3V3 EXT2
50 - GND
4.1.3 Other headers
In addition to the “I/O extension headers” on page 11, SAM4S Xplained Pro has two additional headers
with spare signals that offers access to the I/O of the microcontroller which are otherwise not easily available
elsewhere or might be favourable to have collected toghether. All headers have a pitch of 2.54mm.
Table 4.5. SPARE SIGNALS header
Pin on header SAM4S pin Function Shared functionality
1 PA2 DATRG User button, SW0
2 PA9 PWMF10 EXT2
3 PA26 TI0A2 SD Card and PIOD Interface header
4 PA27 TI0B2 SD Card and PIOD Interface header
5 PA28 TCLK1 SD Card and PIOD Interface header
6 PA29 TCLK2 SD Card and PIOD Interface header
7 PA31 PCK2 SD Card and PIOD Interface header
8 PB0 RTCOUT0 EXT2
9 PB1 RTCOUT1 EXT2
10 PB13 DAC0
11 PB14 DAC1
12 - - GND
Table 4.6. PIOD INTERFACE header
Pin on header SAM4S pin Function Shared functionality
1 PA15 PIODCEN1 LCD connector
2 PA16 PIODCEN2 EXT3
3 PA23 PIODCCLK EXT1
4 PA24 PIODC0 EXT1
5 PA25 PIODC1 EXT1
6 PA26 PIODC2 SD Card and SPARE Signals header
7 PA27 PIODC3 SD Card and SPARE Signals header
8 PA28 PIODC4 SD Card and SPARE Signals header
9 PA29 PIODC5 SD Card and SPARE Signals header
10 PA30 PIODC6 SD Card
11 PA31 PIODC7 SD Card and SPARE Signals header
12 - - GND
4.2 Peripherals
4.2.1 NAND Flash
The SAM4S Xplained Pro kit has one 2Gb NAND Flash connected to the external bus interface of the SAM4S.Atmel SAM4S Xplained Pro [USER GUIDE]
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Table 4.7. NAND Flash connections
SAM4S pin Function NAND Flash
function
Shared functionality
PC0 D0 IO0 LCD connector
PC1 D1 IO1 LCD connector
PC2 D2 IO2 LCD connector
PC3 D3 IO3 LCD connector
PC4 D4 IO4 LCD connector
PC5 D5 IO5 LCD connector
PC6 D6 IO6 LCD connector
PC7 D7 IO7 LCD connector
PC9 NANDOE RE (active low)
PC10 NANDWE WE (active low)
PC13 GPIO R (active high)/ B
(active low)
PC14 NCS[0] CE (active low)
PC16 NANDALE ALE (active low)
PC17 NANDCLE CLE
4.2.2 SD Card connector
The SAM4S Xplained Pro kit has one SD card connector which is connected to High Speed Multimedia Card
Interface (HSMCI) of the SAM4S
Table 4.8. SD Card connections
SAM4S pin Function SD Card function Shared functionality
PA26 MCDA2 DAT2 SPARE Signal and PIOD Interface
headers
PA27 MCDA3 DAT3 SPARE Signal and PIOD Interface
headers
PA28 MCCDA CMD SPARE Signal and PIOD Interface
headers
PA29 MCCK CLK SPARE Signal and PIOD Interface
headers
PA30 MCDA0 DAT0 PIOD Interface header
PA31 MCDA1 DAT1 SPARE Signal and PIOD Interface
headers
PC12 GPIO Card Detect
4.2.3 Crystals
The SAM4S Xplained Pro kit contains two crystals that can be used as clock sources for the SAM4S device.
Each crystal has a cut-strap next to it that can be used to measure the oscillator safety factor. This is done by
cutting the strap and adding a resistor across the strap. More information about oscillator allowance and safety
factor can be found in appnote AVR4100
1
.
Table 4.9. External 32.768kHz crystals
Pin on SAM4S Function
PA49 XIN32
PA48 XOUT32
1
http://www.atmel.com/images/doc8333.pdfAtmel SAM4S Xplained Pro [USER GUIDE]
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Table 4.10. External 12MHz crystals
Pin on SAM4S Function
PB9 XIN0
PB8 XOUT0
4.2.4 Mechanical buttons
SAM4S Xplained Pro contains two mechanical buttons. One button is the RESET button connected to the
SAM4S reset line and the other is a generic user configurable button. When a button is pressed it will drive the
I/O line to GND.
Table 4.11. Mechanical buttons
Pin on SAM4S Silkscreen text
NRST RESET
PC24 SW0
4.2.5 LED
There is one yellow LED available on the SAM4S Xplained Pro board that can be turned on and off. The LED
can be activated by driving the connected I/O line to GND.
Table 4.12. LED connections
Pin on SAM4S LED
PC23 Yellow LED0
4.2.6 Analog reference
An adjustable voltage reference is implemented on the kit to have a reference for the ADC or DAC. The
reference can be adjusted with the on-board multiturn trimmer potentiometer. Next to the potentiometer, a 2-pin
header is available to measure the reference voltage for the AREF pin of the SAM4S. The voltage output range
for the reference is 0V - 3.36V.
4.3 Embedded Debugger implementation
SAM4S Xplained Pro contains an Embedded Debugger (EDBG) that can be used to program and debug the
ATSAM4SD32C using Serial Wire Debug (SWD). The Embedded Debugger also include a Virtual Com port
interface over UART, an Atmel Data Gateway Interface over SPI and TWI and it monitors four of the SAM4S
GPIOs. Atmel Studio can be used as a front end for the Embedded Debugger.
4.3.1 Serial Wire Debug
The Serial Wire Debug (SWD) use two pins to communicate with the target. For further information on how to
use the programming and debugging capabilities of the EDBG, see “Embedded Debugger” on page 6.
Table 4.13. SWD connections
Pin on SAM4S Function
PB7 SWD clock
PB6 SWD data
PB5 SWD trace output
PB12 Erase
4.3.2 Virtual COM port
The Embedded Debugger act as a Virtual Com Port gateway by using one of the ATSAM4SD32C UARTs. For
further information on how to use the Virtual COM port see “Embedded Debugger” on page 6.
Table 4.14. Virtual COM port connections
Pin on SAM4S Function
PB3 UART TXD (SAM4S TX line)Atmel SAM4S Xplained Pro [USER GUIDE]
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Pin on SAM4S Function
PB2 UART RXD (SAM4S RX line)
4.3.3 Atmel Data Gateway Interface
The Embedded Debugger features an Atmel Data Gateway Interface (DGI) by using either a SPI or TWI port.
The DGI can be used to send a variety of data from the SAM4S to the host PC. For further information on how
to use the DGI interface see “Embedded Debugger” on page 6.
Table 4.15. DGI interface connections when using SPI
Pin on SAM4S Function
PA5 Slave select (SAM4S is Master)
PA12 SPI MISO (Master In, Slave Out)
PA13 SPI MOSI (Master Out, Slave in)
PA14 SPI SCK (Clock Out)
Table 4.16. DGI interface connections when using TWI
Pin on SAM4S Function
PA3 SDA (Data line)
PA4 SCL (Clock line)
Four GPIO lines are connected to the Embedded Debugger. The EDBG can monitor these lines and time
stamp pin value changes. This makes it possible to accurately time stamp events in the SAM4S application
code. For further information on how to configure and use the GPIO monitoring features see “Embedded
Debugger” on page 6.
Table 4.17. GPIO lines connected to the EDBG
Pin on SAM4S Function
PA6 GPIO0
PA22 GPIO1
PA24 GPIO2
PA25 GPIO3Atmel SAM4S Xplained Pro [USER GUIDE]
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5. Hardware revision history and known issues
5.1 Identifying product ID and revision
The revision and product identifier of Xplained Pro boards can be found in two ways, through Atmel Studio or
by looking at the sticker on the bottom side of the PCB.
By connecting a Xplained Pro MCU board to a computer with Atmel Studio running, an information window will
pop up. The first 6 digits of the serial number, which is listed under kit details, contain the product identifier and
revision. Information about connected Xplained Pro extension boards will also appear in the Atmel Kits window.
The same information can be found on the sticker on the bottom side of the PCB. Most kits will print the
identifier and revision in plain text as A09-nnnn\rr where nnnn is the identifier and rr is the revision. Boards with
limited space have a sticker with only a QR-code which contains a serial number string.
The serial number string has the following format:
"nnnnrrssssssssss"
n = product identifier
r = revision
s = serial number
The kit identifier for SAM4S Xplained Pro is 1803.
5.2 Revision 5
On this revision, the SPI clock net is improved to reduce any issues that might be caused by reflections. The
SPI has been removed from the LCD (EXT4 connector) to reduce load on the clock net. The remaining clock
lines have been divided into four terminated nets for each SPI source (EXT1, EXT2, EXT3, and EDBG) and
routed in a star like layout. A series terminator resistor of 43ohm is placed on each clock net, close to the SPI
clock pin. This reduces any issues that might be caused by reflections comming back from unterminated/
unused clock lines. It also reduces the rise/fall time of the clock edges and that will also help to reduce any
reflection issues.
5.3 Revision 4
Known issues
● SAM4S has an on-die series termination of the SPI CLK which makes this signal not usable for a multi
drop clock distribution because all devices along the line will see a fraction of VCC until the signal is
reflected from the end of the transmission line. On the SAM4S Xplained Pro revision 4 this signal is
routed to each extension connector with EXT1 at the end of the line. That means extensions that are
connected along the transission line e.g. EXT3 header is likely to fail due to a non-monotinic edge caused
by relections and the fraction of VCC that is present for a short time until the reflection comes back from
the end of the line.
Workaround:
● By slowing down the clock rise time with a capacitor, and thus effectively increasing the line length at
which point it becomes a transmission line, it is possible to remove the clock issue. A 56pF capacitor
has been mounted on the bottom side of the board between the SPI clock and GND. This however
reduces the maximum SPI clock speed and it is recommended to not run this faster than 30MHz (this
also depends on how much additional capacitance is added by connected extensions and needs to
be checked case by case). The capacitor was added on revision 4 on the bottom side of the EXT3
header.Atmel SAM4S Xplained Pro [USER GUIDE]
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6. Document revision history
Doc. Rev. Date Comment
B 15/03/2013 Added information about changes done on rev 5
A 11/02/2013 First releaseAtmel SAM4S Xplained Pro [USER GUIDE]
Atmel-42075B-MCU-Atmel SAM4S Xplained Pro-USER GUIDE-03/2013
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7. Evaluation board/kit important notice
This evaluation board/kit is intended for use for FURTHER ENGINEERING, DEVELOPMENT,
DEMONSTRATION, OR EVALUATION PURPOSES ONLY. It is not a finished product and may not (yet)
comply with some or any technical or legal requirements that are applicable to finished products, including,
without limitation, directives regarding electromagnetic compatibility, recycling (WEEE), FCC, CE or UL
(except as may be otherwise noted on the board/kit). Atmel supplied this board/kit "AS IS," without any
warranties, with all faults, at the buyer's and further users' sole risk. The user assumes all responsibility
and liability for proper and safe handling of the goods. Further, the user indemnifies Atmel from all claims
arising from the handling or use of the goods. Due to the open construction of the product, it is the user's
responsibility to take any and all appropriate precautions with regard to electrostatic discharge and any other
technical or legal concerns.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER USER NOR
ATMEL SHALL BE LIABLE TO EACH OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR
CONSEQUENTIAL DAMAGES.
No license is granted under any patent right or other intellectual property right of Atmel covering or relating
to any machine, process, or combination in which such Atmel products or services might be or are used.
Mailing Address: Atmel Corporation
1600 Technology Drive
San Jose, CA 95110
USAAtmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com
© 2013 Atmel Corporation. All rights reserved. / Rev.: Atmel-42075B-MCU-Atmel SAM4S Xplained Pro-USER GUIDE-03/2013
Atmel®, Atmel logo and combinations thereof, AVR®, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel
Corporation or its subsidiaries. Windows® is a registered trademark of Microsoft Corporation in U.S. and or other countries. ARM® is a registered
trademark of ARM Ltd. Other terms and product names may be trademarks of others.
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted
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ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT
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Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended
to support or sustain life.
APPLICATION NOTE
Atmel AVR600: STK600 Expansion, Routing and Socket
Boards
Atmel Microcontrollers
Introduction
This application note describes the process of developing new routing, socket and
expansion cards for the Atmel STK®
600. It also describes the physical parameters for
creating such cards.
The STK600 starter kit from Atmel has a sandwich design to match a specific part
package and pin out to the generic pin headers. It also features an expansion area
where most part pins are available.
While the variety of IC packages is relatively limited, the number of possible pinouts
increases rapidly with the number of pins. I.e. a 6-pin IC can have 720 (6!) different
pinouts!
The routing / socket card design provides a lowcost solution to support upcoming
devices as the socket is the cost driving factor.
STK600 users might also want to create their own routing cards to include
specialized hardware to prototype their own design.
Figure 1. STK600 router and socket card.
8170C−AVR−03/2013Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
2
Table of Contents
1. Routing Cards ...................................................................................... 3
1.1 Connector footprints .......................................................................................... 3
1.2 Physical dimensions and component placement .............................................. 4
1.3 Atmel STK600 socket connectors pinout .......................................................... 5
1.3.1 Signal descriptions .............................................................................. 8
2. Socket Cards ..................................................................................... 10
2.1 Power design issues ....................................................................................... 10
2.2 Connector MPN ............................................................................................... 10
2.3 Physical dimensions and component placement ............................................ 10
3. Expansion Cards ................................................................................ 11
3.1 Connector MPN ............................................................................................... 11
3.2 Physical dimensions and component placement ............................................ 12
3.3 Atmel STK600 expansion connectors pinout .................................................. 13
4. ID System .......................................................................................... 17
4.1 Signal usage ................................................................................................... 17
4.2 ID functions ..................................................................................................... 18
4.3 Examples ........................................................................................................ 19
5. Design Example ................................................................................. 20
6. Revision History ................................................................................. 22Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
3
1. Routing Cards
The routing cards sit between the generic socket card and the Atmel STK600. It has one pair of electric pads
underneath to mate with the STK600 spring loaded connector, and one pair of pads on top where the socket card
connector connects. A part specific card with the target IC soldered on can be viewed as a routing card without the top
pads.
1.1 Connector footprints
A routing card should have pads to mate with the following spring loaded connectors:
Table 1-1. Router card connectors.
Manufacturer and MPN Quantity Comment
SAMTEC, FSI-140-03-G-D-AD 2 80-pins to socket card (top)
SAMTEC, FSI-150-03-G-D-AD 2 100-pins to STK600 (bottom)
Figure 1-1. PCB land pattern for mating to FSI connectors. Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
4
1.2 Physical dimensions and component placement
Figure 1-2. Routing card connector pad placement and dimensions.
Figure 1-3. Clip hole dimensions.
The board thickness should be 1.6mm to be compatible with the clips.
Note: Components on the main board might conflict with through hole mounted or secondary side mounted components.
Areas with such components are highlighted in Figure 1-4. Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
5
Figure 1-4. Height restricted areas due to main board components.
1.3 Atmel STK600 socket connectors pinout
Figure 1-5 shows the pinout for the STK600 headers. This corresponds to the routing card connectors J1 and J2.
Figure 1-5. STK600 socket connectors’ pinout. Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
6
Table 1-2. Atmel STK600 J201 left, routing card connector J1 pinout.
Signal name Pin number Signal name
VTG 2 1 GND
PA1 4 3 PA0
PA3 6 5 PA2
PA5 8 7 PA4
PA7 10 9 PA6
VTG 12 11 GND
PB1 14 13 PB0
PB3 16 15 PB2
PB5 18 17 PB4
PB7 20 19 PB6
VTG 22 21 GND
PC1 24 23 PC0
PC3 26 25 PC2
PC5 28 27 PC4
PC7 30 29 PC6
VTG 32 31 GND
PD1 34 33 PD0
PD3 36 35 PD2
PD5 38 37 PD4
PD7 40 39 PD6
VTG 42 41 GND
PE1 44 43 PE0
PE3 46 45 PE2
PE5 48 47 PE4
PE7 50 49 PE6
VTG 52 51 GND
PF1 54 53 PF0
PF3 56 55 PF2
PF5 58 57 PF4
PF7 60 59 PF6
VTG 62 61 GND
PG1 64 63 PG0
PG3 66 65 PG2
PG5 68 67 PG4
PG7 70 69 PG6
VTG 72 71 GND
PH1 74 73 PH0
PH3 76 75 PH2
PH5 78 77 PH4 Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
7
PH7 80 79 PH6
VTG 82 81 GND
AREF0 84 83 XTAL1
AREF1 86 85 XTAL2
TGT_MOSI 88 87 GND
TGT_MISO 90 89 TOSC1
TGT_SCK 92 91 TOSC2
TDI 94 93 TGT_RESET
TDO 96 95 GND
TMS 98 97 Vext
TCK 100 99 Vcc
Table 1-3. Atmel STK600 J202 right, routing card connector J2 pinout.
Signal name Pin number Signal name
VTG 2 1 GND
PJ1 4 3 PJ0
PJ3 6 5 PJ2
PJ5 8 7 PJ4
PJ7 10 9 PJ6
VTG 12 11 GND
PK1 14 13 PK0
PK3 16 15 PK2
PK5 18 17 PK4
PK7 20 19 PK6
VTG 22 21 GND
PL1 24 23 PL0
PL3 26 25 PL2
PL5 28 27 PL4
PL7 30 29 PL6
VTG 32 31 GND
PM1 34 33 PM0
PM3 36 35 PM2
PM5 38 37 PM4
PM7 40 39 PM6
VTG 42 41 GND
PN1 44 43 PN0
PN3 46 45 PN2
PN5 48 47 PN4
PN7 50 49 PN6
VTG 52 51 GND
PP1 54 53 PP0 Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
8
PP3 56 55 PP2
PP5 58 57 PP4
PP7 60 59 PP6
VTG 62 61 GND
PQ1 64 63 PQ0
PQ3 66 65 PQ2
PQ5 68 67 PQ4
PQ7 70 69 PQ6
VBUST 72 71 DP
UVCON 74 73 DN
Vcc 76 75 UID
Vext 78 77 GND
TGT_PDATA1 80 79 TGT_PDATA0
TGT_PDATA3 82 81 TGT_PDATA2
TGT_PDATA5 84 83 TGT_PDATA4
TGT_PDATA7 86 85 TGT_PDATA6
TGT_PCTRL1 88 87 TGT_PCTRL0
TGT_PCTRL3 90 89 TGT_PCTRL2
TGT_PCTRL5 92 91 TGT_PCTRL4
TGT_PCTRL7 94 93 TGT_PCTRL6
BOARD_ID1 96 95 BOARD_ID0
BOARD_ID3 98 97 BOARD_ID2
BOARD_ID5 100 99 BOARD_ID4
1.3.1 Signal descriptions
Table 1-4. Socket card connector pin description.
Atmel STK600 signal name MCU Comment
PAx, PBx etc PAx, PBx etc 1-to-1 MCU pin mapping
VTG Vcc Target supply rail controlled by Atmel AVR Studio®
/ STK600
GND GND
AREFx AREF Analog reference voltage, controlled by AVR Studio / STK600
XTALx XTALx Clock pins connected to oscillator on STK600
TGT_SCK, TGT_MISO, TGT_MOSI ISP pins ISP programming interface
TGT_TDI, TGT_TDO, TGT_TMS,
TGT_TCK JTAG pins JTAG programming interface
VBUST VBUS VBUS (sense) for USB
UID UID ID pin for USB OTG
UVCON UVCON
USB VBUS generation control for USB OTG. A low level on this
signal enables VBUS generation
DP, DN DP, DN USB differential pair
TGT_PDATA(0-7) (HV) data pins Data pins for high voltage (PP/HVSP) programming Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
9
TGT_CTRL0 (HV) BS2
Control signals for High voltage Parallel Programming / Serial
Programming. Refer to AVR datasheet for further information.
On AVRs with common XA1/BS2, XA1 is used.
On AVRs with common BS1/PAGEL, BS1 is used.
TGT_CTRL1 (HV) Ready/Busy
TGT_CTRL2 (HV) /OE
TGT_CTRL3 (HV) /WR
TGT_CTRL4 (HV) BS1
TGT_CTRL5 (HV) XA0
TGT_CTRL6 (HV) XA1
TGT_CTRL7 (HV) PAGEL
BOARD_IDn none
ID system for router / socket / expansion cards, see Chapter 4 -
ID System
Notes: 1. Not all AVR will have every pin (ex. two aref pins, tosc or usb).
2. A MCU pin will fan-out to both Pnx pin and to the programming interface(s) located at that pin. Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
10
2. Socket Cards
Socket cards route each pin from the IC socket to separate pins on the spring loaded connectors on the bottom side,
facing the routing card.
2.1 Power design issues
As all routing is handled by the routing card, even power lines and power decoupling is ignored at the socket card. This
produces less than ideal power design, which may lead to unwanted noise, ground bounce, and other effects. It should
therefore be expected that heavily loaded designs cannot run at full speed on the Atmel STK600. Likewise, such power
design is not recommended for custom designs.
2.2 Connector MPN
Table 2-1. Socket card connector.
Manufacturer and MPN Quantity Comment
SAMTEC, FSI-140-03-G-D-AD 2 Spring loaded 80-pin connector
2.3 Physical dimensions and component placement
Figure 2-1. Socket card connector placement and dimensions.
ST1
J1 J2
45°
Note!
105mm
94mm
66mm
7mm
The board thickness should be 1.6mm to be compatible with the clips. Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
11
3. Expansion Cards
The Atmel STK600 features an expansion area where cards for custom peripherals like memory expansion, LCD etc
can be placed. STK600 routes all part pins and power to the expansion card connectors.
3.1 Connector MPN
Table 3-1. Expansion card connector.
Manufacturer and MPN Quantity Comment
FCI, 61082-101402LF 2 Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
12
3.2 Physical dimensions and component placement
Figure 3-1. Expansion card connector placement and dimensions.
There is no requirement to board thickness. Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
13
3.3 Atmel STK600 expansion connectors pinout
Figure 3-2. Pinout for expansion connectors.
Table 3-2. STK600 J301 “expand0” connector pinout.
Signal name Pin number Signal name
VTG 2 1 GND
PA1 4 3 PA0
PA3 6 5 PA2
PA5 8 7 PA4
PA7 10 9 PA6
VTG 12 11 GND
PB1 14 13 PB0
PB3 16 15 PB2
PB5 18 17 PB4
PB7 20 19 PB6
VTG 22 21 GND
PC1 24 23 PC0
PC3 26 25 PC2
PC5 28 27 PC4
PC7 30 29 PC6
VTG 32 31 GND
PD1 34 33 PD0 Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
14
PD3 36 35 PD2
PD5 38 37 PD4
PD7 40 39 PD6
VTG 42 41 GND
PE1 44 43 PE0
PE3 46 45 PE2
PE5 48 47 PE4
PE7 50 49 PE6
VTG 52 51 GND
PF1 54 53 PF0
PF3 56 55 PF2
PF5 58 57 PF4
PF7 60 59 PF6
VTG 62 61 GND
PG1 64 63 PG0
PG3 66 65 PG2
PG5 68 67 PG4
PG7 70 69 PG6
VTG 72 71 GND
PH1 74 73 PH0
PH3 76 75 PH2
PH5 78 77 PH4
PH7 80 79 PH6
VTG 82 81 GND
AREF0 84 83 XTAL1
AREF1 86 85 XTAL2
TGT_MOSI 88 87 GND
TGT_MISO 90 89 TOSC1
TGT_SCK 92 91 TOSC2
TDI 94 93 TGT_RESET
TDO 96 95 Vcc6
TMS 98 97 GND
TCK 100 99 Vcc6
Table 3-3. Atmel STK600 J302 “expand1” connector pinout.
Signal name Pin number Signal name
VTG 2 1 GND
PJ1 4 3 PJ0
PJ3 6 5 PJ2
PJ5 8 7 PJ4
PJ7 10 9 PJ6 Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
15
VTG 12 11 GND
PK1 14 13 PK0
PK3 16 15 PK2
PK5 18 17 PK4
PK7 20 19 PK6
VTG 22 21 GND
PL1 24 23 PL0
PL3 26 25 PL2
PL5 28 27 PL4
PL7 30 29 PL6
VTG 32 31 GND
PM1 34 33 PM0
PM3 36 35 PM2
PM5 38 37 PM4
PM7 40 39 PM6
VTG 42 41 GND
PN1 44 43 PN0
PN3 46 45 PN2
PN5 48 47 PN4
PN7 50 49 PN6
VTG 52 51 GND
PP1 54 53 PP0
PP3 56 55 PP2
PP5 58 57 PP4
PP7 60 59 PP6
VTG 62 61 GND
PQ1 64 63 PQ0
PQ3 66 65 PQ2
PQ5 68 67 PQ4
PQ7 70 69 PQ6
Vext 72 71 GND
Vext 74 73 GND
GND 76 75 Vcc
GND 78 77 Vcc
TGT_PDATA1 80 79 TGT_PDATA0
TGT_PDATA3 82 81 TGT_PDATA2
TGT_PDATA5 84 83 TGT_PDATA4
TGT_PDATA7 86 85 TGT_PDATA6
TGT_PCTRL1 88 87 TGT_PCTRL0
TGT_PCTRL3 90 89 TGT_PCTRL2
TGT_PCTRL5 92 91 TGT_PCTRL4 Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
16
TGT_PCTRL7 94 93 TGT_PCTRL6
Vcc3 96 95 GND
BOARD_ID1 98 97 BOARD_ID0
BOARD_ID7 100 99 BOARD_ID6 Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
17
4. ID System
The Atmel STK600 features an ID system to identify which routing, socket and expansion card is attached. The STK600
can impose voltage limitations based on the IDs, and Atmel AVR Studio will notify the user if the combination is
incorrect.
The ID system consists of two common output and two board unique input signals. Each input is one of sixteen possible
values based in the input signals – giving a total ID space of 256.
Three IDs are reserved for custom use and can be implemented without use of ICs.
Table 4-1. IDs reserved for custom use.
Type ID
Board limited to 1.8V 0xCA
Board limited to 3.3V 0xCC
No limit on voltage 0xCF
The ID 0xff indicates no board present.
4.1 Signal usage
Table 4-2. ID system signal usage.
Name Direction Function
BOARD_ID0 Output (A) Common output to functions
BOARD_ID1 Output (B) Common output to functions
BOARD_ID2 Input Input from routing card
BOARD_ID3 Input Input from routing card
BOARD_ID4 Input Input from socket card
BOARD_ID5 Input Input from socket card
BOARD_ID6 Input Input from expansion card
BOARD_ID7 Input Input from expansion card Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
18
4.2 ID functions
The functions and their output according to input A and B:
B A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Functions as logic expressions:
Function Expression ID
0 0 0x0
1 A + B 0x1
2 AB 0x2
3 B 0x3
4 AB 0x4
5 A 0x5
6 ⊕ BA 0x6
7 AB 0x7
8 AB 0x8
9 ⊕ BA 0x9
10 A 0xA
11 B + AB 0xB
12 B 0xC
13 B A⋅+ B 0xD
14 A + B 0xE
15 1 0xF Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
19
4.3 Examples
For a socket card to report the ID 0xCA:
Route BOARD_ID1 to BOARD_ID4 and BOARD_ID0 to BOARD_ID5
Figure 4-1. Socket card ID example.
For an expansion card to report the ID 0xCF:
Route BOARD_ID0 to BOARD_ID6 and VCC to BOARD_ID7
Figure 4-2. Expansion card ID example.
For a router card to report the ID 0xCC:
Route BOARD_ID1 to both BOARD_ID2 and BOARD_ID3.
Figure 4-3. Routing card ID example. Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
20
5. Design Example
To support a new package type one would typically start with designing the socket card. The pinout between the socket
card and routing card is not defined and left to the designer. An example is given in Figure 5-1.
Next is the design of the routing card (Figure 5-3). The routing card’s role is to connect each pin from the socket card to
the corresponding pin on the Atmel STK600. In addition to decoupling etc, the routing card should also fan-out the
correct signals to programming headers.
Each card in the stack has its own board_id pins; the routing card is responsible for passing on the signal to the socket
card.
Figure 5-1. Schema capture of socket card.
Both the socket and routing card must also include the clip holes:
Figure 5-2. Clip holes included in schematic. Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
21
Figure 5-3. Schema capture of routing card.
Copyright © 2008, Atmel Corporation Atmel AVR600: STK600 Expansion, Routing and Socket Boards [APPLICATION NOTE] 8170C−AVR−03/2013
22
6. Revision History
Doc. Rev. Date Comments
8170C 03/2013 Example schematics for the ID system are updated
8170B 12/2010
8170A 10/2008 Initial document release
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© 2013 Atmel Corporation. All rights reserved. / Rev.: 8170C−AVR−03/2013
Atmel®, Atmel logo and combinations thereof, AVR®, AVR Studio®, Enabling Unlimited Possibilities®, STK®, and others are registered trademarks or trademarks of
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automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
8159E–AVR–02/2013
Features
• High-performance, Low-power Atmel®AVR® 8-bit Microcontroller
• Advanced RISC Architecture
– 130 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16MIPS Throughput at 16MHz
– On-chip 2-cycle Multiplier
• High Endurance Non-volatile Memory segments
– 8KBytes of In-System Self-programmable Flash program memory
– 512Bytes EEPROM
– 1KByte Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85C/100 years at 25C(1)
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– Programming Lock for Software Security
• Atmel QTouch® library support
– Capacitive touch buttons, sliders and wheels
– Atmel QTouch and QMatrix acquisition
– Up to 64 sense channels
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
– Real Time Counter with Separate Oscillator
– Three PWM Channels
– 8-channel ADC in TQFP and QFN/MLF package
• Eight Channels 10-bit Accuracy
– 6-channel ADC in PDIP package
• Six Channels 10-bit Accuracy
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby
• I/O and Packages
– 23 Programmable I/O Lines
– 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF
• Operating Voltages
– 2.7 - 5.5V
– 0 - 16MHz
• Power Consumption at 4MHz, 3V, 25C
– Active: 3.6mA
– Idle Mode: 1.0mA
– Power-down Mode: 0.5µA
8-bit Atmel Microcontroller with 8KB In-System Programmable Flash
ATmega8AATmega8A [DATASHEET] 2
8159E–AVR–02/2013
1. Pin Configurations
Figure 1-1. Pinout ATmega8A
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
(INT1) PD3
(XCK/T0) PD4
GND
VCC
GND
VCC
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7
PC1 (ADC1)
PC0 (ADC0)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK)
32
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
(T1) PD5
(AIN0) PD6
(AIN1) PD7
(ICP1) PB0
(OC1A) PB1
(SS/OC1B) PB2
(MOSI/OC2) PB3
(MISO) PB4
PD2 (INT0)
PD1 (TXD)
PD0 (RXD)
PC6 (RESET)
PC5 (ADC5/SCL)
PC4 (ADC4/SDA)
PC3 (ADC3)
PC2 (ADC2)
TQFP Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
(RESET) PC6
(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3
(XCK/T0) PD4
VCC
GND
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7
(T1) PD5
(AIN0) PD6
(AIN1) PD7
(ICP1) PB0
PC5 (ADC5/SCL)
PC4 (ADC4/SDA)
PC3 (ADC3)
PC2 (ADC2)
PC1 (ADC1)
PC0 (ADC0)
GND
AREF
AVCC
PB5 (SCK)
PB4 (MISO)
PB3 (MOSI/OC2)
PB2 (SS/OC1B)
PB1 (OC1A)
PDIP
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
MLF Top View
(INT1) PD3
(XCK/T0) PD4
GND
VCC
GND
VCC
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7
PC1 (ADC1)
PC0 (ADC0)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK)
(T1) PD5
(AIN0) PD6
(AIN1) PD7
(ICP1) PB0
(OC1A) PB1
(SS/OC1B) PB2
(MOSI/OC2) PB3
(MISO) PB4
PD2 (INT0)
PD1 (TXD)
PD0 (RXD)
PC6 (RESET)
PC5 (ADC5/SCL)
PC4 (ADC4/SDA)
PC3 (ADC3)
PC2 (ADC2)
NOTE:
The large center pad underneath the MLF
packages is made of metal and internally
connected to GND. It should be soldered
or glued to the PCB to ensure good
mechanical stability. If the center pad is
left unconneted, the package might
loosen from the PCB.ATmega8A [DATASHEET] 3
8159E–AVR–02/2013
2. Overview
The Atmel®AVR® ATmega8A is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By
executing powerful instructions in a single clock cycle, the ATmega8A achieves throughputs approaching 1 MIPS
per MHz, allowing the system designer to optimize power consumption versus processing speed.
2.1 Block Diagram
Figure 2-1. Block Diagram
INTERNAL
OSCILLATOR
OSCILLATOR
WATCHDOG
TIMER
MCU CTRL.
& TIMING
OSCILLATOR
TIMERS/
COUNTERS
INTERRUPT
UNIT
STACK
POINTER
EEPROM
SRAM
STATUS
REGISTER
USART
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
PROGRAMMING
LOGIC SPI
ADC
INTERFACE
COMP.
INTERFACE
PORTC DRIVERS/BUFFERS
PORTC DIGITAL INTERFACE
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
+
-
PORTB DRIVERS/BUFFERS
PORTB DIGITAL INTERFACE
PORTD DIGITAL INTERFACE
PORTD DRIVERS/BUFFERS
XTAL1
XTAL2
CONTROL
LINES
VCC
GND
MUX &
ADC
AGND
AREF
PC0 - PC6 PB0 - PB7
PD0 - PD7
AVR CPU
TWI
RESETATmega8A [DATASHEET] 4
8159E–AVR–02/2013
The Atmel®AVR® AVR core combines a rich instruction set with 32 general purpose working registers. All the 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be
accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient
while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega8A provides the following features: 8K bytes of In-System Programmable Flash with Read-WhileWrite
capabilities, 512 bytes of EEPROM, 1K byte of SRAM, 23 general purpose I/O lines, 32 general purpose
working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable
USART, a byte oriented Two-wire Serial Interface, a 6-channel ADC (eight channels in TQFP and
QFN/MLF packages) with 10-bit accuracy, a programmable Watchdog Timer with Internal Oscillator, an SPI serial
port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM,
Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register
contents but freezes the Oscillator, disabling all other chip functions until the next Interrupt or Hardware Reset. In
Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the
rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous
timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the
crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined
with low-power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The Flash Program memory
can be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory
programmer, or by an On-chip boot program running on the AVR core. The boot program can use any interface to
download the application program in the Application Flash memory. Software in the Boot Flash Section will continue
to run while the Application Flash Section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel
ATmega8A is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded
control applications.
The Atmel AVR ATmega8A is supported with a full suite of program and system development tools, including C
compilers, macro assemblers, program simulators and evaluation kits.
2.2 Pin Descriptions
2.2.1 VCC
Digital supply voltage.
2.2.2 GND
Ground.
2.2.3 Port B (PB7:PB0) – XTAL1/XTAL2/TOSC1/TOSC2
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers
have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator amplifier and
input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator amplifier.
If the Internal Calibrated RC Oscillator is used as chip clock source, PB7:6 is used as TOSC2:1 input for the Asynchronous
Timer/Counter2 if the AS2 bit in ASSR is set.ATmega8A [DATASHEET] 5
8159E–AVR–02/2013
The various special features of Port B are elaborated in “Alternate Functions of Port B” on page 56 and “System
Clock and Clock Options” on page 24.
2.2.4 Port C (PC5:PC0)
Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers
have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
2.2.5 PC6/RESET
If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6 differ
from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer than the
minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given in
Table 26-3 on page 228. Shorter pulses are not guaranteed to generate a Reset.
The various special features of Port C are elaborated on page 59.
2.2.6 Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers
have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the ATmega8A as listed on page 61.
2.2.7 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock
is not running. The minimum pulse length is given in Table 26-3 on page 228. Shorter pulses are not guaranteed to
generate a reset.
2.2.8 AVCC
AVCC is the supply voltage pin for the A/D Converter, Port C (3:0), and ADC (7:6). It should be externally connected
to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter.
Note that Port C (5:4) use digital supply voltage, VCC.
2.2.9 AREF
AREF is the analog reference pin for the A/D Converter.
2.2.10 ADC7:6 (TQFP and QFN/MLF Package Only)
In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered
from the analog supply and serve as 10-bit ADC channels.ATmega8A [DATASHEET] 6
8159E–AVR–02/2013
3. Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
http://www.atmel.com/avr.
Note: 1.
4. Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20
years at 85°C or 100 years at 25°C.
5. About Code Examples
This datasheet contains simple code examples that briefly show how to use various parts of the device. These
code examples assume that the part specific header file is included before compilation. Be aware that not all C
compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent.
Please confirm with the C compiler documentation for more details.
6. Capacitive touch sensing
The Atmel® QTouch® Library provides a simple to use solution to realize touch sensitive interfaces on most Atmel
AVR® microcontrollers. The QTouch Library includes support for the QTouch and QMatrix® acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR Microcontroller.
This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the
touch sensing API’s to retrieve the channel information and determine the touch sensor states.
The QTouch Library is FREE and downloadable from the Atmel website at the following location:
www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch Library
User Guide - also available for download from the Atmel website.ATmega8A [DATASHEET] 7
8159E–AVR–02/2013
7. AVR CPU Core
7.1 Overview
This section discusses the Atmel®AVR® core architecture in general. The main function of the CPU core is to
ensure correct program execution. The CPU must therefore be able to access memories, perform calculations,
control peripherals, and handle interrupts.
Figure 7-1. Block Diagram of the AVR MCU Architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories
and buses for program and data. Instructions in the Program memory are executed with a single level pipelining.
While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept
enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable
Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle
access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands
are output from the Register File, the operation is executed, and the result is stored back in the Register File
– in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing –
enabling efficient address calculations. One of the these address pointers can also be used as an address pointer
for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register,
described later in this section.
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
Direct Addressing
Indirect Addressing
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
i/O Module 2
i/O Module1
i/O Module nATmega8A [DATASHEET] 8
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The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single
register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated
to reflect information about the result of the operation.
The Program flow is provided by conditional and unconditional jump and call instructions, able to directly address
the whole address space. Most AVR instructions have a single 16-bit word format. Every Program memory
address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot program section and the Application program
section. Both sections have dedicated Lock Bits for write and read/write protection. The SPM instruction that writes
into the Application Flash memory section must reside in the Boot program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack
is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total
SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines
or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O space. The data
SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in
the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have
priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the
priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other
I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register
File, 0x20 - 0x5F.
7.2 Arithmetic Logic Unit – ALU
The high-performance Atmel®AVR® ALU operates in direct connection with all the 32 general purpose working registers.
Within a single clock cycle, arithmetic operations between general purpose registers or between a register
and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical,
and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both
signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.
7.3 Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction. This
information can be used for altering program flow in order to perform conditional operations. Note that the Status
Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases
remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when returning
from an interrupt. This must be handled by software.
7.3.1 SREG – The AVR Status Register
Bit 7 6 5 4 3 2 1 0
I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0ATmega8A [DATASHEET] 9
8159E–AVR–02/2013
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control
is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts
are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an
interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set
and cleared by the application with the SEI and CLI instructions, as described in the Instruction Set Reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated
bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be
copied into a bit in a register in the Register File by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic.
See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See
the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description”
for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for
detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a Carry in an arithmetic or logic operation. See the “Instruction Set Description” for
detailed information.
7.4 General Purpose Register File
The Register File is optimized for the Atmel®AVR® Enhanced RISC instruction set. In order to achieve the required
performance and flexibility, the following input/output schemes are supported by the Register File:
• One 8-bit output operand and one 8-bit result input.
• Two 8-bit output operands and one 8-bit result input.
• Two 8-bit output operands and one 16-bit result input.
• One 16-bit output operand and one 16-bit result input.
Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU.ATmega8A [DATASHEET] 10
8159E–AVR–02/2013
Figure 7-2. AVR CPU General Purpose Working Registers
Most of the instructions operating on the Register File have direct access to all registers, and most of them are single
cycle instructions.
As shown in Figure 7-2, each register is also assigned a Data memory address, mapping them directly into the first
32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory
organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set to
index any register in the file.
7.4.1 The X-register, Y-register and Z-register
The registers R26:R31 have some added functions to their general purpose usage. These registers are 16-bit
address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y and Z are
defined as described in Figure 7-3.
Figure 7-3. The X-, Y- and Z-Registers
In the different addressing modes these address registers have functions as fixed displacement, automatic increment,
and automatic decrement (see the Instruction Set Reference for details).
7.5 Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses
after interrupts and subroutine calls. Note that the Stack is implemented as growing from higher to lower memory
7 0 Addr.
R0 0x00
R1 0x01
R2 0x02
…
R13 0x0D
General R14 0x0E
Purpose R15 0x0F
Working R16 0x10
Registers R17 0x11
…
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte
15 XH XL 0
X-register 7 0 7 0
R27 (0x1B) R26 (0x1A)
15 YH YL 0
Y-register 7 0 7 0
R29 (0x1D) R28 (0x1C)
15 ZH ZL 0
Z-register 7 0 7 0
R31 (0x1F) R30 (0x1E)ATmega8A [DATASHEET] 11
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locations. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer points to the data
SRAM Stack area where the Subroutine and Interrupt Stacks are located. A Stack PUSH command will decrease
the Stack Pointer.
The Stack in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts
are enabled. Initial Stack Pointer value equals the last address of the internal SRAM and the Stack Pointer must be
set to point above start of the SRAM, see Figure 8-2 on page 16.
See Table 7-1 for Stack Pointer details.
The Atmel®AVR® Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually
used is implementation dependent. Note that the data space in some implementations of the AVR architecture is
so small that only SPL is needed. In this case, the SPH Register will not be present.
7.5.1 SPH and SPL – Stack Pointer High and Low Register
7.6 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The Atmel®AVR®CPU is
driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock
division is used.
Figure 7-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture
and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with
the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
Table 7-1. Stack Pointer instructions
Instruction Stack pointer Description
PUSH Decremented by 1 Data is pushed onto the stack
CALL
ICALL
RCALL
Decremented by 2 Return address is pushed onto the stack with a subroutine call or
interrupt
POP Incremented by 1 Data is popped from the stack
RET
RETI
Incremented by 2 Return address is popped from the stack with return from
subroutine or return from interrupt
Bit 15 14 13 12 11 10 9 8
SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
00000000ATmega8A [DATASHEET] 12
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Figure 7-4. The Parallel Instruction Fetches and Instruction Executions
Figure 7-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using
two register operands is executed, and the result is stored back to the destination register.
Figure 7-5. Single Cycle ALU Operation
7.7 Reset and Interrupt Handling
The Atmel®AVR® provides several different interrupt sources. These interrupts and the separate Reset Vector
each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable
bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to
enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when
Boot Lock Bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory
Programming” on page 207 for details.
The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors.
The complete list of Vectors is shown in “Interrupts” on page 44. The list also determines the priority levels of the
different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next
is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the boot Flash section
by setting the Interrupt Vector Select (IVSEL) bit in the General Interrupt Control Register (GICR). Refer to
“Interrupts” on page 44 for more information. The Reset Vector can also be moved to the start of the boot Flash
section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming”
on page 194.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software
can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current
interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For
these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clkCPUATmega8A [DATASHEET] 13
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handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing
a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding
interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the
flag is cleared by software. Similarly, if one or more interrupt conditions occur while the global interrupt enable bit is
cleared, the corresponding Interrupt Flag(s) will be set and remembered until the global interrupt enable bit is set,
and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily
have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will
not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction
before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when
returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be
executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example
shows how this can be used to avoid interrupts during the timed EEPROM write sequence.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending
interrupts, as shown in the following example.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMWE ; start EEPROM write
sbi EECR, EEWE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<