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Farnell PDF
Atmel AT42QT1070 Datasheet - Farnell Element 14
Atmel AT42QT1070 Datasheet - Farnell Element 14
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Farnell Element 14 :
See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…
Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.
Puce électronique / Microchip :
Sans fil - Wireless :
Texas instrument :
Ordinateurs :
Logiciels :
Tutoriels :
Autres documentations :
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9596C–AT42–05/2013
Features
Configurations:
Comms mode
Standalone mode
Number of Keys:
Comms mode: 1 – 7 keys (or 1 – 6 keys plus a Guard Channel)
Standalone mode: 1 – 4 keys plus a fixed Guard Channel on key 0
Number of I/O Lines:
Standalone mode: 5 outputs
Technology:
Patented spread-spectrum charge-transfer
Key Outline Sizes:
6 mm x 6 mm or larger (panel thickness dependent); widely different sizes and
shapes possible
Layers Required:
One
Electrode Materials:
Etched copper; Silver; Carbon; Indium Tin Oxide (ITO)
Panel Materials:
Plastic; Glass; Composites; Painted surfaces (low particle density metallic
paints possible
Panel Thickness:
Up to 10 mm glass; Up to 5 mm plastic (electrode size dependent)
Key Sensitivity:
Comms mode: individually settable via simple commands over I2
C-compatible
interface
Standalone mode: settings are fixed
Interface:
I
2
C-compatible slave mode (400 kHz). Discrete detection outputs
Signal Processing:
Self-calibration
Auto drift compensation
Noise filtering
Adjacent Key Suppression® (AKS®) – up to three groups possible
Power:
1.8 V – 5.5 V
Package:
14-pin SOIC RoHS compliant IC
20-pin VQFN RoHS compliant IC
Atmel AT42QT1070
Seven-channel QTouch® Touch Sensor IC
DATASHEETAT42QT1070 [DATASHEET] 2
9596C–AT42–05/2013
1. Pinouts and Schematics
1.1 Pinout Configuration – Comms Mode (14-pin SOIC)
1.2 Pinout Configuration – Standalone Mode (14-pin SOIC)
VDD
MODE (Vss)
RESET
SDA
CHANGE
KEY2
KEY1
KEY0
1
2
3
4
5
6
7 8
9
10
11
12
13
14
QT1070
SCL
KEY6
KEY3
VSS
KEY5
KEY4
VDD
MODE (Vdd)
RESET
OUT0
OUT4
KEY2
KEY1
KEY0
1
2
3
4
5
6
7 8
9
10
11
12
13
14
QT1070
OUT3
OUT2
KEY3
VSS
OUT1
KEY4AT42QT1070 [DATASHEET] 3 9596C–AT42–05/2013
1.3 Pinout Configuration – Comms Mode (20-pin VQFN)
1.4 Pinout Configuration – Standalone Mode (20-pin VQFN) NCNC VSS VDDNC
KEY4
KEY3
KEY2
KEY1
KEY0 MODE (Vss)
SDA
1
2
3
4
5 11
12
13
14
15
20 19 18 17 16
6 7 8 9 10
QT1070 RESET
CHANGE
SCL
NC
NC
NC
KEY5
KEY6
NC
NC
VSS
VDD
NC
KEY4
KEY3
KEY2
KEY1
KEY0 MODE (Vdd)
OUT0
1
2
3
4
5 11
12
13
14
15
20 19 18 17 16
6 7 8 9 10
QT1070 RESET
OUT4
OUT3
NC
NC
NC
OUT1
OUT2AT42QT1070 [DATASHEET] 4
9596C–AT42–05/2013
1.5 Pin Descriptions
I Input only O Output only, push-pull
OD Open drain output P Ground or power
Table 1-1. Pin Listings (14-pin SOIC)
Pin
Name
(Comms
Mode)
Name
(Standalone
Mode) Type Description
If Unused,
Connect
To...
1 VDD VDD P Power –
2 MODE MODE I
Mode selection pin
Comms Mode – connect to Vss
Standalone Mode – connect to Vdd
–
3 SDA OUT0 OD
Comms Mode – I2
C data line
Standalone Mode – open drain output for guard
channel
Open
4 RESET RESET I RESET – has internal pull-up 60 k resistor Open
5 CHANGE OUT4 OD
CHANGE line for controlling the communications
flow
Comms Mode – connect to CHANGE line
Standalone Mode – connect to output
Open
6 SCL OUT3 OD
Comms Mode – connect to I
2
C clock
Standalone Mode – connect to output Open
7 KEY6 OUT2 O/OD
Comms Mode – connect to Key 6
Standalone Mode – connect to output Open
8 KEY5 OUT1 O/OD
Comms Mode – connect to Key 5
Standalone Mode – connect to output Open
9 KEY4 KEY4 O Key 4 Open
10 KEY3 KEY3 O Key 3 Open
11 KEY2 KEY2 O Key 2 Open
12 KEY1 KEY1 O Key 1 Open
13 KEY0 KEY0 O Key 0 Open
14 VSS VSS P Ground –AT42QT1070 [DATASHEET] 5 9596C–AT42–05/2013
I Input only O Output only, push-pull
OD Open drain output P Ground or power
Table 1-2. Pin Listings (20-pin VQFN)
Pin
Name
(Comms
Mode)
Name
(Standalone
Mode) Type Description
If Unused,
Connect
To...
1 KEY4 KEY4 O Key 4 Open
2 KEY3 KEY3 O Key 3 Open
3 KEY2 KEY2 O Key 2 Open
4 KEY1 KEY1 O Key 1 Open
5 KEY0 KEY0 O Key 0 Open
6 NC NC – Not connected –
7 NC NC – Not connected –
8 VSS VSS P Ground –
9 VDD VDD P Power –
10 NC NC – Not connected –
11 MODE MODE I
Mode selection pin
Comms Mode – connect to Vss
Standalone Mode – connect to Vdd
–
12 SDA OUT0 OD
Comms Mode – I2
C data line
Standalone Mode – open drain output for
guard channel
Open
13 RESET RESET I RESET – has internal pull-up 60 k resistor Open
14 CHANGE OUT4 OD
CHANGE line for controlling the communications
flow
Comms Mode – connect to CHANGE line
Standalone Mode – connects to output
Open
15 SCL OUT3 OD
Comms Mode – connect to I
2
C clock
Standalone Mode – connect to output Open
16 KEY6 OUT2 O/OD
Comms Mode – connect to Key 6
Standalone Mode – connect to output Open
17 KEY5 OUT1 O/OD
Comms Mode – connect to Key 5
Standalone Mode – connect to output Open
18 NC NC – Not connected –
19 NC NC – Not connected –
20 NC NC – Not connected –AT42QT1070 [DATASHEET] 6
9596C–AT42–05/2013
1.6 Schematics
Figure 1-1. Typical Circuit – Comms (14-pin SOIC)
Figure 1-2. Typical Circuit – Standalone (14-pin SOIC)
Rs6
C1
K4
RSCL
Rs5
Rs4
Rs3
Rs2
Rs1
K3
K2
K1
1
QT1070
MODE (Vss)
2
SDA 3
RESET 4
CHANGE 5
SCL 6
KEY6 7
KEY5 8
KEY4 9
KEY3 10
KEY2 11
KEY1 12
KEY0 13
14
Vss
Rs0 K0
Vss
Vdd
CHANGE
SDA
RESET
K5
K6
Vdd
SCL
Vdd
Vss
RSDA
Vdd
RCHG RRST
ROUT2
C1
K4
ROUT3
ROUT1
Rs4
Rs3
Rs2
Rs1
K3
K2
K1
1
OUT0 3
RESET 4
OUT4 5
OUT3 6
OUT2 7
OUT1 8
KEY4 9
KEY3 10
KEY2 11
KEY1 12
KEY0 13
Vss
Rs0 K0
Vss
ROUT4
Vdd
RESET
COUT1
COUT2
COUT3
Vss
COUT4
COUT0
14
Vss
QT1070
Vdd
Vss
OUTPUTS
OUTPUTS
ROUT0
MODE (Vdd)
2
COUT1, 2 3 and are optional
COUT0 4 and are optional
R1
VddAT42QT1070 [DATASHEET] 7 9596C–AT42–05/2013
Figure 1-3. Typical Circuit – Comms (20-pin VQFN)
Figure 1-4. Typical Circuit – Standalone (20-pin VQFN)
For component values in Figure 1-1, 1-2, 1-3, and 1-4, check the following sections:
Section 3.1 on page 12: Series resistors (Rs0 – Rs6 for comms mode and Rs0 – Rs4 for standalone mode)
Section 3.2 on page 12: LED traces
Section 3.4 on page 12: Power Supply (voltage levels)
Section 4.4 on page 14: SDA, SCL pull-up resistors
Rs6
C1
K4
Rs5
Rs4
Rs3
Rs2
Rs1
K3
K2
K1
9
QT1070
SCL 15
SDA 12
RESET 13
CHANGE 14 KEY6 16
KEY5 17
KEY4 1
KEY3 2
KEY2 3
KEY1 4
KEY0 5
8
Vss
Rs0 K0
Vss
Vdd
K5
K6
RSCL
Vdd Vdd
Vss
11
MODE (Vss)
N/C
N/C 18
N/C 19
N/C 20
N/C 7
N/C 6
10
CHANGE
SDA
RESET
RSDA
Vdd
RCHG RRST
RsOUT2
K4
RsOUT3
RLOUT1
Rs4
Rs3
Rs2
Rs1
K3
K2
K1
OUT0 12
RESET 13
OUT4 14
OUT3 15
OUT2 16
OUT1 17
KEY4 1
KEY3 2
KEY2 3
KEY1
KEY0 5
Vss
Rs0 K0
ROUT4
RESET
COUT1
COUT2
COUT3
Vss
COUT4
COUT0
8
QT1070
Vss
OUTPUTS
OUTPUTS
N/C
N/C 18
N/C 19
N/C 20
N/C 7
N/C 6
10
4
ROUT0
Vss
C1
9 Vss
Vdd
MODE (Vdd) Vdd
11
COUT1, 2 3 and are optional
COUT0 4 and are optional
R1
VddAT42QT1070 [DATASHEET] 8
9596C–AT42–05/2013
2. Overview
2.1 Introduction
The AT42QT1070 (QT1070) is a digital burst mode charge-transfer (QT™) capacitive sensor driver. The device can
sense from one to seven keys, dependent on mode.
The QT1070 includes all signal processing functions necessary to provide stable sensing under a wide variety of
changing conditions, and the outputs are fully debounced. Only a few external parts are required for operation and
no external Cs capacitors are required.
The QT1070 modulates its bursts in a spread-spectrum fashion in order to heavily suppress the effects of external
noise, and to suppress RF emissions. The QT1070 uses a dual-pulse method of acquisition. This provides greater
noise immunity and eliminates the need for external sampling capacitors, allowing touch sensing using a single pin.
2.2 Modes
2.2.1 Comms Mode
The QT1070 can operate in comms mode where a host can communicate with the device via an I2
C bus. This allows
the user to configure settings for Threshold, Adjacent Key Suppression (AKS), Detect Integrator, Low Power (LP)
Mode, Guard Channel and Max Time On for keys.
2.2.2 Standalone Mode
The QT1070 can operate in a standalone mode where an I2
C interface is not required. To enter standalone mode,
connect the Mode pin to Vdd before powering up the QT1070.
In standalone mode, the start-up values are hard coded in firmware and cannot be changed. The default start-up
values are used. This means that key detection is reported via their respective IOs. The Guard channel feature is
automatically implemented on key 0 in standalone mode. This means that this channel gets priority over all other
keys going into touch.
2.3 Keys
Dependent on mode, the QT1070 can have a minimum of one key and a maximum of seven keys. These can be
constructed in different shapes and sizes. See “Features” on page 1 for the recommended dimensions.
Comms mode – 1 to 7 keys (or 1 to 6 keys plus Guard Channel)
Standalone mode – 1 to 4 keys plus a Guard Channel
Unused keys should be disabled by setting the averaging factor to zero (see Section 5.9 on page 18).
The status register can be read to determine the touch status of the corresponding key. It is recommended using the
open-drain CHANGE line to detect when a change of status has occurred.
2.4 Input/Output (IO) Lines
There are no IO lines in comms mode.
In Standalone mode pins OUT0 – OUT4 can be used as open drain outputs for driving LEDs.
2.5 Acquisition/Low Power Mode (LP)
There are 255 different acquisition times possible. These are controlled via the LP mode byte (see Section 5.11 on
page 19) which can be written to via I2
C communication.
LP mode controls the intervals between acquisition measurements. Longer intervals consume lower power but have
an increased response time. During calibration, touch and during the detect integrator (DI) period, the LP mode is
temporarily set to LP mode 1 for a faster response.AT42QT1070 [DATASHEET] 9 9596C–AT42–05/2013
The QT1070 operation is based on a fixed cycle time of approximately 8 ms. The LP mode setting indicates how
many of these periods exist per measurement cycle. For example, If LP mode = 1, there is an acquisition every cycle
(8 ms). If LP mode = 3, there is an acquisition every 3 cycles (24 ms). If a high Averaging Factor (see Section 5.9 on
page 18) setting is selected then the acquisition time may exceed 8 ms.
LP settings above mode 32 (256 ms) result in slower thermal drift compensation and should be avoided in
applications where fast thermal transients occur.
2.6 Adjacent Key Suppression (AKS) Technology
The device includes the Atmel-patented Adjacent Key Suppression (AKS) technology, to allow the use of tightly
spaced keys on a keypad with no loss of selectability by the user.
There can be up to three AKS groups, implemented so that only one key in the group may be reported as being
touched at any one time. Once a key in a particular AKS group is in detect no other key in that group can go into
detect. Only when the key in detect goes out of detection can another key go into detect state.
The keys which are members of the AKS groups can be set (see Section 5.9 on page 18). Keys outside the group
may be in detect simultaneously.
2.7 CHANGE Line (Comms Mode Only)
The CHANGE line is active low and signals when there is a change of state in the Detection or Input key status
bytes. It is cleared (allowed to float high) when the host reads the status bytes.
If the status bytes change back to their original state before the host has read the status bytes (for example, a touch
followed by a release), the CHANGE line will be held low. In this case, a read to any memory location will clear the
CHANGE line.
The CHANGE line is open-drain and should be connected via a 47 k resistor to Vdd. It is necessary for minimum
power operation as it ensures that the QT1070 can sleep for as long as possible. Communications wake up the
QT1070 from sleep causing a higher power consumption if the part is randomly polled.
Note: The CHANGE line is pulled low 100 ms after power-up or reset.
2.8 Types of Reset
2.8.1 External Reset
An external reset logic line can be used if desired, fed into the RESET pin. However, under most conditions it is
acceptable to tie RESET to Vdd.
2.8.2 Soft Reset
The host can cause a device reset by writing a nonzero value to the RESET byte. This soft reset triggers the internal
watchdog timer on a 125 ms interval. After 125 ms the device resets and wakes again.
The device NACKs any attempts to communicate with it during the first 30 ms of its initialization period.
2.9 Calibration
Writing a non-zero value to the calibration byte can force a recalibration at any time. This can be useful to clear out a
stuck key condition after a prolonged period of uninterrupted detection.
Note: A calibrate command clears all key status bits and the overflow bit (until it is checked on the next cycle).AT42QT1070 [DATASHEET] 10
9596C–AT42–05/2013
2.10 Guard Channel
A guard channel to help prevent false detection is available in both modes. This is fixed on key 0 for standalone
mode and programmable for comms mode.
Guard channel keys should be more sensitive than the other keys (physically bigger). Because the guard channel
key is physically bigger it becomes more susceptible to noise so it has a higher Averaging Factor (see Section 5.9 on
page 18) and a lower Threshold (see Section 5.8 on page 18) than the other keys. In standalone mode it has an
Averaging Factor of 16 and a Threshold of 10 counts.
A channel set as the guard channel (there can only be one) is prioritised when the filtering of keys going into detect
is taking place. So if a normal key is filtering into touch (touch present but DI has not been reached) and the key set
as the guard key begins filtering in, then the normal key’s filter is reset and the guard key filters in first.
The guard channel is connected to a sensor pad which detects the presence of touch and overrides any output from
the other keys.
Figure 2-1. Guard Channel Example
2.11 Signal Processing
2.11.1 Detect Threshold
The device detects a touch when the signal has crossed a threshold level and remained there for a specified number
of counts (see Section 5.10 on page 19). This can be altered on a key-by-key basis using the key threshold I2C
commands.
In standalone mode the detect threshold is set to a fixed value of 10 counts of change with respect to the internal
reference level for the guard channel and 20 counts for the other four keys. The reference level has the ability to
adjust itself slowly in accordance with the drift compensation mechanism.
The drift mechanism will drift toward touch at a rate of 160 ms × 18 = 2.88 seconds and away from touch at a rate of
160 ms × 6 = 0.96 seconds. The 160 ms is based on 20 × 8 ms cycles. If the cycle time exceeds 8 ms then the
overall times will be extended to match.
2.11.2 Detect Integrator
The device features a fast detection integrator counter (DI filter), which acts to filter out noise at the small expense of
a slower response time. The DI filter requires a programmable number of consecutive samples confirmed in
detection before the key is declared to be touched. The minimum number for the DI filter is 2. Settings of 0 and 1 for
the DI also default to 2.
The DI is also implemented when a touch is removed. This uses the Fast Out DI option. When bit 5 of Address 53 is
set the a key filters out with an integrator of 4.
Guard channelAT42QT1070 [DATASHEET] 11 9596C–AT42–05/2013
2.11.3 Cx Limitations
The recommended range for key capacitance Cx is 1 pF – 30 pF. Larger values of Cx will give reduced sensitivity.
2.11.4 Max On Duration
If an object or material obstructs the sense pad the signal may rise enough to create a detection, preventing further
operation. To prevent this, the sensor includes a timer which monitors detections. If a detection exceeds the timer
setting the sensor performs a key recalibration. This is known as the Max On duration feature and is set to
approximately 30 s in standalone mode.
In comms mode this feature can be changed by setting a value in the range 1 – 255
(160 ms – 40,800 ms) in steps of 160 ms. A setting of 0 disables the Max On Duration recalibration feature.
Note: If bit 4 of address 53 is clear then a recalibration of all keys occurs on Max On Duration, otherwise individual
key recalibration occurs.
2.11.5 Positive Recalibration
If a keys signal jumps in the negative direction (with respect to its reference) by more than the Positive Recalibration
setting (4 counts), then a recalibration of that key takes place.
2.11.6 Drift Hold Time
Drift Hold Time (DHT) is used to restrict drift on all keys while one or more keys are activated. DHT restricts the
drifting on all keys until approximately four seconds after all touches have been removed.
This feature is particularly useful in cases of high-density keypads where touching a key or hovering a finger over the
keypad would cause untouched keys to drift, and therefore create a sensitivity shift, and ultimately inhibit touch
detection.
2.11.7 Hysteresis
Hysteresis is fixed at 12.5% of the Detect Threshold. When a key enters a detect state once the DI count has been
reached, the NTHR value is changed by a small amount (12.5% of NTHR) in the direction away from touch. This is
done to affect hysteresis and so makes it less likely a key will dither in and out of detect. NTHR is restored once the
key drops out of detect.+AT42QT1070 [DATASHEET] 12
9596C–AT42–05/2013
3. Wiring and Parts
3.1 Rs Resistors
Series resistors Rs (Rs0 – Rs6 for comms mode and Rs0 – Rs4 for standalone mode) are in line with the electrode
connections and should be used to limit electrostatic discharge (ESD) currents and to suppress radio frequency
interference (RFI). Series resistors are recommended for noise reduction. They should be approximately 4.7 k to
20 k each.
3.2 LED Traces and Other Switching Signals
Digital switching signals near the sense lines induce transients into the acquired signals, deteriorating the signal-tonoise
(SNR) performance of the device. Such signals should be routed away from the sensing traces and electrodes,
or the design should be such that these lines are not switched during the course of signal acquisition (bursts).
LED terminals which are multiplexed or switched into a floating state, and which are within, or physically very near, a
key (even if on another nearby PCB) should be bypassed to either Vss or Vdd with at least a 10 nF capacitor. This is
to suppress capacitive coupling effects which can induce false signal shifts. The bypass capacitor does not need to
be next to the LED, in fact it can be quite distant. The bypass capacitor is noncritical and can be of any type.
LED terminals which are constantly connected to Vss or Vdd do not need further bypassing.
3.3 PCB Cleanliness
Modern no-clean flux is generally compatible with capacitive sensing circuits.
If a PCB is reworked in any way, clean it thoroughly to remove all traces of the flux residue around the capacitive
sensor components. Dry it thoroughly before any further testing is conducted.
3.4 Power Supply
See Section 6.2 on page 22 for the power supply range. If the power supply fluctuates slowly with temperature, the
device tracks and compensates for these changes automatically with only minor changes in sensitivity. If the supply
voltage drifts or shifts quickly, the drift compensation mechanism is not able to keep up, causing sensitivity
anomalies or false detections.
The usual power supply considerations with QT parts apply to the device. The power should be clean and come from
a separate regulator if possible. However, this device is designed to minimize the effects of unstable power, and
except in extreme conditions should not require a separate Low Dropout (LDO) regulator.
It is assumed that a larger bypass capacitor (such as1 µF) is somewhere else in the power circuit; for example, near
the regulator.
CAUTION: If a PCB is reworked in any way, it is highly likely that the behavior of the
no-clean flux will change. This can mean that the flux changes from an inert material
to one that can absorb moisture and dramatically affect capacitive measurements
due to additional leakage currents. If so, the circuit can become erratic and exhibit
poor environmental stability.
CAUTION: A regulator IC shared with other logic can result in erratic operation and is
not advised.
A single ceramic 0.1 µF bypass capacitor, with short traces, should be placed very
close to the power pins of the IC. Failure to do so can result in device oscillation, high
current consumption and erratic operation.AT42QT1070 [DATASHEET] 13 9596C–AT42–05/2013
4. I2
C Communications (Comms Mode Only)
4.1 I2
C Protocol
4.1.1 Protocol
The I2C protocol is based around access to an address table (see Table 5-1 on page 15) and supports multibyte
reads and writes. The maximum clock rate is 400 kHz.
See Section A. on page 29 for an overview of I2
C bus operation.
4.1.2 Signals
The I2
C interface requires two signals to operate:
SDA - Serial Data
SCL - Serial Clock
A third line, CHANGE, is used to signal when the device has seen a change in the status byte:
CHANGE: Open-drain, active low when any capacitive key has changed state since the last I2
C read. After reading
the two status bytes, this pin floats (high) again if it is pulled up with an external resistor. If the status bytes change
back to their original state before the host has read the status bytes (for example, a touch followed by a release), the
CHANGE line is held low. In this case, a read to any memory location clears the CHANGE line.
4.2 I2
C Address
There is one preset I2
C address of 0x1B. This is not changeable.
4.3 Data Read/Write
4.3.1 Writing Data to the Device
The sequence of events required to write data to the device is shown next.
1. The host initiates the transfer by sending the START condition
2. The host follows this by sending the slave address of the device together with the WRITE bit.
3. The device sends an ACK.
Table 4-1. Description of Write Data Bits
Key Description
S START condition
SLA+W Slave address plus write bit
A Acknowledge bit
MemAddress Target memory address within device
Data Data to be written
P Stop condition
S SLA+W A A MemAddress Data A P
Host to Device Device Tx to HostAT42QT1070 [DATASHEET] 14
9596C–AT42–05/2013
4. The host then sends the memory address within the device it wishes to write to.
5. The device sends an ACK if the write address is in the range 0x00 – 0x7F, otherwise it sends a NACK.
6. The host transmits one or more data bytes; each is acknowledged by the device (unless trying to write to an
invalid address).
7. If the host sends more than one data byte, they are written to consecutive memory addresses.
8. The device automatically increments the target memory address after writing each data byte.
9. After writing the last data byte, the host should send the STOP condition.
Note: the host should not try to write to addresses outside the range 0x20 to 0x39 because this is the limit of the
device internal memory address.
4.3.2 Reading Data From the Device
The sequence of events required to read data from the device is shown next.
1. The host initiates the transfer by sending the START condition
2. The host follows this by sending the slave address of the device together with the WRITE bit.
3. The device sends an ACK.
4. The host then sends the memory address within the device it wishes to read from.
5. The device sends an ACK if the address to be read from is less than 0x80 otherwise it sends a NACK).
6. The host must then send a STOP and a START condition followed by the slave address again but this time
accompanied by the READ bit.
Note: Alternatively, instead of step 6 a repeated START can be sent so the host does not need to
relinquish control of the bus.
7. The device returns an ACK, followed by a data byte.
8. The host must return either an ACK or NACK.
1. If the host returns an ACK, the device subsequently transmits the data byte from the next address. Each
time a data byte is transmitted, the device automatically increments the internal address. The device
continues to return data bytes until the host responds with a NACK.
2. If the host returns a NACK, it should then terminate the transfer by issuing the STOP condition.
9. The device resets the internal address to the location indicated by the memory address sent to it previously.
Therefore, there is no need to send the memory address again when reading from the same location.
Note: Reading the 16-bit reference and signal values is not an automatic operation; reading the first byte of a 16-
bit value does not lock the other byte. As a result glitches in the reported value may be seen as values
increase from 255 to 256, or decrease from 256 to 255.
4.4 SDA, SCL
The I2
C bus transmits data and clock with SDA and SCL respectively. They are open-drain; that is I2
C master and
slave devices can only drive these lines low or leave them open. The termination resistors pull the line up to Vdd if no
I
2
C device is pulling it down.
The termination resistors commonly range from 1 k to 10 k and should be chosen so that the rise times on SDA
and SCL meet the I2
C specifications (1 µs maximum).
Standalone mode: if I2
C communications are not required, then standalone mode can be enabled by connecting the
MODE pin to Vdd. See Section 2.4 on page 8 for more information.
S SLA+W A A MemAddress S SLA+R A
A P
Host to Device Device Tx to Host
P
Data 1 Data 2 A Data n AAT42QT1070 [DATASHEET] 15 9596C–AT42–05/2013
5. Setups
5.1 Introduction
The device calibrates and processes signals using a number of algorithms specifically designed to provide for high
survivability in the face of adverse environmental challenges. User-defined Setups are employed to alter these
algorithms to suit each application. These Setups are loaded into the device over the I2C serial interfaces. In
standalone mode these settings are fixed to predetermined values.
Table 5-1. Internal Register Address Allocation
Address Use Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W
0 Chip ID Major ID (= 2) Minor ID (= E) R
1 Firmware Version Firmware version number R
2 Detection status CALIBRATE OVERFLOW – – – – – TOUCH R
3 Key status Reserved Key 6 Key 5 Key 4 Key 3 Key 2 Key 1 Key 0 R
4 – 5 Key signal 0 Key signal 0 (MSByte) – Key signal 0 (LSByte) R
6 – 7 Key signal 1 Key signal 1 (MSByte) – Key signal 1 (LSByte) R
8 – 9 Key signal 2 Key signal 2 (MSByte) – Key signal 2 (LSByte) R
10 – 11 Key signal 3 Key signal 3 (MSByte) – Key signal 3 (LSByte) R
12 – 13 Key signal 4 Key signal 4 (MSByte) – Key signal 4 (LSByte) R
14 – 15 Key signal 5 Key signal 5 (MSByte) – Key signal 5 (LSByte) R
16 – 17 Key signal 6 Key signal 6 (MSByte) – Key signal 6 (LSByte) R
18 – 19 Reference data 0 Reference data 0 (MSByte) – Reference data 0 (LSByte) R
20 – 21 Reference data 1 Reference data 1 (MSByte) – Reference data 1 (LSByte) R
22 – 23 Reference data 2 Reference data 2 (MSByte) – Reference data 2 (LSByte) R
24 – 25 Reference data 3 Reference data 3 (MSByte) – Reference data 3 (LSByte) R
26 – 27 Reference data 4 Reference data 4 (MSByte) – Reference data 4 (LSByte) R
28 – 29 Reference data 5 Reference data 5 (MSByte) – Reference data 5 (LSByte) R
30 – 31 Reference data 6 Reference data 6 (MSByte) – Reference data 6 (LSByte) R
32 NTHR key 0 Negative Threshold level for key 0 R/W
33 NTHR key 1 Negative Threshold level for key 1 R/W
34 NTHR key 2 Negative Threshold level for key 2 R/W
35 NTHR key 3 Negative Threshold level for key 3 R/W
36 NTHR key 4 Negative Threshold level for key 4 R/W
37 NTHR key 5 Negative Threshold level for key 5 R/W
38 NTHR key 6 Negative Threshold level for key 6 R/W
39 AVE/AKS key 0 Adjacent key suppression level for key 0 R/W
40 AVE/AKS key 1 Adjacent key suppression level for key 1 R/WAT42QT1070 [DATASHEET] 16
9596C–AT42–05/2013
5.2 Address 0: Chip ID
MAJOR ID: Reads back as 2
MINOR ID: Reads back as E
5.3 Address 1: Firmware Version
FIRMWARE VERSION: this shows the 8-bit firmware version 1.5 (0x15).
41 AVE/AKS key 2 Adjacent key suppression level for key 2 R/W
42 AVE/AKS key 3 Adjacent key suppression level for key 3 R/W
43 AVE/AKS key 4 Adjacent key suppression level for key 4 R/W
44 AVE/AKS key 5 Adjacent key suppression level for key 5 R/W
45 AVE/AKS key 6 Adjacent key suppression level for key 6 R/W
46 DI key 0 Detection integrator counter for key 0 R/W
47 DI key 1 Detection integrator counter for key 1 R/W
48 DI key 2 Detection integrator counter for key 2 R/W
49 DI key 3 Detection integrator counter for key 3 R/W
50 DI key 4 Detection integrator counter for key 4 R/W
51 DI key 5 Detection integrator counter for key 5 R/W
52 DI key 6 Detection integrator counter for key 6 R/W
53 FO/MO/Guard No FastOutDI/ Max Cal/Guard Channel R/W
54 LP Low Power (LP) Mode R/W
55 Max On Duration Maximum On Duration R/W
56 Calibrate Calibrate R/W
57 RESET RESET R/W
Table 5-1. Internal Register Address Allocation (Continued)
Address Use Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W
Table 5-2. Chip ID
Address b7 b6 b5 b4 b3 b2 b1 b0
0 MAJOR ID MINOR ID
Table 5-3. Firmware Version
Address b7 b6 b5 b4 b3 b2 b1 b0
1 FIRMWARE VERSION AT42QT1070 [DATASHEET] 17 9596C–AT42–05/2013
5.4 Address 2: Detection Status
CALIBRATE: This bit is set during a calibration sequence.
OVERFLOW: This bit is set if the time to acquire all key signals exceeds 8 ms.
TOUCH: This bit is set if any keys are in detect.
5.5 Address 3: Key Status
KEY0 – 6: bits 0 to 6 indicate which keys are in detection, if any. Touched keys report as 1, untouched or disabled
keys report as 0.
5.6 Address 4 – 17: Key Signal
KEY SIGNAL: addresses 4 – 17 allow key signals to be read for each key, starting with key 0. There are two bytes of
data for each key. These are the key’s 16-bit key signals which are accessed as two 8-bit bytes, stored MSByte first.
These addresses are read-only.
Table 5-4. Detection Status
Address b7 b6 b5 b4 b3 b2 b1 b0
2 CALIBRATE OVERFLO
W – – – – – TOUCH
Table 5-5. Key Status
Address b7 b6 b5 b4 b3 b2 b1 b0
3 Reserved KEY6 KEY5 KEY4 KEY3 KEY2 KEY1 KEY0
Table 5-6. Key Signal
Address b7 b6 b5 b4 b3 b2 b1 b0
4 MSByte OF KEY SIGNAL FOR KEY 0
5 LSByte OF KEY SIGNAL FOR KEY 0
6 – 17 MSByte/LSByte OF KEY SIGNAL FOR KEYS 1 – 6AT42QT1070 [DATASHEET] 18
9596C–AT42–05/2013
5.7 Address 18 – 31: Reference Data
REFERENCE DATA: addresses 18 – 31 allow reference data to be read for each key, starting with key 0. There are
two bytes of data for each key. These are the key’s 16-bit reference data which is accessed as two 8-bit bytes, stored
MSByte first. These addresses are read-only.
5.8 Address 32 – 38: Negative Threshold (NTHR)
NTHR Keys 0 – 6: these 8-bit values set the threshold value for each key to register a detection.
Default: 20 counts
Note: Do not use a setting of 0 as this causes a key to go into detection when its signal is equal to its reference.
5.9 Address 39 – 45: Averaging Factor/Adjacent Key Suppression (AVE/AKS)
AVE 0 – 5: The Averaging Factor (AVE) is the number of pulses which are added together and averaged to get the
final signal value for that channel.
For example, if AVE = 8 then 8 ADC samples are taken and added together. The result is divided by the original
number of pulses (8). If sixteen pulses are used then the result is divided by sixteen.
This provides a better signal-to-noise ratio but requires longer acquire times. Values for AVE are restricted internally
to 1, 2, 4, 8, 16 or 32.
Default: 8 (In standalone mode key 0 is 16)
AKS 0 – 1: these bits control which keys are included in an AKS group. There can be up to three groups, each
containing any number of keys (up to the maximum allowed for the mode).
Each key can have a value between 0 and 3, which assigns it to an AKS group of that number. A key may only go
into detect when it has the largest signal change of any key in its group. A value of 0 means the key is not in any AKS
group.
Default: 0x01
Table 5-7. Reference Data
Address b7 b6 b5 b4 b3 b2 b1 b0
18 MSByte OF REFERENCE DATA FOR KEY 0
19 LSByte OF REFERENCE DATA FOR KEY 0
20 – 31 MSByte/LSByte OF REFERENCE DATA FOR KEYS 1 – 6
Table 5-8. NTHR
Address b7 b6 b5 b4 b3 b2 b1 b0
32 – 38 NEGATIVE THRESHOLD FOR KEYS 0 – 6
Table 5-9. AVE/AKS
Address b7 b6 b5 b4 b3 b2 b1 b0
39 – 45 AVE5 AVE4 AVE3 AVE2 AVE1 AVE0 AKS1 AKS0AT42QT1070 [DATASHEET] 19 9596C–AT42–05/2013
5.10 Address 46 – 52: Detection Integrator (DI)
DETECTION INTEGRATOR: addresses 46 – 52 allow the DI level to be set for each key. This 8-bit value controls
the number of consecutive measurements that must be confirmed as having passed the key threshold before that
key is registered as being in detect. The minimum value for the DI filter is 2. Settings of 0 and 1 for the DI also default
to 2 because a minimum of two consecutive measurements must be confirmed.
Default: 4
5.11 Address 53: FastOutDI/Max Cal/Guard Channel
FO: Fast Out DI – when bit 5 is set then a key filters out with an integrator of 4. Could have a DI in of 100 but filter out
with DI of 4 (global setting for all keys).
MAX CAL: if this bit is clear then all keys recalibrate after a Max On Duration timeout, otherwise only the key with the
incorrect timing gets recalibrated.
GUARD CHANNEL: bits 0 – 3 are used to set a key as the guard channel (which gets priority filtering). Valid values
are 0 – 6, with any larger value disabling the guard key feature.
5.12 Address 54: Low Power (LP) Mode
Table 5-10. Detection Integrator
Address b7 b6 b5 b4 b3 b2 b1 b0
46 – 52 DETECTION INTEGRATOR
Table 5-11. Max Cal/Guard Channel
Address b7 b6 b5 b4 b3 b2 b1 b0
53 – FO MAX CAL GUARD CHANNEL
Table 5-12. LP Mode
Address b7 b6 b5 b4 b3 b2 b1 b0
54 LOW POWER MODEAT42QT1070 [DATASHEET] 20
9596C–AT42–05/2013
LP MODE: this 8-bit value determines the number of 8 ms intervals between key measurements. Longer intervals
between measurements yield a lower power consumption but at the expense of a slower response to touch.
Default: 2 (16 ms between key acquisitions)
5.13 Address 55: Max On Duration
MAX ON DURATION: this is a 8-bit value which determines how long any key can be in touch before it recalibrates
itself.
A value of 0 turns Max On Duration off.
Default: 180 (160 ms × 180 = 28.8s)
Setting Time
0 8 ms
1 8 ms
2 16 ms
3 24 ms
4 32 ms
254 2.032s
255 2.040s
Table 5-13. Max Time On
Address b7 b6 b5 b4 b3 b2 b1 b0
55 MAX ON DURATION
Setting Time
0 Off
1 160 ms
2 320 ms
3 480 ms
4 640 ms
255 40.8sAT42QT1070 [DATASHEET] 21 9596C–AT42–05/2013
5.14 Address 56: Calibrate
Writing any nonzero value into this address triggers the device to start a calibration cycle. The CALIBRATE flag in
the detection status register is set when the calibration begins and clears when the calibration has finished.
5.15 Address 57: RESET
Writing any nonzero value to this address triggers the device to reset.
Table 5-14. Calibrate
Address b7 b6 b5 b4 b3 b2 b1 b0
56 Writing a nonzero value forces a calibration
Table 5-15. RESET
Address b7 b6 b5 b4 b3 b2 b1 b0
57 Writing a nonzero value forces a resetAT42QT1070 [DATASHEET] 22
9596C–AT42–05/2013
6. Specifications
6.1 Absolute Maximum Specifications
6.2 Recommended Operating Conditions
6.3 DC Specifications
Vdd –0.5 to +6 V
Max continuous pin current, any control or drive pin ±10 mA
Short circuit duration to ground, any pin infinite
Short circuit duration to Vdd, any pin infinite
Voltage forced onto any pin –0.5 V to (Vdd + 0.5) V
CAUTION: Stresses beyond those listed under Absolute Maximum Specifications may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or other conditions beyond
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
specification conditions for extended periods may affect device reliability.
Operating temperature –40o
C to +85o
C
Storage temperature –55o
C to +125o
C
Vdd +1.8 V to 5.5 V
Supply ripple+noise ±25 mV
Cx load capacitance per key 1 to 30 pF
Vdd = 3.3 V, Cs = 10 nF, load = 5 pF, 32 ms default sleep, Ta = recommended range, unless otherwise noted
Parameter Description Minimum Typical Maximum Units Notes
Vil Low input logic level – – 0.2 × Vdd V
Vih High input logic level 0.7 × Vdd – Vdd + 0.5 V
Vol Low output voltage – – 0.6 V
Voh High output voltage Vdd –
0.7V – – V
Iil Input leakage current – – ±1 µAAT42QT1070 [DATASHEET] 23 9596C–AT42–05/2013
6.4 Power Consumption Measurements
6.5 Timing Specifications
Cx = 5 pF, Rs = 4.7 k
LP Mode
Idd (µA) at Vdd =
5 V 3.3 V 1.8 V
0 (8 ms) 1744 906 442
1 (16 ms) 1375 615 305
2 (24 ms) 1263 525 261
4 (32 ms) 1168 486 234
5 (40 ms) 1119 445 221
6 (48 ms) 1089 434 211
Paramete
r Description Minimum
Typica
l Maximum Units Notes
TR Response time DI
setting × 8 ms – LP mode +
(DI setting × 8 ms) ms Under host control
FQT Sample frequency 162 180 198 kHz
Modulated
spread-spectrum
(chirp)
TD
Power-up delay to
operate/calibration
time
– <230 – ms Can be longer if burst
is very long.
FI2C I
2
C clock rate – – 400 kHz –
Fm Burst modulation,
percentage ±8 % –
RESET pulse width 5 – – µs –AT42QT1070 [DATASHEET] 24
9596C–AT42–05/2013
6.6 Mechanical Dimensions
6.7 AT42QT1070-SSU – 14-pin SOIC
42077B-MCU-10/2013
USER GUIDE
Atmel OLED1 Xplained Pro
Preface
Atmel® OLED1 Xplained Pro is an extension board to the Atmel Xplained
Pro evaluation platform. The board enables the user to experiment with user
interface applications with buttons, LEDs and a display.Atmel OLED1 Xplained Pro [USER GUIDE]
42077B-MCU-10/2013
2
Table of Contents
Preface .......................................................................................... 1
1. Introduction .............................................................................. 3
1.1. Features .............................................................................. 3
1.2. Kit overview ......................................................................... 3
2. Getting started ......................................................................... 4
2.1. 3 Steps to start exploring the Atmel Xplained Pro platform ............. 4
2.2. Connecting OLED1 Xplained Pro to the Xplained Pro MCU
board. ................................................................................. 4
2.3. Design documentation and related links ..................................... 4
3. Xplained Pro ............................................................................ 5
3.1. Hardware identification system ................................................. 5
3.2. Standard headers and connectors ............................................ 5
3.2.1. Xplained Pro Standard Extension Header ...................... 5
4. Hardware user guide .............................................................. 7
4.1. Headers and connectors ......................................................... 7
4.1.1. OLED1 Xplained Pro extension header ......................... 7
4.2. Peripherals ........................................................................... 7
4.2.1. LEDs ...................................................................... 7
4.2.2. Push buttons ............................................................ 7
4.2.3. OLED display ........................................................... 8
5. Hardware revision history and known issues .......................... 9
5.1. Identifying product ID and revision ............................................ 9
5.2. Revision 3 ........................................................................... 9
6. Document revision history ..................................................... 10
7. Evaluation board/kit important notice .................................... 11Atmel OLED1 Xplained Pro [USER GUIDE]
42077B-MCU-10/2013
3
1. Introduction
1.1 Features
● UG-2832HSWEG04 monochrome OLED display
● 128 x 32 Pixels
● Controlled by 4-wire SPI interface, up to 100MHz
● Three LEDs
● Three Mechanical push buttons
● Xplained Pro hardware identification system
1.2 Kit overview
OLED1 Xplained Pro is a basic extension board for the Xplained Pro platform with three LEDs, three push
buttons and an OLED display. The OLED display is controlled via a SPI interface up to 100MHz. OLED1
Xplained Pro connects to any Xplained Pro standard extension header on any Xplained Pro MCU board.
Figure 1-1. OLED1 Xplained Pro top overview.Atmel OLED1 Xplained Pro [USER GUIDE]
42077B-MCU-10/2013
4
2. Getting started
2.1 3 Steps to start exploring the Atmel Xplained Pro platform
1. Download and install Atmel Studio.
2. Launch Atmel Studio.
3. Connect OLED1 Xplained Pro to an Xplained Pro MCU board and connect a USB cable to DEBUG USB
port on the Xplained Pro MCU board.
2.2 Connecting OLED1 Xplained Pro to the Xplained Pro MCU board.
Atmel OLED1 Xplained Pro has been designed to be connected to the Xplained Pro header marked EXT3.
However it is compatible with all Xplained Pro EXT headers. Please refer to the pin-out of your Xplained Pro
evaluation kit to find out which Xplained Pro EXT headers that can be used.
Once the Xplained Pro MCU board is powered the green power LED will be lit and Atmel Studio will auto
detect which Xplained Pro MCU- and extension board(s) that is connected. You will be presented with
relevant information like datasheets and kit documentation. You also have the option to launch Atmel Software
Framework (ASF) example applications. The target device is programmed and debugged by the on-board
Embedded Debugger. No external programmer or debugger tool is needed.
2.3 Design documentation and related links
The following list contains links to the most relevant documents and software for OLED1 Xplained Pro.
1. Xplained Pro products 1
- Atmel Xplained Pro is a series of small-sized and easy-to-use evaluation kits
for 8- and 32-bit Atmel microcontrollers. It consists of a series of low cost MCU boards for evaluation and
demonstration of features and capabilities of different MCU families.
2. OLED1 Xplained Pro User Guide 2
- PDF version of this User Guide.
3. OLED1 Xplained Pro Design Documentation 3
- Package containing schematics, BOM, assembly
drawings, 3D plots, layer plots etc.
4. Atmel Studio 4
- Free Atmel IDE for development of C/C++ and assembler code for Atmel
microcontrollers.
1
http://www.atmel.com/XplainedPro
2
http://www.atmel.com/Images/Atmel-42077-OLED1-Xplained-Pro_User-Guide.pdf
3
http://www.atmel.com/Images/Atmel-42077-OLED1-Xplained-Pro_User-Guide.zip
4
http://www.atmel.com/atmelstudioAtmel OLED1 Xplained Pro [USER GUIDE]
42077B-MCU-10/2013
5
3. Xplained Pro
Xplained Pro is an evaluation platform that provides the full Atmel microcontroller experience. The platform
consists of a series of Microcontroller (MCU) boards and extension boards that are integrated with Atmel
Studio, have Atmel Software Framework (ASF) drivers and demo code, support data streaming and more.
Xplained Pro MCU boards support a wide range of Xplained Pro extension boards that are connected through
a set of standardized headers and connectors. Each extension board has an identification (ID) chip to uniquely
identify which boards are mounted on a Xplained Pro MCU board. This information is used to present relevant
user guides, application notes, datasheets and example code through Atmel Studio. Available Xplained Pro
MCU and extension boards can be purchased in the Atmel Web Store
1
.
3.1 Hardware identification system
All Xplained Pro compatible extension boards have an Atmel ATSHA204 CryptoAuthentication™ chip mounted.
This chip contains information that identifies the extension with its name and some extra data. When an
Xplained Pro extension board is connected to an Xplained Pro MCU board the information is read and sent
to Atmel Studio. The Atmel Kits extension, installed with Atmel Studio, will give relevant information, code
examples and links to relevant documents. Table 3-1, “Xplained Pro ID Chip Content” on page 5 shows the
data fields stored in the ID chip with example content.
Table 3-1. Xplained Pro ID Chip Content
Data Field Data Type Example Content
Manufacturer ASCII string Atmel’\0’
Product Name ASCII string Segment LCD1 Xplained Pro’\0’
Product Revision ASCII string 02’\0’
Product Serial Number ASCII string 1774020200000010’\0’
Minimum Voltage [mV] uint16_t 3000
Maximum Voltage [mV] uint16_t 3600
Maximum Current [mA] uint16_t 30
3.2 Standard headers and connectors
3.2.1 Xplained Pro Standard Extension Header
All Xplained Pro kits have one or more dual row, 20 pin, 100mil extension headers. Xplained Pro MCU boards
have male headers while Xplained Pro extensions have their female counterparts. Note that all pins are not
always connected. However, all the connected pins follow the defined pin-out described in Table 3-2, “Xplained
Pro Extension Header” on page 5. The extension headers can be used to connect a wide variety of
Xplained Pro extensions to Xplained Pro MCU boards and to access the pins of the target MCU on Xplained
Pro MCU board directly.
Table 3-2. Xplained Pro Extension Header
Pin number Name Description
1 ID Communication line to the ID chip on extension board.
2 GND Ground.
3 ADC(+) Analog to digital converter , alternatively positive part of
differential ADC.
4 ADC(-) Analog to digital converter , alternatively negative part of
differential ADC.
5 GPIO1 General purpose I/O.
6 GPIO2 General purpose I/O.
7 PWM(+) Pulse width modulation , alternatively positive part of
differential PWM.
8 PWM(-) Pulse width modulation , alternatively positive part of
differential PWM.
1
http://store.atmel.com/Atmel OLED1 Xplained Pro [USER GUIDE]
42077B-MCU-10/2013
6
Pin number Name Description
9 IRQ/GPIO Interrupt request line and/or general purpose I/O.
10 SPI_SS_B/GPIO Slave select for SPI and/or general purpose I/O.
11 TWI_SDA Data line for two wire interface. Always implemented, bus
type.
12 TWI_SCL Clock line for two wire interface. Always implemented, bus
type.
13 USART_RX Receiver line of Universal Synchronous and Asynchronous
serial Receiver and Transmitter.
14 USART_TX Transmitter line of Universal Synchronous and
Asynchronous serial Receiver and Transmitter.
15 SPI_SS_A Slave select for SPI. Should be unique if possible.
16 SPI_MOSI Master out slave in line of Serial peripheral interface. Always
implemented, bus type.
17 SPI_MISO Master in slave out line of Serial peripheral interface. Always
implemented, bus type.
18 SPI_SCK Clock for Serial peripheral interface. Always implemented,
bus type.
19 GND Ground.
20 VCC Power for extension board.Atmel OLED1 Xplained Pro [USER GUIDE]
42077B-MCU-10/2013
7
4. Hardware user guide
4.1 Headers and connectors
4.1.1 OLED1 Xplained Pro extension header
OLED1 Xplained Pro implements one Xplained Pro Standard Extension Header on page 5 marked with
EXT in silkscreen. This header makes it possible to connect the board to any Xplained Pro MCU board.
The pin-out definition for the extension header can be seen in Table 4-1, “OLED1 Xplained Pro extension
header” on page 7.
Table 4-1. OLED1 Xplained Pro extension header
Pin Number Function Description
1 ID Communication line to ID chip
2 GND Ground
3 BUTTON2 Push button 2, active low
4 BUTTON3 Push button 3, active low
5 DATA_CMD_SEL Data / command select for OLED display. High = data, low =
command.
6 LED3 LED3, active low
7 LED1 LED1, active low
8 LED2 LED2, active low
9 BUTTON1 Push button 1, active low
10 DISPLAY_RESET Reset line for OLED display, active low
11 NC
12 NC
13 NC
14 NC
15 DISPLAY_SS OLED display slave select, active low
16 SPI MOSI MOSI signal SPI connected to OLED display
17 NC
18 SPI SCK Clock signal for SPI connected to OLED display
19 GND Ground
20 VCC Target supply voltage
4.2 Peripherals
4.2.1 LEDs
There are three yellow LEDs available on OLED1 Xplained Pro. The LEDs can be activated by driving the
connected I/O line low.
Table 4-2. LED connections
Pin on EXT connector Silk screen marking
7 LED1
8 LED2
6 LED3
4.2.2 Push buttons
There are three push buttons available on OLED1 Xplained Pro. When a button is pushed the corresponding
IO pin is connected to ground. There are no external pull-up resistors on OLED1 Xplained Pro, so internal pullup
resistors have to be enabled in the target microcontroller.Atmel OLED1 Xplained Pro [USER GUIDE]
42077B-MCU-10/2013
8
Note Remember to enable internal pull-up resistors in the target device to get a defined electrical level
on the IO lines connected to the buttons.
Table 4-3. Push button connections
Pin on EXT connector Silk screen marking
9 BUTTON1
3 BUTTON2
4 BUTTON3
4.2.3 OLED display
OLED1 Xplained Pro features a 128 x 32 pixel white monochrome OLED display, UG-2832HSWEG041
from
WiseChip Semiconductor Inc. The display has a SSD1306 display controller by Solomon Systech built in
and is controlled via a 4-wire SPI interface + reset with the signals described in Table 4-4, “OLED display
connections” on page 8. The datasheets for the display module or the display controller is not publicly
available and has to be acquired from the respective manufacturers.
Note Note that the OLED display does not have a SPI MISO signal. That means that data can only be
written to the display, not read.
Table 4-4. OLED display connections
Pin on EXT connector Signal Name Description
16 SPI_MOSI SPI master out, slave in signal.
Used to write data to the display
18 SPI_SCK SPI clock signal, generated by
the master.
5 DATA_CMD_SEL Data/command select.
Used to choose whether the
communication is data to the
display memory or a command to
the LCD controller.
15 DISPLAY_SS SPI slave select signal,
must be held low during SPI
communication.
10 DISPLAY_RESET Reset signal to the OLED
display, active low. Used during
initialization of the display.
1
http://www.wisechip.com.tw/english/Products_02-04.aspAtmel OLED1 Xplained Pro [USER GUIDE]
42077B-MCU-10/2013
9
5. Hardware revision history and known issues
5.1 Identifying product ID and revision
The revision and product identifier of Xplained Pro boards can be found in two ways, through Atmel Studio or
by looking at the sticker on the bottom side of the PCB.
By connecting a Xplained Pro MCU board to a computer with Atmel Studio running, an information window will
pop up. The first 6 digits of the serial number, which is listed under kit details, contain the product identifier and
revision. Information about connected Xplained Pro extension boards will also appear in the Atmel Kits window.
The same information can be found on the sticker on the bottom side of the PCB. Most kits will print the
identifier and revision in plain text as A09-nnnn\rr where nnnn is the identifier and rr is the revision. Boards with
limited space have a sticker with only a QR-code which contains a serial number string.
The serial number string has the following format:
"nnnnrrssssssssss"
n = product identifier
r = revision
s = serial number
The kit identifier for OLED1 Xplained Pro is 1769.
5.2 Revision 3
Revision 3 of OLED1 Xplained Pro is the initial released version.
OLED1 Xplained Pro boards with a serial number that ends with a number lower than 11148 may have a wrong
revision programmed into the Xplained Pro ID chip. This will only affect the information displayed by the Atmel
Kits extension in Atmel Studio. It will not affect the operation of the board.Atmel OLED1 Xplained Pro [USER GUIDE]
42077B-MCU-10/2013
10
6. Document revision history
Document
revision
Date Comment
42077B 09/2013 Added errata about revision 3 of the board.
42077A 25/02/2013 First releaseAtmel OLED1 Xplained Pro [USER GUIDE]
42077B-MCU-10/2013
11
7. Evaluation board/kit important notice
This evaluation board/kit is intended for use for FURTHER ENGINEERING, DEVELOPMENT,
DEMONSTRATION, OR EVALUATION PURPOSES ONLY. It is not a finished product and may not (yet)
comply with some or any technical or legal requirements that are applicable to finished products, including,
without limitation, directives regarding electromagnetic compatibility, recycling (WEEE), FCC, CE or UL
(except as may be otherwise noted on the board/kit). Atmel supplied this board/kit "AS IS," without any
warranties, with all faults, at the buyer's and further users' sole risk. The user assumes all responsibility
and liability for proper and safe handling of the goods. Further, the user indemnifies Atmel from all claims
arising from the handling or use of the goods. Due to the open construction of the product, it is the user's
responsibility to take any and all appropriate precautions with regard to electrostatic discharge and any other
technical or legal concerns.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER USER NOR
ATMEL SHALL BE LIABLE TO EACH OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR
CONSEQUENTIAL DAMAGES.
No license is granted under any patent right or other intellectual property right of Atmel covering or relating
to any machine, process, or combination in which such Atmel products or services might be or are used.Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com
© 2013 Atmel Corporation. All rights reserved. / Rev.: 42077B-MCU-10/2013
Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel
Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted
by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE,
ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR
ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS
INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to
specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise,
Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended
to support or sustain life.
Atmel-8303H-AVR-ATtiny1634-Datasheet–02/2014
Features
• High Performance, Low Power AVR® 8-bit Microcontroller
• Advanced RISC Architecture
– 125 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
• High Endurance, Non-volatile Memory Segments
– 16K Bytes of In-System, Self-Programmable Flash Program Memory
• Endurance: 10,000 Write/Erase Cycles
– 256 Bytes of In-System Programmable EEPROM
• Endurance: 100,000 Write/Erase Cycles
– 1K Byte of Internal SRAM
– Data retention: 20 years at 85C / 100 years at 25C
– Programming Lock for Self-Programming Flash & EEPROM Data Security
• Peripheral Features
– Dedicated Hardware and QTouch® Library Support for Capacitive Touch Sensing
– One 8-bit and One 16-bit Timer/Counter with Two PWM Channels, Each
– 12-channel, 10-bit ADC
– Programmable Ultra Low Power Watchdog Timer
– On-chip Analog Comparator
– Two Full Duplex USARTs with Start Frame Detection
– Universal Serial Interface
– Slave I2
C Serial Interface
• Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– Internal and External Interrupt Sources
• Pin Change Interrupt on 18 Pins
– Low Power Idle, ADC Noise Reduction, Standby and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit with Supply Voltage Sampling
– Calibrated 8MHz Oscillator with Temperature Calibration Option
– Calibrated 32kHz Ultra Low Power Oscillator
– On-chip Temperature Sensor
• I/O and Packages
– 18 Programmable I/O Lines
– 20-pad QFN/MLF, and 20-pin SOIC
• Operating Voltage:
– 1.8 – 5.5V
• Speed Grade:
– 0 – 2MHz @ 1.8 – 5.5V
– 0 – 8MHz @ 2.7 – 5.5V
– 0 – 12MHz @ 4.5 – 5.5V
• Temperature Range: -40C to +105C
• Low Power Consumption
– Active Mode: 0.2mA at 1.8V and 1MHz
– Idle Mode: 30µA at 1.8V and 1MHz
– Power-Down Mode (WDT Enabled): 1µA at 1.8V
– Power-Down Mode (WDT Disabled): 100nA at 1.8V
8-bit Atmel tinyAVR Microcontroller with
16K Bytes In-System Programmable Flash
ATtiny1634ATtiny1634 [DATASHEET] 2
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
1. Pin Configurations
Figure 1-1. Pinout of ATtiny1634
1
2
3
4
5
QFN/MLF
15
14
13
12
11
20
19
18
17
16
6
7
8
9
10
NOTE
Bottom pad should be
soldered to ground.
(PCINT1/AIN0) PA1
(PCINT0/AREF) PA0
GND
VCC
PC5 (XTAL1/CLKI/PCINT17)
PC0 (ADC9/OC0A/XCK0/PCINT12)
PC1 (ADC10/ICP1/SCL/USCK/XCK1/PCINT13)
PC2 (ADC11/CLKO/INT0/PCINT14)
PC3 (RESET/dW/PCINT15)
PC4 (XTAL2/PCINT16)
PA7 (PCINT7/RXD0/ADC4)
PB0 (PCINT8/TXD0/ADC5)
PB1 (ADC6/DI/SDA/RXD1/PCINT9)
PB2 (ADC7/DO/TXD1/PCINT10)
PB3 (ADC8/OC1A/PCINT11)
(PCINT6/OC1B/ADC3) PA6
(PCINT5/OC0B/ADC2) PA5
(PCINT4/T0/ADC1) PA4
(PCINT3/T1/SNS/ADC0) PA3
(PCINT2/AIN1) PA2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
(PCINT8/TXD0/ADC5) PB0
(PCINT7/RXD0/ADC4) PA7
(PCINT6/OC1B/ADC3) PA6
(PCINT5/OC0B/ADC2) PA5
(PCINT4/T0/ADC1) PA4
(PCINT3/T1/SNS/ADC0) PA3
(PCINT2/AIN1) PA2
(PCINT1/AIN0) PA1
(PCINT0/AREF) PA0
GND
PB1 (ADC6/DI/SDA/RXD1/PCINT9)
PB2 (ADC7/DO/TXD1/PCINT10)
PB3 (ADC8/OC1A/PCINT11)
PC0 (ADC9/OC0A/XCK0/PCINT12)
PC1 (ADC10/ICP1/SCL/USCK/XCK1/PCINT13)
PC2 (ADC11/CLKO/INT0/PCINT14)
PC3 (RESET/dW/PCINT15)
PC4 (XTAL2/PCINT16)
PC5 (XTAL1/CLKI/PCINT17)
VCC
SOICATtiny1634 [DATASHEET] 3
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
1.1 Pin Descriptions
1.1.1 VCC
Supply voltage.
1.1.2 GND
Ground.
1.1.3 XTAL1
Input to the inverting amplifier of the oscillator and the internal clock circuit. This is an alternative pin configuration
of PC5.
1.1.4 XTAL2
Output from the inverting amplifier of the oscillator. Alternative pin configuration of PC4.
1.1.5 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock
is not running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 24-5
on page 231. Shorter pulses are not guaranteed to generate a reset.
The reset pin can also be used as a (weak) I/O pin.
1.1.6 Port A (PA7:PA0)
This is an 8-bit, bi-directional I/O port with internal pull-up resistors (selected for each bit). Output buffers have the
following drive characteristics:
• PA7, PA4:PA0: Symmetrical, with standard sink and source capability
• PA6, PA5: Asymmetrical, with high sink and standard source capability
As inputs, port pins that are externally pulled low will source current provided that pull-up resistors are activated.
Port pins are tri-stated when a reset condition becomes active, even if the clock is not running.
This port has alternate pin functions to serve special features of the device. See “Alternate Functions of Port A” on
page 62.
1.1.7 Port B (PB3:PB0)
This is a 4-bit, bi-directional I/O port with internal pull-up resistors (selected for each bit).Output buffers have the
following drive characteristics:
• PB3: Asymmetrical, with high sink and standard source capability
• PB2:PB0: Symmetrical, with standard sink and source capability
As inputs, port pins that are externally pulled low will source current provided that pull-up resistors are activated.
Port pins are tri-stated when a reset condition becomes active, even if the clock is not running.
This port has alternate pin functions to serve special features of the device. See “Alternate Functions of Port B” on
page 65.
1.1.8 Port C (PC5:PC0)
This is a 6-bit, bi-directional I/O port with internal pull-up resistors (selected for each bit). Output buffers have the
following drive characteristics:ATtiny1634 [DATASHEET] 4
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
• PC5:PC1: Symmetrical, with standard sink and source capability
• PC0: Asymmetrical, with high sink and standard source capability
As inputs, port pins that are externally pulled low will source current provided that pull-up resistors are activated.
Port pins are tri-stated when a reset condition becomes active, even if the clock is not running.
This port has alternate pin functions to serve special features of the device. See “Alternate Functions of Port C” on
page 67.
2. Overview
ATtiny1634 is a low-power CMOS 8-bit microcontrollers based on the AVR enhanced RISC architecture. By executing
powerful instructions in a single clock cycle, the ATtiny1634 achieves throughputs approaching 1 MIPS per
MHz allowing the system designer to optimize power consumption versus processing speed.
Figure 2-1. Block Diagram
DEBUG
INTERFACE
CALIBRATED ULP
OSCILLATOR
WATCHDOG
TIMER
CALIBRATED
OSCILLATOR
TIMING AND
CONTROL
VCC RESET GND
8-BIT DATA BUS
CPU CORE
PROGRAM
MEMORY
(FLASH)
DATA
MEMORY
(SRAM)
POWER
SUPERVISION:
POR
BOD
RESET
ISP
INTERFACE
PORT A PORT B PORT C
VOLTAGE
REFERENCE
MULTIPLEXER ANALOG
COMPARATOR
ADC
TEMPERATURE
SENSOR
TWO-WIRE
INTERFACE
USART0
TOUCH
SENSING
EEPROM
ON-CHIP
DEBUGGER
PA[7:0] PB[3:0] PC[5:0]
8-BIT
TIMER/COUNTER
16-BIT
TIMER/COUNTER
USI
USART1ATtiny1634 [DATASHEET] 5
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are
directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in a single
instruction, executed in one clock cycle. The resulting architecture is compact and code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
ATtiny1634 provides the following features:
• 16K bytes of in-system programmable Flash
• 1K bytes of SRAM data memory
• 256 bytes of EEPROM data memory
• 18 general purpose I/O lines
• 32 general purpose working registers
• An 8-bit timer/counter with two PWM channels
• A16-bit timer/counter with two PWM channels
• Internal and external interrupts
• A 10-bit ADC with 5 internal and 12 external channels
• An ultra-low power, programmable watchdog timer with internal oscillator
• Two programmable USART’s with start frame detection
• A slave Two-Wire Interface (TWI)
• A Universal Serial Interface (USI) with start condition detector
• A calibrated 8MHz oscillator
• A calibrated 32kHz, ultra low power oscillator
• Four software selectable power saving modes.
The device includes the following modes for saving power:
• Idle mode: stops the CPU while allowing the timer/counter, ADC, analog comparator, SPI, TWI, and interrupt
system to continue functioning
• ADC Noise Reduction mode: minimizes switching noise during ADC conversions by stopping the CPU and all
I/O modules except the ADC
• Power-down mode: registers keep their contents and all chip functions are disabled until the next interrupt or
hardware reset
• Standby mode: the oscillator is running while the rest of the device is sleeping, allowing very fast start-up
combined with low power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The Flash program memory
can be re-programmed in-system through a serial interface, by a conventional non-volatile memory
programmer or by an on-chip boot code, running on the AVR core.
The ATtiny1634 AVR is supported by a full suite of program and system development tools including: C compilers,
macro assemblers, program debugger/simulators and evaluation kits.ATtiny1634 [DATASHEET] 6
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
3. General Information
3.1 Resources
A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available
for download at http://www.atmel.com/avr.
3.2 Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. These
code examples assume that the part specific header file is included before compilation. Be aware that not all C
compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent.
Please confirm with the C compiler documentation for more details.
For I/O Registers located in the extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must
be replaced with instructions that allow access to extended I/O. Typically, this means “LDS” and “STS” combined
with “SBRS”, “SBRC”, “SBR”, and “CBR”. Note that not all AVR devices include an extended I/O map.
3.3 Capacitive Touch Sensing
Atmel QTouch Library provides a simple to use solution for touch sensitive interfaces on Atmel AVR microcontrollers.
The QTouch Library includes support for QTouch® and QMatrix® acquisition methods.
Touch sensing is easily added to any application by linking the QTouch Library and using the Application Programming
Interface (API) of the library to define the touch channels and sensors. The application then calls the API to
retrieve channel information and determine the state of the touch sensor.
The QTouch Library is free and can be downloaded from the Atmel website. For more information and details of
implementation, refer to the QTouch Library User Guide – also available from the Atmel website.
3.4 Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20
years at 85°C or 100 years at 25°C.
4. CPU Core
This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct
program execution. The CPU must therefore be able to access memories, perform calculations, control
peripherals, and handle interrupts.ATtiny1634 [DATASHEET] 7
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
4.1 Architectural Overview
Figure 4-1. Block Diagram of the AVR Architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories
and buses for program and data. Instructions in the Program memory are executed with a single level pipelining.
While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept
enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable
Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle
access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands
are output from the Register File, the operation is executed, and the result is stored back in the Register File
– in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing –
enabling efficient address calculations. One of the these address pointers can also be used as an address pointer
for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register,
described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single
register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated
to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, capable of directly addressing
the whole address space. Most AVR instructions have a single 16-bit word format but 32-bit wide instructions also
exist. The actual instruction set varies, as some devices only implement a part of the instruction set.
INTERRUPT
UNIT
STATUS AND
CONTROL
PROGRAM
MEMORY
(FLASH)
DATA
MEMORY
(SRAM)
PROGRAM
COUNTER
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
DIRECT ADDRESSING
INDIRECT ADDRESSING
8-BIT DATA BUSATtiny1634 [DATASHEET] 8
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack
is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total
SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines
or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data
SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in
the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have
priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the
priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other
I/O functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the Register
File, 0x20 - 0x5F. In addition, the ATtiny1634 has Extended I/O Space from 0x60 - 0xFF in SRAM where only
the ST/STS/STD and LD/LDS/LDD instructions can be used.
4.2 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers.
Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an
immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bitfunctions.
Some implementations of the architecture also provide a powerful multiplier supporting both
signed/unsigned multiplication and fractional format. See external document “AVR Instruction Set” and “Instruction
Set Summary” on page 278 section for more information.
4.3 Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction. This
information can be used for altering program flow in order to perform conditional operations. Note that the Status
Register is updated after all ALU operations. This will in many cases remove the need for using the dedicated compare
instructions, resulting in faster and more compact code. See external document “AVR Instruction Set” and
“Instruction Set Summary” on page 278 section for more information.
The Status Register is neither automatically stored when entering an interrupt routine, nor restored when returning
from an interrupt. This must be handled by software.
4.4 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance
and flexibility, the following input/output schemes are supported by the Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 4-2 below shows the structure of the 32 general purpose working registers in the CPU.ATtiny1634 [DATASHEET] 9
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 4-2. General Purpose Working Registers
Most of the instructions operating on the Register File have direct access to all registers, and most of them are single
cycle instructions.
As shown in Figure 4-2, each register is also assigned a Data memory address, mapping them directly into the first
32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory
organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to
index any register in the file.
4.4.1 The X-register, Y-register, and Z-register
The registers R26..R31 have added functions to their general purpose usage. These registers are 16-bit address
pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as
described in Figure 4-3 below.
7 0 Addr. Special Function
R0 0x00
R1 0x01
R2 0x02
R3 0x03
… ...
R12 0x0C
R13 0x0D
R14 0x0E
R15 0x0F
R16 0x10
R17 0x11
… ...
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High ByteATtiny1634 [DATASHEET] 10
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 4-3. The X-, Y-, and Z-registers
In the different addressing modes these address registers have functions as fixed displacement, automatic increment,
and automatic decrement (see the instruction set reference for details).
4.5 Stack Pointer
The stack is mainly used for storing temporary data, local variables and return addresses after interrupts and subroutine
calls. The Stack Pointer registers (SPH and SPL) always point to the top of the stack. Note that the stack
grows from higher memory locations to lower memory locations. This means that the PUSH instructions decreases
and the POP instruction increases the stack pointer value.
The stack pointer points to the area of data memory where subroutine and interrupt stacks are located. This stack
space must be defined by the program before any subroutine calls are executed or interrupts are enabled.
The pointer is decremented by one when data is put on the stack with the PUSH instruction, and incremented by
one when data is fetched with the POP instruction. It is decremented by two when the return address is put on the
stack by a subroutine call or a jump to an interrupt service routine, and incremented by two when data is fetched by
a return from subroutine (the RET instruction) or a return from interrupt service routine (the RETI instruction).
The AVR stack pointer is typically implemented as two 8-bit registers in the I/O register file. The width of the stack
pointer and the number of bits implemented is device dependent. In some AVR devices all data memory can be
addressed using SPL, only. In this case, the SPH register is not implemented.
The stack pointer must be set to point above the I/O register areas, the minimum value being the lowest address of
SRAM. See Table 5-2 on page 16.
4.6 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the
CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.
Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture
and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with
the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
15 0
X-register 7 XH 0 7 XL 0
R27 R26
15 0
Y-register 7 YH 0 7 YL 0
R29 R28
15 0
Z-register 7 ZH 0 7 ZL 0
R31 R30ATtiny1634 [DATASHEET] 11
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 4-4. The Parallel Instruction Fetches and Instruction Executions
Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using
two register operands is executed, and the result is stored back to the destination register.
Figure 4-5. Single Cycle ALU Operation
4.7 Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a
separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which
must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the
interrupt.
The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors.
The complete list of vectors is shown in “Interrupts” on page 47. The list also determines the priority levels of the
different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next
is INT0 – the External Interrupt Request 0.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software
can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current
interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For
these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt
handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing
a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding
interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the
flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit
is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is
set, and will then be executed by order of priority.
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clkCPUATtiny1634 [DATASHEET] 12
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily
have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will
not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction
before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when
returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be
executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example
shows how this can be used to avoid interrupts during the timed EEPROM write sequence.
Note: See “Code Examples” on page 6.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending
interrupts, as shown in the following example.
Note: See “Code Examples” on page 6.
4.7.1 Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock
cycles the Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1< 1MHz 12 – 22 pF
XTAL2
XTAL1
GND
C2
C1ATtiny1634 [DATASHEET] 29
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster
than the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were
readable, and the exact time it takes to switch from one clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the new clock frequency
is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2
is the period corresponding to the new prescaler setting.
6.4 Clock Output Buffer
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT_IO bit has to be programmed.
The CKOUT fuse determines the initial value of the CKOUT_IO bit that is loaded to the CLKSR register
when the device is powered up or has been reset. The clock output can be switched at run-time by setting the
CKOUT_IO bit in CLKSR as described in chapter “CLKSR – Clock Setting Register” on page 29.
This mode is suitable when the chip clock is used to drive other circuits on the system. Note that the clock will not
be output during reset and that the normal operation of the I/O pin will be overridden when the fuse is programmed.
Any clock source, including the internal oscillators, can be selected when the clock is output on CLKO. If the System
Clock Prescaler is used, it is the divided system clock that is output.
6.5 Register Description
6.5.1 CLKSR – Clock Setting Register
• Bit 7 – OSCRDY: Oscillator Ready
This bit is set when oscillator time-out is complete. When OSCRDY is set the oscillator is stable and the clock
source can be changed safely.
• Bit 6 – CSTR: Clock Select Trigger
This bit triggers the clock selection. It can be used to enable the oscillator in advance and select the clock source,
before the oscillator is stable.
If CSTR is set at the same time as the CKSEL bits are written, the contents are directly copied to the CKSEL register
and the system clock is immediately switched.
If CKSEL bits are written without setting CSTR, the oscillator selected by the CKSEL bits is enabled, but the system
clock is not switched yet.
• Bit 5 – CKOUT_IO: Clock Output
This bit enables the clock output buffer. The CKOUT fuse determines the initial value of the CKOUT_IO bit that is
loaded to the CLKSR register when the device is powered up or has been reset
• Bit 4 – SUT: Start-Up Time
The SUT and CKSEL bits define the start-up time of the device, as shown in Table 6-2, below. The initial value of
the SUT bit is determined by the SUT fuse. The SUT fuse is loaded to the SUT bit when the device is powered up
or has been reset.
Bit 7 6 5 4 3 2 1 0
0x32 (0x52) OSCRDY CSTR CKOUT_IO SUT CKSEL3 CKSEL2 CKSEL1 CKSEL0 CLKSR
Read/Write R W R R R/W R/W R/W R/W
Initial Value 0 0 0 See Bit DescriptionATtiny1634 [DATASHEET] 30
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Note: 1. Device start-up time from power-down sleep mode.
2. When BOD has been disabled by software, the wake-up time from sleep mode will be approximately 60µs to
ensure the BOD is working correctly before MCU continues executing code.
3. Device start-up time after reset.
4. The device is shipped with this option selected.
5. This option is not suitable for use with crystals.
6. This option should not be used when operating close to the maximum frequency of the device, and only if frequency
stability at start-up is not important for the application.
7. This option is intended for use with ceramic resonators and will ensure frequency stability at start-up. It can also be
used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at
start-up is not important for the application.
• Bits 3:0 – CKSEL[3:0]: Clock Select Bits
These bits select the clock source of the system clock and can be written at run-time. The clock system ensures
glitch free switching of the clock source. CKSEL fuses determine the initial value of the CKSEL bits when the
device is powered up or reset.
The clock alternatives are shown in Table 6-3 below.
Table 6-2. Device Start-up Times
SUT CKSEL Clock From Power-Down (1)(2) From Reset (3)
0 (4)
0000 External 6 CK 22 CK + 16ms
0010 (4) Internal 8MHz 6 CK 20 CK + 16ms
0100 Internal 32kHz 6 CK 22 CK + 16ms
0001
0011
0101 ... 0111
Reserved
1XX0 Ceramic resonator (5) 258 CK (6) 274 CK + 16ms
1XX1 Crystal oscillator 16K CK 16K CK + 16 ms
1
0000 ... 0111
1XX1 Reserved
1XX0 Ceramic resonator 1K CK (7) 1K CK +16ms
Table 6-3. Device Clocking Options
CKSEL[3:0] (1) Frequency Device Clocking Option
0000 Any External Clock (see page 26)
0010 8MHz Calibrated Internal 8MHz Oscillator (see page 27) (2)
0100 32kHz Internal 32kHz Ultra Low Power (ULP) Oscillator (see page 27)
00X1
0101 ... 0111 — Reserved
100X 0.4...0.9MHz
Crystal Oscillator / Ceramic Resonator (see page 27)
101X 0.9...3MHz
110X 3...8MHz
111X > 8MHzATtiny1634 [DATASHEET] 31
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Note: 1. For all fuses “1” means unprogrammed and “0” means programmed.
2. This is the default setting. The device is shipped with this fuse combination.
To avoid unintentional switching of clock source, a protected change sequence must be followed to change the
CKSEL bits, as follows:
1. Write the signature for change enable of protected I/O register to register CCP.
2. Within four instruction cycles, write the CKSEL bits with the desired value.
6.5.2 CLKPR – Clock Prescale Register
• Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system clock. These bits
can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the
master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used.
The division factors are given in Table 6-4 on page 31.
To avoid unintentional changes of clock frequency, a protected change sequence must be followed to change the
CLKPS bits:
1. Write the signature for change enable of protected I/O register to register CCP.
2. Within four instruction cycles, write the desired value to CLKPS bits.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted.
Bit 7 6 5 4 3 2 1 0
0x33 (0x53) – – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 See Bit Description
Table 6-4. Clock Prescaler Select
CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor
0 0 0 0 1 (1)
0001 2
0010 4
0 0 1 1 8 (2)
0 1 0 0 16
0 1 0 1 32
0 1 1 0 64
0 1 1 1 128
1 0 0 0 256ATtiny1634 [DATASHEET] 32
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Note: 1. This is the initial value when CKDIV8 fuse has been unprogrammed.
2. This is the initial value when CKDIV8 fuse has been programmed. The device is shipped with the CKDIV8 Fuse
programmed.
The initial value of clock prescaler bits is determined by the CKDIV8 fuse (see Table 22-5 on page 210). When
CKDIV8 is unprogrammed, the system clock prescaler is set to one and, when programmed, to eight. Any value
can be written to the CLKPS bits regardless of the CKDIV8 fuse bit setting.
When CKDIV8 is programmed the initial value of CLKPS bits give a clock division factor of eight at start up. This is
useful when the selected clock source has a higher frequency than allowed under present operating conditions.
See “Speed” on page 229.
6.5.3 OSCCAL0 – Oscillator Calibration Register
Although temperature slope and frequency are in part controlled by registers OSCTCAL0A and OSCTCAL0B it is
possible to replace factory calibration by simply writing to this register alone. Optimal accuracy is achieved when
OSCCAL0, OSCTAL0A and OSCTCAL0B are calibrated together.
• Bits 7:0 – CAL0[7:0]: Oscillator Calibration Value
The oscillator calibration register is used to trim the internal 8MHz oscillator and to remove process variations from
the oscillator frequency. A pre-programmed calibration value is automatically written to this register during chip
reset, giving the factory calibrated frequency specified in Table 24-2 on page 230.
The application software can write this register to change the oscillator frequency. The oscillator can be calibrated
to frequencies specified in Table 24-2 on page 230. Calibration outside that range is not guaranteed.
The lowest oscillator frequency is reached by programming these bits to zero. Increasing the register value
increases the oscillator frequency. A typical frequency response curve is shown in “Calibrated Oscillator Frequency
(Nominal = 8MHz) vs. OSCCAL Value” on page 273.
Note that this oscillator is used to time EEPROM and Flash write accesses, and write times will be affected accordingly.
Do not calibrate to more than 8.8MHz if EEPROM or Flash is to be written. Otherwise, the EEPROM or Flash
write may fail.
To ensure stable operation of the MCU the calibration value should be changed in small steps. A step change in
frequency of more than 2% from one cycle to the next can lead to unpredictable behavior. Also, the difference
between two consecutive register values should not exceed 0x20. If these limits are exceeded the MCU must be
kept in reset during changes to clock frequency.
1001
Reserved
1010
1011
1100
1101
1110
1111
Table 6-4. Clock Prescaler Select (Continued)
CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor
Bit 7 6 5 4 3 2 1 0
(0x63) CAL07 CAL06 CAL05 CAL04 CAL03 CAL02 CAL01 CAL00 OSCCAL0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value Device Specific Calibration ValueATtiny1634 [DATASHEET] 33
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
6.5.4 OSCTCAL0A – Oscillator Temperature Calibration Register A
This register is used for changing the temperature slope and frequency of the internal 8MHz oscillator. A pre-programmed
calibration value is automatically written to this register during chip reset, giving the factory calibrated
frequency specified in Table 24-2 on page 230.
This register need not be updated if factory defaults in OSCCAL0 are overwritten although optimal accuracy is
achieved when OSCCAL0, OSCTAL0A and OSCTCAL0B are calibrated together.
• Bit 7 – Sign of Oscillator Temperature Calibration Value
This is the sign bit of the calibration data.
• Bits 6:0 – Oscillator Temperature Calibration Value
These bits contain the numerical value of the calibration data.
6.5.5 OSCTCAL0B – Oscillator Temperature Calibration Register B
A pre-programmed calibration value is automatically written to this register during chip reset, giving the factory calibrated
frequency specified in Table 24-2 on page 230.
This register need not be updated if factory defaults in OSCCAL0 are overwritten although optimal accuracy is
achieved when OSCCAL0, OSCTAL0A and OSCTCAL0B are calibrated together.
• Bit 7 – Temperature Compensation Enable
When this bit is set the contents of registers OSCTCAL0A and OSCTCAL0B are used for calibration. When this bit
is cleared the temperature compensation hardware is disabled and registers OSCTCAL0A and OSCTCAL0B have
no effect on the frequency of the internal 8MHz oscillator.
Note that temperature compensation has a large effect on oscillator frequency and, hence, when enabled or disabled
the OSCCAL0 register must also be adjusted to compensate for this effect.
• Bits 6:0 – Temperature Compensation Step Adjust
These bits control the step size of the calibration data in OSCTCAL0A. The largest step size is achieved for 0x00
and smallest step size for 0x7F.
6.5.6 OSCCAL1 – Oscillator Calibration Register
• Bits 7:2 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bit 7 6 5 4 3 2 1 0
(0x64) Oscillator Temperature Calibration Data OSCTCAL0A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value Device Specific Calibration Value
Bit 7 6 5 4 3 2 1 0
(0x65) Oscillator Temperature Calibration Data OSCTCAL0B
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value Device Specific Calibration Value
Bit 7 6 5 4 3 2 1 0
(0x66) – – – – – – CAL11 CAL10 OSCCAL1
Read/Write R R R R R R R/W R/W
Initial Value Device Specific Calibration ValueATtiny1634 [DATASHEET] 34
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
• Bits 1:0 – CAL1[1:0]: Oscillator Calibration Value
The oscillator calibration register is used to trim the internal 32kHz oscillator and to remove process variations from
the oscillator frequency. A pre-programmed calibration value is automatically written to this register during chip
reset, giving the factory calibrated frequency as specified in Table 24-3 on page 231.
The application software can write this register to change the oscillator frequency. The oscillator can be calibrated
to frequencies as specified in Table 24-3 on page 231. Calibration outside that range is not guaranteed.
The lowest oscillator frequency is reached by programming these bits to zero. Increasing the register value
increases the oscillator frequency.
7. Power Management and Sleep Modes
The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low
power applications. In addition, sleep modes enable the application to shut down unused modules in the MCU,
thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to
the application’s requirements.
7.1 Sleep Modes
Figure 6-1 on page 25 presents the different clock systems and their distribution in ATtiny1634. The figure is helpful
in selecting an appropriate sleep mode. Table 7-1 shows the different sleep modes and the sources that may be
used for wake up.
Note: 1. Start frame detection, only.
2. Start condition, only.
3. Address match interrupt, only.
4. For INT0 level interrupt, only.
To enter a sleep mode, the SE bit in MCUCR must be set and a SLEEP instruction must be executed. The SMn
bits in MCUCR select which sleep mode will be activated by the SLEEP instruction. See Table 7-2 on page 37 for
a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for
four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction
following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from
sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.
Table 7-1. Active Clock Domains and Wake-up Sources in Different Sleep Modes
Sleep Mode
Oscillators Active Clock Domains Wake-up Sources Main Clock Source Enabled clkCPU clkFLASH clkIO clkADC Watchdog Interrupt INT0 and Pin Change SPM/EEPROM Ready Interrupt ADC Interrupt USART USI
TWI Slave
Other I/O
Idle X X X X X X X X X X X
ADC Noise
Reduction X X X X (4) X X X (1) X (2) X (3)
Standby X X X (4) X (1) X (2) X (3)
Power-down X X (4) X (1) X (2) X (3)ATtiny1634 [DATASHEET] 35
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Note that if a level triggered interrupt is used for wake-up the changed level must be held for some time to wake up
the MCU (and for the MCU to enter the interrupt service routine). See “External Interrupts” on page 48 for details.
7.1.1 Idle Mode
This sleep mode basically halts clkCPU and clkFLASH, while allowing other clocks to run. In Idle Mode, the CPU is
stopped but the following peripherals continue to operate:
• Watchdog and interrupt system
• Analog comparator, and ADC
• USART, TWI, and timer/counters
Idle mode allows the MCU to wake up from external triggered interrupts as well as internal ones, such as Timer
Overflow. If wake-up from the analog comparator interrupt is not required, the analog comparator can be powered
down by setting the ACD bit in ACSRA. See “ACSRA – Analog Comparator Control and Status Register” on page
182. This will reduce power consumption in Idle mode.
If the ADC is enabled, a conversion starts automatically when this mode is entered.
7.1.2 ADC Noise Reduction Mode
This sleep mode halts clkI/O, clkCPU, and clkFLASH, while allowing other clocks to run. In ADC Noise Reduction
mode, the CPU is stopped but the following peripherals continue to operate:
• Watchdog (if enabled), and external interrupts
• ADC
• USART start frame detector, and TWI
This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is
enabled, a conversion starts automatically when this mode is entered.
The following events can wake up the MCU:
• Watchdog reset, external reset, and brown-out reset
• External level interrupt on INT0, and pin change interrupt
• ADC conversion complete interrupt, and SPM/EEPROM ready interrupt
• USI start condition, USART start frame detection, and TWI address match
7.1.3 Power-Down Mode
This sleep mode halts all generated clocks, allowing operation of asynchronous modules, only. In Power-down
Mode the oscillator is stopped, while the following peripherals continue to operate:
• Watchdog (if enabled), external interrupts
The following events can wake up the MCU:
• Watchdog reset, external reset, and brown-out reset
• External level interrupt on INT0, and pin change interrupt
• USI start condition, USART start frame detection, and TWI address matchATtiny1634 [DATASHEET] 36
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
7.1.4 Standby Mode
Standby Mode is identical to power-down, with the exception that the oscillator is kept running. From Standby
mode, the device wakes up in six clock cycles.
7.2 Power Reduction Register
The Power Reduction Register (PRR), see “PRR – Power Reduction Register” on page 38, provides a method to
reduce power consumption by stopping the clock to individual peripherals. When the clock for a peripheral is
stopped then:
• The current state of the peripheral is frozen.
• The associated registers can not be read or written.
• Resources used by the peripheral will remain occupied.
The peripheral should in most cases be disabled before stopping the clock. Clearing the PRR bit wakes up the
peripheral and puts it in the same state as before shutdown.
Peripheral shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption.
In all other sleep modes, the clock is already stopped.
7.3 Minimizing Power Consumption
There are several issues to consider when trying to minimize the power consumption in an AVR controlled system.
In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as
few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular,
the following modules may need special consideration when trying to achieve the lowest possible power
consumption.
7.3.1 Analog to Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering
any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion.
See “Analog to Digital Converter” on page 185 for details on ADC operation.
7.3.2 Analog Comparator
When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise
Reduction mode, the Analog Comparator should be disabled. In the other sleep modes, the Analog Comparator is
automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as
input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will
be enabled, independent of sleep mode. See “Analog Comparator” on page 181 for details on how to configure the
Analog Comparator.
7.3.3 Brown-out Detector
If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detector
is enabled by the BODPD Fuses, it will be enabled in all sleep modes, and hence, always consume power. In
the deeper sleep modes, this will contribute significantly to the total current consumption. If the Brown-out Detector
is needed in the application, this module can also be set to Sampled BOD mode to save power. See “Brown-Out
Detection” on page 41 for details on how to configure the Brown-out Detector.
7.3.4 Internal Voltage Reference
The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator
or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be
disabled and it will not be consuming power. When turned on again, the user must allow the reference to start upATtiny1634 [DATASHEET] 37
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. See Internal
Bandgap Reference in Table 24-5 on page 231 for details on the start-up time.
7.3.5 Watchdog Timer
If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is
enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this
will contribute to the total current consumption. See “Watchdog Timer” on page 43 for details on how to configure
the Watchdog Timer.
7.3.6 Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing
is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clkI/O) and the ADC
clock (clkADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed
by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and
it will then be enabled. See the section “Digital Input Enable and Sleep Modes” on page 58 for details on which pins
are enabled. If the input buffer is enabled and the input signal is left floating or has an analog signal level close to
VCC/2, the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC/2
on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to
the Digital Input Disable Register (DIDR0). See “DIDR0 – Digital Input Disable Register 0” on page 200 for details.
7.3.7 On-chip Debug System
If the On-chip debug system is enabled by the DWEN Fuse and the chip enters sleep mode, the main clock source
is enabled and hence always consumes power. In the deeper sleep modes, this will contribute significantly to the
total current consumption.
7.4 Register Description
7.4.1 MCUCR – MCU Control Register
The MCU Control Register contains control bits for power management.
• Bits 7, 3:2 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 6:5 – SM[1:0]: Sleep Mode Select Bits 1 and 0
These bits select between available sleep modes, as shown in Table 7-2.
Bit 7 6 5 4 3 2 1 0
0x36 (0x56) – SM1 SM0 SE – – ISC01 ISC00 MCUCR
Read/Write R R/W R/W R/W R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 7-2. Sleep Mode Select
SM1 SM0 Sleep Mode
0 0 Idle
0 1 ADC Noise Reduction
1 0 Power-down
1 1 Standby(1)ATtiny1634 [DATASHEET] 38
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Note: 1. Only recommended with external crystal or resonator selected as clock source
• Bit 4 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.
To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to
write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately
after waking up.
7.4.2 PRR – Power Reduction Register
The Power Reduction Register provides a method to reduce power consumption by allowing peripheral clock signals
to be disabled.
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit and will always read zero.
• Bit 6 – PRTWI: Power Reduction Two-Wire Interface
Writing a logic one to this bit shuts down the Two-Wire Interface module.
• Bit 5 – PRTIM1: Power Reduction Timer/Counter1
Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation
will continue like before the shutdown.
• Bit 4 – PRTIM0: Power Reduction Timer/Counter0
Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation
will continue like before the shutdown.
• Bit 3 – PRUSI: Power Reduction USI
Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When waking up the USI
again, the USI should be re initialized to ensure proper operation.
• Bit 2 – PRUSART1: Power Reduction USART1
Writing a logic one to this bit shuts down the USART1 module. When the USART1 is enabled, operation will continue
like before the shutdown.
• Bit 1 – PRUSART0: Power Reduction USART0
Writing a logic one to this bit shuts down the USART0 module. When the USART0 is enabled, operation will continue
like before the shutdown.
• Bit 0 – PRADC: Power Reduction ADC
Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator
cannot be used when the ADC is shut down.
Bit 7 6 5 4 3 2 1 0
0x34 (0x54) – PRTWI PRTIM1 PRTIM0 PRUSI PRUSART1 PRUSART0 PRADC PRR
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0ATtiny1634 [DATASHEET] 39
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
8. System Control and Reset
8.1 Resetting the AVR
During reset, all I/O registers are set to their initial values, and the program starts execution from the Reset Vector.
The instruction placed at the Reset Vector should be a JMP (two-word, direct jump) instruction to the reset handling
routine, although other one- or two-word jump instructions can be used. If the program never enables an
interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations.
The circuit diagram in Figure 8-1 shows the reset logic. Electrical parameters of the reset circuitry are defined in
section “System and Reset” on page 231.
Figure 8-1. Reset Logic
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not
require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the
power to reach a stable level before normal operation starts.
8.2 Reset Sources
The ATtiny1634 has four sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT)
• External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum
pulse length when RESET function is enabled
• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled
• Brown-out Reset. The MCU is reset when the supply voltage VCC is below the Brown-out Reset threshold (VBOT)
and the Brown-out Detector is enabled
8.2.1 Power-on Reset
A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detection level is defined in “System
and Reset” on page 231. The POR is activated whenever VCC is below the detection level. The POR circuit can
be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset
threshold voltage invokes the delay counter, which determines how long the device is kept in reset after VCC rise.
The reset signal is activated again, without any delay, when VCC decreases below the detection level.
DATA BUS
RESET FLAG REGISTER RESET FLAG REGISTER
(RSTFLR) (RSTFLR)
POWER-ON POWER-ON RESET CIRCUIT RESET CIRCUIT
PULL-UP PULL-UP
RESISTOR RESISTOR
BODLEVEL2...0 BODLEVEL2...0
VCC
SPIKE
FILTER RESET
EXTERNAL EXTERNAL
RESET CIRCUIT RESET CIRCUIT
BROWN OUT BROWN OUT RESET CIRCUIT RESET CIRCUIT
RSTDISBL RSTDISBL
WATCHDOG WATCHDOG
TIMER
DELAY
COUNTERS COUNTERS
S
R
Q
WATCHDOG WATCHDOG OSCILLATOR OSCILLATOR
CLOCK GENERATOR GENERATOR
BORF
PORF
EXTRF
WDRF
INTERNAL INTERNAL
RESET
CK
TIMEOUT TIMEOUT
COUNTER RESET COUNTER RESETATtiny1634 [DATASHEET] 40
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 8-2. MCU Start-up, RESET Tied to VCC
Figure 8-3. MCU Start-up, RESET Extended Externally
8.2.2 External Reset
An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer than the minimum
pulse width (see section “System and Reset” on page 231) will generate a reset, even if the clock is not running.
Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage
– VRST – on its positive edge, the delay counter starts the MCU after the time-out period – tTOUT – has expired.
External reset is ignored during Power-on start-up count. After Power-on reset the internal reset is extended only if
RESET pin is low when the initial Power-on delay count is complete. See Figure 8-2 and Figure 8-3.
Figure 8-4. External Reset During Operation
V
TIME-OUT
RESET
RESET
TOUT
INTERNAL
t
VPOT
VRST
CC
V
TIME-OUT
TOUT
TOUT
INTERNAL
CC
t
VPOT
VRST
> t
RESET
RESET
CCATtiny1634 [DATASHEET] 41
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
8.2.3 Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse. On the falling edge of this pulse, the delay timer
starts counting the time-out period tTOUT. See page 43 for details on operation of the Watchdog Timer and Table
24-5 on page 231 for details on reset time-out.
Figure 8-5. Watchdog Reset During Operation
8.2.4 Brown-Out Detection
The Brown-Out Detection (BOD) circuit monitors that the VCC level is kept above a configurable trigger level, VBOT.
When the BOD is enabled, a BOD reset will be given when VCC falls and remains below the trigger level for the
length of the detection time, tBOD. The reset is kept active until VCC again rises above the trigger level.
Figure 8-6. Brown-out Detection reset.
The BOD circuit will not detect a drop in VCC unless the voltage stays below the trigger level for the detection time,
tBOD (see “System and Reset” on page 231).
The BOD circuit has three modes of operation:
• Disabled: In this mode of operation VCC is not monitored and, hence, it is recommended only for applications
where the power supply remains stable.
CK
CC
VCC
TIME-OUT
INTERNAL
RESET
VBOTVBOT+
t
TOUT
t
BODATtiny1634 [DATASHEET] 42
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
• Enabled: In this mode the VCC level is continuously monitored. If VCC drops below VBOT for at least tBOD a
brown-out reset will be generated.
• Sampled: In this mode the VCC level is sampled on each negative edge of a 1kHz clock that has been derived
from the 32kHz ULP oscillator. Between each sample the BOD is turned off. Compared to the mode where BOD
is constantly enabled this mode of operation reduces power consumption but fails to detect drops in VCC
between two positive edges of the 1kHz clock. When a brown-out is detected in this mode, the BOD circuit is set
to enabled mode to ensure that the device is kept in reset until VCC has risen above VBOT . The BOD will return
to sampled mode after reset has been released and the fuses have been read in.
The BOD mode of operation is selected using BODACT and BODPD fuse bits. The BODACT fuse bits determine
how the BOD operates in active and idle mode, as shown in Table 8-1.
The BODPD fuse bits determine the mode of operation in all sleep modes except idle mode, as shown in Table 8-
2.
See “Fuse Bits” on page 209.
8.3 Internal Voltage Reference
ATtiny1634 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be
used as an input to the Analog Comparator or the ADC. The bandgap voltage varies with supply voltage and
temperature.
8.3.1 Voltage Reference Enable Signals and Start-up Time
The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given
in “System and Reset” on page 231. To save power, the reference is not always turned on. The reference is on
during the following situations:
1. When the BOD is enabled (see “Brown-Out Detection” on page 41).
2. When the internal reference is connected to the Analog Comparator (by setting the ACBG bit in ACSRA).
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow
the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power conTable
8-1. Setting BOD Mode of Operation in Active and Idle Modes
BODACT1 BODACT0 Mode of Operation
0 0 Reserved
0 1 Sampled
1 0 Enabled
1 1 Disabled
Table 8-2. Setting BOD Mode of Operation in Sleep Modes Other Than Idle
BODPD1 BODPD0 Mode of Operation
0 0 Reserved
0 1 Sampled
1 0 Enabled
1 1 DisabledATtiny1634 [DATASHEET] 43
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
sumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is
turned off before entering Power-down mode.
8.4 Watchdog Timer
The Watchdog Timer is clocked from the internal 32kHz ultra low power oscillator (see page 27). By controlling the
Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 8-5 on page 46. The
WDR – Watchdog Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled
and when a Chip Reset occurs. Ten different clock cycle periods can be selected to determine the reset
period. If the reset period expires without another Watchdog Reset, the ATtiny1634 resets and executes from the
Reset Vector. For timing details on the Watchdog Reset, refer to Table 8-5 on page 46.
The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can be very helpful
when using the Watchdog to wake-up from Power-down.
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, two different safety
levels are selected by the fuse WDTON as shown in Table 8-3 See “Timed Sequences for Changing the Configuration
of the Watchdog Timer” on page 43 for details.
Figure 8-7. Watchdog Timer
8.4.1 Timed Sequences for Changing the Configuration of the Watchdog Timer
The sequence for changing configuration differs slightly between the two safety levels. Separate procedures are
described for each level.
• Safety Level 1
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to one without
any restriction. A timed sequence is needed when disabling an enabled Watchdog Timer. To disable an
enabled Watchdog Timer, the following procedure must be followed:
Table 8-3. WDT Configuration as a Function of the Fuse Settings of WDTON
WDTON
Safety
Level
WDT Initial
State
How to Disable the
WDT
How to Change Timeout
Unprogrammed 1 Disabled Timed sequence No limitations
Programmed 2 Enabled Always enabled Timed sequence OSC/512 OSC/1K OSC/2K OSC/4K OSC/8K OSC/16K OSC/32K OSC/64K OSC/128K OSC/256K
MCU RESET
WATCHDOG
PRESCALER
32 kHz
ULP OSCILLATOR
WATCHDOG
RESET
WDP0
WDP1
WDP2
WDP3
WDE
MUXATtiny1634 [DATASHEET] 44
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
a. Write the signature for change enable of protected I/O registers to register CCP
b. Within four instruction cycles, in the same operation, write WDE and WDP bits
• Safety Level 2
In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed
sequence is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the
following procedure must be followed:
a. Write the signature for change enable of protected I/O registers to register CCP
b. Within four instruction cycles, write the WDP bit. The value written to WDE is irrelevant
8.4.2 Code Examples
The following code example shows how to turn off the WDT. The example assumes that interrupts are controlled
(e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions.
Note: See “Code Examples” on page 6.
8.5 Register Description
8.5.1 MCUSR – MCU Status Register
The MCU Status Register provides information on which reset source caused an MCU Reset.
• Bits 7:4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny1634 and will always read as zero.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the
flag.
Assembly Code Example
WDT_off:
wdr
; Clear WDRF in RSTFLR
in r16, RSTFLR
andi r16, ~(1< ; Address 0x0038
...ATtiny1634 [DATASHEET] 49
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
The pin change interrupts trigger as follows:
• Pin Change Interrupt 0 (PCI0): triggers if any enabled PCINT[7:0] pin toggles
• Pin Change Interrupt 1 (PCI1): triggers if any enabled PCINT[11:8] pin toggles
• Pin Change Interrupt 2 (PCI2): triggers if any enabled PCINT[17:12] pin toggles
Registers PCMSK0, PCMSK1, and PCMSK2 control which pins contribute to the pin change interrupts.
Pin change interrupts on PCINT[17:0] are detected asynchronously, which means that these interrupts can be
used for waking the part also from sleep modes other than Idle mode.
External interrupt INT0 can be triggered by a falling or rising edge, or a low level. See “MCUCR – MCU Control
Register” on page 37. When INT0 is enabled and configured as level triggered, the interrupt will trigger as long as
the pin is held low.
Note that recognition of falling or rising edge interrupts on INT0 requires the presence of an I/O clock, as described
in “Clock System” on page 24.
9.2.1 Low Level Interrupt
A low level interrupt on INT0 is detected asynchronously. This means that the interrupt source can be used for
waking the part also from sleep modes other than Idle (the I/O clock is halted in all sleep modes except Idle).
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long
enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of
the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the
SUT and CKSEL fuses, as described in “Clock System” on page 24.
If the low level on the interrupt pin is removed before the device has woken up then program execution will not be
diverted to the interrupt service routine but continue from the instruction following the SLEEP command.
9.2.2 Pin Change Interrupt Timing
A timing example of a pin change interrupt is shown in Figure 9-1.ATtiny1634 [DATASHEET] 50
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 9-1. Timing of pin change interrupts
clk
PCINT(0)
pin_lat
pin_sync
pcint_in_(0)
pcint_syn
pcint_setflag
PCIF
PCINT(0)
pin_sync
pcint_syn pin_lat
D Q
LE
pcint_setflag
PCIF
clk
clk PCINT(0) in PCMSK(x)
pcint_in_(0) 0
xATtiny1634 [DATASHEET] 51
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
9.3 Register Description
9.3.1 MCUCR – MCU Control Register
• Bits 1:0 – ISC0[1:0]: Interrupt Sense Control 0 Bit 1 and Bit 0
External Interrupt 0 is triggered by activity on pin INT0, provided that the SREG I-flag and the corresponding interrupt
mask are set. The conditions required to trigger the interrupt are defined in Table 9-2.
Note: 1. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction
to generate an interrupt.
2. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last
longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
9.3.2 GIMSK – General Interrupt Mask Register
• Bits 7, 2:0 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 6 – INT0: External Interrupt Request 0 Enable
The external interrupt for pin INT0 is enabled when this bit and the I-bit in the Status Register (SREG) are set. The
trigger conditions are set with the ISC0n bits.
Activity on the pin will cause an interrupt request even if INT0 has been configured as an output.
• Bit 5 – PCIE2: Pin Change Interrupt Enable 2
When this bit and the I-bit of SREG are set the Pin Change Interrupt 2 is enabled. Any change on an enabled
PCINT[17:12] pin will cause a PCINT2 interrupt. See Table 9-1 on page 47.
Each pin can be individually enabled. See “PCMSK2 – Pin Change Mask Register 2” on page 52.
• Bit 4 – PCIE1: Pin Change Interrupt Enable 1
When this bit and the I-bit of SREG are set the Pin Change Interrupt 1 is enabled. Any change on an enabled
PCINT[11:8] pin will cause a PCINT1 interrupt. See Table 9-1 on page 47.
Each pin can be individually enabled. See “PCMSK1 – Pin Change Mask Register 1” on page 53.
Bit 7 6 5 4 3 2 1 0
0x36 (0x56) – SM1 SM0 SE – – ISC01 ISC00 MCUCR
Read/Write R R/W R/W R/W R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 9-2. External Interrupt 0 Sense Control
ISC01 ISC00 Description
0 0 The low level of INT0 generates an interrupt request (1)
0 1 Any logical change on INT0 generates an interrupt request (2)
1 0 The falling edge of INT0 generates an interrupt request (2)
1 1 The rising edge of INT0 generates an interrupt request (2)
Bit 7 6 5 4 3 2 1 0
0x3C (0x5C) – INT0 PCIE2 PCIE1 PCIE0 – – – GIMSK
Read/Write R R/W R/W R/W R/W R R R
Initial Value 0 0 0 0 0 0 0 0ATtiny1634 [DATASHEET] 52
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
• Bit 3 – PCIE0: Pin Change Interrupt Enable 0
When this bit and the I-bit of SREG are set the Pin Change Interrupt 0 is enabled. Any change on an enabled
PCINT[7:0] pin will cause a PCINT0 interrupt. See Table 9-1 on page 47.
Each pin can be individually enabled. See “PCMSK0 – Pin Change Mask Register 0” on page 53.
9.3.3 GIFR – General Interrupt Flag Register
• Bits 7, 2:0 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bit 6 – INTF0: External Interrupt Flag 0
This bit is set when activity on INT0 has triggered an interrupt request. Provided that the I-bit in SREG and the
INT0 bit in GIMSK are set, the MCU will jump to the corresponding interrupt vector.
The flag is cleared when the interrupt service routine is executed. Alternatively, the flag can be cleared by writing a
logical one to it.
This flag is always cleared when INT0 is configured as a level interrupt.
• Bit 5 – PCIF2: Pin Change Interrupt Flag 2
This bit is set when a logic change on any PCINT[17:12] pin has triggered an interrupt request. Provided that the Ibit
in SREG and the PCIE2 bit in GIMSK are set, the MCU will jump to the corresponding interrupt vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical
one to it.
• Bit 4 – PCIF1: Pin Change Interrupt Flag 1
This bit is set when a logic change on any PCINT[11:8] pin has triggered an interrupt request. Provided that the Ibit
in SREG and the PCIE1 bit in GIMSK are set, the MCU will jump to the corresponding interrupt vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical
one to it.
• Bit 3 – PCIF0: Pin Change Interrupt Flag 0
This bit is set when a logic change on any PCINT[7:0] pin has triggered an interrupt request. Provided that the I-bit
in SREG and the PCIE0 bit in GIMSK are set, the MCU will jump to the corresponding interrupt vector.
The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical
one to it.
9.3.4 PCMSK2 – Pin Change Mask Register 2
• Bits 7:6 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bit 7 6 5 4 3 2 1 0
0x3B (0x5B) – INTF0 PCIF2 PCIF1 PCIF0 – – – GIFR
Read/Write R R/W R/W R/W R/W R R R
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x29 (0x49) – – PCINT17 PCINT16 PCINT15 PCINT14 PCINT13 PCINT12 PCMSK2
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0ATtiny1634 [DATASHEET] 53
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
• Bits 5:0 – PCINT[17:12]: Pin Change Enable Mask 17:12
Each PCINTn bit selects if the pin change interrupt of the corresponding I/O pin is enabled. Pin change interrupt on
a pin is enabled by setting the mask bit for the pin (PCINTn) and the corresponding group bit (PCIEn) in GIMSK.
When this bit is cleared the pin change interrupt on the corresponding pin is disabled.
9.3.5 PCMSK1 – Pin Change Mask Register 1
• Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 3:0 – PCINT[11:8]: Pin Change Enable Mask 11:8
Each PCINTn bit selects if the pin change interrupt of the corresponding I/O pin is enabled. Pin change interrupt on
a pin is enabled by setting the mask bit for the pin (PCINTn) and the corresponding group bit (PCIEn) in GIMSK.
When this bit is cleared the pin change interrupt on the corresponding pin is disabled.
9.3.6 PCMSK0 – Pin Change Mask Register 0
• Bits 7:0 – PCINT[7:0]: Pin Change Enable Mask 7:0
Each PCINTn bit selects if the pin change interrupt of the corresponding I/O pin is enabled. Pin change interrupt on
a pin is enabled by setting the mask bit for the pin (PCINTn) and the corresponding group bit (PCIEn) in GIMSK.
When this bit is cleared the pin change interrupt on the corresponding pin is disabled.
Bit 7 6 5 4 3 2 1 0
0x28 (0x48) – – – – PCINT11 PCINT10 PCINT9 PCINT8 PCMSK1
Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x27 (0x47) PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0ATtiny1634 [DATASHEET] 54
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
10. I/O Ports
10.1 Overview
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that
the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the
SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling
of pull-up resistors (if configured as input). Most output buffers have symmetrical drive characteristics with
both high sink and source capability, while some are asymmetrical and have high sink and standard source capability.
The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up
resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both VCC and Ground as
indicated in Figure 10-1 on page 54. See “Electrical Characteristics” on page 228 for a complete list of parameters.
Figure 10-1. I/O Pin Equivalent Schematic
All registers and bit references in this section are written in general form. A lower case “x” represents the numbering
letter for the port, and a lower case “n” represents the bit number. However, when using the register or bit
defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented
generally as PORTxn. The physical I/O Registers and bit locations are listed in “” on page 70.
Four I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data
Direction Register – DDRx, Pull-up Enable Register – PUEx, and the Port Input Pins – PINx. The Port Input Pins
I/O location is read only, while the Data Register, the Data Direction Register, and the Pull-Up Enable Register are
read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit
in the Data Register.
Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page 54. Most port pins
are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes
with the port pin is described in “Alternate Port Functions” on page 59. Refer to the individual module sections
for a full description of the alternate functions.
Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port
as general digital I/O.
10.2 Ports as General Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a functional description of
one I/O-port pin, here generically called Pxn.
Cpin
Logic
Rpu
See Figure
"General Digital I/O" for
Details
PxnATtiny1634 [DATASHEET] 55
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 10-2. General Digital I/O(1)
Note: 1. WEx, WRx, WPx, WDx, REx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, and SLEEP
are common to all ports.
10.2.1 Configuring the Pin
Each port pin consists of four register bits: DDxn, PORTxn, PUExn, and PINxn. As shown in “Register Description”
on page 71, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, the
PUExn bits at the PUEx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured
as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If
PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).
clk
RPx
RRx
RDx
WDx
SYNCHRONIZER
clkI/O: I/O CLOCK
D
L
Q
Q
RESET
RESET
Q
D Q
Q
Q D
CLR
PORTxn
Q
Q D
CLR
DDxn
PINxn
DATA BUS
SLEEP
SLEEP: SLEEP CONTROL
Pxn
I/O
WPx
0
1
WRx
WEx
REx
RESET
Q
Q D
CLR
PUExn
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
RDx: READ DDRx
WEx: WRITE PUEx
REx: READ PUEx
WPx: WRITE PINx REGISTERATtiny1634 [DATASHEET] 56
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
The pull-up resistor is activated, if the PUExn is written logic one. To switch the pull-up resistor off, PUExn has to
be written logic zero.
Table 10-1 summarizes the control signals for the pin value.
Port pins are tri-stated when a reset condition becomes active, even when no clocks are running.
10.2.2 Toggling the Pin
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI
instruction can be used to toggle one single bit in a port.
10.2.3 Break-Before-Make Switching
In Break-Before-Make mode, switching the DDRxn bit from input to output introduces an immediate tri-state period
lasting one system clock cycle, as indicated in Figure 10-3. For example, if the system clock is 4MHz and the
DDRxn is written to make an output, an immediate tri-state period of 250 ns is introduced before the value of
PORTxn is seen on the port pin.
To avoid glitches it is recommended that the maximum DDRxn toggle frequency is two system clock cycles. The
Break-Before-Make mode applies to the entire port and it is activated by the BBMx bit. For more details, see
“PORTCR – Port Control Register” on page 71.
When switching the DDRxn bit from output to input no immediate tri-state period is introduced.
Table 10-1. Port Pin Configurations
DDxn PORTxn PUExn I/O Pull-up Comment
0 X 0 Input No Tri-state (hi-Z)
0 X 1 Input Yes Sources current if pulled low externally
1 0 0 Output No Output low (sink)
1 0 1 Output Yes
NOT RECOMMENDED.
Output low (sink) and internal pull-up active.
Sources current through the internal pull-up
resistor and consumes power constantly
1 1 0 Output No Output high (source)
1 1 1 Output Yes Output high (source) and internal pull-up activeATtiny1634 [DATASHEET] 57
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 10-3. Switching Between Input and Output in Break-Before-Make-Mode
10.2.4 Reading the Pin Value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As
shown in Figure 10-2 on page 55, the PINxn Register bit and the preceding latch constitute a synchronizer. This is
needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces
a delay. Figure 10-4 shows a timing diagram of the synchronization when reading an externally applied pin
value. The maximum and minimum propagation delays are denoted tpd,max and tpd,min respectively.
Figure 10-4. Synchronization when Reading an Externally Applied Pin value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when
the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC
LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at
the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition
on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 10-5
on page 58. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the
delay tpd through the synchronizer is one system clock period.
out DDRx, r16 nop
0x02 0x01
SYSTEM CLK
INSTRUCTIONS
DDRx
intermediate tri-state cycle
out DDRx, r17
PORTx 0x55
0x01
intermediate tri-state cycle
Px0
Px1
tri-state
tri-state tri-state
r17 0x01
r16 0x02
XXX in r17, PINx
0x00 0xFF
INSTRUCTIONS
SYNC LATCH
PINxn
r17
XXX
SYSTEM CLK
tpd, max
tpd, minATtiny1634 [DATASHEET] 58
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 10-5. Synchronization when Reading a Software Assigned Pin Value
10.2.5 Digital Input Enable and Sleep Modes
As shown in Figure 10-2 on page 55, the digital input signal can be clamped to ground at the input of the schmitttrigger.
The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down and Standby
modes to avoid high power consumption if some input signals are left floating, or have an analog signal level close
to VCC/2.
SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled,
SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in
“Alternate Port Functions” on page 59.
If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising
Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding
External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these
sleep mode produces the requested logic change.
10.2.6 Unconnected Pins
If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of
the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to
reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle
mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the
pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use
an external pull-up or pulldown. Connecting unused pins directly to VCC or GND is not recommended, since this
may cause excessive currents if the pin is accidentally configured as an output.
out PORTx, r16 nop in r17, PINx
0xFF
0x00 0xFF
SYSTEM CLK
r16
INSTRUCTIONS
SYNC LATCH
PINxn
r17
t pdATtiny1634 [DATASHEET] 59
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10.2.7 Program Examples
The following code example shows how to set port A pins 0 and 1 high, 2 and 3 low, and define the port pins from
4 to 5 as input with a pull-up assigned to port pin 4. The resulting pin values are read back again, but as previously
discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins.
Note: Two temporary registers are used to minimize the time from pull-ups are set on pins 0, 1 and 4, until the direction bits
are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.
Note: See “Code Examples” on page 6.
10.3 Alternate Port Functions
Most port pins have alternate functions in addition to being general digital I/Os. In Figure 10-6 below is shown how
the port pin control signals from the simplified Figure 10-2 on page 55 can be overridden by alternate functions.
Assembly Code Example
...
; Define pull-ups and set outputs high
; Define directions for port pins
ldi r16,(1<>8);
UBRRnL = (unsigned char)baud;
/* Enable receiver and transmitter */
UCSRnB = (1<> 1) & 0x01;
return ((resh << 8) | resl);
}ATtiny1634 [DATASHEET] 157
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16.8.3 Receive Compete Flag and Interrupt
The USART receiver has one flag that indicates the receiver state.
The Receive Complete flag (RXCn) indicates if there are unread data present in the receive buffer. This flag is set
when unread data exist in the receive buffer, and cleared when the receive buffer is empty (i.e., it does not contain
any unread data). If the receiver is disabled (RXENn = 0), the receive buffer will be flushed and, consequently, the
RXCn bit will become zero.
When the Receive Complete Interrupt Enable (RXCIEn) is set, the USART Receive Complete interrupt will be executed
as long as the RXCn flag is set (and provided that global interrupts are enabled). When interrupt-driven data
reception is used, the receive complete routine must read the received data from UDRn in order to clear the RXCn
flag, otherwise a new interrupt will occur once the interrupt routine terminates.
16.8.4 Receiver Error Flags
The USART Receiver has three Error Flags: Frame Error (FEn), Data OverRun (DORn) and Parity Error (UPEn).
All can be accessed by reading UCSRnA. Common for the Error Flags is that they are located in the receive buffer
together with the frame for which they indicate the error status. Due to the buffering of the Error Flags, the UCSRnA
must be read before the receive buffer (UDRn), since reading the UDRn I/O location changes the buffer read
location. Another equality for the Error Flags is that they can not be altered by software doing a write to the flag
location. However, all flags must be set to zero when the UCSRnA is written for upward compatibility of future
USART implementations. None of the Error Flags can generate interrupts.
The Frame Error (FEn) Flag indicates the state of the first stop bit of the next readable frame stored in the receive
buffer. The FEn Flag is zero when the stop bit was correctly read (as one), and the FEn Flag will be one when the
stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions
and protocol handling. The FEn Flag is not affected by the setting of the USBSn bit in UCSRnC since the Receiver
ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when writing
to UCSRnA.
The Data OverRun (DORn) Flag indicates data loss due to a receiver buffer full condition. A Data OverRun occurs
when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a
new start bit is detected. If the DORn Flag is set there was one or more serial frame lost between the frame last
read from UDRn, and the next frame read from UDRn. For compatibility with future devices, always write this bit to
zero when writing to UCSRnA. The DORn Flag is cleared when the frame received was successfully moved from
the Shift Register to the receive buffer.
The Parity Error (UPEn) Flag indicates that the next frame in the receive buffer had a Parity Error when received. If
Parity Check is not enabled the UPEn bit will always be read zero. For compatibility with future devices, always set
this bit to zero when writing to UCSRnA. For more details see “Parity Bit Calculation” on page 150 and “Parity
Checker” on page 157.
16.8.5 Parity Checker
The parity checker is active when the high USART Parity Mode bit (UPMn1) is set. The type of parity check to be
performed (odd or even) is selected by the UPMn0 bit. When enabled, the parity checker calculates the parity of
the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the
check is stored in the receive buffer together with the received data and stop bits. The Parity Error flag (UPEn) can
then be read by software to check if the frame had a parity error.
If parity checking is enabled, the UPEn bit is set if the next character that can be read from the receive buffer had a
parity error when received. This bit is valid until the receive buffer (UDRn) is read.ATtiny1634 [DATASHEET] 158
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
16.8.6 Disabling the Receiver
Unlike the transmitter, the receiver is disabled immediately and any data from ongoing receptions will be lost.
When disabled (RXENn = 0), the receiver will no longer override the normal function of the RxDn port pin and the
FIFO buffer is flushed, with any remaining data in the buffer lost.
16.8.7 Flushing the Receive Buffer
The receiver buffer FIFO will be flushed when the receiver is disabled, i.e., the buffer will be emptied of its contents.
Unread data will be lost. To flush the buffer during normal operation, due to for instance an error condition, read the
UDRn until the RXCn flag is cleared.
The following code example shows how to flush the receive buffer.
Note: 1. See “Code Examples” on page 6.
16.9 Asynchronous Data Reception
The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The
clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous
serial frames at the RxDn pin. The data recovery logic samples and low pass filters each incoming bit,
thereby improving the noise immunity of the receiver. The asynchronous reception operational range depends on
the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.
16.9.1 Asynchronous Clock Recovery
The clock recovery logic synchronizes the internal clock to the incoming serial frames. Figure 16-5 illustrates the
sampling process of the start bit of an incoming frame. In normal mode the sample rate is 16 times the baud rate,
in double speed mode eight times. The horizontal arrows illustrate the synchronization variation due to the sampling
process. Note the larger time variation when using the double speed mode of operation (U2Xn = 1). Samples
denoted zero are samples done when the RxDn line is idle (i.e., no communication activity).
Assembly Code Example(1)
USART_Flush:
sbis UCSRnA, RXCn
ret
in r16, UDRn
rjmp USART_Flush
C Code Example(1)
void USART_Flush( void )
{
unsigned char dummy;
while ( UCSRnA & (1< max(16fSCL, 250kHz) 0 400 kHz
tHD:STA Hold time (repeated) START Condition 0.6 – µs
tLOW Low period of SCL clock 1.3 – µs
tHIGH High period of SCL clock 0.6 – µs
tSU:STA Set-up time for repeated START condition 0.6 – µs
tHD:DAT Data hold time 0 0.9 µs
tSU:DAT Data setup time 100 – ns
tSU:STO Setup time for STOP condition 0.6 – µs
tBUF Bus free time between STOP and START condition 1.3 – µs
t
SU:STA
t
LOW
t
HIGH
t
LOW
t
OF
t
HD:STA t
HD:DAT t
SU:DAT
t
SU:STO
t
BUF
SCL
SDA
t
RATtiny1634 [DATASHEET] 234
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24.7 Analog to Digital Converter
Table 24-9. ADC Characteristics, Single Ended Channels. T = -40C to +85C
Symbol Parameter Condition Min Typ Max Units
Resolution 10 Bits
Absolute accuracy
(Including INL, DNL, and
Quantization, Gain and Offset
Errors)
VREF = 4V, VCC = 4V,
ADC clock = 200kHz 2.0 LSB
VREF = 4V, VCC = 4V,
ADC clock = 1MHz 2.5 LSB
VREF = 4V, VCC = 4V,
ADC clock = 200kHz
Noise Reduction Mode
1.5 LSB
VREF = 4V, VCC = 4V,
ADC clock = 1MHz
Noise Reduction Mode
2.0 LSB
Integral Non-Linearity (INL)
(Accuracy after Offset and
Gain Calibration)
VREF = 4V, VCC = 4V,
ADC clock = 200kHz 1.0 LSB
Differential Non-linearity
(DNL)
VREF = 4V, VCC = 4V,
ADC clock = 200kHz 0.5 LSB
Gain Error VREF = 4V, VCC = 4V,
ADC clock = 200kHz 2.0 LSB
Offset Error (Absolute) VREF = 4V, VCC = 4V,
ADC clock = 200kHz 1.5 LSB
Conversion Time Free Running Conversion 14 280 µs
Clock Frequency 50 1000 kHz
VIN Input Voltage GND VREF V
Input Bandwidth 38.5 kHz
AREF External Voltage Reference 2.0 VCC V
VINT Internal Voltage Reference 1.0 1.1 1.2 V
RREF Reference Input Resistance 32 k
RAIN Analog Input Resistance 100 M
ADC Conversion Output 0 1023 LSBATtiny1634 [DATASHEET] 235
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
24.8 Analog Comparator
24.9 Temperature Sensor
Note: 1. Firmware calculates temperature based on factory calibration value.
2. Min and max values are not guaranteed. Contact your local Atmel sales office if higher accuracy is required.
24.10 Parallel Programming
Figure 24-4. Parallel Programming Timing, Including some General Timing Requirements
Table 24-10. Analog Comparator Characteristics, TA = -40C to +85C
Symbol Parameter Condition Min Typ Max Units
VAIO Input Offset Voltage VCC = 5V, VIN = VCC / 2 < 10 40 mV
ILAC Input Leakage Current VCC = 5V, VIN = VCC / 2 -50 50 nA
tAPD
Analog Propagation Delay
(from saturation to slight overdrive)
VCC = 2.7V 750
ns
VCC = 4.0V 500
Analog Propagation Delay
(large step change)
VCC = 2.7V 100
VCC = 4.0V 75
tDPD Digital Propagation Delay VCC = 1.8 - 5.5V 1 2 CLK
Table 24-11. Accuracy of Temperature Sensor at Factory Calibration
Symbol Parameter Condition Min Typ Max Units
ATS Accuracy VCC = 4.0, TA = 25C – 85C 10 C
Data & Contol
(DATA, XA0/1, BS1, BS2)
CLKI t
XHXL
t
WLWH
t
DVXH t
XLDX
t
PLWL
t
WLRH
WR
RDY/BSY
PAGEL t
PHPL
t t
BVPH PLBX
t
XLWL
t
WLBX
tBVWL
WLRLATtiny1634 [DATASHEET] 236
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 24-5. Parallel Programming Timing, Loading Sequence with Timing Requirements(1)
Note: 1. The timing requirements shown in Figure 24-4 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation.
Figure 24-6. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing
Requirements(1)
Note: 1. The timing requirements shown in Figure 24-4 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation.
CLKI
PAGEL
t XLXH PLXH t t
XLPH
z
DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)
BS1
XA0
XA1
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
LOAD DATA
(HIGH BYTE)
LOAD DATA LOAD ADDRESS
(LOW BYTE)
CLKI
OE
DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)
BS1
XA0
XA1
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
t
BVDV
t
OLDV
t
XLOL
t
OHDZATtiny1634 [DATASHEET] 237
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands.
2. tWLRH_CE is valid for the Chip Erase command.
Table 24-12. Parallel Programming Characteristics, TA = 25C, VCC = 5V
Symbol Parameter Min Typ Max Units
VPP Programming Enable Voltage 11.5 12.5 V
IPP Programming Enable Current 250 A
tDVXH Data and Control Valid before CLKI High 67 ns
tXLXH CLKI Low to CLKI High 200 ns
tXHXL CLKI Pulse Width High 150 ns
tXLDX Data and Control Hold after CLKI Low 67 ns
tXLWL CLKI Low to WR Low 0 ns
tXLPH CLKI Low to PAGEL high 0 ns
tPLXH PAGEL low to CLKI high 150 ns
tBVPH BS1 Valid before PAGEL High 67 ns
tPHPL PAGEL Pulse Width High 150 ns
tPLBX BS1 Hold after PAGEL Low 67 ns
tWLBX BS2/1 Hold after WR Low 67 ns
tPLWL PAGEL Low to WR Low 67 ns
tBVWL BS1 Valid to WR Low 67 ns
tWLWH WR Pulse Width Low 150 ns
tWLRL WR Low to RDY/BSY Low 0 1 s
tWLRH WR Low to RDY/BSY High(1) 3.7 4.5 ms
tWLRH_CE WR Low to RDY/BSY High for Chip Erase(2) 3.7 9 ms
tXLOL CLKI Low to OE Low 0 ns
tBVDV BS1 Valid to DATA valid 0 250 ns
tOLDV OE Low to DATA Valid 250 ns
tOHDZ OE High to DATA Tri-stated 250 nsATtiny1634 [DATASHEET] 238
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
24.11 Serial Programming
Figure 24-7. Serial Programming Timing
Figure 24-8. Serial Programming Waveform
Table 24-13. Serial Programming Characteristics, TA = -40C to +85C
Symbol Parameter Min Typ Max Units
1/tCLCL Oscillator Frequency @ VCC = 1.8V - 5.5V 0 1 MHz
tCLCL Oscillator Period @ VCC = 1.8V - 5.5V 1000 ns
1/tCLCL Oscillator Frequency @ VCC = 4.5V - 5.5V 0 6 MHz
tCLCL Oscillator Period @ VCC = 4.5V - 5.5V 167 ns
tSHSL SCK Pulse Width High 2 tCLCL ns
tSLSH SCK Pulse Width Low 2 tCLCL ns
tOVSH MOSI Setup to SCK High tCLCL ns
tSHOX MOSI Hold after SCK High 2 tCLCL ns
MOSI
MISO
SCK
t
OVSH
t
SHSL
t t
SHOX SLSH
MSB
MSB
LSB
LSB
SERIAL CLOCK INPUT
(SCK)
SERIAL DATA INPUT
(MOSI)
(MISO)
SAMPLE
SERIAL DATA OUTPUTATtiny1634 [DATASHEET] 239
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
25. Electrical Characteristics @ 105C
25.1 Absolute Maximum Ratings*
25.2 DC Characteristics
Table 25-1. DC Characteristics. TA = -40 to +105C
Operating Temperature . . . . . . . . . . . -55C to +125C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only
and functional operation of the device at these
or other conditions beyond those indicated in
the operational sections of this specification is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature . . . . . . . . . . . . . -65C to +150C
Voltage on any Pin except RESET
with respect to Ground. . . . . . . . . . -0.5V to VCC+0.5V
Voltage on RESET with respect to Ground-0.5V to +13.0V
Maximum Operating Voltage . . . . . . . . . . . . . . . . 6.0V
DC Current per I/O Pin. . . . . . . . . . . . . . . . . . 40.0 mA
DC Current VCC and GND Pins . . . . . . . . . . 200.0 mA
Symbol Parameter Condition Min Typ (1) Max Units
VIL
Input Low Voltage
VCC = 1.8 - 2.4V -0.5 0.2VCC (2) V
VCC = 2.4 - 5.5V -0.5 0.3VCC (2) V
Input Low Voltage,
RESET Pin as Reset (4) VCC = 1.8 - 5.5V -0.5 0.2VCC (2)
VIH
Input High-voltage
Except RESET pin
VCC = 1.8 - 2.4V 0.7VCC(3) VCC +0.5 V
VCC = 2.4 - 5.5V 0.6VCC(3) VCC +0.5 V
Input High-voltage
RESET pin as Reset (4) VCC = 1.8 - 5.5V 0.9VCC(3) VCC +0.5 V
VOL
Output Low Voltage(5)
Except RESET pin(7)
Standard I/O: IOL = 10 mA, VCC = 5V
0.6 V
High-sink I/O: IOL = 20 mA, VCC = 5V
Standard I/O: IOL = 5 mA, VCC = 3V
0.5 V
High-sink I/O: IOL = 10 mA, VCC = 3V
VOH
Output High-voltage(6)
Except RESET pin(7)
IOH = -10 mA, VCC = 5V 4.3 V
IOH = -5 mA, VCC = 3V 2.5 V
ILIL
Input Leakage Current
I/O Pin VCC = 5.5V, pin low (absolute value) < 0.05 1 (8) µA
ILIH
Input Leakage Current
I/O Pin VCC = 5.5V, pin high (absolute value) < 0.05 1 (8) µAATtiny1634 [DATASHEET] 240
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Notes: 1. Typical values at +25C.
2. “Max” means the highest value where the pin is guaranteed to be read as low.
3. “Min” means the lowest value where the pin is guaranteed to be read as high.
4. Not tested in production.
5. Although each I/O port can sink more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state conditions (non-transient), the sum of
all IOL (for all ports) should not exceed 100 mA. If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current
greater than the listed test condition.
6. Although each I/O port can source more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state conditions (non-transient), the sum
of all IOH (for all ports) should not exceed 100 mA. If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source
current greater than the listed test condition.
7. The RESET pin must tolerate high voltages when entering and operating in programming modes and, as a consequence, has a weak drive strength as compared
to regular I/O pins. See “Output Driver Strength” on page 259.
8. These are test limits, which account for leakage currents of the test environment. Actual device leakage currents are lower.
9. Values are with external clock using methods described in “Minimizing Power Consumption” on page 39. Power Reduction is enabled (PRR = 0xFF) and there
is no I/O drive.
10. Bod Disabled.
25.3 Clock
Table 25-2. Accuracy of Calibrated 8MHz Oscillator
Notes: 1. See device ordering codes on page 280 for alternatives.
2. Accuracy of oscillator frequency at calibration point (fixed temperature and fixed voltage).
RPU
Pull-up Resistor, I/O Pin VCC = 5.5V, input low 20 50 k
Pull-up Resistor, Reset
Pin VCC = 5.5V, input low 30 60 k
ICC
Supply Current,
Active Mode (9)
f = 1MHz, VCC = 2V 0.23 0.4 mA
f = 4MHz, VCC = 3V 1.3 1.7 mA
f = 8MHz, VCC = 5V 4.3 6 mA
Supply Current,
Idle Mode (9)
f = 1MHz, VCC = 2V 0.04 0.1 mA
f = 4MHz, VCC = 3V 0.26 0.4 mA
f = 8MHz, VCC = 5V 1.1 1.7 mA
Supply Current,
Power-Down Mode(10)
WDT enabled, VCC = 3V 1.7 6 µA
WDT disabled, VCC = 3V 0.1 4 µA
Symbol Parameter Condition Min Typ (1) Max Units
Calibration
Method Target Frequency VCC Temperature Accuracy
Factory
Calibration 8.0MHz 2.7 – 4V 25C to +105C ±10% (1)
User
Calibration
Within:
7.3 – 8.1MHz
Within:
1.8 – 5.5V
Within:
-40C to +105C ±1% (2)ATtiny1634 [DATASHEET] 241
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Table 25-3. Accuracy of Calibrated 32kHz Oscillator
Table 25-4. External Clock Drive
25.4 System and Reset
Table 25-5. Enhanced Power-On Reset
Note: 1. Values are guidelines only.
2. Threshold where device is released from reset when voltage is rising.
3. The Power-on Reset will not work unless the supply voltage has been below VPOA.
Calibration
Method Target Frequency VCC Temperature Accuracy
Factory
Calibration 32kHz 1.8 – 5.5V -40C to +105C ±30%
Symbol Parameter
VCC = 1.8 - 5.5V VCC = 2.7 - 5.5V VCC = 4.5 - 5.5V
Min. Max. Min. Max. Min. Max. Units
1/tCLCL Clock Frequency 0 2 0 8 0 10 MHz
tCLCL Clock Period 500 125 100 ns
tCHCX High Time 200 40 20 ns
tCLCX Low Time 200 40 20 ns
tCLCH Rise Time 2.0 1.6 0.5 s
tCHCL Fall Time 2.0 1.6 0.5 s
tCLCL
Change in period from one
clock cycle to next 2 2 2 %
Symbol Parameter Min(1) Typ(1) Max(1) Units
VPOR Release threshold of power-on reset (2) 1.1 1.4 1.7 V
VPOA Activation threshold of power-on reset (3) 0.6 1.3 1.7 V
SRON Power-On Slope Rate 0.01 V/msATtiny1634 [DATASHEET] 242
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
26. Typical Characteristics
The data contained in this section is largely based on simulations and characterization of similar devices in the
same process and design methods. Thus, the data should be treated as indications of how the part will behave.
The following charts show typical behavior. These figures are not tested during manufacturing. During characterisation
devices are operated at frequencies higher than test limits but they are not guaranteed to function properly
at frequencies higher than the ordering code indicates.
All current consumption measurements are performed with all I/O pins configured as inputs and with internal pullups
enabled. Current consumption is a function of several factors such as operating voltage, operating frequency,
loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are
operating voltage and frequency.
A sine wave generator with rail-to-rail output is used as clock source but current consumption in Power-Down
mode is independent of clock selection. The difference between current consumption in Power-Down mode with
Watchdog Timer enabled and Power-Down mode with Watchdog Timer disabled represents the differential current
drawn by the Watchdog Timer.
The current drawn from pins with a capacitive load may be estimated (for one pin) as follows:
where VCC = operating voltage, CL = load capacitance and fSW = average switching frequency of I/O pin.
26.1 Current Consumption in Active Mode
Figure 26-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz)
I
CP VCC CL f
SW
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
ICC[mA]
Frequency [MHz]
5.5V
5.0V
4.5V
4.0V
3.3V
1.8V
2.7VATtiny1634 [DATASHEET] 243
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 26-2. Active Supply Current vs. Frequency (1 - 12 MHz)
Figure 26-3. Active Supply Current vs. VCC (Internal Oscillator, 8 MHz)
0
1
2
3
4
5
6
7
0 1 2 3 4 5 6 7 8 9 10 11 12
ICC [mA]
Frequency [MHz]
5.5V
5.0V
4.5V
4.0V
3.3V
2.0V
2.7V
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
1.5 2 2.5 3 3.5 4 4.5 5 5.5
ICC[mA]
VCC [V]
INTERNAL RC OSCILLATOR, 8 MHz
105°C
85°C
25°C
-40°C
125°CATtiny1634 [DATASHEET] 244
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 26-4. Active Supply Current vs. VCC (Internal Oscillator, 1 MHz)
Figure 26-5. Active Supply Current vs. VCC (Internal Oscillator, 32kHz)
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.5 2 2.5 3 3.5 4 4.5 5 5.5
ICC[mA]
VCC [V]
105°C
85°C
25°C
-40°C
125°C
0
5
10
15
20
25
30
35
40
45
1.5 2 2.5 3 3.5 4 4.5 5 5.5
ICC [µA]
VCC[V]
105°C
85°C
25°C
-40°C
125°CATtiny1634 [DATASHEET] 245
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
26.2 Current Consumption in Idle Mode
Figure 26-6. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz)
Figure 26-7. Idle Supply Current vs. Frequency (1 - 12 MHz)
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
ICC[mA]
Frequency [MHz]
5.5V
5.0V
4.5V
4.0V
3.3V
1.8V
2.7V
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0 1 2 3 4 5 6 7 8 9 10 11 12
ICC[mA]
Frequency [MHz]
5.5V
5.0V
4.5V
4.0V
3.3V
1.8V
2.7VATtiny1634 [DATASHEET] 246
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 26-8. Idle Supply Current vs. VCC (Internal Oscillator, 8 MHz)
Figure 26-9. Idle Supply Current vs. VCC (Internal Oscillator, 1 MHz)
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5
ICC [mA]
VCC [V]
105°C
85°C
25°C
-40°C
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
1.5 2 2.5 3 3.5 4 4.5 5 5.5
ICC[mA]
VCC [V]
105 °C
85°C
25°C
-40°CATtiny1634 [DATASHEET] 247
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 26-10. Idle Supply Current vs. VCC (Internal Oscillator, 32kHz)
26.3 Current Consumption in Standby Mode
Figure 26-11. Standby Supply Current vs. VCC (Watchdog Timer Enabled)
0
5
10
15
20
25
30
35
40
45
1.5 2 2.5 3 3.5 4 4.5 5 5.5
ICC [µA]
VCC [V]
105°C
85°C
25°C
-40°C
0
0.025
0.05
0.075
0.1
0.125
0.15
0.175
0.2
0.225
0.25
1.5 2 2.5 3 3.5 4 4.5 5 5.5
ICC [mA]
VCC [V]
8MHz
32kHzATtiny1634 [DATASHEET] 248
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
26.4 Current Consumption in Power-down Mode
Figure 26-12. Power-down Supply Current vs. VCC (Watchdog Timer Disabled)
Figure 26-13. Power-down Supply Current vs. VCC (Watchdog Timer Enabled)
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
1.5 2 2.5 3 3.5 4 4.5 5 5.5
ICC [µA]
VCC [V]
105°C
85°C
25°C
-40°C
0
1
2
3
4
5
6
7
8
1.5 2 2.5 3 3.5 4 4.5 5 5.5
ICC [µA]
VCC [V]
105°C
85°C
25°C
-40°CATtiny1634 [DATASHEET] 249
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
26.5 Current Consumption in Reset
Figure 26-14. Reset Current vs. Frequency (0.1 – 1MHz, Excluding Pull-Up Current)
Figure 26-15. Reset Current vs. Frequency (1 – 12MHz, Excluding Pull-Up Current)
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
ICC [mA]
Frequency [MHz]
5.5V
5.0V
4.5V
4.0V
3.3V
1.8V
2.7V
0
1
2
3
4
5
6
7
8
9
10
0 1 2 3 4 5 6 7 8 9 10 11 12
ICC [mA]
Frequency [MHz]
5.5V
5.0V
4.5V
4.0V
3.3V
1.8V
2.7VATtiny1634 [DATASHEET] 250
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 26-16. Reset Current vs. VCC (No Clock, excluding Reset Pull-Up Current)
26.6 Current Consumption of Peripheral Units
Figure 26-17. Current Consumption of Peripherals at 4MHz
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.5 2 2.5 3 3.5 4 4.5 5 5.5
ICC [mA]
VCC [V]
105°C
85°C
25°C
-40°C
100
200
300
400
500
600
700
800
900
1000
1100
1.5 2 2.5 3 3.5 4 4.5 5 5.5
ICC [µA]
VCC [V]
ADC
AC
T/C1
T/C0ATtiny1634 [DATASHEET] 251
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 26-18. Watchdog Timer Current vs. VCC
Figure 26-19. Brownout Detector Current vs. VCC
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
105°C
85°C
25°C
-40°C
ICC [µA]
VCC [V]
13
14
15
16
17
18
19
20
21
22
23
1.6 1.9 2.2 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2
ICC [µA]
VCC [V]
105°C
85°C
25°C
-40°CATtiny1634 [DATASHEET] 252
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 26-20. Sampled Brownout Detector Current vs. VCC
Figure 26-21. AREF External Reference Pin Current (VCC = 5V)
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
1.8 2.1 2.4 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1
ICC [µA]
VCC [V]
105°C
85°C
25°C
-40°C
40
50
60
70
80
90
100
110
120
130
140
150
1.4 1.8 2.2 2.6 3 3.4 3.8 4.2 4.6 5
AREF pin current [µA]
AREF [V]
105°C
85°C
25°C
-40°CATtiny1634 [DATASHEET] 253
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
26.7 Pull-up Resistors
Figure 26-22. I/O pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V)
Figure 26-23. I/O Pin Pull-up Resistor Current vs. input Voltage (VCC = 2.7V)
0
5
10
15
20
25
30
35
40
45
50
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
IOP [µA]
105ºC
85ºC
25ºC
-40ºC
VOP [V]
0
10
20
30
40
50
60
70
80
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
IOP [µA]
VOP [V]
105ºC
85ºC
25ºC
-40ºCATtiny1634 [DATASHEET] 254
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 26-24. I/O pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)
Figure 26-25. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V)
0
20
40
60
80
100
120
140
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
IOP [µA]
VOP [V]
105ºC
85ºC
25ºC
-40ºC
0
5
10
15
20
25
30
35
40
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
IRESET [µA]
VRESET [V]
105ºC
85ºC
25ºC
-40ºCATtiny1634 [DATASHEET] 255
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 26-26. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)
Figure 26-27. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
0
6
12
18
24
30
36
42
48
54
60
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
IRESET [µA]
VRESET [V]
105ºC
85ºC
25ºC
-40ºC
0
10
20
30
40
50
60
70
80
90
100
110
120
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
IRESET [µA]
VRESET [V]
105ºC
85ºC
25ºC
-40ºCATtiny1634 [DATASHEET] 256
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
26.8 Input Thresholds
Figure 26-28. VIH: Input Threshold Voltage vs. VCC (I/O Pin, Read as ‘1’)
Figure 26-29. VIL: Input Threshold Voltage vs. VCC (I/O Pin, Read as ‘0’)
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
1.6 1.9 2.2 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC [V]
105ºC
85ºC
25ºC
-40ºC
Vthreshold [
V]
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
1.6 1.9 2.2 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC [V]
105ºC
85ºC
25ºC
-40ºC
Vthreshold [
V]ATtiny1634 [DATASHEET] 257
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 26-30. VIH-VIL: Input Hysteresis vs. VCC (I/O Pin)
Figure 26-31. VIH: Input Threshold Voltage vs. VCC (Reset Pin as I/O, Read as ‘1’)
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
1.6 1.9 2.2 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC [V]
105ºC
85ºC
25ºC
-40ºC
Vthreshold [
V]
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
1.6 1.9 2.2 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC [V]
105ºC
85ºC
-40ºC 25ºC
Vthreshold [
V]ATtiny1634 [DATASHEET] 258
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 26-32. VIL: Input Threshold Voltage vs. VCC (Reset Pin as I/O, Read as ‘0’)
Figure 26-33. VIH-VIL: Input Hysteresis vs. VCC (Reset Pin as I/O)
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
1.6 1.9 2.2 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC [V]
Vthreshold [V]
105ºC
85ºC
25ºC
-40ºC
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
1.6 1.9 2.2 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC [V]
105ºC
85ºC
25ºC
-40ºCATtiny1634 [DATASHEET] 259
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
26.9 Output Driver Strength
Figure 26-34. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 1.8V)
Figure 26-35. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 3V)
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VOH [V]
IOH [mA]
105ºC
85ºC
25ºC
-40ºC
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
0 1 2 3 4 5 6 7 8 9 10
VOH [V]
IOH [mA]
105ºC
85ºC
25ºC
-40ºCATtiny1634 [DATASHEET] 260
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 26-36. VOH: Output Voltage vs. Source Current (I/O Pin, VCC = 5V)
Figure 26-37. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 1.8V)
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5
0 2 4 6 8 10 12 14 16 18 20
VOH [V]
IOH [mA]
105ºC
85ºC
25ºC
-40ºC
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VOL [V]
IOL [mA]
105ºC
85ºC
25ºC
-40ºCATtiny1634 [DATASHEET] 261
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 26-38. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 3V)
Figure 26-39. VOL: Output Voltage vs. Sink Current (I/O Pin, VCC = 5V)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0 1 2 3 4 5 6 7 8 9 10
VOL [V]
IOL [mA]
105ºC
85ºC
25ºC
-40ºC
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 2 4 6 8 10 12 14 16 18 20
VOL [V]
IOL [mA]
105ºC
85ºC
25ºC
-40ºCATtiny1634 [DATASHEET] 262
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 26-40. VOH: Output Voltage vs. Source Current (Reset Pin as I/O, VCC = 1.8V
Figure 26-41. VOH: Output Voltage vs. Source Current (Reset Pin as I/O, VCC = 3V
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
VOH [V]
IOH [mA]
105ºC
85ºC
25ºC
-40ºC
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
2.4
2.5
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
VOH [V]
IOH [mA]
105ºC
85ºC
25ºC
-40ºCATtiny1634 [DATASHEET] 263
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 26-42. VOH: Output Voltage vs. Source Current (Reset Pin as I/O, VCC = 5V
Figure 26-43. VOL: Output Voltage vs. Sink Current (Reset Pin as I/O, VCC = 1.8V)
2.7
2.9
3.1
3.3
3.5
3.7
3.9
4.1
4.3
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
VOH [V]
IOH [mA]
105ºC
85ºC
25ºC
-40ºC
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
VOL [V]
IOL [mA]
105ºC
85ºC
25ºC
-40ºCATtiny1634 [DATASHEET] 264
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 26-44. VOL: Output Voltage vs. Sink Current (Reset Pin as I/O, VCC = 3V)
Figure 26-45. VOL: Output Voltage vs. Sink Current (Reset Pin as I/O, VCC = 5V)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VOL [V]
IOL [mA]
105ºC
85ºC
25ºC
-40ºC
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4
VOL [V]
IOL [mA]
105ºC
85ºC
25ºC
-40ºCATtiny1634 [DATASHEET] 265
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
26.10 BOD
Figure 26-46. BOD Threshold vs Temperature (BODLEVEL = 4.3V)
Figure 26-47. BOD Threshold vs Temperature (BODLEVEL = 2.7V)
4.16
4.18
4.2
4.22
4.24
4.26
4.28
4.3
4.32
4.34
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Rising Vcc
Falling Vcc
Temperature [°C]
VThreshold [
V]
2.62
2.64
2.66
2.68
2.7
2.72
2.74
2.76
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Rising Vcc
Falling Vcc
Temperature [°C]
VThreshold [
V]ATtiny1634 [DATASHEET] 266
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 26-48. BOD Threshold vs Temperature (BODLEVEL = 1.8V)
Figure 26-49. Sampled BOD Threshold vs Temperature (BODLEVEL = 4.3V)
1.75
1.76
1.77
1.78
1.79
1.8
1.81
1.82
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Rising Vcc
Falling Vcc
Temperature [°C]
VThreshold [
V]
4.25
4.26
4.27
4.28
4.29
4.3
4.31
4.32
4.33
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130
Rising Vcc
Falling Vcc
Temperature [°C]
VThreshold [
V]ATtiny1634 [DATASHEET] 267
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 26-50. Sampled BOD Threshold vs Temperature (BODLEVEL = 2.7V)
Figure 26-51. Sampled BOD Threshold vs Temperature (BODLEVEL = 1.8V)
2.71
2.715
2.72
2.725
2.73
2.735
2.74
2.745
2.75
2.755
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Rising Vcc
Falling Vcc
Temperature [°C]
VThreshold [
V] 1.772
1.774
1.776
1.778
1.78
1.782
1.784
1.786
1.788
1.79
1.792
1.794
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Rising Vcc
Falling Vcc
Temperature [°C]
VThreshold [
V]ATtiny1634 [DATASHEET] 268
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
26.11 Bandgap Voltage
Figure 26-52. Bandgap Voltage vs. Supply Voltage
Figure 26-53. Bandgap Voltage vs. Temperature
1.04
1.045
1.05
1.055
1.06
1.065
1.07
1.075
1.08
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Bandgap [V]
105°C
85°C
25°C
-40°C
VCC [V]
1.042
1.044
1.046
1.048
1.05
1.052
1.054
1.056
1.058
1.06
1.062
1.064
1.066
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Bandgap Voltage [V]
5.5V
3.3V
1.8V
Temperature [°C]ATtiny1634 [DATASHEET] 269
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
26.12 Reset
Figure 26-54. VIH: Input Threshold Voltage vs. VCC (Reset Pin, Read as ‘1’)
Figure 26-55. VIL: Input Threshold Voltage vs. VCC (Reset Pin, Read as ‘0’)
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
1.6 1.9 2.2 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC [V]
Vthreshold [V]
105ºC
85ºC
25ºC
-40ºC
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
1.6 1.9 2.2 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC [V]
Vthreshold [V]
105ºC
85ºC
25ºC
-40ºCATtiny1634 [DATASHEET] 270
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 26-56. VIH-VIL: Input Hysteresis vs. VCC (Reset Pin )
Figure 26-57. Minimum Reset Pulse Width vs. VCC
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
1.6 1.9 2.2 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC [V]
VHysteresis [V]
105ºC
85ºC
25ºC
-40ºC
0
200
400
600
800
1000
1200
1400
1600
1800
2000
2200
2400
1.6 1.9 2.2 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
VCC [V]
105ºC
85ºC
25ºC
-40ºC
TRST [ns]ATtiny1634 [DATASHEET] 271
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
26.13 Analog Comparator Offset
Figure 26-58. Analog Comparator Offset vs. VIN (VCC = 5V)
Figure 26-59. Analog Comparator Offset vs. VCC (VIN = 1.1V)
0
10
20
30
40
50
60
70
80
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Offset [mV]
VIN [V]
105°C 85°C
25°C
-40°C
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Offset [mV]
VCC [V]
105°C
85°C
25°C
-40°CATtiny1634 [DATASHEET] 272
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 26-60. Analog Comparator Hysteresis vs. VIN (VCC = 5.0V)
26.14 Internal Oscillator Speed
Figure 26-61. Calibrated Oscillator Frequency (Nominal = 8MHz) vs. VCC
0
5
10
15
20
25
30
35
40
45
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Hysteresis [mV]
VIN [V]
105°C 85°C
25°C
-40°C
7.8
7.85
7.9
7.95
8
8.05
8.1
8.15
8.2
8.25
8.3
1.9 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
FRC [MHz]
VCC [V]
105ºC
85ºC
25ºC
-40ºCATtiny1634 [DATASHEET] 273
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 26-62. Calibrated Oscillator Frequency (Nominal = 8MHz) vs. Temperature
Figure 26-63. Calibrated Oscillator Frequency (Nominal = 8MHz) vs. OSCCAL Value
7.92
7.94
7.96
7.98
8
8.02
8.04
8.06
8.08
8.1
8.12
8.14
8.16
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
FRC [MHz]
5.0V
3.0V
Temperature [°C]
0
2
4
6
8
10
12
14
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
FRC [MHz]
OSCCAL [X1]
105ºC
85ºC
25ºC
-40ºCATtiny1634 [DATASHEET] 274
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 26-64. Calibrated Oscillator Frequency (Nominal = 1MHz) vs. VCC
Figure 26-65. Calibrated Oscillator Frequency (Nominal = 1MHz) vs. Temperature
0.97
0.98
0.99
1
1.01
1.02
1.03
1.04
1.05
1.5 2 2.5 3 3.5 4 4.5 5 5.5
FRC [MHz]
VCC [V]
105ºC
85ºC
25ºC
-40ºC
0.975
0.98
0.985
0.99
0.995
1.00
1.005
1.01
1.015
1.02
1.025
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
FRC [MHz]
5.0V
1.8V
Temperature [°C]
3.0VATtiny1634 [DATASHEET] 275
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
Figure 26-66. ULP Oscillator Frequency (Nominal = 32kHz) vs. VCC
Figure 26-67. ULP Oscillator Frequency (Nominal = 32kHz) vs. Temperature
28.0
28.5
29.0
29.5
30.0
30.5
31.0
31.5
32.0
1.6 1.9 2.2 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 4.9 5.2 5.5
FRC [kHz]
VCC [V]
105ºC
85ºC
25ºC
-40ºC
26
27
28
29
30
31
32
33
-45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
FRC [kHz]
Temperature [°C]ATtiny1634 [DATASHEET] 276
Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014
27. Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page(s)
(0xFF) Reserved – – – – – – – –
(0xFE) Reserved – – – – – – – –
(0xFD) Reserved – – – – – – – –
(0xFC) Reserved – – – – – – – –
(0xFB) Reserved – – – – – – – –
(0xFA) Reserved – – – – – – – –
(0xF9) Reserved – – – – – – – –
... ... ... ... ... ... ... ... ... ... ...
(0x85) Reserved – – – – – – – –
(0x84) Reserved – – – – – – – –
(0x83) Reserved – – – – – – – –
(0x82) Reserved – – – – – – – –
(0x81) Reserved – – – – – – – –
(0x80) Reserved – – – – – – – –
(0x7F) TWSCRA TWSHE – TWDIE TWASIE TWEN TWSIE TWPME TWSME 127
(0x7E) TWSCRB TWAA TWCMD[1:0] 127
(0x7D) TWSSRA TWDIF TWASIF TWCH TWRA TWC TWBE TWDIR TWAS 128
(0x7C) TWSA TWI Slave Address Register 130
(0x7B) TWSAM TWI Slave Address Mask Register 130
(0x7A) TWSD TWI Slave Data Register 130
(0x79) UCSR1A RXC1 TXC1 UDRE1 FE1 DOR1 UPE1 U2X1 MPCM1 167
(0x78) UCSR1B RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 168
(0x77) UCSR1C UMSEL11 UMSEL10 UPM11 UPM01 USBS1 UCSZ11 UCSZ10 UCPOL1 169
(0x76) UCSR1D RXSIE1 RXS1 SFDE1 171
(0x75) UBRR1H USART1 Baud Rate Register High Byte 172
(0x74) UBRR1L USART1 Baud Rate Register Low Byte 172
(0x73) UDR1 USART1 I/O Data Register 167
(0x72) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 111
(0x71) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 113
(0x70) TCCR1C FOC1A FOC1B – – – – – – 114
(0x6F) TCNT1H Timer/Counter1 – Counter Register High Byte 114
(0x6E) TCNT1L Timer/Counter1 – Counter Register Low Byte 114
(0x6D) OCR1AH Timer/Counter1 – Compare Register A High Byte 114
(0x6C) OCR1AL Timer/Counter1 – Compare Register A Low Byte 114
(0x6B) OCR1BH Timer/Counter1 – Compare Register B High Byte 115
(0x6A) OCR1BL Timer/Counter1 – Compare Register B Low Byte 115
(0x69) ICR1H Timer/Counter1 – Input Capture Register High Byte 115
(0x68) ICR1L Timer/Counter1 – Input Capture Register Low Byte 115
(0x67) GTCCR TSM – – – – – – PSR10 118
(0x66) OSCCAL1 – – – – – – CAL11 CAL10 33
(0x65) OSCTCAL0B Oscillator Temperature Compensation Register B 33
(0x64) OSCTCAL0A Oscillator Temperature Compensation Register A 33
(0x63) OSCCAL0 CAL07 CAL06 CAL05 CAL04 CAL03 CAL02 CAL01 CAL00 32
(0x62) DIDR2 – – – – – ADC11D ADC10D ADC9D 200
(0x61) DIDR1 – – – – ADC8D ADC7D ADC6D ADC5D 200
(0x60) DIDR0 ADC4D ADC3D ADC2D ADC1D ADC0D AIN1D AIN0D AREFD 184, 200
0x3F (0x5F) SREG I T H S V N Z C 14
0x3E (0x5E) SPH – – – – – SP10 SP9 SP8 13
0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 13
0x3C (0x5C) GIMSK – INT0 PCIE2 PCIE1 PCIE0 – – – 51
0x3B (0x5B) GIFR – INTF0 PCIF2 PCIF1 PCIF0 – – – 52
0x3A (0x5A) TIMSK TOIE1 OCIE1A OCIE1B – ICIE1 OCIE0B TOIE0 OCIE0A 88, 115
0x39 (0x59) TIFR TOV1 OCF1A OCF1B – ICF1 OCF0B TOV0 OCF0A 89, 116
0x38 (0x58) QTCSR QTouch Control and Status Register 6
0x37 (0x57) SPMCSR – – RSIG CTPB RFLB PGWRT PGERS SPMEN 207
0x36 (0x56) MCUCR – SM1 SM0 SE – – ISC01 ISC00 37, 51
0x35 (0x55) MCUSR – – – – WDRF BORF EXTRF PORF 44
0x34 (0x54) PRR – PRTWI PRTIM0 PRTIM0 PRUSI PRUSART1 PRUSART0 PRADC 38
0x33 (0x53) CLKPR – – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 31
0x32 (0x52) CLKSR OSCRDY CSTR CKOUT_IO SUT CKSEL3 CKSEL2 CKSEL1 CKSEL0 29
0x31 (0x51) Reserved – – – – – – – –
0x30 (0x50) WDTCSR WDIF WDIE WDP3 – WDE WDP2 WDP1 WDP0 45
0x2F (0x4F) CCP CPU Change Protection Register 13
0x2E (0x4E) DWDR DWDR[7:0] 202
0x2D (0x4D) USIBR USI Buffer Register 144
0x2C (0x4C) USIDR USI Data Register 143ATtiny1634 [DATASHEET] 277
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Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
0x2B (0x4B) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 142
0x2A (0x4A) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC 140
0x29 (0x49) PCMSK2 – – PCINT17 PCINT16 PCINT15 PCINT14 PCINT13 PCINT12 52
0x28 (0x48) PCMSK1 – – – – PCINT11 PCINT10 PCINT9 PCINT8 53
0x27 (0x47) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 53
0x26 (0x46) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM 167
0x25 (0x45) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 168
0x24 (0x44) UCSR0C UMSEL01 UMSEL00 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 169
0x23 (0x43) UCSR0D RXCIE0 RXS0 SFDE0 – – – – – 171
0x22 (0x42) UBRR0H – – – – USART0 Baud Rate Register High Byte 172
0x21 (0x41) UBRR0L USART0 Baud Rate Register Low Byte 172
0x20 (0x40) UDR0 USART0 I/O Data Register 167
0x1F (0x3F) EEARH – – – – – – – –
0x1E (0x3E) EEARL EEAR[7:0] 22
0x1D (0x3D) EEDR EEPROM Data Register 22
0x1C (0x3C) EECR – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE 22
0x1B (0x3B) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 84
0x1A (0x3A) TCCR0B FOC0A FOC0B – – WGM02 CS02 CS01 CS00 86
0x19 (0x39) TCNT0 Timer/Counter0 88
0x18 (0x38) OCR0A Timer/Counter0 – Compare Register A 88
0x17 (0x37) OCR0B Timer/Counter0 – Compare Register B 88
0x16 (0x36) GPIOR2 General Purpose Register 2 23
0x15 (0x35) GPIOR1 General Purpose Register 1 24
0x14 (0x34) GPIOR0 General Purpose Register 0 24
0x13 (0x33) PORTCR – – – – – BBMC BBMB BBMA 71
0x12 (0x32) PUEA PUEA7 PUEA6 PUEA5 PUEA4 PUEA3 PUEA2 PUEA1 PUEA0 71
0x11 (0x31) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 71
0x10 (0x30) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 71
0x0F (0x2F) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 71
0x0E (0x2E) PUEB – – – – PUEB3 PUEB2 PUEB1 PUEB0 72
0x0D (0x2D) PORTB – – – – PORTB3 PORTB2 PORTB1 PORTB0 72
0x0C (0x2C) DDRB – – – – DDB3 DDB2 DDB1 DDB0 72
0x0B (0x2B) PINB – – – – PINB3 PINB2 PINB1 PINB0 72
0x0A (0x2A) PUEC – – PUEC5 PUEC4 PUEC3 PUEC2 PUEC1 PUEC0 72
0x09 (0x29) PORTC – – PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 72
0x08 (0x28) DDRC – – DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 72
0x07 (0x27) PINC – – PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 72
0x06 (0x26) ACSRA ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 182
0x05 (0x25) ACSRB HSEL HLEV ACLP – ACCE ACME ACIRS1 ACIRS0 183
0x04 (0x24) ADMUX REFS1 REFS0 REFEN ADC0EN MUX3 MUX2 MUX1 MUX0 196
0x03 (0x23) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 197
0x02 (0x22) ADCSRB VDEN VDPD – – ADLAR ADTS2 ADTS1 ADTS0 199
0x01 (0x21) ADCH ADC Data Register High Byte 198
0x00 (0x20) ADCL ADC Data Register Low Byte 198
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page(s)ATtiny1634 [DATASHEET] 278
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28. Instruction Set Summary
Mnemonics Operands Description Operation Flags #Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD Rd, Rr Add two Registers Rd Rd + Rr Z,C,N,V,H 1
ADC Rd, Rr Add with Carry two Registers Rd Rd + Rr + C Z,C,N,V,H 1
ADIW Rdl,K Add Immediate to Word Rdh:Rdl Rdh:Rdl + K Z,C,N,V,S 2
SUB Rd, Rr Subtract two Registers Rd Rd - Rr Z,C,N,V,H 1
SUBI Rd, K Subtract Constant from Register Rd Rd - K Z,C,N,V,H 1
SBC Rd, Rr Subtract with Carry two Registers Rd Rd - Rr - C Z,C,N,V,H 1
SBCI Rd, K Subtract with Carry Constant from Reg. Rd Rd - K - C Z,C,N,V,H 1
SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl Rdh:Rdl - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Registers Rd Rd Rr Z,N,V 1
ANDI Rd, K Logical AND Register and Constant Rd Rd K Z,N,V 1
OR Rd, Rr Logical OR Registers Rd Rd v Rr Z,N,V 1
ORI Rd, K Logical OR Register and Constant Rd Rd v K Z,N,V 1
EOR Rd, Rr Exclusive OR Registers Rd Rd Rr Z,N,V 1
COM Rd One’s Complement Rd 0xFF Rd Z,C,N,V 1
NEG Rd Two’s Complement Rd 0x00 Rd Z,C,N,V,H 1
SBR Rd,K Set Bit(s) in Register Rd Rd v K Z,N,V 1
CBR Rd,K Clear Bit(s) in Register Rd Rd (0xFF - K) Z,N,V 1
INC Rd Increment Rd Rd + 1 Z,N,V 1
DEC Rd Decrement Rd Rd 1 Z,N,V 1
TST Rd Test for Zero or Minus Rd Rd Rd Z,N,V 1
CLR Rd Clear Register Rd Rd Rd Z,N,V 1
SER Rd Set Register Rd 0xFF None 1
BRANCH INSTRUCTIONS
JMP k Direct Jump PC k None 3
RJMP k Relative Jump PC PC + k + 1 None 2
IJMP Indirect Jump to (Z) PC Z None 2
CALL k Direct Subroutine PC k None 4
RCALL k Relative Subroutine Call PC PC + k + 1 None 3
ICALL Indirect Call to (Z) PC Z None 3
RET Subroutine Return PC STACK None 4
RETI Interrupt Return PC STACK I 4
CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC PC + 2 or 3 None 1/2/3
CP Rd,Rr Compare Rd Rr Z, N,V,C,H 1
CPC Rd,Rr Compare with Carry Rd Rr C Z, N,V,C,H 1
CPI Rd,K Compare Register with Immediate Rd K Z, N,V,C,H 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC PC + 2 or 3 None 1/2/3
SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC PC + 2 or 3 None 1/2/3
SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC PC + 2 or 3 None 1/2/3
SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC PC + 2 or 3 None 1/2/3
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PCPC+k + 1 None 1/2
BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PCPC+k + 1 None 1/2
BREQ k Branch if Equal if (Z = 1) then PC PC + k + 1 None 1/2
BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 None 1/2
BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1 None 1/2
BRCC k Branch if Carry Cleared if (C = 0) then PC PC + k + 1 None 1/2
BRSH k Branch if Same or Higher if (C = 0) then PC PC + k + 1 None 1/2
BRLO k Branch if Lower if (C = 1) then PC PC + k + 1 None 1/2
BRMI k Branch if Minus if (N = 1) then PC PC + k + 1 None 1/2
BRPL k Branch if Plus if (N = 0) then PC PC + k + 1 None 1/2
BRGE k Branch if Greater or Equal, Signed if (N V= 0) then PC PC + k + 1 None 1/2
BRLT k Branch if Less Than Zero, Signed if (N V= 1) then PC PC + k + 1 None 1/2
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC PC + k + 1 None 1/2
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC PC + k + 1 None 1/2
BRTS k Branch if T Flag Set if (T = 1) then PC PC + k + 1 None 1/2
BRTC k Branch if T Flag Cleared if (T = 0) then PC PC + k + 1 None 1/2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1 None 1/2
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None 1/2
BRIE k Branch if Interrupt Enabled if ( I = 1) then PC PC + k + 1 None 1/2
BRID k Branch if Interrupt Disabled if ( I = 0) then PC PC + k + 1 None 1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI P,b Set Bit in I/O Register I/O(P,b) 1 None 2
CBI P,b Clear Bit in I/O Register I/O(P,b) 0 None 2
LSL Rd Logical Shift Left Rd(n+1) Rd(n), Rd(0) 0 Z,C,N,V 1
LSR Rd Logical Shift Right Rd(n) Rd(n+1), Rd(7) 0 Z,C,N,V 1
ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V 1ATtiny1634 [DATASHEET] 279
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ROR Rd Rotate Right Through Carry Rd(7)C,Rd(n) Rd(n+1),CRd(0) Z,C,N,V 1
ASR Rd Arithmetic Shift Right Rd(n) Rd(n+1), n=0..6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) None 1
BSET s Flag Set SREG(s) 1 SREG(s) 1
BCLR s Flag Clear SREG(s) 0 SREG(s) 1
BST Rr, b Bit Store from Register to T T Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) T None 1
SEC Set Carry C 1 C1
CLC Clear Carry C 0 C 1
SEN Set Negative Flag N 1 N1
CLN Clear Negative Flag N 0 N 1
SEZ Set Zero Flag Z 1 Z1
CLZ Clear Zero Flag Z 0 Z 1
SEI Global Interrupt Enable I 1 I1
CLI Global Interrupt Disable I 0 I 1
SES Set Signed Test Flag S 1 S1
CLS Clear Signed Test Flag S 0 S 1
SEV Set Twos Complement Overflow. V 1 V1
CLV Clear Twos Complement Overflow V 0 V 1
SET Set T in SREG T 1 T1
CLT Clear T in SREG T 0 T 1
SEH Set Half Carry Flag in SREG H 1 H1
CLH Clear Half Carry Flag in SREG H 0 H 1
DATA TRANSFER INSTRUCTIONS
MOV Rd, Rr Move Between Registers Rd Rr None 1
MOVW Rd, Rr Copy Register Word Rd+1:Rd Rr+1:Rr None 1
LDI Rd, K Load Immediate Rd K None 1
LD Rd, X Load Indirect Rd (X) None 2
LD Rd, X+ Load Indirect and Post-Inc. Rd (X), X X + 1 None 2
LD Rd, - X Load Indirect and Pre-Dec. X X - 1, Rd (X) None 2
LD Rd, Y Load Indirect Rd (Y) None 2
LD Rd, Y+ Load Indirect and Post-Inc. Rd (Y), Y Y + 1 None 2
LD Rd, - Y Load Indirect and Pre-Dec. Y Y - 1, Rd (Y) None 2
LDD Rd,Y+q Load Indirect with Displacement Rd (Y + q) None 2
LD Rd, Z Load Indirect Rd (Z) None 2
LD Rd, Z+ Load Indirect and Post-Inc. Rd (Z), Z Z+1 None 2
LD Rd, -Z Load Indirect and Pre-Dec. Z Z - 1, Rd (Z) None 2
LDD Rd, Z+q Load Indirect with Displacement Rd (Z + q) None 2
LDS Rd, k Load Direct from SRAM Rd (k) None 2
ST X, Rr Store Indirect (X) Rr None 2
ST X+, Rr Store Indirect and Post-Inc. (X) Rr, X X + 1 None 2
ST - X, Rr Store Indirect and Pre-Dec. X X - 1, (X) Rr None 2
ST Y, Rr Store Indirect (Y) Rr None 2
ST Y+, Rr Store Indirect and Post-Inc. (Y) Rr, Y Y + 1 None 2
ST - Y, Rr Store Indirect and Pre-Dec. Y Y - 1, (Y) Rr None 2
STD Y+q,Rr Store Indirect with Displacement (Y + q) Rr None 2
ST Z, Rr Store Indirect (Z) Rr None 2
ST Z+, Rr Store Indirect and Post-Inc. (Z) Rr, Z Z + 1 None 2
ST -Z, Rr Store Indirect and Pre-Dec. Z Z - 1, (Z) Rr None 2
STD Z+q,Rr Store Indirect with Displacement (Z + q) Rr None 2
STS k, Rr Store Direct to SRAM (k) Rr None 2
LPM Load Program Memory R0 (Z) None 3
LPM Rd, Z Load Program Memory Rd (Z) None 3
LPM Rd, Z+ Load Program Memory and Post-Inc Rd (Z), Z Z+1 None 3
SPM Store Program Memory (z) R1:R0 None
IN Rd, P In Port Rd P None 1
OUT P, Rr Out Port P Rr None 1
PUSH Rr Push Register on Stack STACK Rr None 2
POP Rd Pop Register from Stack Rd STACK None 2
MCU CONTROL INSTRUCTIONS
NOP No Operation None 1
SLEEP Sleep (see specific descr. for Sleep function) None 1
WDR Watchdog Reset (see specific descr. for WDR/Timer) None 1
BREAK Break For On-chip Debug Only None N/A
Mnemonics Operands Description Operation Flags #ClocksATtiny1634 [DATASHEET] 280
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29. Ordering Information
Notes: 1. For speed vs. supply voltage, see section 24.3 “Speed” on page 229.
2. All packages are Pb-free, halide-free and fully green, and they comply with the European directive for Restriction of Hazardous
Substances (RoHS).
3. Denotes accuracy of the internal oscillator. See Table 24-2 on page 230.
4. Code indicators:
– U: matte tin
– R: tape & reel
5. Can also be supplied in wafer form. Contact your local Atmel sales office for ordering information and minimum quantities.
29.1 ATtiny1634
Speed (MHz) (1) Supply Voltage (V) Temperature Range Package (2) Accuracy (3) Ordering Code (4)
12 1.8 – 5.5
Industrial
(-40C to +85C)(5)
20M1
±10% ATtiny1634-MU
±2% ATtiny1634R-MU
±10% ATtiny1634-MUR
±2% ATtiny1634R-MUR
20S2
±10% ATtiny1634-SU
±2% ATtiny1634R-SU
±10% ATtiny1634-SUR
±2% ATtiny1634R-SUR
Extended
(-40C to +105C)(5) 20M1
±10% ATtiny1634-MN
±10% ATtiny1634-MNR
Package Type
20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead / Micro Lead Frame Package (QFN/MLF)
20S2 20-lead, 0.300" Wide Body, Plastic Gull Wing Small Outline Package (SOIC)ATtiny1634 [DATASHEET] 281
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30. Packaging Information
30.1 20M1
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO. REV.
20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, 20M1 B
12/02/2014
2.6 mm Exposed Pad, Micro Lead Frame Package (MLF)
A 0.70 0.75 0.80
A1 – 0.01 0.05
A2 0.20 REF
b 0.18 0.23 0.30
D 4.00 BSC
D2 2.45 2.60 2.75
E 4.00 BSC
E2 2.45 2.60 2.75
e 0.50 BSC
L 0.35 0.40 0.55
SIDE VIEW
Pin 1 ID
Pin #1
Notch
(0.20 R)
BOTTOM VIEW
TOP VIEW
Note: Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5.
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D
E
e
A2
A1
A
D2
E2
0.08 C
L
1
2
3
b
1
2
3ATtiny1634 [DATASHEET] 282
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30.2 20S2ATtiny1634 [DATASHEET] 283
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31. Errata
The revision letters in this section refer to the revision of the corresponding ATtiny1634 device.
31.1 ATtiny1634
31.1.1 Rev. C
• Port Pin Should Not Be Used As Input When ULP Oscillator Is Disabled
1. Port Pin Should Not Be Used As Input When ULP Oscillator Is Disabled
Port pin PB3 is not guaranteed to perform as a reliable input when the Ultra Low Power (ULP) oscillator is not
running. In addition, the pin is pulled down internally when ULP oscillator is disabled.
Problem Fix / Workaround
The ULP oscillator is automatically activated when required. To use PB3 as an input, activate the watchdog
timer. The watchdog timer automatically enables the ULP oscillator.
31.1.2 Rev. B
• Port Pin Should Not Be Used As Input When ULP Oscillator Is Disabled
1. Port Pin Should Not Be Used As Input When ULP Oscillator Is Disabled
Port pin PB3 is not guaranteed to perform as a reliable input when the Ultra Low Power (ULP) oscillator is not
running. In addition, the pin is pulled down internally when ULP oscillator is disabled.
Problem Fix / Workaround
The ULP oscillator is automatically activated when required. To use PB3 as an input, activate the watchdog
timer. The watchdog timer automatically enables the ULP oscillator.
31.1.3 Rev. A
• Flash / EEPROM Can Not Be Written When Supply Voltage Is Below 2.4V
• Port Pin Should Not Be Used As Input When ULP Oscillator Is Disabled
1. Flash / EEPROM Can Not Be Written When Supply Voltage Is Below 2.4V
When supply voltage is below 2.4V write operations to Flash and EEPROM may fail.
Problem Fix / Workaround
Do not write to Flash or EEPROM when supply voltage is below 2.4V.
2. Port Pin Should Not Be Used As Input When ULP Oscillator Is Disabled
Port pin PB3 is not guaranteed to perform as a reliable input when the Ultra Low Power (ULP) oscillator is not
running. In addition, the pin is pulled down internally when ULP oscillator is disabled.
Problem Fix / Workaround
The ULP oscillator is automatically activated when required. To use PB3 as an input, activate the watchdog
timer. The watchdog timer automatically enables the ULP oscillator.ATtiny1634 [DATASHEET] 284
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32. Datasheet Revision History
32.1 Rev. 8303H – 02/2014
1. Updated:
– Updated the front page. Temperature range changed to -40C to +105C
– Table 19-2 on page 195. Added 375 LSB for 105C
– “Electrical Characteristics @ 105°C” on page 239
– “Typical Characteristics” on page 242 @ 105C
– “Ordering Information” on page 280. Ordering code: ATtiny1634-MNR added
2. Added:
– “Errata” “Rev. C” on page 283.
32.2 Rev. 8303G – 11/2013
1. Removed references to Wafer Level Chip Scale Package option.
32.3 Rev. 8303F – 08/2013
1. Updated Bit 2 from the UCSR1C register from “USBSZ11” to “UCSZ11” in “Register Summary” on page
276.
32.4 Rev. 8303E – 01/2013
1. Updated:
– Applied the Atmel new brand template that includes new log and new addresses.
32.5 Rev. 8303D – 06/12
1. Updated:
– “Ordering Information” on page 280
2. Added:
– Wafer Level Chip Scale Package “Errata” on page 283
32.6 Rev. 8303C – 03/12
1. Updated:
– “Register Description” on page 167
– “Self-Programming” on page 203
32.7 Rev. 8303B – 03/12
1. Removed Preliminary status.
2. Added:
– “Typical Characteristics” on page 242
– “Temperature Sensor” on page 235
– “Rev. B” on page 283
3. Updated:
– “Pin Descriptions” on page 3
– “Calibrated Internal 8MHz Oscillator” on page 27
– “OSCTCAL0A – Oscillator Temperature Calibration Register A” on page 33ATtiny1634 [DATASHEET] 285
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– “OSCTCAL0B – Oscillator Temperature Calibration Register B” on page 33
– “TWSCRA – TWI Slave Control Register A” on page 127
– “USART (USART0 & USART1)” on page 145
– “Temperature vs. Sensor Output Voltage (Typical)” on page 195
– “DC Characteristics” on page 228
– “Calibration Accuracy of Internal 32kHz Oscillator” on page 231
– “External Clock Drive Characteristics” on page 231
– “Reset, Brown-out, and Internal Voltage Characteristics” on page 231
– “Analog Comparator Characteristics, TA = -40°C to +85°C” on page 235
– “Parallel Programming Characteristics, TA = 25°C, VCC = 5V” on page 237
– “Serial Programming Characteristics, TA = -40°C to +85°C” on page 238
– “Ordering Information” on page 280
32.8 Rev. 8303A – 11/11
Initial revision.ATtiny1634 [DATASHEET] i
Atmel-8303HS-AVR-ATtiny1634-Datasheet_02/2014
Table of Contents
Features .....................................................................................................1
1 Pin Configurations ...................................................................................2
1.1 Pin Descriptions .................................................................................................3
2 Overview ...................................................................................................4
3 General Information .................................................................................6
3.1 Resources .........................................................................................................6
3.2 Code Examples .................................................................................................6
3.3 Capacitive Touch Sensing .................................................................................6
3.4 Data Retention ...................................................................................................6
4 CPU Core ...................................................................................................6
4.1 Architectural Overview .......................................................................................7
4.2 ALU – Arithmetic Logic Unit ...............................................................................8
4.3 Status Register ..................................................................................................8
4.4 General Purpose Register File ..........................................................................8
4.5 Stack Pointer ...................................................................................................10
4.6 Instruction Execution Timing ...........................................................................10
4.7 Reset and Interrupt Handling ...........................................................................11
4.8 Register Description ........................................................................................13
5 Memories .................................................................................................15
5.1 Program Memory (Flash) .................................................................................15
5.2 Data Memory (SRAM) and Register Files .......................................................16
5.3 Data Memory (EEPROM) ................................................................................17
5.4 Register Description ........................................................................................22
6 Clock System ..........................................................................................24
6.1 Clock Subsystems ...........................................................................................25
6.2 Clock Sources .................................................................................................26
6.3 System Clock Prescaler ..................................................................................28
6.4 Clock Output Buffer .........................................................................................29
6.5 Register Description ........................................................................................29
7 Power Management and Sleep Modes .................................................34
7.1 Sleep Modes ....................................................................................................34
7.2 Power Reduction Register ...............................................................................36
7.3 Minimizing Power Consumption ......................................................................36ATtiny1634 [DATASHEET] ii
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7.4 Register Description ........................................................................................37
8 System Control and Reset .....................................................................39
8.1 Resetting the AVR ...........................................................................................39
8.2 Reset Sources .................................................................................................39
8.3 Internal Voltage Reference ..............................................................................42
8.4 Watchdog Timer ..............................................................................................43
8.5 Register Description ........................................................................................44
9 Interrupts .................................................................................................47
9.1 Interrupt Vectors ..............................................................................................47
9.2 External Interrupts ...........................................................................................48
9.3 Register Description ........................................................................................51
10 I/O Ports ..................................................................................................54
10.1 Overview ..........................................................................................................54
10.2 Ports as General Digital I/O .............................................................................54
10.3 Alternate Port Functions ..................................................................................59
10.4 Register Description ........................................................................................71
11 8-bit Timer/Counter0 with PWM ............................................................73
11.1 Features ..........................................................................................................73
11.2 Overview ..........................................................................................................73
11.3 Clock Sources .................................................................................................74
11.4 Counter Unit ....................................................................................................74
11.5 Output Compare Unit .......................................................................................75
11.6 Compare Match Output Unit ............................................................................77
11.7 Modes of Operation .........................................................................................78
11.8 Timer/Counter Timing Diagrams ......................................................................82
11.9 Register Description ........................................................................................84
12 16-bit Timer/Counter1 ............................................................................90
12.1 Features ..........................................................................................................90
12.2 Overview ..........................................................................................................90
12.3 Timer/Counter Clock Sources .........................................................................92
12.4 Counter Unit ....................................................................................................92
12.5 Input Capture Unit ...........................................................................................93
12.6 Output Compare Units .....................................................................................95
12.7 Compare Match Output Unit ............................................................................97
12.8 Modes of Operation .........................................................................................98ATtiny1634 [DATASHEET] iii
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12.9 Timer/Counter Timing Diagrams ....................................................................106
12.10 Accessing 16-bit Registers ............................................................................107
12.11 Register Description ......................................................................................111
13 Timer/Counter Prescaler ......................................................................117
13.1 Prescaler Reset .............................................................................................117
13.2 External Clock Source ...................................................................................118
13.3 Register Description ......................................................................................118
14 I2C Compatible, Two-Wire Slave Interface .........................................119
14.1 Features ........................................................................................................119
14.2 Overview ........................................................................................................119
14.3 General TWI Bus Concepts ...........................................................................119
14.4 TWI Slave Operation .....................................................................................125
14.5 Register Description ......................................................................................127
15 USI – Universal Serial Interface ..........................................................131
15.1 Features ........................................................................................................131
15.2 Overview ........................................................................................................131
15.3 Three-wire Mode ...........................................................................................132
15.4 Two-wire Mode ..............................................................................................134
15.5 Alternative Use ..............................................................................................136
15.6 Program Examples ........................................................................................137
15.7 Register Descriptions ....................................................................................140
16 USART (USART0 & USART1) ..............................................................145
16.1 Features ........................................................................................................145
16.2 USART0 and USART1 ..................................................................................145
16.3 Overview ........................................................................................................145
16.4 Clock Generation ...........................................................................................147
16.5 Frame Formats ..............................................................................................149
16.6 USART Initialization .......................................................................................151
16.7 Data Transmission – The USART Transmitter ..............................................152
16.8 Data Reception – The USART Receiver .......................................................154
16.9 Asynchronous Data Reception ......................................................................158
16.10 Multi-processor Communication Mode ..........................................................162
16.11 Examples of Baud Rate Setting .....................................................................163
16.12 Register Description ......................................................................................167
17 USART in SPI Mode ..............................................................................173ATtiny1634 [DATASHEET] iv
Atmel-8303HS-AVR-ATtiny1634-Datasheet_02/2014
17.1 Features ........................................................................................................173
17.2 Overview ........................................................................................................173
17.3 Clock Generation ...........................................................................................173
17.4 SPI Data Modes and Timing ..........................................................................173
17.5 Frame Formats ..............................................................................................174
17.6 Data Transfer .................................................................................................176
17.7 Compatibility with AVR SPI ...........................................................................178
17.8 Register Description ......................................................................................178
18 Analog Comparator ..............................................................................181
18.1 Analog Comparator Multiplexed Input ...........................................................181
18.2 Register Description ......................................................................................182
19 Analog to Digital Converter .................................................................185
19.1 Features ........................................................................................................185
19.2 Overview ........................................................................................................185
19.3 Operation .......................................................................................................186
19.4 Starting a Conversion ....................................................................................187
19.5 Prescaling and Conversion Timing ................................................................188
19.6 Changing Channel or Reference Selection ...................................................191
19.7 ADC Noise Canceler .....................................................................................192
19.8 Analog Input Circuitry ....................................................................................192
19.9 Noise Canceling Techniques .........................................................................193
19.10 ADC Accuracy Definitions .............................................................................193
19.11 ADC Conversion Result .................................................................................195
19.12 Temperature Measurement ...........................................................................195
19.13 Register Description ......................................................................................196
20 debugWIRE On-chip Debug System ...................................................201
20.1 Features ........................................................................................................201
20.2 Overview ........................................................................................................201
20.3 Physical Interface ..........................................................................................201
20.4 Software Break Points ...................................................................................202
20.5 Limitations of debugWIRE .............................................................................202
20.6 Register Description ......................................................................................202
21 Self-Programming ................................................................................203
21.1 Features ........................................................................................................203
21.2 Overview ........................................................................................................203ATtiny1634 [DATASHEET] v
Atmel-8303HS-AVR-ATtiny1634-Datasheet_02/2014
21.3 Lock Bits ........................................................................................................203
21.4 Self-Programming the Flash ..........................................................................203
21.5 Preventing Flash Corruption ..........................................................................206
21.6 Programming Time for Flash when Using SPM .............................................206
21.7 Register Description ......................................................................................207
22 Lock Bits, Fuse Bits and Device Signature .......................................208
22.1 Lock Bits ........................................................................................................208
22.2 Fuse Bits ........................................................................................................209
22.3 Device Signature Imprint Table .....................................................................210
22.4 Reading Lock, Fuse and Signature Data from Software ...............................211
23 External Programming .........................................................................214
23.1 Memory Parametrics .....................................................................................214
23.2 Parallel Programming ....................................................................................214
23.3 Serial Programming .......................................................................................223
23.4 Programming Time for Flash and EEPROM ..................................................227
24 Electrical Characteristics ....................................................................228
24.1 Absolute Maximum Ratings* .........................................................................228
24.2 DC Characteristics .........................................................................................228
24.3 Speed ............................................................................................................229
24.4 Clock ..............................................................................................................230
24.5 System and Reset .........................................................................................231
24.6 Two-Wire Serial Interface ..............................................................................233
24.7 Analog to Digital Converter ............................................................................234
24.8 Analog Comparator .......................................................................................235
24.9 Temperature Sensor ......................................................................................235
24.10 Parallel Programming ....................................................................................235
24.11 Serial Programming .......................................................................................238
25 Electrical Characteristics @ 105C .....................................................239
25.1 Absolute Maximum Ratings* .........................................................................239
25.2 DC Characteristics .........................................................................................239
25.3 Clock ..............................................................................................................240
25.4 System and Reset .........................................................................................241
26 Typical Characteristics ........................................................................242
26.1 Current Consumption in Active Mode ............................................................242
26.2 Current Consumption in Idle Mode ................................................................245ATtiny1634 [DATASHEET] vi
Atmel-8303HS-AVR-ATtiny1634-Datasheet_02/2014
26.3 Current Consumption in Standby Mode ........................................................247
26.4 Current Consumption in Power-down Mode ..................................................248
26.5 Current Consumption in Reset ......................................................................249
26.6 Current Consumption of Peripheral Units ......................................................250
26.7 Pull-up Resistors ...........................................................................................253
26.8 Input Thresholds ............................................................................................256
26.9 Output Driver Strength ...................................................................................259
26.10 BOD ...............................................................................................................265
26.11 Bandgap Voltage ...........................................................................................268
26.12 Reset .............................................................................................................269
26.13 Analog Comparator Offset .............................................................................271
26.14 Internal Oscillator Speed ...............................................................................272
27 Register Summary ................................................................................276
28 Instruction Set Summary .....................................................................278
29 Ordering Information ...........................................................................280
29.1 ATtiny1634 ....................................................................................................280
30 Packaging Information .........................................................................281
30.1 20M1 ..............................................................................................................281
30.2 20S2 ..............................................................................................................282
31 Errata .....................................................................................................283
31.1 ATtiny1634 ....................................................................................................283
32 Datasheet Revision History .................................................................284
32.1 Rev. 8303H – 02/2014 ...................................................................................284
32.2 Rev. 8303G – 11/2013 ..................................................................................284
32.3 Rev. 8303F – 08/2013 ...................................................................................284
32.4 Rev. 8303E – 01/2013 ...................................................................................284
32.5 Rev. 8303D – 06/12 .......................................................................................284
32.6 Rev. 8303C – 03/12 .......................................................................................284
32.7 Rev. 8303B – 03/12 .......................................................................................284
32.8 Rev. 8303A – 11/11 .......................................................................................285
Table of Contents.......................................................................................iX X X X X X
Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com
© 2014 Atmel Corporation. / Rev.: Atmel-8303H-AVR-ATtiny1634-Datasheet_02/2014.
Atmel®, Atmel logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product
names may be trademarks of others.
DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right
is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE
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Features
• High Performance, Low Power Atmel®AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16MHz
– On-Chip 2-cycle Multiplier
• High Endurance Non-volatile Memory Segments
– In-System Self-programmable Flash Program Memory
• 32KBytes (ATmega329/ATmega3290)
• 64KBytes (ATmega649/ATmega6490)
– EEPROM
• 1Kbytes (ATmega329/ATmega3290)
• 2Kbytes (ATmega649/ATmega6490)
– Internal SRAM
• 2Kbytes (ATmega329/ATmega3290)
• 4Kbytes (ATmega649/ATmega6490)
– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C(1)
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– Programming Lock for Software Security
• JTAG (IEEE std. 1149.1 compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• Peripheral Features
– 4 x 25 Segment LCD Driver (ATmega329/ATmega649)
– 4 x 40 Segment LCD Driver (ATmega3290/ATmega6490)
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Universal Serial Interface with Start Condition Detector
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and
Standby
• I/O and Packages
– 53/68 Programmable I/O Lines
– 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP
• Speed Grade:
– ATmega329V/ATmega3290V/ATmega649V/ATmega6490V:
– 0 - 4MHz @ 1.8 - 5.5V, 0 - 8MHz @ 2.7 - 5.5V
– ATmega329/3290/649/6490:
– 0 - 8MHz @ 2.7 - 5.5V, 0 - 16MHz @ 4.5 - 5.5V
• Temperature range:
– -40°C to 85°C Industrial
• Ultra-Low Power Consumption
– Active Mode:
• 1MHz, 1.8V: 350µA
• 32kHz, 1.8V: 20µA (including Oscillator)
• 32kHz, 1.8V: 40µA (including Oscillator and LCD)
– Power-down Mode:
• 100nA at 1.8V
8-bit Atmel
Microcontroller
with In-System
Programmable
Flash
ATmega329/V
ATmega3290/V
ATmega649/V
ATmega6490/V
2552K–AVR–04/112
2552K–AVR–04/11
ATmega329/3290/649/6490
1. Pin Configurations
Figure 1-1. Pinout ATmega3290/6490 (OC2A/PCINT15) PB7 DNC (T1/SEG33) PG3 (T0/SEG32) PG4 RESET/PG5
VCC
GND
(TOSC2) XTAL2
(TOSC1) XTAL1
DNC
DNC
(PCINT26/SEG31) PJ2
(PCINT27/SEG30) PJ3
(PCINT28/SEG29) PJ4
(PCINT29/SEG28) PJ5
(PCINT30/SEG27) PJ6
DNC
(ICP1/SEG26) PD0
(INT0/SEG25) PD1
(SEG24) PD2
(SEG23) PD3
(SEG22) PD4
(SEG21) PD5
(SEG20) PD6
(SEG19) PD7
AVCC
AGND
AREF
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
PF7 (ADC7/TDI)
DNC
DNC
PH7 (PCINT23/SEG36)
PH6 (PCINT22/SEG37)
PH5 (PCINT21/SEG38)
PH4 (PCINT20/SEG39)
DNC
DNC
GND
VCC
DNC
PA0 (COM0)
PA1 (COM1)
PA2 (COM2)
PA3 (COM3)
PA4 (SEG0)
PA5 (SEG1)
PA6 (SEG2)
PA7 (SEG3)
PG2 (SEG4)
PC7 (SEG5)
PC6 (SEG6)
DNC
PH3 (PCINT19/SEG7)
PH2 (PCINT18/SEG8)
PH1 (PCINT17/SEG9)
PH0 (PCINT16/SEG10)
DNC
DNC
DNC
DNC
PC5 (SEG11)
PC4 (SEG12)
PC3 (SEG13)
PC2 (SEG14)
PC1 (SEG15)
PC0 (SEG16)
PG1 (SEG17)
PG0 (SEG18)
INDEX CORNER
ATmega3290/6490
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
LCDCAP
(RXD/PCINT0) PE0
(TXD/PCINT1) PE1
(XCK/AIN0/PCINT2) PE2
(AIN1/PCINT3) PE3
(USCK/SCL/PCINT4) PE4
(DI/SDA/PCINT5) PE5
(DO/PCINT6) PE6
(CLKO/PCINT7) PE7
VCC
GND
DNC
(PCINT24/SEG35) PJ0
(PCINT25/SEG34) PJ1
DNC
DNC
DNC
DNC
(SS/PCINT8) PB0
(SCK/PCINT9) PB1
(MOSI/PCINT10) PB2
(MISO/PCINT11) PB3
(OC0A/PCINT12) PB4
(OC1A/PCINT13) PB5
(OC1B/PCINT14) PB6
TQFP3
2552K–AVR–04/11
ATmega329/3290/649/6490
Figure 1-2. Pinout ATmega329/649
Note: The large center pad underneath the QFN/MLF packages is made of metal and internally connected
to GND. It should be soldered or glued to the board to ensure good mechanical stability. If
the center pad is left unconnected, the package might loosen from the board.
PC0 (SEG12)
VCC
A
GND
AREF
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
PF7 (ADC7/TDI)
GND
VCC 17
61
60
18
59
20
58
19
21
57
22
56
23
55
24
54
25
53
26
52
27
51
28
29
50
49
30
31
32
(RXD/PCINT0) PE0
(TXD/PCINT1) PE1
LCDCAP
(XCK/AIN0/PCINT2) PE2
(AIN1/PCINT3) PE3
(USCK/SCL/PCINT4) PE4
(DI/SDA/PCINT5) PE5
(DO/PCINT6) PE6
(CLKO/PCINT7) PE7
(SCK/PCINT9) PB1
(MOSI/PCINT10) PB2
(MISO/PCINT11) PB3
(OC0A/PCINT12) PB4
(OC2A/PCINT15) PB7
(T1/SEG24) PG3
(OC1B/PCINT14) PB6
(T0/SEG23) PG4
(OC1A/PCINT13) PB5
PC1 (SEG11)
PG0 (SEG14)
(SEG15) PD7
PC2 (SEG10)
PC3 (SEG9)
PC4 (SEG8)
PC5 (SEG7)
PC6 (SEG6)
PC7 (SEG5)
PA7 (SEG3)
PG2 (SEG4)
PA6 (SEG2)
PA5 (SEG1)
PA4 (SEG0)
PA3 (COM3)
PA0 (COM0)
PA1 (COM1)
PA2 (COM2)
PG1 (SEG13)
(SEG19) PD3
(SEG18) PD4
(SEG17) PD5
(SEG16) PD6
(SEG20) PD2
(ICP1/SEG22) PD0
(INT0/SEG21) PD1
(TOSC2) XTAL2
(TOSC1) XTAL1
RESET/PG5
V
GND
CC
INDEX CORNER
(SS/PCINT8) PB0
2
3
1
4
5
6
7
8
9
10
11
12
13
14
16
15
64
63
62
47
46
48
45
44
43
42
41
40
39
38
37
36
35
33
34
ATmega329/6494
2552K–AVR–04/11
ATmega329/3290/649/6490
2. Overview
The ATmega329/3290/649/6490 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture.
By executing powerful instructions in a single clock cycle, the ATmega329/3290/649/6490 achieves throughputs
approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
2.1 Block Diagram
Figure 2-1. Block Diagram
PROGRAM
COUNTER
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
STACK
POINTER
PROGRAM
FLASH
MCU CONTROL
REGISTER SRAM
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
TIMER/
COUNTERS
INSTRUCTION
DECODER
DATA DIR.
REG. PORTB
DATA DIR.
REG. PORTE
DATA DIR.
REG. PORTA
DATA DIR.
REG. PORTD
DATA REGISTER
PORTB
DATA REGISTER
PORTE
DATA REGISTER
PORTA
DATA REGISTER
PORTD
TIMING AND
CONTROL
OSCILLATOR
INTERRUPT
UNIT
EEPROM
USART SPI
STATUS
REGISTER
Z
Y
X
ALU
PORTE DRIVERS PORTB DRIVERS
PORTF DRIVERS PORTA DRIVERS
PORTD DRIVERS
PORTC DRIVERS
PE0 - PE7 PB0 - PB7
PF0 - PF7 PA0 - PA7 GND VCC
XTAL1
XTAL2
CONTROL
LINES
+
-
ANALOG
COMPARATOR
PC0 - PC7
8-BIT DATA BUS
RESET
CALIB. OSC
DATA DIR.
REG. PORTC
DATA REGISTER
PORTC
ON-CHIP DEBUG
JTAG TAP
PROGRAMMING
LOGIC
BOUNDARYSCAN
DATA DIR.
REG. PORTF
DATA REGISTER
PORTF
ADC
PD0 - PD7
DATA DIR.
REG. PORTG
DATA REG.
PORTG
PORTG DRIVERS
PG0 - PG4
AGND
AREF
AVCC
UNIVERSAL
SERIAL INTERFACE
AVR CPU
LCD
CONTROLLER/
DRIVER
PORTH DRIVERS
PH0 - PH7
DATA DIR.
REG. PORTH
DATA REGISTER
PORTH
PORTJ DRIVERS
PJ0 - PJ6
DATA DIR.
REG. PORTJ
DATA REGISTER
PORTJ5
2552K–AVR–04/11
ATmega329/3290/649/6490
The Atmel® AVR® core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two
independent registers to be accessed in one single instruction executed in one clock cycle. The
resulting architecture is more code efficient while achieving throughputs up to ten times faster
than conventional CISC microcontrollers.
The Atmel ATmega329/3290/649/6490 provides the following features: 32/64K bytes of In-System
Programmable Flash with Read-While-Write capabilities, 1/2K bytes EEPROM, 2/4K byte
SRAM, 54/69 general purpose I/O lines, 32 general purpose working registers, a JTAG interface
for Boundary-scan, On-chip Debugging support and programming, a complete On-chip LCD
controller with internal contrast control, three flexible Timer/Counters with compare modes, internal
and external interrupts, a serial programmable USART, Universal Serial Interface with Start
Condition Detector, an 8-channel, 10-bit ADC, a programmable Watchdog Timer with internal
Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode
stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue
functioning. The Power-down mode saves the register contents but freezes the Oscillator,
disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode,
the asynchronous timer and the LCD controller continues to run, allowing the user to maintain a
timer base and operate the LCD display while the rest of the device is sleeping. The ADC Noise
Reduction mode stops the CPU and all I/O modules except asynchronous timer, LCD controller
and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator
Oscillator is running while the rest of the device is sleeping. This allows very fast
start-up combined with low-power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip In-System re-Programmable (ISP) Flash allows the program memory to be reprogrammed
In-System through an SPI serial interface, by a conventional non-volatile memory
programmer, or by an On-chip Boot program running on the AVR core. The Boot program can
use any interface to download the application program in the Application Flash memory. Software
in the Boot Flash section will continue to run while the Application Flash section is updated,
providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System
Self-Programmable Flash on a monolithic chip, the Atmel ATmega329/3290/649/6490 is a powerful
microcontroller that provides a highly flexible and cost effective solution to many embedded
control applications.
The Atmel ATmega329/3290/649/6490 is supported with a full suite of program and system
development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators,
In-Circuit Emulators, and Evaluation kits.6
2552K–AVR–04/11
ATmega329/3290/649/6490
2.2 Comparison between ATmega329, ATmega3290, ATmega649 and ATmega6490
The ATmega329, ATmega3290, ATmega649, and ATmega6490 differs only in memory sizes,
pin count and pinout. Table 2-1 on page 6 summarizes the different configurations for the four
devices.
2.3 Pin Descriptions
The following section describes the I/O-pin special functions.
2.3.1 VCC
Digital supply voltage.
2.3.2 GND
Ground.
2.3.3 Port A (PA7..PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port A also serves the functions of various special features of the ATmega329/3290/649/6490
as listed on page 67.
2.3.4 Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B has better driving capabilities than the other ports.
Port B also serves the functions of various special features of the ATmega329/3290/649/6490
as listed on page 68.
Table 2-1. Configuration Summary
Device Flash EEPROM RAM
LCD
Segments
General Purpose
I/O Pins
ATmega329 32Kbytes 1Kbytes 2Kbytes 4 x 25 54
ATmega3290 32Kbytes 1K bytes 2Kbytes 4 x 40 69
ATmega649 64Kbytes 2Kbytes 4Kbytes 4 x 25 54
ATmega6490 64Kbytes 2Kbytes 4Kbytes 4 x 40 697
2552K–AVR–04/11
ATmega329/3290/649/6490
2.3.5 Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of special features of the ATmega329/3290/649/6490 as listed
on page 71.
2.3.6 Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATmega329/3290/649/6490
as listed on page 73.
2.3.7 Port E (PE7..PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port E also serves the functions of various special features of the ATmega329/3290/649/6490
as listed on page 75.
2.3.8 Port F (PF7..PF0)
Port F serves as the analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical
drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will
be activated even if a reset occurs.
Port F also serves the functions of the JTAG interface.8
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2.3.9 Port G (PG5..PG0)
Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port G output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port G pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port G also serves the functions of various special features of the ATmega329/3290/649/6490
as listed on page 75.
2.3.10 Port H (PH7..PH0)
Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port H output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port H pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port H also serves the functions of various special features of the ATmega3290/6490 as listed
on page 75.
2.3.11 Port J (PJ6..PJ0)
Port J is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port J output buffers have symmetrical drive characteristics with both high sink and source capability.
As inputs, Port J pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port J pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port J also serves the functions of various special features of the ATmega3290/6490 as listed on
page 75.
2.3.12 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in “System and Reset
Characteristics” on page 330. Shorter pulses are not guaranteed to generate a reset.
2.3.13 XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
2.3.14 XTAL2
Output from the inverting Oscillator amplifier.
2.3.15 AVCC
AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected
to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC
through a low-pass filter.
2.3.16 AREF
This is the analog reference pin for the A/D Converter.9
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2.3.17 LCDCAP
An external capacitor (typical > 470nF) must be connected to the LCDCAP pin as shown in Figure
23-2. This capacitor acts as a reservoir for LCD power (VLCD). A large capacitance reduces
ripple on VLCD but increases the time until VLCD reaches its target value.
3. Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
Note: 1.
4. Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
5. About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. These code examples assume that the part specific header file is included before
compilation. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation
for more details.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.10
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6. AVR CPU Core
6.1 Overview
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
6.2 Architectural Overview
Figure 6-1. Block Diagram of the AVR Architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruction
is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
Direct Addressing
Indirect Addressing
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
I/O Module 2
I/O Module1
I/O Module n11
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The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical
ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointers
can also be used as an address pointer for look up tables in Flash program memory. These
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single register operations can also be executed in the ALU. After an arithmetic operation,
the Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most AVR instructions have a single 16-bit word format.
Every program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the
Application Program section. Both sections have dedicated Lock bits for write and read/write
protection. The SPM instruction that writes into the Application Flash memory section must
reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack
Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position.
The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers,
SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data
Space locations following those of the Register File, 0x20 - 0x5F. In addition, the
ATmega329/3290/649/6490 has Extended I/O space from 0x60 - 0xFF in SRAM where only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
6.3 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general purpose
registers or between a register and an immediate are executed. The ALU operations are divided
into three main categories – arithmetic, logical, and bit-functions. Some implementations of the
architecture also provide a powerful multiplier supporting both signed/unsigned multiplication
and fractional format. See the “Instruction Set” section for a detailed description.12
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6.4 AVR Status Register
The Status Register contains information about the result of the most recently executed arithmetic
instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the Instruction Set Reference. This will in many cases remove the need for using the
dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored
when returning from an interrupt. This must be handled by software.
6.4.1 SREG – AVR Status Register
The AVR Status Register – SREG – is defined as:
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt
enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination
for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful
in BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
Bit 7 6 5 4 3 2 1 0
0x3F (0x5F) I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 013
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• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
6.5 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve
the required performance and flexibility, the following input/output schemes are supported by the
Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 6-2 shows the structure of the 32 general purpose working registers in the CPU.
Figure 6-2. AVR CPU General Purpose Working Registers
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 6-2, each register is also assigned a data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically implemented
as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
7 0 Addr.
R0 0x00
R1 0x01
R2 0x02
…
R13 0x0D
General R14 0x0E
Purpose R15 0x0F
Working R16 0x10
Registers R17 0x11
…
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte14
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6.5.1 The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers
are 16-bit address pointers for indirect addressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in Figure 6-3.
Figure 6-3. The X-, Y-, and Z-registers
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
6.6 Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations
to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack
with the PUSH instruction, and it is decremented by two when the return address is pushed onto
the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is incremented by two when data is
popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementations
of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
15 XH XL 0
X-register 7 07 0
R27 (0x1B) R26 (0x1A)
15 YH YL 0
Y-register 7 07 0
R29 (0x1D) R28 (0x1C)
15 ZH ZL 0
Z-register 70 7 0
R31 (0x1F) R30 (0x1E)
Bit 15 14 13 12 11 10 9 8
0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH
0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
0000000015
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6.7 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the
chip. No internal clock division is used.
Figure 6-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard
architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 6-4. The Parallel Instruction Fetches and Instruction Executions
Figure 6-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destination
register.
Figure 6-5. Single Cycle ALU Operation
6.8 Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section “Memory Programming”
on page 293 for details.
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 49. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clkCPU16
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priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL
bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 49 for more information.
The Reset Vector can also be moved to the start of the Boot Flash section by programming the
BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page
278.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled.
The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector
in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)
to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt
Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The following example shows how this can be used to avoid interrupts during the
timed EEPROM write sequence.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMWE ; start EEPROM write
sbi EECR, EEWE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
__disable_interrupt();
EECR |= (1< xxx
;
.org 0x3802/0x7802
0x3804/0x7804 jmp EXT_INT0 ; IRQ0 Handler
0x3806/0x7806 jmp PCINT0 ; PCINT0 Handler
... ... ... ;
0x1C2C jmp SPM_RDY ; Store Program Memory Ready Handler
When the BOOTRST Fuse is programmed and the Boot section size set to 4K bytes, the most
typical and general program setup for the Reset and Interrupt Vector Addresses is:
Address Labels Code Comments
.org 0x0002
0x0002 jmp EXT_INT0 ; IRQ0 Handler
0x002
2
jmp USI_OVF ; USI Overflow Handler
0x002
4
jmp ANA_COMP ; Analog Comparator Handler
0x002
6
jmp ADC ; ADC Conversion Complete
Handler
0x002
8
jmp EE_RDY ; EEPROM Ready Handler
0x002
A
jmp SPM_RDY ; SPM Ready Handler
0x002
C
jmp LCD_SOF ; LCD Start of Frame Handler
0x002
E
jmp PCINT2 ; PCINT2 Handler
0x003
0
jmp PCINT3 ; PCINT3 Handler
;
0x003
2
RESET
:
ldi r16,
high(RAMEND)
; Main program start
0x003
3
out SPH,r16 ; Set Stack Pointer to top of
RAM
0x003
4
ldi r16, low(RAMEND)
0x003
5
out SPL,r16
0x003
6
sei ; Enable interrupts
0x003
7
xxx
... ... ...52
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0x0004 jmp PCINT0 ; PCINT0 Handler
... ... ... ;
0x002C jmp SPM_RDY ; Store Program Memory Ready Handler
;
.org 0x3800/0x7800
0x3800/0x7801RESET:ldir16,high(RAMEND); Main program start
0x3801/0x7801 out SPH,r16 ; Set Stack Pointer to top of RAM
0x3802/0x7802 ldi r16,low(RAMEND)
0x3803/0x7803 out SPL,r16
0x3804/0x7804 sei ; Enable interrupts
0x3805/0x7805 xxx
When the BOOTRST Fuse is programmed, the Boot section size set to 4K bytes and the IVSEL
bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general
program setup for the Reset and Interrupt Vector Addresses is:
Address Labels Code Comments
;
.org 0x3800/0x7800
0x3800/0x7800 jmp RESET ; Reset handler
0x3802/0x7802 jmp EXT_INT0 ; IRQ0 Handler
0x3804/0x7804 jmp PCINT0 ; PCINT0 Handler
... ... ... ;
0x382C/0x782C jmp SPM_RDY ; Store Program Memory Ready Handler
;
0x382E/0x782ERESET:ldir16,high(RAMEND); Main program start
0x382F/0x782F out SPH,r16 ; Set Stack Pointer to top of RAM
0x3830/0x7830 ldi r16,low(RAMEND)
0x3831/0x7831 out SPL,r16
0x3832/0x7832 sei ; Enable interrupts
0x3833/0x7833 xxx
11.1.1 Moving Interrupts Between Application and Boot Space
The MCU Control Register controls the placement of the Interrupt Vector table.
11.2 Register Description
11.2.1 MCUCR – MCU Control Register
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash
memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot
Loader section of the Flash. The actual address of the start of the Boot Flash Section is determined
by the BOOTSZ Fuses. Refer to the section “Boot Loader Support – Read-While-Write
Bit 7 6 5 4 3 2 1 0
0x35 (0x55) JTD – – PUD – – IVSEL IVCE MCUCR
Read/Write R/W R R R/W R R R/W R/W
Initial Value 0 0 0 0 0 0 0 053
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Self-Programming” on page 278 for details. To avoid unintentional changes of Interrupt Vector
tables, a special write procedure must be followed to change the IVSEL bit:
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled
in the cycle IVCE is set, and they remain disabled until after the instruction following the write to
IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status
Register is unaffected by the automatic disabling.
Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,
interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed
in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while
executing from the Boot Loader section. Refer to the section “Boot Loader Support – Read-WhileWrite
Self-Programming” on page 278 for details on Boot Lock bits.
• Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by
hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable
interrupts, as explained in the IVSEL description above. See Code Example below.
Assembly Code Example
Move_interrupts:
;Get MCUCR
in r16, MCUCR
mov r17, r16
; Enable change of Interrupt Vectors
ori r16, (1<