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Farnell PDF
Atmel ATtiny25, ATtiny45, ATtiny85 Datasheet - Farnell Element 14
Atmel ATtiny25, ATtiny45, ATtiny85 Datasheet - Farnell Element 14
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Farnell Element 14 :
See the trailer for the next exciting episode of The Ben Heck show. Check back on Friday to be among the first to see the exclusive full show on element…
Connect your Raspberry Pi to a breadboard, download some code and create a push-button audio play project.
Puce électronique / Microchip :
Sans fil - Wireless :
Texas instrument :
Ordinateurs :
Logiciels :
Tutoriels :
Autres documentations :
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2586Q–AVR–08/2013
Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
• Non-volatile Program and Data Memories
– 2/4/8K Bytes of In-System Programmable Program Memory Flash
• Endurance: 10,000 Write/Erase Cycles
– 128/256/512 Bytes In-System Programmable EEPROM
• Endurance: 100,000 Write/Erase Cycles
– 128/256/512 Bytes Internal SRAM
– Programming Lock for Self-Programming Flash Program and EEPROM Data Security
• Peripheral Features
– 8-bit Timer/Counter with Prescaler and Two PWM Channels
– 8-bit High Speed Timer/Counter with Separate Prescaler
• 2 High Frequency PWM Outputs with Separate Output Compare Registers
• Programmable Dead Time Generator
– USI – Universal Serial Interface with Start Condition Detector
– 10-bit ADC
• 4 Single Ended Channels
• 2 Differential ADC Channel Pairs with Programmable Gain (1x, 20x)
• Temperature Measurement
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
• I/O and Packages
– Six Programmable I/O Lines
– 8-pin PDIP, 8-pin SOIC, 20-pad QFN/MLF, and 8-pin TSSOP (only ATtiny45/V)
• Operating Voltage
– 1.8 - 5.5V for ATtiny25V/45V/85V
– 2.7 - 5.5V for ATtiny25/45/85
• Speed Grade
– ATtiny25V/45V/85V: 0 – 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
– ATtiny25/45/85: 0 – 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
• Industrial Temperature Range
• Low Power Consumption
– Active Mode:
• 1 MHz, 1.8V: 300 µA
– Power-down Mode:
• 0.1 µA at 1.8V
Atmel 8-bit AVR Microcontroller with 2/4/8K
Bytes In-System Programmable Flash
ATtiny25/V / ATtiny45/V / ATtiny85/V
Rev. 2586Q–AVR–08/2013ATtiny25/45/85 [DATASHEET] 2
2586Q–AVR–08/2013
1. Pin Configurations
Figure 1-1. Pinout ATtiny25/45/85
1.1 Pin Descriptions
1.1.1 VCC
Supply voltage.
1.1.2 GND
Ground.
1.1.3 Port B (PB5:PB0)
Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers
have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
1
2
3
4
8
7
6
5
(PCINT5/RESET/ADC0/dW) PB5
(PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3
(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4
GND
VCC
PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)
PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)
PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)
PDIP/SOIC/TSSOP
1
2
3
4
5
QFN/MLF
15
14
13
12
11
20
19
18
17
16
6
7
8
9
10
DNC
DNC
GND
DNC
DNC
DNC
DNC
DNC
DNC
DNC
NOTE: Bottom pad should be soldered to ground.
DNC: Do Not Connect
NOTE: TSSOP only for ATtiny45/V
(PCINT5/RESET/ADC0/dW) PB5
(PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3
DNC
DNC
(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4
VCC
PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)
DNC
PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)
PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)ATtiny25/45/85 [DATASHEET] 3
2586Q–AVR–08/2013
Port B also serves the functions of various special features of the ATtiny25/45/85 as listed in “Alternate Functions
of Port B” on page 60.
On ATtiny25, the programmable I/O ports PB3 and PB4 (pins 2 and 3) are exchanged in ATtiny15 Compatibility
Mode for supporting the backward compatibility with ATtiny15.
1.1.4 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock
is not running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 21-4
on page 165. Shorter pulses are not guaranteed to generate a reset.
The reset pin can also be used as a (weak) I/O pin.ATtiny25/45/85 [DATASHEET] 4
2586Q–AVR–08/2013
2. Overview
The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By
executing powerful instructions in a single clock cycle, the ATtiny25/45/85 achieves throughputs approaching 1
MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
2.1 Block Diagram
Figure 2-1. Block Diagram
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are
directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one
single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
PROGRAM
COUNTER
CALIBRATED
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
STACK
POINTER
PROGRAM
FLASH SRAM
MCU CONTROL
REGISTER
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
TIMER/
COUNTER0
SERIAL
UNIVERSAL
INTERFACE
TIMER/
COUNTER1
INSTRUCTION
DECODER
DATA DIR.
REG.PORT B
DATA REGISTER
PORT B
PROGRAMMING
LOGIC
TIMING AND
CONTROL
MCU STATUS
REGISTER
STATUS
REGISTER
ALU
PORT B DRIVERS
PB[0:5]
VCC
GND
CONTROL
LINES
8-BIT DATABUS
Z
ADC /
ANALOG COMPARATOR
INTERRUPT
UNIT
DATA
EEPROM OSCILLATORS
Y
X
RESETATtiny25/45/85 [DATASHEET] 5
2586Q–AVR–08/2013
The ATtiny25/45/85 provides the following features: 2/4/8K bytes of In-System Programmable Flash, 128/256/512
bytes EEPROM, 128/256/256 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working registers, one
8-bit Timer/Counter with compare modes, one 8-bit high speed Timer/Counter, Universal Serial Interface, Internal
and External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and
three software selectable power saving modes. Idle mode stops the CPU while allowing the SRAM, Timer/Counter,
ADC, Analog Comparator, and Interrupt system to continue functioning. Power-down mode saves the register contents,
disabling all chip functions until the next Interrupt or Hardware Reset. ADC Noise Reduction mode stops the
CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions.
The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash
allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional
non-volatile memory programmer or by an On-chip boot code running on the AVR core.
The ATtiny25/45/85 AVR is supported with a full suite of program and system development tools including: C Compilers,
Macro Assemblers, Program Debugger/Simulators and Evaluation kits.ATtiny25/45/85 [DATASHEET] 6
2586Q–AVR–08/2013
3. About
3.1 Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
http://www.atmel.com/avr.
3.2 Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. These
code examples assume that the part specific header file is included before compilation. Be aware that not all C
compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent.
Please confirm with the C compiler documentation for more details.
For I/O Registers located in the extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must
be replaced with instructions that allow access to extended I/O. Typically, this means “LDS” and “STS” combined
with “SBRS”, “SBRC”, “SBR”, and “CBR”. Note that not all AVR devices include an extended I/O map.
3.3 Capacitive Touch Sensing
Atmel QTouch Library provides a simple to use solution for touch sensitive interfaces on Atmel AVR microcontrollers.
The QTouch Library includes support for QTouch® and QMatrix® acquisition methods.
Touch sensing is easily added to any application by linking the QTouch Library and using the Application Programming
Interface (API) of the library to define the touch channels and sensors. The application then calls the API to
retrieve channel information and determine the state of the touch sensor.
The QTouch Library is free and can be downloaded from the Atmel website. For more information and details of
implementation, refer to the QTouch Library User Guide – also available from the Atmel website.
3.4 Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20
years at 85°C or 100 years at 25°C.ATtiny25/45/85 [DATASHEET] 7
2586Q–AVR–08/2013
4. AVR CPU Core
4.1 Introduction
This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct
program execution. The CPU must therefore be able to access memories, perform calculations, control
peripherals, and handle interrupts.
4.2 Architectural Overview
Figure 4-1. Block Diagram of the AVR Architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories
and buses for program and data. Instructions in the Program memory are executed with a single level pipelining.
While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept
enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable
Flash memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle
access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operFlash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
Direct Addressing
Indirect Addressing
Interrupt
Unit
Watchdog
Timer
Analog
Comparator
I/O Module 2
I/O Module1
I/O Module nATtiny25/45/85 [DATASHEET] 8
2586Q–AVR–08/2013
ands are output from the Register File, the operation is executed, and the result is stored back in the Register File
– in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing –
enabling efficient address calculations. One of the these address pointers can also be used as an address pointer
for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register,
described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single
register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated
to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the
whole address space. Most AVR instructions have a single 16-bit word format, but there are also 32-bit
instructions.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack
is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total
SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines
or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data
SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in
the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have
priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the
priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other
I/O functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the Register
File, 0x20 - 0x5F.
4.3 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers.
Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an
immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bitfunctions.
Some implementations of the architecture also provide a powerful multiplier supporting both
signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.
4.4 Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction. This
information can be used for altering program flow in order to perform conditional operations. Note that the Status
Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases
remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when returning
from an interrupt. This must be handled by software.ATtiny25/45/85 [DATASHEET] 9
2586Q–AVR–08/2013
4.4.1 SREG – AVR Status Register
The AVR Status Register – SREG – is defined as:
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control
is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts
are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an
interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set
and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated
bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be
copied into a bit in a register in the Register File by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic.
See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See
the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description”
for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for
detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for
detailed information.
Bit 7 6 5 4 3 2 1 0
0x3F I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0ATtiny25/45/85 [DATASHEET] 10
2586Q–AVR–08/2013
4.5 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance
and flexibility, the following input/output schemes are supported by the Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU.
Figure 4-2. AVR CPU General Purpose Working Registers
Most of the instructions operating on the Register File have direct access to all registers, and most of them are single
cycle instructions.
As shown in Figure 4-2, each register is also assigned a Data memory address, mapping them directly into the first
32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory
organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to
index any register in the file.
4.5.1 The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit
address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are
defined as described in Figure 4-3.
7 0 Addr.
R0 0x00
R1 0x01
R2 0x02
…
R13 0x0D
General R14 0x0E
Purpose R15 0x0F
Working R16 0x10
Registers R17 0x11
…
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High ByteATtiny25/45/85 [DATASHEET] 11
2586Q–AVR–08/2013
Figure 4-3. The X-, Y-, and Z-registers
In the different addressing modes these address registers have functions as fixed displacement, automatic increment,
and automatic decrement (see the instruction set reference for details).
4.6 Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses
after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the
Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a
Stack PUSH command decreases the Stack Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This
Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts
are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one
when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return
address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when
data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the
Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is
implementation dependent. Note that the data space in some implementations of the AVR architecture is so small
that only SPL is needed. In this case, the SPH Register will not be present.
4.6.1 SPH and SPL — Stack Pointer Register
4.7 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the
CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.
Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture
and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with
the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
15 XH XL 0
X-register 7 0 7 0
R27 (0x1B) R26 (0x1A)
15 YH YL 0
Y-register 7 0 7 0
R29 (0x1D) R28 (0x1C)
15 ZH ZL 0
Z-register 7 0 7 0
R31 (0x1F) R30 (0x1E)
Bit 15 14 13 12 11 10 9 8
0x3E SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH
0x3D SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMENDATtiny25/45/85 [DATASHEET] 12
2586Q–AVR–08/2013
Figure 4-4. The Parallel Instruction Fetches and Instruction Executions
Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using
two register operands is executed, and the result is stored back to the destination register.
Figure 4-5. Single Cycle ALU Operation
4.8 Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a
separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which
must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the
interrupt.
The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors.
The complete list of vectors is shown in “Interrupts” on page 48. The list also determines the priority levels of the
different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next
is INT0 – the External Interrupt Request 0.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software
can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current
interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For
these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt
handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing
a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding
interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the
flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit
is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is
set, and will then be executed by order of priority.
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clkCPUATtiny25/45/85 [DATASHEET] 13
2586Q–AVR–08/2013
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily
have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will
not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction
before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when
returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be
executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example
shows how this can be used to avoid interrupts during the timed EEPROM write sequence.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending
interrupts, as shown in this example.
4.8.1 Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock
cycles the Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle
period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and
this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction
is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution
response time is increased by four clock cycles. This increase comes in addition to the start-up time from the
selected sleep mode.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1< ; Address 0x000F
...ATtiny25/45/85 [DATASHEET] 50
2586Q–AVR–08/2013
the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the
SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 23.
If the low level on the interrupt pin is removed before the device has woken up then program execution will not be
diverted to the interrupt service routine but continue from the instruction following the SLEEP command.
9.2.2 Pin Change Interrupt Timing
An example of timing of a pin change interrupt is shown in Figure 9-1.
Figure 9-1. Timing of pin change interrupts
clk
PCINT(0)
pin_lat
pin_sync
pcint_in_(0)
pcint_syn
pcint_setflag
PCIF
PCINT(0)
pin_sync
pcint_syn pin_lat D Q
LE
pcint_setflag
PCIF
clk
clk PCINT(0) in PCMSK(x)
pcint_in_(0) 0
xATtiny25/45/85 [DATASHEET] 51
2586Q–AVR–08/2013
9.3 Register Description
9.3.1 MCUCR – MCU Control Register
The External Interrupt Control Register A contains control bits for interrupt sense control.
• Bits 1:0 – ISC0[1:0]: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt
mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 9-2. The
value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer
than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If
low level interrupt is selected, the low level must be held until the completion of the currently executing instruction
to generate an interrupt.
9.3.2 GIMSK – General Interrupt Mask Register
• Bits 7, 4:0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is
enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU Control Register (MCUCR) define
whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on
the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External
Interrupt Request 0 is executed from the INT0 Interrupt Vector.
• Bit 5 – PCIE: Pin Change Interrupt Enable
When the PCIE bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt is
enabled. Any change on any enabled PCINT[5:0] pin will cause an interrupt. The corresponding interrupt of Pin
Change Interrupt Request is executed from the PCI Interrupt Vector. PCINT[5:0] pins are enabled individually by
the PCMSK0 Register.
Bit 7 6 5 4 3 2 1 0
0x35 BODS PUD SE SM1 SM0 BODSE ISC01 ISC00 MCUCR
Read/Write R R/W R/W R/W R/W R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 9-2. Interrupt 0 Sense Control
ISC01 ISC00 Description
0 0 The low level of INT0 generates an interrupt request.
0 1 Any logical change on INT0 generates an interrupt request.
1 0 The falling edge of INT0 generates an interrupt request.
1 1 The rising edge of INT0 generates an interrupt request.
Bit 7 6 5 4 3 2 1 0
0x3B – INT0 PCIE – – – – – GIMSK
Read/Write R R/W R/W R R R R R
Initial Value 0 0 0 0 0 0 0 0ATtiny25/45/85 [DATASHEET] 52
2586Q–AVR–08/2013
9.3.3 GIFR – General Interrupt Flag Register
• Bits 7, 4:0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
• Bit 6 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in
SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag
is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
This flag is always cleared when INT0 is configured as a level interrupt.
• Bit 5 – PCIF: Pin Change Interrupt Flag
When a logic change on any PCINT[5:0] pin triggers an interrupt request, PCIF becomes set (one). If the I-bit in
SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag
is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
9.3.4 PCMSK – Pin Change Mask Register
• Bits 7:6 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
• Bits 5:0 – PCINT[5:0]: Pin Change Enable Mask 5:0
Each PCINT[5:0] bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[5:0] is
set and the PCIE bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT[5:0] is
cleared, pin change interrupt on the corresponding I/O pin is disabled.
Bit 7 6 5 4 3 2 1 0
0x3A – INTF0 PCIF – – – – – GIFR
Read/Write R R/W R/W R R R R R
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x15 – – PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0ATtiny25/45/85 [DATASHEET] 53
2586Q–AVR–08/2013
10. I/O Ports
10.1 Introduction
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that
the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the
SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling
of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with
both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins
have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection
diodes to both VCC and Ground as indicated in Figure 10-1. Refer to “Electrical Characteristics” on page 161 for a
complete list of parameters.
Figure 10-1. I/O Pin Equivalent Schematic
All registers and bit references in this section are written in general form. A lower case “x” represents the numbering
letter for the port, and a lower case “n” represents the bit number. However, when using the register or bit
defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented
generally as PORTxn. The physical I/O Registers and bit locations are listed in “Register Description” on
page 64.
Three I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data
Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins I/O location is read only, while the
Data Register and the Data Direction Register are read/write. However, writing a logic one to a bit in the PINx Register,
will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable – PUD bit
in MCUCR disables the pull-up function for all pins in all ports when set.
Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page 53. Most port pins
are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes
with the port pin is described in “Alternate Port Functions” on page 57. Refer to the individual module sections
for a full description of the alternate functions.
Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port
as general digital I/O.
10.2 Ports as General Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a functional description of
one I/O-port pin, here generically called Pxn.
Logic
Rpu
See Figure
"General Digital I/O" for
Details
PxnATtiny25/45/85 [DATASHEET] 54
2586Q–AVR–08/2013
Figure 10-2. General Digital I/O(1)
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are
common to all ports.
10.2.1 Configuring the Pin
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register Description” on
page 64, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and
the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured
as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch
the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The
port pins are tri-stated when reset condition becomes active, even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If
PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).
10.2.2 Toggling the Pin
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI
instruction can be used to toggle one single bit in a port.
10.2.3 Switching Between Input and Output
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate
state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must
occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the
clk
RPx
RRx
RDx
WDx
PUD
SYNCHRONIZER
WDx: WRITE DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
PUD: PULLUP DISABLE
clkI/O: I/O CLOCK
RDx: READ DDRx
D
L
Q
Q
RESET
RESET
Q
D Q
Q
Q D
CLR
PORTxn
Q
Q D
CLR
DDxn
PINxn
DATA BUS
SLEEP
SLEEP: SLEEP CONTROL
Pxn
I/O
WPx
0
1
WRx
WPx: WRITE PINx REGISTERATtiny25/45/85 [DATASHEET] 55
2586Q–AVR–08/2013
difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register
can be set to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user must use either the tristate
({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b10) as an intermediate step.
Table 10-1 summarizes the control signals for the pin value.
10.2.4 Reading the Pin Value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As
shown in Figure 10-2, the PINxn Register bit and the preceding latch constitute a synchronizer. This is needed to
avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a
delay. Figure 10-3 shows a timing diagram of the synchronization when reading an externally applied pin value.
The maximum and minimum propagation delays are denoted tpd,max and tpd,min respectively.
Figure 10-3. Synchronization when Reading an Externally Applied Pin value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when
the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC
LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at
the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition
on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 10-4.
The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd
through the synchronizer is one system clock period.
Table 10-1. Port Pin Configurations
DDxn PORTxn
PUD
(in MCUCR) I/O Pull-up Comment
0 0 X Input No Tri-state (Hi-Z)
0 1 0 Input Yes Pxn will source current if ext. pulled low.
0 1 1 Input No Tri-state (Hi-Z)
1 0 X Output No Output Low (Sink)
1 1 X Output No Output High (Source)
XXX in r17, PINx
0x00 0xFF
INSTRUCTIONS
SYNC LATCH
PINxn
r17
XXX
SYSTEM CLK
tpd, max
tpd, minATtiny25/45/85 [DATASHEET] 56
2586Q–AVR–08/2013
Figure 10-4. Synchronization when Reading a Software Assigned Pin Value
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from
4 to 5 as input with a pull-up assigned to port pin 4. The resulting pin values are read back again, but as previously
discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins.
Note: 1. For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins 0, 1
and 4, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high
drivers.
Assembly Code Example(1)
...
; Define pull-ups and set outputs high
; Define directions for port pins
ldi r16,(1< CS0[2:0] > 1). The number of system clock cycles from when the timer is
enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor
(8, 64, 256, or 1024).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execution.
Table 11-1. Definitions
Constant Description
BOTTOM The counter reaches BOTTOM when it becomes 0x00
MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255)
TOP
The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the
value stored in the OCR0A Register. The assignment depends on the mode of operationATtiny25/45/85 [DATASHEET] 67
2586Q–AVR–08/2013
11.3.3 External Clock Source
An external clock source applied to the T0 pin can be used as timer/counter clock (clkT0). The T0 pin is sampled
once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed
through the edge detector. Figure 11-2 shows a functional equivalent block diagram of the T0 synchronization and
edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is
transparent in the high period of the internal system clock.
The edge detector generates one clkT0 pulse for each positive (CS0[2:0] = 7) or negative (CS0[2:0] = 6) edge it
detects.
Figure 11-2. T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has
been applied to the T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T0 has been stable for at least one system clock
cycle, otherwise it is a risk that a false timer/counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling.
The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2)
given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it
can detect is half the sampling frequency (following the Nyquist sampling theorem). However, due to variation of
the system clock frequency and duty cycle caused by oscillator source (crystal, resonator, and capacitors) tolerances,
it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5.
An external clock source can not be prescaled.
Tn_sync
(To Clock
Select Logic)
Synchronization Edge Detector
D Q D Q
LE
Tn D Q
clkI/OATtiny25/45/85 [DATASHEET] 68
2586Q–AVR–08/2013
Figure 11-3. Timer/Counter0 Prescaler
The synchronization logic on the input pins (T0) in Figure 11-3 is shown in Figure 11-2 on page 67.
11.4 Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 11-4 shows a
block diagram of the counter and its surroundings.
Figure 11-4. Counter Unit Block Diagram
Signal description (internal signals):
count Increment or decrement TCNT0 by 1.
direction Select between increment and decrement.
clear Clear TCNT0 (set all bits to zero).
clkTn Timer/Counter clock, referred to as clkT0 in the following.
top Signalize that TCNT0 has reached maximum value.
bottom Signalize that TCNT0 has reached minimum value (zero).
Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock
(clkT0). clkT0 can be generated from an external or internal clock source, selected by the Clock Select bits
(CS0[2:0]). When no clock source is selected (CS0[2:0] = 0) the timer is stopped. However, the TCNT0 value can
PSR10
Clear
clkT0
T0
clkI/O
Synchronization
DATA BUS
TCNTn Control Logic
count
TOVn
(Int.Req.)
Clock Select
top
Tn Edge
Detector
( From Prescaler )
clkTn
bottom
direction
clearATtiny25/45/85 [DATASHEET] 69
2586Q–AVR–08/2013
be accessed by the CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all
counter clear or count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter
Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter Control Register B (TCCR0B). There
are close connections between how the counter behaves (counts) and how waveforms are generated on the Output
Compare output OC0A. For more details about advanced counting sequences and waveform generation, see
“Modes of Operation” on page 71.
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by the WGM0[1:0]
bits. TOV0 can be used for generating a CPU interrupt.
11.5 Output Compare Unit
The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers (OCR0A and OCR0B).
Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a match. A match will set the Output Compare
Flag (OCF0A or OCF0B) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output
Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when
the interrupt is executed. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit location.
The Waveform Generator uses the match signal to generate an output according to operating mode set by the
WGM0[2:0] bits and Compare Output mode (COM0x[1:0]) bits. The max and bottom signals are used by the Waveform
Generator for handling the special cases of the extreme values in some modes of operation (See “Modes of
Operation” on page 71.).
Figure 11-5 shows a block diagram of the Output Compare unit.
Figure 11-5. Output Compare Unit, Block Diagram
The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the
normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering
synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence.
The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the
output glitch-free.
OCFnx (Int.Req.)
= (8-bit Comparator )
OCRnx
OCnx
DATA BUS
TCNTn
WGMn[1:0]
Waveform Generator
top
FOCn
COMnX[1:0]
bottomATtiny25/45/85 [DATASHEET] 70
2586Q–AVR–08/2013
The OCR0x Register access may seem complex, but this is not case. When the double buffering is enabled, the
CPU has access to the OCR0x Buffer Register, and if double buffering is disabled the CPU will access the OCR0x
directly.
11.5.1 Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to
the Force Output Compare (FOC0x) bit. Forcing Compare Match will not set the OCF0x Flag or reload/clear the
timer, but the OC0x pin will be updated as if a real Compare Match had occurred (the COM0x[1:0] bits settings
define whether the OC0x pin is set, cleared or toggled).
11.5.2 Compare Match Blocking by TCNT0 Write
All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the next timer clock
cycle, even when the timer is stopped. This feature allows OCR0x to be initialized to the same value as TCNT0
without triggering an interrupt when the Timer/Counter clock is enabled.
11.5.3 Using the Output Compare Unit
Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer clock cycle, there are
risks involved when changing TCNT0 when using the Output Compare Unit, independently of whether the
Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the Compare Match will be
missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM
when the counter is down-counting.
The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output.
The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal
mode. The OC0x Registers keep their values even when changing between Waveform Generation modes.
Be aware that the COM0x[1:0] bits are not double buffered together with the compare value. Changing the
COM0x[1:0] bits will take effect immediately.
11.6 Compare Match Output Unit
The Compare Output mode (COM0x[1:0]) bits have two functions. The Waveform Generator uses the COM0x[1:0]
bits for defining the Output Compare (OC0x) state at the next Compare Match. Also, the COM0x[1:0] bits control
the OC0x pin output source. Figure 11-6 shows a simplified schematic of the logic affected by the COM0x[1:0] bit
setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O
Port Control Registers (DDR and PORT) that are affected by the COM0x[1:0] bits are shown. When referring to the
OC0x state, the reference is for the internal OC0x Register, not the OC0x pin. If a system reset occur, the OC0x
Register is reset to “0”.ATtiny25/45/85 [DATASHEET] 71
2586Q–AVR–08/2013
Figure 11-6. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either
of the COM0x[1:0] bits are set. However, the OC0x pin direction (input or output) is still controlled by the Data
Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0x pin (DDR_OC0x) must be
set as output before the OC0x value is visible on the pin. The port override function is independent of the Waveform
Generation mode.
The design of the Output Compare pin logic allows initialization of the OC0x state before the output is enabled.
Note that some COM0x[1:0] bit settings are reserved for certain modes of operation. See “Register Description” on
page 77.
11.6.1 Compare Output Mode and Waveform Generation
The Waveform Generator uses the COM0x[1:0] bits differently in Normal, CTC, and PWM modes. For all modes,
setting the COM0x[1:0] = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed
on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 11-2 on page 78.
For fast PWM mode, refer to Table 11-3 on page 78, and for phase correct PWM refer to Table 11-4 on page 78.
A change of the COM0x[1:0] bits state will have effect at the first Compare Match after the bits are written. For nonPWM
modes, the action can be forced to have immediate effect by using the FOC0x strobe bits.
11.7 Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the
combination of the Waveform Generation mode (WGM0[2:0]) and Compare Output mode (COM0x[1:0]) bits. The
Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do.
The COM0x[1:0] bits control whether the PWM output generated should be inverted or not (inverted or noninverted
PWM). For non-PWM modes the COM0x[1:0] bits control whether the output should be set, cleared, or
toggled at a Compare Match (See “Compare Match Output Unit” on page 70.).
PORT
DDR
D Q
D Q
OCn
OCnx Pin
D Q Waveform
Generator
COMnx1
COMnx0
0
1
DATA BU
S
FOCn
clkI/OATtiny25/45/85 [DATASHEET] 72
2586Q–AVR–08/2013
For detailed timing information refer to Figure 11-10, Figure 11-11, Figure 11-12 and Figure 11-13 in “Timer/Counter
Timing Diagrams” on page 76.
11.7.1 Normal Mode
The simplest mode of operation is the Normal mode (WGM0[2:0] = 0). In this mode the counting direction is always
up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-
bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow
Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case
behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special
cases to consider in the Normal mode, a new counter value can be written anytime.
The Output Compare Unit can be used to generate interrupts at some given time. Using the Output Compare to
generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
11.7.2 Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM0[2:0] = 2), the OCR0A Register is used to manipulate the counter
resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0A. The
OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the
Compare Match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 11-7. The counter value (TCNT0) increases until a Compare
Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared.
Figure 11-7. CTC Mode, Timing Diagram
An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the
interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP
to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with
care since the CTC mode does not have the double buffering feature. If the new value written to OCR0A is lower
than the current value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur.
For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each
Compare Match by setting the Compare Output mode bits to toggle mode (COM0A[1:0] = 1). The OC0A value will
not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have
a maximum frequency of fOC0 = fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by
the following equation:
TCNTn
OCn
(Toggle)
OCnx Interrupt Flag Set
Period 1 2 3 4
(COMnx[1:0] = 1)
f
OCnx
f
clk_I/O
2 N 1 OCRnx + = --------------------------------------------------ATtiny25/45/85 [DATASHEET] 73
2586Q–AVR–08/2013
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts
from MAX to 0x00.
11.7.3 Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM0[2:0] = 3 or 7) provides a high frequency PWM waveform
generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter
counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM0[2:0] = 3, and
OCR0A when WGM0[2:0] = 7.
In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match between
TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match
and cleared at BOTTOM.
Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the
phase correct PWM mode that use dual-slope operation. This high frequency makes the fast PWM mode well
suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external
components (coils, capacitors), and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then
cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 11-8. The
TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram
includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent
Compare Matches between OCR0x and TCNT0.
Figure 11-8. Fast PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the
interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the
COM0x[1:0] bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting
the COM0x[1:0] to three: Setting the COM0A[1:0] bits to one allowes the AC0A pin to toggle on Compare Matches
if the WGM02 bit is set. This option is not available for the OC0B pin (See Table 11-3 on page 78). The actual
OC0x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveTCNTn
OCRnx Update and
TOVn Interrupt Flag Set
Period 1 2 3
OCn
OCn
(COMnx[1:0] = 2)
(COMnx[1:0] = 3)
OCRnx Interrupt Flag Set
4 5 6 7ATtiny25/45/85 [DATASHEET] 74
2586Q–AVR–08/2013
form is generated by setting (or clearing) the OC0x Register at the Compare Match between OCR0x and TCNT0,
and clearing (or setting) the OC0x Register at the timer clock cycle the counter is cleared (changes from TOP to
BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represents special cases when generating a PWM waveform output in
the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1
timer clock cycle. Setting the OCR0A equal to MAX will result in a constantly high or low output (depending on the
polarity of the output set by the COM0A[1:0] bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0x to toggle
its logical level on each Compare Match (COM0x[1:0] = 1). The waveform generated will have a maximum frequency
of fOC0 = fclk_I/O/2 when OCR0A is set to zero. This feature is similar to the OC0A toggle in CTC mode,
except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode.
11.7.4 Phase Correct PWM Mode
The phase correct PWM mode (WGM0[2:0] = 1 or 5) provides a high resolution phase correct PWM waveform generation
option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly
from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGM0[2:0] = 1, and
OCR0A when WGM0[2:0] = 5. In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on
the Compare Match between TCNT0 and OCR0x while upcounting, and set on the Compare Match while downcounting.
In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum
operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope
PWM modes, these modes are preferred for motor control applications.
In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter
reaches TOP, it changes the count direction. The TCNT0 value will be equal to TOP for one timer clock cycle. The
timing diagram for the phase correct PWM mode is shown on Figure 11-9. The TCNT0 value is in the timing diagram
shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and
inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches
between OCR0x and TCNT0.
f
OCnxPWM
f
clk_I/O
N 256 = ------------------ATtiny25/45/85 [DATASHEET] 75
2586Q–AVR–08/2013
Figure 11-9. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can
be used to generate an interrupt each time the counter reaches the BOTTOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting
the COM0x[1:0] bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting
the COM0x[1:0] to three: Setting the COM0A0 bits to one allows the OC0A pin to toggle on Compare Matches if
the WGM02 bit is set. This option is not available for the OC0B pin (See Table 11-4 on page 78). The actual OC0x
value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is
generated by clearing (or setting) the OC0x Register at the Compare Match between OCR0x and TCNT0 when the
counter increments, and setting (or clearing) the OC0x Register at Compare Match between OCR0x and TCNT0
when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated
by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represent special cases when generating a PWM waveform output in
the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the output will be continuously low and if set
equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will
have the opposite logic values.
At the very start of period 2 in Figure 11-9 OCn has a transition from high to low even though there is no Compare
Match. The point of this transition is to guaratee symmetry around BOTTOM. There are two cases that give a transition
without Compare Match, as follows:
• OCR0A changes its value from MAX, like in Figure 11-9. When the OCR0A value is MAX the OCn pin value is
the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn
value at MAX must correspond to the result of an up-counting Compare Match.
TOVn Interrupt Flag Set
OCnx Interrupt Flag Set
1 2 3
TCNTn
Period
OCn
OCn
(COMnx[1:0] = 2)
(COMnx[1:0] = 3)
OCRnx Update
f
OCnxPCPWM
f
clk_I/O
N 510 = ------------------ATtiny25/45/85 [DATASHEET] 76
2586Q–AVR–08/2013
• The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare
Match and hence the OCn change that would have happened on the way up.
11.8 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal
in the following figures. The figures include information on when Interrupt Flags are set. Figure 11-10 contains timing
data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all
modes other than phase correct PWM mode.
Figure 11-10. Timer/Counter Timing Diagram, no Prescaling
Figure 11-11 shows the same timing data, but with the prescaler enabled.
Figure 11-11. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
Figure 11-12 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC mode and PWM
mode, where OCR0A is TOP.
Figure 11-12. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8)
clkTn
(clkI/O/1)
TOVn
clkI/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
TOVn
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1
clkI/O
clkTn
(clkI/O/8)
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2
clkI/O
clkTn
(clkI/O/8)ATtiny25/45/85 [DATASHEET] 77
2586Q–AVR–08/2013
Figure 11-13 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM mode where
OCR0A is TOP.
Figure 11-13. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8)
11.9 Register Description
11.9.1 GTCCR – General Timer/Counter Control Register
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization Mode. In this mode, the value written to
PSR0 is kept, hence keeping the Prescaler Reset signal asserted. This ensures that the timer/counter is halted and
can be configured without the risk of advancing during configuration. When the TSM bit is written to zero, the PSR0
bit is cleared by hardware, and the timer/counter start counting.
• Bit 0 – PSR0: Prescaler Reset Timer/Counter0
When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware,
except if the TSM bit is set.
11.9.2 TCCR0A – Timer/Counter Control Register A
• Bits 7:6 – COM0A[1:0]: Compare Match Output A Mode
• Bits 5:4 – COM0B[1:0]: Compare Match Output B Mode
The COM0A[1:0] and COM0B[1:0] bits control the behaviour of Output Compare pins OC0A and OC0B, respectively.
If any of the COM0A[1:0] bits are set, the OC0A output overrides the normal port functionality of the I/O pin it
is connected to. Similarly, if any of the COM0B[1:0] bits are set, the OC0B output overrides the normal port functionality
of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to
the OC0A and OC0B pins must be set in order to enable the output driver.
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1 TOP BOTTOM BOTTOM + 1
clkI/O
clkTn
(clkI/O/8)
Bit 7 6 5 4 3 2 1 0
0x2C TSM PWM1B COM1B1 COM1B0 FOC1B FOC1A PSR1 PSR0 GTCCR
Read/Write R/W R R R R R R R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x2A COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 TCCR0A
Read/Write R/W R/W R/W R/W R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0ATtiny25/45/85 [DATASHEET] 78
2586Q–AVR–08/2013
When OC0A/OC0B is connected to the I/O pin, the function of the COM0A[1:0]/COM0B[1:0] bits depend on the
WGM0[2:0] bit setting. Table 11-2 shows the COM0x[1:0] bit functionality when the WGM0[2:0] bits are set to a
normal or CTC mode (non-PWM).
Table 11-3 shows the COM0x[1:0] bit functionality when the WGM0[2:0] bits are set to fast PWM mode.
Note: 1. A special case occurs when OCR0A or OCR0B equals TOP and COM0A1/COM0B1 is set. In this case, the compare
match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 73 for more details.
Table 11-4 shows the COM0x[1:0] bit functionality when the WGM0[2:0] bits are set to phase correct PWM mode.
Note: 1. A special case occurs when OCR0A or OCR0B equals TOP and COM0A1/COM0B1 is set. In this case, the Compare
Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 74 for more
details.
• Bits 3:2 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
Table 11-2. Compare Output Mode, non-PWM Mode
COM0A1
COM0B1
COM0A0
COM0B0 Description
0 0 Normal port operation, OC0A/OC0B disconnected.
0 1 Toggle OC0A/OC0B on Compare Match
1 0 Clear OC0A/OC0B on Compare Match
1 1 Set OC0A/OC0B on Compare Match
Table 11-3. Compare Output Mode, Fast PWM Mode(1)
COM0A1
COM0B1
COM0A0
COM0B0 Description
0 0 Normal port operation, OC0A/OC0B disconnected.
0 1 Reserved
1 0 Clear OC0A/OC0B on Compare Match, set OC0A/OC0B at BOTTOM
(non-inverting mode)
1 1 Set OC0A/OC0B on Compare Match, clear OC0A/OC0B at BOTTOM
(inverting mode)
Table 11-4. Compare Output Mode, Phase Correct PWM Mode(1)
COM0A1
COM0B1
COM0A0
COM0B0 Description
0 0 Normal port operation, OC0A/OC0B disconnected.
0 1 Reserved
1 0 Clear OC0A/OC0B on Compare Match when up-counting.
Set OC0A/OC0B on Compare Match when down-counting.
1 1 Set OC0A/OC0B on Compare Match when up-counting.
Clear OC0A/OC0B on Compare Match when down-counting.ATtiny25/45/85 [DATASHEET] 79
2586Q–AVR–08/2013
• Bits 1:0 – WGM0[1:0]: Waveform Generation Mode
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the
counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see
Table 11-5. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on
Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see “Modes of Operation”
on page 71).
Notes: 1. MAX = 0xFF
2. BOTTOM = 0x00
11.9.3 TCCR0B – Timer/Counter Control Register B
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when
operating in PWM mode. When writing a logical one to the FOC0A bit, an immediate Compare Match is forced on
the Waveform Generation unit. The OC0A output is changed according to its COM0A[1:0] bits setting. Note that
the FOC0A bit is implemented as a strobe. Therefore it is the value present in the COM0A[1:0] bits that determines
the effect of the forced compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0A as TOP.
The FOC0A bit is always read as zero.
• Bit 6 – FOC0B: Force Output Compare B
The FOC0B bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when
operating in PWM mode. When writing a logical one to the FOC0B bit, an immediate Compare Match is forced on
the Waveform Generation unit. The OC0B output is changed according to its COM0B[1:0] bits setting. Note that
the FOC0B bit is implemented as a strobe. Therefore it is the value present in the COM0B[1:0] bits that determines
the effect of the forced compare.
A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP.
Table 11-5. Waveform Generation Mode Bit Description
Mode
WGM
02
WGM
01
WGM
00
Timer/Counter Mode
of Operation TOP
Update of
OCRx at
TOV Flag
Set on
0 0 0 0 Normal 0xFF Immediate MAX(1)
1 0 0 1 PWM, Phase Correct 0xFF TOP BOTTOM(2)
2 0 1 0 CTC OCRA Immediate MAX(1)
3 0 1 1 Fast PWM 0xFF BOTTOM(2) MAX(1)
4 1 0 0 Reserved – – –
5 1 0 1 PWM, Phase Correct OCRA TOP BOTTOM(2)
6 1 1 0 Reserved – – –
7 1 1 1 Fast PWM OCRA BOTTOM(2) TOP
Bit 7 6 5 4 3 2 1 0
0x33 FOC0A FOC0B – – WGM02 CS02 CS01 CS00 TCCR0B
Read/Write W W R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0ATtiny25/45/85 [DATASHEET] 80
2586Q–AVR–08/2013
The FOC0B bit is always read as zero.
• Bits 5:4 – Res: Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.
• Bit 3 – WGM02: Waveform Generation Mode
See the description in the “TCCR0A – Timer/Counter Control Register A” on page 77.
• Bits 2:0 – CS0[2:0]: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the
pin is configured as an output. This feature allows software control of the counting.
11.9.4 TCNT0 – Timer/Counter Register
The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit
counter. Writing to the TCNT0 Register blocks (removes) the Compare Match on the following timer clock. Modifying
the counter (TCNT0) while the counter is running, introduces a risk of missing a Compare Match between
TCNT0 and the OCR0x Registers.
11.9.5 OCR0A – Output Compare Register A
The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value
(TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the
OC0A pin.
Table 11-6. Clock Select Bit Description
CS02 CS01 CS00 Description
0 0 0 No clock source (Timer/Counter stopped)
0 0 1 clkI/O/(No prescaling)
0 1 0 clkI/O/8 (From prescaler)
0 1 1 clkI/O/64 (From prescaler)
1 0 0 clkI/O/256 (From prescaler)
1 0 1 clkI/O/1024 (From prescaler)
1 1 0 External clock source on T0 pin. Clock on falling edge.
1 1 1 External clock source on T0 pin. Clock on rising edge.
Bit 7 6 5 4 3 2 1 0
0x32 TCNT0[7:0] TCNT0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x29 OCR0A[7:0] OCR0A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0ATtiny25/45/85 [DATASHEET] 81
2586Q–AVR–08/2013
11.9.6 OCR0B – Output Compare Register B
The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value
(TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the
OC0B pin.
11.9.7 TIMSK – Timer/Counter Interrupt Mask Register
• Bits 7, 0 – Res: Reserved Bits
These bits are reserved bits and will always read as zero.
• Bit 4 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Compare
Match A interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter0
occurs, i.e., when the OCF0A bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0.
• Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare
Match B interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter occurs,
i.e., when the OCF0B bit is set in the Timer/Counter Interrupt Flag Register – TIFR0.
• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Overflow interrupt
is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the
TOV0 bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0.
11.9.8 TIFR – Timer/Counter Interrupt Flag Register
• Bits 7, 0 – Res: Reserved Bits
These bits are reserved bits and will always read as zero.
• Bit 4 – OCF0A: Output Compare Flag 0 A
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A – Output
Compare Register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling
vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A
(Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt
is executed.
Bit 7 6 5 4 3 2 1 0
0x28 OCR0B[7:0] OCR0B
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x39 – OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 – TIMSK
Read/Write R R/W R/W R/W R/W R/W R/W R
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x38 – OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 – TIFR
Read/Write R R/W R/W R/W R/W R/W R/W R
Initial Value 0 0 0 0 0 0 0 0ATtiny25/45/85 [DATASHEET] 82
2586Q–AVR–08/2013
• Bit 3 – OCF0B: Output Compare Flag 0 B
The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – Output
Compare Register0 B. OCF0B is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, OCF0B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter
Compare B Match Interrupt Enable), and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.
• Bit 1 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the
SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow
interrupt is executed.
The setting of this flag is dependent of the WGM0[2:0] bit setting. Refer to Table 11-5, “Waveform Generation
Mode Bit Description” on page 79.ATtiny25/45/85 [DATASHEET] 83
2586Q–AVR–08/2013
12. 8-bit Timer/Counter1
The Timer/Counter1 is a general purpose 8-bit Timer/Counter module that has a separate prescaling selection
from the separate prescaler.
12.1 Timer/Counter1 Prescaler
Figure 12-1 shows the Timer/Counter1 prescaler that supports two clocking modes, a synchronous clocking mode
and an asynchronous clocking mode. The synchronous clocking mode uses the system clock (CK) as the clock
timebase and asynchronous mode uses the fast peripheral clock (PCK) as the clock time base. The PCKE bit from
the PLLCSR register enables the asynchronous mode when it is set (‘1’).
Figure 12-1. Timer/Counter1 Prescaler
In the asynchronous clocking mode the clock selections are from PCK to PCK/16384 and stop, and in the synchronous
clocking mode the clock selections are from CK to CK/16384 and stop. The clock options are described in
Table 12-5 on page 89 and the Timer/Counter1 Control Register, TCCR1. Setting the PSR1 bit in GTCCR register
resets the prescaler. The PCKE bit in the PLLCSR register enables the asynchronous mode. The frequency of the
fast peripheral clock is 64 MHz (or 32 MHz in Low Speed Mode).
12.2 Counter and Compare Units
The Timer/Counter1 general operation is described in the asynchronous mode and the operation in the synchronous
mode is mentioned only if there are differences between these two modes. Figure 12-2 shows Timer/Counter
1 synchronization register block diagram and synchronization delays in between registers. Note that all clock gating
details are not shown in the figure. The Timer/Counter1 register values go through the internal synchronization
registers, which cause the input synchronization delay, before affecting the counter operation. The registers
TCCR1, GTCCR, OCR1A, OCR1B, and OCR1C can be read back right after writing the register. The read back
values are delayed for the Timer/Counter1 (TCNT1) register and flags (OCF1A, OCF1B, and TOV1), because of
the input and output synchronization.
The Timer/Counter1 features a high resolution and a high accuracy usage with the lower prescaling opportunities.
It can also support two accurate, high speed, 8-bit Pulse Width Modulators using clock speeds up to 64 MHz (or 32
MHz in Low Speed Mode). In this mode, Timer/Counter1 and the output compare registers serve as dual standalone
PWMs with non-overlapping non-inverted and inverted outputs. Refer to page 86 for a detailed description
on this function. Similarly, the high prescaling opportunities make this unit useful for lower speed functions or exact
timing functions with infrequent actions.
TIMER/COUNTER1 COUNT ENABLE
PSR1
CS10
CS11
CS12
PCK 64/32 MHz
0
CS13
14-BIT
T/C PRESCALER
T1CK
T1CK/2
T1CK/4
T1CK/8
T1CK/16
T1CK/32
T1CK/64
T1CK/128
T1CK/256
T1CK/512
T1CK/1024
T1CK/2048
T1CK/4096
T1CK/8192
T1CK/16384
CK
PCKE
T1CKATtiny25/45/85 [DATASHEET] 84
2586Q–AVR–08/2013
Figure 12-2. Timer/Counter 1 Synchronization Register Block Diagram.
Timer/Counter1 and the prescaler allow running the CPU from any clock source while the prescaler is operating on
the fast 64 MHz (or 32 MHz in Low Speed Mode) PCK clock in the asynchronous mode.
Note that the system clock frequency must be lower than one third of the PCK frequency. The synchronization
mechanism of the asynchronous Timer/Counter1 needs at least two edges of the PCK when the system clock is
high. If the frequency of the system clock is too high, it is a risk that data or control values are lost.
The following Figure 12-3 shows the block diagram for Timer/Counter1.
8-BIT DATABUS
OCR1A OCR1A_SI
OCR1B OCR1B_SI TCNT_SO
OCR1C OCR1C_SI
TCCR1 TCCR1_SI
GTCCR GTCCR_SI
TCNT1 TCNT1_SI
OCF1A OCF1A_SI
OCF1B OCF1B_SI
TOV1 TOV1_SI TOV1_SO
OCF1B_SO
OCF1A_SO
TCNT1
S
A
S
A
PCKE
CK
PCK
IO-registers Input synchronization
registers
Timer/Counter1 Output synchronization
registers
SYNC
MODE
ASYNC
MODE
1 CK Delay
1 PCK Delay No Delay ~1 CK Delay
TCNT1
OCF1A
OCF1B
TOV1
1/2 CK Delay 1 CK Delay 1/2 CK Delay
1..2 PCK DelayATtiny25/45/85 [DATASHEET] 85
2586Q–AVR–08/2013
Figure 12-3. Timer/Counter1 Block Diagram
Three status flags (overflow and compare matches) are found in the Timer/Counter Interrupt Flag Register - TIFR.
Control signals are found in the Timer/Counter Control Registers TCCR1 and GTCCR. The interrupt enable/disable
settings are found in the Timer/Counter Interrupt Mask Register - TIMSK.
The Timer/Counter1 contains three Output Compare Registers, OCR1A, OCR1B, and OCR1C as the data source
to be compared with the Timer/Counter1 contents. In normal mode the Output Compare functions are operational
with all three output compare registers. OCR1A determines action on the OC1A pin (PB1), and it can generate
Timer1 OC1A interrupt in normal mode and in PWM mode. Likewise, OCR1B determines action on the OC1B pin
(PB4) and it can generate Timer1 OC1B interrupt in normal mode and in PWM mode. OCR1C holds the
Timer/Counter maximum value, i.e. the clear on compare match value. In the normal mode an overflow interrupt
(TOV1) is generated when Timer/Counter1 counts from $FF to $00, while in the PWM mode the overflow interrupt
is generated when Timer/Counter1 counts either from $FF to $00 or from OCR1C to $00. The inverted PWM outputs
OC1A and OC1B are not connected in normal mode.
In PWM mode, OCR1A and OCR1B provide the data values against which the Timer Counter value is compared.
Upon compare match the PWM outputs (OC1A, OC1A, OC1B, OC1B) are generated. In PWM mode, the Timer
Counter counts up to the value specified in the output compare register OCR1C and starts again from $00. This
feature allows limiting the counter “full” value to a specified value, lower than $FF. Together with the many prescaler
options, flexible PWM frequency selection is provided. Table 12-3 on page 88 lists clock selection and
OCR1C values to obtain PWM frequencies from 20 kHz to 250 kHz in 10 kHz steps and from 250 kHz to 500 kHz
in 50 kHz steps. Higher PWM frequencies can be obtained at the expense of resolution.
8-BIT DATABUS
TIMER INT. FLAG
REGISTER (TIFR)
TIMER/COUNTER1
8-BIT COMPARATOR
T/C1 OUTPUT
COMPARE REGISTER
TIMER INT. MASK
REGISTER (TIMSK)
TIMER/COUNTER1
(TCNT1) T/C CLEAR T/C1 CONTROL
LOGIC
TOV1
OCF1B
OCIE1A
OCIE1B
TOIE1
TOIE0
OCF1A
OCF1B
TOV1
OCF1A
CK
PCK
T/C1 OVERFLOW
IRQ
T/C1 COMPARE
MATCH B IRQ
OC1A
(PB1)
T/C1 COMPARE
MATCH A IRQ
T/C CONTROL
REGISTER 1 (TCCR1) PWM1A
COM1B1
PWM1B
COM1B0
FOC1B
FOC1A
(OCR1A) (OCR1B) (OCR1C)
8-BIT COMPARATOR
T/C1 OUTPUT
COMPARE REGISTER TOV0
COM1A1
COM1A0
8-BIT COMPARATOR
T/C1 OUTPUT
COMPARE REGISTER
GLOBAL T/C CONTROL
REGISTER (GTCCR)
CS12
CS11
CS10
PSR1
CTC1
CS13
OC1A
(PB0)
OC1B
(PB4)
OC1B
(PB3)
DEAD TIME GENERATOR DEAD TIME GENERATORATtiny25/45/85 [DATASHEET] 86
2586Q–AVR–08/2013
12.2.1 Timer/Counter1 Initialization for Asynchronous Mode
To set Timer/Counter1 in asynchronous mode first enable PLL and then wait 100 µs for PLL to stabilize. Next, poll
the PLOCK bit until it is set and then set the PCKE bit.
12.2.2 Timer/Counter1 in PWM Mode
When the PWM mode is selected, Timer/Counter1 and the Output Compare Register C - OCR1C form a dual 8-bit,
free-running and glitch-free PWM generator with outputs on the PB1(OC1A) and PB4(OC1B) pins and inverted
outputs on pins PB0(OC1A) and PB3(OC1B). As default non-overlapping times for complementary output pairs are
zero, but they can be inserted using a Dead Time Generator (see description on page 100).
Figure 12-4. The PWM Output Pair
When the counter value match the contents of OCR1A or OCR1B, the OC1A and OC1B outputs are set or cleared
according to the COM1A1/COM1A0 or COM1B1/COM1B0 bits in the Timer/Counter1 Control Register A - TCCR1,
as shown in Table 12-1.
Timer/Counter1 acts as an up-counter, counting from $00 up to the value specified in the output compare register
OCR1C, and starting from $00 up again. A compare match with OC1C will set an overflow interrupt flag (TOV1)
after a synchronization delay following the compare event.
Note that in PWM mode, writing to the Output Compare Registers OCR1A or OCR1B, the data value is first transferred
to a temporary location. The value is latched into OCR1A or OCR1B when the Timer/Counter reaches
OCR1C. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized
OCR1A or OCR1B. See Figure 12-5 for an example.
Table 12-1. Compare Mode Select in PWM Mode
COM1x1 COM1x0 Effect on Output Compare Pins
0 0 OC1x not connected.
OC1x not connected.
0 1 OC1x cleared on compare match. Set whenTCNT1 = $00.
OC1x set on compare match. Cleared when TCNT1 = $00.
1 0 OC1x cleared on compare match. Set when TCNT1 = $00.
OC1x not connected.
1 1 OC1x Set on compare match. Cleared when TCNT1= $00.
OC1x not connected.
PWM1x
PWM1x
t non-overlap=0 t non-overlap=0 x = A or BATtiny25/45/85 [DATASHEET] 87
2586Q–AVR–08/2013
Figure 12-5. Effects of Unsynchronized OCR Latching
During the time between the write and the latch operation, a read from OCR1A or OCR1B will read the contents of
the temporary location. This means that the most recently written value always will read out of OCR1A or OCR1B.
When OCR1A or OCR1B contain $00 or the top value, as specified in OCR1C register, the output PB1(OC1A) or
PB4(OC1B) is held low or high according to the settings of COM1A1/COM1A0. This is shown in Table 12-2.
In PWM mode, the Timer Overflow Flag - TOV1 is set when the TCNT1 counts to the OCR1C value and the
TCNT1 is reset to $00. The Timer Overflow Interrupt1 is executed when TOV1 is set provided that Timer Overflow
Interrupt and global interrupts are enabled. This also applies to the Timer Output Compare flags and interrupts.
The frequency of the PWM will be Timer Clock 1 Frequency divided by (OCR1C value + 1). See the following
equation:
Resolution shows how many bits are required to express the value in the OCR1C register and can be calculated
using the following equation:
Table 12-2. PWM Outputs OCR1x = $00 or OCR1C, x = A or B
COM1x1 COM1x0 OCR1x Output OC1x Output OC1x
0 1 $00 L H
0 1 OCR1C H L
1 0 $00 L Not connected.
1 0 OCR1C H Not connected.
1 1 $00 H Not connected.
1 1 OCR1C L Not connected.
PWM Output OC1x
PWM Output OC1x
Unsynchronized OC1x Latch
Synchronized OC1x Latch
Counter Value
Compare Value
Counter Value
Compare Value
Compare Value changes
Glitch
Compare Value changes
f
PWM
f
TCK1
OCR1C + 1 = ------------------------------------
R = log2 OCR1C 1 ( ) +ATtiny25/45/85 [DATASHEET] 88
2586Q–AVR–08/2013
Table 12-3. Timer/Counter1 Clock Prescale Select in the Asynchronous Mode
PWM Frequency Clock Selection CS1[3:0] OCR1C RESOLUTION
20 kHz PCK/16 0101 199 7.6
30 kHz PCK/16 0101 132 7.1
40 kHz PCK/8 0100 199 7.6
50 kHz PCK/8 0100 159 7.3
60 kHz PCK/8 0100 132 7.1
70 kHz PCK/4 0011 228 7.8
80 kHz PCK/4 0011 199 7.6
90 kHz PCK/4 0011 177 7.5
100 kHz PCK/4 0011 159 7.3
110 kHz PCK/4 0011 144 7.2
120 kHz PCK/4 0011 132 7.1
130 kHz PCK/2 0010 245 7.9
140 kHz PCK/2 0010 228 7.8
150 kHz PCK/2 0010 212 7.7
160 kHz PCK/2 0010 199 7.6
170 kHz PCK/2 0010 187 7.6
180 kHz PCK/2 0010 177 7.5
190 kHz PCK/2 0010 167 7.4
200 kHz PCK/2 0010 159 7.3
250 kHz PCK 0001 255 8.0
300 kHz PCK 0001 212 7.7
350 kHz PCK 0001 182 7.5
400 kHz PCK 0001 159 7.3
450 kHz PCK 0001 141 7.1
500 kHz PCK 0001 127 7.0ATtiny25/45/85 [DATASHEET] 89
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12.3 Register Description
12.3.1 TCCR1 – Timer/Counter1 Control Register
• Bit 7 – CTC1 : Clear Timer/Counter on Compare Match
When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle after a compare
match with OCR1C register value. If the control bit is cleared, Timer/Counter1 continues counting and is unaffected
by a compare match.
• Bit 6 – PWM1A: Pulse Width Modulator A Enable
When set (one) this bit enables PWM mode based on comparator OCR1A in Timer/Counter1 and the counter
value is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value.
• Bits 5:4 – COM1A[1:0]: Comparator A Output Mode, Bits 1 and 0
The COM1A1 and COM1A0 control bits determine any output pin action following a compare match with compare
register A in Timer/Counter1. Since the output pin action is an alternative function to an I/O port, the corresponding
direction control bit must be set (one) in order to control an output pin.
In Normal mode, the COM1A1 and COM1A0 control bits determine the output pin actions that affect pin PB1
(OC1A) as described in Table 12-4. Note that OC1A is not connected in normal mode.
In PWM mode, these bits have different functions. Refer to Table 12-1 on page 86 for a detailed description.
• Bits 3:0 - CS1[3:0]: Clock Select Bits 3, 2, 1, and 0
The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.
Bit 7 6 5 4 3 2 1 0
0x30 CTC1 PWM1A COM1A1 COM1A0 CS13 CS12 CS11 CS10 TCCR1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Table 12-4. Comparator A Mode Select in Normal Mode
COM1A1 COM1A0 Description
0 0 Timer/Counter Comparator A disconnected from output pin OC1A.
0 1 Toggle the OC1A output line.
1 0 Clear the OC1A output line.
1 1 Set the OC1A output line
Table 12-5. Timer/Counter1 Prescale Select
CS13 CS12 CS11 CS10
Asynchronous
Clocking Mode
Synchronous
Clocking Mode
0 0 0 0 T/C1 stopped T/C1 stopped
0 0 0 1 PCK CK
0 0 1 0 PCK/2 CK/2
0 0 1 1 PCK/4 CK/4
0 1 0 0 PCK/8 CK/8
0 1 0 1 PCK/16 CK/16
0 1 1 0 PCK/32 CK/32ATtiny25/45/85 [DATASHEET] 90
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The Stop condition provides a Timer Enable/Disable function.
12.3.2 GTCCR – General Timer/Counter1 Control Register
• Bit 6 – PWM1B: Pulse Width Modulator B Enable
When set (one) this bit enables PWM mode based on comparator OCR1B in Timer/Counter1 and the counter
value is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value.
• Bits 5:4 – COM1B[1:0]: Comparator B Output Mode, Bits 1 and 0
The COM1B1 and COM1B0 control bits determine any output pin action following a compare match with compare
register B in Timer/Counter1. Since the output pin action is an alternative function to an I/O port, the corresponding
direction control bit must be set (one) in order to control an output pin.
In Normal mode, the COM1B1 and COM1B0 control bits determine the output pin actions that affect pin PB4
(OC1B) as described in Table 12-6. Note that OC1B is not connected in normal mode.
In PWM mode, these bits have different functions. Refer to Table 12-1 on page 86 for a detailed description.
• Bit 3 – FOC1B: Force Output Compare Match 1B
Writing a logical one to this bit forces a change in the compare match output pin PB4 (OC1B) according to the values
already set in COM1B1 and COM1B0. If COM1B1 and COM1B0 written in the same cycle as FOC1B, the new
settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the
timer value. The automatic action programmed in COM1B1 and COM1B0 takes place as if a compare match had
0 1 1 1 PCK/64 CK/64
1 0 0 0 PCK/128 CK/128
1 0 0 1 PCK/256 CK/256
1 0 1 0 PCK/512 CK/512
1 0 1 1 PCK/1024 CK/1024
1 1 0 0 PCK/2048 CK/2048
1 1 0 1 PCK/4096 CK/4096
1 1 1 0 PCK/8192 CK/8192
1 1 1 1 PCK/16384 CK/16384
Table 12-5. Timer/Counter1 Prescale Select (Continued)
CS13 CS12 CS11 CS10
Asynchronous
Clocking Mode
Synchronous
Clocking Mode
Bit 7 6 5 4 3 2 1 0
0x2C TSM PWM1B COM1B1 COM1B0 FOC1B FOC1A PSR1 PSR0 GTCCR
Read/Write R/W R/W R/W R/W W W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Table 12-6. Comparator B Mode Select in Normal Mode
COM1B1 COM1B0 Description
0 0 Timer/Counter Comparator B disconnected from output pin OC1B.
0 1 Toggle the OC1B output line.
1 0 Clear the OC1B output line.
1 1 Set the OC1B output lineATtiny25/45/85 [DATASHEET] 91
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occurred, but no interrupt is generated. The FOC1B bit always reads as zero. FOC1B is not in use if PWM1B bit is
set.
• Bit 2 – FOC1A: Force Output Compare Match 1A
Writing a logical one to this bit forces a change in the compare match output pin PB1 (OC1A) according to the values
already set in COM1A1 and COM1A0. If COM1A1 and COM1A0 written in the same cycle as FOC1A, the new
settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the
timer value. The automatic action programmed in COM1A1 and COM1A0 takes place as if a compare match had
occurred, but no interrupt is generated. The FOC1A bit always reads as zero. FOC1A is not in use if PWM1A bit is
set.
• Bit 1 – PSR1 : Prescaler Reset Timer/Counter1
When this bit is set (one), the Timer/Counter prescaler (TCNT1 is unaffected) will be reset. The bit will be cleared
by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always read
as zero.
12.3.3 TCNT1 – Timer/Counter1
This 8-bit register contains the value of Timer/Counter1.
Timer/Counter1 is realized as an up counter with read and write access. Due to synchronization of the CPU,
Timer/Counter1 data written into Timer/Counter1 is delayed by one and half CPU clock cycles in synchronous
mode and at most one CPU clock cycles for asynchronous mode.
12.3.4 OCR1A –Timer/Counter1 Output Compare RegisterA
The output compare register A is an 8-bit read/write register.
The Timer/Counter Output Compare Register A contains data to be continuously compared with Timer/Counter1.
Actions on compare matches are specified in TCCR1. A compare match does only occur if Timer/Counter1 counts
to the OCR1A value. A software write that sets TCNT1 and OCR1A to the same value does not generate a compare
match.
A compare match will set the compare interrupt flag OCF1A after a synchronization delay following the compare
event.
12.3.5 OCR1B – Timer/Counter1 Output Compare RegisterB
The output compare register B is an 8-bit read/write register.
The Timer/Counter Output Compare Register B contains data to be continuously compared with Timer/Counter1.
Actions on compare matches are specified in TCCR1. A compare match does only occur if Timer/Counter1 counts
Bit 7 6 5 4 3 2 1 0
0x2F MSB LSB TCNT1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x2E MSB LSB OCR1A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x2B MSB LSB OCR1B
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0ATtiny25/45/85 [DATASHEET] 92
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to the OCR1B value. A software write that sets TCNT1 and OCR1B to the same value does not generate a compare
match.
A compare match will set the compare interrupt flag OCF1B after a synchronization delay following the compare
event.
12.3.6 OCR1C – Timer/Counter1 Output Compare RegisterC
The output compare register C is an 8-bit read/write register.
The Timer/Counter Output Compare Register C contains data to be continuously compared with Timer/Counter1.
A compare match does only occur if Timer/Counter1 counts to the OCR1C value. A software write that sets TCNT1
and OCR1C to the same value does not generate a compare match. If the CTC1 bit in TCCR1 is set, a compare
match will clear TCNT1.
This register has the same function in normal mode and PWM mode.
12.3.7 TIMSK – Timer/Counter Interrupt Mask Register
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.
• Bit 6 – OCIE1A: Timer/Counter1 Output Compare Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare
MatchA, interrupt is enabled. The corresponding interrupt at vector $003 is executed if a compare matchA occurs.
The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register.
• Bit 5 – OCIE1B: Timer/Counter1 Output Compare Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare
MatchB, interrupt is enabled. The corresponding interrupt at vector $009 is executed if a compare matchB occurs.
The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register.
• Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt
is enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter1 occurs.
The Overflow Flag (Timer1) is set (one) in the Timer/Counter Interrupt Flag Register - TIFR.
• Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.
Bit 7 6 5 4 3 2 1 0
0x2D MSB LSB OCR1C
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
0x39 – OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 – TIMSK
Read/Write R R/W R/W R/W R/W R/W R/W R
Initial value 0 0 0 0 0 0 0 0ATtiny25/45/85 [DATASHEET] 93
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12.3.8 TIFR – Timer/Counter Interrupt Flag Register
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.
• Bit 6 – OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1A -
Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling
vector. Alternatively, OCF1A is cleared, after synchronization clock cycle, by writing a logic one to the flag. When
the I-bit in SREG, OCIE1A, and OCF1A are set (one), the Timer/Counter1 A compare match interrupt is executed.
• Bit 5 – OCF1B: Output Compare Flag 1B
The OCF1B bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1B -
Output Compare Register 1A. OCF1B is cleared by hardware when executing the corresponding interrupt handling
vector. Alternatively, OCF1B is cleared, after synchronization clock cycle, by writing a logic one to the flag. When
the I-bit in SREG, OCIE1B, and OCF1B are set (one), the Timer/Counter1 B compare match interrupt is executed.
• Bit 2 – TOV1: Timer/Counter1 Overflow Flag
In normal mode (PWM1A=0 and PWM1B=0) the bit TOV1 is set (one) when an overflow occurs in Timer/Counter1.
The bit TOV1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV1 is cleared, after synchronization clock cycle, by writing a logical one to the flag.
In PWM mode (either PWM1A=1 or PWM1B=1) the bit TOV1 is set (one) when compare match occurs between
Timer/Counter1 and data value in OCR1C - Output Compare Register 1C.
When the SREG I-bit, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the
Timer/Counter1 Overflow interrupt is executed.
• Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.
Bit 7 6 5 4 3 2 1 0
0x38 – OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 – TIFR
Read/Write R R/W R/W R/W R/W R/W R/W R
Initial value 0 0 0 0 0 0 0 0ATtiny25/45/85 [DATASHEET] 94
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12.3.9 PLLCSR – PLL Control and Status Register
• Bit 7 – LSM: Low Speed Mode
The high speed mode is enabled as default and the fast peripheral clock is 64 MHz, but the low speed mode can
be set by writing the LSM bit to one. Then the fast peripheral clock is scaled down to 32 MHz. The low speed mode
must be set, if the supply voltage is below 2.7 volts, because the Timer/Counter1 is not running fast enough on low
voltage levels. It is highly recommended that Timer/Counter1 is stopped whenever the LSM bit is changed.
Note, that LSM can not be set if PLLCLK is used as system clock.
• Bit 6:3 – Res : Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and always read as zero.
• Bit 2 – PCKE: PCK Enable
The PCKE bit change the Timer/Counter1 clock source. When it is set, the asynchronous clock mode is enabled
and fast 64 MHz (or 32 MHz in Low Speed Mode) PCK clock is used as Timer/Counter1 clock source. If this bit is
cleared, the synchronous clock mode is enabled, and system clock CK is used as Timer/Counter1 clock source.
This bit can be set only if PLLE bit is set. It is safe to set this bit only when the PLL is locked i.e the PLOCK bit is 1.
The bit PCKE can only be set, if the PLL has been enabled earlier.
• Bit 1 – PLLE: PLL Enable
When the PLLE is set, the PLL is started and if needed internal RC-oscillator is started as a PLL reference clock. If
PLL is selected as a system clock source the value for this bit is always 1.
• Bit 0 – PLOCK: PLL Lock Detector
When the PLOCK bit is set, the PLL is locked to the reference clock. The PLOCK bit should be ignored during initial
PLL lock-in sequence when PLL frequency overshoots and undershoots, before reaching steady state. The
steady state is obtained within 100 µs. After PLL lock-in it is recommended to check the PLOCK bit before enabling
PCK for Timer/Counter1.
Bit 7 6 5 4 3 2 1 0
0x27 LSM - - - - PCKE PLLE PLOCK PLLCSR
Read/Write R/W R R R R R/W R/W R
Initial value 0 0 0 0 0 0 0/1 0ATtiny25/45/85 [DATASHEET] 95
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13. 8-bit Timer/Counter1 in ATtiny15 Mode
The ATtiny15 compatibility mode is selected by writing the code “0011” to the CKSEL fuses (if any other code is
written, the Timer/Counter1 is working in normal mode). When selected the ATtiny15 compatibility mode provides
an ATtiny15 backward compatible prescaler and Timer/Counter. Furthermore, the clocking system has same clock
frequencies as in ATtiny15.
13.1 Timer/Counter1 Prescaler
Figure 13-1 shows an ATtiny15 compatible prescaler. It has two prescaler units, a 10-bit prescaler for the system
clock (CK) and a 3-bit prescaler for the fast peripheral clock (PCK). The clocking system of the Timer/Counter1 is
always synchronous in the ATtiny15 compatibility mode, because the same RC Oscillator is used as a PLL clock
source (generates the input clock for the prescaler) and the AVR core.
Figure 13-1. Timer/Counter1 Prescaler
The same clock selections as in ATtiny15 can be chosen for Timer/Counter1 from the output multiplexer, because
the frequency of the fast peripheral clock is 25.6 MHz and the prescaler is similar in the ATtiny15 compatibility
mode. The clock selections are PCK, PCK/2, PCK/4, PCK/8, CK, CK/2, CK/4, CK/8, CK/16, CK/32, CK/64,
CK/128, CK/256, CK/512, CK/1024 and stop.
13.2 Counter and Compare Units
Figure 13-2 shows Timer/Counter 1 synchronization register block diagram and synchronization delays in between
registers. Note that all clock gating details are not shown in the figure. The Timer/Counter1 register values go
through the internal synchronization registers, which cause the input synchronization delay, before affecting the
counter operation. The registers TCCR1, GTCCR, OCR1A and OCR1C can be read back right after writing the
register. The read back values are delayed for the Timer/Counter1 (TCNT1) register and flags (OCF1A and TOV1),
because of the input and output synchronization.
The Timer/Counter1 features a high resolution and a high accuracy usage with the lower prescaling opportunities.
It can also support an accurate, high speed, 8-bit Pulse Width Modulator (PWM) using clock speeds up to 25.6
MHz. In this mode, Timer/Counter1 and the Output Compare Registers serve as a stand-alone PWM. Refer to
“Timer/Counter1 in PWM Mode” on page 97 for a detailed description on this function. Similarly, the high prescaling
opportunities make this unit useful for lower speed functions or exact timing functions with infrequent actions.
TIMER/COUNTER1 COUNT ENABLE
PSR1
CS10
CS11
CS12
PCK (25.6 MHz)
0
CS13
3-BIT T/C PRESCALER PCK PCK/2 PCK/4 PCK/8
CK/2
CK/4
CK/8
CK/16
CK/32
CK/64
CK/128
CK/256
CK/512
CK/1024
10-BIT T/C PRESCALER
CK (1.6 MHz)
CK
CLEAR CLEARATtiny25/45/85 [DATASHEET] 96
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Figure 13-2. Timer/Counter 1 Synchronization Register Block Diagram.
Timer/Counter1 and the prescaler allow running the CPU from any clock source while the prescaler is operating on
the fast 25.6 MHz PCK clock in the asynchronous mode.
The following Figure 13-3 shows the block diagram for Timer/Counter1.
8-BIT DATABUS
OCR1A OCR1A_SI
OCR1C OCR1C_SI TCNT_SO
TCCR1 TCCR1_SI
GTCCR GTCCR_SI
TCNT1 TCNT1_SI
OCF1A OCF1A_SI
TOV1 TOV1_SI TOV1_SO
OCF1A_SO
TCNT1
S
A
S
A
PCKE
CK
PCK
IO-registers Input synchronization
registers
Timer/Counter1 Output synchronization
registers
SYNC
MODE
ASYNC
MODE
1 PCK Delay No Delay ~1 CK Delay
1PCK Delay No Delay
TCNT1
OCF1A
TOV1
1..2 PCK Delay
1..2 PCK Delay ~1 CK DelayATtiny25/45/85 [DATASHEET] 97
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Figure 13-3. Timer/Counter1 Block Diagram
Two status flags (overflow and compare match) are found in the Timer/Counter Interrupt Flag Register - TIFR.
Control signals are found in the Timer/Counter Control Registers TCCR1 and GTCCR. The interrupt enable/disable
settings are found in the Timer/Counter Interrupt Mask Register - TIMSK.
The Timer/Counter1 contains two Output Compare Registers, OCR1A and OCR1C as the data source to be compared
with the Timer/Counter1 contents. In normal mode the Output Compare functions are operational with
OCR1A only. OCR1A determines action on the OC1A pin (PB1), and it can generate Timer1 OC1A interrupt in normal
mode and in PWM mode. OCR1C holds the Timer/Counter maximum value, i.e. the clear on compare match
value. In the normal mode an overflow interrupt (TOV1) is generated when Timer/Counter1 counts from $FF to
$00, while in the PWM mode the overflow interrupt is generated when the Timer/Counter1 counts either from $FF
to $00 or from OCR1C to $00.
In PWM mode, OCR1A provides the data values against which the Timer Counter value is compared. Upon compare
match the PWM outputs (OC1A) is generated. In PWM mode, the Timer Counter counts up to the value
specified in the output compare register OCR1C and starts again from $00. This feature allows limiting the counter
“full” value to a specified value, lower than $FF. Together with the many prescaler options, flexible PWM frequency
selection is provided. Table 12-3 on page 88 lists clock selection and OCR1C values to obtain PWM frequencies
from 20 kHz to 250 kHz in 10 kHz steps and from 250 kHz to 500 kHz in 50 kHz steps. Higher PWM frequencies
can be obtained at the expense of resolution.
13.2.1 Timer/Counter1 in PWM Mode
When the PWM mode is selected, Timer/Counter1 and the Output Compare Register A - OCR1A form an 8-bit,
free-running and glitch-free PWM generator with output on the PB1(OC1A).
8-BIT DATABUS
TIMER INT. FLAG
REGISTER (TIFR)
TIMER/COUNTER1
8-BIT COMPARATOR
T/C1 OUTPUT
COMPARE REGISTER
TIMER INT. MASK
REGISTER (TIMSK)
TIMER/COUNTER1
(TCNT1) T/C CLEAR T/C1 CONTROL
LOGIC
TOV1
OCIE1A
TOIE1
TOIE0
OCF1A
TOV1
OCF1A
CK
PCK
T/C1 OVERFLOW
IRQ
OC1A
(PB1)
T/C1 COMPARE
MATCH A IRQ
GLOBAL T/C CONTROL
REGISTER 2 (GTCCR)
PWM1A
FOC1A
(OCR1A) (OCR1C)
8-BIT COMPARATOR
T/C1 OUTPUT
COMPARE REGISTER TOV0
COM1A1
COM1A0
T/C CONTROL
REGISTER 1 (TCCR1)
CTC1
CS13
CS12
CS11
CS10
PSR1ATtiny25/45/85 [DATASHEET] 98
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When the counter value match the content of OCR1A, the OC1A and output is set or cleared according to the
COM1A1/COM1A0 bits in the Timer/Counter1 Control Register A - TCCR1, as shown in Table 13-1.
Timer/Counter1 acts as an up-counter, counting from $00 up to the value specified in the output compare register
OCR1C, and starting from $00 up again. A compare match with OCR1C will set an overflow interrupt flag (TOV1)
after a synchronization delay following the compare event.
Note that in PWM mode, writing to the Output Compare Register OCR1A, the data value is first transferred to a
temporary location. The value is latched into OCR1A when the Timer/Counter reaches OCR1C. This prevents the
occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR1A. See Figure 13-4 for an
e xample.
Figure 13-4. Effects of Unsynchronized OCR Latching
During the time between the write and the latch operation, a read from OCR1A will read the contents of the temporary
location. This means that the most recently written value always will read out of OCR1A.
When OCR1A contains $00 or the top value, as specified in OCR1C register, the output PB1(OC1A) is held low or
high according to the settings of COM1A1/COM1A0. This is shown in Table 13-2.
Table 13-1. Compare Mode Select in PWM Mode
COM1A1 COM1A0 Effect on Output Compare Pin
0 0 OC1A not connected.
0 1 OC1A not connected.
1 0 OC1A cleared on compare match. Set when TCNT1 = $00.
1 1 OC1A set on compare match. Cleared when TCNT1 = $00.
Table 13-2. PWM Outputs OCR1A = $00 or OCR1C
COM1A1 COM1A0 OCR1A Output OC1A
0 1 $00 L
0 1 OCR1C H
1 0 $00 L
PWM Output OC1A
PWM Output OC1A
Unsynchronized OC1A Latch
Synchronized OC1A Latch
Counter Value
Compare Value
Counter Value
Compare Value
Compare Value changes
Glitch
Compare Value changesATtiny25/45/85 [DATASHEET] 99
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In PWM mode, the Timer Overflow Flag - TOV1 is set when the TCNT1 counts to the OCR1C value and the
TCNT1 is reset to $00. The Timer Overflow Interrupt1 is executed when TOV1 is set provided that Timer Overflow
Interrupt and global interrupts are enabled. This also applies to the Timer Output Compare flags and interrupts.
The PWM frequency can be derived from the timer/counter clock frequency using the following equation:
The duty cycle of the PWM waveform can be calculated using the following equation:
...where TPCK is the period of the fast peripheral clock (1/25.6 MHz = 39.1 ns).
Resolution indicates how many bits are required to express the value in the OCR1C register. It can be calculated
using the following equation:
1 0 OCR1C H
1 1 $00 H
1 1 OCR1C L
Table 13-3. Timer/Counter1 Clock Prescale Select in the Asynchronous Mode
PWM Frequency Clock Selection CS1[3:0] OCR1C RESOLUTION
20 kHz PCK/16 0101 199 7.6
30 kHz PCK/16 0101 132 7.1
40 kHz PCK/8 0100 199 7.6
50 kHz PCK/8 0100 159 7.3
60 kHz PCK/8 0100 132 7.1
70 kHz PCK/4 0011 228 7.8
80 kHz PCK/4 0011 199 7.6
90 kHz PCK/4 0011 177 7.5
100 kHz PCK/4 0011 159 7.3
110 kHz PCK/4 0011 144 7.2
120 kHz PCK/4 0011 132 7.1
130 kHz PCK/2 0010 245 7.9
140 kHz PCK/2 0010 228 7.8
150 kHz PCK/2 0010 212 7.7
Table 13-2. PWM Outputs OCR1A = $00 or OCR1C
COM1A1 COM1A0 OCR1A Output OC1A
f f
TCK1
OCR1C + 1 = -----------------------------------
D OCR1A 1 + TTCK1 TPCK –
OCR1C 1 + TTCK1 = ----------------------------------------------------------------------------
R = log2 OCR1C 1 ( ) +ATtiny25/45/85 [DATASHEET] 100
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13.3 Register Description
13.3.1 TCCR1 – Timer/Counter1 Control Register
• Bit 7 – CTC1 : Clear Timer/Counter on Compare Match
When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle after a compare
match with OCR1A register. If the control bit is cleared, Timer/Counter1 continues counting and is unaffected by a
compare match.
• Bit 6 – PWM1A: Pulse Width Modulator A Enable
When set (one) this bit enables PWM mode based on comparator OCR1A in Timer/Counter1 and the counter
value is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value.
• Bits 5:4 – COM1A[1:0]: Comparator A Output Mode, Bits 1 and 0
The COM1A1 and COM1A0 control bits determine any output pin action following a compare match with compare
register A in Timer/Counter1. Output pin actions affect pin PB1 (OC1A). Since this is an alternative function to an
I/O port, the corresponding direction control bit must be set (one) in order to control an output pin.
In PWM mode, these bits have different functions. Refer to Table 13-1 on page 98 for a detailed description.
160 kHz PCK/2 0010 199 7.6
170 kHz PCK/2 0010 187 7.6
180 kHz PCK/2 0010 177 7.5
190 kHz PCK/2 0010 167 7.4
200 kHz PCK/2 0010 159 7.3
250 kHz PCK 0001 255 8.0
300 kHz PCK 0001 212 7.7
350 kHz PCK 0001 182 7.5
400 kHz PCK 0001 159 7.3
450 kHz PCK 0001 141 7.1
500 kHz PCK 0001 127 7.0
Table 13-3. Timer/Counter1 Clock Prescale Select in the Asynchronous Mode (Continued)
PWM Frequency Clock Selection CS1[3:0] OCR1C RESOLUTION
Bit 7 6 5 4 3 2 1 0
0x30 CTC1 PWM1A COM1A1 COM1A0 CS13 CS12 CS11 CS10 TCCR1A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Table 13-4. Comparator A Mode Select
COM1A1 COM1A0 Description
0 0 Timer/Counter Comparator A disconnected from output pin OC1A.
0 1 Toggle the OC1A output line.
1 0 Clear the OC1A output line.
1 1 Set the OC1A output lineATtiny25/45/85 [DATASHEET] 101
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• Bits 3:0 – CS1[3:0]: Clock Select Bits 3, 2, 1, and 0
The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.
The Stop condition provides a Timer Enable/Disable function.
13.3.2 GTCCR – General Timer/Counter1 Control Register
• Bit 2 – FOC1A: Force Output Compare Match 1A
Writing a logical one to this bit forces a change in the compare match output pin PB1 (OC1A) according to the values
already set in COM1A1 and COM1A0. If COM1A1 and COM1A0 written in the same cycle as FOC1A, the new
settings will be used. The Force Output Compare bit can be used to change the output pin value regardless of the
timer value. The automatic action programmed in COM1A1 and COM1A0 takes place as if a compare match had
occurred, but no interrupt is generated. The FOC1A bit always reads as zero. FOC1A is not in use if PWM1A bit is
set.
• Bit 1 – PSR1 : Prescaler Reset Timer/Counter1
When this bit is set (one), the Timer/Counter prescaler (TCNT1 is unaffected) will be reset. The bit will be cleared
by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always read
as zero.
Table 13-5. Timer/Counter1 Prescale Select
CS13 CS12 CS11 CS10 T/C1 Clock
0 0 0 0 T/C1 stopped
0 0 0 1 PCK
0 0 1 0 PCK/2
0 0 1 1 PCK/4
0 1 0 0 PCK/8
0 1 0 1 CK
0 1 1 0 CK/2
0 1 1 1 CK/4
1 0 0 0 CK/8
1 0 0 1 CK/16
1 0 1 0 CK/32
1 0 1 1 CK/64
1 1 0 0 CK/128
1 1 0 1 CK/256
1 1 1 0 CK/512
1 1 1 1 CK/1024
Bit 7 6 5 4 3 2 1 0
0x2C TSM PWM1B COM1B1 COM1B0 FOC1B FOC1A PSR1 PSR0 GTCCR
Read/Write R/W R/W R/W R/W W W R/W R/W
Initial value 0 0 0 0 0 0 0 0ATtiny25/45/85 [DATASHEET] 102
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13.3.3 TCNT1 – Timer/Counter1
This 8-bit register contains the value of Timer/Counter1.
Timer/Counter1 is realized as an up counter with read and write access. Due to synchronization of the CPU,
Timer/Counter1 data written into Timer/Counter1 is delayed by one CPU clock cycle in synchronous mode and at
most two CPU clock cycles for asynchronous mode.
13.3.4 OCR1A – Timer/Counter1 Output Compare RegisterA
The output compare register A is an 8-bit read/write register.
The Timer/Counter Output Compare Register A contains data to be continuously compared with Timer/Counter1.
Actions on compare matches are specified in TCCR1. A compare match does only occur if Timer/Counter1 counts
to the OCR1A value. A software write that sets TCNT1 and OCR1A to the same value does not generate a compare
match.
A compare match will set the compare interrupt flag OCF1A after a synchronization delay following the compare
event.
13.3.5 OCR1C – Timer/Counter1 Output Compare Register C
The Output Compare Register B - OCR1B from ATtiny15 is replaced with the output compare register C - OCR1C
that is an 8-bit read/write register. This register has the same function as the Output Compare Register B in
ATtiny15.
The Timer/Counter Output Compare Register C contains data to be continuously compared with Timer/Counter1.
A compare match does only occur if Timer/Counter1 counts to the OCR1C value. A software write that sets TCNT1
and OCR1C to the same value does not generate a compare match. If the CTC1 bit in TCCR1 is set, a compare
match will clear TCNT1.
13.3.6 TIMSK – Timer/Counter Interrupt Mask Register
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.
Bit 7 6 5 4 3 2 1 0
0x2F MSB LSB TCNT1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x2E MSB LSB OCR1A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x2D MSB LSB OCR1C
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 1 1 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 0
0x39 – OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 – TIMSK
Read/Write R R/W R/W R/W R/W R/W R/W R
Initial value 0 0 0 0 0 0 0 0ATtiny25/45/85 [DATASHEET] 103
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• Bit 6 – OCIE1A: Timer/Counter1 Output Compare Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare
MatchA, interrupt is enabled. The corresponding interrupt at vector $003 is executed if a compare matchA occurs.
The Compare Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register.
• Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt
is enabled. The corresponding interrupt (at vector $004) is executed if an overflow in Timer/Counter1 occurs.
The Overflow Flag (Timer1) is set (one) in the Timer/Counter Interrupt Flag Register - TIFR.
• Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.
13.3.7 TIFR – Timer/Counter Interrupt Flag Register
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.
• Bit 6 – OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data value in OCR1A -
Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling
vector. Alternatively, OCF1A is cleared, after synchronization clock cycle, by writing a logic one to the flag. When
the I-bit in SREG, OCIE1A, and OCF1A are set (one), the Timer/Counter1 A compare match interrupt is executed.
• Bit 2 – TOV1: Timer/Counter1 Overflow Flag
The bit TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, TOV1 is cleared, after synchronization clock cycle,
by writing a logical one to the flag. When the SREG I-bit, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable),
and TOV1 are set (one), the Timer/Counter1 Overflow interrupt is executed.
• Bit 0 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.
13.3.8 PLLCSR – PLL Control and Status Register
• Bits 6:3 – Res : Reserved Bits
These bits are reserved bits in the ATtiny25/45/85 and always read as zero.
• Bit 2 – PCKE: PCK Enable
The bit PCKE is always set in the ATtiny15 compatibility mode.
• Bit 1 – PLLE: PLL Enable
The PLL is always enabled in the ATtiny15 compatibility mode.
Bit 7 6 5 4 3 2 1 0
0x38 – OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 – TIFR
Read/Write R R/W R/W R/W R/W R/W R/W R
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x27 LSM – – – – PCKE PLLE PLOCK PLLCSR
Read/Write R/W R R R R R/W R/W R
Initial value 0 0 0 0 0 0 0/1 0ATtiny25/45/85 [DATASHEET] 104
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• Bit 0 – PLOCK: PLL Lock Detector
When the PLOCK bit is set, the PLL is locked to the reference clock. The PLOCK bit should be ignored during initial
PLL lock-in sequence when PLL frequency overshoots and undershoots, before reaching steady state. The
steady state is obtained within 100 µs. After PLL lock-in it is recommended to check the PLOCK bit before enabling
PCK for Timer/Counter1.ATtiny25/45/85 [DATASHEET] 105
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14. Dead Time Generator
The Dead Time Generator is provided for the Timer/Counter1 PWM output pairs to allow driving external power
control switches safely. The Dead Time Generator is a separate block that can be connected to Timer/Counter1
and it is used to insert dead times (non-overlapping times) for the Timer/Counter1 complementary output pairs
(OC1A-OC1A and OC1B-OC1B). The sharing of tasks is as follows: the timer/counter generates the PWM output
and the Dead Time Generator generates the non-overlapping PWM output pair from the timer/counter PWM signal.
Two Dead Time Generators are provided, one for each PWM output. The non-overlap time is adjustable and the
PWM output and it’s complementary output are adjusted separately, and independently for both PWM outputs.
Figure 14-1. Timer/Counter1 & Dead Time Generators
The dead time generation is based on the 4-bit down counters that count the dead time, as shown in Figure 46.
There is a dedicated prescaler in front of the Dead Time Generator that can divide the Timer/Counter1 clock (PCK
or CK) by 1, 2, 4 or 8. This provides for large range of dead times that can be generated. The prescaler is controlled
by two control bits DTPS1[1:0] from the I/O register at address 0x23. The block has also a rising and falling
edge detector that is used to start the dead time counting period. Depending on the edge, one of the transitions on
the rising edges, OC1x or OC1x is delayed until the counter has counted to zero. The comparator is used to compare
the counter with zero and stop the dead time insertion when zero has been reached. The counter is loaded
with a 4-bit DT1xH or DT1xL value from DT1x I/O register, depending on the edge of the PWM generator output
when the dead time insertion is started.
Figure 14-2. Dead Time Generator
The length of the counting period is user adjustable by selecting the dead time prescaler setting in 0x23 register,
and selecting then the dead time value in I/O register DT1x. The DT1x register consists of two 4-bit fields, DT1xH
and DT1xL that control the dead time periods of the PWM output and its’ complementary output separately. Thus
TIMER/COUNTER1
OC1A OC1A OC1B OC1B
DEAD TIME GENERATOR
PWM GENERATOR
PCKE
T15M
PCK
CK
DT1AH DT1BH
DEAD TIME GENERATOR
PWM1A PWM1B
DT1AL DT1BL
CLOCK CONTROL
OC1x
OC1x
T/C1 CLOCK
PWM1x
4-BIT COUNTER
COMPARATOR
DT1xH
DT1xL
DT1x
I/O REGISTER
DEAD TIME
PRESCALER
DTPS1[1:0]ATtiny25/45/85 [DATASHEET] 106
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the rising edge of OC1x and OC1x can have different dead time periods. The dead time is adjusted as the number
of prescaled dead time generator clock cycles.
Figure 14-3. The Complementary Output Pair
14.1 Register Description
14.1.1 DTPS1 – Timer/Counter1 Dead Time Prescaler Register 1
The dead time prescaler register, DTPS1 is a 2-bit read/write register.
• Bits 1:0 – DTPS1[1:0]: Dead Time Prescaler
The dedicated Dead Time prescaler in front of the Dead Time Generator can divide the Timer/Counter1 clock (PCK
or CK) by 1, 2, 4 or 8 providing a large range of dead times that can be generated. The Dead Time prescaler is
controlled by two bits DTPS1[1:0] from the Dead Time Prescaler register. These bits define the division factor of
the Dead Time prescaler. The division factors are given in table 46.
OC1x
x = A or B
t non-overlap / rising edge t non-overlap / falling edge
OC1x
PWM1x
Bit 7 6 5 4 3 2 1 0
0x23 DTPS11 DTPS10 DTPS1
Read/Write R R R R R R R/W R/W
Initial value 0 0 0 0 0 0 0 0
Table 14-1. Division factors of the Dead Time prescaler
DTPS11 DTPS10 Prescaler divides the T/C1 clock by
0 0 1x (no division)
0 1 2x
1 0 4x
1 1 8xATtiny25/45/85 [DATASHEET] 107
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14.1.2 DT1A – Timer/Counter1 Dead Time A
The dead time value register A is an 8-bit read/write register.
The dead time delay of is adjusted by the dead time value register, DT1A. The register consists of two fields,
DT1AH[3:0] and DT1AL[3:0], one for each complementary output. Therefore a different dead time delay can be
adjusted for the rising edge of OC1A and the rising edge of OC1A.
• Bits 7:4 – DT1AH[3:0]: Dead Time Value for OC1A Output
The dead time value for the OC1A output. The dead time delay is set as a number of the prescaled timer/counter
clocks. The minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period
multiplied by 15.
• Bits 3:0 – DT1AL[3:0]: Dead Time Value for OC1A Output
The dead time value for the OC1A output. The dead time delay is set as a number of the prescaled timer/counter
clocks. The minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period
multiplied by 15.
14.1.3 DT1B – Timer/Counter1 Dead Time B
The dead time value register Bis an 8-bit read/write register.
The dead time delay of is adjusted by the dead time value register, DT1B. The register consists of two fields,
DT1BH[3:0] and DT1BL[3:0], one for each complementary output. Therefore a different dead time delay can be
adjusted for the rising edge of OC1A and the rising edge of OC1A.
• Bits 7:4 – DT1BH[3:0]: Dead Time Value for OC1B Output
The dead time value for the OC1B output. The dead time delay is set as a number of the prescaled timer/counter
clocks. The minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period
multiplied by 15.
• Bits 3:0 – DT1BL[3:0]: Dead Time Value for OC1B Output
The dead time value for the OC1B output. The dead time delay is set as a number of the prescaled timer/counter
clocks. The minimum dead time is zero and the maximum dead time is the prescaled time/counter clock period
multiplied by 15.
Bit 7 6 5 4 3 2 1 0
0x25 DT1AH3 DT1AH2 DT1AH1 DT1AH0 DT1AL3 DT1AL2 DT1AL1 DT1AL0 DT1A
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x24 DT1BH3 DT1BH2 DT1BH1 DT1BH0 DT1BL3 DT1BL2 DT1BL1 DT1BL0 DT1B
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0ATtiny25/45/85 [DATASHEET] 108
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15. USI – Universal Serial Interface
15.1 Features
• Two-wire Synchronous Data Transfer (Master or Slave)
• Three-wire Synchronous Data Transfer (Master or Slave)
• Data Received Interrupt
• Wakeup from Idle Mode
• Wake-up from All Sleep Modes In Two-wire Mode
• Two-wire Start Condition Detector with Interrupt Capability
15.2 Overview
The Universal Serial Interface (USI), provides the basic hardware resources needed for serial communication.
Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code
space than solutions based on software only. Interrupts are included to minimize the processor load.
A simplified block diagram of the USI is shown in Figure 15-1 For actual placement of I/O pins refer to “Pinout
ATtiny25/45/85” on page 2. Device-specific I/O Register and bit locations are listed in the “Register Descriptions”
on page 115.
Figure 15-1. Universal Serial Interface, Block Diagram
The 8-bit USI Data Register (USIDR) contains the incoming and outgoing data. It is directly accessible via the data
bus but a copy of the contents is also placed in the USI Buffer Register (USIBR) where it can be retrieved later. If
reading the USI Data Register directly, the register must be read as quickly as possible to ensure that no data is
lost.
The most significant bit of the USI Data Register is connected to one of two output pins (depending on the mode
configuration, see “USICR – USI Control Register” on page 116). There is a transparent latch between the output
of the USI Data Register and the output pin, which delays the change of data output to the opposite clock edge of
the data input sampling. The serial input is always sampled from the Data Input (DI) pin independent of the
configuration. DATA BUS
USIPF
USICS1
USICS0
USICLK
USITC
USIOIF USIOIE
USISIF
USIDC
USISIE Bit7
USIWM1
USIWM0
Two-wire
Clock
Control Unit
DO (Output only)
DI/SDA (Input/Open Drain)
USCK/SCL (Input/Open Drain)
4-bit Counter
USIDR
USISR
D Q
LE
USICR
CLOCK
HOLD
TIM0 COMP
Bit0
[1]
3
0
1
2
3
0
1
2
0
1
2
USIBRATtiny25/45/85 [DATASHEET] 109
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The 4-bit counter can be both read and written via the data bus, and it can generate an overflow interrupt. Both the
USI Data Register and the counter are clocked simultaneously by the same clock source. This allows the counter
to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. Note
that when an external clock source is selected the counter counts both clock edges. This means the counter registers
the number of clock edges and not the number of data bits. The clock can be selected from three different
sources: The USCK pin, Timer/Counter0 Compare Match or from software.
The two-wire clock control unit can be configured to generate an interrupt when a start condition has been detected
on the two-wire bus. It can also be set to generate wait states by holding the clock pin low after a start condition is
detected, or after the counter overflows.
15.3 Functional Descriptions
15.3.1 Three-wire Mode
The USI three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but does not have the
slave select (SS) pin functionality. However, this feature can be implemented in software, if required. Pin names
used in this mode are DI, DO, and USCK.
Figure 15-2. Three-wire Mode Operation, Simplified Diagram
Figure 15-2 shows two USI units operating in three-wire mode, one as Master and one as Slave. The two USI Data
Registers are interconnected in such way that after eight USCK clocks, the data in each register has been interchanged.
The same clock also increments the USI’s 4-bit counter. The Counter Overflow (interrupt) Flag, or
USIOIF, can therefore be used to determine when a transfer is completed. The clock is generated by the Master
device software by toggling the USCK pin via the PORTB register or by writing a one to bit USITC bit in USICR.
SLAVE
MASTER
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
DO
DI
USCK
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
DO
DI
USCK
PORTxnATtiny25/45/85 [DATASHEET] 110
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Figure 15-3. Three-Wire Mode, Timing Diagram
The three-wire mode timing is shown in Figure 15-3 At the top of the figure is a USCK cycle reference. One bit is
shifted into the USI Data Register (USIDR) for each of these cycles. The USCK timing is shown for both external
clock modes. In external clock mode 0 (USICS0 = 0), DI is sampled at positive edges, and DO is changed (USI
Data Register is shifted by one) at negative edges. In external clock mode 1 (USICS0 = 1) the opposite edges with
respect to mode 0 are used. In other words, data is sampled at negative and changes the output at positive edges.
The USI clock modes corresponds to the SPI data mode 0 and 1.
Referring to the timing diagram (Figure 15-3), a bus transfer involves the following steps:
1. The slave and master devices set up their data outputs and, depending on the protocol used, enable their
output drivers (mark A and B). The output is set up by writing the data to be transmitted to the USI Data
Register. The output is enabled by setting the corresponding bit in the Data Direction Register of Port B.
Note that there is not a preferred order of points A and B in the figure, but both must be at least one half
USCK cycle before point C, where the data is sampled. This is in order to ensure that the data setup
requirement is satisfied. The 4-bit counter is reset to zero.
2. The master software generates a clock pulse by toggling the USCK line twice (C and D). The bit values on
the data input (DI) pins are sampled by the USI on the first edge (C), and the data output is changed on
the opposite edge (D). The 4-bit counter will count both edges.
3. Step 2. is repeated eight times for a complete register (byte) transfer.
4. After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate that the transfer has
been completed. If USI Buffer Registers are not used the data bytes that have been transferred must now
be processed before a new transfer can be initiated. The overflow interrupt will wake up the processor if it
is set to Idle mode. Depending of the protocol used the slave device can now set its output to high
impedance.
15.3.2 SPI Master Operation Example
The following code demonstrates how to use the USI as an SPI Master:
SPITransfer:
out USIDR,r16
ldi r16,(1< 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
High: > 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
20.5.1 Serial Programming Algorithm
When writing serial data to the ATtiny25/45/85, data is clocked on the rising edge of SCK.
When reading data from the ATtiny25/45/85, data is clocked on the falling edge of SCK. See Figure 21-4 and Figure
21-5 for timing details.
Table 20-10. Pin Mapping Serial Programming
Symbol Pins I/O Description
MOSI PB0 I Serial Data in
MISO PB1 O Serial Data out
SCK PB2 I Serial Clock
VCC
GND
SCK
MISO
MOSI
RESET
+1.8 - 5.5VATtiny25/45/85 [DATASHEET] 152
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To program and verify the ATtiny25/45/85 in the Serial Programming mode, the following sequence is recommended
(see four byte instruction formats in Table 20-12):
1. Power-up sequence: apply power between VCC and GND while RESET and SCK are set to “0”
– In some systems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse after SCK has been set to '0'. The duration of the pulse
must be at least tRST plus two CPU clock cycles. See Table 21-4 on page 165 for minimum pulse width
on RESET pin, tRST
2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction
to pin MOSI.
3. The serial programming instructions will not work if the communication is out of synchronization. When in
sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable
instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the
0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying
the 5 LSB of the address and data together with the Load Program memory Page instruction. To ensure
correct loading of the page, the data low byte must be loaded before data high byte is applied for a given
address. The Program memory Page is stored by loading the Write Program memory Page instruction
with the 6 MSB of the address. If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH
before issuing the next page. (See Table 20-11.) Accessing the serial programming interface before the
Flash write operation completes can result in incorrect programming.
5. A: The EEPROM array is programmed one byte at a time by supplying the address and data together with
the appropriate Write instruction. An EEPROM memory location is first automatically erased before new
data is written. If polling (RDY/BSY) is not used, the user must wait at least tWD_EEPROM before issuing the
next byte. (See Table 20-11.) In a chip erased device, no 0xFFs in the data file(s) need to be programmed.
B: The EEPROM array is programmed one page at a time. The Memory page is loaded one byte at a time
by supplying the 2 LSB of the address and data together with the Load EEPROM Memory Page instruction.
The EEPROM Memory Page is stored by loading the Write EEPROM Memory Page Instruction with
the 6 MSB of the address. When using EEPROM page access only byte locations loaded with the Load
EEPROM Memory Page instruction is altered. The remaining locations remain unchanged. If polling
(RDY/BSY) is not used, the used must wait at least tWD_EEPROM before issuing the next page (See Table
20-9). In a chip erased device, no 0xFF in the data file(s) need to be programmed.
6. Any memory location can be verified by using the Read instruction which returns the content at the
selected address at serial output MISO.
7. At the end of the programming session, RESET can be set high to commence normal operation.
8. Power-off sequence (if needed):
Set RESET to “1”.
Turn VCC power off.ATtiny25/45/85 [DATASHEET] 153
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20.5.2 Serial Programming Instruction set
Table 20-12 on page 153 and Figure 20-2 on page 154 describes the Instruction set.
Notes: 1. Not all instructions are applicable for all parts.
Table 20-11. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
Symbol Minimum Wait Delay
tWD_FLASH 4.5 ms
tWD_EEPROM 4.0 ms
tWD_ERASE 9.0 ms
tWD_FUSE 4.5 ms
Table 20-12. Serial Programming Instruction Set
Instruction/Operation
Instruction Format
Byte 1 Byte 2 Byte 3 Byte4
Programming Enable $AC $53 $00 $00
Chip Erase (Program Memory/EEPROM) $AC $80 $00 $00
Poll RDY/BSY $F0 $00 $00 data byte out
Load Instructions
Load Extended Address byte(1) $4D $00 Extended adr $00
Load Program Memory Page, High byte $48 adr MSB adr LSB high data byte in
Load Program Memory Page, Low byte $40 adr MSB adr LSB low data byte in
Load EEPROM Memory Page (page access) $C1 $00 0000 000aa data byte in
Read Instructions
Read Program Memory, High byte $28 adr MSB adr LSB high data byte out
Read Program Memory, Low byte $20 adr MSB adr LSB low data byte out
Read EEPROM Memory $A0 $00 00aa aaaa data byte out
Read Lock bits $58 $00 $00 data byte out
Read Signature Byte $30 $00 0000 000aa data byte out
Read Fuse bits $50 $00 $00 data byte out
Read Fuse High bits $58 $08 $00 data byte out
Read Extended Fuse Bits $50 $08 $00 data byte out
Read Calibration Byte $38 $00 $00 data byte out
Write Instructions(6)
Write Program Memory Page $4C adr MSB adr LSB $00
Write EEPROM Memory $C0 $00 00aa aaaa data byte in
Write EEPROM Memory Page (page access) $C2 $00 00aa aa00 $00
Write Lock bits $AC $E0 $00 data byte in
Write Fuse bits $AC $A0 $00 data byte in
Write Fuse High bits $AC $A8 $00 data byte in
Write Extended Fuse Bits $AC $A4 $00 data byte inATtiny25/45/85 [DATASHEET] 154
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2. a = address
3. Bits are programmed ‘0’, unprogrammed ‘1’.
4. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) .
5. Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size.
6. Instructions accessing program memory use a word address. This address may be random within the page range.
7. See htt://www.atmel.com/avr for Application Notes regarding programming and programmers.
If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until this bit returns ‘0’
before the next instruction is carried out.
Within the same page, the low data byte must be loaded prior to the high data byte.
After data is loaded to the page buffer, program the EEPROM page, see Figure 20-2 on page 154.
Figure 20-2. Serial Programming Instruction example
Byte 1 Byte 2 Byte 3 Byte 4
Adr MSB Adr LSB
Bit 15 B 0
Serial Programming Instruction
Program Memory/
EEPROM Memory
Page 0
Page 1
Page 2
Page N-1
Page Buffer
Write Program Memory Page/
Write EEPROM Memory Page
Load Program Memory Page (High/Low Byte)/
Load EEPROM Memory Page (page access)
Byte 1 Byte 2 Byte 3 Byte 4
Bit 15 B 0
Adr MSB Adr LSB
Page Offset
Page Number
Adr MSB Adr LSBATtiny25/45/85 [DATASHEET] 155
2586Q–AVR–08/2013
20.6 High-voltage Serial Programming
This section describes how to program and verify Flash Program memory, EEPROM Data memory, Lock bits and
Fuse bits in the ATtiny25/45/85.
Figure 20-3. High-voltage Serial Programming
The minimum period for the Serial Clock Input (SCI) during High-voltage Serial Programming is 220 ns.
20.7 High-voltage Serial Programming Algorithm
To program and verify the ATtiny25/45/85 in the High-voltage Serial Programming mode, the following sequence is
recommended (See instruction formats in Table 20-16):
Table 20-13. Pin Name Mapping
Signal Name in High-voltage
Serial Programming Mode Pin Name I/O Function
SDI PB0 I Serial Data Input
SII PB1 I Serial Instruction Input
SDO PB2 O Serial Data Output
SCI PB3 I Serial Clock Input (min. 220ns period)
Table 20-14. Pin Values Used to Enter Programming Mode
Pin Symbol Value
SDI Prog_enable[0] 0
SII Prog_enable[1] 0
SDO Prog_enable[2] 0
VCC
GND
SDO
SII
SDI
(RESET)
+4.5 - 5.5V
PB0
PB1
PB2
PB5
+11.5 - 12.5V
SCI PB3ATtiny25/45/85 [DATASHEET] 156
2586Q–AVR–08/2013
20.7.1 Enter High-voltage Serial Programming Mode
The following algorithm puts the device in High-voltage Serial Programming mode:
1. Set Prog_enable pins listed in Table 20-14 to “000”, RESET pin and VCC to 0V.
2. Apply 4.5 - 5.5V between VCC and GND. Ensure that VCC reaches at least 1.8V within the next 20 µs.
3. Wait 20 - 60 µs, and apply 11.5 - 12.5V to RESET.
4. Keep the Prog_enable pins unchanged for at least 10 µs after the High-voltage has been applied to
ensure the Prog_enable Signature has been latched.
5. Release the Prog_enable[2] pin to avoid drive contention on the Prog_enable[2]/SDO pin.
6. Wait at least 300 µs before giving any serial instructions on SDI/SII.
7. Exit Programming mode by power the device down or by bringing RESET pin to 0V.
If the rise time of the VCC is unable to fulfill the requirements listed above, the following alternative algorithm can be
used:
1. Set Prog_enable pins listed in Table 20-14 to “000”, RESET pin and VCC to 0V.
2. Apply 4.5 - 5.5V between VCC and GND.
3. Monitor VCC, and as soon as VCC reaches 0.9 - 1.1V, apply 11.5 - 12.5V to RESET.
4. Keep the Prog_enable pins unchanged for at least 10 µs after the High-voltage has been applied to
ensure the Prog_enable Signature has been latched.
5. Release the Prog_enable[2] pin to avoid drive contention on the Prog_enable[2]/SDO pin.
6. Wait until VCC actually reaches 4.5 - 5.5V before giving any serial instructions on SDI/SII.
7. Exit Programming mode by power the device down or by bringing RESET pin to 0V.
20.7.2 Considerations for Efficient Programming
The loaded command and address are retained in the device during programming. For efficient programming, the
following should be considered.
• The command needs only be loaded once when writing or reading multiple memory locations.
• Skip writing the data value 0xFF that is the contents of the entire EEPROM (unless the EESAVE Fuse is
programmed) and Flash after a Chip Erase.
• Address High byte needs only be loaded before programming or reading a new 256 word window in Flash or
256 byte EEPROM. This consideration also applies to Signature bytes reading.
20.7.3 Chip Erase
The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock bits are not reset until the
Program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed
before the Flash and/or EEPROM are re-programmed.
Note: 1. The EEPROM memory is preserved during Chip Erase if the EESAVE Fuse is programmed.
Table 20-15. High-voltage Reset Characteristics
Supply Voltage RESET Pin High-voltage Threshold
Minimum High-voltage Period for
Latching Prog_enable
VCC VHVRST tHVRST
4.5V 11.5V 100 ns
5.5V 11.5V 100 nsATtiny25/45/85 [DATASHEET] 157
2586Q–AVR–08/2013
1. Load command “Chip Erase” (see Table 20-16).
2. Wait after Instr. 3 until SDO goes high for the “Chip Erase” cycle to finish.
3. Load Command “No Operation”.
20.7.4 Programming the Flash
The Flash is organized in pages, see Table 20-12 on page 153. When programming the Flash, the program data is
latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following
procedure describes how to program the entire Flash memory:
1. Load Command “Write Flash” (see Table 20-16).
2. Load Flash Page Buffer.
3. Load Flash High Address and Program Page. Wait after Instr. 3 until SDO goes high for the “Page Programming”
cycle to finish.
4. Repeat 2 through 3 until the entire Flash is programmed or until all data has been programmed.
5. End Page Programming by Loading Command “No Operation”.
When writing or reading serial data to the ATtiny25/45/85, data is clocked on the rising edge of the serial clock, see
Figure 20-5, Figure 21-6 and Table 21-12 for details.
Figure 20-4. Addressing the Flash which is Organized in Pages
Figure 20-5. High-voltage Serial Programming Waveforms
PROGRAM MEMORY
WORD ADDRESS
WITHIN A PAGE
PAGE ADDRESS
WITHIN THE FLASH
INSTRUCTION WORD
PAGE PCWORD[PAGEMSB:0]:
00
01
02
PAGEEND
PAGE
PCPAGE PCWORD
PCMSB PAGEMSB
PROGRAM
COUNTER
MSB
MSB
MSB LSB
LSB
LSB
0 1 2 3 4 5 6 7 8 9 10
SDI
PB0
SII
PB1
SDO
PB2
SCI
PB3ATtiny25/45/85 [DATASHEET] 158
2586Q–AVR–08/2013
20.7.5 Programming the EEPROM
The EEPROM is organized in pages, see Table 21-11 on page 170. When programming the EEPROM, the data is
latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm
for the EEPROM Data memory is as follows (refer to Table 20-16):
1. Load Command “Write EEPROM”.
2. Load EEPROM Page Buffer.
3. Program EEPROM Page. Wait after Instr. 2 until SDO goes high for the “Page Programming” cycle to
finish.
4. Repeat 2 through 3 until the entire EEPROM is programmed or until all data has been programmed.
5. End Page Programming by Loading Command “No Operation”.
20.7.6 Reading the Flash
The algorithm for reading the Flash memory is as follows (refer to Table 20-16):
1. Load Command "Read Flash".
2. Read Flash Low and High Bytes. The contents at the selected address are available at serial output SDO.
20.7.7 Reading the EEPROM
The algorithm for reading the EEPROM memory is as follows (refer to Table 20-16):
1. Load Command “Read EEPROM”.
2. Read EEPROM Byte. The contents at the selected address are available at serial output SDO.
20.7.8 Programming and Reading the Fuse and Lock Bits
The algorithms for programming and reading the Fuse Low/High bits and Lock bits are shown in Table 20-16.
20.7.9 Reading the Signature Bytes and Calibration Byte
The algorithms for reading the Signature bytes and Calibration byte are shown in Table 20-16.
20.7.10 Power-off sequence
Set SCI to “0”. Set RESET to “1”. Turn VCC power off.
Table 20-16. High-voltage Serial Programming Instruction Set for ATtiny25/45/85
Instruction
Instruction Format
Instr.1/5 Instr.2/6 Instr.3 Instr.4 Operation Remarks
Chip Erase
SDI
SII
SDO
0_1000_0000_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_0100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
x_xxxx_xxxx_xx
Wait after Instr.3 until SDO
goes high for the Chip Erase
cycle to finish.
Load “Write
Flash”
Command
SDI
SII
SDO
0_0001_0000_00
0_0100_1100_00
x_xxxx_xxxx_xx
Enter Flash Programming
code.
Load Flash
Page Buffer
SDI
SII
SDO
0_bbbb_bbbb _00
0_0000_1100_00
x_xxxx_xxxx_xx
0_eeee_eeee_00
0_0010_1100_00
x_xxxx_xxxx_xx
0_dddd_dddd_00
0_0011_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0111_1101_00
x_xxxx_xxxx_xx
Repeat after Instr. 1 - 5 until
the entire page buffer is filled
or until all data within the
page is filled.(2)
SDI
SII
SDO
0_0000_0000_00
0_0111_1100_00
x_xxxx_xxxx_xx
Instr 5.ATtiny25/45/85 [DATASHEET] 159
2586Q–AVR–08/2013
Load Flash
High Address
and Program
Page
SDI
SII
SDO
0_0000_000a_00
0_0001_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_0100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
x_xxxx_xxxx_xx
Wait after Instr 3 until SDO
goes high. Repeat Instr. 2 - 3
for each loaded Flash Page
until the entire Flash or all
data is programmed. Repeat
Instr. 1 for a new 256 byte
page.(2)
Load “Read
Flash”
Command
SDI
SII
SDO
0_0000_0010_00
0_0100_1100_00
x_xxxx_xxxx_xx
Enter Flash Read mode.
Read Flash
Low and High
Bytes
SDI
SII
SDO
0_bbbb_bbbb_00
0_0000_1100_00
x_xxxx_xxxx_xx
0_0000_000a_00
0_0001_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1000_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
q_qqqq_qqqx_xx
Repeat Instr. 1, 3 - 6 for each
new address. Repeat Instr. 2
for a new 256 byte page.
SDI
SII
SDO
0_0000_0000_00
0_0111_1000_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0111_1100_00
p_pppp_pppx_xx
Instr 5 - 6.
Load “Write
EEPROM”
Command
SDI
SII
SDO
0_0001_0001_00
0_0100_1100_00
x_xxxx_xxxx_xx
Enter EEPROM Programming
mode.
Load
EEPROM
Page Buffer
SDI
SII
SDO
0_00bb_bbbb_00
0_0000_1100_00
x_xxxx_xxxx_xx
0_aaaa_aaaa_00
0_0001_1100_00
x_xxxx_xxxx_xx
0_eeee_eeee_00
0_0010_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1101_00
x_xxxx_xxxx_xx
Repeat Instr. 1 - 5 until the
entire page buffer is filled or
until all data within the page is
filled.(3)
SDI
SII
SDO
0_0000_0000_00
0_0110_1100_00
x_xxxx_xxxx_xx
Instr. 5
Program
EEPROM
Page
SDI
SII
SDO
0_0000_0000_00
0_0110_0100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
x_xxxx_xxxx_xx
Wait after Instr. 2 until SDO
goes high. Repeat Instr. 1 - 2
for each loaded EEPROM
page until the entire
EEPROM or all data is
programmed.
Write
EEPROM
Byte
SDI
SII
SDO
0_bbbb_bbbb_00
0_0000_1100_00
x_xxxx_xxxx_xx
0_aaaa_aaaa_00
0_0001_1100_00
x_xxxx_xxxx_xx
0_eeee_eeee_00
0_0010_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1101_00
x_xxxx_xxxx_xx
Repeat Instr. 1 - 6 for each
new address. Wait after Instr.
6 until SDO goes high.(4)
SDI
SII
SDO
0_0000_0000_00
0_0110_0100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
x_xxxx_xxxx_xx
Instr. 6
Load “Read
EEPROM”
Command
SDI
SII
SDO
0_0000_0011_00
0_0100_1100_00
x_xxxx_xxxx_xx
Enter EEPROM Read mode.
Read
EEPROM
Byte
SDI
SII
SDO
0_bbbb_bbbb_00
0_0000_1100_00
x_xxxx_xxxx_xx
0_aaaa_aaaa_00
0_0001_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1000_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
q_qqqq_qqq0_00
Repeat Instr. 1, 3 - 4 for each
new address. Repeat Instr. 2
for a new 256 byte page.
Write Fuse
Low Bits
SDI
SII
SDO
0_0100_0000_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_A987_6543_00
0_0010_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_0100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
x_xxxx_xxxx_xx
Wait after Instr. 4 until SDO
goes high. Write A - 3 = “0” to
program the Fuse bit.
Table 20-16. High-voltage Serial Programming Instruction Set for ATtiny25/45/85 (Continued)
Instruction
Instruction Format
Instr.1/5 Instr.2/6 Instr.3 Instr.4 Operation RemarksATtiny25/45/85 [DATASHEET] 160
2586Q–AVR–08/2013
Notes: 1. a = address high bits, b = address low bits, d = data in high bits, e = data in low bits, p = data out high bits, q = data out low
bits, x = don’t care, 1 = Lock Bit1, 2 = Lock Bit2, 3 = CKSEL0 Fuse, 4 = CKSEL1 Fuse, 5 = CKSEL2 Fuse, 6 = CKSEL3
Fuse, 7 = SUT0 Fuse, 8 = SUT1 Fuse, 9 = CKOUT Fuse, A = CKDIV8 Fuse, B = BODLEVEL0 Fuse, C = BODLEVEL1
Fuse, D = BODLEVEL2 Fuse, E = EESAVE Fuse, F = WDTON Fuse, G = SPIEN Fuse, H = DWEN Fuse, I = RSTDISBL
Fuse, J = SELFPRGEN Fuse
2. For page sizes less than 256 words, parts of the address (bbbb_bbbb) will be parts of the page address.
3. For page sizes less than 256 bytes, parts of the address (bbbb_bbbb) will be parts of the page address.
4. The EEPROM is written page-wise. But only the bytes that are loaded into the page are actually written to the EEPROM.
Page-wise EEPROM access is more efficient when multiple bytes are to be written to the same page. Note that auto-erase
of EEPROM is not available in High-voltage Serial Programming, only in SPI Programming.
Write Fuse
High Bits
SDI
SII
SDO
0_0100_0000_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_IHGF_EDCB_00
0_0010_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0111_0100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0111_1100_00
x_xxxx_xxxx_xx
Wait after Instr. 4 until SDO
goes high. Write I - B = “0” to
program the Fuse bit.
Write Fuse
Extended Bits
SDI
SII
SDO
0_0100_0000_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_0000_000J_00
0_0010_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_0110_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1110_00
x_xxxx_xxxx_xx
Wait after Instr. 4 until SDO
goes high. Write J = “0” to
program the Fuse bit.
Write Lock
Bits
SDI
SII
SDO
0_0010_0000_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_0000_0021_00
0_0010_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_0100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
x_xxxx_xxxx_xx
Wait after Instr. 4 until SDO
goes high. Write 2 - 1 = “0” to
program the Lock bit.
Read Fuse
Low Bits
SDI
SII
SDO
0_0000_0100_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1000_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
A_9876_543x_xx
Reading A - 3 = “0” means
the Fuse bit is programmed.
Read Fuse
High Bits
SDI
SII
SDO
0_0000_0100_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0111_1010_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0111_1110_00
I_HGFE_DCBx_xx
Reading I - B = “0” means the
Fuse bit is programmed.
Read Fuse
Extended Bits
SDI
SII
SDO
0_0000_0100_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1010_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1110_00
x_xxxx_xxJx_xx
Reading J = “0” means the
Fuse bit is programmed.
Read Lock
Bits
SDI
SII
SDO
0_0000_0100_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0111_1000_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0111_1100_00
x_xxxx_x21x_xx
Reading 2, 1 = “0” means the
Lock bit is programmed.
Read
Signature
Bytes
SDI
SII
SDO
0_0000_1000_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_0000_00bb_00
0_0000_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1000_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0110_1100_00
q_qqqq_qqqx_xx
Repeats Instr 2 4 for each
signature byte address.
Read
Calibration
Byte
SDI
SII
SDO
0_0000_1000_00
0_0100_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0000_1100_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0111_1000_00
x_xxxx_xxxx_xx
0_0000_0000_00
0_0111_1100_00
p_pppp_pppx_xx
Load “No
Operation”
Command
SDI
SII
SDO
0_0000_0000_00
0_0100_1100_00
x_xxxx_xxxx_xx
Table 20-16. High-voltage Serial Programming Instruction Set for ATtiny25/45/85 (Continued)
Instruction
Instruction Format
Instr.1/5 Instr.2/6 Instr.3 Instr.4 Operation RemarksATtiny25/45/85 [DATASHEET] 161
2586Q–AVR–08/2013
21. Electrical Characteristics
21.1 Absolute Maximum Ratings*
21.2 DC Characteristics
Operating Temperature.................................. -55C to +125C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature ..................................... -65°C to +150°C
Voltage on any Pin except RESET
with respect to Ground ................................-0.5V to VCC+0.5V
Voltage on RESET with respect to Ground......-0.5V to +13.0V
Maximum Operating Voltage ............................................ 6.0V
DC Current per I/O Pin ............................................... 40.0 mA
DC Current VCC and GND Pins................................ 200.0 mA
Table 21-1. DC Characteristics. TA = -40C to +85C
Symbol Parameter Condition Min. Typ.(1) Max. Units
VIL
Input Low-voltage, except
XTAL1 and RESET pin
VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V
-0.5
-0.5
0.2VCC(3)
0.3VCC(3)
V
V
VIH
Input High-voltage, except
XTAL1 and RESET pin
VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V
0.7VCC(2)
0.6VCC(2)
VCC +0.5
VCC +0.5
V
V
VIL1
Input Low-voltage, XTAL1 pin,
External Clock Selected VCC = 1.8V - 5.5V -0.5 0.1VCC(3) V
VIH1
Input High-voltage, XTAL1 pin,
External Clock Selected
VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V
0.8VCC(2)
0.7VCC(2)
VCC +0.5
VCC +0.5
V
V
VIL2
Input Low-voltage,
RESET pin VCC = 1.8V - 5.5V -0.5 0.2VCC(3) V
V
VIH2
Input High-voltage,
RESET pin VCC = 1.8V - 5.5V 0.9VCC(2) VCC +0.5 V
VIL3
Input Low-voltage,
RESET pin as I/O
VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V
-0.5
-0.5
0.2VCC(3)
0.3VCC(3)
V
V
VIH3
Input High-voltage,
RESET pin as I/O
VCC = 1.8V - 2.4V
VCC = 2.4V - 5.5V
0.7VCC(2)
0.6VCC(2)
VCC +0.5
VCC +0.5
V
V
VOL
Output Low-voltage,(4)
Port B (except RESET) (6)
IOL = 10 mA, VCC = 5V
IOL = 5 mA, VCC = 3V
0.6
0.5
V
V
VOH
Output High-voltage, (5)
Port B (except RESET) (6)
IOH = -10 mA, VCC = 5V
IOH = -5 mA, VCC = 3V
4.3
2.5
V
V
IIL
Input Leakage
Current I/O Pin
VCC = 5.5V, pin low
(absolute value) < 0.05 1 µA
IIH
Input Leakage
Current I/O Pin
VCC = 5.5V, pin high
(absolute value) < 0.05 1 µA
RRST Reset Pull-up Resistor VCC = 5.5V, input low 30 60 kATtiny25/45/85 [DATASHEET] 162
2586Q–AVR–08/2013
Notes: 1. Typical values at 25C.
2. “Min” means the lowest value where the pin is guaranteed to be read as high.
3. “Max” means the highest value where the pin is guaranteed to be read as low.
4. Although each I/O port can sink more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state
conditions (non-transient), the following must be observed:
1] The sum of all IOL, for all ports, should not exceed 60 mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test condition.
5. Although each I/O port can source more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state
conditions (non-transient), the following must be observed:
1] The sum of all IOH, for all ports, should not exceed 60 mA.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current
greater than the listed test condition.
6. The RESET pin must tolerate high voltages when entering and operating in programming modes and, as a consequence,
has a weak drive strength as compared to regular I/O pins. See Figure 22-23, Figure 22-24, Figure 22-25, and Figure 22-26
(starting on page 184).
7. Values are with external clock using methods described in “Minimizing Power Consumption” on page 36. Power Reduction
is enabled (PRR = 0xFF) and there is no I/O drive.
8. Brown-Out Detection (BOD) disabled.
Rpu I/O Pin Pull-up Resistor VCC = 5.5V, input low 20 50 k
ICC
Power Supply Current (7)
Active 1 MHz, VCC = 2V 0.3 0.55 mA
Active 4 MHz, VCC = 3V 1.5 2.5 mA
Active 8 MHz, VCC = 5V 5 8 mA
Idle 1 MHz, VCC = 2V 0.1 0.2 mA
Idle 4 MHz, VCC = 3V 0.35 0.6 mA
Idle 8 MHz, VCC = 5V 1.2 2 mA
Power-down mode (8) WDT enabled, VCC = 3V 10 µA
WDT disabled, VCC = 3V 2 µA
Table 21-1. DC Characteristics. TA = -40C to +85C (Continued)
Symbol Parameter Condition Min. Typ.(1) Max. UnitsATtiny25/45/85 [DATASHEET] 163
2586Q–AVR–08/2013
21.3 Speed
Figure 21-1. Maximum Frequency vs. VCC
Figure 21-2. Maximum Frequency vs. VCC
10 MHz
4 MHz
1.8V 2.7V 5.5V
Safe Operating Area
20 MHz
10 MHz
2.7V 4.5V 5.5V
Safe Operating AreaATtiny25/45/85 [DATASHEET] 164
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21.4 Clock Characteristics
21.4.1 Calibrated Internal RC Oscillator Accuracy
It is possible to manually calibrate the internal oscillator to be more accurate than default factory calibration. Please
note that the oscillator frequency depends on temperature and voltage. Voltage and temperature characteristics
can be found in Figure 22-40 on page 193 and Figure 22-41 on page 193.
Notes: 1. Accuracy of oscillator frequency at calibration point (fixed temperature and fixed voltage).
2. ATtiny25/V, only: 6.4 MHz in ATtiny15 Compatibility Mode.
3. Voltage range for ATtiny25V/45V/85V.
4. Voltage range for ATtiny25/45/85.
21.4.2 External Clock Drive
Figure 21-3. External Clock Drive Waveforms
Table 21-2. Calibration Accuracy of Internal RC Oscillator
Calibration
Method Target Frequency VCC Temperature
Accuracy at given Voltage
& Temperature (1)
Factory
Calibration 8.0 MHz (2) 3V 25C ±10%
User
Calibration
Fixed frequency within:
6 – 8 MHz
Fixed voltage within:
1.8V - 5.5V (3)
2.7V - 5.5V (4)
Fixed temperature
within:
-40C to +85C
±1%
VIL1
VIH1
Table 21-3. External Clock Drive Characteristics
Symbol Parameter
VCC = 1.8 - 5.5V VCC = 2.7 - 5.5V VCC = 4.5 - 5.5V
Min. Max. Min. Max. Min. Max. Units
1/tCLCL Clock Frequency 0 4 0 10 0 20 MHz
tCLCL Clock Period 250 100 50 ns
tCHCX High Time 100 40 20 ns
tCLCX Low Time 100 40 20 ns
tCLCH Rise Time 2.0 1.6 0.5 µs
tCHCL Fall Time 2.0 1.6 0.5 µs
t
CLCL Change in period from one clock cycle to the next 2 2 2 %ATtiny25/45/85 [DATASHEET] 165
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21.5 System and Reset Characteristics
Note: 1. Values are guidelines only.
Two versions of power-on reset have been implemented, as follows.
21.5.1 Standard Power-On Reset
This implementation of power-on reset existed in early versions of ATtiny25/45/85. The table below describes the
characteristics of this power-on reset and it is valid for the following devices, only:
• ATtiny25, revision D, and older
• ATtiny45, revision F, and older
• ATtiny85, revision B, and newer
Note: Revisions are marked on the package (packages 8P3 and 8S2: bottom, package 20M1: top)
Note: 1. Values are guidelines, only
2. Threshold where device is released from reset when voltage is rising
3. The power-on reset will not work unless the supply voltage has been below VPOA
21.5.2 Enhanced Power-On Reset
This implementation of power-on reset exists in newer versions of ATtiny25/45/85. The table below describes the
characteristics of this power-on reset and it is valid for the following devices, only:
• ATtiny25, revision E, and newer
Table 21-4. Reset, Brown-out and Internal Voltage Characteristics
Symbol Parameter Condition Min(1) Typ(1) Max(1) Units
VRST RESET Pin Threshold Voltage VCC = 3V 0.2 VCC 0.9 VCC V
tRST
Minimum pulse width on
RESET Pin VCC = 3V 2.5 µs
VHYST Brown-out Detector Hysteresis 50 mV
tBOD
Min Pulse Width on
Brown-out Reset 2 µs
VBG
Bandgap reference
voltage
VCC = 5.5V
TA = 25°C 1.0 1.1 1.2 V
tBG
Bandgap reference
start-up time
VCC = 2.7V
TA = 25°C 40 70 µs
IBG
Bandgap reference
current consumption
VCC = 2.7V
TA = 25°C 15 µA
Table 21-5. Characteristics of Standard Power-On Reset. TA = -40 to +85C
Symbol Parameter Min(1) Typ(1) Max(1) Units
VPOR Release threshold of power-on reset (2) 0.7 1.0 1.4 V
VPOA Activation threshold of power-on reset (3) 0.05 0.9 1.3 V
SRON Power-on slope rate 0.01 4.5 V/msATtiny25/45/85 [DATASHEET] 166
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• ATtiny45, revision G, and newer
• ATtiny85, revision C, and newer
Note: 1. Values are guidelines, only
2. Threshold where device is released from reset when voltage is rising
3. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling)
21.6 Brown-Out Detection
Note: 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the
device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-out Reset will occur
before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed.
Table 21-6. Characteristics of Enhanced Power-On Reset. TA = -40C to +85C
Symbol Parameter Min(1) Typ(1) Max(1) Units
VPOR Release threshold of power-on reset (2) 1.1 1.4 1.6 V
VPOA Activation threshold of power-on reset (3) 0.6 1.3 1.6 V
SRON Power-On Slope Rate 0.01 V/ms
Table 21-7. BODLEVEL Fuse Coding. TA = -40C to +85C
BODLEVEL[2:0] Fuses Min(1) Typ(1) Max(1) Units
111 BOD Disabled
110 1.7 1.8 2.0
101 2.5 2.7 2.9 V
100 4.1 4.3 4.5
0XX ReservedATtiny25/45/85 [DATASHEET] 167
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21.7 ADC Characteristics
Note: 1. Values are guidelines only.
Table 21-8. ADC Characteristics, Single Ended Channels. TA = -40C to +85C
Symbol Parameter Condition Min Typ Max Units
Resolution 10 Bits
Absolute accuracy
(Including INL, DNL, and
Quantization, Gain and
Offset errors)
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz 2 LSB
VREF = 4V, VCC = 4V,
ADC clock = 1 MHz 3 LSB
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz
Noise Reduction Mode
1.5 LSB
VREF = 4V, VCC = 4V,
ADC clock = 1 MHz
Noise Reduction Mode
2.5 LSB
Integral Non-linearity (INL)
(Accuracy after offset and gain
calibration)
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz 1 LSB
Differential Non-linearity (DNL) VREF = 4V, VCC = 4V,
ADC clock = 200 kHz 0.5 LSB
Gain Error VREF = 4V, VCC = 4V,
ADC clock = 200 kHz 2.5 LSB
Offset Error VREF = 4V, VCC = 4V,
ADC clock = 200 kHz 1.5 LSB
Conversion Time Free Running Conversion 14 280 µs
Clock Frequency 50 1000 kHz
VIN Input Voltage GND VREF V
Input Bandwidth 38.4 kHz
AREF External Reference Voltage 2.0 VCC V
VINT
Internal Voltage Reference 1.0 1.1 1.2 V
Internal 2.56V Reference (1) VCC > 3.0V 2.3 2.56 2.8 V
RREF 32 k
RAIN Analog Input Resistance 100 M
ADC Output 0 1023 LSBATtiny25/45/85 [DATASHEET] 168
2586Q–AVR–08/2013
Note: 1. Values are guidelines only.
Table 21-9. ADC Characteristics, Differential Channels (Unipolar Mode). TA = -40C to +85C
Symbol Parameter Condition Min Typ Max Units
Resolution
Gain = 1x 10 Bits
Gain = 20x 10 Bits
Absolute accuracy
(Including INL, DNL, and
Quantization, Gain and Offset
Errors)
Gain = 1x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz
10.0 LSB
Gain = 20x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz
20.0 LSB
Integral Non-Linearity (INL)
(Accuracy after Offset and
Gain Calibration)
Gain = 1x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz
4.0 LSB
Gain = 20x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz
10.0 LSB
Gain Error
Gain = 1x 10.0 LSB
Gain = 20x 15.0 LSB
Offset Error
Gain = 1x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz
3.0 LSB
Gain = 20x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz
4.0 LSB
Conversion Time Free Running Conversion 70 280 µs
Clock Frequency 50 200 kHz
VIN Input Voltage GND VCC V
VDIFF Input Differential Voltage VREF/Gain V
Input Bandwidth 4 kHz
AREF External Reference Voltage 2.0 VCC - 1.0 V
VINT
Internal Voltage Reference 1.0 1.1 1.2 V
Internal 2.56V Reference (1) VCC > 3.0V 2.3 2.56 2.8 V
RREF Reference Input Resistance 32 k
RAIN Analog Input Resistance 100 M
ADC Conversion Output 0 1023 LSBATtiny25/45/85 [DATASHEET] 169
2586Q–AVR–08/2013
Note: 1. Values are guidelines only.
Table 21-10. ADC Characteristics, Differential Channels (Bipolar Mode). TA = -40C to +85C
Symbol Parameter Condition Min Typ Max Units
Resolution
Gain = 1x 10 Bits
Gain = 20x 10 Bits
Absolute accuracy
(Including INL, DNL, and
Quantization, Gain and Offset
Errors)
Gain = 1x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz
8.0 LSB
Gain = 20x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz
8.0 LSB
Integral Non-Linearity (INL)
(Accuracy after Offset and
Gain Calibration)
Gain = 1x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz
4.0 LSB
Gain = 20x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz
5.0 LSB
Gain Error
Gain = 1x 4.0 LSB
Gain = 20x 5.0 LSB
Offset Error
Gain = 1x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz
3.0 LSB
Gain = 20x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz
4.0 LSB
Conversion Time Free Running Conversion 70 280 µs
Clock Frequency 50 200 kHz
VIN Input Voltage GND VCC V
VDIFF Input Differential Voltage VREF/Gain V
Input Bandwidth 4 kHz
AREF External Reference Voltage 2.0 VCC - 1.0 V
VINT
Internal Voltage Reference 1.0 1.1 1.2 V
Internal 2.56V Reference (1) VCC > 3.0V 2.3 2.56 2.8 V
RREF Reference Input Resistance 32 k
RAIN Analog Input Resistance 100 M
ADC Conversion Output -512 511 LSBATtiny25/45/85 [DATASHEET] 170
2586Q–AVR–08/2013
21.8 Serial Programming Characteristics
Figure 21-4. Serial Programming Waveforms
Figure 21-5. Serial Programming Timing
Note: 1. 2 tCLCL for fck < 12 MHz, 3 tCLCL for fck >= 12 MHz
Table 21-11. Serial Programming Characteristics, TA = -40C to +85C, VCC = 1.8 - 5.5V (Unless Otherwise
Noted)
Symbol Parameter Min Typ Max Units
1/tCLCL Oscillator Frequency (VCC = 1.8 - 5.5V) 0 4 MHz
tCLCL Oscillator Period (VCC = 1.8 - 5.5V) 250 ns
1/tCLCL Oscillator Frequency (VCC = 2.7 - 5.5V) 0 10 MHz
t
CLCL Oscillator Period (VCC = 2.7 - 5.5V) 100 ns
1/tCLCL Oscillator Frequency (VCC = 4.5V - 5.5V) 0 20 MHz
t
CLCL Oscillator Period (VCC = 4.5V - 5.5V) 50 ns
t
SHSL SCK Pulse Width High 2 tCLCL* ns
t
SLSH SCK Pulse Width Low 2 tCLCL* ns
t
OVSH MOSI Setup to SCK High tCLCL ns
t
SHOX MOSI Hold after SCK High 2 tCLCL ns
tSLIV SCK Low to MISO Valid 100 ns
MSB
MSB
LSB
LSB
SERIAL CLOCK INPUT
(SCK)
SERIAL DATA INPUT
(MOSI)
(MISO)
SAMPLE
SERIAL DATA OUTPUT
MOSI
MISO
SCK
t
OVSH
t
SHSL
t t
SHOX SLSH
t
SLIVATtiny25/45/85 [DATASHEET] 171
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21.9 High-voltage Serial Programming Characteristics
Figure 21-6. High-voltage Serial Programming Timing
Table 21-12. High-voltage Serial Programming Characteristics TA = 25C ± 10%, VCC = 5.0V ± 10% (Unless otherwise
noted)
Symbol Parameter Min Typ Max Units
tSHSL SCI (PB3) Pulse Width High 125 ns
tSLSH SCI (PB3) Pulse Width Low 125 ns
tIVSH SDI (PB0), SII (PB1) Valid to SCI (PB3) High 50 ns
t
SHIX SDI (PB0), SII (PB1) Hold after SCI (PB3) High 50 ns
t
SHOV SCI (PB3) High to SDO (PB2) Valid 16 ns
tWLWH_PFB Wait after Instr. 3 for Write Fuse Bits 2.5 ms
SDI (PB0), SII (PB1)
SDO (PB2)
SCI (PB3)
t
IVSH
t
SHSL
t t
SHIX SLSH
t
SHOVATtiny25/45/85 [DATASHEET] 172
2586Q–AVR–08/2013
22. Typical Characteristics
The data contained in this section is largely based on simulations and characterization of similar devices in the
same process and design methods. Thus, the data should be treated as indications of how the part will behave.
The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption
measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A
sine wave generator with rail-to-rail output is used as clock source.
The power consumption in Power-down mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of
I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating
voltage and frequency.
The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where CL = load capacitance,
VCC = operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at
frequencies higher than the ordering code indicates.
The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down
mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer.
22.1 Active Supply Current
Figure 22-1. Active Supply Current vs. Low frequency (0.1 - 1.0 MHz)
ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY
0.1 -1.0 MHz
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0
0,2
0,4
0,6
0,8
1
1,2
0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1
Frequency (MHz)
ICC (mA)ATtiny25/45/85 [DATASHEET] 173
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Figure 22-2. Active Supply Current vs. Frequency (1 - 20 MHz)
Figure 22-3. Active Supply Current vs. VCC (Internal RC oscillator, 8 MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY
1 - 20 MHz
5.5 V
5.0 V
4.5 V
0
2
4
6
8
10
12
14
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)
ICC (mA)
1.8V
2.7V
3.3V
4.0V
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 8 MHz
85 ˚C
25 ˚C
-40 ˚C
0
1
2
3
4
5
6
7
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (mA)ATtiny25/45/85 [DATASHEET] 174
2586Q–AVR–08/2013
Figure 22-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)
Figure 22-5. Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 1 MHz
85 ˚C
25 ˚C
-40 ˚C
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,6
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (mA)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 128 KHz
85 ˚C
25 ˚C
-40 ˚C
0
0,05
0,1
0,15
0,2
0,25
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (mA)ATtiny25/45/85 [DATASHEET] 175
2586Q–AVR–08/2013
22.2 Idle Supply Current
Figure 22-6. Idle Supply Current vs. low Frequency (0.1 - 1.0 MHz)
Figure 22-7. Idle Supply Current vs. Frequency (1 - 20 MHz)
IDLE SUPPLY CURRENT vs. LOW FREQUENCY
0.1 - 1.0 MHz
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0
0,05
0,1
0,15
0,2
0,25
0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1
Frequency (MHz)
ICC (mA)
IDLE SUPPLY CURRENT vs. FREQUENCY
1 - 20 MHz
5.5 V
5.0 V
4.5 V
0
0,5
1
1,5
2
2,5
3
3,5
4
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)
ICC (mA)
1.8V
2.7V
3.3V
4.0VATtiny25/45/85 [DATASHEET] 176
2586Q–AVR–08/2013
Figure 22-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)I
Figure 22-9. Idle Supply Current vs. VCC (Internal RC Oscilllator, 1 MHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 8 MHz
85 ˚C
25 ˚C
-40 ˚C
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,6
1,8
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (mA)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 1 MHz
85 ˚C
25 ˚C
-40 ˚C
0
0,05
0,1
0,15
0,2
0,25
0,3
0,35
0,4
0,45
0,5
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (mA)ATtiny25/45/85 [DATASHEET] 177
2586Q–AVR–08/2013
Figure 22-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz)
22.3 Supply Current of I/O modules
The tables and formulas below can be used to calculate the additional current consumption for the different I/O
modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled by the Power Reduction
Register. See “PRR – Power Reduction Register” on page 38 for details.
It is possible to calculate the typical current consumption based on the numbers from Table 22-2 for other VCC and
frequency settings that listed in Table 22-1.
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 128 kHz
85 ˚C
25 ˚C
-40 ˚C
0
0,01
0,02
0,03
0,04
0,05
0,06
0,07
0,08
0,09
0,1
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (mA)
Table 22-1. Additional Current Consumption for the different I/O modules (absolute values)
PRR bit Typical numbers
VCC = 2V, f = 1 MHz VCC = 3V, f = 4 MHz VCC = 5V, f = 8 MHz
PRTIM1 45 uA 300 uA 1100 uA
PRTIM0 5 uA 30 uA 110 uA
PRUSI 5 uA 25 uA 100 uA
PRADC 15 uA 85 uA 340 uA
Table 22-2. Additional Current Consumption (percentage) in Active and Idle mode
PRR bit
Additional Current consumption
compared to Active with external clock
(see Figure 22-1 and Figure 22-2)
Additional Current consumption
compared to Idle with external clock
(see Figure 22-6 and Figure 22-7)
PRTIM1 20 % 80 %
PRTIM0 2 % 10 %
PRUSI 2 % 10 %
PRADC 5 % 25 %ATtiny25/45/85 [DATASHEET] 178
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22.3.1 Example
Calculate the expected current consumption in idle mode with USI, TIMER0, and ADC enabled at VCC = 2.0V and f
= 1 MHz. From Table 22-2 on page 177, third column, we see that we need to add 10% for the USI, 25% for the
ADC, and 10% for the TIMER0 module. Reading from Figure 22-9, we find that the idle current consumption is
~0,18 mA at VCC = 2.0V and f = 1 MHz. The total current consumption in idle mode with USI, TIMER0, and ADC
enabled, gives:
22.4 Power-down Supply Current
Figure 22-11. Power-down Supply Current vs. VCC (Watchdog Timer Disabled)
ICC = 0 18 , mA 1 01 ++ + , 0 25 , 0 1, 0 261 , mA
POWER-DOWN SUPPLY CURRENT vs. VCC
WATCHDOG TIMER DISABLED
85 ˚C
25 ˚C
-40 ˚C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (uA)ATtiny25/45/85 [DATASHEET] 179
2586Q–AVR–08/2013
Figure 22-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled)
22.5 Pin Pull-up
Figure 22-13. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V)
POWER-DOWN SUPPLY CURRENT vs. VCC
WATCHDOG TIMER ENABLED
85 ˚C
25 ˚C
-40 ˚C
0
2
4
6
8
10
12
14
1.5 2 2.5 3 3.5 4 4.5 5 5.5
VCC (V)
ICC (uA)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
VCC = 1.8V
85 ˚C
25 ˚C
0 -40 ˚C
10
20
30
40
50
60
0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
VOP (V)
IOP (uA)ATtiny25/45/85 [DATASHEET] 180
2586Q–AVR–08/2013
Figure 22-14. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)
Figure 22-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
VCC = 2.7V
85 ˚C
25 ˚C
-40 ˚C
0
10
20
30
40
50
60
70
80
0 0,5 1 1,5 2 2,5 3
VOP (V)
IOP (uA)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
VCC = 5V
85 ˚C
25 ˚C
-40 ˚C
0
20
40
60
80
100
120
140
160
0123456
VOP (V)
IOP (uA)ATtiny25/45/85 [DATASHEET] 181
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Figure 22-16. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V)
Figure 22-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
VCC = 1.8V
85 ˚C
25 ˚C
-40 ˚C
0
5
10
15
20
25
30
35
40
0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
VRESET (V)
IRESET (uA)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
VCC =2.7V
85 ˚C
25 ˚C
-40 ˚C
0
10
20
30
40
50
60
0 0,5 1 1,5 2 2,5 3
VRESET (V)
IRESET (uA)ATtiny25/45/85 [DATASHEET] 182
2586Q–AVR–08/2013
Figure 22-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
22.6 Pin Driver Strength
Figure 22-19. I/O Pin Output Voltage vs. Sink Current (VCC = 3V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
VCC = 5V
85 ˚C
25 ˚C
-40 ˚C
0
20
40
60
80
100
120
0123456
VRESET (V)
IRESET (uA)
I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT
VCC = 3V
85
25
-40
0
0,2
0,4
0,6
0,8
1
1,2
0 5 10 15 20 25
IOL (mA)
VOL (V)ATtiny25/45/85 [DATASHEET] 183
2586Q–AVR–08/2013
Figure 22-20. I/O Pin Output Voltage vs. Sink Current (VCC = 5V)
Figure 22-21. I/O Pin Output Voltage vs. Source Current (VCC = 3V)
I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT
VCC = 5V
85
25
-40
0
0,1
0,2
0,3
0,4
0,5
0,6
0 5 10 15 20 25
IOL (mA)
VOL (V)
I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT
VCC = 3V
85
25
-40
0
0,5
1
1,5
2
2,5
3
3,5
0 5 10 15 20 25
IOH (mA)
VOH (V)ATtiny25/45/85 [DATASHEET] 184
2586Q–AVR–08/2013
Figure 22-22. I/O Pin Output Voltage vs. Source Current (VCC = 5V)
Figure 22-23. Reset Pin Output Voltage vs. Sink Current (VCC = 3V)
I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT
VCC = 5V
85
25
-40
4,4
4,5
4,6
4,7
4,8
4,9
5
5,1
0 5 10 15 20 25
IOH (mA)
VOH (V)
RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT
VCC = 3V
-45 °C
0 °C
85 °C
0
0.5
1
1.5
0 0.5 1 1.5 2 2.5 3
IOL (mA)
VOL (V)ATtiny25/45/85 [DATASHEET] 185
2586Q–AVR–08/2013
Figure 22-24. Reset Pin Output Voltage vs. Sink Current (VCC = 5V)
Figure 22-25. Reset Pin Output Voltage vs. Source Current (VCC = 3V)
RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT
VCC = 5V
-45 °C
0 °C
85 °C
0
0.2
0.4
0.6
0.8
1
0 0.5 1 1.5 2 2.5 3
IOL (mA)
VOL (V)
RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT
VCC = 3V
-45 °C
25 °C
85 °C
0
0.5
1
1.5
2
2.5
3
3.5
0 0.5 1 1.5 2
IOH (mA)
VOH (V)ATtiny25/45/85 [DATASHEET] 186
2586Q–AVR–08/2013
Figure 22-26. Reset Pin Output Voltage vs. Source Current (VCC = 5V)
22.7 Pin Threshold and Hysteresis
Figure 22-27. I/O Pin Input Threshold Voltage vs. VCC (VIH, IO Pin Read as ‘1’)
RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT
VCC = 5V
-45 °C
25 °C
2.5 85 °C
3
3.5
4
4.5
5
0 0.5 1 1.5 2
IOH (mA)
VOH (V)
I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC
VIH, IO PIN READ AS '1'
85 ˚C
25 ˚C
-40 ˚C
0
0,5
1
1,5
2
2,5
3
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Threshold (V)ATtiny25/45/85 [DATASHEET] 187
2586Q–AVR–08/2013
Figure 22-28. I/O Pin Input Threshold Voltage vs. VCC (VIL, IO Pin Read as ‘0’)
Figure 22-29. I/O Pin Input Hysteresis vs. VCC
I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC
VIL, IO PIN READ AS '0'
85 ˚C
25 ˚C
-40 ˚C
0
0,5
1
1,5
2
2,5
3
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Threshold (V)
85 °C
25 °C
-40 °C
0
0,1
0,2
0,3
0,4
0,5
0,6
1,5 2 2,5 3 3,5 4 4,5 5 5,5
Input Hysteresis (V)
V CC (V)
I/O PIN INPUT HYSTERESIS vs. VCCATtiny25/45/85 [DATASHEET] 188
2586Q–AVR–08/2013
Figure 22-30. Reset Input Threshold Voltage vs. VCC (VIH, IO Pin Read as ‘1’)
Figure 22-31. Reset Input Threshold Voltage vs. VCC (VIL, IO Pin Read as ‘0’)
RESET INPUT THRESHOLD VOLTAGE vs. VCC
VIH, IO PIN READ AS '1'
85 °C
25 °C
-40 °C
0
0,5
1
1,5
2
2,5
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Threshold (V)
RESET INPUT THRESHOLD VOLTAGE vs. VCC
VIL, IO PIN READ AS '0'
85 °C
25 °C
-40 °C
0
0,5
1
1,5
2
2,5
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Threshold (V)ATtiny25/45/85 [DATASHEET] 189
2586Q–AVR–08/2013
Figure 22-32. Reset Pin Input Hysteresis vs. VCC
22.8 BOD Threshold
Figure 22-33. BOD Threshold vs. Temperature (BOD Level is 4.3V)
RESET PIN INPUT HYSTERESIS vs. VCC
85 °C
25 °C
-40 °C
0
0,05
0,1
0,15
0,2
0,25
0,3
0,35
0,4
0,45
0,5
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Input Hysteresis (V)
BOD THRESHOLDS vs. TEMPERATURE
Rising VCC
Falling VCC
4,26
4,28
4,3
4,32
4,34
4,36
4,38
4,4
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature (C)
Threshold (V)ATtiny25/45/85 [DATASHEET] 190
2586Q–AVR–08/2013
Figure 22-34. BOD Threshold vs. Temperature (BOD Level is 2.7V)
Figure 22-35. BOD Threshold vs. Temperature (BOD Level is 1.8V)
BOD THRESHOLDS vs. TEMPERATURE
Rising VCC
Falling VCC
2,68
2,7
2,72
2,74
2,76
2,78
2,8
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature (C)
Threshold (V)
BOD THRESHOLDS vs. TEMPERATURE
Rising VCC
Falling VCC
1,795
1,8
1,805
1,81
1,815
1,82
1,825
1,83
1,835
1,84
1,845
1,85
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature (C)
Threshold (V)ATtiny25/45/85 [DATASHEET] 191
2586Q–AVR–08/2013
Figure 22-36. Bandgap Voltage vs. Supply Voltage
Figure 22-37. Bandgap Voltage vs. Temperature
BANDGAP VOLTAGE vs. VCC
85 °C
25 °C
-40 °C
1
1,02
1,04
1,06
1,08
1,1
1,12
1,14
1,16
1,18
1,2
1,5 2 2,5 3 3,5 4 4,5 5 5,5
Vcc (V)
Bandgap Voltage (V)
BANDGAP VOLTAGE vs. Temperature
5 V
3 V
1.8 V
1
1,02
1,04
1,06
1,08
1,1
1,12
1,14
1,16
1,18
1,2
-40 -20 0 20 40 60 80 100
Temperature
Bandgap Voltage (V)ATtiny25/45/85 [DATASHEET] 192
2586Q–AVR–08/2013
22.9 Internal Oscillator Speed
Figure 22-38. Watchdog Oscillator Frequency vs. VCC
Figure 22-39. Watchdog Oscillator Frequency vs. Temperature
WATCHDOG OSCILLATOR FREQUENCY vs. VCC
85 ˚C
25 ˚C
-40 ˚C
0,112
0,114
0,116
0,118
0,12
0,122
0,124
0,126
0,128
2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
FRC (MHz)
WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE
5.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0,108
0,11
0,112
0,114
0,116
0,118
0,12
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature
FRC (MHz)ATtiny25/45/85 [DATASHEET] 193
2586Q–AVR–08/2013
Figure 22-40. Calibrated 8 MHz RC Oscillator Frequency vs. VCC
Figure 22-41. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature
CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. VCC
85 ˚C
25 ˚C
-40 ˚C
7,5
7,6
7,7
7,8
7,9
8
8,1
8,2
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
FRC (MHz)
CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
5.0 V
3.0 V
7,7
7,75
7,8
7,85
7,9
7,95
8
8,05
8,1
8,15
-60 -40 -20 0 20 40 60 80 100
Temperature
FRC (MHz)ATtiny25/45/85 [DATASHEET] 194
2586Q–AVR–08/2013
Figure 22-42. Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value
Figure 22-43. Calibrated 1.6 MHz RC Oscillator Frequency vs. VCC
CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
85 ˚C
25 ˚C
-40 ˚C
0
2
4
6
8
10
12
14
16
18
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
OSCCAL (X1)
FRC (MHz)
CALIBRATED 1.6 MHz RC OSCILLATOR FREQUENCY vs. VCC
85 ˚C
25 ˚C
-40 ˚C
1,4
1,45
1,5
1,55
1,6
1,65
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
FRC (MHz)ATtiny25/45/85 [DATASHEET] 195
2586Q–AVR–08/2013
Figure 22-44. Calibrated 1.6 MHz RC Oscillator Frequency vs. Temperature
Figure 22-45. Calibrated 1.6 MHz RC Oscillator Frequency vs. OSCCAL Value
CALIBRATED 1.6MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
5.0 V
3.0 V
1,5
1,52
1,54
1,56
1,58
1,6
1,62
1,64
-60 -40 -20 0 20 40 60 80 100
Temperature
FRC (MHz)
CALIBRATED 1.6 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
85 ˚C
25 ˚C
-40 ˚C
0
0,5
1
1,5
2
2,5
3
3,5
4
4,5
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
OSCCAL (X1)
FRC (MHz)ATtiny25/45/85 [DATASHEET] 196
2586Q–AVR–08/2013
22.10 Current Consumption of Peripheral Units
Figure 22-46. Brownout Detector Current vs. VCC
Figure 22-47. ADC Current vs. VCC (AREF = AVCC)
BROWNOUT DETECTOR CURRENT vs. VCC
85 °C
25 °C
-40 °C
0
5
10
15
20
25
30
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (uA)
ADC CURRENT vs. VCC
AREF = AVCC
85 °C
25 °C
-40 °C
0
50
100
150
200
250
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (uA)ATtiny25/45/85 [DATASHEET] 197
2586Q–AVR–08/2013
Figure 22-48. Analog Comparator Current vs. VCC
Figure 22-49. Programming Current vs. VCC
ANALOG COMPARATOR CURRENT vs. VCC
85 °C
25 °C
-40 °C
0
5
10
15
20
25
30
35
40
45
50
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (uA)
PROGRAMMING CURRENT vs. Vcc
Ext Clk
85 °C
25 °C
-40 °C
0
2
4
6
8
10
12
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
ICC (mA)ATtiny25/45/85 [DATASHEET] 198
2586Q–AVR–08/2013
22.11 Current Consumption in Reset and Reset Pulsewidth
Figure 22-50. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current Through The Reset Pull-up)
Figure 22-51. Reset Supply Current vs. VCC (1 - 20 MHz, Excluding Current Through The Reset Pull-up)
RESET SUPPLY CURRENT vs. VCC
0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP
5.5 V
5.0 V
4.5 V
4.0 V
3.3 V
2.7 V
1.8 V
0
0,02
0,04
0,06
0,08
0,1
0,12
0,14
0,16
0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1
Frequency (MHz)
ICC (mA)
RESET SUPPLY CURRENT vs. VCC
1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP
5.5 V
5.0 V
4.5 V
0
0,5
1
1,5
2
2,5
0 2 4 6 8 10 12 14 16 18 20
Frequency (MHz)
ICC (mA)
1.8V
2.7V
3.3V
4.0VATtiny25/45/85 [DATASHEET] 199
2586Q–AVR–08/2013
Figure 22-52. Minimum Reset Pulse Width vs. VCC
MINIMUM RESET PULSE WIDTH vs. VCC
85 ˚C
25 ˚C
-40 ˚C
0
500
1000
1500
2000
2500
1,5 2 2,5 3 3,5 4 4,5 5 5,5
VCC (V)
Pulsewidth (ns)ATtiny25/45/85 [DATASHEET] 200
2586Q–AVR–08/2013
23. Register Summary
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
0x3F SREG I T H S V N Z C page 8
0x3E SPH – – – – – – SP9 SP8 page 11
0x3D SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 page 11
0x3C Reserved –
0x3B GIMSK – INT0 PCIE – – – – – page 51
0x3A GIFR – INTF0 PCIF – – – – – page 52
0x39 TIMSK – OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 – pages 81, 102
0x38 TIFR – OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 – page 81
0x37 SPMCSR – – RSIG CTPB RFLB PGWRT PGERS SPMEN page 145
0x36 Reserved –
0x35 MCUCR BODS PUD SE SM1 SM0 BODSE ISC01 ISC00 pages 37, 51, 64
0x34 MCUSR – – – – WDRF BORF EXTRF PORF page 44,
0x33 TCCR0B FOC0A FOC0B – – WGM02 CS02 CS01 CS00 page 79
0x32 TCNT0 Timer/Counter0 page 80
0x31 OSCCAL Oscillator Calibration Register page 31
0x30 TCCR1 CTC1 PWM1A COM1A1 COM1A0 CS13 CS12 CS11 CS10 pages 89, 100
0x2F TCNT1 Timer/Counter1 pages 91, 102
0x2E OCR1A Timer/Counter1 Output Compare Register A pages 91, 102
0x2D OCR1C Timer/Counter1 Output Compare Register C pages 91, 102
0x2C GTCCR TSM PWM1B COM1B1 COM1B0 FOC1B FOC1A PSR1 PSR0 pages 77, 90, 101
0x2B OCR1B Timer/Counter1 Output Compare Register B page 92
0x2A TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 – WGM01 WGM00 page 77
0x29 OCR0A Timer/Counter0 – Output Compare Register A page 80
0x28 OCR0B Timer/Counter0 – Output Compare Register B page 81
0x27 PLLCSR LSM – – – – PCKE PLLE PLOCK pages 94, 103
0x26 CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 page 32
0x25 DT1A DT1AH3 DT1AH2 DT1AH1 DT1AH0 DT1AL3 DT1AL2 DT1AL1 DT1AL0 page 107
0x24 DT1B DT1BH3 DT1BH2 DT1BH1 DT1BH0 DT1BL3 DT1BL2 DT1BL1 DT1BL0 page 107
0x23 DTPS1 - - - - - - DTPS11 DTPS10 page 106
0x22 DWDR DWDR[7:0] page 140
0x21 WDTCR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 page 45
0x20 PRR – PRTIM1 PRTIM0 PRUSI PRADC page 36
0x1F EEARH EEAR8 page 20
0x1E EEARL EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 page 21
0x1D EEDR EEPROM Data Register page 21
0x1C EECR – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE page 21
0x1B Reserved –
0x1A Reserved –
0x19 Reserved –
0x18 PORTB – – PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 page 64
0x17 DDRB – – DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 page 64
0x16 PINB – – PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 page 64
0x15 PCMSK – – PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 page 52
0x14 DIDR0 – – ADC0D ADC2D ADC3D ADC1D AIN1D AIN0D pages 121, 138
0x13 GPIOR2 General Purpose I/O Register 2 page 10
0x12 GPIOR1 General Purpose I/O Register 1 page 10
0x11 GPIOR0 General Purpose I/O Register 0 page 10
0x10 USIBR USI Buffer Register page 115
0x0F USIDR USI Data Register page 115
0x0E USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 page 115
0x0D USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC page 116
0x0C Reserved –
0x0B Reserved –
0x0A Reserved –
0x09 Reserved –
0x08 ACSR ACD ACBG ACO ACI ACIE – ACIS1 ACIS0 page 120
0x07 ADMUX REFS1 REFS0 ADLAR REFS2 MUX3 MUX2 MUX1 MUX0 page 134
0x06 ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 page 136
0x05 ADCH ADC Data Register High Byte page 137
0x04 ADCL ADC Data Register Low Byte page 137
0x03 ADCSRB BIN ACME IPR – – ADTS2 ADTS1 ADTS0 pages 120, 137
0x02 Reserved –
0x01 Reserved –
0x00 Reserved –ATtiny25/45/85 [DATASHEET] 201
2586Q–AVR–08/2013
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.ATtiny25/45/85 [DATASHEET] 202
2586Q–AVR–08/2013
24. Instruction Set Summary
Mnemonics Operands Description Operation Flags #Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD Rd, Rr Add two Registers Rd Rd + Rr Z,C,N,V,H 1
ADC Rd, Rr Add with Carry two Registers Rd Rd + Rr + C Z,C,N,V,H 1
ADIW Rdl,K Add Immediate to Word Rdh:Rdl Rdh:Rdl + K Z,C,N,V,S 2
SUB Rd, Rr Subtract two Registers Rd Rd - Rr Z,C,N,V,H 1
SUBI Rd, K Subtract Constant from Register Rd Rd - K Z,C,N,V,H 1
SBC Rd, Rr Subtract with Carry two Registers Rd Rd - Rr - C Z,C,N,V,H 1
SBCI Rd, K Subtract with Carry Constant from Reg. Rd Rd - K - C Z,C,N,V,H 1
SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl Rdh:Rdl - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Registers Rd Rd Rr Z,N,V 1
ANDI Rd, K Logical AND Register and Constant Rd Rd K Z,N,V 1
OR Rd, Rr Logical OR Registers Rd Rd v Rr Z,N,V 1
ORI Rd, K Logical OR Register and Constant Rd Rd v K Z,N,V 1
EOR Rd, Rr Exclusive OR Registers Rd Rd Rr Z,N,V 1
COM Rd One’s Complement Rd 0xFF Rd Z,C,N,V 1
NEG Rd Two’s Complement Rd 0x00 Rd Z,C,N,V,H 1
SBR Rd,K Set Bit(s) in Register Rd Rd v K Z,N,V 1
CBR Rd,K Clear Bit(s) in Register Rd Rd (0xFF - K) Z,N,V 1
INC Rd Increment Rd Rd + 1 Z,N,V 1
DEC Rd Decrement Rd Rd 1 Z,N,V 1
TST Rd Test for Zero or Minus Rd Rd Rd Z,N,V 1
CLR Rd Clear Register Rd Rd Rd Z,N,V 1
SER Rd Set Register Rd 0xFF None 1
BRANCH INSTRUCTIONS
RJMP k Relative Jump PC PC + k + 1 None 2
IJMP Indirect Jump to (Z) PC Z None 2
RCALL k Relative Subroutine Call PC PC + k + 1 None 3
ICALL Indirect Call to (Z) PC Z None 3
RET Subroutine Return PC STACK None 4
RETI Interrupt Return PC STACK I 4
CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC PC + 2 or 3 None 1/2/3
CP Rd,Rr Compare Rd Rr Z, N,V,C,H 1
CPC Rd,Rr Compare with Carry Rd Rr C Z, N,V,C,H 1
CPI Rd,K Compare Register with Immediate Rd K Z, N,V,C,H 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC PC + 2 or 3 None 1/2/3
SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC PC + 2 or 3 None 1/2/3
SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC PC + 2 or 3 None 1/2/3
SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC PC + 2 or 3 None 1/2/3
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PCPC+k + 1 None 1/2
BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PCPC+k + 1 None 1/2
BREQ k Branch if Equal if (Z = 1) then PC PC + k + 1 None 1/2
BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 None 1/2
BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1 None 1/2
BRCC k Branch if Carry Cleared if (C = 0) then PC PC + k + 1 None 1/2
BRSH k Branch if Same or Higher if (C = 0) then PC PC + k + 1 None 1/2
BRLO k Branch if Lower if (C = 1) then PC PC + k + 1 None 1/2
BRMI k Branch if Minus if (N = 1) then PC PC + k + 1 None 1/2
BRPL k Branch if Plus if (N = 0) then PC PC + k + 1 None 1/2
BRGE k Branch if Greater or Equal, Signed if (N V= 0) then PC PC + k + 1 None 1/2
BRLT k Branch if Less Than Zero, Signed if (N V= 1) then PC PC + k + 1 None 1/2
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC PC + k + 1 None 1/2
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC PC + k + 1 None 1/2
BRTS k Branch if T Flag Set if (T = 1) then PC PC + k + 1 None 1/2
BRTC k Branch if T Flag Cleared if (T = 0) then PC PC + k + 1 None 1/2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1 None 1/2
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None 1/2
BRIE k Branch if Interrupt Enabled if ( I = 1) then PC PC + k + 1 None 1/2
BRID k Branch if Interrupt Disabled if ( I = 0) then PC PC + k + 1 None 1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI P,b Set Bit in I/O Register I/O(P,b) 1 None 2
CBI P,b Clear Bit in I/O Register I/O(P,b) 0 None 2
LSL Rd Logical Shift Left Rd(n+1) Rd(n), Rd(0) 0 Z,C,N,V 1
LSR Rd Logical Shift Right Rd(n) Rd(n+1), Rd(7) 0 Z,C,N,V 1
ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V 1
ROR Rd Rotate Right Through Carry Rd(7)C,Rd(n) Rd(n+1),CRd(0) Z,C,N,V 1
ASR Rd Arithmetic Shift Right Rd(n) Rd(n+1), n=0..6 Z,C,N,V 1ATtiny25/45/85 [DATASHEET] 203
2586Q–AVR–08/2013
SWAP Rd Swap Nibbles Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) None 1
BSET s Flag Set SREG(s) 1 SREG(s) 1
BCLR s Flag Clear SREG(s) 0 SREG(s) 1
BST Rr, b Bit Store from Register to T T Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) T None 1
SEC Set Carry C 1 C1
CLC Clear Carry C 0 C 1
SEN Set Negative Flag N 1 N1
CLN Clear Negative Flag N 0 N 1
SEZ Set Zero Flag Z 1 Z1
CLZ Clear Zero Flag Z 0 Z 1
SEI Global Interrupt Enable I 1 I1
CLI Global Interrupt Disable I 0 I 1
SES Set Signed Test Flag S 1 S1
CLS Clear Signed Test Flag S 0 S 1
SEV Set Twos Complement Overflow. V 1 V1
CLV Clear Twos Complement Overflow V 0 V 1
SET Set T in SREG T 1 T1
CLT Clear T in SREG T 0 T 1
SEH Set Half Carry Flag in SREG H 1 H1
CLH Clear Half Carry Flag in SREG H 0 H 1
DATA TRANSFER INSTRUCTIONS
MOV Rd, Rr Move Between Registers Rd Rr None 1
MOVW Rd, Rr Copy Register Word Rd+1:Rd Rr+1:Rr None 1
LDI Rd, K Load Immediate Rd K None 1
LD Rd, X Load Indirect Rd (X) None 2
LD Rd, X+ Load Indirect and Post-Inc. Rd (X), X X + 1 None 2
LD Rd, - X Load Indirect and Pre-Dec. X X - 1, Rd (X) None 2
LD Rd, Y Load Indirect Rd (Y) None 2
LD Rd, Y+ Load Indirect and Post-Inc. Rd (Y), Y Y + 1 None 2
LD Rd, - Y Load Indirect and Pre-Dec. Y Y - 1, Rd (Y) None 2
LDD Rd,Y+q Load Indirect with Displacement Rd (Y + q) None 2
LD Rd, Z Load Indirect Rd (Z) None 2
LD Rd, Z+ Load Indirect and Post-Inc. Rd (Z), Z Z+1 None 2
LD Rd, -Z Load Indirect and Pre-Dec. Z Z - 1, Rd (Z) None 2
LDD Rd, Z+q Load Indirect with Displacement Rd (Z + q) None 2
LDS Rd, k Load Direct from SRAM Rd (k) None 2
ST X, Rr Store Indirect (X) Rr None 2
ST X+, Rr Store Indirect and Post-Inc. (X) Rr, X X + 1 None 2
ST - X, Rr Store Indirect and Pre-Dec. X X - 1, (X) Rr None 2
ST Y, Rr Store Indirect (Y) Rr None 2
ST Y+, Rr Store Indirect and Post-Inc. (Y) Rr, Y Y + 1 None 2
ST - Y, Rr Store Indirect and Pre-Dec. Y Y - 1, (Y) Rr None 2
STD Y+q,Rr Store Indirect with Displacement (Y + q) Rr None 2
ST Z, Rr Store Indirect (Z) Rr None 2
ST Z+, Rr Store Indirect and Post-Inc. (Z) Rr, Z Z + 1 None 2
ST -Z, Rr Store Indirect and Pre-Dec. Z Z - 1, (Z) Rr None 2
STD Z+q,Rr Store Indirect with Displacement (Z + q) Rr None 2
STS k, Rr Store Direct to SRAM (k) Rr None 2
LPM Load Program Memory R0 (Z) None 3
LPM Rd, Z Load Program Memory Rd (Z) None 3
LPM Rd, Z+ Load Program Memory and Post-Inc Rd (Z), Z Z+1 None 3
SPM Store Program Memory (z) R1:R0 None
IN Rd, P In Port Rd P None 1
OUT P, Rr Out Port P Rr None 1
PUSH Rr Push Register on Stack STACK Rr None 2
POP Rd Pop Register from Stack Rd STACK None 2
MCU CONTROL INSTRUCTIONS
NOP No Operation None 1
SLEEP Sleep (see specific descr. for Sleep function) None 1
WDR Watchdog Reset (see specific descr. for WDR/Timer) None 1
BREAK Break For On-chip Debug Only None N/A
Mnemonics Operands Description Operation Flags #ClocksATtiny25/45/85 [DATASHEET] 204
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25. Ordering Information
Notes: 1. For speed vs. supply voltage, see section 21.3 “Speed” on page 163.
2. All Pb-free, halide-free, fully green, and comply with European directive for Restriction of Hazardous Substances (RoHS).
3. Code indicators: H = NiPdAu lead finish, U/N = matte tin, R = tape & reel.
4. Can also be supplied in wafer form. Contact your local Atmel sales office for ordering information and minimum quantities.
5. For characteristics, see “Appendix A – Specification at 105C”.
6. For characteristics, see “Appendix B – Specification at 125C”.
25.1 ATtiny25
Speed (MHz) (1) Supply Voltage (V) Temperature Range Package (2) Ordering Code (3)
10 1.8 – 5.5
Industrial
(-40C to +85C) (4)
8P3 ATtiny25V-10PU
8S2
ATtiny25V-10SU
ATtiny25V-10SUR
ATtiny25V-10SH
ATtiny25V-10SHR
S8S1
ATtiny25V-10SSU
ATtiny25V-10SSUR
ATtiny25V-10SSH
ATtiny25V-10SSHR
20M1 ATtiny25V-10MU
ATtiny25V-10MUR
Industrial
(-40C to +105C) (5)
8S2 ATtiny25V-10SN
ATtiny25V-10SNR
S8S1 ATtiny25V-10SSN
ATtiny25V-10SSNR
Industrial (-40C to +125C) (6) 20M1 ATtiny25V-10MF
ATtiny25V-10MFR
20 2.7 – 5.5
Industrial
(-40C to +85C) (4)
8P3 ATtiny25-20PU
8S2
ATtiny25-20SU
ATtiny25-20SUR
ATtiny25-20SH
ATtiny25-20SHR
S8S1
ATtiny25-20SSU
ATtiny25-20SSUR
ATtiny25-20SSH
ATtiny25-20SSHR
20M1 ATtiny25-20MU
ATtiny25-20MUR
Industrial
(-40C to +105C) (5)
8S2 ATtiny25-20SN
ATtiny25-20SNR
S8S1 ATtiny25-20SSN
ATtiny25-20SSNR
Industrial (-40C to +125C) (6) 20M1 ATtiny25-20MF
ATtiny25-20MFR
Package Types
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S2 8-lead, 0.208" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)
S8S1 8-lead, 0.150" Wide, Plastic Gull-Wing Small Outline (JEDEC SOIC)
20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)ATtiny25/45/85 [DATASHEET] 205
2586Q–AVR–08/2013
Notes: 1. For speed vs. supply voltage, see section 21.3 “Speed” on page 163.
2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous
Substances (RoHS).
3. Code indicators:
– H: NiPdAu lead finish
– U: matte tin
– R: tape & reel
4. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
25.2 ATtiny45
Speed (MHz) (1) Supply Voltage (V) Temperature Range Package (2) Ordering Code (3)
10 1.8 – 5.5 Industrial
(-40C to +85C) (4)
8P3 ATtiny45V-10PU
8S2
ATtiny45V-10SU
ATtiny45V-10SUR
ATtiny45V-10SH
ATtiny45V-10SHR
8X ATtiny45V-10XU
ATtiny45V-10XUR
20M1 ATtiny45V-10MU
ATtiny45V-10MUR
20 2.7 – 5.5 Industrial
(-40C to +85C) (4)
8P3 ATtiny45-20PU
8S2
ATtiny45-20SU
ATtiny45-20SUR
ATtiny45-20SH
ATtiny45-20SHR
8X ATtiny45-20XU
ATtiny45-20XUR
20M1 ATtiny45-20MU
ATtiny45-20MUR
Package Types
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S2 8-lead, 0.208" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)
8X 8-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline Package (TSSOP)
20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)ATtiny25/45/85 [DATASHEET] 206
2586Q–AVR–08/2013
Notes: 1. For speed vs. supply voltage, see section 21.3 “Speed” on page 163.
2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous
Substances (RoHS).
3. Code indicators:
– H: NiPdAu lead finish
– U: matte tin
– R: tape & reel
4. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
25.3 ATtiny85
Speed (MHz) (1) Supply Voltage (V) Temperature Range Package (2) Ordering Code (3)
10 1.8 – 5.5 Industrial
(-40C to +85C) (4)
8P3 ATtiny85V-10PU
8S2
ATtiny85V-10SU
ATtiny85V-10SUR
ATtiny85V-10SH
ATtiny85V-10SHR
20M1 ATtiny85V-10MU
ATtiny85V-10MUR
20 2.7 – 5.5 Industrial
(-40C to +85C) (4)
8P3 ATtiny85-20PU
8S2
ATtiny85-20SU
ATtiny85-20SUR
ATtiny85-20SH
ATtiny85-20SHR
20M1 ATtiny85-20MU
ATtiny85-20MUR
Package Types
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S2 8-lead, 0.208" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)
20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)ATtiny25/45/85 [DATASHEET] 207
2586Q–AVR–08/2013
26. Packaging Information
26.1 8P3
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
01/09/02
8P3 B
D
D1
E
E1
e
b2 L
b
A2 A
1
N
eA
c
b3
4 PLCS
Top View
Side View
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
A 0.210 2
A2 0.115 0.130 0.195
b 0.014 0.018 0.022 5
b2 0.045 0.060 0.070 6
b3 0.030 0.039 0.045 6
c 0.008 0.010 0.014
D 0.355 0.365 0.400 3
D1 0.005 3
E 0.300 0.310 0.325 4
E1 0.240 0.250 0.280 3
e 0.100 BSC
eA 0.300 BSC 4
L 0.115 0.130 0.150 2ATtiny25/45/85 [DATASHEET] 208
2586Q–AVR–08/2013
26.2 8S2
TITLE GPC DRAWING NO. REV.
Package Drawing Contact:
packagedrawings@atmel.com STN F 8S2
8S2, 8-lead, 0.208” Body, Plastic Small
Outline Package (EIAJ)
4/15/08
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs aren't included.
3. Determines the true geometric position.
4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.
A 1.70 2.16
A1 0.05 0.25
b 0.35 0.48 4
C 0.15 0.35 4
D 5.13 5.35
E1 5.18 5.40 2
E 7.70 8.26
L 0.51 0.85
θ 0° 8°
e 1.27 BSC 3
θ
1
N
E
TOP VIEW TOP VIEW
C
E1
END VIEW END VIEW
A
b
L
A1
e
D
SIDE VIEW SIDE VIEWATtiny25/45/85 [DATASHEET] 209
2586Q–AVR–08/2013
26.3 S8S1
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
S8S1, 8-lead, 0.150" Wide Body, Plastic Gull Wing Small
Outline (JEDEC SOIC)
7/28/03
S8S1 A
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums,etc.
E 5.79 6.20
E1 3.81 3.99
A 1.35 1.75
A1 0.1 0.25
D 4.80 4.98
C 0.17 0.25
b 0.31 0.51
L 0.4 1.27
e 1.27 BSC
0o
8o
Top View
Side View
End View
1
N
C
A
A1
b
L
e
D
E1 EATtiny25/45/85 [DATASHEET] 210
2586Q–AVR–08/2013
26.4 8X
TITLE DRAWING NO.
R
REV.
Note: These drawings are for general information only. Refer to JEDEC Drawing MO-153AC.
2325 Orchard Parkway
San Jose, CA 95131
4/14/05
8X, 8-lead, 4.4 mm Body Width, Plastic Thin Shrink
Small Outline Package (TSSOP) 8X A
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 1.05 1.10 1.20
A1 0.05 0.10 0.15
b 0.25 – 0.30
C – 0.127 –
D 2.90 3.05 3.10
E1 4.30 4.40 4.50
E 6.20 6.40 6.60
e 0.65 TYP
L 0.50 0.60 0.70
Ø 0o – 8o
C
A
b
L
A1
D
Side View
Top View
End View
E
1
E1
e
ØATtiny25/45/85 [DATASHEET] 211
2586Q–AVR–08/2013
26.5 20M1
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, 20M1 B
10/27/04
2.6 mm Exposed Pad, Micro Lead Frame Package (MLF)
A 0.70 0.75 0.80
A1 – 0.01 0.05
A2 0.20 REF
b 0.18 0.23 0.30
D 4.00 BSC
D2 2.45 2.60 2.75
E 4.00 BSC
E2 2.45 2.60 2.75
e 0.50 BSC
L 0.35 0.40 0.55
SIDE VIEW
Pin 1 ID
Pin #1
Notch
(0.20 R)
BOTTOM VIEW
TOP VIEW
Note: Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5.
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D
E
e
A2
A1
A
D2
E2
0.08 C
L
1
2
3
b
1
2
3ATtiny25/45/85 [DATASHEET] 212
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27. Errata
27.1 Errata ATtiny25
The revision letter in this section refers to the revision of the ATtiny25 device.
27.1.1 Rev D – F
No known errata.
27.1.2 Rev B – C
• EEPROM read may fail at low supply voltage / low clock frequency
1. EEPROM read may fail at low supply voltage / low clock frequency
Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data.
Problem Fix/Workaround
Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below 2V. If operating frequency
can not be raised above 1MHz then supply voltage should be more than 2V. Similarly, if supply voltage
can not be raised above 2V then operating frequency should be more than 1MHz.
This feature is known to be temperature dependent but it has not been characterised. Guidelines are given for
room temperature, only.
27.1.3 Rev A
Not sampled.
27.2 Errata ATtiny45
The revision letter in this section refers to the revision of the ATtiny45 device.
27.2.1 Rev F – G
No known errata
27.2.2 Rev D – E
• EEPROM read may fail at low supply voltage / low clock frequency
1. EEPROM read may fail at low supply voltage / low clock frequency
Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data.
Problem Fix/Workaround
Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below 2V. If operating frequency
can not be raised above 1MHz then supply voltage should be more than 2V. Similarly, if supply voltage
can not be raised above 2V then operating frequency should be more than 1MHz.
This feature is known to be temperature dependent but it has not been characterised. Guidelines are given for
room temperature, only.ATtiny25/45/85 [DATASHEET] 213
2586Q–AVR–08/2013
27.2.3 Rev B – C
• PLL not locking
• EEPROM read from application code does not work in Lock Bit Mode 3
• EEPROM read may fail at low supply voltage / low clock frequency
• Timer Counter 1 PWM output generation on OC1B- XOC1B does not work correctly
1. PLL not locking
When at frequencies below 6.0 MHz, the PLL will not lock
Problem fix / Workaround
When using the PLL, run at 6.0 MHz or higher.
2. EEPROM read from application code does not work in Lock Bit Mode 3
When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does not work from the
application code.
Problem Fix/Work around
Do not set Lock Bit Protection Mode 3 when the application code needs to read from EEPROM.
3. EEPROM read may fail at low supply voltage / low clock frequency
Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data.
Problem Fix/Workaround
Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below 2V. If operating frequency
can not be raised above 1MHz then supply voltage should be more than 2V. Similarly, if supply voltage
can not be raised above 2V then operating frequency should be more than 1MHz.
This feature is known to be temperature dependent but it has not been characterised. Guidelines are given for
room temperature, only.
4. Timer Counter 1 PWM output generation on OC1B – XOC1B does not work correctly
Timer Counter1 PWM output OC1B-XOC1B does not work correctly. Only in the case when the control bits,
COM1B1 and COM1B0 are in the same mode as COM1A1 and COM1A0, respectively, the OC1B-XOC1B output
works correctly.
Problem Fix/Work around
The only workaround is to use same control setting on COM1A[1:0] and COM1B[1:0] control bits, see table 14-
4 in the data sheet. The problem has been fixed for Tiny45 rev D.
27.2.4 Rev A
• Too high power down power consumption
• DebugWIRE looses communication when single stepping into interrupts
• PLL not locking
• EEPROM read from application code does not work in Lock Bit Mode 3
• EEPROM read may fail at low supply voltage / low clock frequency
1. Too high power down power consumption
Three situations will lead to a too high power down power consumption. These are:
– An external clock is selected by fuses, but the I/O PORT is still enabled as an output.
– The EEPROM is read before entering power down.
– VCC is 4.5 volts or higher.
Problem fix / WorkaroundATtiny25/45/85 [DATASHEET] 214
2586Q–AVR–08/2013
– When using external clock, avoid setting the clock pin as Output.
– Do not read the EEPROM if power down power consumption is important.
– Use VCC lower than 4.5 Volts.
2. DebugWIRE looses communication when single stepping into interrupts
When receiving an interrupt during single stepping, debugwire will loose
communication.
Problem fix / Workaround
– When singlestepping, disable interrupts.
– When debugging interrupts, use breakpoints within the interrupt routine, and run into the interrupt.
3. PLL not locking
When at frequencies below 6.0 MHz, the PLL will not lock
Problem fix / Workaround
When using the PLL, run at 6.0 MHz or higher.
4. EEPROM read from application code does not work in Lock Bit Mode 3
When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does not work from the
application code.
Problem Fix/Work around
Do not set Lock Bit Protection Mode 3 when the application code needs to read from EEPROM.
5. EEPROM read may fail at low supply voltage / low clock frequency
Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data.
Problem Fix/Workaround
Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below 2V. If operating frequency
can not be raised above 1MHz then supply voltage should be more than 2V. Similarly, if supply voltage
can not be raised above 2V then operating frequency should be more than 1MHz.
This feature is known to be temperature dependent but it has not been characterized. Guidelines are given for
room temperature, only.ATtiny25/45/85 [DATASHEET] 215
2586Q–AVR–08/2013
27.3 Errata ATtiny85
The revision letter in this section refers to the revision of the ATtiny85 device.
27.3.1 Rev B – C
No known errata.
27.3.2 Rev A
• EEPROM read may fail at low supply voltage / low clock frequency
1. EEPROM read may fail at low supply voltage / low clock frequency
Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in invalid data.
Problem Fix/Workaround
Do not use the EEPROM when clock frequency is below 1MHz and supply voltage is below 2V. If operating frequency
can not be raised above 1MHz then supply voltage should be more than 2V. Similarly, if supply voltage
can not be raised above 2V then operating frequency should be more than 1MHz.
This feature is known to be temperature dependent but it has not been characterised. Guidelines are given for
room temperature, only.ATtiny25/45/85 [DATASHEET] 216
2586Q–AVR–08/2013
28. Datasheet Revision History
28.1 Rev. 2586Q-08/13
28.2 Rev. 2586P-06/13
28.3 Rev. 2586O-02/13
Updated ordering codes on page 204, page 205, and page 206.
28.4 Rev. 2586N-04/11
1. Added:
– Section “Capacitive Touch Sensing” on page 6.
2. Updated:
– Document template.
– Removed “Preliminary” on front page. All devices now final and in production.
– Section “Limitations” on page 36.
– Program example on page 49.
– Section “Overview” on page 122.
– Table 17-4 on page 135.
– Section “Limitations of debugWIRE” on page 140.
– Section “Serial Programming Algorithm” on page 151.
– Table 21-7 on page 166.
– EEPROM errata on pages 212, 212, 213, 214, and 215
– Ordering information on pages 204, 205, and 206.
28.5 Rev. 2586M-07/10
1. Clarified Section 6.4 “Clock Output Buffer” on page 31.
2. Added Ordering Codes -SN and -SNR for ATtiny25 extended temperature.
28.6 Rev. 2586L-06/10
1. Added:
– TSSOP for ATtiny45 in “Features” on page 1, Pinout Figure 1-1 on page 2, Ordering Information in
Section 25.2 “ATtiny45” on page 205, and Packaging Information in Section 26.4 “8X” on page 210
– Table 6-11, “Capacitance of Low-Frequency Crystal Oscillator,” on page 29
– Figure 22-36 on page 191 and Figure 22-37 on page 191, Typical Characteristics plots for Bandgap
Voltage vs. VCC and Temperature
– Extended temperature in Section 25.1 “ATtiny25” on page 204, Ordering Information
– Tape & reel part numbers in Ordering Information, in Section 25.1 “ATtiny25” on page 204 and Section
25.2 “ATtiny45” on page 205
1. “Bit 3 – FOC1B: Force Output Compare Match 1B” description in “GTCCR – General Timer/Counter1 Control
Register” on page 90 updated: PB3 in “compare match output pin PB3 (OC1B)” corrected to PB4.
1. Updated description of “EEARH – EEPROM Address Register” and “EEARL – EEPROM Address Register” on page
20.ATtiny25/45/85 [DATASHEET] 217
2586Q–AVR–08/2013
2. Updated:
– “Features” on page 1, removed Preliminary from ATtiny25
– Section 8.4.2 “Code Example” on page 44
– “PCMSK – Pin Change Mask Register” on page 52, Bit Descriptions
– “TCCR1 – Timer/Counter1 Control Register” on page 89 and “GTCCR – General Timer/Counter1
Control Register” on page 90, COM bit descriptions clarified
– Section 20.3.2 “Calibration Bytes” on page 150, frequencies (8 MHz, 6.4 MHz)
– Table 20-11, “Minimum Wait Delay Before Writing the Next Flash or EEPROM Location,” on page 153,
value for tWD_ERASE
– Table 20-16, “High-voltage Serial Programming Instruction Set for ATtiny25/45/85,” on page 158
– Table 21-1, “DC Characteristics. TA = -40°C to +85°C,” on page 161, notes adjusted
– Table 21-11, “Serial Programming Characteristics, TA = -40°C to +85°C, VCC = 1.8 - 5.5V (Unless
Otherwise Noted),” on page 170, added tSLIV
– Bit syntax throughout the datasheet, e.g. from CS02:0 to CS0[2:0].
28.7 Rev. 2586K-01/08
1. Updated Document Template.
2. Added Sections:
– “Data Retention” on page 6
– “Low Level Interrupt” on page 49
– “Device Signature Imprint Table” on page 149
3. Updated Sections:
– “Internal PLL for Fast Peripheral Clock Generation - clkPCK” on page 24
– “System Clock and Clock Options” on page 23
– “Internal PLL in ATtiny15 Compatibility Mode” on page 24
– “Sleep Modes” on page 34
– “Software BOD Disable” on page 35
– “External Interrupts” on page 49
– “Timer/Counter1 in PWM Mode” on page 97
– “USI – Universal Serial Interface” on page 108
– “Temperature Measurement” on page 133
– “Reading Lock, Fuse and Signature Data from Software” on page 143
– “Program And Data Memory Lock Bits” on page 147
– “Fuse Bytes” on page 148
– “Signature Bytes” on page 150
– “Calibration Bytes” on page 150
– “System and Reset Characteristics” on page 165
4. Added Figures:
– “Reset Pin Output Voltage vs. Sink Current (VCC = 3V)” on page 184
– “Reset Pin Output Voltage vs. Sink Current (VCC = 5V)” on page 185
– “Reset Pin Output Voltage vs. Source Current (VCC = 3V)” on page 185
– “Reset Pin Output Voltage vs. Source Current (VCC = 5V)” on page 186ATtiny25/45/85 [DATASHEET] 218
2586Q–AVR–08/2013
5. Updated Figure:
– “Reset Logic” on page 39
6. Updated Tables:
– “Start-up Times for Internal Calibrated RC Oscillator Clock” on page 28
– “Start-up Times for Internal Calibrated RC Oscillator Clock (in ATtiny15 Mode)” on page 28
– “Start-up Times for the 128 kHz Internal Oscillator” on page 28
– “Compare Mode Select in PWM Mode” on page 86
– “Compare Mode Select in PWM Mode” on page 98
– “DC Characteristics. TA = -40°C to +85°C” on page 161
– “Calibration Accuracy of Internal RC Oscillator” on page 164
– “ADC Characteristics” on page 167
7. Updated Code Example in Section:
– “Write” on page 17
8. Updated Bit Descriptions in:
– “MCUCR – MCU Control Register” on page 37
– “Bits 7:6 – COM0A[1:0]: Compare Match Output A Mode” on page 77
– “Bits 5:4 – COM0B[1:0]: Compare Match Output B Mode” on page 77
– “Bits 2:0 – ADTS[2:0]: ADC Auto Trigger Source” on page 138
– “SPMCSR – Store Program Memory Control and Status Register” on page 145.
9. Updated description of feature “EEPROM read may fail at low supply voltage / low clock frequency” in
Sections:
– “Errata ATtiny25” on page 212
– “Errata ATtiny45” on page 212
– “Errata ATtiny85” on page 215
10. Updated Package Description in Sections:
– “ATtiny25” on page 204
– “ATtiny45” on page 205
– “ATtiny85” on page 206
11. Updated Package Drawing:
– “S8S1” on page 209
12. Updated Order Codes for:
– “ATtiny25” on page 204
28.8 Rev. 2586J-12/06
1. Updated “Low Power Consumption” on page 1.
2. Updated description of instruction length in “Architectural Overview” .
3. Updated Flash size in “In-System Re-programmable Flash Program Memory” on
page 15.
4. Updated cross-references in sections “Atomic Byte Programming” , “Erase” and
“Write” , starting on page 17.
5. Updated “Atomic Byte Programming” on page 17.
6. Updated “Internal PLL for Fast Peripheral Clock Generation - clkPCK” on page 24.
7. Replaced single clocking system figure with two: Figure 6-2 and Figure 6-3.ATtiny25/45/85 [DATASHEET] 219
2586Q–AVR–08/2013
8. Updated Table 6-1 on page 25, Table 6-13 on page 30 and Table 6-6 on page 27.
9. Updated “Calibrated Internal Oscillator” on page 27.
10. Updated Table 6-5 on page 26.
11. Updated “OSCCAL – Oscillator Calibration Register” on page 31.
12. Updated “CLKPR – Clock Prescale Register” on page 32.
13. Updated “Power-down Mode” on page 35.
14. Updated “Bit 0” in “PRR – Power Reduction Register” on page 38.
15. Added footnote to Table 8-3 on page 46.
16. Updated Table 10-5 on page 63.
17. Deleted “Bits 7, 2” in “MCUCR – MCU Control Register” on page 64.
18. Updated and moved section “Timer/Counter0 Prescaler and Clock Sources”, now
located on page 66.
19. Updated “Timer/Counter1 Initialization for Asynchronous Mode” on page 86.
20. Updated bit description in “PLLCSR – PLL Control and Status Register” on page 94
and “PLLCSR – PLL Control and Status Register” on page 103.
21. Added recommended maximum frequency in“Prescaling and Conversion Timing” on
page 125.
22. Updated Figure 17-8 on page 129 .
23. Updated “Temperature Measurement” on page 133.
24. Updated Table 17-3 on page 134.
25. Updated bit R/W descriptions in:
“TIMSK – Timer/Counter Interrupt Mask Register” on page 81,
“TIFR – Timer/Counter Interrupt Flag Register” on page 81,
“TIMSK – Timer/Counter Interrupt Mask Register” on page 92,
“TIFR – Timer/Counter Interrupt Flag Register” on page 93,
“PLLCSR – PLL Control and Status Register” on page 94,
“TIMSK – Timer/Counter Interrupt Mask Register” on page 102,
“TIFR – Timer/Counter Interrupt Flag Register” on page 103,
“PLLCSR – PLL Control and Status Register” on page 103 and
“DIDR0 – Digital Input Disable Register 0” on page 138.
26. Added limitation to “Limitations of debugWIRE” on page 140.
27. Updated “DC Characteristics” on page 161.
28. Updated Table 21-7 on page 166.
29. Updated Figure 21-6 on page 171.
30. Updated Table 21-12 on page 171.
31. Updated Table 22-1 on page 177.
32. Updated Table 22-2 on page 177.
33. Updated Table 22-30, Table 22-31 and Table 22-32, starting on page 188.
34. Updated Table 22-33, Table 22-34 and Table 22-35, starting on page 189.
35. Updated Table 22-39 on page 192.
36. Updated Table 22-46, Table 22-47, Table 22-48 and Table 22-49.ATtiny25/45/85 [DATASHEET] 220
2586Q–AVR–08/2013
28.9 Rev. 2586I-09/06
28.10 Rev. 2586H-06/06
28.11 Rev. 2586G-05/06
28.12 Rev. 2586F-04/06
1. All Characterization data moved to “Electrical Characteristics” on page 161.
2. All Register Descriptions are gathered up in seperate sections in the end of each
chapter.
3. Updated Table 11-3 on page 78, Table 11-5 on page 79, Table 11-6 on page 80 and
Table 20-4 on page 148.
4. Updated “Calibrated Internal Oscillator” on page 27.
5. Updated Note in Table 7-1 on page 34.
6. Updated “System Control and Reset” on page 39.
7. Updated Register Description in “I/O Ports” on page 53.
8. Updated Features in “USI – Universal Serial Interface” on page 108.
9. Updated Code Example in “SPI Master Operation Example” on page 110 and “SPI
Slave Operation Example” on page 111.
10. Updated “Analog Comparator Multiplexed Input” on page 119.
11. Updated Figure 17-1 on page 123.
12. Updated “Signature Bytes” on page 150.
13. Updated “Electrical Characteristics” on page 161.
1. Updated “Calibrated Internal Oscillator” on page 27.
2. Updated Table 6.5.1 on page 31.
3. Added Table 21-2 on page 164.
1. Updated “Internal PLL for Fast Peripheral Clock Generation - clkPCK” on page 24.
2. Updated “Default Clock Source” on page 30.
3. Updated “Low-Frequency Crystal Oscillator” on page 29.
4. Updated “Calibrated Internal Oscillator” on page 27.
5. Updated “Clock Output Buffer” on page 31.
6. Updated “Power Management and Sleep Modes” on page 34.
7. Added “Software BOD Disable” on page 35.
8. Updated Figure 16-1 on page 119.
9. Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page 120.
10. Added note for Table 17-2 on page 125.
11. Updated “Register Summary” on page 200.
1. Updated “Digital Input Enable and Sleep Modes” on page 57.
2. Updated Table 20-16 on page 158.
3. Updated “Ordering Information” on page 204.ATtiny25/45/85 [DATASHEET] 221
2586Q–AVR–08/2013
28.13 Rev. 2586E-03/06
28.14 Rev. 2586D-02/06
28.15 Rev. 2586C-06/05
28.16 Rev. 2586B-05/05
28.17 Rev. 2586A-02/05
Initial revision.
1. Updated Features in “Analog to Digital Converter” on page 122.
2. Updated Operation in “Analog to Digital Converter” on page 122.
3. Updated Table 17-2 on page 133.
4. Updated Table 17-3 on page 134.
5. Updated “Errata” on page 212.
1. Updated Table 6-13 on page 30, Table 6-10 on page 29, Table 6-3 on page 26,
Table 6-9 on page 28, Table 6-5 on page 26, Table 9-1 on page 48,Table 17-4 on
page 135, Table 20-16 on page 158, Table 21-8 on page 167.
2. Updated “Timer/Counter1 in PWM Mode” on page 86.
3. Updated text “Bit 2 – TOV1: Timer/Counter1 Overflow Flag” on page 93.
4. Updated values in “DC Characteristics” on page 161.
5. Updated “Register Summary” on page 200.
6. Updated “Ordering Information” on page 204.
7. Updated Rev B and C in “Errata ATtiny45” on page 212.
8. All references to power-save mode are removed.
9. Updated Register Adresses.
1. Updated “Features” on page 1.
2. Updated Figure 1-1 on page 2.
3. Updated Code Examples on page 18 and page 19.
4. Moved “Temperature Measurement” to Section 17.12 page 133.
5. Updated “Register Summary” on page 200.
6. Updated “Ordering Information” on page 204.
1. CLKI added, instances of EEMWE/EEWE renamed EEMPE/EEPE, removed some
TBD.
Removed “Preliminary Description” from “Temperature Measurement” on page 133.
2. Updated “Features” on page 1.
3. Updated Figure 1-1 on page 2 and Figure 8-1 on page 39.
4. Updated Table 7-2 on page 38, Table 10-4 on page 63, Table 10-5 on page 63
5. Updated “Serial Programming Instruction set” on page 153.
6. Updated SPH register in “Instruction Set Summary” on page 202.
7. Updated “DC Characteristics” on page 161.
8. Updated “Ordering Information” on page 204.
9. Updated “Errata” on page 212.ATtiny25/45/85 [DATASHEET] 222
2586Q–AVR–08/2013ATtiny25/45/85 [DATASHEET] 223
2586Q–AVR–08/2013ATtiny25/45/85 [DATASHEET] 224
2586Q–AVR–08/2013ATtiny25/45/85 [DATASHEET] 225
2586Q–AVR–08/2013ATtiny25/45/85 [DATASHEET] 226
2586Q–AVR–08/2013ATtiny25/45/85 [DATASHEET] i
2586Q–AVR–08/2013
Table of Contents
Features .....................................................................................................1
1 Pin Configurations ...................................................................................2
1.1 Pin Descriptions .................................................................................................2
2 Overview ...................................................................................................4
2.1 Block Diagram ...................................................................................................4
3 About .........................................................................................................6
3.1 Resources .........................................................................................................6
3.2 Code Examples .................................................................................................6
3.3 Capacitive Touch Sensing .................................................................................6
3.4 Data Retention ...................................................................................................6
4 AVR CPU Core ..........................................................................................7
4.1 Introduction ........................................................................................................7
4.2 Architectural Overview .......................................................................................7
4.3 ALU – Arithmetic Logic Unit ...............................................................................8
4.4 Status Register ..................................................................................................8
4.5 General Purpose Register File ........................................................................10
4.6 Stack Pointer ...................................................................................................11
4.7 Instruction Execution Timing ...........................................................................11
4.8 Reset and Interrupt Handling ...........................................................................12
5 AVR Memories ........................................................................................15
5.1 In-System Re-programmable Flash Program Memory ....................................15
5.2 SRAM Data Memory ........................................................................................15
5.3 EEPROM Data Memory ..................................................................................16
5.4 I/O Memory ......................................................................................................19
5.5 Register Description ........................................................................................20
6 System Clock and Clock Options .........................................................23
6.1 Clock Systems and their Distribution ...............................................................23
6.2 Clock Sources .................................................................................................25
6.3 System Clock Prescaler ..................................................................................31
6.4 Clock Output Buffer .........................................................................................31
6.5 Register Description ........................................................................................31
7 Power Management and Sleep Modes .................................................34
7.1 Sleep Modes ....................................................................................................34ATtiny25/45/85 [DATASHEET] ii
2586Q–AVR–08/2013
7.2 Software BOD Disable .....................................................................................35
7.3 Power Reduction Register ...............................................................................36
7.4 Minimizing Power Consumption ......................................................................36
7.5 Register Description ........................................................................................37
8 System Control and Reset .....................................................................39
8.1 Resetting the AVR ...........................................................................................39
8.2 Reset Sources .................................................................................................39
8.3 Internal Voltage Reference ..............................................................................42
8.4 Watchdog Timer ..............................................................................................42
8.5 Register Description ........................................................................................44
9 Interrupts .................................................................................................48
9.1 Interrupt Vectors in ATtiny25/45/85 .................................................................48
9.2 External Interrupts ...........................................................................................49
9.3 Register Description ........................................................................................51
10 I/O Ports ..................................................................................................53
10.1 Introduction ......................................................................................................53
10.2 Ports as General Digital I/O .............................................................................53
10.3 Alternate Port Functions ..................................................................................57
10.4 Register Description ........................................................................................64
11 8-bit Timer/Counter0 with PWM ............................................................65
11.1 Features ..........................................................................................................65
11.2 Overview ..........................................................................................................65
11.3 Timer/Counter0 Prescaler and Clock Sources ................................................66
11.4 Counter Unit ....................................................................................................68
11.5 Output Compare Unit .......................................................................................69
11.6 Compare Match Output Unit ............................................................................70
11.7 Modes of Operation .........................................................................................71
11.8 Timer/Counter Timing Diagrams ......................................................................76
11.9 Register Description ........................................................................................77
12 8-bit Timer/Counter1 ..............................................................................83
12.1 Timer/Counter1 Prescaler ...............................................................................83
12.2 Counter and Compare Units ............................................................................83
12.3 Register Description ........................................................................................89
13 8-bit Timer/Counter1 in ATtiny15 Mode ...............................................95
13.1 Timer/Counter1 Prescaler ...............................................................................95ATtiny25/45/85 [DATASHEET] iii
2586Q–AVR–08/2013
13.2 Counter and Compare Units ............................................................................95
13.3 Register Description ......................................................................................100
14 Dead Time Generator ...........................................................................105
14.1 Register Description ......................................................................................106
15 USI – Universal Serial Interface ..........................................................108
15.1 Features ........................................................................................................108
15.2 Overview ........................................................................................................108
15.3 Functional Descriptions .................................................................................109
15.4 Alternative USI Usage ...................................................................................114
15.5 Register Descriptions ....................................................................................115
16 Analog Comparator ..............................................................................119
16.1 Analog Comparator Multiplexed Input ...........................................................119
16.2 Register Description ......................................................................................120
17 Analog to Digital Converter .................................................................122
17.1 Features ........................................................................................................122
17.2 Overview ........................................................................................................122
17.3 Operation .......................................................................................................123
17.4 Starting a Conversion ....................................................................................124
17.5 Prescaling and Conversion Timing ................................................................125
17.6 Changing Channel or Reference Selection ...................................................128
17.7 ADC Noise Canceler .....................................................................................128
17.8 Analog Input Circuitry ....................................................................................129
17.9 Noise Canceling Techniques .........................................................................129
17.10 ADC Accuracy Definitions .............................................................................130
17.11 ADC Conversion Result .................................................................................132
17.12 Temperature Measurement ...........................................................................133
17.13 Register Description ......................................................................................134
18 debugWIRE On-chip Debug System ...................................................139
18.1 Features ........................................................................................................139
18.2 Overview ........................................................................................................139
18.3 Physical Interface ..........................................................................................139
18.4 Software Break Points ...................................................................................140
18.5 Limitations of debugWIRE .............................................................................140
18.6 Register Description ......................................................................................140
19 Self-Programming the Flash ...............................................................141ATtiny25/45/85 [DATASHEET] iv
2586Q–AVR–08/2013
19.1 Performing Page Erase by SPM ....................................................................141
19.2 Filling the Temporary Buffer (Page Loading) .................................................141
19.3 Performing a Page Write ...............................................................................142
19.4 Addressing the Flash During Self-Programming ...........................................142
19.5 EEPROM Write Prevents Writing to SPMCSR ..............................................142
19.6 Reading Lock, Fuse and Signature Data from Software ...............................143
19.7 Preventing Flash Corruption ..........................................................................144
19.8 Programming Time for Flash when Using SPM .............................................145
19.9 Register Description ......................................................................................145
20 Memory Programming .........................................................................147
20.1 Program And Data Memory Lock Bits ...........................................................147
20.2 Fuse Bytes .....................................................................................................148
20.3 Device Signature Imprint Table .....................................................................149
20.4 Page Size ......................................................................................................150
20.5 Serial Downloading ........................................................................................151
20.6 High-voltage Serial Programming ..................................................................155
20.7 High-voltage Serial Programming Algorithm ..................................................155
21 Electrical Characteristics ....................................................................161
21.1 Absolute Maximum Ratings* .........................................................................161
21.2 DC Characteristics .........................................................................................161
21.3 Speed ............................................................................................................163
21.4 Clock Characteristics .....................................................................................164
21.5 System and Reset Characteristics ................................................................165
21.6 Brown-Out Detection .....................................................................................166
21.7 ADC Characteristics ......................................................................................167
21.8 Serial Programming Characteristics ..............................................................170
21.9 High-voltage Serial Programming Characteristics .........................................171
22 Typical Characteristics ........................................................................172
22.1 Active Supply Current ....................................................................................172
22.2 Idle Supply Current ........................................................................................175
22.3 Supply Current of I/O modules ......................................................................177
22.4 Power-down Supply Current ..........................................................................178
22.5 Pin Pull-up .....................................................................................................179
22.6 Pin Driver Strength ........................................................................................182
22.7 Pin Threshold and Hysteresis ........................................................................186
22.8 BOD Threshold ..............................................................................................189ATtiny25/45/85 [DATASHEET] v
2586Q–AVR–08/2013
22.9 Internal Oscillator Speed ...............................................................................192
22.10 Current Consumption of Peripheral Units ......................................................196
22.11 Current Consumption in Reset and Reset Pulsewidth ...................................198
23 Register Summary ................................................................................200
24 Instruction Set Summary .....................................................................202
25 Ordering Information ...........................................................................204
25.1 ATtiny25 ........................................................................................................204
25.2 ATtiny45 ........................................................................................................205
25.3 ATtiny85 ........................................................................................................206
26 Packaging Information .........................................................................207
26.1 8P3 ................................................................................................................207
26.2 8S2 ................................................................................................................208
26.3 S8S1 ..............................................................................................................209
26.4 8X ..................................................................................................................210
26.5 20M1 ..............................................................................................................211
27 Errata .....................................................................................................212
27.1 Errata ATtiny25 ..............................................................................................212
27.2 Errata ATtiny45 ..............................................................................................212
27.3 Errata ATtiny85 ..............................................................................................215
28 Datasheet Revision History .................................................................216
28.1 Rev. 2586Q-08/13 .........................................................................................216
28.2 Rev. 2586P-06/13 ..........................................................................................216
28.3 Rev. 2586O-02/13 .........................................................................................216
28.4 Rev. 2586N-04/11 .........................................................................................216
28.5 Rev. 2586M-07/10 .........................................................................................216
28.6 Rev. 2586L-06/10 ..........................................................................................216
28.7 Rev. 2586K-01/08 ..........................................................................................217
28.8 Rev. 2586J-12/06 ..........................................................................................218
28.9 Rev. 2586I-09/06 ...........................................................................................220
28.10 Rev. 2586H-06/06 .........................................................................................220
28.11 Rev. 2586G-05/06 .........................................................................................220
28.12 Rev. 2586F-04/06 ..........................................................................................220
28.13 Rev. 2586E-03/06 ..........................................................................................221
28.14 Rev. 2586D-02/06 .........................................................................................221
28.15 Rev. 2586C-06/05 .........................................................................................221ATtiny25/45/85 [DATASHEET] vi
2586Q–AVR–08/2013
28.16 Rev. 2586B-05/05 ..........................................................................................221
28.17 Rev. 2586A-02/05 ..........................................................................................221
Table of Contents.......................................................................................iATtiny25/45/85 [DATASHEET] vii
2586Q–AVR–08/2013Atmel Corporation
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San Jose, CA 95110
USA
Tel: (+1) (408) 441-0311
Fax: (+1) (408) 487-2600
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© 2013 Atmel Corporation. All rights reserved. / Rev.: 2586Q–AVR–08/2013
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this
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42330A-MCU-07/2014
USER GUIDE
Atmel-ICE
The Atmel-ICE Debugger
Atmel-ICE is a powerful development tool for debugging and programming
ARM®
Cortex®
-M based Atmel®
SAM and Atmel AVR
®
microcontrollers with OnChip
Debug capability.
It supports:
● Programming and on-chip debugging of all Atmel AVR 32-bit
microcontrollers on both JTAG and aWire interfaces
● Programming and on-chip debugging of all Atmel AVR XMEGA
®
family
devices on both JTAG and PDI 2-wire interfaces
● Programming (JTAG and SPI) and debugging of all Atmel AVR 8-bit
microcontrollers with OCD support on either JTAG or debugWIRE interfaces
● Programming and debugging of all Atmel SAM ARM Cortex-M based
microcontrollers on both SWD and JTAG interfaces
● Programming (TPI) of all Atmel tinyAVR
®
8-bit microcontrollers with support
for this interface
Consult the supported devices list in the Atmel Studio User Guide for a full list of
devices and interfaces supported by this firmware release.Atmel-ICE [USER GUIDE]
42330A-MCU-07/2014
2
Table of Contents
The Atmel-ICE Debugger ............................................................. 1
1. Introduction .............................................................................. 4
1.1. Introduction to the Atmel-ICE ................................................... 4
1.2. Atmel-ICE Features ............................................................... 4
1.3. System Requirements ............................................................ 4
2. Getting Started with the Atmel-ICE ......................................... 6
2.1. Full Kit Contents ................................................................... 6
2.2. Basic Kit Contents ................................................................. 6
2.3. PCBA Kit Contents ................................................................ 7
2.4. Spare Parts Kits .................................................................... 7
2.5. Kit Overview ......................................................................... 8
2.6. Assembling the Atmel-ICE ...................................................... 8
2.7. Opening the Atmel-ICE ......................................................... 10
2.8. Powering the Atmel-ICE ........................................................ 12
2.9. Connecting to the Host Computer ........................................... 12
2.10. USB Driver Installation ......................................................... 12
2.10.1. Windows ................................................................ 12
3. Connecting the Atmel-ICE .................................................... 13
3.1. Overview: Connecting to AVR and SAM Target Devices .............. 13
3.2. Connecting to a JTAG Target ................................................. 13
3.3. Connecting to an aWire Target ............................................... 14
3.4. Connecting to a PDI Target ................................................... 15
3.5. Connecting to a debugWIRE Target ........................................ 15
3.6. Connecting to a SPI Target ................................................... 16
3.7. Connecting to a TPI Target .................................................... 17
3.8. Connecting to a SWD Target ................................................. 17
4. On-Chip Debugging .............................................................. 19
4.1. Introduction to On-Chip Debugging (OCD) ................................ 19
4.2. Physical Interfaces ............................................................... 19
4.2.1. JTAG ..................................................................... 19
4.2.2. aWire .................................................................... 21
4.2.3. PDI Physical ........................................................... 22
4.2.4. debugWIRE ............................................................ 22
4.2.5. SPI ....................................................................... 22
4.2.6. TPI ....................................................................... 23
4.2.7. SWD ..................................................................... 23
4.3. Atmel OCD Implementations .................................................. 23
4.3.1. Atmel AVR UC3 OCD (JTAG and aWire) ...................... 23
4.3.2. Atmel AVR XMEGA OCD (JTAG and PDI Physical) ........ 24
4.3.3. Atmel megaAVR OCD (JTAG) .................................... 24
4.3.4. Atmel megaAVR / tinyAVR OCD (debugWIRE) .............. 24
4.3.5. ARM Coresight Components ..................................... 24
5. Hardware Description ............................................................ 25
5.1. LEDs ................................................................................. 25
5.2. Rear Panel ......................................................................... 25
5.3. Bottom Panel ...................................................................... 25
5.4. Architecture Description ........................................................ 26
5.4.1. Atmel-ICE Mainboard ............................................... 26
5.4.2. Atmel-ICE Target Connectors ..................................... 27
5.4.3. Atmel-ICE target Connectors Part Numbers .................. 27
6. Software Integration .............................................................. 28
6.1. Atmel Studio ....................................................................... 28
6.1.1. Software Integration in Atmel Studio ............................ 28
6.1.2. Programming Options ............................................... 28
6.1.3. Debug Options ........................................................ 28Atmel-ICE [USER GUIDE]
42330A-MCU-07/2014
3
7. Command Line Utility ............................................................ 30
8. Advanced Debugging Techniques ........................................ 31
8.1. Atmel AVR UC3 Targets ....................................................... 31
8.1.1. EVTI / EVTO Usage ................................................. 31
8.2. debugWIRE Targets ............................................................. 31
8.2.1. Software Breakpoints ............................................... 31
9. Special Considerations ......................................................... 32
9.1. Atmel AVR XMEGA OCD ...................................................... 32
9.2. Atmel megaAVR OCD and debugWIRE OCD ............................ 32
9.2.1. Atmel megaAVR OCD (JTAG) .................................... 33
9.2.2. debugWIRE OCD .................................................... 34
9.3. Atmel AVR UC3 OCD ........................................................... 35
9.4. SAM / Coresight OCD .......................................................... 35
10. Firmware Upgrade ................................................................ 37
11. Release History and Known issues ...................................... 38
11.1. What's New ........................................................................ 38
11.2. Firmware Release History ..................................................... 38
11.2.1. Atmel Studio 6.2 ..................................................... 38
11.2.2. Atmel Studio 6.2 (beta)2 ........................................... 38
11.3. Known Issues Concerning the Atmel-ICE ................................. 38
11.3.1. Atmel AVR XMEGA OCD Specific Issues ..................... 38
11.3.2. Atmel megaAVR OCD and Atmel tinyAVR OCD
Specific Issues ........................................................ 38
11.4. Device Support ................................................................... 38
12. Product Compliance .............................................................. 39
12.1. RoHS and WEEE ................................................................ 39
12.2. CE and FCC ...................................................................... 39
13. Document Revisions ............................................................. 40Atmel-ICE [USER GUIDE]
42330A-MCU-07/2014
4
1. Introduction
1.1 Introduction to the Atmel-ICE
Atmel-ICE is a powerful development tool for debugging and programming ARM Cortex-M based Atmel SAM
and Atmel AVR microcontrollers with On-Chip Debug capability.
It supports:
● Programming and on-chip debugging of all Atmel AVR UC3 microcontrollers on both JTAG and aWire
interfaces
● Programming and on-chip debugging of all AVR XMEGA family devices on both JTAG and PDI 2-wire
interfaces
● Programming (JTAG and SPI) and debugging of all AVR 8-bit microcontrollers with OCD support on both
JTAG or debugWIRE interfaces
● Programming and debugging of all Atmel SAM ARM Cortex-M based microcontrollers on both SWD and
JTAG interfaces
● Programming (TPI) of all Atmel tinyAVR 8-bit microcontrollers with support for this interface
1.2 Atmel-ICE Features
● Fully compatible with Atmel Studio
● Supports programming and debugging of all Atmel AVR UC3 32-bit microcontrollers
● Supports programming and debugging of all 8-bit AVR XMEGA devices
● Supports programming and debugging of all 8-bit Atmel megaAVR
®
and tinyAVR devices with OCD
● Supports programming and debugging of all SAM ARM Cortex-M based microcontrollers
● Target operating voltage range of 1.62V to 5.5V
● Draws less than 3mA from target VTref when using debugWIRE interface and less than 1mA for all other
interfaces
● Supports JTAG clock frequencies from 32kHz to 7.5MHz
● Supports PDI clock frequencies from 32kHz to 7.5MHz
● Supports debugWIRE baud rates from 4kbit/s to 0.5Mbit/s
● Supports aWire baud rates from 7.5kbit/s to 7Mbit/s
● Supports SPI clock frequencies from 8kHz to 5MHz
● Supports SWD clock frequencies from 32kHz to 2MHz
● USB 2.0 high-speed host interface
● ITM serial trace capture at up to 3MB/s
● Supports 10-pin 50-mil JTAG connector with both AVR and Cortex pinouts. The standard probe cable
supports AVR 6-pin ISP/PDI/TPI 100-mil headers as well as 10-pin 50-mil. An adapter is available to
support 6-pin 50-mil, 10-pin 100-mil and 20-pin 100-mil headers. Several kit options are available with
different cabling and adapters.
1.3 System Requirements
The Atmel-ICE unit requires that a front-end debugging environment Atmel Studio version 6.2 or later is
installed on your computer.Atmel-ICE [USER GUIDE]
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The Atmel-ICE should be connected to the host computer using the USB cable provided, or a certified USBmicro
cable.Atmel-ICE [USER GUIDE]
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2. Getting Started with the Atmel-ICE
2.1 Full Kit Contents
The Atmel-ICE full kit contains these items:
● Atmel-ICE unit
● USB cable (1.8m, high-speed, micro-B)
● Adapter board containing 50-mil AVR, 100-mil AVR/SAM and 100-mil 20-pin SAM adapters
● IDC flat cable with 10-pin 50-mil connector and 6-pin 100-mil connector
● 50-mil 10-pin mini squid cable with 10 x 100-mil sockets
Figure 2-1. Atmel-ICE Full Kit Contents
2.2 Basic Kit Contents
The Atmel-ICE basic kit contains these items:
● Atmel-ICE unit
● USB cable (1.8m, high-speed, micro-B)
● IDC flat cable with 10-pin 50-mil connector and 6-pin 100-mil connectorAtmel-ICE [USER GUIDE]
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Figure 2-2. Atmel-ICE Basic Kit Contents
2.3 PCBA Kit Contents
The Atmel-ICE PCBA kit contains these items:
● Atmel-ICE unit without plastic encaptulation
Figure 2-3. Atmel-ICE PCBA Kit Contents
2.4 Spare Parts Kits
The following spare parts kits are available:
● Adapter kit
● Cable kitAtmel-ICE [USER GUIDE]
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Figure 2-4. Atmel-ICE Adapter Kit Contents
Figure 2-5. Atmel-ICE Cable Kit Contents
2.5 Kit Overview
The Atmel-ICE kit options are shown diagrammatically here:
Figure 2-6. Atmel-ICE Kit Overview
PCBA
PCBA kit
basic kit
adapter kit
full kit
SAM AVR
cable kit
2.6 Assembling the Atmel-ICE
The Atmel-ICE unit is shipped with no cables attached. Two cable options are provided in the full kit:
● 50-mil 10-pin IDC flat cable with 6-pin ISP and 10-pin connectorsAtmel-ICE [USER GUIDE]
42330A-MCU-07/2014
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● 50-mil 10-pin mini-squid cable with 10 x 100-mil sockets
Figure 2-7. Atmel-ICE Cables
For most purposes, the 50-mil 10-pin IDC flat cable can be used, connecting either natively to its 10-pin or 6-
pin connectors, or connecting via the adapter board. Three adapters are provided on one small PCBA. The
following adapters are included:
● 100-mil 10-pin JTAG/SWD adapter
● 100-mil 20-pin SAM JTAG/SWD adapter
● 50-mil 6-pin SPI/debugWIRE/PDI/aWire adapter
Figure 2-8. Atmel-ICE Adapters
Note A 50-mil JTAG adapter has not been provided - this is because the 50-mil 10-pin IDC cable can
be used to connect directly to a 50-mil JTAG header. For the part number of the component used
for the 50-mil 10-pin connector, see “Atmel-ICE target Connectors Part Numbers” on page 27.
The 6-pin ISP/PDI header is included as part of the 10-pin IDC cable. This termination can be cut off if it is not
required.
To assemble your Atmel-ICE into its default configuration, connect the 10-pin 50-mil IDC cable to the unit as
shown below. Be sure to orient the cable so that the red wire (pin 1) on the cable aligns with the triangular
indicator on the blue belt of the enclosure. The cable should connect upwards from the unit. Be sure to connect
to the port corresponding to the pinout of your target - AVR or SAM.
Figure 2-9. Atmel-ICE Cable ConnectionAtmel-ICE [USER GUIDE]
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Figure 2-10. Atmel-ICE AVR Probe Connection
Figure 2-11. Atmel-ICE SAM Probe Connection
2.7 Opening the Atmel-ICE
Note For normal operation, the Atmel-ICE unit must not be opened. Opening the unit is done at your
own risk. Anti-static precautions should be taken.
The Atmel-ICE enclosure consists of three separate plastic components - top cover, bottom cover and blue
belt - which are snapped together during assembly. To open the unit, simply insert a large flat screwdriver into
the openings in the blue belt, apply some inward pressure and twist gently. Repeat the process on the other
snapper holes, and the top cover will pop off.Atmel-ICE [USER GUIDE]
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Figure 2-12. Opening the Atmel-ICE (1)
Figure 2-13. Opening the Atmel-ICE (2)Atmel-ICE [USER GUIDE]
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Figure 2-14. Opening the Atmel-ICE(3)
To close the unit again, simply align the top and bottom covers correctly, and press together firmly.
2.8 Powering the Atmel-ICE
The Atmel-ICE is powered by the USB bus voltage. It requires less than 100mA to operate, and can therefore
be powered through a USB hub. The power LED will illuminate when the unit is plugged in. When not
connected in an active programming or debugging session, the unit will enter low-power consumption mode to
preserve your computer's battery. The Atmel-ICE cannot be powered down - it should be unplugged when not
in use.
2.9 Connecting to the Host Computer
The Atmel-ICE communicates primarily using a standard HID interface, and does not require a special driver on
the host computer. To use the advanced data gateway functionality of the Atmel-ICE, be sure to install the USB
driver on the host computer. This is done automatically when installing the front-end software provided free by
Atmel. See www.atmel.com
1
for further information or to download the latest front-end software.
The Atmel-ICE must be connected to an available USB port on the host computer using the USB cable
provided, or suitable USB certified micro cable. The Atmel-ICE contains a USB 2.0 compliant controller, and
can operate in both full-speed and high-speed modes. For best results, connect the Atmel-ICE directly to a
USB 2.0 compliant high-speed hub on the host computer using the cable provided.
2.10 USB Driver Installation
2.10.1 Windows
When installing the Atmel-ICE on a computer running Microsoft®
Windows®
, the USB driver is loaded when the
Atmel-ICE is first plugged in.
Note Be sure to install the front-end software packages before plugging the unit in for the first time.
Once successfully installed, the Atmel-ICE will appear in the device manager as a "Human Interface Device".
1
http://www.atmel.com/Atmel-ICE [USER GUIDE]
42330A-MCU-07/2014
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3. Connecting the Atmel-ICE
3.1 Overview: Connecting to AVR and SAM Target Devices
The Atmel-ICE probe has two 50-mil 10-pin JTAG connectors accessible on the front of the tool's enclosure.
Both connectors are directly electrically connected, but conform to two different pinouts - the AVR JTAG header
and the ARM Cortex Debug header. The connector should be selected based on the pinout of the target board,
and not the target MCU type - for example a SAM device mounted in a AVR STK600 stack should use the AVR
header.
Various cabling and adapters are available in the different Atmel-ICE kits. An overview of connection options is
shown.
Figure 3-1. Atmel-ICE Connection Options
6-pin 100-mil AVR ISP/
debugWIRE/PDI/aWire/
TPI header
10-pin 100-mil AVR
JTAG header
10-pin 50-mil AVR
JTAG header
SAM AVR
20-pin 100-mil SAM
header
(for EVKs etc)
10-pin 100-mil
JTAG/SWD header
10-pin 50-mil JTAG/SWD
(Cortex debug header)
SAM AVR
6-pin 50-mil AVR ISP/
debugWIRE/PDI/aWire/
TPI header
3.2 Connecting to a JTAG Target
The Atmel-ICE probe has two 50-mil 10-pin JTAG connectors accessible on the front of the tool's enclosure.
Both connectors are directly electrically connected, but conform to two different pinouts - the AVR JTAG header
and the ARM Cortex Debug header. The connector should be selected based on the pinout of the target board,
and not the target MCU type - for example a SAM device mounted in a AVR STK600 stack should use the AVR
header.
The recommended pinout for the 10-pin AVR JTAG connector is shown in Figure 4-2, “AVR JTAG Header
Pinout” on page 20.
The recommended pinout for the 10-pin ARM Cortex Debug connector is shown in Figure 4-3, “SAM JTAG
Header Pinout” on page 20.
Direct connection to a standard 10-pin 50-mil header
Use the 50-mil 10-pin flat cable (included in some kits) to connect directly to a board supporting this header
type. Use the AVR connector port on the Atmel-ICE for headers layed out in the AVR pinout, and the SAM
connector port for headers complying with the ARM Cortex Debug header pinout.
The pinouts for both 10-pin connector ports are shown below.
Connection to a standard 10-pin 100-mil header
Use a standard 50-mil to 100-mil adapter to connect to 100-mil headers. An adapter board (included in some
kits) can be used for this purpose, or alternatively the JTAGICE3 adapter can be used for AVR targets.Atmel-ICE [USER GUIDE]
42330A-MCU-07/2014
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Note The JTAGICE3 100-mil adapter cannot be used with the SAM connector port, since pins 2 and 10
(AVR GND) on the adapter are connected.
Connection to a custom 100-mil header
If your target board does not have a compliant 10-pin JTAG header in 50- or 100-mil, you can map to a custom
pinout using the 10-pin "mini-squid" cable (included in some kits), which gives access to ten individual 100-mil
sockets.
Connection to a 20-pin 100-mil header
Use the adapter board (included in some kits) to connect to targets with a 20-pin 100-mil header.
Table 3-1. Atmel-ICE JTAG Pin Description
Name AVR
port
pin
SAM
port
pin
Description
TCK 1 4 Test Clock (clock signal from the Atmel-ICE into the target device).
TMS 5 2 Test Mode Select (control signal from the Atmel-ICE into the target device).
TDI 9 8 Test Data In (data transmitted from the Atmel-ICE into the target device).
TDO 3 6 Test Data Out (data transmitted from the target device into the Atmel-ICE).
nTRST 8 - Test Reset (optional, only on some AVR devices). Used to reset the JTAG
TAP controller.
nSRST 6 10 Reset (optional) Used to reset the target device. Connecting this pin is
recommended since it allows the Atmel-ICE to hold the target device in a
reset state, which can be essential to debugging in certain scenarios.
VTG 4 1 Target voltage reference. The Atmel-ICE samples the target voltage on this
pin in order to power the level converters correctly. The Atmel-ICE draws
less than 3mA from this pin in debugWIRE mode and less than 1mA in other
modes.
GND 2, 10 3, 5, 9 Ground. All must be connected to ensure that the Atmel-ICE and the target
device share the same ground reference.
3.3 Connecting to an aWire Target
The aWire interface only requires one data line in addition to Vcc and GND. On the target this line is the
nRESET line, although the debugger uses the JTAG TDO line as the data line.
The recommended pinout for the 6-pin aWire connector is shown in Figure 4-5, “aWire Header
Pinout” on page 22.
Connection to a 6-pin 100-mil aWire header
Use the 6-pin 100-mil tap on the flat cable (included in some kits) to connect to a standard 100-mil aWire
header.
Connection to a 6-pin 50-mil aWire header
Use the adapter board (included in some kits) to connect to a standard 50-mil aWire header.
Connection to a custom 100-mil header
The 10-pin mini-squid cable should be used to connect between the Atmel-ICE AVR connector port and the
target board. Three connections are required, as described in the table below.
Table 3-2. Atmel-ICE aWire Pin Mapping
Atmel-ICE AVR port
pins
Target pins Mini-squid pin aWire pinout
Pin 1 (TCK) 1
Pin 2 (GND) GND 2 6Atmel-ICE [USER GUIDE]
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Atmel-ICE AVR port
pins
Target pins Mini-squid pin aWire pinout
Pin 3 (TDO) DATA 3 1
Pin 4 (VTG) VTG 4 2
Pin 5 (TMS) 5
Pin 6 (nSRST) 6
Pin 7 (Not connected) 7
Pin 8 (nTRST) 8
Pin 9 (TDI) 9
Pin 10 (GND) 0
3.4 Connecting to a PDI Target
The recommended pinout for the 6-pin PDI connector is shown in Figure 4-6, “PDI Header
Pinout” on page 22.
Connection to a 6-pin 100-mil PDI header
Use the 6-pin 100-mil tap on the flat cable (included in some kits) to connect to a standard 100-mil PDI header.
Connection to a 6-pin 50-mil PDI header
Use the adapter board (included in some kits) to connect to a standard 50-mil PDI header.
Connection to a custom 100-mil header
The 10-pin mini-squid cable should be used to connect between the Atmel-ICE AVR connector port and the
target board. Four connections are required, as described in the table below.
Note There is a difference from the JTAGICE mkII JTAG probe, where PDI_DATA is connected to pin 9.
The Atmel-ICE is compatible with the pinout used by the JTAGICE3, AVR ONE! and AVR Dragon
products.
Table 3-3. Atmel-ICE PDI Pin Mapping
Atmel-ICE AVR port
pin
Target pins Mini-squid pin Atmel STK600 PDI
pinout
Pin 1 (TCK) 1
Pin 2 (GND) GND 2 6
Pin 3 (TDO) PDI_DATA 3 1
Pin 4 (VTG) VTG 4 2
Pin 5 (TMS) 5
Pin 6 (nSRST) PDI_CLK 6 5
Pin 7 (Not connected) 7
Pin 8 (nTRST) 8
Pin 9 (TDI) 9
Pin 10 (GND) 0
3.5 Connecting to a debugWIRE Target
The recommended pinout for the 6-pin debugWIRE (SPI) connector is shown in Figure 4-7, “debugWIRE (SPI)
Header Pinout” on page 22.
Connection to a 6-pin 100-mil SPI header
Use the 6-pin 100-mil tap on the flat cable (included in some kits) to connect to a standard 100-mil SPI header.Atmel-ICE [USER GUIDE]
42330A-MCU-07/2014
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Connection to a 6-pin 50-mil SPI header
Use the adapter board (included in some kits) to connect to a standard 50-mil SPI header.
Connection to a custom 100-mil header
The 10-pin mini-squid cable should be used to connect between the Atmel-ICE AVR connector port and
the target board. Three connections are required, as described in Table 3-4, “Atmel-ICE debugWIRE Pin
Mapping” on page 16.
Although the debugWIRE interface only requires one signal line (RESET), Vcc and GND to operate correctly,
it is advised to have access to the full SPI connector so that the debugWIRE interface can be enabled and
disabled using SPI programming.
When the DWEN fuse is enabled the SPI interface is overridden internally in order for the OCD module to have
control over the RESET pin. The debugWIRE OCD is capable of disabling itself temporarily (using the button
on the debugging tab in the properties dialog in Atmel Studio), thus releasing control of the RESET line. The
SPI interface is then available again (only if the SPIEN fuse is programmed), allowing the DWEN fuse to be
un-programmed using the SPI interface. If power is toggled before the DWEN fuse is un-programmed, the
debugWIRE module will again take control of the RESET pin.
Note It is highly advised to simply let Atmel Studio handle setting and clearing of the DWEN fuse.
It is not possible to use the debugWIRE interface if the lockbits on the target AVR device are programmed.
Always be sure that the lockbits are cleared before programming the DWEN fuse and never set the lockbits
while the DWEN fuse is programmed. If both the debugWIRE enable fuse (DWEN) and lockbits are set,
one can use High Voltage Programming to do a chip erase, and thus clear the lockbits. When the lockbits
are cleared the debugWIRE interface will be re-enabled. The SPI Interface is only capable of reading fuses,
reading signature and performing a chip erase when the DWEN fuse is un-programmed.
Table 3-4. Atmel-ICE debugWIRE Pin Mapping
Atmel-ICE AVR port pin Target pins Mini-squid pin
Pin 1 (TCK) 1
Pin 2 (GND) GND 2
Pin 3 (TDO) 3
Pin 4 (VTG) VTG 4
Pin 5 (TMS) 5
Pin 6 (nSRST) RESET 6
Pin 7 (Not connected) 7
Pin 8 (nTRST) 8
Pin 9 (TDI) 9
Pin 10 (GND) 0
3.6 Connecting to a SPI Target
The recommended pinout for the 6-pin SPI connector is shown in Figure 4-8, “SPI Header
Pinout” on page 23.
Connection to a 6-pin 100-mil SPI header
Use the 6-pin 100-mil tap on the flat cable (included in some kits) to connect to a standard 100-mil SPI header.
Connection to a 6-pin 50-mil SPI header
Use the adapter board (included in some kits) to connect to a standard 50-mil SPI header.
Connection to a custom 100-mil header
The 10-pin mini-squid cable should be used to connect between the Atmel-ICE AVR connector port and the
target board. Six connections are required, as described in the table below.Atmel-ICE [USER GUIDE]
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Note The SPI interface is effectively disabled when the debugWIRE enable fuse (DWEN) is
programmed, even if SPIEN fuse is also programmed. To re-enable the SPI interface, the 'disable
debugWIRE' command must be issued while in a debugWIRE debugging session. Disabling
debugWIRE in this manner requires that the SPIEN fuse is already programmed. If Atmel Studio
fails to disable debugWIRE, it is probable that the SPIEN fuse is NOT programmed. If this is the
case, it is necessary to use a high-voltage programming interface to program the SPIEN fuse.
Table 3-5. Atmel-ICE SPI Pin Mapping
Atmel-ICE AVR port
pins
Target pins Mini-squid pin SPI pinout
Pin 1 (TCK) SCK 1 3
Pin 2 (GND) GND 2 6
Pin 3 (TDO) MISO 3 1
Pin 4 (VTG) VTG 4 2
Pin 5 (TMS) 5
Pin 6 (nSRST) /RESET 6 5
Pin 7 (Not connected) 7
Pin 8 (nTRST) 8
Pin 9 (TDI) MOSI 9 4
Pin 10 (GND) 0
3.7 Connecting to a TPI Target
The recommended pinout for the 6-pin TPI connector is shown in Figure 4-9, “TPI Header
Pinout” on page 23.
Connection to a 6-pin 100-mil TPI header
Use the 6-pin 100-mil tap on the flat cable (included in some kits) to connect to a standard 100-mil TPI header.
Connection to a 6-pin 50-mil TPI header
Use the adapter board (included in some kits) to connect to a standard 50-mil TPI header.
Connection to a custom 100-mil header
The 10-pin mini-squid cable should be used to connect between the Atmel-ICE AVR connector port
and the target board. Six connections are required, as described in Table 3-6, “Atmel-ICE TPI Pin
Mapping” on page 17.
Table 3-6. Atmel-ICE TPI Pin Mapping
Atmel-ICE AVR port
pins
Target pins Mini-squid pin TPI pinout
Pin 1 (TCK) CLOCK 1 3
Pin 2 (GND) GND 2 6
Pin 3 (TDO) DATA 3 1
Pin 4 (VTG) VTG 4 2
Pin 5 (TMS) 5
Pin 6 (nSRST) /RESET 6 5
Pin 7 (Not connected) 7
Pin 8 (nTRST) 8
Pin 9 (TDI) 9
Pin 10 (GND) 0
3.8 Connecting to a SWD TargetAtmel-ICE [USER GUIDE]
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The ARM SWD interface is s subset of the JTAG interface, making use of TCK and TMS pins, which means
that when connecting to an SWD device, the 10-pin JTAG connector can technically be used. The ARM JTAG
and AVR JTAG connectors are however not pin-compatible, so this depends upon the layout of the target board
in use. When using STK600 or a board making use of the AVR JTAG pinout, the AVR connector port on the
Atmel-ICE must be used. When connecting to a board which makes use of the ARM JTAG pinout, the SAM
connector port on the Atmel-ICE must be used.
The recommended pinout for the 10-pin Cortex Debug connector is shown in Figure 4-10, “Recommended
ARM SWD/JTAG Header Pinout” on page 23.
Connection to a 10-pin 50-mil Cortex header
Use the flat cable (included in some kits) to connect to a standard 50-mil Cortex header.
Connection to a 10-pin 100-mil Cortex-layout header
Use the adapter board (included in some kits) to connect to a 100-mil Cortex-pinout header.
Connection to a 20-pin 100-mil SAM header
Use the adapter board (included in some kits) to connect to a 20-pin 100-mil SAM header.
Connection to a custom 100-mil header
The 10-pin mini-squid cable should be used to connect between the Atmel-ICE AVR or SAM connector port
and the target board. Six connections are required, as described in the table below.
Table 3-7. Atmel-ICE SWD Pin Mapping
Name AVR
port
pin
SAM
port
pin
Description
SWDCLK 1 4 Serial Wire Debug Clock.
SWDIO 5 2 Serial Wire Debug Data Input/Output.
SWO 3 6 Serial Wire Output (optional- not implemented on all devices).
nSRST 6 10 Reset.
VTG 4 1 Target voltage reference.
GND 2, 10 3, 5 Ground.Atmel-ICE [USER GUIDE]
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4. On-Chip Debugging
4.1 Introduction to On-Chip Debugging (OCD)
A traditional Emulator is a tool which tries to imitate the exact behaviour of a target device. The closer this
behaviour is to the actual device’s behaviour, the better the emulation will be.
The Atmel-ICE is not a traditional Emulator. Instead, the Atmel-ICE interfaces with the internal On-Chip Debug
system inside the target device, providing a mechanism for monitoring and controlling its execution. In this way
the application being debugged is not emulated, but actually executed on the real target device.
With an OCD system, the application can be executed whilst maintaining exact electrical and timing
characteristics in the target system – something not technically realisable with a traditional emulator.
Run Mode
When in Run mode, the execution of code is completely independent of the Atmel-ICE. The Atmel-ICE will
continuously monitor the target device to see if a break condition has occurred. When this happens the OCD
system will interrogate the device through its debug interface, allowing the user to view the internal state of the
device.
Stopped Mode
When a breakpoint is reached, program execution is halted, but all I/O will continue to run as if no breakpoint
had occurred. For example assume that a USART transmit has just been initiated when a breakpoint is
reached. In this case the USART continues to run at full speed completing the transmission, even though the
core is in stopped mode.
Hardware Breakpoints
The target OCD module contains a number of program counter comparators implemented in hardware. When
the program counter matches the value stored in one of the comparator registers, the OCD enters stopped
mode. Since hardware breakpoints require dedicated hardware on the OCD module, the number of breakpoints
available depends upon the size of the OCD module implemented on the target. Usually one such hardware
comparator is ‘reserved’ by the debugger for internal use. For more information on the hardware breakpoints
available in the various OCD modules, see “Atmel OCD Implementations” on page 23 .
Software Breakpoints
A software breakpoint is a BREAK instruction placed in program memory on the target device. When this
instruction is loaded, program execution will break and the OCD enters stopped mode. To continue execution
a "start" command has to be given from the OCD. Not all AVR devices have OCD modules supporting the
BREAK instruction. For more information on the software breakpoints available in the various OCD modules,
see “Atmel OCD Implementations” on page 23.
For further information on the considerations and restrictions when using an OCD system, see “Special
Considerations” on page 32.
4.2 Physical Interfaces
The Atmel-ICE supports several hardware interfaces as described in the following sections.
4.2.1 JTAG
The JTAG interface consists of a 4-wire Test Access Port (TAP) controller that is compliant with the IEEE
1149.1 standard. The IEEE standard was developed to provide an industry-standard way to efficiently test
circuit board connectivity (Boundary Scan). Atmel AVR and SAM devices have extended this functionality to
include full Programming and On-Chip Debugging support.
Figure 4-1. JTAG Interface Basics
Atmel
target device
Atmel-ICE
Vcc
TMS
TDI
TDO
TCKAtmel-ICE [USER GUIDE]
42330A-MCU-07/2014
20
When designing an application PCB which includes an Atmel AVR with the JTAG interface, it is recommended
to use the pinout as shown in Figure 4-2, “AVR JTAG Header Pinout” on page 20. The Atmel-ICE can
connect to both 100-mil and 50-mil variants of this pinout.
Figure 4-2. AVR JTAG Header Pinout
GND
VCC
/RESET
(TRST)
GND
TCK
TDO
TMS
TDI
1 2
AVR JTAG
(NC)
Table 4-1. AVR JTAG Pin Description
Name Pin Description
TCK 1 Test Clock (clock signal from the Atmel-ICE into the target device).
TMS 5 Test Mode Select (control signal from the Atmel-ICE into the target device).
TDI 9 Test Data In (data transmitted from the Atmel-ICE into the target device).
TDO 3 Test Data Out (data transmitted from the target device into the Atmel-ICE).
nTRST 8 Test Reset (optional, only on some AVR devices). Used to reset the JTAG TAP
controller.
nSRST 6 Reset (optional) Used to reset the target device. Connecting this pin is recommended
since it allows the Atmel-ICE to hold the target device in a reset state, which can be
essential to debugging in certain scenarios.
VTG 4 Target voltage reference. The Atmel-ICE samples the target voltage on this pin in
order to power the level converters correctly. The Atmel-ICE draws less than 3mA
from this pin in debugWIRE mode and less than 1mA in other modes.
GND 2, 10 Ground. Both must be connected to ensure that the Atmel-ICE and the target device
share the same ground reference.
Tip Remember to include a decoupling capacitor between pin 4 and GND.
When designing an application PCB which includes an Atmel SAM with the JTAG interface, it is recommended
to use the pinout as shown in Figure 4-3, “SAM JTAG Header Pinout” on page 20. The Atmel-ICE can
connect to both 100-mil and 50-mil variants of this pinout.
Figure 4-3. SAM JTAG Header Pinout
TMS
TCK
TDO
TDI
nRESET
VCC
GND
GND
(KEY)
GND
1 2
SAM JTAG
Table 4-2. SAM JTAG pin description
Name Pin Description
TCK 4 Test Clock (clock signal from the Atmel-ICE into the target device).
TMS 3 Test Mode Select (control signal from the Atmel-ICE into the target device).
TDI 8 Test Data In (data transmitted from the Atmel-ICE into the target device).
TDO 6 Test Data Out (data transmitted from the target device into the Atmel-ICE).
nRESET 10 Reset (optional) Used to reset the target device. Connecting this pin is recommended
since it allows the Atmel-ICE to hold the target device in a reset state, which can be
essential to debugging in certain scenarios.Atmel-ICE [USER GUIDE]
42330A-MCU-07/2014
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Name Pin Description
VTG 1 Target voltage reference. The Atmel-ICE samples the target voltage on this pin in
order to power the level converters correctly. The Atmel-ICE draws less than 3mA
from this pin in debugWIRE mode and less than 1mA in other modes.
GND 3, 5, 9 Ground. All must be connected to ensure that the Atmel-ICE and the target device
share the same ground reference.
KEY 7 Connected internally to TRST pin on the AVR connector. Recommended as not
connected.
Tip Remember to include a decoupling capacitor between pin 4 and GND.
The JTAG interface allows for several devices to be connected to a single interface in a daisy-chain
configuration. The target devices must all be powered by the same supply voltage, share a common ground
node, and must be connected as shown in Figure 4-4, “JTAG Daisy-Chain” on page 21.
Figure 4-4. JTAG Daisy-Chain
target
device
1
Atmel-ICE
TMS
TDI
TDO
TCK
target
device
2
target
device
3
When connecting devices in a daisy-chain, the following points must be considered:
● All devices must share a common ground, connected to GND on the Atmel-ICE probe
● All devices must be operating on the same target voltage. VTG on the Atmel-ICE must be connected to this
voltage
● TMS and TCK are connected in parallel; TDI and TDO are connected in a serial chain
● nSRST on the Atmel-ICE probe must be connected to RESET on the devices if any one of the devices in
the chain disables its JTAG port
● "Devices before" refers to the number of JTAG devices that the TDI signal has to pass through in the daisy
chain before reaching the target device. Similarly "devices after" is the number of devices that the signal
has to pass through after the target device before reaching the Atmel-ICE TDO pin
● "Instruction bits before" and "after" refers to the sum total of all JTAG devices' instruction register lengths
which are connected before and after the target device in the daisy chain
● The total IR length (instruction bits before + Atmel AVR IR length + instruction bits after) is limited to a
maximum of 256 bits. The number of devices in the chain is limited to 15 before and 15 after
Tip Daisy chaining example: TDI → ATmega1280 → ATxmega128A1 → ATUC3A0512 → TDO
In order to connect to the Atmel AVR XMEGA device, the daisy chain settings are:
● Devices before: 1
● Devices after: 1
● Instruction bits before: 4 (8-bit AVR devices have 4 IR bits)
● Instruction bits after: 5 (32-bit AVR devices have 5 IR bits)
4.2.2 aWireAtmel-ICE [USER GUIDE]
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The aWire interface makes use the RESET wire of the AVR device to allow programming and debugging
functions. A special enable sequence is transmitted by the Atmel-ICE which disables the default RESET
functionality of the pin.
When designing an application PCB which includes an Atmel AVR with the aWire interface, it is recommended
to use the pinout as shown in Figure 4-5, “aWire Header Pinout” on page 22. The Atmel-ICE ships with both
100-mil and 50-mil adapters supporting this pinout.
Figure 4-5. aWire Header Pinout
(RESET_N) DATA VCC
GND
1 2
aWire
(NC)
(NC)
(NC)
Tip Since aWire is a half-duplex interface, a pull-up resistor on the RESET line in the order of 47k is
recommended to avoid false start-bit detection when changing direction.
The aWire interface can be used as both a programming and debugging interface, all features of the OCD
system available through the 10-pin JTAG interface can also be accessed using aWire.
4.2.3 PDI Physical
The Program and Debug Interface (PDI) is an Atmel proprietary interface for external programming and onchip
debugging of a device. PDI Physical is a 2-pin interface providing a bi-directional half-duplex synchronous
communication with the target device.
When designing an application PCB which includes an Atmel AVR with the PDI interface, the pinout shown in
Figure 4-6, “PDI Header Pinout” on page 22 should be used. One of the 6-pin adapters provided with the
Atmel-ICE kit can then be used to connect the Atmel-ICE probe to the application PCB.
Figure 4-6. PDI Header Pinout
PDI_DATA
PDI_CLK
VCC
GND
1 2
PDI
(NC) (NC)
4.2.4 debugWIRE
The debugWIRE interface was developed by Atmel for use on low pin-count devices. Unlike the JTAG interface
which uses four pins, debugWIRE makes use of just a single pin (RESET) for bi-directional half-duplex
asynchronous communication with the debugger tool.
When designing an application PCB which includes an Atmel AVR with the debugWIRE interface, the pinout
shown in Figure 4-7, “debugWIRE (SPI) Header Pinout” on page 22 should be used.
Figure 4-7. debugWIRE (SPI) Header Pinout
PDO/MISO
SCK
/RESET
VCC
PDI/MOSI
GND
1 2
SPI
Note The debugWIRE interface can not be used as a programming interface. This means that the SPI
interface must also be available (as shown in Figure 4-8, “SPI Header Pinout” on page 23) in
order to program the target.
When the debugWIRE enable (DWEN) fuse is programmed and lock-bits are un-programmed, the debugWIRE
system within the target device is activated. The RESET pin is configured as a wire-AND (open-drain)
bi-directional I/O pin with pull-up enabled and becomes the communication gateway between target and
debugger.
4.2.5 SPIAtmel-ICE [USER GUIDE]
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In-System Programming uses the target Atmel AVR’s internal SPI (Serial Peripheral Interface) to
download code into the flash and EEPROM memories. It is not a debugging interface. When designing an
application PCB which includes an AVR with the SPI interface, the pinout shown in Figure 4-8, “SPI Header
Pinout” on page 23 should be used.
Figure 4-8. SPI Header Pinout
PDO/MISO
SCK
/RESET
VCC
PDI/MOSI
GND
1 2
SPI
4.2.6 TPI
TPI is a programming-only interface for some AVR ATtiny devices. It is not a debugging interface, and these
devices to not have OCD capability. When designing an application PCB which includes an AVR with the TPI
interface, the pinout shown in Figure 4-9, “TPI Header Pinout” on page 23 should be used.
Figure 4-9. TPI Header Pinout
TPIDATA
TPICLK
/RESET
VCC
GND
1 2
TPI
(NC)
4.2.7 SWD
The ARM SWD interface is a subset of the JTAG interface, making use of TCK and TMS pins. The ARM JTAG
and AVR JTAG connectors are however not pin-compatible, so when designing an application PCB which uses
a SAM device with SWD or JTAG interface, it is recommended to use the ARM pinout shown in Figure 4-10,
“Recommended ARM SWD/JTAG Header Pinout” on page 23. The SAM connector port on the Atmel-ICE
can connect directly to this pinout.
Figure 4-10. Recommended ARM SWD/JTAG Header Pinout
SWDIO
SWDCLK
SWO
nRESET
VCC
GND
GND
(KEY)
GND
1 2
SAM SWD
(NC)
The Atmel-ICE is capable of streaming UART-format ITM trace to the host computer. Trace is captured on the
TRACE/SWO pin of the 10-pin header (JTAG TDO pin). Data is buffered internally on the Atmel-ICE and is sent
over the HID interface to the host computer. The maximum reliable data rate is about 3MB/s.
4.3 Atmel OCD Implementations
4.3.1 Atmel AVR UC3 OCD (JTAG and aWire)
The Atmel AVR UC3 OCD system is designed in accordance with the Nexus 2.0 standard (IEEE-ISTO
5001™-2003), which is a highly flexible and powerful open on-chip debug standard for 32-bit microcontrollers.
It supports the following features:
● Nexus compliant debug solution
● OCD supports any CPU speed
● Six program counter hardware breakpoints
● Two data breakpoints
● Breakpoints can be configured as watchpoints
● Hardware breakpoints can be combined to give break on rangesAtmel-ICE [USER GUIDE]
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● Unlimited number of user program breakpoints (using BREAK)
● Real-time program counter branch tracing, data trace, process trace (not supported by Atmel-ICE)
For special considerations regarding this debug interface, see “Atmel AVR UC3 OCD” on page 35.
For more information regarding the UC3 OCD system, consult the AVR32UC Technical Reference Manuals,
located on www.atmel.com/uc3
1
.
4.3.2 Atmel AVR XMEGA OCD (JTAG and PDI Physical)
The Atmel AVR XMEGA OCD is otherwise known as PDI (Program and Debug Interface). Two physical
interfaces (JTAG and PDI physical) provide access to the same OCD implementation within the device. It
supports the following features:
● Complete program flow control
● One dedicated program address comparator or symbolic breakpoint (reserved)
● Four hardware comparators
● Unlimited number of user program breakpoints (using BREAK)
● No limitation on system clock frequency
For special considerations regarding this debug interface, see “Special Considerations” on page 32.
4.3.3 Atmel megaAVR OCD (JTAG)
The Atmel megaAVR OCD is based on the JTAG physical interface. It supports the following features:
● Complete program flow control
● Four program memory (hardware) breakpoints (one is reserved)
● Hardware breakpoints can be combined to form data breakpoints
● Unlimited number of program breakpoints (using BREAK) (except ATmega128[A])
For special considerations regarding this debug interface, see “Atmel megaAVR OCD (JTAG)” on page 33.
4.3.4 Atmel megaAVR / tinyAVR OCD (debugWIRE)
The debugWIRE OCD is a specialised OCD module with a limited feature set specially designed for Atmel AVR
devices with low pin-count. It supports the following features:
● Complete program flow control
● Unlimited Number of User Program Breakpoints (using BREAK)
● Automatic baud configuration based on target clock
For special considerations regarding this debug interface, see “Atmel megaAVR OCD (JTAG)” on page 33.
4.3.5 ARM Coresight Components
Atmel ARM Cortex-M based microcontrollers implement Coresight™ compliant OCD components. The features
of these components can vary from device to device. For further information consult the device's datasheet.
1
http://www.atmel.com/uc3Atmel-ICE [USER GUIDE]
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5. Hardware Description
5.1 LEDs
The Atmel-ICE top panel has three LEDs which indicate the status of current debug or programming sessions.
Table 5-1. LEDs
LED Function Description
Left Target power GREEN when target power is OK. Flashing indicates a target power
error. Does not light up until a programming/debugging session
connection is started.
Middle Main power RED when main-board power is OK.
Right Status GREEN when the target is running. ORANGE when target is
stopped.
5.2 Rear Panel
The rear panel of the Atmel-ICE houses the micro-B USB connector.
5.3 Bottom Panel
The bottom panel of the Atmel-ICE has a sticker which shows the serial number and date of manufacture.
When seeking technical support, include these details.Atmel-ICE [USER GUIDE]
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5.4 Architecture Description
The Atmel-ICE architecture is shown in the block diagram in Figure 5-1, “Atmel-ICE block
diagram” on page 26.
Figure 5-1. Atmel-ICE block diagram
5.4.1 Atmel-ICE Mainboard
Power is supplied to the Atmel-ICE from the USB bus, regulated to 3.3V by a step-down switchmode regulator.
The VTG pin is used as a reference input only, and a separate power supply feeds the variable-voltage side of
the on-board level converters At the heart of the Atmel-ICE mainboard is the Atmel AVR UC3 microcontroller
AT32UC3A4256, which runs at between 1MHz and 60MHz depending on the tasks being processed. The
microcontroller includes an on-chip USB 2.0 high-speed module, allowing high data throughput to and from the
debugger.
Communication between the Atmel-ICE and the target device is done through a bank of level converters that
shift signals between the target's operating voltage and the internal voltage level on the Atmel-ICE. Also in
the signal path are zener overvoltage protection diodes, series termination resistors, inductive filters and ESD
protection diodes. All signal channels can be operated in the range 1.62V to 5.5V, although the Atmel-ICE
hardware can not drive out a higher voltage than 5.0V. Maximum operating frequency varies according to the
target interface in use.Atmel-ICE [USER GUIDE]
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5.4.2 Atmel-ICE Target Connectors
The Atmel-ICE does not have an active probe. A 50-mil IDC cable is used to connect to the target application
either directly, or through the adapters included in some kits. For more information on the cabling and adapters,
see section Assembling the Atmel-ICE
5.4.3 Atmel-ICE target Connectors Part Numbers
In order to connect the Atmel-ICE 50-mil IDC cable directly to a target board, any standard 50-mil 10-pin
header should suffice. It is advised to use keyed headers to ensure correct orientation when connecting to the
target, such as those used on the adapter board included with the kit.
The part number for this header is: FTSH-105-01-L-DV-K-A-P from SAMTEC.Atmel-ICE [USER GUIDE]
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6. Software Integration
6.1 Atmel Studio
6.1.1 Software Integration in Atmel Studio
Atmel Studio is an Integrated Development Environment (IDE) for writing and debugging Atmel AVR and Atmel
SAM applications in Windows environments. Atmel Studio provides a project management tool, source file
editor, simulator, assembler and front-end for C/C++, programming, emulation and on-chip debugging.
Atmel Studio version 6.2 or later must be used in conjunction with the Atmel-ICE.
6.1.2 Programming Options
Atmel Studio supports programming of Atmel AVR and Atmel SAM ARM devices using the Atmel-ICE. The
programming dialog can be configured to use JTAG, aWire, SPI, PDI, TPI or SWD modes, according to the
target device selected.
When configuring the clock frequency, different rules apply for different interfaces and target families:
● SPI programming makes use of the target clock. Configure the clock frequency to be lower than one fourth
the frequency at which the target device is currently running
● JTAG programming on Atmel megaAVR devices is clocked by the programmer. This means that the
programming clock frequency is limited to the maximum operating frequency of the device itself. (Usually
16MHz)
● AVR XMEGA programming on both JTAG and PDI interfaces is clocked by the programmer. This means
that the programming clock frequency is limited to the maximum operating frequency of the device itself.
(Usually 32MHz)
● AVR UC3 programming on JTAG interface is clocked by the programmer. This means that the
programming clock frequency is limited to the maximum operating frequency of the device itself. (Limited to
33MHz)
● AVR UC3 programming on aWire interface is clocked by the programmer. The optimal frequency is given
by the SAB bus speed in the target device. The Atmel-ICE debugger will automatically tune the aWire baud
rate to meet this criteria. Although it's usually not necessary the user can limit the maximum baud rate if
needed (e.g. in noisy environments)
● SAM device programming on SWD interface is clocked by the programmer. The maximum frequency
supported by Atmel-ICE is 2MHz. The frequency should not exceed the target CPU frequency times 10,
.
6.1.3 Debug Options
When debugging an Atmel AVR device using Atmel Studio, the 'Tool' tab in the project properties view contains
some important configuration options. Those options which need further explanation are:
● Target Clock Frequency
Accurately setting the target clock frequency is vital to achieve reliable debugging of Atmel megaAVR
device over the JTAG interface. This setting should be less than one fourth of the lowest operating
frequency of your AVR target device in the application being debugged. See “Atmel megaAVR OCD
(JTAG)” on page 33 for more information.
Debug sessions on debugWIRE target devices are clocked by the target device itself, and thus
no frequency setting is required. The Atmel-ICE will automatically select the correct baud rate for
communicating at the start of a debug session. However, if you are experiencing reliability problems
related to a noisy debug environment, it is possible to force the debugWIRE speed to a fraction of its
"recommended" setting.
Debug sessions on AVR XMEGA target devices can be clocked at up to the maximum speed of the device
itself (usually 32MHz).
Debug sessions on AVR UC3 target devices over the JTAG interface can be clocked at up to the maximum
speed of the device itself (limited to 33MHz). However the optimal frequency will be slightly below the
current SAB clock on the target device.Atmel-ICE [USER GUIDE]
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Debug sessions on UC3 target devices over the aWire interface will be automatically tuned to the optimal
baud rate by the Atmel-ICE itself. However, if you are experiencing reliability problems related to a noisy
debug environment, it is possible to force the aWire speed below a configurable limit.
Debug sessions on SAM target devices over the SWD interface can be clocked at up to ten times the CPU
clock (but limited to 2MHz max).
● Preserve EEPROM
Select this option to avoid erasing the EEPROM during reprogramming of the target before a debug
session.
● Use external reset
If your target application disables the JTAG interface, the external reset must be pulled low during
programming. Selecting this option avoids repeatedly being asked whether to use the external reset.Atmel-ICE [USER GUIDE]
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7. Command Line Utility
Atmel Studio comes with a command line utility called atprogram that can be used to program targets using
the Atmel Atmel-ICE. During the Atmel Studio installation a shortcut called Atmel Studio 6.2 Command Prompt
were created in the Atmel folder on the Start menu. By double clicking this shortcut a command prompt will be
opened and programming commands can be entered. The command line utility is installed in the Atmel Studio
installation path in the folder Atmel/Atmel Studio 6.2/atbackend/.
To get more help on the command line utility type the command: atprogram --help.Atmel-ICE [USER GUIDE]
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8. Advanced Debugging Techniques
8.1 Atmel AVR UC3 Targets
8.1.1 EVTI / EVTO Usage
The EVTI and EVTO pins are not accessible on the Atmel-ICE. However, they can still be used in conjunction
with other external equipment.
EVTI can be used for the following purposes:
● The target can be forced to stop execution in response to an external event. If the Event In Control (EIC)
bits in the DC register are written to 0b01, high-to-low transition on the EVTI pin will generate a breakpoint
condition. EVTI must remain low for one CPU clock cycle to guarantee that a breakpoint is triggered. The
External Breakpoint bit (EXB) in DS is set when this occurs
● Generating trace synchronisation messages. Not used by the Atmel-ICE
EVTO can be used for the following purposes:
● Indicating that the CPU has entered debug mode. Setting the EOS bits in DC to 0b01 causes the EVTO
pin to be pulled low for one CPU clock cycle when the target device enters debug mode. This signal can be
used as a trigger source for an external oscilloscope
● Indicating that the CPU has reached a breakpoint or watchpoint. By setting the EOC bit in a corresponding
Breakpoint / Watchpoint Control Register, breakpoint or watchpoint status is indicated on the EVTO pin.
The EOS bits in DC must be set to 0xb10 to enable this feature. The EVTO pin can then be connected to
an external oscilloscope in order to examine watchpoint timing
● Generating trace timing signals. Not used by the Atmel-ICE
8.2 debugWIRE Targets
8.2.1 Software Breakpoints
The debugWIRE OCD is drastically scaled down when compared to the Atmel megaAVR (JTAG) OCD. This
means that it does not have any program counter breakpoint comparators available to the user for debugging
purposes. One such comparator does exist for purposes of run-to-cursor and single-step operations, but user
breakpoints are not supported in hardware
Instead, the debugger must make use of the Atmel AVR BREAK instruction. This instruction can be placed
in FLASH, and when it is loaded for execution will cause the AVR CPU to enter stopped mode. To support
breakpoints during debugging, the debugger must insert a BREAK instruction into FLASH at the point at which
the users requests a breakpoint. The original instruction must be cached for later replacement. When single
stepping over a BREAK instruction, the debugger has to execute the original cached instruction in order to
preserve program behaviour. In extreme cases, the BREAK has to be removed from FLASH and replaced
later. All these scenarios can cause apparent delays when single stepping from breakpoints, which will be
exacerbated when the target clock frequency is very low.
It is thus recommended to observe the following guidelines, where possible:
● Always run the target at as high a frequency as possible during debugging. The debugWIRE physical
interface is clocked from the target clock
● Try to minimise on the number of breakpoint additions and removals, as each one require a FLASH page
to be replaced on the target
● Try to add or remove a small number of breakpoints at a time, to minimise the number of FLASH page
write operations
● If possible, avoid placing breakpoints on double-word instructionsAtmel-ICE [USER GUIDE]
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9. Special Considerations
9.1 Atmel AVR XMEGA OCD
OCD and clocking
When the MCU enters stopped mode, the OCD clock is used as MCU clock. The OCD clock is either the JTAG
TCK if the JTAG interface is being used, or the PDI_CLK if the PDI interface is being used.
I/O modules in stopped mode
In contrast to earlier Atmel megaAVR devices, in XMEGA the I/O modules are stopped in stop mode. This
means that USART transmissions will be interrupted, timers (and PWM) will be stopped.
Hardware breakpoints
There are four hardware breakpoint comparators - two address comparators and two value comparators. They
have certain restrictions:
● All breakpoints must be of the same type (program or data)
● All data breakpoints must be in the same memory area (IO, SRAM or XRAM)
● There can only be one breakpoint if address range is used
Here are the different combinations that can be set:
● Two single data or program address breakpoints
● One data or program address range breakpoint
● Two single data address breakpoints with single value compare
● One data breakpoint with address range, value range or both
Atmel Studio will tell you if the breakpoint can't be set, and why. Data breakpoints have priority over program
breakpoints, if software breakpoints are available.
External reset and PDI physical
The PDI physical interface uses the reset line as clock. While debugging, the reset pullup should be 10k
or more or be removed. Any reset capacitors should be removed. Other external reset sources should be
disconnected.
Debugging with sleep for ATxmegaA1 rev H and earlier
There was a bug in the early versions of the ATxmegaA1 family that prevented the OCD to be enabled while
the device was in certain sleep modes. There are two methods to use to get back on the debugging:
● Go into the Atmel-ICE Options in the Tools menu and enable "Always activate external reset when
reprogramming device"
● Perform a chip erase
The sleep modes that trigger this bug are:
● Power-down
● Power-save
● Standby
● Extended standby
9.2 Atmel megaAVR OCD and debugWIRE OCD
IO Peripherals
Most I/O peripherals will continue to run even though the program execution is stopped by a breakpoint.
Example: If a breakpoint is reached during a UART transmission, the transmission will be completed andAtmel-ICE [USER GUIDE]
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corresponding bits set. The TXC (transmit complete) flag will be set and will be available on the next single step
of the code even though it normally would happen later in an actual device.
All I/O modules will continue to run in stopped mode with the following two exceptions:
● Timer/Counters (configurable using the software front-end)
● Watchdog Timer (always stopped to prevent resets during debugging)
Single Stepping I/O access
Since the I/O continues to run in stopped mode, care should be taken to avoid certain timing issues. For
example, the code:
OUT PORTB, 0xAA<
IN TEMP, PINB
When running this code normally, the TEMP register would not read back 0xAA because the data would not yet
have been latched physically to the pin by the time it is sampled by the IN operation. A NOP instruction must be
placed between the OUT and the IN instruction to ensure that the correct value is present in the PIN register.
However, when single stepping this function through the OCD, this code will always give 0xAA in the PIN
register since the I/O is running at full speed even when the core is stopped during the single stepping.
Single stepping and timing
Certain registers need to be read or written within a given number of cycles after enabling a control signal.
Since the I/O clock and peripherals continue to run at full speed in stopped mode, single stepping through such
code will not meet the timing requirements. Between two single steps, the I/O clock may have run millions of
cycles. To successfully read or write registers with such timing requirements, the whole read or write sequence
should be performed as an atomic operation running the device at full speed. This can be done by using a
macro or a function call to execute the code, or use the run-to-cursor function in the debugging environment.
Accessing 16-bit Registers
The Atmel AVR peripherals typically contain several 16-bit registers that can be accessed via the 8-bit data bus
(eg: TCNTn of a 16-bit timer). The 16-bit register must be byte accessed using two read or write operations.
Breaking in the middle of a 16-bit access or single stepping through this situation may result in erroneous
values.
Restricted I/O registeraccess
Certain registers cannot be read without affecting their contents. Such registers include those which contain
flags which are cleared by reading, or buffered data registers (eg: UDR). The software front-end will prevent
reading these registers when in stopped mode to preserve the intended non-intrusive nature of OCD
debugging. In addition, some registers cannot safely be written without side-effects occurring - these registers
are read-only. For example:
● Flag registers, where a flag is cleared by writing '1' to any bit. These registers are read-only
● UDR and SPDR registers cannot be read without affecting the state of the module. These registers are not
accessible
9.2.1 Atmel megaAVR OCD (JTAG)
Software breakpoints
Since it contains an early version of the OCD module, ATmega128[A] does not support the use of the BREAK
instruction for software breakpoints.
JTAG clock
The target clock frequency must be accurately specified in the software front-end before starting a debug
session. For synchronisation reasons, the JTAG TCK signal must be less than one fourth of the target clock
frequency for reliable debugging. When programming via the JTAG interface, the TCK frequency is limited by
the maximum frequency rating of the target device, and not the actual clock frequency being used.
When using the internal RC oscillator, be aware that the frequency may vary from device to device and is
affected by temperature and VCC changes. Be conservative when specifying the target clock frequency.Atmel-ICE [USER GUIDE]
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See “Debug Options” on page 28 for details on how to set the target clock frequency using the software frontend.
JTAGEN and OCDEN fuses
The JTAG interface is enabled using the JTAGEN fuse, which is programmed by default. This allows access to
the JTAG programming interface. Through this mechanism, the OCDEN fuse can be programmed (by default
OCDEN is un-programmed). This allows access to the OCD in order to facilitate debugging the device. The
software front-end will always ensure that the OCDEN fuse is left un-programmed when terminating a session,
thereby restricting unnecessary power consumption by the OCD module. If the JTAGEN fuse is unintentionally
disabled, it can only be re-enabled using SPI or PP programming methods.
If the JTAGEN fuse is programmed, the JTAG interface can still be disabled in firmware by setting the JTD bit.
This will render code un-debuggable, and should not be done when attempting a debug session. If such code
is already executing on the Atmel AVR device when starting a debug session, the Atmel-ICE will assert the
RESET line while connecting. If this line is wired correctly, it will force the target AVR device into reset, thereby
allowing a JTAG connection.
If the JTAG interface is enabled, the JTAG pins cannot be used for alternative pin functions. They will remain
dedicated JTAG pins until either the JTAG interface is disabled by setting the JTD bit from the program code, or
by clearing the JTAGEN fuse through a programming interface.
Note Be sure to check the "use external reset" checkbox in both the programming dialog and debug
options dialog in order to allow the Atmel-ICE to assert the RESET line and re-enable the JTAG
interface on devices which are running code which disables the JTAG interface by setting the JTD
bit.
IDR events
When the application program writes a byte of data to the OCDR register of the AVR device being debugged,
the Atmel-ICE reads this value out and displays it in the message window of the software front-end. The IDR
register is polled every 50ms, so writing to it at a higher frequency will NOT yield reliable results. When the
AVR device loses power while it is being debugged, spurious IDR events may be reported. This happens
because the Atmel-ICE may still poll the device as the target voltage drops below the AVR’s minimum operating
voltage.
9.2.2 debugWIRE OCD
The debugWIRE communication pin (dW) is physically located on the same pin as the external reset (RESET).
An external reset source is therefore not supported when the debugWIRE interface is enabled.
The debugWIRE Enable fuse (DWEN) must be set on the target device in order for the debugWIRE interface
to function. This fuse is by default un-programmed when the Atmel AVR device is shipped from the factory. The
debugWIRE interface itself cannot be used to set this fuse. In order to set the DWEN fuse, SPI mode must be
used. The software front-end handles this automatically provided that the necessary SPI pins are connected. It
can also be set using SPI programming from the Atmel Studio programming dialog.
● Either:
Attempt to start a debug session on the debugWIRE part. If the debugWIRE interface is not enabled, Atmel
Studio will offer to retry, or attempt to enable debugWIRE using SPI programming. If you have the full SPI
header connected, debugWIRE will be enabled, and you will be asked to toggle power on the target - this
is required for the fuse changes to be effective.
● Or:
Open the programming dialog in SPI mode, and verify that the signature matches the correct device.
Check the DWEN fuse to enable debugWIRE.
Note It is important to leave the SPIEN fuse programmed, the RSTDISBL fuse unprogrammed! Not
doing this will render the device stuck in debugWIRE mode, and high-voltage programming
will be required to revert the DWEN setting.
To disable the debugWIRE interface, use high-voltage programming to unprogram the DWEN fuse. Alternately,
use the debugWIRE interface itself to temporarily disable itself, which will allow SPI programming to take place,
provided that the SPIEN fuse is set.Atmel-ICE [USER GUIDE]
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Note If the SPIEN fuse was NOT left programmed, Atmel Studio will not be able to complete this
operation, and high-voltage programming must be used.
● During a debug session, select the 'Disable debugWIRE and Close' menu option from the 'Debug' menu.
DebugWIRE will be temporarily disabled, and Atmel Studio will use SPI programming to unprogram the
DWEN fuse
Having the DWEN fuse programmed enables some parts of the clock system to be running in all sleep modes.
This will increase the power consumption of the AVR while in sleep modes. The DWEN Fuse should therefore
always be disabled when debugWIRE is not used.
When designing a target application PCB where debugWIRE will be used, the following considerations must be
made for correct operation:
● Pull-up resistors on the dW/(RESET) line must not be smaller (stronger) than 10kΩ. The pull-up resistor is
not required for debugWIRE functionality, since the debugger tool provides this
● Connecting the RESET pin directly to VCC will cause the debugWIRE interface to fail, and may result in
hardware damage to the Atmel-ICE
● Any stabilising capacitor connected to the RESET pin must be disconnected when using debugWIRE,
since they will interfere with correct operation of the interface
● All external reset sources or other active drivers on the RESET line must be disconnected, since they may
interfere with the correct operation of the interface
Never program the lock-bits on the target device. The debugWIRE interface requires that lock-bits are cleared
in order to function correctly.
9.3 Atmel AVR UC3 OCD
JTAG interface
On some Atmel AVR UC3 devices the JTAG port is not enabled by default. When using these devices it is
essential to connect the RESET line so that the Atmel-ICE can enable the JTAG interface.
aWire interface
The baud rate of aWire communications depends upon the frequency of the system clock, since data must
be synchronised between these two domains. The Atmel-ICE will automatically detect that the system clock
has been lowered, and re-calibrate its baud rate accordingly. The automatic calibration only works down to a
system clock frequency of 8kHz. Switching to a lower system clock during a debug session may cause contact
with the target to be lost.
If required, the aWire baud rate can be restricted by setting the aWire clock parameter. Automatic detection will
still work, but a ceiling value will be imposed on the results.
Any stabilising capacitor connected to the RESET pin must be disconnected when using aWire since it
will interfere with correct operation of the interface. A weak external pullup (10kΩ or higher) on this line is
recommended.
Shutdown sleep mode
Some AVR UC3 devices have an internal regulator that can be used in 3.3V supply mode with 1.8V regulated
I/O lines. This means that the internal regulator powers both the core and most of the I/O. The Atmel-ICE does
not support the Shutdown sleep mode were this regulator is shut off. In other words this sleep mode cannot be
used during debugging. If it is a requirement to use this sleep mode during debugging, use an Atmel AVR ONE!
debugger instead.
9.4 SAM / Coresight OCD
Some SAM devices include an ERASE pin which is asserted to perform a complete chip erase and unlock
devices on which the security bit is set. This pin is NOT routed to any debug header, and thus the Atmel-ICE is
unable to unlock a device. In such cases the user should perform the erase before starting a debug session.
JTAG interface
The RESET line should always be connected so that the Atmel-ICE can enable the JTAG interface.Atmel-ICE [USER GUIDE]
42330A-MCU-07/2014
36
SWD interface
The RESET line should always be connected so that the Atmel-ICE can enable the SWD interface.Atmel-ICE [USER GUIDE]
42330A-MCU-07/2014
37
10. Firmware Upgrade
For information on how to upgrade the firmware, see the Atmel Studio user guide in Atmel Studio (USER
GUIDE).Atmel-ICE [USER GUIDE]
42330A-MCU-07/2014
38
11. Release History and Known issues
11.1 What's New
Atmel-ICE is new!
11.2 Firmware Release History
11.2.1 Atmel Studio 6.2
Table 11-1. New in this Release
Release platform Atmel Studio 6.2 (final)
Firmware version 1.13
New features None
Fixes ● Fixed oscillator calibration command
● Improved debugWIRE reliability
11.2.2 Atmel Studio 6.2 (beta)2
Table 11-2. New in this Release
Release platform Atmel Studio 6.2 (beta)
Firmware version 1.09
New features First release of Atmel-ICE
Fixes N/A
11.3 Known Issues Concerning the Atmel-ICE
11.3.1 Atmel AVR XMEGA OCD Specific Issues
● For the ATxmegaA1 family, only revision G or later is supported
11.3.2 Atmel megaAVR OCD and Atmel tinyAVR OCD Specific Issues
● Cycling power on ATmega32U6 during a debug session may cause a loss of contact with the device
11.4 Device Support
For a full device support table for all Atmel Tools, see the “Supported Devices” in Atmel Studio (USER GUIDE).Atmel-ICE [USER GUIDE]
42330A-MCU-07/2014
39
12. Product Compliance
12.1 RoHS and WEEE
The Atmel-ICE (all kits) and its accessories are manufactured in accordance to both the RoHS Directive
(2002/95/EC) and the WEEE Directive (2002/96/EC).
12.2 CE and FCC
The Atmel-ICE unit has been tested in accordance to the essential requirements and other relevant provisions
of Directives:
● Directive 2004/108/EC (class B)
● FCC part 15 subpart B
● 2002/95/EC (RoHS, WEEE)
The following standards are used for evaluation:
● EN 61000-6-1 (2007)
● EN 61000-6-3 (2007) + A1(2011)
● FCC CFR 47 Part 15 (2013)
The Technical Construction File is located at:
Atmel Norway
Vestre Rosten 79
7075 Tiller
Norway
Every effort has been made to minimise electromagnetic emissions from this product. However, under
certain conditions, the system (this product connected to a target application circuit) may emit individual
electromagnetic component frequencies which exceed the maximum values allowed by the abovementioned
standards. The frequency and magnitude of the emissions will be determined by several factors, including
layout and routing of the target application with which the product is used.Atmel-ICE [USER GUIDE]
42330A-MCU-07/2014
40
13. Document Revisions
Document
revision
Date Comment
42330A 06/2014 Initial document for release.Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com
© 2014 Atmel Corporation. / Rev.: 42330A-MCU-07/2014
Atmel®
, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®
, AVR
®
, AVR Studio
®
, megaAVR
®
, tinyAVR
®
, XMEGA®
, and others are registered
trademarks or trademarks of Atmel Corporation in U.S. and other countries. ARM®
, ARM Connected®
, Cortex®
logo and others are the registered trademarks or
trademarks of ARM Ltd. Windows®
is a registered trademark of Microsoft Corporation in the U.S. and other countries. Other terms and product names may be
trademarks of others.
DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted
by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE,
ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION,
OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products
descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable
for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any applications where the failure
of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without an Atmel officer's specific written consent. Safety-Critical
Applications include, without limitation, life support devices and systems, equipment or systems for the operation of nuclear facilities and weapons systems. Atmel products are not designed
nor intended for use in military or aerospace applications or environments unless specifically designated by Atmel as military- grade. Atmel products are not designed nor intended for use in
automotive applications unless specifically designated by Atmel as automotive-grade.
Features
• High Performance, Low Power Atmel® AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
– 135 Powerful Instructions – Most Single Clock Cycle Execution
– 32 × 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16MHz
– On-Chip 2-cycle Multiplier
• High Endurance Non-volatile Memory Segments
– 64K/128K/256KBytes of In-System Self-Programmable Flash
– 4Kbytes EEPROM
– 8Kbytes Internal SRAM
– Write/Erase Cycles:10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/ 100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– Programming Lock for Software Security
• Endurance: Up to 64Kbytes Optional External Memory Space
• Atmel® QTouch® library support
– Capacitive touch buttons, sliders and wheels
– QTouch and QMatrix® acquisition
– Up to 64 sense channels
• JTAG (IEEE std. 1149.1 compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– Four 16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode
– Real Time Counter with Separate Oscillator
– Four 8-bit PWM Channels
– Six/Twelve PWM Channels with Programmable Resolution from 2 to 16 Bits
(ATmega1281/2561, ATmega640/1280/2560)
– Output Compare Modulator
– 8/16-channel, 10-bit ADC (ATmega1281/2561, ATmega640/1280/2560)
– Two/Four Programmable Serial USART (ATmega1281/2561, ATmega640/1280/2560)
– Master/Slave SPI Serial Interface
– Byte Oriented 2-wire Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,
and Extended Standby
• I/O and Packages
– 54/86 Programmable I/O Lines (ATmega1281/2561, ATmega640/1280/2560)
– 64-pad QFN/MLF, 64-lead TQFP (ATmega1281/2561)
– 100-lead TQFP, 100-ball CBGA (ATmega640/1280/2560)
– RoHS/Fully Green
• Temperature Range:
– -40°C to 85°C Industrial
• Ultra-Low Power Consumption
– Active Mode: 1MHz, 1.8V: 500µA
– Power-down Mode: 0.1µA at 1.8V
• Speed Grade:
– ATmega640V/ATmega1280V/ATmega1281V:
• 0 - 4MHz @ 1.8V - 5.5V, 0 - 8MHz @ 2.7V - 5.5V
– ATmega2560V/ATmega2561V:
• 0 - 2MHz @ 1.8V - 5.5V, 0 - 8MHz @ 2.7V - 5.5V
– ATmega640/ATmega1280/ATmega1281:
• 0 - 8MHz @ 2.7V - 5.5V, 0 - 16MHz @ 4.5V - 5.5V
– ATmega2560/ATmega2561:
• 0 - 16MHz @ 4.5V - 5.5V
8-bit Atmel
Microcontroller
with
64K/128K/256K
Bytes In-System
Programmable
Flash
ATmega640/V
ATmega1280/V
ATmega1281/V
ATmega2560/V
ATmega2561/V
2549P–AVR–10/20122
2549P–AVR–10/2012
ATmega640/1280/1281/2560/2561
1. Pin Configurations
Figure 1-1. TQFP-pinout ATmega640/1280/2560
GND
VCC
PA0 (AD0)
PA1 (AD1)
PA2 (AD2)
PA3 (AD3)
PA4 (AD4)
PA5 (AD5)
PA6 (AD6)
PA7 (AD7)
PG2 (ALE)
AVCC
GND
AREF
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
PF7 (ADC7/TDI)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PK0 (ADC8/PCINT16) PK1 (ADC9/PCINT17) PK2 (ADC10/PCINT18) PK3 (ADC11/PCINT19) PK4 (ADC12/PCINT20) PK5 (ADC13/PCINT21) PK6 (ADC14/PCINT22) PK7 (ADC15/PCINT23)
(OC2B) PH6
(TOSC2) PG3
(TOSC1) PG4
(T4) PH7
RESET
(ICP4) PL0
VCC
GND
XTAL2
XTAL1
PL6
PL7
GND
VCC
(OC0B) PG5
VCC
GND
(RXD2) PH0
(TXD2) PH1
(XCK2) PH2
(OC4A) PH3
(OC4B) PH4
(OC4C) PH5
(RXD0/PCINT8) PE0
(TXD0) PE1
(XCK0/AIN0) PE2
(OC3A/AIN1) PE3
(OC3B/INT4) PE4
(OC3C/INT5) PE5
(T3/INT6) PE6
(CLKO/ICP3/INT7) PE7
(SS/PCINT0) PB0
(SCK/PCINT1) PB1
(MOSI/PCINT2) PB2
(MISO/PCINT3) PB3
(OC2A/PCINT4) PB4
(OC1A/PCINT5) PB5
(OC1B/PCINT6) PB6
(OC0A/OC1C/PCINT7) PB7
PC7 (A15)
PC6 (A14)
PC5 (A13)
PC4 (A12)
PC3 (A11)
PC2 (A10)
PC1 (A9)
PC0 (A8)
PG1 (RD)
PG0 (WR)
(TXD1/INT3) PD3
(ICP1) PD4
(XCK1) PD5
(T1) PD6
(T0) PD7
(SCL/INT0) PD0
(SDA/INT1) PD1
(RXD1/INT2) PD2
(ICP5) PL1
(T5) PL2
(OC5A) PL3
(OC5B) PL4
PJ6 (PCINT15)
PJ5 (PCINT14)
PJ4 (PCINT13)
PJ3 (PCINT12)
PJ2 (XCK3/PCINT11)
PJ1 (TXD3/PCINT10)
PJ0 (RXD3/PCINT9)
PJ7
(OC5C) PL5
INDEX CORNER3
2549P–AVR–10/2012
ATmega640/1280/1281/2560/2561
Figure 1-2. CBGA-pinout ATmega640/1280/2560
Note: The functions for each pin is the same as for the 100 pin packages shown in Figure 1-1 on page 2.
A
B
C
D
E
F
G
H
J
K
1 2 3 4 5 6 7 8 9 10
A
B
C
D
E
F
G
H
J
K
10 9 8 7 6 5 4 3 2 1
Top view Bottom view
Table 1-1. CBGA-pinout ATmega640/1280/2560
1 2 3 4 5 6 7 8 9 10
A GND AREF PF0 PF2 PF5 PK0 PK3 PK6 GND VCC
B AVCC PG5 PF1 PF3 PF6 PK1 PK4 PK7 PA0 PA2
C PE2 PE0 PE1 PF4 PF7 PK2 PK5 PJ7 PA1 PA3
D PE3 PE4 PE5 PE6 PH2 PA4 PA5 PA6 PA7 PG2
E PE7 PH0 PH1 PH3 PH5 PJ6 PJ5 PJ4 PJ3 PJ2
F VCC PH4 PH6 PB0 PL4 PD1 PJ1 PJ0 PC7 GND
G GND PB1 PB2 PB5 PL2 PD0 PD5 PC5 PC6 VCC
H PB3 PB4 RESET PL1 PL3 PL7 PD4 PC4 PC3 PC2
J PH7 PG3 PB6 PL0 XTAL2 PL6 PD3 PC1 PC0 PG1
K PB7 PG4 VCC GND XTAL1 PL5 PD2 PD6 PD7 PG04
2549P–AVR–10/2012
ATmega640/1280/1281/2560/2561
Figure 1-3. Pinout ATmega1281/2561
Note: The large center pad underneath the QFN/MLF package is made of metal and internally connected
to GND. It should be soldered or glued to the board to ensure good mechanical stability. If
the center pad is left unconnected, the package might loosen from the board.
(RXD0/PCINT8/PDI) PE0
(TXD0/PDO) PE1
(XCK0/AIN0) PE2
(OC3A/AIN1) PE3
(OC3B/INT4) PE4
(OC3C/INT5) PE5
(T3/INT6) PE6
(ICP3/CLKO/INT7) PE7
(SS/PCINT0) PB0
(OC0B) PG5
(SCK/PCINT1) PB1
(MOSI/PCINT2) PB2
(MISO/PCINT3) PB3
(OC2A/ PCINT4) PB4
(OC1A/PCINT5) PB5
(OC1B/PCINT6) PB6
(OC0A/OC1C/PCINT7) PB7
(TOSC2) PG3
(TOSC1) PG4
RESET
VCC
GND
XTAL2
XTAL1
(SCL/INT0) PD0
(SDA/INT1) PD1
(RXD1/INT2) PD2
(TXD1/INT3) PD3
(ICP1) PD4
(XCK1) PD5
PA3 (AD3)
PA4 (AD4)
PA5 (AD5)
PA6 (AD6)
PA7 (AD7)
PG2 (ALE)
PC7 (A15)
PC6 (A14)
PC5 (A13)
PC4 (A12)
PC3 (A11)
PC2 (A10)
PC1 (A9)
PC0 (A8)
PG1 (RD)
PG0 (WR)
AVCC
GND
AREF
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
PF7 (ADC7/TDI)
GND
VCC
PA0 (AD0)
PA1 (AD1)
PA2 (AD2)
(T1) PD6
(T0) PD7
INDEX CORNER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
325
2549P–AVR–10/2012
ATmega640/1280/1281/2560/2561
2. Overview
The ATmega640/1280/1281/2560/2561 is a low-power CMOS 8-bit microcontroller based on the
AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
ATmega640/1280/1281/2560/2561 achieves throughputs approaching 1 MIPS per MHz allowing
the system designer to optimize power consumption versus processing speed.
2.1 Block Diagram
Figure 2-1. Block Diagram
CPU
GND
VCC
RESET
Power
Supervision
POR / BOD &
RESET
Watchdog
Oscillator
Watchdog
Timer
Oscillator
Circuits /
Clock
Generation
XTAL1
XTAL2
PC7..0 PORT C (8)
PA7..0 PORT A (8)
PORT D (8)
PD7..0
PORT B (8)
PB7..0
PORT E (8)
PE7..0
PORT F (8)
PF7..0
PORT J (8)
PJ7..0
PG5..0 PORT G (6)
PORT H (8)
PH7..0
PORT K (8)
PK7..0
PORT L (8)
PL7..0
XRAM
TWI SPI
EEPROM
JTAG
8 bit T/C 0 8 bit T/C 2
16 bit T/C 1
16 bit T/C 3
FLASH SRAM
16 bit T/C 4
16 bit T/C 5
USART 2
USART 1
USART 0
Internal
Bandgap reference
Analog
Comparator
A/D
Converter
USART 3
NOTE:
Shaded parts only available
in the 100-pin version.
Complete functionality for
the ADC, T/C4, and T/C5 only
available in the 100-pin version.6
2549P–AVR–10/2012
ATmega640/1280/1281/2560/2561
The Atmel® AVR® core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two
independent registers to be accessed in one single instruction executed in one clock cycle. The
resulting architecture is more code efficient while achieving throughputs up to ten times faster
than conventional CISC microcontrollers.
The ATmega640/1280/1281/2560/2561 provides the following features: 64K/128K/256K bytes of
In-System Programmable Flash with Read-While-Write capabilities, 4Kbytes EEPROM, 8
Kbytes SRAM, 54/86 general purpose I/O lines, 32 general purpose working registers, Real
Time Counter (RTC), six flexible Timer/Counters with compare modes and PWM, 4 USARTs, a
byte oriented 2-wire Serial Interface, a 16-channel, 10-bit ADC with optional differential input
stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI
serial port, IEEE® std. 1149.1 compliant JTAG test interface, also used for accessing the Onchip
Debug system and programming and six software selectable power saving modes. The Idle
mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system
to continue functioning. The Power-down mode saves the register contents but freezes the
Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Powersave
mode, the asynchronous timer continues to run, allowing the user to maintain a timer base
while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all
I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC
conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the
device is sleeping. This allows very fast start-up combined with low power consumption. In
Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.
Atmel offers the QTouch® library for embedding capacitive touch buttons, sliders and wheelsfunctionality
into AVR microcontrollers. The patented charge-transfer signal acquisition
offersrobust sensing and includes fully debounced reporting of touch keys and includes Adjacent
KeySuppression® (AKS™) technology for unambiguous detection of key events. The easy-to-use
QTouch Suite toolchain allows you to explore, develop and debug your own touch applications.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The Onchip
ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial
interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program
running on the AVR core. The boot program can use any interface to download the application
program in the application Flash memory. Software in the Boot Flash section will continue to run
while the Application Flash section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,
the Atmel ATmega640/1280/1281/2560/2561 is a powerful microcontroller that provides a highly
flexible and cost effective solution to many embedded control applications.
The ATmega640/1280/1281/2560/2561 AVR is supported with a full suite of program and system
development tools including: C compilers, macro assemblers, program
debugger/simulators, in-circuit emulators, and evaluation kits.7
2549P–AVR–10/2012
ATmega640/1280/1281/2560/2561
2.2 Comparison Between ATmega1281/2561 and ATmega640/1280/2560
Each device in the ATmega640/1280/1281/2560/2561 family differs only in memory size and
number of pins. Table 2-1 summarizes the different configurations for the six devices.
2.3 Pin Descriptions
2.3.1 VCC
Digital supply voltage.
2.3.2 GND
Ground.
2.3.3 Port A (PA7..PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port A also serves the functions of various special features of the
ATmega640/1280/1281/2560/2561 as listed on page 78.
2.3.4 Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B has better driving capabilities than the other ports.
Port B also serves the functions of various special features of the
ATmega640/1280/1281/2560/2561 as listed on page 79.
2.3.5 Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
Table 2-1. Configuration Summary
Device Flash EEPROM RAM
General
Purpose I/O pins
16 bits resolution
PWM channels
Serial
USARTs
ADC
Channels
ATmega640 64KB 4KB 8KB 86 12 4 16
ATmega1280 128KB 4KB 8KB 86 12 4 16
ATmega1281 128KB 4KB 8KB 54 6 2 8
ATmega2560 256KB 4KB 8KB 86 12 4 16
ATmega2561 256KB 4KB 8KB 54 6 2 88
2549P–AVR–10/2012
ATmega640/1280/1281/2560/2561
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of special features of the ATmega640/1280/1281/2560/2561 as
listed on page 82.
2.3.6 Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the
ATmega640/1280/1281/2560/2561 as listed on page 83.
2.3.7 Port E (PE7..PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port E also serves the functions of various special features of the
ATmega640/1280/1281/2560/2561 as listed on page 86.
2.3.8 Port F (PF7..PF0)
Port F serves as analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical
drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will
be activated even if a reset occurs.
Port F also serves the functions of the JTAG interface.
2.3.9 Port G (PG5..PG0)
Port G is a 6-bit I/O port with internal pull-up resistors (selected for each bit). The Port G output
buffers have symmetrical drive characteristics with both high sink and source capability. As
inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are
activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock
is not running.
Port G also serves the functions of various special features of the
ATmega640/1280/1281/2560/2561 as listed on page 90.
2.3.10 Port H (PH7..PH0)
Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port H output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up9
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resistors are activated. The Port H pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port H also serves the functions of various special features of the ATmega640/1280/2560 as
listed on page 92.
2.3.11 Port J (PJ7..PJ0)
Port J is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port J output buffers have symmetrical drive characteristics with both high sink and source capability.
As inputs, Port J pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port J pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port J also serves the functions of various special features of the ATmega640/1280/2560 as
listed on page 94.
2.3.12 Port K (PK7..PK0)
Port K serves as analog inputs to the A/D Converter.
Port K is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port K output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port K pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port K pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port K also serves the functions of various special features of the ATmega640/1280/2560 as
listed on page 96.
2.3.13 Port L (PL7..PL0)
Port L is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port L output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port L pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port L pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port L also serves the functions of various special features of the ATmega640/1280/2560 as
listed on page 98.
2.3.14 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in “System and Reset
Characteristics” on page 372. Shorter pulses are not guaranteed to generate a reset.
2.3.15 XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
2.3.16 XTAL2
Output from the inverting Oscillator amplifier.10
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2.3.17 AVCC
AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected
to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC
through a low-pass filter.
2.3.18 AREF
This is the analog reference pin for the A/D Converter.11
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3. Resources
A comprehensive set of development tools and application notes, and datasheets are available
for download on http://www.atmel.com/avr.
4. About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation
for more details.
These code examples assume that the part specific header file is included before compilation.
For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI"
instructions must be replaced with instructions that allow access to extended I/O. Typically
"LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".
5. Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 ppm over 20 years at 85°C or 100 years at 25°C.
6. Capacitive touch sensing
The Atmel®QTouch® Library provides a simple to use solution to realize touch sensitive interfaces
on most Atmel AVR® microcontrollers. The QTouch Library includes support for the
QTouch and QMatrix® acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library
for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels
and sensors, and then calling the touch sensing API’s to retrieve the channel information
and determine the touch sensor states.
The QTouch Library is FREE and downloadable from the Atmel website at the following location:
www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the
Atmel QTouch Library User Guide - also available for download from the Atmel website.12
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7. AVR CPU Core
7.1 Introduction
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
7.2 Architectural Overview
Figure 7-1. Block Diagram of the AVR Architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruction
is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
Direct Addressing
Indirect Addressing
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
I/O Module 2
I/O Module1
I/O Module n13
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The fast-access Register File contains 32 × 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical
ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointers
can also be used as an address pointer for look up tables in Flash program memory. These
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single register operations can also be executed in the ALU. After an arithmetic operation,
the Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most AVR instructions have a single 16-bit word format.
Every program memory address contains a 16-bit or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the
Application Program section. Both sections have dedicated Lock bits for write and read/write
protection. The SPM instruction that writes into the Application Flash memory section must
reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack
Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position.
The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers,
SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data
Space locations following those of the Register File, 0x20 - 0x5F. In addition, the
ATmega640/1280/1281/2560/2561 has Extended I/O space from 0x60 - 0x1FF in SRAM where
only the ST/STS/STD and LD/LDS/LDD instructions can be used.
7.3 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general purpose
registers or between a register and an immediate are executed. The ALU operations are divided
into three main categories – arithmetic, logical, and bit-functions. Some implementations of the
architecture also provide a powerful multiplier supporting both signed/unsigned multiplication
and fractional format. See the “Instruction Set Summary” on page 416 for a detailed description.14
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7.4 Status Register
The Status Register contains information about the result of the most recently executed arithmetic
instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the “Instruction Set Summary” on page 416. This will in many cases remove the
need for using the dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored
when returning from an interrupt. This must be handled by software.
7.4.1 SREG – AVR Status Register
The AVR Status Register – SREG – is defined as:
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt
enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the “Instruction Set Summary”
on page 416.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination
for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful
in BCD arithmetic. See the “Instruction Set Summary” on page 416 for detailed information.
• Bit 4 – S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Summary” on page 416 for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction Set Summary” on page 416 for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Summary” on page 416 for detailed information.
Bit 7 6 5 4 3 2 1 0
0x3F (0x5F) I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 015
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• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction
Set Summary” on page 416 for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set
Summary” on page 416 for detailed information.
7.5 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve
the required performance and flexibility, the following input/output schemes are supported by the
Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU.
Figure 7-2. AVR CPU General Purpose Working Registers
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 7-2, each register is also assigned a data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically implemented
as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
7.5.1 The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers
are 16-bit address pointers for indirect addressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in Figure 7-3 on page 16.
7 0 Addr.
R0 0x00
R1 0x01
R2 0x02
…
R13 0x0D
General R14 0x0E
Purpose R15 0x0F
Working R16 0x10
Registers R17 0x11
…
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte16
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Figure 7-3. The X-, Y-, and Z-registers
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the “Instruction Set Summary” on page 416
for details).
7.6 Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations
to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x0200. The initial value of the stack pointer is the last address of the internal
SRAM. The Stack Pointer is decremented by one when data is pushed onto the Stack with the
PUSH instruction, and it is decremented by two for ATmega640/1280/1281 and three for
ATmega2560/2561 when the return address is pushed onto the Stack with subroutine call or
interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the
POP instruction, and it is incremented by two for ATmega640/1280/1281 and three for
ATmega2560/2561 when data is popped from the Stack with return from subroutine RET or
return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementations
of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
15 XH XL 0
X-register 7 07 0
R27 (0x1B) R26 (0x1A)
15 YH YL 0
Y-register 7 07 0
R29 (0x1D) R28 (0x1C)
15 ZH ZL 0
Z-register 70 7 0
R31 (0x1F) R30 (0x1E)
Bit 15 14 13 12 11 10 9 8
0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH
0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 1 0 0 0 0 1
1111111117
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7.6.1 RAMPZ – Extended Z-pointer Register for ELPM/SPM
For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown
in Figure 7-4. Note that LPM is not affected by the RAMPZ setting.
Figure 7-4. The Z-pointer used by ELPM and SPM
The actual number of bits is implementation dependent. Unused bits in an implementation will
always read as zero. For compatibility with future devices, be sure to write these bits to zero.
7.6.2 EIND – Extended Indirect Register
For EICALL/EIJMP instructions, the Indirect-pointer to the subroutine/routine is a concatenation
of EIND, ZH, and ZL, as shown in Figure 7-5. Note that ICALL and IJMP are not affected by the
EIND setting.
Figure 7-5. The Indirect-pointer used by EICALL and EIJMP
The actual number of bits is implementation dependent. Unused bits in an implementation will
always read as zero. For compatibility with future devices, be sure to write these bits to zero.
7.7 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the
chip. No internal clock division is used.
Figure 7-6 on page 18 shows the parallel instruction fetches and instruction executions enabled
by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining
concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions
per cost, functions per clocks, and functions per power-unit.
Bit 7 6 5 4 3 2 1 0
0x3B (0x5B) RAMPZ7 RAMPZ6 RAMPZ5 RAMPZ4 RAMPZ3 RAMPZ2 RAMPZ1 RAMPZ0 RAMPZ
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit
(Individually)
7 0 7 07 0
RAMPZ ZH ZL
Bit (Z-pointer) 23 16 15 8 7 0
Bit 7 6 5 4 3 2 1 0
0x3C (0x5C) EIND7 EIND6 EIND5 EIND4 EIND3 EIND2 EIND1 EIND0 EIND
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit
(Individually)
7 07 07 0
EIND ZH ZL
Bit (Indirectpointer)
23 16 15 8 7 018
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Figure 7-6. The Parallel Instruction Fetches and Instruction Executions
Figure 7-7 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destination
register.
Figure 7-7. Single Cycle ALU Operation
7.8 Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section “Memory Programming”
on page 335 for details.
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 105. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL
bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 105 for more information.
The Reset Vector can also be moved to the start of the Boot Flash section by programming
the BOOTRST Fuse, see “Memory Programming” on page 335.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled.
The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clkCPU19
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There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector
in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)
to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt
Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The following example shows how this can be used to avoid interrupts during the
timed EEPROM write sequence.
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed
before any pending interrupts, as shown in this example.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
__disable_interrupt();
EECR |= (1< xxx
;
.org 0x1F002
0x1F002 jmp EXT_INT0 ; IRQ0 Handler
0x1F004 jmp EXT_INT1 ; IRQ1 Handler
... ... ... ;
0x1FO70 jmp USART3_TXC ; USART3 TX Complete Handler
0x0040 jmp TIM3_COMPA ; Timer3 CompareA Handler
0x0042 jmp TIM3_COMPB ; Timer3 CompareB Handler
0x0044 jmp TIM3_COMPC ; Timer3 CompareC Handler
0x0046 jmp TIM3_OVF ; Timer3 Overflow Handler
0x0048 jmp USART1_RXC ; USART1 RX Complete Handler
0x004A jmp USART1_UDRE ; USART1,UDR Empty Handler
0x004C jmp USART1_TXC ; USART1 TX Complete Handler
0x004E jmp TWI ; 2-wire Serial Handler
0x0050 jmp SPM_RDY ; SPM Ready Handler
0x0052 jmp TIM4_CAPT ; Timer4 Capture Handler
0x0054 jmp TIM4_COMPA ; Timer4 CompareA Handler
0x0056 jmp TIM4_COMPB ; Timer4 CompareB Handler
0x0058 jmp TIM4_COMPC ; Timer4 CompareC Handler
0x005A jmp TIM4_OVF ; Timer4 Overflow Handler
0x005C jmp TIM5_CAPT ; Timer5 Capture Handler
0x005E jmp TIM5_COMPA ; Timer5 CompareA Handler
0x0060 jmp TIM5_COMPB ; Timer5 CompareB Handler
0x0062 jmp TIM5_COMPC ; Timer5 CompareC Handler
0x0064 jmp TIM5_OVF ; Timer5 Overflow Handler
0x0066 jmp USART2_RXC ; USART2 RX Complete Handler
0x0068 jmp USART2_UDRE ; USART2,UDR Empty Handler
0x006A jmp USART2_TXC ; USART2 TX Complete Handler
0x006C jmp USART3_RXC ; USART3 RX Complete Handler
0x006E jmp USART3_UDRE ; USART3,UDR Empty Handler
0x0070 jmp USART3_TXC ; USART3 TX Complete Handler
;
0x0072 RESET: ldi r16, high(RAMEND) ; Main program start
0x0073 out SPH,r16 ; Set Stack Pointer to top of RAM
0x0074 ldi r16, low(RAMEND)
0x0075 out SPL,r16
0x0076 sei ; Enable interrupts
0x0077 xxx
... ... ... ...109
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When the BOOTRST Fuse is programmed and the Boot section size set to 8Kbytes, the most
typical and general program setup for the Reset and Interrupt Vector Addresses is:
Address Labels Code Comments
.org 0x0002
0x00002 jmp EXT_INT0 ; IRQ0 Handler
0x00004 jmp EXT_INT1 ; IRQ1 Handler
... ... ... ;
0x00070 jmp USART3_TXC ; USART3 TX Complete Handler
;
.org 0x1F000
0x1F000 RESET: ldi r16,high(RAMEND); Main program start
0x1F001 out SPH,r16 ; Set Stack Pointer to top of RAM
0x1F002 ldi r16,low(RAMEND)
0x1F003 out SPL,r16
0x1F004 sei ; Enable interrupts
0x1F005 xxx
When the BOOTRST Fuse is programmed, the Boot section size set to 8Kbytes and the IVSEL
bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general
program setup for the Reset and Interrupt Vector Addresses is:
Address Labels Code Comments
;
.org 0x1F000
0x1F000 jmp RESET ; Reset handler
0x1F002 jmp EXT_INT0 ; IRQ0 Handler
0x1F004 jmp EXT_INT1 ; IRQ1 Handler
... ... ... ;
0x1F070 jmp USART3_TXC ; USART3 TX Complete Handler
;
0x1F072 RESET: ldi r16,high(RAMEND) ; Main program start
0x1F073 out SPH,r16 ; Set Stack Pointer to top of RAM
0x1F074 ldi r16,low(RAMEND)
0x1F075 out SPL,r16
0x1F076 sei ; Enable interrupts
0x1FO77 xxx
14.3 Moving Interrupts Between Application and Boot Section
The MCU Control Register controls the placement of the Interrupt Vector table, see Code Example
below. For more details, see “Reset and Interrupt Handling” on page 18.110
2549P–AVR–10/2012
ATmega640/1280/1281/2560/2561
14.4 Register Description
14.4.1 MCUCR – MCU Control Register
• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash
memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot
Loader section of the Flash. The actual address of the start of the Boot Flash Section is determined
by the BOOTSZ Fuses. Refer to the section “Memory Programming” on page 335 for
details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must
be followed to change the IVSEL bit (see “Moving Interrupts Between Application and Boot Section”
on page 109):
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Assembly Code Example
Move_interrupts:
; Get MCUCR
in r16, MCUCR
mov r17, r16
; Enable change of Interrupt Vectors
ori r16, (1<